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MC-8 Controller Service Manual

1. 8 7 6 5 4 3 2 1 3 8VD 3 3VD 3 3VD AUDIO_CCLK AUDIO DONE REVISIONS 999999 4 2 03 AUDIO DIN REV DESCRIPTION PENES PROG ekeskle abel RWH CW 5 342 18 2 lt R327 XC17S20 1 CHANGED PER DCR 020430 00 5 16 02 6724 02 2343 i 52 3 947K VPP 7 KB KB AUDIO PROGRAM _ 106 Mi 50 __ 8 i42 6 26 02 IODY 7 0 186 DONE 4 2 CHANGED PER DCR 020731 00 34 02 3 D6 12 A6 485 DO IO INIT ofeg 4 390E DATA 5 NC kB 184 EM 7153 CU CEOP 8 5 02 8 14 02 181 03 Io Dour 154 5 GND 3 CHANGED PER DCR 020827 00 FH CN 180 8 30 0
2. 8 7 4 2 1 2 3 8 4 5 0 REVISIONS DESCRIPTION DRAFTER AUTH 3 3VD 1 SHOW DEPOPULATION FOR MIC BD RWH Cw 0412045006 127104 12 14 04 AF MSJ DSPAB_A 23 0 42 9 04 12 9 04 cx 2 83 3 83 0 1 DSPAB 2 24 DSPAB_A2 SVBD2 3 3VD DSPAB_A3 4 2 4 _ 4 18 128KX8 _ 5 14 12 5 TENE Ma pos DSPAB A6 15 6 SRAM e e DSPAB A7 16 DSPAB A13 23 pay VDDQ DSPAB_AQ 18 8 6 DO DSPAB 12 22 9 DO BAO DSPAB_A10 19 7 _ DSPAB 01 DSPAB_SDA10 24 58 DSPAB D30 20 A 10 DSPAB D2 2 D1 2 D3 3 D3 4 A0 A12 21 14 DSPAB 03 DSPAB A9 66 53 029 A12 D3 A9 DQ29 DSPAB A13 29 22 DSPAB D4 DSPAB A8 65 51 D28 A13 D4 A8 DQ28 DSPAB 14 30 23 D5 DSPAB A7 64 50 027 14 05 0027 A15 31 26 06 DSPAB
3. 8 7 6 5 4 3 2 1 5VD ZD 7 0 REVISIONS n 2 D6 3 D7 5 A7 6 B6 7 A6 8 A6 REV DESCRIPTION DRAFTER id CHECKER AUTH RWH CW l 1 CHANGED PER DCR 020430 00 shea 32 KB KB R402 R404 6 4 02 6 26 02 vo PXTAL VCC P 1 C1 2 D5 2 CHANGED PER DCR 020731 00 PWH cw 56 XTAL 56 8 1 02 8 5 02 CBV KB 256 Z8S180 33 5 0 8 5 02 8 14 02 RWH CW 201 36 D1 2 0 gt 2 08 4 07 5 7 6 6 7 6 8 6 12 61 3x CHANGED RER DCR 02082700 8 30 02 9 12 02 a 38 02 33MHZ 542 558 39 103 A2 9 2 02 9 12 02 ZD5 40 D4 13 ZA4 4 CHANGED SHEETS 10 13 14 PER ECO RWH CW C392 C393 259 21105 Ge Sie 13 02 19 03 02 20 03 4 25 710 10 p 106 Ab 1 2 5 030213 00 CBV KB pe D7 6 15 249 02 19 03 02 20 03 56 NC 2 e 18 _ ZA8 5 CHANGED SHEET 22 PER 031111 00 EW NC 3 19 2 9 04 Nea NC2 A9 25 10 GAP KAB NC 25 NC3 A10 20 5 18 04 5 26 04 NC4 A11 RWH CW NC 23 Nes AJ2 24 _ 2412 6
4. 7 6 5 4 3 2 1 EM REVISIONS DRAFTER J15 CHECKER AUTH 55 CW RWH ANa 08 R95 R94 1 CHANGED PER DCR 020523 00 P 01 50 47K 2 2K 1 VIDEO_DATA Ed 6500 5 L33pr 4892 4 2 UPDATED FOR DCR 040922 00 RWH CW T 275 3 VIDEGESCEK 9 27 04 10 14 04 1 4W 74HCU04 74HCU04 4 5 88 7 08 MH20 gt AT AT 102 37 4 5 050 CS 9 27 04 9 27 04 1 2 Y 5VD U8 U8 VIDEO_REG 17 88 4 9 10 50 06 R89 R88 NG 6 D3 SYNC DETECT NC 12 01 50 AK 22K 14 VIDEO_RST 3 7 88 1 33PF 1 R86 15 75 16 1 4W 74HCU04 74HCU04 Lio i 1 59 3 4 Li t 1 19 5VD U7 U7 21 20 2 21 2 23 56 2 d 09 536 ROE COAX4 25 5VR BAV99 26 1 01 50 4 47K 2 2K 1 t Ae _ gt 28
5. 8 7 6 2 1 REVISIONS REV DESCRIPTION DRAFTER QC AUTH _ 7 0 74 574 1 A3 mere 2 1019 LEDO LED 18 0 2 2042 1257 D3 5130 16 LED3 L_CTRL2 FP_D4 6 15 LED4 05 710 5014 LED5 5VD L_CTRL1 De 8190 6 13 1 06 L_CTRL0 FPD7 9 D 7012 LED7 74VHCT138 1390 FP A 2 0 EB AU 15 LED _ Yo I LED_CTRL1 1 83 1 218 ape 1 CTRL2 U4 2 318 212 7 574 FPD 2 40119 LED8 Blo 350 FP Di 3110 2018 LED9 SWRD_LEDWR 4 15 Pg SWITCH_COLUMN 02 4 17 LED10 1 6 QG2A 3D 50924 1607 SWITCH_ROW 03 5 16 LED11 4028 vr 54 640 4015 IED U6 65 7150 50 44 TED13 FP D6 8 90 13 FP D7 91 0 5012 LEDI5 um SW COL SW ROW U2 74HC574 EP DT 3 D 1918 0 FP D2 4130 ad 17 LED18 53 5 16 54 640 4015 POST 209 05 7 50 50 14 SYSTEM_ON_LED 06 78190 60 13 NC 1 08 u 7D FPD 90 59112 m LK U5 74HC574 FP_DO 2 19 SWITCHCOL 0 SWITC
6. 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER 15 MAIN SOURCE SELECT LEFT CHECKER AUTH OdBFS 4 0Vrms 15V 15 1 CHANGED PER DCR 020430 00 ew bim 5 16 02 6 24 02 KB KB R155 C208 99408 RWH OW Ue MEM GND v 2 CHANGED PER DCR 020731 00 3 100 D17 10 25 1 CBV KB 1 4W 99 5 52 8 5 02 8 14 02 6 53 2 RWH CW 2 17 54 518 2 ou LEFT MAIN IN 3 CHANGED PER DOR 02027700 8 30 02 9 12 02 11155 1 00K KB KB 10156 2 R199 9 12 02 9 12 02 057 lt RWH CW L By L 957 R200 Bs 4 CHANGED U21 28 PER ECO 030213 00 ADAT 62 19 08 1 16 15 2 042 RWH CW T C202 o 5 UPDATED FOR MC4 PER DCR 040922 00 Bound 2 2 So 100 015 10 25 14 D5 21 C3 MAIN ANG SELT 9 27 04 9 27 04 208 1 4W BAV93 14 D5 21 C3 UNITY GAIN PASS THRU 14 05 21 23 MAIN ANLG C200 lt R152 15 D4 LEFT MAIN SW 150 lt 100K ES LEFT DIR IN 2 SOURCE SELECT LEFT R197 15 4 5 3 14 3
7. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH cw RWH 1 020523 00 57909 55 02 1 lt 5 ls R120 6 4 02 6 5 02 222 cw RWH 1 25 51 lt 4 75 2 CHANGED U24 PER DCR 020715 00 8 5 02 8 14 02 050 Y IN R118 iad OSD_PY_OUT POM KB 2 D5 Y VA 4 05 8 13 02 8 14 02 470K 5 RWH Cw coL 4 UPDATED FOR PER DCR 040922 00 01 50 T 126 124 Y 2 15 245K R149 EPI T 1592104 51 514 VA 475 196 R127 C98 lt 19 Ts 1 25 100 lt 7 99 R135 R136 R128 HW Y 3139 ean Bids 74HC4053 16 4 10 16 1 1 92 OSD_SY_OUT 2 05 E 74HC4053 16 E 1 3 12 116 L LC114 Y 59 MSVID YOFF R146 VCC 12PF7 JRH438 7 T 12PF 57 NH 475 18 7 2750 AA Y C115 1 L 1 gn SECAM 065 VW INH 6 VSS VEE 035 8 7 OSD_Y C_OUT He cU B 2 85 OY SPARES 5VV 41 5VV 1415 e 4 C105 teas ai 4 C117 C123 5VV lt 4 75K 1 25 lt 1 1 25 8 AD8072 C106 32 gt gt lt lt lt
8. 8 7 6 5 4 3 2 1 REVISIONS 5VAD TEV REV DESCRIPTION DRAFTER Q C n A CHECKER AUTH RWH CW FB13 2 LEFT amp RIGHT SIDE D A CONVERSION 1 CHANGED PER DCR 020430 00 5 16 02 6 24 02 KB KB 6 4 02 6 26 02 C143 C141 C139 RWH cw ua cp 2 CHANGED PER DCR 020731 00 BE C 47 47 330 6 3 8 5 02 8 14 02 1 142 C140 C138 DUE RWH cw MP OdBFS 8Vrms 95 CHANGED PEFLDCR 020827 00 8 30 02 9 12 02 45V 5 3 1 25 1 25 1 25 OdBFS 1 7Vrms A KB KB 5 ME E15 A 9 12 02 9 12 02 Z 13 12 RWH CW J22 R112 C102 ADG451 4 UPDATED FOR MC4 PER DCR 040922 00 4395 nee 2i 18 121K 330 63 R76 280 15 10 LSIDE_DACOUT 19 B8 9 27 04 9 27 04 5 76K 1 IN 1962 SIDE DAC MCKI 3 17 L C134 C79 1 4 GND 4 82 MCLK VREFH 1 4 s U8 18 D8 20 D8 21 83 MAIN DAC RST 45pp AOUTL 23 Lb 15V 4 2114 103 75 C77 Y 77 4 1 4 2 20 08 MAIN DAC 5 AOUTL 22 4 q ppc 15V 1 21K 330 6 3 280 220 M 4 C1 4 B4 SIDE DAC SDI 6 9 1 1 R74 15V 5 n
9. 8 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH MAIN ZONE 2 5VD 5VD 5VD 5VD 5VD 5VD 5VD 5VD 5VD YEL RED LED16 LED17 D22 1 5K 021 180 LED 18 0 2 03 C SWITCHCOL 20 __ 201 2 23 1N914 D19 SWITCHCOL 1 1 914 018 SWITCHCOL_0 1N914 1 2 SROW_0 7 ELE LAIT 13 sRow 0 9 1 1 2 SROW 1 2 SROW 0 2 SROW 1 2 SROW 2 2 SROW 3 2 SROW 0 2 SROW 1 2 SROW 2 2 SROW_3 41 62 pa wasapa SN LL L L 47 1 sRow 1 7 a sRow o T sRow 1 T sRow 2 7 a sRow 3 T sRow o T sRow 1 T sRow 2 T a sRow 3 SW18 8 SW7 SW6 SW5 5 4 Sw3 2 SW1 2 SROW 4 2 SROW 5 2 SROW 6 2 SROW 7 2 SROW 4 2 SROW 5 2 SROW 6 2 SROW 7 LI LLL EL L L Ip Lt 1 ZEE T sRow 4 T sROW 5 T 913 sROW 6 T 13 SROW 7 T 2 3 4 T sRow 5 T 2 3 sRow 6 T SROW 7 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SROW 7 0 2 87 2 SROW 3 2 SROW 4 1 2 SROW 2 et LII 3 SROW 3 3 SROW 4 4 3 2 SW20 SW19 21 exicon NO 01730 TITLE APPROVALS DATE SCHEM SW LED BD MC8 DRAWN RWH 12 21 01 SWITCHES 8
10. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER AUTH RWH CW 1 CHANGED PER DCR 020430 00 5 16 02 6 24 02 6 4 02 6 26 02 RWH CW 2 CHANGED PER DCR 020731 00 8 1 02 8 5 02 CBV KB 8 5 02 8 14 02 _ RWH CW 15V BYPASS CAPACITORS 3 CHANGED PER DCR 020827 00 8 30 02 9 12 02 D 15V KB KB 1 9 12 02 9 12 02 RWH CW H z i 4 UPDATED FOR MC4 PER DCR 040922 00 9 24 04 10 14 04 5 9 ceos C67 C68 C75 C76 C83 C84 C91 C92 169 175 181 187 C193 199 205 211 233 235 c2378 238 242 252 254 2569 0257 C261 C298 Ec 4 mw 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 11 25 1 25 1 25 1 25 1 25 1 25 C438 C46 C49 C52 C55 C64 C72 C80 C88 C96 C168 C174 C180 C186 C192 C198 C204 C210 C234 C239 c2408 241 C243 C253 C258 C259 260 C262 c300 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 W 15V 5VD 5VA 216 C306 C345 C346 C347 348 358 C359 C360 C361 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 C277
11. 8 7 6 5 4 2 1 REVISIONS REV DESCRIPTION 5VV 5VV 1 CHANGED PER DCR 020523 00 NS 74HC4053 16 6 4 02 6 5 02 5 x _ RWH CW 2 UPDATED FOR DCR 040922 00 JAM cs AT AT y 9 27 04 9 27 04 INH VSS VEE 7 voy 5VV 8 04 VIDEO DATA VIDEO DATA 8 D4 s VIDEO SCLK VIDEO_SCLK CONTROL REGISTERS FLASH INTERFACE 5VV 5VV 5VV 4 16 16 15 MVID SEL0 _ vcc 14 QA 1 1 sEL1 gt 2 08 14 L QB 2 08 LL SER QB 2 MVID 8 2 gt i 11 Bers 1 MCVID EN 2 08 11 QC o iP 2 MSvip YOFF 12 08 1 8 QD O gt 5 2 o SRCLR 12 QF MTHRU 2 7 12 ROSE QG HINH 2 5 pRCLK SPARES 13 QH 5 6 C4 asl QH up QHH OG GND QHH 8 U38 8 Es NZ 57 A 74 42 l 5VV 5VV 31 020 16 16 15 ZVID SELO vcc 14 oor zvip 8 08 14 4 SER QB 3 08 QB 4 oc 2 t ZVID_SEL2 8 08 L 1 ZSVID YOEE 3ID8 8 1 2 O SRCLR qE gt 3IC5 OSRCLR 9 11 NC 12 QF 6 P
12. 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 6 4 02 6 26 02 RWH CW 2 CHANGED PER DCR 020731 00 aie CBV KB 8 5 02 8 14 02 RWH CW 3 CHANGED PER DCR 020827 00 Bun 5VD 9 12 02 9 12 02 RWH CW 4 4 CHANGED U56 PER ECO 030213 00 2 19 03 CBV KB 02 19 03 02 20 03 RWH CW dian p D26 5 UPDATED FOR MC4 PER DCR 040922 00 954 04 1N4002 78105 9 27 04 9 27 04 VIN 4 COMMON 1 C292 2 35 7 054 T 1 25 C293 ld 10 10 77 5 PLL SPARES 5_ U55 1312 NC 74 04 FB25 3 d FB28 FB26 U55 11 nc 74 04 ee 033 1 C307 297 EI 1 25 1 25 74HCU04 1N914 302 p 1 50 057 2261 C303 74HCU04 bao 11 10 NC 1 2K 055 D30 47 16 2 83 E PLL_PUMP_UP 17 2 UP R255 J TAACTOA 12 VCOV Z 4HCU04 BAR35 1 2K T 5 6 NC e 5 R256 100 25 74HCU04 2 83 PLL PUMP DOWN 3 4 P_DOWN PJ C304 3 o VCO MODULE 13 _12 74 04 D34 12 1 25 tlo 55 057 77 055 5 R257 PLL LOCK DOWN 5 6 L_DOWN 5 C206 74HCU04 4 R260 7AACTOA 632 499 080
13. 8 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 SHOW DEPOPULATION FOR 3 PER 041201 00 AE 3 3VD 42 9 04 12 9 04 MASTER 00 HIGH ID1LOW 4 SLAVE IDO LOW ID1 HIGH ae pp eee 4202 eere leladi seagreusue CN O LO f KO LO co LO O GN GN TOW CO I 0010 D O AO oo eS a Veg RAS 42 DSPCD_RAS 5 C1 5 D3 7 C8 RAS 043 DSPCD_CAS CAS 543 PSECD SOWE 5 C1 5 D3 7 C8 SDWE 5 PCD_ 5 C1 5 D3 7 C8 46 DSPCD DOM gt 5 C1 5 D3 7 C8 DSPD_CLK 30 48 DSP D SDAID 1 5 03 7 8 10 C6 CLKIN SDA10 49 5 C1 5 D3 7 D8 NC 31 2 SDCLK0 5 C1 5 D3 7 C8 BseL 34 5 C8 8 B4 8 C1 RESET 144 mus 153 DSPCD BMS 142 100 BMS 279 DSPCD SURAM 5 D1 5 C3 8 B7 222 DSPCD 69 01 MSO 571 DSPCD HOST 657 5 1 5 3 7 8 5 C8 8 B4 8 C1 ACK MS1 gt 5 C1 5 C3 8 B7 52 574 DSPCD SRAM CS 5 1 5 7 04 2 C8 3 C8 5 C8 8 B4 8 C1 amp DSP_FSI_IRQ 205 MS3 79 SP RACD 207 ROT ADSP21065 SW S DSPCD_WR 2 207 WR 258 5 C3 5 D1 7 B4 RD D 5 C3 5 D1 7 B4 CNC 195 DSPCD AO 5 5 6 6 DSPD_FSI 7
14. REVISIONS DSPCD D 31 0 5 A3 6 A3 8 B4 DESCRIPTION DRAFTER CHECKER AUTH RWH CW CHANGED PER DCR 020429 00 Eig TIT TR 5 6 02 5 13 02 DSPCD A 23 0 5 B3 6 C3 DSPCD 0 11 0018 DSPCD_A1 2 24 DSPCD_A2 aM 3 3VD DSPCD_A3 4 1 2 DSPCD A4 13 A4 128KX8 D 4 A5 12 A6 SRAM DSPCD A13 23 A8 12 22 DSPCD_A10 19 1 9 Bo DSPCD b1 DSPCD SDA10 24 DSPCD ATi 20 p2 10 DSPCD D2 5 C1 5 D2 6 D3 10 2930 DSPCD 12 21 11 DSPCD D3 DSPCD A9 66 53 DSPCD 029 A12 D3 A9 DQ29 DSPCD A13 29 22 DSPCD 04 DSPCD A8 65 51 _ DSPCD 028 A13 04 0028 DSPCD A14 30 23 DSPCD D5 DSPCD A7 64 50 _ DSPCD 027 A14 05 AT DQ27 DSPCD 15 31 26 DSPCD 06 DSPCD AG 631 6 0026 48 26 DSPCD A16 32415 06 727 DSPCD_D7 DSPCD A5 6240 Dass 47 DSPCD D25 A16 07 DSPCD A4 6149 Da2 45 DSPCD D24 Benen DSPCD 6044 222342 DSPCD D23 SRA DSPCD_A2 2743 40 DSPCD 022 DS CD WR DSPCD Ai 26142 Doe 39 DSPCD_D21 DSPCD A0 25 37 _ DSPCD D20 0 0020 35 019 gt 5 1 5102 63 DSPCD 59 bams pais 34 DSPCD D18 882 28 BOM Dos 38 DSPCD D17 U tB eeu 31 DSPCD 516 16 DOMO 2218185 5 515 DSPCD 0
15. 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH cw RWH 1 CHANGED PER DCR 020523 00 ero 6 4 02 6 5 02 cw RWH 2 CHANGED SHEETS 3 5 PER DCR 020715 00 AOZ ECM KB 8 3 02 8 14 02 CW RWH 3 CHANGED SHEET 4 PER 021105 00 11 12 02 11 12 02 RWH CW 4 UPDATED FOR MC4 PER DCR 040922 00 Aonad AT AT 9 27 04 9 27 04 5VV R80 5VV S VIDEO INPUTS SCIB Digg 3904 00 3904 21390 100K _ 2390 271 ue Sv C45 R81 0074 R78 1 25 R79 010 R84 S 2 C8 3 C8 275 0 T 75 05 E 2 88 3 88 749 x N 5 R85 476 22 sR82 1 T gea 470K gt x Y 5VV 5VV 5VV ps 2N3904 J12 100K C38 2 a ae C41 Q7 2 oft 1125 R71 R76 2 C8 3 C8 A 215 0 D eels 05 VAS 2 88 3 88 R77 4e 22 11 AE NE Wi xem 2 470K 2 Sk S AK Y Y 5VV 5VV EL M 2 2 88 n 2N3904 J11 100K _ 2 3904 Ae 3 w I avs C37 R65 Q5 RED 1125 R63 06 R68 SS 2 C8 3 C8 275 0 ED 7505 2 B8 3 B8 476 22 4 1 V 1 4 22 Reas gt P v 2 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W y Y 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5
16. 2 A3 3 A3 8 C4 DSPAB DIO REVISIONS D CHECKER AUTH 3 3VD CHANGED PER DCR 020429 00 und Rd 5 6 02 5 13 02 2 83 3 83 0 DSPAB A0 0018 DSPAB A1 A2 3 3 3VD DSPAB_A3 4 2 DSPAB 4 13 1 5 14 12NS lt lt DSPAB A13 23 VDD VDDQ DSPAB_AS 17 5 _ 9 18 6 _ DSPAB A12 22 9 DO BAO 2 DSPAB_A10 15 7 01 DSPAB_SDA10 24 DS PARE 030 2 10 D2 2 D1 2 D3 3 D3 A10 DQ30 21 11_ 03 DSPAB AS 66141 DSPAB 029 2 D3L25 BSEAS Dd DSPAB 8 65 51 028 A13 D4 0028 23 05 DSPAB A7 64 50 027 14 D5 AT DQ27 26 DSPAB A6 63 A 026 15 6 59 A5 6240 025 16 07 DSPAB A4 611 DQ24 024 DSPAB SRAM CS 5 DSPAB 60 D23 0023 12 DSPAB A2 _ 2742 0022 022 DSPAB_RD 28 q W _ 26 021 dG 100MHZ 2919134 DSPAB D18 352 2101 2103 3 03 DOM 59 DQ1835 BSpAS DS 3 3VD DQM2 DQ17 020 ra Ber Daie 21 DSPAB D16 16 015 DSPAB_AO 1 8 DQM0 DQ15 mar 140 voo 2014 PAB 2 002 2
17. REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH CW 1 CHANGED PER DCR 020429 00 5705 5 13 02 2 UPDATE SIGNAL NAMES ON SHEETS 1 8 CW BER DG 020977 U0 9 30 02 10 15 02 KAB KAB D 10 15 02 10 15 02 5VD 3 3VD TEST POINTS non sog PSEA OA SD SD C32 1 A32 1 AUDIO0 DSP_MCKI gt 8 B7 8 C1 1 2 IO A2 C30 C3 NAME C3 A30 AUDIO1 DSP_FSI 220 a gt gt 8 B7 8 C1 29 A A4 AUDIO2 DSP_PROG G c T 8 D7 A28 5 Ab AUDIO3 DSPA_0A_SDI 1 D1 2IC8 c c6 27 A6 A6 AUDIO4 DSPA 50 aL 25 5 1 D1 2 C8 26 AUDIO5 AUDIO5 25 P gt 25 8 DSPD_1A_SDO AUDIO6 A8 24 C9 6 C8 C9 A24 DS PD 18 SDO AUDIO 9 cz3 c 6 8 C10 A23 _ 8 AUDIOS A10 cn 8 A4 C1 A22 AT AUDIO AUDIO_4MHZ 21 12 12 L 8 A4 A21 A12 A12 NC C20 C13 C13 A20 A13 A13 NC C19 14 C14 9 14 NC 15 15 17 16 NC 7 me 6 16 17 C17 NC 16 17 17 15 18 18 15 18 18 DSP_A4 NOTES 14 19 19 DSP_A3 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 14 19 19 DSP_A2 co c20 DSP 2 UNLESS OTHERWISE INDICATED RES
18. 8 Controller Service Manual Harman Specialty Group Oak Park MA 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070 17536 Rev 0 5 This document contains general safety and service instructions for the MC 8 is important to read this manual before attempting service instructions Pay particular attention to safety instructions The following symbols are used in this document Appears on the component to indicate the presence of uninsulated dangerous voltage inside the enclosure voltage that may be sufficient to constitute a risk of shock Appears on the component to indicate important operating and maintenance instructions in the accompanying literature Calls attention to a procedure practice condition or the like that if not correctly performed or adhered to could result in injury or death Calls attention to a procedure practice condition or the like that if not correctly performed or adhered to could result in damage or destruction to part or all of the product Calls attention to information that is essential to highlight IMPORTANT SAFETY INSTRUCTIONS oN Oa PF YO DN 10 11 12 13 14 15 16 17 18 19 Read and keep these instructions Heed all warnings Follow all operation instructions Do
19. FROM VIDEO BD 442 in 417 NOT USED E TORQUE TORQUE ON SDP 5 NOT USED SPS SUPPORT MOUNTS 4e 18 ON Me SB z OUTSIDE SURFACE 1 SEE SHT 3 FOR PARTS LIST P d OF CHASSIS FOLD 2 PLCS 4 PLCS CRIMP ON 2 SEE SHT 2 FOR MC 8B TORQUE THIS SIDE 1U CHASSIS ASSEMBLY 6 IN L Rh v P O ITEM 10 26 63 3 FOR SDP 5 415 ON BD IS REPLACED TORQUE 2 4 IN LBS dila MAIN BD 55 52 Td WITH DIN CONN 17 MOUNT TO A TORQUE 4 45 amp 432 REAR PANEL WITH SCREW ITEM 33 DOCUMENT CONTROL BLOCK DOC f DESCRIPTION REV 080 15462 SH 1 03 5 080 15462 SHT 2 03 1 080 1562 SH 5075 3 TORQUE 8 10 IN LBS 27 Pics 5 TORQUE 55 6 PLCS PLCS 4 6 IN LBS TORQUE 4 6 IN LBS NOT USED 4 PLCS MC 8B pros oe ASSY DWG CHASSIS 8 12 IN LBS L pm me MC 8 B 50 5 APPLICATION DO NOT SCALE DRAWING 5507 e 7 3170 sne 1 1 8 7 6 5 4 2 2 10 05 SUE OW woo e B 080 15462 serio 4 D A 8 7 6 5 4 3 2 1 DESCRIPTON ADD DETAIL B ITEM 73 PWR AN 11 18 03 5 12 04 T
20. DEVELOPMENT ONLY PIN 7 BTCK JUMP TO PIN 8 PIN 9 BTRST JUMP TO PIN 10 DSPCD D 31 0 3 3VD 3 3VD 6 A3 7 D7 8 B4 53 DSPC_BMSTR DSPC_BMSTR S R82 DSPC_TDO DSPCD_EMU DSPCD EMU gt GND 208 NC DSPCD_TMS 2 DSPCD_TMS 6 B8 xr co xr o i0 i6 o sr Lo o 1 o xr 8 DSPCD DSPCD_TCK e o gt IE olor oss U14 l l 6 88 DSPCD TDI gt 6 B8 NO 3 PARK 55838 exicon BEDFORD MA 01730 La DSPCD TRST DSPCD TRST TITLE 2 APPROVALS DATE 77 7 DSPC 4 A8 8 B7 DEAW SCHEM MIC DSP BD MC8 4 A8 8 B7 RWH 5 2002 pspc 6 B8 5 01 10 6 DSPD TDO DSPC 0070 DSPCD CHECKED 5 29 02 SIZE CODE NUMBER REV 060 15389 1 cw 6 3 02 CILE NAME ISSUED KB 6 3 02 15389 2 5 SHEET 5 OF 10 8 7 6 5 4 3 2 1 12 15 2004 8 52
21. 10 035 R209 Z 25 AINR SCLK 14 4 MAIN_ADC_SCKI lt 4 C4 ie 100PF N 24 7 MAIN AC EA i 4 L 2 49K y 2 AGND 9 13 Re VC MUTE 267 2 BOND Vo 15 B8 2200 0 TEST 8 10 MAIN ADC RST 4 21 3 C248 R210 D 045 D E A R20 47 16 5 62K AZ 19 51 n 1 4W E26 fexicon sompa BEDFORD 01730 TITLE APPROVALS DATE DRAWN SCHEM MAIN BD MC4 MC8 RWH 2 15 02 MIC INPUTS amp MAIN A D CONVERTER CHECKED 3 29 02 SIZE CODE NUMBER REV 060 15259 4 cw 4 3002 NAME ISSUED kaB 4 3 02 15259 6 15 SHEET 15 OF 23 8 7 6 5 4 3 2 1 10 19 2004_ 9 04 8 7 6 5 4 3 2 1 REVISIONS SVAD REV DESCRIPTION DRAFTER 4 4 CHECKER AUTH 5VAD 5 5VR RWH CW l 13 12 ADG451 1 CHANGED PER DCR 020430 00 8 VDD Nu FB11 3 13 02 EFT ZONE 8 s p f sang 126 02 o IN 2 CHANGED PER
22. 9 mum 102 C54 01730 10 1 857 MIC SEL1 AEROS BUE TITLE R56 47PF 5102 SCHEM MIC DSP BD MC8 MIC_IN_4 in RWH 5 2002 MICROPHONE INPUTS ANE 10 45 10 0K CHECKED p 5 29 02 SIZE CODE NUMBER REV 1 ac B 060 15389 0 cw 6 3 02 CILE NAME ISSUED KB 6 3 02 15389 2 9 sHEET 9 oF 10 8 7 6 5 4 3 2 1 12 7 2004_10 16 REVISIONS REV DESCRIPTION DRAFTER Q C 3 3VD CHECKER AUTH 3 3V DIGITAL BYPASS CAPACITORS 1 SHOW DEPOPULATION FOR PER 041201 00 MSJ 3 3VD I I 12 9 04 12 9 04 1 c18 c2 8 4 8 658 598 ceo ce18 ce28 c63 8 8 C659 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 lt R108 30 000MHZ 4 gt 10K 3 3V VDD 8 OUT lt R12 334 DSP S0MHZ
23. T 21183 SIDE VC ZCEN i SEEN 9 4 a 18 A8 20 A8 21 83 MAINOUT VC MUTE spout 7 keas C26 R12 2 19 C3 RSIDE_DACOUT 9 ANR AOUTR 71 ids VV RIGHT SIDE OUT AGNDR VA 089 5 R18 4 4W 10 13 U3 S 40K L 25 1 57 CA Moe 3 NO exicon BEDFORD MA 01730 2 2 35 R33 APPROVALS LE ey A RSIDE 21 C8 DEAW SCHEM MAIN BD MC4 MC8 100 RWH 2 1502 UR SIDE DACS CHECKED 3 29 02 SIZE CODE NUMBER REV ac B 060 15259 4 E6 cw 4 302 Lig AME ISSUED kaB 4 3 02 15259 6 19 sHEET 19 oF 23 8 7 6 5 4 3 2 1 10 19 2004 8 58 8 7 6 5 4 3 2 1 REVISIONS SVAD REV DESCRIPTION DRAFTER A CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 FB12 3 LEFT amp RIGHT REAR D A CONVERSION 21602 612202 6 4 02 6 26 02 C133 C131 C129 F RWH CW 2 CHANGED PER DCR 020731 00 BE 2 47 47 330 6 3 TR 8 5 02 8 14 02 old C132 C130 C128 i z RWH CW 92 eem L OdBFS 8Vrms HEV 5VAD CHANGED DOES Q2082 00 8 30 02 9 12 02
24. TALVCAA 053 6 R46 8 21103 11 5 10 7 IN pus LEFT MAIN SW 1308 A 15V f 9 MIC IN 2 7K R45 RIGHT MAIN SW 2 A 14 D5 4 2 7K J19 5 5VA MAIN A D CONVERTER s R191 5VA 3 3VD 510 N OdBFS 0 884Vrms FB23 MAIN INPUT LEVEL CONTROL R219 C266 C270 R215 46 yt 5VA rd 7 1 47 47 1AW C268 C269 C244 pa z 274 125 lt gt 1125 OdBFS 2 0Vrms T 2200PF AK5383 23 7 25 VA 7 R203 OdBFS 2 0Vrms 1 25 e C24 R216 1 EE 15 12 PGA2311 bd A R214 s AINL ZCAL 2 AGNDL VA MEE E JANG p v e 6 4 SPARES LEFT MAIN IN 16 14 1 4W C271 13 D2 amp AINL AOUTL i E 1 VREFL HPFE 19 3 __ MAININ 6 4 47 272 ic MAININ VC DATA 3 Hes e C251 C250 ue 4 M ps 2 GNDL sue pu 9 b NC 4 D4 SDIN Eeh RAT 273 skoner 12 47K epe CS PR 5 e HK gt gt 4 D4 065 DGND e 1 R207 C265 18 77 MAIN 96K EN __ lt 125 DFS 21 C3 B 26 7 77 MAININ_VC_MUTE 8 0293 VREFR R20 15 2 _VC_ MUTE 900 __ RIGHT MAIN IN 9 11 I 210 0K T 4 25 47 14 D2 AINR ri 1 25 10 10 co 27 GNDR trek 13 2 a
25. 5 DRAWN RWH 12 7 01 SCHEM STANDBY BD MC8 CHECKED yap 1 4 02 SIZE CODE NUMBER REV ac SENS B 060 15329 0 gt 8 FILE ISSUED 1 8 02 15329 0 1 SHEET 10F 1 e 6 2 1 6 5 i REVISIONS REV DESCRIPTION DRAFTER QC CHECKER AUTH RWH CW 1 UPDATED FOR MC4 PER DCR 040922 00 9 24 04 10 14 04 9 27 04 9 27 04 D VIDEO BOARD CONNECTOR n Si ZONE E 2 YEL J 2 3 4 92 93 7 MONITOR 7 2 YEL NOTES 1 LAST REFERENCE DESIGNATORS USED J3 2 COMPONENTS MARKED WITH 8 ARE INSTALLED 27 2004 2004 Lexicon Inc Xi n AGAR BARE A NO lexicon BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM VIDEO OUT BD MC4 MC8 RWH 1 9 02 RCA OUTPUTS CHECKED 1 10 02 SIZE CODE NUMBER REV cw moe ISSUED FILE NAME S KAB 1 11 02 15339 1 1 5 1 OF 1 6 5 2 1 s 8 7 6 5 4 3 2 REVISIONS CHECKER AUTH LFR2 5VD 5VD R96 R99 um MAIN OUTPUTS 2 94K 3 01K 1 1 2 2134 R100 C85
26. 3 03 NO 01730 TITLE APPROVALS DATE SCHEM MAIN BD MC4 MC8 DRAWN RwH 2 15 02 OPTION BD 2 CONNECTOR CHECKED cy 3 29 02 SIZE CODE NUMBER REV 060 15259 4 CW 4 3 02 FILE NAME ISSUED kaB 4 3 02 15259 6 8 SHEET 8 OF 23 7 6 5 4 2 1 10 21 2004_8 21 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH MAIN DIGITAL AUDIO RECEIVER 1 CHANGED PER DCR 020430 00 Fo a _ MAIN_ERR STATUS KB KB 263 6 4 02 6 26 02 RWH CW ses 2 CHANGED PER DCR 020731 00 8102 CBV KB C334 8 5 02 8 14 02 RWH CW pu 3 3 CHANGED PER DCR 020827 00 7 7 8 VE SON CS8414 9 12 02 9 12 02 RWH CW s VAIN DRCVR NRZI 9 4 UPDATED FOR PER 040922 00 S 4971403 19 2310 56 MAIN DRCVR MCKO A A 26 M MAIN LDRCVR 800 2 D1 2 B5 MAIN DRCVR FSI 11 SDATA x 4 D1 4 C8 9 27 04 9 27 04 4 01 4 4 FSYNC 16 SEL 4 C4 4 01 MAIN DRCVR_SCKI 12 6 MAIN_CO 4 C8 2183 812 13 cs412 FCK 9
27. 2002 Lexicon Inc 2 A5 3 C3 m XPOUTS MUTE 3 390 02 01730 TITLE APPROVALS DATE BRAWN SCHEM XLR BD MC 8B cw 4 8 02 FRONT CENTER SUB OUTPUTS CHECKED 4 9 02 SIZE CODE NUMBER REV ac 060 15349 0 RWH 4902 ISSUED 4 10 02 15349 0 1 sHEET 1 3 8 7 6 5 4 3 2 1 4 12 2002 11 43 REVISIONS DESCRIPTION DRAFTER CHECKER 1802 5VD 50 R56 R59 3 03 SIDE 4 MAIN OUTPUTS A SEE COD 2134 Reo C57 Di RELAY LSD1 18PF LSD 1 4002 57 47 25 R54 LEFT SIDE OUT 22K C59 IA R55 15V R58 18PF R53 3 D3 m LSIDE 22K 2 94K 3 01K 1 1 Rs 56 150 apy 47025 RY6 RSD2 eng RSIDE R46 R49 2 94K 3 01 C53 1 1 558 RSD1 8PF RIGHT SIDE OUT 52 VENE ME 18PF RSIDE R45 R48 2 94K 3 01K 1 1 RSD 51 47 25 5 15V R36 R39 15V C46 RELAY LRR LRR1 LEFT OUT C45 R41 15V R35 15V R38 18PF LREAR 3 C3 2 94K 3 01K 1 1 LRR
28. 5VV 5VV R56 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE A 2 8 4 2N3904 E 2N3904 4 DIGITAL 1 ANALOG CHASSIS POWER C30 7 GROUND GROUND GROUND GROUND 4 Vp t I mm 5 DENOTES SHEET NUMBER SECTOR C33 0377700 RBA 4 25 44 Q4 R60 2IC8 3IC8 SY4 5750 304 2 B8 3 B8 6 LAST REFERENCE DESIGNATORS USED ON C148 CP2 09 J19 L1 476 22 Rsg 11 22 015 R172 038 Y1 470K 2 S K L 7 COMPONENTS MARKED WITH ARE NOT INSTALLED I 8 COMPONENTS MARKED WITH 8 ARE NOT INSTALLED 5VV 5VV R48 5VV nv 558 gt 2 88 un 2N3904 J9 100K 2N3904 r N v Y SUE C29 R46 1125 Ine S2 R52 m 2 C8 3 C8 275 0 275 0 AP 2 48 3 88 gt 47 6 22 4 1 1 22 P lt Ra os gt 2 Ro 1 DOCUMENT CONTROL BLOCK 060 15269 1 REVISION TITLE 8 4 S VIDEO INPUTS Y y 20F 8 2 MONITOR 5VV 5VV 30F 8 3 ZONE 40 8 3 COMPONENT VIDEO 8 3 ON SCREEN DISPLAY 6 OF 8 2 SYNC STRIPPER 8 2 CONTROL REGISTERS 8 8 2 PWR SPDIF MAIN amp RCA BD CONNS 2004 Lexicon Inc CONTRACT NO 01730 TITLE APPROVALS DATE OCT 27 2004 DRAWN SCHEM VIDEO BD MC4 MC8 RWE 3 19 02 S VIDEO INPUTS CHECKED 3 48 02 SZE CODE NUMBER REV 060 15269 4 i
29. DSPCD A4 188 DSPCD A5 PA_DSPCDRDX 12 Drop 185 DSPCD DSPCD A7 A 183 NC DSPCD_A9 DSPCD A10 SERIE 11 18 1 175__ 5 _ 2 19 174__ 5 _ 13 22 ae Ala 173 DSPCD_A14 NC 231145 171 15 NC 26 A16 16 DSC PWMEVENTO 17 166 DSPCD A18 drm A21 et DMAG2 2 160 _ 23 6 C3 7 D5 40 82 DSPCD 52JHER Do 83 DSPCD_D1 539 H8 84 DSPCD D2 NC ES Cep y 82 86__DSPCD_D3 56 87 __ 5 _ 4 5875 04 Bod 88 DSPCD D5 PST 6 88 SPED ERT ACPA D6 S1 Pope Dy 5 C1 6 88 BR1 D7 DSPCD_BR2 284 ERI 0792 DSPCD D8 96 5 09 DSPCD_EMU 145 09 97 8 010 DSPC_TDO 1464 ENG Dio 98_DSPCD_Di1 B BSPOD TCK rer DSPCD D13 DSPCD TMS 149 813 104 DSPCD Di4 DSPCD_TRST 147 TES DSPCD 015 q 812 108 _DSPCD D16 DSPCD_STATUS_FULL 109 017 I 2 88 3 88 6 B8 8 B4 818 112 DSPCD 519 0191413 DSPCD 520 020 116 DSPCD 021 021117 DSPCD 022 0221118 DSPCD_D23 121 DSPCD 024 024 122 DSPCD 025 DEVELOPMENT ONLY 26 23 26 027 PIN 7 BTCK JUMP TO PIN 8 D28 421 028 PIN 9 BTRS
30. 16 Connect the S video output from the DVD player to the 8 S video input 1 Connect the main S video output of the MC 8 to the S video input of the video monitor Turn on the DVD player monitor and the MC 8 The monitor should display a blue screen Press the remote DVD1 button to select this as the input for testing the video paths Press the Menu arrow The Main Menu should appear on the screen With the Menu arrow scroll down to Setup and then select it by pressing the menu arrow The Setup Menu will appear and the Inputs at the top will be highlighted Press the Menu arrow again The display will read Input Setup DVD1 Press the Menu gt arrow The display on the MC 8 will now be at the top on the DVD1 Menu Using the Menu arrow scroll down to the Video In parameter and select it by pressing the Menu arrow Using the Menu arrow scroll to the video input S video 1 Press the Menu arrow to select the S video 1 input This will assign the S video 1 input jack to the Main Zone S video output jack of the MC 8 Press the remote OSD button This will turn off the onscreen video information from the MC 8 and allow viewing of the video from the DVD player The video path is now set for testing Test Load a disc into the player and press play Verify a clean undistorted picture appears on the monitor screen Pause the DVD player To test the Zone 2 S vi
31. 8 7 6 4 3 2 1 REVISIONS DESCRIPTION DRAFTER CHECKER _ AUTH RWH CW CHANGED PER DCR 020429 00 Eig 5 6 02 5 13 02 3 3VD D MASTER IDO HIGH ID1 LOW SLAVE IDO LOW 01 HIGH D OID 0 lt 0 be 9 5 1 6 03 7 8 DSPCD CAS 5 1 6 03 7 8 DSPCD SDWE 15 1 6 03 7 8 TEST POINTS 46 DSPCD_DQM P 5 1 6 03 7 8 4 DSPCD SDCKE _ y 5 1 6 03 7 8 DSPC_CLK DSPC_CLK 30 d a anoles DSPCD_SDA10 Pica eng 78 DSPCD_ICE_CLK ed Ne 31 2 37 DSPCD_SDCLK 5 C1 6 D3 7 C8 DW 152 SpcLk1 4 NC e 5 6 D8 8 84 8 C1 CD RST l TS RESET T 2 IDO 5 D1 6 D3 8 B7 DSPCD ACK 6510 DSPCD HOST GS gt B C1 6 D3 7 C8 2 6 D8 8 B4 8 C1 w ACK HOST CS 5 1 6 03 8 87 Ms2b4 DSPCD CS 5 1 6 7 04 2 C8 3 C8 6 C8 GS FSRA 2051 rd 6 C8 8 B4 spp 2 ADSP21065 gt DSPCD_WR 8 B4 8 C1 LCMD RDY 5 D1 6 C3 7 84 WR P59 DSPCD_RD C3 DSPABC 5 01 6 23 7 84 DSPC_SCKI 4 CERE 195 DSPCD 0 5 550 nt 194 _ 5 _ FB2 EID SN DSPB SDO 5 2 193 DSPCD 2 84 DSPCD WR X 7 50 190 DSPCD n 8 B7 NC E
32. c66 8 ces 8 99 c70 719 729 c738 c748 C758 768 8 GND R11 8 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 lt R138 2 022 233 4 Du N 777 ANE 8 cso 8 818 828 838 4 8 858 8 898 Do MN gt 2 08 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 74LCX14 3 3V ia i 3 3VD 3 44 R85 33SDSPB_CLK 908 18 co28 co3 8 c94 8 co58 968 cos 8 c99 8 c1008 c1018 Ni 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 7ALCX14 3 3V 14 8 R 2 R E 4 024 sne R86 33SDSPAB 1028 1038 1048 c1058 c1068 c1078 c1088 c1098 c1108 c1118 c1128 c1138 u 8 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 R91 6 74LCX14 3 3V by da SKN VOD 4 4 4 4 4 4 4 4 4 4 4 ee x 2 alaa 13 5 12 R88 33 DSPC 5 08 1148 1158 1168 1178 c1188 c1198 1208 c1218 c1228 c1238 c1248 c1258 7 1 25 1 25 1 25 4 25 1 25 4 25 T 4 25 4 25 1 25 1 25 1 25 1 25 7 W181 01 74LCX14 3 3V 54752 ow e LEE u248 5 m eu 3 23 1 9 5 8 R89 339DSPD e d yy E 10 06 1268
33. HOST ADDRESS BUFFER ADDR ADDR 0 1 PANEL ADDR F BUT MUX TON DISPLAY SWITCH READ LED WRITE RESET LED REG LED S IR AUX DATA gt gt IR AUX DATA IR IR ACK LED gt IR ACK LED RECEIVER DATA 0 1 jo ENCODER 0 1 N ENCODER FRONT PANEL SWITCH LED BOARD FRONT PANEL ENCODER 8 OSD IR ENCODER BOARD 6 6 Lexicon Video Board amp OSD The control interface to the Video Board consists of e Serial control data serial control bit clock e OSD chip select enables the serial control port of the On Screen Display chip e Video Register chip select enables the serial to parallel registers that generate the control bits used on the video board video reset line SERIAL DATA gt SERIAL CLOCK BUFFER VIDEO DETECT 3V gt 5V OSD CHIP SELECT gt VIDEO REG CHIP SELECT RESET gt VIDEO BOARD INTERFACE CONNECTOR DSP and Daughter Board Connectors The DSP and daughter board connectors ha
34. T G54 275 2 1 29 vee TEST POINTS 1 4W 74HCU04 74HCU04 30 BE suo a COA OPTO3 ROWER SUPPLY FB2 GND3 32 ABV O SZ 5VD U8 U8 OPTO4 33 SS LX FROM MAIN BOARD css l 100 25 O GND2 A 10 16 T m gt C87 J19 J17 51 A 07 R90 R91 1 5VD 5VAS 99 A 2 5VA FB3 RCA 01 50 47 2 2 6 s O 5VAS P v 1 33 R87 4 SVA T c49 275 10 16 T T C88 1 4W 74HCU04 74HCU04 11 13 gt 11 10 ___ x gt U7 U7 FB4 10 16 L 4 C89 85 100 25 VIDEO INPUTS ree NE 5 476 C140 CVID5 _ i 47 6 uc BYPASS CAPACITORS 5VV UB 3 4 C141 CVID4 2 08 3 081 74HCU04 47 6 51 6 NC 6 6 C142 A CVID3 2 D8 3 D8 N gt gt 5VD 7 07 8 4716 C143 CVID2 ong 3 08 2 C4 C13 C21 C23 C27 C31 C35 C39 C43 C58 5VV 9 aig e AIDE 3 08 1 25 1 25 1 25 1 25 1 25 4 25 4 25 4 25 4 25 1 25 4 25 74HCUOA 4 10 S CVID 2 D8 3 D8 5VD i i i i i i i i i on 8 12 R171 2 R170 2 R169 2 R168 2 R167 2 U7 13 TOI SOK Co ices l co 1 5 c79 _ _ 7 1 b L 1 25 r 125 T 125 125 T 425 125 T 125 1
35. 012 NC 4 DSPAB Di 14 30 14 Ds 23 013 NC 21 02012 DO 15 31 26 014 NC 44 NCO DSPAB_A16 32 5 27 015 vss oln 178 DSPAB_SRAM_CS 5 28014 3 3VD 425 vss2 5 4 R45 SRN 09 0 1 8 DSP ALED 1 DSPAB 2 0 001 54 270 046 DSEAB 5 002 S RED DSPAB A3 4 12 R3 5 DSPAB 4 13 12 A DSP A LED 2 DSPAB A5 14 12 8 270 D3g B DSPAB A6 15 5 SRAM DSPAB A7 16 29 GRN DSPAB_A8 17 74VHC244 3 3V w DSP BLED 1 ee 18 6 016 DSPA tele Sube 270 D2 DSPAB_A10 19 M0 Di DSPAB_D17 2 A3 8 C7 wat yE AW 8 DSPAB_A11 20 10 10 018 2 A3 8 C7 1342 nE RED DSPAB A12 21 15 02 1i 019 3 A3 8 C7 15 v3 R1 5 DSPAB A13 29 14 03 22 DSPAB 020 3 A3 8 C7 17 DSP B LED 2 14 30 14 Ds 23 021 d 270 Dig 15 31 e Da 26 022 8 A16 32 27 023 A16 07 DSPAB SRAM CS 5 5 77 DSPAB WR 275 5 CRN DSPAB RD 2845 R53 qG 3 3VD DSP D LED 2 9 270 D5 H 381 mE 8 568 011 DSP D LED 1 ee D6 5 0 VDD1 2 24 IAW RN DSEAB
36. 206 A 205 B10 207 a s 2 JUMPER W2 TO GND TO USE CONFIGURATION ROM ZA6 11 28 PLL_PUMP_UP E ZAT B12 12 2 D1 9 D4 48 _ _ PEL PUMP_UP 29 PLL PUMP DOWN 110 88 ZAQ 14 m 4896_MCK LOCK_ 1 ZA4 C15 ZA13 A15 44 MAIN_MCKO E 21 ae 815 77 MAIN_MCKO 4101 4 8 Galen ERNSTATUS J48 45 MAIN_CS12 ECK MAIN_DRDVRCS12 FCK 9 D7 RA 22 15 __________ 1 B3 B 2 D1 9 B4 ZONE_DRCVR_MCKO 39 2 DRCVR ZONE 39 ZONE MCKO 4 C1 4 B8 40 ZONE DRCVR RST MEMORY BOARD CONNECTOR TEETH ZONE_ERRISTATUS gt ZONE DRCVR ERR STATUS 45 ANE ESTER 9 C7 ZONE DRCVR CS12 FCK 9 87 4 MHz 20 AUDIO 4 2 2 D1 4 C8 3 3VD MEM 10180 R388 1 83 G AUDIO 87 R322 IO AUDIO LA 12 03 0 33 VIDEO 0 TDI IO 5 0 5 16 L C357 4R326 24 576 7 VIDEO 2 61 DEC TCK Tone 34 3 F 425 10K VDD gt SYNC DETECT 62 43 4 3 8325 56 12 D3 VIDEO 3 TEMP2 lt OUT A J33 GND 9 R314 9 R313 2 U73 4 px 072 o lexicon zoek 01730 TITLE APPROVALS DATE DRAWN SCHEM MAIN BD MC4 MC8 12 ce RWH 2 15 02 MEMORY CONN RAM FPGA 12 C6 CHECKED 3 29 02 SIZE CODE NUMBER REV B 060 1525
37. 3 902 1559 3 19 02 15269 4 1 SHEET 1 OF 8 7 6 5 4 2 1 gt 10 19 2004_8 43 8 7 6 4 3 2 1 REVISIONS 5VV REV DESCRIPTION 5VV 16 74HC4051 1 CHANGED PER DCR 020523 00 dino BS 13 VCC EL4421 R150 ECM KAB _ CVID4 14 YO 5 jue 6 4 02 6 5 02 3 D8 8 B6 9c 15 1 8121 V p 15K BUE CW 3 08 8 86 NC S 2 ay l A 2 UPDATED FOR MC4 PER DCR 040922 00 3 08 8 86 e CVID OUTIN s Nd 8 SY_MAIN NC 5 _ gt vout AV 9 27 04 9 27 04 CVID3 2 ve Y IN 5 08 5 C2 5 gt in2 75 0 CVID5 4 1 8 86 Y7 MVID_SELO 11 ay ES U26 7 C5 MVID_SEL1 10 7 2 SEL2 918 S y ba MY 5VV ics MCVID 6 NH VSS VEE C139 i 4 8 7 U18 S E 2 EL4421 R152 4 y 10 16 6 5VV V 15K 4 Ay 1 5VV IN1 D 2 Y 1 e pm 16 74HC4051 A _ 080 C OUT 5 al 13 R165 20 77 ds gt T 185 8 YO 2 58
38. 0 2 B7 3 B1 FHS1 PIN13 IS PULLED LOW SDATAN3 GPIO27 AUDATA1 HOS Saz 2 87 3 84 PIN12 IS PULLED HIGH FB1 AUDATA2 2 B7 3 B1 CLKIN XTALI AUDATA3 XMT958A 106 DEC 5003 2 87 3 81 2570 15 PLLVDD SCLK1 DSP FILT2 LRCLK1 USH2 PIN143 IS PULLED HIGH 2 DEC GLK SEL 724 FILT1 AUDATA4 GPIO28 172 Ne USH1 PIN2 IS PULLED LOW CLK 128 CLKSEL AUDATAS GPIO29 58 Nc UHSO PIN1 IS PULLED HIGH PLLVSS AUDATAG GPIO30 55 N UE AUDATA7 XMT958B GPIO31 1 3 AA 43 UHS2 CS_OUT GPIO17 gt 15 33K 6 RP4 7 UHS1 GPIO19 26 RP2 1 8 10K L 33K 63 641150 18 DBCK ee Ri 2 GPIO20 DBDALS 68PF 27 GPIO21 9999 23 RP23 6 10K 1 10 2900 2 4 5 10 16 3 3VD DEC_GPIO21 perac DEC GPIO20 CONTRACT J C17 R2 12288MHZ 2 87 3 1 3 1 25 10 01730 3 DEC_CLK 2 87 3 C1 APPROVALS DATE I DRAWN SCHEM DECODER BD MC8 MC12 RWH 3 21 02 DOLBY DIGITAL DTS DECODER U3 CHECKED 3 26 02 SIZE CODE NUMBER REV ac B 060 15319 2 CW 3 26 02 FILE NAME ISSUED KB 3 26 02 15319 2 3 SHEET 3 4 3 2002_ 14 48 N EN 10 2 REVISIONS DESCRIPTION DRAFTER CHECKER _ AUTH RWH CW CHANGED PER DCR 020604 00 RAN 12 6 12 02
39. 11 14 TXDA gt s 8 cts 4 DTR ee FB17 n ic m RXDA 25 5 GND 18 lt R160 lt R159 COM1 TX TXDB lt P FB19 RX1 9 8 RXDB m 214 1 C212 1 C215 T 150PF F 150 029 150 724 77 eT lexicon sonra NO lexicon BEDFORD MA 01730 TITLE APPROVALS DATE R164 56 1_ DEAW BD MC4 MC8 RWH 2 15 02 REMOTE POWER 8 85232 PORTS CHECKED 3 29 02 SIZE CODE NUMBER REV R163 56 COMO RX _ 060 15259 4 41302 HENNE ISSUED kaB 4 3 02 15259 6 11 SHEET 11 23 7 6 5 4 3 2 1 10 19 2004 8 58 74VHCT244 REVISIONS 15V 5VD 4 B1 4 04 VIDEO DATA 2 m 18 A VIDEO BOARD CONNECTOR REV DESCRIPTION A A 4 B1 4 C4 P OSD 2 2 14 5 RWH cw 4C1 4 C4 gt VIDEO REG Sa ni gt 1 CHANGED PER DCR 020430 00 R277 4 C1 4 C4
40. 7 i NOTES 05 4 5VD FP_D2 5 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W FP_D3 6 93 00 7 2 UNLESS OTHERWISE INDICATED RESISTORS 5 26 FP_D1 8 25 _ 1 9 3 UNLESS OTHERWISE INDICATED CAPACITORS UF V 24 IR_AUXIN SRD_LWR VFD_EN IR_DATA VFD_EN 10 23 IR AUXRET 11 5VD 4 DIGITAL 1 ANALOG CHASSIS CHASSIS POWER 22 IR DATA FP 0 12 GROUND V GROUND GROUND SCREW GROUND 2 Encore 5 XX XX DENOTES SHEET NUMBER SECTOR 19 1 6 LAST REFERENCE DESIGNATORS USED C7 022 93 01 R29 SW21 U6 18 C1 17 VFD EN i lt lt T 100UF B 18 i SWRD _LEDWR p ce 7 14 2 B8 12 NC 11 FP A0 FP A 2 0 10 1 2 D8 9 2 8 01 7 DO 6 03 5 52 4 05 3 54 2 07 06 FP D 7 0 bas DOCUMENT CONTROL BLOCK 060 15289 2706 SHEET REVISION TITLE 10F 3 0 777 20F 3 0 CONTROL amp STATUS 3 0 SWITCHES 8 LEDS FERENGE COPY Gia 2002 Lexicon Inc z A ve exicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM SW LED BD MC8 DRAWN 12 21 01 CHECKED KAB 1 4 02 SIZE CODE NUMBER REV amp ac P B 060 15289 0 ISSUED kaB 1 8 02 15289 0 1 SHEET 10r 3 e 8 6 5 3 2 1
41. 21 07 DATA1 ADR19 D2 46 ADR20 15 NC 4FSC GND 03 27 DATAS U34 2 lt 40K D5 49 DATAA XS i7 5VV DG 50 DATAS EXS 0 t 5VV 4 57 51 DATAG n 1 1 74 4053 16 4 17 73448 NC 2 vec 050 CS a PALEN 75 7 B5 7 B4 8 D4 Y 10 C5 7 B5 E S L1 GND 5 INH A 0mm U33 5 VSS VEE L c109 14H 031 035 7 els vy alt 10PF Cr 15PF v 5VV m 4XFSC OSCILLATORS CONTRACT exicon 3 OAK PARK ON SCREEN DISPLAY A 15 0 BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM VIDEO BD MC4 MC8 RWH 3 13 02 D 7 0 ON SCREEN DISPLAY CHECKED 3 48 02 SZE CODE NUMBER REV E 3 Q C cw 3 19 02 FILE NAME 060 15269 ISSUED KB 3 19 02 15269 46 sHEET 5 OF 8 8 7 6 5 4 3 2 1 gt 10 19 2004_8 34 8 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 CHANGED PER DCR 020523 00 KHA NE ECM KAB 6 4 02 6 5 02 SYNC STRIPPER 2 UPDATED FOR PER DCR 040922 00 NUM EUM AT AT 5VAS 9 27 04 9 27 04 5VV 4 4 NJM2229 15 Vl 8 LF353 V 5 74HC02 vipEO IN vsYNc out 19 8 10 VSYNC _ VIDR 1 9 gt o 5 C8 1 25 7 14 NC lt R16 Ra EPP SYNCDETOUT 2 40K
42. DRAWN RWH SCHEM MIC DSP BD MC8 5 20 02 MAIN BD CONNECTOR CHECKED KB cw 5 29 02 SE CODE NUMBER REV 060 15389 2 6 3 02 FILE NAME ISSUED KB 6 3 02 15389 2 1 1 OF 10 2 1 12 28 2004 16 35 8 7 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH 1 SHOW DEPOPULATION FOR BD PER 041201 00 12 9 04 12 9 04 3 3VD MASTER IDOHIGH IDILOW pki SLAVE 120 LOW ID1 HIGH ABWR WR RD ee RR 9 4 9 ee ABRD 5 A ENS HOST CS TES SRAM 5 gt 98668 9867 d 9 RAS 2 D1 3 D3 4 C8 ABSDRAM CS e 5 SDWE D IAEA DSPAB_CAS cei DSPAB_SDWE DSPAB_SDCKE DOM e DSPA_CLK 30 DSPAB_SDA10 P sey S DO
43. DSP_CS 3 03 amp _ DSP_RST CONTRACT z lexicon sop BEDFORD MA 01730 TITLE APPROVALS DATE DRAWN SCHEM MAIN BD MC4 MC8 RWH 2 15 00 psp BOARD CONNECTOR CHECKED cy 3 29 02 SIZE CODE NUMBER REV 060 15259 4 cw 41302 FILENAME ISSUED kaB 4 3 02 15259 6 5 SHEET 5 OF 23 7 6 4 2 1 10 19 2004_ 8 58 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 Nono Ps e KB KB 6 4 02 6 26 02 2 CHANGED PER DCR 020731 00 3 3VD 5VD CBV KB 8 5 02 8 14 02 RWH CW 3 CHANGED PER DCR 020827 00 Rona 134 C32 9 12 02 9 12 02 ADDIOLTOUI AUDIOO 2 4 UPDATED FOR PER DCR 040922 00 ew C31 9 24 04 10 14 04 DB0 IO A31 AT AT 2 83 wn C30 9 27 04 9 27 04 DBO AUDIO1 A30 C29 DB0_AUDIO2 A29 C28 DB0_AUDIO3 28 C27 DB0_AUDIO4 27 26 DB0_AUDIO5 A26 25 DB0_AUDIO6 25 24 DB0_AUDIO7 A24 C23
44. 83 DSPCD DT4 DSPCD_A1 2 24 DSPCD_RAS 19 82 DSPCD_D13 DSPCD_A2 3 5 1 5 02 6 03 RAS DQ13 2 5 1 5 02 6 03 CAS 12 50 DSPCD D12 4 PCD _SDWE as Dot 79 DSPCD Dii DSPCD A4 13 128 8 502 DSPCD_SDRAM_CS 204 WE 77 _ DSPCD_D10 5 1256 5 C1 5 C2 6 D3 CS 7 BSPCD Dg ae AS 09 74 DSPCD_D8 PCD 7 A6 SRAM 5 1 5 02 6 03 ST DQ8 13 BSpGD D PERA A7 5 1 5 02 6 03 SDCLK 502 DSPCD D6 9 188 2 6 DSPCD 08 NC 73 096 10 05 DSPCD A10 19149 DSPCD 09 NC 70 NCS 095 DSPCD DSPCD A11 20 0 0410 DSPCD 210 NC 69 05 Dasz DSPCD D3 DSPCD 24 M2 DSPCD Dii NC 57 NCa Dao 5 DSPCD 02 DSPCD A13 29 D4L22 DSPCD 12 NC 30 L4 DSPCD Di DSPCD 14 30 413 23 N oil 0912 03260 00 DSPCD A1 31 82 26 DSPCD Di4 NC 14 PCD A16 27 DSPCD 015 NCO vss VSSQ pr 33 4 PCD_SRAM_CS 3 3VD U11 DSPCD_A0 1 8 DSPCD_A1 2 40 VDD 75 DSPCD 2 3 VDD2 DSPCD 4 1 2 5 3 128KX8 5 12 5 17 DSPCD 18 6 DSPCD 016 DSPCD 19 49 D DSPCD D17 DSPCD A11 20 10 01 16 DSPCD D18 DSPCD 211141 02 77 DSPCD D19 DSPCD_A13 29 412 03922 020 DSPCD A14 30413 DSPCD D21 DSPCD A15 31 Da 26 DSPCD D22
45. 97 95 Digital DIG_MAIN_COAX1_IN_48K_TO_ANLG_MAIN_OUT DIG MAIN COAX1 IN 48K TO ANLG MAIN OUT GAIN 3 40 00dBFS 0 00dBFS 997 Vrms Level 8 10 8 83 7 43 40kHz LP 100k lt 10 gt 500k 1 8 5 7 2 4 6 8 11 48000 Digital DIG MAIN COAX1 IN 48K TO ANLG MAIN OUT THD 3 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100 lt 10 gt 500k 1 3 5 7 2 4 6 8 na n a 11 External 48000 Digital DIG MAIN COAX1 IN 48K TO ANLG MAIN OUT DYNRNG 3 60 00dBFS 60 00dBFS 997 THD N gt 110 00 108 00 140 00 40kHz LP 100k 10 22k 135 7 2 4 6 8 11 External 48000 Digital DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT DIG MAIN COAX1 IN 44K TO ANLG MAIN OUT 3 40 00dBFS 0 00dBFS 997 Vrms Level 8 10 8 83 7 43 40kHz LP 100k lt 10 gt 500k 1 9 5 7 2 4 6 8 External 44100 Digital DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT_THD 3 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100 lt 10 gt 500k 19 5 7 2 4 6 8 11 44100 Digital DIG MAIN COAX1 IN 44K TO ANLG MAIN OUT DYNRNG 3 60 00dBFS 60 00dBFS 997 na dBr THD N gt 110 00 108 00 140 00 40kHz LP 100k lt 10 22k 1 3 5 7 2 4 6 8 n a 11 External 44100 Digital D A XLR Tests MC 8B ONLY Digital Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio T
46. ADG451 U17 1 21K 330 63 VCG VDD 125 6 p 4 AX i 145 15 I RREAR DACOUT 20 A8 499K IN GND 6 49 U7 1n 4 5 15V 15V 5VAD 17 88 18 A3 19 B8 s MAIN RLY_CNTL 12 ADG451 VDD 14 A2 19 B4 RSUR_DIR_IN 3 5 2 0 IN LEFT amp RIGHT REAR VEE GND LEVEL CONTROL T 4 5 U7 77 15V R27 C21 lt LREAR 21 C8 100 22 85 622 5 A OdBFS 8 1Vrms 1125 15 12 2 10 2848 gt J2 LREAR_DACOUT 16 14 G17 R6 FB3 RELAY 2003 ANL AOUTL pi EET LEFT REAR OUT 4 D4 17 88 18 B8 19 B8 VAINOUT VC 6 4 n 67 6 4 C4 17 A8 18 B8 19 B8 VAINOUT VC DATA 3 gt 8 450PF A s REAR VC CS 2 8 at _ p NIIT n 1 21 83 REAR VC ZCEN Lil Ese Bis v 18 A8 19 A8 21 B3 VC MUTE spout 9 LEN 92 lt 20 c3 RREAR_DACOUT 9 ANR AOUTR l ES 4 RIGHT REAR OUT 41125 _ 100 AGNDR VA C4 10 134 02 gt 10K RY2 150 T C19 pe u sa 1 25 3 OAK PARK gt NO 2 exICOn Was BEDFORD MA 01730 C 22135 TITLE APPROVALS DATE L R29 ren 4 8 by RWH 2 15 02 15V 54 21 8 REAR DACS 100 CHECKED cy 3 29 02 SIZE
47. REFERENCE ONLY AND DOES NOT SUPERSEDE SCRW M3X6MM PNH PH BZ BOM 022 15424 COMMON 640 10498 2 PLCS BOM 022 15423 MC 8 B TORQUE 4 6 IN LBS BOM 022 15756 50 5 SCRW 2 56 1 4 PNH PH ZN MAY 6 2004 Awe CABLE 079 SCKT SCKT 4 4 4680 14854 CABLE 100 PLUG SCKT 2 7 10 5 680 14693 NOTE PIN 1 OF CABLE MOUNTS TO PIN 13 ON DISPLAY irum eos om ASSY DWG MECH SDP 5 XXX 005 MC 8 B 5 5 MC 8 CHECKED 6 14 02 FSCM NO 006 NO NEXT assy USEDON P pP P 0B0 15463 APPLICATION DO NOT SCALE DRAWING NOT SCALE DRAWING SSUED 7 31 02 sene 1 2 10F 1 5 4 5 2 1 8 7 6 5 4 5 2 1 zs D D REMOTE CONTROL 750 15480 8 Rum 750 15775 50 5 T BAG BATTERIES PLACE HERE C AA BATTERIES 2 C 1460 08345 CLEAR BAG 2X3 Co gt 4730 15483 a TRAY ACCESSERY 730 15286 17 75 12 125 2 5 NOTES 7002 9 AVN y N SCRW M4 FH 640 14680 6 CLEAR BAG 3X5 730 02824 BRACKET MTG RACK PUT LITERATURE IN BAG 1 PART NUMBERS SHOWN ARE FOR 701 15453 2 PLACE REFERENCE ONLY AND DO NOT 70 02883 2 PRE BOM MES CLEAR BAG 12X12 022 15754 60 5 INCLUDE MTG BRKT
48. 1278 1289 1298 1308 C1318 1328 1338 1348 C1358 1368 C1378 gt gt 74LCX14 3 3V 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 amp U q i U i 11 10 R87 333DSPCD ICE eo s P SIDA SIA8 c1388 c1398 1409 1418 1428 1438 1448 1458 1468 1478 1498 1508 74 14 3 3 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 gt MICROPHONE BIAS VOLTAGE SUPPLY 15VA 1 1 4002 CASE VOUT R1 5 R1 4 vouT 2 gt A AA 330 2 2 c37 R20 D10 67 1036 ADJ 237 1 N4002 K 22 16 1 25 4L C41 R16 PUE 1 012 55 7 10 16 e 9 C7 2 2K R23 4 lt 1 50 E NR R23 MICIN2 BYPASS CAPACITORS 330 2 2K 15VA L C17 R30 T 10 16 A 2 2 2 Ed C16 22 30 58 C26 1 25 1 25 1 25 1 25 1 25 R40 R39 22 16 AS MIC_IN_3 9 B7 e o o o o o o 330 2 2K a c9 ct5lc211c29 1Cc56 216 1 25 1 25 1 25 1 25 1 25 10 16 AA 3 i i 2 2 R51 R50 AA AA MIC_IN_4 330 2 2 exicon 9 NO lexicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM MIC DSP BD MC8 DRAWN 5 20 02 BYPASS CAPACITORS amp DSP CLOCKS CHECKED xB 5 29 02 SIZE CO
49. 2VID_SEL2 7 013 gt 7 1 4 775 R98 ZCVID_EN 750 cs 2940 vore VSS VEE 2 5VV 8 8 011 40 736 M T 7 x8 5VV 5VV 4 16 74HC4051 13 yo 1 B7 2 C8 574 14 YA x 1 C7 2 C8 Y2 N ja 1 C7 2 C8 5 Ma OUT IN 2 Y6 6 8K 1 7 Y7 5 C61 R100 sczoNE SYZONE V3 125 75 0 5 1 VSS VEE 3 8 7 U10 N V 8 Y 475 1 6 2 S VIDEO OUT 1 COMPONENTS ON THIS PAGE ARE NOT INSTALLED ON 4 5VV 16 74HC4051 13 yo VCC 1 84 2 B8 SER 14 YA x e 1 C4 2 B8 NC 12 B s C64 1 C4 2 B8 SC1 1 Y4 OUTIN As SCZON 503 2 6 5 1 84 R112 d 100K 2 10 96 R111 INH 750 VSS VEE 1 R1105 5 R108 8 7 U9 00 A R106 5 D 8 1 15K A y 51 4 15 PU Y 5VV 15K ZSVID_SEL0 ZONE 7 5 R105 as ZSVID_SEL1 AA 20 VIDEO ZSVID_SEL2 1 7 5 pe 75 0 OUT 1 CONTRACT 9 50 01730 8 5 THTLE DRAWN SCHEM VIDEO BD MC4 MC8 RWH 3 13 02 ZONE CHECKED 3 48 02 SZE CODE NUMBER REV 3 Qc cw 3 19 02 FILE NAME 060 15269 ISSUED KB 3 19 02 15269 4 3 3 OF 8 8 7 6 5 4 3 2 1 gt 10 21 2004_8
50. Connect a digital audio cable from the output of the Digital Function Generator to S PDIF coaxial input 1 on the rear of the MC 8 Connect an audio cable between the left front RCA output of the MC 8 and the input of the Analog Distortion Analyzer Using the remote control Menu arrow scroll through the Diagnostic Menu and select the Audio Tests In the Audio Test Menu highlight S PDIF Input CX number 1 Test then press the Menu arrow to engage the test The MC 8 is now set to pass digital audio from the S PDIF coaxial RCA input 1 to the front left and right RCA output Gain Test GAIN Po NM Apply a 997Hz signal 0 00dBFS 1Vrms to S PDIF coaxial input labeled 1 Set the scale on the Distortion Analyzer to measure 8Vrms signal level Turn all the filters off on the Analyzer Filters not required for Gain Test Verify that the output level measurement from the MC 8 is between the range of 3 73Vrms and 4 47Vrms Note this level Total Harmonic Distortion Noise Test THD N 1 4 6 Adjust the scale on the Distortion Analyzer to measure 0 001 THD N and turn on the 40kHz low pass or audio band pass filter Sweep the oscillator frequency from 20Hz to 2kHz and 8kHz to 40 2 Verify that the THD N measured on the Analyzer is less than 0 005 20Hz to 2kHz and 0 0175 8 2 to 40 2 Lexicon Frequency Response Test FREQ 1 Set scale the Distortion Analyzer to measure 8V
51. DSPCD SDCLK 097 13 DSPCD 07 DSPCD A8 ms P 11 DSPCD 06 DSPCD A9 18 pg 6 DSPCD 08 NC 73 NC6 Dos 10 _ DSPCD 05 DSPCD A10 19 p1 Z DSPCD D9 NC 701405 Daa 8 DSPCD 04 DSPCD_A11 20 A41 O DSPCD_D10 NC 69 003 _ DSPCD_D3 DSPCD_A12 21 A12 ps 11 DSPCD_D11 NC 57 Daz 5 DSPCD 02 DSPCD_A13 29 4 22 DSPCD_D12 NC 03 Da1 4 DSPCD Di DSPCD_A14 30 4 Ds 23 NC 21 Dag L2 DSPCD DO DSPCD A15 31 Aje 26 DSPCD Di4 NC DSPCD A16 32 de 27 DSPCD D15 vss VSSQ anlo olo 158 DSPCD_SRAM_CS 5 uli EIS DSPCD WR 12 W DSPCD_RD 2815 3 3VD 28 VSS1 2 852 5 U4 DSPCD_A0 1 8 DSPCD 2 7247771 DSPCD A2 DSPCD 44 5 DSPCD A4 13 A4 128KX8 DSPCD A5 14 5 128 DSPCD_A6 15 SRAM DSPCD_A7 16 9 DSPCD_A8 17 DSPCD A9 18 po 5 DSPCD 016 DSPCD A10 19 p4 Z DSPCD D17 DSPCD A11 20 4 O DSPCD DSPCD A12 21 AJ ps 11 DSPCD 19 DSPCD A13 29 p4 22 DSPCD 020 DSPCD A14 30 Aja Ds 23 DSPCD 021 DSPCD A15 31 s 09 26 DSPCD 022 DSPCD A16 32 6 27 DSPCD 023 DSPCD SRAM CS 5 E DSPCD WR 1245 DSPCD_RD 28 13 9 3 3VD 25 VSS1 VSS2 2 02 DSPCD_A0 1 8 DSPCD_A2 3 155 DSPCD A3 4 DSPCD A4 13 A4 128KX8 DSPCD A5 14 5 128 DSPCD_A6 15 SRAM DSPCD_A7 16 9 DSPCD A8 17 DSPCD A9 18 6 DSPCD 024 DSPCD A10 19 p1 Z DSPCD 0
52. SRAM ABSDRAM ABRAS ABCAS PAB_SDWE season PAB_SDCKE PAB_SDA10 ABSDA10 SAID ABSDCLKS DSPAB CPA BERT eram DSPAB_BR2 CONTRAGT 3 01730 APPROVALS DRAWN RWH CHECKED KB TITLE SCHEM DSP BD MC8 2 28 02 DSP A Q C ISSUED KB 3 5 02 SIZE CODE NUMBER REV ud B 060 15309 1 3 5 02 FILENAME 3 5 02 15309 2 2 5 20F 9 N EN 11 1 8 2002 15 51 8 2002_15 51 REVISIONS CHECKER AUTH PER DCR 020429 00 und Rd 5 6 02 5 13 02 3 3VD MASTER 100 HIGH 101 LOW SLAVE ID0 LOW ID1 HIGH TEST POINTS 44 O R43 2 D1 2 D3 4 C8 DSPAB SDWE P 201 203 4 8 DSPB_1A_SDO DSPAB_DQM aca haps Bie Spa DSPB iB SDO SDCKE P 2 01 2 03 4 DSPB_CLK 30 DSPAB_SDA10 2 01 2 03 4 8 9 04 NC SERE RDALE 2 D1 2 D3 4 D8 Ne 2 D1 2 D3 4 C8 152 2103 AB_RST 157 144 DSPAB_BMS TR 143 SDRAM 5 2 C8 8 C4 8 C1 be DSPAB_ACK 69 DSPAB HOST CS 2 D1 2 C3 8 C7 USE ESUIR
53. dite GND v 3 5151 UNITY GAIN PASS THRU 5 100 di 013 10 25 3 99 7 1 4W 12153 8 1 Sd LEFT ZONE IN 16 04 C194 5 R148 11 52 R196 150 100 10 57 58 R201 L SE A0 A1 A2 EN 100K 1 16 15 2 0416 ZONE_ANLG_SEL0 Y T 14 C5 21 C3 ANLG_ R143 C190 14 C5 21 C3 ZONE_ANLG y 21 63 ZONE ANLG SEL2 L A 100 D11 10 25 8 4 4W BAV99 14 C5 21 C3 ZONE_ANLG_EN C188 lt 8144 150PF lt 100K 15V 5VAD s 15V D ADG451 UNITY GAIN PASS THRU 3 l 184 5 D t R139 SD CNTR_DIRIN 18 4 e T VEE GND R192 UB 4 4W 19 U40 J9 4 5 C182 5 R140 L 150 lt 100K 15V 15V 5VAD 57 15V Y 4 4 13 12 ADGA51 VDD 178 16 9 6 VA RCA 10 25 R193 J8 4 5 U40 gt 100 176 lt R136 150 5 100K v 15V V 57 R131 C172 15V 7 A 10 25 4 4W 99 13 12 06451 UNITY GAIN PASS THRU L 170 4 R132 4 VDD T 150PF lt 100K 5 14 A5 21 D3 ANLG 4 5 DIR IN P LSUR DIR IN 20 4 VEE GND R194 Y 4 5 40 V lt 15V 8 15V 5VAD 4 03 10 25 4 4 BAVo 13 12 ADG451 F ONTRACT I 3 OAK PARK NO VDD 6 5 p 7 exicon BEDFORD MA 01730 14 A5 21 03 ANLG 7 8 DIR IN APPROVALS TE b VEE GND lt R195 SAN SCHEM M
54. gt 500k 1 2 gr 19 Internal 96000 Analog ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_XTALK 8 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 None 100k 10 gt 22k 1 2 f 19 Internal 96000 Analog ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_SNR 8 OFF OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100 lt 10 gt 22k 1 2 7 19 Internal 96000 Analog ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT ANLG_MAIN_IN8_96K_TO_ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 7 80 8 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 8 20 Internal 96000 Analog ANLG_MAIN_IN8_96K_TO_ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100 lt 10 gt 500k 1 2 8 20 Internal 96000 Analog ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_THD 8 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N 005 010 010 020 00005 40kHz LP 100 lt 10 gt 500k 1 2 8 20 Internal 96000 Analog ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float Level gt 85 00 80 00 150 00 100 lt 10 gt 22k 1 2 8 20 Internal 96000 Analog MAIN IN8 96K ANLG MAIN OUT SNR 3 OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 None 100k 10 gt 22k 1 2 8 20 Internal 96000 Analog ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT ANLG_MAIN_IN345_96K_TO_ANLG MAIN DIR OUT GAIN 3 4 00 Vrms 4 00 Vrms 997 20 Unbal Float
55. 16 LSIDE 2 08 tis StS RREAR el 55 _ lc lc oo 27 des GND 6 BREARY 2788 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 2 88 20 LREAR 2 88 21 9 GND 7 L gt 1 23 15V 24 RZONE RZONE 5VD LZONE 8 A LZONE 58 5V 30 EXPOUTS MUTE gt gt 1 5 2 A5 ZONE RLY CNTL 32 33 MUTE J11 15V 7 22 2 5TURN 15V c92 T 560 35 i c91 FB21 T 560 35 NOTES 1 15V 2 5TURN 15V LZN2 mE 545 5VD ZONE2 OUTPUTS 3 C3 LZONE 4 2 94K 15V 3 01K C32 196 196 C29 L LZN1 18PF 2134 425 1 R14 LEFT ZONE OUT 02 22 C31 J2 ONE R15 15V R18 18PF R13 3 C3 gt 22K ane cas 1 51 47 25 1 4 RY2 RZN2 Ak R6 RQ e 3 C3 RZONE 2 94K 15 3 01K C25 1 1 RZN1 18PF 2134 1 RIGHT ZONE OUT C24 R11 15V J1 n 3 OAK PARK NO 18PF 3 C3 pe RZONE Ay 01730 2 94 3 01K TITLE 1 1 DATE SCHEM XLR BD MC 8B OdBFS 2 0Vrms OdBFS 4 0Vrms E ow ZONE2 OUTPUTS 9 74 VAW RY1 CHECKED 4 9 02 SIZE CODE NUMBER x at B 060 15349 o RWH 419 02 a ISSUED _ 4 10 02 15349 0 3 3 8 N 8 7 6 5 4 3 2 1 5 10 EURO64 RA M C32 A32 5VD 3 3VD 4 AUD 00 DSP C31 A31
56. 1913 OdBFS 1 7Vrms 24 1 25 pr 1 25 1 25 E13 1 4 9 12 02 9 12 02 J21 a T 13 32 ADG451 4 UPDATED FOR MC4 PER DCR 040922 00 RWH Cw R107 C98 R67 9 24 04 10 14 04 AK4395 s 2 gt m 121K 33063 R66 280 1 5 D LREAR_DACOUT 2088 9 27 04 9 27 04 2 1 576 2 1 Sc IN 1 lt __ REAR DAC MCKI 3 17 1 C124 C71 GND 4 82 MCLK VREFH 220PF T y 4 s U 18 D8 19 D8 21 83 MAIN 4 AOUTL 23 15 MAIN_DAC_SCKI1 5 22 R109 099 R65 er 4 C1 4 C2 19 D8 BICK AOUTL voe oo 4 e 15V 1 21K 330 6 3 280 220 N 4 C1 4 B4 REAR_DAC_SDI 6 pzeR 28 1 1 R64 ANAVAN 4 C1 4 C2 19 c8 MAIN DAC FSI 7 27 499 R62 A 13 12 4 C4 18 C8 19 C8 CS 868 pzrL 26 Eos LSUR DIR 1 Me VDD 9_ P S AN 13 A2 19 C4 LSUR_DIR_IN 6 5 pf 32 IN 4 4 17 8 18 8 19 8 MAIN_DAC_CCLK 19 4 VEE GND 4 C4 17 C8 18 C8 19 C8 MAIN 11 AOUTR 21 4 5 U 121K 32063 R71 12 piro AOUTR 20 1 5 76K 2 18 C4 19 C4 21 83 MAIN DACOUT hor 7 AGND 9 C126 Leis 1 18 4 19 4 21 83 I T 1500 14 16 15V 5VAD DIF2 VREFL 47 R111 C101 E14 4 1 C127 a A 13 12
57. 1958 5842 58420 lt 419 ug 220 5220 220 YEL GRN YEL L 051 050 49 R180 5VD oe 5VD A REAR PANEL IR INPUT 1K 1 2 DM IR DATA 2 BLACK 2 58 Rais R416 18 99 IR0_AUXIN 24 10K 2 10K 2 23 1 22 IR DATA 21 ENCODER ined I 20 ENCODER_A t 1 A8 1 C1 020 77 18 R417 gt R418 gt VED_EN_BUF 17 1002 1002 __ SWRD LEDWR 16 2 C3 gt 15 C411 C412 FP RST 14 01 50 01 50 5 13 74NHCT244 NC 12 2 0 18 FP A0 11 2 1 4l 6 _ 1 10 s PIC 22 5 3 Gel 00 7 us 4 D4 2 D8 4 D7 5 C7 6 C6 7 C6 8 C6 220581 Dd 1 D4 2 D8 4 D7 5 C7 6 C6 7 C6 8 C6 FP_D7 2 FP_D6 1 446 77 74VHCT245 3 IODY 7 0 FP D 7 0 CONTRACT A 3 D6 4 D7 ZM B NO e XICO n 3 OAK PARK 4 AS P FRONT PANEL CONNECTOR BEDFORD MA 01730 A4 B4 6 APPROVALS LE TA SCHEM MAIN BD MC4 MC8 gj 6 86 DRAWN RwH 2 15 02 87 SHECKED FRONT PANEL STANDBY VIDEO CONN A8 B8 CV 3 29 02 SIZE CODE NUMBER REV 2 3 ERONI PANEL 1926 060 15259 4 2 D1 2 D3 3 D7 3 C7 5 A7 6 A7 7 A6 8 A6 DIR 413102 997 ISSUED Kap 4 3 02 15259 6 12 SHEET 12 OF 23 8 7 6 5 4 3 2 1 10 19 2004 9 02
58. 43 2 ZONE _ 48 ZONE DAC FSI gt 9 87 1 2 R265 56 SIDE DAC MCKI e LUE 9 84 2 _ ZONE DAC FSI e 4 C1 16 C8 gt RA DAC 19 D8 VIDEO CONTROL 9 B4 ZONE 42 ZONE DAC 5 47 8 ZONE_DAC_SCKI L 1 16 8 U58 9 B4 ZONE EP 41 ZONE ZONE DAC 119 ZONE 4 C1 16 D8 OSD 9 B4 BONE ERE 36 ZONE ZONE 801 35 BEEN 4 C1 16 C8 74VHC04 3 3V OSD REG 9 84 ZONE_ERF ZONE_NRZO E 9 7 97 8 R268 56 REAR DAC MCKI 20 D8 SCR VIDEO SCLK _ DSP AUDIO 10 0 AUDIO2 136 138 psP Aubioo DSP_AUDIO 10 0 U58 VDATA e VIDEO DATA 4 B4 5 D6 DSP AUDIOS 132 DSP_AUDIO2 DSP_AUDIO0 157 DSP AUDIOT 4 87 5 06 DSP_AUDIO7 129 DSP AUDIOG DSP_AUDION 135 DSP_AUDIO3 DSP_AUDIO8 128 DSP_AUDIO7 DSP_AUDIO3 134 DSP_AUDIO4 PIC CLOCK DSP_AUDIO9 126 DSP_AUDIO8 DSP_AUDIO4 133 DSP_AUDIO5 DSP_AUDIO10 125 DSP AUDIOS DSP_AUDIOS 7 57 DSP_AUDIO_4MHZ MHZ SPO 152 DSP_AUDIO10 DSP_AUDIO_4MHZ 5 7 1MHZ B C7 DSP AUDIO SPO SPARES AUDIO 10 0 84 6106 ime 28022 0 0 __ AUDIO 19 060 AUDIO2 AUDIOO 16 4 87 6 06 7 24 DB0_AUDIO6 DBO AUDIOT 55 AUDIO3 27 DBO AUDIO AUDIOS 51 AUDIO4 74VHC04 3 3V DB0_AUDIO8 DB0_AUDIO4 11 10 9 29 22 AU
59. 5VA Y Y 15 15 j SEE NOTE 1 5VA NOTES 15V 5VR 1 INSTALL FOR USE WITH POWER SUPPLIES WITHOUT 5V 5VR REGULATOR DIGITAL POWER S 1N4002 3 3V REGULATOR IND 5VD 5VD A D48 9 3 3VD 5V POWER CONNECTOR lt ETI 5VD J45 e 4 1 4002 eae em 1 RED 100 25 C409 Sios LMS1585A 7805 410 T 22 0 11 CASE VOUT L C291 D25 FROM POWER SUPPLY 3 BLACK 150 125 TERM GND 7 4 BLACK emn VOUT i 4 2 4 1N4002 T 24UH TO 220 GNDD _ C404 C402 GND C403 T1125 560 35 T 10 10 ve 4 5VA 5VD A A J29 3 3V CONNECTOR USED ONLY IF ALTERNATE SUPPLY USED 4 2 CONTRACT 3 TO VIDEO BOARD NO 3 pt 100 25 C406 C407 BEDFORD MA 01730 1 RED cA 150 FROM SUPPLY 2 BLACK ee Pag APPROVALS TE E DEAW SCHEM MAIN BD MC4 MC8 2 15 02 power SUPPLY CHECKED 3 29 02 SIZE CODE NUMBER REV Qc B 060 15259 5 cw 413102 ETE NAME ISSUED kaB 4 3 02 15259 6 22 SHEET 22 23 8 7 6 5 4 3 2 1 10 19 2004 8 58
60. 60000000 6 00004 2 1 CHAPTER 3 SPECIFICATIONS 3 1 CHAPTER 4 FUNCTIONAL VERIFICATION 4 1 4 1 Functional Audio V O Tests e EE EL 4 2 Audio Performance 4 5 Video Input Output 5 4 9 Lexicon Audio Precision ATE 4 11 CHAPTER 5 TROUBLESHOOTING aeta 5 1 Diagnostic Categories nnas 1 u a ua al aa aaa a eet 5 1 cene e eui tu RR 5 1 Diagnostics User Interface 5 1 i a o Em 5 2 Power 5 8 Extended Diagnostics Tesla uu 5 11 Repair Diagnostics 5 5 12 Functional Diagnostic Suite a 5 14 Repair Diagnostic Sute 5 19 Audi O Naa 5 20 Video VO euda diora Tail 5 21 CHAPTER 6 THEORY OF OPERATION a t itat 6 1 Main Board 2180 Host 6 1 amp 6 3 Host Interface to Other 6
61. 8 B4 8 C1 TFS0 8 A4 _ 5 TCLK0 12 DTOB RFS1 RCLK1 DR1A DR1B TFS1 __ DSPD 1A SDO TELKA spp 500 1B_ DT1B NC 26 PWMEVENTO NC 24 PWMEVENT4 A18 39 DMAR2 519 DMAG1 DSPCD A 23 0 DMAG2 5 83 7 D5 4041 5 82 DSPCD_DO 1 NC 52 Hee en 83 DSPCD D1 55 84 DSPCD 02 NC D2 86 DSPCD_D3 56 REDY 87 DSPCD D4 SBTS 04 88 DSPCD_D5 05 _ _ DSPCD_CPA 65_ 90 DSPCD 06 DSPCD_BR1 27 DS DSPCD_D7 DSPCD_BR2 28 BR 07 92 DSPCD_D8 08 96 DSPCD_D9 22 DSPCD EMU 1455 97 DSPCD_D10 ABL a DSPD 146 ENG 10 DSPCD D11 DSPC_TDO 148 100 DSPCD 012 SAS gt DSPCD TCK ABUT DSPCD_D13 DSPCD_TMS 149 104 _ DSPCD 014 Se E DSPCD TRST 147 we Dis 107 DSPCD D15 5 B6 8 84 s DSPCD STATUS FULL 192 FL AGO BU 108 DSPCD DI 8 B4 P FLAG1 111 DSPCD D18 2 B8 3 B8 5 B8 8 B4 E FLAG1 D18 NC 499 CAGI 018 112 DSPCD_D19 201 D19 113 DSPCD D20 138 FAGS 020 116 DSPCD D21 021 417 DSPCD D22 022 118 DSPCD_D23 D23 E121 DSPCD D24 024 122 ___ 5 _025 79 025 123 DSPCD_D26 78 FL 126 _ DSPCD 027 NC 76 127 DSPCD_D28 028 128 DSPCD_D29 NC 102 132 _ DSPCD D30 NC1 D30 W DSPCD D 31 0 103 2 031 138 031 zDI3101 5 A3 7 D7 8 B4 NC3 Ne 242 BMSTR 53
62. ANLG ZONE XLR OUT 600 1 00dBFS 1 00dBFS 100 n a THD N lt 002 005 0002 40kHz LP 100 lt 10 gt 500k 21 22 11 96000 Digital DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_RELAY_MUTE DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT RELAY MUTE 40 00dBFS 0 00dBFS 997 n a Vrms Level 135 00 120 00 1001 00 40kHz LP 100k lt 10 gt 500k 21 22 11 External 96000 Digital DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT GAIN 3 40 00dBFS 0 00dBFS 997 n a Vrms Level 16 10 17 60 14 80 40kHz LP 100k 10 gt 500 13 15 17 19 14 16 18 20 11 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT FREQ 3 1 0048 6 i 00dBFS 10 20 40 n a n a n a dBr Level lt 0 05 0 25 0 05 0 1 0 5 None 100k lt 10 gt 500k 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT THD 3 1 00dBFS 1 00dBFS 20 1k 5k 40k n a THD N lt 003 010 005 020 0002 40kHz LP 100 lt 10 gt 500k 13 15 17 19 14 16 18 20 11 96000 Digital DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_XTALK 3 1 0008 5 1 0048 5 15 n a Level gt 83 00 80 00 150 00 None 100k lt 10 22k 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a n a na THD N
63. IR Encoder Board Assembly 202 00528 RES CF 5 1 4W 820 OHM 202 00530 RES CF 5 1 4W 1 2K OHM 202 00531 RES CF 5 1 4W 1 5K OHM 245 03609 CAP CER 1uF 50V Z5U AX 80 20 345 14780 IC INTER GP1U28 38kHz IR DET 430 10594 LED T1 3 4 IR 430 14487 LED T1 BLU 430NM 430 14787 LED T1 RED 700NM 430 14788 LED T1 YEL 585NM 452 13640 SW RTY ENC 24POS INC B 25L VRT 630 14778 SPCR LED T1 375 H 680 14082 CABLE 100 PLUG SCKT 2X7C 3 L 710 13690 PC BD IR ENC MC12 Assembly 700 14838 HOUSING VCO MC12 700 14839 COVER VCO MC12 202 09899 RESSM RO 5 1 10W 47 OHM 245 09895 CAPSM CER 10pF 50V COG 10 245 12485 CAPSM CER 1uF 25V Z5U 20 270 11545 FERRITESM CHIP 600 OHM 0805 270 14359 COILSM VAR 1UH 5 5 6X6 2X6MM 300 13881 DIODESM VARACTOR BB132 20 000 20 000 2 000 20 000 40 000 20 000 2 000 20 000 30 000 20 000 20 000 2 000 2 000 2 000 10 000 10 000 10 000 1 000 10 000 1 000 1 000 1 000 1 000 2 000 1 000 1 000 1 000 1 000 1 000 1 000 3 000 1 000 1 000 1 000 1 000 1 000 1 000 4 000 1 000 1 000 1 000 R7 10 17 20 27 R30 37 40 47 50 R57 60 67 70 77 R80 87 90 97 100 R3 4 13 14 23 24 R33 34 43 44 53 R54 63 64 73 74 R83 84 93 94 1 2 5 6 15 16 25 26 35 36 45 46 55 R56 65 66 75 76 R85 86 95 96 R8 9 11 12 18 19 21 R22 28 29 31 32 38 R39 41 42 48 49 51 R52 58 59 61 62 68 R69 71 72 78 79 81 R82 88 89 91 92 98 R99 101 102 C21 22 28 29 35 36 C42 43 49 50 5
64. S 15 15 NC 6 24 NC 8 i RY1 R37 PB R18 5 5 6 lt 45K lt 45k 75 24 NC 8 is COMPONENT VIDEO OUTPUTS 5 INPUT 3 6 24 98 6 4 PY_IN_SEL 8 gt o 4 PY_IN13 8 Y 1 RY4 lt R42 RY6 lt 15 OSD_PR_OUT dics 11 CN 18 PR OUT ilag 13 PR SEL 9 29 13 PR IN13 9 9 5 1 3 lt lt R40 RY6 S 15K 4 OSD_PB_OUT 11 11 213 2 11 ong 13 PB IN SEL 95 3 18 IN13 9 RY1 B8 I RY2 1 R38 RY5 7 515 gt E 5VR 5VR 1 1 1 1 05 D 512 04 4 9 03 15 2 144002 2 2 Tor die _ 1N4002 4 2 CONTBAET r _ NO 3 OAK PARK 16 16 16 16 RY5 RY6 RY2 RY4 exicon BEDFORD MA 01730 R44 5 THLE sen R45 S 7 85 s P SEL2 21401 7 85 NA d 204401 SCHEM VIDEO BD MC4 MC8 lt lt Q13 K Q12 RWH 31302 COMPONENT VIDEO L CHECKED 3 48 02 SZE CODE NUMBER REV 060 15269 3 3902 ere NAME ISSUED 3 19 02 15269 4 4 SHEET 4 OF 8 8 7 6 5 4 3 2 1 gt 10 19 2004_8 34
65. lt 10 gt 22k 9 10 6 18 n a Internal 96000 Analog ANLG ZONE IN7 96K TO ANLG ZONE DIR OUT ANLG ZONE IN7 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 44 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 7 19 n a Internal 96000 Analog ANLG ZONE IN7 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level lt 0 10 0 10 0 25 100 10 gt 500k 9 10 7 19 Internal 96000 Analog ANLG ZONE IN7 96K ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40k 20 Unbal Float THD N lt 010 015 00005 40kHz LP 100k lt 10 gt 500k 9 10 7 19 Internal 96000 Analog ANLG ZONE IN7 96K ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100k lt 10 gt 22k 9 10 19 Internal 96000 Analog ANLG ZONE IN7 96K TO ANLG ZONE DIR OUT SNR 997 20 Float dBr Level 108 00 95 00 140 00 100 lt 10 gt 22k 9 10 7 19 Internal 96000 Analog ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT ANLG ZONE IN8 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 34 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 8 20 Internal 96000 Analog ANLG ZONE IN8 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 10 0 10 0 25 None 100k lt 10 gt 500k 9 10 8 20 n a Internal 96000 Analog ANLG ZONE IN8 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 2
66. 1 B3 2 C5 4 C8 amp 9 RST STATUS 4 PIC 2 ora 5VD gt 98 NZ 2N3906 5V MONITOR 2 5 0 5 0 i lt R431 lt R432 4 lt 1 5VD SRAM_EN R439 34164 4 2 C8 A 2 1 00K gt R434 2N3904 Sus 2 2K D60 1 2 1 8435 8436 lt R440 4 IN RESETO vr a C396 100K 10K 4 7K M 4 25 5 gt 1 914 5VD ae i Q6 GND R430 1 C414 77 4 098 10K T 470 L C415 2 3906 T 2 2 35 777 lt R433 J S4 7K R437 061 2 3904 PWR_RST R438 AN 1 BAR35 CONTRACT z 2 7 we exicon sowa RST __ 1 88 01730 TITLE APPROVALS DATE SCHEM MAIN BD MC4 MC8 DRAWN RwH 2 45 02 STATUS amp CTL REGISTERS IR RCVR CHECKED 3 29 02 SIZE CODE NUMBER REV 060 15259 4 CW 4 3 02 FILE NAME ISSUED KAB 4 3 02 15259 6 3 5 23 8 7 6 5 4 3 2 1 10 19 2004 8 58
67. 1 M1 M0 HAVE WEAK PULLUPS M1 M0 1 1 SLAVE SERIAL MODE M1 M0 1 0 MASTER SERIAL MODE 2 JUMPER W1 TO GND TO USE CONFIGURATION ROM 90 DB_SDO3 3 81 3 83 S CUCU 8003 DB WRITE ENABLE DELAYS USE THE THROUGH PART DELAY TO MEET THE FLASH WRITE ADDRESS SETUP TIME FOR THE REV A2 CS49400 DEC_CLK_SEL 2 C1 3 B8 1 83 2 1 m UDIO12 76 AUDIO42 1 D3 2 C 1 0 85 SPARE CONTRACT 1 3 NO exicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM DECODER BD MC8 MC12 RWH 2 28 02 coca KB 3 5 02 SIZE CODE NUMBER REV a B 060 15319 2 cw 3 9 02 FILENAME ISSUED KB 3 5 02 15319 2 2 Ee 2 4 N EN 10 2 3 2002 14 48 8 7 6 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER _ AUTH CS49400 PINS ARE DUAL PURPOSE OPEN DRAIN CHANGES BER DER 00 bs Ss WHEN RESET RISES WITH ABOOT LOW AUTOBOOT MODE A AT RUN TIME PIN IS THE IRQ OUTPUT CS49400 REQUIRES 2 5 VOLT SUPPLY 2 B7 6 1202 6 24 02 PIN SHOULD NOT BE DRIVEN
68. 37 DSPCD 34 NC CD_RST 5 C8 8 B4 8 C1 b gt 70 DSPCD SDRAM CS DSPCD_ACK 71 DSPCD HOST CS 5 8 8 84 8 1 74 DSPCD_SRAM_CS 2 C8 3 C8 5 C8 8 B4 8 C1 DSP FSI NC 5 C8 8 B4 SP IRQCD IRQ1 NC 20701801 58 DSPCD_WR 59 DSPCD_RD 2 6 195 DSPCD_AO 5 194 DSPCD A1 proa 6 193 DSPCD_A2 4 6 prog DSPD_FSI 7 190 DSPCD_A3 8 DSPD_SCKI 8 189 DSPCD_A4 8 A4 TED 188 DSPCD A5 185 184 DSPCD A7 43 183 DSPCD nl 15 180 DSPCD A9 18 179 DSPCD t ir PE 178 DSPCD 11 1 18 175 DSPCD 12 19 174 DSPCD_A13 ee DSPD_1A_SDO 173 DSPCD 14 Hen DSPD_1B_SDO 23 pean 171 DSPCD_A15 170 DSPCD A16 26 169 DSPCD 17 166 DSPCD_A18 165 DSPCD 19 164 DSPCD A20 AR 162 DSPCD 21 161 DSPCD A22 160 23 DSPCD 23 0 82 HER 83 DSPCD_D1 84 DSPCD_D2 eae 86 DSPCD_D3 87 DSPCD_D4 56 515 88 05 DSPCD_CPA 65 90 DSPCD_D6 55 pon lt gt DSPCD BR1 2 91 DSPCD_D7 Doane lt P gt DSPCD_BR2 zag BRI 92 08 96 DSPCD D9 DSPCD_EMU 148 97 DSPCD_D10 ae DSPD_TDO 1464 98 DSPCD_D11 DSPC 148 10 100 DSPCD 012 DSPCD Ee 101 DSPCD_D13 DSPCD TMS 149 104 DSPCD 014 gt DSPCD TRST 147 jae 107 DSPCD 015 108 016 DSPCD_STATUS_FULL 197 109 DSPCD_D17 5 B8 8 B4 gt FLAGI REAGO 111
69. 5 8 DSPAB_TCK DSPAB_EMU 9 10 DSPAB_TRST DSPAB_TRST NC 11 12 TDI 13 14 3 R47 3 88 gt _ _ 2 D1 9 C4 DS PAB ICE 102 103 115 142 202 203 DSPAB SDWE 47 5 P 12 01 3 03 4 2 D1 3 D3 4 C8 2 D1 3 D3 4 C8 2 D1 3 D3 4 C8 DSPAB SDA10 2 D1 3 D3 4 C8 DSPAB SDCLK 2 D1 3 D3 4 D8 NC 2 D1 3 D3 4 C8 ADSP21065 DSPAB SDRAM CS DSPAB HOST CS DSPAB SRAM CS 2 01 3 3 8 7 2 D1 3 C3 4 C8 2 D1 3 C3 8 C 7 2 D1 3 C3 4 D4 2 D1 3 C3 4 B4 PWMEVENTO PWMEVENT1 38 MARI PAB A12 PAB A23 PAB DO PAB D1 PAB D2 PAB D3 PAB D4 PAB D5 PAB D6 PAB D7 PAB D8 PAB D9 PAB D10 PAB D11 PAB D12 PAB D13 PAB D14 PAB D15 PAB D16 PAB D17 PAB D18 PAB D19 PAB D20 PAB D21 PAB D22 PAB D23 PAB D24 PAB D25 PAB D26 PAB D27 PAB D28 PAB D29 030 031 23 BMSTR BMSTR DSPAB_A 23 0 DSPAB D 31 0 2 D1 3 C3 4 B4 3 B3 4 D6 3 A3 4 D7 8 C4 4 B8 8 C7 4 B8 8 C7 REVISIONS DESCRIPTION DRAFTER CHECKER _ AUTH CHANGED PER DCR 020429 00 5 3 02 5 7 02 5 13 02 KAB TEST POINTS DSPAB_ICE_CLK ABCLK ABWRI ABRD S ABBMS 0 HOST 5 ABHOST CS 8 SRAM CS ABSRAM_CS
70. 51 47 25 RY4 E 15V 3 C3 m RBREAR s J 2 94K 3 01K 1 196 945 2134 R30 C36 RELAY Hm RRRI MN U3 51 4725 RIGHT OUT C38 R31 15V R25 15V 828 18PF 93 1 RREAR 3 C3 2 94K 3 01K 196 196 18PF R27 RRR apy 47025 OdBFS 16Vrms OdBFS 8Vrms CONTRACT lt n NO R1 01730 EXPOUTS MUTE 2N4401 TITLE 1 A5 3 C3 APPROVALS DATE 390 79 1 DRAWN SCHEM XLR BD MC 8B Q CW 4 8 02 SIDE REAR OUTPUTS CHECKED 4 9 02 NUMBER 060 15349 0 2d RWH 4 9 02 FILE NAME ISSUED KAB 4 10 02 15349 0 2 ES 2 3 8 6 5 4 3 2 1 4 12 2002 11 43 8 7 6 5 4 3 2 1 REVISIONS CHECKER AUTH FROM ANALOG BOARD GND 1 1 1 C8 2 RFRONT icd BYPASS CAPACITORS 3 LFRONT 1 D8 GND 2 4 FRONT P Bo SUB 1 D8 508 7 15V GND 3 CENTERS Wed 9 10 GND 4 711 c44 Lost Loss 065 _ Lose 1 1037 12 sang 1 25 1 25 p 125 1 25 1 25 1 25 1 25 1 25 1 25 1 25 2 8 I T 1 GND 5 14 RSIDE 2 C8 4 4 4 5 15 LSIDE
71. 750 6 8157 R158 1 INH 7505 25 VSS VEE 117 e 7 U16 v 57 v Y 5VV MSVID_SEL0 7 B5 P MSVID SEL F ONTRACT 3 4 NO exicon OSD C IN 5 C7 BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM VIDEO BD MC4 MC8 RWH 3 13 02 MONITOR CHECKED SIZE CODE NUMBER REV 3 18 02 060 15269 2 37902 ISSUED 3 19 02 15269 4 2 sHEET 2 8 8 7 6 4 3 2 1 gt 10 19 2004_8 34 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH CW RWH 1 CHANGED PER DCR 020523 00 gt 6 4 02 6 5 02 CW RWH ay 2 CHANGED 014 15 PER DCR 020715 00 2502 5714102 8 13 02 8 14 02 16 74HC4051 5VV 3 UPDATED FOR PER DCR 040922 00 ALA 3914 4 CVID4 12 ZY 5 4 21 i 2 D8 8 B6 CVID2 e EL4421 9 27 04 9 27 04 2 D8 8 B6 NC 1212 666 8 AD8072 CVID1 1 3 E ve 2 D8 8 B6 NC 5 Y4 OUT IN SYZON 4 lt NC 5 47 16 7 R99 gt 1 8 86 Y7 100K 75 0 ZVID_SEL0 11 1 7IC5 ZVID SEL1 105 IN A0 GND V 8 165
72. 8 4 DSPD 1A 8500 AUDIOG C30 A30 AUD O1 8 B7 8 C1 DSP FSI C29 A29 AUD 02 8 B7 8 C1 DSP_PROG C28 A28 AUD 03 8 07 501 27 27 AUD O4 1 D1 2 C8 501 26 26 AUD 05 1 D1 2 C8 AUDIOS C25 A25 6 C8 DSPD 18 SDO AUDIO8 AUDIO7 AUDIO8 C24 A24 C23 A23 B A4 AUDIO_SPO AUDIO SPO C22 A22 AUDIO 8 4 AUDIO_4MHZ C21 A21 C20 A20 C19 A19 C18 18 17 17 16 16 15 15 DSP_A4 C14 DSP_A3 A14 DSP_A2 C13 DSP_A1 A13 DSP_A0 C12 A12 8 A4 DSP A 4 0 ZDSP RD 8 D7 C11 A11 8 C7 8 D1 ZDSP WR C10 AUDIO9 8 C7 8 D1 DSP_CCLK AUDIO10 8 05 DSP_DIN ZDSP_DO ZDSP_D1 ZDSP_D2 ZDSP_D3 ZDSP_D4 ZDSP_D5 ZDSP_D6 ZDSP_D7 ASPO NC 8 05 ZDSP_D 7 0 8 C7 ZDSP_CS 8 C7 8 D1 ZDSP RST 8 C7 8 C1 REV REVISIONS DESCRIPTION DRAFTER Q C CHECKER AUTH 1 REVISED SIGN ADD NOTE 8 PER DCR 020926 00 CW RWH IAL NAMES ON SHEETS 1 8
73. 8 10 8 83 7 43 40kHz LP 100k 10 gt 500k 13 57 2 4 6 8 n a n a 11 External 96000 Digital DIG MAIN OPT1 IN 96K TO ANLG MAIN OUT DSP THD 3 amp 5 1 00dBFS 1 00dBFS 997 n a n a THD N lt 002 005 0002 40kHz LP 100k 10 gt 500k 1 3 5 7 2 4 6 8 n a n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT DSP DYNRNG 3 amp 5 60 00dBFS 60 00dBFS 997 n a n a 9 THD N gt 110 00 108 00 140 00 40kHz LP 100 lt 10 22k 1 8 5 7 2 4 6 8 n a n a 11 External 96000 Digital Notes 1 The Analog Zone Direct Input paths are selected at the MUX while the Zone D A converter is being driven with a 1dBFS Digital Input from COAX1 2 The Analog Main Direct Input paths are selected at the MUX while the Main D A converters are being driven with a 1dBFS Digital Input from COAX1 3 The Audio Precision Switcher channels are selected during the Audio ATE macro 4 The CLKRNG Tests are used to verify the operation of the PLL circuitry 5 The DSP Tests are used to verify the operation of the Decoder and DSP Boards Lexicon CHAPTER 5 TROUBLESHOOTING This chapter contains a complete description of the diagnostic tests for the MC 8 MC 8 Balanced MC8 B The diagnostics in the MC8 B are used to verify functionality of the unit and to aid in troubleshooting defective units Familiarity is assumed with the MC8 B BOM structure all applicable assembly drawings FAT process and Audio ATE processes Diagnos
74. 8 7 6 5 4 3 2 1 10 21 2004_8 20 8 7 6 5 4 2 1 REVISIONS 5VAD 5 45VR DESCRIPTION DRAFTER 4 CHECKER AUTH RWH CW FB15 LEFT amp RIGHT FRONT D A CONVERSION 1 CHANGED PER DCR 020430 00 5 46 02 6 24 02 KB KB 6 4 02 6 26 02 C163 C161 C159 RWH CW ye tL 2 CHANGED PER DCR 020731 00 BE 47 47 330 63 13 548 13 C162 C160 C158 OdBFS 8Vrms RUH CN i OdBFS 17Vrms 15V 5VAD S CHANGED FE pots 08200 8 30 02 9 12 02 1 25 125 1 25 157 19 x 9 2 02 9 12 02 R122 110 R97 4 UPDATED FOR MC4 PER DCR 040922 00 4395 ve sal x e _ _ 17 88 AT AT 22 va 181 1 576K gt 1 9 27 04 9 27 04 1 2 __ FRONT DAC MCKI 3 47 1 C154 95 L 4 C2 21 84 FRONT DAC RST 4 55 23 8124 4 C1 4 C2 18 D8 MAIN SCKIO 5 AOUTL 22 gt 121 330 6 3 4 C1 4 C4 30 4 pzrR 28 196 15V 5VAD 4 C1 4 C2 18 C8 MAIN DAC FSIO 7 cani 27
75. 9 27 02 10 15 02 KAB KAB 10 11 02 10 15 02 2 SHOW DEPOPULATION FOR MIC BD ON SHTS 2 8 amp 10 RWH CW PER ECO 041201 00 12 7 04 12 14 04 AF MSJ 12 9 04 12 9 04 AOA_SDI AOB_SDI TEST POINTS 01 DSPA 01 1 UNLESS OTHERW 2 UNLESS OTHERWI 3 UNLESS OTHERW 4 DIGITAL 77 GROUND 5 XX XX DENOTES 6 LAST REFERENCE U26 W1 7 COMPONENTS INDICATED RESISTORS ARE 1 10W INDICATED RESISTORS ARE 5 INDICATED CAPACITORS ARE ANALOG _ CHASSIS POWER GROUND GROUND GROUND SHEET NUMBER SECTOR DESIGNATORS USED C150 D11 FB14 J8 Q1 R95 RKED WITH NOT INSTALLED 8 COMPONENTS RKED WITH ARE NOT INSTALLED ON MIC BD 9 NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC DOCUMENT CONTROL BLOCK 060 15389 9 m m 2 lt MAIN 05 05 05 05 05 05 MICROPHONE INPUTS 5 PASS CAPACITORS 8 DSP CLOCKS 2004 Lexicon Inc 3 01730 APPROVALS DATE TITLE
76. CODE NUMBER REV DSPAB ICE Qc 060 15389 1 2 D1 10 C6 CW 6 3 02 ISSUED KB 6 3 02 15389 2 2 SHEET 2 OF 10 8 7 5 4 3 2 1 12 15 2004_ 8 52 8 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER AUTH 1 SHOW DEPOPULATION FOR BD 3 PER ECO 041201 00 T ae 42 9 04 12 9 04 3 3VD MASTER IDO HIGH ID1 LOW SLAVE 00 LOW ID1 HIGH R 42918 55 85 a TEST POINTS 2564 863 RAS 42 BSBA RAS 2 01 2 03 4 8 51248 a4 DSPAB 2 01 2 03 4 8 DSPB 1A SDO 2 D1 2 D3 4 C8 B1A_SDO SDO 46 gt DSPB_1B_SDO 55 DSPAB SDCKE D1 2JD3 4 C8 B1B SDO DSPB 18 500 ___ DSPB CLK 30 SDCKE 48 SDA10 2 01 2 03 4 8 10 06 NC 39 CLKIN SDA10 28 2 D1 2 D3 4 D8 m 12 XTAL2 SDCLKO NC 2 D1 2 D3 4 C8 2 C8 8 C4 8 C1 RESET 144 100 BMS 5153 DSPAB_BMS 2 D1 2 C3 8 C7 143 MSO 570 _ CS 2 01 2 3 4 2
77. FLASH_RST 2 RESET N s 2 3 LAST REFERENCE DESIGNATORS USED 65 J1 R1 U3 1 NC 22 33 NC 4 DUAL LAYOUT INSTALL EITHER U1 C1 C2 212400 5 34 Nc OR 02 63 C4 21 nce 34 NC ics 02 4 5VD 5VD FLASH 4 4 20 vocoj 28 VCC1 2 C1 C2 243 27 200 1 25 1 25 22144 D1 32 201 i ZA5 _ 21 5 02133 202 2 6 20149 3134 203 ZA 19 9 D4 28 204 248 18 ps 39 205 2 9 17 Da 40 206 16 2 41 707 07 15 2412 10 12 2 24139 13 70 5 _ 8 ee TINS __5 15 REFERENCE 3 24 1 3 RA20 4649 NC5 55 A20 NC6 NG FLASHO Mes 45 NC MEM RD 47 NC 2002 Lexicon Inc FLASH_WR 4 4g NCM REM io NO FLASH RST 14 exicon 42 BSY RDY BEDFORD MA 01730 3 BSY RDY 36 GNDO TITLE E DATE SCHEM MEMORY gs U4 DRAWN RWH 12 6 01 CHECKED KAB 1 4 02 SIZE CODE NUMBER REV ac OW um B 060 15299 0 ss FILE NAME ISSUED 1 8 02 15299 0 1 10F 1 e 8 7 6 5 4 3 2 1
78. MAIN ANLG e Main A D calibration and 96kHz sample rate enable MAIN_AD_RST MAIN_AD_96K_EN Control Register 3 provides the following Analog source selection for the Zone audio path ZONE_ANLG_SEL 2 0 ZONE ANLG EN e Zone DAC reset control ZONE_DAC_RST e Zone output selection DSP or analog direct path ZONE_DACOUT_SEL ZONE_DIRECT_SEL e Mute for Zone output level control ZONEOUT_VC_MUTE Control Register 4 provides the following e Independent Zero crossing enable for each Main output level control FRONT_VC_ZCEN etc Zero crossing enable for the Zone output level control ZONE_VC_ZCEN Control Register 6 provides the following e Main DACs reset control MAIN_DAC_RST Main outputs selection DSP or analog direct path MAIN DACOUT SEL MAIN_DIRECT_SEL e Mute for Main output level controls MAINOUT VC MUTE e Front Main DACs reset control FRONT_DAC_RST e Front Main output selection DSP or analog direct path FRONT_DACOUT_SEL FRONT_DIRECT_SEL e Mute for Front Main output level control FRONT VC MUTE 6 19 8 Service Manual Power Supply Connections and Regulators There is a separate feed from the 60W switching power supply to the Analog section of the Main board The Video board gets its power from the analog section The Analog board has a 6 pin connector that accepts 15 volts 5 volts and two ground connections to the supply A 4 pin connector supplies the video
79. THEORY OF OPERATION Main Board Z180 Host Processor The 2180 is responsible for all systems control in the unit It runs off the 29 491mHz crystal oscillator It is reset by the PWR_RST signal ZCLK is a buffered synchronous clock output that is used to synchronize signals in the Memory CPLD and the I O FPGA 29 491 MHZ CRYSTAL RS 232 RS 232 gt INTERRUPTS ZA 7 0 ZWaAIT gt Z180 ZD 7 0 HOST PROCESSOR SRAM CONTROL MEMORY ZCTRL BOARD 7180 CONTROL SRAM HOST INTERFACE FPGA PROGRAM RESETS STANDBY BUTTON MEMORY EPROM ENCODER INTERFACE MEMORY CPLD FLASH ROM HOST PROCESSOR MEMORY BLOCK BOARD Memory CPLD The Memory CPLD is programmed at the factory like an EPROM It can be programmed before or after it is soldered to the PC board It provides the following functionality e Host data address and control interface provides all memory space address decoding plus a small section of I O space that is occupied by the Memory CPLD internal control and status registers e SRAM read write signals and bank address bit e Flash ROM and EPROM control signals and bank address bits RA 22 15 e The I O FPGA programming bits e Reset lines under host control to the analog circuitry
80. benzene or acetone based cleaners or any strong commercial cleaners Avoid using abrasive materials such as steel wool or metal polish If the unit is exposed to a dusty environment a vacuum may be used to remove dust from the unit s exterior Ordering Parts When ordering parts identify each part by type board assembly location component location price and HSG Lexicon Part Number Replacement parts can be ordered from Harman Specialty Group 3 Oak Park Drive Bedford MA 01730 1441 Telephone 781 280 0300 Fax 781 280 0499 email csupport harmanspecialtygroup com ATTN Customer Service Returning Units to HSG Lexicon for Service Before returning a unit for warranty or non warranty service consult with HSG Lexicon Customer Service to determine the extent of the problem and to obtain Return Authorization No equipment will be accepted without Return Authorization from HSG Lexicon If HSG Lexicon recommends that a MC 8 be returned for repair and you choose to return the unit to HSG Lexicon for service HSG Lexicon assumes no responsibility for the unit in shipment from the customer to the factory whether the unit is in or out of warranty All shipments must be well packed using the original packing materials if possible properly insured and consigned prepaid to a reliable shipping agent When returning a unit for service please include the following information e Name e Company Name e Street Address e City St
81. dBr Level 0 10 40 10 0 25 None 100k 10 gt 500k 9 10 1 13 n a Internal 96000 Analog ZONE IN1 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40 20 Unbal Float THD N lt 010 015 00005 40kHz LP 100 lt 10 gt 500k 8 10 1 13 n a Internal 96000 Analog ZONE IN1 96K TO ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0 15 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 10 1 13 n a Internal 96000 Analog ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_SNR OFF OFF 997 20 Unbal Float dBr Level 108 00 95 00 140 00 None 100k 10 gt 22k 9 10 13 Internal 96000 Analog ANLG ZONE IN2 96K TO ANLG ZONE DIR OUT ZONE IN2 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 44 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 2 14 n a Internal 96000 Analog ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 10 0 10 0 25 None 100k lt 10 gt 500k 9 10 2 14 Internal 96000 Analog ANLG_ZONE_IN2 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40 20 Unbal Float THD N lt 010 015 100005 40kHz LP 100 lt 10 gt 500k 9 10 2 14 n a Internal 96000 Analog ZONE IN2 96K TO ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 9 10 2 14 n a Internal 96000 Analog ZONE IN2 96K TO ANLG ZONE DIR OUT SNR OFF OFF 997 20 Unb
82. which reduces high frequency peaking in the transmission path to the video board Composite video outputs Composite video outputs originating on the video board are fed through individual pins of J3 to the corresponding output RCA jacks The on board traces are controlled impedance and form part of a 75 ohm wideband transmission system and output level is 1Vp p when terminated in 75 ohms 2Vp p open circuit S video inputs Specific references are to input 1 other inputs are similar S video luminance inputs pin 4 of the mini din jacks are terminated and buffered the same as composite inputs AC coupling is applied after buffering C45 couples S video 1 luminance Chrominance input 1 pin 3 of mini din jack J13 is first ac coupled by C42 and then buffered by emitter follower Q10 The dc level at the chroma input pin is direct coupled to subsequent sense circuitry through R80 6 20 Lexicon Main Monitor Composite S video Composite and S video luminance connect to multiplexers U17 and U18 S video chrominance connects to U16 The composite multiplexer is addressed by the MVID_SELn bits and the S video multiplexers are addressed by the MSVID_SELn bits When MCVID_EW is asserted low 018 is enabled and all MSVID_SELn bits are forced to 0 U20 sheet 7 Composite multiplexer U18 selects one composite source With MSVID_SELn set to 0 the S video path is disabled because U17 is selecting a disconnected input and U16 is selectin
83. 00 1001 00 40kHz LP 100k lt 10 gt 500k 1 3 5 7 2 4 6 8 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT RELAY MUTE DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT RELAY 3 40 00dBFS 0 000 5 997 n a n a Vrms Level 125 00 120 00 1001 00 40kHz LP 100k lt 10 gt 500k 1 3 5 7 2 4 6 8 11 External 96000 Digital DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_CLKRNG DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT CLKRNG 4 1 00dBFS 1 000 5 997 THD N gt 92 00 82 00 105 00 None 100k 10 22k 1 11 External 87 3K 89 1K Digital DIG MAIN COAX1 IN 88K TO ANLG MAIN OUT DIG MAIN COAX1 IN 88K TO ANLG MAIN OUT GAIN 3 40 00dBFS 0 00dBFS 997 Vrms Level 8 10 8 83 7 43 40kHz LP 100k lt 10 gt 500k 19 57 2 4 6 8 11 External 88200 Digital DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_THD 3 1 00dBFS 1 00dBFS 897 THD N lt 003 005 0002 40kHz LP 100 lt 10 gt 500k 139 57 2 4 6 8 11 88200 Digital DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_DYNRNG 3 60 00dBFS 60 00dBFS 997 na dBr THD N gt 110 00 108 00 140 00 40kHz LP 100k lt 10 22k 1 3 5 7 2 4 6 8 n a 11 External 88200 Digital DIG MAIN COAX1 IN 88K TO ANLG MAIN OUT CLKRNG DIG MAIN COAX1 IN 88K TO ANLG MAIN OUT CLKRNG 4 1 00dBFS 1 004 5 997 THD N gt 92 00 82 00 105 00 None 100k lt 10 22k 1 11
84. 02 9 12 02 arising 15 12 12 z 4 CHANGED PWR SUPPLY PER 031111 00 pa GAP 5 18 04 5 26 04 5 UPDATED 040922 00 aSa A d 5 9 27 04 9 27 04 29 5VAD SOURCE V 2 5TURN 7 t D34 3 C328 C322 100 25 C312 1 C313 C321 1 C320 100 25 C309 C308 4A Pa 22 50 T 150PF C310 T 22 50 150 Wig 2250 TOP 22 50 150 L lt R278 2 5TURN M V a 5VA REGULATOR e v EM 1N4002 A TEST POINTS ANALOG POWER plt 5 1N4002 M5V e i 038 15 J32 15V 805 4 5 CASE GND C329 2 vN vour 1019 E 1 3 NC FB31 15V SOURCE FROM POWER SUPPLY 4 15 zs RN L C330 GND 037 15V 6 15 1 C325 _ C324 100 25 10314 1 C315 1 25 2 U63 4 1 4002 4 T 22 50 F 150 C316 T T 22 50 F 150PF P 4 4 4 5 GNDA ED v REGULATOR 3 3VD2 15V SOURCE GNDD2 n 1 I GNDD3 D35 039 gt 327 10826 40025 1 C318 1 C349 dl 1N4002 ad GNDD4 T 22 50 T 150PF FB32 C317 T T 22160 T 150PF L 1 25 1 U59 125 5 GNDD5 m T C331 GND C333 T 2 5TURN M GNDD6 i Jw gt GNDD7 CASE VIN Ee GNDD8 7905 GNDD9 I D40 GNDA10 GNDD10 t9 15V gt v 1 GNDA11 GNDD11 1N4002
85. 1 000 1 000 1 000 1 000 1 000 4 000 16 000 9 000 1 000 13 000 4 000 12 000 8 000 3 000 5 000 1 000 3 000 2 000 2 000 4 000 1 000 1 000 PICK REV 5 PC BOARD R1 C5 C1 2 IF U1 POP C3 4 IF U2 POP U1 TSOP pkg or U2 for SOIC pkg PICK REV 0 PC BOARD R88 91 94 97 R1 15 43 45 50 51 R58 59 66 67 74 75 82 83 131 R3 7 10 12 16 117 133 134 172 2 18 35 42 106 150 152 153 89 90 95 96 11 48 56 64 72 80 112 116 119 140 161 166 53 61 69 77 85 118 167 171 R6 13 14 R132 R98 102 R86 87 92 93 R109 114 158 164 R49 52 57 60 65 R68 73 76 81 84 27 34 46 47 54 55 R62 63 70 71 78 79 R99 100 105 147 148 R151 155 R19 24 25 32 R9 101 121 146 149 R29 31 104 107 110 R111 113 115 138 R143 157 160 163 165 135 141 103 108 137 139 R144 145 159 162 R20 R120 122 125 128 130 R26 33 R123 124 126 127 129 R17 R21 R28 30 136 142 R22 R23 C87 89 C6 29 33 37 41 45 140 144 17 83 85 99 106 125 139 66 86 101 50 51 55 56 100 109 14 15 137 10 12 C8 9 C48 49 53 54 7 C11 DESCRIPTION QTY EFFECT INACT REFERENCE 245 10976 CAPSM CER 47pF 50V COG 5 3 000 20 25 115 245 10977 CAPSM CER 330pF 50V COG 5 1 000 C18 245 11625 CAPSM CER 33pF 50V COG 5 1 000 122 245 12070 CAPSM CER 15pF 50V COG 10 1 000 C108 245 12485 CAPSM CER 1uF 25V Z5U 20 90 000 C1 5 13 16 21 23 C26 28 30 32 34 36 C38 40 42 44 46 47 C52 57 65
86. 1 OF 23 6 HOST amp MEMORY CPLD J35 FP 35 FP RST 12 B7 2 OF 23 4 MEMORY CONN CPLD 1 RST 19 O_RST 2 C5 3 B8 4 C8 3 OF 23 4 STATUS amp CTL REGISTERS IR RCVR 2 4 23 4 3 30 MEM 10 37 MEM IO 2 A3 5 OF 23 4 DSP BOARD CONNECTOR m A 59 MEM AUDIO 62 MEM_AUDIO amp 4 A4 6 OF 23 4 OPTION BD 0 CONNECTOR 28 100 MEM DAR 7 OF 23 4 OPTION BD 1 CONNECTOR 2910 8 OF 23 4 OPTION BD 2 CONNECTOR TMS s Ep 48 9 OF 23 4 DIGITAL AUDIO RECEIVERS amp ZONE DIGITAL OUTPUT STANDBY SWITCH 58 T 61 207 10 23 5 LOCK LOOP 12 23 5 5 S SW RD 11 OF 23 4 REMOTE POWER amp RS232 PORTS DEBE EO 1 253 STANDBY 12 OF 23 4 FRONT VIDEO CONN 1 C1 12 B2 ENCODE f 41 _ 1 7 206 12725 13 23 5 LEFT ANALOG INPUT MUXES a 5 TRIGGER 21 14 23 5 RIGHT MUXES 1 C1 12 82 CHARG T TRIGGER HARGE 51 CHARGE 15 OF 23 4 MIC INPUTS amp MAIN A D CONVERTER T_RUN 24 T RUN TEST_LED0 E 1 5 16 23 4 DAC TEST gt C 17 OF 23 4 L R FRONT DACS TEST LED 43 3 18 23 4 CENTER SUB DACS NOTE 9572 I O HAS INTERNAL 10K PULLUPS TEST LEDs 40 49 19 OF 23 4 UR SIDE DACS DURING POWER UP AND PROGRAMMING 5VD 5VD 20 OF 23 4 UR REAR DACS GNDGNDGNDGNDGNDGND R389 4 21 23 4 XLR CONN CONTROL 8 16 27 42 44 60 083 lt 220 5 R391
87. 15737 RESSM NET 5 ISOL 3 3KX4 2 000 RP3 4 241 09798 CAPSM TANT 10uF 10V 20 1 000 C27 241 11799 CAPSM TANT 4 7uF 6 3V 20 1 000 C12 245 12485 CAPSM CER 1uF 25V Z5U 2096 24 000 C1 11 13 14 17 26 28 245 12524 CAPSM CER 68pF 50V COG 5 1 000 C15 245 13810 CAPSM CER 1200pF 50V COG 5 08 1 000 16 270 11545 FERRITESM CHIP 600 0805 1 000 1 300 11599 DIODESM GP 1N4002 MELF 1 000 D3 300 14286 DIODESM SCHOTTKY 1A SMB 1 000 D1 310 10510 TRANSISTORSM 2N3904 SOT23 1 000 Q1 340 13883 ICSM LIN LM2937 2 5V REG TO263 1 000 U6 350 13854 ICSM FPGA XCSO5XL 4 10X10 VQOFP 1 000 U4 350 15491 ICSM FLASH 512KX8 3V 200NS TSO 1 000 U1 365 15490 ICSM uPROC DSP CS49400 LQFP 1 000 U2 390 12076 CRYSTAL OSCSM 12 288MHz 1 000 U3 430 10421 LEDSM INNER LENS GRN 1 000 D2 500 04557 CONN EURO C ROW a c MALE RA 1 000 J1 710 15310 PC BD DECODER MC8 MC 12 1 000 REV 2 Switch LED Board Assembly 202 09795 RESSM RO 5 1 10W 2 2K OHM 8 000 R17 23 29 202 10597 RESSM RO 5 1 10W 180 OHM 2 000 R24 25 202 10599 RESSM RO 5 1 10W 3K OHM 2 000 R26 27 202 10945 RESSM RO 5 1 10W 1 5K OHM 9 000 R1 4 9 12 28 202 10948 RESSM RO 5 1 10W 390 OHM 8 000 R5 8 13 16 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 1 000 C1 245 12485 CAPSM CER 1uF 25V Z5U 20 6 000 C2 7 300 10509 DIODESM 1N914 SOT23 3 000 D17 19 310 10510 TRANSISTORSM 2N3904 SOT23 1 000 Q1 330 10372 ICSM DIGITAL 74HC574 SOIC 4 000 U2 5 330 10537 ICSM DIGITAL 74HC541 SOIC 1 000 U1 330 14244 ICSM
88. 15k Level gt 90 00 80 00 150 00 None 100k 10 22k 9 10 n a 11 External 96000 Digital DIG ZONE COAX1 IN 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a THD N gt 108 00 103 00 140 00 100k 10 22k 9 10 11 96000 Digital DIG ZONE 1 IN 88k TO ANLG ZONE OUT DIG ZONE COAX1 IN 88k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 Vrms Level 4 10 4 47 3 73 40kHz LP 100k lt 10 gt 500k 9 10 n a 11 External 88200 Digital DIG ZONE COAX1 IN 88k TO ANLG ZONE OUT THD 1 00dBFS 1 004 5 997 n a na THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 11 External 88200 Digital DIG ZONE COAX1 IN 88k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a dBr THD N gt 108 00 103 00 140 00 None 100k 10 22k 9 10 n a 11 External 88200 Digital DIG ZONE IN 48k TO ANLG ZONE OUT DIG ZONE COAX1 48k TO ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 n a n a Vrms Level 4 10 4 47 3 73 40kHz LP 100 lt 10 gt 500k 9 10 11 48000 Digital DIG ZONE COAX1 IN 48k TO ANLG ZONE OUT THD 1 00dBFS 1 004 5 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 11 48000 Digital DIG ZONE 1 IN 48k ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a n a THD
89. 2 1 11 18 2002 15 51 2 84 2 C1 08 8000 AUDIO4 EURO64 RA M 32 A32 5VD 3 3VD 4 AUDIOO DB MCKI C31 A31 MC12 DAR 2 B7 2 C1 C30 A30 AUDIO1 DB_FSI gt 2 A7 2 C1 29 29 28 28 27 27 DB 5001 AUDIO5 26 26 2 B4 2 C1 DB 8002 AUDIO6 C25 A25 2 B4 2 C1 2 B4 DB_SDO3 2 4 AUDIO7 AUDIO8 24 24 23 23 22 22 AUDIO2 AUDIO3 AUDIO DB_PROG DB_SDI DB_4MHZ 2 B7 2 C1 2 07 2 87 21 21 20 20 19 19 18 18 17 17 16 16 15 15 4 14 14 13 13 2 DB 1 12 12 11 11 0 DB A 4 0 2 D6 RD DB WR 2 C7 2 C7 2 D1 C10 AUDIO9 DB CCLK gt 2 7 2 01 AUDIO10 DB DO DB D1 DB D2 DB D3 04 05 DB 06 DB 07 07 01 2 C6 AUDIO12 12 10 DB DIN AUDIO12 2 05 2 D5 NC DB CS DB RST 2 A7 2 C1 2 C7 2 D1 gt 2 7 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH B RWH CW 1 020604 00 6 10 02 6 24 02 W 6 12 02 6 24 02 RWH C 8 29 02 9 5
90. 2 C8 8 C1 T DSP 3 C3 _ DSPAB STAT FULL 28 D AR ATUS 2 B8 3 B8 ER ESI DSP FSI SP IRQAB 2 C8 3 C8 FSI 2 A3 4 B8 DSPA OUTO 4 _ DSPB_OUTO 5 3 A3 4 B8 DSPB_OUTO DSPA_OUT1 27 2 A3 4 B8 PSEA QUTI 27 3 A3 4 B8 DSPB_OUT1 pspcp po 20 DSPCD DO NOTES DSPCD_D1 DSPCD_D2 1 M1 M0 HAVE WEAK PULLUPS 1 0 1 1 SLAVE SERIAL DSPCD D5 1 0 1 0 MASTER SERIAL MODE DsPCD pe 83 DSPCD D6 DSPCD D 31 0 DSPCD 07 5 A3 6 A3 7 D7 2 JUMPER W1 TO GND TO USE CONFIGURATION ROM B C1 5 C3 6 D3 08 0 8 411 DSPCD HOST CS 30 RST 5 C8 6 D8 8 C1 5 01 5 3 6 03 SECO WE Xj 42 DSPCD_BMS DSPCD 39 SEED CH RENT 5 C8 6 D8 8 C1 5 2 54 05 WR DSPCD_CMD_RDY 46 08 5 C8 8 C1 5 C2 RD DSPCD RD DSP CD STAT FULL 33 PEPE SAILS 5 B8 6 B8 SP IRQCD 2 5 C8 6 C8 4 A8 5 A3 DSPC_OUTO IpsPC OUTO DSPD OUTO 56 4 A8 6 A3 DSPD_OUTO DSPC_OUT1 86 4 A8 5 A3 BEBE BUT 86 IDSPC OUT 4 A8 6 A3 DSPD OUT pen DSP_FLAG1 wo sans aH dE 1 D3 8 C1 99 DSP FSI IRQ 91 IRO 2 C8 3 C8 5 C8 6 C8 8 C1 1 C3 8 C1 DB FSI DSPABC FSI 21 BEBO ERI 2 C8 3 C6 5 C8 8 C1 DSPD_FSI 956 R74 33 6 6 8 1 DSPA SCKI A E 2 C8 8 C1 DSPA_SCKI 96 R75 33 DSPB_SCKI DsPc_sck 97 R76 3
91. 22 4 A4 ex 082 AUDIO 082 A13 A21 A A8 551 DB2 A12 A20 C19 DB2 A11 A19 C18 082 A10 A18 082 9 C17 DB2 A8 A17 DB2 A7 C16 DB2 A6 A16 NOTES DB2 A5 C15 ZA 15 0 2 5 082 5 DB2 A 13 0 DB2 A4 A15 1 COMPONENTS ON THIS PAGI RE NOT INSTA JON MC4 1 D4 2 D8 4 D7 5 C7 6 C6 7 C6 12 A6 a 4 At 18 DEZAS DB2_A3 C14 COMPONENTS ON THIS PAGE ARE NOT INSTALLED ON MC 2 2 082 2 14 6 14 082 1 IO_RD 8 3 12 ZDB2_RD DB2 1 AE 2 D1 2 D3 4 D8 5 C7 6 C7 7 C6 10 QM 082 13 d C12 U70 ZDB2_RD 12 1 74 244 11 2 D1 2 D3 4 C8 5 B7 6 B7 7 86 O_WR 1 Y1 3 a 2082 2 Y2 5 2 2 DB2_AUDIO9 10 M 3313 0824 9 JA DB2_AUDIO10 A9 9 U70 6 ZDB2 DO 74VHCT244 py 58 1 Y1 18 2 2082 03 A2 vae DEP 48 ZDB2 D4 14 pee 208205 2082 070 2082 06 5 46 _D 7 0 208207 071 C4 74VHCT244 DB2_AUDIO_SP0 A4 m y 2 DB2 A13 C3 7 082 11 2 5 5 2 9 C2 M 3313 082 082 CS 2 1 082 RST Al 4 EURO64 F 74VHCT245 2 18 2082 DO 1 03 2 06 3 07 5 7 6 6 7 6 Stak UB Z ZDB2D1 A2 B2 4 B3 19 5 4 5415 2082 03 65 Bs 14 2082 D4 13 2082 D5 8 12 2082 06 9 8 Bs 11 2082 07 DB2 CS 195 __ 1 2 D1 2 D3 3 D7 3 C7 5 A7 6 A7 7 A6 12 A7 DIR 1698 082 CS 2 3 DB2 RST
92. 25 1 25 C15 16 lc48 C19 C20 C21 22 C24 Lcs C26 JT 1 25 is 4 25 1 25 T 1 25 T 1 25 ies 1 25 29 I C31 32 __ I C34 LC35 il C36 1 37 I C38 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 5h3 1 25 1 25 TL 425 1 25 9 LL cao C41 1 42 C43 C44 C45 C46 C48 cag 50 T 1 25 TS 1 25 1 25 T 1 25 1 25 1 25 TS C51 4 C52 I C53 C54 I C55 1656 1 57 I C58 59 C60 C62 1 25 T 1 25 1 25 1 25 1 25 1 25 1 25 1 25 T 1 25 1 25 1 25 1 25 C63 lce4 C65 ces C67 C68 C69 Lev C74 155 T 1 25 1 25 1 25 T 1 25 T 1 25 JES T 1 25 qeu C75 _ ji I Locs I C82 a C84 1 85 C86 1 25 T 1 25 1 25 1 25 1 25 1 25 1 25 1 25 71 1 25 1 25 T 1 25 1 25 C87 lc C91 C92 C93 C98 CONTRACT 1 25 T 1 25 1 25 1 25 1 25 T 1 25 1 25 T 1 25 1 25 1 25 1 25 3 4 I T T exicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM DSP BD MC8 2 28 02 BYPASS CAPACITORS 8 DSP CLOCKS KB 3 5 02 SIZE CODE NUMBER a B 060 15309 CW 3 5 02 FILE NAME ISSUED KB 3 5 02 15309 2 9 Es 9 or 9 6 4
93. 26 1 25 1125 T 1 25 7 16 C46 C47 C52 C57 4 04 4 4 4 4 4 4 4 5VV 1 25 71 25 r 125 1 25 18 C90 C91 C92 C93 C94 C95 C96 C97 C103 C107 1 C110 20 125 125 1 25 1425 r 1425 4 25 1 25 1 25 T 1 25 1125 T 1 25 din 74 4 NV e C111 1 119 l C124 C126 C128 C131 C134 C136 C146 LC147 1 C148 125 r A25 4 25 1 25 T 4 25 4 25 1 25 1 26 25 1125 1 25 OPTICAL INPUTS TORX173 z 2 gt C1 C3 C22 1528 10632 1 36 1040 1844 105 iced 1 ces 1 25 r 125 T 125 1 25 425 4 25 T 125 1 25 1 25 1125 T 1 25 6247 1 1 1 1 2 L 2 4 TORX173 ce ices 1 c74 C76 c78 1 80 118 LC427 1 129 454 1 25 r 125 4 25 1 25 T 4125 125 1 25 1 25 1 25 1125 T 1 25 H C86 l C16 4 4 4 4 4 4 4 4 4746 T 4 25 1 NO 01730 4 b C132 135 138 145 TITLE 1 25 1 25 1 25 1 25 APPROVALS DATE SCHEM VIDEO 4 8 3 3 02 pwR SPDIF MAIN amp RCA BD CONNS CHECKED 3 48 02 SZE CODE NUMBER REV t 2 Qc 31902 erent 060 15269 5VV ISSUED KB 3 19 02 15269 4 8 SHEET 8 8 7 6 5 4 3 2 1 gt 10 21 2004_8 1
94. 4 5 CABLE PWR HSG 110 QDC 2C 5 CABLE HSG HSG 4C 4 AC CONN TO PWR SW PWR SW TO 60W PWR SUP MAIN BD TO VIDEO BD gt LEXICON INC SW LED BD ASSY 023 15437 SCRW M3X6MM PNH BZ 640 10498 6 PLCS TORQUE 4 6 IN LBS AdOI 903 3139 CABLE 100 PLUG SCKT 2X13C 2 680 14083 REF 7002 9 AYIN BUTTON BLK W LT 550 13634 20 PLCS CABLE 100 PLUG SCKT 2X7C 3 680 14082 REF SHIELD 701 15456 SCRW M3X6MM PNH PH BZ _ 640 10498 9 PLCS TORQUE 4 6 IN LBS SCRW M4X8MM PNH PH ZN 640 15476 2 PLCS TORQUE 8 10 IN LBS BUTTON BLK 550 13633 2 5 ROUTE DISPLAY CABLE OUTSIDE THE SHIELD DISPLAY 430 13143 7 PLACE THIS EDGE FLUSH TO WALL CENTER VERTICALLY 5 4 2 1 BRACKET SUPPORT COVER 701 15454 amp SUPPLIED WITH ENCODER P N 452 13640 TORQUE 5 7 IN LBS KNOB 1 75 X 91H 4550 15459 PEWTER 8 550 15762 BLACK SDP 5 IR ENC ASSY 023 14068 SPCR M3 CL X 6MM 6MM RD 635 14526 SCRW 12 PNH 2 4640 10495 TORQUE 4 6 IN LBS LABEL FP JBL geo 740 15774 SDP 5 ONLY PANEL FRONT MC 8 B 702 15440 SDP 5 702 15763 LENS STANDBY BD ASSY 023 15438 1 PART NUMBER LISTING IS
95. 4 C1 4 2 20 c8 MAIN_DAC_FSI1 7 27 499K R72 A e RAZ 13 12 4 C4 18 C8 20 C8 DAC 5 8555 pzrL 26 9 CADO pig 25 ruo dici LSUR_DIR_IN 8s ol R113 4 7 4 C4 17 C8 18 C8 20 C8 MAIN 10 24 __ MAIN DAC CDATA 11 OPA2134 U8 4 C4 17 C8 18 C8 20 C8 CDTI AOUTR 200542183 DACOUT SEL 412 DIF0 AOUTR 18 C4 20 C4 21 83 gt MAIN DIRECT_SEL 13 pIF4 AGND 19 14 pig 47 15V Pus j i R116 C105 R79 78 16 n DGND BGND 19 C137 eH 131 12 00451 121K 330 6 3 280 220 U18 1 1 R78 RSIDE_DACOUT NM GENS 145 19 A8 WU RT GND AS 6 49K m 4 5 U8 Yow 15V 4 17 B8 18 A3 20 88 MAIN RLY 445V 5VAD 4 13 12 ADG451 VDD 14 A2 20 B4 RSUR_DIR_IN 3 5 p 2 5 9 IN LEFT amp RIGHT SIDE a LEVEL CONTROL 4 s U8 v Y 15V 15V R31 LSIDE C27 p 21 C8 L 22088 28 4 OdBFS 8 1Vrms 125 15 12 PGA2310 2 AGNDL VA __ LSIDE_DACOUT 16 14 R10 19 D3 AINL AOUTL _ ae LEFT SIDE OUT 47 25 4 D4 17 B8 18 B8 20 B8 6 44 R11 6 A TAN lt 410K __ MAINOUT VC DATA 3 L C47 8 4 4 17 8 18 88 20 8 SDIN um 5 7 VC CS 265
96. 4 Y4 5 275 42 62 6 6 4 02 6 26 02 ee 077 Zr 2 CHANGED PER DCR 020731 00 PWH OW 584105 8 1 02 8 5 02 9 9 VIDEO 0 CBV KB SEE NOTE 1 SEE NOTE 1 10 VIDEO 1 8 5 02 8 14 02 2 rael 3 CHANGED PER DCR 020827 00 RWH CW RED 12 SYNC DETECT 83002 9 12 02 Ds 1 13 2 5 _ VIDEO RST 14 9 2 02 9 12 02 1 4002 2 1 83 45 RWH CW BACK 122 15 4 UPDATED FOR PER DCR 040922 00 Spade dard 1 17 8412 5 11718 9 27 04 9 27 04 __ _ 2 4401 COAXI4 1 3 03 5 N J oes FAN CONNECTOR 19 COAX1 4 1 4 21 2 2 4 22 23 1 24 25 COAX4 26 4 u OPTO1 OPTOJ4 1 4 C7 SPARES TEMPERATURE SENSOR gt OPTO2 5VD 3 3VD 30 31 5 732 74VHCT244 57 SRS178 LM56 t 33 4 on 9 NC 2100 228 34 13 vN I 15 5 O O TEMEI I2 AS J30 1 17 3 8 28316 2 2 5 L L 1 6 4 2K a 5VD 062 47 VTEMP 3 4 h TERA 066 R3153 R414 S1K eds STANDBY SWITCH 188 gt 7 1 NOTES R413 STANDBY SWITCH STANDBY_LED 3 CONNECTOR 1 INSTALL R410 FOR 12V FAN INSTALL R411 FOR 5V FAN 220 J43 77 74NHCT244 4 D2 AUDIO DONE Y1 A2 Y2 IO DONE 45 5 2 03 2723 gt val
97. 47 gt 10 1085 10 0K 1 X 1 2 MIC IN 2 E R33 3 MIC IN 2 HOS 15 SVAD 4 15VA 5 1 C43 1 5 11 12 00451 LEFT_MAIN_IN 7 1 5 18 R31 47PF R37 C14 VDD 8 m EIER RR n 57 11 10 RIGHT MAIN IN 9 1 15VA v H 5 10 16 10 0 270 5 1 1 10 25 JIN 1 150 1 4W R38 VEE GND J4 15K 5 025 15VA _ C42 150PF Y 2 00K C19 R32 1 C45 PU 15VA 10 16 10 0K ag e 1 R35 R34 47 2107 MIC_IN_2 10 85 10 0 1 5 3 R44 MIC IN 3 74 108 v 15VA 15 5VAD 1 1 13 12 00451 47 FB7 C24 R42 47PF L3 R48 C20 vcc VDD VA 1 15VA M A 35 L 10 16 4 270 ae i T 150 1 4W 5 R49 GND 4 S 15 4 s U25 F Y 15VA Y R47 15VA RR 2 00K 150PF C25 R43 Y 1 ceo E 4 pu 15VA Ww 10 0K C49 FB8 10 16 P 47 1 1 1 246 R45 212 AA gt 196 MIC IN 3 10 5 10 0 1 d MIC IN 4 MIC IN 4 10 A5 R55 15VA SVAD 15VA 1 C53 dh 1 ADG451 FB9 232 R53 R59 C28 VCC VDD ae o RK p 14 15 5 1051 10 16 4 270 10 25 150PF 1 4W lt R60 VEE GND ns 4 5 025 gt 15VA 7 15 x C52 1 e 7 150PF 7 2 00K CONTRACT C33 R54 EUR 1 NO exIico n 3 OAK PARK
98. 5 DIR 13 A5 14 A5 CLR 10 END 3 7 8 13 A5 14 A5 R42 100 048 741 14 47IA3 e RFRONT 2 i z 152224 LFRONT R40 100 74VHC273 17183 LFRONT 4 e 20 L 5 SUB R38 100 IODX0 3 4D 22 94 R235 MAIN ANLG_SELO 13 5 14 5 18 A3 _598 6 IODX1 4 5 R238 MAIN ANLG 7 5 R36 100 2D 2Q v 13 05 14 05 7 4 IODX2 7 6 R239 MAIN SEL2 _ 8 M xS 13 D5 14 D5 48 B3 IODX3 8402 409 R240 AIN_ANLG_EN 13 05 14 5 9 IODX4 13180 12 R237 MAIN RST L 4 IODX5 14 15 R236 MAIN ADC 96K 11 Tope 60 15 B2 12 7 IODX7 18 70 7940 29 13 RSIDE R34 100 8D _13 ven 4 ANLG CS 11 e RSIDE 14 PSY 4 A4 426 oe LSIDE 8 R32 100 40 CLR 19 83 16 GND d 17 RREAR 8 R30 100 051 20 A3 18 5 i 9 LREAR R28 00 _ LREAR 20 4 74VHC273 20 B3 21 vec 20 2 R21 ZONE ANLG 0 _ 4 1 1 ale R232 ZONE ANLG 727 EUST IODX2 7302 6 6233 ZONE ANLG SEL2 I sce 44 05 25 RZONE 8 R26 100 IODX3 8 40 9 8234 ZONE ANLG d 13 C5 14 C5 RZONE 26 IODX4 13 5 59 12 6230 ZONE DAC RST EOD 16 A2 57 LZONE 8 R24 100 IODX5 1801257 2228 R
99. 5792mHz crystal oscillator that provides either a 44 1kHz or 88 2kHz sample rate the 24 576 oscillator that provides either a 48kHz or 96kHz sample rate or the master clock output of the Zone digital receiver In practice the unit runs off the crystal 96 2 when the input is analog When the input is digital the master clock output of the digital receiver is used Depending on the input selected the appropriate master clock is routed from the DAR FPGA to the Audio FPGA Here it drives a clock tree that divides down the master clock which is 256 times the sample rate 256FS to create the other clock rates required e The Digital Receiver uses a word clock FS and bit clock 64FS e The Analog Board receives a 256FS Master Clock and a word clock FS These are used on the analog board to derive the audio clock signals required by the devices on that board 24 576 MHZ 4896 ZONE ZONE DRCVR MCKO DRCVR IO FPGA ZONE DRCVR SDO ZONE MCKO ZONE E DRCVR _ DRCVR FSI gt DIGITAL ZONE DRCVR SCKI CLOCK DRCVR ZONE FSI ZONE ZONE gt ANALOG CLOCKS SECTION ZONE AUDIOCLOCKS AUDIO FPGA ANALOG INPUT CONNECTORS MUX ZONE ZONE DRCVR SDO gt
100. 63 6 page 48 026 DSPAB_A16 2 5 06 57 07 62 46 0026 47 025 16 07 A4 61 A4 2024 49 _ DSPAB 024 DSPAB SRAM CS 5 DSPAB A3 60 42 DSPAB_D23 0023 DSPAB WR 129 E DSPAB A2 27 40 DSPAB_D22 Jw A2 DQ22 DSPAB RD 280 26 A 0022 39 021 A0 25 37 DSPAB 020 3 AO 2MX32 DQ20 3h DSPAB D19 100MHZ 00193 SPAB D1 2 01 2 03 3 031 _ 59 DQ18 34 018 28 33 DSPAB_D17 DQM2 DQ17 pois 31 DSPAB D16 Daie 85 015 DSPAB 0 0012 014 A1 2 D1 2 03 3 03 19 0012182 DSPAB_A2 CAS 184 80 D12 DSPAB 2 D1 2 D3 3 D3 PSPAB S CAS DQ12 25 DSPAB SDWE Te 26 1 79 DSPAB 011 DSPAB 4 ADT 3103 DSPAB SDRAM CS 285 Daio 77 __ _ 10 DSPAB 5 203 159176 09 DSPAB 2101 2103 3 03 DSPAB SDCKE 67 74 8 DSPAB_A7 Sint 203 DSPAB_SDCLK 68 Day 13 07 DSPAB 8 2703 097 11 DSPAB 06 DSPAB 9 AE DSPAB_D8 NC 73 098 10 05 DSPAB A10 19 9 00 7 09 NC 70 6 099 8 04 DSPAB_A11 20 0 01 10 DSPAB D10 NC NC4 00317 DSPAB 03 DSPAB_A12 21 15 p4 11 Dii NC 57 NC3 Daz 5 02 DSPAB A13 29 5 03 22
101. 67 82 90 98 102 105 107 110 113 117 119 124 126 132 134 136 138 145 148 245 12524 CAPSM CER 68pF 50V COG 5 1 000 123 245 14762 CAPSM CER 6 8pF 50V COG 5 1 000 120 245 14763 CAPSM CER 12pF 50V COG 5 4 000 C19 24 114 116 245 14764 CAPSM CER 82pF 50V COG 5 1 000 C121 270 00779 FERRITE BEAD 4 000 FB1 4 270 11289 INDUCTORSM 10uH 10 1 000 L1 300 10509 DIODESM 1N914 SOT23 1 000 D2 300 10563 DIODESM DUAL SERIES GP SOT23 5 000 D1 6 9 300 11599 DIODESM GP 1N4002 MELF 3 000 D3 5 310 10510 TRANSISTORSM 2N3904 SOT23 11 000 Q1 10 15 310 10565 TRANSISTORSM 2N3906 SOT23 1 000 Q14 310 10566 TRANSISTORSM 2N4401 SOT23 3 000 Q11 13 330 09797 ICSM DIGITAL 74AC04 SOIC 1 000 U5 330 10505 ICSM DIGITAL 74HCO02 SOIC 1 000 U4 330 10506 ICSM DIGITAL 74HC595 SOIC 3 000 U21 22 30 330 10523 INVERTER 74HCU04 SOP 2 000 U7 8 330 10524 ICSM DIGITAL 74HC08 SOIC 2 000 U12 20 330 15667 ICSM DIGITAL 74HCT594 SOIC 3 000 U36 38 340 10502 ICSM LIN LF353 DUAL OPAMP SOIC 2 000 U2 23 340 11495 ICSM LIN LT1229 VID OPAMP SOIC 2 000 U24 29 340 13856 ICSM LIN EL4421C VIDAMP W MUX 3 000 U13 26 27 340 14791 ICSM LIN EL4422C VIDAMP W MUX 1 000 U28 340 15683 ICSM LIN AD8072 VIDAMPX2 SOIC 4 000 U6 14 15 25 345 10503 ICSM INTER NJM2229 SYNSEP SOIC 1 000 U3 346 10507 15 55 SWITCH 74HC4051 SOIC 7 000 U9 11 16 19 346 10508 5 55 SWITCH 74HC4053 SOIC 2 000 U1 35 350 15672 ICSM FLASH 128KX8 5V 90NS PLCC 1 000 031 365 13288 ICSM uPROC
102. 74A 1 000 L1 300 10509 DIODESM 1N914 SOT23 5 000 D29 33 42 46 60 300 10563 DIODESM DUAL SERIES GP SOT23 18 000 D3 20 300 10564 DIODESM SCHOTTKY LOW VF SOT23 5 000 028 30 32 61 300 11599 DIODESM GP 1N4002 MELF 11 000 01 2 24 27 36 38 047 48 300 14286 DIODESM SCHOTTKY 1A SMB 2 000 034 35 310 10510 TRANSISTORSM 2N3904 SOT23 2 000 07 9 310 10565 TRANSISTORSM 2N3906 SOT23 3 000 04 6 8 310 10566 TRANSISTORSM 2N4401 SOT23 3 000 01 2 5 310 15016 TRANSISTOR MOSFET 30V TO220 1 000 330 09889 ICSM DIGITAL 74ACT04 SOIC 1 000 055 330 10523 INVERTER 74HCU04 SOP 1 000 057 330 12452 ICSM DIGITAL 74VHCT244 SOIC 10 000 062 67 68 70 71 076 77 81 82 91 330 13865 ICSM DIGITAL 74VHC04 SOIC 3 000 044 58 88 330 13876 ICSM DIGITAL 74VHC273 SOIC 7 000 048 52 93 94 330 14247 ICSM DIGITAL 74VHCT245 SOIC 7 000 061 69 74 75 80 095 97 330 14534 ICSM DIGITAL 74VHCT541 SOIC 1 000 092 330 15084 ICSM DIGITAL 74LVC14A SOIC 1 000 053 340 00742 7805 LM 340 T 5 1 000 063 340 09244 ICSM LINEAR 78LS05 5V REG SOIC 1 000 054 340 10502 ICSM LIN LF353 DUAL OPAMP SOIC 9 000 02 19 03 021 28 56 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 6 000 U30 34 39 43 46 47 340 10567 ICSM LIN MC34164 4 5V MON SOIC 1 000 U98 340 11575 ICSM LIN 7805 5V REG TO263 1 000 U60 340 11597 ICSM LIN TLO72 DUAL OPAMP SOIC 9 000 02 19 03 021 28 56 340 12936 ICSM LIN OPA2134 DU OP AMP SO8 5 000 U11 15 340 13137 IC LINEAR LM2941CT ADJ TO 220 3 00
103. 8 C1 8 A4 8 C1 3 D1 3 C8 3 D1 3 C8 8 87 DSPCD_BR1 DSPCD BR2 o o 2 gt N CDCPA CDBR1 8 B7 CDBR2 NC NC NC 10 178 DSPCD 11 175 12 174 A13 173 14 171 A15 170 16 169 17 166 18 165 19 164 20 162 DSPCD 21 161 22 23 17 1 18 DMAR1 20 0 DMAR2 A21 DMAG1 A22 DMAG2 A23 DSPCD A 23 0 6 C3 7 D5 82 DSPCD DO DSPCD CPA p DSPCD BR1 DSPCD_BR2 5 C1 6 B8 5 21 6 88 5 C1 6 B8 DSPCD 08 96 DSPCD_D9 97 DSPCD_D10 98 DSPCD 011 100 DSPCD 012 101 DSPCD D13 104 DSPCD 014 107 DSPCD 015 108 DSPCD 016 109 DSPCD 017 111 DSPCD 018 112 DSPCD 019 113 DSPCD 020 116 DSPCD D21 117 DSPCD 022 118 DSPCD D23 121 DSPCD 024 122 DSPCD 025 123 026 126 DSPCD 027 127 028 128 DSPCD 029 132 DSPCD 030 133 DSPCD 031 DSPCD EMU DSPC TDO DSPCD TDI DSPCD TCK DSPCD TMS DSPCD TRST DSPCD STATUS FULL DSP FLAG1 6 B8 8 B4 2 88 3 88 6 88 8 84
104. 8MM MIN LENGTH STANDARDS JOINTS SHOULD BE SMOOTH OF PIN TO BE FREE OF SOLDER AND NEAT WITH NO EXCESS BUILDUP VCO BD ASSY 22 ACAD 2000 FILE 023 16129 DECIMALS ANGLES mE X xo _ 1 2 DATE ASSY DWG MECH VCO MCLK FSCM REV B 080 14834 2 KB APPLICATION DO NOT SCALE DRAWING ESUD sone 21 1 4 5 2 5 ac um lt ADD 230V LABEL FOR 50 5 AN 10 25 03 11 25 03 M PER 031023 00 CLC 10 28 03 11 25 03 _ ADD LABEL 740 16019 FOR AN 7 28 04 8 26 04 Mo 2 Bee 730 15488 0 2 5 022 15754 50 5 REMOVE BOM 3 FROM NOTE 1 AN 1 3 08 2 9 05 PER ECO 041201 00 CLO 1 5 05 MAG 2 9 05 M UNIT IN BAG 730 02819 FOAM INSERT BASE 730 15487 BLOCK FOR 8 PLACE UNIT IN BAG FOLD AND TAPE BAG WITH CREASES AND ON BOTTOM SIDE OF UNIT USE CLEAR TAPE SET UNIT IN BOTTOM INSERT 9 PLACE FOAM INSERTS ON BOTH SIDES OF UNIT NOTES 1 PART NUMBERS SHOWN ARE FOR REFERENCE ONLY amp DO NOT SUPERSEDE BOMS lt PLACE BOTTOM INSERT ASSEMBLY 2 FOAM PIECES ATTACHED TO A CORRUGATED PAD IN THE BOTTOM OF THE BOX REMOVE PERFORATED B PLACE ACCESSORY KIT ON TOP
105. 9 10 n a 11 External 96000 Digital DIG ZONE IN 96k ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a THD N gt 108 00 103 00 140 00 100k 10 22k 9 10 11 96000 Digital DIG ZONE OPT2 IN 96k TO ANLG ZONE OUT DIG ZONE OPT2 IN 96k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 Vrms Level 4 10 4 47 3 73 40kHz LP 100 lt 10 gt 500k 9 10 12 External 96000 Digital DIG ZONE OPT2 96 TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 n a n a THD N lt 003 005 0002 40kHz LP 100 10 gt 500k 9 10 n a 12 External 96000 Digital DIG ZONE OPT2 IN 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 THD N gt 108 00 103 00 140 00 100 lt 10 22 9 10 n a 12 External 96000 Digital DIG ZONE OPT3 IN 96k TO ANLG ZONE OUT DIG ZONE OPT3 IN 96k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 n a Vrms Level 4 10 4 47 3 73 40kHz LP 100k lt 10 gt 500k 8 10 n a 13 External 96000 Digital DIG ZONE OPT3 IN 96k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 n a 13 External 96000 Digital DIG ZONE OPT3 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a n a dBr THD N gt 108 00 103 00 140 00 None 100k 10 22k 9 10 13 External 96000 Digital DIG_ZONE_OPT4_I
106. A A 13 12 4 FRONT DAC CS 8 pzrL 26 ADG451 9 capo Pis s 13 2 LEFT_DIR_IN 8123 77 4 C4 18 C8 19 C8 20 C8 MAIN_DAC_CCLK 10 24 did R125 4 C4 18 C8 19 C8 20 C8 MAIN DAC 11 AOUTR 21 21 43 4 5 110 1 21 330 6 3R101 12 AOUTR 20 1 5 76 2 21 43 FRONT_DIRECT_SEL 77 1 2 13 19 156 C155 DIF1 AGND 156 14 pir2 vaL 47 v d 126 C113 E20 A 1 pend 15 C157 iaj 2 020 M ee 330 6 3 125 o gt RFRONT DACOUT 492K Ros 6 49K 1 15 5VAD 18 A3 19 B8 20 B8 MAIN_RLY_CNTL 13 42 ADGA51 14 02 RIGHT DIR IN LEFT amp RIGHT FRONT LEVEL CONTROL E9 839 Ve LFRONT 21 8 100 OdBFS 8 1Vrms 851 S10 LFRONT_DACOUT Mi R18 gt RELAY 17 D3 pm LEFT OUT 4 04 18 88 19 88 20 881 MAINOUT_VC_CLK 5 R19 4 10K 4 C4 18 B8 19 B8 20 A8 MAINOUT VC ae in i i N 5VAD 4 D4 amp RONT VC CS 2 68 17 10 45 s VC ZCEN m Z FRONT_VC_MUTE spour 7 1 2 820 17 03 RFRONT DACOUT 9 ANR 7 RIGHT OUT NS 47 25 100 NDR VA 1 4W 10 13 U5 S 10 RVE C37 4 25 CONTRACT C3
107. After a failure the unit will attempt to display on the VFD and the front panel LEDs the failed test number and loop on the failing test If the 2180 CPU and support circuitry is not working the unit will not attempt to read any front panel switches To execute the next Diagnostic Test after a failure occurs Press and hold the front panel MAIN TV and ZONE2 TV buttons This will cause the MC8 B to attempt to execute the next power on diagnostic step If a failure occurs the MC8 B attempts to enter a test loop to keep the signal lines active as an aid in debugging the failure At the end of each successive loop the diagnostics will check to see if the MAIN TV and ZONE 2 TV buttons are being held Depending on the length of the test the amount of time required pressing and holding the buttons will vary DIAGNOSTIC REPORTING All diagnostic functionality is reported to the Vacuum Fluorescent Display VFD and to the front panel LEDs They report on what test is being executed and if the test passed or failed The LEDs are used to report diagnostic status in the event that the VFD is not functioning Diagnostic status and data is also available on an external PC or a terminal via the serial debug port located at the D9 connector labeled RS232 2 on the rear panel The D9 connector labeled RS232 1 is used for updating the flash memory In the event a diagnostic failure occurs for those diagnostic tests that report to the error log additional fail
108. C281 gt gt 5 4 1 25 1 25 c3628 C363 C364 C365 C383 C384 C386 C387 C388 C390 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 280 284 lt gt 5 1 25 1 25 91 C394 C397 C398 C401 1 25 1 25 1 25 1 25 1 25 y 5VAD BYPASS 5VAD 579 66 74 C82 C90 C236 C255 1 25 1 25 1 25 1 25 1 25 1 25 1 25 S77 3 3V DIGITAL BYPASS CAPACITORS 3 3VD B 232 C344 5 C349 C350 C351 C352 C353 C354 C355 C356 C366 C367 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 C368 C369 C370 C371 C372 C373 C374 C375 C376 C377 C378 C379 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 C380 C381 C382 C389 C395 C399 C400 1 25 1 25 1 25 1 25 1 25 1 25 1 25 3 3V ANALOG BYPASS CAPACITORS 3 4 2 k 2 3 n NO C285 C286 288 289 290 exicon BEDFORD MA 01730 1 25 1 25 T 1 25 1 25 1 25 1 25 TITLE t e M APPROVALS DATE SCHEM MAIN BD MC4 MC8 DRAWN RwH 2 15 02 BYPASS CAPACITORS CHECKED 3 29 02 SIZE CODE NUMBER REV 5 a B 060 15259 AE Cw 41302 FILE NAME ISSUED kap 4 3 02 15259 6 23 23 23 9 8 7 6 5 4 3 2 1 E
109. C7 11 81 D18 2 A3 8ICT PAB A12 11__ DSPAB 019 3 A3 8 CT 0110 13 D 22 DSPAB_D20 3 A3 8 C7 DSP B LED 2 PAB 14 23 021 D 15 Ais Dal 26 D22 A16 32 0927 023 SRAM CS 5 wz 1295 R25 DSPAB_RD 2845 DSP D LED 2 H 3 3VD DSP D LED 1 G T TAVHC244 3 3V DSP C LED Z2 6 3 8 7 gt 5SPD F AS MBA DSPC_OUTO DSPC OUTI 5 A3 8 B7 DSP C LED 1 DSPAB A9 18 DSPAB 024 DSPAB 025 11 026 12 027 A13 DSPAB 028 14 029 CONTACT PAB A15 030 25 977 somrar e 01730 2 D1 2 C3 3 C3 SRAM TITLE DSPAB WR APPROVALS DATE 2 D1 2 03 3 C3 5 RD SCHEM DSP BD MC8 2 D1 2 C3 3 C3 DRAWN 2 28 02 EES DSPAB EXT MEM KB 3 5 02 SIZE CODE NUMBER REV ac B 060 15309 1 U17 EN 3 8 02 FILENAME ISSUED KB 3 5 02 15309 24 SHEET 4 9 29 N EN 11 1 8 2002 15 51
110. C8 8 C4 8 C1 69 ack 51 071 DSPAB_HOST_CS 2 01 2 3 8 7 Ms2 74 5 L 2 D1 2 C3 4 D4 2 8 5 8 6 8 8 84 8 1 DSP_FSIIRQ 205_iRQ0 53 5 NC PER SP IRQAB 206 Qd 193 64 NC 207 ADSP21065 WR 258 DSPAB WR 2 D1 2 C3 4 B4 Sr 59 _ 1 2 3 4 4 gt RD D i 2 D1 2 C3 4 B4 195 DSPAB_AO 2 DROA 128 2 DSPAB WR XI 2 C8 5 C8 8 B4 8 C1 FSI 7 TFSO A3 8 gt DSPB SCKI 8 FB11 B A4 Nc 41 A Fm DSPAB RD DTOA A5 n RD 8 C7 NC 12 A6 AT N A8 16 RCLK1 DSPAB A10 t 17 PRIA mE DSPAB 11 1 18 an DSPAB A12 19 DSPAB A13 3 D1 5 C8 DSPB SDO 2 IA DSPAB_A14 3 D1 5 C8 18 800 23 DT4B DSPAB A15 DSPAB A16 24 WMEVENTO A17 DSPAB ATS PWMEVENT1 19 38 DSPAB A20 1 38 A20 0 DMAR2 A21 DSPAB A21 20 pwaci 22 23 0 4 9 A23 2 83 4 D6 40 82 DSPAB T NC 52 ree DO DSPAB_D1 55H D1 84 02 NOCHE 02 86 DSPAB 03 56 87 DSPAB_D4 SBTS 04 88 DSPAB 05 05 _____ 5 _ 65 90 DSPAB 06 188 2101 DSPAB BR1 27 06 91 DSPAB_D7 DSPAB 2 284855 07 92 08 gt 96 9
111. D1 2 D3 3 D3 1 20 3 13 2 21012103 3 03 0012 _ 12 DSPAB 4 2104 2 03 3 03 gt DSPAB_SDWE WE 2911 011 _ 4 13 A4 128KX8 m SDRAM CS 10 5 144 12 5 2103 Das L76 09 DSPAB 15 ne SRAM 2 D1 2 D3 3 D3 67 Dag L74 DSPAB 08 DSPAB_A7 161 6 DSPAB SDCEK Day 13 DSPAB D7 ir 213 Das 1 DSPAB D6 5 _ 9 18 5 pol DSPAB D8 NC 73 DSPAB A10 7 _ DSPAB 09 NC6 005 A10 D1 NC 70 11 10 D10 NC5 004 A11 D2 NC 69 PAB A12 11__ DSPAB D11 NC4 DQ3 12 D3 NC 57 404 A13 2 04 22 012 NC 30 43 Doi PAB 14 Ala 5523 DSPAB D13 NC 2 Dao PAB A15 Ais Del26 014 A16 32 e 0627 015 MER sram 5 loja co DSPAB_SRAM_CS _5 dE S E d lod a d b SS d U14 DSPAB WR 12 417 5 Rp 2344 9 1551 25 VSS2 3 3VD GRN U19 R32 DSPAB_AO 1 8 DSP ALED 1 240 VDDir5 DSPAB A2 Pp 2992 DSPAB A3 414 _ 4 13 A4 128KX8 DSP A LED 2 DSPAB 5 14 12NS DSPAB A6 15 ne SRAM DSPAB_A7 161 6 Bep EDdH 9 18 JAS pgL8 DSPAB D16 A10 7___ 5 _ 17 2 A3 8
112. DCR 020731 00 352 C1238 121 C1198 VEE GND CBV KB 21 s ZONE2 D A CONVERSION 0969 8 5 02 8 14 02 S 2 RWH CW 47 47 330 6 3 gt CHANGED DOES Q2082 00 8 30 02 9 12 02 od C1228 C1208 C118 5 OdBFS 4 0Vrms Z 4 15V 9 12 02 9 12 02 gt 4 1 25 1 25 1 25 OdBFS 1 7Vrms E11 1 4 UPDATED FOR PER 040922 00 9 24 04 10 14 04 5 13 12 AT AT J20 81038 8578 eae ADG451 9 27 04 9 27 04 4395 MSS T XXL Wt qi des XE ad LZONE_DACOUT 2 18 1 15 56 357 9 8 16 88 lt VD 1 A 4716 I IN gt 2 8663 L lt R52 VEE GND 4 C1 4 B4 2 3 17 c3 680PF T S ATK 5 5 U6 21103 ZONE_DAC_RST 4 aouTL 23 4 ZONE DAC 5 22 R1048 R55 8 d 4 C1 4 B4 a BICK AOUTL VAS VA 15V 1 15 357 _ ZONE DAC 801 6 28 NC 397 4 C1 4 B4 SDATA DZFR 28 196 R548 Jone DACOUT SEU ZONE DAC FSI T MN 21 23 gt 4 C1 4 B4 DAC LRCK 2 74K 1 ZONE_DIRECT_SEL ZONE_DAC_CS 8955 DZFL 21 C3 9 15V 5 9 capo PIS ZONE DAC 10 E12 DAC CCLK VCOM 13 12 ADG451 1058 8605 _ ZONE DAC CDATA 11 21 A C598 VDD arca eon AQUTR 14 15 RZONE_DACOUT 55 20 1 15 R615 357 ftis D 16 A8 _ DIFO AOUTR 1 e 47 6 GIN 22 65 4 R53 13 19 C
113. DSP engines which reside on a daughter board Each pair shares four 128kx8 12ns SRAMs and one 2Mx32 The SHARCs communicate with this external memory and each other over a 32 bit wide data bus All necessary chip selects are generated by the SHARCs including the clocking required for the Synchronous DRAM The SHARCs master clock is provided by a 30MHz crystal oscillator that is distributed through a 74LCX14 inverter used as a buffer 30 MHZ SHARC SHARC A ADDRESS amp DATA SHARC B DSP DSP DSP Hosr COMMAND SRAM SDRAM STATUS HOST DATA REGISTER 4 REGISTER DATA DSP FPGA DSP FPGA A SHARC SHARC C ADDRESS amp DATA SHARC D DSP SHARC C D DSP BLOCK DSP DSP Host COMMAND SRAM SDRAM STATUS HOST DATA REGISTER X4 REGISTER DATA DSP FPGA DSPFPGA 6 10 Lexicon DSP Board FPGA The DSP FPGA has byte wide data path for the host interface with five bits of addressing It provides the following functions e Host communication with DSPs A B C and D This includes resets wait lines status control bits data registers and interrupts e One GPIO bit from each DSP and one Flag bit common to all four Uses FS signals from the Audio FPGA on the main board to deri
114. FOR 50 5 750 06760 IS OPTIONAL FOR MC 8 B hinc 3 PLACE ITEMS TRAY CAVITIES AS SHOWN MTG BRKT HARDWARE POWER CORD HERE 630 08670 4 SEE BOM 4 CLOSE BOX COVER OF COMPLETED SCRW 10 32 640 08671 4 AND A E SOT oa 6 2004 wm Anas ASSY DWG ACCESS s HS S 073070 8 50 5 ECC i ae k Lens umo APPLICATION DO NOT SCALE DRAWING 55085 sene 1 2 tor 8 7 6 5 4 5 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER RWH CW 1 CHANGED PER DCR 000327 00 ira KB KB 4 10 00 4 10 00 RWH TW 2 CHANGED PER DCR 000925 01 ism oao 40 20 00 10 20 00 CHANGED FROM 2 4K 1 5 Ren 010130 00 130 01 13001 1 30 01 1 30 01 5VD 4 IRM 8755 H2 3 4 4 SYSTEMON OVERLOAD IR ACK 5VD 5VD 5VD p2w YEL IR_AUXRET R2 R1 F AD WS im SEE NOTE 4 9 5 5 SYSTEM_ON_LED OVLD_LED LED NOTES 1 UNLESS OTHERWISE INDICATED CAPACITORS ENCODER_A 2 DIGITAL ANALOG 11 CHAS
115. ID1 HIGH VCC 1 42 DSPCD_RAS 4 5 C1 6 D3 7 C8 CAS 043 DSPCD_CAS 5 C1 6 D3 7 C8 TEST POINTS SDWE 044 DSPCD SDWE 5 1 6 037 46 DSPCD_DQM 46 03 5 C1 6 D3 7 C8 47 DSPCD_SDCKE 5 48 DSPCD_SDA10 5 C1 6 D3 7 C8 CDCLK 5 C1 6 D3 7 D8 CDWR DSPCD SDCLK L 15 1 6 0377 8 CDRD BSEL SDCLK1 34 CDBMS RESET CDHOST_CS 153 DSPCD_BMS P70 DSPCD SDRAM CS 5 D1 6 D3 8 B7 CDSRAM CS 5 C1 6 D3 7 C8 DSPCD HOST CS i x 14 DSPCD SRAM CS gt 5 C1 6 D3 8 B7 CDSDRAM CS 5 C1 6 C3 7 D4 CDRAS 5 NC CDCAS WR 58 DSPCD WR 15 01 6 3 7 4 159 _ gt 5 D1 6 C3 7 B4 CDDCKE RFSO CDSDA10 195 DSPCD AO CDSDCLK e 2 1 DSPCD RD X _ 12 50 9 gt DSPCD_WR DSPCD_RD DSPCD_BMS DSPCD_HOST_CS DSPCD_SRAM_CS DSPC_CLK DSPC_CLK 30 NC 31 10 C6 6 D8 8 B4 8 C1 CD_RST DSPCD_SDRAM_CS DSPCD_RAS DSPCD_CAS DSPCD_SDWE DSPCD_DQM 6 D8 8 B4 8 C1 DSP_FSI_IRQ SP_IRQCD 2 C8 3 C8 6 C8 8 B4 8 C1 DSPCD CMD RDY 6 C8 8 B4 8 B4 8 C1 DSPABC FSI DSPC SCKI DSPB 1A SDO DSPB 1B SDO 2 C8 3 C6 8 B4
116. LEDS CHECKED KAB 1 4 02 SIZE CODE NUMBER REV amp E Tum B 060 15289 0 FILE NAME g ISSUED KAB 1 8 02 15289 0 3 8 6 5 4 2 1 8 7 6 5 4 3 2 1 REVISIONS RA 22 15 REV DESCRIPTION PATTER ZD 7 0 LL 5VD 5VD 27C020 zao 121 5 32 4 2 1 11144 C5 ZAZ 0013 2009 T 4 25 Sag 01145 22 TEST POINTS 4 02 77 ZA5 7 0217 203 zas 61 9 D4L18 204 2 7_ 51 9 ps 19 205 248 271 4 20 206 15 249 26 57 21 207 RA16 ZA10 23 A10 RA17 7 11 25 11 18 ZA12 441 RA19 2 13 28 413 RA20 2 14 29 21 RAIS 31414 RA22 6 21446 30 47 6 7 1 5VD 256KX8 ZA2 1 70NS ZA3 4 tag ver EURO48 M RA EURO48 M RA EURO48 M RA MEM_RD 247 OE e ZA5 A1 RA20
117. MAINE 4 MAIN CB CB E2 4 C8 NC 1 3 MAIN Nec 4 C8 NC 14 2 MAIN NC 159 CD P1 27 MAIN CE 15 CE F2 4 C8 23 25 4 C8 1 283 gt MAIN DRCVR_RST 18 2 s 107 Fr 20 _ VA AGND R309 lt 470 C335 IE FB33 338 068 63 4 ZONE DIGITAL AUDIO RECEIVER ZONE ERRISTATUS 5VD CS8414 _ ZONE_DRCVR_NRZI 4 84 SR312 56 ZONE DRCVR MCKO ____ 12 01 2 851 ZONE DRCVR SDO 5 614088 e ZONE DRCVR FSI 4 84 4 C1 e ZONE DRCVR SCKI ZONE C0 _ ZONE_CS12 FCK ZONE_CA 2 83 ZONE ZONE gt 4 88 ZONE CD ZONE E ABa ZONE ERF 23 gt ZONE_DRCVR_RST lt 470 1634064 F 1 25 L C343 5 F 068 63 47 d ZONE DIGITAL OUTPUT C227 ZONE NRZO Res ZONE_S PDIF_OUT 374 R177 125 ZONE PARK 1 BEDFORD MA 01730 51 TIT APPROVALS DATE SEHEM MAIN BD MC4 MC8 77 2 2 DRAWN DIGITAL AUDIO RECEIVERS AND RWH 2 15 00 ZONE DIGITAL OUTPUT CHECKED 3 29 02 SIZE CODE NUMBER REV B 060 15259 4 413102 ISSUED kaB 4 3 02 15259 6 9 sHEET 9 23 7 6 5 4 3 2 1 10 19 2004 9 02
118. MC33078 DU OPAMP SOIC 4 00 U18 20 26 340 11559 ICSM LIN LM317M ADJ REG DPAK 1 00 U12 346 14583 5 55 SW ADG451QUAD 1P1T SOI 1 00 U25 500 04557 CONN EURO C ROW a c MALE RA 1 00 J3 510 10595 PHONE JACK 3 5MM PCRA 3C STER 4 00 J5 8 640 10498 SCRW M3X6MM PNH PH BZ 4 00 2 PER BRKT 680 15743 CABLE 100 PLUG SCKT 2X5C 2 5 L 1 00 J4 701 15738 BRACKET MTG MIC DSP BD MC8 1 00 PHONE JACKS 701 15739 BRACKET MTG OPT 1 00 710 15380 PC BD MIC DSP MC8 1 00 PICK REV 1 PC BOARD 740 11287 LABEL S N PCB PRIN 1 00 Power Supply Assembly 454 13850 SW ROCKER 2P1T 5A 80A 250 TV5 1 000 490 11462 CONN AC 3MC SNAP 04TH IEC 10A 1 000 530 02488 TIE CABLE NYL 14 X5 5 8 2 000 FERRITE SLEEVE TO PS SPT 640 10467 SCRW M3X6MM FH PH BZ 2 000 PWR SW TO PS SPT 640 10498 SCRW M3X6MM PNH PH BZ 2 000 PWR SUP TO PS SPT 640 12534 X SCRW M3X20MM PNH PH BZ 4 000 FAN TO PS SPT 643 10492 NUT M4X 7MM KEP ZN 1 000 CHASSIS GND 644 01737 WSHR LOCK SPLIT t4 2 000 PWR SUP TO PS SPT 644 02716 WSHR FL 4CLX 3120DX 03THK 2 000 PWR SUP TO PS SPT 644 10494 WSHR FL MACLX9ODX 8MM THK 1 000 CHASSIS GND 680 11461 WIRE 18G G Y 2 5 187QDC LUG 8 1 000 AC CONN TO CHAS GND 680 14536 CABLE PWR 187 110QDC SLV 4 5 1 000 AC CONN TO PWR SW 680 14537 CABLE PWR HSG 110QDC 2C 5 1 000 PWR SW TO PWR SUP 680 15465 CABLE HSG HSG 8C SLV 16 17 1 000 PWR SUP TO MAIN BD J32 amp J45 700 15449 SUPPORT PS MC8 1 000 720 14852 GASKET FAN 1 5D 1 7SQ BLK 1 000 FAN TO PS SPT
119. OF UNIT BETWEEN FOAM PIECES 6 CLOSE INNER BOX FLAPS AND ADD ID LABEL TO INNER BOX IN SPACE PROVDED FOR SDP 5 PLACE LABELS S N amp P N IN BLANK SPACE NEAR PRINTED BAR CODE 2 PLCS FOR 230V 5 COVER 120 MARKING OVER THE BAR CODE WITH 230V LABEL 2 PLCS SUP INNER BOX INTO OUTER SHIPPING BOX INNER BOX ID LABEL 8 CLOSE FLAPS AND 730 15484 MC 8 B 730 15771 SDP 5 740 15489 8 8 PLACE SECOND ID LABEL ON OUTER SHIPPING BOX 2 PLCS 5 PLACE LABELS S N amp P N IN BLANK 740 15773 S N SDP 5 SPACE NEAR PRINTED BAR CODE 4 PLCS 5 6 PLCS FOR 230V SDP 5 COVER 120 MARKING OVER THE 4720 76018 BN 5085 BAR CODE WITH 230V LABEL 4 PLCS 6 PLCS e 230V LABEL OUTER BOX 740 16124 230V SDP 5 6 PLCS 730 15486 MC 8 B UNLESS OTHERWISE SPECIFIED ACAD 2002 FILE NAME j 730 15769 SDP 5 ary as oe T ASSY DWG SHIPMENT L SDP 5 __ aene 8 50 5 e ______ MC 8 B CHECKED 6 14 02 SIZE 5 NO 0 NO REV 59 uo ss B 080 15461 lt APPLICATION DO NOT SCALE DRAWING SSUED ysver scur 174 Tor 8 7 6 5 4 5 2 1 2 10 05 50 0 2 03813798 8 7 6 5 4 5 2 1 RBEASNS omenon ac um 00 22 1 17 03 1 23 0
120. Out PGM Source Rate Source DIG_ZONE_COAX1_IN_96k_TO_DIG_ZONE_COAX_OUT DIG ZONE IN 96k TO DIG ZONE COAX OUT GAIN idBFS idBFS 997 n a dBFS Level 0 999 0 90 1 10 n a n a lt 10 Fs 2 n a n a n a n a 11 External 96000 Analog DIG ZONE COAX1 IN 96k TO DIG ZONE COAX OUT THD 1dBFS 1dBFS 10 40k dBFS THD N 144 00 140 00 999 00 lt 10Hz gt 20kHz LP n a 11 96000 Analog D A Tests Digital Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band Bin A Out B Out Source Rate Source DIG ZONE IN 96k TO ANLG ZONE OUT DIG ZONE 1 96k ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 n a n a Vrms Level 4 10 4 47 3 73 40kHz LP 100 lt 10 gt 500k 9 10 11 External 96000 Digital DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_FREQ 1 00dBFS 1 00dBFS 10 20k 40k Level lt 0 07 0 39 0 10 0 25 0 75 None 100k lt 10 gt 500k 9 10 n a 11 External 96000 Digital DIG ZONE COAX1 IN 96k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 20 2k 8k 40k n a na THD N lt 003 0075 005 0175 0002 40kHz LP 100k 10 gt 500k 9 10 11 External 96000 Digital DIG ZONE COAX1 IN 96k TO ANLG ZONE OUT XTALK 1 00dBFS 1 00dBFS
121. SDCKE 10 06 NC 31 SDCLK 2 D1 3 D3 4 D8 ABSDCKE DSPAB SDA10 2 N 2 D1 3 D3 4 C8 ABSDA10 1 152 ABSDCLK AB_RST 157 3 C8 8 C4 8 C1 157 sinus 143 DSPAB SDRAM CS DICAS meee DSPAB_CPA 3 08 8 04 8 01 a DSPAB_ACK DSPAB_ACK 69 HOST CS BR1 e MS2 DSPAB SRAM CS 2 04 3 23 4 04 ABBR2 DSPAB_BR2 DSP FSI IRQ 205 MS2 NC ADT ICS 3 C8 5 C8 6 C8 8 B4 8 C1 e Ge FS 208 1500 MS3 3 8 8 4 207 ADSP21065 SW WR 8 4 8 1 CMD WR BSPAB RD 2 D1 3 C3 4 B4 3 C6 5 C8 8 B4 8 C1 e DSPABC_FSI 2 RFS0 SCKI 195 DSPAB A0 1 01 1 SDI DROA 1 D1 1 C3 OB 5 DROB TFS0 Ne 18 TCLKO NC 12 DTOB 13 RFS1 15 RCLK1 7S Ore 18 19 23 DT1B NC 26 WMEVENTO NC 24 8 1 SOC DMAR2 50 DMAG1 DSPAB_A 23 0 DMAG2 3 B3 4 D6 40 e 82 _ Nc 52 ABR 00 83 D1 55 05184 DSPAB 02 nc 63768 D2 86 03 56 87 04 R65 8 SBTS 88 05 21 388 s 77 65 05 90 _ 06 p DSPAB BRI ene 27 06 07 DSPAB BR2 28 07 92 08 96 DSPAB_D9 DSPAB_EMU
122. The MC 8 is now set to route audio from the left and right RCA inputs labeled 1 to all RCA analog outputs Power on the amplifier Slowly increase the volume on the amplifier to a comfortable listening level Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep Power down the amplifier Repeat steps 5 through 7 for the remaining paired RCA outputs 4 3 8 Service Manual 11 If testing an MC 8 Balanced unit repeat the above procedure using XLR cables to connect the appropriate MC 8 XLR Main Zone outputs to the amplifier 12 The above procedure should be repeated to test Analog inputs 2 through 8 To do this repeat the procedure changing the Input Test selected in step 4 to the next appropriate Input The oscillator outputs will need to be moved to the appropriate MC 8 Input corresponding to the Input selected in the Audio I O Test Menu Digital Inputs to Main Zone Outputs Test This test will verify the audio path between the S PDIF coaxial and optical digital inputs labeled 1 to 4 to all analog outputs both RCA and XLR Note This test requires the use of a DVD CD player as a source The tests to follow will be run using a PCM signal at a 44 1kHz sample rate Test 1 Connect S PDIF coaxial digital output of the DVD CD player to the S PDIF coaxial digital input 1 on the rear of the MC 8 2 With the amplifier off connect the RCA left and ri
123. U4 4 L 680K 100 T SYNCDETOUT 13 lt gt 5VAS gt CSYNC OUT SYNC DETECT 8 05 R17 R12 2 30 1K C10 R7 40K 2 1 AFC IN H E 12 MM INT 220 10K HINH 4174HC02 46 7 C5 M5 7418 GMHSYN cg MM TC AFC OUT 24 lt 15 SYNC GND INTEGR AFC FILT VCO FILT VCO OUT lus 8 9 3 2 1 U3 s R6 5 R13 SR14 2 L S22K 5220 522 e lt R8 C18 R5 gt Y1 550 y Y Y T 1559 5VV 503KHZ L RM Cl C6 C11 4 100 2 1000 68 T 1 50 3300 q 1 x 57 7 NA V R10 MULA won 10K x 1 02 12 Lawe T 220 475 1 914 ME 196 574 02 SA 15KHZ Y 6 6 7 04 RESTORER 5VV 4 74 4053 16 12 y x 2 14 13 2 07 56 INH VSS VEE CONTRACT Ul NO exicon 3 OAK PARK V BEDFORD MA 01730 5 THLE DRAWN SCHEM VIDEO BD MC4 MC8 RWH 3 13 02 SYNC STRIPPER CHECKED 3 18 02 SZE CODE NUMBER REV Qc 060 15269 2 3 1902 ISSUED 3 19 02 15269 4 6 SHEET 6 OF 8 8 6 5 4 3 2 1 gt 10 19 2004_8 34
124. Vrms Level 4 00 4 15 3 85 40kHz LP 100k lt 10 gt 500k 3 4 5 5 15 16 17 17 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_FREQ 8 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 03 40 05 0 25 None 100k 10 gt 500 3 4 5 5 15 16 17 17 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_THD 3 4 0Vrms 4 0Vrms 20 5k 10k 40k 20 Unbal Float THD N lt 01 015 010 020 00005 40kHz LP 100k 10 gt 500k 3 4 5 5 15 16 17 17 2 4 6 8 Internal 96000 Analog ANLG MAIN IN345 96K TO ANLG MAIN DIR OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level 2 104 95 00 150 00 None 100k 10 gt 22k 3 4 5 5 15 16 17 17 2 4 6 8 n a Internal 96000 Analog MAIN IN345 96K TO ANLG MAIN DIR OUT SNR 3 OFF 997 20 Unbal Float dBr Level 108 00 100 00 140 00 None 100k 10 gt 22k 3 4 5 5 15 16 17 17 2 4 6 8 n a Internal 96000 Analog ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX 2 amp 3 JOFF OFF 997 20 Unbal Float Vrms Level 80 00 70 00 140 00 40kHz LP 100k lt 10 gt 500k 3 4 5 5 15 16 17 17 2 4 6 8 Internal 96000 Analog ANLG MAIN IN678 96K ANLG MAIN DIR OUT MAIN IN678 96K TO ANLG MAIN DIR OUT GAIN 3 4 00 Vrms 4 00 Vrms 997 20 Float Vrms Level 4 00 4 15 3 85 40kHz LP 100k lt 10 gt 500k 6 7 8 8 18 19 20 20 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_FR
125. amp 5 on the rear panel of the MC8 B labeled RS232 Once these plugs are installed the test can be executed 1 When you select the test the display will read EXTENDED DIAGNOSTICS RS232 Test All buttons except for the Mode will be inactive The encoder knob is active to select another test 2 Press the Mode button to execute the test The display will read the following if both ports pass SERIAL PORT A PASSED SERIAL PORT B PASSED If Serial Port A Failed the display will read SERIAL PORT A Failed SERIAL PORT B PASSED If Serial Port B Failed the display will read SERIAL PORT A PASSED SERIAL PORT B Failed If both Serial Ports Failed the display will read SERIAL PORT A Failed SERIAL PORT B Failed To troubleshoot this type of failure use the front panel Mode gt button Each time the button is pressed a message is sent out the RS232 port at pin2 of J4 This will activate the COMO TXO signal coming from the 2180 pin 48 In the situation where the test passes the COMO signal is present 5 14 Lexicon at Z180 pin 49 as long as the wraparound plug is connected Another way to test this circuit is to verify the IR Receiver green LED lights briefly when the button is pressed This approach can be helpful when troubleshooting intermittent failures Note If the unit is attached to a debugging PC then serial port A will fail However if the PC s terminal software is showing results a
126. apparatus has been exposed to rain or moisture does not operate normally or has been dropped Refer to the operating instructions for power requirements Be advised that different operating voltages may require the use of different line cord and or attachment plug Do not install the unit in an unventilated rack or directly above heat producing equipment such as power amplifiers Observe the maximum ambient operating temperature listed in the product specification Never attach audio power amplifier outputs directly to any of the unit s connectors To reduce the risk of fire or electric shock do not expose this apparatus to rain or moisture This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and radiates radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio or television reception which can be determined by turning the equipment off and on The user is encouraged to try to correct the interference by one or more of the following measures Re orient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver i
127. gt 110 00 108 00 140 00 100 lt 10 22 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT 600 DIG MAIN COAX1 IN 96K TO ANLG MAIN XLR OUT GAIN 600 3 3 0048 6 3 00dBFS 997 n a n a Vrms Level 49 65 410 63 48 93 40kHz LP 100k 10 gt 500k 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital DIG MAIN IN 96K TO ANLG MAIN XLR OUT 600 3 3 00dBFS 3 0048 5 100 n a n a THD N lt 003 005 0002 40kHz LP 100k lt 10 gt 500k 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_RELAY_MUTE DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_RELAY_MUTE 3 0 00dBFS 0 00dBFS 997 n a n a na Vrms Level 140 00 120 00 1001 00 40kHz LP 100k 10 gt 500k 13 15 17 19 14 16 18 20 n a n a 11 External 96000 Digital A A Tests Analog Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Test Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band A In Bin AOut B Out s Source Rate Source ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 4 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 1 13 n a Internal 96000 Analog ZONE IN1 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float
128. not use this apparatus near water Clean only with a dry cloth Do not block any ventilation openings Install in accordance with the manufacturer s instructions Do not install near any heat sources such as radiators heat registers stoves or another apparatus including amplifiers that produces heat Do not defeat the safety purpose of the polarized or grounding type plug A polarized plug has two blades with one wider than the other A grounding type plug has two blades and a third grounding prong The wide blade or the third prong are provided for your safety If the provided plug does not fit into your outlet consult an electrician for replacement of the obsolete outlet Protect the power cord from being walked on or pinched particularly at plugs convenience receptacles and the point where they exit from the apparatus Only use attachments accessories specified by the manufacturer Use only with the cart stand tripod bracket or table specified by the manufacturer or sold with the apparatus When a cart is used use caution when moving the cart apparatus combination to avoid injury from tip over Unplug this apparatus during lightning storms or when unused for long periods of time Refer all servicing to qualified service personnel Servicing is required when the apparatus has been damaged in any way such as when a power supply cord or plug is damaged liquid has been spilled or objects have fallen into the apparatus the
129. second row of the VFD will briefly indicate Pass or Errors Loop SRAM Test The Burn In SRAM Test reads a bit pattern from a known location by the NON_VOL RAM SETUP AUDIO I O TESTS The Audio tests contain the following tests e Audio Input 1 Test Audio Input 2 Test e Audio Input 3 Test e Audio Input 4 Test e Audio Input 5 Test e Audio Input 6 Test e Audio Input 7 Test e Audio Input 8 Test 5 20 Lexicon e SPDIF Input CX1 Test SPDIF Input CX2 Test e SPDIF Input CX3 Test e SPDIF Input CX4 Test e SPDIF Input OP1 Test e SPDIF Input OP2 Test SPDIF Input Test SPDIF Input Test These tests put the unit into a state to pass audio through the path that is contained in the test name for troubleshooting For instance the Audio Input 1 Test would pass analog audio from analog input 1 to all the outputs VIDEO I O TESTS The Video I O tests contain the following tests e INIT INT SYNC INIT EXT SYNC e Select PAL e Select e Load Font e Color Bars e Show CHARS The video I O tests initialize the video circuitry to put the unit into a known state for troubleshooting The menu items select a few of the basic setups that can be used for troubleshooting These selections will instruct the On Screen Display OSD IC in the unit to output a video signal that can be used to verify the video circuit from the OSD to the monitor outputs of the unit 5 21 Lexicon CHAPTER 6
130. software 6 22 Lexicon On Screen Display Signals OSD chip U32 produces a character based video display that can be overlaid on program video or that can occupy a full screen based on an independent internal video generator OSD modes and parameters are controlled by an extensive set of internal registers accessed via serial interface The character strings to be displayed are loaded serially into the screen memory within the chip The bitmapped patterns that define the shapes of individual characters are stored in external font memory interfaced through the A 15 0 and D 7 0 buses see below Character dot clock is fixed at about 15 MHz based on the external LC circuit formed by L1 C108 C109 Oscillator 033 PAL 034 NTSC supplies a crystal clock The active oscillator is determined by a high level on either NTSC_EN or PAL_EN enabling the respective oscillator In overlay mode composite or S video luminance from the input amplifier is applied to YIN and similarly S video chrominance if applicable is applied to CIN The video applied to YIN is shifted to have a back porch dc level of about 1 57Vdc by 023 and associated circuitry C101 C102 passively couple the ac content of the luminance signal with the op amp providing the dc response The chroma channel is biased to the same 1 57V level by R129 R130 The OSD video is related to program video by the separate H and V syncs GMHSYN VSYNC derived by the sync stripper T
131. 0 202 09795 RESSM RO 5 1 10W 2 2K OHM 2 000 R179 434 202 09871 RESSM RO 5 1 10W 1K OHM 43 000 R180 220 248 278 280 284 290 294 R305 308 381 409 R414 431 432 437 202 09872 RESSM RO 5 1 10W 33 OHM 31 000 R328 333 335 341 R356 361 363 364 R368 377 202 09873 RESSM RO 5 1 10W 10K OHM 29 000 R3 5 7 9 11 13 15 17 R19 21 319 326 342 R378 392 401 408 R415 416 430 435 202 09874 RESSM RO 5 1 10W 2 2M OHM 2 000 R252 254 202 09897 RESSM RO 5 1 10W 470 OHM 3 000 R309 311 412 202 09899 RESSM RO 5 1 10W 47 OHM 1 000 R204 202 10557 RESSM RO 5 1 10W 4 7K OHM 10 000 R159 162 318 327 R379 380 433 436 202 10558 RESSM RO 5 1 10W 47K OHM 6 000 R52 53 205 258 R259 438 202 10559 RESSM RO 5 1 10W 100 OHM 59 000 23 42 264 269 276 279 281 283 285 289 R291 293 295 304 306 R307 352 355 417 418 202 10569 gt RESSM RO 5 6 1 10W 10 OHM 7 000 R47 51 191 251 202 10571 RESSM RO 5 1 10W 100K OHM 25 000 R128 129 132 133 136 R137 140 141 144 145 R148 149 152 153 156 R157 182 184 189 190 R193 195 200 201 440 202 10585 RESSM RO 5 1 4W 51 OHM 4 000 R208 209 214 215 202 10586 RESSM RO 5 1 4W 100 OHM 26 000 R2 4 6 8 10 12 14 16 R18 20 127 130 131 R134 135 138 139 142 R143 146 147 150 151 R154 155 158 202 10598 RESSM RO 5 1 10W 330 OHM 2 000 R249 250 202 10836 RESSM RO 5 1 4W 1K OHM 6 000 R166 167 170 171 R174 175 202 10890 RESSM RO 5 1 10W 220 OHM 18 000 R43 44 382 389 391 R413 419 429 202 10946 RESSM RO 5 1 10W 3 3K OHM 1 000 R407 2
132. 0 Mounting Option 630 08670 WSHR FIN 10 NYL BLK 4 000 640 08671 SCRW 10 32X3 4 FH PH BLK 4 000 640 14680 SCRW M4X14MM FH SCKT SS 6 000 701 15453 BRACKET MTG RACK 2U MC8 2 000 MC 8 to MC 8B Upgrade Option 023 15439 PL XLR BD ASSY MC8B 1 000 540 02472 PLUG HOLE 3 8 BLK 4 000 640 10499 SCRW M3X8MM PNH PH BZ 2 000 XLR BD TO 1U CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 3 000 1U FP TO 1U CHAS 640 15476 SCRW M4X8MM PNH PH ZN 4 000 641 14898 SCRW TAP 4X1 4 PNH PH BZ TRI 20 000 XLR BD TO 1U CHASSIS 680 14494 CABLE 10 SCKTX2 180 2X17C 6 1 000 XLR BD J11 700 15450 CHASSIS 1U MC8B 1 000 702 14454 PANEL FRONT 1U MC12B 1 000 720 13632 PAD FOOT 1 438DIA 4 000 10 CHASSIS 4 5 2 1 REVISIONS zm ADD ASSEMBLY SEQUENCE a V D CW 1 17 01 BOM NO PER DCR 010109 01 wy 1 17 01 1 17 01 ADD 023 16129 VCO ASSY AN 5 5 03 cw 5 9 03 PER ECO 030314 00 CLC 5 8 03 KAB 5 12 03 5 1 PART NO S SHOWN FOR REFERENCE ONLY SEE BOM 022 14458 STEP SOLDER SEAM BETWEEN COVER amp HOUSINC TYPICAL 4 EDGES STER AS INSTALL COVER 700 14839 STEP 4 HOUSING SOLDER BOX SEAMS TYPICAL 4 CORNERS SIER SOLDER BD ASSY TO HOUSING 4700 14838 SIEP 2 SOLDER 2 PINS TO HOUSING STEPS 4 amp 5 ALL HOUSING SEAMS amp SEAMS BETWEEN THE COVER amp HOUSING ARE TO BE SOLDERED PER PCB WORKMANSHIP 0 07 1
133. 0 036 38 340 14535 1585 3 3 REG TO220 1 000 096 340 15492 ICSM LIN PGA2310 VOL 15V SOIC 5 000 01 5 340 15493 ICSM LIN PGA2311 VOL 5V SOIC 1 000 035 340 15740 ICSM LIN LM56C THERMO LP SOIC 1 000 U66 345 13138 ICSM INTER CS8414 RCVR SOIC 2 000 U64 65 345 13140 ICSM INTER RS232 XCVR 5V SOIC 1 000 U29 346 10549 ICSM SS SWITCH DG408 SOIC 4 000 U32 33 41 42 346 14583 5 55 SW ADG451QUAD 1P1T SOI 7 000 U6 10 31 40 350 13676 ICSM CPLD MC12 MEM V1 00 1 000 U83 350 13854 ICSM FPGA XCSO5XL 4 10X10 VQFP 1 000 U72 350 13863 ICSM SRAM 32KX8 70NS SOIC 20uA 1 000 U90 350 14540 ICSM FPGA XCS20XL 4 20X20 PQFP 1 000 U87 355 13829 ICSM ADC AKM5383 24b 96kHz SOP 1 000 U45 355 14761 ICSM DAC AK4395 24BIT VSOP 5 000 U16 20 365 13861 ICSM uPROC Z8S180 33MHz PQFP 1 000 U84 365 14683 ICSM uPROC PIC16C54 MC12 V1 00 1 000 U89 390 13885 CRYSTAL OSCSM 29 491MHz TRI 1 000 U85 390 14544 CRYSTAL OSCSM 24 576MHz TRI 3V 1 000 U73 410 11639 RELAY 2P2T DIP 5V HI SENS 5 000 RY1 5 430 10419 LEDSM INNER LENS RED 3 000 D23 43 45 430 10420 LEDSM INNER LENS YEL 7 000 021 49 51 52 54 056 58 430 10421 LEDSM INNER LENS GRN 8 000 022 41 44 50 53 055 57 59 460 04598 BATTERY LITH 3V 160 2 1 000 500 03620 CONN EURO C ROW a c FEM 4 000 J34 36 38 500 13643 CONN EURO C 48P abc RECP VERT 1 000 J48 510 03922 CONN POST 100X025 HDR 6MCG 1 000 J35 510 10546 CONN POST 079 HDR 4MC 1 000 J43 510 10745 CONN POST 100X025 H
134. 0 05 0 10 0 50 None 100k 10 gt 500k 13 57 2 4 6 8 11 External 96000 Digital DIG MAIN COAX1 IN 96K ANLG MAIN OUT THD 3 1 00dBFS 1 00dBFS 20 2k 8k 40k THD N lt 003 010 005 0175 0002 40kHz LP 100k 10 gt 500k 1 9 5 7 2 4 6 8 n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT XTALK 3 1 00dBFS 1 004 5 15k n a dB Level gt 90 00 80 00 150 00 None 100k 10 22k 18 57 2 4 6 8 11 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT DYNRNG 3 60 00dBFS 60 00dBFS 997 n a n a THD N gt 110 00 108 00 140 00 40kHz LP 100k 10 22k 13 57 2 4 6 8 1 External 96000 Digital D A Tests Digital Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band Bin A Out B Out PGM s Source Rate Source DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT OUTLEVEL MUTE DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT OUTLEVEL MUTE 3 40 00dBFS 0 00dBFS 997 Vrms Level 104 00 100
135. 0 40k 20 Unbal Float THD N lt 010 015 400005 40kHz LP 100k lt 10 gt 500k 9 10 8 20 n a Internal 96000 Analog ANLG ZONE IN8 96K TO ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 9 10 8 20 Internal 96000 Analog ANLG ZONE IN8 96K TO ANLG ZONE DIR OUT SNR OFF OFF 997 20 Unbal Float dBr Level 108 00 95 00 140 00 100k lt 10 gt 22k 9 10 8 20 Internal 96000 Analog ANLG MAIN IN1 96K TO ANLG MAIN OUT ANLG MAIN IN1 96K TO ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 47 80 48 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 1 13 n a Internal 96000 Analog ANLG MAIN IN1 96K TO ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100 lt 10 gt 500k 1 2 1 13 Internal 96000 Analog ANLG MAIN IN1 96K TO ANLG MAIN OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k lt 10 gt 500k 1 2 1 13 Internal 96000 Analog ANLG MAIN IN1 96K ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 100 lt 10 gt 22k 1 2 1 13 n a Internal 96000 Analog ANLG MAIN IN1 96K TO ANLG MAIN OUT SNR 3 OFF OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100k lt 10 gt 22k 1 2 1 13 Internal 96000 Analog ANLG MAIN IN2 96K TO ANLG MAIN OUT ANLG MA
136. 00 in parallel with 150pF 200mVrms typical 4Vrms maximum RCA connectors 400mVrms typical 8Vrms maximum XLR connectors MC 8 Balanced only maximum value with full scale input signal and volume at OdB 1000 in parallel with 150pF RCA connectors 500 in parallel with 150pF XLR connectors MC 8 Balanced only Video Input and Output Connectors Video Inputs Video Outputs 5 composite RCA 5 S video and 3 component video RCA 2 composite RCA 1 monitor 1 Zone 2 2 S video 1 monitor 1 Zone2 and 1 component BNC Composite and S video Performance Compatibility Switching Output Level Impedance Input Return Loss Differential Gain Differential Phase Bandwidth K Factor Gain 3 2 NTSC PAL and SECAM Active 1 0V peak to peak 750 gt 40dB lt 0 5 lt 0 5 gt 25MHz lt 0 3 0 15dB Lexicon Signal to Noise Ratio Frequency Response gt 65dB 10Hz to 10 2 0 1 0 3dB Component Video Performance Compatibility Switching Impedance Bandwidth Insertion Loss 3 Channel Y Pb Pr format independent Passive 750 gt 150MHz lt 3dB Microphone Input Connectors For V2 and Higher Units Input Input Sensitivity Input Impedance Other Trigger Outputs RS 232 Serial Input Output Power Requirements 4 3 5 miniature phone jacks 10mVrms 400mV maximum input level 20kQ accepts balanced or unbalanced input signals 1 power on off and 1 progra
137. 01737 644 02716 680 11461 680 14854 680 15469 680 14083 680 14494 680 14536 680 14537 680 14539 7 6 5 4 2 1 DESCRIPTION QTY WHERE USED DESCRIPTION PL MECH ASSY FP MC8 B MECH ASSY SDP5 es PL MECH ASSY VIDEO 1 Grates PeR 4031111200 90 8 13 04 PL FAN ASS D 55 8 1 PL BD ASSY 50 5 PL MEMORY BD ASSY MC8 B 1 PL MEMORY BD ASSY 50 5 PL DSP BD ASSY 1 PL DECODER BD ASSY 1 ITEM PART DESCRIPTION QTY WHERE USED PL XLR BD ASSY 1 8B ONLY PL MIC BD ASSY 1 MC8 B V2 ONLY 50 680 15465 CABLE HSG HSG 8C SLV 16 17 1 6OW PWR SUP TO MAIN BD 51 680 15470 CABLE 3 5MM JACK HSG 2C 3 1 IR CONN TO MAIN BD LOCTITE 242 D CONN JSCKT 52 680 16405 CABLE PWR HSG 110 QDC 2C 5 P3 N 1 PWR SW 80W PWR SUP 53 680 16406 CABLE HSG HSG 12 10 SLV 16 17 1 80W PWR SUP TO SWITCH ROCKER 1 54 700 15447 CHASSIS 20 1 CONN AC 3C SNAP IEC 1 55 700 15448 COVER 2U 1 CONN PLUG 200 4FC RA 1 MC8 8B 56 700 15449 SUPPORT PS 1 CONN DIN 5FC 180DEG PCRA SHLD 1 BD J16 SDP5 ONLY 57 700 15450 CHASSIS IU 1 8B ONLY CONN DSUB JSCKT 4 40 4 D CONN TO REAR 58 702 14495 PANEL ACCESS 1 CHASSIS BOTTOM MC8 0 5 TIE CABLE NYL 2 FERRITE SLV TO PS SPRT 59 702 14454 PANEL FRONT 1U 1 8B ON
138. 02 LFR 1 4002 010 apy 47125 2 R94 150 LEFT FRONT OUT 22K 4 C87 R101 15V os h 150PF T LFRONT R95 id R98 18PF gt m 3 03 1 Res 2 94K 3 01K 1 1 18 C84 Y AB 47 25 1 15 R86 R89 3 03 RERONT 2134 Roo 1 T 5 Tm ap 47 25 R84 150PF RIGHT FRONT OUT 22K U9 4 C80 R91 15V m L 150PF J9 RFRONT R85 15V R88 18PF 8 T 3 03 1 2 94 3 01K 1 1 pia R76 R79 3 03 SUB 3 D3 m SUB OdBFS 8Vrms R75 2 94K 1 R66 R65 2 94K 1 3 01K C74 1 R78 18PF 3 01K 1 R69 3 01K C67 1 SUB2 R68 18PF 3 01K 1 CENTER OUT SUB OUT OdBFS 16Vrms 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V POWER 4 zm DIGITAL V ANALOG CHASSIS GROUND GROUND GROUND 7 GROUND 5 XX XX DENOTES SHEET NUMBER SECTOR 6 LAST REFERENCE DESIGNATORS USED C92 D2 FB22 J11 Q2 R102 RY10 010 7 COMPONENTS MARKED WITH ARE NOT ON BOM DOCUMENT CONTROL BLOCK 74060 15349 SHEET NUMBER REVISION TITLE 10F3 0 FRONT CENTER SUB OUTPUTS 20F3 0 SIDE REAR OUTPUTS 3 0 ZONE2 OUTPUTS COPY
139. 02 KB KB 9 5 02 9 9 02 2 CHANGED PER DCR 020814 00 D NOTES 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE 4 DIGITAL gt ANALOG 1 CHASSIS j POWER GROUND GROUND 7 GROUND GROUND 5 XX XX DENOTES SHEET NUMBER SECTOR 6 LAST REFERENCE DESIGNATORS USED C28 D3 FB1 J1 Q1 R8 RP6 U6 W1 7 COMPONENTS MARKED WITH NOT ON BOM 8 NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC DOCUMENT CONTROL BLOCK 74060 15319 SHEET REV DESCRIPTION 1 4 2 MAIN 2 4 2 4 2 DOLBY DIGITAL DTS DECODER 3 4 2 REGULATOR amp BYPASS CAPS COPY 2002 Lexicon Inc 3 01730 TITLE SCHEM DECODER BD MC8 MC12 DRAWN 3 21 02 MAIN BD CONNECTOR CHECKED KB 3 26 02 SEE CODE NUMBER REV 060 15319 cw 3 26 02 ISSUED FILE NAME 3 26 02 15319 2 1 SHEET 1 OF 4 A W 3 2002_14 31 N 10 2 1 C3 1 B5 1 B5 DB PROG NC NC 3 3VD SEE NOTES R7 M1 NC2 PROGRAM DB D 7 0 DB DB RD 1 B3 2 D1 gt DB WR 1 B3 2
140. 02 10948 RESSM RO 5 1 10W 390 OHM 1 000 R22 202 10949 RESSM RO 5 1 10W 1 2K OHM 4 000 R255 256 261 316 202 11041 RESSM RO 5 1 10W 680 OHM 1 000 R1 202 11071 RESSM RO 5 1 4W 75 OHM 1 000 R277 202 12836 RESSM RO 5 1 10W 2 7K OHM 2 000 R45 46 202 14792 RESSM RO 5 1 10W 56 OHM 23 000 R163 164 260 265 268 R310 312 325 334 R344 351 366 367 R402 404 203 10424 RESSM RO 1 1 10W 4 99K OHM 2 000 R262 263 203 10583 RESSM RO 1 1 10W 10 0K OHM 3 000 R206 207 317 203 10896 RESSM RO 1 1 10W 1 00K OHM 4 000 R168 172 176 439 203 11088 RESSM RO 1 1 10W 49 9K OHM 8 000 R64 68 74 78 84 R88 94 98 203 11737 RESSM RO 1 1 10W 5 76K OHM 8 000 R66 71 76 81 86 R91 96 101 203 11741 RESSM RO 1 1 10W 18 2K OHM 1 000 R253 203 11993 RESSM RO 196 1 10W 357 OHM 4 000 R55 57 59 60 203 11996 RESSM RO 1 1 10W 6 49K OHM 8 000 R62 63 72 73 R82 83 92 93 203 11997 RESSM RO 1 1 10W 13 7K OHM 1 000 R315 203 12167 RESSM RO 1 1 10W 374 OHM 1 000 R178 203 12363 RESSM RO 1 1 10W 90 9 OHM 1 000 R177 203 12370 RESSM RO 1 1 10W 280 OHM 16 000 R65 67 69 70 75 77 R79 80 85 87 89 90 R95 97 99 100 203 12371 RESSM THIN 1 1 10W 2 74K OHM 4 000 R54 56 58 61 7 1 EFFECT REFERENCE 203 12719 RESSM THIN 1 1 10W 2 00K OHM 4 000 R212 213 218 219 203 12722 RESSM THIN 1 1 10W 49 9K OHM 1 000 R257 203 13131 RESSM RO 1 1 10W 8 45K OHM 3 000 R165 169 173 203 13133 RESSM THIN 1 1 10W 1 15K OHM 4 000 R10
141. 09 222 EMU 145 97 010 D AS _ DSPB_TDO 146 FMU 010 DSPAB_D11 DIAG 148 D11100 DSPAB D12 ine DSPAB TCK 151 ok 013 101 DSPAB D13 DSPAB_TMS 149 104 DSPAB_D14 A TRST 147 we 107 015 2 6 01508 D16 _ DSPAB_STATUS_FULL 197 109 D17 2 B8 8 C4 gt psp 1 DIT 11 DSPAB_D18 2 88 5 88 6 88 8 84 FLAG1 018 x NC 499 E AGA D18 12 D19 201 EACS 113 ___ _020 138 0201416 021 137 FLAGS Doo 117_ 022 022 023 023 121 24 80 FLAGS 024 122 DSPAB_D25 79 Ed 025 123 DSPAB D26 PAGG 05 126 027 NC 76 058 127 028 055 128 DSPAB 029 102 132 030 NC1 D30 DSPAB D 31 0 103 NC2 031 133 031 CAU NR 2 A3 4 D7 8 C4 NC3 NE 2 NC4 BMSTR 23 DSPB BMSTR 805 BMSTR NC 202 405 GND j 01 LLI LLLI lexicon 01730 TITLE APPROVALS DATE DRAWN SCHEM MIC DSP BD MC8 DSPB_OUT1 RWH 5 20 02 4 B8 8 C7 4 B8 8 C7 CHECKED 5 29 02 SIZE CODE NUMBER REV 060 15389 1 cw 6 3 02 NAME ISSUED KB 6 3 02 15389 2 3 SHEET 3 OF 10 8 6 5 4 3 2 1 12 15 2004 8 57
142. 1 a EC HINBSY 141 HINBSY GPIO8 SD 8 8 66 3 10 DEC 17 61 44 DEC AB CS 120 WR DS GPIO10 SD 7 AA 2 10K DEC 91 4 ABCS 6 121 W GPIO11 SDWEp22 _RP1 3 A AG 10K EC SCDIN 130 RD R_W DEC_NVWE_DLY ABIN AQ GPIO13 2 84 QWE 139 1 12 NVCSN GPIO14 22 2 B4 3 C1 EEG FLASH CS 300 ABOUT 116 1 1 DEC NVOE 324 115 HDATAO GPIOO NVOEN GPIO15 37 512 8 DE US 115 NVWEN GPIO16 GND 200NS CCS BEC C Ses HDATA2 2 DEC SCDIN tae HDATA3 GPIO3 SDADDRO EXTAO U1 DEC C SCDQUT 4 03 HDATA4 GPIO4 SDADDR1 EXTA1 C HDATAS GPIOS SDADDR2 EXTA2 25 GPIO6 79 S 7 GPIO7 SDADDR4 EXTA4L 67 24 ELIT SDADDR5 EXTA5 AB MM 2 c7 ale DEC AB ABOOT IRQ NTREG 65 DEC_NVCS __ _6 1020 5 E 63 DEC A7 DEC FLASH AO 21 4 3 1 DEC 6970 62 8 DEC NVWE DEC FLASH A1 2 C4 3 C4 DERE ERES 2 FAO FSCCLK SDADDR8 EXTA8 2 B7 3 C1 4 3 1 7 SDADDR9 EXTAQ 2 C7 3 C1 _ FHS2 FSCDIO FSCDOUT SDADR10 EXTA10 NVOE RP3 6 333 1211 NVWET 12 FHS
143. 1 gt KA 1 1125 Uus U57 17 74HCU04 56 029 R259 R258 que 44 1K AND 48K 512FS lt R263 47K 47K 1 914 299 lt 4 99 88 2 AND 96 256 FS 9 1 1 C295 252 gt 5 R254 ane 2 2M lt 15V 1 25 gt 2 2M T C301 R262 27 028 7476 24 Loeme 253 1 BAR35 18 2 77 74 04 HA NO lexicon BEDFORD MA 01730 TITLE APPROVALS DATE SCHEM MAIN BD MC4 MC8 DRAWN RwH 2 15 02 LOCK LOOP CHECKED cv 3 29 02 SIZE CODE NUMBER REV 060 15259 5 cw 4 3002 NAME ISSUED kaB 4 3 02 15259 6 10 sHEET 10 oF 23 8 7 6 5 4 3 2 1 10 19 2004 8 58 7 6 5 4 3 2 1 REVISIONS tq 10 REV DESCRIPTION aov CASE GND 1 CHANGED PER DCR 020430 00 Ko ON OFF FB20 KB KB 5 m TRIGGER TT 82872 LM2941CT R165 RET Rige 2 CHANGED PER DCR 020731 00 8 1 02 8 5102 C229 GND_ ADJ gt 8 45K C222 Sy C221 CBV KB ATUF 3 1036 71 T 22 16 w 150PF 8 5 02 8 14 02 RWH CW
144. 10 5 17 Internal 96000 Analog ANLG ZONE IN5 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40k 20 Unbal Float THD N lt 010 015 00005 40kHz LP 100k 10 gt 500 9 10 5 17 Internal 96000 Analog ANLG ZONE IN5 96K ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100k lt 10 gt 22k 9 10 5 17 Internal 96000 Analog ANLG ZONE IN5 96K ANLG ZONE DIR OUT SNR 997 20 Unbal Float dBr Level 108 00 95 00 140 00 100k lt 10 gt 22k 9 10 5 17 Internal 96000 Analog ANLG ZONE IN6 96K TO ANLG ZONE DIR OUT ANLG ZONE IN6 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 4 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 6 18 n a Internal 96000 Analog ANLG ZONE IN6 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 10 0 10 0 25 None 100k lt 10 gt 500k 9 10 6 18 Internal 96000 Analog ANLG ZONE IN6 96K ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40k 20 Unbal Float THD N lt 010 015 400005 40kHz LP 100k lt 10 gt 500k 9 10 6 18 Internal 96000 Analog ANLG ZONE IN6 96K TO ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 9 10 6 18 Internal 96000 Analog ANLG ZONE IN6 96K TO ANLG ZONE DIR OUT SNR 997 20 Float dBr Level 108 00 95 00 140 00 100
145. 10544 CAPSM CER 220pF 50V COG 5 16 000 C69 71 73 77 79 81 C85 87 89 93 95 97 245 10561 CAPSM CER 100pF 50V COG 5 4 000 C278 279 282 283 245 10562 CAPSM CER 150pF 50V COG 10 42 000 C1 10 164 165 170 C171 176 177 182 183 C188 189 194 195 200 C201 206 207 212 215 C221 223 225 308 313 C315 319 320 322 324 C326 408 245 10588 CAPSM CER 33pF 50V COG 10 1 000 C228 245 11592 CAPSM CER 680pF 50V COG 5 4 000 C61 63 65 245 11594 CAPSM CER 2200pF 50V COG 5 4 000 C114 115 267 274 245 11645 CAPSM CER 47UF 50V Z5U 20 3 000 C229 231 245 11949 CAPSM CER 1500pF 50V COG 5 8 000 C124 125 134 135 C144 145 154 155 245 12485 CAPSM CER 1uF 25V Z5U 20 203 000 13 16 19 22 25 28 7 2 31 34 37 40 41 43 44 46 47 49 50 52 53 55 57 58 60 64 66 68 72 74 76 80 82 84 88 90 92 96 117 118 120 122 127 128 130 132 137 138 140 142 147 148 150 152 157 158 160 162 168 169 174 175 180 181 186 187 192 193 198 199 204 205 210 211 216 220 227 232 243 245 246 251 262 264 265 268 C269 272 273 275 277 C280 281 284 292 C294 300 304 307 328 C330 334 335 337 339 C340 342 344 384 C386 391 394 401 C404 413 QTY EFFECT REFERENCE 270 00779 FERRITE BEAD 14 000 FB1 10 20 22 24 270 06671 FERRITE CHOKE 2 5 TURN 4 000 FB29 32 270 09799 FERRITESM CHIP 600 OHM 1206 6 000 FB11 15 23 270 11545 FERRITESM CHIP 600 OHM 0805 9 000 FB16 19 25 26 28 FB33 34 270 13802 INDUCTORSM 24uH 20 2
146. 1168 lctt585w 8 2 GND DIF1 AGND LE 2200PF 680PF 5 47K 4 s 069 14 pir vREFL 47 L i 1068 8595 195 1178 po 15V 4 1 15 357 15V 5VAD 0168 125 1 1 4 4 13 12 ADG451 NOTES VDD 14 02 RIGHT ZONE IN 2 012 VEE GND s 068 15V E1 ZONE2 OUTPUT LEVEL CONTROL T 15 R23 LZONE 21 C8 i 00 15 2 2 35 C16 5VA 4 1 25 OdBFS 2 0Vrms 15 127 PGA2310 284 e J1 LZONE_DACOUT 16 14 8 R2 16 02 AINL AOUTL mum ZONE2 LEFT OUT 4 C4 ZONE_VC_CLK 6 4 aa s R38 i AW __ ZONE DATA 3 418 42 gt 10K 8 SDIN 5522222 ZONE VC CS 2 5 ex 11 4 4 Ve dcs DGND 2 o 21 83 ZONE VC ZCEN Y gt 21 83 e ONE VC MUTE spout 7 8 lt R4 16 C2 RZONE DACOUT 9 AR AouTR 11 T p4 3 A ZONE2 RIGHT OUT 2 100 AGNDR VA 45 144002 0 160 10 U1 gt 10K o fexicon sompa RZONE NO 21 C8 ae lexicon BEDFORD MA 01730 A ZONE_RLY_CNTL x e RE 21 88 APPROVALS LE _ SCHEM MAIN BD MC4 MC8 ZONEOUT MUTE V 2NA401 RWH 2 15 00 70NE2 DAC 21 03 P Nw HE 3 29 02 SIZE CODE NUMBER REV ai 060 15259 4 5 ew 41302 FILE NAME ISSUED 4 3 02 15259 6 16 5 16 23
147. 13 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C 5 gt d AANA R19 1 020523 00 anion nin ECM KAB us 48204 6 4 02 6 5 02 05081 1 2 OSD_B PB R21 5 02 Rs 2 USE SPARE PER 021105 00 04 LL 29 4K Us 11 12 02 11 12 02 05081 3 4 080 R 3 UPDATED FOR 040922 00 RWH CW 5 86 amp 92 5 080 R20 9 27 04 10 14 04 74 04 U5 11 gt 10 OSD_R 150 R28 9 27 04 9 27 04 R25 75 0 74 4 1528 lt 1 am 1 05 1 75 12 2750 W 5 B6 030 61 5 6 OSD G in p 74 04 5VV 47PF ospg 824 10 0 1 050 61 9K 12 R30 R23 R34 osp pg our 11 8K 976 PR 1 R33 1 75 0 RS 19765 N 1 COMPONENT VIDEO INPUTS 1 5 1 lt bea s 55 INPUT 1 2 7 L 71 SPARES J8 J5 05 AE ATPF 13055012 Y TANCOA y Y S R41 gt R36 15 S 15K gt NC 6 NC 8 9 gt R39 PR R35
148. 145 10 97 DSPAB D10 DSPA_TDO 146 D11 DSPAB TDI 148 011 100 012 DSPAB TCK 151 012 101 D13 DSPAB TMS 149 013 104 DSPAB 014 DSPAB_TRST 147 TEST 015 107 DSPAB 015 DSPAB_STATUS_FULL 197 x 3 88 188 DSP FLAG 198 FLAG1 D18 111 _018 5 88 6 88 499 FAS 018 112 019 201 D19 113 020 138 Boc 020 116 DSPAB 021 137 eee 021 117 022 136 Frace 022 118 023 134 D23 121 DSPAB 024 FLAGS 025 123 DSPAB D26 DEVELOPMENT ONLY FLAG10 120 627 PIN 7 JUMP PIN 8 FLAG11 628 15 DSPAB D29 PIN 9 BTRST JUMP TO PIN 10 p29 125 DS NC 103 1 030 133 031 DSPAB 0131 01 3 3VD 3 3VD 115 NC2 D31 3 A3 4 D7 8 C4 NC 142 Nea BMSTR 53 BMSTR BMSTR NC 202 4 DSPA_ 08615 TDO NC 203 woo Nc 208 DSPAB EMU DSPAB EMU NC ICE 13 88 GND DSPAB_TMS DSPAB_TMS 3 8 RSRSSSOOSSREESSSSISSRSSESSSSSKSSS 016 DSPAE TEST DSPAB TEST gt 3 88 5 CONTRACT 1 TDI 3 88 5O exico n PARK 01730 5 8625 APPROVALS THLE E DSPA OUT1 4 B8 8 C7 DRAWN SCHEM MIC DSP BD MC8 7 77 DSPA OUTO 4 B8 8 C7 RWH 5 20 02 DSPA 3188 DSPB CHECKED 5 29 02 SIZE
149. 164 196 1 87 3 28 2 4 4 v4 7905 45VV IN GND V SY2 15 1 027 NC 12 __ MSTHRU 7 21 Sj Z x 7 05 i 1 C7 3 C8 gt NG 5 Ma OUT IN 74HC4053 16 2 2 vec RE Y 56 28 INH VSS 6 U1 8 7 VSS V y 8 7 017 5VV 4 Uu 7105 5 5 5VV 4 5VV R134 2 10K 2 i 74HC4051 R133 iy et NC 13 Veg 1 85 SC4B 14 Yi 2N3906 cs SC2B 15 v5 _ 2 3904 C113 NC 12 1 25 1 05 SC1B 1 M OUT IN I lt R131 5 NC 2 3038 255 5 132 015 1 88 p SC5B 4 S 33K s CVID ZON la 10 C112 1 25 1 1 15 5VV Sinn 7 B5 VSS R162 EL4422 R153 7 019 1 15 1 1 15K V 4 2 x 4 IN1 z __ R159 XJ 8 RISS CVID_MAIN 4 1 VOUT 7 A _OSD_Y C_OUT 5 am 1 a id 74HC4051 1 080 J16 v 13 vo MC IN 0 GND V U28 864 14 ra puaa amal 552 15 n 715 7 1 2 COMPOSITE VIDEO NC 12 8171229 R156 V OUTPUTS _ 561 1 1 1 C4 3 B8 Y4 OUT IN SC3 Ne ANG 1 1 2154 301 1 SCO R1612 3012 100K gt 452 11 5VV t R160 s lt 9 vm DUE
150. 1730 TITLE APPROVALS DATE SCHEM MAIN BD MC4 MC8 DRAWN RwH 2 15 02 OPTION BD 1 CONNECTOR CHECKED cy 3 29 02 SIZE CODE NUMBER REV 060 15259 4 cw 41302 FILENAME ISSUED kaB 4 3 02 15259 6 7 SHEET 7 OF 23 7 6 5 4 3 2 1 10 21 2004_8 21 7 6 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 KB KB 6 4 02 6 26 02 RWH CW 2 CHANGED PER DCR 020731 00 352 8 5 02 8 14 02 3 CHANGED PER DCR 020827 00 cw 130102 9 12 02 3 3VD 5VD 9 12 02 9 12 02 RWH CW 4 UPDATED FOR MC4 PER DCR 040922 00 236 8 AT AT C32 9 27104 9 27 04 aaa 82 AUDIO 10 0 AUDIO 532 27 27 C31 ___ 2 1 2 83 DB2_AUDIO1 A30 29 DB2_AUDIO2 29 28 DB2_AUDIO3 A28 27 DB2_AUDIO4 A27 C26 082 AUDIOS A26 C25 DB2_AUDIO6 25 24 DB2_AUDIO7 24 C23 DB2_AUDIO8 A23 C22 082 AUDIO 4 2
151. 2 9 12 02 179 ano 199 ZINTO 078 178 05 ZINTO 108 ZINT1 1 1 1 8 9 2 02 9 12 02 177 06 ZINT1 197 ZINT2 1 614 68 RWH CW D7 ZINTZ 1 C1 1 C8 4 UPDATED FOR MC4 PER DCR 040922 00 Spande Ciona z 2 15 0 194 XCS20XL 4PQ208 75 MAININ_VC_CS AT AT 1 D4 2 D8 5 C7 6IC6 7 C6 8 C6 12 A6 A0 MAIN_IN_VC_CS DAA 15 B8 ZA1 193 76 MAININ_VC_CLK 9 27 04 9 27 04 7 2 191141 MAIN_IN_VC_CLK go 15 881 T qp A2 MAIN VC DATA 15 8 244 189 AUDIO FPGA FRONT VC CS 87 FERONT YO ES ZA5 188 ALPONI CENTER VC CS CTR_SUB_VC_CS 18 A8 2 6 187 2 8 005 89 SIDE 5 A6 VC CS 00 REAR VC CS w 19 AB IO RD 206 REAR MAINOUT 20 A8 2 01 2 03 5 7 6 7 71 6 8 86 O WR 5070 RD MAIN_OUT_VC_CLK MAINOUT VC DATA 17 B8 18 B8 19 B8 20 B8 12 01 2 03 5 7 6 7 7 6 8 6 AUDIO FPON Aog WR MAIN OUT DATA gt a 17 A8 18 B8 19 B8 20 A8 2 23 dcs 1 B3 2 C5 3 B8 O_RST 204 RESET FRONT DAC CS 95 ERENT DAC ES 17 8 TEST POINTS _ AUDIO 4MHZ 55 CS 97 MAIN DAC CCLK gt 18 C8 19 C8 20 C8 MAIN PATH 2 01 2 83 4 MHZ TDI MAIN DAC CCLK MAIN DAC CDATA 17 C8 18 8 19 C8 20 C8 COAXI4 1 MAIN DAC CDATA 17 C8 18 C8 19 C8 20 C8 COAX1 56 PLL_MCKO 112 03 2 57 COAX 112 ZONE_V
152. 22 OF 23 5 POWER SUPPLY R390 220 5 381 lt R379 23 OF 23 4 BYPASS CAPACITORS lt R382 OAK S47K Ren 722 TRIGGER D43 4 D45 1 914 3 OAK PARK GRN GRN j No exicon AV BEDFORD MA 01730 D44 041 TITLE APPROVALS DATE L 385 4R378 lt R380 DRAWN SCHEM MAIN BD MC4 MC8 1 50 gt 10K 547K RWH 2 15 02 HOST 8 MEMORY CPLD CHECKED 3 29 02 SIZE CODE NUMBER REV ac B 060 15259 6 cw 41302 FILENAME ISSUED 4 3 02 15259 6 1 SHEET 1 OF 23 8 7 6 5 4 3 2 1 10 19 2004_8 58 REVISIONS REV DESCRIPTION gt 1 B3 10_CCLK lO_DONE 12 B7 1 CHANGED PER DCR 020430 00 YA Num 4 SICT G CO
153. 229 ZONE DACOUT SEU 18007 LL LZONE 28 1 IODX6 228 ZONE DIRECT SEL gt 16 2 29 IODX7 18 19 R227 ZONE_VC_MUTE 16 A8 21 03 EXPOUTS_MUTE 2 4 A4 ANLG_REG3_CS CLK ZONE_RLY_CNTL 32 10 ERE 16 A2 NU 33 ND 34 U50 J28 8 74VHC273 20 voy IODX0 Bag T R228 FRONT ZCEN jg IODX1 4D 205 R224 CENTER VC ZCEN 27 18 A8 IODX2 7302 6 IODX3 8 0 409 R226 SIDE_VC_ZCEN IODX4 1360 8012 R225 REAR VC ZCEN gt 5 90 60 16 100 7 18 19 ANLG_REG4_CS 1 R222 1K ZONE_VC_ZCEN 16 A8 10 049 IODX 7 0 18 06 gt 74VHC273 20 IODX0 3 2 R245 MAIN_DAC_RST IODX1 58 5 R246 MAIN DACOUT SEL BICI PIC IODX2 a sals R247 MAIN_DIRECT_SEL 27 anion IODX3 409 R248 MAINOUT VC 2 iras 19 A8 20 A8 IODX4 13 502 5012 R244 DAC RSTI gt IODX5 14 15 R243 FRONT SEL IODX6 17 7 24116 R242 FRONT DIRECT NLS RECS 100 7 18 24119 R241 _ _ gt gt PBA RST 1 an GND Lb U52 CONTRACT z 9 sowa BEDFORD MA 01730 TITLE APPROVALS DATE BD MC4 MC8 DRAWN RWH 2 15 02 XLR BD CONN CONTROL REG CHECKED 3 29 02 SIZE CODE NUMBER REV 060 15259 4 CW 4 3 02 NAME ISS
154. 25 DSPCD_A11 20 44 10 DSPCD 026 DSPCD_A12 21 412 03 11 DSPCD_D27 DSPCD_A13 29 412 22 DSPCD_D28 DSPCD_A14 30 Aja Ds 23 DSPCD_D29 CONTRACT DSPCD_A15 31 26 DSPCD 030 3 15 D6 NO XI na DSPCD_A16 32 27 DSPCD 031 u AIDi BEDFORD 01730 222 DSPCD SRAM CS DSPCD SRAM CS 5 B C1 5 C3 6 C3 EE 5 LE 5 C3 5 D1 6 C3 BSECD_WR AW DEAW SCHEM MIC DSP BD MC8 5 C3 5 D1 6 C3 x RWH 5 20 02 DSPCD EXT MEM 9 CHECKED 5 29 02 SIZE CODE NUMBER REV 25 VSS2 060 15389 1 5 cw 6 3 02 U1 ISSUED 7 6 3 02 15389 2 7 7 10 12 15 2004 8 52 8 7 5 4 3 2 1 m REVISIONS 4 DESCRIPTION DRAFTER Qc CHECKER AUTH CW RWH 8958 1 REVISED SIGNAL NAMES PER DCR 020926 00 070 1 83 PSP 22 FPGA DONE LED maj amp DSP CCLK eo 10 14 02 10 15 02 47 p418 2 SHOW DEPOPULATI
155. 28 97 DSPAB 010 DSPB_TDO 146 98 DSPAB 011 2 8 TDO 148 10 D11100 DSPAB_D12 2 6 151110 012101 013 gt DSPAB TMS 149 IK Bud 104 DSPAB D14 DSPAB_TRST 147 9 107 DSPAB_D15 2 6 TRST D s He Dis D16 DSPAB_STATUS_FULL 109 DSPAB_D17 2 88 DSP FLAGI FLAGI DSPAB 018 5 88 6 88 NC 499 018 112 DSPAB 019 201 65 019 113 020 020 116 021 LAO 021 117 DSPAB 522 FLAGS 022 118 023 EL 524 12 024 D24122 025 025 123 026 026 126 027 027 127 028 028 126 029 132 030 030 DSPAB D 31 0 p31 133 D31 0510 2 A3 4 D7 8 C4 53 DSPB_BMSTR DSPB_BMSTR 208 NC GND CONTRACT z NO exICOn BEDFORD MA 01730 APPROVALS DATE SCHEM DSP DRAWN DSPB_OUTI 4 B8 8 C7 2 28 02 4 B8 8 C7 CHECKED 3 5 02 SIZE CODE NUMBER REV 060 15309 1 cw 3 9 02 ISSUED KB 3 5 02 15309 2 3 SHEET 3 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
156. 3 8 7 6 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH COMPOSITE VIDEO INPUTS 5VV CVID 1 J5 41 25 2N3904 1 O K D R15 R14 CVID 5 1 1 2 YEL RCA 75 0 i CVID1 CVID5 2 R13 us CVID4 i 1 1K 5 9 CVID3 6 1 OPTICAL INPUTS 7 leun 57 4 25 CVID2 5 TORX173 CVID1 10 1 A LC13 em 11 T 10 16 12 1 13 5VV 2 Y 14 6 24 15 16 C14 J4 Cok 1 17 T 10 16 57 2 3904 TORX173 18 19 2 _ 53 20 v R12 Yaa R11 1 h gt AN 2 YEL 75 0 1 CVID2 96 1 Ri 22 624 5VD 5VD M CP2 1 1 7 11 12 11 25 4 25 T 1 25 5VV C 57 5VV 4 NOTES J3 57 1125 onagoa 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 3 oY 1 v 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 596 5 7 Pa Q3 R8 UD 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 1 1 22 4 DIGITAL ANALOG 1 CHASSIS POWER 77 GROUND 7 GROUND GROUND GROUND C5 5 LAST REFERENCE DESIGNATORS USED C14 CP2 J6 Q5 R15 A 57 4 25 5VV
157. 3 CHANGED PER DCR 020827 00 R168 4 A4 KE 1 00K 9 2 02 9 12 02 1 4 UPDATED 040922 00 RWE Cw 9 24 04 10 14 04 REMOTE POWER CONTROL AT AT U44 9 27 04 9 27 04 03 REMOTE 13 12 74VHC04 3 3V 15 ON OFF FB21 1 Hvn vouri TRIGGER1 2 LM2941CT R169 17174 C230 GND 8 45K tLc224 l R170 c223 t T A7UF 3 1037 1 T 22 16 5 4 W T 150PF v SPARES R172 p 3 3VD 4 1 00 044 044 1 4 NC _ _ 9 8 3 03 gt d 74VHC04 3 3V 74VHC04 3 3V CASE GND 044 ON OFF FB22 parce No vour S TRIGGERO 74VHC04 3 3V LM2941CT R173 U44 C231 GND 8 45K c226 R175 R174 c225 o gt T 47UF 3 1038 1 Tr 226 150PF v E 74VHC04 3 3V REMOTE_PWRENx MUST BE HIGH AT POWER UP R176 J 77 177 HIGH OFF LOW Jr non d 1 5VD RS 232 TRANSCEIVER RS 232 MAX202E FEMALE S R161 R162 NOTES 2 FAIK DE9F 1 INSTALL FOR JBL PRODUCTS ONLY C217 L 218 AST 1 25 T T 1 25 E 2 3 9 05 NE T 125 A8 RS 232 PINOUT MALE RXD_A 7 220 L 219 NEA CAP J14 1 DCD NBT 5 71 125 gt 6 DSR V C2 lt 2 RXD 7 RTS FB16 li 8 TXD
158. 3 PER ECO 030110 00 CLC 1 21 03 KB 1 24 03 CHG P N ITEM 62 PER ECO 11 19 03 CW 5 12 04 ADD MIC BD ITEM 10 FOR 2 AN 1 3 05 Cw 2 8 05 PER 4041201 00 CLC 1 5 05 MAG 2 9 05 TO ELEM FRONT PANEL ASSY zu 13 PLCS COVER DWG 080 1546 TORQUE 3 2 PLCS 8 10 IN LBS i TORQUE 4 6 IN LBS TO MAIN BD 30 31 TORQUE J29 8 10 IN LBS 2 PLCS TORQUE 7 2 4 6 IN LBS d d 27 7 7 gt 4 PLCS 7 24 7 TORQUE 7 P d 4 6 IN UBS 3 PLCS VIDEO ASSY TORQUE SEE DWG 080 15464 a 4 6 IN LBS 4 PLCS TORQUE 73 3 TORQUE 4 6 IN LBS 4 6 IN LBS MN p _ OPI d Pd p E P d 7 2 PLCS 53 7 TORQUE E 7 FROM we i 4 6 IN LBS PWR SUP 2 a ROUTE POWER CABLE 445 UNDER FAN 4 STANDBY SW CABLES Pi amp ATTACH TO SHIELD WITH CLIP ITEM 22 4 6 49 2 ONLY f ASSEMBLY IS SHOWN TRANSPARENT SO OTHER PARTS 4 amp CABLE CONNECTIONS ARE VISIBLE SEE NOTE 3 0 5 ONLY 2 PLCS TORQUE 5 PLCS 4 6 IN LBS VIDEO 68 TORQUE 4 6 IN LBS 2 6 8 IN LBS NOTE DIRECTION OF AIRFLOW 64 TORQUE e 4 6 IN LBS PRESS CABLE INTO SPACE DRESS NUT SUPPLIED WITH d 3 5 49 AT NOTCH 432
159. 3 106 203 13134 RESSM THIN 1 1 10W 1 00K OHM 4 000 R187 188 198 199 203 13537 RESSM THIN 1 1 10W 5 62K OHM 2 000 R210 216 203 13638 RESSM THIN 1 1 10W 2 49K OHM 2 000 R211 217 203 15479 RESSM THIN 1 1 10W 1 21K OHM 16 000 R107 109 112 114 117 119 122 R124 126 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 16 000 C166 167 172 173 C178 179 184 185 C190 191 196 197 C202 203 208 209 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 5 000 C310 311 316 317 410 240 10758 CAPSM ELEC 1uF 50V 20 5 5mmH 2 000 C302 385 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 2 000 C56 59 240 12330 CAPSM ELEC 2 2uF 35V 20 11 000 12 15 18 21 24 27 30 33 36 39 415 240 13216 CAPSM ELEC 22uF 16V 20 3 000 222 224 226 240 13217 CAPSM ELEC 47uF 16V 20 4 000 248 249 301 303 240 13642 CAP ELEC 47uF 25V RAD NPOL 6D 10 000 11 14 17 20 23 26 29 32 35 38 240 13803 CAP ELEC 560uF 35V RAD LOW ESR 1 000 C402 240 15668 CAPSM ELEC 330uF 6 3V 20 105C 21 000 C98 113 119 129 C139 149 159 241 09798 5 10 10 20 6 000 C244 247 276 293 C329 403 241 11799 CAPSM TANT 4 7uF 6 3V 20 27 000 42 45 48 51 54 116 121 123 126 131 133 136 141 143 146 151 153 156 161 163 250 263 266 270 271 336 341 244 10423 CAP MYL 22uF 50V RAD 5 BOX 9 000 309 312 314 318 321 323 325 327 409 244 11589 CAP MYL 068uF 63V RAD 5 BOX 2 000 C338 343 245 09291 CAPSM CER 470pF 50V COG 5 1 000 C414 245 09876 CAPSM CER 01uF 50V Z5U 20 2 000 C411 412 245
160. 3 5 2 CENTER amp SUB E7 LEVEL CONTROL 4 5 U9 y 2 Ki Has 15V C33 CENTERS 21 C8 100 22135 634 4 1 25 OdBFS 8 1Vrms 15 127 PGA2310 2 50 b CNTR DACOUT 16 14 814 EB RELAY 18 D3 E AINL AOUTL pm CENTER OUT 4 D4 17 B8 19 88 20 B8 6 4 2 R15 6 4 avi gt 10 v 4 C4 17 A8 19 B8 20 A8 VC DATA 3 050 51 8 150 125 5VAD s CENTER VC CS 2165 TN P 1 283 CENTER_VC_ZCEN 1 EN gt 9 3 19 A8 20 A8 21 B3 MAINOUT VC MUTE 8 MuTE 7 C32 R16 18 C3 SUB_DACOUT 9 ANR AouTR 11 02 AA SUB OUT 47 25 134002 100 AGNDR VA lt R17 1 4W C8 10 13 U4 10K RY4 150 T C31 41 14 C30 jui 5 _ SUB 21 C8 CONTRACT 3 OAK PARK He MAIN_RLY_CNTL __ 22135 17 B8 19 B8 20 B8 BEDFORD MA 01730 y E8 TITLE s APPROVALS DATE FROM HOST Es DRAWN SCHEM MAIN BD MC4 MC8 21 03 MAINOUTS MUTE v 2NAA01 RWH 2 15 02 CENTER SUB DACS must be low on power up CHECKED 3 29 02 SIZE CODE NUMBER REV Q2 060 15259 4 cw 41302 FILENAME ISSUED kaB 4 3 02 15259 6 18 SHEET 18 OF 23 8 7 6 5 4 3 2 1 10 19 2004_ 8 58
161. 3 DSFC_SCKI 5 C8 8 C1 DSPD_SCKI 6 8 DSP 30MHZ 2 8738 10 06 DSP_CLK 92 SES T 0 gt SP1 79 2729 5 2 79 3 2 3 AUDIOS 55 5 1 3 spa 56 871 TT AUDOB yon R68 AUDIO 4MHZ CONTRACT 3 1 C3 NO Gus BEDFORD MA 01730 eism 8 TITLE 015 APPROVALS DATE SCHEM MIC DSP BD MC8 5 4 RWH 5 2002 FPGA 777 CHECKED 5 29 02 SIZE CODE NUMBER REV S B 060 15389 2 cw 6 3 02 ElLE NAME ISSUED KB 6 3 02 15389 2 8 SHEET 8 OF 10 8 7 5 4 3 2 1 12 15 2004_ 8 52 REVISIONS REV DESCRIPTION DRAFTER Q C MIC_IN_1 R21 5VAD CHECKER AUTH MIC IN 1 15VA 5VA FB13 100K C38 C12 tes 131 12 ADGA51 E ps 47 D R26 C8 5 VDD 7 1 E 15 AA C34 10 16 10 0K pos amp D L 1 10 25 j 150 1 4W R VEE GND ey Y 4 5 025 T 1125 57 1 15VA Y L R25 15VA x 1 C35 1 1 150PF Y ru MET DEM 5 B BVA 10 0 1 4 10 16 822
162. 400 interrupt to the host The Main Zone input analog or digital is always routed through the Crystal decoder except during audio diagnostics The serial audio interface consists of DEC SDI 2 channel PCM audio stream input from either the Main Digital Receiver or the Main Analog ADC DEC 500 3 0 four 2 channel PCM audio stream outputs that are routed down to the Audio FPGA on the main board where they are converted into octal data streams that are then sent to the Sharc DSPs DEC IN FSI Input side word clock audio framing signal 1 x input sample rate DEC IN SCKI Input side audio bit clock 64 x input sample rate DEC OUT FSI Output side word clock audio framing signal 1 x output sample rate DEC OUT Output side audio bit clock 64 x output sample rate It is possible for the input side of the CS49400 to run at half the sample rate of the output side This is required for DTS 96 24 decoding FLASH DSP AB SERIAL ROM CONTROL CLOCKS ADDRESSES DSP AB SERIAL CONTROL DATA DEC AB gt CRYSTA EPROM DATA DATA DSP C SERIAL CONTROL CLOCKS 49326 DSP C SERIAL CONTROL DATA DEC C amp CLOCKS IN AUDIO DATA 4x2 CHANNEL PCM AUDIO DATA OUT CIRRUS CS49400 DSP BLOCK 6 9 8 Service Manual DSP BOARD The principle DSP in the system consists of two pairs of Analog Device 21065 SHARC
163. 5 DSPD_BMSTR NC5 NC 203 NOS Nc 208 NC GND i BEBRRESESER u138 ZZ CONTRACT lexicon DSPD_OUTI 01730 neat APPROVALS LE DRAWN SCHEM MIC DSP BD MC8 RWH 5 20 02 DSPD CHECKED 5 29 02 SIZE CODE NUMBER REV 060 15389 1 cw 6 3 02 ElLE NAME ISSUED KB 6 3 02 15389 2 6 SHEET 6 OF 10 8 6 5 4 3 2 1 12 15 2004_ 8 52 REVISIONS _ DSPCD D 31 0 5 A3 6 A3 8 B4 m REV DESCRIPTION DRAFTER Q C CHECKER AUTH 1 SHOW DEPOPULATION FOR MIC BD dd SEA 3 3VD PER ECO 041201 00 AF MSJ 12 9 04 12 9 04 __ A 23 0 DSPCD_A0 1 8 5 B3 6 C3 DSBCD Ad 2 VDD1 4 DSPCD 2 su AL VDD2 3 3VD DSPCD_A3 4 2 DSPCD_A4 13 128KX8 DSPCD_A5 14 25 128 M LEE SRAM REM DSPCD A13 23 DSECD_AS M ag DSPC
164. 5456 SHIELD 6 5X1 8X 4 H 1 000 703 14098 LENS 6 36X1 55 MC12 1 000 Video Mechanical Assembly 023 15431 PL VIDEO BD ASSY MC8 B 1 000 023 15432 RCA BD ASSY MC8 B 1 000 023 15433 PL VIDEO OUT BD ASSY MC8 B 1 000 635 15716 SPCR M3X17MM 6MM HEX 1 000 VID RCA TO VIDEO 640 01701 SCRW 4 40X1 4 PNH PH ZN 3 000 VIDEO 640 10498 SCRW M3X6MM PNH PH BZ 2 000 VID RCA TO VIDEO 641 13116 SCRW TAP AB 4X3 8 FH PH BZ 15 000 701 15455 BRACKET VIDEO BD MC8 1 000 Packaging Miscellaneous 022 15306 55 PKG MC8 B 1 000 070 15039 NOTES RELEASE ERRATA MC8 1 000 070 15481 GUIDE USER MC8 B 1 000 460 08345 2 000 730 11459 BOX 21X5X19 LEXICON 1 000 SHIPMENT 730 15286 BOX 17 75X12 125X2 5 1 000 730 15484 21 3 4 19 9 3 4 LEXICON 1 000 INNER BOX 730 15486 BOX 22 1 2X19 3 4X11 BLANK 1 000 OUTER BOX 730 14896 INSERT FOAM ENDCAP 1U MC12B 2 000 730 15487 INSERT FOAM BASE 2 amp 3UX15 1 000 730 15488 INSERT FOAM TOP 2 amp 3UX15 2 000 730 15483 TRAY ACCESSORY MC8 B 1 000 750 15480 REMOTE CONTROL MC8 1 000 Power Cord Options 680 09149 CORD POWER IEC 10A 2M NA SVT 1 000 N AMER 680 08830 CORD POWER IEC 6A 2M EURO 1 000 680 10093 CORD POWER IEC 5A 2M UK 1 000 680 10094 CORD POWER IEC 6A 2M ITALY 1 000 680 10095 CORD POWER IEC 6A 2M SWISS 1 000 680 10096 CORD POWER IEC 6A 2M AUSTRALIA 1 000 680 10097 CORD POWER IEC 6A 2M JAPAN 1 00
165. 5VV J2 i7 2N3904 4 t R6 2 YEL D 4 CVID4 22 R4 Y 1K 57 1 25 5VV 5VV c2 J1 E 2N3904 5 Oo 77 Y R3 uv m 2 YEL 75 0 4 VIDS Y ERU ENCE COPY th 1125 2002 Lexicon Inc sw CON NO BEDFORD 01730 TITLE APPROVALS DATE DRAWN SCHEM VIDEO RCA RWH 1 9 02 RCA OPTICAL DIGITAL INPUTS is CHECKED EcM 1 10 02 SIZE CODE NUMBER 060 15279 o CW 1 10 02 a ISSUED Kap 1 11 02 15279 0 1 sHEET 10F 1 9 8 7 6 4 3 2 1 i 8 6 5 3 2 1 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH IRIENCODER BOARD CONNNECTOR D 5VD A J2 1 2 IR AUXIN 3 AUXRET 4 5 IR DATA 6 SYSTEM 7 2 C3 IR LED 9 10 11 ENCODER 2N3904 12 HOST ACK LED 527 2 C3 14 R26 Q1 777 3K 1 06 1 PANEL
166. 6 3 8 IO_RD S gt 1 23 14 70NS ZA13 9 A13 7 IODX EN 58 3 D7 IO_WR Sone ex IODX EN 59 IODY RDWR e _ 1 C3 ENT 27 WE 25 65 DSP_CS lt 61 MAIN_DRCVR_MCKO MAIN DRCVR MCKO 3 85 10 aces 131 CS xd ZONE DRCVR MCKO ZONE DRCVR SRAM RD 22 7 6 13 7 DB0_CS 53 DBi CS 6 B4 AUDIO AMHZ 14 SND 14146 DB1 C8 78 082 CS ME E 5 A DB2 CS 8 84 77 090 243 164 1 CONTROL_2 ee 2 2 82 CONTROL 3 cee ZA 18 42 TMS STATUS STATUS 4 E 15 TMS STATUS4 9 3 88 AO 1 C3 1 C1 E ZORO 98 1 B5 1 C1 9 250 1 C3 1 C1 2 1 1 B3 3 B8 4 c8 O RST 87 RESET BSY RDY EURO48 F EURO48 F APR AUDIO ___ 1183 EPROMI 1 a RA20 9VD pe FLASH RST c2 15 B2 Bnet 2 4 TMS AUDIO DIN 2 R321 AUDIO DIN ADA 1 83 FLASH_WR RATS B3 RA22 A3 E z NOTES cs RAM B4 AS 1 66 DSP 10 1 83 RA18 B5 DSP IO 5 07 1 1 HAVE WEAK PULLUPS 183 C6 RA19 B6 AG 3 3VD 1032 280 10 6 D7 C7 200 lO 54 DB1 10 1 0 1 1 SLAVE SERIAL MODE C8 701 Bis DA A8 IO 79 DB2 10 7 06 58 255 8 205 DB2 IO 8 06 1 1 0 MASTER SERIAL MODE
167. 6 Decoder Boards overt e piste dea Receipt a eed 6 8 DSP Board te an 6 10 Audio ROUTING i e ec c REM 6 13 Board a au ua Sasa aysa 6 16 MC 8 Analog 6 16 MC 8 Video System Circuit 6 20 CHAPTER Z u ayar negate fan Fa Main Board Assembly ie se o peter Y ue Y eua Y uh 7 1 Memory Board 4444444 7 4 Video RCA Board Assembly nennen entrent rens nnne eene 7 5 Video Out Board Assembly nennen sentent rennen 7 5 DSP Board Assembly ono eR GE Pie HP a RD 7 5 Decoder Board 55 7 6 Switch EED Board Assembly esce tn dt UH DR ed e usaha Qs 7 6 Standby Board nannten nnns 7 6 XLR Board Assembly ati cee eti eade emat 7 7 IR Encoder Board 7 7 MEN sm 7 7 Chassis Assembly rr ende Ri e d Ra Eas 7 8 Mic Board ee e TER IE ea PIER Denis 7 9 Power Supply Assemlbly 7 9 Fan cie nete eene ia AAEE mee nece nda
168. 6 24 02 RWH CW 2 CHANGED PER DCR 020814 00 2 5 REGULATOR 9 5 02 9 9 02 5VD 2 5VD D3 2 5VD 1 4002 1 2937 VOUT GND _ 27 F 1 25 BYPASS CAPACITORS 3 3VD Tie TE thes Toi Tei k m Jus Tes p 26 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 2 5VD Ts Tes Ts Ten Tun C14 1 25 1 25 1 25 1 25 1 25 1 25 1 25 n 3 OAK PARK BEDFORD 01730 TITLE SCHEM DECODER BD MC8 MC12 REGULATOR amp BYPASS CAPS SIZE CODE NUMBER B 060 15319 2 APPROVALS DATE RWH 3 21 02 CHECKED 3 26 02 cw 3 26 02 a ak ISSUED KB 3 26 02 15319 2 4 SHEET 4 4 10 23 2002_14 48 6 5 4 3 2 1 2 1 REVISIONS REV DESCRIPTION DRAFTER Qc CHECKER J1 4 2 2 RED 417 Ts 3 STANDBY LED 4 SW1 D1 777 1 j DIGITAL lt ANALOG __ CHASSIS POWER GROUND GROUND GROUND GROUND 2 LAST REFERENCE DESIGNATORS USED D1 J1 SW1 B D 2 G D I L 2002 Lexicon Inc exicon i NO BEDFORD MA 01730
169. 6 57 C63 64 70 71 77 78 C84 85 C91 92 C1 20 C24 26 31 33 38 40 45 47 52 54 59 61 66 68 73 75 80 82 87 89 23 27 30 34 37 41 44 48 51 55 58 62 65 69 72 76 79 83 86 90 1 20 21 22 01 2 01 2 01 10 RY1 10 J1 10 J11 J1 10 PICK REV 0 PC BOARD SYSTEM ON 04 OVERLOAD D2 4 IR ENC BD J1 TO SW LED BD PICK REV 2 PC BOARD R1 1 2 4 5 1 D1 7 7 DESCRIPTION EFFECT REFERENCE 340 14528 ICSM LIN MC100EL1648 VCO SOIC 1 000 U1 or 340 16132 ICSM LIN MC100EL1648 VCO TSSOP 1 000 U1 510 14836 CONN POST 100X025 HDR 5MC RA 1 000 J1 710 14840 PC BD VCO MC12 1 000 PICK REV 0 PC BOARD 710 16130 PC BD VCO MCLK 1 000 PICK REV 0 BOARD Chassis Assembly Note items are on MC 8 only Aitems are on MC 8B only 120 09621 ADHESIVE THRDLOCK GP 0 003 DSUB JSCKT 490 13144 CONN PLUG 200 4FC RA 12 30G 1 000 REAR PANEL 527 12974 CONN DSUB JSCKT 4 40 187X 25 4 000 DCONN R PANEL 540 02472 PLUG HOLE 3 8 BLK 4 000 541 15458 FOOT 1 97X 43H ABS BLK 4 000 CHASSIS 635 13637 SPCR M3X34MM M F 6MM HEX 2 000 VIDEO BD TO MAIN BD 635 14779 SPCR M3X14MM 6MM HEX 2 000 MEM BD TO CHASSIS DECODER TO CHASSIS 635 15468 SPCR M3X16MM M F 6MM HEX 4 000 DSP BD TO MAIN BD 640 10467 SCRW M3X6MM FH PH BZ 2 000 PS SPT TO CHASSIS 640 10467 SCRW M3X6MM FH PH BZ 2 000 MEM BD TO CHASSIS DECODER TO CHASSIS 640 10498 SCRW M3X6MM PNH PH BZ 2 000 PS SPT T
170. 6 8 A6 12 A7 DIR U94 U61 74VHC273 3 3V IODY0 3 2 1 1D 10 74 245 1001 72D 202 20 A1 8 100 8130 385 1 49 17 IODY1 4D 40 2 82 16 IA IODY4 13 5 5012 z 52 A3 IODY5 14 15 6 4 B4 15 0075 IODY6 1760 6016 7 712 A5 85 14 loDY4 IODY7 1870 79 9 t 8 SPARES 863 100 CONTROL_3 11180 80 7 90 B7 12 100 6 2 1 5 R422 lt R423 lt R424 lt R425 lt R426 lt R427 lt R428 lt R429 11 IODY7 O CLR 5220 5220 5220 5220 5220 5220 220 220 J47 A8 8 5VD GRN GRN 2 D1 2 D3 3 D7 5 A7 6 A7 7 A6 8 A6 i Usa 47 053 AL 055 2 GRN i 195 y YEL yy YEL YE D57 059 74VHC04 5V a D52 7 054 2 056 27 058 3 3VD 3 3VD 3 3VD 1 088 A 4 74VHC04 5V 7 5 6 NC 046 16 54 lt R408 74VHC04 5V 4i 1 914 14 10 74VHCT541 17 2 NC 1MHZ 052 NOD 2 18 1 t 6 M B1 4 C4 5C RST 51_ Rpo 2 yt 18 088 3 03 RB1 7 Y2 1 IODY2 DATA R409 RA0 RB2 9 5 A3 15 74VHC04 5V 12 82 amp R DATA IRAI 7 5 Y4 19 eats 8 NC 1K TIMERINT 2 RA2 RBA 44 7 Y5 43 055 Te zu PIC_CONFIG 3 RAS 5 12 86 Y6 15 105 088 2 3 5 RTCC RB6 13 9 AT Y 1 IODY7 74VHC04 5V 74VHC04 5V URBI TE 5 05 47 1 48 8 13 12 11 10 19126 U92 U88 U88
171. 6 NO 3 He BEDFORD MA 01730 22135 TITLE APPROVALS DATE RFRONT _ SCHEM MAIN BD MC4 MC8 M 21 C8 DRAWN RwH 2 15 02 100 DACS CHECKED 3 29 02 SIZE CODE NUMBER REV B 060 15259 4 E10 CW 4 3 00 FILENAME ISSUED kaB 4 3 02 15259 6 17 SHEET 17 OF 23 8 7 6 5 4 2 1 10 19 2004_ 8 58 8 7 6 5 4 3 2 1 REVISIONS SVAD REV DESCRIPTION DRAFTER 4 CHECKER AUTH CENTER 8 SUB D A CONVERSION 1 CHANGED PER DCR 020430 00 Mise FB14 KB KB 6 4 02 6 26 02 C153 C151 C149 F RWH CW g v TNR 2 CHANGED PER DCR 020731 00 BE S 2 47 47 330 6 3 8 5 02 8 14 02 152 C150 C148 OdBFS 8Vrms 3 CHANGED PER DCR 020827 00 PAIN OdBFS 1 7Vrms Dayan KB KB 4125 1125 1125 15 17 A 9 12 02 9 12 02 2 sZ v v 13 102 RWH CW 106 Rus ADG451 4 UPDATED FOR MC4 PER DCR 040922 00 4395 0 AT AT gt i 121 R86 280 5 10 CNTR_DACOUT S 18
172. 67 on the main board on page 2 of the schematics The FPGA is used to program the other DAR FPGA the Audio FPGA and the Analog FPGA If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix 5 9 8 Service Manual DSP FPGA Test The DSP test loads and verifies the programming of the XCS05 VQ100 U7 on the DSP board revision 1 and page 8 of the schematics The Audio FPGA must be functioning since it is used to program the DSP If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Decoder FPGA Test The Decoder FPGA test loads and verifies the programming of the XCSO5XL VQ100 U4 on the decoder board and page 2 of the schematics The Audio FPGA must be functioning since it is used to program the Decoder FPGA If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Crystal 49400 Test This test verifies that the Crystal 49400 U2 on the decoder board and page 3 of the schematics can communicate with the Host Z180 processor through the Audio FPGA If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix SHARC SDRAM Test This test verifies th
173. 70 RA21 RXS CTS1 TXS 07 81 20 2 UNLESS OTHERWISE INDICATED RESISTORS 5 CKS 58 RA20 CKS NG 2 15 84 ats 80 __ 9 TEST ZA14 551442 Raig 79 3 UNLESS OTHERWISE INDICATED CAPACITORS GNDGNDGNDGND 2 13 33 113 RA17 15 8394 4R393 4R392 R395 8396 lt 2397 aa ZA12 77 Rate 72 6 4 1 ANALOG CHASSIS POWER S10K OK OK lt U84 55 7 71 __ 15 22 15 77 GROUND GROUND GROUND GROUND 2 6 25 5 XX XX DENOTES SHEET NUMBER SECTOR 744 15 5 MEM RD 4 MEM_RD 2 88 6 LAST REFERENCE DESIGNATORS USED C415 D61 E34 FB35 39 4 EPROM 63 2 C8 E 55 EPROM 69 FLASHO gt 2 56 J48 L1 Q9 R440 RY5 U98 W3 2 1 14 2 MEM SPARE 52 2 88 7 COMPONENTS MARKED WITH ARE NOT INSTALLED 2 0 37 1 FLASH WR 46 LASH WR 2 2 88 A0 FLASH RST 8 COMPONENTS MARKED WITH ARE NOT INSTALLED BSY RDY 10 BsY RDY RD 9 2 23 ZMREQ PROGRAM 25 O PROGRAM 2 D6 12 47 gt ZRD 67 ZIORQ Io CCLK 17 DIN 2 04 ZWRI 54 ANE IO DIN 2 04 DOCUMENT CONTROL BLOCK 060 15259 3 5 PWR_RST i PWR RST VIDEO RST 32 VIDEO RST 12 D5 SHEET REVISION TITLE 45VD DBA BST 31 R308 1 DBA RST 21 A7
174. 740 08556 LABEL GROUND SYMBOL O 5 DIA 1 000 PS SUPPORT 740 15745 LABEL FUSE CAUTION 2 5A 250V 1 000 PS SUPPORT 750 15466 PWR SUP 5V 15V 60W 1 000 Fan Assembly 410 14851 FAN 40X40X10MM 12VDC 3 43CFM 1 000 525 12536 CONN CONT CRIMP 22 26AWG AMP 2 000 CRIMP CONN TO WIRES 527 12537 CONN HSG CRIMP 100X2 POL LK 1 000 Front Panel Mechanical Assembly 550 15459 KNOB 1 75X 91H 6MM ALUM PEWTER 1 000 ENCODER 702 15440 PANEL FRONT MC8 1 000 023 14068 BD ASSY MC12 B 1 000 023 15437 PL SW LED BD ASSY MC8 B 1 000 023 15438 PL STANDBY ASSY MC8 B 1 000 430 13143 DISPLAY VF 20X2 CHAR 5X8DOT 1 000 530 09382 CLIP WIRE HRNS 15DIA ADH 1 000 FP SHIELD CENTER 550 13633 BUTTON 276X 572 BLK 2 000 550 13634 BUTTON 276X 572 BLK W LTPIPE 20 000 7 9 DESCRIPTION QTY EFFECT INACT REFERENCE 635 14526 SPCR M3CLX6MM 6MMRD 1 000 IR ENC BD 640 01841 SCRW 2 56X1 4 PNH PH ZN 4 000 DISPLAY 640 10495 SCRW M3X12MM PNH PH ZN 1 000 640 10498 SCRW M3X6MM PNH PH BZ 9 000 SHIELD 640 10498 SCRW M3X6MM PNH PH BZ 6 000 SW LED BD 640 10498 SCRW M3X6MM PNH PH BZ 2 000 640 15476 SCRW M4X8MM PNH PH ZN 2 000 SPT BRKT TO FP 680 14693 CABLE 100 PLUG SCKT 2X7C 10 5 1 000 DSPLY TO SW LED J1 SOLDER TO DSPLY 680 14854 CABLE 079 SCKT SCKT 4C 4 CMP 1 000 STANDBY BD J1 TO MAIN BD 43 701 15454 BRACKET SUPPORT COVER MC8 1 000 701 1
175. 80 48 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 5 17 Internal 96000 Analog ANLG MAIN IN5 96K TO ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 40 05 0 15 0 50 None 100k 10 gt 500 1 2 5 17 Internal 96000 Analog MAIN IN5 96K ANLG MAIN OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k lt 10 gt 500k 1 2 5 17 Internal 96000 Analog ANLG MAIN IN5 96K TO ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 100k lt 10 gt 22k i 2 5 17 Internal 96000 Analog ANLG MAIN IN5 96K TO ANLG MAIN OUT SNR 3 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100 lt 10 gt 22k 1 2 5 17 n a Internal 96000 Analog Tests Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Name Note Left Right Freq Hz Z out Unbal Float Level Measure Limit Limit Filter Imp Band Bin A Out B Out ANLG_MAIN_IN6_96K_TO_A
176. 88 9 27 04 9 27 04 2 va 18 1 5 76K 1 1 2 CENTER_DAC_MCKI 3 17 L C144 C87 GND 4 82 s 19 D8 20 D8 21 B3 MAIN_DAC_RST 45 BD AOUTL 23 MAIN_DAC_SCKI0 5 22 R85 4 21 4 22 17 08 DAC AOUTL oe 15V 1 24K 330 6 3 280 4 C1 4 B4 e CENTER_DAC_SDI 28 196 1 R84 4 C1 4 C2 17 C8 MAIN DAC 7 capi 27 499K R82 A 4 A C4 t9 C8 20 C8 s MAIN DAC CS 26 AA 13 12 ADG451 p VDD capo pig sv 13 82 CNTR_DIR_IN 6 5 DH R118 77 4 C4 17 C8 19 C8 20 C8 IN DAC 10 24 GND 2120 C108 8 4 C4 17 C8 19 C8 20 C8 11 AOUTR 21 5 MAIN DACOUT SEL 4 5 U9 121k R91 280 19 C4 20 C4 21 B3 412 piro 20 196 5762 1 19 C4 20 C4 21 83 MAIN_DIRECT i 224 1 2 E 13 19 C146 L 145 C89 4 pi AGND s F 1500 220PF T 14 pip 18 x 45 15V 5 M R121 C109 R89 86 18 4 4 1 19 147 AA M Jr 18 349 66484 121K 330 6 3 280 220 U19 ups 1 1 RBB qui SUB_DACOUT ivi 4 8 18 A8 499 16 1 GND 6 49K Y 15V 15V 5VAD d 13 12 ADGA451 VCC VDD 14 82 SUB_DIR_IN
177. 9 4 cw 413102 NAME ISSUED kaB 4 3 02 15259 6 2 sHEET 2 OF 23 8 6 5 4 3 2 1 10 19 2004 8 58 8 7 6 5 4 3 2 1 REVISIONS DRAFTER C _ _ IODX 7 0 REV DESCRIPTION 21 86 RWH CW IODY 7 0 1 CHANGED PER DCR 020430 00 5 16 02 6 24 02 4 D7 12 A6 KB KB ZD 7 0 1 D3 2 D6 5 A7 6 B6 7 A6 8 A6 B 0 642 6 26 02 2 CHANGED PER DCR 020731 00 3 02 gt 74VHC273 3 3V 8502 8 14 02 TAVHOT246 IODY0 3 2 3 020827 00 3142102 1 47 72D 296 7 B4 2 B2 16 10578 230 306 DSP R 1 8 B4 9 12 02 9 12 02 A3 4D 40 5 7 RWH CW A 28715 IODY4 13 5 5012 PIC_RST B C8 4 UPDATED FOR 4 PER DCR 040922 00 apande cionada 14 IODX4 IODY5 14 15 REMOTE PWRENO A5 5 6D 60 11 7 AT AT 13 IODX5 IODY6 17 16 REMOTE_PWREN1 A6 86 gt 16770 EAN ON 11 07 9 27 04 9 27 04 IODX7 CONTROL 2 11 8D 12 08 j55 BS espe u TOLK 2 C3 RD WR oG 2 D1 2 D3 3 C7 5 A7 6 A7 7 A
178. 95 PANEL ACCESS MC12 1 000 CHASSIS BOTTOM 702 15457 PANEL OPTION BLANK MC8 2 000 REAR PANEL 720 13632 PAD FOOT 1 438DIA 4 000 1U CHASSIS BOTTOM 720 15256 TAPE COPPER 1 2 W EMBOSSED PSA 16 500 APPLY TO R PNL TOP 740 14888 LABEL LIC PAT WARN MC12 1 000 MC8 2U CHASSIS 7 8 BOTTOM MC8B 1U CHASSIS BOTTOM DESCRIPTION QTY EFFECT REFERENCE Mic Board Assembly 202 09795 RESSM RO 5 1 10W 2 2K OHM 8 00 R41 50 52 R14 16 28 30 39 202 09871 RESSM RO 5 1 10W 1K OHM 1 00 R17 202 10426 RESSM RO 5 1 10W 15K OHM 4 00 R27 38 49 60 202 10598 RESSM RO 5 1 10W 330 OHM 4 00 R15 29 40 51 202 11073 RESSM RO 5 1 4W 270 OHM 4 00 R26 37 48 59 203 11077 RESSM RO 1 1 10W 237 OHM 1 00 R20 203 11980 RESSM THIN 1 1 10W 10 0K OHM 16 00 R18 19 21 22 31 3 R42 45 53 56 203 12481 RESSM RO 1 1 10W 1 50K OHM 1 00 R23 203 12719 RESSM THIN 1 1 10W 2 00K OHM 4 00 R25 36 47 58 203 12723 RESSM THIN 1 1 10W 102 OHM 4 00 R24 35 46 57 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 4 00 C8 14 20 28 240 11827 CAPSM ELEC 10uF 16V 20 12 00 C11 13 17 19 23 2 C31 33 240 13216 CAPSM ELEC 22uF 16V 20 1 00 C7 245 10562 CAPSM CER 150pF 50V COG 10 8 00 34 35 41 42 46 4 51 52 45 10976 CAPSM CER 47pF 50V COG 5 12 00 C38 40 43 45 48 5 245 12485 CAPSM CER 1uF 25V Z5U 20 13 00 9 10 15 16 21 22 30 36 37 56 58 270 11545 FERRITESM CHIP 600 OHM 0805 9 00 FB3 10 13 300 11599 DIODESM GP 1N4002 MELF 2 00 D9 10 340 10552 ICSM LIN
179. A 100 06 ao 10 25 PASS THRU 5 133 BD gt 100K 13 A5 21 D3 e ANLG_4_5 DIR ES RSUR DIR IN 2084 R183 15V Y 167 8 th 04 10 25 BAV99 CONTRACT s R129 NO 3 lt 100 15 13 A5 21 C3 ANLG_7_8_DIR_IN 01730 TITLE APPROVALS DATE 5 184 BD MC4 MC8 7 100K DRAWN RwH 2 15 02 RIGHT ANALOG INPUT MUXES lt CHECKED 3 29 02 SIZE CODE NUMBER REV 15V Z 060 15259 5 cw 4 3002 NAME ISSUED kaB 4 3 02 15259 6 14 SHEET 14 OF 23 8 7 5 4 3 2 1 10 19 2004_ 9 04 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 3 3VA 7 RWH Cw 1 CHANGED PER DCR 020430 00 6 4 02 6 26 02 RWH CW 2 CHANGED PER DCR 020731 00 3402 5 02 8 5 02 8 14 02 o RHS 3 CHANGED PER DCR 020827 00 anaes PAIN KB KB e T MIC INPUT CONNECTOR 94202 94202 RWH CW we a GRN 4 UPDATED FOR MC4 PER DCR 040922 00 323 04 x D21 D22 AT AT MIC 3 5 9 27104 9 27 04 21 03
180. AIN BD MC4 MC8 4 5 U40 gt 100K RWH 21502 LEFT ANALOG INPUT MUXES y CHECKED cy 3 29 02 SIZE CODE NUMBER REV Aly 060 15259 5 cw 413102 ISSUED kaB 4 3 02 15259 6 13 SHEET 13 23 8 7 5 4 3 2 1 10 19 2004_8 58 8 7 5 4 3 2 1 REVISIONS Pa REV DESCRIPTION DRAFTER ae MAIN SOURCE SELECT RIGHT 15V RIGHT ANALOG INPUTS je OdBFS 4 0Vrms 15V 45V 1 CHANGED PER DCR 020430 00 4 13 14 6 4 02 6 26 02 R158 209 06408 RWH cw 1 ps T GND 2 CHANGED PER DCR 020731 00 54102 5 02 3 4 100 D18 10 25 1 CBV KB 1AW 99 9 82 2 OVIS 8 5 02 8 14 02 4 53 15 T RWH CW C207 5 R157 A R187 RIGHT MAIN IN 3 CHANGED PER DCR 020827 00 EE 150 S 100K 12 D A 15 88 1195 TOOR 56 9 12 02 9 12 02 1057 1 R188 120 HEY L 9 5 L R189 100 4 121 28 030213 00 4 A0 1 A2 lt 100K Y 02 19 03 02 20 03 I 1 16 15 2 U33 RWH CW p C203 5 UPDATED FOR MC4 PER DC
181. AL 5 84 12 U12 E 5 A4 x i SECAM EN Z od E 13 9 13 b o GND QHH 1 0G GNpQHH 8 U36 8 lt gt lt 5VV 5VV 4 4 16 16 08 T SER QB i amp QC NE i1 9 10 SRCLK 23 SRCLK 0 QD QE 5 2 87 8 04 VIDEO_REG 12 5 A8 8 D4 OSD_CS 12 VIDEO_RST RoR I NC 2 DAS 13 l OH 8 04 yp QHH 8 037 7 57 1 74 08 3 3 MSVID SELO 73020 4 74HC08 2 C 5 8 SEU jag 020 9 74HC08 10 8 SEL2 73020 1 74HC08 2793 ZSVID SELO 73012 4 74HC08 5 9 ZSVID SEL CONTRACT T U12 NO exicon 3 OAK PARK 9 01730 fo 08 ZSVID_SEL2 amp TITLE 4 APPROVALS DATE U12 SCHEM VIDEO BD 4 29 13 02 CONTROL REGISTERS CHECKED 3 48 02 SZE CODE NUMBER REV Qc 060 15269 2 3902 ISSUED 3 19 02 15269 4 7 SHEET 7 OF 8 8 7 6 5 4 2 1 gt 10 19 2004_8 34
182. AO VDD2 R78 DSPAB A3 414 DSPD_OUTO 270 J PSEC 1 Agee _ 12NS 6 8 7 DSPD_OUT1 4181 1740 5 15 sean 6 A3 8 B7 2 RED A6 DSPC OUTO 6 14 5 A7 16 5 3 8 87 R8 z 2 gt DSPC 8 12 amp DSPAB A8 17 5 8 7 4 2 DSPC LED 1 DSPAB A9 18 8 6 024 270 08 A9 5 1 4W E DSPAB_A10 19 9 00 7 025 U6 DSPAB_A11 20 10 01 10 DSPAB 026 DSPAB_A12 21 15 02 11 DSPAB_D27 77 77 A13 29 14 03 22 028 14 30 14 Ds 23 DSPAB 029 15 31 26 030 DSPAB_A16 32 pe 27 DSPAB 031 NO exicon 3 OAK PARK DSPAB SRAM CS DSPAB SRAM CS 5 BEDFORDIMA 01740 2 D1 2 C3 3 C3 gt DSPAB WR 120E TITLE _ QW APPROVALS DATE DSPAB_RD DSPAB RD 248 DEAW SCHEM MIC DSP BD MC8 RWH 5 2002 DSPAB EXT 9 25 881 CHECKED 5 29 02 SIZE CODE NUMBER REV VSS2 8 060 15389 1 010 CW 6 3 02 FLE NAME ISSUED KB 6 3 02 15389 2 4 SHEET 4 OF 10 8 7 4 2 1 12 15 2004_8 52 REVISIONS REV DESCRIPTION DRAFTER Q C CHECKER AUTH RWH Cw 1 SHOW DEPOPULATION FOR MIC BD 12 7 04 12 14 04 PER ECO 041201 00 AF MSJ 12 9 04 12 9 04 3 3VD MASTER IDO HIGH 121 LOW SLAVE IDO LOW
183. BSY RDY B1 1 EPROM 22 7 2 RA21 B2 15 2 FLASH_RST 16 ND ZA7 RA22 B3 RA16 FLASH WR 4 4 4 FLASH0 U3 ZA9 5 18 5 NC ZA10 AG 6 19 C6 MEM RD ZA11 204 7 200 C7 5VD 5VD ZA12 8 3 3VD 205 8 201 C8 A A ZA13 AQ 1 706 9 202 9 FLASH ZA14 10 207 B10 ZD3 C10 240 160 44 4 200 11 11 ZAG ZA0 15 A 23 i 701 C A12 4 12 12 ZA1 ZA2 14 A2 702 13 B13 ZA8 C13 ZA2 13 A3 Tas dos 703 A14 ZA12 B14 ZAQ C14 ZA3 ZA4 10 4 5 704 15 2 13 15 2 10 15 ZA4 2 5 _ 9 705 16 2 14 B16 ZA11 C16 745 746 8 706 2477 707 J1 J1 J1 zas 6 EPROM RD 249 __ 2 8 BSYIRDY RD 2 10 4 70NS BSY RDY 10 FLASH_RST ZAM RST 11 FLASH_WR ZA12 42 17 200 WR 41 12 Doa 261 gFLASH0 F0 A13 01 2 14 401411 02119 202 5VD SP RAIS 391 4 92 20 203 RA16 381 42 4124 204 371 12 65 25 205 RATE 361 17 5 26 206 RA19 35 27 207 NOTES 32 A19 D7 10K A20 28 1 UNLESS OTHERWISE INDICATED CAPACITORS FLASHO 43 MEM_RD 29 2 gt DIGITAL ANALOG 1 CHASSIS POWER FLASH_WR 1 GROUND GROUND GROUND GROUND 2
184. C 8 balanced only stereo connector 1 S PDIF coaxial RCA connector Main Zone Audio Performance Conversion D A Conversion Frequency Response THD Noise Dynamic Range Signal to Noise Ratio Input Sensitivity Input Impedance Output Level Output Impedance 24 bit 96kHz dual bit A gt architecture 24 bit 44 1 to 192kHz multi bit A gt architecture 10Hz to 20kHz 0 05dB 0 1dB 0 5dB at 40kHz reference 1kHz Below 0 008 at 1kHz maximum output level 108dB minimum 22kHz bandwidth 108dB minimum 22kHz bandwidth 200mVrms 2Vrms for maximum output level at 0dB input gain 100 in parallel with 150pF 150mVrms typical 6Vrms maximum RCA connectors 300mVrms typical 12Vrms maximum XLR connectors MC 8 Balanced only Maximum value with full scale input signal and volume at 12dB 1000 in parallel with 150pF RCA connectors 500 in parallel with 150pF XLR connectors MC 8 Balanced only 3 1 8 Service Manual Zone 2 and Audio Performance D A Conversion Frequency Response THD Noise Dynamic Range Signal to Noise Ratio Input Sensitivity Input Impedance Output Level Output Impedance 24 bit 44 1 to 192kHz multi bit A gt architecture 10Hz to 20kHz 0 1dB 0 25dB 0 75dB at 40kHz reference 1kHz Below 0 005 at 1kHz maximum output level 103dB minimum 108dB typical 22kHz bandwidth 103dB minimum 108dB typical 22kHz bandwidth 200mVrms 4Vrms for maximum output level 1
185. CODE NUMBER REV 060 15259 4 E4 4 3 02 _ FLENAWE ISSUED kaB 4 3 02 15259 6 20 SHEET 20 OF 23 8 7 6 5 4 3 2 1 10 19 2004_8 58 8 7 6 5 4 3 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 3 3VD 3 6 4 02 6 26 02 h RWH CW R251 FB24 2 CHANGED PER DCR 020731 00 3402 5 02 A A ri 3 CBV KB pos 8 5 02 8 14 02 RWH CW 43 3VA L R250 3 CHANGED PER DCR 020827 00 lt 330 9 12 02 9 12 02 74VHC273 ay RWH CW 20 D23 4 UPDATED FOR MC4 PER DCR 040922 00 IODXO 3 VCe 2 1 R22 MAINOUTS_MUTE 9 24 04 10 14 04 IODX1 40 105 R249 ExPOUTS 18 48 ODK 2 20 292 NG 21 88 9 27 04 9 27 04 IODX3 8 30 ad 9 8 R1 ZONEOUT MUTE ging TO XLR BD MC 8B 100 4 i3 8221 MIC_SELO ian HD7 IODX5 14 15 8220 SEL1 gt 15 07 5VD 15V 19 aD 19 ANLG_4_5_DIR_IN VIA ANLG_REGO_CS 1 m 4
186. C_CS MAIN_MCKO COAXS sg COAX2 ZONE OUT VC C8 118 SONE VC CK 16 A8 COAX3 TCK_ZONE_OUT_VC_CLK 16 B8 MAIN DRCVR FSI 59 114 2 COAX4 ZONE_OUT_VC_DATA AA 16 B8 FS OPTO 4 1 OPTO1 60 115 ZONE DAC CCLK MAIN DRCVR SCKI 12 C3 B OPTO1 ZONE DAC CCLK 16 C8 MDRX_SCKI MAN DRCVR SDO MAIN 800 2 61 116 ZONE CDATA MDRX SDO 62 2 ZONE DAC CDATA 117 ZONE DAC GS 16 8 a 83 ZONE CS DAC 16 C8 OPTO4 MDAC MAIN DAC FSI 4MHZ led OSD 3 C8 4 B1 MDAC MAIN DAC SCKI OSD 67 4 1 12 05 MDAC MAIN_DAC_MCKI VIDEO REG VIDEO SCLK 4 C1 12 D5 SDI DAC 501 VIDEO_CCLK 69 VIDEO DATA 4 B1 12 D5 CDAC SDI CENTER_DAC_SDI VIDEO_CDATA 4 B1 12 D5 R348 56 MAIN DAC FSI0 SDAC SDI SIDE_DAC_SDI 2 83 4 01 MAIN 2 MAIN_MCKO MAIN DRCVR FSI 3 MAIN DRCVR FSI 4 D1 9 D7 R347 56 MAIN DAC FSI1 4 gt H gt 15 82 800 500 MAIN DRCVR_SCKI 4 MAINCDRCVR NRZI gt 4 01 9 07 R346 56 MAIN_DAC_SCKI0 L E MDAC FSIO MAIN DAC 4 D1 9 D4 MAIN 6 MAIN DRCVR 500 MAIN DRCVR MAIN ADC FET E 9 07 A 4 C1 17 D8 18 D8 FSM F
187. D A9 18 6 DSPCD DO DSPCD A12 22 A9 DO BAO DSPCD A10 19 7 DSPCD D1 26 DSPCD D81 DSPCD 11 20 10 DI 10 DSPCD D2 DSPCD SDA10 24 54 030 A11 D2 5 C1 5 D3 6 D3 A10 0030 DSPCD_A12 21 DSPCD_D3 DSPCD_A9 66 53 029 12 03 9 0029 DSPCD_A13 29 22 DSPCD_D4 DSPCD A8 65 51 _ _ 028 A13 04 0028 DSPCD 14 30 23 05 DSPCD A7 64 50 _ 027 A14 05 AT DQ27 DSPCD A15 31 26 DSPCD 06 DSPCD A6 6344 0026 48 DSPCD 026 DSPCD AlS 32 A15 06 57 DSBCD D DSPCD A5 62 5 8 025 A16 07 DSPCD A4 61 49 45 DSPCD 024 BSEEB SRAM CSI DSPCD A3 60 42 _ 023 0023 DSPCD_WR 12 DSPCD A2 27 gt 0022140 DSPCD_D22 DSECD BD 10 DSPCD 2644 21 39 021 E DSPCD_A0 25 37 020 3 3VD 0 2 32 0920 36 DSPCD_D19 9 0019 34 DSPCD D18 25 552 5 C1 5 D3 6 D3 SP CD DOM DQ18 2 BSPCD D17 8 DQ17 _ gt U3 Dole 31 DSPCD D16 018185 15 DSPCD_A0 001483 DSPCD_D14 DSPCD A1 2 24 EDD DS DSPCD RAS DO13 82 DSPCD DSPCD A2 3 14 S CSB DSPCD_CAS 0012 80 DSPCD D12 DSPCD_A3 4 DSPCD_SDWE 19 DSPCD D11 DSPCD_A4 18 4 128KX8 SCA ECS 6 D3 _DSPCD_ 5 77 DSPCD D10 DSPCD 5 14 128 5 63 bag 76 _DSPCD_D9 DSPCD_A6 15 SRAM BIC 5 D3 6 D3 DSPCD SDCKE 74 DSPCD 08 DSPCD A7 16 9 BICA B D36 D3
188. D1 P 1 C3 DB CS A 1 B3 2 D 1 B O cs 1 B3 2 C4 S RST DB 4MHZ 3 C1 3 C7 DEC AB SCDOUT DB 4MHZ 35 DEC C SCDOUT DEC AB SCDOUT 3 C 1 3 C 8 Ig DEC_C_SCDOUT DEC AB ABOOT IRQ 3 C1 3 C8 F AB DEC C ABOOT IRQ 8 C1 3 C8 a DEC C ABOOT IRQ 3 C1 3 C8 m DEC_HINBSY 57 DEC HINBSY 3 C3 S EC NVCS 42 DEC NV CS DEC A0 27 DEC A 19 0 DECAL Hi DEC at 3 D3 DEC A19 DEC GPIO20 39 3 C1 3 A3 DEC GPIO20 3 C1 3 A3 21 40 DEC GPIO 1 3 C1 3 C3 m DEC_NVWE 41 DEC_CLK 48 3 C1 3 A3 p Yd _ 79 1 D3 2 C 1 B DB FSI 80 1 C3 2 C 4 B M DB_FSI 1 C3 DB SDI DEC SDOO DB SDI 3 81 3 83 gt DEC 000 5001 3 81 3 83 001 5002 3 81 3 83 gt 002 _ 003 DECODER DEC_NVWE_DLY IO_DIN 3 DOUT DEC RST s 3 D1 3 D8 8832 DEC_AB_CS gt 3 C1 3 C8 33 DEC DEC SCLKS AB SCDIM gt 3 C1 3 C8 DEC AB SCDI gt 3 1 3 8 53 DEC C CS DEC ERA 3 1 3 08 54 DEC C
189. DATA STATUS DATA FPGA le DSP STATUS RD DSP STATUS WR 4 HOST DSP COMUNICATIONS SHARC DSP WRITES DATA TO HOST BLOCK 6 12 Lexicon AUDIO ROUTING Digital Audio Input Path Digital Audio can be either PCM 2 channel data or one of the compressed data formats It enters the unit one the digital input connectors that are connected to the Audio FPGA The FPGA functions as mux and routes the output NRZ Non Return to Zero data of the connector selected by the user to the two Digital Receivers Main and Zone These receivers lock to the incoming signal and extract a 2 channel PCM audio signal that is returned to the Audio FPGA Main Audio Data Path The Main Audio Data Path is as follows IN streams the Audio 9 These four 2 channel streams are sent to the Analog board as MAIN_DAC 0 4 _SDI Output of the Main Digital Receiver and the Main ADC to the Audio FPGA Output of the Audio FPGA to the Crystal 49400 Decoder on the Decoder Board Daughter Board 0 Four 2 channel outputs from the Crystal 49400 Decoder back to the Audio FPGA The four 2 channel streams are packed into a single octal data stream in the Audio FPGA The output of the octal packer is sent to SHARC A on the DSP Board The octal output of SHARC B is sent to the input of Sharc C Two octal outputs of SHARC D are sent back to the Audio FPGA on the Main board The two o
190. DB0_AUDIO8 A23 22 gt DB0_AUDIO 4MHZ 22 E C21 e DB0 AUDIO DBO A13 A21 2 20 12 20 1 19 A11 19 1 18 10 18 4 17 A17 A7 C16 A6 A16 A5 C15 ZA 15 0 TAVHCT244 1 D4 2 D8 4 D7 5 C7 7 C6 8 C6 12 A6 15 0 y 9 5 DB0_A 13 0 DBO A4 A Y2L DB AI 2 A14 IO RD 17 Y3 3 2080 C13 2 D1 2 D3 4 D8 5 C7 7 C6 8 B6 0 y DBO 0 1 C12 u68 ZDBO RD A12 74VHCT244 11 4 2 D1 2 D3 4 C8 5 87 7 86 8 86 1 2 1 Y1 18 ZDBO WR ZDB0_WR 2 E 4 6 As 14 A2 080 AUDIO9 A10 33 12 080 A C9 1A 080 AUDIO10 A9 36 2080 D T7 0 ZDBO C8 968 2080 01 TAVHCT244 d 208002 C7 2 v1 18 DB0_A6 208003 A7 4 16 8 gaz 2 16 7080 04 C6 2580 05 6 8 12 12 Sm y 2080 D6 C5 2580 67 5 67 C4 244 AUDIO SPO 4 y 9 C3 13 7 11 A3 e 15 4 v 5 080 9 C2 WES 17 13 3 DBOAT CS A2 19 1 7 Nee DBO RST 1 EURO64 F 74VHCT245 20 7 0 1 D3 2 D6 3 D7 5 A7 7 A6 8 A6 20 200 2 1 18 2080 00 3142 2 1 5 A3 83 19 5 15 645 65 13 8613 SA 0_ 5 19 88 RD WR 2 D1 2 D3 3 D7 3 C7 5 A7 7 A6 8 A6 12 7 DIR U74 DBO_CS __
191. DE NUMBER REV At B 060 15389 1 cw 6 3 02 NAME ISSUED KB 6 3 02 15389 2 10 SHEET 10 10 7 6 5 4 3 2 1 12 15 2004_8 52 2 1 2 1 25 1 2 3 OUT VREF AGC GND1 GND2 C1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 4 DIGITAL ANALOG CHASSIS POWER 7 GROUND 57 GROUND GROUND GROUND 5 LAST REFERENCE DESIGNATORS USED C5 D1 FB1 J1 L1 R1 Ut ENCE COPY 2003 Lexicon Inc CONTRACT Xi n CO BEDFORD MA 01730 APPROVALS pate DRAWN 3 3 03 SCHEM VCO BD MCLK CHECKED 3 5 03 SEE CODE NUMBER REV Q C 060 16139 0 cw 3 7 03 FILENAME ISSUED KAB 3 11 03 16139 0 1 SHEET 1 OF 1 2 1 3 18 2003_9 15 Specialty Group 3 Oak Park 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070 17536 Rev 0
192. DIGITAL 74VHCT138 SOIC 1 000 U6 430 13639 LEDSM BLU 30MCB AX ZBEND 2 5MM 8 000 D5 8 13 16 430 13888 LEDSM RED 60MCD AX ZBEND 2 5MM 2 000 D20 21 430 14527 LEDSM SYEL 250MCD AX ZBEND 2 5 9 000 D1 4 9 12 22 453 13899 SWSM PBM 1P1T 6 2MMSQ 200GF 21 000 SW1 21 510 13145 CONN POST 100 HDR 2X7MCG LP 2 000 J1 2 680 14083 CABLE 100 PLUG SCKT 2X13C 2 L 000 J3 710 15280 PC BD SW LED MC8 1 000 PICK REV 1 PC BOARD Standby Board Assembly 430 13888 LEDSM RED 60MCD AX ZBEND 2 5MM 1 000 D1 453 13899 SWSM PBM 1P1T 6 2MMSQ 200GF 1 000 SW1 510 10546 CONN POST 079 HDR 4MC 1 000 J1 710 15320 PC BD STANDBY MC8 1 000 PICK REV 0 PC BOARD 7 6 QTY EFFECT INACT REFERENCE XLR Board Assembly 202 10585 RESSM RO 5 1 4W 51 OHM 202 10943 RESSM RO 5 1 10W 22K OHM 202 10948 RESSM RO 5 1 10W 390 OHM 203 12720 RESSM THIN 1 1 10W 2 94K OHM 203 13132 RESSM THIN 1 1 10W 3 01K OHM 240 13642 CAP ELEC 47uF 25V RAD NPOL 6D 240 13803 CAP ELEC 560uF 35V RAD LOW ESR 245 10562 CAPSM CER 150pF 50V COG 10 245 10587 CAPSM CER 18pF 50V COG 10 245 12485 CAPSM CER 1uF 25V Z5U 20 270 00779 FERRITE BEAD 270 06671 FERRITE CHOKE 2 5 TURN 300 11599 DIODESM GP 1N4002 MELF 310 10566 TRANSISTORSM 2N4401 SOT23 340 12936 ICSM LIN OPA2134 DU OP AMP SO8 410 11639 RELAY 2P2T DIP 5V HI SENS 510 10881 CONN XLR 3MC PCRA SMALL 510 14890 CONN POST 100 HDR 2X17MCG LK 620 12428 LUG 4 INT STAR XLR GND 710 15340 PC BD XLR MC8B
193. DIOS DB0_AUDIO10 30 DBO_AUDIOS DBO AUDIOS 38 AUDIO 4MHZ Lo Hun DBO AUDIO SPO 34 080 AUDIO10 DBO_AUDIO_4MHz lt E 6 C7 U58 6 C7 AUDIO SPO DB1_AUDIO 10 0 3 4 B4 7 D5 lt DBI AUDIO 10 0 DB AUDIOZ 102 DB1_AUDIO2 DB1_AUDIOO 2 5 4 B7 7 D5 _13 12__ DB1 AUDIOG DB1 AUDIO1 5 DB1_AUDIO7 147 151 5 DB1_AUDIO3 U58 DB1_AUDIO8 146 DB1 AUDIO DB1 AUDIOS 455 8 DB1 AUDIO4 AUDIOS 142 DB1_AUDIO8 DB1_AUDIO4 71 5 5 081 AUDIOS 081 AUDIO10 141 DB1 AUDIO9 DB1 AUDIOS 145 8 E DB1 AUDIO 4MHZ NOTES 13g DB1_AUDIO10 DB1 AUDIO 4MHZ 1 7 C6 7 6 T DB1 AUDIO SPO OBS AUBIOHOS 1 M1 M0 HAVE WEAK PULLUPS 4 A4 8 DG DB2 AUDIO 10 0 DB2 AUDIO2 160 DB2 AUDIO2 DB2 AUDIOO _ 174 8 DB2_AUDIO0 10 gt 4 A7 8 D6 1 1 1 SLAVE SERIAL I 082 AUDIOS 167 082 AUDIO6 DB2_AUDIO1 1 2 082 AUDIO 1 0 1 0 MASTER SERIAL MODE DB2_AUDIO7 166 DB2 AUDIO7 DBZ AUDIOS 171 DB2_AUDIO3 1 DB2_AUDIO8 164 555 OS 4 169 8 082 AUDIO4 DB2 AUDIOS 162 082 AUDI 082 AUDIO4 ag 5 082 AUDIO5 2 JUMPER GND TO USE CONFIGURATION ROM DB2_AUDIO10 161 1082 AUDIO9 DB2 AUDIOS 163 8 DB2_AUDIO_4MHZ 158 DB2_AUDIO10 DB2 AUDIO 4MHZ is 8 C6 8 C6 082 AUDIO amp ANLG 0 ESO 21 D6 ANLG 1 83 ANLG REGSES 21 6 CONTRACT 1 3 _REG3_ NO ces ANLG 4 6 A
194. DR 2MC POL 2 000 J18 42 510 12319 CONN D SUB 9FCX2 STACKED PCRA 1 000 J14 510 13146 CONN HDR 200 4MC PCRA 1 000 J15 510 13149 CONN RCA PCRA 1FCGX2V WH RED G 13 000 J1 13 510 13538 CONN RCA PCRA 1FCG BLK GND 1 000 J17 510 13877 CONN POST 100 HDR 2X5MCG LP 1 000 J19 510 13887 CONN POST 100 HDR 2X13MCG POL 1 000 J46 510 14079 CONN POST 156X045 HDR 4MC LOK 2 000 929 45 510 14080 CONN POST 156X045 HDR 6MC LOK 1 000 932 510 14890 CONN POST 100 HDR 2X17MCG LK 2 000 428 30 640 01701 SCRW 4 40X1 4 PNH PH ZN 2 000 5 704 14452 704 06165 HEATSINK TO220 75X 5X 5 TAB 3 000 U36 38 704 14452 HEATSINK TO220 MTTAB NUT 1 45H 2 000 U63 96 710 15250 PC BD MAIN MC8 1 000 01 17 03 PICK REV 4 PC BOARD 7 3 710 15250 PC BD MAIN MC8 Memory Board Assembly 202 09873 RESSM RO 5 1 10W 10K OHM 245 12485 CAPSM CER 1uF 25V Z5U 20 350 15741 ICSM FLASH 16M MC8 V1 00 350 15742 IC ROM 27C020 MC8 MEM V1 00 500 13644 CONN EURO C 48P abc PLUG RA 520 04999 IC SCKT 32 PIN MACH TIN 710 15290 PC BD MEM MC8 Video Board Assembly 202 09795 RESSM RO 5 1 10W 2 2K OHM 202 09871 RESSM RO 5 1 10W 1K OHM 202 09873 RESSM RO 5 1 10W 10K OHM 202 09874 RESSM RO 5 1 10W 2 2M OHM 202 10426 RESSM RO 5 1 10W 15K OHM 202 10558 RESSM RO 5 1 10W 47K OHM 202 10571 RESSM RO 5 1 10W 100K OHM 202 10573 RESSM RO 5 1 10W 470K OHM 202 10943 RES
195. DRCVR i as MR OUTPUT OUTPUT MUX CONNECTOR ZONE 500 DAC DSP BOARD DOWNMIX AUDIO ZONE AUDIO DATA FPGA 8 Service Manual VCO BOARD OVERVIEW The MC 8 VCO board is an isolated Voltage Controlled Oscillator module that forms part of an overall PLL for generating master clocks for digital audio in the MC 8 system The board is housed in a shielded enclosure and mounts to the main board through a 5 pin in line header J1 which carries control voltage input oscillator output and 5 volt power and ground The VCO assembly is soldered to the MC 8 main board which incorporates the phase detector and error amplifier to form the complete PLL MC 8 ANALOG OVERVIEW The analog section of the MC 8 encompasses all of the analog audio inputs and outputs level controls and A D and D A converters This section is located near the rear panel connections on the MC 8 Main Board There are two separate signal paths Main and Zone 2 Each of the eight analog stereo inputs or eight digital inputs can be routed to any of the two paths The Main path digitizes the analog signal if selected and passes it to the DSP Refer to the Main Audio Path 2 Channel Input block diagram in the next column The DSP creates eight different output signals from the 2 channel input D A converter ICs convert each of the eight signals from the DSP to analog The signals pass through level controls to their respective RCA connectors A direct analog pa
196. DSPCD_D18 2 88 3 88 5 88 8 84 FLAG1 m psreD D18 FLAG2 113 DSPCD_D20 BE EC 116 DSPCD_D21 DE EAE 117 DSPCD_D22 118 023 121 DSPCD 024 Dra FLAGS 122 025 123 DSPCD_D26 ER 126 DSPCD_D27 PAG 127 DSPCD_D28 128 DSPCD_D29 102 132 DSPCD_D30 103 ad 133 DSPCD_D31 DSPCD_DJ31 0 42 NCS 53 DSPD_BMSTR 04 DSPD_BMSTR 203 Nee 208 NC DSPD_OUT1 DSPD_OUTO 5 C1 5 D2 7 C8 5 C1 5 D2 7 C8 5 C1 5 D2 7 C8 5 C1 5 D2 7 C8 5 C1 5 D2 7 C8 5 C1 5 D2 7 D8 5 C1 5 D2 7 C8 5 D1 5 C2 8 B7 5 C1 5 C2 7 C8 5 C1 5 C2 8 B7 5 C1 5 C2 7 D4 5 C2 5 D1 7 B4 5 C2 5 D1 7 B4 5 83 7 05 5 A3 7 D7 8 B4 4 8 8 B7 4 A8 8 B7 REVISIONS DESCRIPTION DRAFTER CHECKER AUTH CHANGED PER DCR 020429 00 5 3 02 5 6 02 CONTRACT 01730 5 DRAWN RWH 2 28 02 CHECKED 3 5 02 3 5 02 ISSUED KB 3 5 02 TITLE SCHEM DSP BD MC8 DSP D SEE CODE NUMBER 060 15309 FILE NAME N EN 11 1 8 2002 15 51 15309 2 6 ms 6 9
197. DSP_AUDIO3 28 27 DSP_AUDIO4 A27 26 DSP_AUDIO5 A26 25 DSP_AUDIO6 A25 24 DSP_AUDIO7 A24 C23 DSP_AUDIO8 23 C22 DSP AUDIO 4MHZ A22 2 DSP AUDIO SPO DSP A13 A21 4 88 21 DSP A12 A20 C19 DSP A11 A19 C18 DSP A10 A18 DSP 9 C17 DSP 17 DSP A7 C16 DSP A6 A16 DSP A5 C15 ZA 15 0 TAVHCT244 1 D4 2 D8 4 D7 6 C6 7 C6 8 C6 12 A6 15 0 2 18 DSP_A5 DSP A 13 0 DSP 4 A15 DSP A3 C14 4 y2 16 DSP A3 DSP_A2 14 6 14 1 IO_RD Y3 42 ZDSP_RD DSP A1 613 2 D1 2 D3 4 D8 6 C7 7 C6 8 B6 19 8 DSP 0 A13 12 081 ZDSP_RD 12 1 74VHCT244 Cit 2 D1 2 D3 4 C8 6 B7 7 B6 8 B6 O_WR 1 vis 205 208 WR An 2 5 DSP DSP_AUDIO9 A10 M 3 DSP DSP_AUDIO10 9 ZDSP_D 7 0 sere oe 74VHCT244 205 D1 8 18 DSP_A6 18 DSP 6 ZDSP 03 A7 A2 Y2 16 ZDSP 04 C6 A3 1 DSP ATO ZDSP 05 205 06 C5 ZDSP 07 5 082 C4 74VHCT244 DSP_AUDIO_SP0 A4 m 9 DSP A13 C3 M X f DSP A3 5 DSP A9 C2 3313 DSP_CS 2 A 1 T DSP 2 EURO64 F TAVHCT245 ZD 7 0 1 03 2 06 3 07 6 86 7 6 8 6 7 0 _ 2 1 18 205500 3 a2 2 4a 3 18 24 15 86 45 Bs 13 246 B6 3 9 11 ZDSP 07 DSP CS 19 22 RDWR 1 2 D1 2 D3 3 D7 3 C7 6 A7 7 A6 8 A6 12 A7 DIR U80
198. EQ 3 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 03 0 05 0 25 None 100k 10 gt 500k 6 7 8 8 18 19 20 20 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_THD 3 4 0Vrms 4 0Vrms 20 5k 10k 40k 20 Unbal Float THD N 01 015 010 020 00005 40kHz LP 100k lt 10 gt 500k 6 7 8 8 18 19 20 20 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float Level gt 104 95 00 150 00 None 100k lt 10 gt 22k 6 7 8 8 18 19 20 20 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_SNR 3 OFF OFF 997 20 Unbal Float dBr Level 108 00 100 00 140 00 None 100k 10 gt 22k 6 7 8 8 18 19 20 20 2 4 6 8 Internal 96000 Analog ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX 2 amp 3 OFF 997 20 Unbal Float Vrms Level 80 00 70 00 140 00 40kHz LP 100k 10 gt 500k 6 7 8 8 18 19 20 20 1 3 5 7 2 4 6 8 Internal 96000 Analog D A DSP Tests Digital Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band Bin A Out B Out Source Rate Source DIG_MAIN_OPT1_IN_96K_TO_ANLG_MAIN_OUT_DSP DIG MAIN OPT1 IN 96K TO ANLG MAIN OUT DSP GAIN 3 amp 5 0 00dBFS 0 00dBFS 997 n a n a Vrms Level
199. EXTERNALLY WHEN CHIP IS RUN PINS ARE 3 3 VOLT TOLERANT 2 CHANGED PER DCR 020814 00 Eo KB 9 9 02 3 3VD AT29LV040A 2 5VD 3 3VD DEC_FLASH_A0 20 8 2 B4 3 C1 DEC FLASH 19 A0 VCC SPARES A 2 B4 3 C1 DEC A2 DECAS 17142 NC RP15 4 10K NC 16143 NC RP54 YY5 10K NC 5 1546 100 21 DEC po 8 8 5 DEC 141 2 01 22 01 3 3K 23 3K 5 S 13146 161 23 DEC 02 lt LANDY _ 8 25 DEC 03 A8 103 x BESET 2 4 3 01 DEC_RST y 144 RESET 0000 DEC 29 04 26 04 5 2 4 3 1 DEC C 5 35455 DEC A10 311410 105 27 05 DEC RST 142 SCS k SESS peshes __ 6 8 110K DEC ATI 11410 10528 DEC D6 DRST SCDIN 136 CSP84 RP5 6 10K 12 29 7 DCLK 2 C4 3 C1 SCDIN SDCKED A12 107 2 C7 3 C1 a L EC C SCDOUT 140 CDOUT SCDIO 51 5 74A 2 DEC 4143 DEC AB DEC C ABOOT IRQ SDCLKO 1514 eae DEC C 2 C7 3 C1 4 CS494001 CL 4 15 HINBSY RPE 4 5 10K _ 1294 NI RP1 1 10K DEC A16 10 HINBSY CS GPIO9 DOM1D 4 A16 2 C7 3 C
200. FD will display the test number and the error code In the event that the VFD is not operable the same information will be written to the LED matrix The test number will be read out as in the top row The error number can be read out in the second row Most Significant Byte and third row Least Significant Byte Vacuum Fluorescent Display VFD Test The VFD performs a busy test and a memory test The busy test sends information to the VFD and verifies that the VFD asserts then de asserts its busy status The VFD memory test consists of writing 55h AAh a walking 1 and finally a 0 to the character generator memory and display memory space of the VFD and reading them back After the MC8 B has passed the VFD Test for the rest of the power on diagnostics the VFD displays DIAGNOSTIC TESTS The dots increment in number from both sides simultaneously as the rest of the power on diagnostic tests are completed This keeps a user informed as to the functioning of a MC8 B If a failure occurs the test will attempt to write an entry into the error log and enter a loop to exercise signal lines to aid in debugging The error log is stored in the non volatile section of the SRAM so that it is not destroyed during the power on diagnostics A single error log entry is made each time the MC8 B is powered up a diagnostic test is executed and a failure encountered FPGA Test The FPGA test loads and verifies the programming of the XCS05 VQ100 U
201. FPGA Video Board and Front Panel Board The Standby LED e The Standby button e Front Panel Encoder interface 6 1 8 Service Manual Host Processor Memory There are three devices located in the Z180 s memory space the SRAM which is on the Main Board and the FLASH ROM and EPROM which are located on the Memory Board The 32kx8 70ns SRAM is powered by the battery backup so that user and factory default settings are preserved when the unit is powered down The Z180 boots from the 256kx8 70ns EPROM at power up Once the EPROM SRAM and FLASH diagnostics have passed the Z180 sets a bit in the Memory CPLD that allows the Z180 to run out of the FLASH ROM The 2Mx8 FLASH ROM is programmable from the RS 232 serial port Host Processor All peripheral devices and boards live in the 2180 I O address space The I O FPGA handles all address decoding Due to the size of the Main Board the Z180 data bus is buffered through two 74VHCT245s creating the IODX and IODY data buses All data and address buses going to other boards are also buffered RS 232 Serial Interface The 29 491mHz crystal oscillator is divided down to provide the 19 2K Serial Baud Rate of the MC 8 The TXO TX1 and RX1 ports on the 2180 are connected to the Max202E Transceiver that drives the two female DB9 connectors RS 232 1 and 2 6 2 Lexicon FPGAs Host Programming of FPGAs All FPGAs are programmed by the Host processo
202. H PH 2 BD TO 1U CHASSIS 8B ONLY B SCRW M3X20MM PNH PH 4 FAN TO PS SPRT SCRW M4X10MM FH SCKT 13 COVER TO CHASSIS SCRW M4X8MM PNH PH 9 FP TO CHAS 2 10 CHAS TO 20 CHAS 4 88 1U FRT TO 10 CHAS 3 88 SCRW M4X12MM PNH PH 4 FEET TO CHAS MC8 SDP5 SCRW TAP AB 2X1 4 PNH PH BZ 1 DIN CONN TO REAR SDP5 ONLY SCRW TAP AB 4X1 4 PNH PH 2 ACCESS PNL TO CHASSIS BOTTOM 8 SDP5 SCRW TAP AB 4X3 8 PNH PH 6 PNL TO CHASSIS SCRW TAP 4X3 8 PNH PH TRI 14 CONN TO REAR SCRW TAP 4X1 4 PNH PH BZ TRI 20 XLR CONN 1U CHASSIS 8B ONLY 1 PART NUMBER LISTING IS FOR NUT M4X 7MM KEP 1 CHASSIS GND REFERENCE ONLY AND DOES NOT WSHR FL M4 CL X 9 OD X 8MM THK 1 CHASSIS GND SUPERSEDE THE BOMS WSHR LOCK SPLIT 4 2 SUPPLY TO PS SPRT PS FL 4CL X 312 OD X 03 THK 2 SUPPLY TO PS SPRT 60W PS ONLY WIRE 186 G Y 2 5 187 QDC LUG 8 1 AC CONN TO CHASSIS GND CABLE 079 SCKT SCKT 4C 4 REF STANDBY BD TO BD CABLE 100 PLUG SCKT 2X17C 2 L REF VIDEO BD TO MAIN BD CABLE 100 PLUG SCKT 2X13C 2 L REF SW LED BD TO BD CABLE 100 SCKTX2 180 2X17C 6 L 1 MAIN BD TO BD 8B ONLY Aa ss meros oe ASSY ey CHASSIS 5 MC 8 B 50 5 _ MC 8 B CHECKED 6 14 02 ee NNNM 080 15462 steer Sor 3 7 6 9 4 5 2 1 CABLE PWR 187 110 QDC SLV
203. HCOL 2 0 FP Di 3 10 18 SWITCHCOL 1 FP D2 4 D 2917 SWITCHCOL 2 Tm 05 7 22 14 FED FP RST 1180 1 86 744 0C U3 SROW 7 0 3 A2 B R22 22k R23 74HC541 SROW 1 SROWO 9 FP DO R29 2 2K SROW 1 8 12 01 SROW 2 m SROW2 7 13 FP D2 2 2K SROW 3 6 14 D3 SROW SROW4 5145 15 04 2 2K SROW 5 4 16 05 SROW 4 SROW 6 3 2 17 06 srows 22K R20 SROW7 2 41 yi 18 016 srowe 22k 719210 U1 SROW 7 2 2K R21 2 22K 55 5VD CONTRACT n A Les 106 102 NO exICOn 3 OAK PARK 1 25 T 1 25 125 1 25 Tr 4 25 T 4 25 BEDFORD 01730 TTE 5 CHEM SW LED DRAWN RWH 122101 CONTROL amp STATUS REG CHECKED KAB 1 4 02 SIZE CODE NUMBER REV amp pu TUE B 060 15289 0 8 FILE NAME g ISSUED KAB 1 9 02 15289 0 2 2 or 3 e 8 7 6 2 1 i
204. Hee eve eed e aee enean 7 9 Switch LED Board 7 9 Front Panel Mechanical 7 9 Video Mechanical 7 10 7 10 Power Gord Options eiim iie 7 10 Mounting s u u o pr rn e ett Et 7 10 MC8 to MC8B Upgrade 7 10 ASSEMBLY DRAWINGS 080 14834 080 15461 080 15462 080 15463 080 15482 SCHEMATICS 060 13699 060 14849 060 15259 060 15279 060 15289 060 15299 060 15309 060 15319 060 14849 060 15329 060 15339 060 15349 060 15389 060 16139 ASSY DWG MECH VCO ASSY DWG SHIPMENT ASSY DWG CHASSIS M ASSY DWG MECH FP M ASSY DWG ACCESS MC SCHEM IR ENCODER BD SCHEM VCO BD SCHEM MAIN BD SCHEM VIDEO RCA BD SCHEM SWITCH LED BD SCHEM MEMORY BD SCHEM DSP BD SCHEM DECODER BD SCHEM VCO BD SCHEM STANDBY BD SCHEM VIDEO OUT BD SCHEM XLR BD SCHEM MIC DSP BD SCHEM MCLK VCO BD Lexicon CHAPTER 1 REQUIRED EQUIPMENT Reference Document Refer to the MC 8 User Guide Lexicon P N 070 15481 Required Equipment The following is a minimum suggested equipment list required to perform the proof of performance tests High quality amplifier with RCA and XLR input con
205. IISS RIT ______ _ __________ 2 88 61 DSPB ICI DSPC RIS A 33 DESEE SERI 5 C8 8 C1 pspp R14 4 33 DSPDSCKL 6 C8 DSP_30MHZ 2 R38 9 04 DSP_CLK spo 22 gt 5 1 R35 0005 gt 1 C3 SP4 AUDIO8 E A CONTRACT z AUDIO_4MHZ 1 C3 NO 3 01730 U7 APPROVALS DATE DRAWN SCHEM DSP BD MC8 RWH 2 28 02 FPGA CHECKED 3 5 02 SIZE CODE NUMBER REV ac B 060 15309 2 ew 3 5 02 ISSUED KB 3 5 02 15309 2 8 SHEET 8 OF 9 8 7 6 5 4 3 2 1 6 4 2 1 REVISIONS CHECKER AUTH CHANGED PER DCR 020429 00 E 3 EG 5 6 02 5 13 02 3 3VD 30 000MHZ DSP_30MHZ B A7 R7 33 U3 4 1 2 R11 33 DSPA 2 08 741 14 3 3 4 3 4 R12 33 DSPB 3 08 74LCX14 3 3V U3 5 gt R13 33 DSPAB 2 D1 2 A8 74LCX14 3 3V U3 13 12 R8 33 DSPC CLK 5 08 74LCX14 3 3V U3 9 8 R10 33 DSPD CLK 6 D8 74LCX14 3 3V U3 11 10 RQ 33 DSPCD ICE 5 01 5 8 74LCX14 3 3V 3 3V DIGITAL BYPASS CAPACITORS g _ Te _ Lcs Lco Tei Tos 1 25 1 25 1 25 125 1 25 1 25 1 25 1 25 T 1 25 1 25 T 1
206. IN IN2 96K TO ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 7 80 8 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 2 14 Internal 96000 Analog ANLG MAIN IN2 96K TO ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100 lt 10 gt 500 1 2 2 14 Internal 96000 Analog ANLG MAIN IN2 96K TO ANLG MAIN OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k lt 10 gt 500k 1 2 2 14 n a Internal 96000 Analog ANLG MAIN IN2 96K TO ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 100 lt 10 gt 22k 1 2 2 14 Internal 96000 Analog ANLG MAIN IN2 96K TO ANLG MAIN OUT SNR 3 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100 lt 10 gt 22k 1 2 2 14 n a Internal 96000 Analog ANLG MAIN IN3 96K TO ANLG MAIN OUT ANLG MAIN IN3 96K TO ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 47 80 48 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 3 15 Internal 96000 Analog ANLG MAIN IN3 96K TO ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100k lt 10 gt 500k 1 2 3 15 Internal 96000 Analog ANLG MAIN IN3 96K ANLG MAIN OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k 10 g
207. ISTORS 5 A20 DSP A0 DSP A 4 0 8 07 3 UNLESS OTHERWISE INDICATED CAPACITORS UF V 12_ 21 A21 205 8 C7 8 D1 11 22 22 4 2 DIGITAL ANALOG 4 CHASSIS POWER A11 22 22 ZDSP_WR B C7 8 D1 GROUND GROUND GROUND GROUND 10 23 C23 g on 523 AUDIOS 5 XX XX DENOTES SHEET NUMBER SECTOR C24 C24 8 05 6 LAST REFERENCE DESIGNATORS USED 98 09 FBS J3 01 R48 020 W1 9 24 24 AUDIO10 DSP DIN B 8 05 7 WITH ARE NOT INSTALLED B 25 A25 ZDSP_D1 8 NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED es c26 705 02 ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC A7 A A26 ZDSP_D3 ce 27 cz 205 04 27 27 705 05 5 C28 C28 205 06 A5 A28 A28 205 07 ZDSP D 7 0 we C4 C29 C29 8 7 DOCUMENT CONTROL BLOCK 060 15309 a 1 9 5 AUDIO_SPO 259 DESCRIPTION em 1 9 2 MAIN DSP A c2 c31 30F9 1 DSP B A91 ZDSP CS 8 C7 8 D1 4029 1 DSPABEXT MEM T es C32 A32 A32 ZDSP_RST 5059 1 5 8 C7 8 C1 6OF9 1 70 9 1 DSPCD EXT MEM EURO64 F EURO64 M J1 8 OF 9 2 2 90 9 1 BYPASS CAPACITORS amp DSP CLOCKS 2002 Lexicon In
208. K TO ANLG ZONE DIR OUT SNR 997 20 Unbal Float dBr Level 108 00 95 00 140 00 None 100 lt 10 gt 22k 9 10 3 15 Internal 96000 Analog ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT ANLG ZONE IN4 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 4 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 4 16 Internal 96000 Analog ANLG ZONE IN4 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float 9 Level lt 0 10 0 10 0 25 None 100k lt 10 gt 500k 9 10 4 16 n a Internal 96000 Analog ANLG ZONE IN4 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40k 20 Unbal Float THD N lt 010 015 00005 40kHz LP 100k lt 10 gt 500k 9 10 4 16 Internal 96000 Analog ANLG ZONE IN4 96K ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 9 10 4 16 Internal 96000 Analog ANLG ZONE IN4 96K TO ANLG ZONE DIR OUT SNR 997 20 Unbal Float 9 Level 108 00 95 00 140 00 None 100k lt 10 gt 22k 8 10 4 16 n a Internal 96000 Analog ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT ANLG ZONE IN5 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 4 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 5 17 Internal 96000 Analog ANLG ZONE IN5 96K ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 10 40 10 0 25 None 100k 10 gt 500 9
209. LY C PLUG HOLE 3 8 BLK 4 10 CHAS 8B ONLY 60 702 15444 PANEL REAR MC8 B 1 FOOT 1 97 DIA X 43H ABS BLK 4 CHASSIS MC8 50 5 702 15766 PANEL SDP5 CLIP WIRE HRNS 15 DIA 1 SHIELD 61 702 15457 PANEL OPTION BLANK 2 REAR PANEL QTY 1 FOR MC8 B V2 SPCR M3X34MM M F 6MM HEX 2 VIDEO TO BD 62 720 15656 CU EMBOSSED PSA 16 7 X 5 1 FOLD OF REAR PANEL SPCR M3X14MM 6 2 MEM amp DECODER BDS TO CHASSIS 63 720 13632 PAD FOOT 4 10 CHASSIS BOTTOM 8B ONLY SPCR M3X16MM M F 6MM HEX 4 DSP BD TO MAIN BD 64 720 14852 GASKET FAN 1 FAN TO PS SUPPORT SCRW M3X6MM FH PH 6 PS SPRT TO CHAS 2 MEM BD CHAS 1 65 DECD BD TO CHAS 1 PWR SW TO PS SPRT 2 66 740 08556 LABEL GROUND SYMBOL 0 5 DIA 1 PS SUPPORT SCRW M3X6MM PNH PH 34 VIDEO ASSY TO REAR 5 67 VIDEO BD TO MAIN BD 2 68 740 09538 LABEL S N CHASSIS 1 REAR PANEL MAIN BD TO CHASSIS 4 69 740 14888 LABEL LIC PAT WARN 1 CHASSIS BOTTOM DSP BD TO MAIN BD 4 70 740 15745 LABEL FUSE CAUTION 60W PS 1 PS SUPPORT FRONT PANEL TO CHASSIS 3 71 740 16403 LABEL FUSE CAUT 80W PS PS SPRT TO CHASSIS 2 72 OPTION PANELS TO REAR 4 73 750 15466 PWR SUP 5V 15V 60W 1 SEE BOM amp SHT 2 DETAIL B MEM amp DECD BDS TO CHASSIS 2 74 750 16408 PWR SUP 5V 15V 80W FOR 60W PS PWR SUPPLY TO PS SPRT 8 75 635 12112 SPCR M3X10MM 6MM 4 PS TO PS SPRT SCRW M3X8MM PN
210. MB90092 OSDC PQFP 1 000 032 390 10516 503 2 1 000 1 390 13857 CRYSTAL OSCSM 14 31818MHz TRI 1 000 U34 390 13858 CRYSTAL OSCSM 17 73448MHz TRI 1 000 U33 410 11639 RELAY 2P2T DIP 5V HI SENS 6 000 RY1 6 510 13128 CONN MINIDIN 4FC PCRA GND 7 000 J1 2 9 13 510 13148 CONN RCA PCRA 1FCGX2V BLK GND 2 000 J14 15 510 13840 CONN OPTO PCRA TORX173 6Mbps 2 000 CP1 2 510 14079 CONN POST 156X045 HDR 4MC LOK 1 000 J17 510 15471 CONN RCA PCRA 1FCGX2V GRN GND 2 000 95 8 510 15472 CONN RCA PCRA 1FCGX2V RED GND 2 000 94 7 510 15473 CONN RCA PCRA 1FCGX2V BLU GND 2 000 93 6 680 15469 CABLE 100 PLUG SCKT 2X17C 2 L 1 000 919 710 15260 PC BD VIDEO MC8 1 000 PICK 3 PC BOARD Video RCA Board Assembly 202 09871 RESSM RO 5 1 10W 1K OHM 5 000 R1 4 7 10 13 202 13579 RESSM RO 5 1 10W 22 OHM 5 000 R2 5 8 11 14 203 10560 RESSM RO 1 1 10W 75 0 OHM 5 000 R3 6 9 12 15 240 11827 CAPSM ELEC 10uF 16V 20 2 000 C13 14 245 12485 10 25 250 20 12 000 1 12 310 10510 TRANSISTORSM 2N3904 SOT23 5 000 91 5 510 13147 CONN RCA PCRA 1FCG YEL GND 5 000 1 5 510 13840 CONN OPTO PCRA TORX173 6Mbps 2 000 1 2 680 15475 CABLE FFC 20CX 1 CRMP ST RA 3 1 000 96 710 15270 PC BD VIDEO RCA MC8 1 000 2 Video Out Board Assembly 510 13147 CONN RCA PCRA 1FCG YEL GND 2 000 J1 2 680 15474 CABLE FFC 4CX 1 CRMP ST RA 3 1 000 J3 710 15330 PC BD VIDEO OUT MC8 1 000 PICK REV 1 PC BOARD DS
211. N gt 106 00 103 00 140 00 100k 10 22k 9 10 11 Digital DIG_ZONE_COAX1_IN_44k_TO_ANLG_ZONE_OUT DIG ZONE IN 44k ANLG ZONE OUT GAIN 0 00dBFS 0 00dBFS 997 Vrms Level 4 10 4 47 3 73 40kHz LP 100 10 gt 500k 9 10 11 44100 Digital DIG ZONE COAX1 IN 44k ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 n a n a THD N lt 003 005 0002 40kHz LP 100 lt 10 gt 500k 9 10 11 44100 Digital DIG ZONE COAX1 IN 44k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a THD N gt 106 00 103 00 140 00 100 lt 10 22 9 10 11 44100 Digital DIG ZONE COAX2 IN 96k TO ANLG ZONE OUT DIG ZONE COAX2 IN 44k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 n a Vrms Level 4 10 4 47 3 73 40kHz LP 100k lt 10 gt 500k 9 10 n a 12 External 96000 Digital DIG ZONE COAX2 IN 44k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 n a na na THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 n a 12 External 96000 Digital DIG ZONE COAX2 96k TO ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a n a dBr THD N gt 108 00 103 00 140 00 None 100k 10 22k 9 10 12 External 96000 Digital DIG_ZONE_COAX3_IN_96k_TO_ANLG_ZONE_OUT DIG_ZONE_COAX3_IN_44k_TO_ANLG_ZONE_OUT_GAIN 0 00dBFS 0 00dBFS 997 n a V
212. NIG RECA gt ups 01730 34 5 0 ANLG 6 21 6 E SP1 APPROVALS DATE 5 GND NC AUDIO 200 1 83 DEAWN SCHEM MAIN BD MC4 MC8 SP3 XT IO AUDIO 2 A3 SG RWH 2 5 02 AUDIO FPGA Seek ase SIZE CODE NUMBER REV 55858288 087 32902 52 UMBER i 4 3 02 4 9090 227 UE ISSUED kaB 4 3 02 15259 6 4 sHEET 4 OF 23 8 7 6 5 4 3 2 1 10 19 2004_8 59 7 6 4 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH RWH CW 1 CHANGED PER DCR 020430 00 Nono Ps e KB KB 6 4 02 6 26 02 RWH CW 2 CHANGED PER DCR 020731 00 3 3VD 5VD CBV KB 8 5 02 8 14 02 RWH CW 3 CHANGED PER DCR 020827 00 Rona 238 9 12 02 9 12 02 DSP_AUDIO 10 0 CW B4 AIB7 10 0 DSP_AUDIOO 4 UPDATED FOR 040922 00 m 9 27 04 9 27 04 DSP_AUDIO1 C29 DSP AUDIO2 A29 C28
213. NLG_MAIN_OUT ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_GAIN 3 4 0Vrms 4 0 Vrms 997 20 Unbal Float Vrms Level 7 80 8 90 6 60 40kHz LP 100k 10 gt 500k 1 2 6 18 Internal 96000 Analog ANLG_MAIN_IN6_96K_TO_ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100 lt 10 gt 500k 1 2 6 18 Internal 96000 Analog ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_THD 8 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100 10 gt 500k 1 2 6 18 Internal 96000 Analog ANLG_MAIN_IN6_96K_TO_ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 None 100k lt 10 gt 22k 1 2 6 18 Internal 96000 Analog ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_SNR 8 OFF OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 None 100k 10 gt 22k 1 2 6 18 Internal 96000 Analog ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 7 80 8 90 6 60 40kHz LP 100k lt 10 gt 500k 1 2 J 19 Internal 96000 Analog ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_FREQ 8 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 40 05 0 15 0 50 100k 10 gt 500k 1 2 T 19 n a Internal 96000 Analog MAIN IN7 96K TO ANLG MAIN OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k 10
214. N_96k_TO_ANLG_ZONE_OUT DIG ZONE OPT4 IN 96k TO ANLG ZONE OUT 40 00dBFS 0 00dBFS 997 Vrms Level 4 10 4 47 3 73 40kHz LP 100k 10 gt 500k 9 10 14 External 96000 Digital DIG ZONE OPT4 IN 96k ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 n a 14 External 96000 Digital DIG ZONE OPT4 IN 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a na n a THD N gt 108 00 103 00 140 00 100k 10 22k 9 10 n a 14 External 96000 Digital DIG ZONE IN 96k TO ANLG ZONE OUT OUTLEVEL DIG ZONE 4 IN 96k TO ANLG ZONE OUT OUTLEVEL 40 00dBFS 0 00dBFS 997 Vrms Level 103 00 99 00 1001 00 40kHz LP 100 lt 10 gt 500k 9 10 n a 14 External 96000 Digital DIG ZONE IN 96k TO ANLG ZONE OUT RELAY MUTE DIG ZONE IN 96k TO ANLG ZONE OUT RELAY MUTE 40 00dBFS 0 00dBFS 997 Vrms Level 125 00 120 00 1001 00 40kHz LP 100k lt 10 gt 500k 9 10 n a 14 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT GAIN 3 40 00dBFS 0 00dBFS 997 Level 8 10 8 83 7 43 40kHz LP 100 10 gt 500k 1 8 5 7 2 4 6 8 n a 11 External 96000 Digital DIG MAIN COAX1 IN 96K TO ANLG MAIN OUT FREQ 3 1 000BFS 1 00dBFS 10 20k 40k n a na n a Level 0 07 0 30 4
215. O FWR FDS SDDAT8 EXTA11 NVWE DEC TLASE CS 13 FHS1 FRD FR_W SDDAT9 EXTA12 FLASHCS ESI 344 FDAT SDDAT10 EXTA13 2 INFSI 27 SDDAT11 EXTA14 53 AH 24 FDAT2 SDDAT12EXTA15 2 DECAS SDI FDAT3 SDDAT13 EXTA16 19 47 DEC DEC MCKI FDAT4 SDDAT14 EXTA17 46 DEC A18 DEC OUT FSI 18 DATS 36 218 OUTFSI DEC GUI SGH 4 4 FDATe SD 19 RENEE OUTSCKI OUT 7 34 DEC 00 _0 7 0 8000 EC sSDO1 DEC_IN_FSI 119 35 01 5001 2 B4 3 C1 119 FLRCLKN1 SDDAT1 EXTD1 32 8002 3002 2 B4 3 C1 134 FSCLKN1 STCCLK2 SDDAT2 EXTD2 36 DEC D 003 2 B4 3 C1 FSDATAN1 SDDAT3 s i SDDATA 4 38 REE Di L Tr CMPREQ FLRCLKN2 SDDATS EXTD5 42 PEC DS NOTES CMPCLK FSCLKN2 SDDAT6 EXTD6 DEC CLK SEL 118 44 07 2 A4 2 C1 CLK 118 FSDATAN2 SDDAT7 7 1 SELECT SERIAL INTERFACE CLKSEL LOW FAST CLOCK FOR NORMAL MODE 85 99 DEC_MCKI et OW EOR FERSK LOND L se LROLKN GPIO23 MCLK lt lt 2 84 3 81 RISING 2 5VD 1 35 SDATANO 1 2 SCLKO 4 DEC SU SCK lt 2 B4 3 B1 DSP AB 4 1 SDATAN1 62025 LRCLKO O8 DEC SDOO 2843811 FSH2 PIN7 IS PULLED HIGH 80 SDATAN2 GPIO26 110
216. O BOOT SUCCESS MESSAGE 0 101 CS49400_INIT_ERROR 0x102 CS49400_ERR_WRITE_TIMEOUT 0x103 CS49400_ERR_READ_TIMEOUT 0x104 CS49400_INTREQ_TIMEOUT 0x105 CS49400_AUTO_BOOT_FAILURE 0x106 CS49400_ENQ_MSG_FAILURE 0x107 5 5 8 Service Manual CS49400_DEQ_MSG_FAILURE 0x108 CS49400_FINTREQ_TIMEOUT 0x109 CS49400_NO_APP_START_MESSAGE 0x110 CS49400_AB_SPI_TIMEOUT 0 111 549400 SPI TIMEOUT 0 112 CS49400_HOST_BOOT_FAILURE 0x113 CS49400_FLASH_WRITE_TIMEOUT 0x114 CS49400_BAD_FLASH_DATA 0x115 CS49400_BAD_RESP_OPCODE 0x116 CS49400_FLASH_READ_TIMEOUT 0 117 CS49400_MASTER_BOOT_FAILURE 0x118 CS49400_BAD_FLASH_VERSION 0x119 CS49400_ERASED_FLASH 0 11 CS49400_CHECKSUM_FAIL 0x11B The sharc error codes use from 0x0300 through OxOSFF SHARC_WCLK_FAILURE Ox3F9 SHARC_SRAM_FAILURE Ox3FA SHARC_SDRAM_FAILURE Ox3FB GPIO FAILURE Ox3FC TIMEOUT 0x3FD SHARC_TX_TIMEOUT 0x3FE SHARC_BAD_OPCODE 0x3FF The following codes are used to interpret the results from the SHARC GPIO SRAM SDRAM and Word Clock Tests available from the Extended Diagnostic Repair Menu The Error code is 16 bits with the most significant byte always being 0x03 The least significant byte is broken into bits as shown MSBit B7 B6 B5 B4 B3 B2 B1 LSBit B7 Semaphore indicator 1 failed 0 passed B6 GPIO LED failure 1 indicates that neither LED lit up from
217. O BOTTOM OF SUP PER ECO 031111 00 CLC 3 5 04 KB 5 13 04 2U CHASSIS D 4 PLCS D TORQUE 8 10 IN LBS 2 PLCS TORQUE 4 6 IN LBS C C FEED CABLE THRU OPENING IN CHASSIS BOTTOM amp MAIN BD 2 PLCS TO J28 ON MAIN BD TORQUE TORQUE 6 8 IN LBS 8 10 IN LBS 20 PLCS TORQUE 1 2 IN LBS B B TO MAIN BD J45 amp J32 DETAIL MC 8B DETAIL B ASSEMBLE 1U CHASSIS amp ATTACH POWER SUPPLY ASSEMBLY TO BOTTOM OF 2U ASSEMBLY SHT 1 WITH 60W SUPPLY 750 15466 1 SHT 3 PARTS LIST 2 SHT 1 8 20 ASSEMBLY UNLESS OTHERWISE SPECIFIED 2000 FILE DIMENSIONS ARE INCHES 15462 12 o ie wes oe E ASSY DWG CHASSIS tt a ws MC 8 B MC 8B ORC 080 15462 ser 2 3 LEXICON NC Fa aen uo B APPLICATION DO NOT SCALE DRAWING we sar 1 1 8 7 6 5 4 5 2 1 LEXICON NC ITEM PART 022 15423 022 15756 022 15426 022 14850 023 15428 023 15758 023 15429 023 15757 023 15434 023 15436 023 15439 023 16303 120 09621 454 13850 490 11462 490 13144 510 09790 527 12974 530 02488 540 02472 541 15458 530 09382 635 13637 635 14779 635 15468 640 10467 640 10498 640 10499 640 12534 640 13645 640 15476 640 15477 641 12759 641 01703 641 10989 641 11466 641 14898 643 10492 644 10494 644
218. O CHASSIS 640 10498 SCRW M3X6MM PNH PH BZ 4 000 MAIN BD TO CHASSIS 640 10498 SCRW M3X6MM PNH PH BZ 3 000 F PANEL TO CHASSIS 640 10498 SCRW M3X6MM PNH PH BZ 4 000 DSP BD TO MAIN BD 640 10498 SCRW M3X6MM PNH PH BZ 5 000 VIDEO ASSY TO R PNL 640 10498 SCRW M3X6MM PNH PH BZ 2 000 VIDEO ASSY TO MAINBD 640 10498 SCRW M3X6MM PNH PH BZ 2 000 MEM BD TO CHASSIS DECODER TO CHASSIS 640 10498 SCRW M3X6MM PNH PH BZ 4 000 OPT PANELS TO REAR 640 10499 SCRW M3X8MM PNH PH BZ 2 000 XLR BD TO 1U CHASSIS 640 13645 SCRW M4X10MM FH SCKT BZ 13 000 COVER TO CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 2 000 F PANEL TO CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 3 000 1U FP TO 1U CHASSIS 640 15476 SCRW M4X8MM PNH PH ZN 4 000 1U CHAS TO 2U CHAS 640 15477 SCRW MA4X12MM PNH PH ZN 4 000 FEET TO CHASSIS 641 01703 SCRW TAP AB 4X1 4 PNH PH ZN 2 000 ACCESS PANEL TO CHAS 641 10989 SCRW TAP AB 4X3 8 PNH PH BZ 6 000 R PANEL TO CHASSIS 641 11466 SCRW TAP 4X3 8 PNH PH BZ TRI 14 000 RCA CONN TO R PANEL 641 14898 SCRW TAP 4X1 4 PNH PH BZ TRI 20 000 XLR BD TO 1U CHASSIS 680 14494 CABLE 10 SCKTX2 180 2X17C 6 1 000 XLR J11 TO 428 680 14539 CABLE HSG HSG 4C 4 1 000 MN J29 TO VID J17 680 15470 CABLE ASSY 3 5mmJACK HSG 2C 3 1 000 IR CONN TO MAIN BD J18 DRESS NUT SUPPLIED W JACK 700 15447 CHASSIS 2U MC8 1 000 700 15448 COVER 2U MC8 1 000 700 15450 CHASSIS 1U MC8B 1 000 702 15444 PANEL REAR MC8 1 000 702 14454 PANEL FRONT 1U MC12B 1 000 702 144
219. O9 TO AUDIO 4MHZ PER DCR 020927 00 3 3VD 3 3VD 243904 10 15 02 10 15 02 D FPGA DONE 4 7K R36 SEE NOTES J R41 Q1 me 7 oO NC a iu R37 NC2 XCS05XL VQ100 DONE ucs DSP PROG P S2 INIT CCLK m DSP A 4 0 DSP A0 7 IO DIN TEST POINTS DSP 1 8A IO DOUT DSP A2 9 ZDSP RD DSP A3 10 Re ZDSP DSP A4 13 A4 DSP FPGA zes SSF 5 a 000 zose oo A gt ZRST ZDSP_D1 15109 _ 705 02 16 5 DSPAB_CMD_RDY ZDSP_D3 17 05 feces AB_RST ZDSP_D4 18 23 205 05 1994 2056 06 20 06 00 80 DO ene DSPCD_ACK D7 DSPAB D1 DSPCD_CMD_RDY DSPAB_D2 CD_RST 1 83 8 01 203 29 758 RD DSPAB D3 1 83 8 D4 WR 21 7ZDB WR 04 DSPABC FSI LU DI ec ZDSP CS 32 20841 DSPAB D5 ABC_FS 1 83 8 C4 2050 RST RST 06 _0 31 0 D_FS 0 psP FSi RG C DSPAB_D7 2 A3 3 A3 4 D7 FSLIRQS D 52 S A SCK 8 SCKI 2 D1 2 C3 3 C3 DSPAB HOST CS 34 DSPAB HOST CS AB RST 43 AB_RST 2 C8 3 C8 8 C1 C_SCK DSPAB_BMS 35 PSPAB_HOS a7 DSPAB_ACK 2 D1 2 C3 3 C3 DSPAB BMS DSPAB DSPAB_ACK_ 2 C8 3 C8 8 C1 DSPAB WR X 48 DSPAB 45 DSPAB_CMD_RDY P gt BSPAB RD X 40 DSPAB_WR 58 STATUS FULL P 2 28 8 21 DSF_MCK 3 C3 RD DSPAB RD DSPAB S
220. ON FOR MIC BD ndm PER 041201 00 MSJ 3 3VD 12 9 04 12 9 04 79 4 3 3VD NOTES R93 018 XC47S05XL 1 27 laol HARNS NC 22 24 veo 8 NC 26 50 4 26 Nc2 XCSO5XL VQ100 20 3 5 1 C3 DSP PROG 52 PROGRAM Se 220 58 NC DSP_A0 a TEST POINTS 1 B4 DSP 1 7 5 GND DSP_A2 9 2 U21 ZRD ZDSP RD DSP_A3 10 2E 881 ZDSP_WRI DSP_A4 13 205 ZDSP RETI 705 D 7 0 ZDSP_D0 14 po 1 B4 205 01 15 D Anke DSPAB ACK ZDSP_D2 16 DSPAB_CMD_RDY ZDSP_D3 17102 ABRDYL AB RST ZDSP_D4 18103 ABRST 7 ZDSP 05 19 BE 5085 06 20 06 DSPAB_Do 60 DO 7 DSPAB_D1 CDRDY DSPCD_CMD_RDY DSPAB_D2 CDRST CD_RST ZDSP RD DSPAB_D3 1 83 8 01 ZDB_RD ZDSP_WRI 21 2DB RD DSPAB D4 1 B3 8 D1 ZDB WR DSPABC FSI 203 CSj 32 DSPAB 05 ABC FSI quiae eed p irem opo Xm 3 Wels DSPAB 07 2 A3 3 A3 4 D7 FSI BEDA SG DSPC 8 2 D1 2 3 3 C3 BEAR EOS T 34 HOST CS AB RST 43 RST CK 2 C8 3 C8 8 C1 C_SCKI 2 D1 2 C3 3 C3 BEACH XI 35 DSPAB BMS DSPAB 47 DSPAB CMS ROVE 2 C8 3 C8 8 C1 3 C3 WR X 38 DSPAB WR DSPAB_CMD_RDY 39 pr 7
221. P Board Assembly 202 09794 RESSM RO 0 0805 13 000 R4 18 19 21 24 43 48 202 09872 RESSM RO 5 1 10W 33 OHM 12 000 R6 17 202 09873 RESSM RO 5 1 10W 10K OHM 2 000 R3 36 7 5 DESCRIPTION EFFECT REFERENCE 202 10557 RESSM RO 5 1 10W 4 7K OHM 2 000 839 41 202 11073 RESSM RO 5 1 4W 270 OHM 9 000 R25 32 40 202 11496 RESSM RO 0 OHM 1206 7 000 R20 33 35 37 38 42 245 12485 CAPSM CER 1uF 25V Z5U 20 96 000 C3 98 270 11545 FERRITESM CHIP 600 OHM 0805 4 000 FB2 5 310 10510 TRANSISTORSM 2N3904 SOT23 1 000 Q1 330 13866 ICSM DIGITAL 74VHC244 SOIC 1 000 U8 330 13882 ICSM DIGITAL 74LCX14 SOIC 1 000 U3 350 12456 ICSM SRAM 128KX8 12NS 3 3V SOJ 8 000 U9 12 17 20 350 13854 ICSM FPGA XCSO5XL 4 10X10 VOFP 1 000 U7 350 13879 ICSM SDRAM 512KX32X4 3 3V TSOP 2 000 U4 14 365 13860 ICSM uPROC ADSP21065 60MHz PQF 4 000 U5 6 15 16 390 13886 CRYSTAL OSCSM 30 0MHz TRI 3 3V 1 000 U2 430 10419 LEDSM INNER LENS RED 4 000 D3 4 7 8 430 10421 LEDSM INNER LENS GRN 5 000 D1 2 5 6 9 500 03619 CONN EURO R 96P a c PLUG VERT 1 000 J1 710 15300 PC BD DSP MC8 1 000 PICK REV 2 PC BOARD Decoder Board Assembly 202 09872 RESSM RO 5 1 10W 33 OHM 1 000 R5 202 09873 RESSM RO 5 6 1 10W 10K OHM 2 000 R2 3 202 10557 RESSM RO 5 1 10W 4 7K OHM 2 000 R7 8 202 10599 RESSM RO 5 1 10W 3K OHM 1 000 R1 202 11073 RESSM RO 5 6 1 4W 270 OHM 1 000 R6 202 11496 gt RESSM RO 0 1206 1 000 R4 205 14586 RESSM NET 5 ISOL 10KX4 4 000 RP1 2 5 6 205
222. PCD A16 0627 DSPCD D23 PCD_SRAM_CS PCD_WRI 3 3VD U10 DSPCD_A0 1 8 DSPCD_A1 2 0 VODI A DSPCD_A2 3411 0802 DSPCD_A3 05 13 128KX8 05 14 45 12NS pS 6 SRAM DS 05 18 6 DSPCD D24 DSPCD 19 49 007 DSPCD D25 DSPCD A11 20 10 01 16 DSPCD D26 DSPCD 211141 22 47 DSPCD D27 DSPCD A13 29 Me D4L22 DSPCD 028 Di DSPCE AIS Ds 3s DSPCD D30 3 DSPCD 16 32 415 06 27 DSPCD 031 A16 D7 01730 DSPCD_SRAM_CS DSPCD SRAM 5 5 5 1 5 2 6 3 WR DSPCD_WRY 124 APPROVALS DATE 5 C2 5 D1 6 C3 DSPCD RD DSPCD RD 28 QW DRAWN SCHEM DSP BD MC8 5 C2 5 D1 6 C3 RWH 2 28 02 psPCD EXT 9 CHECKED 3 5 02 SIZE CODE NUMBER REV 122 060 15309 1 2 72 3 5 02 U9 FILE NAME ISSUED KB 3 5 02 15309 27 SHEET 7 OF 9 N EN 11 1 8 2002 15 51 8 2002_15 51 8 7 6 4 3 2 1 T REVISIONS 3 DESCRIPTION DRAFTER CHECKER _ AUTH R40 CHANGED PER DCR 020429 00 Es DSP DIN 1 83 m SP 270 FPGA DONE LED DSP_CCLK 4 4W B3 GRN pi CHANGE SIGNAL AUDI
223. R 040922 00 R154 E AE 9 24 04 _ 10 14 04 2 13 D5 21 C3 MAN ANLC SELI AT AT N 100 0246 10 25 13 D5 21 C3 MAIN ANLO SEL 9 27 04 9 27 04 B 1 4W BAV99 13 D5 21 C3 amp UNITY PASS THRU J12 MAIN_ANLG_EN 13 D5 21 C3 gt ANLG C201 lt R153 5 04 RIGHT MAIN SW 45V 150 lt 100K PN RIGHT DIR IN 15V 17 84 15V 15V SOURCE SELECT RIGHT R186 15V 4 4 MC33078 13 43 gis GND v 150 1 3 2 tT 5 52 y UNITY GAIN PASS THRU RCA 100 dh 014 10 25 7 53 15 1 4W BAV99 12154 8 lt RIGHT ZONE IN nere 1 C195 5 R149 ps R1855 150PF lt 100K 10 5 15 9 8 58 lt R190 s 1 A2 EN gt 100K 1 16 15 2 09325 ZONE_ANLG_SELO 13 C5 21 C3 ANLG R146 191 3 5 21 3 ZONE_ANLG_SEL1 4 2 ZA T 13 5 21 ZONE_ANLG_SEL2 100 012 10 25 BAV99 13 C5 21 03 ZONE ANLG EN C189 lt 145 150 lt 100 15V SZ 15 57 15 UNITY PASS THRU R142 1 C185 5 AA SUB DIR IN 1884 V RCA 100 010 10 25 R181 93 1 4W BAV99 C183 y lt R141 150PF 100K 15V EX 15 R138 C179 6 VN 1 V RCA 100 08 10 25 8 10 182 177 lt R137 100 150 lt 100K 15V 15 8134 C173 7 15V RC
224. RCA jacks component inputs 1 2 3 feed a 3 wide two tier tree of double throw relays Each tier is comprised of a pair of dpdt relays The tree selects one of the input sets and presents it to the bank of final output relays The final tier of relays RY3 RY1 connects the output RCA jacks to either the selected component source or to the OSD One transistor driver is associated with each pair of relays Relays are actuated when the associated PSELn bit is asserted high switching from the normally closed to the normally open circuits Component OSD luminance Y is taken from the normal analog luminance output of the OSD chip Color difference signals Pr Pb are derived from logic level signals from the RGB port of the chip U5 buffers the logic levels and provides inverted versions of R and B A resistor array forms a weighted sum of the RGB levels along with appropriate dc offset and scaling to implement the standard color difference matrix Y 587G 299R 114B Pr 713 R Y e Pb 564 B Y U6 serves as buffer filter output driver for the Pr and Pb and drives the outputs through series terminating resistors R27 and R34 One normally closed pole of RY5 grounds OSD_PY_OUT in order to effectively disable component output The signals generated by the MC 12 OSD are compatible only with the 480i component format When incompatible formats are in use the component OSD is inapplicable and is not accessed by the operating system
225. S Each converter gets MCLK through a separate source resistor The SCLK 64xFS LRCK 1xFS are distributed to two sets of two DACs via separate source resistors All of the D A converters operate 125 mode The AK4395 DACs are configured through their serial ports pins 8 10 11 FRONT_DAC_RST puts the Front L R pair of DACs into reset while all other DACs share the same reset line MAIN_DAC_RST A second order low pass filter follows the DACs The filter amplifies the 1 7Vrms differential signal to 8Vrms 13 5 dB and converts it to single ended for the level controls Note these values assume a 0 dBFS digital input signal to the DAC ADG451 analog switches are used to select either the DAC output or analog input for the respective output These direct analog signal paths have been designed to support two modes 2 channel analog direct or bypass mode Any analog input be routed directly to the L R Front outputs 5 1 analog direct or bypass mode When this mode is enabled specific analog input signals are routed to specific analog outputs according to the table below Two different pairs of control bits are used to select the DSP DAC signals or analog input signals for the Main outputs FRONT_DACOUT_SEL selects the Front L R DAC outputs for the Left and Right Front outputs when low FRONT_DIRECT_SEL selects the analog input for the Front outputs MAIN_DACOUT_SEL selects the respective DAC outputs for
226. SCCLKPZL r 3 1 3 8 55 DEC 3 1 3 8 DB AB C INT DEC C SCCLK DEC C SCDIN DB AB C INT 43 DEC_FLASH_CS 1 C7 FLASH CS 3 1 3 3 DEC SRAM CS 44 DEC SRAM CS DEC FLASH 0 SRAM 3 C1 3 D3 45 DEC FLASH A1 DEC FLASH A0 Mv P nT PT n 3 C1 3 D3 DEC_NVWE_DLY 78 5 33 3 C3 3 81 3 83 59 DEC_IN_FSI DEC IN FSIEzZ 3 1 3 8 DEC OUT FSI 66 DEC Sen 3 B1 3 B3 8 67 DEC OUT SCKI 3 C1 3 B8 DEC OUT SCKI x 3 B1 3 B3 DEC 501 62 DEC SD 3 C1 3 B8 83 DB SDOO DB_SDO0R 3 F 1 7 2 1 84 DB SDO1 8001 F 1 7 2 1 82 DB SDO2 _ 2 F 1 7 2 1 FPGA DONE 7 6 4 3 2 1 3 3 0 REVISIONS REV DESCRIPTION DRAFTER AUTH DEDIN R6 CHANGED PER DCR 020604 00 nS Es 11 83 270 FPGA DONE LED KB taw PH 1 83 GRN 6 12 02 6 24 02 RWH CW D2 2 CHANGED PER DCR 020814 00 aise 2N3904 KB 3 3VD 9 9 02 TEST POINTS DB_RD RD DB wR DB_CS 5 AS RST DB FSI DB_SDOO D DB SDO1 DB 5002 AUDIO12 ciRee DEC CLK SEL
227. SI1 9 04 MAIN_C0 MAIN AD FSI w 15 B2 2345 _ MAIN DAC MDAC SCKIO e DAC SCKIO 7 73 6 A 4 C1 19 D8 20 D8 MAIN SCKIT MAN MAN AD VAN wee Z 984 VDAC SOKN 9 MAN DAC 9 D4 9 MAIN DAC FSI 99 MAIN DAC ZONE PATH 904 _ MAIN CD 10 AN CD MAIN DAC seki 100 SCKI 74VHC04 3 3V MAIN CE 11 _DAC_ 101 5 6 R267 56 FRONT DAC ZONE 9 C4 MAIN_CE MAIN DAC MCKI 17 08 ZMCK A MAN 15 107 FRONT DAC 501 ZONE DRCVR FSI 9 4 MAIN_DACO_SDI 108 CENTER MICT 17 C8 058 ZDRX FSI MAIN DAC1 501 109 SIDE DAC SDI 4 C1 18 C8 ZDRX SCKI ZONE DRCVR SCKI MAIN DAC2 801 110 REAR DAC 501 E 4 C1 19 C8 74VHC04 3 3V ZDRX SDO ZONE DRCVR 500 ZONE MORO 25 MAIN 501 4 C1 20 C8 4 R266 56 CENTER DAC T ZONE DAC 2 BS 4G ZONE_DRCVR_SDO 46 20 M 04227 ZONE_DRCVR_FSI 058 ZDAC FSI 9 ZONE DAC 8 4 C1 9 B4 ZONE_DRCVR_SDO ZONE_DRCVR_FSI 4 C1 9 B7 5 20 ZONE DAC MCKI 9 B4 ZONE 45 ZONE DRCVR SCK 120 9 ZONE DRCVR 9 B7 ZDAC ZONE 44 37 8 ZONE DRCVR NRzi 4 C1 9 B7 74VHC04 3 3V ZONE_DAC_SDI 9 84 ZONE
228. SIS POWER ENCODER B 777 GROUND GROUND GROUND GROUND 3 LAST REFERENCE DESIGNATORS USED C2 04 J1 SW1 U1 4 INSTALL ONE ONLY OF B C SW1 1 1 1 CONTRACT lexicon gompa 01730 APPROVALS pate TITLE DRAWN 10 27 99 SCHEM IR ENC BD MC12 10 27 99 Eu CODE NUMBER REV 060 13699 3 10 27 99 ISSUED KB 10 27 99 13699 3 1 SHEET 1 1 7 6 5 4 3 2 1 1 30 2001 15 17 5 4 2 1 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH D FB1 5VD A C4 77 MC1648 L1 NOTES T UNLESS OTHERWISE INDICATED RESISTORS 171017 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 4 DIGITAL ANALOG CHASSIS POWER 77 GROUND GROUND GROUND GROUND 5 LAST REFERENCE DESIGNATORS USED C5 D1 FB1 J1 L1 R1 Ut B REFERENCE COPY G CONTRACT z n S UNCBARK A NO 01730 APPROVALS DRAWN 102500 SCHEM VCO BD 12 CHECKED 11 700 SIZE CODE NUMBER REV CW B 060 14849 0 9 In FILE NAME 8 ISSUED _ 11 7 00 14849 0 1 SHEET 1 oF 1 5 4 2 1
229. SM RO 5 1 10W 22K OHM 202 10944 RESSM RO 5 1 10W 33K OHM 202 10945 RESSM RO 5 1 10W 1 5K OHM 202 10947 RESSM RO 5 1 10W 680K OHM 202 10948 RESSM RO 5 1 10W 390 OHM 202 11042 RESSM RO 5 1 10W 6 8K OHM 202 11071 RESSM RO 5 1 4W 75 OHM 202 12369 RESSM RO 5 1 10W 36K OHM 202 13579 gt RESSM RO 5 1 10W 22 OHM 203 10560 RESSM RO 1 1 10W 75 0 OHM 203 10583 RESSM RO 1 1 10W 10 0K OHM 203 10837 RESSM RO 1 1 10W 475 OHM 203 10840 RESSM RO 1 1 10W 750 OHM 203 10895 RESSM RO 1 1 10W 681 OHM 203 11080 RESSM RO 1 1 10W 1 15K OHM 203 11082 RESSM RO 1 1 10W 15 0K OHM 203 11723 RESSM RO 1 1 10W 4 75K OHM 203 11726 RESSM RO 1 1 10W 301 OHM 203 11730 RESSM RO 1 1 10W 1 37K OHM 203 12198 RESSM RO 1 1 10W 2 15K OHM 203 12298 RESSM RO 1 1 10W 30 1K OHM 203 12838 RESSM RO 1 1 10W 29 4K OHM 203 12897 RESSM RO 1 1 10W 976 OHM 203 14789 RESSM RO 1 1 10W 61 9K OHM 203 14790 RESSM RO 1 1 10W 11 8K OHM 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 240 10758 CAPSM ELEC 1uF 50V 20 5 5mmH 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 240 11827 CAPSM ELEC 10uF 16V 20 240 13217 CAPSM ELEC 47uF 16V 20 245 09876 CAPSM CER 01uF 50V Z5U 20 245 09895 CAPSM CER 10pF 50V COG 10 245 10416 CAPSM CER 1000pF 50V COG 5 245 10544 CAPSM CER 220pF 50V COG 5 245 10561 CAPSM CER 100pF 50V COG 5 245 10588 CAPSM CER 33pF 50V COG 10 245 10972 CAPSM CER 068uF 50V X7R 20 245 10975 CAPSM CER 3300pF 50V X7R 10 7 4 1 000 01 17 03 1 000 3 000
230. T JUMP TO PIN 10 MG do D29 155 DSSCD Dg NC1 D30 DSPCD D 31 0 NC 103 1 133_ DSPCD 031 6 A3 7 D7 8 B4 3 3VD 3 3VD NC 115 NC 202 23 8 DSPC BMSTR NC5 NC 203 208 NC R24 DSPC TDO NC6 DSPCD_EMU DSPCD EMU ee GND i DSPCD_ICE_CLK Ue DSPCD_TMS DSPCD TMS 6 88 20 69 DSPCD_TCK DSPCD_TCK A DSPCD_TRST DSPCD TRST pa CONTRACT DSPCD TDI NO R23 BEDFORD MA 01730 DSPC_OUT1 TITLE 4 A8 8 B7 APPROVALS DATE DSPD_TDO SCHEM DSP 6 88 RWH 2 28 02 DSPCD ICE DSPE 5 01 9 4 CHECKED 3 5 02 SIZE CODE NUMBER REV 9 ac B 060 15309 1 cw 3 5 02 FILE NAME S ISSUED KB 3 5 02 15309 25 SHEET 5 9 N EN 11 1 MASTER IDO HIGH 121 LOW SLAVE IDO LOW ID1 HIGH lt 0 00 0 7 ex 60 lo co o t 42 DSPCD_RAS 23 DSPCD_CAS DSPCD_SDWET 16 DSPCD_DQM 47 DSPCD SDCKE p DSPD CLK 48 DSPCD_SDA10 9 C4
231. TAT FUL SAB STATUS FULL 2 88 3 88 Ke DSP FSI 5 _ 2 C8 3 C8 DSPA OUTO 4 2 A3 4 B8 x DSPA OUTO 3 A3 4 BB De Se 10 52 DSPB_OUTO 2 A3 4 B8 2 3 A3 4 B8 DSPB OUT1 polZ9 DSPCD 00 NOTES DSPCD D1 DSPCD 02 PPCD D3 1 1 HAVE WEAK PULLUPS Ba DSPCD_D4 1 0 1 1 SLAVE SERIAL MODE DSPCD D5 M1 MO 1 0 MASTER SERIAL MODE DSPCD D6 DSPCD D7 5 3 6 3 7 07 2 JUMPER W1 GND USE CONFIGURATION 5 1 5 2 6 03 HOST 5 43 DSPCD_HOST_CS 30 ORS 5 C8 6 D8 8 C1 5 D1 5 C2 6 D3 DSPCD_BMS DSPCD_ACK 5 C8 6 D8 8 C1 DSPCD WR 54 46 DSPCD_CMD_RDY 5 C2 P gt BSPCD 44 5 0 WR DSPCD STATUS FULL 5 8 8 1 5 2 RD DSPCD RD DSP CD STAT 5 88 6 88 B SP SP IROCD 5 C8 6 C8 4 A8 5 A3 M QUTD DSPC_OUTO 4 A8 6 A3 DSPD_OUTO DSPC_OUT1 86 4 8 5 3 86 DSPC_OUT1 4 A8 6 A3 DSPD OUT1 DsP_FLAG1LZS DSP_FLAG1 s CE ea a Ba 1 D3 8 C1 DSP 33108 DSP FSI IRQ 91 gt 2 8 3 8 5 8 6 8 8 11 1 23 8 21 DB FSI DSPABC FSI gt 2 C8 3 C6 5 C8 8 C1 C3 8 C S 5 91 SED ESI C8 3 C6 5 C8 8 C DSPD z D EE SANI gt 6 C6 8 C1 DSPA SCK
232. THD N and turn on the 40kHz low pass or audio band pass filter Sweep the oscillator frequency from 20Hz to 2kHz and 8kHz to 40kHz Verify that the THD N measured on the Analyzer is less than 0 0196 20Hz to 2kHz and 0 02 8kHz to 40kHz Frequency Response Test FREQ Set the scale on the Distortion Analyzer to measure 4Vrms signal level Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a OdB reference to check Frequency Response for the MC 8 Turn the filter on the analyzer off Sweep the oscillator frequency from 10Hz to 40kHz Verify the signal levels are 0 05dBr to 0 15dBr 10Hz 20kHz and 0 05dBr to 0 50dBr 20kHz 40kHz of reference level over the entire sweep 4 5 8 Service Manual Signal to Noise Test SNR 1 Using the OdBr from step 2 of the Frequency Response Test off the oscillator and noise level measurement lt 108dBr Swap cables from the left RCA input 1 to the right RCA input 1 and the left front RCA output to the right front RCA output Repeat the GAIN THD N FREQ and SNR tests for the remaining Main Zone RCA Outputs Digital Inputs to Main Zone RCA Output Tests Having tested all analog to analog specifications in the previous tests it is now necessary to verify that all the digital inputs pass specifications These tests will verify the specifications of all digital inputs to the front left and right RCA outputs Setup 1
233. TICG 8 C6 12 A6 B3 gt 0 E a gt 5 3 3VD 6 4 02 6 26 02 3 3VD RWH CW 2 020731 00 3 3VD CBV KB 3 3VD lt R318 8 5 02 8 14 02 5 4 7 17505 1 RWH CW ARB ESLSE W 020827 00 3 85 22 24 We R319 2 M1 loo vcc NC 26 0 BONE 50 9 12 02 9 12 02 4 36 RWH CW 43256 R320 XCS05 VQ100 INIT 36 DATA 4 UPDATED FOR MC4 PER DCR 040922 00 zao 1070 vec 28 1 83 52 PROGRAM CCLK 4 CLK NC 2404 101404 ZA 9 IO DIN K 2 2 8 1 D3 1 C1 ZCLK 2 io 73 9 27 04 9 27 04 urs 5 P D 13 ZD2 291 a D1 IO FPGA ZWAIT 89 1 C8 2 D1 ZA6 4 45 02 15 203 25 92 02 85 TBI 2 D1 4 D8 5 C7 6 C7 7 C6 8 B6 ZA 3 46 03 16 204 208 93 03 IOWR 83 ONE 2 01 4 28 5 87 6 87 7 86 8 86 2 8 25 De 17 205 2 9 04 RD WR 2 D1 3 D7 3 C7 7IA6 8 A6 12 A7 ZA9 24 18 206 ZD6 96 05 71 21 9 0619 207 208 96 06 EN 71 12 87 TEST POINTS 23 D7 SWRD_LEDWR 12 87 11 SWRD_LEDWRY 70 FRONT_PANEL E ZA12 2 FRONT PANEL 12 A7 ZA13 26 12 ZA TS 7 A15 AUDIO FPGA 56 AUDIO FPGA 4 C8 ZWAIT SA_14 1 1 oat 8 14 PIC_CONFIG TDO 7
234. UED KAB 4 3 02 15259 6 21 SHEET 21 OF 23 8 7 6 5 4 3 2 1 10 19 2004_8 58 8 7 6 5 4 3 2 1 REVISIONS AC REAR PANEL REV DESCRIPTION INPUT POWER SWITCH POWER SUPPLY 5V 1 NC 1 1 020430 00 aes BON 5V 2 2 5V 2 TOMAINBD E a 5V 3 3 2 2 GND 3 DIGITAL NEUTRAL 2 4 i 4 4 NC FERRITE GND 4 331 E 52002 FERRITE HE GND 5 5 2 CHANGED PER DCR 020731 00 Epid eee SLEEVE 3 3 LINE 5 10A GND 6 6 5V 1 CBV KB C PNE 1 5 TURNS c 5V 0 8A 18 2 TOMAINBD 8502 81402 se 92 15 3 0 i5V 9 9 NC 3 ANALOG 3 CHANGED PER DCR 020827 00 RWA Cw 110 10 NC 4 e 8 30
235. UPDATED FOR MC4 PER DCR 040922 00 NC 30 25 ZA13 gt Ne 30 NCB A13 22 2 AT AT NC 43 14 9 27 04 9 27 04 d NC 51 NC8 15 28 NC NC9 16 28 62 NC10 A17 29 ELEAS NC NC11 TOUT A18 32 lt R398 lt R399 lt R400 NC12 A19 TESTBONTS BUSREQ 79 21 66 2 GBUSREQ MREG ZIORQ ZCLK ZINTO ZINTO IORQ E ZRD 1 1 2 5 ZMREQ 1 C1 4 D4 o INTO RD b 1 C1 2 C5 ZINT1 ZINT1 5 RD ZWRI ZIORQ C1 4 D4 ZINT2 ZINT2 ej NTI WR ZM1 ZRD 1 C1 4 D4 INT2 1 C1 2 C5 NMI papel NC ZWRI 15 5 2 1 2 D1 2 D3 ZWAIT ZWAIT BUSACK 8 HALT 61 4 ENCODER A PWR_RST 80 ENCODER_B RST ENCODER 38 DREQ1 59 BREGT ZINTO RX 49 48 COMO TX 20LK ZINT2 11 4 29 48 COMO TX 11187 250 55 VCCIO DCD0 47 251 7 150 461 50 49 202 2 02 9572 SA 14 83 2 C8 _ 1 54 204 03 RD 66 SRAM 2 68 NOTES 11 A4 CERT 25 1 551 1404 SRAM_WR 2 C8 CKA1 TENDO TXA1 TX 11 A7 25 12405 68 RA22 1 UNLESS OTHERWISE INDICATED RESISTORS 1 10W RXS 57 56 NC 707 06
236. _ RST CONTRACT lexicon 01730 TITLE APPROVALS DATE DRAWN SCHEM MAIN BD MC4 MC8 RWH 2 15 00 OPTION BD 0 CONNECTOR CHECKED 3 29 02 SIZE CODE NUMBER REV 060 15259 4 cw 413102 NAME ISSUED kaB 4 3 02 15259 6 6 SHEET 6 OF 23 7 6 5 4 2 1 10 19 2004_ 8 58 REVISIONS REV DESCRIPTION DRAFTER CHECKER AUTH 1 CHANGED PER DCR 020430 00 Mise 6 4 02 6 26 02 2 CHANGED PER DCR 020731 00 CBV KB 8 5 02 8 14 02 3 3VD 5VD RWH CW CHANGED PER DCR 020827 00 9 12 02 9 12 02 as 4 UPDATED FOR MC4 PER DCR 040922 00 Sound Rm aaar gt _ lt DBLAUDIO 10 0 532 Ai 14 gt C31 9 27104 9 27 04 _ 1 2 B3 231 DB1_AUDIO1 29 DB1_AUDIO2 A29 28 DB1_AUDIO3 A28 C27 DB1_AUDIO4 A27 26 DB1_AUDIO5 A26 25 DB1_AUDIO6 25 24 DB1_AUDIO7 A24 C23 DB1_AUDIO8 23 C22 222 DB1 AUDIO 4MHZ A22 4 A4 254 DB1 AUDIO SPO DB1i A13 4 A8 d
237. ae SRAM CS s 2 D1 2 C3 4 D4 8 5 8 6 8 8 4 8 1 FSI 2108 8 C4 SPTROAS 200 ADSP21065 SWPsg DSPAB WR giaz WR DSPAB_RD 2 x 2 D1 2 C3 4 B4 4 195 DSPAB_AO AO 194 DSPAB_A1 6 DROB 2 193 DSPAB A2 DSPAB WR X DSPABC FSI 7 05 190 DSPAB 8 7 2 C8 5 C8 8 B4 8 CT gt T amp TFSO Hee B A4 We TCLKO A4 2 C NC 188 DSPAB 5 X x __12 510 185 DSPAB AS 184 DSPAB A7 elas AT EES DSPAB_A8 NC Serre 5 _ 9 16880 A10 A LIS DSPAB 11 18 AMEI DSPAB 12 DSPB_1A_SDO 2 TOLKI 13 73 DSPAB AT 3 D1 5 C8 a 5 SPee SDO A15 3 D1 5 C8 18 15 A 170 DSPAB A16 NC 26 169 DSPAB A17 24 ME ENT 766 A18 8 165 DSPAB_A19 19 0164 DSPAB_A20 162 DSPAB A21 504 BMAR2 A21 DSPAB 22 q DMAG1 A22 DSPAB A 23 0 51 DMAG2 A23 160 DSPAB A23 2 B3 4 D6 40 82 DSPAB 00 52988 DO DSPAB 01 552 He 84 02 NC 0286 03 56 REDY 0387 04 88 05 05 _ 65 90 DSPAB_D6 Deoa DSPAB 1 2 0691 07 SICCA DSPAB BR2 284 BRI 07 92 08 C1 DO 96 DSPAB 09 B 216 148 2
238. al Float dBr Level 108 00 95 00 140 00 None 100k 10 gt 22k 9 10 2 14 n a Internal 96000 Analog Tests Analog Generator Analog Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Midiman Clock Sample Audio Test Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band A In B In A Out B Out PGM Source Rate Source ANLG ZONE IN3 96K TO ANLG ZONE DIR OUT ANLG ZONE IN3 96K TO ANLG ZONE DIR OUT GAIN 4 00 Vrms 4 00 Vrms 997 20 Unbal Float Vrms Level 4 00 4 30 3 70 40kHz LP 100k lt 10 gt 500k 9 10 3 15 n a Internal 96000 Analog ANLG ZONE IN3 96K TO ANLG ZONE DIR OUT FREQ 2 00 Vrms 2 00 Vrms 10 40k 20 Unbal Float dBr Level 0 10 0 10 0 25 None 100k lt 10 gt 500k 9 10 3 15 n a Internal 96000 Analog ANLG ZONE IN3 96K TO ANLG ZONE DIR OUT THD 4 0Vrms 4 0Vrms 20 40k 20 Unbal Float THD N lt 010 015 400005 40kHz LP 100k lt 10 gt 500k 9 10 3 15 n a Internal 96000 Analog ANLG ZONE IN3 96K TO ANLG ZONE DIR OUT XTALK 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 115 00 100 00 150 00 100 lt 10 gt 22k 9 10 3 15 Internal 96000 Analog ANLG ZONE IN3 96
239. all of the other Main outputs Center Sub L R Side L R Rear whereas MAIN_DIRECT_SEL selects the 5 1 analog inputs directly The output from the analog switch goes to a PGA2310 output level control and driver This level control operates from 15V rails with a gain range from 31 5dB to 95 5dB 0 5dB steps Each PGA2310 controls a signal pair The outputs from the level control pass through DC blocking caps and relays before going to the RCA connectors The relays mute the Main outputs during a power cycle and whenever the unit is in Standby or Off The relays are controlled by the MAINOUTS_MUTE signal The PGA2310 outputs also go to a 34 pin connector This connector is used for routing the audio to the XLR board in MC 8 Balanced models 6 18 Lexicon Control Registers and XLR Board Connector A 34 pin dual row ribbon connector routes the audio signals to the XLR board for MC 8 Balanced models Five discrete 74 273 control registers are located on the board The Z180 writes to them via the 8 bit data bus IODX_D 7 0 Control Register 0 provides the following e Mute relay control for the Main RCA outputs MAINOUTS_MUTE e Mute relay control for the Main XLR outputs EXPOUTS_MUTE e Mute relay control for the Zone RCA amp XLR outputs ZONEOUT_MUTE e selection e 5 1 direct mux selection Control Register 1 provides the following Analog source selection for the Main audio path MAIN_ANLG_SEL 2 0
240. at the SDRAM for each SHARC that has this test enabled on the DSP board is operational and can be written to and read from The SDRAM test is run using SHARC Pair 0 Processor A and the SDRAM is U14 on the DSP board and page 4 of the schematics The SDRAM test is also run using SHARC Pair 1 Processor C which is U4 on the DSP board and page 7 of the schematics If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix The test writes the test patterns of 0 55555555 OXAAAAAAAA a walking 1 and 0x00000000 are written to each location and read back Once each location is verified a counting test is applied to verify the address buss SHARC SRAM Test This test verifies that the SRAM for each SHARC that has this test enabled on the DSP board is operational and can be written to and read from The SRAM test is run using SHARC Pair 0 Processor B and the SRAMs are U17 U20 on the DSP board and page 4 of the schematics The SRAM test is also run using SHARC Pair 1 Processor D and the SRAMs are U9 U12 on the DSP board and page 7 of the schematics If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix The test writes the test patterns of 0x55555555 OXAAAAAAAA a walking 1 and 0x00000000 are written to each location and read back Once each location is verified a countin
241. ate Zip Code Country e Telephone number including area code and country code where applicable e Serial Number of the unit e Description of the problem e Preferred method of return shipment e Return Authorization number on both the inside and outside of the package 2 1 8 Service Manual Please enclose a brief note describing any conversations with HSG Lexicon personnel indicate the name of the person at HSG Lexicon and give the name and daytime telephone number of the person directly responsible for maintaining the unit Do not include accessories such as manuals cables remote controls etc with the unit unless specifically requested to do so by HSG Lexicon Customer Service personnel 2 2 Lexicon CHAPTER 3 SPECIFICATIONS Audio Input and Output Connectors Analog Audio Inputs Digital Audio Inputs Sample Rates Accepts Main Audio Outputs Zone 2 Audio Outputs 8 stereo RCA or 5 stereo and one 5 1 channel 2 stereo and two 5 1 channel connectors 4 S PDIF coaxial RCA and 4 S PDIF optical connectors coaxial and optical input connectors conform to IEC 958 S PDIF standards 44 1 48 88 2 96kHz 16 24 bits PCM audio Dolby Digital DTS DTS ES discrete data formats 8 unbalanced RCA and 8 balanced XLR MC 8 balanced only connectors for Front L R Center Sub Side L R and Rear L R 1 unbalanced RCA variable output level stereo connector 1 balanced XLR variable output level M
242. atically generates wait states to the Host for devices that require longer access times e Outputs the bits that are used to program the Audio FPGA e Receives Video Board status e Receives temperature sensor status e Generates 4mHz clock used for serial control interfaces e Allows the host to choose between the crystal oscillators for analog audio the master clock output of the Digital Receivers or the output of the Phase Lock Loop PLL as the master clock source for each zone e Digital control signals for the PLL e Control bits and sample rate detection clocks to the Main and Zone Digital Receivers 7180 HOST CHIP INTERFACE SELECTS HOST CONTROL WAIT STATUS STATES CHIP SELECTS VIDEO AUDIO BOARD FPGA STATUS PROGRAM BITS MAIN DRCVR CONTROL TEMPERATURE amp NRZ STATUS AUDIO DATA 2 XTAL OSC CLOCKS PLL amp CONTROL MAIN MASTER CLOCK ZONE MASTER CLOCK FPGA 6 4 Lexicon Audio FPGA The Audio FPGA is the central audio routing block for the system It has a byte wide data path to the host and seven host address lines It performs the following functions Generates word and bit clocks for each zone from the master clocks and distributes them to all audio devices and interfaces on the main board e Allows the host to select which digital audio connector is connected to
243. board with 5VD 5VA and 5VA A 7805 voltage regulator creates the 5VA supply from the 15V rail Heat is dissipated by a heatsink 5VA is an alternative clean 5 volt supply used by the A D and D A converters 5VR is created in a similar way to provide a stable reference for the D A converters MC 8 VIDEO SYSTEM CIRCUIT OVERVIEW The MC 8 video section consists of two major functional blocks video switcher and on screen display OSD generator The video assembly consists of three boards the Video RCA Board schematic 060 15279 the Video Out Board schematic 060 15339 and the Video Board schematic 060 15269 The RCA input and output boards connect to the main board via flexible ribbon connectors with most of the active circuitry contained on the Video Board Video input and output connectors are mounted directly on the boards which attach to the rear panel of the MC 8 Separate cables supply power and control signals to the video assembly Control from the main board is implemented via a serial interface Composite video inputs Specific references are to input 1 other inputs are similar Standard video levels applied to RCA jack J5 develop 1Vp p is across 75 ohm termination resistor R15 Emitter follower Q5 is located close to the connector and buffers the input with a gain slightly less than unity Transistor bias is supplied through R13 Buffered video is fed to pin 10 of ribbon cable J6 through low value series resistor R14
244. c A CONTRACT lexicon oe 01730 TITLE APPROVALS DATE SCHEM DSP DRAWN RWH 2 28 02 MAIN BD CONNECTOR CHECKED 3 5 02 SIZE CODE NUMBER REV 9 060 15309 2 al 3 5 02 FILENAME S ISSUED KB 3 5 02 15309 2 1 _ 1 9 8 7 6 5 4 3 2 1 8 5 8 6 8 8 4 8 1 19 04 gt gt DSPA 3 3VD MASTER IDO HIGH 101 LOW SLAVE IDO LOW ID1 HIGH R45 9846 DSPA_CLK 30 cL qw 3 C8 8 C4 8 C1 AB RST 31 152 157 XTAL2 BSEL Q RESET 3 C8 8 C4 8 C11 FSI SP IRQAB 3 C8 8 C4 DSPAB_CMD_RDY 144 DSPAB_ACK 100 8 C4 8 C1 3 C6 5 C8 8 B4 8 C 1 FSI 8 84 8 C1 p _DSPA_SCKI DSPA 0A SDI 1 D1 1 C3 1 D1 1 C3 DSPA 501 nas NC NC 0 Al RI Ri DI DI TI T DTOA DTOB RI Ri DI DI TI 2 C1 3 B8 BRT 2 C1 3 B8 2 C1 3 B8 DSPAB BR2 3 B8 8 C4 DSPAB STATUS FULL DSPAB EMU DSPA TDO DSPAB TMS DSPAB TDI 148 TO 151 DSPAB_TRST 3 B8 5 B8 6 B8 8 B4 gt DSP FLAGT DEVELOPMENT ONLY PIN 7 BTCK JUMP TO PIN 8 PIN 9 BTRST JUMP TO PIN 10 3 3VD 3 3VD R48 DSPAB EMU DSPAB ICE CLK 6 DSPAB
245. coaxial RCA input 1 to the front left and right XLR output Gain Test GAIN Apply 997Hz signal 0 00dBFS to S PDIF coaxial input 1 Set the scale on the Distortion Analyzer to measure 8Vrms signal level Turn all the filters off on the Analyzer Filter not required for Gain Test Verify that the output level measurement from the 8 is between the range 7 43Vrms 8 83Vrms Note this level 4 7 8 Service Manual Total Harmonic Distortion Noise Test THD N 1 Adjustthe scale on the Distortion Analyzer to measure 0 001 and turn on the 40kHz low pass or audio band pass filter Sweep the oscillator frequency from 20Hz to 1kHz and 5kHz to 40kHz Verify that the THD N measured on the Analyzer is less than 0 005 20Hz to 1kHz and 0 02 5 2 to 40kHz Frequency Response Test FREQ 1 Set scale on the Distortion Analyzer to measure 8Vrms signal level 2 Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a OdB reference to check Frequency Response for the MC 8B Turn the filter on the analyzer off Sweep the oscillator frequency from 10Hz to 40kHz Verify the signal levels are 0 10dBr to 0 25dBr 10Hz 20kHz and 0 10dBr to 0 75dBr 20kHz 40kHz of reference level over the entire sweep Note these levels Dynamic Range DYNRNG Using steps 1 3 of the Gain Test set the oscillator to GOdBFS and a THD N level mea
246. ctal outputs from D not all slots are used are unpacked into four 2 channel MAIN_ADC_SDO MAIN_DRCVR_SDO DECODER_SDO 0 3 DSP D Serial Audio Out CRYSTAL DECOER CS49400 AUDIO CLOCKS amp DATA DECODER_SDI gt 4 STEREO IN 1 OUT CRYSTAL 49400 DECODER DECODER BOARD SHARC DSP A B AUDIO DATA IN DSPA 50 DSP AB DSPB SDI SHARC DSP AUDIO DATA I O SHARC DSP 1 OCTAL IN 4 STEREO OUT DSP BOARD MAIN AUDIO PATH AUDIO FPGA BLOCK 1 MAIN DAC 05 SDI TO ANALOG SECTION 6 13 8 Service Manual Main Audio Clock Path There are two possible sources of master clock for the Main Audio Path The 24 576 oscillator that can provide either a 48kHz or 96kHz sample rate or the master clock output of the main digital receiver In practice the unit runs off the crystal at 96 2 when the input is analog When the input is digital the master clock output of the digital receiver is used This master clock is de jittered by the PLL that is controlled by the FPGA using signals derived from MAIN_DRCVR_MCKO Depending on the input selected the appropriate master clock is routed from the FPGA to the Audio FPGA Here i
247. d op amp U2 Sync stripper U3 accepts analog video and extracts vertical and horizontal sync producing logic level VSYNC OUT and AFC OUT pulses respectively A phase locked loop based on ceramic resonator Y 1 provides robust horizontal sync extraction even from noisy video sources Pull down resistors on the outputs improve the pulse waveshapes Sections of U4 buffer and shape the pulses from U3 AFC OUT is stretched by R15 C18 before buffering in order to meet the minimum width necessary for the OSD chip Sections of U4 and the network formed by R9 R10 D2 and C12 form pulses that are aligned with video back porch These pulses switch U1 which in combination with integrator U2 forms a sample and hold circuit that closes the feedback loop around the input video amplifier during back porch time This acts to 6 23 8 Service Manual maintain the back porch level at 0V D1 limits the negative going output of U2 in order to minimize the undesirable effects of unusual sync patterns inherent in the macrovision video copy protection scheme Additional logic within U3 detects the presence of a valid video input SYNC_DETECT is fed to the main board for use in OSD management With video input absent AFC_OUT free runs at around 15kHz Video Control Registers Control registers are implemented using shift registers as serial to parallel converters U36 37 and 38 are 8 bit shift registers which are cascaded to receive a 24 bit serial word Each chi
248. deo output switch the S video monitor output cable on the back of the MC 8 to the Zone 2 S video output then repeat the procedure The above procedure should be repeated to test S video inputs labeled 2 through 5 To do this repeat the procedure changing the input selected in step 14 to the appropriate input 4 10 Lexicon Component Video Input to Component Video Output Test This test will verify the component video switching function of the MC 8 Setup 1 Connectthe component video output from the DVD player to the MC 8 component video input 1 2 Connect the main component output of the MC 8 to the component input of the video monitor 3 Turn on the DVD player monitor and the MC 8 4 The monitor should display a blue screen 5 Press the remote DVD1 button to select this as the input for testing the video paths 6 Press the Menu arrow The Main Menu should appear on the display 7 Using Menu arrow scroll down to Setup then select pressing the Menu arrow 8 The Setup Menu will appear and the inputs at the top will be highlighted 9 Press the Menu arrow again 10 The display will read Input Setup DVD1 11 Press the Menu arrow The display on the 8 will now be at the top of the DVD1 Menu 12 Using the Menu arrow scroll down to the Component In parameter and select it by pressing the Menu arrow 13 Press the Menu gt arrow to select the Component1 input This will assign the comp
249. est Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band Aln Bin A Out B Out Source Rate Source DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT GAIN 40 00dBFS 0 00dBFS 997 Vrms Level 8 10 8 83 7 43 40kHz LP 100k lt 10 gt 500k 21 22 na 11 96000 Digital DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT FREQ 1 00dBFS 1 000 5 10 20k 40k n a dBr Level lt 0 15 0 60 0 10 0 25 0 75 100 lt 10 gt 500k 21 22 11 External 96000 Digital DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT THD 1 00dBFS 1 00dBFS 20 1k 5k 40k THD N lt 003 075 005 020 0002 40kHz LP 100 lt 10 gt 500k 21 22 11 96000 Digital DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT XTALK 1 00dBFS 1 00dBFS 15k dB Level gt 88 00 80 00 150 00 100 lt 10 22k 21 22 n a 11 External 96000 Digital DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a dBr THD N gt 110 00 105 00 140 00 None 100k lt 10 22k 21 22 11 External 96000 Digital DIG ZONE IN 96K TO ANLG ZONE XLR OUT 600 DIG ZONE COAX1 IN 96K TO ANLG ZONE XLR OUT GAIN 600 40 00dBFS 0 00dBFS 997 n a Vrms Level 6 85 7 50 6 30 40kHz LP 100k lt 10 gt 500k 21 22 11 External 96000 Digital DIG ZONE COAX1 IN 96K
250. forty seconds to complete The power on diagnostics are intended to verify basic hardware functionality of an MC8 B Additional diagnostic tests are available for manufacturing and customer service to completely test the hardware and for debugging failures Initially an attempt is made to illuminate the VFD and front panel LEDs for approximately five seconds However during the first six tests the VFD will not be considered functional due to it not being tested During these tests Trap Op Code EPROM FLASH Checksum Z80 SRAM program FPGAs and VFD the unit will attempt to use the STANDBY LED to indicate if a failure occurs As soon as these are completed the VFD will display DIAGNOSTIC TESTS The dots increment in number from both sides simultaneously as the rest of the power on diagnostic tests are completed This communicates that the unit is still functioning The audio outputs digital and analog will be muted during this sequence The following sections list the test explanations The front panel display is shown only for the first test that can use the VFD The reference designators used are for the MC8 Revision 3 Main Board 710 15250 used on BOM 023 15428 and revision memory board used on BOM 023 15429 The schematic for the main board is 060 15259 and the memory board is schematic 060 15299 Trap Opcode The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched The INT TRAP Contr
251. g a grounded input to feed the chrominance channel When MCVID is high 018 is disabled disconnecting the composite inputs and 020 passes addresses to the MSVID_SELn bits allowing 017 and U16 to select one of the S video sources The composite luminance MY signal from U17 U18 is amplified by non inverting stage U29 R164 makes the gain slightly greater than the desired factor of two in order to make up for slight losses in other stages The signal from U29 1 is fed through R121 to the sync stripper and dc restorer The dc correction signal BPCOR returns through R166 to close the dc feedback loop and maintain the video back porch near OVdc The signal OSD_Y_IN is distributed to output amplifiers 026 U28 and also feeds the on screen display Chroma selected by U16 MC is ac coupled by C137 and amplified by U29 also with gain slightly greater than two With a composite source selected U16 is forced to input 0 grounding the chroma channel The signal OSD_C_IN is distributed to output amplifiers U27 and U28 and also feeds the on screen display The dc level on the chroma channel of the selected source is fed to the base of Q15 through multiplexer U19 and the associated 100k series resistor R132 raises the threshold for sensing a high level The dc amplifier formed by 015 and Q14 is disabled when is high When enabled a high dc level on the chroma input will drive base current into Q15 Q15 saturates and turns on Q14 wh
252. g test is applied to verify the address buss 5 10 Lexicon Power On Diagnostics Completed After the power on diagnostics are completed the VFD will display the appropriate power up message MANUFACTURER MODEL VX XX c 200X OPTIONS At this point the operating system takes over the functioning of the MC8 B EXTENDED DIAGNOSTIC TESTS As described earlier the extended diagnostic tests are accessible by pressing and holding the MAIN VCR and ZONE 2 VCR front panel buttons when powering a MC8 B The audio outputs analog and digital are muted When the VFD displays LEXICON the front panel buttons can be released After the model banner is briefly displayed on the VFD the display will indicate DIAGS MENU FUNCTIONAL TESTS The extended diagnostics can also be entered via the serial debug port by first entering the debug program Type debug when connected to the RS232 2 serial port to access the debug program The debug program is case sensitive Once in debug type x 2e and the unit will go into extended diagnostics In addition the extended diagnostics can be entered through the RS232 2 serial port by sending ed which stands for extended diagnostics to the unit via the serial debug port during the first ten seconds after powering on the unit After extended diagnostics are entered use the front panel encoder Mode and Mode buttons to navigate through the diagnostics The front panel encode
253. ght front outputs of the MC 8 to the amplifier left and right inputs Connect the outputs of the amplifier to a pair of speakers 3 Using the remote control Menu gt arrow scroll through the Diagnostic Menu and select the Audio I O Tests 4 Inthe Audio I O Test Menu highlight S PDIF Input CX 1 Test then press the Menu arrow to engage the test The MC 8 is now set to route digital audio from the S PDIF coaxial digital input 1 to all the RCA analog outputs Insert a CD and press play on the player Power on the amplifier Slowly increase the volume on the amplifier to a comfortable listening level Verify that clean undistorted audio can be heard Stop the DVD player and power down the amplifier 50 369 9 0 Repeat steps 2 through 7 for the remaining paired RCA outputs 1 If testing 8 Balanced unit repeat above procedure using XLR cables to connect the appropriate MC 8 XLR Main Zone Outputs to the amplifier 12 The above procedure should be repeated to test digital S PDIF Inputs 2 through 4 as well as optical Inputs labeled 1 to 4 To do this repeat the procedure changing the Input test selected in step 4 to the next appropriate Input The DVD output will need to be moved to the appropriate MC 8 Input corresponding to the Input selected in the Audio I O Test Menu When testing the optical inputs be sure to use the appropriate digital cable 4 4 Lexicon AUDIO PERFORMANCE VERIFICATION Pe
254. he Zone 2 Audio Paths block diagram below An analog source can be passed directly to the analog outputs Likewise a digital source can be passed directly to the digital outputs and be routed to a D A converter for the analog outputs In addition a 5 1 Dolby Digital or DTS encoded 5 1 digital source may also be selected and passed through a decoder which will output a 2 channel downmix for the Zone 2 outputs One S PDIF RCA coaxial output port is available 6 16 Lexicon Analog Audio Inputs The Left input jacks and associated circuitry are on the first sheet See the second sheet for the Right input jacks and circuitry Each input pair is buffered by a dual TL072 op amp Each buffer connects to two DG408 8x1 CMOS switches There are separate switches for the Main and Zone 2 analog source selection with independent switches for left and right channels for a total of four DG408s The outputs of the Main source selectors feed the Main Input Level control Two dual op amps are used for the direct analog path to the Front L R outputs and the Zone 2 outputs and buffer a 6dB voltage divider that feeds the level control At the bottom right hand corner of sheets one and two are two op amps These amplifiers are used when routing a 5 1 analog source One buffers the Center and Subwoofer signals from Inputs 4 or 7 while the other buffers the Surround L R signals from Input 5 or 8 Microphone Inputs and Main A D Converter Two microphone inputs are
255. he following on the VFD START ALL TESTS When the Start All Tests menu option is selected the Loop tests are run continuously The first time the burn in loop is run the decoder flash and the video flash will be programmed They will each take about 3 5 minutes to complete This flash programming is only performed one time All subsequent looping of the burn in loop will not program the flash These are the tests available in the Loop Test Suite Z180 Burn In SRAM Z180 EPROM checksum Z180 FLASH checksum VFD Memory 5 19 8 Service Manual e I O FPGA Verify ID e DSP FPGA Verify ID e Decoder FPGA e Crystal 49400 Boot Sharc Internal GPIO 4 Sharc SRAM x4 e Sharc SDRAM x4 Sharc Boot x2 Trigger 0 ON Trigger 1 ON Trigger 0 OFF Trigger 1 OFF There is only item this menu selecting it will start the sweep through the whole suite of loop tests As long as there are no errors the test will continue to run If there is a failure the entire bottom row of eight LEDs on the front panel will light These are the TV CD and AUX LEDs for the Main and Zone2 sections Depending upon the failure the failing test will cycle and the error code will be displayed on the second line of the VFD For example if the Decoder FPGA verify fails the VFD will indicate DEC FPGA TEST Fail 001 continue press the MODE switch Upon completion of all of the tests the
256. he full screen mode is independent of video and sync inputs Raster generation is based on the appropriate crystal clock The OSD luminance output is dc shifted back to OV back porch level by U23 and associated circuitry C98 C99 passively couple the ac content with the op amp providing the dc response Chroma is simply ac coupled by C117 C125 The shifted OSD video is buffered and filtered by U24 to produce OSD SY OUT and OSD SC OUT OSD PY OUT is buffered separately by U25 to drive the component osd luminance output Switch U35 permits the S video luminance to be turned off when MSVID YOFF is asserted high OSD OUT is formed as half the sum of the buffer outputs These OSD output signals feed the output amplifiers as described earlier In order to produce usable overlays in the SECAM system the OSD switching action is bypassed at high frequency through 035 and R146 preserving an attenuated version of the fm color carriers On Screen Display Serial Control The internal registers of the OSD are programmed serially from the main board in multiple 8 bit packets on VIDEO DATA accompanied by VIDEO SCLK operating at 1 MHz During routine OSD updating 0 0_ 5 is fed through 035 as the OSD chip select Each logical transfer to the OSD chip consists of a pair of single byte transfers Sync Stripper DC Restorer Video from input amplifier U29 is fed through R121 to U2 which drives sync stripper U3 and the dc restorer formed by switch U1 an
257. ich applies a high dc level to the filter formed by R31 and C112 With low dc level input both transistors remain off and no dc is fed to the filter This circuit discriminates a low or high dc voltage on the selected chroma input and forms 0 or 5V level accordingly The sensing threshold is around Main S video at J2 is driven by gain of one amplifiers 026 and U27 chroma Internal multiplexers in these amplifiers determine whether the S video is taken from the OSD path MSTHRU hi or straight through from the input amplifiers MSTHRU low MSTHRU follows MTHRU unless MSVID OFF is asserted allowing main S video luminance to be shut off when a composite source is in use Amplifier outputs are fed through 75 ohm series resistors R148 R151 forming a matched transmission line driver system R150 and R152 compensate for slight impedance errors due to the resistance of the on board connecting traces The chroma output is ac coupled by C130 with a dc level introduced through When is asserted low switch U1 permits the main chroma output to follow the dc sensing circuit Main composite video CVID MAIN is driven by U28 Luma and chroma from the input amplifiers are summed by R162 and R159 scaled by 1 2 The result is amplified by 028 which has a gain of slightly more than two With composite input there is no chroma and the result is simply the composite video With S video input the result is the compos
258. ics MAIN VCR amp ZONE2 VCR Skip Power On Diagnostics MAIN AUX amp ZONE2 AUX Jump to Extended Diagnostics MAIN OFF amp ZONE2 OFF Attempt to Run the Next Diagnostic Test MAIN TV amp ZONE2 TV To Enter Extended Diagnostics Press and hold the front panel MAIN VCR and ZONE 2 VCR buttons when powering on a MC8 B To Enter Extended Diagnostics via Serial Debug Port Enter the debug program by typing debug when connected to the serial port The debug program is case sensitive In addition the extended diagnostics can be entered by sending ed for extended diagnostics to the unit via the serial debug port during the first ten seconds after powering on the unit 5 1 8 Service Manual To skip Power On Diagnostics Press and hold the front panel MAIN AUX and ZONE2 AUX buttons This will cause the unit to skip the power on diagnostics and go immediately to the operating system Immediately after sufficient testing is performed to the system can boot the 2180 CPU EPROM 280 SRAM FPGAs loaded VFD etc the diagnostics check to see if MAIN AUX and the ZONE2 AUX buttons are being pressed together If they are the unit will attempt to skip the rest of the power up diagnostic tests and jump to the operating system To bridge to Extended Diagnostics after a failure occurs Press and hold the front panel MAIN OFF and ZONE2 OFF buttons This will cause the unit to bridge to the extended diagnostics
259. ilure information is available via the serial debug port Specific failure information will depend on the test being executed REPAIR DIAGNOSTICS SUITE The Repair Diagnostics suite allows you to individually execute every diagnostic test on a unit The Functional suite uses the same tests as the Repair Diagnostic suite but automates how the tests are run The following tests are available in the Repair Diagnostics 2180 EPROM checksum 2180 FLASH checksum 2180 e I O FPGA Verify RS232 Wrap Test SHARC Tests Sharc GPIO x12 PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 1 PROC B Sharc SRAM x12 PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 1 PROC B Sharc SDRAM x12 PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 1 PROC B Sharc WCLK x12 SEL 44 WORD CLK SEL 48 WORD CLK SEL 88 WORD CLK SEL 96 WORD CLK SEL 44 48 PLL WCLK 5 12 Lexicon SEL 88 96 PLL WCLK SEL DRCVR WCLK PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 1 PROC B Sharc Boot x2 PAIR 0 PAIR 1 DSP FPGA Verify CS49400 Boot Test FPGA ID Test Boot Test Show Flash Version Flash Checksum Test Load Flash IR Remote VFD Memory Test VFD CHAR Test VFD BLOCK Test OSD CHAR Test SWITCH Test LED Test ENCODER Test VIEW ERRORLOG Clear NON VOL SRAM Set Triggers x3 TRIGGER 0 TRIGGER 1 Expand Output MUTE MIC DSP CONN Test Set FAN Test Show Serial NUM PIC SN Validity Flash Burn Test Thermostat Test Set Co
260. ite version of the S video the sum of Y C The internal U28 multiplexer selects whether the OSD is in the path or whether the input is fed straight through controlled MTHRU Output impedance is structured as with the luma output Standard 1Vp p video input levels produce 1Vp p output on the composite and luminance channels when terminated in 75 ohms or 2Vp p open circuit The composite main output is fed to the output RCA jack on the Video Out board via ribbon cable J16 6 21 8 Service Manual Zone Composite S video Zone video circuitry is structured similarly to main video but without OSD capability Refer to the previous section for additional description Multiplexers U11 and U10 U9 are addressed by the ZVID_SELn and ZSVID_SELn bits respectively to select an independent record source but otherwise operate like their counterparts in the main path There is no dc restorer in the zone path so back porch dc level varies with average picture level due to input ac coupling The multiplexer internal to output amplifier U13 allows the zone S video luminance to be shut off when a composite source is in use The zone composite output is fed to its RCA jack on the Video Out board via ribbon cable J16 Component Video Switcher Component video switching is performed by means of relays to maximize signal fidelity and format compatibility There is no active circuitry in the component video path Three sets of component input
261. le 5 3 8 Service Manual byte written AAAAAAAA 1010 1010 1010 1010 1010 1010 1010 1010 byte read AAAAAA8A 1010 1010 1010 1010 1010 1010 1000 1010 Since data bit 5 is the one that is not correct checking the schematics for the SRAM used for pair 0 DSPA and DSPB that has data bit 5 on it will show which SRAM is associated with the failure See the chart below for further reference SHARC SRAM PIN ASSIGNMENTS SHARC PAIR 0 SHARC PAIR 1 DSPA PS1 amp DSPB PS2 DSPC PS1 amp DSPD PS2 Data Bits U20 U19 U18 017 012 011 010 U9 00 Pin 6 024 016 08 00 024 016 08 00 01 Pin 7 025 017 09 01 025 017 09 D1 02 Pin 10 D26 D18 D10 D2 D26 D18 D10 D2 03 Pin 11 027 019 011 03 027 019 011 03 04 Pin 22 028 020 012 04 028 020 012 D4 D5 Pin 23 029 021 013 05 029 021 013 05 D6 Pin 26 030 022 014 06 030 022 014 06 D7 Pin 27 D31 D23 D15 D7 D31 D23 D15 D7 P N 350 12456 ICSM SRAM 128KX8 12NS 3 3V SOJ Note The reference designators are from MC8 DSP board revision 1 Lexicon P N 710 15300 Error Log An error log or ring buffer containing a log of the last 20 13h failures is available If the error quantity exceeds 20 additional error messages are stored at the first location in the buffer FIFO The error log is stored in the non volatile section of SRAM and is not able to display all diagnostic errors For example SHARC SRAM failures not repo
262. lect the test the VFD will display all As as shown below 2 Rotate the encoder knob to view other characters exit the test press the Mode button Block Test Note When rotating the encoder knob sometimes pixels on the VFD will randomly flicker very briefly This is normal operation The Block Test illuminates all pixels on a single segment of the VFD The encoder knob is then used to move the block to each segment Press the EFFECT DOWN button to execute the test The display will read EP Rotate the encoder knob clockwise to move the block through all VFD locations At the end of the line the block will wrap to the next line In the case of second line the block will return to the starting point on the first line 5 16 Lexicon Switch Test This test will verify all twenty two front panel switches are working Each button on the front panel is pressed and the VFD will indicate which front panel button has been pressed Example Switch Test MODE DN in the second line on the If the button has an LED associated with it the LED will illuminate When all switches have been tested the bottom half of the display will indicate completion Encoder Test The Encoder Test verifies the operation of the encoder knob including direction and the twenty four positions It is designed so that if there was a bad posi
263. lt 31 125 tt _ OSD C IN SCOSD 35 559999 RIH Ri 2 A5 40 3 NC s 050 C OUT R129 VIN VOUT 681 2 C5 10 16 NC 38 39 NC 10 16 lt 2 15 VKIN VKOUT 32 R140 196 145K rim usvwc 14 050 CSYNC lt 100K 16122 623 s SMHSYN 12 VSYNC 15 080 VSYNC OSD VSYNC T 6 D3 S YNC 13 16 OIC 57 MB90092 vog 3 NC 21 5 050 amp 4 08 6 OSD_R1 4 D8 6127 OSD_G1 4 08 15 0 20 FILTERS 7 C3 pos 22 7 85 OSD_TSC ADR0 0 ADR1 94 A1 D 7 0 gt VIDEO DATA 10 SIN ADR2 55 A2 7 C3 8 D4 VIDEO_SCLK 9 ADR3 96 AS FONT MEMORY 8 57 4 OCS ADR4 58 AS ADR5 59 ADRZ 60 AT 5VV 5VV 19 61 A8 29 010 NC1 8 Mh 25 63 9 12 32 2 A0 VCC NC 26 wc3 10 64 10 1 1114 lt 172 NC 27 wc ADR11 66 A11 A2 10 45 13 DO OSD TEST 510 NC 28 67 A12 A3 9 14 D1 5 5 ADR12 88 5VV 8 A3 001 45 02 ADR13 S DQ2 43 READ 69 5 7 5 pos 17 03 70 15 4 6 18 04 ADR15 14 31818MHZ 004 78 TEST 5 AT pos 19 05 ADR47 72 NC VDD 8 27 20 06 Be 44 DATAO ADR18 73 3 NTSC_EN 7 C5 28 e
264. lyzer Shielded balanced audio cable and a XLR female connector on one end and an appropriate connector on the opposite end for connection to a Low Distortion Analyzer 4 Shielded audio cables with RCA connectors on both ends 1 1 8 Service Manual 2 Shielded audio cables with XLR male on one end and XLR female on the other e Digital S PDIF audio cable with RCA connectors on both ends e Digital S PDIF audio cable with optical connectors on both ends e 2 Video cables with RCA connectors on both ends e 2 Video cables with S video connectors on both ends e 2 Video cables with 3 wire component RCA connectors on both ends e 8 AC power cord see Chapter 7 for list of part numbers Required Tools The following is a minimum suggested equipment list required for performing disassembly assembly and repairs e Clean antistatic well lit work area with grounding wrist strap e Number 1 Phillips tip screwdriver magnetic tip preferred 14mm socket nut driver e 2 5 mm Hex Driver 3 16 Hollow nut driver e Magnification glasses and lamp e Surface Mount Technology SMT Soldering Desoldering bench top repair station 1 2 Lexicon CHAPTER 2 GENERAL INFORMATION Periodic Maintenance Under normal conditions the MC 8 requires minimal maintenance Use soft lint free cloth slightly dampened with warm water and a mild detergent to clean the exterior surfaces of the unit Do not use alcohol
265. mmable connector on detachable screw terminals 12 VDC 0 5 amps each 2 9 pin D sub connectors 90 250 VAC 50 60Hz 60W universal line input detachable power cord MC 8 Dimensions amp Weight Height with feet 3 81 inches 97mm Width 17 3 inches 440mm Depth 14 85 inches 377mm Weight 170 7 6kg 3 3 8 Service Manual MC 8 Balanced Dimensions amp Weight Height with feet 5 04 inches 128mm Width 17 3 inches 440mm Depth 14 85 inches 377 Weight 24lb 10 7kg Rack Mounting Optional brackets are available for installation in a standard 19 equipment rack 2 rack units required for MC 8 3 rack units for MC 8 Balanced Environment Operating Temp 0 to 35 C 32 to 95 F Storage Temp 30 to 75 C 22 to 167 F Relative Humidity 95 maximum without condensation Remote Control Hand held backlit infrared remote control unit preprogrammed amp learning Requires two AA batteries alkaline batteries recommended Specifications are subject to change without notice 3 4 Lexicon CHAPTER 4 FUNCTIONAL VERIFICATION PERFORMANCE VERIFICATION This section describes a quick verification of the operation of the MC 8 and the integrity of its analog and digital audio signal paths Tests that are specifically included for the MC 8 Balanced version can be omitted when testing an MC 8 Dangerous voltages capable of causing death are present in this unit Use extreme cau
266. n Video board to ground In order to properly test the MC 8 as described in this document the MC 8 must be in Diagnostics mode Perform the following procedure to enter the Diagnostics mode To enter Diagnostics mode 1 Connect the video monitor to the composite output This will allow full viewing of the Diagnostics menus of the MC 8 Press and hold the front panel Main VCR and Zone 2 VCR buttons while powering up the MC 8 with the main power switch on the back of the unit When LEXICON appears on the display release the buttons on the front panel The display on the MC 8 front panel will read DIAGS MENU FUNCTIONAL TESTS The full Diagnostics Menu will be displayed on the monitor Analog Inputs To Main Zone Outputs Test This test will verify the audio path between the RCA paired inputs labeled 1 to 8 to all analog outputs both RCA and XLR Test 1 De 00 b OY Ol 0 Connect the low distortion oscillator output to the left and right audio inputs labeled 1 on the rear panel of the MC 8 With the amplifier powered off connect the RCA left and right front outputs of the MC 8 to the amplifier left and right inputs Connect the outputs of the amplifier to the pair of speakers Using the remote control Menu arrow scroll through the Diagnostics Menu and select the Audio Tests In the Audio Test menu highlight Audio Input 1 Test and then press the Menu arrow to engage the test
267. nd the user is able to type in commands or run debug scripts then the port is working Thermostat Test The thermostat test verifies the temperature sensor installed at U66 on the main board To verify the IC s functionality a shorting jumper is installed at W1 This shorting jumper changes the resistance presented at pin 2 of the temperature sensor The temperature sensor sets the temperature it detects via a resistor divider network Grounding pin 2 will cause the diagnostic test to verify the TEMP signal lines have changed state 1 Upon entering the test the VFD will indicate THERMOSTAT TEST Insert Jumpers 2 If the test passed when the button is pressed the VFD will indicate THERMOSTAT TEST Test PASSED The diagnostic test will then prompt for the jumper to be removed THERMOSTAT TEST Remove jumpers If the jumpers are not removed the test will prompt a second time to have the jumpers removed THERMOSTAT TEST Jumpers not removed Fan Test The fan test verifies operation of the fan 1 When you select the test the will indicate SET FAN FAN OFF 2 Rotate the encoder knob clockwise and the VFD will indicate SET FAN FAN ON The fan will be spinning 3 Rotate the encoder knob counter clockwise and the VFD will indicate SET FAN FAN OFF The fan will stop spinning 8 Service Manual IR Remote This test verifies the functionality of the IR Rem
268. nectors and volume control capabilities A pair of high quality speakers High quality video monitor with composite RCA S video and component RCA and BNC input connections CD disc for use as a test audio source DVD disc for use as a test video source DAT Recorder for testing the digital output of the MC 8 Variable AC power supply 2 amp minimum Digital multimeter DMM 3 5 digits 0 5 or better accuracy Low Distortion Audio Oscillator with single ended and balanced analog outputs switchable 40kHz low pass filter or band pass 20 20 2 filter and output THD N lt 0 001 100 MHz oscilloscope S PDIF Digital Distortion Analyzer with coaxial and optical input S PDIF Digital Function Generator with coaxial and optical output Low Distortion Audio Analyzer with switchable 30Hz high pass filter or band pass 20 20 2 filter capable of measuring THD N lt 0 01 DVD CD player with RCA analog L R outputs digital coaxial outputs optical outputs and composite S video and component outputs 2 RS232 wrap around plugs These are made by connecting pins 2 amp a female 9 connector MC 8 remote control Required Cables Shielded audio cable with an RCA connector on one end and an appropriate connector on the opposite end for connection to a Low Distortion Audio Oscillator Shielded audio cable with an RCA connector on one end and an appropriate connector on the opposite end for connection to a Low Distortion Audio Ana
269. nstant Cycle Normal Operation The extended diagnostic tests that are the same as in the power on tests are not described here 5 13 8 Service Manual FUNCTIONAL DIAGNOSTIC SUITE The manufacturing suite is available from the top level DIAGS MENU and the FUNCTIONAL TESTS item is selected 1 When you select the menu item the VFD will display FUNCTIONAL TESTS START ALL TESTS There is only one menu item in this menu and selecting it will start the sweep through the whole repair suite As long as there are no errors the test will continue until the tests requiring an operator response are encountered If there is a failure the offending test will cycle and the error code will be displayed on the second line For example if the DEC FPGA verify fails the VFD will display DIAGNOSTIC TESTS DEC FPGA E 001E 2 continue hit the button Some tests require you to help with the test by pressing the MODE key or by turning the encoder to iterate through the test 3 Upon completion all of the tests the second row of the VFD displays Pass or RS232 Wrap Test This test verifies the RS232 ports are working by comparing the transmitted signal at pin 2s of J5 to the received signal at 3s J5 If the signals are the same the test passed In order to test this circuit 2 RS232 Wraparound plugs are needed and must be installed at the female D9 connectors J4
270. ocedure testing will be performed with the top cover removed and the unit turned on Due to risk of shock do not remove the cover with the unit powered on Test Set the variable AC supply to 120 volts Verify that the 8 is powered off at its rear panel power switch Connect the power cord between the supply and the MC 8 Remove the top cover Check for power supply shorts to ground Turn on the MC 8 using the rear main power switch Power on the unit at 120VAC Verify the current draw on the Variac does not exceed 0 6 amps c gu 200 eo Using a DMM measure all the power supply rails as stated in the tables below being sure to use the MC 8 chassis as ground 10 Verify that all the voltages are within the tolerance range shown below Main Board Supply Rail Tolerance Test Points 5VD 4 75 5 25 Red wire at J45 behind front panel center at volume knob left to ground Battery 22 5 Right side to the Left of U69 measure the top of the battery to ground 15V 15 00 16 95 Yellow wire at J32 to ground 15V 14 25 15 75 Blue wire at J32 to ground 5VAD 4 75 5 25 Red wire at J32 to ground 4 15 5 25 Gray wire J32 to ground 4 2 Lexicon Video Board Supply Rail Tolerance Test Points 5VAD 4 75 5 25 Red wire at J17 on Video board to ground 5VA 4 75 5 25 Black wire at J17 on Video board to ground 4 75 5 25 Gray wire J17 o
271. ol register can be used to determine the starting address of the undefined instruction If the trap error occurs an attempt will be made to blink the STANDBY LED using a rate of a single blink per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging EPROM Checksum Test The EPROM Checksum test verifies the 2 Meg 27C020 EPROM U3 on the Memory Board has the correct program by adding up all the values in each bank of the EPROM The test verifies the separate banks and the bank switching of the MC8 B The checksum of each bank is reported to the Serial Debug Port The test verifies that the calculated checksum in each bank matches the checksum value stored in the EPROM If an error occurs an attempt will be made to blink the STANDBY LED using a rate of two blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging Z180 SRAM Test The Z180 SRAM test performs non destructive testing on the 256k SRAM U90 on the Main board on page 2 of the main board schematics The non destructive test first saves the data in the location being tested Then that location is tested by writing and reading patterns 0x00 OxFF 0x55 OxAA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 and 0x80 The original data is then returned to the SRAM and the next location tested Once each location in the SRAM is verified a counting memory check is done throughout the SRAM to test b
272. onent 1 video input jack to the main component video output jack of the MC 8 14 Press the remote OSD button This will turn off the on screen video information from the MC 8 and allow viewing of the video from the DVD player 15 The video path is now set for testing Test 1 Load a disc into the DVD player and press play 2 Verify a clean undistorted picture appears on the monitor screen 3 Pause the DVD player 4 The above procedure should be repeated to test the remaining two component Video inputs To do this repeat the procedure changing the Input selected in step 14 to the appropriate Input LEXICON AUDIO PRECISION ATE SUMMARY This chart which begins on the next page represents a summary of Audio Precision test settings and parameters used by Lexicon in production testing of all MC 8 products This chart as well as the MC 8 ATE summary is provided as a reference and supplement to bench test settings found in the rest of the Performance Verification section 0 0 Tests Digital Generator Digital Analyzer Switcher Module MC 8 B Setup See Bal Gnd Typical Upper Lower Clock Sample Audio Name Note Left Right Freq Hz Z out Unbal Float Level Measure Reading Limit Limit Filter Imp Band Bin A Out B
273. ontinue to be illuminated The diagnostics will attempt to continuously execute the failed test a test loop to keep the signal lines active as an aid in debugging the failure Serial Debug Port The Serial Debug Port is available to provide diagnostic status to be viewed on an external PC from the D9 connector labeled RS232 2 Using a terminal or a PC running a terminal program connected to RS232 2 the progress of the diagnostics can be monitored and test failure information is reported Also there is an error log can be dumped to the serial debug port while in extended diagnostics The serial protocol is 19 200bps 8 N 1 8 data bits no parity and 1 stop bit Serial Debug Cable The cable required to connect the RS232 2 serial debug port to the computer is a straight through serial interface cable null modem adapter or cable should not be used The MC8 B RS232 on the rear panel is a D9 female so one end of the serial cable must be a D9 male The other connector on the cable depends upon the RS232 connector used on the computer The computer may have a D9 or a D25 male connector Typically computers have a D9 for COM 1 and a D25 for COM 2 However some newer computers use a D9 for both COM 1 and COM 2 The COM port used on the computer does not matter however you must ensure that the serial communications program being used has the correct computer COM port selected Serial Debug Program The serial debug program c
274. ontrols the communication from an MC8 B to a computer The program allows a user to view activity of the unit and to control the unit The debug program is used extensively to perform audio and video testing of a unit in the audio and video ATE programs This section will demonstrate an example of using debug to troubleshoot a SHARC failure The MC8 B has four SHARCS on the DSP board organized as pairs pair 0 and pair 1 Each pair of SHARCS has four SRAMs and SDRAM In the case of a SHARC SRAM failure the debug program can be used to determine which of the four SRAMs is defective Power on the unit with the RS232 2 port connected to the computer while the computer is running a terminal program with the correct COM port and protocol enabled When the unit reports the SHARC SRAM failure and has entered a diagnostic loop with the same error data continuously cycling on the monitor power off the unit The data will appear as follows SHARC Failed Test test num 00000003 test phase 00000000 sharc address 02 000 sharc byte written AAAAAAAA sharc byte read AAAAAA8A Sharc Error Code 0318 sharcpairO_ps2 sram sharcpairO_ps2 sram test failed Error code 0318 DIAG FAIL ShSRAM 02 0318 Compare the data from the sharc byte written to the sharc byte read If the failure is a defective SRAM the typical failure mode is to be off by one bit and the byte comparison will determine which IC is at fault In the above examp
275. or All signals are connected to the Switch LED Board It then passes signals as required to the IR Encoder Board and the VF Display The signals used by the Switch LED Board are as follows FP_RST this prevents the LEDs from lighting when the unit is first powered up until the host is initialized SWRD LEDWRHR when this signal is high the MUX generates the enable for reading the Switch Buffer When it is low it generates write strobes to the LED Registers and the Switch Column register In order to read the switches the host must first select a column e Front Panel data bi directional e Front Panel address used by the MUX Signals used by the VF Display are as follows EN BUF chip select to the display e Data byte wide e Address two address bits Address determines whether an access is a read or a write Signals used by the IR Encoder Board are as follows IR auxiliary data from the rear panel connector This is optically coupled with the incoming IR signal at the IR receiver e The IR acknowledge LED bit This comes from the PIC and is used to indicate that the unit is detecting an infrared signal e System On and Overload LED bits Encoder 0 1 these are the output of the front panel encoder knob They are read and interpreted on the main board VFD ENABLE gt gt VFD ENABLE IO DATA BUFFER FRONT DATA DATA VFD DATA
276. ote by pressing on the remote and verifying that the VFD displays which IR remote button was pressed The VFD displays in hexadecimal the code received when a remote key is pressed The hex display on the VFD remains unchanged until another remote key is pressed While the remote key is being pressed the IR acknowledge LED will flash and the VFD displays the message IR without the quotes next to the hex value When you have successfully exited the test the VFD will display an arrow on the left side pointing to the word REMOTE 1 When you select the test the display will read IR REMOTE Remote Test All buttons except for Mode will be inactive 2 When you hold down a remote button such as the DVD 1 button the display will read IR REMOTE Remote Test 20IR The 20 is the hex code for the DVD 1 button IR is displayed to indicate the remote is currently transmitting a signal and the amber IR acknowledge LED will be flashing As different buttons are held down the hex code will change indicating which is being pressed VFD Character Test The combination of the Character Test and the Block Test verifies that all display segments are functioning The Character Test places the same character on all VFD segments The ENCODER knob is then used to change the character The test has sufficient variation of characters to verify complete functionality of the VFD All characters present in the VFD can be observed 1 When you se
277. ou DB1 A12 A20 C19 A11 A19 C18 DB1 A10 A18 A9 C17 DB1 A17 DB1 A7 C16 DB1 A6 A16 DB1 A5 C15 ZA 15 0 TAVHCT244 4 __ 1 D4 2 D8 4 D7 5 C7 6 C6 8 C6 12 A6 D 5 75 2 18 081 5 DB1 A 13 0 DBI A 15 4 v 16 DBI 6 14 1 218 101 2003 4 08 5 7 6 7 8 86 Bina va 12 2081 1 8 12 4 ZDB1 RD A12 74VHCT244 11 NOTES 1 2 D1 2 D3 4 C8 5 B7 6 B7 8 B6 O WR 1 y 9 2081 ZDBT WR A2 Y2 7 DB1_A0 C10 1 COMPONENTS ON THIS PAGI ED ON 5 1 2 DB1_AUDIO9 A10 3 DB1 A4 19 Y4 E DB1 AUDIO10 9 1 96 ZDB1 017 01 3 ZDB1 DO C8 U76 ZDB1 D1 TAVHCT244 208102 C7 A Y1 18 DBI A6 708103 A7 A2 2 18 DBI ATO 7581 54 C6 14 DB1 AI 708105 208106 C5 208107 UIT Ca TAVHCT244 DB1 AUDIO SPO A4 m 9 DB1 C3 M A3 5 AO C2 8 3 DBI AT DB1_CS A2 19 G C1 0776 DB1_RST EURO64 F TAVHCT245 ZD 7 0 2 18 ZDB1 DO D3 2 D6 3 D7 5 A7 6 B6 8 A6 E SAT Bt 18 See A2 B2 4 16 2081 02 5 B4 15 208103 6 5 Bs 14 2081 D4 Flee 13 2081 D5 8 6 86 12 ZDB1 D6 Ba 11 ZDBi D7 081 CS 19 178 2 D1 2 D3 3 D7 3 C7 5 A7 6 A7 8 A6 12 A7 DIR 0758 CIS 3 03 lexicon zoek 0
278. over any surface Insert circuit boards with the proper orientation Use static shielded containers for storing and transporting circuit boards exicon These service instructions are only intended for use by qualified personnel Do not perform any servicing other than 3 Oak Park that contained in these instructions unless qualified to do so Bedford MA 01730 1413 USA Refer to the Safety Summary on the previous page prior to Telephone 781 280 0300 performing any service Fax 781 280 0490 www lexicon com Lexicon and the Lexicon logo are registered trademarks of Customer Service Harman International Industries Incorporated Telephone 781 280 0300 Sales Fax 781 280 0495 U S patent numbers and other worldwide patents issued and pending Service Fax 781 280 0499 Product Shipments 16 Progress Road 2005 Harman International Industries Inc All rights Billerica MA 01821 5730 USA reserved H A Harman International Company This document should not be construed as a commitment on the part of Harman Specialty Group The information it contains is subject to change without notice Harman Specialty Group assumes no responsibility for errors that may appear within this document No 070 17536 Rev 0 08 05 5 CHAPTER 1 REFERENCE DOCUMENT amp EQUIPMENT LISTS 1 1 CHAPTER 2 GENERAL 2 222 0000002
279. p contains internal shift stages plus a set of output latches The shift clock and data are VIDEO_SCLK and VIDEO_DATA shared in common with the OSD All VIDEO_DATA gets accumulated in the shift stages but the 24 output latches are only updated on the rising edge of VIDEO_REG which acts as a chip select for the control registers All control bits are initialized to 0 at power up by VIDEO_RST Font Flash Programming Interface Three additional shift registers are dedicated to the in system programming of flash memory U31 which holds the bitmapped OSD font pattern U22 is interfaced to the memory D 7 0 bus and U21 U30 are interfaced to the A 15 0 bus The shift stages of U22 21 and 30 receive VIDEO_SCLK and VIDEO_DATA in common with the OSD and the video control register chips and their serial to parallel transfers are clocked by OSD_CS in common with the OSD chip U32 However in normal operation the tri state outputs of these chips are disabled so they do not drive the buses and the only bus activity is the fetching of font patterns from U31 over the A 15 0 D 7 0 buses under the control of OSD U32 When necessary the host processor on the main board manages the programming of the font flash memory by means of control register bits OSD_TSC and VROM WhH In normal operation both bits are de asserted set high When OSD 5 is asserted low the bus interface of OSD U32 is disabled and the bus interface of the three shift registe
280. ple rates MAIN SCKI which is 64xFS and MAIN ADC FSI which is 1xFS where FS sample rate Zone 2 D A converter The AK4395 24 bit delta sigma stereo D A converter operates up to 192 kHz The DAC is configured through its serial control port pins 8 10 11 with a separate Reset pin The output of the DAC passes through a second order low pass filter with its frequency at 83kHz The filter is flat out to 20 2 It has an overall gain of 7 4dB when measured at the test points This means a 0 dBFS signal at the D A converter will be 4Vrms going into the analog switches ADG451 analog switches select either the output of the respective DAC or the analog input source directly The selected signal goes to the PGA2310 output level control and driver These are special volume controls that run from 15 volt supplies and have a built in op amp driver Zone 2 analog output has a maximum output level of 4 Vrms The signal passes through a muting relay on the way to the output jacks The relays are controlled by the ZONEOUT MUTE signal 8 Service Manual Main D A Converters There are eight outputs for the Main Audio Path The D A circuitry is shown for two outputs on each sheet The circuitry is identical for all eight outputs The AK4395 is the same 24 bit D A converter that operates Zone 2 The Analog FPGA sheet 4 is the source for the clocks and data for the D A converters The MCLK is at 256 times the sample rate F
281. provided for use with an optional daughter card with 1 8 inch microphone connectors and preamplifiers A DG411 analog switch can select Mic inputs 1 and 2 to be passed to the Main Input level control and A D converter When the Mic input is selected the Analog inputs are disabled by bringing MAIN_ANLG_EN low The Main Input level control is the PGA2311 which has a range from 31 5 to 95 5 dB 0 5 dB steps The PGA2311 operates on 5 volt rails and cannot handle signal levels greater than 7 5 Vpp Two dual op amps provide the left and right differential audio signals to the A D converter The op amp circuits bias the signals at 2 5 V and attenuate it by 7dB This means a 2 Vrms signal at the output of the level control will be equivalent to 0 dBFS after the A D conversion The AK5383 stereo A D converter incorporates a dual bit deltasigma architecture It outputs 24 bits at a 96kHz sample rate under normal operation The serial audio data from the A D converter goes directly to the digital part of the Main board The A D also provides a signal to mute the Main analog inputs VC MUTE when it is going through calibration during power up or sample rate changes Control signals are used for reset MAIN RST and to place the converter in 88 2k or 96k sample rate mode MAIN 96 EN The Audio FPGA sheet 4 provides three clocks MAIN MCKI which is 256xFS for 44 1k and 48k sample rates 128xFS for 88 2k and 96k sam
282. r part of the boot process when the unit is powered on from the rear panel The FPGA is programmed by the host through the Memory CPLD The Audio FPGA is programmed the host through the FPGA Any FPGAs residing on daughter boards programmed through the Audio FPGA It is important to understand that until the FPGAs have been programmed most of the unit including the front panel and on screen display are in reset There are LEDs that light to indicate when the programming for each FPGA is complete Z180 ADDRESS Z180 DATA MEMORY CPLD 2180 gt HOST INTERFACE gt FPGA gt 7180 HOST INTERFACE 10 FPGA PROGRAM PINS PROGRAM AUDIO FPGA 2180 HOST INTERFACE PROGRAM PINS DAUGHTER BOARDS FPGA PROGRAM FPGA PROGRAMMING DAUGHTER BOARD 0 DAUGHTER BOARD 1 DAUGHTER BOARD 2 6 3 8 Service Manual FPGA The I O FPGA has a byte wide data path for the host interface It provides the following functions e Handles the entire space memory map for the system e Generates the chip selects for all peripheral devices that the host communicates with over the I O data bus e Autom
283. r is rotated to display the desired tests Press the Mode button to move down through the menu selections and to execute the desired diagnostic test Use the Mode button to back up through the menu selections similar to an escape ESC button on a computer keyboard Types of Tests The extended diagnostic tests fall into two categories functional and repair The functional diagnostic tests are required to functionally verify an MC8 B and are performed on every unit The repair or troubleshooting category is for troubleshooting defective units The repair tests are used only if there is a failure The repair tests can be used to help isolate the source of failures so that units can be cost effectively fixed Two groups of functional tests are executed on every MC8 B Loop Tests and the Functional Test Suite These tests comprise the automated set of diagnostic tests used to verify functional operation of every unit All of the diagnostic tests in the loop tests and in the functional test suite are run in sequence If there is a failure the failing test will loop to allow the electrical signals to be active for troubleshooting The operator can optionally continue the diagnostic tests to see what other diagnostic tests might be failing User Interface The user interface consists of a set of menus The top menu is the DIAGS MENU and is shown in the top line of the VFD display To view the available menu items turn the encoder knob in either direc
284. rforming these tests assures that the audio signal paths in the MC 8 meet published specifications These tests will verify the performance specifications of the A D and D A circuitry gain frequency response THD N S N ratio and dynamic range when applicable of each channel Analog Audio Inputs To Main Zone RCA Output Tests These tests will verify the specifications of the Main Zone RCA output channels Setup 1 Connect an audio cable between the output of the Low Distortion Oscillator and the 8 left RCA input 1 Connect an audio cable between the left front RCA output of the MC 8 and the input of the Distortion Analyzer Using the MC 8 Remote Control Menu arrow scroll through the Diagnostic Menu and select the Audio I O Tests In the Audio Test Menu highlight Audio Input 1 Test and then press the Menu arrow to engage the test The MC 8 is now set to route audio from the left and right RCA inputs labeled 1 to all RCA analog outputs Gain Test GAIN Test Pe Jo x Apply a 997Hz signal 4Vrms to Analog input labeled 1 Set the scale on the Distortion Analyzer to measure 8Vrms signal level Turn all the filters off on the Analyzer Filter not required for Gain Test Verify that the output level measurement from the MC 8 is between the range of 6 60Vrms and 8 90Vrms Note this level Total Harmonic Distortion Noise Test THD N 1 Adjust the scale on the Distortion Analyzer to measure 0 001
285. rms Level 4 10 4 47 3 73 40kHz LP 100k lt 10 gt 500k 9 10 13 External 96000 Digital DIG ZONE COAX3 IN 44k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 13 External 96000 Digital DIG ZONE COAX3 IN 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 n a dBr THD N gt 108 00 103 00 140 00 100k 10 22k 9 10 13 External 96000 Digital DIG ZONE 4 IN 96k TO ZONE OUT DIG ZONE COAX4 IN 44k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 Vrms Level 4 10 4 47 3 73 40kHz LP 100k lt 10 gt 500k 9 10 n a 14 External 96000 Digital DIG ZONE 4 IN 44k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k 9 10 14 External 96000 Digital DIG ZONE COAX4 IN 96k TO ANLG ZONE OUT DYNRNG 60 00dBFS 60 00dBFS 997 THD N gt 108 00 103 00 140 00 None 100k 10 22k 9 10 n a 14 External 96000 Digital DIG ZONE IN 96k ANLG ZONE OUT DIG ZONE OPT1 96k TO ANLG ZONE OUT GAIN 40 00dBFS 0 00dBFS 997 n a n a Vrms Level 4 10 4 47 3 73 40kHz LP 100 lt 10 gt 500k 9 10 11 External 96000 Digital DIG_ZONE_OPT1_IN_96k TO ANLG ZONE OUT THD 1 00dBFS 1 00dBFS 997 THD N lt 003 005 0002 40kHz LP 100k 10 gt 500k
286. rms signal level 2 Using the output level from step 4 of the Gain Test set the Distortion Analyzer for a 0dB reference to check Frequency Response for the MC 8 Turn the filter on the analyzer off Sweep the oscillator frequency from 10Hz to 40kHz Verify the signal levels are 0 05dBr to 0 10dBr 10Hz 20kHz and 0 05dBr to 0 50dBr 20kHz 40kHz of reference level over the entire sweep Note these levels Dynamic Range Test DYNRNG Using steps 1 3 of the Gain Test set the oscillator to GOdBFS and a THD N level measurement lt 108dBr Test the remaining inputs Use the GAIN THD FREQ and DYNRNG tests described above to test the remaining digital inputs three coaxial and four optical When testing the optical inputs be sure to use the appropriate digital cable Digital Inputs to Main Zone XLR Outputs Test Note This test is for MC 8 Balanced units only Setup 1 Connect a digital audio cable from the output of the Digital Function Generator to S PDIF coaxial input 1 on the rear of the MC 8B 2 Connect an audio cable between the left front XLR output of the MC 8B and the input of the Analog Distortion Analyzer 3 Using the MC 8B Remote Control Menu arrow scroll through the Diagnostic Menu and select the Audio I O Tests 4 Inthe Audio Test Menu highlight S PDIF Input CX number 1 Test then press the Menu arrow to engage the test The MC 8B is now set to pass digital audio from the S PDIF
287. rs is enabled 035 disconnects OSD 8 from 032 and the OSD chip select remains high due to internal pullup so the OSD chip will be isolated from subsequent serial transfers involving 050 5 The host loads the shift registers with memory address and data patterns which are transferred to the parallel holding registers on the rising edge of OSD CS With the tri state outputs enabled address and data are driven onto the memory buses Data is written to the flash rom when the host asserts VROM Digital Audio Input Ports The Video board incorporates two optical S PDIF connectors CP1 CP2 and four coaxial S PDIF connectors J14 J15 with associated amplifiers U7 U8 S PDIF signals are fed to the main board via J19 Power and Control Interface J19 is the control and status interface to the host J17 supplies power from a connector on the main board The main video 5 volt rail is 5VV a filtered version of system 5VD which also supplies relay coils through FB1 The negative rail is 5VV derived from the main board 5VA The sync stripper U3 is specially powered from a well regulated rail 5VAS derived from the main board 5 6 24 CHAPTER 7 PARTS LIST PART NO DESCRIPTION QTY EFFECT REFERENCE Main Board Assembly 022 14458 PL MECH ASSY VCO MC12 B 1 000 J31 202 09794 RESSM RO 0 OHM 0805 31 000 R102 108 113 118 123 R181 183 185 186 192 R194 196 197 202 313 R314 320 324 343 362 R365 383 388 41
288. rted to the error log Every failure stored in the error log has six parts NN E aYYYYYY wZZZZZZ rQQQQQQ NN Error Log Number The error log location number hexadecimal It goes from 00 to 13 Turning the encoder knob clockwise allows one to scroll through all twenty error log locations E Failure Number The E stands for error and the hexadecimal after the E indicates test number from the list on the next page 5 4 Lexicon 1 Error Code List NO_ERROR 0x0 ADDR_FAILURE 0x1 DATA_FAILURE 0x2 TIMEOUT_FAILURE 0x3 COUNTER_FAILURE 0x4 VOL DATA FAILURE 0x5 OPCODE FAILURE 0x6 IO FPGA ID NO MATCH Ox7 DAR FPGA ID NO MATCH only for MC12 0x8 AUDIO FPGA ID NO MATCH 0 9 ID NO MATCH only for MC12 VFD_TIME_OUT 0xB VFD_RAM_ERROR OxC TEST INCOMPLETE OxD RS232 WRAP FAILURE OxE SRAM PREBURNIN FAILURE 0x13 SRAM_BURN_IN_FAILURE 0x14 EPROM_CHKSUM_FROM_FLASH 0x15 SRAM FAILURE 0x16 FIFO ERROR OVERRUN 0x17 PIC SN INVALID 0x18 FLASH BURN FAIL 0x19 FLASH BURN NO ROOM LEFT 0 1 FLASH_BURN_NOT_FLASH_PART 0x1B SHARC_TIMEOUT_REBOOT 0x1C DSP_FPGA_ID_NO_MATCH 0x1D DEC FPGA ID NO MATCH Ox1E DIAG TEST EXIST 0x20 THERMOSTAT FAILURE 0x21 ERROR ID BAD VALUE 0x40 ERROR SEMA CREATE 0x60 549400 NO START MESSAGE 0x100 549400 N
289. s connected Consult the dealer or an experienced radio television technician for help SUMMARY The following general safety precautions must be observed during all phases of operation service and repair of this unit Failure to comply with these precautions or with specific warnings elsewhere in these instructions violates manufacturer safety standards and intended use this unit Harman Specialty Group assumes liability for failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the unit chassis and cabinet must be connected to an electrical ground The unit is equipped with a three wire grounding type plug It will only fit into a grounding type power outlet This is a safety feature If you are unable to insert the plug into the outlet contact your electrician to replace your obsolete outlet Do not defeat the safety purpose of the grounding type plug DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the unit in the presence of flammable gasses or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove unit covers Qualified maintenance personnel must make component replacements and internal adjustments Do not replace components with the power cord connected Under certain conditions dangerous voltages may exist even with the power cord removed To a
290. stics will now automatically perform the PIC S N test which verifies that the software ID programmed into the PIC microcontroller is within the range allowed per the Lexicon specification sheet 5 18 Lexicon REPAIR DIAGNOSTICS SUITE View Error Log This is not a test but it enables you to view the contents of the error log Turning the encoder knob allows you to view the error log contents Clear Non Volatile RAM This is not a test but allows you to clear out the error log contents and other areas of RAM that are not cleared on a power up 1 When you select this menu item the display will show CLEAR NON VOL SRAM Confirm Press MUTE When MUTE is pressed the second line will display Initializing RAM for a second then it will display TEST COMPLETED LOOP TEST SUITE The Loop burn in suite is available from the top level DIAGS MENU when the LOOP TESTS item is selected 1 When you select LOOP TESTS the VFD will display LOOP TESTS NON_VOL RAM SETUP The NON_VOL RAM setup initializes the non volatile section of the SRAM with a byte pattern that is verified by the loop tests As the unit is in burn in this byte is continuously verified ensuring that the register section of the SRAM continues to hold data This will also set a flag for programming the decoder and video flash memories at the beginning of the burn in loop the first time the test is run Rotating the encoder knob will display t
291. surement lt 108dBr Test the remaining inputs Use the GAIN THD FREQ and DYNRNG tests described above to test the remaining digital inputs three coaxial and four optical When testing the optical inputs be sure to use the appropriate digital cable 4 8 Lexicon VIDEO INPUT OUTPUT TESTS These tests will verify that all thirteen video inputs and five video outputs pass video There are three different video paths to be tested in the MC 8 composite S video and component Composite and S video paths each have five inputs and two outputs Component paths have three inputs and one output The following tests will verify that the MC 8 is passing clear undistorted video It is not necessary to enter the Extended Diagnostics as was done in the audio tests Composite Video Input to Composite Video Outputs Test This test will verify the composite video switching function of the MC 8 Setup ON Oa Connect the composite video output from the DVD player to the MC 8 s composite video input 1 Connect the main composite output of the MC 8 to the composite input of the video monitor Turn on the DVD player monitor and the MC 8 The monitor should display a blue screen Press the remote DVD1 button to select DVD 1 as the input for testing the video paths Press the Menu arrow The MC 8 Main Menu will be displayed With the Menu arrow scroll down to SETUP then select by pressing the Menu arrow The Setup Menu
292. t 500 1 2 3 15 Internal 96000 Analog ANLG MAIN IN3 96K TO ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float dB Level gt 85 00 80 00 150 00 100k lt 10 gt 22k 1 2 3 15 n a Internal 96000 Analog ANLG MAIN IN3 96K TO ANLG MAIN OUT SNR 3 OFF OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100 lt 10 gt 22k 1 2 3 15 Internal 96000 Analog ANLG MAIN IN4 96K TO ANLG MAIN OUT ANLG MAIN IN4 96K TO ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 47 80 48 90 6 60 40kHz LP 100k lt 10 gt 500k 3 2 4 16 Internal 96000 Analog ANLG MAIN 4 96K TO ANLG MAIN OUT FREQ 3 2 00 Vrms 2 00 Vrms 10 20k 40k 20 Unbal Float dBr Level 0 05 0 25 0 05 0 15 0 50 100k lt 10 gt 500k 1 2 4 16 Internal 96000 Analog ANLG_MAIN_IN4 96K_TO_ANLG_MAIN_OUT THD 3 4 0Vrms 4 0Vrms 20 2k 8k 40k 20 Unbal Float THD N lt 005 010 010 020 00005 40kHz LP 100k lt 10 gt 500k 1 2 4 16 n a Internal 96000 Analog ANLG MAIN IN4 96K TO ANLG MAIN OUT XTALK 3 4 0Vrms 4 0Vrms 15k 20 Unbal Float Level gt 85 00 80 00 150 00 100 lt 10 gt 22k 1 2 4 16 Internal 96000 Analog ANLG MAIN IN4 96K TO ANLG MAIN OUT SNR 3 OFF OFF 997 20 Unbal Float dBr Level 99 00 97 00 140 00 100k lt 10 gt 22k 1 2 4 16 Internal 96000 Analog ANLG MAIN IN5 96K TO ANLG MAIN OUT ANLG MAIN IN5 96K TO ANLG MAIN OUT GAIN 3 4 0Vrms 4 0Vrms 997 20 Unbal Float Vrms Level 47
293. t drives a clock tree that divides down the master clock which is 256 times the sample rate 256FS to create the other clock rates required e The SHARC DSPs receive a word clock or framing signal FS and a bit clock of 256FS The Digital Receiver ADCs and DACs use word clock FS and bit clock 64FS e The DSP and Decoder Boards receive a 256FS Master Clock and a word clock FS These are used on each individual board to derive the audio clock signals required by that particular board PLL_MCKO gt PLL PLL 24 576 MHZ 4896 gt MAIN MAIN DRCVR MCKO IO FPGA MAIN MCKO MAIN MAIN DRCVR FSI DRCVR MAIN DRCVR SCKI MAIN MAIN ANLG FSI MAIN ANLG 8 ANALOG MAIN MCKI DEx FSI DSP BOARD DBx MCKI DAUGHTER DBx BOARDS DBx_MCKI gt 0 1 2 MAIN AUDIO CLOCKS AUDIO FPGA 6 14 Lexicon Zone Audio Clock and Data Paths The Zone Audio Data Path is as follows Output of the Zone Digital Receiver to the Audio FPGA e A2 channel stream is sent to the Analog section as ZONE DAC SDI This stream is either the output of the Zone Digital Receiver or a 2 channel down mix of the Main Audio content There are three possible sources of master clock for the Zone Audio Path The 22
294. th is also provided which passes a 2 channel analog input signal directly to the Left and Right Front outputs via the level controls bypassing the DSP and converters The MC 8 Balanced version offers additional Balanced Main and Zone 2 analog outputs using XLR connectors In this version an internal 34 pin ribbon cable routes the post level control signals from the Analog board to the XLR board The XLR board incorporates active balanced output drivers for each of the ten outputs In addition two 5 1 channel sources can be selected for the Main audio path There are two possible methods of getting a 5 1 source into the box Refer to the Main Audio Path 5 1 Channel Input block diagram above 1 S PDIF signal may be encoded in Dolby Digital or DTS format and pass through a decoder that outputs the 5 1 channels These channels are then passed along to the DSP 2 Two sets of three separate analog input pairs can be routed directly to the outputs bypassing the DSP and converters This mode is available for DVD Audio and multi channel SACD players with 5 1 analog outputs In the first case Input 3 would pass to the Left and Right Front outputs Input 4 would pass to the Center and Subwoofer outputs Input 5 would pass to the Left and Right Side and Rear outputs A duplicate set uses inputs 6 7 and 8 in a similar manner Any of the eight analog or eight digital audio inputs can be selected as the source for the Zone 2 Audio Path as shown in t
295. the Main and Zone Digital Receivers e Receives status bits from the Main and Zone Digital Receivers e Host Serial Control Interface to the to the Video Board and On Screen Display Consists of the chip select serial clock and data The FPGA converts the host parallel data to a serial data stream e Serial control of the Main and Zone DACs and Volume Controls e The 1mHz clock signal used by the 16C54 PIC IR Receiver e Routes all 12S audio data in the system e Packs and unpacks 125 audio into octal streams for the Sharc DSPs e Provides interrupts to the Z180 Host processor e Provides twelve programmable tie lines each to the DSP board connector and the three daughter board connectors HOST INTERRUPTS HOST INTERFACE VIDEO SERIAL CONTROL MAIN DRCVR ANALOG STATUS VOLUME ZONE CONTROL HAGE SERIAL STATUS INTERFACE ANALOG CONTROL REGISTER CHIP SELECTS COAX OPTO S PDIF NRZ INPUTS DATA OUT MAIN AUDIO CLOCKS amp DATA ZONE 2 AUDIO CLOCKS amp DATA DSP BOARD INTERFACE DAUGHTER BD 0 INTERFACE DECODER DAUGHTER BD 1 INTERFACE DAUGHTER BD 2 INTERFACE SPARES AUDIO FPGA BLOCK 6 5 8 Service Manual HOST INTERFACE TO OTHER BOARDS Front Panel IR Encoder and VFD The interface to all of the front panel boards with the exception of the standby board is a single ribbon connect
296. the test B5 Read Back Reg Fail 1 indicates the Readback register failed B4 Test Fail 1 indicates the test failed O success B3 SHARC Test Completed 1 indicates that the sharc was able to finish executing the test B2 READ Timeout 1 means that 2180 could not read back from the SHARC 1 indicated timeout B1 WRITE Timeout 1 means there was a timeout 5 6 Lexicon B0 SHARC write timeout id 0 is for PS1 1 is for PS2 If there is a WRITE TIMEOUT then check to see which SHARC pair caused the fault B3 shows if the SHARC was able to run the code and determine whether there was success or failure Success or failure can be determined by either the GPIO LEDs green success red failure or by the return code in the register readback OxAA for success and 0x55 for failure If is 0 then make sure that is 1 before deciding whether the SHARC test passed If the GPIO LED failure bit indicates a failure then check the circuitry surrounding the LED An LED failure occurs when the number of LEDs lit is NOT 1 If 2 are lit then there is probably a short between them If 0 are lit then parts may be missing or a short exists Bits B2 B1 and BO are read together If a time out occurs then B2 or B1 will indicate what operation caused the fault BO will indicate which processor failed Processor A or B Bit B3 is used to indicate whether the SHARC was able to run the code If this bit is zero the code
297. tic Categories There are two types of diagnostics in the MC8 B power on and extended The extended diagnostics contain the tests that are used by manufacturing personnel to verify functionality and by repair to aid in troubleshooting The entire set of power on diagnostics is executed every time a unit is powered on using the rear panel power switch The power on diagnostic tests can be run individually in the extended diagnostics The extended diagnostics also contain additional tests used to verify all the front panel controls infrared communications audio and video performance etc The troubleshooting or repair diagnostics are used to troubleshoot an MC8 B if any test fails Power On Modes There are two power on modes available Power on via the rear panel power switch or by bringing the unit out of standby mode The power on diagnostics are executed every time the rear panel power switch is switched on When MC8 B is operating if the front panel Standby button is pressed the unit goes into low power Standby mode Pressing any front panel button or any remote key will bring the MC8 B out of Standby mode No diagnostics are run when the unit is brought out of Standby Diagnostics User Interface Various combinations of button pushes are used to control diagnostic activity The table below summarizes the options available followed by more detailed descriptions Action Buttons to be Held Enter Diagnost
298. tion and the menu choices will appear in the second row The available choices are Functional Tests Repair Tests Loop Tests Audio I O Tests Video I O Tests and Normal Operation When the desired menu item is shown press the Mode gt button This selects the menu item If the item is another menu the menu s 8 Service Manual title now appears in the top line of the VFD and its menu items are in the second row If a test is selected the test name will appear in the top line and the results or information to run the test will be on the second row Once test is finished or to get out of a menu press the Mode button Pressing and holding the Mode button returns you to the top level diagnostic menu There are groups of diagnostic tests in which if a test passes the diagnostics automatically execute the next test Group tests are the Power On Diagnostics in the Manufacturing suite the Pre Burn In test and the Burn In Loop For the Burn In Loop upon successful completion of the group tests the VFD will briefly display either Pass or Fail and continuously loops until power is removed from the unit test fails the VFD and front panel LEDs will attempt to indicate the failed test The test will attempt to loop to keep the signal lines active for debugging purposes If an individual test is selected it will continuously run and report if it passes every time it successfully completes the test In addition test progress and fa
299. tion on the encoder knob the display will never indicate a Passed message This is achieved by having the accumulator value reset to 0 if a switch position was bad or if the encoder was turned in the opposite direction during the test Therefore the accumulator will never see the expected value of 24 so the program would not be able to perform the next task i e instruct the user to perform the counter clockwise test or display Passed When the encoder is being tested the bottom right half of the display will indicate the direction and position value The test requires the clockwise direction to be tested first 1 When you turn the encoder knob clockwise the display will read EXTENDED DIAGNOSTICS Encoder Test CW 05 In this example the encoder knob was turned five positions clockwise 2 After the encoder knob is turned one 1 revolution clockwise covering all twenty four positions the display will read EXTENDED DIAGNOSTICS Encoder Test CCW 24 The bottom half of the display CCW 24 indicates the counter clockwise test is ready to be executed 3 After you turn the encoder knob one complete revolution counter clockwise covering all positions the display will read ENCODER TEST Encoder test passed LED Test The LED test illuminates each LED by turning the encoder knob clockwise or counter clockwise As the encoder knob is turned each individual LED is illuminated 8 Service Manual Expand O
300. tion when handling testing or adjusting Always power down all equipment before breaking making connections Initial Inspection 1 Inspectthe MC 8 for obvious signs of physical abuse Verify that all switches operate smoothly e With the power off for ten minutes and the AC cord disconnected remove the MC 8 top cover using a hex wrench 2 5mm Remove the 13 screws on the top cover of the unit to remove the cover Verify that all socketed ICs are correctly seated Verify that all cables are correctly installed and are securely fastened Check for burnt or obviously damaged components Put the top cover back on Power on the MC 8 using the main power switch on the back of the unit and verify that the MC 8 runs through its Power On Diagnostics 9 Check each of the front panel switches for smooth mechanical operation verify each LED turns on and off when the associated switch is depressed and that the display acknowledges each switch function 10 Press each button on the remote and verify that the MC 8 is responding to all the remote commands 4 1 8 Service Manual FUNCTIONAL AUDIO TESTS The following tests verify the basic functions of the MC 8 Power Supply Tests The main power supply in the MC 8 has an operational range of 100 240VAC 50 60Hz 60W The following test is for North American line voltage of 120VAC Lethal voltages capable of causing death are present in this unit In this pr
301. udio data to and from the CS 49400 The input is single 12 2 channel data line The output of the chip consists of four 125 2 channel data lines HOST INTERFACE DSP AB CONTROL DSP C CONTROL AUDIO CLOCKS AUDIO DATA FLASH ROM INTERFACE DECODER FPGA BLOCK 6 8 Lexicon CIRRUS CS49400 DSP Audio Decoder The CIRRUS DSP is responsible for detecting and decoding all compressed audio data formats Dolby AC 3 and DTS It is a 2 5 Volt part Its processor clock is a 12 288 MHz crystal oscillator The internal speed at which the chip runs is selected by DEC_CLK_SEL The chip actually consists of two linked processors which are referred to as DSP AB and DSP C In the following section x refers to AB or C To boot chip the Host processor sets the DEC_ x _ABOOT IRQ pin low and sets the ECODER_RST pin high The chip then boots from the external Flash Rom Processor C boots first followed by processor AB The host through the CS49400 can program the Flash ROM During run time the host communicates with the Crystal Decoder through a serial control interface that consists of the following signals DEC_ x _SCDIN host serial control data generated in the DAR FPGA SCDOUT CS49400 Decoder status data output to the host DEC_ x _SCCLK serial data bit clock DEC x CS serial port chip select x ABOOT IRQ CS49
302. ure information such as data sent data received address location etc is listed in the error log For example SRAM failures are not reported to the error log The error log can be viewed via the VFD or it can be sent to the serial debug port Vacuum Fluorescent Display VFD The VFD is the primary source of information during diagnostics The exact display information will depend on the test s being executed When an individual diagnostic test is executed the VFD will display the name of that test Groups of tests such as the power on diagnostics or the burn in loop have a generic message on the top line of the VFD For example DIAGNOSTIC TESTS is on the VFD while the power on diagnostics is being run An E followed by a number indicates a test failure message Front Panel LEDs The top row of the front panel LEDs is also used to display diagnostic status The LEDs are used in binary format with the Zone 2 VCR LED as the LSB and the Main DVD 1 LED as the MSB Running test number 1 would illuminate the Zone 2 VCR LED only with all the others off Running test number 2 would illuminate the Zone 2 Sat LED only with all others off Running test number 3 would illuminate the Zone 2 SAT and the Zone 2 VCR LEDs together with all others off etc 5 2 Lexicon failure occurs the LED illuminated to indicate the test failure and the LEDs indicating which test was running when the failure occurred will also c
303. uss integrity First each byte in a special 32 byte section is written with a count Then 5 8 Lexicon starting from the beginning of the block and incrementing through it the count is verified to be correct If so this area will be used to store the contents of the rest of SRAM as it under goes the count check in 32 byte blocks If an error occurs an attempt will be made to blink the STANDBY LED using rate of three blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging In order for the test to pass the Z180 and the CPLD U84 and U83 respectively on the main board and page 1 of the schematics and associated support circuitry must be functioning Flash Checksum Test The Flash checksum test verifies the data in the 16 Meg flash memory either U1 or U2 on the memory board For all banks the checksum test adds up all the data in each bank except for the bank number and stored checksum locations stored in the last three locations of each bank The added value is then verified against stored values If an error occurs an attempt will be made to blink the STANDBY LED using a rate of four blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging DISPLAY FOR THE REMAINING TESTS If any of the following tests fail the VFD display and LED matrix will display the test and error fault if one occurs as previously discussed The V
304. utput MUTE Test The Expand output MUTE test verifies that the MUTE signal going to the XLR board is functioning 1 When you select the test the VFD display will indicate EXPAND OUTPUT MUTE EXPOUT Low On the main board the red LED D23 will be lit when the VFD indicates that the EXPOUT signal is low Rotate the encoder knob clockwise and the VFD will indicate EXPAND OUTPUT MUTE EXPOUT High And the red LED at D23 will be off If the unit being tested is a MC 8 Balanced the relay on the XLR board can also be heard Turn the encoder knob counter clockwise to set the expand and mute signal low Trigger Test This test will verify the trigger circuits of the MC 8 For this test you will need the MC 8 remote control and a Digital Multimeter DMM Test o gm o N Power on the MC 8 Turn on the DMM and set it to read DC voltage for a 12V level Using the remote control Menu arrow select SETUP form the Main Menu Scroll down through the SETUP menu and select TRIGGERS Scroll to DVD1 and change the trigger from OFF to ON Ress the remote control MAIN button then press the remote control DVD1 button to select DVD1 as the input for the Main Zone On the MC 8 rear panel locate the Trigger Outputs block Connect the red probe to positive and connect the black probe to negative Measure the PWR and the 1 trigger outputs for 12 volts DC PIC Software ID Test The functional diagno
305. ve the following interface Host I O data bus Host I O address bus Host control RD WR and CS Reset e 4MHzclock used on the analog board to derive serial control clocks 12 programmable tie lines to the Audio FPGA which be used as needed for audio clocks and data or control e 1 programmable tie line to the FPGA BUFFER DBA DATA HOST ADDRESS ADDR BUFFER RD gt RD IO WR WR DAUGHTER BOARD CHIP SELECT 4 MHZ SERIAL CONTROL 12 TIE LINES RESET DAUGHTER BOARD DAUGHTER INTERFACE BOARD CONNECTOR 6 7 8 Service Manual DECODER BOARD The Decoder board is installed in the Daughter Board 0 slot Decoder FPGA The Decoder FPGA has byte wide data path for the host interface with 5 bits of addressing It provides the following functions Provides ABOOT IRQ and HINBUSY lines for control of the Cirrus 49400 Converts Host parallel data for serial control of the 49400 DSP AB and C Uses the daughter board audio clock inputs DB_MCKI and DB FSI to create the input and output frame sync SCLKs required by the 49400 audio interface This includes running the input and output sides of the CS49400 at different rates for DTS 96 24 decoding Uses the Decoder GPIO pins to enable the correct Decoder Flash write signals and addresses Routes a
306. ve the necessary audio clocks FS which is used as the sample interrupt 4FS which is the octal frame sync and 256FS the serial bit clock for the octal data stream HOST INTERFACE DSP AB CONTROL amp DATA DSP CD CONTROL amp DATA AUDIO CLOCKS AUDIO DATA DSP FPGA BLOCK Host Communication with the SHARC DSPs The lowest byte of the SHARC external data bus is also connected to the Host to DSP Command Register and the DSP to Host Status Register in the DSP FPGA There are three modes of communication between the Host and the DSPs The first occurs at boot time When it comes out of reset the SHARC asserts DSP_BMS DSP_RD These are combined by the DSP FPGA to create This signal is used to generate the DSP_WAIT signal which is re clocked by the DSP_30MHZ to synchronize it to the SHARCs It is then sent to the SHARC as where it keeps the SHARC in a wait state until the Z180 has written the data to the DSP Command Register ____ 5 _ DSP_ACK SHARC Bus DSP TO DSP S HCMD_REG_FULL DSP RD FPGA Kata HOST N DSP DATA DSP DATA DSP COMMAND WR CMD I DSP RD REG FPGA le DSP_COMMAND_RD DSP COMMAND WR HOST LOADS SHARC AFTER RESET BOOT MODE 8 Ser
307. vice Manual Host Writes Data to a SHARC DSP This is how the host transmits data to the SHARCs during run time The Host writes a byte to the DSP Command Register The write strobe DSP_COMMAND_WR also interrupts the SHARC to let it know that a byte is waiting The SHARC then retrieves the byte by asserting DSP_HOST_CS and DSP RD This also clears a status bit in the DSP FPGA informing the host that the command register is empty and can be written to again DSP COMMAND WR m SHARC nosr cs TO DSP S REG FULL PSP_RD FEGA Ee Bos DSP LN DSP_COMMAND_WR DATA CMD DATA DSP CMD REG en FPGA le DSP_COMMAND_RD DSP_COMMAND_WR HOST WRITES DATA TO SHARC SHARC DSP writes Data to the Host The SHARC writes a byte into the DSP to Host Status Register in the DSP FPGA by asserting DSP HOST CS DSP WRH This sets a bit in the DSP FPGA that informs the host that that register is full and waiting to be read When the host reads the byte the DSP STATUS FULL line to the SHARC is cleared so the SHARC knows that the register is empty and can be written to again DSP STATUS FULL DSP STATUS FULL DSP HOST svar REG psp FPGA HOST 08 STATUS RD DSP S DSP STATUS WR y N DSP DSP HOST
308. void personal injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the unit DANGEROUS PROCEDURE WARNINGS Warnings such as the example shown below precede potentially dangerous procedures throughout this document Instructions contained in warnings must be followed Dangerous voltages capable of causing death are present in this unit Use extreme caution when handling testing or adjusting ta ELECTROSTATIC DISCHARGE ESD PRECAUTIONS The following practices minimize possible damage to circuit boards resulting from electrostatic discharge or improper insertion Keep circuit boards in their original packaging until ready for use Avoid having plastic vinyl or Styrofoam in the work area Wear an anti static wrist strap Discharge personal static before handling circuit boards Remove and insert circuit boards with care When removing circuit boards handle only by non conductive surfaces Never touch open edge connectors except at a static free workstation Minimize handling of circuit boards Handle each circuit board by its edges Do not slide circuit boards
309. was not able to run a 1 indicates the SHARC was able to run Bit B4 indicates whether the test passed or failed This bit is only valid if B3 is a 1 Bit B5 indicates that the read back register failed There is a fault in the read back register circuitry if this bit is a 1 Bit B6 indicates whether the circuitry around the SHARC LEDs failed A 1 indicates a failure When the SHARC passes these tests it will return a value of 0x0300 aYYYYYY Failing address location The address in hexadecimal where the failure occurred 22 Value Written The target value in hexadecimal that was written to the address where the failure occurred rQQ Value Read The actual value in hexadecimal that was read from the address where the failure occurred The error log is available as a menu item in the extended diagnostics under Repair Tests In addition the error log can be viewed on an external PC or terminal via the D9 connector labeled RS232 2 on the rear panel of the MC8 B The error log is sent to RS232 2 when the VIEW ERRORLOG selection is made 5 7 8 Service Manual Power On Diagnostics As described earlier there are two power on modes in the MC8 B Power on via the rear panel power switch and by coming out of standby mode Power on diagnostics are executed every time the rear panel power switch is switched on Diagnostics are not run when the unit is brought out of Standby mode Power on diagnostics take approximately
310. will appear and Inputs at the top will be highlighted 9 Press the Menu arrow again 10 The display will read DVD1 Input Setup 11 Press the Menu arrow The DVD1 Menu will now be displayed 12 Using the Menu arrow scroll down to the Video In parameter and select it by pressing the Menu arrow 13 Using the Menu arrow scroll to the video input Composite 1 14 Press the Menu arrow to select video input Composite 1 This will assign the Composite 1 Video input to the main composite output of the MC 8 15 Press the remote OSD button to turn off the onscreen video information from the MC 8 and allow viewing of the video from the DVD player 16 The video path is now set for testing Test 1 Load a disc into the DVD player and press play 2 a clean undistorted picture appears on the monitor 3 Pause the DVD player 4 To test the second composite output switch the composite monitor output cable on the rear of the MC 8 to the composite Zone 2 video output then repeat the procedure 5 The setup and test procedure should be repeated to test composite video inputs labeled 2 through 5 To do this repeat the procedure changing the Input Test selected in step 14 to the appropriate Input 4 9 8 Service Manual S video Inputs to S video Outputs Test This test will verify the S video switching function of the MC 8 Setup 19 N gt ak

MC-8 Controller Service Manual

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