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SERVICE MANUAL MODEL ER-A750

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1. 59140 sau 50140 99 9 woul S3u vos L OV1VOXH m AQHAOH EAGUNYL HESS eye ZAQUNHL EdNINEL 124 10 250 TdNINHL 50 L 7009924 991 ASH ES HOS SH 984 HOS Sd SUL HOS HON SUL HOS NOO 5 ola ace TAUG ZANINHL zAQUAOH ZLOAOH ZAQUNH I 209Q 28 12 219 IHS LdW3NHL LAQHAOH LLGAOH LAQUNH L LOOQ LS 19 LIO Q39NVHO AdAL LYOd 1711 9661 240 982 13 948 L A9HdNOL 10102 O3TWISNIION z zsea 7 L k bog gez Xd 99 AOG 4N00L padais OUZSZ9H 6 297958 AOSHnOOL 793 209 29 1 20102 09 3 001 vSHddS 1 19836208 2563 Q3TIVISNI LON S1uHVd 9 11 9661 2563 Q39NVHO 108WAS 1 1 1 9661 AZL AZL APZ Q3959NVHO 108WAS 1 1 1 9661 vVcOHVL AND oz 1545 MS 99 VAL MOL 3 EAT e
2. 12 SHARP COPYRIGHT 1997 BY SHARP CORPORATION All right reserved Printed in the USA No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without prior written permission of the publisher SHARP CORPORATION Information Systems Group Quality and Reliability Control Center Yamatokoriyama Nara 639 11 Japan March 1997 Printed in the USA
3. SLISZNS 696881 6697952 N oio 5 9668 L Hono VUA S1H Nus ve ESESS 6010 SLLSZNS Vv OI vas CrIVLSNI LON ML 18 46 NYS SY L e 799 435 599009 98 4 N 101 2181752 s s 16697952 60 SIH NHS 9 OODHbL OS Jn L O NOS 3nzz 0 620 820 63 IONAS 16 0 1 9661 6 5 lt ZNYS Q39NVHO 31111 1 0 1 9661 G CNYUS ald esessl 2 28 2 4 MAP LLOLG Ie olay od iut ex vo 99 99 as 35 DS 35 dV NOD dNdOd LJA aec 215 08 2 SE 9 9 e Ix ZH89Z 2 x P da dV NOD OS 3S 3s as 95 PX
4. oo 0 X 8588999888982 Figure 2c 44 pin Quad Flat Pack Pin Assignments 4 Functional description The Z80 CTC has four independent counter timer channels Each channel is individually programmed with two words a control word and a time constant word The control word selects the operating mode counter or timer enables or disables the channel interrupt and selects certain other operating parameters If the timing mode is selected the control word also sets a prescaler which divides the System clock by either 16 or 256 The time constant word is a value from 1 to 256 During operation the individual counter channel counts down from the preset time constant value In counter mode operation the counter decrements on each of the CLK TRG input pulses until zero count is reached Each decrement is synchronized by the system clock For counts greater than 256 more than one counter can be cascaded At zero count the down counter is automatically reset with the time constant value The timer mode determines time intervals as small as 2 us 8 MHz 3 us 6 MHz or 4 us 4 MHz without additional logic or software timing loops Time intervals are generated by dividing the system clock with a prescaler that decrements a preset down counter Thus the time interval is an integral multiple of the clock period the prescaler value 16 or 256 and the time constant that is preset in the
5. 340066 AOS2 WS ZL L NOO E H SETt H096r1 Aver Q39NVHO IONAS 1 01 966 1 LINDYID H3MOd Aver Ave AZL AZL G39NVHO TOSWAS 1 0 1 9661 1 936608 zaz zx nos T anoee 99 799955 319100 1 vIO T Nve LU e L 4 eu v S DON 34088 99109 moor 102 001 89 759955 4 N cold 9919 LU e L LINDUID ANO 680 HOLO3NNOO 94 X Lea L 34088 ES volo EE 992 34088 Te Lg 90vSv LOIN 35 sez 2518 99 2 2519 gt 99 2 O 1O93NNOO 90vSv LOW 2LQAOHu gt 96 2 cAGHNHI V12 688IN 109 LEG 15 ISIH sez LOS 159 L 1
6. 3snioN 99 179 NOdA4 2910 910 9910 1919 t SNS INd 18545 MS T Hegud o SX3d001 p INO Tdl ING lar P A ERE HOS ZNUS HOS INHS HOS ZEZSH HOS WVvuSd HOS ASH3MOd HOS AF2H3MOd HOS AZ LYIMOd HOS 2dO HOS 9VOdW HIS dSIAGDT 8618 HOS H3MV HO LOHI HOS NOO XLE 439 FITALS 1HOd 1 01 9661 ANIT 99 DON 99 99 17198 991 4 228852 AZL H31H3ANI 0 j Im 2 v so 2 MATLLOLG SO AOL SNOL L G3TIV1SNI JONO MArv LIVIA L e 120295 3181035 20 01 X 3001 SELO 610 919 2119 ae 8 19 0 19 YELO Zeto 6119 4619 SXLENTE EA ZHINOL f ed ex L_ gj og SSA 149 5 dM SNSINd SSA A0S Ane 451 NOO GOT 0 gt A91Jne e O 89 07 S 0 V 09 1 SNSINd 98 09 L V9 L Zola
7. T RJRST SLRST PRST RJTMG SLTMG PTMG Print gate Print pulse control Output selection with CAPS PRST PTMG J x G G m z Z ILOS Printer control port dd 9815 DHL 1NDd 1024 ar dAVIS Fig 2 4 TES MTD MTD RJMTR EN SLMTD SLMTS SLMTR SLMTD gt 315 3 Pin description Function Function Nu Serial port shift clock input Nu from CPU Nu IRQO IRQO Interrput request to CPU Nu Address bus Nu Address bus Nu Address bus Nu Address bus Nu Address bus Nu Address bus Peripheral output reset GND Nu 45V Nu Address bus Power off signal input Address bus Interrupt signal Key Address bus interrupt request Address bus 8 bit serial port output Address bus Serial port shift clock output Address bus 8 bit serial port input Address bus Chip select Address bus Nu Address bus 45V Address bus GND Address bus Interrupt signal MCR Address bus Turns active when reset and Address bus power down is met Address bus GND Address bus GND Address bus Address strobe Address bus Read strobe LCDC LCDC chip select signal Write strobe Address bus 6 System clock 9 83MHz GND Nu PTMG Nu Nu PRST Nu Nu INT4 5V To option connector Nu GND Nu GND Nu TEST 5V Nu MA15 Image address 15 Data bus MA18 Nu Nu Data bus MA19 Nu Nu
8. 22 92 Sc vc c ec r4 02 6L ZL 91 St vt L e LL OL 60 80 20 90 90 v0 0 20 10 3309 od ta ea a Sa 9d 1 NO ldl HS3H tO HI OLNIX3 H NIX3 LOHL 2Oul MOVv8 Odug LIVMX3 88NOO X19 eHOW 1HOW cAQUHOW LAGHYOW INAS 50140 13534 ov Iv wW Sv 9v IN sv 6v ov 6 86 Ze 9 SE vt og 6c 8c 22 92 Sc vc c ec te 02 6L 28 9L SL et LL OL 60 80 20 90 90 v0 0 20 10 qu ov 6 9 Ze 96 SE vt og 6c 8c 22 92 Sc vc tc 74 r4 02 6L Zt SE 91 vt L LL 60 80 20 90 90 v0 50 20 10 ov 6 9 Ze SVH 896 AQUVN SE 239VN HM sv LE 538 og ev 6c 8c 86NOO 1HVSN 119 eHOW 1HOW cAQHHOIN LAGHY OW INAS SOLdO 13534 ov Sv 9v AN sv 6v oly
9. 261 8618 92101 v ap Sau I FDA G 13538 vel 909 DOMDN o 9119 5119 9219 LELO 0819 8019 982929205 ILLO Z O 6219 8219 2519 6010 0121 OLLO OND 91 8 001 9019 019 vald 2010 019 9219 ezio Tasndw 13938 nondw AQv3u IMODI asz UMS SONIWN CHOI Sool Mz lt y9 0214 G3ONVHO S1HVd 9 11 9661 OF ova SOL Orr VIA G3TVLSNI LON SLUVd 9 11 9661 AZ Lt OOON osiy 1O8WAS L 01 966 1 LE LY SilH SELY 218 Hu 8518 211 9 8 c iH iHd veld 9618 S 6014 6613 1219 90098 Wdu 101 ZIJA 1353 NIXL fez olv 28 1 1N0X8 XL HI 4 FIFA e 9 ASeidnzv o vodWv o 924 7 SIVA 24 1 TAGHYON 94 4 GAGHYON lese 2299610895599 EE ZHNBZLE zx og
10. 5 ve vOOHbL Sau S l13s3uNHs 29 T L04OVG S 009HvZ MDvA S MINA S v Iova 8 0xovd S YOOHvZ 45 08 7201 v vOOHvZ 91801 992014091 L e 02 ec amp 5385 3409 9720 EL Dg ot e ANI S 12 LIVM S ME 0429 445 6929 vt Sc 905 8969 sas squ 1929 vas 6L SUM S 9929 91 OHO eas SL OYW 5 9929 2 s ve WS Lg L 129 99 7929 ias 920 8x 09 045 29001 21 0N3 gist 38 YAN guns YHHNO 10 516 51718 SO E1U va c1b E0 T1H ZO 1H TO 6H 0 8BH EDNUNG ZOAXUWO TO0NUNG DYYKO t 141 91 S 5 S 5 AU H 13528 2 1883s 311 Sav EL IM a 18 ou 88 vU EH A9VJnOL peo
11. e NI o IN M a 50140 sau MDHL OWLVOXY AQHAOH AQUNH L eu ZAQHNHL dW3NH1 124 819 250 L ZdW3NHl 850 lo m 009923 6121 A9H INOL 10 T lt LASSYNYS Is olv_ lt I13S3HNHS ola 89 O O8 135385 28 2 09 1 9 1 290001 azz 2210 99 1 lt SdOG OH3MVHUG e L e L 380 9 UNS ONS UNS aNg EI ed x 71 as n 79 za as DF 11 T zz vetu MOL lt 42 DST LH Q39NVHO SLUVd 9 11 9661 ano 9 3 s1uvd 9 11 9661 Avert G39NVHO 108WAS 16 01 9661 daaMvad 13938 3YVMAYVH d08 LNO OI ov MS 20115 MS 6 es 86 56 ve 4 avr uw n sw 18 9 as sau og 390001 1 St 6c 340001 390001 82 DITADA i dE T 9019 24047 EG pe T sz Os r ve v as 608 2 a9 1 lt I3sau ov ve S13S3u ez 91 1 ase iz 28 6 oz oe aus
12. Reversed pattern of the above The outermost peripheral of the LCD s active area is displayed in one dot line H pattern H is displayed in 40 digits and 15 lines The 15th line only has 39 digits of H H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH H HHHHHHHHH 3 Terminating procedure Press the ENTER key at the final pattern or press the CANCEL key to terminate the check 3 7 Rear Display Diagnostics The rear display is checked The test program displays the following patterns When the CANCEL key is pressed the display returns to the diagnostics menu 1 Rear Display Check 1 Check content The test patterns are displayed in the following sequence When the ENTER key is pressed the next pattern is displayed The test pattern below is displayed 83455 1 The test pattern we with all the elements ON is displayed 5 55 8355 2 Display Rear Display Check 3 Terminating procedure Press the CANCEL key to turn off all the elements of the rear display 3 8 SHARP Retail Network Diagnostics The SRN test is performed
13. Segment A 3 Address map 3 1 Total memory space The address map of the total memory space is shown below As you can see the memory space is divided into the following 5 blocks Opage area including the I O area VRAM RAM ROM Extended I O area The low order 32 KB of the ROM area and the low order approximately 32 KB of the RAM area are mapped over the Opage area By mapping the ROM area it is possible to accommodate vector addressing processes including reset start 000000h 0 page area OOFFFFh 64KB 100000h 180000h C00000h ROM F00000h 3MB Extended I O area FFFFFFh GME The extended I O area is a space for I O devices which are to be addressed in spaces other than the Opage area In the MPCA7 the addresses from FFFFOOh to FFFFFFh are used for the SSP s addd ressing register Fig 2 3 2 Opage area The Opage area consists of four spaces the ROM mapped area RAM mapped area internal and external I O areas The ROM and RAM mapped spaces have been devised for the fol lowing purposes 1 Simplifying the procedure for booting the IPL program 2 Separating the static RAM access from file space 3 Achieving high speed accessing and accessing by abbreviated instructions n the ER A750 the low order 32 KB of the RASP space 180000h 1FFFFFh is mapped With the MPCA7 s internal registers RASPE 1 and RASEL 0 the address line MA15 should be used Th
14. U AIM OAO O O ODO M OIJOIO O O O Battery label Canada ER A750 2 Bottom cabinet etc y SP x N P 5 VL p lt N 1 lt I a ni MESS C 47 RCPS0151 p NS 0 ER A750 Packing material amp Accessories PARTS CODE DESCRIPTION SPAKA8377BHZL Packing add L SSAKH0003DHZZ Vinyl bag 640 X 560mm SPAKA8377BHZR Packing add R SPAKC8378BHZZ Packing case U S A SPAKC8379BHZZ Packing case Canada SPAKA8384BHZZ Packing pad SSAKH4231CCZZ Vinyl bag 140 X 500mm SSAKH3015CCZZ Vinyl bag 200 X 300mm TINSE7382BHZZ Instruction book U S A TINSE7384BHZZ Instruction book E Canada TINSF7385BHZZ Instruction book F Canada TCADH6805BHZZ L A card TCADH6788BHZA Caution card UBNDA6629BHZZ AC cord band 4mm 200mm Green Packing material amp Accessories RCPS0152 Main PWB unit PARTS CODE DESCRIPTION ER A750 RCRMZ1016LCZZ Crystal 16MHz X4 VCEAPS1CC106M Capacitor 16WV 10 C11 12 14
15. co o S82NOO INO1dO or 6 8 28 Ov 6 8E 2HOW LE sAgl Wd na m ZAQUUOW ZAQHHOIN SE a LAGHHON PA uuo ve ONAS Blir ce SOLdO Fe 41 Og ov 0 62 81 86 82 zz yv 92 96 11 Sv gg ov vo ez EI lV c 22 sv ev 16 oz 02 EE LIV 61 NO dl ae En BI 01 tiv OL SL SIV SL giv l 21 eJ SNId a 1 11 9661 81 OD ozy 91 60 G3QQV LAN 1 11 9661 Lew 80 cow 10 p 20 50 vo OHM 0 OGY 20 0 er VZNOO NOD SUL Avet G395NVHO TOSWAS 16 0 1 9661 PY Svu AQUVN 23OVN L30VN Sv S3u ev ov 6 9 Ze 9 SE vt t og 6c 8c E LNOLdO Svu AGHVN 23OVN L30VN Sv S3u ev 909 3309 oa ed va Sa 9d 1a NO ldl HS3H 2Oul LOul OLNIX3 3 LOHL Odug LIVMX3
16. LIV riv SIV giv LIN 8 6 ozy 12 26 9c Sc vc 3404 c 22 0 2 ig 02 a Zt Sa 9r 9 91 pr NOTldl L 538 at 2Oul LL 198 OLNIX3 3 60 80 20 MOV8 90 90 O3ug v0 LIVMX3 90 au 20 10 g0LNO9 6 1HVSN 419 86 Ze 1HOW 9 cAQHHOIN SE LAGHYOW ve ONAS t SOLdO 1395388 og 6c I 8c 22 tv 9c Sc Sv 9v vc c AN sv ec ev 2 02 6L 28 91 8 vl 511 LL OL 60 80 20 90 90 v0 0 20 99 8Md YAHLOW XLE 10 VOLNOO AS2 any vo PARTS GUIDE MODEL ER A750 For U amp A version CONTENTS Top cabinet etc CKDC PWB unit Bottom cabinet etc N F PWB unit Packing material amp Accessories Inverter PWB unit Main PWB unit Rear display PWB unit
17. 026 2o J p CJ il 333 T 8 64 2 me R9 RM eo 2 2 I 1 22 d COM SI 5 Rear display PWB SHARP F7513BH 6X AD IV 0A 6 Invator PWB cow 8 2 1 q orem i SHARP N7512BH 6X 000000008 96 7 Noise filter PWB WOR 1V 0A SHARP F75088H 6X 1 N 51 TETEE CONI Knet RISK OF ELECTRILA SHOCX AND FIRE Y WITH THE SAPE TYPE AND f Des 1AL 250V UL CSA 1 5A 125V c2 H w CON2 8 9001 0919 Sto 1919 2919 89 07 g 0 v 6910 8viO 419 9vi9 08 08 2 09 1 Ay so 1 99 8019179 Ord Led 964 SEd LYG gt 9v 9 ved 0 gt 59 9 d Sdod ed MOVE 164 lez olv gt Ig ALL V8 E Sa 7HIN9 6L E za 5818 ta 99202508 UO gt ges 08 ver
18. 1FFFFFh C00000h FLASH ROM CFFFFFh Fig 17 When leaving the factory 000000h N 0 page PROM 007FFFh C00000h FLASH ROM D00000h DFFFFFh Fig 18 3 During IPL Typical procedure for rewriting flash memory When IPLON1 L is detected at starting the IPL routine is written into the PSRAM as shown in the figure below and the IPL routine is used for rewriting the flash memory The IPLON1 signal is con trolled by the DIP switch and connected to the CPU P11 0 page PROM IP RUITINE COPY FLASH ROM 0 page PROM PROGRAM DAT SERIAL FLASH ROM WRITE Fig 19 18 IR communication The ER A750 has IR communication function which is softwarewisely compatible with the ER A460 Data is exchanged with the MPCA7 using the channel 1 SCI1 of the serial communication interface of the CPU 18 1 CPU interface and modulator demodulator Here is its block diagram RPM850CB IRDA modulation demodulation ASK modulation demodulation Baud rate x m Divider Baud rate X16 7 3728MHz Fig 20 19 SRN The SRN of the ER A750 is compatible with the ER A6IN 20 Standard RS232 Two standard RS232 channels are compatible with the ER A5RS However while the ER A5RS uses the IRQ2 terminal of the CPU for interruption of the RS232 the E
19. Nu Nu Nu Nu Nu Nu Nu Nu Nu LCDC wait signal Standard RAM chip select signal 2 3 OPC1 F256004PJ 1 General description The OPC1 is a gate array of integrated peripheral circuits of RS 232 Simple IRC interface One chip of the OPC1 is equipped with four communication circuits Three of them are for RS 232 only UNIT 0 2 one is for selection of simple IRC RS 232 UNIT 3 The ER A750 uses UNITO RS 232 interface and UNIT7 RS 232 inter face UNIT NO Purpose ER A750 UNITO RS 232 Used UNIT1 RS 232 Used UNIT2 RS 232 Not used UNIT3 RS 232 IRC Not used Each UNIT of the OPC1 has the following functions 1 Timer function Used for the timer between characters in data reception 2 Address decode USART chip select output and own select 3 Interruption control RSRQ TRRQ output using outputs from USART TRNRDY TRNEMP RCVRDY BRK and RS 232 control signals Cl CTS CD as interruption factors For the simple IRC TRNEMP is excluded RSRQ ForRS 232 TRRQ ForIRC 4 Simple IRC send receive control UNIT3 only Not used 2 Pin configuration a OQolwuloriEb5ooessser DEY To we PR12382 EER ESERaaaa xsl SEECRaadaa CS3 1 SL12 052 2 RCVRDY2 TRNEMP3 3 RCVDT1 BRK3 4 RCVRDY1 TRANDY3 5 TRNRDY1 RCVRDY3 6 BRK1 RXDATAO 7 DB7 TRCK 8 DB6 RES DB5 OPT
20. 2 5 4 p ON 2510 ON ZLOAOY ON 251 ON zala _ 9019 1uvsn 119 oorspron 79 158 lgvsn Sau 119159 LHY LXIBHG ONAS 010788 ansa LAWINY L Haw LAQHAOH LAQHAOH M HYM ius LAGUNYL LAQUNH L 1518 51 gq 15107 gt DITONEL 980 1510 sga vaa Haar LOAD ega gt 1519 18a 1 15 1519 VESZLN 3dOd AOS JnL _ eco SESSI LINOUIO 440d I ie SO A9 WAN00L 619 eo 91795 e 4 OZZIVST 849 SsadH L 91 3n0001 vaz R 819 297 SO anyo 9919 LINOYIO H3MOd I LINDUID 330d AS 34 00 1 V20 72S8 XIN zo 7 AE9 A001 4ni0 0 Z 929 2 20 go 3 29 7455 VNIA saz 060
21. C262 VCKYTV1HF104Z Capacitor 50WV 0 10uF C124 144 146 156 158 160 162 163 184 243 245 248 250 251 256 VCKYTV1HF104Z Capacitor SOWV 0 10 C257 261 263 265 30 VCKYTV1HB333K Capacitor SOWV 0 033uF VHEUDZ33B 1 Zener diode UDZ33B 20101 102 VHD1SS353 1 Diode 195353 D106 108 109 111 112 VHDSFPB54 1 Diode SFPB54 D101 105 107 VHDSFPL52V 1 Diode SFPL52V D110 VRS TS2AD100J Resistor 1 10W 100 5 R102 277 VRS TS2AD101J Resistor 1 10W 1000 5 R159 161 163 165 166 168 192 VRS TS2AD102J R109 241 289 291 VRS TS2AD103J Resistor 1 10W 1 0KQ 5 Resistor 1 10W 5 R101 106 108 110 119 122 123 126 140 142 148 157 158 162 164 VRS TS2AD103J Resistor 1 10W 10KQ 5 R167 172 174 177 179 181 183 184 186 191 193 197 199 206 VRS TS2AD103J Resistor 1 10W 10KQ 5 R208 240 243 261 265 270 272 274 276 278 279 288 298 304 VRS TS2AD104J Resistor 1 10W 100KQ 5 R155 VRS TS2AD105J Resistor 1 10W 1MQ 5 VRS TS2AD112J Resistor 1 10W 1 1KQ 5 R182 VRS TS2AD122F Resistor 1 10W 1 2KO 1 R264 VRS TS2AD122J Resistor 1 10W 1 2KQ 5 R294 121 VRS TS2AD123J Resistor 1 10W 12KQ 5 R293 VRS TS2AD152G Resistor 1 10W 1 5KQ 2 R295 VRS TS2AD152J Resistor 1 10W 1 5KQ 5
22. Merchandise subtotal excluding taxes 0 04 9 03 _ Tax amounts 0 05 111 9 7 Sales amount including taxes CASH 9 3 SERUERO1 Server name RX Sentinel mark X Appears in the lower comer of the Screen when the cash in drawer exceeds a programmed sentinel amount The sentinel check is performed for the total cash in drawer Receipt ON OFF status Receipt OFF R Menu level shift indicator L1 Receipt ON Blank Shows the menu level currently selected Numeric entry Entered figures appear at the cursor position Received media type Window Price level shift indicator P1 L Stock alarm lamp Shows the PLU price level currently selected In the REG mode it shows sales information you have just entered such as items tax amounts and media types Screen example 2 PGM mode Time 1 A4A PRICE 2 00 SIGN DESCRIPTION ITEM 1 DISABLE ITEM 2 DISABLE ITEM 3 DISABLE ITEM 4 DISABLE ITEM 5 DISABLE ITEM 6 DISABLE ITEM DISABLE ITEM 8 DISABLE 10 09AM PGM2 Mode I Items remain bottom of the window M j Casp lock indicator A a Window In the PGM mode programmable items are listed The upeer case letter A appears when Caps Lock is on and the lower case letter a appears when C
23. NC NC 2 8 MB62H149 1 Outline The MB62H149 is a semi custom LSI chip for the peripheral circuits in the SRN SHARP Retail Network its main function is to communicate data with the host CPU and control the peripheral circuits and transmission control circuits of the Sub CPU Z 80 Fig 2 shows the general configuration of the functions SUB CPU TIMER 2 80 COUNTER TRANS MISSION CONTROL DATA HAND SHAKING CIRCUIT PERIPHERAL CIRCUIT CIRCUIT 2 Internal functions 1 Data handshaking circuit Is used because data processing speeds vary and the timing of the HOST CPU and SUB CPU do not synchronize the MB62H149 is used for data handshaking When the data handshaking portion is broken down the system consists of a Write Signal from the HOST CPU to the MB62H149 Read Signal from the MB62H149 of the SUB CPU Write Signal from the SUB CPU to the MB62H149 and Read Signal from the MB62H149 of the HOST CPU all of which from two blocks as shown HOST ceu Write 199 Sus ceu HOST CPU TO SUB CPU HOST cpu 1984 _ MBe2H149 Write SUBCPU FROM SUB CPU TO HOST CPU Fig 3 HOST CPU write register HOST CPU SUB CPU DATA BUS SUB CPU t x DATA BUS 8bit read register 8bit SUB CPU write register HOST CPU read register HOST CPU write amp SUB CPU read control unit DMA amp CPU HOST CPU addr
24. GND P54 NU GND P55 NU GND P56 NU GND P57 System reset output Normally P60 NU GND P61 NU GND P62 NU GND P63 NU GND P64 NU GND P65 NU GND P66 NU GND P67 NU GND VSS NU GND AVSS NU GND P70 NU GND P71 NU GND P72 NU GND P73 NU GND AVCC AVCC 45V VCC VCC 5V IRQO IRQO Interrupt signal 0 IRQ1 IRQ1 Interrupt signal 1 SCK1 RQ2 UASCK Synchronizing shift lock signal for IR SCK2 SCKi CKDC Interface sync shift clock RXD1 UARX RXD signal for IR TXD1 UATX TXD signal for IR RXD2 RXDi CKDC Interface shift input data CKDC Interface shift output data GND Crystal oscillator connection Crystal oscillator connection GND System clock Nu Address strobe Read Write Nu Refresh cycle 45V 45V MODE 3 45V MODE 3 Function RF JF PCUT FCUT VF STAMP SLF SLRS SLPMTD RES TRG TRG INTO INT1 HTS1 SCK1 STH1 RASV NU VEG VSS INTMCR VRESC SLTMG SLRST AS RD WR PHA SDT7 SDT6 SDT5 VSS SDT4 SDT3 SDT2 SDT1 DO D1 D2 O Q GQ RASP DOTEN LCDWT NU NU NU NU NU D4 D5 D6 D7 ET e
25. P35 Drawer 2 optional drawer P36 Reserved P37 Reserved One port corresponds to one drawer Theoretically it is possible to drive multiple drawers at the same time but this processing must be inhibited softwarewisely because of power supply capacity and driver hardware factors If a power failure is detected the drawer solenoid drive must be stopped as soon as possible The drawer solenoid drive time must controlled in the range of 40 ms to 50 ms by the timer 16 2 Drawer open close sense The drawer open close sense signal is input into the built in port of the CPU the sense signal of an optional drawer sensor is also wired ORed before inputting P33 1 Any of the drawers is open 17 Rewriting flash memory Below are the memory maps at the time of normal operation ship ping from the factory and IPL 1 During normal operation Fig 17 2 When leaving the factory Fig 18 When a service PWB or AMRS PWB is inserted into an expansion I O port the PROM addresses on the service PWB are D00000H DFFFFFh and 000000 007FFFFh the map of D00000h DO7FFFh At this time IPLONO signal input into the input port P10 of the CPU becomes L level Typical procedure for rewriting flash memory If PLONO is found to be at L level by the program inside the Opage PROM the contents in the PROM is written into the flash memory During normal operation 000000h 0 page ROM 007FFFh 180000h
26. Clock Buzzer System reset 11 1 Interface CKDCT7 is connected through the MPCA7 TXD2 P87 SCK2 P83 RXD2 P84 H8 510 HTS SCK STH Standard STOP P57 FT12 Fig 11 Fig 10 S E L E J E EXWAITZ gt d gt gt WAITZ n LCDWT T i ADDRESS lt 00FF8Dh gt 12 Keyboard The ER A750 uses the 13x12 keyboard The keyboard is controlled through the CKDC7 12 1 Interface KRO KR3 18x 12 Keyborad KROA KR3A KROB KR3B KROC KR3C 13 RAM expansion bus As expansion RAM boards the conventional ER 03MB and 04MB are used 13 1 Interface The ER 03 04 have been originally designed for use in the ER A850 Therefore when using the RAM expansion bus of the same construc tion for the ER A750 the two following points on the interface need to be considered 1 Output address change 2 Decode base signal change Here is the explanation for the above two points 1 Output address change The ER A750 uses the expansion RAM board at the RASS area and its high order IMB space 200000h 3FFFFFh Basically the ER 03MB is supposed to be used in the area from 300000h 7FFFFFh the ER 04MB in the area from 700000h 8FFFFFh Therefore it is necessary to convert the addresses as shown below ER 03MB proe ER 04MB 200000H 700000H 300000H zo 800000H e 400000H 900000H Fig 12 Table 16 lt Addres
27. Sv lt sv Jari DIYA lt WVHA Q39NVHO 3AVN YT1OSWAS LE 0L 966L INVH WOH Q39NVHO 1 15 1HOd 1 01 9661 eXug zdW3NHl ZAQHAOH 7 LOAOH 2AQHNHL 2Q9Q 2819 2I0 DIB8 LdN3NH L LAQHAOH LLGAOH LAQUNHI LOOQ 15197 HO 1 3TNAON lt SNA G39NVHO 1HOd 18 01 9661 09201103 214 lt LYVSN 119 C uvsn sau 538 2215 2670 8810 2819 2810 1 020 9810 819 1810 0618 Dia OdWANYL TAGYADH 0AQHAOH 1 o h L 929 gezo 0629 6229 loo F ko M TAQYNYL OAQHNHL ZdW3NHL LANINHL oga tga zga ega 98a gq bide BAGUNdL 2 LAGHADH 1 ZAQHAOH 2118 9554 1618 zzz 2158 n H lo n o 5 ko ko In leo ko leo tol Ise 1 p o A o IN IN ko ho b 061H 0115 M e DON 2015 1015 0015 I BEZH 962 9528 2 6 8 6674 sid LOHU gt okt DON LADG IS15 8re
28. VRAM address bus VRAM address bus VA2 VRAM address bus VAS VRAM address bus VA4 VRAM address bus Symbol In Out Function VA5 Out VRAM address bus VA6 Out VRAM address bus VA7 Out VRAM address bus Out VRAM address bus VA9 Out VRAM address bus VA10 Out VRAM address bus VA11 Out VRAM address bus VA12 Out VRAM address bus VA13 Out VRAM address bus VA14 Out VRAM address bus VA15 NC NC VCS4 NC NC VCS3 NC NC VCS2 NC NC VCS1 VCS1 Out VRAM chip select signal VCSO VCSO Out VRAM chip select signal VDO VDO In Out VRAM data bus VD1 VD1 In Out VRAM data bus VD2 VD2 In Out VRAM data bus VD3 VD3 In Out VRAM data bus VD4 VD4 In Out VRAM data bus VD5 VD5 In Out VRAM data bus VD6 VD6 In Out VRAM data bus VD7 VD7 In Out VRAM data bus VD8 VCC 5V VD9 VCC 5V VD10 VCC 5V VDD VCC 5V VSS VCC 5V VD11 VCC 5V VD12 VCC 5V VD13 VCC 5V VD14 VCC 5V VD15 VCC 5V LCDENB LCDENB LCD control signal XSCL XSCL Clock for display data transmission LP LP Display data l
29. oe vos e 98 2 09 1 V9 1 old 91 5 L Tear ori Ik OINIXS 60 TOHI 80 ZOUL 20 over 90 EEE 50 LIVMX3 L au 0 20 10 d0S NOO 8 LNO o sv 2 NS 6 9v Sr EE 1HVSn Ho 5 EE ZHOW LE zy Wy HON 9 Ov 6 SE se 26 oy LAQHHON vi v 38SVug 9 56 ONAS 6 5 SO1dO z LE n LE av 13538 06 57 OV E Qe amp v 143usd 82 12 66 gc V gz va gz SV 26 zw 16 V z oz 6 96 ziv 9 S FLY a 91 ZV ve ee 1v8 zL LL lz oL DAADA Gv od z vrv Ossvud 6l i Levu p Le OND 9L 1928 AND 9 vi zh LL _ AQWANOL a 219 l 60 58445 80 40 7 5 50 vora vo 0 20 10 VeLNOO LINIX
30. GFTAS6790BHSA Side cover R GCOVA7085BHSA Rear cover PFILW6939BHSA Display filter GFTAS6789BHSA Side cover L XJSSF30P12000 Screw M3 X 12 QCNW 7714BHZZ BNC cable LANGK7562BHZZ IN line angle GCABA7205BHSA Bottom cabinet QACCD8411BHZZ AC cord SP 035 XUPSD40P12000 Screw 4 X 12 LHLDK6830BHZZ AC cord holder XUBSD30P12000 Screw 3 X 12 GLEGG6656BHZZ Gum leg DUNTK4810BHZB Battery unit GFTAB6788BHSA Battery cover LCHSM6703BHZZ Main chassis GFTAS6787BHSA AT cover GLEGP6658BHZZ Tilt leg B GLEGP6657BHZZ Tilt leg A GLEGG6659BHZZ Tilt gum leg TLABG6967BHZZ Battery label TCAUZ6687BHZA Caution label U S A TCAUZ6685BHZA Caution label Canada LANGT7563BHZZ RS232C angle QCNW 7834BHZZ Earth wire PSHEZ6824BHZZ Insulate sheet RCORF6695BHZZ Core LHLDW6821BHZZ Clamp small QCNW 7833BHZZ Earth wire Green Yellow TLABG6978BHZA Battery label QTANP0004BHZA Earth terminal GP20076 U LANGQ7610BHZZ Earth angle PFILW6964BHZZ I R sheet LANGT7569BHZZ Display angle CPWBF7513BH01 Rear display PWB unit PSPAG6728BHZZ Display spacer TLABS7021BHZZ Battery label Canada TLABG7026BHZZ O O O m OJO O O U O OJO UIO
31. IDA amp ASK Diagnostics IrDAS amp SASKSCheck IrDA amp ASK Check Data Transmission Check Data Transmission Check CHECKER MODE Receive MODE Send MODE 6 10 1 IrDA amp ASK Check IR communication is checked between the ER A750 sending unit and the receiving unit 1 Check content Data transmission is made from the machine to be checked in ASK format The transmission rate is 9600bps Data of 00H 11H 22H 33H 44H 55H 66H 77H 88H 99H AAH BBH CCH EEH and FFH are transmitted The checker machine sends back the received data The machine to be checked compares the data sent back and the data transmitted first If both data are the same it displays PASS and if not the same ERROR Data transmission is made from the machine to be checked in IrDA format The transmission rate is 9600bps Data of 00H 11H 22H 33H 44H 55H 66H 77H 88H 99H AAH BBH CCH EEH and FFH are transmitted The checker machine sends back the received data The machine to be checked compares the data sent back and the data transmitted first If both data are the same it displays PASS and if not the same ERROR 2 Display amp ASK Check DATA or TIMEOUT PASS I or ERROR 3 Terminating procedure Press the CANCEL key to terminate the check 2 IrDA amp ASK Check checker mode Set the checker machine ER A750 corresponding to the above check con
32. Satellite Input Terminal Number Enter the terminal No 000 254 3 digits of the machine to be checked and press the ENTER key The display is as shown below Data Transmission Check Satellite The entered terminal No is displayed Terminal Number XXX Input Data Sequence Number 0000 Master machine setting In the menu screen select Data Transmission Check Master Machine The display is as shown below Data Transmission Check Master Input Master Terminal Number Enter the terminal No 000 254 3 digits of the machine to be checked and press the ENTER key The display is as shown below Data Transmission Check Master Theentered terminal No is displayed Input Master Terminal Number Input Satellite Terminal Number Enter the terminal No 000 254 3 digits of the machine to be connected to the machine to be checked and press the ENTER key The display is as shown below Data Transmission Check Master Number Number xxx Master Terminal Satellite Terminal Input Input The entered terminal No of satellite machine is displayed When checking with two or more satellite machines connected enter the terminal No 000 254 3 digits and press the ENTER key similarly To execute press the ENTER key without entering the terminal No The display is as shown below Do not use the same terminal No for different machines master sat
33. To perform this test the following composition is required ER A750 Terminal resistor Branch trunk cable only for data transfer test The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed When the individual diagnostics program is completed the display returns to this menu screen When the CANCEL key is pressed the display returns to the diagnostics menu SRN Diagnostics Self Check Flag Send Check Data Send Check Data Check Satellite Machine Data Check Master Machine 1 SRN Self Check 1 Check content The ROM and RAM for SRN are checked and CTC interruption and carrier sense are checked Also ADLC function and transmis sion reception DMA check is made by using the self loop function of ADLC MC6854 In addition the other signals are checked The check procedure is as follows Execute diagnostics command 2 The number of resending is displayed Execute diagnostics command 0 The error status is displayed The error status is as shown in the table below When an error occurs in this test the following tests are not performed An error occurs The error print is always 1 An unexpected interruption is made A collision is generated An interruption of send complete cannot be made DMAC TC UP interruption An inte
34. 3 Install the ER A7RS to the ER A750 The ER A750 power should be turned OFF ER A750 SIDE VIEW ER A7RS HIF gt Turn on the power of the ER A750 The following display is shown and the IPL procedure is started G When the procedure is completed the message of Com pleted is shown LCDDISPLAY IPL from PROM C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF Completed 6 Turn off the power of the ER A750 7 Removethe ER A7RS from the ER A750 8 Perform the master reset Refer to CHAPTER 4 4 IPL from PC via IR infrared communication 1 IR communication between the ER A750 and PC is as follows RS 232C without IR PC with IR ER A750 2 PC only system 2 Procedures on the PC side and on the ER A750 side are as follows Procedure on P C side Procedure on ER A750 side Copy A7IPL EXE and S type ROM object file ex A750 0A ROM into your Personal Computer P C A7IPL EXE and S type ROM object file is separately supplied Turn OFF the power Select IPL Receiving Mode Set IPL switch ON 1 Open the IR cover of the ER A750 2 IPL switch Set the IPLIR SW to the left side when viewed from the front ER A750 SIDE VIEW IR unit IPLIR SW gr ET 1 pur sw Turn ON the power Starting of IPL Receiving Mode ER A750shows IPL from IR IPL from IR Connect P C and ER A750 via IR E
35. ADLC 3 Transmission control circuit The transmission control circuit is divided into the modem unit carrier detect unit collision detect unit ADLC TDY MODEM unit ADLC RDX Collision detect unit To transmission driver From transmission receiver Collision detect Carrier detect 1 for data Carrier detect unit Carrier detect 2 for resronse Fig 6 Modem circuit The transmission data input from the ADLC are PE modulated phase encoding modulation the circuit to be output to the transmission driver and the reception data input from the trans mission receiver are demodulated and produced at the ADLC a Collision detect circuit The data transmitted from the home station is received and detects a collision on the transmission line by means of an exclusive OR gate Carrier detect circuit This circuit detects whether data is flowing on the transmission line It consists of a circuit which immediately senses a no data status on the line When data is not on the line the circuit functions to sense an elapse of the fixed time rate The immediate sensing circuit is used for response testing and the delayed sensing circuit is used for data testing The fixed time rate is selectable according to the transmission speed as shown below via SRV mode programming Job 4922 Transmission speed 1 MBPS 480KBPS Delay time 1 6m sec 3 2m sec 4 8m sec 6 4m sec 3 2m sec 6
36. Fig 1 Dummy network The oscillator should be connected to the points indicated by and Connect the positive side of the oscillator Connect the negative side of the oscillator 3 Connections Main PWB 900000000000000d BNC connector Fig 2 Attach the BNC connector to the SRN connector CON 15 on the main PWB 4 Alignment Procedure 1 When Using an Oscillator a Checking the 1MHz oscillator output Using an oscilloscope check the 1MHz oscillator s output waveform SJELER r 1 0 5uS 0 54 S Fig 3 1MHz oscillator output waveform NOTE The oscillator used should have an output impedance of 500 b Connecting the oscillator and its adjustment Connect a dummy network or branch trunk network to the output of the SRN connector CON 15 and connect the oscillator to the dummy or branch trunk network Waveform adjustment Adjust VR4 until the signal waveform as shown in Fig 5 is obtained across IC34 1 of the 75115 and GND pin Turning VR4 clockwise extends the interval of T1 T1 580 to 620ms T2 380 to 420ms VOL Fig 5 Receiver regeneration waveform with dummy network 7 Main PWB Fig 6 Board location 2 When the Branch Trunk Network and Two POS S are Available a Connecting terminals Both ends of the network must be terminated with a 50Q terminator If only two active terminals are tested and left on the
37. LCD front cabinet RCORF6705BHZZ Core LHLDW6821BHZZ Clamp small QCNW 7831BHZZ Earth wire Green Yellow LX BZ6787BHZZ Screw M3 X 5 LX WZ7056AFZZ Fiber washer DUNTK4783BHZZ Keyboard flat include No 9 13 VVLLM320153 1 mim Oo O DI EO O OD DIO O ONO O OJO CO C O OJ OA LCD LM320153 ER A750 1 Top cabinet etc RCPS0150 ER A750 Bottom cabinet etc PARTS CODE DESCRIPTION LANGK7564BHZZ Option angle 1 XHBSD30P04000 Screw 3 X 4 LX BZ1085CCZZ Screw 3 X 8 LX BZ6782BHZZ Screw 3 X 8KS LANGK7571BHZZ Option angle 2 LANGT7607BHZZ M B angle CPWBX7517BH01 Mother PWB unit LANGK7606BHZZ AC sw angle OINI A OVIN XBPSD30P06K00 Screw M3 X 6K XEBSD30P08000 Screw M3 X 8 XBPBZ40P06K00 Screw 4 X 6K LHLDW6820BHZZ Quick clamp Large XHBSD30P12000 Screw 3 X 12 CPWBF7508BH01 N F PWB unit XBPSD30P08KS0 Screw M3 X 8KS RTRNP6892BHZZ Power transformer LBNDJ2003SCZZ Cable band QCNW 7708BHZZ Battery cable 2P CPWBX7510BH01 Main PWB unit
38. M9SVvn Xavi XIVN 661 d 9x4d001 9129 49001 2669 2129 6129 8129 d Z 0229 azzazs Odu or DEL 99 1 92 4 3 MOL H 9169 8129 Q7 a s 84 1 08 s 8 g S 1041 82 LLNIX3 8 01NDXY 02 8 SO1dO arr ISOH art eSOu BR 6668 6174 0628 99 1824 268 Lied 29001 1269 944 LONAS 88 0 lt eSvY MOL Eezy as z 1Ma91 087 lt dSVu LAQUAOH cAQUAOH 9091 cov Lev 02 61 oly SIV viv ev Hv oiv ev 8v IN 9v 99 SS sv wW ev aec L A9 V 3noL 20 99 0OHl 1195 1 13538 vz INN 89 0a7 S O V 08 2 09 1 v9 L I 0819 6410 1110 8219 9419 N MOS SIH zdOd S3u VLL OL S ASe dnZv 19 63 NOILOANNOO 1 11 9661 99098 Wdu GSDNVHO TOSNAS 1711 966
39. Mother PWB unit 10 Service tools m Index ER A750 Top cabinet etc PARTS CODE DESCRIPTION GCOVA7080BHSA LCD cover A GCOVB7081BHZZ Key cover A GCABB7202BHSA Top cabinet MHNG 6638BHZZ Tilt hinge R XBBSD40P12000 Screw M4 X 12 MHNG 6637BHZZ Tilt hinge L PSHEK6818BHZZ Blank key sheet GCOVB7082BHZZ Key cover B OISIN A VIN LFRM 6691BHZZ Key frame PGUMM6712BHZZ Key rubber CSHEP6817BH01 Key sheet unit LPLTM6693BHZZ Key plate XEBSD30P08000 Screw M3 X 8 XEBSD30P10000 Screw 3 X 10 LANGT7559BHZZ PWB angle A GCOVA7131BHZZ Cleark cover LANGQ7565BHZZ Earth spring LX BZ6782BHZZ Screw 3 X 8KS CPWBN7512BH01 Inverter PWB unit CPWBN7511BH01 CKDC PWB unit GCOVH7133BHZZ Invertor cover QCNW 7830BHZZ Flat cable 18pin PSHEK6849BHZZ Key sheet Standard PSHEK6850BHZZ Key sheet Programing LHLDWO0006SCZZ Wire holder NK 3N XBBSD30P06000 Screw 3 X 6 RCORF6698BHZZ Core EF SC18B LHLDW6820BHZZ Quick clamp Large LBNDJ2003SCZZ Cable band QCNW 7829BHZZ Inverter cable XEBSF30P08000 Screw 3 X 8 GCABR7256BHZZ LCD rear cabi LPLTM6714BHZZ LCD plate XHBSD30P04000 Screw 3 X 4 QCNW 7828BHZZ LCD cable XEBSD30P06000 Screw M3 X 6 GCABF7255BHZZ
40. P13 P12 P11 P10 P27 A23 P26 A22 P25 A21 P24 A20 P23 A19 Clock Watch oscillator H8 500 CPU DTC Interruption controller Refresh controller Wait state controller dog timer timer x 2ch 16bit free running Data bus Lower Data bus Upper P22 A18 P21 A17 P20 A16 Address bus A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P37 P36 P35 P34 P33 8bit timer VSS gt VSS VSS gt VSS A D convertor i Serial communication interface x 2ch BREQ BACK WAIT P47 P46 P45 P44 VSS VSS VSS AVCC AVSS gt TXD2 RXD2 TXD1 RXD1 SCK2 IRQ3 mem med uns P43 P42 P41 TMCI P40 IRQ1 SCK1 IRQ2 Port 7 IRQO P73 P72 P71 P70 Fig 2 2 Port 6 P67 P66 P65 P64 P63 62 P61 P60 P57 P56 P55 P544 P53 P52 P51 P50 3 Pin description Function Reset input Non maskable interrupt input for SSP interrupt input NU GND IPLONO IPLON signal for factory setting from expansion I O port PNLSNS IPLON signal for servicing IPLON2 LCD sensin
41. SSP FFFFFFh 4 LCD display The main display is a 320 x 240 dot liquid crystal display The display controller is capable of performing cycle steal actions dis cussed later thus achieving high speed display 9 3MHyr BACK LIGHT ONOFF Fig 4 2 LCD panel The LCD panel is the model LM320153 dot matrix liquid crystal unit which is a blue mode transmission type with a CCFT back light The resolution is 320 x 240 dots with each dot size being 0 33 x 0 33 4 3 Display controller The display controller is the Epson SED1351F0A VRAM is located on the address space of the CPU and it is possible to write and read data freely to and from the CPU Access to VRAM is performed in the cycle steal method so that data can be written and read without disturbing the display screen while the screen is scanned While the Screen is scanned access to VRAM is inhibited Instead VRAM is generally accessed at the fly back time VRAM uses 32 KB of SRAM 7 27 4 4 LCD ON controller The LCD display is turned ON and OFF by controlling the LCD power supply VEE through the LCDENB terminal of the SED1351 The LCDENB is in the L state after resetting Electric power is supplied from the VEE to the LCD by setting the LCDE bit inside the R1 register of the SED1351 to H This makes it possible to turn ON the LCD display 4 5 Back light control The back light is turned on and off through the port P15 of the C
42. U U QCNW 7833BHZZ zuzzzzzzz GLEGP6658BHZZ QCNW 7834BHZZ L QFS B0101QCZZ LANGK7562BHZZ LANGK7564BHZZ QFS B1039CCZZ LANGK7571BHZZ QFS C5012CCZZ LANGK7606BHZZ LANGQ7565BHZZ QFSHD2109AFZZ LANGQ7610BHZZ LANGT7559BHZZ QSOCZ6428ACZZ LANGT7563BHZZ QSW C1262QCZZ LANGT7569BHZZ QSW S0744AFZZ LANGT7607BHZZ QSW S6894BHZZ QTANN6658RCZZ LBNDJ2003SCZZ QTANP0004BHZA O O U U OUO OOO gt gt gt LCHSM6703BHZZ R LFRM 6691BHZZ RALMB6640RCZZ LHLDK6830BHZZ RC AZ1801RCOF LHLDWOO006SCZZ RC FZ1041RC2E LHLDW6820BHZZ RC FZ2241RC2A RCILC6652RCZZ RCILC6653BHZZ LHLDW6821BHZZ RCILC6654BHZZ LPLTM6693BHZZ RCILC6659RCZZ LPLTM6714BHZZ RCILZ1003BHZZ LX BZ1085CCZZ LX BZ6782BHZZ RCILZ5017SCZZ RCORF1008ACZZ RCORF6685BHZZ LX BZ6787BHZZ RCORF6691BHZZ LX WZ7056AFZZ M RCORF6695BHZZ MHNG 6637BHZZ RCORF6698BHZZ MHNG 6638BHZZ RCORF6702BHZZ P RCORF6705BHZZ PFILW6939BHSA RCRMZ1016LCZZ PFILW6964BHZZ RCRSP5019BCZZ PGUMM6712BHZZ RCRSP6664RCZZ PR
43. VERSION example 00 DFFFFFH CHECK SUM CORRECTION DATA This SERVICE ROM allows to write into the FLASH ROM when re execution is impossible because of an abnormality during rewriting into the FLASH ROM The composition is the same as the standard ROM The program version of the IPL is displayed so that OPAGE where the IPL is stored is individually controlled 2 Display Service ROM Sum Check IPL PROGRAM Version PASS or ERROR APL PROGRAM Version 27801R lt Displays the version ER A750 BLOCK Version C0 C1 C2 C3 C4 C5 C6 C7 3 Terminating procedure After displaying the check result press the CANCEL key to ter minate the check 3 SSP Check 1 Check content By starting this check program the SSP setting for checking is automatically performed and the SSP check is executed and the result is displayed The SSP check sets data for check in the vacant space in the SSP entry register and deletes the data for check after comple tion of checking Therefore the already set data are not changed by this check 2 Display SSP Check SSP NMI Check PASS ERROR 3 Terminating procedure After displaying the check result press the CANCEL key to ter minate the check 3 4 Timer amp Keyboard amp Clerk Switch Diagnostics The operation of the clock crystal of CKDC the keyboard and the clerk switch are tested When the CANCEL key is pressed the display retu
44. VHIZ84C3006FE VCCCTV1HH221J VHI27512RDM1A VHI51V8512T12 VCCCTV1HH331J VHI74F02SJ 1 VCCCTV1HH471J VHI74F04SJ 1 VCEAGA1HW104M VHI74F08SJ 1 VCEAGA1HW105M VHI74LVX00 SJ VCEAGA1HW107M VHI7ALVX32 SJ VCEAGA1HW224M VHI7ALVX74 SJ VCEAGA1HW335M VHI76C88LFW15 VCEAGA1HW337M VHVICPSO 5 1 VCEAGU1CW108M VRD RB2HY394J VCEAGU1CW225M VRD RC2EY221J VCEAGU1JW226M VCEAGU1JW228M VRS RE3AAR39J VCEAPS1CC106M VRS RE3LA151J VRS TS1HD122J VCEAPS1CC225M VRS TS2AD000J VCEAPS1CC476M VRS TS2AD100J VRS TS2AD101J VRS TS2AD102J VOKYTV1CF105Z VRS TS2AD103J VCKYTV1HB102K VRS TS2AD104J VCKYTV1HB222K VCKYTV1HB332K VRS TS2AD105J VCKYTV1HB333K VOKYTV1HF104Z VRS T D112J VCQYNA2AM103K VRS TS2AD122F VRS TS2AD122J VCQYNU1HM153K VRS TS2AD123J VHDCP301 1 VHDPS102R 1 VRS TS2AD152G VHDSFPB54 1 VRS TS2AD152J VRS TS2AD153G VHDSFPL52V 1 VRS TS2AD153J VRS TS2AD162J VHD1SS353 1 VRS TS2AD183J VHEMTZ5 1A 1 VRS TS2AD202F VHERD30PB 1 VRS TS2AD222J VHERD36EB4 1 VRS TS2AD224J VHERD5 6PB 1 VRS TS2AD272J VHERD6 8E 1 VRS TS2AD302J VHEUDZ33B 1 VHIF256004PJ1 VRS TS2AD303F VHIGD74HCU04D VRS TS2AD331J VHIGD74HC138D VRS TS2AD332J VHI
45. counter timer channels each with a readable downcounter and a selectable 16 or 256 pre scaler Downcounters are reloaded automatically at zero count Selectable positive or negative trigger initiates timer operation Three channels have Zero Count Timeout outputs capable of driv ing Darlington transistors 1 5mV 9 1 5V NMOS version for cost sensitive performance solutions CMOS version for the designs requiring low power consumption NMOS Z0843004 4 MHz 20843006 6 17 MHz CMOS Z84C3006 DC to 6 17 MHz Z84C3008 DC to 8 MHz Z840C3010 DC to 10 MHz Interfaces directly to the Z80 CPU or for baud rate generation to the Z80 SIO Standard Z80 Family daisy chain interrupt structure provides fully vectored prioritaized interrupts without external logic The CTC may also be used as an interrupt controller 6 MHz version supports 6 144 MHz CPU clock operation 2 General description The Z80 CTC hereinafter referred to as Z80 CTC or CTC four chan nel counter timer can be programmed by system software for a broad range of counting and timing applications The four indepen dently programmable channels of the Z80 CTC satisfy common mi crocomputer system requirements for event counting interrupt and interval timing and general clock rate generation System design is simplified because the CTC connects directly to both the Z80 CPU and the Z80 SIO with no additional logic In larger Systems address deco
46. down counter A timer is triggered automatically when its time constant value is programmed or by an external CLK TRG input Three channels have two outputs that occur at zero count The first output is a zero count timeout pulse at the ZC TO output The fourth channel Channel 3 does not have a ZC TO output inter rupt request is the only output available from Channel 3 The second output is Interrupt Request INT which occurs if the channel has its interrupt enabled during programming When the Z80 CPU acknowledges Interrupt Request the Z80 CTC places an interrupt vector on the data bus The four channels of the Z80 CTC are fully prioritized and fit into four configuous slots in a standard Z80 daisy chain interrupt structure Channel 0 is the highest priority and Channel 3 the lowest Interrupts can be individually enabled or disabled for each of the four chan nels 5 Pin description In Out Function In Out Data bus In Out Data bus In Out Data bus In Out Data bus NC NC NC In Out Data bus In Out Data bus In Out Data bus NC In Out Data bus GND Read cycle status signal NC ZC TOO Zero count Timeout signal NC NC ZC TO1 NC ZC TO2 NC NC NC IORQ Input Output request signal NC Interrupt request signal NC 45V NC Machine cycle one signal N
47. e gt SSPRQ RES STH2 INT2 INT3 RXDI SCK2 HTS2 SLMTR TXDI SLMTS SCKI SLMTD IRQO RJMTR RAS3 NU AO A1 2 2 G A MPCA7 1 Pin configuration VSS ASKRX SYNC DOT8 DOT9 RJMTD RJMTS DOT5 DOT6 DOT7 VSS DOT1 DOT2 DOT3 DOT4 RJTMG RJRST RAS1 RAS2 ROS2 ROS1 A3 4 5 Vcc A6 A7 A8 GATEARRAY LZ9AH30 MPCA7 Fig 2 3 A9 A10 A11 A12 A13 A15 A16 A17 A18 A19 A22 LCDC OPTCS EXINTO EXINT2 EXINT3 WRO RDO RA15 RA16 VSS RA17 RA18 EXWAIT WAIT MCR2 DAX2 PHAI RC IRRX GND VCC UATX UARX UASCK IRTX RCO RCVRDY2 RCVRDY1 MA19 MA18 MA15 TEST MDO MD1 IPLON INT4 PRST PTMG TRGI A23 2 Block diagram A23 A0 IRLON ROST ROS2 RAS1 RAS2 RAS3 OPTCS RASEL Image control Address decode External CS Internal CS SSP comparison register BAR D0 D7 Buffer CHS serial select Read write control Divider INTO control WAIT control CAPS select SSPRQ IRTX I R Control I RCI I ASKRX Multiplexer TXDI SCKI RXDI HTS1 SCK1 STH1 HTS2 SCK2 STH2 INT4 INTI INT2 INT3 EXINT2 gt IRQO Print mode
48. input internal schmit circuit Three state output I O port internal pullup resistor RTS2 2 4 USART MB89371A 1 General The MB89371A Serial data transmitter receiver 2 units is a versa tile use interface LSI for communication lines which is equipped with two sets of equivalent units of the MB89251A serial data trans mitter receiver the baud rate generating section and the interrup tion adjustment section It is positioned between the line Modem and the computer and used for serial parallel conversion of data data send receive opera tion check and the synchronization mode selection according to the program assignment The transmitter section converts parallel data into serial data and adds the parity bit the start bit and the stop bit to them and transmits them In the synchronization mode it transmits synchroni zation characters during no transmission data period In the ad vancement synchronization mode it allows selection of transmission clocks and transmission baud rates The receiving section converts serial data into parallel data and checks parities to judge that data are properly transmitted In the synchronization mode it detects synchronization characters and makes synchronization of transmission reception operations with the transmitter side In the advancement synchronization mode it allows selection of transmission clocks and reception baud rates The baud rate generating sectio
49. network dis connect all other terminals from the network In this case as well both ends of the trunk network must be terminated with 509 R50 Q R50 Q ER A750 ER A750 Fig 7 Terminal connection b Receive level adjustment i Turn on both the receiver terminal and the transmitter terminal ii Run the diagnostic program Flag send check on the transmitter terminal to send a flag iii Checking transmitter terminals output waveform Using an oscilloscope check the transmitter terminal s output signal waveform 105 ius Fig 8 Transmitter terminal s output waveform at transmitter output At the receiver terminal the transmitter terminal s output wave form is subject to attenuation and distortion due to the length of the trunk cable this depends on the characteristics of the cable itself 3 8V Ee EO EO ae ae 0 8V Fig 9 Example of distorted signal waveform at the receiver terminal RG58 U 400m Adjust the receiver terminal adjust VR4 20kQ on the main PWB until the waveform as shown in Fig 10 is obtained at IC34 pin 1 of the 75115 For the location of VR4 see Fig 6 Board location of this subsection Clockwise rotation of VR4 extends the High level pulse width of the signal at IC34 pin 1 of the 75115 Fig 10 Waveform at IC34 pin 1 of the 75115 IC in the receiver terminal 5 Other Checks These Checks should be done After the Receive Level Adjustment is Completed 1 Line driver bias cont
50. not used 14 I O expansion bus specifications 15 Reset sequence The table below shows the standard bus for expanding optional The reset sequence block diagram is shown below Note that RESET devices signal system reset and CKDCR signal CKDC reset are different Table 18 from each other Signal name Signal name VCC GND SLIDE GND Sw CKDCR CKDC reset RD o SUPPLY System reset Fig 14 15 1 Power ON OFF The flow of signal processing at the time of the power supply turning On Off is as follows Table 19 Power OFF Power supply POFF gt L STOP gt L RESET gt L System reset A1 AU Table 20 RESET OPTCS SYNC MCRRDY1 MCRRDY2 Power ON gt Power supply CKDC7 POFF gt H RESET gt H System reset The table below shows the timing chart 1 5V 12V lone N 20ms is assured when as power is off 10ms 1 PGGOOD lt x 200ms lt RESET MIN at System x 4 SHEN in ty gm SCK 8 PULSE Fig 15 15 2 MRS SRV reset The ER A750 does not have the mode switch The procedure for resetting MRS SRV is different from that of conventional cash regis ters in the ER A750 MRS SRV resetting is sele
51. of loop back connector UKOG 6717RCZZ The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed When the CANCEL key is pressed the display returns to the diagnostics menu When setting channels of RS232 do not set two or more ports to one channel In the ER A750 max two units of ER A7RS can be installed In each PWB do not set two or more ports to the same channel If two or more ports should be set to one channel the hardware would be destroyed RS232 I F Diagnostics CHANNELSCheck CH1 Check CH2 Check CH3 Check CH4 Check CH5 Check CH6 Check CH7 Check 1 CHANNEL Check 1 Check content The CHANNEL setting of the connected RS232 is displayed The display content and the setting of DIP SW for CHANNEL setting on the RS232 I F PWB are compared Since the RS232 on the main PWB of the ER A750 is fixed to CH1 and CH2 that in the ER A7RS must be set to CH3 CH7 RS232 I F Diagnostics CHANNEL Check lt Display when channel present CH1 exis t lt Display when no channel CH2 exis t CH3 no CH4 no CH5 no CH6 no CH7 no Reference ER A7RS CHANNEL setting In the table below 1 SW OFF 0 SW ON ER A7RS CON2 O m amp CHANNEL Invalid CHANNEL 1 Impossible to set CHANNEL 2 Impossible to set CHANNEL
52. reemplace la bater a Time to replace Austauschzeit Le temps de la remplacer Tiempo de reemplazo 3 Precautions in installing optional RAM PWBs 1 Background The ER A750 can use the ER 03MB or the ER 04MB as an optional RAM PWB The ER 03MB and the ER 04MB are available in two versions according to the difference in access time of the pseudo SRAM 1 150 ns access time version Not marked with manufactured before June 1996 shipped only to North America and Europe 2 120 ns access time version Marked with manufactured after July 1996 These two versions can be identified one from the other by whether or not the mark is stamped on the white background as shown in Fig 1 and by the marking on the case See Fig 1 PWB marking ER 03MB 04MB PWB Face side Imprint O on this white area Packing case Indivi dual case Imprint O on the right side of the model rabel Colleclive case Imprint O under the model label 2 Cautions to be exercised when using the RAM PWBs with the ER A750 When using the above mentioned RAM PWB version 1 with the ER A750 it is necessary to correct the RAM access timing Use of the above mentioned RAM PWB version 2 does not require the correction of the RAM access timing For this purpose a hardware jumper JP1 designed to judge to determine whether or not to correct the RAM access timing is located on th
53. the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed When the individual diagnostics program is completed the display returns to the menu screen To terminate the diagnostics press the CANCEL key Then the display returns to the SRV mode menu screen ER A750 Diagnostics V 1 0A Product amp Test Diagnostics RAM Diagnostics ROM SSP Diagnostics Clock amp Keyboard amp Clerk Diagnostics Serial I O Diagnostics LCD Diagnostics Rear Display Diagnostics SRN Diagnostics IrDA Diagnostics MCR Diagnostics Drawer Diagnostics Diagnostics End Product amp Test Diagnostics is used only in the production process and must be not used in servicing 3 2 RAM Diagnostics This diagnostics is used to test the standard RAM and the expansion RAM The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed RAM Diagnostics Standard RAM Check VRAM Check ER 03MB Check ER 04MB Check 1 Standard RAM Check 1 Check content For the pseudo SRAM of the standard RAM 512KB the following check is performed The memory contents will not be changed by this check The following processes are performed for the memory address 180000H 1FFFFFH to be checked PASS1 Memo
54. week hour minute Alarm Hour minute Interrupt request event control Detection of key input switch position change alarm issue and counter overflow 2 Pin description In Out Function SB Out Segment B SC Out Segment C SD Out Segment D SE Out Segment E SF Out Segment F SG Out Segment G COM AP Out NC INC NC ING DP Decimal point ID Indicator 5V Clerk key Feed key Switch return signal Key exchange signal Key exchange signal GND 5V Key strobe signal Key strobe signal Key strobe signal Key strobe signal Power off signal STOP signal In Out Function 45V NC 45V Clock signal Key data from host Key data to host GND Buzzer NC Reset signal NC Shift enable signal Key request signal Key return signal Key return signal Key return signal Key return signal CKDC reset signal Clock Clock GND Time clock Time clock 45V Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal NC NC NC NC
55. 00 A62 8X 85 LIS a8 z OLS XEN OX3M YS49 vr z A9L NOL x SO AOL NOL 33Od dOLS S13S3H N3HS Oul MOS SIH HIS dNdOd HOS Sd QJAI HOS SIAIA ANNI 41909 lt Q39NVHO 3NWVN S1HVd 9 1 1 9661 9039 lt 9420 Q35NVHO 31111 1 108661 Zn8 A62 u Q395NVHO TOSNAS 1 1 1 9661 HOS Sd Q4AHOS 3IAIY HOS dNdOd Q3AOWN3H 133HS 1 1 1 9661 9092 92157 4 ga sessi 4 HS39 05 1 ved 868 GZLSTbZ EG OH PL 3991 oc DL 8 v akt LEM 9215794 9901 ab ESLOH PL SzISTr oz 921 DL 8 v a 91 1 lt 92157174 GEDI ran vonono 91 1 lt su z o 921514 DEDI c8Md GMO lt 31 AIM ZEMd 90310 Q39NVHO JIL 1 1 1 966 02 ESESSL 8 51 SzISTrZ 8
56. 00H 220000H 240000H 280000H 300000H 2 Display ER 04MB Check Extended RAM size 2048KB PASS l or ERR Address XXXXXxH Write Data Read Data Error The error address and the bit are displayed only when the error occurs If the error does not occur they are not displayed 3 Terminating procedure After completion of check press the CANCEL key 3 3 ROM amp SSP Diagnostics The standard ROM and the service ROM are checked The SSP circuit is also checked The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed ROM amp SSP Check Standard ROM Check Service ROM Check SSP Check 1 Standard ROM Check 1 Check contents The standard ROM area C00000H CFFFFFH is added in the unit of byte If the lower two digits of the result is 10H it is normal The ROM version and the model name code which are stored in address CFFFEOH CFFFEFH where the ROM version and the check sum correction data are stored are displayed The format of data ASCII to be stored is as follows CFFFEOH CFFFEFH Model name code example ER A750 Display is made up to 00H of data CFFFFOH CFFFF9H 27801 R PROGRAM VERSION CFFFFAH CFFFFBH BLOCK NO CO CF CFFFFCH TERMINATOR CFFFFDH CFFFFEH B
57. 1 LLNIX3 01NIX3 20H1 LOHL 3 ALS 1HOd 1 01 9661 ZVOdW 9W0dN Q3WVN3H 81091 1 01 9661 1NS008482H1 99 DON 99 ddA OND OND OND 5 gt 3 E BE 43 BEE ol 13539 ol 13938 vet eSOH OrF ISOH OF 1 SdSVvu ec 01 338 54 HV ev 8v YM 12 r4 vc Sc 9c 26 86 66 Og LAVZIS8ALSOL SIVIN 16 vO l SON 90 1 ZONA 39 HS4u30 ev sv am Lv SIV 99 SSA eon 10 1 00 1 Ov I ev rv Sv 9v lv 9 81 9121 0910 019 SO AOL ANOL 89 07 6 08 08 2 09 1 v9 L VZXNTYL O9r lt sgesvud 5 lt 5 d 0821 o3 LLL L 98021 v SAYA 13538 I3S3H ve j3HSd VZXNTL SINN ver 8 43538 svHu ort 135538 30001 dsvu are a 9 6 ar ZL m gt LL L ord 1438584 5 S dw v L 13538
58. 10uF Capacitor SOWV 0 1uF C3 13 16 VCKYTV1HF104Z Capacitor SOWV 0 1 BC1 2 4 5 8 VHD1SS353 1 Diode 155353 D1 13 24 26 VHIGD74HC138D IC 74HC138 IC1 2 VHIGL339AD 1 IC GL339A SOP IC7 VHIH4728A96FS IC H4728A96FS IC8 VHISN74HC153D IC 74HC153 1C4 5 VRS TS2AD000J Resistor 1 10W 0Q 5 R27 34 VRS TS2AD103J Resistor 1 10W 10KQ 5 R54 55 VRS TS2AD104J Resistor 1 10W 100KQ 5 R29 32 40 48 51 57 65 VRS TS2AD105J Resistor 1 10W 1MQ 5 VRS TS2AD112J Resistor 1 10W 1 1KQ 5 VRS TS2AD152G Resistor 1 10W 1 5KQ 2 VRS TS2AD202F Resistor 1 10W 2KQ 1 VRS TS2AD303F Resistor 1 10W 30KQ 1 VRS TS2AD432J Resistor 1 10W 4 3KQ 5 VRS TS2AD472J Resistor 1 10W 4 7KQ 5 VRS TS2AD473J Resistor 1 10W 47KQ 5 R1 12 15 26 VRS TS2AD513J Resistor 1 10W 51KQ 5 R56 VRS TS2AD562J Resistor 1 10W 5 6KQ 5 VRS TS2AD622J Resistor 1 10W 6 2KQ 5 VSDTC114YK 1 Transistor DTC114YK QFSHD2109AFZZ Fuse holder RCORF6691BHZZ Core BFS3550R2F VCEAGU1JW226M Capacitor 63WV 22uF VCQYNU1HM153K Capacitor SOWV 0 015 QCNCM5091BC1B Connector MLX 5597 12CPB QCNCM7136BHZZ KEY connector 5229 13APB QCNCW7207RC1H Connector MLX5597 18CPB QC
59. 12 GND SL20 GND RS 232 UNIT2 channel select OI GOO N SL21 GND SL22 GND SL30 GND RS 232 UNIT3 channelselect SL31 GND SL32 GND CS0 CS1 RS 232 USART chip select CS1 CS2 CS2 NC CS3 SRCS RS 232 INLINE USART chip select CDO DCD1 RS 232 control signal CD input CD1 DCD2 CD2 45V CD3 P0 SINT RS 232CD INLINEPO CTSO CTS1 RS 232 control signal CTS input CTS1 CTS2 CTS2 45V CTS3 P1 GND RS 232CTS INLINEP1 Clo CI1 RS 232 control signal Cl input CI1 Cl2 Cl2 5V CI3 P2l GND RS 232CI INLINEP2I BRKO BRK1 RS 232 USART BREAK signal BRK1 BRK2 POFF POFF POFF signal LOW P OFF HIGH P ON BRK3 GND RS 232 INLINEUSARTBREAKsignal RCVRDYO RCVRDY 1 RS 232USARTRCVRDY signal RCVRDY 1 RCVRDY2 RCVRDY2 GND RCVRDY3 GND RS 232 INLINEUSARTRCVRDYsignal TRNRDYO TRNRDY1 RS 232USART TRNRDY signal TRNRDY1 TRNRDY2 TRNRDY2 GND TRNRDY3 GND RS 232 INLINEUSARTTRNRDYsignal TRNEMPO TRNEMP1 RS 232 USARTTRNEMP signal TRNEMP1 TRNEMP2 TRNEMP2 GND TRNEMP3 5V RS 232 INLINEUSARTTRNEMP signal RCVDTO RCVDT1 RS 232 RCVDT signal LOW TIMER START RCVDT1 RCVD
60. 16 17 21 23 26 VCEAPS1CC476M Capacitor 16WV 47uF C1 27 VHERD30PB 1 Zener diode RD30P ZD5 VHERD5 6PB 1 Zener diode RD5 6PB 204 VHI51V8512T12 PSRAM TC51V8512AFT 15 IC16 VHI74F02SJ 1 IC 74F02SJ IC4 VHI74F04SJ 1 74F048J IC9 OINI A VIN VHI74F08SJ 1 74F08 IC5 VHI74LVX00 SJ 74LVX00 IC3 VHI74LVX32 SJ IC IC IC IC 74LVX32 IC8 VHI74LVX74 SJ IC 74LVX74 IC7 VHI76C88LFW15 64K S RAM GM76C88ALFW 15 IC33 VHIF256004PJ1 IC F256004PJ1 IC19 VHIG76C256F70 G76D256F70 IC10 VHIGD75189D 1 GD75189pD IC21 VHIGL339AD 1 GL339 IC13 VHIH641510810 IC IC 41 510810 IC17 VHIIR9393N 1 IC IR9393N IC30 VHILHF80S01 1 FLASH ROM LH28F800SUT 1C6 VHILZ9AH39 1 IC LZ9AH39 IC18 VHIMB62H149 1 IC MB62H149 IC25 VHIMB89371APF IC MB89371APF G BND 1020 VHIMC145406F 1 IC MC145406F IC14 22 VHIMC34063AM1 IC MC34063AM1 IC29 VHIRHSRE33A 1 RX5RE IC27 VHISED135FLOA IC SED135F IC11 VHISN74HCOONS IC SN74HCOONS 1C2 36 37 VHISN74HC04NS IC SN74HCO4NS IC31 VHISN74HCO8NS SN74HC08 038 VHISN74HC32NS IC SN74HC32NS IC12 VHIGD74HC74D1 IC GD74HC74 IC
61. 20 veo 889 15 9 8 v 221 8 51 92157 4 VEO ELS aet rAMTHONDHRO z o eo N Ang 100 019 vt 99 29838908 u 6E 0 ML 6ru 2 VS L v 9 Moor 719 34088 T a et 04221 15 LL 688281 99 ywost ega9equ 102 9 4 22 519 N 14 Oe v eed Q39VNHO9 S1HVd 1 1 1 9661 GMd 2039 lt AlddNS H3MOd GSA Q35NVHO ITIL 1 9661 EGMd 9092 YS ZdNINHLZAAYAOU ZLOADH ZAGYNHLZOOA TSLO ZID bya Ld N3NHL LAQHAOH LLGAOH FAGHNHL LAOG LS19 HO Q39NVHO 1HOd 1 01 9661 Li AQWANOL 90vSt LOW VIZE68EN SLO I 6 ansa OND ZXIHS ONAS 25197 ZdWANYL TAWINYL 2519 ZAQHAOH ZAQHAOH Cso gt 5157 25107 ZAQHNHI ZAQUNHL N3dO t 9 2X9 9H N3dO
62. 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 0 1 0 1 0 1 0 1 ER A7RS CON3 CHANNEL a 2 Invalid CHANNEL 1 Impossible to set CHANNEL 2 Impossible to set CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 4 o o a a 0 o OO OO OO 2 Terminating procedure Press the CANCEL key to terminate the check 2 CH1 Check 1 Check content When the channel is not set an error display is made ERROR CH1 When the channel is set the following check is performed Control signal check The read check of the above inputs and the interruption check of CS CI and CD are performed In the read check ER and RS are changed over in the above sequence and the logic states of DR CI CD and CS are checked If the logic differs from that in the table an error display is made ON in the table means Active LOW and OFF means Active HIGH In the interruption check an interruption of CS CI or CD is allowed one by one MASK is canceled If an interruption is not made when each signal is active or if an interruption is made when each signal is not active an error display is made The above check is repeated four cycles Data transfer check The loop back data 256 bytes of 00H OFFH are used for data transfer check The b
63. 3 OINIX3 ZOHL LOH L 212 G3ONVHO FTALS 1HOd 16 01 9661 go Aal t AWZ Q35NVHO TOSNAS 1 01 9661 DIHA lt WVHA J G3ONVHO 3WVNY1OSWAS 16 01 9661 IDA HOLO3NNOO NIVIN 8cH Q31HOHS Q3AOW3H SLYVd S L 1 9661 7oo iqu la1 s3H 8 538 NYS LYOd HOS ZNuS aaaav 180d GONW Q3AOW3H 133HS 16 01 9661 6SESH1 Zeol ddA 30 39 viv ev uv ev sv Lv 9v sv 2 NYS lt INHS 439 31111 LE 0L 966L L A9H 4NOL 019 082 6691 201792 10092 HOHL MTO 0002 0941 79 2 309 vee 92 2 1 NYS OLe 8518 NYS 104Ova S MOI S v 99221 1 800HvZ 88 800HvZ TE ISH S 058 5 L 35 34066 IM 6v LH298IN Nid 22 Nid 9 Nid c Nid 2 ON 080 ser MOL 6829 99 SO AOLHnOL 910 6919 HYM HOu vYOOHvZ 3 01
64. 3BHZZ Connector MLX 5046 02A CON15 QCNCM7205RCOB PS connector MLX 5274 02A CON13 QCNCW1057ACZZ Connector Short socket JP1 5 6 QCNCW7081BHZZ Connector 2P 5267 02A Blue CON1 1 QCNCW7086RC5J Connector 50pin CON14 QCNCW7204RC8J Connector 80pin ST 10 5061 080 CON12 QCNCW7206RC1H CKDC connector 18pin MLX52045 1845 CONS QFS B1039CCZZ Fuse UL1 5A 125V F1 QFS C5012CCZZ Fuse S 0 5 250T F2 QSOCZ6428ACZZ IC socket 28P IC32 QSW S0744AFZZ Reset switch 555312 S2 QSW S6894BHZZ Slide switch RA S1 RCILC6652RCZZ Coil MC182 201M L1 RCILC6653BHZZ Choke coil 1804H L2 RCRSP6664RCZZ Crystal 19 66MHz X1 RCRSZ6662RCZZ Crystal 9 83MHz X3 RTRNH6894RCZZ Converter transformer SEE 16 T201 RVR B2410QCZZ Variable resistor 5K VR1 2 RVR M2415QCN3 Variable resistor 20K VR4 VCEAGA1HW337M Capacitor 50WV 330 C5 VCEAGU1CW108M Capacitor 16WV 1000uF C18 VCEAGU1JW228M Capacitor 63WV 2200 C25 VHDCP301 1 Diode CP301 BD201 VHEMTZ5 1A 1 Zener diode MTZ5 1A ZD3 VHIKIA7806P 1 IC KIA7806P 035 VHIL4960 1 IC L4960 IC40 VHIMC68B54 1 IC MC6BB54P 1C39 VHI27512RDM1A IC 27512RDM1A IC32 VH
65. 41 VHIGD74HCU04D IC GD74HCU04 1026 VHISN75115NS1 IC SN75115NS1 1034 VHITC7S86F 1 IC TC7S86F IC28 VHITD62308F 1 IC TD62308F IC15 VHIUPD71037GB IC UPD71037GB IC42 VHIZ84C0006FE IC 284 0006 IC24 VHIZ84C3006FE IC 8403006 1023 VRS TS1HD122J Resistor 1 2W 1 2KQ 5 R1 VS28C4699KP 1 Transistor 25 4699 Q9 10 VS2SJ187 1 Transistor 2SJ187 Q8 VSDTA144EK 1 Digital transistor DTA144EK Q4 VSDTC114YK 1 Transistor DTC114YK Q5 RCILZ5017SCZZ Chip coil BLM3 FB101 109 111 126 RCORF1008ACZZ Chip bead BUM21A05 FB110 127 VCCCTV1HH101J Capacitor SOWV 100PF C101 107 109 121 126 143 148 155 159 164 169 170 174 176 183 VCCCTV1HH101J Capacitor 50WV 100PF C185 187 189 192 195 202 203 207 209 211 214 227 236 VCCCTV1HH101J Capacitor 50WV 100PF C238 242 258 267 274 VCCCTV1HH221J Capacitor 50WV 220PF C252 253 264 VCCCTV1HH38381J Capacitor 50WV 330PF C147 161 175 188 193 194 196 201 204 206 212 228 234 210 VCCCTV1HH38381J Capacitor 50WV 330PF C213 235 237 254 VCKYTV1CF105Z Capacitor 16WV 1 C249 VCKYTV1HB102K Capacitor BOWV 1000PF C108 122 123 125 255 260 VCKYTV1HB222K Capacitor 50WV 2200pF C276 VCKYTV1HBS332K Capacitor 50WV 3300PF
66. 45V Z80 CPU Al D2 AO D7 GND DO RFSH Di RESET 11 23 12 22 ES HO c G 5 e I o 2 3 m m 44 pin Quad Flat Pack QFP Pin Assignments Only available for 84C00 3 General description The CPUs are fourth generation enhanced microprocessors with ex ceptional computational power They offer higher system throughput and more efficient memory utilization than comparable second and third generation microprocessors The internal registers contain 208 bits of read write memory that are accessible to the programmer These registers include two sets of six general purpose registers which may be used individually as either 8 bit registers or as 16 bit register pairs In addition there are two sets of accumulator and flag registers A group of Exchange instructions makes either set of main or alternate registers accessible to the programmer The alter nate set allows operation in foreground background mode or it may be reserved for very fast interrupt response The CPU also contains a Stack Pointer Program Counter two index registers a Refresh register counter and an Interrupt register The CPU is easy to incorporate into a system since it requires only a single 5V power source All output signals are fully decoded and timed to control standard memory or peripheral circuits the CPU is supported by an extensive family of peripheral controllers The internal block diagram Figure 3 shows th
67. 4m sec 9 6m sec 12 8m sec 3 Terminal Name and Description MB62H149 Terminal nana Description RES Reset 23 9 0 6 I O write 20 IO RD I O read 63 JO AEN Address enable from DMAC NAN AST Address strobe from DMAC TT 49 TCS DAK23 DMA acknowledge 2 3 DRQRS DMA request read to sub DRQWS DMA request write to sub C D ELI RDH Read from Host EE VE WRH write from Host ES INTH Interrupt to host DAK DMA acknowledge from host a TCH Terminal count from host START ET TTT EAP ET TT DROWH DIMA eG host LEAD DRQWH DMA request write to host iS mE 035201 CS Chip select from host VSS GND N U DBO Data bus DB1 Data bus DB2 Data bus DB3 Data bus DB4 Data bus DB5 Data bus DB6 Data bus DB7 Data bus ABO Address bus from host N U AB1 Address bus from host COL Collision detect signal RDI Receive data from receiver TDI Transmmit data to driver RTS Request to send RXC Receive clock to ADLC RXD Receive data to ADLC Terminal name CLK Clock in 16 MHz N U IORQ I O request MREQ Memory request RDS Read from sub WRS Write from sub INTS Interrupt to sub Clock out TMO Timer 0 TM1 Timer 1 MRD Memory read VSS GND WAIT Wait signal A15 Address bus for DMA A9 A8 Description TXC Transmmit clock TXD Transmmit data VDD 5V E Enable clock to ADLC IRQ Interrupt req
68. 8197 gt osv 183 OND gt gez 99 OND ZAQHNHL DAHON eysa 2510 6518 8 L88 ONAS dWANYL LAGHADH LAGHNHI 1 Fas 1510 L1GAOH 1519 1810 LONHL 2 DET 90 4 99 1HVSn 319 luvsn Sau IHY 9 2 OHV az ale 9 2 azz are YE Zd ANY L Z AQHAOH ZLOAOH ZAGHNHLZADAZSLO TID ID4H8 LdW3NHI LAQHAOH LLOAOH LAQHNH L LIOQ LS19 HO Q39NVHO AdAL 1HOd 17 11 9661 TEZSU SUL lt Iuvsn X19 94 981 lt 1uvsn sau 938 2215 LIO 6119 1219 219 1NOX 9110 020 220 velo 0615 g9 1 Dua 89 1 LdW3NHL OdW3NHL 89 1 IAGHA9H 0AQHAOH 09 1 11 99 1 FAGHNSL OAGHNHL 99 1 ZANINUL zga ega OND vaa sga 98a 19 ZAGHNHL LAGUNHL ZAQHAOH LAGHADH ZLOADY ZAQHAOH 2115 0118 2015 1015 9 did MS 0015 5 009 os 1 1S197 0510 1
69. C System clock NC Chip enable signal Reset signal Channelselect signal NC Channelselect signal CLK TRG3 External clock timer signal CLK TRG2 External clock timer signal NC NC NC NC CLK TRG1 External clock timer signal CLK TRGO 5V NC NC 5V 5V NC NC 2 7 uPD71037 3 Pin configuration DMACONTROLLER In Out Function The uPD71037 is a direct memory access controller DMAC for the Ready signal micro processor system It provides higher processing speed and Hold led Gaal lower power consumption in comparison with those in conventional MO ACKNOW oe signa use Each of the four built in DMA channels has 64 KB addresses Address strobe signal and the function of counting the number of bytes of transferred data Address enable signal and can transfer data from I O to memory and from memory to Hold request signal memory as well NC RE I FEATURES Chip select signal The clock speed is 10 MHz twice that of the uPD8237A 5 clock Clock speed of 5 MHz RESET SRNRESET Reset signal Each of the four DMA channels can be operated independently DMAAK2 SDACK2 DMA acknowlidge signal Each channel can be self initialized DMAAK3 SDACK3 DMA acknowlidge signal Data is transferrable from memory to memory DMARQ3 SDRQ3 DMA request signal Data in memory can independ
70. CS DB4 DO GND D1 DB3 D2 OPC1 DB2 D3 F256004PJ GND DBO D4 TRNEMP1 D5 TRNRDYO D6 RCVDTO D7 RCVRDYO RSRQ TRNEMPO A0 BRKO 5130 2 5122 4 RES 3 Block diagram e TO FROM USART m m c cn m m m m xXx or gt x KE D7 TCR D6 Inline OCS DS cont a Data bus buff D3 TASUS YTE Timer0 control RCVDTO D2 D1 DO WRO TCR1 RDO nee Read write W control Timer1 control RCVDT1 R lt RES AB1 Timer1 ABO ns TCR2 A4 A3 Decorder A2 control I A1 Timer2 control RCVDT2 0 lt Timer2 SL00 SL01 SL02 TCR3 SL10 8111 SL12 Timer3 control RCVDT3 SL20 5121 8 e SL22 3 SL30 5131 o SL32 S GER RTS CNT iu USICH RTSO CS3 CS2 CS1 TSO RCVRDY3 RCVRDY2 Interrupt control RCVRDYO TRNEMP3 TRNEMP2 TRNEMP1 TRNEMPO x u e 2 a o S Aje er amp O S B GERE BC CP Ree gss Gregg o o KE 22 2 FREE 4 Pin description OPC1 pin table z o Pin name The signals marked with at the end are LOW active signals Example CS1 CS1 ER A750 Description SLOO 5V RS 232 UNITO channel select SLO1 GND 5102 GND SL10 GND RS 232 UNIT1 channel select SL11 45V SL
71. DAF6667BHZZ RCRSP6676RCZZ PSHEK6818BHZZ RCRSZ6644RCZZ PSHEK6849BHZZ RCRSZ6662RCZZ PSHEK6850BHZZ RTRNH6894RCZZ PSHEZ6824BHZZ RTRNH6895RCZZ RTRNH6896RCZZ PSPAG6728BHZZ O OO OU U U RTRNP6892BHZZ 10 www O O O O ER A750 PARTS CODE PARTS CODE RVR B2410QCZZ VHIGL339AD 1 RVR M2415QCN3 S VHIG76C256F70 SPAKA8377BHZL VHIH4728A96FS SPAKA8377BHZR VHIH641510810 SPAKA8384BHZZ VHIIR9393N 1 SPAKC8378BHZZ VHIKIA7806P 1 SPAKC8379BHZZ VHILHF80S01 1 SSAKH0003DHZZ VHILT1184CS 1 SSAKH3015CCZZ VHILZ9AHS9 1 SSAKH4231CCZZ U U VHIL4960 1 T VHIMB62H149 1 TCADH6788BHZA VHIMB89371APF TCADH6805BHZZ VHIMC145406F1 TCAUZ6685BHZA VHIMC34063AM1 TCAUZ6687BHZA VHIMC68B54 1 TINSE7382BHZZ VHIRHSRE33A 1 TINSE7384BHZZ VHIRPM850CB 1 TINSF7385BHZZ VHISED135FLOA TLABG6967BHZZ VHISN74HCOONS TLABG6978BHZA VHISN74HCO4NS TLABG7026BHZZ VHISN74HC08NS TLABS7021BHZZ VHISN74HC153D U VHISN74HC32NS UBNDA6629BHZZ VHISN75115NS1 UKOG 6705RCZZ VHITC7S86F 1 UKOG 6718RCZZ VHITD62308F 1 IV VHIUPD71037GB VCCCTV1HH101J VHIZ84C0006FE VCCCTV1HH150J
72. Data bus RCVRDY1 MCRRDY 1 Data bus RCVRDY2 MCRRDY2 GND RCO Nu Nu Data bus IRTX IRTX output for LED Data bus UASCK UASCK V R serial data shift clock Data bus UARX UARX V R serial data for CPU Data bus UATX UATX I R serial data from CPU SSP interrupt request to CPU VCC 5V MPCA reset GND 5V I R input from IR unit 5V GND 8 bit serial port output to System clock 7 3728MHz GPU System clock 7 3728MHz 8 bit serial port input from CPU Function Wait request signal Function External wait control input signal NU Nu Nu Nu Nu Expansion RD signal Option Expansion WR signal Option Expansion interrupt signal Option Expansion interrupt signal OPC1 Expansion interrupt signal Option Expansion interrupt signal Option Chip select base siganal for expansion option ROM 1 chip select signal ROM 2 chip select signal Nu Nu Nu Nu Nu Nu Nu Nu Nu Nu Nu Nu Nu I R input from IR unit 45V GND Nu RAMS chip select signal GND
73. FUNC TEX1 TEX2 87 8 90 ae 1 more f RP V EMP AUTO 79 ai senol 2 nc ES DRV n 72 rer BEND 25 gt sje NDSE CHK CH 52 B 54 SBTL 4 e m som PAST f SBTL PLU TRAY 45 VOID VOID SUB SBTL 2 e w o s Q i 8 Je Je Je Je Le Le Je N N m m a je lete AASS hse 21 4 5 ef CHEESE A 3 12 s Je Je foof Lec 7 2 Key top name 1 Standard key top KEYTOP DESCRIPTION 0 9 00 Numeric keys Decimal point key CL Clear key FOR Multiplication Split pricing key RCPT Receipt print key RPSEND Remote printer send key d1 Discount 1 key 1 Percent 1 key TAX1SHIFT TAX2SHIFT Tax 1 and 2 shift keys RFND Refund key VOID Void key PASTVOID Past void key SBTLVOID Subtotal void key RTN Return key PLU SUB Price lookup Subdepartment key 1 99 Direct price look up key LEVEL 1 5 PLU level shift 1 5 keys SRVC Service key FINAL Final key BAL Balance key DRVNC New check 2 key For drive through DRVGLU Gest look up 2 key For drive through SERV Server code ent
74. GD74HC74D1 VRS TS2AD362F VHIGD75189D 1 DDD OD Q DDD UIO O OO O O OO OI OJ O O O O O O OJ OJ O FOO OJOIOJO JO JO IO JO TO VRS TS2AD392G ENS OOO O O OBO OJ OJ TO O O OIOIOIO IO Q IOJOIOIOIOIOO OIOIOIOIOIOIOJO O O OU DC 07 07 07 07 07 07 07 07 07 07 07 07 07 OJ 07 07 07 07 07 OJ 07 07 UU UJ UU J UJ U UU ER A750 PARTS CODE PARTS CODE VRS TS2AD432J VRS 1 D470J VRS 1 D472J VRS 1 D473J VRS 1 D512F VRS 1 D513J VRS 1 D561J VRS 1 D562J D563J D622J D682F D751J D752F VRS 1 D8R2J VRS 1 D822G VRS TS2HD470J VSDTA144EK 1 VSDTC114YK 1 VSKTD14151 1 VS2SA1270 1 VS2SB822 1 VS2SC2021 1 VS2SC4352 1 VS2SC4699KP 1 VS2SC5001R 1 VS2SJ187 1 VVKFIP7B13 1 VVLLM320153 1 X XBBSD30P06000 XBBSD40P12000 XBPBZ40P06K00 XBPSD30P06K00 XBPSD30P08KS0 XEBSD30P06000 XEBSD30P08000 07 UD DDD XEBSD30P10000 XEBSF30P08000 XHBSD30P04000 XHBSD30P 12000 XJSSF30P 12000 XUBSD30P 12000 XUPSD40P 12000
75. H write PASS5 Data AAAAH read compare PASS6 Memory data writed the saved data In case of a compare error in the check sequences of PASS1 PASS6 an error display is made If there is no error at all the check is normally terminated In addition the following address check is performed in the above check sequence In case of an error an error display is made and read write of the address where the error occurred is repeated Check point address 100000H 100001H 100002H 100004H 100008H 100010H 100020H 100040H 100080H 100100H 100200H 100400H 100800H 101000H 102000H 2 Display VRAM Check VRAM memory size 32KB RROR PASS or Error Address XXXXXxH Write Data Read Data The error address and the bit are displayed only when the error occurs If the error does not occur they are not displayed 3 Terminating procedure After completion of check press the CANCEL key 3 ER 03MB Check 1 Check content The ER 03MB presence check is performed in the following pro cedure The memory contents will not be changed by this check 55AAH is written into 2FFFFEH 2FFFFEH is read and compared with 55AAH If the both data are correct the following procedure is performed If not Ex tended RAM size OKB is displayed and the check is ter minated 55AAH is written into 3FFFFEH 3FFFFEH is read and compared with 55AAH If the both data are not correct the followi
76. ING ADDRESS GENERATING CIRCUIT COUNTER DISPLAY DATA CONTROL UD0 UD3 CIRCUIT LDO LD3 VD0 VD15 4 Pin description Function GND 45V IOC Chip select signal for control register OW Write strobe signal for control register IORD Read strobe signal for control register MEMCS VRAM chip select signal MEMWR VRAM write strobe signal MEMRD VRAM read strobe signal READY Ready signal MPUCLK Clock signal RESET RESET Reset signal MPUSEL GND GND BHE VCC 5V ABO AO Address bus AB1 A1 Address bus AB2 A2 Address bus AB3 A3 Address bus AB4 A4 Address bus AB5 A5 Address bus AB6 A6 Address bus AB7 A7 Address bus AB8 A8 Address bus AB9 A9 Address bus AB10 Address bus AB11 Address bus AB12 Address bus AB13 Address bus AB14 Address bus AB15 Address bus DBO In Out Data bus DB1 In Out Data bus DB2 In Out Data bus DB3 In Out Data bus DB4 In Out Data bus DB5 In Out Data bus DB6 In Out Data bus DB7 In Out Data bus DB8 GND DB9 GND DB10 GND DB11 GND DB12 GND DB13 GND DB14 GND DB15 GND VWE VRAM write strobe signal VAO
77. IRPM850CB 1 IC RPM 850CB IC1 VRD RC2EY221J Resistor 1 4W 2200 5 R6 VRS RE3AAR39J Resistor 1W 0 390 5 R2 VRS RE3LA151J Resistor 3 0W 1500 5 R4 VS28B822 1 Transistor 2SB822 VS28C2021 1 Transistor 2902021 VS28C4352 1 VSKTD14151 1 DDD DOO 07 DDD WOO O 0 DDD TOO U MO gt P OJ O OJO OI OJ O O O O OJO JO JO OBO JO OJ OJ OIJO Transistor 2904952 Transistor KTD1415 Main PWB unit PARTS CODE DESCRIPTION ER A750 LX BZ6782BHZZ Screw 3 X 8KS IC40 Unit CPWBX7510BH01 Main PWB unit Mother PWB unit PARTS CODE DESCRIPTION QCNCM7203RC8J Option connector 20 5061 080 CON10 QCNCW7204RC8J connector 80pin ST 10 5061 080 CON8 9 VCEAPS1CC476M Capacitor 16WV 47 C8 Unit CPWBX7517BH01 Mother PWB unit CKDC PWB unit PARTS CODE DESCRIPTION RCILZ5017SCZZ Chip coil BLM3 FB10 17 VCCCTV1HH150J Capacitor BOWV 15PF C8 9 VCCCTV1HH3831J Capacitor 50WV 330PF C14 VCCCTV1HHA471J Capacitor 50WV 470PF C4 5 6 7 VCEAPS1CC106M C2 12 VCKYTV1HB102K Capacitor 50WV 1000PF C11 VCKYTV1HF104Z Capacitor 16WV
78. KOG 6705RCZZ PARTSCODE For RS232 connector DESCRIPTION STANDARDKEYSHEET PSHEK6849BHZZ PROGRAMMINGKEYSHEET PSHEK6850BHZZ BLANKKEY SHEET PSHEK6818BHZZ 5 How to use service tools Connection diagram 5 1 Expansion PWB CKOG 6724BHZZ Extrenal view ER A7RS ER A750 bus connector Plain view Test pins Used to check the bus signals 5 2 MCR test card UKOG 6718RCZZ Used when executing the diagnostics of the ER A8MR Bus connector Used to check the bus signals External view 0000000000000000 0000000000000000 Connected to the ER A750 Mother PWB CHAPTER 3 SERVICE PRECAUTION 1 Adjustment for SRN IN LINE interface circuit If transistor Q10 in the transmitter receiver section has been re placed or if the SRN level requires readjustment the following align ment is required 1 Tools and Instruments Required 1 Oscilloscope 50MHz or better 1 2 ER A750 2 Dummy Network Specifications R2 C1 4 R1 100 J 1 4W carbon R2 150 Q J 1 4W carbon 0 011 F mylar firm
79. LOCK VERSION example 00 CFFFFFH CHECK SUM CORRECTION DATA The flash ROM used as the standard ROM has rewriting block of 64KB as the unit To control the version in each block the com position is the same as the above CFFFFOH or later and arranged in each 64KByte At that time correction is made so that the sum of each block becomes 01H and the total of 1MByte is 10H The program version of the IPL is displayed so that OPAGE where the IPL is stored is individually controlled 2 Display Standard ROM Sum Check IPL PROGRAM Version PASS or ERROR APL PROGRAM Version 27801R lt Displays the version ER A750 BLOCK Version C0 C1 C2 C3 C4 C5 C6 C7 3 Terminating procedure After displaying the check result press the CANCEL key to ter minate the check 2 SERVICE ROM Check 1 Check content The standard ROM area D00000H DFFFFFH is added in the unit of byte If the lower two digits of the result is 10H it is normal The ROM version and the model name code which are stored in address DFFFEOH DFFFEFH where the ROM version and the check sum correction data are stored are displayed The format of data ASCII to be stored is as follows DFFFEOH DFFFEFH Model name code example ER A750 Display is made up to 00H of data DFFFFOH DFFFF9H 27801R PROGRAM VERSION DFFFFAH DFFFFBH BLOCK NO CO CF DFFFFCH TERMINATOR DFFFFDH DFFFFEH BLOCK
80. NW 7826BHZZ Pop up cable 9pin QCNW 7827BHZZ Pop up cable 11pin QFS B0101QCZZ Fuse 125V 150mA RALMB6640RCZZ Buzzer SMX06 RCRSP6676RCZZ Crystal 32 768KHz RCRSZ6644RCZZ Crystal 4 19MHz RTRNH6895RCZZ Converter transformer VHDPS102R 1 Diode PS102R VHERD36EB4 1 Zener diode RD36BB4 VHERD6 8E 1 Zener diode RD6 8E VRS RE3AAR39J Resistor 1W 0 390 5 VS28C4352 1 mO D DD D UD DV gt O O O O O O OJO GO OJ O DID 00 U U OO Transistor 2904952 Unit CPWBN7511BH01 CKDC PWB unit ER A750 N F PWB unit PARTS CODE DESCRIPTION VRD RB2HY394J Resistor 1 2W 390KQ 5 QCNCW7199BHOE Connector 35328 0510 QFS B1039CCZZ Fuse UL1 5A 125V QFSHD2109AFZZ Fuse holder QSW C1262QCZZ Power switch AJ7241B QTANN6658RCZZ Block terminal GSK801 2DS RC FZ1041RC2E Capacitor 250WV 0 1uF INS DJOT AJ 0m RCILC6654BHZZ O O O DO gt O O Coil 5021C Unit CPWBF7508BH01 m N F PWB unit PARTS CODE Inverter PWB unit DESCRIPTION RCILC6659RCZZ Chock coil D10F A814AY 101K RTRNH6896RCZZ Transformer BLC216HP 841TN 1024 VCEAPS1CC225M Capacitor 16WV 2 2uF RC AZ1801RCOF Capaci
81. PU The initial value is L in which the back light is OFF Writing H in the P15 turns the back light on 4 6 Luminance and contrast adjustment Luminance is adjusted with an inverter which has dimming function Contrast is adjusted by controlling the contrast ad justment voltage VO of the LM320153 Luminance Contrast 5 Customer display The customer display uses the same vacuum fluorescent tube FIP7B13 as the ER A8DP has The display is turned on and off by the CKDC7 6 Pseudo SRAM Here is an explanation for pseudo SRAM interfaces 6 1 CPU interface The figure below shows a typical pseudo SRAM interface in the ER 31Xsystem 741 00 VRAM RESET gt 74F32 e 174508 jo 74LVX32 TIT Fig 8 6 2 Pseudo SRAM address To use the decoding signal RASP for the pseudo SRAM RASPE or the RASP enabling bit for the must be first enabled When RASPE is enabled the pseudo SRAM is decoded by the RASP signal as follows 1 180000h 1FFFFFh 2 008000h 00FE7Fh same as 180000h 187E7Fh In 2 the Opage mapping function of the MPCA7 is used Approxi mately 30 KB from the beginning of the addresses in the pseudo SRAM can be also accessed from the Opage space 7 NOR type flash memory Here is the explanation for the interface of NOR type flash memory The device is Sharp s LH28F800SU flash memory which consists of 512 K words x 16 or 1 MB x 8 w
82. Peripheral Controller by the OPTCS signal for an optional decoder signal OPTCS They do not exist as external signals Fig 4 3 4 ROM space Fig 5 shows the ROM space The ER A750 uses 1MB of NOR type flash memory instead of conventional ROM so that the ROS1 and ROS2 from the MPCA7 are ORed and input into the chip enable of the flash memory C00000h The low order 32 KB of ROS1 is mapped over the Opage area ROS1 C80000h MAX512KB ROS1 and ROS2 are decoded by the MPCA7 ROS2 MAX512KB D00000h ROS3 is not supported by the MPCA7 Reserved for 1PL writing ROM on the ER A7RS DFFFFFh Fig 5 3 5 VRAM amp RAM space The VRAM is the display memory of the LCD Correspondence of the memory address and the display content is described Section 5 Display 100000h The VRAM which is mo unted on the ER A750 has 32 KB of memory 180000h The addresses form 180000h to 187E7FH approximately less than 32 KB are mapp ed over the Opage area 200000h The RASS3 signal from the MPCA7 corresponds to 2 MB of memory from 200000h to 3FFFFFh ER 03 04MB interfaces RAS3 as the base 400000h Signal NOTUSE BFFFFFh L All the decode signals in the figure are supported by the MPCA7 Fig 6 3 6 Extended I O area The addresses from F00000h to FFFFFFh are called an extended I O area The ER A750 uses the following addresses as the break ad dress register BAR for
83. R A750 cannot use the IRQ1 terminal instead of it The IRQ2 terminal is used for IR as the SCK1 terminal CHAPTER 8 PWB LAYOUT 1 Main PWB Side A t 311 HLIM ANO 30v 1 GR gt 3uIj4 ONV XODHS HII CNOIMI23B 40 SIN QO Ee HSNIVOV O3 NI1NO2 803 t Ty NOIINVI STNOO Ac 15 i ev s e us TG e T8 rau Hp Com Br en DET OW UT 8 E Gomer ux L T ae T P r E f xx j ga ee amp 48 3 oe sss SE u e CP S e3 Ce fus e E EE ir T 2 Main PWB Side B C189 C176 C171 178 C172 Crea 8 1 174 e C185 E BA BE c Cie3 1 181 Ci 25 c R189 R262 ROG C198 Rigs TES cze C ete Rud GI GA CI Gras ram 249 RH GA GI Eras RS AG NG C CIR cimi cos 5213 au RIE EI EEE C1 2 RBC RT DO CoCr CI RiZ2 C103 sri re DE Gores ETE asn E C CCS R277 5 au Co Ge ceca ioe Cis esc Ci C399 98133 C312 GI OG omis Ros C253 RAD vea AG Ber Ritz Ri asl ies cue LITE OD ECCE R281 R24 Riis C Yam Oo Gidea R282 78286 eus 44 ES ca Cc i cC Ce E SR My ooo eSris oan nan sc LI E C315 c CI CI R228 R261 R237 sm C mus RS R
84. R152 154 VRS TS2AD153G Resistor 1 10W 15KQ 2 R287 VRS TS2AD153J O O OJO DDD OD O OI O OJ O OC TD U U OO UJ 07 07 07 07 07 07 D 07 07 U 07 OoOO Resistor 1 10W 15KQ 4596 R104 292 302 107 ER A750 Main PWB unit PARTS CODE DESCRIPTION VRS TS2AD162J Resistor 1 10W 1 6KQ 5 R296 297 VRS TS2AD183J Resister 1 10W 18KQ 5 R301 VRS TS2AD222J Resister 1 10W 2 2KQ 5 R125 VRS TS2AD272J Resistor 1 10W 2 7KQ 5 R281 284 VRS TS2AD302J Resistor 1 10W 3 0KQ 5 R271 273 VRS TS2AD303F Resistor 1 10W 30KQ 1 R151 VRS TS2AD331J Resistor 1 10W 3300 5 R198 VRS TS2AD362F Resistor 1 10W 3 6KQ 1 R263 VRS TS2AD392G Resistor 1 10W 3 9KQ 2 R299 VRS TS2AD432J Resistor 1 10W 4 3KQ 5 R185 303 VRS TS2AD470J Resistor 1 10W 470 5 R149 150 169 170 VRS TS2AD472J Resistor 1 10W 4 7KQ 5 R173 300 VRS TS2AD473J Resistor 1 10W 47KQ 5 R103 120 124 VRS TS2AD512F Resistor 1 10W 5 1KQ 1 R153 VRS TS2AD513J Resistor 1 10W 51KQ 5 R178 VRS TS2AD561J Resistor 1 10W 5600 5 R290 VRS TS2AD562J Resistor 1 10W 5 6 5 R242 VRS TS2AD563J Res
85. RCVDT1 RCVDT2 RCVDT2 RS 232 reception data signal GND GND TRNCLK1 GND TRNCLK2 GND Data transmission clock W WRH Write signal CS1 CS1 CS2 CS2 RS 232 chip select RSLCTO AHO RSLCT 1 AH1 Address bus R RDH Read signal RCVRDY 1 RCVRDY 1 RCVRDY2 RCVRDY2 RS 232 data reception enable signal TRNRDY1 TRNRDY1 TRNRDY2 TRNRDY2 RS 232 data transmission enable signal BRK1 BRK1 BRK2 BRK2 Break code detection signal CTS1 CTS1 GND CTS2 CTS2 GND RS 232 clear to send signal TRNEMP1 TRNEMP1 TRNEMP2 Oo o olololooo TRNEMP2 RS 232 transmission buffer empty signal NC NC NC NC NC NC NC NC OPEN NC OPEN NC TRNDT1 TRNDT2 RS 232 transmission data signal DSR1 DSR2 RS 232 data set ready signal RTS1 NC RTS2 NC Request to send signal DTR1 DTR1 DTR2 DTR2 RS 232 data terminal ready signal RCVCLK1 GND RCVCLK2 GND Data reception clock CLOCK CLKUSART Clock signal RST O O O O OoOO RESUSART RESET signal VCC 5V 5V 2 5 Z80 CPU 1 Features The extensive instruction set contains 158 instructions including the 8080A instruction set
86. SHARP SERVICE MANUAL CODE 00ZE RA750U SME MODEL ER A750 For amp A version CONTENTS CHAPTER 1 SPECIFICATIONS 1 1 CHAPTER 2 OPTIONS 2 1 CHAPTER 3 SERVICE PRECAUTION 3 1 CHAPTER 4 SRV RESET Program Loop Reset and switch to SRV mode 4 1 CHAPTER 5 MASTER RESET 5 1 CHAPTER 6 DIAGNOSTICS 6 1 CHAPTER 7 CIRCUIT DESCRIPTION 0 006 0 cece m 7 1 CHAPTER 8 PWBLAYOUT u uuu uum a ees hm rh 8 1 CHAPTER 9 CIRCUIT DIAGRAMS 9 1 PARTS GUIDE Parts marked with is important for maintaining the safety of the set Be sure to replace these parts with specified ones for maintaining the safety and performance of the set a 7202 20200m0mmm s 3 This document has been published to be SHARP CORPORATION used for after sales service only The con tents are subject to change without notice TheRBRC Seal TheRBRC Seal on the easily removable nickel cadmium battery pack contained in our product indicates that SHARP is voluntarily participating in an industry program to collect and recycle these battery packs at the end of their useful life when taken out of service within the United States The RBRC program provid
87. T2 RCVDT2 45V RCVDT3 GND RS 232 INLINERCVDT signal RSRQ RSRQ RS 232 IRQ signal TRV GND INLINEYES NO RXDATAO NC INLINERXDATAOUT TXE SRESET INLINETRNSENABLE TRRQ TRQ2 INLINE IRQ signal Pin name ER A750 Description TRQ1 TRQ1 TIMER IRQ signal RS 232 TRQ2 NC TIMER IRQ signal INLINE DO DO DATABUS MAIN D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 DATABUS USART AO ADDRESSBUS MAIN A1 A2 A3 A4 A5 OPTCS OPTION CHIP SELECT from MPCA7 RDO READ signal from MPCA7 WRO WRITE signal from MPCA7 RES RESET signal from MAIN RDH READ signal To USART WRH WRITE signal To USART RESUSART RESET signal To USART NC cillation circuit CLKUSART Clock for USART NC T R clock for 1CH USART AHO Address bus for USART AH1 o00000 olol o o GND UNIT3 USART 1CH 2CH select NC Power source clock 45V 45V GND GND GND GND RTS1 RS 232 control signal RTS output ICU IS ISC IOU CMOS level input internal pullup resistor Output TTL level input internal schmit circuit CMOS level
88. alid invalid Even parity odd parity Operations in the advancement synchronization mode Detection of framing error overrun error parity error Transmission reception buffer state acknowledgment Break characters detection Error start bit detection IBM Bi sync system operation allowed Duplex buffer system in the transmission and the reception sec tions Loop back diagnostic functions 9 signal level TTL compatible Compatible with standard microprocessor in connecting pins and signal timing 9 Standard 42 pin plastic DIP 48 pin plastic QFP 5V single power source 2 Pin configuration TRNDT1 TRNEMP1 ST1 1 CTS1 SYNC BRK1 RCVDT 2 C4 3 Block diagram DB0 DB7 TRNDT1 CS1 CS2 RTS1 RSLCTO RSLCT1 Address DTR1 WR decoder RCVDT1 TRNRDY1 CTS1 RCVRDY1 DSR1 SYNC BRK1 Mode settin TRNEMP1 register 1 4 Baud rate ANGI setting control mE register 1 1 Baud rate generator TRNDT2 RST RTS2 DTR2 RCVDT2 TRNRDY2 CTS2 RCVRDY2 DSR2 SYNC BRK2 TRNEMP2 Mode setting register 2 4 CLOCK Baud rate pr eontro REVEIRE register 2 5 VCC GND 4 Pin description z o Pin name ER A750 DB4 DB4 DB5 DB5 DB6 DB6 DB7 DB7 DBO DBO DB1 DB1 DB2 DB2 DB3 DB3 RCVDT1
89. aps Lock is off during text programming Double size character mode indicator W Apperars when the double size character mode is selected during text programming Device type LCD display Dot format 320 W x 240 H Full dot Dot size 0 33x 0 33 mm Dot space 0 03 mm Dot color White Back color Dark blue Weight 180g 2 Customerdisplay WLC MDI 1JO ST CG TL VOID RFND ST Lights up when a subtotal is displayed CG Lights up when the change due amount appears in the dis play or when the total sale amount is negative TL Lights up when you finalize a transaction by pressing the CA2 7 throuth 777 or 7 through CH without any amount tendered entry VOID Lights up when the VOID key or yo key is pressed or when an item void entry is made RFND Lights up when the RFND key is pressed or when a refund item entry is made Device type 7 segment display tube Number of lines 1 line Number of positions 7 positions numeric display Color of display Green Character size 13 H x 6 W mm 3 Displayadjustment You can adjust the brightness and contrast of the display by using the corresponding controls ama Brightness control Turning the control backwards Contrast control darkens the display and turning it Turning the control backwards forwards brighten
90. as a subset NMOS version for low cost high performance solutions CMOS version for high performance low power designs e 20840006 6 17 MHz CMOS Z84C0006 DC to 6 17 MHz Z84C008 DC to 8 MHz Z84C0010 DC to 10 MHz Z84C0020 DC 20 MHz 6 MHz version can be operated at 6 144 MHz clock The Z80 microprocessors and associated family of peripherals can be linked by a vectored interrupt system This system can be daisy chained to allow implementation of a priority interrupt scheme Duplicate set of both general purpose and flag registers Two sixteen bit index registers Three modes of maskable interrupts Mode 0 8080A similar Mode 1 Non Z80 environment location 38H Mode 2 Z80 family peripherals vectored interrupts On chip dynamic memory refresh counter SYSTEM CONTROL ADDRESS BUS 8400 CONTROL 280 CPU me BUSREQ CONTROL BUSACK DATA BUS 45V GND Figure 1 Pin functions 2 Pin configuration LO TNN e lt O o r lt lt lt lt lt Z lt lt lt lt lt 44 34 1 33 CLK rr NC D4 IN A5 D3 M D5 A3 D6 A2
91. ases the error status is dis played with the error occurrence bit as 1 The normal bit shows 0 The error status from the host to the controller is as shown in the table below Not used 0 is always displayed Power interruption notice Not used 0 is always displayed Not used 0 is always displayed Not used 0 is always displayed Not used 0 is always displayed Power ON continuation Power ON initializing The error status from the controller to the host is as shown in the table below Not used 0 is always displayed Power interruption notice Not used 0 is always displayed CH2 reception data exits CH1 reception data exits Power interruption process complete Not used 0 is always displayed Not used 0 is always displayed 2 Display SRN Self Check DATA RETRY ONT xxx The number of resending is displayed in xxx with a decimal number ACK RETRY Inthe sequence of b7 b6 bO from he left 1 is displayed in case of an XXXX error and 0 when normal n the sequence of b7 b6 bO from he left 1 is displayed in case of an error and 0 when normal n the sequence of b7 b6 bO from he left 1 is displayed in case of an error and 0 when normal n the sequence of b7 b6 bO DIAG 5 XXXXXX the left 1 is displayed in case o error and 0 whe
92. atch pulse signal WF WF Frame signal Liquid crystal alternating current signal YD YD Scanning line start signal Screen display data Screen display data Screen display data Screen display data NC NC NC NC System clock System clock 2 10 CKDC7 HD404728A91FS 1 General description The CKDCT7 is a 4 bit microcomputer developed for the ER A750 and provides functions to control the real time clock keys and displays The basic functions of the CKDC7 are shown below Keys The CKDC7 is capable of controlling a maximum of 256 momentary keys Sharp 2 key rollover control Simultaneous scanning of key and switch When a key is scanned the state of a mode and clerk switch is also buffered The host can scan the state of Switch together with the key entry data at the same time the key is scanned Switches switch with 14 positions maximum 8 bit clerk cashier switch 2 bit feed switch 1 bit receipt on off switch 1 bit option switch 4 bit general purpose switch 1 bit is used for keyboard select Displays 16 column dot display 12 column 7 segment display column digit selectable All column blink controlled for the dot and 7 segment display decimal point and indicators Programmable patterns for 7 segment display Four patterns Internal driver for 7 segment display Buzzer Single tone control Clock Year month day of month day of
93. aud rate is set to 38400BPS Timer check RS232 on board timer Before performing the check set the timer to TCVDT start and 5ms Then perform the following procedure During execution of the check TRQ must not be generated After 5ms from completion of the check TRQ must be generated 2 Display RS232 CH1 Check ER DR ERROR All the contents of an error must be displayed ERROR display ERROR content ER DR ERROR ER Cl ERROR RS CD ERROR RS CS ERROR CI INT ERROR CD INT ERROR CS INT ERROR TXEMP ERROR TXEMP INT ERROR TXRDY ERROR TXRDY INT ERROR RCVRDY ERROR ER DR LOOP ERROR ER CI LOOP ERROR RS CD LOOP ERROR RS CS LOOP ERROR Cl interruption is not made CD interruption is not made CS interruption is not made TXEMP is not set TXEMP interruption is not made TXRDY interruption is not made TXRDY interruption is not made RCVRDY is not set Reception enabled TR Q is generated during check RCVRDY interruption is not made SD RD LOOP ERROR DATA ERROR SD RD LOOP ERROR DATA ERROR FRAMING ERROR etc TIMER ERROR is not set after completion of check TRQ 1 interruption is not made RCVRDY INT ERROR SD RD ERROR SD RD ERROR TIMER ERROR TIMER INT ERROR 3 Terminating procedure Press the CANCEL key to terminate the check 3 CH2 Check 1 Check content The check procedure the display and t
94. cept for during transmission No data received Received data present Received data remained Remote station not ready in sending NTDY is sent back because the remote station is not ready for reception Reception buffer full in sending The controller reception buffer of the remote machine is full Resend error in sending Retry over 5 times when no response Collision error in sending When an collision occurred in data transmission retry over 16 times at re collision after a random time 0 255ms Line busy time out Transmission cannot be made by multi station communication to cause time out in data send wait time Reception size over in receiving The reception buffer size is insufficient Hardware error Interface abnormality No SRN interface or abnormality in SRN controller 3 Terminating procedure Press the CANCEL key to terminate the check After terminating perform the service reset 3 9 IrDA amp ASK Diagnostics This is used to check the IR communication To execute this check the following composition is required ER A750 ER A750 as checker The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed When the CANCEL key is pressed the display returns to the diagnostics menu IR
95. ck is performed in the following pro cedure The memory contents must not be changed by this check e 55AAH is written into 3FFFFEH 3FFFFEH is read and compared with 55AAH If the both data are correct the following procedure is performed If not go to 22222 55AAH is written into 2FFFFEH 2FFFFEH is read and compared with 55AAH If the both data are correct Extend RAM is ER 03MB is displayed and the check is terminated If not Extended RAM size OKB is dis played and the check is terminated For the ER 04MB the following check is performed The following processes are performed for the check address 200000H 3FFFFFH PASS1 Memory data save PASS2 Data 0000H write PASS3 Data 0000H read compare data 5555H write PASS4 Data 5555H read compare data AAAAH write PASS5 Data AAAAH read compare PASS6 Memory data writed the saved data In case of a compare error in the check sequences of PASS1 PASS6 an error display is made If there is no error at all the check is normally terminated In addition the following address check is performed in the above check sequence In case of an error an error display is made and read write of the address where the error occurred is repeated without performing the check Check point address 200000H 200001H 200002H 200004H 200008H 200010H 200020H 200040H 200080H 200100H 200200H 200400H 200800H 201000H 202000H 204000H 208000H 2100
96. cted and executed by the key which has bee depressed when the CKDC reset is released to start the system In the case of MRS security is added by a key operation equivalent to a pass word Procedure 1 POWEROFF 2 Slide CKDC reset switch to reset position slide switch 3 POWERON 4 Slide CKDC reset switch to normal position At this time if no key is pressed go to step 5 ifa specified key is pressed go to step 6 Perform program reset SRV reset The machine waits for secret key input Enter 4 kinds of secret keys before master resetting secret key positions are fixed Which type of master reset should be performed at this time MRS1 or MRS2 is determined by the key which was pressed in step 4 If the secret key input is wrong reset the program The secret key input is like a pass word to prevent the user from master resetting inadvertently Flow chart CKDC start condition read Hard reset No start Yes Slide Switch SRV reset operation Yes Secret key judgement Yes lt gt Yes Secret key judgement reset Yes 10 key position input sequence Fig 16 16 Drawer The ER A750 can use up to 2 optional external drawers 16 1 Drawer solenoid drive P34 P37 inside the CPU are allocated for the port output of the drawer solenoid drive Table 22 Built in port Remarks P34 Drawer 1 optional drawer Signal name
97. ders and buffers may be required Do CLK TRGO 01 ZC TOO D2 CPU D3 CLK TRG1 BUS D4 ZC TO1 D5 CHANNEL D6 CLK TRG2 SIGNALS L D7 ZC TO2 CE CTC cso CLK TRG3 CONTROL cst FROM Wi RESET GRU ORG Z80 CTC DAISY CHAIN INTERRUPT CONTROL CLK 5V GND Figure 1 Pin Functions Programming the CTC is straightforward each channel is pro grammed with two bytes a third is necessary when interrupts are enabled Once started the CTC counts down automatically reloads its time constant and resumes counting Software timing loops are completely eliminated Interrupt processing is simplified because only one vector need be specified the CTC internally generates a unique vector for each channel The Z80 CTC requires a single 5 V power supply and the stan dard Z80 single phase system clock It is packaged in 28 pin DIPs a 44 pin plastic chip carrier and a 44 pin Quad Flat Pack Figures 2a 2b and 2c Note that the QFP package is only available for CMOS versions 3 Pin configuration cso RESET CE NC CLK NC M1 NG IEI NC INT NC IEO CSI TORQ CLK TRG3 NC CLK TRG2 ZC TO2 a CMOS 5 Z80 CTC CLK TRG1 ZC TOO CLK TRGO NC NC RD 45V GND NC D7
98. ds tracks 1 and 2 of the magnetic card of ISO 7811 1 5 and displays the data in ASCII code 2 Display MCR Check Magnetic Card Reader TRACK1 TRACK2 XXXXX shows the data read by the Incase of an error the error code is displayed as shown below Magnetic Card Reader Check TRACK1 BUFFER EMPTY TRACK1 MCR ERROR TRACK2 BUFFER EMPTY TRACK2 MCR ERROR Displayed when TRACK1 empty code is sent back Displayed when TRACK1 error code is sent back Displayed when TRACK2 empty code is sent back Displayed when TRACK2 error code is sent back 3 Terminating procedure Press the CANCEL key to terminate the check 6 11 3 11 Drawer Diagnostics This diagnostics is used to check the drawer open and sensors The following menu is displayed The cursor position is highlighted Use T key and J key to move the cursor Move the cursor to the process you desire and press the enter key The selected individual diagnostics program is executed When the CANCEL key is pressed the display returns to the diagnostics menu Drawer Drawer1 Check Drawer 2 Check Diagnostics 1 Drawer 1 Check 1 Check content The solenoid of drawer 1 is turned on and the drawer open
99. e addresses from C00000h to CO7FFFh the low order 32 KB of the ROS1 are mappd over the ROM 000000h mapped are ROM mapping area 080000h RAM mapping area OOFE80h Internal I O area OOFF80h I O area External I O area OOFFFFh If the MPCA7 s address line MA15 is used with the MPCAT s internal register RASPE 1 the addresses from 180000h to 187E7Fh about less than 32 KB of the RASP space are mapped over the Opage area Fig 3 3 3 areas The addresses from OOFE80h to 00FF7Fh are called the internal I O area while those from OOFF80h to OOFFFFh the external I O area The internal I O area is a space where the control registers and built in ports inside the CPU are addressed The external I O area is a space where the peripheral devices outside the CPU or devices on an optional card are addressed OOFE80h Internal I O area The MPCCS signal is the base signal for de coding the MPCA7 s internal register and does not exit as the external signal OOFF80h OOFFAOh LCDCZ is the chip select signal for the LCDCZ LCD controller and OOFFBOh MCR1Z and MCR2Z OOFFB4h MCR1Z are those for the ER 00FFB8h MCR2Z A7RS MCR I F OOFFB9h Reserved OOFFBAh Reserved OOFFBBh Not used OOFFCOh OPCCS1 OOFFDOh OPCCS2 OOFFEOh Reserved OPTCSZ Not used OOFFFOh Reserved OOFFFFh v OPCCS1 and OPCCS2 signals are decoded inside the OPC Option
100. e main PWB of the ER A750 Fig 2 Before installing an optional RAM PWB check its version by referring to the description given in the above mentioned 1 and 2 and set the jumper as shown below The ER A750 has been factory set for 150ns access time and TP cycle inserted MAIN PWB o IN case of 1 IN case of 2 J IC16 Short position Fig 3 Setting of the JP1 on the main PWB of the ER A750 1 Setting when the ER 03MB or the ER 04MB is not marked with Position to which the ER A750 has been factory set EI Not N I E 2 2 Setting when the ER 03MB or the ER 04MB is marked with O TO Q 1 3 3 Difference in operation according to the setting of the jumper Only when the ER 03MB or the ER 04MB is used in the above setting state 1 will one cycle i e cycle for generating pre charge time of the quasi SRAM TP cycle of access be additionally inserted into the CPU thereby delaying the CPU speed slightly 4 Factory setting of the ER A750 The ER A750 has been factory set so that the JP1 is in the setting state 1 TP cycle inserted However if it has neither the ER 03MB or the ER 04MB installed to it this is automatically detected by soft ware so the additional insertion of the TP cycle is not performed Note When installing the ER 03MB or the ER 04MB check the position of the jumper by referring to Fig 3 Improper setting of the jumpe
101. e primary functions of the processors Subsequent text provides more detail on the I O controller family registers instruction set interrupts and daisy chaining and CPU timing aN 8 BIT DATA BUS DATA BUS INTERFACE PS INSTRUCTION H INSTRUCTION DECODER REGISTER INTERNAL DATABUS ALU 45V GND CLOCK gt SES TIMING CONTROL IL Er ADDRESS 8 SYSTEMS 5 CPU pss m ANDCPU CONTROL CONTROL INPUTS mu OUTPUTS ADDRESS BUS Figure 3 Z80C CPU Block Diagram 4 Pin description In Out Function In Clock In Out Data bus In Out Data bus In Out Data bus In Out Data bus 45V In Out Data bus In Out Data bus In Out Data bus In Out Data bus NC Interrupt request signal Non maskable interrupt signal 45V Memory request signal Input Output request signal NC Rread signal Write signal Bus acknowledge signal Wait signal Bus request signal Reset signal Machine cycle one signal NC GND Address bus Address bus Address bus Address bus Address bus Address bus NC Address bus Address bus Address bus Address bus Address bus NC Address bus Address bus Address bus Address bus Address bus 2 6 Z80 CTC 1 Features Four independently programmable
102. ellite Data Transmission Check Master Input Master Terminal Number Input Satellite Terminal Number XXX XXX XXX Data Sequence Number With the above setting data transmission between the master machine and the satellite machine is started 2 Check content Data in the following format composed of 2byte sequence No and 254byte AAH data are transmitted from the master machine to the satellite machine The master machine displays the sequence No 1 2 3 254 255 256 Byte XXXX Sequence No 2byte 4digits of binary decimal numbers AA Transmission data AAH x 254 bytes The satellite machine sends back the received data to the master machine The satellite machine displays the received sequence No The master machine receives the data and checks the se quence No and 256byte AAH data In case of an error the master machine displays an error code and terminates the check If two or more satellite machines are used the above operation is repeated If data transmission with all the satellite machines are normally completed the master machine incre ments the sequence No The above operation is repeated 3 Error display Data Transmission Check Master Input Master Terminal Number Satellite Terminal Number XXX XXX XXX Input The error code is displayed Data Sequence Number XXXX IRC Error XX The error codes are as shown below Command abnormality ex
103. ently initialized by block DMARQ2 SDRQ2 DMA request signal High speed data transfer DMARQ1 SDRQ1 DMA request signal 3 2 MB sec clock seed of 10 MHz normal transfer mode DMARQO SDRQO DMA request signal 5 0 MB sec clock speed of 10 MHz compression transfer mode GND GND GND The number of DMA channels can directly be expanded NC NC NC Expansion mode A15 D7 SD7 In Qut Data bus END input when data transfer is finished A14 D6 S D6 In Out Data bus Software DMA request available A13 D5 S D5 In Out Data bus CMOS DMAAK1 SDACK1 Out DMA acknowlidge signal Low power consumption DMAAKO SDACKO Out DMA acknowlidge signal 2 Pin configuration A12 D4 504 In Out Data bus le A11 D3 SD3 In Out Data bus E 6 8 A10 D2 SD2 In Out Data TITTET Pale bus OG q q 5 A9 D1 SD1 In Out Data bus A8 DO S DO In Out Data bus NC NC READY 1 VCC 45V HLDAK SAO Address bus er SA1 Address bus AEN 4 HLDRQ c 5 SA2 Address bus NC C 6 yPD71037GB 3B4 SA3 Address bus cs 7 NC NC ps TC End Terminal cut signal RESET c 9 DMAAK2 c 10 Address bus DMAAK3 C 11 Address bus Address bus Address bus In Out read signal O Q x Oo g g 2 5 5 In Out 11 write signal lt lt lt Z 2 Memory read signal
104. er reset is started DISPLAY MASTER RESET 8 After completion of the master reset the buzzer sounds three times and the following SRV mode display is shown DISPLAY 12 15AM SRU SRU MODE L1 READING 0 2 SETTING 3 IRC SETTING 4 DOWN LOAD 5 DIAGNOSTIC MODE FOR EXIT CHAPTER 6 DIAGNOSTICS SPECIFICATIONS CONTENTS 2 System configuration 1 3 DIagnostics RR 1 1 Master reset 1 2 Program reset service reset procedure wl 3 1 Execution of diagnostics eee 1 3 2 RAM Diagnostics eene tene 2 1 Standard RAM Check 2 2 VBAM Gh6Ck ecce cte erts 2 3 ER 03MB Check a 3 4 ER 04MB CGIHiecK oorr tet dede 3 3 3 ROM amp SSP Diagnostics a 4 1 Standard ROM 4 2 SERVICE 4 3 SSP Check cote tgp tH 4 3 4 Timer Keyboard Clerk Switch Diagnostics 5 1 Timer Check iE nter pe niue 2 Keyboard Check 3 Clerk SW Check 3 5 RS232 I F Diagnostics ranernrrrnvrnvrrnenvrrrvenrvnrvennrervernrernernen 5 1 CHANNEL iid eet ele
105. es a convenient alternative to placing spent nickel cadmium battery packs into the trash or municipal waste stream which is illegal in some areas SHARP spaymentsto RBRC makes it easy for you to drop off the spent battery pack at local retailers of replacement nickel cadmium batteries or at authorized SHARP product service centers You may also contact your local recycling center for information on where to return the spent battery pack SHARP s involvement in this program is part of its commitment to protecting our environment and conserving natural resources RBRC is a trademark of the Rechargeable Battery Recycling Corporation CHAPTER 1 SPECIFICATION 1 Apearance Externalview Front view AC cord Power switch in sure that the power Switch is placed in the OFF position prior to Left side of connecting AC power the machine i Brightness Contrast contro control IR receiver cover Rear view Rear cover Customer Display Power switch 2 Rating External dimensions 11 4x 14 4 10 3 in 290 x 365 x 262 mm Weight 11 2 Ibs 5 1 kg Power source 120V AC 10 60 Hz Power consumption Stand by 22W Operating 25W max Working temperatures 32 to 104 F 0 to 40 C 3 Keyboard 1 Standard keyboard layout 91 92 93 u o is fe fe 15 BAG LEVEL LEVELI LEVEL LEVEL LEVEL misc 96 s 2 3 4 5
106. ess HOST CPU acce and RD WR address SUB CPU HOST CPU SUB CPU amp DMAC control write amp HOST CPU read control unit DMA amp CPU access Fig 4 2 Peripheral circuit The peripheral circuit consists of an I O address generation unit on the SUB CPU block dividing circuit and the wait signal control unit SUB CPU address amp RD WR SUD CPU Address VO address decoding unit CPU amp DMAC wait signal control unit Clock dividing circuit Fig 5 I O address generation circuit A total of 11 addresses are generated by AO A1 A4 A5 and RD and WR signals CPU and DMAC wait signal control unit Clocks into the CPU Z 80 SUB CPU and its peripheral LSI DMAC and CTC are operated respectively on 4 MHz While the ADLC MC68B54 Advanced Data Link Control is operated by the E Enable clock of 2 MHz according to restric tions in terms of the hardware of the LSI It is necessary to synchronize the timing of the write and read in the ADLC To control synchronization timing and input the wait signal goes into the CPU for CPU access and into the DMAC for DMA access This block is a circuit to generate such wait signal Wait signal CLK 16 MHz System clock 4 MHz Clock dividing circuit This block divides the blocks according to the CLK supplied from outside to generate the clock for CPU DMAC and CTC and the E and transmission clock rate 480 KBPS or 1 MBPS selectable for the
107. ft keys DEPOSIT Deposit key DEPOSITRF Deposit refund key TAX Manual tax key GRTEX Gratuity exempt key COVERCNT Cover count entry key BILL Bill print key CONV Currency conversion menu key SHIFT1 SHIFTS Price level shift 1 5 keys BACKSPACE Backspace key DELETE Delete key NC New check key GLU Guest look up key Non add code entry key NS No sale key MGR Manager code entry key OPENTARE Tare entry Key REPEAT Repeat entry key PERSON Person number entry key IND PAYMENT Individual payment key EMPL SALES Employee sales key RCP SW Receipt ON OFF key KEYTOP DESCRIPTION SCALE Scale entry key 3 Text programming key sheet layout ya me BO Onc Su a Ba EE SPACE SHIFT 5 SPACE SPACE E CD pug CJ CL L Er ERENG NEN J fnis EFE eo 1 2 3 4 Blank key sheet layout BEN HH HH SH B an L J EE Jil 2 LL LJ 3 Display 1 Operatordisplay Screen example 1 REG mode Ts 10 06AM REG Mode name 1 PL000001 1 PLO00002 25 MDSE ST 9 25
108. ftware interrupt 5 OR input BIT4 1 Sl4 SH Software interrupt BITO EXINTO S10 Table 10 IRQO component bits 25 Address BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO OOFF81h EXINTQ 1 SHENF SHEN1 Edge interrupt BIT7 Not used BIT6 EXINTO Optional external interrupt signal BIT5 3 KRQ1 SHEN1 Event request signal for CKDC interface channel 1 9 2 2 IRQ1 layout The IRQ1 is an external interrupt terminal for an external optional RS232 and input into the CPU through an optional slot bus 9 2 3 IRQ2 layout The IRQ2 terminal is used as the shift lock terminal SCK1 for IR interface 10 WAIT control The weight control function built in the MPCA7 is used to provide an interface with low speed devices 10 1 Block diagram The block diagram of the weight control function is shown in Figure 10 tO ADDRESS lt 00FF8Fh gt WAIT PULSE GENERATOR In the figure the decoder wait enabling register AND OR sections are the same as those in the MPCA5 or 6 but other components are newly incorporated in the MPCA7 EXWAITZ and LCDWT are external weight signals which are to be ORed inside the CPU and output to the WAITZ The EXWAITZ is a general purpose wait request terminal and LCDWT is the wait re quest signal from the LCD controller 11 CKDC7 The ER A750 performs the following controls using CKDC7 Keyboard Customer display
109. g signal at main PWB side NORDY Flash memory RY BY signal FVPON Flash memory write protect signal output BKLT Backlight control signal Nu GND MVDT Memory version detect DO Data bus D1 Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6 Data bus D7 Data bus NU GND AO Address bus A1 Address bus A2 Address bus Address bus A4 Address bus A5 Address bus A6 Address bus A7 Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus GND Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus GND Wait signal Bus control request acknowledge Bus control request Drawer open signal Option drawer open signal Remote drawer No 1 open signal NU NU Symbol Function VCC 5V P40 5V P41 NU GND P42 NU GND P43 NU GND FTi1 P44 INTMCR MCR interrupt signal P45 NU GND FTi2 P46 SHEN CKDC Interface shift enable signal P47 NU GND VSS VSS GND P50 NU GND P51 NU GND P52 NU GND P53 NU
110. h the MPU by the READY WAIT signal Access from MPU to VRAM is performed through the cycle steal method No effect on the screen VRAM Mapping MPU memory space Capacity 64 Kbytes 218 LCD display mode Binary display mode ON OFF Graduation display mode ON OFF and pseudo intermediate dou ble tone LCD panel Single screen drive panel Transfer by 4 bits or 8 bits Double screen drive panel 4 bits x 2 Maximum number of characters in horizonal direction 256 characters 2048 dots binary display mode 1024 dots graduation display mode Maximum number of vertical lines 1024 lines single screen drive 2048 lines double screen drive Divided screen OR function Either function is available when sin gle screen drive is set Divided screen The screen can be divided into two upper and lower sections OR function Two different data can ORed Virtual display can be set Smooth scroll in vertical direction Built in chip select output for VRAM CMOS operation 2 Block diagram RESET READY MPUSEL MPUCLK IOCS IOWR IORD VO MEMCS MEMWR MEMRD CONTROL CIRCUIT CONTROL REGISTER AB0 AB15 BHE ADDRESS BUFFER R1 LCDENB XSCL LP YD WF DISPLAY TIMING CONTROL CIRCUIT DB0 DB15 D DATA BUFFER OSCILLATION CIRCUIT OSC1 OSC2 VAO VA15 VCS0 VCS4 3 Pin configuration SED1351F0A REFRESH BASIC TIM
111. he terminating procedure are the same as CH1 Check 4 CH3 Check 1 Check content The check procedure the display and the terminating procedure are the same as CH1 Check 5 CH4 Check 1 Check content The check procedure the display and the terminating procedure are the same as CH1 Check 6 CH5 Check 1 Check content The check procedure the display and the terminating procedure are the same as CH1 Check 7 CH6 Check 1 Check content The check procedure the display and the terminating procedure are the same as CH1 Check 8 CH7 Check 1 Check content The check procedure the display and the terminating procedure are the same as CH1 Check 3 6 Liquid Crystal Display Diagnostics The ER A750 LCD display is checked The test program displays the patterns in the following sequence Every time when the ENTER key is pressed the next pattern is displayed When the ENTER key is pressed at the final pattern or when the CANCEL key is pressed at the midst of the check the display returns to the menu screen 1 Liquid Crystal Display Check 1 Check content The test patterns are displayed in the following sequence When the ENTER key is pressed the next pattern is displayed Black and white pattern at 1 dot pitch Vertical stripe pattern at 1 dot pitch Reversed pattern of the above Horizontal stripe pattern at 1 dot pitch
112. iss az cs F2ss e es C mA D JR13S sR181 eC Cc e gt ci5e Ries cu CO mm at R247 FB127 ieu MES ca ci C118 el eus oa Eu 8157 mz2 m9 gas as E C rc Eje3 R173 cies 556 C I C316 C255 2 C1H8 a gt CIO 227 D D L J8272 c Ec ciee Coas 228 Cai 34 p Gos mE ecis 68 JON R230 E NE ce 182 as Coc pc ra 283 Co CM 58 DO In 2 Goes a7 Rm Ra OO Sas oso e ar Se SG wam 122 EE 22 225 G cat ret ce ue OI ae Ve rs Sop ICR Fusdts coc RIS Cone Ed UC ruse Cc um Sos as Gris cisi DO CIR 91 C206 2 L masi cce RACE 85 cus 2181 0182 RIST ae 1 2 c1s3 129 FBi25 ro RIS COCO 1 1912 FHi21 FBi25 cant BL cies mI res cx 2121 2E ET rei Koes t3 3 C si Bie gt ca re I raus 22 eld Er LJ EJ R2 R3 0112 238 L Mo SG oa EI TE Ro C262 R2SS nF 0088 38 3 Mother PWB Side A 4 CKDC PWB f m oT 5542528555 me FB S ANA uL RE EE EN ex 00 00000000 v 6 oc P2222222 FB8 Y FB9 f 9 en 125V 150 00 i 701 Cs R35 E R34 1702 CONS R40 5 at ET 2 LJ
113. istor 1 10W 56KQ 5 R282 VRS TS2AD622J Resistor 1 10W 6 2KQ 5 R180 VRS TS2AD682F Resistor 1 10W 6 8KQ 1 R285 VRS TS2AD752F Resistor 1 10W 7 5KQ 1 R286 VRS TS2AD8R2J Resistor 1 10W 8 20 5 R105 VRS TS2HDA470J Resistor 1 2W 47Q 5 R262 QFSHD2109AFZZ Fuse holder F1 2 RCILZ1003BHZZ Dip coil BFW7550R2 F81 2 3 RCORF6685BHZZ Bead core BF2070R FB5 RCORF6691BHZZ Core BFS3550R2F FB4 RCORF6702BHZZ EMI filter 100pF FL1 2 3 VCEAGU1CW225M Capacitor 16WV 2 2uF C30 VCEAGA1HW104M Capacitor 50WV 0 1uF C31 VCEAGA1HW105M Capacitor 50WV 1uF C22 VCEAGA1HW107M Capacitor 50WV 100 C6 7 20 VCEAGA1HW224M Capacitor 50WV 0 22uF C29 VCEAGA1HW335M Capacitor 50WV 3 3uF C3 4 VCQYNA2AM103K Capacitor 100WV 0 010 C24 VCQYNU1HM153K Capacitor SOWV 0 015 C13 VS2SA1270 1 Transistor KTA1270 Q6 RCRSP5019BCZZ Crystal 7 37MHz X2 PRDAF6667BHZZ Heat sink IC40 QCNCM1060AC03 Connector Short Pin 3P JP1 5 6 QCNCM5278NCZZ CON4 5 QOCNCM7125BHOI Connector MLX 5046 03A Connector 9P MLX 87023 6066 CON6 7 QCNCM7128BH1E Connector MLX 53047 1510 CON2 QCNCM7129BHOD Inverter connector 4pin QCNCM713
114. ith 16 blocks of 64 KB In addition the LH28F800SU is the second generation device which has a number of functional blocks including page buffer command queue and block status register Taking advantage of these func tions will improve the performance especially in writing data 7 1 CPU interface The figure below shows a typical interface for the LH28F800SU of the ER A750 system H8 510 7 2 Device control After resetting the device automatically enters the array read mode and perform the same action as the usual ROM thus requiring no special consideration when reading data Data can be written at high speed by using the page buffer 8 SSP control The ER A750 uses flash memory in the place of EPROM so it is possible to rewrite the contents of the flash memory in changing the program However since the existing gate array MPCA7 is used it is also possible to use the conventional SSP 8 1 Operation Like the MPCA6 the MPCA7 adopts the break address register com parison method for detecting addresses The operation of this method is briefly explained below The gate array always compares the break address register ABR built in the gate array with the address bus to monitor the address bus If both agree the gate array outputs the NMI signal to the CPU which in turn shifts from normal handling to exception handling In both the MPCA6 and the MPCA7 SSP is achieved by the above operation The
115. n generates clock pulse signals which are used in transmission and reception and delivered through the baud rate selecting section to the SDTR section It provides the loop back diagnostic function which crosses interface lines of the Modem and loops transmission and reception signals facilitating the operation check Features Two independent channels of SDTR Built in baud rate generator which allows setting for each channel External clock available Internal clock output available Maskable interruption generating circuit Two channels are assigned to different address spaces Baud rate DC 240K baud with external clocks Full duplex communication Program assignment in synchronization mode Data bit length 5 8 bits Character synchronization system Internal synchronization external synchronization Number of synchronized characters Single character double characters Parity occurrence and check parity valid invalid even parity odd parity Operations in the synchronization mode Overrun error and parity error detection Transmit receive buffer state acknowledgment Synchronization character detection Automatic insertion of synchronization character Program assignment function in the advancement synchroniza tion mode Data bit length 5 8 bits Stop bit length 1 112 2 bits Baud rate Transmission clock reception clock x 1 x 1 16 x 1 64 Parity occurrence and check Parity v
116. n normal DIAG 5 HeC 3 Terminating procedure Press the CANCEL key to terminate the check After terminating perform the service reset 2 SRN Flag Send Check 1 Check content Execute diagnostics 3 command to send Flag 7EH continuously 2 Display SRN Flag Send Check 3 Terminating procedure Perform the service reset 3 SRN Data Send Check 1 Check content Execute diagnostics 4 command to send data of 00H FFH 256Byte as one packet at 12 8msec packet interval at 1Mbps continuously 2 Display SRN Data Send Check 3 Terminating procedure Perform the service reset 4 Data Transmission Check Data transmission is checked in an actually composed system The System is composed of one master machine and max 15 satellite machines Note for starting the check When checking the set in which the SRN setting has been made cancel the SRN setting before starting this check When checking the actually composed system disconnect the SRM cables of the sets which are not checked or cancel the SRN setting If it is set to SRN exits data may be destroyed The transmission check setting must be performed after canceling the SRN setting of all the sets in the system First set the satellite machines then set the master machine 1 Setting procedure Satellite machine setting In the menu screen select Data Transmission Check Satel lite The display is as follows Data Transmission Check
117. ng procedure is performed If correct Extend RAM is ER 04MB is displayed and the check is terminated For the ER 03MB the following check is performed The following processes are performed for the check address 200000H 2FFFFFH PASS1 Memory data save PASS2 Data 0000H write PASS3 Data 0000H read compare data 5555H write PASS4 Data 5555H read compare data AAAAH write PASS5 Data AAAAH read compare PASS6 Memory data writed the saved data In case of a compare error in the check sequences of PASS1 PASS6 an error display is made If there is no error at all the check is normally terminated In addition the following address check is performed in the above check sequence In case of an error an error display is made and read write of the address where the error occurred is repeated Check point address 200000H 200001H 200002H 200004H 200008H 200010H 200020H 200040H 200080H 200100H 200200H 200400H 200800H 201000H 202000H 204000H 208000H 210000H 220000H 240000H 280000H 2 Display ER 03MB Check Extended RAM size 1024KB PASS or ERR OR Address XXXXXxH Write Data Read Data Error The error address and the bit are displayed only when the error occurs If the error does not occur they are not displayed 3 Terminating procedure After completion of check press the CANCEL key 4 ER 04MB Check 1 Check content The ER 04MB presence che
118. ods to perform a master reset MRS 1 Master resetting 1 Used to clear all memory contents and return machine back to its initial settings Return keyboard back to default for default kyeboard layout PROCEDURE 1 Turn off the AC switch 2 3 Turn on the AC switch 4 While holding down MRS 1 key turn to ON the reset switch MRS 1key The key located on Left upper corner of the key board Set the reset switch to OFF position MRS 1 Key i Keyboard layout 5 Enter the password key operation DISPLAY ENTEFPASSWORD Password input procedure Press the four corners of the key board in the sequence of a b c and d Keyboard layout 6 Master reset is started DISPLAY MASTER RESET 7 After completion of the master reset the buzzer sounds three times and the following SRV mode display is shown DISPLAY 12 15M SRU SRU MODE 2 SETTING 3 IRC SETTING 4 DOWN LOAD 5 DIAGNOSTIC MODE FOR EXIT MRS 2 Master resetting 2 Used to clear all memory and keyboard contents This reset returns all programming back to defaults The keyboard must be entered by hand This reset is used if an application needs different keyboard layout other than that supplied by a normal MRS 1 PROCEDURE 1 Turn off the AC switch 2 Set the reset switch
119. r may result in malfunction 4 IR module PRM 850 soldering conditions Main PWB N L Location No IC1 Part code VHIRPM850CB 1 When replacing the IR module IC1 observe the following condi tions Solder the IR module with the solder tip temperature at 280 degrees C within 3 sec 5 IPL Initial Program Loading function 1 Introduction The application software of the ER A750 is written in the flash ROM IC6 VHILH80S01 1 In the following cases writing procedure of the application software into the flash ROM is required When the flash ROM IC6 VHILH80S01 1 is replaced with new one The service part flash ROM does not include the application software in it When IPL writing is required because of change in the application software The service part of the main PWB unit CPWBX7510BH01 in cludes the flash ROM IC6 VHILH80S01 1 with the application software written in it and there is no need for writing the applica tion software when replacing the main PWB unit 2 IPLprocedure There are two ways of IPL procedures PLfrom P ROM via ER A7RS PL from PC via IR infrared communication The detailed descriptions on the above procedures are given below 3 IPL from P ROM via ER A7RS Install the master ROM to the IC socket IC12 on the ER A7RS Master ROM Part code VHI27801RAA1A IPL switch on the ER A7RS Set the IPL SW to ON position 1 2
120. ri 5 2 GHT Check ertet 6 3 CH2 Check 6 4 CHI Checker iiiter ede 6 5 CH4 CheCK uiid rie 6 6 CH5 Ch6Cck iere 6 PACHE tien 6 8 CH7 Check suu eiecti 6 3 6 Liquid Crystal Display Diagnostics 7 1 Liquid Crystal Display Check 7 3 7 Rear Display Diagnostics 1 Rear Display Check 3 8 SHARP Retail Network Diagnostics 8 1 SRN Self Check sse 8 2 SRN Flag Send Check 9 3 SRN Data Send Check Lag 4 Data Transmission Check 9 3 9 IDA amp ASK Diagnostics a 10 1 IDA tote 10 2 IrDA amp ASK Check checker mode 10 3 Data Transmission Check Receive mode 10 4 Data Transmission Check Send mode 11 3 10 Magnetic Card Reader Diagnostics 11 1 Magnetic Card Reader Check 11 3 11 Drawer Diagnostics seen 11 1 Drawer 1 Check u 11 2 Drawer 2 Check sese 11 1 General This diagnostics program is used for simplified check of the ER A750 series opera
121. rns to the diagnos tics menu Timer amp Keyboard amp Clerk SW Diagnostics DATA amp TIME YY MM DD HH MM lt in the display is highlighted every 500ms KEY CODE CLERK CODE 1 Timer Check 1 Check content The operation of the clock crystal of CKDC7 is checked YY MM DD MM HH in the display is highlighted every 500ms Check the highlighted display 2 Keyboard Check 1 Check content The A750 main body keyboard input test is performed The posi tion code corresponding to the inputted key is displayed in three digits The key layout corresponding to the input is displayed on the LCD screen Press the corresponding key to input The display of the inputted key is changed from white square k to black square C and a catch sound is generated 3 Clerk SW Check 1 Check content The code of the key which is inserted into the clerk key switch is displayed in a hexadecimal number 3 5 RS232 Diagnostics The main PWB and the option PWB RS232 interface of ER A7RS are checked Attach the 9 pin D Sub loop back connector UKOG 6717RCZZ of wiring in Fig 3 11 CD 1pin RD 2pin _ SD 3pin ER 4pin 34 GND 5pin DR 6pin RS 7pin 1 CS 8pin CI 9pin Fig 3 11 Wiring diagram
122. rol circuit Make sure that the voltage at the A side lead of the R4 resistor 1500 3W shown in Fig 6 is properly switched Procedure i Connect a terminating resistor or read network to the BNC con nector QONW 6856RCZZ Fig 2 ii Run the diagnostic program Data send check and make sure that the voltage at point A in Fig 6 is switched as shown in Fig 11 12 _ v 4 3ms 17ms Fig 11 bias circuit switching waveform iii If the waveform as shown in Fig 11 is not obtained it is most probable that transistor Q10 2904699 is defective 2 For the other check items refer to DIAGNOSTICS SPECIFICATIONS 2 Battery label The battery label is attached to the main chassis on the back surface of the set The battery label has the column to show the battery replacement date Put down the date in the following cases The battery life is about 3 years after replacement When the set is installed When the battery is replaced after installation CAUTION When the time written below comes ask your dealer for a replacement of the battery VORSICHT Wenn die untenbenannte Zeit erreicht wird ersuchen Sie bitte Ihren Fachh ndler um den Austausch der Batterie PRECAUTION Lorsque le temps crit ci apr s arrive demander votre revendeur local de remplacer la batterie par une nouvelle ADVERTENCIA Cuando se alcance el tiempo indicado abajo solicite a su distribuidor que
123. rruption of carrier OFF cannot be made The mirror image of carrier OFF shows carrier ON An interruption of CTC CH2 or CH3 cannot be made Timer interruption ROM sum check error TAM error Execute diagnostics command 1 The error status is displayed The error status is as shown in the table below An error is generated The error print is always 1 An unexpected interruption is generated DMA sent data and received data are different The number of data received in DMA is abnormal The number of data transmitted in DMA is abnormal An overrun error is generated An underrun error is generated An interruption of send complete cannot be made DMAC TC UP interruption Execute diagnostics command 5 The error status is displayed The names and the directions of the signals which are subject to diagnostics 5 command are as shown in the table below Direction Signal name Host gt Controller Host gt Controller Host gt Controller Host Controller Host Controller Host lt Controller Power interruption notice Power interruption ON initialization Power interruption ON continuation Power interruption process complete CH1 reception data present CH2 reception data present Check that the target bit of two statuses obtained by diagnos tics 5 command is 0 for ST1 and 1 for ST2 The other bits must be masked In the other c
124. ry data save PASS2 Data 0000H write PASS3 Data 0000H read compare data 5555H write PASS4 Data 5555H read compare data AAAAH write PASS5 Data AAAAH read compare PASS6 Memory data writed the saved data In case of a compare error in the check sequences of PASS1 PASS6 an error display is made If there is no error at all the check is normally terminated In addition the following address check is performed In case of an error an error display is made and read write of the address where the error occurred is repeated Check point address 180000H 180001H 180002H 180004H 180008H 180010H 180020H 180040H 180080H 180100H 180200H 180400H 180800H 181000H 188000H 190000H 1A0000H 1C0000H 2 Display Standard RAM Check Standard memory size 512KB PASSII or ERROR Error Address XXXXXxH Write Data Read Data The error address and the bit are displayed only when the error occurs If the error does not occur they are not displayed 3 Terminating procedure After completion of check press the CANCEL key 2 VRAM Check 1 Check content The following check on VRAM is executed The memory contents will not be changed by the check The following processes are performed for the check address 100000H 107FFFH PASS1 Memory data save PASS2 Data 0000H write PASS3 Data 0000H read compare data 5555H write PASS4 Data 5555H read compare data AAAA
125. ry key EMP Employee code entry key MISC FUNC Miscellaneous function key MODE Mode key ENTER Enter key AUTO1 2 Automatic sequencing 1 and 2 keys CH Charge menu key CHK Check menu key TRAYSBTL Tray subtotal key MDSESBTL Merchandise subtotal key KEYTOP DESCRIPTION SBTL Subtotal key CA AT Cash Amount tendered key 5 10 20 Speed tender key Used for AUTO8 9 and 10 key PAGEUP Page up key PAGEDOWN Page down key Cursor right key Cursor left key Cursor up key Cursor down key CANCEL 2 Optional key top KEYTOP Cancel key DESCRIPTION 000 000 key 98 135 Direct price look up keys 1 50 Department keys 2 9 Percent 2 9 keys d2 d9 keys Discount 2 9 keys CH1 CH8 Charge 1 8 keys CA2 Cash 2 key CONV1 CONV4 Conversion 1 4 keys RA1 RA2 Received on account 1 and 2 keys PO1 PO2 Paid out 1 and 2 keys AUTOS AUTO7 Automatic sequencing 3 7 keys CHK1 CHK4 Check 1 4 keys BT Bill totalize Bill transfer key CHECK ADD TRANSOUT Transfer out key TRANSIN Transfer in key CASHTIP Cash tip key CHARGETIP Charge tip key TIPPAID Tip paid key EAT IN 1 EAT IN Eat in 1 3 keys TAX3SHIFT TAX4SHIFT Tax 3 and 4 shi
126. s conversion table gt ER A750 A23 A22 Address 2XXXXXh 3XXXXXh 4XXXXXh 5XXXXXh ER 03 04MB RA23 RA22 Address 7XXXXXh 0 1 8XXXXXh 1 0 9XXXXXh 1 0 AXXXXXh 1 0 In the tables the address 400000h and after at the side of the ER A750 are not used by the ER 03MB or ER 04MB but is kept consid ering the commercialization of 4 Mb of expansion RAM in future The ER 03MB and ER 04MB use RA21 and RA20 respectively be cause they do not have RA23 or RA22 The address conversion circuit of RA21 and RA20 is shown below A24 gt JJ RA21 Z RA20 Fig 13 2 Decode base signal change As decode signals RAS3E and RAS30 signals are generated for even and odd addresses respectively based on the RAS3 signal 200000h 3FFFFFh To allocate even and odd addresses the ad dress line AO is used 13 2 Terminal table The terminal table of the RAM connector is shown below Table 17 Expansion RAM connector terminal table gt Signal name Signal name GND GND GND GND RA21 RA20 PSX Open PRAS30 5V 5V VCKDC VCKDC VRAM VRAM A16 A15 A14 WR A12 A13 A7 A8 A6 A9 A5 A11 A4 PSREF A3 A10 A2 A17 A1 A19 AO PRAS3E D7 DO D6 D1 D5 D2 D4 D3 The signals in are
127. s the display darkens the display and turning it forwards lightens the display Maro MGE0 43 uondo Jewel aJOWDY SuZv ua UM HIASV H3 uondo HON aro yaweo ua uondo pyeoq 5 eoo T eseuound 90 143 JOUISUI uoisuedx SuZv ud uondo 262 59 oseuound eoo T Od OGZV 4H3 uy eu JEJSEN uomeorunululo zec sH uomeorunuJul0 HI 4 0 uondo J luud ajoway OG V H3 NALS Ln ET he WE le ad NYS INNI uoneanDijuoo uu s S L SNOILdO cH3ldVHO 2 Options NAME MODEL DESCRIPTION ON LINESYSTEM ER A7RS 2 port RS232 I F MCR I F EXPANSION ER 03MB 1MBPS RAM MEMORYBOARD ER 04MB 2MBPS RAM REMOTEPRINTER ER 03RP ER 04RP MCR ER A8MR Magnet Card Reader DATABACKUP ER 02FD FD unit CE IR4 3 Service tools NAME Wireless I F for IR comunication PARTSCODE DESCRIPTION TERMINATOR 500 QCNCM7145RCZZ For SRN in line system EXPANSIONPWB CKOG 6724BHZZ MCR test card UKOG 6718RCZZ ForER A8MR RS232 LOOP BACK CONNECTOR 4 Supplies NAME U
128. sensor value is sensed at every 100ms and the state is displayed 2 Display Drawer 1 Check Drawer Open Sensor OPEN or CLOSE 3 Terminating procedure Press the CANCEL key to terminate the check 2 Drawer 2 Check 1 Check content The solenoid of drawer 2 is turned on and the drawer open sensor value is sensed at every 100ms and the state is displayed The display and the terminating procedure are the same as Drawer 1 Check CHAPTER 7 CIRCUIT DESCRIPTION 1 Hardware block diagram Drawer x 2 CPU 024 DRIVER 24V H8 510 Os DRIVER424V IR ART RS232 x 2 A DRIVER PSEUDO RECEIVER SRAM Or OPC1 512KB i TR fonna 80pin x 2 RAMCN bOpin LCD CONTROLLER CKDC7 KEY CUSTOMER DISP BRIGHTNESS CONTROL KNOB POWER SUPPLY FOR VACUUM FLUORESCENT TUBE INVERTOR LCD 320 x 240 dots CONTRAST ADJUSTMENT KNOB VCC POWER SUPPLY 2 Description of main 515 2 1 CPU HD6415108FX x dh A oM 15 m eR ERAS KES S 2 Block diagram EXTAL XTAL X E O OQ N 1 w o o c OQ00039030000 a a A A Data bus
129. setting of the break address register BAR is directly written in the addresses from FFFFOOh to FFFFFFh 9 Interrupt control There are roughly two types of interrupts Controlled inside the CPU Input into the CPU from outside Internal interrupts External interrupts 9 1 Internal interrupts Device interrupts built in the CPU are used for the following applica tions Table 8 Event factor SC11 SC12 FRT1 Application Interrupt source as IR channel Not used SC1 is used for CKDC interface INTMCR MCR interrupt to FT11 terminal Standard SHEN event for CKDC Simple IRC timer event RS232 timer event System timer 53 ms Drawer open timer Not used SSP request 9 2 External interrupts The following types of external interrupts are available NMI SSP RQO Standard I O interrupt IRG1 RS232 interrupt RQ 2 Used as terminal IRQ3 Used as SCK terminal 9 2 1 IRQO layout The interrupt factors for a total of 16 standard I Os are ORed inside the MPCA7 and input into the CPU as IRQO Each interrupt factor can be read by the internal register of the MPCA7 Table 9 lt IRQ0 component bits 1 gt BIT7 POFF SI7 Power failure detection signal input and software inter rupt 7 OR input BIT6 EXINT3 SI6 Optional external interrupt signal and software interrupt 6 OR input BIT5 EXINT2 SI5 Optional external interrupt signal and so
130. tent 1 2 Display IDA amp ASK Check DATA or TIMEOUT CHECKER MODE PASS or ERROR 3 Terminating procedure Press the CANCEL key to terminate the check 3 Data Transmission Check Receive mode 1 Check content Continuous IR communication between the ER A750 and the ER A750 This mode is on the reception side When data of 256byte 00H OFFH are received data packet counter is incremented by one Check that the counter increments 2 Display Data Transmission Check Receive MODE The RING COUNTER COUNTER 0 9999 is displayed 3 Terminating procedure Press the CANCEL key to terminate the check 4 Data Transmission Check Send mode 1 Check content Continuous IR communication between the ER A750 and the ER A750 This mode is on the transmission side When data of 256byte 00H OFFH are transmitted data packet counter is incremented by one Check that the counter increments 2 Display Data Transmission Check COUNTER Send MODE The RING COUNTER 0 9999 is displayed 3 Terminating procedure Press the CANCEL key to terminate the check 3 10 Magnetic Card Reader Diagnostics Read check of the optional ER A8MR ER A7RS is performed The test program reads the magnetic card of ISO 7811 1 5 standard and displays the data When the CANCEL key is pressed the display returns to the diagnostics menu 1 Magnetic Card Reader Check 1 Check content The test program rea
131. test card for ER ASMR UKOG 6705RCZZ RS232 loop back connector for RS232 connector m index PARTS CODE PARTS CODE ER A750 C Q CKOG 6724BHZZ QACCD8411BHZZ QCNCM1060AC03 CPWBF7508BH01 QCNCM5091BC1B CPWBF7513BH01 QCNCMS5278NCZZ QCNCM7125BHOI QCNCM7128BH1E CPWBN7511BH01 QCNCM7129BHOD CPWBN7512BH01 QCNCM7133BHZZ QCNCM7136BHZZ CPWBX7510BH01 QCNCM7145RCZZ QCNCM7179BHOD QCNCM7179BHOI CPWBX7517BH01 Zz ZZ Z ZZ Z Z Z Z Z Z QCNCM7179BH1A CSHEP6817BH01 O mmm mm m mimm mmm TI m o QCNCM7203RC8J D QCNCM7205RCOB DUNTK4783BHZZ QCNCM7209RC1E DUNTK4810BHZB mim QCNCM7212RC0B G QCNCW1057ACZZ GCABA7205BHSA QCNCW7081BHZZ GCABB7202BHSA QCNCW7086RC5J GCABF7255BHZZ QCNCW7199BHOE GCABR7256BHZZ QCNCW7204RC8J GCOVA7080BHSA GCOVA7085BHSA QCNCW7206RC1H GCOVA7131BHZZ 2121212121212 QCNCW7207RC1H GCOVB7081BHZZ QCNCW7208RC1B GCOVB7082BHZZ QCNW 7708BHZZ GCOVH7133BHZZ QCNW 7714BHZZ GFTAB6788BHSA QCNW 7826BHZZ GFTAS6787BHSA QCNW 7827BHZZ GFTAS6789BHSA QCNW 7828BHZZ GFTAS6790BHSA QCNW 7829BHZZ GLEGG6656BHZZ QCNW 7830BHZZ GLEGG6659BHZZ QCNW 7831BHZZ GLEGP6657BHZZ U U U U U U U D U U
132. tions in servicing The diagnostics program is built in the standard ROM 2 System configuration 2 1 Test system ER A750 only 3 Diagnostics Starting the diagnostics This diagnostics program is written in the external ROM and executed by the CPU H8 510 To operate this program the following condi tions must be satisfied 1 The power for the logic system is proper 45V VRAM VCKDC POFF 24V 2 The input output pins and the internal logic of the CPU are normal In addition CKDC7 MPCAT the system bus and the standard ROM RAM are normal To start the machine for the first time perform the master reset In order to add an option unit when the machine is normally operat ing perform the program reset 1 Master reset procedure 1 Turn off the power 2 Setthe CKDC reset switch to RESET position 3 Turn on the power 4 While pressing the specified key set the CKDC reset switch to the normal position 2 Program reset service reset procedure 1 Turn off the power Set the CKDC reset switch to RESET position Turn on the power N Set the CKDC reset switch to the normal position Do not press any key 3 1 Execution of diagnostics start the diagnostics select DIAGNOSTICS with the cursor in the menu selection in SRV mode and press the enter key The DIAG MAIN MENU is started and the following menu screen is display The cursor position is highlighted Use T key and key to move
133. to OFF position 3 Turn on the AC switch 4 While holding down MRS 2 key turn to ON the reset switch MRS 2key The key located on Right upper corner of the keyboard MRS 2 Key Keyboard layout 5 Enter the password key operation ENTEFPASSWORD Password input procedure Press the four corners of the key board in the sequence of a b c and d DISPLAY Keyboard layout 6 Set the fixed keys in the table below Start from the zero 0 key The keys are displayed sequentially DISPLAY ENTER 0 KEY Key setup procedure MRS 2 Key Setup Free key executed position set complete 0 Disable NOTES 1 When the 0 key is pressed the key of the key number on display is disabled 2 Push the key on the position to be assigned With this the key of the key number on display is assigned to that key position 8 When relocating the keyboard the PGM 1 2 mode use stan dard key layout Key name Key name Key name 0 key 00 key Decimal point key CL key FOR key SBTL key MODE key UP key DOWN J key LEFT key RIGHT key CANCEL key key ENTER key key key key key key key key CA AT key 7 Mast
134. tor 3KV 18pF RC FZ2241RC2A Capacitor 100WV 0 22uF VCKYTV1CF105Z Capacitor 16WV 1uF VCKYTV1HB102K Capacitor 50WV 1000pF VHDSFPB54 1 Diode SFPB54 VHILT1184CS 1 IC LT1184CS VHVIGPS0 5 1 Varistor ICPS0 5 VRS TS2AD822G Resistor 1 10W 8 2KQ 2 VRS TS2AD104J Resistor 1 10W 100KQ 5 VRS TS2AD224J Resistor 1 10W 220KQ 5 VRS TS2AD332J Resistor 1 10W 3 3KQ 5 VRS TS2AD472J Resistor 1 10W 4 7KQ 5 VRS TS2AD751J Resistor 1 10W 7500 5 VS2SC5001R 1 Transistor C5001 QCNCM7209RC1E LCD I F connector MLX53048 1510 QCNCM7212RCO0B CCFT connector EH S2B QCNCM7179BHOD INV connector MLX53015 0410 QCNCW7208RC1B LCD connector MLX 52044 1245 Unit CPWBN7512BH01 m Inverter PWB unit PARTS CODE DESCRIPTION PSPAG6728BHZZ Display spacer QCNCM7179BH0I Connector ML53015 0910 QCNCM7179BH1A Connector ML53015 1110 VVKFIP7B13 1 Display tube FIP7B13 Unit CPWBF7513BH01 Rear display PWB unit 10 Service tools PARTS CODE DESCRIPTION QCNCM7145RCZZ Temainator 509 for SRN in line system CKOG 6724BHZZ Expansion PWB UKOG 6718RCZZ MCR
135. uest from ADLC LCS Link controller chip select N U RS1 Register select 1 RSO Register select 0 MSK Mask signal DMA acknowledge 0 1 N U Memory write Data bus 2 9 SED1351FOA LB The SED1351FOA LB is a display controller that is used for the high duty dot matrix type LCD for graphic display This unit can interface with an 8 bit or 16 bit MPU with the READY WAIT input terminal Access to the VRAM is performed by the cycle steal method so that distortion of the screen is minimal Also the unit incorporates all the addresses and the data control circuits necessary for cycle steal requiring no external circuit The chip select output terminal for VRAM allows direct connection of eight 64K SRAMs or two 256K SRAMs without having to use any external decoder circuit The VRAM is mapped on the MPU s memory space to make it possible to address all the display data directly from the MPU thus providing efficient processing of display data including those of pictures TheSED1351Foa has two display modes the conventional ON OFF binary display mode and the gradation display mode including ON OFF and pseudo intermediate double tone In the binary display mode the maximum number of display dots is 524288 dpi and in the gradation display mode it is 262144 dpi when all the 64KB of memory of the VRAM 1 FEATURES The unit can be controlled with an 8 bit or 16 bit MPU Intel MPU Canbe interfaced wit
136. ve 59 4 ZAZ ZAGYYIN LAZ 2 OI LAQHUHON VAL AE EAL evi s 510 ZAL ZYL LAL LVL Sed oW SIHOW Sx V1Z2 688IN IET og LE 6518 res 99 ano 2X3H8 ONAS TdNINYL TAGYANDE TAGHNHL 9X LENTE zasa 9 09 0 6519 6518 cula GLONYL Tavsn 15 iuysn vec luvsn Sau gzz 3538 LdW3NHL GU g9 s LAGHADH UN V9 S LAGHNHL STHOW SIYOW LX T9A9H Lysa 1519 ISLE Iul SEE Lola 02 2 1 brid 9viu l nod ZOOHbL s 20 OL Q3193NNOO 38 LSNW qaSn LON dO SUL INO1dO Ov 6 98 28 9 SE oev YW ze sv 16 ore Sdu og ev 66 ev sz 22 92 92 vc c 404 zz 0 ig za i ri Sa or 1895 MS SL 2 NOTdl x LOHI LL ov 60 lt 80 E s 90 50 YO oev lt Qu 50 20 10 ram
137. xecute A7IPL EXE on P C Operation gt A7IPL 750 O0A ROM A750_0A ROM is file name of S type ROM object Program data is sent to ER A750 automatically Program data is received from P C automatically IPL from IR Connected IRDA 115200 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF A7IPL EXE is completed P C shows Completed ER A750shows Completed IPL from IR Connected IRDA 115200 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF Completed Turn OFF the power Select Normal Mode Set IPL switch Execute Master reset on ER A750 End CHAPTER 4 SRV RESET Program In the ER A750 the following reset switch location No S2 is used Loop Reset and switch to SRV mode to switch to the service SRV mode and to reset S2 S2 switch 1Side Rear side ON position Reset state 3Side Front side OFF position Reset cancel SRV reset Used to return the machine back to its operation state after a lock up has occurred PROCEDURE 1 Turn off the AC switch 2 Set the reset switch to OFF position 3 Turn on the AC switch 4 5 Turn to ON the reset switch The SRV mode is displayed as shown below DISPLAY 12 154M SRU SRU MODE 1 READING 2 SETTING 3 IRC SETTING 4 DUUM LOAD 5 DIAGNOSTIC MODE FOR EXIT CHAPTER 5 MASTER RESET All Memory Clear There are two possible meth

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