Hewlett- Packard 98034A HP-IB Interface Installation and Service
Contents
1. 098034 66502 CONTROL AHP i POLL LOGIC SWITCH 5V HP IB TRANSCEIVER 5 1 5V 1 1 2 I BUS LOAD BUS CLAMP R2 CR2 2 i 45V 12V v RI EE NS r m J FCRI 1 1 2 i 3 I pu PROCESSOR a iL ie LE tebe Li DATA BUS mh to Be Lo 5 5 m HP IB ADDRESS REGISTER 6 D PROCESSOR DATA BUS F 06 6 5 BUS i STORE INPUT DATA ADDRESS gt E s lt SWITCH mem Hv RE 51 u9 202K DO el 19 10 1 1 CALCULATOR INTERFACE 1 DATA INPUT DATA REGISTERS MULTIPLEXER H M 2 AH g TERRUPT 1 v INTERRUPT LOGIC Do BN CLR SELECT CODE DECODE DI Hag pe E 5 5 DI gt IACK f 45V tok 1 15 Si tack Da i i o REQ a pte e T e pin s eee sese 5 le ll s 8 1 0 REGISTER DECODEI i D i B2. 1 VO ROM CARAS e errare I Gate sen Bie dies 1 Technical Specifications 0 ooo oo 1 Bus Functions and Messages 4 Data HPAI IER MADE UEM 6 Chapter 2 Installation Unpacking Inspection 22 eros ved ebur a Reds 7 ERA Interconnecting Cables 0 0 8 Cable ECnOMRESHICUONS e rre lei eb 8 CORVCISIONAKI 05 37 ferns Nia eco ve I XO dera ts a SECC COCO CIA 9 ie ela cala lose a 10 Removing the Interface yin be E e 10 Changing Talk Listen Addresses a Ned pe EB bling System Controler o Luce soos eR EE ae VER Ora EAS 13 cuc xs Ev ona Ase 13 Chapter 3 Service luec CETERIS 15 PUNCUOM TCS oo feos edet a Bhs eost ak hated adidas n oe s e sucia 15 BeplaceableASSembllBS c c oo dn cesa tec tt Naso DR Ee CM 17 a ER ET EA 21 E 21 BuU LEHRER E ESS E SE 21 Guo ME nn 21 lcu Prou 22 caglio 22 TREO eta delia a 24 selec ode Decoder and s ct c oret tase ut 24 I O Register Decoder and Calculator Command Register 25 Calculator VO Dale Regi
3. t 2 I O REGISTER DECODER o Del 5 a 3 2 HP IB ADDRESS REI BUS ADDRESS SWITCHES 51 CALCULATOR INTERFACE DATA REGISTERS SYSTEM CONTROLLER SWITCH PROCESSOR DATA BUS 1 2 ii i pii BUS LOAD BUS CLAMP c 5 i 3 3 cR2 5 gt zev lt 1 lt sai 45V NIS P SEC a ARPES 7 ees gt 2 gt gt lt 3 as 5 S 22 Ly Ss 04 gt lt s D DO D7 de 95 lt 6 PROCESSOR DATA BUS P3 i de 5 P3 S gt 5V 4 5 sa 7 26 RCOD 5 79 CGR 2 1 J2 1 I I 45V 302K Sy yet RCCR CALCULATOR INTERRUPT LOGIC i 1 ni SHIELD EX P2 X a INTERRUPT LOGIC DATA INPUT MULTIPLEXER 2 4 6 i Gi 1 1 2 OSCILLATOR RIO 1 5V 1 6 TP 052 oss 5 Zouk oct P O U2 MICRO PROCESSOR CLR HP IB OUTPUT LATCH
4. DESIGNATOR PART NO DESCRIPTION 1 A1 di C2 0160 3847 2 Cap Fixed O 014F 100V A1C3 0180 0106 1 Cap Fixed 60yF 6V A1C4 C5 C6 0160 3622 3 Cap Fixed 0 1uF 100V A1P1 P5 1251 4257 5 Plug 6 pin A1Q1 1854 0019 1 Transistor NPN Si A1R1 0683 5625 1 Res Fixed 5 6 5 1 4W A1R2 R5 R8 0683 2225 5 Res Fixed 2 2KQ 5 1 4W A1R6 0683 1025 1 Res Fixed 1KQ 5 1 4W A1R7 0683 4725 1 Res Fixed 4 7 5 1 4W A1SW1 3101 2097 1 Switch 4PDT Select Code A1SW2 3101 1341 1 Switch 1PDT Parallel Poll Sense A1SW3 3100 3364 1 Switch 6 Gang Address amp System Controller A1U1 1820 1297 1 IC 74LS266 Quad NOR Gate A1U2 U6 U8 U11 U16 U18 1820 1198 7 IC SN74LSOSN Quad Gate A1U3 U4 U12 U13 1820 1562 4 MM74C175N 4 bit Register A1U5 1820 1199 1 IC 74LS04A Hex Inverter A1U9 1820 1284 1 IC SN74LS55 A1U10 1820 1427 1 IC SN74LS56 Decoder A1U14 1820 1144 1 IC SN74LSO2N Quad NOR Gate A1U15 1820 1195 1 IC 745175 4 bit Register A1U17 1820 1203 1 IC SN74LS11N 3 input AND Gate A1U19 1820 1266 1 MM80C97N A2 98034 66502 1 PC Assembly HP IB Control Logic 98034 69502 PC Assembly without U1 and U2 A2C1 C2 0180 0210 2 Cap Fixed 3 3uF 15V A2C3 C6 C8 C10 0160 3622 5 Cap Fixed 0 1pF 100V A2C4 0160 3334 1 Cap Fixed 0 01F 50V A2C5 0180 0106 1 Cap Fixed 60uF 6V A2C7 0160 3847 1 Cap Fixed 0 01uF 25V A2C11 0160 3482 1 Cap Fixed 430 PF 300V 1 A2CR1 1906 0075 1
5. e e Data Input Output 8 Data Valid Not Ready for Data Data Not Accepted Interface Clear Attention Service Request Hemote Enable End or Identify ground on interface card Figure 1 HP IB Cable Pinouts General Information 3 Logic Levels All signals use negative true logic low logical 1 High 22 4 V Low 0 4 V Line Termination Each of the 16 bus signal lines is terminated as shown here HP IB 6e2KQ Line Drivers Each of the signal lines has a driver circuit with the following characteristics Type Open Collector Output Voltage Low State lt 0 4 V 48 mA Output Voltage High State gt 2 4 V 5 2mA Line Receivers Each of the signal lines is received with a circuit having the following characteristics Hysteresis V pos V 0 4 V Low State Negative Threshold voltage V neg 20 6 V High State Positive Threshold voltage 2 0 V V pos Cable Length A 4 meter cable is supplied with the card Also see Cable Length Restrictions in Chapter 2 Operating Temperature Qed5 Power Requirements The calculator supplies all power for the card 4 General Information Bus Functions and Messages The following table lists the HP IB functions and the capability available with the bus interface A complete description of these interface functions can be found in the IEEE Standard 488 1975 Table 2 Bus Functions Available with the 98034A Function Implementation SH1 Sour
6. Initialize Circuit The Initialize Circuit applies 9 V to the processor after all other power supplies are stable This condition is indicated by the initialize signal INIT from the calculator and causes the processor to execute an initialize algorithm If the interface is the system controller this algorithm issues the Abort message IFC and sets the REN line true If the interface is not the system controller this algorithm clears all HP IB interface functions This circuit also provides a reset pulse to the HP IB Control Bus Latch Service 29 Controlling the Interface The calculator controls the interface via four I O registers through R7 These registers are memory locations used for the storage of input and output data It should be noted that these four registers are not dedicated components on the bus interface Instead all data passes through the Calculator I O Registers see block diagram on page 24 and is temporarily stored in the processor s read write memory A store operation from the calculator to any one of these registers transfers the data to the interface previously selected by the peripheral address A load operation from any of these registers into the calculator transfers the data from the selected interface to the calculator The calculator I O signals IC1 and IC2 determine which I O register is addressed as shown below Register The contents of each I O register are assigned unique roles such as data
7. status or control see the next table These assignments are described in the following pages NOTE The calculator s store and load instructions mentioned here are internal routines used by I O ROM to implement the user language l O statements and functions Registers R4 through 7 are not intended to be directly accessible via user language operations 30 Service Table 8 1 0 Register Assignments Register Direction I O Instruction Request Data from Bus R4 Send Data to Bus Interface Status Request R5 Interrupt Byte Null Operation R6 Send Multiline Interface Message Get Parallel Poll Byte R7 Send Uniline Interface Message Send Data The least significant eight bits of data contained in the calculator accumulator is transferred to the HP IB data bus DIO1 through DIO8 when a Store R4 instruction is executed Data transfer occurs only if the interface has previously been addressed as a talker on the HP IB If the interface has not been addressed to talk the calculator status line STS is cleared Receive Data When a Load R4 instruction is executed the interface accepts a data byte from the HP IB and places it in the Calculator Input Data Register If the interface has not been addressed to listen however the calculator status line STS is cleared and data is not accepted The first Load R4 instruction received by the interface after any other I O instruction is essen tialy a request data byte instruc
8. 0 1 13 15 0 1 1 1 0 14 16 0 1 1 1 1 15 17 0 1 0 0 0 0 16 20 1 Q 1 0 0 0 1 1 7 21 2 R 1 0 0 1 0 18 22 3 5 1 0 0 1 1 19 23 4 T 1 0 1 0 0 20 24 5 U 1 0 1 0 1 21 25 lt preset 6 V 1 0 1 1 0 22 26 1 W 1 0 1 1 1 23 27 8 X 1 1 0 0 0 24 30 9 Y 1 1 0 0 1 25 31 Z 1 1 0 1 0 26 32 1 1 0 1 1 27 33 1 1 1 0 0 28 34 1 1 1 0 1 29 35 1 1 1 1 0 30 36 Installation 13 Enabling System Controller Switch S3 6 on the A1 circuit board enables the calculator as the system controller The system controller function is enabled when A1S3 6 is ON Refer to the preceding photo Parallel Poll Switches Switch 51 on the A2 circuit board determines which data bit is output in response to a parallel poll operation 251 is preset to bit 1 at the factory To change the setting rotate the switch using a small screwdriver Switch S2 on the A1 circuit board determines the logic level used when sending the parallel poll bit The switch is preset to use negative true logic To use positive true logic set 152 to the 0 position 14 installation Notes 15 Chapter 3 Service Introduction This chapter contains a description of interface operation and instructions to help you repair the interface A complete circuit diagram and alist of replaceable parts are at the back of this chapter Due to the microprocessor based organization of this interface it s recommended that the interface not be repaired to the discrete compon
9. 1 Latch Plastic 7120 5166 1 Label Front Housing 7120 5167 1 Label Rear Housing 98034 90000 1 Manual Installation and Service 98034 66501 PC Assembly Calculator I O Logic Service 37 38 Service parallel poll logic 1 COMPONENT SIDE 2 A1 hp Part No 98034 66501 Rev B select code 7 talk listen address off on off on off system controller on 5 S 2 ite Q CIRCUIT SIDE i777 Ip Ep Sa I bo seo bod U 4 lo c e cu va ca 485 Dl RI 6 Leal NOTE 98034 66501 Rev B and Rev C boards are electrically identical To convert a Rev A board to Rev B C lift pin 5 on U14 and connect a jumper from U14 pin 5 to U14 pin 7 COMPONENT SIDE A2 hp Part No 98034 66502 Rev B E CIRCUIT SIDE ohms and capacitor values are shown in SS The first number indicates the base color color indicates the narrower strip e g 924 6 Blue 8 Grey 7 Violet 9 White voltage in the range of 2 thru 5 volts 5V T5V SHIELD X17 42v 18 iev vy STORE INPUT DATA 2 2 SELECT CODE DECODE i6 4 PAZ i5 98034 51005
10. Send Interface Bus Data SIBD command The outputs of this latch are routed to the HP IB data lines via the drivers contained in the HP IB Tranceivers The HP IB Control Bus Latch is a 5 bit latch which holds the bit pattern to be applied to the HP IB control lines EOI ATN SRQ REN and IFC The appropriate bit pattern is transferred from the processor data bus into this latch when the processor issues the Send Interface Bus Control SIBC command This latch consists of one 4 bit latch and one D flip flop The outputs of this latch are routed to the bus drivers contained in the HP IB Transceivers HP IB Address Register The HP IB Address Register consists of a hex tri state buffer and six switches Five of the switches are used to set the five least significant bits of the HP IB talk listen address When each switch is off its corresponding bit is set to a logical 1 The HP IB address switches are 28 Service connected to the five least significant bits of the processor data bus DO through D4 In addition to the HP IB address switches this module also contains the System Controller switch When this switch is on the interface assumes the role of system controller This switch is connected to bit D5 of the processor data bus The contents of this register is gated onto the processor data bus when the processor issues a Read Interface Bus Address RIBA instruc tion Data Input Multiplexer The function of the Data Input Multiplexer
11. disabled and control is returned to the system controller When IFC is high it has no effect on the bus operation SRQ Service Request is driven low by a device to indicate that it wants the attention of the controller SRQ may be set low at any time except when IFC is low EOI End or Identify may be used to indicate the end of an instrument s character string When ATN is high the addressed talker may indicate the end of its data by setting low at the same time that it places the last byte on the data lines REN Remote Enable is driven by the system controller and is one of the conditions for operating instruments under remote control Only instruments capable of remote operation use REN and they monitor it at all times Instruments that do not use REN terminate the line in a resistor load The system controller may change the state of REN at any time Transfer Lines NRFD NDAC and DAV The three transfer handshake lines are used to execute the transfer of each byte of informa tion on the data lines All instruments use these lines and employ an interlocked handshake technique to pass information This allows asynchronous data transfer without timing restric tions being placed on any instrument connected to the bus Transfer of each byte is ac complished at the speed of the slowest instrument NRFD Not Ready for Data indicates that all listeners are ready to accept information on the data lines When NRFD is low one or
12. more listeners are not ready for data NDAC Not Data Accepted is high to indicate the acceptance of information on the data lines by all listeners When NDAC is low all listeners have not accepted the information DAV Data Valid indicates the validity of information on the data lines When DAV is low the information on the data lines is valid for the listener s When DAV is high the information on the data lines is not valid Data Transfer Transfer of data on the bus is asynchronous It places no restrictions on the data rates of instruments connected to the bus The timing and levels required to transfer a byte of informa tion on the data lines are shown in the next figure Transfer is under the control of three Service 23 lines DAV NRFD and NDAC The talker sender of data controls the data lines and DAV Data Valid and the listeners acceptors of data controls both NRFD Not Ready for Data and NDAC Not Data Accepted The transfer of a byte of data is initiated by all listeners signifying they are ready for data by setting NRFD high When the talker recognizes NRFD is high and has placed valid data on the data lines it sets DAV low When the listener senses that DAV is low and has finished using the data it sets NDAC high Notice that the assertive or action state of both NRFD and NDAC is high Since all instruments on the bus have their corresponding lines connected together all listeners must be in a high state bef
13. which can assume the bus supervisory role Abort IFC Halts all bus operation and causes control to unconditionally pass back to the system controller NOTE When the 9825A Calculator is the system controller pres sing automatically outputs the Abort and Clear Lockout Local messages Data Transfer Rate The 98034A Interface transfers data at the rate of about 45k bytes 8 bit characters per second The actual rate can be considerably slower however and is determined by the talker and listener s on line at any given time The slowest device always determines the actual data rate Chapter 2 Installation Unpacking and Inspection If the shipping carton is damaged ask that the carrier s agent be present when the interface is unpacked Inspect the interface for damage If the interface is damaged or fails to meet electrical specifications immediately notify the carrier and the nearest HP sales and service office offices are listed at the back of this manual Retain the shipping carton and padding material for the carrier s inspection The sales and service office will arrange for the repair or replacement of your interface without waiting for the claim against the carrier to be settled Installation Before plugging in the bus card verify that its address and function switches are set to your system s needs The switches are preset at the factory as follows Table 4 98034A Factory Settings Switch Function Fa
14. Address Lines gt thru IC2 Register Code Lines DOUT Direction of Data Transfer 1 output gt IOSB Strobe Line c FLG Interface Flag 1 interface ready lt STS Interface Status 1 interface present lt INIT Calculator Initialize reset gt TRL Interrupt Request Low 0 7 lt Interrupt Request High 8 15 lt INT Demand Response to Interrupt Poll gt Bus Lines and Timing The standard HP IB signal lines are described next The function of each line is fully described by IEEE Standard 488 1975 Data Lines 0101 8 The data lines are used to communicate all data including input output and program codes addresses control and status information between instruments connected to the bus Data is sent one character byte at a time i e byte serial and bit parallel under control of the Transfer Lines In most instruments data is based on the 7 bit ASCII code Unused data lines terminate in a resistor load Control Lines ATN IFC SRQ EOI and REN The five control lines govern the flow of information over the data and transfer lines ATN Attention is driven by the active controller and indicates whether address commands ATN is low or data ATN is high are being transmitted 22 Service IFC Interface Clear is used only by the system controller to initialize the bus via the Abort message When IFC is low for at least 100 us all talkers and listeners are stopped the serial poll mode is
15. Diode Array A2CR2 CR3 CR5 1901 0040 3 Diode Si 0 05A 30V A2CR4 1902 3018 1 Diode Zener A2P1 P5 1251 4215 5 Connector 6 pin A2J1 1251 4333 1 Connector 24 A2Q1 1853 0016 1 Transistor PNP Si A2R1 1810 0264 1 Resistor Network A2R2 0683 5615 1 Res Fixed 5600 5 1 4W A2R3 0683 3325 1 Res Fixed 3 3K0 5 1 4W A2R4 R9 R12 0683 2225 3 Res Fixed 2 2K 5 1 4W A2R5 E 1 Optimum value selected at the factory A2R6 0683 1815 1 Res Fixed 1 8 5 1 4W A2R7 0683 2025 1 Res Fixed 2 5 1 4W A2R8 0683 5625 1 Res Fixed 5 6 5 1 4W A2R10 0698 3225 1 Res Fixed 14300 1 1 8W A2R11 0698 3557 1 Res Fixed 8060 1 1 8W A2R13 0683 1035 1 Res Fixed 10 596 1 4W A2SW1 3100 3378 1 Switch 1P10T Parallel Poll Bit A2U1 1816 0868 1 IC PROM A2U2 1820 1691 1 IC Nanoprocessor 2 1820 1216 1 IC SN74LS138N A2U4 U5 U11 1820 1562 3 IC MM74C175N 4 bit Register A2U6 1820 1753 1 IC MM74C74N A2U7 1820 1201 1 IC SN74LSO8N A2U8 1820 1199 1 IC 74LSO4N Hex Inverter A2U9 U10 1820 1439 2 IC SN74LS258N A2U12 1820 1417 1 IC 74LS26N A2U13 1820 1425 1 IC SN74LS132N A2U14 U17 1820 1689 1 IC MC3446P WI 98034 61601 1 Cable Assembly 5040 7801 1 Cover Plastic Left Front Housing 5040 7802 1 Cover Plastic Right Front Housing 5040 7803 1 Cover Plastic Left Rear Housing 5040 7804 1 Cover Plastic Right Rear Housing 2200 0510 2 Screws 4 40 long 2200 0536 8 Screws 4 40 short 5040 7836
16. Hewlett Packard 98034A HP IB Interface Installation and Service Manual HEWLETT PACKARD Warranty Statement Hewlett Packard products are warranted against defects in materials and workmanship For Hewlett Packard Desktop Computer Division products sold in the U S A and Canada this warranty applies for ninety 90 days from date of delivery Hewlett Packard will at its option repair or replace equipment which proves to be defective during the warranty period This warranty includes labor parts and surface travel costs if any Equipment returned to Hewlett Packard for repair must be shipped freight prepaid Repairs necessitated by misuse of the equipment or by hardware software or interfacing not provided by Hewlett Packard are not covered by this warranty NO OTHER WARRANTY IS EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE HEWLETT PACKARD SHALL NOT BE LIABLE FOR CONSEQUENTIAL DAMAGES For other countries contact your local Sales and Service Office to determine warranty terms 98034A HP IB Interface Installation and Service Manual Hewlett Packard Desktop Computer Division 3404 East Harmony Road Fort Collins Colorado 80525 For World wide Sales and Service ices see back of manual Copyright by Hewlett Packard Company 1976 Table of Contents iii Table of Contents Chapter 1 General Information Introduction
17. Switch Data Input Multiplexer Processor and ROM Control and Interrupt Logic Calculator Command Register Bus Transceivers Figure 6 98034A Simplified Block Diagram Foldout HP IB Data DIO1 DIO8 Transfer DAV NRFD NDAC Control IFC ATN SRQ REN EOI Theory of Operation The 98034A interfaces the calculator to the HP IB by performing four me preting control bytes from the calculator transferring data bytes from HP IB transferring data bytes from the HP IB to the calculator and transfi tion to the calculator A simplified block diagram of the interface is shown on the left The interconnections between processor ROM I O registers and other circui the processor calculator I O and HP IB The processor monitors the status of both the calculator I O and the HP II calculator is requesting an I O operation by monitoring the CFLG Calci the calculator command register If this signal is true the processor is instructions to the other modules to decode and execute the requeste processor monitors the status of the HP IB by periodically sampling it SRQ REN IFC and EOI and its transfer lines DAV NRFD and NDAC Multiplexer If a condition is detected that requires action message the processor issues the appropriate instructions to comple quested Please refer to the Complete Block Diagram on page 35 while reading section Select Cod
18. alculator is not the active control ler The processor enables the interrupt logic via the Interrupt Enable IENA line When an Abort message is received via the HP IB the interrupt causes the processor to generate a 100 us pulse on the IFC line and then initializes all of the HP IB interface functions within the interface The IFC line was previously set true as the result of an I O operation from the calculator When the interface is not the active controller the processor not only enables the interrupt logic via the Interrupt Enable line but also sets the Immediate Control line IMD true When an Abort message is received the interrupt logic generates a vectored interrupt to the algorithm which initializes all of the HP IB interface functions In addition when the controller in charge of the HP IB sets the ATN line true the interrupt logic immediately clears the HP IB Output Data Latch and disables the HP IB Transceivers for the HP IB data lines DIO1 through 0108 the DAV line the NRFD line and the EOI line then the NDAC line is set low This leaves the interface ready to receive data from the controller A vectored interrupt is also generated to the algorithm which controls the acceptance and analysis of the data sent by the controller HP IB Output Data and Control Bus Latches The HP IB Output Data Latch consists of two 4 bit latches Data is transferred from the processor data bus into this 8 bit latch when the processor issues the
19. ay be instrument program ming information or data readings Trigger GET Signals a group of selected devices to simultaneouslv in g y itiate a set of device dependent actions Clear DCL or SDL Causes an instrument to be initialized to a predefined or power up state a certain range function etc Remote REN Enables remote operation of all devices allowing paramet ers and device characteristics to be programmed via data messages Local GTL Causes selected instruments to switch to local front or rear panel control Local Lockout LLO Prevents local front or rear panel control of instrument func tions Clear Lockout Local REN Removes all devices from Local Lockout mode and causes all devices to revert to manual control See the following note Require Service SRQ Indicates a device s need for interaction with the controller Status Byte Transfers a byte 8 bits of status information to a listener One bit indicates whether or not the device is currently send ing the require service message The other 7 bits optional Continued indicate device dependent status 6 General Information Table 3 HP IB Message cont Message command or line Description Status Bit Transfers a single bit of device dependent status which may be logically combined with other Status Bit messages to the controller Pass Control TCT Passes bus controller responsibilities from the current con troller to a device
20. ce Handshake Complete Capability AH1 Acceptor Handshake Complete Capability T5 Talker Basic Talker Serial Poll Talk Only Mode Unaddress if my listen address MLA L3 Listener Basic Listener Listen Only Mode Unaddress if my talk address MTA SR1 Service Request Complete Capability RLg Remote Local Not Implemented PP2 Parallel Poll Omits capability of being configured by controller DC1 Device Clear Complete Capability Device Trigger Not Implemented C1 2 3 4 5 Controller System Controller Send Interface Clear IFC Send Remote Enable REN Respond to Service Request SRQ Send Interface Message Receive Control Pass Control Parallel Poll Take Control Synchronously General Information 5 The interface and calculator I O ROMs determine how these functions are implemented to generate messages for controlling the bus Some functions are not available to the user with certain calculator I O ROMs In many cases the I O ROM and interface handle the functions automatically as required to simplify bus operation for the user Here is a complete list of bus messages and their corresponding bus command or line name as described in previous HP IB manuals Refer to the appropriate I O ROM manual for more details Table 3 Messages Message command or line Description Data Transfer instrument dependent information between a talker and one or more listeners it m
21. ctory Setting A1S1 Select Code 7 152 Parallel Sense Neg True Logic position 1 153 1 5 Calculator Address Talk U Listen 5 off on off on off A1S3 6 System Controller Enabled on 251 Parallel Poll Bit Bit 1 Changing any of the switch settings except select code requires opening the interface case see page 10 for instructions After verifying or changing the switch settings install the card as follows 1 Switch the calculator off 2 Insert the bus card into any one of the 1 0 slots at the back of the calculator Press the card firmly into the slot 3 Verify that the required I O ROM is plugged in to provide the calculator with bus control see the manual furnished with the ROM 4 Switch the calculator back on 8 Installation Interconnecting Cables A 4 meter cable is supplied with the bus card The piggy back connector end is connected to the peripheral device Other devices may be added to the bus by using the standard bus cables listed below Accessory Number 1 meter 10631A 2 meters 10631B 4 meters 10631C Figure 2 Standard HP IB Cables Cabling Length Restrictions In order to ensure proper operation of the bus two rules must be observed regarding the total length of bus cables when they are connected together e The total length of cable permitted with one bus card must be less than or equal to two meters times the number of devices connected together the i
22. e Decoder and Switch The function of the Select Code Decoder is to determine when the interf the calculator The interface responds only when the code on the through matches the select code set on the select code switch code enables the interface to look for an I O command from the calculato is ready for an operation the interface indicates its presence to the the flag line FLG low and setting the status line STS low when no errc the interface Theory of Operation The 980344 interfaces the calculator to the HP IB by performing four major functions inter preting control bytes from the calculator transferring data bytes from the calculator to the HP IB transferring data bytes from the HP IB to the calculator and transferring status informa tion to the calculator A simplified block diagram of the interface is shown on the left The diagram shows the interconnections between processor ROM 1 0 registers and other circuits needed to support the processor calculator I O and HP IB The processor monitors the status of both the calculator I O and the HP IB It determines if the calculator is requesting an I O operation by monitoring the CFLG Calculator Flag line from the calculator command register If this signal is true the processor issues the appropriate instructions to the other modules to decode and execute the requested I O operation The processor monitors the status of the HP IB by periodically samplin
23. e mounting fasteners on any bus cable connector Additional conversion kits can be ordered by specifying HP Part Number 5060 0138 Select Code The select code switch is accessible through a small hole on the top of the interface case The switch is preset to select code 7 at the factory To change the setting rotate the switch using a small screwdriver Figure 3 Select Code Switch 10 Installation NOTE When the 9825A Calculator is used the bus card should not be set to select code O or 1 Those codes are reserved for internal calculator peripherals display keyboard etc Also do not use the same code for more than one interface Interrupt Priority Some calculator I O ROMs enable a peripheral interrupt scheme based on the interface select code Select codes 2 through 7 have a low interrupt priority while select codes 8 through 15 have a high interrupt priority If a device on the bus requires fast interrupt service the inter face should be set to a high priority select code See the appropriate I O ROM manual for more details Removing the Interface Covers Follow these steps to open the interface case 1 2 Switch the calculator off then unplug the interface from both the calculator and the bus Position the interface as shown in the first photo and remove only the four screws shown Then flip the interface over and remove only the upper right and lower left screws Carefully seperate the hal
24. ent level Instead run the Functional Test described next and then the 98034A Test Procedure described in your calculator s System Test Booklet If either test indicates a defective interface use the following Theory of Opera tion and Circuit Diagram to find the defective assembly If you have difficulty repairing the interface or if you would rather have HP repair it contact the nearest Sales and Service office for assistance office locations are listed after the circuit diagram Functional Test This test checks operation of most 980344 circuits To perform a complete test of the inter face follow the 98034A Test Procedure in your calculator s System Test Booklet This test assumes that the interface switches are set to their factory settings 98034A Factory Settings Switch Function Factory Setting 151 Select Code 7 152 Parallel Sense Negative True Logic position 1 153 1 thru 5 Calculator Address Talk U Listen 5 off on off on off 153 6 System Controller Enabled on 251 Parallel Bit Bit 1 least significant bit Refer to Chapter 2 for instructions on setting the switches 16 Service To Test the Interface Card T Plug the interface card into any I O slot the back of the calculator Verify that either a General 1 0 ROM or an Extended I O with General 1 0 ROM is plugged in the cal culator not appear refer to the 9825A System Test Booklet When an Extended I O ROM is plug
25. eral address matches the most significant address bit from the Select Code switch the Calculator Interrupt Logic pulls one of the calculator input output data lines low The setting of the Select Code switch determines which line is pulled low as shown in the following table Interrupt Request Bits Select Code Line Pulled Low Control Logic The Processor ROM 1 0 Register Selector and Oscillator form the control logic portion of this interface The Processor controls all interface operations by issuing instructions via seven control lines the 8 bit processor data bus and selecting I O registers via the I O Register Selector The algorithms for interface control and the implementation of the HP IB interface functions are contained in the 4096 bit ROM The Oscillator generates a 2 mHz approx asymmetrical waveform which is used as the main clock for the Processor and as the enable signal for the I O Register Selector The Processor also contains a vectored interrupt structure for conditions that require im mediate action These conditions are described next Service 27 Processor Interrupt Logic The Processor Interrupt Logic is a network of gates that provides the ability to interrupt the processor for either of two conditions e When an Abort message IFC is received from the HP IB or e When the control line is set true by the controller in charge An interrupt occurs for the second condition only when the c
26. g its control lines ATN SRQ REN IFC and EOI and its transfer lines DAV NRFD and NDAC via the Data Input Multiplexer If a condition is detected that requires action for example a Require Service message the processor issues the appropriate instructions to complete the operation re quested Please refer to the Complete Block Diagram on page 35 while reading the remainder of this section Select Code Decoder and Switch The function of the Select Code Decoder is to determine when the interface is addressed by the calculator The interface responds only when the code on the peripheral address lines through matches the select code set on the select code switch Receiving the preset code enables the interface to look for an I O command from the calculator When the interface is ready for an I O operation the interface indicates its presence to the calculator by setting the flag line FLG low and setting the status line STS low when no error conditions exist on the interface Service 25 I O Register Decoder and Calculator Command Register The I O Register Decoder is a network of gates which interprets the type of I O operation being requested by the calculator It determines whether the transfer is an input or output operation by looking at the DOUT line For an output operation the data on the calculator input output data lines IODg through IOD7 is latched into the Calculator Output Data Register when the I O str
27. ged in execute this line and verify the display When only a General I O ROM is plugged in execute this line and verify the display J If the display does not return after the line is executed press and rotate the select code switch to 0 and back to 7 Then repeat the appropriate line above If the display still does not return or if an incorrect number is returned the interface card is defective NOTE The numbers returned in this procedure will be incorrect when the Address and or System Controller switches are incorrectly set Service 17 Heplaceable Assemblies These assemblies are available for direct replacement Table 6 Replaceable Assemblies Assembly HP Part Number Calculator Logic Board A1 98034 66501 HP IB Control Logic Board A2 98034 66502 98034 69502 1820 1691 1816 0868 98034 61601 HP IB Control Logic Board without processor or ROM Processor ROM Cable Assembly 18 Service Notes Service 19 Notes 20 Service Notes Service 21 Calculator I O Lines The data and control lines available at the calculator I O slots are listed on the next page The lines are also shown in the block diagram on page 24 The bar above each line name indicates that negative true logic is used Table 7 Calculator I O Lines Signal Direction Line Description Calc 9 interface IODg thru 10D7 Input Output Data Lines gt PAS thru Peripheral
28. is register holds the data to be transferred from the calculator to the interface The data contained in the latches is gated onto the processor data bus when the processor issues a Read Calculator Output Data RCOD instruction The Calculator Input Data Register consists of two 4 bit latches and eight open collector NAND gates The data on the processor data bus is latched into the two 4 bit latches when the processor issues the Send Calculator Input Data SCID command The data in this register is transferred to the calculator input output data lines when the calculator requests an input operation 26 Service Calculator Interrupt Logic The Calculator Interrupt Logic allows the interface to request service from the calculator for several conditions which are described later in the section Controlling the Interface The Calculator Interrupt Logic is a network of gates and a one of eight decoder This logic pulls the appropriate interrupt request line IRL or IRH low when the processor issues a Calculator Interrupt Request CIRQ instruction and the calculator is not conducting an interrupt poll INT IRL is pulled low when the select code switch is set to an address between 0 and 7 and IRH is pulled low when the switch is set between 8 and 15 When the calculator senses a service request it conducts an interrupt poll to determine which interface requires service A poll is conducted when INT is low When the most significant bit of the periph
29. is to route either a data byte 0101 through DIO8 or a control byte EOI SRQ REN IFC DAV NRFD and NDAC from the HP IB Transceivers to the processor data bus The processor selects the data byte by issuing the Read Interface Bus Data RIBD command The control byte is selected when the processor issues the Read Interface Bus Control RIBC command This module consists of one AND gate and two quad 2 to 1 multiplexers HP IB Transceivers The interface uses four bus transceiver modules Two are used for the HP IB data lines DIO1 through DIO8 and two are used for the HP IB control lines EOI SRQ REN IFC DAV NRFD and NDOC These transceivers allow bidirectional flow of data and control information between the interface and the HP IB Each transceiver provides four open collector drivers and four receivers with hysteresis Parallel Poll Logic The Parallel Poll Logic provides the capability to respond to a parallel poll conducted by the controller in charge of the HP IB When the controller initiates a parallel poll ATN and EOI true and the calculator has requested service from the controller via the SRQ line the parallel poll logic sends one bit of status to the controller via one data line DIO1 through DIOS This logic consists of a 3 input NAND gate a slide switch to set the logic level of the bit and a switch to select which bit on the HP IB data lines will be used to send the response to the parallel poll
30. nstruction also causes the interface to enter a read status algorithm which transfers each of the four additional status bytes to the calculator with suc cessive Load R6 instructions If the status line STS is clear it will be set by the fourth Load R6 instruction The calculator does not have to read all four status bytes The read status algorithm terminates whenever the interface detects an instruction other than Load R6 before the fourth status byte has been transferred to the calculator The read interface status instruction must be com pleted however in less than 100 ms This restriction is necessary to insure that the Abort message IFC sent by the controller in charge is not missed The bit assignments of the four bytes are summarized on the next page 32 Service First Status Byte BitO Is 1 when error detected Bit2 15 1 when Device Clear received Second Status Byte HP IB Address Logical 1 indicates corresponding signal line is true Fourth Status Byte 6 7 Service Controller Talker Listener System ra p Request Active Active Active ER Set Esc odd Is 1 when the SRQ signal line is true Is 1 when the calculator is the active controller Is 1 when the calculator is the active talker Is 1 when the calculator is an active listener Is 1 when the calculator is the active system controller Is always 1 Is 1 when a serial poll is in process Is 1 when the EOI end of record line is true Fig
31. nterface card is counted as one device e The total length of cable must not exceed 20 meters For example there may be up to 4 meters of cable between the first two devices 2 devices x 2 m device 4m Additional devices may be added using 2 meter cables up to a total of 10 devices 10 device x 2 m device 20 meters using one 4 meter and eight 2 meter cables 4 8 2 20 If more than ten devices are to be connected together cables shorter than two meters must be used between some of the devices For example 15 devices can be connected together using one 4 meter and thirteen 1 meter cables 4 13 x 1 17 Other combinations may be used as long as both requirements are met There are no restrictions to the ways cables may be connected together However it is recommended that no more than 3 or 4 piggy back connectors be stacked together on one device The resulting structure could exert great force on the connector mounting and cause mechanical damage Installation 9 Metric Conversion The HP IB cable furnished with the 98034A Interface is supplied with mounting fasteners having metric threads Other HP IB instruments however may have either National Coarse American threads or metric threads The American threaded fasteners are chromium plated while the metric threaded fasteners are black Since metric and American threads cannot be connected together a conversion kit can be ordered Use this kit to replace th
32. o li w 25 07 RIBA J3 2 gt SCD Ka m v2 RCOD so lt Gael CA i LELR HP 1B 1 le 1 OUTPUT DATA LATCH 2 SCR ie ad a Gai 1 B i i i se 1 1 5 Sd 1 O 1 t 1 OSCILATOR RIO 7 1 i I t 1 r 1 1 1 ef P70 02 RE uw 45V Pe RCCR CALCULATOR INTERRUPT LOGIC 1 PROG cate 26 Pag PAI 2 SHIELD A 3 i lt DA CONTROL BUS LATCH 5 de GND INITIALIZE LOGIC RT 121 2K PAS Pag vee 2 45v ground on interface card Service 39 GROUND SHIELD ATN ATN SRO SRQ IFC IFC NDAC NDAC NRFD NRFD Dav DAV REN EOI DIO8 DIO4 DIO7 DIO3 006 DIO2 0105 DIO1 B 51000 HP IB Cable Pinouts Figure 10 98034A Circuit Diagram 98034 90000 MICROFICHE NO 98034 99000 HEWLETT il p Es PACKARD PRINTED IN U S A May 3 1979 99E491U 1 Vr 086 ENUEIN eolA18S pue
33. o the calculator with a Load R6 The parallel poll is terminated when the calculator executes a Store R7 instruction with the appropriate byte to clear the ATN and EO lines Notes CALCULATOR SELECT CODE SWITCH 10D g ERES 5 e SELECT CODE DECODER CALCULATOR OUTPUT DATA REGISTER CALCULATOR INPUT DATA REGISTER INTERRUPT LOGIC INITIALIZE LOGIC CALCULATOR COMMAND REGISTER IRL IRH EE H tT INIT 1 0 REGISTER DECODE INHIBIT 1508 DSB STORE 1 0 REGISTER 10 D OUT ici lt ic2 PROCESSOR DATA BUS 8 LINES 1 0 REGISTER SELECT LINES 9 HP IB ADDRESS REGISTER SWITCH PARALLEL REOI POLL LOGIC SWITCH RATN CONTROL LINES 7 RIFC HP IB DATA LATCH OUTPUT DIO1 DIOS Service 35 DIO i 8 LINES RANSCENERS 5 RANSCEIVERS 8 LINES HP IB HP IB RATN TRANSCEIVER NRFD IMD CLEAR HP IB INTERRUPT 1 VO REGISTER PROCESSOR p SELECTOR OSCILLATOR HP 18 BUS LATCH Figure 9 CONTROL 4 LINES 98034A Detailed Block Diagram 36 Service Interface Assemblies 98034 66501 5040 7802 98034 66502 5040 780 5040 7803 Table 9 Replaceable Parts
34. obe pulse IOSB occurs For an input operation when the calculator is not conducting an interrupt poll INT the data in the Calculator Input Data Register is placed on the cal culator data lines For both input and output the code on the DOUT IC1 and IC2 lines is latched into the Calculator Command Register when the I O strobe pulse IOSB occurs The Calculator Command Register consists of a 4 bit latch and four open collector NAND gates The latch holds the I O register code through R7 determined by IC1 and IC2 and the direction of the I O transfer determined by DOUT In addition one bit of the latch is always set when the calculator requests an I O operation This bit is buffered through one of the NAND gates and becomes the Calculator Flag line CFLG Setting this line true causes the flag line FLG to go high indicating that the interface is busy The other three NAND gates are used to gate the DOUT IC1 and IC2 signals onto the processor s data bus when it issues a Read Calculator Command Register RCCR instruction When the processor has executed the requested I O operation and is ready for another I O operation it issues a Clear Calculator Command Register CCCR instruction which clears the Calculator Command Register and readies the interface for another I O operation Calculator Data Registers The Calculator Output Data Register consists of two 4 bit latches and eight open collector NAND gates As described earlier th
35. ore that line goes high This wired AND situation allows a talker to recognize when the slowest listener has accepted a byte of data and is ready for the next byte The next figure also shows the timing of the transition to the non assertive state of these lines A listener may set NRFD low when it recognizes that DAV has been set low it must do so either before or at the same time it puts NDAC high The talker may return DAV to its high state after it detects that NDAC is high A listener may set NDAC low as soon as it recognizes that DAV is high it must do so either before or at the same time it places NRFD in its high state DAV TALKER NRFD LISTENER NDAC LISTENER The curved lines indicate interlocked signal sequence Listener becomes reacy to accept da a Tai er has put data on the ines Incicates data is valid Listener has accepted the data anc no icnger eques Talker indicates the is no longer valid anc change Listener indicates it is ready for new cata A new cycle begins equivaient to t o Time the data is put on ines before DAV is se ow Figure 5 HP IB Three wire Handshake 24 Service e o U Y DOUT Calculator O Calculator VO Registers Processor Data Bus Data Output Latch Bus Bus Transceivers Address Switch Calculator Interface Interrupt Logic Select Code
36. s active talker e Interface is active listener e Output register empty The calculator status line STS is cleared when the interface generates an interrupt for any of the above five conditions The status line is only cleared on the first output register empty interrupt All subsequent output register empty interrupts will have status set The interrupt request from the interface IRL or IRH can only be cleared by executing a Load R6 instruction If the status line has been cleared as the result of an interrupt it can be set by reading the interface status 34 Service Sending Interface Messages When a Store R6 instruction is executed the eight least significant bits of the data contained in the calculator are transferred to the Calculator Output Data Register on the interface The interface interprets this instruction as a command to send a multiline interface message to other devices on the HP IB If the interface is the active controller the ATN line on the HP IB is then set true and the byte in the Calculator Output Data Register is transferred to the HP IB After this multiline message has been transferred the ATN line remains true until either an instruction other than Store R6 is received by the interface or a Pass Control message TCT is transferred to another device on the HP IB with a Store R6 instruction When the calculator is not the active controller when the Store R6 instruction is received the interface clears the stat
37. sters LETT 25 Calculator Interrupt Logic isses 26 Gon 26 FTODGSSSOFABIGEDUDLISDUIC o cc ans o a ma 2f HP IB Output Data and Control Bus Latches 27 iv Table of Contents HP IB Address Register Data Input Multiplexer HP IB Transceivers Parallel Poll Logic Initialize Circuit Controlling the Interface Send Data Receive Data Read Interface Status Interrupt Operation Send Interface Messages Request Service Parallel poll Interface Assemblies Replaceable Parts List Circuit Diagram Figures 2 3 4 5 6 7 8 9 1 Tables wo m I 0 HP IB Cable Pinouts Standard HP IB Cables Select Code Switch Opening the Interface Case HP IB Three Wire Handshake Timing Diagram 98034A Simplified Block Diagram Interface Status Bytes Interrupt Status Byte 98034A Detailed Block Diagram 98034A Circuit Diagram HP IB Signal Lines Bus Functions Available with the 98034A HP IB Messages 9809344 Factory Settings Available Bus Addresses and Codes Replaceable Assemblies Calculator I O Lines I O Register Assignments Replaceable Parts 23 24 31 32 33 35 39 Chapter 1 General Information Introduction The HP 980344 Interface Card connects the HP 9825 Calculator to the HP Interface Bus The interface card conforms to the IEEE Standard 488 1975 allowing the calculator to perform a
38. tion The data byte placed in the Calculator Input Data Register may be transferred into the least significant eight bits of the calculator accumulator by executing either a Load R6 instruction or another Load R4 instruction In this case both the Load R6 and Load R4 instructions are treated as no operations by the interface The Load R6 causes the interface to remain in the input data routine permitting successive Load R4 instructions to rapidly input data Two Load R4 instructions are needed to input each data byte the first Load requests the byte and the second Load transfers the byte to the calculator Service 31 Read Interface Status The calculator can read the status of this interface by executing a sequence of five instruc tions The following table shows the sequence of instructions and the information transferred to the calculator 98034A Read Status Sequence Instruction Data Byte Load R5 HP IB Interface Signature Load R6 First Status Byte Device Clear and Error Load R6 Second Status Byte HP IB Address Load R6 Third Status Byte HP IB Control Byte Load R6 Fourth Status Byte Interface Status The execution of the Load R5 instruction causes the interface to transfer a data byte to the calculator The fifth and sixth bits are always set to a logical 1 The remaining six bits are determined by the contents of the Calculator Input Data Register and are ignored This byte is used to identify the interface This i
39. ure 7 Interface Status Bytes Service 33 Interrupt Operation The 98034A can be enabled to interrupt the calculator by transferring an interrupt enable byte from the calculator accumulator to the interface with a Store R5 instruction The bit assign ments in the interrupt enable byte are shown in the following table Service Controller Talker Listener Output Other i Register Register Interrupt Request Active Active Active Full Empty Conditions Logical 1 enables interrupt on SRQ Logical 1 enables interrupt on active controller Logical 1 enables interrupt on active talker Logical 1 enables interrupt on active listener Logical 1 enables interrupt on input register full Logical 1 enables interrupt on output register empty Logical 1 enables interrupt when error detected device clear or selective device clear received when not active controller or EOI received Enable EOI to clear status line STS Figure 8 Interrupt Enable Byte When the interface receives a Store R5 instruction the interrupt enable byte is transferred from the Calculator Output Data Register to an internal read write register in the processor The interrupt enable algorithm then checks the byte against existing conditions to determine if an immediate interrupt should be generated Any of the following conditions cause an im mediate interrupt e SRQ service request detected e Interface is active controller e Interface i
40. us line STS to indicate an error The interface sends uniline interface messages to other devices on the HP IB when the calculator executes a Store H7 instruction If the byte received via a Store H7 instruction has the eighth bit set to a logical 1 the remaining bits in the byte are sent as uniline messages as shown in the following diagram 7 6 5 4 3 2 1 0 Request Service When the eighth bit of the byte received with a Store R7 instruction is set to a logical 0 the instruction is interpreted as a Require Service message The seven least significant bits of this byte are stored in one of the processor s read write registers This byte is transferred to the controller in charge when a serial poll is conducted If the seventh bit of the byte is a logical 1 the interface automatically sets the SRQ line true and requests service from the controller in charge Parallel Poll The calculator can conduct a parallel poll when it is the controller in charge A parallel poll is initiated by setting both the ATN and EOI lines true The calculator can accomplish this by executing a Store H7 instruction with the appropriate byte as described in the Send Interface Messages section Once a parallel poll has been initiated the Status Bit message on the HP IB must be transferred to the Calculator Input Data Register This occurs when the cal culator executes a Load H7 instruction The byte that represents the parallel poll response is then transferred t
41. ves of the interface case and position them as shown in the last photo To reassemble the interface 1 Be sure that all five pin connectors on one board are aligned with their sockets on the other board Position the cable wires so that they are not crimped as the case halves are pressed together Secure the cable end of the case first using the two long screws Then replace the other screws Installation 11 A Remove only the four screws shown above B Flip the card over and remove these two screws ak S L2 wi L 3 LA E C Seperate the case halves and position them as shown Figure 4 Opening the Interface Case 12 installation Changing Talk Listen Addresses The bus interface is set to talk address U and listen address 5 at the factory These may be changed to any talk listen pair of characters listed in the next table by setting switch S3 1 through 5 on the A1 circuit board Setting each slide to the ON position corresponds to a 0 in the table Table 5 Available Bus Addresses and Codes Address Characters Address Switch Settings Address Codes Listen Talk 5 4 8 2 1 decimal octal SP 0 0 0 0 0 0 0 A 0 0 0 0 1 1 1 i B 0 0 0 1 0 2 2 C 0 0 0 1 1 3 3 D 0 0 1 0 0 4 4 E 0 0 1 0 1 5 5 amp F 0 0 1 1 0 6 6 i G 0 0 1 1 1 7 7 H 0 1 0 0 0 8 10 0 1 0 0 1 9 11 J 0 1 0 1 0 10 12 0 1 0 1 1 13 13 L 0 1 1 0 0 12 14 M 0 1 1
42. wide variety of operations via an HP IB system This manual describes how to install and service the 980344 Interface In addition a general description of HP IB operations is given in the following pages ROM Cards The I O ROMs plugged into the calculator determine which bus operations can be performed For example the General I O ROM for the HP 9825A Calculator provides control of one instrument at a time on the bus Use of the Extended I O ROM however enables complete control of bus functions After the interface is connected as described in Chapter 2 refer to the appropriate I O ROM manual for all bus control operating instructions Technical Specifications The bus card s electrical characteristics are listed below For complete details on HP IB electrical mechanical and timing requirements refer to IEEE Standard 488 1975 Select Code The bus card is preset to select code 7 at the factory A switch permits changing the setting if necessary Addresses The bus card is preset to ASCII talk address U and listen address 5 Any one of 30 other pairs of talk listen addresses can be switch selected on the card IEEE Standard Digital Interface for Programmable Instrumentation This standard describes the functional electrical and mechan ical elements of the HP IB system 2 General Information Bus Signal Lines The bus consists of 16 signal lines as follows Table 1 HP IB Signal Lines Data Input Output 1 e
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