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ASC2S Maintenance Manual

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1. ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION FGR PART 31769P61 TRANSORB 6 27 25 7 28 4V GEN INST CR1 CR22 CR23 P6KE27A 31769P59 TRANSORB P6KE6 8A 600W UNIDIRECTIONAL OTOROLA CR14 6 45 7 14V 6 6 8 31769 60 TRANSORB 6 600W UNIDIRECTIONAL OTOROLA CR18 CR19 31 4 34 7V 6 33870 1 DIODE FDLL4148 SMT 0035 NATIONAL CR2 CR12 CR13 CR15 FDLL4148 CR17 CR20 58064P12 DIODE 1N4763A 1W ZENER OTOROLA CR24 1N4763A 32416P6 DIODE BRIDGE 1A 800V 4 PIN DIP DIODES INC CR25 DB106 OR DF08 33831P4 DIODE 0520 20V 1 2 SCHOTTKY SMT CASE 403 OTOROLA CR3 CRS CR11 BR0520LT1 33831P3 DIODE MRB340 34V SCHOTTKY SMT CASE 403 OTOROLA CR4 CR6 CR7 CR8 BRS340TS CR10 58873P29 DIODE 1N5232B 5 6V 5 500MW ZENER OTOROLA CR9 REPLACES 58052P6 1N5232B 55205P17 FUSE 3 4A 250V 3AG S B 1 25 X 25 ITTELFUSE Fl 313 750 55205P19 FUSE 1A 250V 3AG S B 3 1 25X 25 ITTELFUSE F2 313001 32183P4 FUSE HLDR W CARRIER SOLDER TERM SCHURTER 1 XF2 FEU031 1659 31912 1 SPCR NYL 50ID X 760D 18 THK 3 AG F HLDR SEASTROM 1 XF2 5606 44 177 57255P700 WIRE 22AWG BLK 19 STRD TYPE B N 600V 1 XF2 SEE ENG SPEC 32758P1 INDUCTOR FERRITE BEAD TDK FB1 FB2 FB3 FB4 BF45 4002 31058P4 CONN CIRC 61S BOX MTG D SLDR CONT MIL C 26482 CANNON
2. ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION FGR PART 33764P4 IC MAX214 QUAD RS 232 XMTR RCVR 080 SMT 5028 300 AX214CWI 33853P1 IC 490 RS 485 XMTR SMT 508 150 LINEAR TECH 081 082 1 490 58 3385 IC MMBZ15VDLT1 SMT SOT23 OTOROLA U83 984 985 986 MBZ15VDLT1 U87 988 989 990 43730 2 6 DUAL 1501 8P DIP ONSANTO 091 CT6 33737P3 XTAL 32 768 2 SMT 405 EPSON 1 C 405 32 768K A2 33737P4 XTAL 14 7456MHZ SMT MA 505 EPSON Y2 505 14 745 2 33245 8 HEATSINK PLUG IN TO 220 AAVID XU79 576802B03100 32289 1 JUMPER SHORTING AMP XJP2 XJP3 XJP4 5 531220 2 XJ7 XJ8 56671P41 STNDF SWAGE 4 X 125 25 DIA BRS NI UNICORP M2 M3 8240 1 D 7 56671P4 STNDF SWAGE 4 X 469L 25 DIA BRS NI UNICORP XJ10 XJ11 XJ12 55251 1 7 56671P42 STNDF SWAGE 4 X 250 25 DIA BRS NI UNICORP XJ13 XJ14 XJ15 XJ17 SS244 1 D 7 56671P25 STNDF SWAGE 2 X 38L 16 DIA BRS NIC UNICORP XJ4 ss130 1 D 7 56671P37 STNDF SWAGE 6 X 406 25 DIA BRS NI UNICORP XJ9 ss359 1 D 7 N57P5006C SCRW 2 X 3 8 PH SLT STL CD MACH XJ4 N404P8C WSHR LK INT 2 STL CAD PLATED XJ4 33395P3 SPCR PCB LKING 38L 1 4 TURN PLASTIC HARTWELL HNST4 375 1 53048P12 TIE CABLE 75 DIA STD BLACK DENNISON 08 404 5 22 Table 5 8 Processor I O PCB Subassembly ASC 2S 2100 Exp W Olap 3425064 ECONOLITE P N 3425063
3. ECONOLITE P N PRIMARY DESC REF DESGN 34250 ASSEMBLY DRAWING 34251 SCHEMATIC PROCESSOR 1 0 34253 MASTER ARTWORK 34254 TEST SPEC 34252P1 PCB PROCESSOR I O INTF 32911P21 BTRY 3V PC MTG Bl 33748P5103 CAPAC 01 50V cl ES C4 C8 C13 C14 C15 C16 CI C18 C19 C20 C21 C22 C23 C24 C26 C27 C28 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C45 C46 C47 C48 C49 C50 C51 C52 C53 c54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C70 GTS 33740P5220 CAPAC 22PF 50V C12 33741P5104 CAPAC 1MF 50V C2 11 68 33877 105 CAPAC 1MF 35V TANT C29 33878P10 CAPAC 10MF 35V ELECT cal C69 33740P5270 CAPAC 27PF 50V C43 33740P5330 CAPAC 33PF 50V 44 31884P4 CAP VARIABLE 7 50PF C5 32895P7 CAPAC 120MF 50V ELECT C6 C7 33878P047 CAPAC 4 7MF 25V ELECT C66 C67 CH2 C73 32169P19 CAPAC ELECT 18000MF 35V C76 For Parts lists 34250G1 34250G2 One 8 MB of flash PROM U2 U2 and U92 33748P5103 CAPAC 01 50V CI8 C19 33748P5471 CAPAC 470PF 50V C80 33872P122 RES 1 2K 5 1 16W R82 R83 33901P1 IC 29F400BB FLASH 4 MB U2 U92 33902P32 IC 74VHC32 SMT S014 U93 SECONDARY DESCRIPTION MFGR PART PROCESSOR PROCESSOR 1 0 PROCESSOR ASC 2S LITHIUM PANASONIC VL2330 1VC SMT 0603 10 X7R CERM AVX 06035C103KAT2A SMT 0805 COG CERAM MURA
4. ES 22 MEG ES 0 5 13 R21 ES 5 49K 1 ES 13K 1 E N Ed ho d N N WAN FN EN Ed H gt Co E p 1 4W 5 1 16W SMT R81 1 16W SMT 1 16W SMT ES 4 7K 1 16W SMT 19 R30 22 1K 1 1 16W SMT 10K 1 R76 1M 5 R25 1K 5 1 16W SMT R77 R78 1 16W SMT 1 16W SMT 220 5 1 16W SMT 47K 5 R34 90 9K 1 1 16W SMT 1 16W SMT 15 OHMS 1 2W 5 DH DD WU tU UU nU UU SO DDD J 0 UU TX VU VU J VU J J UU UU UD UU ES ZERO OHM JUMPER R35 DIODE FDLL4148 CR2 CR16 CR12 CR17 CR13 CR20 R79 CR15 CR21 SECONDARY DESCRIPTION 100 CTRS D SLDR CONT PLASTIC 100 CTRS DO3316 SMT SOT23 GENERAL PURPOSE SMT SOT23 0603 0603 0603 MIL R 11F FIXED COMP 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 FIXED COMP THICK FILM 0805 SMT D035 MFGR PART MO EX 22 03 2021 AMP 206455 2 MO EX 22 03 2031 COILCRAFT DO3316P 104 JW MILLER 5254 GEN INST 01 T3904 NDA 2222 CRCW0603103J DAL E CRCW0603681J DALE CRCW0 6033317 RC07GF226J DALE DALE CRCWO 6030007 CRCW06035491F DALE CRCW06031302F DALE CRCWO603472J DALE CRCW06032212F DALE CRCW06031002F DALE CRCWO603105J DALE CR
5. NIC TOD Inputs 1 This test displays the state of each input from connectors A B and C when the controller is con nected to a suitcase tester Perform the following steps 1 Attach controller to a suitcase tester 2 Select INPUTS 1 from the DIAGNOSTICS SUBMENU When this is selected the controller beeps and displays a message saying that it will go into flash when this test is started 3 When the INPUT DIAGNOSTIC screen is displayed push VEH DETECTOR 1 input on the suitcase tester An X will be displayed on the screen in the VEH DETECTOR 1 position Activate the other switches on the suitcase tester to verify proper opera tion of all inputs 4 Press the NEXT PAGE F6 key to view and activate inputs on the remaining screens Push SUB MENU F3 to exit this test If this test uncovers an input failure use the detailed description of the I O section of the Processor l O and the schematic included in the document to pinpoint the problem 3 13 MAINTENANCE ADJUSTMENTS AND TEST KK KKK k k k k k k k k k k k k k k k k k k k k k k k k k k ck k k k k kk WARNING THIS DIAGNOSTIC RESULTS IN INTERSECTION FLASH PRESS ENTER TO PROCEED OR SUBMENU TO EXIT x k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k INPUT DIAGNOSTIC CONNECTORS A B amp C RING 1 RING 2 MAX RED
6. tact Ll DI I MIL 3 13 ette asi talas 3 15 Display i 3 16 Keyboard Eoi ib 3 17 5 qapas sasay clue sd Sard HQ 3 17 Telemetry mE 3 18 LOOP DAG 3 19 Memory ME cem EE 3 20 SEGTION p Ere 4 1 TROUBLESHOOTING enpera ara armenan Eu an Eu a iu OD 4 1 PRECAUTIONS 4 2 HARDWARE rr ee 4 3 SECTION 5 puc QNM 5 1 PARTS LISTS aii oe raid acta berg co DIA aue p sce dal 5 1 SECTION Ci RH 5 30 SCHEMATICS AND ASSEMBLY 8 4 40245222 5 30 Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 LIST OF FIGURES Py Zo MY O 1 2 ASC 2S System Block Diagram eiii u Kae een 2 2 Processor Section Block Diagramm te Po Pte REA 2 7 VO Section Block Diagram s a ae 2 8 Processor l O Module Component 2 9 SECTION 1 INTRODUCTION ASC 2S FAMILY The ASC 2S family of actuated controllers consists of three models Each provides the same control functions but uses a different type of input output I O structure to interface with o
7. 0022 50V 022 50V 0068MF 50V 1 50V 22MF 50V 047MF 50V 1 50V C25 C26 SECONDARY DESCRIPTION COG COG COG COG X7R XR7 X7R FGR PART F55C1502F F55C1692F F55C1912F F55C2152F F55C3092F F55C3162F F55C5622F F55C6042F F55C7502F F55C1003F F55C1103F F55C1433F F55C1623F F55C4753F F55C5113F F55C8063F F55C4642F F55C4751F F55C7151F URATA RPE113COG153J50V 121C0G222J50V 114C0G223J50V TA 113C0G68250V TA 122X7R104K50V PA 113X7R224K50V PA 122X7R473K50V TA ERIE 122254104M50V gt gt gt B f f F f Fg E EJ ZU PJ ZU BH E J p m 5 25 ECONOLITE P N 32082P2 58873P1 33214P1 58053P2 31626P2 32219P16 31535P1 31535P2 32099 1 31872 1 40057 10 58874 9 58874 16 58583 2 58583 3 31397P1 31495P1 31495P2 31938P3 31938 1 32529P125 32529P4051 43730P2 58454P33 58454P3 5 26 PARTS LISTS Table 5 9 Telemetry PCB Assembly 3409061 page 3 of 4 PRIMARY DESC REF DE SGN CAPAC TANT 2 2MF 2 cl C2 C4 C12 DIODE 1 5233 6V 5 CR2 CR3 DIODE LED RED 251 252 253 DIODE 1N4148 CR6 CR7 DIODE 1N5817 20V CRS CONN DIN 32S RA 1 WAFER 2 8 9 WAFER 3 1 2 5 JP6 JP7 XSTR NPN 2N22
8. 5 30 moe n ee RP20 1 055 1 IN 24 VEH DET v 40 Dra IRP23 13 13 IGI 12 U45 12 Uo OU n PED CLEAR IN 24 PED OMIT 24 PHASE 061 5 22 OUT U60 3 02 PHASE OMIT 45 6 OUT 24 CHECK U60 13 U59 8 11 15 RING 2 MAX 2 IN 2 CALL 4 CALL IN PREEMPT 5 CALL IN PREEMPT 6 CALL 59 17 COORD FREE b 20 07545 045 7 OUT GRN 2 1073 13 037 10 OUT OVERLAP B GRN OO o nse NET IER ee ee APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES CONNECTOR C ki Sea S ee CODE BUFFER OUTPUT CODE a P N s Yt oum for reo CER Reis ess iN ST M uet 1007 0042 Un zewaK R m E s ums 0546 s L 46 ues 1007 gspowrwk 1 00548 57 mn pez En U rs pes ew fra re LN 35 quet usi 5 O te ere sr m pes O e pres iso temores 848 626 OUT as CHECK AN se juris 34 OUT aT PHASEON RG mar
9. SPECIAL FUNTN 2 13 13 0412 IN PREEMPT 6 CALL 11 106316 1026 6 OUT SPARE 2 RP15 13 043 2 IN PREEMPT 4 CALL 15 066418 1029 4 OUT SPARE 3 RP13 17 048 2 IN PREEMPT 5 CALL 21 106315 1026 7 OUT SPLITBIT 1 12 17 047 2 IN STOP TIME 22 1064 13 1027 10 OUT PREEMPT 3 ACTIVE 042 4 IN SPLITBIT2 15 3 18 048 3 DUAL COORD 064 16 027 6 OUT NIC SPECIAL FUNTION 3 15 14 043 3 IN SPLIT DEMAND 27 06342 U26 11 OUT COORD STATUS 12 75 RP13 15 041 4 1 SE 15 U66 16 029 6 OUT NIC SPECIAL FUNCTN 1 10 77 RP12 15 040 4 IN OFFSET BIT 3 Bka RP12 19 U47 4 OFFSET BIT 2 H 065 13 028 10 OUT PREEMPT 2 ACTIVE ES RP13 19 0484 IN CYCLE BIT 3 33 166 14 1029 9 OUT OFFSET BIT 1 RP14 18 U49 3 IN COORD SYNC 34 u66 12 1029 11 OUT PREEMPT 4 ACTIVE U63 17 U26 5 OUT CROSS STREET SYNC 064 15 027 7 OUT CYCLE BIT 3 PM cope surrer CODE BUFFER OUTPUT d uem pets m Reus RP12 12 040 1 IN EXP DET 8 43 0645 029 7 OUT CYCLE BIT 1 S 7D RP14 19 049 4 PLIT BIT 1 RUN iE lt 14 E Re 45 06418 027 4 OUT SPARE 5 19 zr N s 0269 spurem2 e 40 Retz uet N s quee 0747 OUT PREEMPT 6 ACTIVE 17 81 RP14 16 049 1 IN
10. 5 29 SCHEMATICS AND ASSEMBLY DRAWINGS Schematics and assembly drawings for the controller are listed below in the order that they appear in this section These are subject to revision due to design changes made after the revision date of this manual Contact Econolite if revised drawings are required Schematic Number 34251 34091 33526 32846 Drawing Number 34240 34250 34280 34090 33525 32845 5 30 Description Processor I O Module Telemetry Module RS 232 Telemetry Data Module Description ASC 2S Controller Processor I O Interface Power Supply Telemetry Module RS 232 Telemetry Interface Data Module APPENDIX A TERMINAL CABLE DIAGRAMS The ASC 2S has the capability to switch between Data Communication Equipment DCE and Data Terminal Equipment DTE operation To talk directly to a Personal Computer with a stan dard cable the controller should be set into the DCE mode This makes the controller appear to the PC as a modem When attaching a serial printer or modem to the controller set the control ler to the DTE mode When connecting two controllers together for data transfer set one con troller to DTE and the other to DCE The controller is switched between mode via either jumper 4 34251 7 2 or through the user interface on the PORT 2 configuration screen Set JP4 to the left hand position for DCE mode and the right hand position for DTE mode The Terminal port uses the XON XOFF protocol
11. SGN WAFER 3 CKT Ji Qt L2 XS O1 JP2 JP3 INDUCTOR POWER SMT 4 JP5 HOKE HASH 250MH DIODE LED BRIGHT RED 2N3904 NPN 51 02 5 R1 R27 R54 ES 680 5 LO ES 330 5 11 R16 Hs 2222 10K 5 R6 R8 R32 R55 1 16W SMT R26 R40 R44 1 16W SMT 1 16W SMT R20 R45 R48 R51 R52 ES 22 MEG 1 4W 5 ES 5 49K 1 ES 13K 1 LE No pd NO N N Co E Co DH ho Ed gt 1 16W SMT 1 16W SMT ES 4 7K 1 16W SMT 19 R30 ES 22 1K 1 1 16W SMT 10K 1 R76 IM 5 R25 1K 5 1 16W SMT R77 R78 1 16W SMT 1 16W SMT 220 5 1 16W SMT 47K 5 R34 90 9K 1 1 16W SMT 1 16W SMT 15 OHMS 1 2W 5 un ZERO OHM JUMPER El A oum m mom mm m Um mu mb 0000 0000 Dm GU n Co Dd Co EH Co EW w N ES 0 OHM 5 270 5 1 16W SMT 100 5 R42 1 1K 5 1 16W SMT R47 1 16W SMT 1 2K 5 R41 51 1K 1 R5 1 16W SMT 1 16W SMT 1 16 W W R79 SECONDARY DESCRIPTION 10 DO3 SMT 0 CTRS 316 SOT23 ERAL PURPOSE SMT 060 060 060 MIL 060 060 060 060 060 060 060 060 060 060 FIX SOT23 3 3 3 R 11F FIXED COMP 3 3 3 3 3 3 3 3 3 3 ED COMP THICK FILM 0805
12. SMT 3528 SMT NEMCO CASE B SMT 0805 COG CERAM SMT 0805 COG CERAM SMT A TYPE SMT NEMCO CASE B AL SNAP MTG SMT 3216 20 TANT MFGR PART PANASONIC VL2330 1VC AVX 06035C103KAT2A MURATA GRM40C0G220J050BD K n C 1206C104K5RAC SPRAGUE 293D105X9035B2T NICHICON UWX1V100MCR1GB URATA GRM40C0G270J050BD URATA GRM40C0G330J050BD URATA TZBX4R500BA110 NICHICON UPL1H121MPH NICHICON UWX1E4R7MCR1GB NICHICON LK1V183MHSC KEMET T491A105M016AS For Parts lists 34250G1 34250G2 and 3425063 the following note applies One 8 MB of flash PROM U2 can be replaced by installing two 4 MB flash PROMs in locations U2 and U92 The following parts must also be installed C78 C79 33748P5103 33748P5471 33872P122 33901P1 33902P32 CAPAC 01MF 50V 78 79 CAPAC 470 50V C80 RES 1 2K 5 1 16W R82 R83 IC 29F400BB FLASH 4 MB U2 U92 IC 74VHC32 SMT S014 093 R82 R83 093 AVX 06035C103KAT2A MURATA ERIE GRM3 9X7R47K050B DALE CRCW0603122J AMD AM29F400BB 90EC FAIRCHILD 74VHC32MTC 5 11 PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 2 of 6
13. 060 060 060 060 060 SMT 3 3 3 3 3 0603 MFGR PART MOLEX 22 03 2031 COILCRAFT DO3316P 104 JW MILLER 5254 GEN INST 2 V5752 TEX F O T3904 NDA 2222 DAL CRCW0603103J DAL E CRCW0603681J DALE CRCW0 6033317 RC07GF226J DALE CRCW06035491F DALE CRCW06031302F DALE CRCW06034727 DALE CRCW06032212F DALE CRCW06031002F DALE CRCWO603105J DALE CRCWO603102J DALE CRCWO603221J DALE CRCW0O603473J DALE EB EB DALE CRCW06039092F A BRADLEY 1505 CRCWO80500J DALE CRCWO63271J DALE 06031010 DALE 06031120 DALE CRCW06031227 DALE CRCW06035112F DALE CRCW0603000J 5 13 PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 4 of 6 ECONO P N 33711P000 33873P6813 33713P222 33875P241 33872P753 33872P183 43654P2 33872P152 33872P121 33873P4493 31263P97 33873P1003 43577P3 32876P1 43577P26 31770 1 33859 1 33772 2 33864 09 32878P1 34245P13 33854P32 33703P04 33854P08 5 14 PRIMARY DESC REF DE SGN B Wn R60 681K 1 El Hs o 2 2K 5 240 5 R58 75K 5 1W SMT E Cn El O E N w 18K
14. INTERNAL ADVANCE U59 4 MODE B 62 11 OUT zu p is NE j OE RP20 12 055 12 IN MINIMUM RECALL N RESERVED X un 0 pe poe pres USHNG C APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES CONNECTOR B MEAR CODE BUFFER OUTPUT N Rae set N D 10 1E 1073 16 1037 6 OUT OVERLAP A GRN P zs 0645 N asPenoer E m 0945 0077 VERA Ne som Ca z 7944 0979 OUT OVERLAP R RED es E USE UT Ba RL zen En pre rm jarro H ENG U44 7 CUT OVERLAP C YEL RP19 17 054 2 05 PED OMIT U73 18 U37 4 OUT 3 DON T WALK erre OUT OVERLAP C RED 23 PED OMIT 0354 OUT 23 PHASE ON RP21 17 056 2 G a NUNTII E 07246 16 U36 6 Ur 23 CHECK CHECK 053 13 RING 2 PED RECYCLE 17 U36 5 OUT 23 PHASE NEXT ERROR INPUT CIRCUITS DESCRIPTION CODE BUFFER OUTPUT M 20 45 2F 075 14 30 073 12 n Pon Fe s ues af em e s jeu U55 15 N U45 9 CUT 24 YEL 24 PED DET JOVERLAP B YEL an B RED U45 11 24 WALK OU U44 10 m OVERLAP D GRN n Fear 522 EN 35 H en L eer EN pec X 39 U75 18 045 4 007
15. Record a All controller settings Print all data if possible b Mode of operation coordination preemption c All external conditions temperature humidity lightning d Time of failure e Interconnect type Record details of a failure condition f Controller hangs up g Record The interval how often hang up occurs every cycle during a certain function h Controller skips intervals i Record The interval under what conditions every cycle only when external command is applied Use descriptive statements j Local not responding k Incorrect data in a readback 4 1 TROUBLESHOOTING PRECAUTIONS i Incorrect output at a local j Abnormal LCD indications k Improper signal indications on the same phase conflicting conditions The fault isolation tables are preceded by some precautions It is imperative that these be read and understood before attempting to work on the ASC 2S controller PRECAUTIONS CAUTION Before doing any troubleshooting please note that much of the ASC 2S operation is deter mined by the program contained in the configuration EEPROM 1 3 Make sure that the program number on top of the controller matches the label num on EEPROM U1 located on the Data module If necessary and if PROM programming equipment is available use Appendix G to check EEPROM against required intersection configuration DO NOT unplug Data module while power
16. UAL COMPARATOR 150 5 150 132 M F 34290P1 POS ORGATI 150 El EX INVE RTER T SO14 UAD 2 T SO14 non mQ O 150 NPUT AND GATE 4150 MFGR PART KOA SPE ER RM7322BT DAL CRCW06036813F DALE CRCW2010222J DALE CRCW2512241J DALE CRCW0603753J DALE CRCW0603183J OHMITE 95J2R2 DALE CRCWO 6031 DALE E E 520 06031210 DAL CRCW0604993F DALE CW2C 14 10K 5 DAL CRCW06031003F BOURNS 4610X SPRAGUE 101 103 820C110N187 BOURNS 01 NAT HARRIS V150LA20B 1453 TIONAL LM3 93M OTORO SN74LS09D OTORO C68302FC16C NAT NAT SEE NAT D TIONAL 74 045 TIONAL DM74A1 4310R 101 103 8BDW LA LA ENG DWG TIONAL 74AL 532 LS08M ECONO PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 5 of 6 P N 33863 33860F 33865 34247 34248 33863 33863 33862 33861 33868F 33862 33858F 31414 40029F 33764F 33853F 33851F 43730 33737 39 L34 FE 33245F 32289F P244 1 P21 P22 P138 P245 P259 1 P3 P2 P3 PRIMARY DESC REF DESGN IC HCTMOS 74HCT244 U17 U18 U19 U24 U39 U59 IC 29
17. 56157 6 56157 101 57 9012 58229 3 N238P9B PRIMARY DESC REF DE PCA PROCESSOR 1 0 CONN E CARD 22 44 J6 KEY XJ6 SCREW 4 X 3 4 PH S XJ6 SPCR 25D X 25L XJ6 HEX NUT LK WSHR 44 XJ6 SGN SECONDARY DESC CO 156 CTR R ANGLE US TROLLER TYPE 2 E W 56157P5 ST L CD MACH P6 140 DIA THRU AL RIPTION EXP PARTS LISTS MFGR PART MICROPLASTICS MP0156 22 DW8R 375 MICROPLASTICS 04 0004 000 AMATO 9224 A140 10 5 23 ECONOLIT 34092 1 56829 4 54552 5 N402P3C 56182 54 54 54 54 54 54 54 19 31489 31489 57250F 89 89 89 89 89 89 89 89 89 89 89 89 5 24 P25 P37 P41 P49 P59 P65 P73 P82 P126 P163 P209 P213 P222 P234 P261 P265 P274 P331 P307 P289 P296 P302 E P N Table 5 9 Telemetry PCB Assembly 34090G1 page 1 of 4 PRIMARY DESC REF DESGN PCB HND TELEM 2 amp 4 WIRE PCB 1 251 HDW MTG RIVE T 3 32 X 34L O HD WSHR FL 2 NAR STL ES 1 ES 9 ES 60 ES 5 QU GJ GUOGU UJ UD Hi GG GJ GJ Gj UJ Wi oj GJ GJ oW ow doh Qo 0o No Hw x N 10 OHM 2W 5 W W R3 R28 R29 330 OHM 1 4W 5 R31 470 OHM 1 4W 5 R61 R62 R63 1K 1 4W 5
18. Remove the supply from the enclosure 3 6 MAINTENANCE CLEANING AND INSPECTION CLEANING AND INSPECTION General controller maintenance includes regular cleaning and inspection of the controller printed circuit boards PCB s electronic components connectors cables and plastic and metal parts of the enclosure Use the following cleaning and inspection procedure to prolong equipment life and to minimize the risk of failure Cleaning 1 3 7 The power source must be disconnected before attempting to clean any of the controller components When boards are repaired clean flux residue from solder connections with or an environmentally safe flux remover Free air dry Clean keys and front panels with a soft lint free damp cloth Free air dry Do not allow excessive amounts of water to collect around or enter keyboard and display areas CAUTION Do not apply any cleaning solvents to keyboards front panel display or any other plastic parts Clean PCBs with a non abrasive moisture and residue free aerosol duster MAINTENANCE CLEANING AND INSPECTION Inspection The following inspection guide is provided as a quick reference when inspecting the controller and its components Table 3 1 Visual Inspection Guide Capacitors general Burned spots damaged leads Capacitors ceramic or tantalum Broken or cracked bodies Capacitors electrolytic Ruptured bodies leaking electrolyte Connectors Broken loose
19. TCLK2 on processor chip U12 2 5 C This signal is also used to trigger the processors data request line DREQ 2 5 B of the independent DMA controller which transfers data to the LCD module System Control Pins is a bi directional pin acting as an input and when asserted along with the HALT pin 2 3 B it causes a total system reset The RESET and HALT signals are generated by a combination of U11 74L S09 U5 14538b 8 2 4 B C and U4 LM2598 5 0 3 5 B U4 holds the PWRGOOD signal low anytime VCC is out of tolerance If the program running in the proc essor fails to toggle the WDOG signal 8 5 B the U5 watchdog timer circuit will time out and generate a reset pulse The RESET pin can also act as an output which allows the program to output a RESET signal to peripheral devices BERR BUSW DISCPU and FRZ pins are not used 2 10 THEORY OF OPERATION Processor Module System Busses DETAILED DESCRIPTION System Busses Data Bus DO D16 This 16 bit bi directional three state bus is the general purpose path for exchanging data with memory and other system devices It can transmit and accept data in either byte or word widths For all 16 bit accesses byte 0 the high order byte of a word is available on D8 D15 and the low order byte is available on 00 07 2 3 C The low order data lines are buffered by the system data buffers before being routed to the various circuits Buffering to the parallel I O se
20. forse next oF wem uer uses Im RNG ZRED REST Urt46 45 0077 T ems ser RP20 13 13 RING 2 ALL U67 15 U31 7 OUT 8 GRN RED 069 13 033 10 OUT RING 2 STATUS BIT U67 11 U31 12 28 PED CLEAR NAT OUT W 13 052 13 IN 13 RING 2 STOP TIME RP 17 15 15 28 DET 12 ELM 11 RING 2 STATUS BIT ee 14 U31 9 8 YEL p OUT RP16 13 051 13 IN RING 2 FORCE OFF U33 7 8 DON T WALK OUT U33 12 OUT 2 STATUS PTF RP17 19 0524 28 HOLD G S D 6 745 0940 EL i es pera GOD areas AA U70 11 U34 12 OUT 256 PED CLEAR 6 17 18 052 3 IN PHASE OMIT T eee U53 15 IN 06 PED DET EE U67 12 U31 11 OUT 098 WALK U34 9 OUT 26 YEL 68 067 6 16 U31 6 OUT 28 CHECK EIER U33 5 OUT 26 DON T WALK H R54 R63 R U19 2 IN TESTC 64 RP18 19 0534 26 HOLD SEE TELEMETRY PORT 1 APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES CONNECTOR D PM surrer CODE BUFFER OUTPUT 52 un PREEMPT S ACTIVE Q Pz vere urs oUm PRI5 17_ U502_N PREEMPT CAIL CH U50 3 IN REMOTE FLASH 60 RP14 13 042 2 IN PREEMPT 2 CALL fe U28 6 OUT
21. 150 5014 150 132 6 8 34290 1 5014 150 m m 2 m 0 uoi C m SMT GALI GALI AD 2 INPUT AND GATE BUFFER LINE 5014 150 5014 150 DRVR 5020 300 TSOP48 PLCC44 6V8D M F 33866P1 6V8D M F 33866P1 3 TO 8 LINE DECODE DMUX SMT 5016 150 OCTAL BUS TRANSCVR SMT 8 BI SMT SMT SMT 5020 300 ADDRESSABLE 5016 150 501 16 300 1 OF 8 DATA SEL MPLEX SMT 100 SMT 18P 5016 150 5 50132 500 DIP DARLINGTON TEST ED REPLD 0900 0132 TO 2 20 1 AMP FGR PART OTOROLA C14538BDW NATIONAL LM393M OTOROLA SN74LS09D OTOROLA C68302FC16C E ENG DWG ATIONAL 74ALS32M ATIONAL 4 045 ATIONAL DM74ALS08M OTOROLA C74HCT244AD 0 z AMD AM29F800BB 90EC P S HILLIPS CN2681TC1A44 SEE ENG DWG SEE ENG DWG MOTOROLA MC74HCT138AD MOTOROLA MC74HCT245AD MOTOROLA MC74HC259D MOTOROLA MC68HC68T1DW NATIONAL LM2598 5 0 MOTOROLA MC74HC251D HITACHI HM628128BLFP 10 SPRAGUE ULN2803A MOTOROLA MC7812CP 5 21 PARTS LISTS Table 5 7 Processor I O PCB Subassembly 5 25 2100 3425063 Page 6 of 6
22. 2 27 Line Reference Circula tele 2 27 Processor l DC input CIrcuit u a uuu ce iet ere hte embed e he toe Der 2 27 FSK Telemetry Module u ie 2 28 Modulator Transmitter 2 28 Receive Filter And Demodulator 2 29 Table of Contents continued SECTION Pc emt PR 3 1 MAINTENANCE inen dert be e ede centi di Pa pd d n ede 3 1 UNPACKING T 3 2 INSTALLATION PROCEDURE ern ar 3 2 CONNECTOR CABLE ASSIGNMENT rire else 3 3 ENVIRONMENTAL 6 3 4 TEST EGUIPMEN eaaa tatit 3 5 DISASSEVIB wa tortor iet catre duo June Meter ea 3 6 Processor Module dag eos none 3 6 Power Supply cre eee e SSD a edes ete bay exe asas iin 3 6 CLEANING AND INSPECTION nee netten neri a 3 7 A T PES 3 7 INSPECHON A E e er M EU E 3 8 Lithium Battery ont ctu u UM sd 3 9 IMPORTANT SAFETY INFORMATION 2 3 9 ADJUSTMENTS AND TESTS ioter eter ae ee an 3 10 MODEM Check Out Procedure 2 1 u a I 3 10 Crystal Adjustment Procedure 3 12 Diagnostics Menlo su uma
23. 2 7K 1 4W 5 R33 4 7K 1 4W 5 10K 1 4W 5 R12 R14 R15 R45 R46 24K 1 4W 5 200 OHM 1 8W 1 487 OHM 1 8W 1 WIRE 22AWG SOLID XR58 ES Hs ES Ww ES E ow Ed pH Co D o N Co Ed Ow EH ho EH rm E Hs El 1 47K 1 8W 1 1 62KOHM 1 8W 1 2K OHM 1 8W 1 2 67KOHM 1 8W 1 5 11K OHM 1 8W 1 R30 5 62K OHM 1 8W 1 6 98K OHM 1 8W 1 27 4K OHM 1 8W 1 15 4K OHM 1 8W 1 10K OHM 1 8W 1 11 8K OHM 1 8W 1 13 7K OHM 1 8W 1 SECONDARY DESCRIPTION ASC 2 AL POP CAD PLATED BUS TINN IL R 11F FIXED COMP IL R 11F FIXED COMP IL R 11F FIXED COMP IL R 11F FIXED COMP IL R 11F FIXED COMP IL R 11F FIXED COMP IL R 11F FIXED COMP ED MIL W 3861 1 S QQ W 343 ASTM B3 MFGR PART BIVAR CP 3 CHERRY AAP 34 IRC SPH 10 5 RC07GF331J RCO7GFA471J RCO7GF102J RC07GF272J RC0O7GF472J RCO7GF103J RCO7GF243J MF55C2000F MF55C4870F SEE ENG SPE F55C1471F F55C1621F F55C2001F F55C2671F F55C5111F F55C5621F F55C6981F F55C2742F F55C1542F F55C1002F F55C1182F F55C1372F PARTS LISTS ECONO P N 584 584 584 584 584 584 584 584 1489 1489 1489 1489 1489 1489 1
24. 21 THEORY OF OPERATION Parallel I O Interface DETAILED DESCRIPTION Address Bus Data Bus Logic Level Translators Address Bus This bus carries the address information used by the input multiplexers and output latches to select a particular I O line It is a buffered subset of the processors address bus and includes BA1 BA3 Data Bus This bus carries the data that is sent to the output latches or received from the input multiplex ers It contains the buffered lower ODD data bus which includes BDO BD7 Logic Level Translators Each logic level translator consists of a three resistor network 10K 75K and 18K which con verts the 24 V FALSE 0 V TRUE logic levels of control signals from external equipment to the HCMOS logic levels required by the input multiplexers A 10K pull up resistor biases the input to the FALSE state when the external control input is not connected The voltage divider 75K and 18K establishes the input level to the input multi plexer An external input of 0 V to 8 V is detected as TRUE and an input of 16 V to 24 V is de tected as FALSE inputs are inverted internal to the processor The combination of the 75K resistor acting as a current limiter and the internal protection circuit of the input multiplexer pro tects against transient input voltages exceeding 24 V 2 22 Parallel I O Interface THEORY OF OPERATION Input Multiplexers Input Buffers Overlap Program Inputs DETAILED DESCRIPTION Input Multipl
25. 34260G1 3428561 3428562 3425064 3284562 34280 1 N695P9006C N695P13008C N44P9005C N695P13004C 31348P51 31348P12 34269 1 3254 N u 31144 1 3177561 N138P9008C N238P9B 32542P20 32542P103 32542P106 32542P100 53048P15 55399P1 53048 1 N PRIMARY DESC REF DESGN ASSY DWG 5 25 CHASSIS SUB ASSY ASSY PLATE CONN DISPLAY PANEL ASC 2S C C ASSY PS AC INPUT C C ASSY P S DC OUTPUT PCA PROCESSOR I O INTF PCA DATA MODULE ASC 2 POWER SUPPLY SCRW SEMS 4 X 3 8 SCRW SEMS 6 X 1 2 SCRW 4 X 5 16 FIL SLT SCRW SEMS 6 X 1 4 BLOCK LATCHING 2 PC PKG LATCH SPRING RESTRAINT CABLE STUD SNAP IN 345L IDENT PLATE CNTLR PCB ASSY O LAP STD N SCRW SEMS FSTNR BAIL RING WSHR WEAR CUP SPRING RETAINER RETAINER OCK RING TIE CABLE 4 DIA ST GROMMET STRIP TIE CABLE EMA 4 X PH SLT HEX NUT LK WSHR 4 STL CAD 75 DIA ST SECONDARY DESCRIPTION 5 25 2 5 25 D AD INTERNAL CABLE ASC 2S INTERNAL CABLE ASC 2S CNTRL TYPE 2 EXP W OLAP W EPROM 32K X 8 110 50 60HZ PH PHIL PH PHIL STL CD MACH PH PHIL 1 SET PER PKG ASC 2S A MD SLOTTED HD 1 4 TURN ECONOLITE B AD 31777AW NYLON BLACK 1 4 TUR
26. 5 D a E Hs 2 2 OHMS 5W R67 1 5K 5 R70 120 5 R72 499K 1 N R71 R75 100K 1 R15 R18 ES NTWK 10K CO Pl RP2 RP25 P27 RP29 RP3 P32 RP33 RP3 OGIC LEVEL TRANS P12 RP13 RP1 P16 RP17 RP1 P20 RP21 RP2 P24 ES NTWK 10K CO P3 RP4 RP37 P39 VARISTOR 55 JOULE RV1 RV2 RV3 LC o D F3 Ed gt EU d d UU d WU Ud Ud Ud d Ud Ud d UU d Ud UU SD UU Ud UO Ud UU DU U5 C LM393 10 C TTL LPS 74LS09 11 C 68302 12 C PRGMD PER 3424 13 ALSMOS 74ALS32 14 5 74 04 15 ALSMOS 7441508 016 HC Ex H HC HL C ZERO OHM JUMPE 10K 3W 5 W W m 1 16W SMT 1 16W SMT P 0 4 4 8 2 P S 5 R SMT 1 16W SMT 1 2W SMT 1 16W SMT R73 1 16W SMT 1 16W SMT 1 16W SMT IN RP26 RP31 RP15 RP19 RP23 IN RP38 14538B DUAL MONOSTBL SECONDARY DESCRIPTION THICK FILM 1206 0603 THICK FILM 2010 2512 0603 0603 WIRE WOUND 0603 0603 0603 REPLACES 0500 0039 0603 10 PIN SIP 9 RES 1W 2 REPLACES 0500 0213 SURFACE MTG CUSTOM 5020 300 10 9 RES MOLDED 212V 255V METAL OXIDE UL CSA RECOGNIZED PRECISION SMT 5016 150 D SMT 508 QUAD 2 I SMT 5014 SMT GAL16V8B UAD 2 5014
27. Advance Indicator Lamp Control AC Common Chassis Ground Logic Ground Flashing Logic Out Status Bit C Ring1 1 Yellow N1 Ped Clear N2 Yellow N2 Green Mode Output 18 Mode Output 2 Vehicle Detector 1 Ped Detector 1 Mode Input 1 Force Off Ring 1 Ext Min Recall Manual Control Enable Call To Non Actuated Test A AC Control Mode Bit A Status Bit B Ring 1 N1 Green N1 Walk Mode Output 17 Mode Input 18 Omit All Red Clear Ring1 Red Rest Ring 1 Mode Bit B Call To Non Actuated II Test B Walk Rest Modifier Status Bit A Ring 1 Mode Output 1 Mode Input 17 Ped Recycle Ring 1 Max II Selection Ring 1 Mode Bit C BEN eot mu 20 TYNX lt XS lt CHODUZZEFPACIOTMOOU gt 4 0 0 0 0 0 0 0 0 0 I I I I I I I I I I I 55 Pin Socket 22 55S PIN FUNCTION Mode Output 9 Preempt 2 Detector Mode Output 10 N3 Green N3 Yellow N3 Red N4 Red N4 Ped Clear N4 Don t Walk Mode Output 20 Vehicle Detector 4 Ped Detector 4 Vehicle Detector 3 Ped Detector 3 Mode Input 11 Mode Input 10 Mode Input 21 Mode Input 9 Ped Recycle Ring 2 Preempt 4 Detector
28. CR4 provide a bal anced isolated transient protected output Receive Filter And Demodulator Circuit Transformer T2 R1 R3 RV1 CR1 and CR2 2 5 B provide a balanced isolated input with transient protection C24 and R43 are the initial high pass filter This filter provides 6dB octave attenuation of frequencies below 480Hz 09 LM324 2 4 C is the input preamplifier with ad justable gain U9B U9D are the band pass filter that remove out of band high and low frequency noise signals Jumper JP3 2 5 C allows routing of the signal from the secondary of the output transformer to the input circuit in two wire mode the output transformer T1 is also the input transformer JP7 2 1 B provides a way to bypass the input filter The output from JP7 is then sent to the FSK demodulator as RC 3 6 D U8 XR 2211 3 5 D is the FSK demodulator It outputs the received data RD signal carrier detect CD and drives the carrier detect LED DS4 via 02 2 6 C R22 2 4 D sets the receiver center frequency 1700 2 2 29 SECTION 3 MAINTENANCE Several procedures guides and lists are provided for general maintenance of the ASC 2S family This section contains unpacking and installation procedures useful for the first ASC 2S installation and for later reference A disassembly procedure instructs on removing each module and major components Basic procedures include printed circuit board cleaning voltage checking and down time accumulator crystal
29. EXP DET 1 57 58 0064 OUT SPARE6 25 2 usos 2 en 795 sewer 13 16 048 1 IN EXPDET5 5 EXPDETS 063 13 026 10 OUT SYNC RP14 14 042 3 IN COORD FREE RP12 16 047 1 IN EXPDET7 065 17 028 5 OUT SPARE 8 ENSE RP15 16 050 1 IN EXP DET3 RP15 15 043 4 IN CYCLE BIT2 59 CR16 CR21 OUT PREEMPT CMU INTERLOCK Q3 R62 PREEMPT CMU INTERLOCK R61 U27 5 PREEMPT CMU INTERLOCK PREEMPT CMU INTERLOCK 12 14 040 3 IN TESTD 39 89 RP13 12 041 1 EXPDET6 APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES 25 PIN TELEMETRY CONNECTOR AND PORT 1 ERROR INPUT CIRCUITS DESCRIPTION CODE BUFFER OUTPUT U66 11 0572 RP35 15 11 a Js uem U30443 8 17 RP35 1 05713 IN LM SPARE 1 N T EXT ADDRESS ENABLE T OUT SPF 2 IN IN IN IN SYS DETA2 Rum EC CONFLICT FLASH ERROR INPUT CIRCUITS CODE BUFFER OUTPUT 10 U64 11 U27 12 OUT 5 92 RP36 17 030 6 7 93 RP36 13 30 15 21 94 RP35 17 057 6 IN a pon 0442 oun 96 Reste 008 Im 97 6 12 030 17 6 RP35 1 057 8 16179 Tessa m DESCRIPTION TLM SPF 3 YS DET B1 YS DET D1 ALARM 2 LOCAL FLASH LM SPF 4 SYS DET 2 SYS DET D2 TLM SPARE 2 DOOR OPEN Fi es es
30. J10 02 24 615 SPCL 31058P3 CONN CIRC 55S BOX MTG D SLDR CONT MIL C 26482 CANNON 211 02 22555 SPCL 31058 2 CONN CIRC 55P BOX MTG D SLDR CONT MIL C 26482 CANNON J12 KPTO2E22 55PDV 31369P27 CONN D SUB 25S W W ETAL SHELL CINCH J13 DBKL 25SUT 31369P26 CONN D SUB 15S W W ETAL SHELL CINCH J15 DAKL 15SUT 31369P25 CONN D SUB 9P ETAL SHELL CINCH J17 DEKL 09PUTI 58751P32 HDR 3 CKT LKG STRGHT 156 CTRS W LOCK GOLD MOLEX J18 26 61 4030 58751P14 WAFER POLARIZING 5 CKT 156 CTRS W LOCK AMP 19 640388 5 33852P68 CONN 68 PIN STRAIGHT 050 PITCH OLEX J2 15 92 1468 32158P113 HDR 13 26 CTR POL STR 100 CTRS W SHORT LATCH HIROSE J3 HIF3BAG 26PA 2 54DSA 32219P1 CONN DIN 32P R A W W 512L PANDUIT J4 100 632 051 32219P8 CONN DIN 32S STR A SD PANDUIT 5 100 632 432 31535B1 WAFER 2 100 CTRS OLEX J7 J8 TPL TP2 22 03 2021 TP3 5 12 ECONO PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 3 of 6 P N 31535 33879F 56668F 37129F 33730F 33730F 33872 33872 33872 54719 33873 33873 33872 33873 33873 33872 33872 33872 33872 33873 54582 33825 33872 33872 33872 33872 33873 33872 P2 P103 P681 P331 P153 P5491 P1302 P472 P2212 P1002 P105 P102 P221 P473 P9092 gt P000 P271 P101 P112 P122 P5112 P000 PRI ARY DESC REF DE
31. Phase 5 Phase On Phase 6 Phase On Phase 7 Phase On Phase 8 Phase On Phase 1 Phase Next Phase 2 Phase Next Phase 3 Phase Next Phase 4 Phase Next Phase 5 Phase Next Phase 6 Phase Next Phase 7 Phase Next Phase 8 Phase Next Phase 1 Check Phase 2 Check Phase 3 Check Phase 4 Check Phase 5 Check Phase 6 Check Phase 7 Check Phase 8 Check MODE 1 Inputs Pin A h A M B i B h C X Outputs Pin A DD A e B s B e C N C CC C NN C GG B A B C B t B f C M C DD C PP C HH A u A d B r B K C k C BB C MM C FF INPUT OUTPUT FUNCTIONS Function Preempt 1 Preempt 3 Vehicle Detector 9 Vehicle Detector 10 Vehicle Detector 13 Vehicle Detector 14 Vehicle Detector 15 Vehicle Detector 16 Vehicle Detector 11 Vehicle Detector 12 Timing Plan C Timing Plan D Alternate Sequence A Alternate Sequence B Alternate Sequence Alternate Sequence D Dimming Enable Automatic Flash Timing Plan Timing Plan Offset 1 Offset 2 Offset 3 TBC On Line Function Preempt 1 Status Preempt 3 Status TBC Auxiliary 1 TBC Auxiliary 2 Timing Plan Timing Plan Offset 1 Offset 2 Preempt 2 Status Preempt 4 Status Preempt 5 Status Preempt 6 Status Offset 3 Timing Plan C Timing Plan D Reserved Free Coord Status Automatic Flash TBC Auxiliary 3 Reserved Reserved Reserved Reserved Reserved MODE 2 Inputs Pin A h A M B i B h APPENDIX B PIN LISTS
32. REPLD 0900 0132 ULN2803A 40029P4 VOLT REG 12V TO 220 1 AMP OTOROLA U79 C7812CP 33764P4 IC MAX214 QUAD RS 232 XMTR RCVR U80 SMT 5028 300 AX214CWI 5 9 PARTS LISTS Table 5 5 PCB Subassembly ASC 2S 1000 3425061 Page 5 of 5 ECONOLITE P N 33853P1 33851P1 43730P2 33737P3 33737P4 33245P8 32289 1 56671 41 56671P4 56671P42 56671P25 N57P5006C N404P8C 33395P3 53048P12 5 10 PRIMARY D ESC REF DESG Ic 490 RS 485 XMTR U85 U89 U86 U90 IC MCT6 DUAL OPTO ISO U81 U82 MMBZ15VDLT1 U83 U84 U87 U88 U91 XTAL 32 768KHZ XTAL 14 7456MHZ 2 U7 JU XJP2 XJ7 STN STN XJ1 STN XJ1 STN XJ4 9 XJ8 DF SWAG M3 6 DF SWAGE 4 PER SHORTING XJP3 XJP4 E 4 X 125 X 469L DF SWAGE 4 X 250 3 XJ15 DF SWAGE 42 X XJ17 38L SCRW 42 X 3 8 PH SLT XJ4 WSHR LK INT 2 STL XJ4 SPCR PCB LKING TIE CABLE 38L 75 DIA ST N L Y HEATSINK PLUG IN TO 220 x 5 SECONDARY DESCRIPTION SMT 508 150 SMT SOT23 8P DIP SMT MC 405 SMT MA 505 25 DIA BRS NI 25 DIA BRS NI 25 DIA BRS NI 16 DIA BRS NIC STL CD MACH CAD PLATED 1 4 TURN PLASTIC BLACK MFGR PART INEAR TECH LTC490CS8 OTOROLA MBZ15VDLT1 ONSANTO CT6 EPSON C 4
33. XOFF character is recognized while the port is used for printing 2 Blocks of data of various predefined lengths are received from another device during the direct connect process The receive channel of SCC3 which is used for the SDLC interface generates an interrupt after a complete frame is received from a BIU or MMU Timer 1 is used for the telemetry channel and generates an interrupt when 1 It is time to turn on the carrier signal 2 It is time to transmit the data packet and 3 It is time to turn off the car rier Timer 2 is used for the SDLC channel and generates interrupts that set the proper timing of the transmission of SDLC frames to the BIUs and MMU 2 15 THEORY OF OPERATION DETAILED DESCRIPTION Processor Module Memory Memory Flash EPROM Program Memory The software program that controls processor operation is written into U2 29F800AB 90 5 4 D This is a 90 nanosecond rewritable flash EPROM that provides 1 Megabyte of program address space configured as 512K x 16 words The EPROM is accessed using zero wait states The number of wait states are set using the processors internal wait state generator associated with the master EPROM chip select signal 50 U2 is enabled by chip enable line CSOL U2 puts its data on the data bus 00 015 when the chip enable line is low and either or both output enable lines OEE or OEO 5 6 C are low A write operation to U2 requires that CSOL is low and WEO is low RAM Al
34. ZA NU ua PORT 1 FSK LOOP BACK CONNECTOR OUTPUT INPUT PIN PIN ao ja Attach a 600 ohm resistor between pins 1 and 5 TERMINAL PORT 2 ERROR INPUT CIRCUITS DESCRIPTION CODE BUFFER OUTPUT ERROR INPUT CIRCUITS CODE BUFFER OUTPUT DESCRIPTION PORT 2 TERMINAL LOOP BACK CONNECTOR OUTPUT INPUT PIN PIN APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES PORT 3 SDLC LOOP BACK CONNECTOR OUTPUT INPUT 5 1 Figure 2 1 ASC 2S System Block Diagram Figure 2 2 Processor Section Block Diagram Figure 2 3 Section Block Diagram Figure 2 4 Module Component Placement
35. adjustment A list of test equipment recommended for maintenance is also included The circuit components used in the ASC 2S require care in handling installing storing and operating both unmounted and mounted on printed circuit boards Modules and their components should only be handled at a static free workstation Personnel and equipment MUST be properly grounded Please refer to the Motorola CMOS LOGIC data book or any other MOS manufacturer s procedures for more information 3 1 MAINTENANCE UNPACKING AND INSTALLATION UNPACKING The ASC 2S controller is packed in a specially designed protective shipping carton All necessary precautions have been taken to ensure that the equipment is received intact and in proper working order However the following steps should be taken when unpacking the controller to verify that there is no shipping damage 1 Carefully inspect the shipping container for damage before opening If the container is damaged unpack the controller in the presence of the carrier 2 Do not discard the packing materials foam endcaps and box as they have been specially made for the ASC 2S and must be used should it be necessary to ship the controller again 3 Once unpacked carefully inspect the controller for damage Check for broken wires connectors loose components bent panels and dents or scratches on the enclosure 4 If any physical damage is discovered notify the carrier immediately INSTALLATION PROCE
36. be paired with more than one output or input circuit to generate a different error code with each connection CONNECTORA _ CODE BUFFER CIRCUITS CODE INPUT CIRCUITS T 00 N s pes ur oun s RP22 5 ES e ums quer un zzcm z 976 14 46 9 OUT 12 RP24 15 060 15 IN h 02 084 N um oUm D 763 ES 79 804 m foras 170 zz RED I 642 oun rw 0742 Uem a v 5 002 Nj oa PED OMT 0747 OUT z2 PED CLR Ust N FRING 1 FORCE OFF E RP20 ENG 1 OMIT ALL De 22 DON T WALK ues 064 TOUT or PHASEON x 17 Ree RNG TRED REST 07 RP22 14 058 2748 1061 4 OUT Z2 PHASE ON 2 060 14 IN RING 1 MAX 2 RPT Nj LAMP CONTROL R 09 jer 5242 EXTERNAL START q 19 RP2349 592 o amp ez 05518 Nj 7448 734 OUT FAULT MONITOR U78 13 N OUT IN 007 U62 10 OUT RING 1 STATUS 17 0596 1 0 MODE BIT r U78 12 U RING 1 STATUS BIT 78 16 U62 6 VOLTAGE MONITOR 2 k OC RP18 12 MANUAL CONTROL paz BB RP21 12 JU WALK REST E D C ee Y U78 11 U62 12 OUT RING 1 STATUS BIT 052 12 IN 056 13 10 OUT RP19 12 054 12 IN
37. bent corroded or missing pins cracked insulation incorrect polarization Equipment general Dented or bent Dust dirt lint grease oil excess resin spattered solder metal chips filings or other foreign matter in equipment Worn spots or deep scratches on surfaces marred protective finish exposing bare metal evidence of arcing loosening screw thread assemblies Hardware Incorrect screw length Missing screws nuts bolts rivets lockwashers and nutplates screws nuts or bolts with stripped threads ntegrated circuits Broken or cracked bodies corrosion shorted contacts Markings decals and reference Missing incorrect illegible or obliterated designators Printed circuit boards Broken cracked or burned parts broken or missing rivets broken circuitry chipped contacts copper showing on contacts copper showing on circuitry cracks holes or burns in cards defective soldering joints cracks flat surfaces bubbles or holes lifted pads broken or missing eyelets Wiring Cut burned or abraded insulation exposing bare conductor abrupt V bends which weaken conductor points of abrasion not insulated pinched or damaged wires broken or loose lacing loose clamps 3 8 MAINTENANCE Lithium Battery Safety Information CLEANING AND INSPECTION Lithium Battery The lithium cell battery mounted in the upper left side of the Processor I O module supplies power to the CMOS RAM and the Battery Backed Clock dur
38. functions PHASE ON PHASE NEXT PHASE CHECK GREEN YELLOW and RED DRIVERS WALK DRIVER and PED CLEAR DRIVER It is selected by address E20001 ILE1 is the latch enable for the bank of outputs containing the following functions Phase 1 8 DON T WALK DRIVERS RING 1 AND 2 STATUS BIT DRIVERS and OVERLAP DRIVERS ILE1 is also routed to the expansion I O connector 2 4 It is selected by address E20011 11 00 selects the input multiplexer bank containing the following functions Phase 1 8 HOLD PHASE OMIT PED OMIT VEH CALL DET PED CALL DET RING 1 and 2 INH MAX TERM MAX II SELECT OMIT ALL RED CLEAR RED REST PED RECYCLE FORCE OFF and STOP TIME along with CALL TO NON ACT WALK REST MODIFIER MIN RECALL INTERVAL ADVANCE MANUAL CONTROL ENABLE INDICATOR LAMP CONTROL AND EXTERNAL START It is selected by address E20021 1 selects the input multiplexer bank for the expanded I O function of the ASC 2S 2100 It is selected by address E20031 4 selects the input buffer containing the following functions MODE BIT A C PREEMPT DET 2 4 5 6 and the COORD FREE INPUT It is selected by address E20041 5 selects the input buffer containing the following functions TEST C SPARES 1 6 and the signal that tells the controller that an expansion I O module is present ASCIO It is selected by address E20051 IY6 and YT select the expanded I O input buffers They are selected by addresses E20061 and E20071 respectively 2
39. is applied to the controller Before working on any module ALWAYS take the following precautionary steps 4 5 4 2 Disconnect primary power from the controller before removing or installing modules Allow at least 15 seconds for the filter capacitors to discharge before working on any module in the controller Do not use low resistance VOM or continuity tester for continuity checks These may damage CMOS circuits Remember to handle the Processor module with care to ensure that the on card bat tery is not inadvertently shorted such as by laying the module on a metal surface or bent Be careful not to flex the Processor l O module excessively When bench testing the module should be supported by a fixture so that it lays flat and does not rest on the capacitor mounted on the read of the module WARNING Line voltages are present on the Processor l O Power Supply modules Extreme care should be taken when working in these areas TROUBLESHOOTING HARDWARE FAULT ISOLATION HARDWARE FAULT ISOLATION A Cabinet level fault isolation B Bench level fault isolation PROBLEM POSSIBLE CAUSE ACTION 1 115 VAC fuse blown 2 Controller not supplied with 115 VAC 2 Loose power supply harnesses 4 Power supply module failure Controller is inoperative Processor Monitor LED LED1 is OFF Time is lost when power removed Timing incorrect or inconsistent or controller hangs up 1 Battery jumper JP2 n
40. level serial data that originates at the FSK demodulator from output buffer U10 4 5 D to the SCC1 receive channel on the processor chip 34251 2 5 D The data rate is 1200 baud Data Carrier Detect CDA This signal originates at the FSK demodulator and is routed via U10 4 5 D to the DUART It indicates the status of the MODEM carrier signal The line is HIGH if the carrier is lost usually because of an abnormal condition Under normal conditions the line is LOW indicating that the carrier is present Modem Control 1 MDCTL1 This signal which originates on the DUART is used by the program to turn on the VALID DATA LED DS2 2 5 C Modem Control 2 MDCTL2 This signal which originates on the DUART is used by the program to turn on the transmit inter face circuit When MDCTL2 is LOW the LEDs inside opto isolators U4 and U5 MCT6 turn on thus turning on the transmitter output Modulator Transmitter Circuit U7C 3 4 A in conjunction with U2 3 3 C set the voltages used by U3 3 1 D the FSK modula tor U3 is a voltage to frequency converter One of three voltages are generated by U2 to select 1200 Hz Mark 2200Hz Space or 900Hz Soft Carrier Turn Off generation by U3 During standard four wire operation the TXDA signal selects between Mark and Space generation When Soft Carrier Turn Off operation is selected during two wire operation it operates as fol lows RTSA 3 6 A goes low at the start of a message During this t
41. the transient protection circuit is then applied to the power supply via connector J19 20 2 D Addi tional transient protection and noise filtering circuits are present on the power supply module Line Reference Circuits Signal OPTO1 is the 120 Hz line frequency reference used by the controller program as the in put to the real time clock It is generated by full wave rectifier CR25 VM88 20 3 C which rectifies the 120 VAC 60 Hz line voltage to produce a 120 Hz signal which is presented to dual opto isolator U91 MCT6 Zener diode CR24 1N4763A prevents output of the OPTO1 signal when the line voltage is below 82 VAC The OPTO1 signal is routed to U1B 14538 8 6 A Signal 2 is the 60 Hz line frequency reference used by the controller program during dimming operations It is generated by opto isolator U91 which only turns on during the positive half cycle of the waveform thus producing 60 Hz signal The 2 signal is routed to an input on DUART 020 SCN2681 4 5 A Processor l O DC input circuit 24VDC enters the module on connector 418 Diode CR4 MBRS340T3 20 4 B provides reverse polarity protection CR7 CR8 and CR10 provide current steering for the proper charging and discharging of the hold up capacitor C76 R31 limits inrush current while charging C76 24VE is the primary onboard 24VDC voltage source for I O devices 24VI supplies 24VDC to the 5VDC voltage regulator in the processor
42. the chip select signal for the data module CS3 is the primary chip select for all accesses Address decoding and DTACK and Wait State generation for these signals is performed onboard the processor chip RESETB 2 5 B is an active high reset signal for the DUART SCN2681 U20 4 5 A IWEO 4 5 D is the write enable signal for the odd addressed RAM chip This signal is gener ated by U14B 74ALS32 4 6 D by ORing the lower data strobe LDS from the processor the gated read write signal GR W from 021 GAL16V8 4 4 D GR W is held inactive when VCC fails which write protects the RAM when power is removed OEO 4 5 D is the output enable signal for the odd addressed RAM and EPROM chips and the data module This signal gates the data from the device onto the data bus allowing the proces sor to read the data This signal is generated by U14A 74ALS32 4 6 D by ORing the lower data strobe LDS with the inverted read write line RW RW is generated by U15A 74ACT04 4 5 C by inverting the R W signal from the processor IWEE 4 5 D is the write enable signal for the even addressed RAM chip This signal allows the processor to write data from the data bus into the device if the devices chip select line is active This signal is generated by U14D 74ALS32 4 6 C by ORing the upper data strobe UDS from the processor and the gated read write signal GR W from U21 GAL16V8 4 4 D GR W is held inactive when VCC fails which write pr
43. then reads the data from the data bus EEPROM retains all user data when power is not applied to the controller Memory Expansion Connector Connector J2 9 2 6 A D allows for several functions including memory system expansion Flash EPROM programming and system debugging The Flash EPROM download module can be inserted into this connector for rapid programming of the on board Flash EPROM All 68000 bus signals used by the ASC 2S are present on this connector Voltage Monitor Control The voltage monitor control circuit is used to force the Voltage Monitor output FALSE thus set ting the intersection to flash and turning on LED1 8 2 C The circuit consists of U11C and U11D 74LS09 8 1 C These two gates AND the VM24 and CPUVM signals VM24 is open collector output from comparator U10A LM393 3 4 B that uses as its pull up voltage the output of the watchdog timer DOG If VM24 CPUVM or DOG goes low VMC will go low FALSE VM24 is the output from the power supply voltage monitor circuit This signal is set low if the 24VDC supply voltage goes out of tolerance CPUVM is an output from the proces sor chip This line is set low when a flash condition is detected by the processor DOG is the output from the system watchdog timer circuit U5 14538 8 4 B The watchdog input is tog gled by the processor approximately once every 100 milliseconds DOG is set low if due to er ratic program behavior the processor fails to toggle
44. 0 Hz represents a digital LOW 1200 Hz represents a digital HIGH Common Mode Rejection Greater than 40 dB Input DATA CHANNEL CHARACTERISTICS Communication Line Unconditioned type 3002 voice grade four wire private line channel or equivalent Line Impedance 600 5 Type of Transmission Time division multiplex frequency shift keying Baud Rate 1200 bps Word Length Eight bits plus odd vertical parity Command Message Three words plus odd horizontal parity Readback Message Two words plus odd horizontal parity with phantom address Channel Capacity Twenty five messages per second Channel Operation One command message containing cycle offset split master zero and four special function commands is simultaneously transmitted to all local transceivers Up to twenty four command messages per second are then transmitted requesting status readbacks data and special command and information D 3 APPENDIX E ASC 2S LOOPBACK DIAGNOSTIC INPUT OUTPUT TABLES Loopback diagnostic failures are identified by error codes The tables in this appendix list these error codes and the input and output connections required for loopback diagnostics For connectors A B C D and Telemetry the connector pins and their corresponding input or output buffer circuits are listed with the associated error code The tables show groups of circuits that can be connected for loopback diagnostics Some groups contain one input or output circuit which can
45. 000 RES ZERO OHM JUMPER SMT THICK FILM 1206 KOA SPEER R43 R50 R60 RM7322BT 33873P6813 RES 681K 1 1 16W SMT 0603 DALE R49 CRCW06036813F 33713P222 RES 2 2K 5 1 2W SMT THICK FILM 2010 DALE R56 CRCW2010222J 33872P183 RES 18K 5 1 16W SMT 0603 DALE R64 06031830 43654 2 RES 2 2 OHMS 5W WIRE WOUND OHMITE R65 R67 95J2R2 33872P152 RES 1 5K 5 1 16W SMT 0603 DALE R68 R70 R71 R73 CRCW0603152J 33872P121 RES 120 5 1 16W SMT 0603 DALE R69 R72 CRCW0603121J 33873P4493 RES 449K 1 1 16W SMT 0603 DALE R7 CRCW06034493F 5 8 PARTS LISTS Table 5 5 PCB Subassembly ASC 2S 1000 3425061 Page 4 of 5 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 31263P97 RES 10K 5 W W REPLACES 0500 0039 DALE R74 R75 CW2C 14 10K 5 33873P1003 RES 100K 1 1 16W SMT 0603 DALE R9 R15 R18 CRCW06031003F 43577P3 RES NTWK 10K COM PIN 10 PIN SIP 9 RES 1W 2 BOURNS RP1 RP2 RP10 RP34 REPLACES 0500 0213 4610X 101 103 43577P26 RES NTWK 10K COM PIN 10 PIN 9 RES MOLDED BOURNS RP3 RP4 4310R 101 103 31770P1 VARISTOR 55 JOULES 212V 255V METAL OXIDE HARRIS RV1 RV2 RV3 UL CSA RECOGNIZED V150LA
46. 05 32 768K A2 EPSON 505 14 745 2 AAVID 576802B03100 AMP 531220 2 NICORP 5240 1 7 5251 1 7 S244 1 D 7 ICORP HARTWELL 5 4 375 1 DENNISON 08 404 PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 1 of 6 ECONOLITE P N 34250 34251 34253 34254 34252 1 32911P21 33748P5103 33740P5220 33741P5104 33877P105 33878P10 33740P5270 33740P5330 31884P4 32895P7 33878P047 32169P19 33745P2105 PRIMARY DESC REF DESGN ASSEMBLY DRAWING SCHEMATIC PROCESSOR 1 0 MASTER ARTWORK TEST SPEC PCB PROCESSOR I O INTF BTRY 3V PC MTG Bl CAPAC 01 50V cl C4 C8 C13 C14 C15 C16 C17 C18 C19 C20 C21 E22 C23 C24 C26 C27 C28 C32 C33 C34 235 C36 C37 C38 C45 C46 C47 C48 C49 C50 251 C52 C53 C54 C55 C61 C62 C63 C64 C65 C70 C75 CAPAC 22PF 50V C12 CAPAC 1MF 50V C2 C11 C68 CAPAC 1MF 35V TANT C29 CAPAC 10MF 35V ELECT C31 C69 CAPAC 27PF 50V C43 CAPAC 33PF 50V C44 CAP VARIABLE 7 50PF C5 CAPAC 120MF 50V ELECT C6 C7 CAPAC 4 7MF 25V ELECT C66 C67 C72 CIS CAPAC C76 CAPAC 16V C9 C10 C25 I H ECT 18000MF 35V SECONDARY DESCRIPTION PROCESSOR I O PROCESSOR 1 0 PROCESSOR I O 5 25 LITHIUM SMT 0603 10 X7R CERM SMT 0805 COG CERAM SMT 1206 10 X7R CERM
47. 0mV 750V 10 MS Capacitance lt 100 pF RESISTANCE 2005 20 5 OHMS 3 Frequency counter Used for Down Time Accumulator crystal adjustment Note that the DTA crystal adjustment is a high precision adjustment therefore an accurate frequency counter is required 3 5 MAINTENANCE DISASSEMBLY Processor l O Interface Modules Power Supply DISASSEMBLY When disassembling the controller always disconnect input power before attempting to disassemble any part of the controller Below is a disassembly description for each module CAUTION Disconnect Input Power before attempt ing to disassemble the controller Processor Module Processor l O module is attached to the enclosure by two 1 4 turn fasteners To remove the module 1 Disconnect the interface cable to the front panel 2 Turn the fasteners 1 4 turn to the left 3 Hold onto the assembly by the connector plate and pull the module out from the bottom until it slides out of the card guide on the inside top of the enclosure 4 Pull the module out far enough to disconnect the two power supply harnesses attached to the rear of the module Power Supply The power supply is mounted on the inside rear panel of the enclosure on standoffs The supply is held in place by four screws and washers To remove the Power Supply module 1 Remove the Processor l O module 2 Remove the two wire harnesses from the power supply module 3 Remove the four screws and washers 4
48. 1 OTOROLA N2222 ETEMA DC103H EC 24 PANASONIC ERZ C14DK180 OURNS 299W 1 503 OURNS 299W 1 103 REMIER MAGNETICS SD 544 REMIER MAG SD 545 OTOROLA M339P EXAR R2206CP EXAR R2211P OTOROLA 324N OTOROLA 1741 1 INST 74HC125N TOROLA 74HC4051AN NSANTO T6 RATA E113COG103J50V D un PRAGUE 1020103 050 PARTS LISTS Table 5 9 Telemetry PCB Assembly 3409061 page 4 of 4 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 31913P2 VOLT REG 9V T0 92 NATIONAL U11 LM78L09ACZ 32289 1 JUMPER SHORTING AMP 390088 2 5 27 PARTS LISTS Table 5 10 RS 232 Telemetry PCB Assembly 33525G1 Page 1 of 1 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 33527P1 PWB CAB RS232 TEL INTF ASC 2 SEE ENG SPEC 32082P18 CAPAC TANT 10MF 35V 10 DIPPED RADIAL SPRAGUE cl C2 199D106X9035BE2 58454P3 CAPAC CERM 01MF 50V 20 SPRAGUE C4 C5 C6 1C10ZU103M050B 44076P12 CAPAC CERM 47PF 200V 10 C7 C9 C10 C11 CK05BX470K 58053 2 DIODE 1 4148 REPLACES 0600 0026 NATL CR1 CR2 CR3 CR5 1N4148 33214 1 DIODE LED RED DIFFUSED T 1 3 4 HP DS1
49. 20B 33859P1 IC 14538B DUAL MONOSTBL PRECISION SMT 5016 150 OTOROLA Ul US C14538BDW 33772P2 LM393 DUAL COMPARATOR NATIONAL U10 SMT S08 150 LM3 93M 33864P09 Ic TTL LPS 74LS09 QUAD 2 INPUT POS ANGATE OTOROLA 011 SMT 5014 150 SN74LS09D 32878P1 IC 68302 SMT 132 OTOROLA U12 C68302FC16C 34245P13 IC PRGMD PER 34245 GAL16V8B M F 34290P1 U13 SEE ENG DWG 33854P32 IC ALSMOS 74ALS32 QUAD 2 INPUT POS ORGATE NATIONAL 014 SMT 5014 150 DM74ALS32M 33703P04 5 74 04 NATIONAL U15 SMT 5014 150 74 045 33854 08 IC ALSMOS 7441508 QUAD 2 INPUT AND GATE NATIONAL U16 SMT 5014 150 DM74ALS08M 33863P244 IC HCTMOS 74HCT244 OCTAL BUFFER LINE DRVR OTOROLA 017 018 019 024 SMT 5020 300 C74HCT244AD U39 33860P1 IC 29F800BB SMT TSOP48 AMD U2 AM29F800BB 90EC 33865P1 IC 88C681 SMT PLCC44 PHILLIPS U20 SCN2681TC1A44 34247P21 IC PRGMD PER 34247 GAL16V8D M F 33866 1 U21 SEE ENG DWG 34248P22 IC PRGMD PER 34248 GAL16V8D M F 33866 1 U22 SEE ENG DWG 33863P138 IC HCTMOS 74HCT138 3 TO 8 LINE DECODE DMUX OTOROLA U23 SMT 5016 150 C74HCT138AD 33863P245 IC HCTMOS 74HCT245 OCTAL BUS TRANSCVR OTOROLA U25 U38 SMT 5020 300 C74HCT245AD 33861P1 IC 68HC68T SMT SOIC16 300 OTOROLA U3 C68HC68T1DW 33868P1 IC 2598 VOLTAGE REG SMT NATIONAL U4 LM2598 5 0 33858P1 IC 128K X 8 STATIC RAM 100 NS HITACHI U6 U7 SMT SOL32 500 HM628128BLFP 10 31414P3 XSTR NTWK ULN 2803A 18P DIP DARLINGTON SPRAGUE 064 069 074 TESTED
50. 22 ol 02 THERMISTOR NTC 10K VARISTOR 3 JOULES RV1 RV2 POTEN 50K 5W 10 R20 R22 POTEN 10K 5W 10 R25 XFMR TELE T1 XFMR ISOLATION T2 IC LM339 VOLT COMP 7 El El TP1 COUPL HC XR2206 MONO FUN HC XR2211 FSK DEMO HC OP AMP QUAD 324 OP AMP 741 HC HCMOS 74HC125 HC HCMOS 74HC4051 C Hc ANAFADAWAWANWA H MCT6 DUAL OPTO U US CAPAC CERM C18 C19 C28 C29 C32 CAPAC CERM 01 5 C5 C6 C7 C8 C9 C14 C17 Hs 01 5 C20 OV 9 CR4 54 4 R24 CRMT QUAD C GEN D ISOL OV C22 C33 OV SECONDARY DESCRIPTION 10 oo REPLACES 0400 0097 500MW ZENER DIFFUSED T 1 3 4 HIGH EFFICIENCY RECT SCHOTTKY PWR W BOARD LOCKS 100 CTRS 100 CTRS 14CV 18V METAL OXIDE 25 TRN PC MTG 25 TRN PC MTG LOW POWER 8P DIP QUAD BUS BUFFER W 3 STATE OUTPUTS 8 CHANNEL ANALOG M ULTI PLEXER DE ULTIPLE XE 8P DIP 5 COG M 5 1 1 H H N 1 1 P 1 2 2 2 K 1 D B 3 B 3 P D m Lu E X F B X da 3 3 un S ih FGR PART PRAGUE 99D225X9025AE3 OTOROLA N5233B P LMP 3301 ATL N4148 OTOROLA N5817 ANDUIT 30 632 533B OLEX 2 03 2021 OLEX 2 03 203
51. 2P1 STUD SNAP IN 345L SLOTTED HD 1 4 TURN SOUTHCO 82 11 200 16 1 31144P1 IDENT PLATE CNTLR ECONOLITE SEE ENG DWG 34255G1 CHASSIS SUB ASSY 34259 1 1 3426061 DISPLAY PANEL ASC 2S DENS ITRON 3428561 ASSY PS INPUT HC4129BGHNGO345 N138P9008C SCRW SEMS 4 X PH SLT N238P9B HEX NUT LK WSHR 4 STL CAD 32542P20 FSTNR BAIL RING SOUTHCO 82 15 200 16 32542P103 WSHR WEAR CUP NYLON BLACK SOUTHCO 82 46 101 41 32542P106 SPRING RETAINER 1 4 TURN SOUTHCO 43 13 1 24 32542P100 RETAINER LOCK RING S STL NO 82 SOUTHCO 82 32 201 20 53048P15 TIE CABLE 4 DIA ST BLACK DENNISON 10 408 55399 21 GROMMET STRIP 062 099 PANDUIT GES99F A C 53048P12 TIE CABLE 75 DIA ST BLACK DENNISON 08 404 5 2 ECONOLITE P N 34240 34255G1 34259P2 34260G1 34250G2 32845G2 34280P1 N695P9006C N44P9005C N695P13004C 31348P51 34269 1 32542 1 31144 1 3428561 N138P9008C N238P9B 32542 32542 32542 32542 1 53048 1 55399 53048P1 P20 P103 P106 TEE PARTS LISTS Table 5 2 Controller Assembly ASC 2S 2000 34240G2 Page 1 of 1 PRIMARY DESC REF DESGN ASSY DWG 5 25 CHASSIS SUB ASSY ASSY PLATE CONN DISPLAY PANEL ASC 2S SECONDARY DESCRIPTION 5 25 2 5 25 D AD 5 25 342515 34253AW 256K RAM PCA PROCESSOR I O INTERFACE TYPE 2 PCA DATA MODULE ASC 2 POWER SUPP
52. 489 1489 1489 1489 1489 1489 1489 1489 1489 1489 1489 1489 1489 54 54 54 54 54 54 54 P306 P311 P316 P321 P336 P337 P361 P364 P373 P385 P389 P400 P405 P434 P435 P454 P353 P258 P275 P34 P35 P36 P38 P39 P40 1 Table 5 9 Telemetry PCB Assembly 3409061 page 2 of 4 PRIMARY D ES E N ES 5 AB Ej O1 Ed Awe H N A N SSS FJ Q i AAA os E N gt N w Hs o CRN CU T A CR ANB OC O N E N El pel ws 15 KO R5 16 19 VAR 30 33 5 9K 1K 5K 9K 6K R17 56 60 2K 4K ESC REF DE HM 1 8W 1 R11 R43 OHM 1 8W OHM 1 8W OHM 1 8W 1 8W 1 1 8W 1 OHM 1 8W OHM 1 8W 75K OHM 1 8W 1 SGN 1 1 1 1 1 100K OHM 1 8W 1 11 14 16 47 51 OK 3K 2K 5K 1K 1 8W 1 OHM 1 8W 1 1 8W 1 OHM 1 8W 1 1 8W 1 9 806K OHMS 1 8W 1 46 4K 1 8W 1 4 iis CAPAC C27 CAPAC C31 CAPAC C21 CAPAC 11 23 16 E13 CAPAC C10 R53 15K CER CER CER C24 CER CER CER C30 CER CER C15 OHM 1 8W 015MF 5 75 OHM 1 8W 1 1 OV
53. 5 Not Used P OO N PORT 3 FSK TELEMETRY PIN FUNCTION Vo Transmit 1 O Transmit 2 O Reserved Receive 1 2 Chassis Ground Reserved Reserved Chassis Ground OO OO OO N PORT 3 EIA 232 TELEMETRY PIN FUNCTION 1 0 DCD RXD TXD DTR GND DSR RTS NC NC OONOARWN APPENDIX B PIN LISTS 25 pin TELEMETRY CONNECTOR PIN FUNCTION 3 SYSTEM DETECTOR A1 2 SYSTEM DETECTOR A2 5 SYSTEM DETECTOR B1 19 SYSTEM DETECTOR B2 4 SYSTEM DETECTOR C1 1 SYSTEM DETECTOR C2 7 SYSTEM DETECTOR D1 8 SYSTEM DETECTOR D2 18 LOCAL FLASH 16 DOOR OPEN MAINTENANCE REQUIRED 14 SPARE 1 17 ALARM 1 21 ALARM 2 6 TLMSPARE 2 15 EXTERNAL ADDRESS ENABLE 20 CONFLICT FLASH 24 RECEIVE 1 25 RECEIVE 2 9 TLM SPECIAL FUNCTION 1 22 TLM SPECIAL FUNCTION 2 10 TLM SPECIAL FUNCTION 3 23 TLM SPECIAL FUNCTION 4 12 TRANSMIT 1 13 TRANSMIT 2 TYPE 1 POWER PIN FUNCTION Vo A AC Neutral B Not Used AC Line D Not Used Not Used F Fault Monitor O G Logic Ground O H Chassis Ground I Not Used J Not Used APPENDIX B PIN LISTS CONNECTOR 55 Pin Plug Type 22 55P PIN FUNCTION Fault Monitor 24 VDC External Voltage Monitor N1 Red N1 Don t Walk N2 Red N2 Don t Walk N2 Ped Clear N2 Walk Vehicle Detector 2 Ped Detector 2 Mode Input 2 Stop Time Ring 1 Inhibit Max Term Ring 1 External Start Interval
54. 505 MFGR PART MOTOROLA MC74HCT244AD AMD AM29F800BB 90EC P S HILLIPS CN2681TC1A44 DWG SEE ENG DWG OTOROLA C74HCT138AD OTOROLA C74HCT245AD OTOROLA C74HC259D OTOROLA C68HC68T1DW NATIONAL LM2598 5 0 OTOROLA C74HC251D HITACHI HM628128BLFP 10 SPRAGUE ULN2803A OTOROLA C7812CP AX214CWI LINEAR TECH LTC490CS8 OTOROLA MBZ15VDLT1 ONSANTO CT6 EPSON C 405 32 768K A2 EPSON 505 14 745 2 AAVID 576802B03100 AMP 531220 2 5 15 PARTS LISTS Table 5 6 Processor I O PCB Subassembly ASC 2S 2000 34250G2 Page 6 of 6 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION FGR PART 56671P41 STNDF SWAGE 4 X 125 25 DIA BRS NI UNICORP M2 M3 SS240 1 D 7 56671P4 STNDF SWAGE 4 4691 25 DIA BRS NI UNICORP XJ10 XJ11 XJ12 ss251 1 D 7 56671P42 STNDF SWAGE 4 X 250 25 DIA BRS NI UNICORP XJ13 XJ15 XJ17 SS244 1 D 7 56671P25 STNDF SWAGE 2 X 38L 16 DIA BRS NIC UNICORP XJ4 8130 1 D 7 N57P5006C SCRW 42 X 3 8 PH SLT STL CD MACH XJ4 N404P8C WSHR LK INT 2 STL CAD PLATED XJ4 33395P3 SPCR PCB LKING 38L 1 4 TURN PLASTIC HARTWELL 5 4 375 1 53048P12 TIE CABLE 75 DIA STD BLACK DENNISON 08 404 5 16 PARTS LISTS Table 5 7 Processor I O PCB Subassembly ASC 2S 2100 34250G3 Page 1 of 6
55. 6 to telemetry connector Set oscilloscope to 5 Volts Division and 1mSec Division Adjust R22 to produce a 1 700 15 Hz square wave on JP9 pin 2 This corresponds to ap proximately 5 8 horizontal divisions on the oscilloscope screen 58mS Remove jumper on JP8 and install it on JP9 Attach scope or frequency counter probe across R28 and R29 Go to the controllers telemetry diagnostic display Main Menu 9 6 Select 1 Mark Turn R25 all the way counter clockwise 35 turns max Then turn R25 clockwise until DS3 TD TLEV just turns fully on Set oscilloscope to 5 Volts Division and 2mSec Division Adjust R24 to produce a 1200 15 Hz sine wave This corresponds to approximately 4 2 horizontal divisions on the oscilloscope screen 83mS Go to the controllers telemetry diagnostic display Main Menu 9 6 Select 2 Space Set oscilloscope 5 Volts Division and 1mSec Division Adjust R23 to produce a 2200 15 Hz sine wave This corresponds to approximately 4 5 horizontal divisions on the oscilloscope screen 454mS Verify that the output is 2 2 6 2 volts peak to peak when DS3 is on Adjust R25 as nec essary Turn R20 all the way counter clockwise 35 turns max Then turn R20 8 turns clockwise This sets receiver gain to unity For field adjustment turn R20 clockwise to increase the re ceiver gain Verify that 054 CD 051 RDATA turn on when mark or space are selected on the controll
56. 8 CONN DIN 32S STR A SD PANDUIT 5 100 632 432 33745P2105 CAPAC 1MF 16V SMT 3216 20 TANT KEMET C9 C10 C25 T491A105M016AS 31769P61 TRANSORB P6KE27A 25 7 28 4V GEN INST CR22 CR23 6 27 31769 59 TRANSORB 6 6 8 600W UNIDIRECTIONAL MOTOROLA CR14 6 45 7 14V P6KE6 8A 31769P60 TRANSORB 6 600W UNIDIRECTIONAL MOTOROLA CR18 CR19 31 4 34 7V 6 5 18 ECONO PARTS LISTS Table 5 7 Processor I O PCB Subassembly 5 25 2100 3425063 Page of 6 P N 31535 344563 31535 338 779F 56668F 37129F 33730F 33730F 33872 33872 33872 54719 33872 33873 33873 33872 33873 33873 33872 33872 33872 33872 33873 54582 33825 33870F 1 31 P2 P103 P681 P331 P153 P000 P5491 P1302 P472 P2212 P1002 P105 P102 P221 P473 P9092 P5 P000 PRIMARY DESC REF DE WAFER 2 CKT J7 TP3 SGN J8 TP1 TP2 CONN CIRC 63P BOX MTG 9 WAFER 3 2 4 5 INDUCTOR POWER SMT L1 L2 51 01 5 250 DIODE LED BRIGHT RED 2N3904 NPN 51 02 5 R1 R27 R54 ES 680 5 LO ES 330 5 11 R16 g Hs 2222 Q3 10K 5 R6 R8 R32 R55 1 16W SMT R26 R40 R44 1 16W SMT 1 16W SMT R20 R45 R48 R51 R52
57. ADVANCED SYSTEM CONTROLLER ASC 2S MAINTENANCE MANUAL P N 37539 05 Copyright 1993 by Econolite Control Products Inc 010702 WARRANTY Econolite Control Products Inc warrants for a period as shown below from date of shipment all control equipment listed below to be free from defects in material or workmanship and to be of the kind and quality designated or specified in the contract This warranty does not extend to products not manufactured or sold by Econolite Econolite has the sole right to determine whether or not an item is covered under our warranty policy Controller Warranty Period ASC 2S Series Controller 2 years Econolite is not responsible for damage caused by negligence acts of God or use of equipment in a manner not originally intended Econolite s liability under this warranty shall not exceed the cost of correcting defects in the equipment Upon the expiration of the warranty period all such liability shall terminate To obtain service under this warranty deliver the product to the factory at the address listed be low When returning products to Econolite the following must be done Pack in original or equivalent shipping container Insure it or assume the risk of loss damage during shipment Obtain Return Authorization number from your sales representative Pay all shipping charges to factory Econolite will pay the return shipping charges List on packing sheet inside carton the return Authorization
58. APAC 10MF 35V ELECT SMT NEMCO CASE B NICHICON C31 UWX1V100MCR1GB 33740P5270 CAPAC 27PF 50V SMT 0805 COG CERAM URATA C43 GRM40COG270J050BD 33740P5330 CAPAC 33PF 50V SMT 0805 COG CERAM URATA C44 GRM40COG330J050BD 31884P4 CAP VARIABLE 7 50 SMT A TYPE URATA C5 TZBX4R500BA110 32895 P7 CAPAC 120MF 50V ELECT NICHICON C6 C7 UPL1H121MPH 33878P047 CAPAC 4 7MF 25V ELECT SMT NEMCO CASE B NICHICON C66 C67 C71 C72 UWX1E4R7MCR1GB C73 32169P19 CAPAC ELECT 18000MF 35V AL SNAP MTG NICHICON C76 LK1V183MHSC 31769P61 TRANSORB 6 27 25 7 28 4V GEN INST 6 27 33870 1 DIODE FDLL4148 SMT D035 NATIONAL CR2 CR12 CR13 FDLL4148 For Parts lists 34250G1 34250G2 and 34250G3 the following note applies One 8 MB of flash PROM U2 can be replaced by installing two 4 MB flash PROMs in locations U2 and U92 The following parts must also be installed C78 C79 C80 R82 R83 and U93 33748P5103 CAPAC 01 50V AVX C18 CT9 06035C103KAT2A 33748P5471 CAPAC 470PF 50V MURATA ERIE C80 GRM3 9X7R47K050B 33872P122 RES 1 2K 5 1 16W DALE R82 R83 CRCW0603122J 33901P1 IC 29F400BB FLASH 4 MB AMD U2 U92 AM29F400BB 90EC 33902P32 IC 74VHC32 SMT S014 FAIRCHILD 993 74VHC32MTC 5 6 ECONO PARTS LISTS Table 5 5 PCB Subassembly ASC 2S 1000 3425061 Page 2 of 5 P N 58064 32416F 33831F 33831F 58873 55205 55205 32183F 31912F 57255 32758
59. BRO520LT1 33831P3 DIODE MRB340 34V SCHOTTKY SMT CASE 403 OTOROLA CR4 CR6 CR7 CR8 BRS340TS CR10 58873P29 DIODE 1N5232B 5 6V 5 500MW ZENER OTOROLA CR9 REPLACES 58052P6 1 5232 55205 17 FUSE 3 4 250 S B 1 25 X 425 ITTELFUSE F1 313 750 55205P19 FUSE 1A 250V 3AG S B 3 1250425 ITTELFUSE F2 313001 32183P4 FUSE HLDR W CARRIER SOLDER TERM SCHURTER 1 XF2 FEU031 1659 31912 1 SPCR NYL 50ID X 760D 18 THK 3 AG F HLDR SEASTROM 1 XF2 5606 44 177 57255P700 WIRE 22AWG BLK 19 STRD TYPE B N 600V XF1 XF2 SEE ENG SPEC 32758P1 INDUCTOR FERRITE BEAD TDK FB1 FB2 FB3 FB4 BF45 4002 31058P4 CONN CIRC 61S BOX MTG D SLDR CONT MIL C 26482 CANNON J10 02 24 615 SPCL 31058P3 CONN CIRC 55S BOX MTG D SLDR CONT MIL C 26482 CANNON 211 02 22555 SPCL 31058 2 CONN CIRC 55P BOX MTG D SLDR CONT MIL C 26482 CANNON J12 KPTO2E22 55PDV 31369P27 CONN D SUB 25S W W ETAL SHELL CINCH J13 DBKL 25SUT 31369P28 CONN D SUB 25P W W ETAL SHELL CINCH 14 DBKL 25PUTI 31369P26 CONN D SUB 15S W W ETAL SHELL CINCH J15 DAKL 15SUT 31369P25 CONN D SUB 9P ETAL SHELL CINCH J17 DEKL 09PUTI 58751P32 HDR 3 CKT LKG STRGHT 156 CTRS W LOCK GOLD OLEX J18 26 61 4030 58751P14 WAFER POLARIZING 5 CKT 156 CTRS W LOCK AMP J19 640388 5 33852P68 CONN 68 PIN STRAIGHT 050 PITCH MOLEX J2 15 92 1468 32158P113 HDR 13 26 CTR POL STR 100 CTRS W SHORT LATCH HIROSE J3 HIF3BAG 26PA 2 54DSA 32219 1 CONN DIN 32P R A W W 512L PANDUIT J4 100 632 051 32219P
60. Backed Clock oscillator requires careful adjustment This MUST be done in the lab NOT in the field Required Test Equipment Frequency counter oscilloscope 1 Verify that the battery jumper is in the ON top position 2 Allow controller and test equipment to warm up for approximately 10 minutes This is an important step in achieving an accurate adjustment 3 Connect the oscilloscope frequency counter to the top terminal of Y1 4 Monitor the oscilloscope and set waveform for maximum amplitude by adjusting ca pacitor C5 Adjust the clock using a non metallic adjustment tool 5 Verify frequency is set to 32 768 kHz 2 Hz and remove test equipment 3 12 MAINTENANCE Diagnostics Menu Inputs ADJUSTMENTS AND TEST Diagnostics Menu Several diagnostic functions are included in the standard release controller software These functions are accessed by selecting the DIAGNOSTICS 9 menu item from the MAIN MENU The DIAGNOSTICS menu includes functions for testing INPUTS 1 OUTPUTS 2 DISPLAY 3 KEYBOARD 4 OVERLAP PROGRAM 5 TELEMETRY 6 and LOOPBACK 7 Follow ing is a description of each test function and how to perform the test ASC 2 MAIN DIAGNOSTICS SUBMENU CONFIGURATION 6 DETE RS INPUTS 5 OVERLAP PROGRAM CONTROLLER 7 STATUS DISPLAY OUTPUTS 6 TELEMETRY COORDINATOR 8 UTILITIES DISPLAY 7 LOOPBACK PREEMPTOR DIAGNOSTICS KEYBOARD
61. CWO603102J DALE CRCWO603221J DALE CRCWO603473J DALE EB EB DALE CRCW06039092F A BRADLEY 1505 NAT CRCW080500J TIONAL FD 14148 5 19 PARTS LISTS Table 5 7 Processor I O PCB Subassembly ASC 2S 2100 34250G3 Page 4 of 6 ECONOLITE P N 33872P271 33872P101 33872P112 33872P122 33873P5112 33711P000 33873P6813 337132222 33875 241 33872P222 33875P102 33872P753 33872P183 43654P2 33872P152 33872P121 33873P4993 31263P97 33873P1003 43577P3 32876P1 43577P26 31770P1 5 20 PRIMARY DESC REF DESG ES E w 5 Ww 51 amp Fl co FI 270 5 1 16W SMT 100 5 R42 1 1K 5 1 16W SMT R47 1 16W SMT 1 2K 5 R41 51 1K 1 R5 1 16W SMT ZERO OHM JUMPER S Wn Bj Ed d ER s nd N o Ha N N w N E El lt A R60 681K 1 1 16W SMT 2 2K 5 1 2W SMT 240 5 R58 2 2K 5 1W SMT 1 16W SMT 1K 55 1W SMT 75K 5 1 16W SMT 18K 5 1 16W SMT 2 2 OHMS 5W R67 1 5K 5 1 16W SMT R70 R71 R73 120 5 1 16W SMT R72 499K 15 1 16W SMT 10K 3W 5 W W m muc uuum mmu DH DDD DDD ion J iod 0000000000 00000000000 El El T gt P39 VARI RV1 R75 100K 1 1 16W SMT R15 R18 ES NTWK 10K COM PIN 1 RP2 RP5 RP6 7 RP8 R
62. DS2 DS3 HIGH EFFICIENCY HLMP 3301 32099P1 XSTR NPN 2N2222 MOTOROLA ol 2N2222 54719P41 RES 470 OHM 1 4W 5 MIL R 11F FIXED COMP R2 R3 R4 R5 RCO7GF471J 31283P105 IC TTL 1488 QUAD LINE DRVR NATIONAL 01 DS1488N 31283P106 TTL 1489 QUAD LINE RCVR NATIONAL U2 DS1489N 32219P16 CONN DIN 32S R A W BD LK PANDUIT J1 2 PER 100 632 533 32740 1 SWITCH 6PDT PC DIP ALCO swl ASF62 31535P2 WAFER 3 CKT 100 CTRS MOLEX JP1 JP2 JP3 JP4 22 03 2031 56829P4 HNDLE PCB 1 25L HDW MTG BIVAR CP 3 54552P5 RIVET 3 32 X 34L O HD AL POP CHERRY REPLACES 40418P100 AAP 34 N402P3C WSHR FL 2 NAR STL CAD PLATED 32289P1 JUMPER SHORTING AMP 390088 2 54719P90 RES 51K 1 4W 5 MIL R 11F FIXED COMP R1 R7 R8 RCO7GF513J 54719P57 RES 2 2K 1 4W 5 MIL R 11F FIXED COMP R6 RCO7GF222J 5 28 PARTS LISTS Table 5 11 Data Module PCB Assembly 32845G2 Page 1 of 1 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 32847 DATA MOD ASC 2 C SD C32846S 32848AW SEE ENG SPEC 32082 1 CAPAC TANT 1MF 35V 10 DIPPED RADIAL SPRAGUE el 199D105X9035AE3 58454P3 CAPAC CERM 01MF 50V 20 SPRAGUE C2 1C102U103M050B 32219P7 CONN DIN 32P STR A SD PANDUIT DMP6 100 632 133 32849 1 EEPROM 28C256 256K X 8 BIT ELECTRIC ATMEL ul ERASABLE PROM 90 200 5 AT28C256 20PC 31260P5 SOCKET 28P IC MACH CONT AUTO INSERT ROB NUGENT ICE 286 SD2 TG
63. DURE The ASC 2S should be installed in a location where the front panel is easily accessible Adequate room should be left around the controller to allow easy removal if necessary Care should be taken to install the controller so that vents on the back side are not blocked Before applying AC power perform the following pre installation checks 1 Open the front panel door remove the plug in data module and verify that the number on the EEPROM label matches the program number on the controller label located on the top surface of the unit Reseat the data module 2 Verify that all modules are properly secured and that all connector ribbon cables are in place Once these preliminary steps have been taken the controller is ready for operation Required cable connector part numbers are listed below Refer to Appendix B for the connector pin lists 3 2 CONNECTOR CABLE ASSIGNMENT CONNECTOR CABLE A B CRIMP SOCKET SDLC PORT1 TERMINAL PORT2 TELEMETRY PORT3 TELEMETRY EXPIO 3 3 CONNECTOR MS 3116 22 55S MS 3116 22 55P MS 3116 24 61P AMP 205842 1 DAU 15P CANNON DBC25P DEU 9S CANNON DBC25S MAINTENANCE CONNECTOR CABLE ASSIGNMENT ECONOLITE PART NUMBER 44143 1 44143 2 44143P3 31163P2 31163P4 54665P4 54665P7 54647P9 54647P6 MAINTENANCE ENVIRONMENTAL REQUIREMENTS AND STORAGE ENVIRONMENTAL REQUIREMENTS The ASC 2S meets or exceeds the NEMA environmental standards for traffic control eq
64. ET signal NORESET 4 2 B clears all data from the latches at power on The Q outputs of each latch are applied to a high current high voltage Darlington transistor output driver ULN2803A Logic level transition to 24V FALSE and 0 V TRUE occurs at the driver outputs Output lines are connected to interface connectors A B C and D The ULN2803 output drivers are protected from transients on their output pins by Transient Voltage Suppressors CR16 and CR19 P6KE33A 13 3 C 19 3 C These provide the output devices with a low impedance path to ground for voltages greater than 33VDC This prevents damage to a driver by the reverse voltage generated when a relay coil connected to the output is de energized or other transient occurs The FLASH LOGIC OUT output on A1 X 14 3 A is derived from the Q4 output of latch U62 74HC259 14 6 B When this output is active output driver 078 ULN2803A sinks current from A1 X through diode CR15 When U78 is off Q2 MMBT2222ALT 1 14 4 A is turned on and current is sourced to A1 X through the current sourcing circuit consisting of transistor Q2 diodes CR17 CR20 and current limit resistors R57 R58 This output can source 50mA maxi mum and can sink 200mA maximum Diode CR20 shunts any negative voltages on the output to ground CR17 shunts any voltage greater than 33VDC to ground On the ASC 2S 2100 the PREEMPT CMU INTERLOCK output associated with U27 pin 5 19 5 B is active only if there is a pr
65. F 33857F 31369 31369 31369 58751 58 ESTE 33852F 32158 32219F 32219F 31535F 31535F 33879F 56668F 37129F 33730 33872 P12 P29 P17 P19 P27 P26 P25 P32 P2 P103 PRIMARY DESC REF DESGN DIODE 1N4763A CR24 DIODE BRIDGE 1A 800V CR25 DIODE 0520 20V 1 2A CR3 CRS CR11 DIODE MRB34 34V CR4 CR6 CR7 CR8 CR10 DIODE 1N5232B 5 6V 5 CR9 FUSE 3 4A 250V 3AG S B Fl FUSE 1A 250V 3AG S B 3 F2 FUSE HLDR W CARRIER 1 XF2 SPCR NYL 50ID X 760D XF1 XF2 WIRE 22AWG BLK 19 STRD 1 XF2 INDUCTOR FERRITE BEAD FB1 FB2 FB3 FB4 CONN 10P PCMT J16 CONN D SUB 25S W W J13 CONN D SUB 15S W W J15 CONN D SUB 9P 17 HDR 3 CKT LKG STRGHT J18 WAFER POLARIZING 5 CKT J19 CONN 68 PIN STRAIGHT J2 HDR 13 26 CTR POL STR J3 CONN DIN 32P R A J4 CONN DIN 32S STR 5 WAFER 2 J7 J8 TP1 TP2 TP3 WAFER 3 CKT JP2 JP3 JP4 5 INDUCTOR POWER SMT 1 CHOKE HASH 250MH L2 DIODE LED BRIGHT RED XSTR 2N3904 NPN Ql RES 10K 5 1 16W SMT R1 R6 R8 R26 R27 R32 RAO R44 R55 SECO 1W ZE 4 PI SCHO SCHO 500M NDARY Dl NER N DIP TTKY SMT TTKY SMT W ZENER REPLAC 14 25 12 25 SOLDE X 425 X 25 R TERM 18 T
66. F800BB FLASH 8 MB U2 IC 88C681 U20 IC PRGMD PER 34247 U21 IC PRGMD PER 34248 U22 IC HCTMOS 74HCT138 U23 IC HCTMOS 74HCT245 U25 U38 IC HCMOS 74HC259 U31 U32 U33 U34 U35 U36 U37 044 045 046 061 062 68 68 3 2598 VOLTAGE REG HC C 4 C HCMOS 74HC251 051 052 053 054 055 056 058 060 128 8 STATIC RAM 06 U7 XSTR NTWK ULN 2803A 064 067 068 069 070 071 072 973 U74 075 076 077 078 VOLT REG 12V U79 IC MAX214 U80 Ic 490 RS 485 XMTR 081 082 MMBZ15VDLT1 083 084 085 086 087 088 089 090 6 DUAL ISOL 091 XTAL 32 768 2 1 XTAL 14 7456MHZ Y2 HEATSINK PLUG IN TO 220 XU79 JUMPER SHORTING XJP2 XJP3 XJP4 XJ7 XJ8 5 5 5 5 5 G G 029 0 T un oio ECONDARY DESCRIPTION CTAL BUFFER LINE 5020 300 DRVR T TSOP48 T PLCC44 AL16V8D M F 33866P1 AL16V8D M F 33866 1 TO 8 LINE DECODE DMUX T 5016 150 CTAL BUS TRANSCVR T 5020 300 BIT ADDRESSABLE 5016 150 501 16 300 m OF 8 DATA SEL MPLEX 5016 150 00 5 SOL32 500 8P DIP DARLINGTON ESTED REPLD 0900 0132 220 1 AMP UAD RS 232 XMTR RCVR 5028 300 508 150 50 23 T MC 405 T MA
67. HK 3 AG ESCRIPTION CASE 403 CASE 403 ES 58052P6 F HLDR TYPE B N 600V CIRC ULAR SHELL SHELL SHELL 156 156 050 100 W W A SD 100 100 DO33 SMT GENE CTRS W l CTRS W l PITCH LOCK GOLD LOCK CTRS W SHORT LATCH 512L CTRS CTRS 16 SOT23 RAL PURPOSE 0603 FGR PART OTOROLA 1N4763A DIODES INC DB106 OR DFO8 OTOROLA BR0520LT1 OTOROLA BRS340TS OTOROLA 1N5232B ITTELFUSE 313750 ITTELFUSE 313001 SCHURTER FEU031 1659 SEASTROM 5606 44 177 SEE ENG SPEC TDK BF45 4002 ITT CANNON CA2 4252 2599 CINCH DBKL 25SUT CINCH DAKL 15SUT CINCH DEKL 09PUTI MOLEX 26 61 4030 AMP 640388 5 OLEX 15 92 1 HIROSE HIF3BAG 26PA 2 54DSA PANDUIT 100 632 051 PANDUIT 100 632 432 OLEX 22 03 2021 468 OLEX 22 03 2031 COILCRAFT DO3316P 104 JW MILLER 5254 GEN INST MV5752 ZETEX FMMT3904 NDA DALE CRCW0603103T 5 7 PARTS LISTS Table 5 5 PCB Subassembly ASC 2S 1000 3425061 Page 3 of 5 ECONOLI
68. INPUT OUTPUT FUNCTIONS Function Preempt 1 Preempt 3 Vehicle Detector 9 Vehicle Detector 10 Vehicle Detector 13 Vehicle Detector 14 Vehicle Detector 15 Vehicle Detector 16 Vehicle Detector 11 Vehicle Detector 12 Vehicle Detector 17 Vehicle Detector 18 Vehicle Detector 19 Vehicle Detector 20 Alarm 1 Alarm 2 Dimming Enable Local Flash Status Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3 Address Bit 4 MMU Flash Status Outputs Pin A DD A e B s B e C N C CC C NN C GG B A B C B t B f C M C DD C PP C HH A u A d B r B K C k C BB Function Preempt 1 Status Preempt 3 Status TBC Auxiliary 1 TBC Auxiliary 2 Timing Plan A Timing Plan B Offset 1 Offset 2 Preempt 2 Status Preempt 4 Status Preempt 5 Status Preempt 6 Status Offset 3 Timing Plan C Timing Plan D Reserved Free Coord Status Automatic Flash TBC Auxiliary 3 Reserved System Special Function 1 System Special Function 2 C MMSystem Special Function 3 C FF System Special Function 4 B 5 APPENDIX B PIN LISTS MODE 2 ADDRESS BIT ASSIGNMENT EXTERNAL ADDRESS ADDRESS BITS 10 DOD 12 13 14 15 16 17 18 19 20 21 22 23 24 Oororororororororororororo OOOO v 0000 v O0o0o00 o oooooooocr 7700000000 oO0o000000000000009 cr FALSE 24 VOR OPEN 1 TRUE 0 V OR GROUND 0 B 6 APPENDI
69. KEYS 1 6 TO SELECT 3 16 MAINTENANCE Diagnostics Menu Keyboard Overlap ADJUSTMENTS AND TEST Keyboard 4 This function tests all front panel keys Perform the following steps Select KEYBOARD 4 from the DIAGNOSTICS SUBMENU When this is selected the control ler beeps and displays a message saying that it will go into flash when this test is started 1 When the KEYBOARD DIAGNOSTICS screen is first displayed the user is prompted to push the 0 key Push this key and verify that the number 0 is displayed in the proper position on the keyboard diagram shown on the LCD The user is then prompted to push the next key Continue for all twenty five keys Ifa key is not pressed within twenty seconds or a key is pressed out of sequence the test will fail Push SUB MENU to exit this test Please note There are no user serviceable parts on the User Interface module If it has been determined that a display problem is caused by the module please return it to Econolite Overlap 5 This test is used to verify proper reading of the optional overlap card which can be installed on the optional Expansion I O module Perform the following steps 1 Select OVERLAP 5 from the DIAGNOSTICS SUBMENU 2 Verify that the displayed X s correspond to the jumpers inserted on the overlap card Push SUB MENU F3 to exit this test If this test uncovers an Overlap card failure use the detailed description of the I O section of the Processor
70. LITE P N 33859P1 33772P2 33864P09 32878P1 34245P13 33854P32 33703P04 33854P08 33863P244 33860P1 33865 1 34247 21 34248P22 33863P138 33863P245 33862P259 33861P1 33868P1 33862P251 33858P1 31414P3 40029P4 PRIMARY DESC REF DESGN 13 ALSMOS 74ALS32 14 5 74 04 15 ALSMOS 74ALS08 16 IC HCTMOS 74HCT244 017 018 019 024 030 039 057 059 29F800BB FLASH 8 02 88 681 020 PRGMD PER 34247 021 PRGMD PER 34248 022 5 74HCT138 023 5 74 245 025 038 HCMOS 74 259 026 027 028 029 031 032 033 034 035 036 037 044 045 046 061 062 68 68 3 ET CU C HC 2598 VOLTAGE REG HC C 4 C HCMOS 74HC251 40 041 042 043 47 048 049 050 5 052 053 054 55 056 058 060 128K 8 STATIC RAM 6 5 6 6 7 7 7 07 NTWK ULN 2803A 064 065 066 068 069 070 072 073 074 076 077 078 iT 12V 1 9 C UI H lt IC 14538B DUAL MONOSTBL ul US LM393 U10 TTL LPS 74LS09 011 68302 012 PRGMD PER 34245 SECONDARY DESCRIPTION PRECISION SMT 5016 150 DUAL SMT QUAD 2 INPUT POS ANGATE SMT SMT GALI m UAD 2 INPUT POS ORGATE COMPARATOR 508
71. LY SCRW SEMS 4 X 3 8 SCRW 4 X 5 16 FIL SLT SCRW SEMS 6 X 1 4 BLOCK LATCHING 2 PC PKG RESTRAINT STUD SNAP IN CABLE 3451 IDENT PLATE CNTLR C C ASSY PS AC INPUT SCRW SEMS 4 X PH SLT HEX NUT LK WSHR 4 STL CAD FSTNR BAIL RING WSHR WEAR CUP SPRING RETAINER RETAINER RING TIE CABLE 4 DIA ST GROMMET STRIP TIE CABLE 75 DIA ST W EPROM 32K X 8 110VAC 50 60H2 PH PHIL STL CD MACH PH PHIL ASC 2S A MD SLOTTED HD 1 4 TURN ECONOLITE NYLON BLACK 1 4 TURN S STL NO 82 BLACK 062 099 THK BLACK MFGR PART DENSITRON HC4129BGHNG0345 POWER ONE MAP42 S204 745286 2 SOUTHCO 82 11 200 16 1 ENG DWG 8 OUTHCO 2 15 200 16 OUTHCO 2 46 101 41 OUTHCO 3 13 1 24 OUTHCO 2 32 201 20 ENNISON 0 408 ANDUIT ES99F A C 8 ENNISON 404 5 3 PARTS LISTS Table 5 3 Controller Assembly ASC 2S 2100 34240G3 Page 1 of 1 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY D ESCRIPTION MFGR PA
72. N S STL NO 82 BLACK 062 099 MFGR PART DENSITRON HC4129BGHNG0345 POWER ONE MAP42 S204 AMP 745286 2 CANNON D110277 SOUTHCO 82 11 200 16 1 SEE ENG DWG SOUTHCO 82 15 200 16 SOUTHCO 82 46 101 41 SOUTHCO 43 13 1 24 SOUTHCO 82 32 201 20 DENNISON 10 408 PANDUIT GES99F A C DE 08 ENNISON 404 5 5 PARTS LISTS Table 5 5 Subassembly ASC 2S 1000 34250G1 Page 1 of 5 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 34250 ASSEMBLY DRAWING PROCESSOR 1 0 34251 SCHEMATIC PROCESSOR 1 0 34253 MASTER ARTWORK PROCESSOR 1 0 34254 TEST SPEC PROCESSOR 1 0 34252 1 PCB PROCESSOR I O 5 25 32911 21 BTRY 3V MTG LITHIUM PANASONIC Bl VL2330 1VC 33748P5103 CAPAC 01MF 50V SMT 0603 10 X7R CERM AVX CL C4 C8 06035C103KAT2A CIS C14 C15 C16 CI C18 C19 C20 C21 C22 C23 C24 C26 C27 C28 C32 C33 C34 C35 C36 C37 C38 C45 C46 C47 C48 C75 33740P5220 CAPAC 22 50V SMT 0805 COG CERAM MURATA C12 GRM40COG220J050BD 33741P5104 CAPAC 1MF 50V SMT 1206 10 X7R CERM KEMET C2 611 C68 C1206C104K5RAC 33877P105 CAPAC 1MF 35V TANT SMT 3528 SPRAGUE C29 293D105X9035B2T 33878P10 C
73. No Econo lite s Sales Order No your Purchase Order No equipment serial No description of problem with equipment and date of installation Ship to the nearest Econolite Service Department Econolite Control Products Inc or Econolite Control Products Inc Attn Service Department Attn Service Department 3360 E La Palma 446 Third Street Suite 3 Anaheim California 92806 Neptune Beach Florida 32266 Table of Contents SECTION E M 1 1 INTRODUCTION pr 1 1 ASGI2S EAMIEY iiber ERROR RM t 1 1 MANUALS a DERE eere ee ha pp aS Sh Cath e 1 3 Programming Manuals ee as 1 3 Maintenance Manual 8 1 3 kldeqjeplmu 2 1 THEORY Basis ERR 2 1 FUNCTIONAL DESCRIPTION A 2 1 Processor Modules deed ed ert ahnt e 2 3 YO Interface Modules uuu tre roter teet rrt eti ad ad 2 4 Power Supply Module 2 4 Telemetry Module ne taste 2 Transceiver eee ennemis 2 5 Processor Module Schematic document number 34251 pages 1 20 2 10 D illeiejo fole tol 2 10 Mos gt lati iio eins s 2 10 System Control Pin
74. P9 RP1 11 RP25 RP26 P28 RP29 RP30 P32 RP33 RP34 OGIC LEVEL TRANS P12 RP13 RP14 P16 RP17 RP18 P20 RP21 RP22 P24 RP35 RP36 ES NTWK 10K COM PIN P3 RP4 RP37 RP STOR 55 JOULES RV2 RV3 1 16W SMT MT 0 RP27 RP31 RP15 RP19 RP23 38 S 0 0 0 0 0 603 603 603 603 603 ECONDARY DESCRIPTION THICK FILM 1206 0 603 THICK FILM 2010 2 0 2 0 0 W 0 0 0 R 0 512 603 512 603 603 IRE 603 603 603 WOUND EPLAC ES 0500 0039 603 10 PIN SIP 9 RES 1W 2 R EPLAC ES 0500 0213 SURFACE MTG CUSTOM 5020 300 10 9 RES MOLDED 212V 255V ETAL OXIDE UL CSA RECOGNIZED FGR PART DALE CRCWO63271J DALE 06031010 DALE 06031120 DALE CRCW06031227 DALE CRCW06035112F KOA SPEER RM7322BT DALE CRCW06036813F DALE CRCW2010222J DALE CRCW2512241J DALE CRCWO603222J DALE CRCW2512102J DALE CRCW0O603753J DALE CRCW0603183J OHMITE 95J2R2 DALE CRCW0603152J DALE 06031210 DALE CRCW06034993F DALE CW2C 14 10K 5 DALE CRCW06031003F BOURNS 4610 101 103 SPRAGUE 820C110N187 BOURNS 4310R 101 103 HARRIS V150LA20B PARTS LISTS Table 5 7 Processor I O PCB Subassembly ASC 2S 2100 3425063 Page 5 of 6 ECONO
75. PP N7 Phase Next APPENDIX B PIN LISTS INTERFACE CONNECTORS CONNECTOR D PIN FUNCTION 25 SYSTEM COMMAND CYCLE BIT 1 INPUT 35 SYSTEM COMMAND CYCLE BIT 2 INPUT 6 SYSTEM COMMAND CYCLE BIT INPUT 12 SYSTEM COMMAND OFFSET 1 INPUT EXTERNAL ADDRESS BIT 0 10 SYSTEM COMMAND OFFSET BIT 2 INPUT EXTERNAL ADDRESS BIT 1 36 SYSTEM COMMAND OFFSET BIT 3 INPUT EXTERNAL ADDRESS BIT 2 16 SYSTEM COMMAND SPLIT BIT 1 INPUT EXTERNAL ADDRESS BIT 3 9 SYSTEM COMMAND SPLIT BIT 2 INPUT EXTERNAL ADDRESS BIT 4 4 SYSTEM COMMAND COORD SYNC INPUT 26 COORD FREE 60 REMOTE FLASH 3 SPLIT DEMAND 38 DUAL COORD 14 TIME RESET 20 TEST INPUT 37 TEST INPUT D 19 TEST INPUT E 57 PREEMPTOR CALL 1 49 PREEMPTOR CALL 2 50 CALL 3 BUS PREEMPTOR 1 55 PREEMPTOR CALL 4 BUS PREEMPTOR 2 56 PREEMPTOR CALL 5 BUS PREEMPTOR 3 61 CALL 6 BUS PREEMPTOR 4 58 CMU STOP TIME CONFLICT FLASH 17 EXPANDED DETECTOR 1 47 EXPANDED DETECTOR 2 31 EXPANDED DETECTOR 3 18 EXPANDED DETECTOR 4 30 EXPANDED DETECTOR 5 39 EXPANDED DETECTOR 6 40 EXPANDED DETECTOR 7 13 EXPANDED DETECTOR 8 NOTE Priority preemptors 1 amp 2 will respond to any NEMA defined input that is applied to Preemptor Call input 1 amp 2 respectively Priority preemptors 3 6 will respond to any NEMA defined input that is applied for at least 0 8 seconds to Preemptor Call inputs 3 6 respectively Bus Preemptors 1 4 will respond to a pul
76. Preempt 5 Detector N3 Walk N3 Don t Walk N4 Green N4 Yellow N4 Walk Mode Output 4 Mode Output 12 Mode Input 12 Mode Input 4 Mode Input 3 Mode Input 19 Mode Input 22 Mode Input 23 Mode Input 24 Overlap A Yellow Overlap A Red Mode Output 19 Mode Output 3 Mode Output 11 Overlap D Red Preempt 6 Detector Overlap D Green Mode Input 20 Free No Coord Max Il Selection Ring 2 Overlap A Green pH Seu qo nece T TEC Xxz cuomuzzrAc crommoour BB Overlap B Yellow CC Overlap B Red DD Overlap C Red EE Overlap D Yellow FF Overlap C Green GG Overlap B Green HH Overlap C Yellow Type 2 Modes CONNECTOR C 61 Pin Socket Type 24 61S PIN FUNCTION Status Bit A Ring 2 Status Bit B Ring 2 N8 Don t Walk N8 Red N7 Yellow N7 Red N6 Red 5 Red 5 Yellow 5 Ped Clear NS Don t Walk Mode Output 13 Mode Output 5 Vehicle Detector 5 Ped Detector 5 Vehicle Detector 6 Ped Detector 6 Ped Detector 7 Vehicle Detector 7 Ped Detector 8 Mode Input 8 Force Off Ring 2 Stop Time Ring 2 Inhibit Max Term Ring 2 Test C Status Bit C Ring 2 N8 Walk N8 Yellow N7 Green N6 Green N6 Yellow N5 Green N5 Walk Mode Output 21 Mode Input 5 Mode Input 13 Mode Input 6 Mode Input 14 Mode Input 15 Mode Input 16 Vehicle Detector 8 Red Rest Mode Ring 2 Omit Red Clear Ring 2 N8 Ped Clear N8 Green N7 Don t Walk N6 Don t Walk AA N6 Ped Clear BB Mode Output 22 CC Mode Outpu
77. ROM programming if programming equipment available otherwise contact Econolite for another configuration EEPROM Controller hangs up after a certain condition 1 Program memory failed Watch dog timer timed 1 A Remove replace Processor module occurs out B Use displayed message to localize problem Check program memory and program memory circuit operation Controller hangs up and PROCESSOR MONITOR Processor failed 1 A Remove replace Processor module LED LED1 is ON Power supply failed B Check processor operation 1 A Remove replace power supply B Check power supply for low voltage output Characters are lost while printing 1 XON XOFF handshake protocol not 1 Program printer to recognize XON XOFF recognized protocol SECTION 5 PARTS LISTS The parts list is divided into tables as shown Parts are listed with both Econolite and manufacturer s part numbers and primary and secondary descriptions All components of the ASC 2S controller are listed including software Only one supplier part number is given however qualified equivalent parts as determined by Econolite may be used When ordering controller software always specify the latest software version and part number Table 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 CAUTION HC and HCT CMOS parts are NOT interchangeable When changing parts be careful to replace with the same type of part Title Controller Ass
78. RT 34240 ASSY DWG ASC 2S 34255G1 CHASSIS SUB ASSY 5 25 34259 3 ASSY PLATE CONN TYPE 2 EXP ASC 2S D AD 34260G1 DISPLAY PANEL ASC 2S DENSITRON HC4129BGHNG0345 3428561 ASSY PS INPUT INTERNAL CABLE ASC 2S 34285G2 C C ASSY P S DC OUTPUT INTERNAL CABLE ASC 2S 34250G3 PCA PROCESSOR I O INTF CONTROLLER TYPE 2 EXP 5 25 32845G2 PCA DATA MODULE ASC 2 W EPROM 32K X 8 34280P1 POWER SUPPLY 110VAC 50 60HZ POWER ONE MAP42 S204 N695P9006C SCRW SEMS 4 X 3 8 PH PHIL N695P13008C SCRW SEMS 6 X 1 2 PH PHIL N44P9005C SCRW 44 X 5 16 FIL SLT STL CD MACH N695P13004C SCRW SEMS 46 X 1 4 PH PHIL 31348P51 BLOCK LATCHING 2 PC PKG AMP 745286 2 31348 12 LATCH SPRING 1 SET PER PKG CANNON D110277 34269P1 RESTRAINT CABLE ASC 2S A MD 32542P1 STUD SNAP IN 345L SLOTTED HD 1 4 TURN SOUTHCO 82 11 200 16 1 31144P1 IDENT PLATE CNTLR ECONOLITE SEE ENG DWG N138P9008C SCRW SEMS 4 X PH SLT N238P9B HEX NUT LK WSHR 4 STL CAD 32542P20 FSTNR BAIL RING SOUTHCO 82 15 200 16 32542P103 WSHR WEAR CUP NYLON BLACK SOUTHCO 82 46 101 41 32542P106 SPRING RETAINER 1 4 TURN SOUTHCO 43 13 1 24 32542P100 RETAINER LOCK RING S STL NO 82 SOUTHCO 82 32 201 20 53048P15 TIE CABLE 4 DIA ST BLACK DENNISON 10 408 55399P1 GROMMET STRIP 062 099 THK PANDUIT GES99F A C 53048P12 TIE CABLE 75 DIA ST BLACK DENNISON 08 404 5 4 PARTS LISTS Table 5 4 Controller Assembly ASC 2S 2100 with OLAP 34240G4 Page 1 of 1 ECONOLITE P N 34240 34255G1 34259 3
79. RY OF OPERATION DETAILED DESCRIPTION This section contains detailed descriptions of the various ASC 2S modules Each module is de scribed in detail with references to schematics the format D N X Y where D is the docu ment number N is the schematic page X is the horizontal coordinate and Y is the vertical coordinate of the page The document number D is not always provided in this format but it is normally referenced at the beginning of each new section Part numbers are identified in paren thesis immediately before references to schematic coordinates Example U24 74HCT244 4 2 C Pin and signal names are also printed in bold type The schematics are found in Section VI of this manual Also a module block diagram is shown before the discussion of each module These block diagrams illustrate general functional opera tion 2 6 2 7 Figure 2 2 Processor Section Block Diagram 2 8 Figure 2 3 Section Block Diagram 2 9 Figure 2 4 Processor l O Module Component Placement Processor Module THEORY OF OPERATION Microprocessor Clocks System Control Pins DETAILED DESCRIPTION Processor Module Schematic document number 34251 pages 1 20 Microprocessor The ASC 2S family of controllers uses the Motorola MC68302 integrated multiprotocol proces sor This is a Very Large Scale Integration VLSI CMOS device which includes a 16 bit 68000 core processor a system integration block and a RISC communicatio
80. SC 2S 2100 it includes type D and 25 pin Telemetry connectors and associated input multiplexers logic level translators output latches and output drivers External parallel inputs and outputs are processed as mentioned above plug in NEMA overlap programming card optional is connected to the input multiplexers by connector J6 When programmed the overlap inputs are read by the processor in the same way as external inputs Power Supply Module The Power Supply module is a 40 watt 24 volt off line switching supply set for 120VAC opera tion When configured as ASC 2S 2000 ASC 2S 2100 controller input power is applied through the A connector on the controller front panel and then routed via the AC line transient protection circuit to J19 on the I O module A wire harness connects between J19 and the power supply module When used in the ASC 2S 1000 controller input power is applied through MS connector J16 on the front panel and then routed to the power supply module as mentioned above The 24VDC output from the supply is routed back to the Processor l O module via a wire harness connected to J18 THEORY OF OPERATION Telemetry Module Transceiver Operation FUNCTIONAL DESCRIPTION Telemetry Module The Telemetry module operates as a transceiver providing communication between the ASC 2S 1000 ASC 2S 2000 or ASC 2S 2100 and an ASC 2M 1000 or KMC 10000 master controller The module is controlled by the Processor module and interface
81. STP FRC INH RST TIM OFF MAX RED STP FRC INH RST TIM OFF PED MAX OMT PED MAX OMT REC 2 AR REC 2 AR INPUT DIAGNOSTIC CONNECTOR D CYC CYC CORD OFT OFT OFT REM 1 2 3 FREE 1 2 3 FLSH X X X X SPLT SPLT DUAL SPLT PMT PMT TIME 1 2 CORD DMD 1 2 RESET PMT 3 4 5 6 3 14 Diagnostics Menu Inputs INPUT DIAGNOSTIC CONNECTORS A B amp C PHASE 123 4 5 6 7 8 VEH DETECTOR PED DETECTOR HOLD PHASE OMIT PED OMIT INPUT DIAGNOSTIC CONNECTORS A B amp C MIN WRST CNA CNA TEST TEST TEST REC MOD 1 2 A B C INT NCON LAMP EXT MODE ADV EN OFF STRT A B C PMT PMT PMT PMT CORD 2 4 5 6 FREE INPUT DIAGNOSTIC TELEMETRY CONNECTOR LOC MAIN ALRM ALRM CMU EXTD FLSH REQD 1 2 FLSH ADDR SP SP2 SYSTEM DETECTORS 3 4 5 6 MAINTENANCE Diagnostics Menu Outputs ADJUSTMENTS AND TEST Outputs 2 This test allows for manual activation of each output to connectors A B and C when the control ler is connected to a suitcase tester Perform the following steps 1 Attach controller to a suitcase tester 2 Select OUTPUTS 2 from the DIAGNOSTICS SUBMENU When this is selected the controller beeps and displays a message saying that it will go into flash when this test is started 3 When the OUTPUT DIAGNOSTIC screen is displayed the cursor will be in the PHASE 1 RED position Push the TOGGLE 0 key several times Notice that the PHASE 1 RED LED on the suitcase tester is turned o
82. TA GRM40C0G220J050BD SMT 1206 10 X7R CERM KEMET C1206C104K5RAC SMT 3528 SPRAGUE 293D105X9035B2T SMT NEMCO CASE B NICHICON UWX1V100MCR1GB SMT 0805 COG CERAM URATA GRM40C0G270J050BD SMT 0805 COG CERAM URATA GRM40C0G330J050BD SMT A TYPE URATA TZBX4R500BA110 NICHICON UPL1H121MPH SMT NEMCO CASE B NICHICON UWX1E4R7MCR1GB AL SNAP MTG NICHICON LLK1V183MHSC The following parts must also be installed and 34250G3 the following note applies C78 C79 C80 R82 AVX 0603 MURA GRM3 DALE CRCW AMD AM29 FAIR 74VH can be replaced by installing two 4 MB flash PROMs in locations R83 and U93 5C103KAT2A TA ERIE 9X7R47K050B 0603122J F400BB 90EC CHILD C32MTC 5 17 PARTS LISTS Table 5 7 Processor I O PCB Subassembly 5 25 2100 3425063 Page 2 of 6 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION FGR PART 58064P12 DIODE 1N4763A 1W ZENER OTOROLA CR24 1N4763A 32416P6 DIODE BRIDGE 1A 800V 4 PIN DIP DIODES INC CR25 DB106 OR DFO8 33831P4 DIODE 0520 20 1 2A SCHOTTKY SMT CASE 403 OTOROLA CR3 CRS CR11
83. TE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 33872P681 RES 680 5 1 16W SMT 0603 DALE R10 06036810 33872 000 RESOOHM 5 1 6W SMT0603 DALE R81 CRCWO603000J 33872P331 RES 330 5 1 16W SMT 0603 DALE R11 R16 R20 R45 06033310 R46 R48 R51 R52 54719P153 RES 22 MEG 1 4W 5 MIL R 11F FIXED COMP R12 RC07GF226J 33873P5491 RES 5 49K 1 1 16W SMT 0603 DALE R14 CRCW06035491F 33873P1302 RES 13K 1 1 16W SMT 0603 DALE R17 CRCW06031302F 33872P472 RES 4 7K 1 16W SMT 0603 DALE R19 R30 CRCW06034727 33873P2212 RES 22 1K 1 1 16W SMT 0603 DALE R2 CRCW0602212F 33873P1002 RES 10K 1 1 16W SMT 0603 DALE R22 R76 R77 R78 R79 CRCW06031002F 33872P105 RES 1M 5 1 16W SMT 0603 DALE R23 R25 CRCWO603105J 33872P102 RES 1K 5 1 16W SMT 0603 DALE R24 06031020 33872P221 RES 220 5 1 16W SMT 0603 DALE R28 06032210 33872 473 RES 47K 5 1 16W SMT 0603 DALE R29 R34 06034730 33873 9092 RES 90 9 1 1 16W SMT 0603 DALE R3 CRCW06039092F 54582P5 RES 15 OHMS 1 2W 5 FIXED COMP A BRADLEY R31 EB1505 33825P000 RES ZERO OHM JUMPER THICK FILM 0805 DALE R35 CRCWO80500J 33872P271 RES 270 5 1 16W SMT 0603 DALE R36 CRCWO63271J 33872P101 RES 100 5 1 16W SMT 0603 DALE R37 R42 R47 06031010 33872P112 RES 1 1K 55 1 16W SMT 0603 DALE R38 06031120 33872 122 RES 1 2K 5 1 16W SMT 0603 DALE R39 R41 R82 R83 CRCW06031227 33873P5112 RES 51 1K 1 1 16W SMT 0603 DALE R4 R5 CRCW06035112F 33711P
84. X C SYSTEM INTERCONNECTION A master transceiver can be interconnected with a number of local transceivers to make up a system If a leased line is used for interconnection up to 19 local transceivers be con nected If customer owned twisted pair lines are used up to 24 local transceivers can be con nected Each transmitter output is essentially an open circuit unless it is ON Each receiver input impedance is 15 kilohms The system is interconnected by one or two data channels implying either one or two Telemetry modules at the master For each channel the master transmitter outputs are connected to a wire pair designated as the command line which is connected to all local receiver inputs The master receiver inputs and all local transmitter outputs are connected to another wire pair designated as the readback line Transient protection on these lines is achieved with a Telemetry Interface Board TIB or a Communications Transient Suppressor CTS installed in the cabinets between each transceiver and the communication lines C 1 APPENDIX D GUIDE TO LEASE LINE INSTALLATION Telephone Companies offer several types of networks designed for lease line service This guide is intended to assist Econolite system users and their local telephone company with in stallation of the proper data transmission lines required for Econolite systems Econolite recommends the Broadcast Polling Multipoint Method as a cost effective and reli able mean
85. Yellow N2 Green N2 Check N2 Phase On Vehicle Detector 1 Ped Detector 1 N1 Hold Force Off Ring 1 Ext Min Recall Manual Control Enable Call To Non Actuated Test A AC Control Mode Bit A Status Bit B Ring 1 N1 Green N1 Walk N1 Check N2 Ped Omit Omit All Red Clear Ring1 Red Rest Ring 1 Mode Bit B Call To Non Actuated II TestB BB Walk Rest Modifier CC Status Bit A Ring 1 DD N1 Phase EE N1 Ped Omit Ped Recycle Ring 1 GG Max ll Selection Ring 1 HH I O Mode Bit C lt NXXZ cHdO0mNJUuUzZzzr c crommoour yo II I I I I 1 I I APPENDIX B PIN LISTS INTERFACE CONNECTORS CONNECTOR B 55 Pin Socket Type 22 55S PIN FUNCTION 1 Phase Next Preempt 2 Detector N2 Phase Next N3 Green N3 Yellow N3 Red N4 Red N4 Ped Clear N4 Don t Walk N4 Check Vehicle Detector 4 Ped Detector 4 Vehicle Detector 3 Ped Detector 3 N3 Phase Omit N2 Phase Omit N5 Ped Omit N1 Phase Omit Ped Recycle Ring 2 Preempt 4 Detector Preempt 5 Detector N3 Walk N3 Ped Clear N3 Don t Walk N4 Green N4 Yellow N4 Walk N4 Phase On N4 Phase Next N4 Phase Omit N4 Hold N3 Ho
86. able The display will reflect the pass or fail condition If test fails check signals at RS 485 transceiver chips 081 and 82 in the I O section Refer to detailed descriptions of Processor I O module and document 34251 MAINTENANCE ADJUSTMENTS AND TEST Diagnostics Menu Memory Tests Memory Tests The ASC 2S does not require keyboard entered memory testing All memory tests are per formed automatically as follows During power on the controller does a preliminary check of all memory components All system RAM chips are completely checked for read write integrity A check sum test is performed on each EPROM pair and program compatibility checks are performed A cyclic redundancy check CRC is performed on the data module EEPROM If any of these tests fail an appropriate message is displayed and the program goes into a continuous loop with the voltage monitor ON which forces the intersection into flash After start up checks are performed the controller enters the main program While the main program is running a CRC is continuously run in background on both the EPROMS and EEPROM If either of these tests fail an appropriate message is displayed and the program goes into a continuous loop with the voltage monitor ON which forces the intersection into flash 3 20 SECTION 4 TROUBLESHOOTING The fault isolation tables in this section list malfunctions and their possible causes The list is by no means complete but careful study of the s
87. age PREEMPTOR Submenu 1 A Remove replace Processor I O Interface module B Check output circuit operation for the particular output 2 A Replace EEPROM with correct program B Reprogram EEPROM in order to correct phase omitted 1 Check fuse F1 2 A Remove replace Processor I O module B Check PIOSL decode circuit operation U21 4 4 C Check I O module buffers U24 and 025 4 2 B D 3 Check output latch chip select decoder operation U22 10 6 D 1 A Remove replace Processor l O module B Check output latch and output driver for that phase 1 A Remove replace module Check I O decoder U23 12 6 D 2 A Remove replace Processor I O module B Check PIOSL decode circuit operation U21 4 4 B Check I O buffers 024 and U25 4 3 B D 4 3 TROUBLESHOOTING HARDWARE FAULT ISOLATION All inputs to one phase or one input inoperative 1 I O Interface section failure Input multiplexer 1 A Remove replace module failed B Check input multiplexer operation for that particular phase 2 Phase not IN USE 2 Program phase IN USE on Recall data page Controller Submenu No inputs or outputs from a phase 1 Phase not IN USE 1 Check Recall data page Controller Submenu keyboard inputs failed 6 A D Econolite for repair Phase sequencing problem 1 Incorrect configuration EEPROM installed 1 A Remove replace Data Module B Check configuration EEP
88. am data for each overlap phase A D is output by the multiplexers as eight bits representing the eight controller phases N1 N8 The overlap inputs are read by the proces sor at the multiplexer output pins as described above 2 23 THEORY OF OPERATION Parallel I O Interface DETAILED DESCRIPTION Output Latches Output Latches Output latches are used to interface data from the system data bus with external control output lines The processor controls the data transfer by enabling the latches and addressing the out put thus latching the data from the data bus to be sent to external equipment In this way it controls twelve addressable 8 bit output latches U31 U32 U33 U34 U35 U36 U37 U44 U45 U46 U61 and U62 74HC259 13 14 1 6 A D with associated output drivers U67 U68 U69 U70 U71 U72 U73 U74 U75 U76 U77 and U78 ULN2803A on an ASC 2S 2000 In addition the ASC 2S 2100 also includes latches U26 U29 19 1 6 A D and associated output drivers U63 U66 All output drivers are biased to the 24 V FALSE state when not asserted through a 10K pull up resistor Latches are addressed by bits A1 A3 and enabled by the and LE1 signals from the I O device selector U23 12 6 D At the same time data bits DBO DB7 are input to the addressed latches Data is latched on the rising edges of the enable signals and remains latched until changed dur ing a data update from the processor which occurs every 100 ms The buffered RES
89. ction is performed by 025 74HCT245 4 4 0 Unbuffered data signals are labeled D n and buffered signals are labeled BD n Buffering to the User Interface panel is performed by U38 74HCT245 10 5 C Unbuffered data signals are labeled D n and buffered signals are labeled FPD n Address Bus A1 A23 Pins A1 A23 2 3 D form a 24 bit address bus when combined with the LDS and UDS pins 2 3 B The address bus is a bi directional three state bus capable of addressing 16M bytes of data On the ASC 2S address lines A21 A23 are not used All address lines are buffered be fore being routed to the various I O circuits Buffering to the parallel I O section is performed by U24 74HCT244 4 2 C Unbuffered address signals are labeled A n and buffered signals are labeled BA n Buffering for the User Interface panel is performed by U39 74HCT244 10 5 B Buffered address signals are labeled FPA n Control Bus This is a multipurpose bus that includes all the Processor l O modules chip select write enable and output enable signals These signals are used to control communications with the various RAM and EPROM devices parallel I O devices the data module and the User Interface mod ule The control bus signals are generated by the decode and control section These signals will be explained when their associated circuitry is discussed Telemetry Bus This bus contains the serial data and hand shaking signals which are routed to the Telemetr
90. e address bus A1 A15 When the processor does a word read or write access both odd and even chips within the bank are enabled simultaneously Data Module The Data module is mounted on the Processor I O module The module is connected by J5 6 5 C CAUTION Do not remove or insert data module with power applied to controller 2 16 THEORY OF OPERATION Processor Module Memory Voltage Monitor Control DETAILED DESCRIPTION EEPROM Memory All user entered data is stored on the data module The ASC 2S comes standard with a 32K x 8 250 nanosecond Electrically Erasable Programmable Read Only Memory EEPROM installed on its data module During a write cycle the address and data are latched internally and the cycle is automatically completed by the EEPROM The write cycle takes a maximum of 10 milli seconds during which the chip cannot be accessed The EEPROM is accessed using three wait states This is set using the processors internal wait state generator associated with the master EEPROM chip select signal CS2 The processor writes to EEPROM when the EEPROM chip enable signal CS2 is low the odd output enable signal OEO is HIGH and the write enable signal CSWE is LOW When the EEPROM chip enable signal CS2 and the odd output enable signal OEO are LOW and the write enable signal CSWE is HIGH the EEPROM supplies the data bus 00 07 with the data stored in the location specified by address bus A1 A14 The processor
91. ed U3 uses a combination of VCC and battery B1 8 5 C voltage to operate The processor communicates with U3 over the SPI bus When power is reapplied the processor reads the time from U3 and updates its internal RTC time Local Voltage Regulators Switching regulator U4 LM2598 5 0 3 5 B converts the incoming 24VDC into the 5VDC VCC signal used throughout the module U4 also generates the PWRGOOD signal used by the reset circuit and GR W generation Diode CR11 protects other circuits in the event of a short between U4 2 24VDC and U4 3 Transient voltage suppressor CR1 P6KE27A 3 6 B pro tects the input from any transients greater than about 30VDC Linear regulator U79 LM7812 7 3 D provides a high current short circuit protected 12VDC source for use by the telemetry module and external fiber optic modems 2 18 Processor Module THEORY OF OPERATION Back up Power Supply Display DETAILED DESCRIPTION Back Up Power Supply The back up power supply provides power to the RAM and the battery backed clock during a power failure With power applied the VCC power supply provides power to the battery backed real time clock 68HC68T 8 5 D and the RAM chips via transistor Q1 MMBT3904ALT1 8 5 B As long as VCC is greater than 4 74VDC PWRGOOD will be high and Q1 will turn on When power is removed Q1 turns off and diode CR3 conducts thus supplying power from the lithium battery 1 8 5 C Jumper JP2 disconnects the batt
92. eemption requirement The circuit consists of Q3 MMBT2222ALT 19 3 C R62 CR16 and CR24 If a preemption sequence is not programmed this output is forced LOW This output can be connected to the conflict monitor 24 V monitor input to set the intersection to flash if a required preempt sequence is not programmed The voltage monitor VMC and fault monitor FLTMN signals generated by U11 8 1 C detect out of tolerance voltage levels and processor failures and send control signals to the I O section to be output as VOLTAGE MONITOR and FAULT MONITOR The VMC signal is inverted and buffered by U78 ULN2803A 14 5 B and routed to A1 C The FLTMN signal is inverted and buffered by U74A ULN2803A 14 3 C and routed to J16 F 2 24 Parallel I O Interface THEORY OF OPERATION SDLC Interface Terminal Interface DETAILED DESCRIPTION SDLC EIA 485 Interface The SDLC interface circuit sends and receives its signals on the SDLC bus All TTL to EIA 485 signal level translation is provided by U81 and U82 LT690 7 6 C These contain one EIA 485 driver and EIA 485 receiver each After the signals are translated to EIA 485 they are routed to the outside world via connector J15 DA15S 7 4 D The interface includes the following sig nals TXD and TXD are the differential transmit data pair The processor transmits this serial data signal as TXD3 from SCC3 2 5 C This signal is converted to a differential pair by U81 It is then output on c
93. embly ASC 2S 1000 34240G1 E Controller Assembly ASC 2S 2000 34240G2 E Controller Assembly ASC 2S 2100 34240G3 F Controller Assembly ASC 2S 2100 with OLAP 32420G4 F Processor l O Subassembly ASC 2S 1000 34250G1 J Processor I O PCB Subassembly ASC 2S 2000 34250G2 J Processor I O PCB Subassembly ASC 2S 2100 34250G3 K Processor I O PCB Subassembly ASC 2S 2100 Exp W Olap 34250G4 A Telemetry PCB Assembly 34090G1 G RS 232 Telemetry PCB Assembly 33525G1 F Data Module PCB Assembly 32845G2 A 5 1 PARTS LISTS Table 5 1 Controller Assembly ASC 2S 1000 34240G1 Page 1 of 1 ECONOLITE P N PRIMARY DESC REF DESGN SECONDARY DESCRIPTION MFGR PART 34240 55 DWG 5 25 34285G2 C C ASSY P S DC OUTPUT INTERNAL CABLE ASC 2S 3425061 PROCESSOR I O INTF CONTROLLER TYPE 1 32845G2 PCA DATA MODULE ASC 2 W EPROM 32K X 8 34280 1 POWER SUPPLY 110VAC 50 60HZ POWER ONE MAP42 S204 N695P9008C SCRW SEMS 4 X 1 2 PH PHIL N695P9006C SCRW SEMS 4 X 3 8 PH PHIL N44P9005C SCRW 44 X 5 16 FIL SLT STL CD MACH N695P13004C SCRW SEMS 46 X 1 4 PH PHIL 31348P51 BLOCK LATCHING 2 PC PKG AMP 745286 2 34269P1 RESTRAINT CABLE ASC 2S A MD 3254
94. er menu Go to the controllers telemetry diagnostic display Main Menu 9 6 Select 3 Modem Verify that DS2 VDATA blinks briefly at start of test Verify that Telemetry Data Test Passed message is displayed at end of test 3 10 MAINTENANCE Modem Check ADJUSTMENTS AND TEST 1 Install module in test controller Attach telemetry Master cable to Port 3 2 Set proper telemetry channel 3 If controller is attached to an ASC 2M set telemetry response delay on controller to 8800 Set ASC 2M TELEMETRY WINDOW to 80 If controller is attached to a KMC 10 000 set telemetry response delay to 10 000 4 Verify that controller communicates with master Set jumper JP5 to the DSC position Verify that controller communicates with master Page 1 of 2 7 Verify that jumpers are set according to the following table before shipment 1 4W JP2 4W JP3 4W JP4 2W O JP5 DSC JP6 4W JP7 FE JP8 NOT INSTALLED JP9 INSTALLED rommoouw 27 Remove test equipment 28 If the controller is to be stored set the battery jumper to the OFF position MAINTENANCE ADJUSTMENTS AND TEST Crystal adjustment Crystal Adjustment Procedure Replacement of any Battery Backed Clock oscillator circuit components U3 R12 C5 C12 1 8 4 D requires a crystal adjustment Before the controller is put back in service the following adjustment procedure should be completed CAUTION Setting the Battery
95. ery during troubling shooting or pe riods of extended storage B1 is a rechargeable lithium battery and uses resistors R36 R38 and diode CR13 as the charging circuit Battery voltage is monitored by comparator circuit 010 LM393 3 4 A When battery voltage drops below 2 2 VDC the comparator triggers causing output signal LOBAT to go low thus signaling the processor that the battery is not recharging properly and replacement is required Display The User Interface module contains a Liquid Crystal Display LCD formatted as 16 lines of 40 characters the display contrast control the display backlight circuit the display heater circuit the keyboard matrix and the system buzzer The display contains its own control and drive electronics and appears as two registers to the processor The display is connected to the processor module via User Interface connector J3 Please note The User interface panel should be sent to Econolite for repair Display Interface The processor uses its Independent Direct Memory Access IDMA channel to write to the dis play When a screen update is required the program fills a RAM buffer with screen data The program then initializes and activates the IDMA channel The IDMA transfers one byte at a time from the buffer to transceiver 038 74HCT245 10 5 C 000 007 When FPSEL 10 6 C is low R W is low the data is transferred to the User Interface module data bus and routed to the LCD modules data
96. essor and address lines A17 A19 IKEYSEL is active for the address range ECO000 EDFFFF LCDSEL 10 5 D is the LCD module select line This signal is generated by 022 GAL 16V8 10 5 D by combining the system I O enable signal CS3 from the processor and address lines A17 A19 LCDSEL is routed to the User Interface module connector J3 10 5 A LCDSEL is active for the address range E80000 E9FFFF LCDEN is the LCD module enable line This signal is generated by U22 GAL16V8 10 5 D by stretching LCDSEL by one system clock period and then ANDing this signal with LDS LCDEN is routed to the User Interface module connector J3 10 5 A 2 14 THEORY OF OPERATION Processor Module Interrupt Sources External Internal DETAILED DESCRIPTION External Interrupt Sources An interrupt signal causes the processor to stop normal program execution and go to an ad dress that is the beginning of an interrupt service routine Executing the routine provides what ever action is necessary to service the device generating the interrupt IRQ41 2 5 B is a signal which requests service by the real time clock interrupt routine This AC line referenced 120Hz square wave signal is generated by U1B 14538 8 5 A in conjunc tion with optoisolator U91 20 2 C This routine controls timing of all controller software activity and provides real time clock updates NRQ6 2 3 A is an active LOW open drain signal generated by U20 SCN2681 4 5 B durin
97. exers Input multiplexers interface external control inputs from connectors A B C and D with the sys tem data bus The processor controls the multiplexer functions by enabling the multiplexer ad dressing the inputs and reading the input status In this way it controls the 16 HCMOS tri state 8 bit multiplexers U51 052 053 U54 U55 056 058 and 060 74HC251 14 15 1 6 A D on the ASC 2S 2000 plus U40 U41 U42 U43 U47 U48 U49 U50 on the ASC 2S 2100 Each multiplexer receives eight external control inputs from a corresponding logic level transla tor Each control input has a unique address associated with it When the input is addressed and the multiplexer is enabled the input status ON OFF is routed to a single data bit at the multiplexer output pin W connected to the data bus The processor reads the input data by addressing it through the I O Interface address bus BA1 The selected input is gated onto the I O data bus by the LOW state of signal or 1 01 The processor simultaneously reads eight I O data bits from 8 different multiplexors onto BDO BD7 Typical input operation is described below The signal from input pin A1 h PHASE 1 HOLD 15 4 D is applied via logic level translator RP22 15 4 D to input DO pin 4 of input multiplexer U58 Coded address bits BA1 BA3 from the address bus are applied to address select inputs 50 S1 and S2 pins 11 10 and 9 of in put multiplexer U29 When address li
98. for device to device handshaking In addition to correct cable and jumper connections the TERMINAL PORT page of the CONFIGURATION submenu must be correctly programmed before data transfer occurs The following NULL MODEM cable diagrams are provided for reference only The cables are constructed to mate with the terminal interface on the I O Interface modules Figures A 1 and A 2 represent configurations for ASC 2 to ASC 2 communication Figure A 2 illustrates the minimum cable for both controller to controller and controller to printer communication Figure A 3 illustrates the minimum cable to attach an ASC 2 to a laptop with a DB 9 connector CONTROLLER TO CONTROLLER CONTROLLER TO CONTROLLER CABLE DIAGRAM CABLE DIAGRAM MINIMUM CABLE DB25P DB25P DB25P DB9S CONNECTOR CONNECTOR CONNECTOR CONNECTOR PORT2 PORT2 PORT2 2 3 2 2 3 2 3 3 7 7 7 5 FIGURE A 1 FIGURE A 2 1 CONNECTOR A 55 Pin Plug Type 22 55P PIN FUNCTION Fault Monitor 24 VDC External Voltage Monitor N1 Red N1 Don t Walk N2 Red N2 Don t Walk N2 Ped Clear N2 Walk Vehicle Detector 2 Ped Detector 2 N2 Hold Stop Time Ring 1 Inhibit Max Term Ring 1 External Start Interval Advance Indicator Lamp Control AC Common Chassis Ground Logic Ground Flashing Logic Out Status Bit C Ring1 N1 Yellow N1 Ped Clear N2
99. g telemetry transmissions IIRQ4F 2 5 B interrupt is used to shut down the controller in the event of a power failure IRQAF is one of the highest priority interrupts thus causing the processor to take immediate ac tion for an orderly controller shut down IRQ4F is generated by the missing pulse detector cir cuit U1A 14538 8 4 A The missing pulse detector is used to detect a loss of 120 Hz pulses It is a re triggerable one shot with a period of approximately 22 milliseconds Positive transi tions of OPTO1 from 091 20 2 C are cleaned up by U1B then fed to U1A This signal retrig gers the one shot every 8 33 milliseconds and also produces the IRQ41 signal During a power failure the one shot will not be retriggered and will time out causing an IRQ4F interrupt Also if the power supply output voltage is out of tolerance VM24 will go LOW thus forcing an IRQ4F interrupt Internal Interrupt Sources The 68302 processor contains 16 on board sources which can generate interrupts The ASC 2 controller family uses the following interrupts SCC1 SCC3 and Timers 1 2 The receive chan nel of SCC1 which is used for the telemetry channel is set up to generate an interrupt when 1 The controllers address is recognized on the telemetry line 2 After the block of data has been received and 3 When the checksum has been received The receive channel of SCC2 which is used for the terminal interface generates an interrupt when 1 An XON or
100. he dual asynchronous receiver transmitter DUART chips and their associated interface chips The Processor l O module is connected to the power supply module via connectors J18 J19 The power supply provides 24VDC Auxiliary processor functions include a watchdog timer which checks for proper program opera tion the voltage monitor which checks for power fail conditions and the battery backed clock circuit which keeps accurate time when power is removed from the unit System RAM is pow ered by the rechargeable backup battery circuit so that data integrity is maintained during power fail conditions Also included on the module are the AC line transient protection circuit and line referenced 120Hz interrupt generator The I O interface section connects external inputs and outputs with the microprocessor system address data and serial communications busses This allows the microprocessor to perform all input and output functions 2 3 THEORY OF OPERATION FUNCTIONAL DESCRIPTION Interface Module Power Supply Module Interface Modules The section of the 1 module consists of input multiplexers logic level transla tors output latches output drivers serial communications interface circuits the telemetry mod ule interface connector J4 and expansion I O connector J1 unused External parallel inputs are applied through front panel connectors A B and C The input volt age levels are tran
101. he block diagrams are included in this section and schematics are located in Section VI As an aid to finding circuitry described in the detail text schematic zone references which con tain the schematic coordinates of the circuitry are included in the text where pertinent A sche matic zone reference has the format D N X Y where D is the optional document number N is the schematic page X is the horizontal coordinate and Y is the vertical coordinate of the page The document number is normally referenced at the beginning of each new section Also all part numbers pin and signal names are printed in bold type 2 1 2 2 Figure 2 1 ASC 2S System Block Diagram THEORY OF OPERATION Processor Module FUNCTIONAL DESCRIPTION Processor Module The Processor l O module contains the microprocessor chip memory chips and support cir cuitry required to operate and control ASC 2S functions This module also includes all I O circuitry and controls the User Interface module keyboard and display operations Ribbon con nector J3 connects this module to the User Interface module The system busses include the address bus that identifies the device or memory location tar geted for information exchange the data bus which carries the information and the control bus which synchronizes the data transfers The communications busses include the Telemetry bus SDLC bus and Terminal bus which transfer serial data between the microprocessor and t
102. ices listed above connected to the local transceiver The addressed local controller sends an appropriate response to the master on the readback line Transmission of commands and readbacks occurs simultaneously An error status is gen erated if a readback is not received by the master within a predefined period For more informa tion on master controller operation using telemetry refer to the ASC 2M 1000 or KMC 10 000 Master Programming and Maintenance Manuals At the local transceiver modulated command message signals are transformer coupled to the receiver where they are filtered and demodulated to a serial bit pattern The serial bit pattern is converted by an SCC receive channel on the microprocessor into a parallel pattern four word command message which is read by the microprocessor If the message address corresponds to that of the local transceiver and if the message is valid the microprocessor performs the op eration specified by the message type Where readbacks are required the local transceiver generates a three word readback message containing the requested data and horizontal parity word The three data words from the microprocessor are converted to a serial bit pattern by a transmit channel on the DUART The serial bit pattern is then sent to the MODEM which pro vides frequency shift key FSK modulation for transmission Valid data transmit and received carrier LEDs are ON or flash during normal data transmission 2 5 THEO
103. ime the pull up resistor R14 3 4 A at the output of U7C has no pull up voltage thus the output of U7C is low Because of this the level of the TXDA line is used by U2 to select between Mark and Space voltages At the end of the message RTSA goes high turning on the soft carrier voltage During this time C20 charges through R26 an 8mS time constant After 8mS the threshold voltage of the com parator is exceeded and its output goes low thus turning off the softcarrier voltage R24 3 2 C sets the 1200Hz voltage R23 3 2 B sets the 2200 Hz voltage and R6 sets the 900Hz SCTO voltage When the input voltage to U3 pin 8 changes the frequency output by U3 pin 2 varies R25 3 2 D is the transmitter output level adjust 2 28 Modulator Transmitter Circuit THEORY OF OPERATION Receive Filter And Demodulator Circuit DETAILED DESCRIPTION Opto couplers U4A and U4B gate the analog signal from the FSK modulator according to the level 2 U6 acts as a temperature compensated output buffer with gain Opto cou plers U5A and U5B allow the output stage to be permanently enabled with a 600 ohm load or gated by MDCTL2 U7 Q1 DS3 and associated components are the output level comparator circuit that is used for measurement of the output level and transmit level indication When U5 is ON the FSK output signal is coupled through transformer T1 T2104 4 5 A to transmitter terminations XMIT and XMIT Transformer T1 R28 R29 RV2 CR3 and
104. in conjunction with APPENDIX F document 34251 and the detailed description of the section to determine the cause of failure Attach the 33279G4 loop back cable to the D connector Select EXPANDED I O 2 This tests the parallel I O lines on the Expansion I O module D connector Input and output circuitry including input multiplexers logic level translators output latches and output drivers are exercised The display will output a hexadecimal code corre sponding to any I O loop failure Use this code in conjunction with Appendix F document 34251 and the detailed description of the I O section to determine the cause of failure Attach the 33279G8 loop back cable to the Terminal port PORT 2 Select TERMINAL 3 This starts a test that transmits ASCII characters through the RS 232 level translator chip and exercises the RS 232 hand shake lines The signal is routed back to the translator chips receiver via the loop back cable The display will reflect the pass or fail condition If test fails check signals at RS 232 transceiver chip 080 in the I O section and DUART 20 in the processor section Refer to the detailed descriptions of the Processor I O module and document 34251 Attach the 33279G7 loop back cable to the SDLC port PORT 2 Select SDLC 3 This starts a test that transmits SDLC frames of ASCII characters through the RS 485 level translator chips The signal is routed back to the translator receivers via the loop back c
105. inal Equipment Impedance Isolation To Ground Breakdown Voltage Channel Requirements D 2 Voice Grade Broadcast Polling Multipoint 20 Points or 4 000 Facility Miles DC Voltage shall not be present on the line between tip and ring or tip ring and ground Maximum Transmitted 0 dBm 3 second average 13 dBm instantaneous Received 16 dBm 1 dB No more than 4 dB long term 12 dB to 20 dB No more than 3 dB short term 600 S 10 resistive over the voiceband and balanced At least 50 kS AC 300 3000 Hz At least 1500 VRMS at 60 Hz Two channels minimum 1 transmit 1 receive This is equiva lent to one Econolite telemetry channel For systems larger than 10 intersection controllers Econolite recommends the use of two telemetry channels four leased lines to ensure full data communi cations within 1 second APPENDIX D GUIDE TO LEASE LINE INSTALLATION ECONOLITE TELEMETRY MODULE MODEM SPECIFICATIONS TRANSMITTER CHARACTERISTICS Transmitter Digital to F SK modulator Output Level 0 dBm 15 into a 600 S load adjustable to 6 dBm Transmit Frequencies 2200 Hz represents a digital LOW 1200 Hz represents a digital HIGH Frequency Stability 1 Hz over the operating temperature range RECEIVER CHARACTERISTICS Receiver FSK to digital demodulator Signal To Noise 10 dB or greater In band Signal To 60 Hz Noise Greater than 50 dB at an input signal level of 50 mV Receiver Sensitivity 34 dBm Receiver Frequency 220
106. ing a power failure This battery is rechargeable and should not require replacement during the life of the controller However if a battery requires replacement please observe the following precautions IMPORTANT SAFETY INFORMATION Lithium cells or batteries are very high energy power sources and therefore must be handled with care Please observe the following precautions Do not short battery terminals Cells and batteries contain high energy If they are short circuited or heat up immediately disconnect from load using JP2 8 5 C Do not open puncture or crush batteries Cells and batteries contain sulphur dioxide and flammable material Dispose of properly Do not incinerate Cells and batteries can be disposed of in sanitary land fills Discharged lithium cells and batteries may contain significant amounts of unused energy and should be handled carefully They should be packed for disposal and electrically isolated Do not compact for disposal 3 9 MAINTENANCE ADJUSTMENTS AND TEST Modem Check ADJUSTMENTS AND TESTS MODEM Check Out Procedure 1 RON OON 16 17 18 19 Required Test Equipment Test Loopback Cable 33279G6 Oscilloscope Install jumpers as follows A JP1 AW B JP2 4W C JP3 4W D JP6 4W E JP4 2W O F 5 G JP7 FE H JP8 INSTALLED I JPY OPEN Turn off controller power Install module in controller Reapply power Attach 600 ohm load loop back cable 33279G
107. is enabled by signal KEYSEL The processor then decodes the four column status bytes to determine which key is pressed Buzzer The processor uses its PB1 output signal BUZ 2 5 B to activate the User Interface module buzzer The processor turns the buzzer ON by setting PB1 HIGH BUZ is buffered before go ing to the User Interface module by U39B 74HCT244 10 5 B 2 20 THEORY OF OPERATION Parallel I O Interface DETAILED DESCRIPTION Parallel I O Section The three members of the ASC 2S family use the same Processor 1 O module The model type is differentiated by which components are installed in the parallel I O section The following dis cussion will address the board generically Any circuits associated with a particular model type will be addressed separately All processor access to the parallel I O section is done through buffers 025 74HCT245 4 2 0 U24 74HCT244 4 2 C These chips buffer the 000 007 data lines 01 06 address lines LDS and RESET The I O DECODER 023 74HCT138 12 6 D divides the I O block defined by parallel I O chip select signal PIOSL into 8 sections LE1 1 00 1 01 4 Y5 Y6 Y7 These sig nals are generated by combining the block select signal PIOSL with the buffered lower data strobe BLDS and the addresses appearing on BA4 BA6 and BA17 The following signals are generated is the latch enable for the bank of outputs containing the following phase 1 8
108. k receiver transmitter circuits Refer to the detailed descrip tion of the Telemetry module and document 34091 Attach the 33279G5 loop back cable to 25 pin Telemetry connector J14 34251 7 4 Select TELEMETRY I O LOOP BACK 4 This tests the parallel I O lines on the 25 pin Telemetry connector Input and output circuitry including input multiplexers logic level translators output latches and output drivers are exercised The display will output a hexadecimal code corresponding to any I O loop failure Use this code in conjunction with Appendix F document 34251 and the detailed de scription of the I O section of the Processor I O module to determine the cause of failure TELEMETRY SUBMENU 1 MARK 2 SPACE 3 MODEM 4 TELEMETRY I O LOOPBACK 3 18 PRESS KEYS 1 4 TO SELECT MAINTENANCE Diagnostics Menu Loopback ADJUSTMENTS AND TEST Loopback 7 This menu provides a set of functions for performing loop back tests on the A B C D TERMINAL PORT2 and SDLC PORT1 connectors Proceed as follows 1 3 19 Attach the 33279G1 33279G2 and 33279G3 loop back cables to the A B and C connectors Select STANDARD I O 1 This tests the parallel I O lines on the Type 2 module connectors Input and output circuitry including input multiplexers logic level translators output latches and output drivers are exercised The display will output a hexadecimal code corresponding to any I O loop failure Use this code
109. l O and the schematic included in the document to pinpoint the problem OVERLAP PROGRAM CARD DATA PHASE OVERLAP A OVERLAP B OVERLAP C OVERLAP D 3 17 MAINTENANCE ADJUSTMENTS AND TEST Diagnostics Menu Telemetry Telemet 6 This menu provides a set of functions for testing all aspects of the Telemetry module and the PORT3 and 25 pin Telemetry ports Test loop back cable 33279G6 is required for testing the PORTS Telemetry port Loop back cable 3327965 is required for testing the 25 pin Telemetry port Perform the following steps 1 Select MARK 1 or SPACE 2 This generates a Mark frequency of 1200 Hz or SPACE frequency of 2200 Hz This signal can be viewed with an oscilloscope across resistors R28 and R29 on the telemetry module 34091 4 6 A This signal should also be present across pins 1 and 2 of J17 34251 7 3 B the PORT3 teleme try connector and across pins 12 and 13 of connector J14 34251 7 4 A the 25 pin Telemetry connector if installed These signals can be used for line attenuation test ing in the field Push SUB MENU F3 to exit either test Attach the appropriate loop back cable for the port to be tested Select MODEM 3 This starts a test that transmits ASCII characters modulated by the modem transmit ter The modulated signal is routed back to the modem chips receiver via the loop back cable The display will reflect the pass or fail condition If test fails replace Te lemetry module Chec
110. l variable data is stored in Random Access Memory RAM pair U6 and U7 628128 5 3 D The standard ASC 2S configuration uses 128K x 8 70 nanosecond devices This provides 256K bytes of data memory The RAM is accessed using zero wait states This is set using the processors internal wait state generator associated with the master RAM chip select signal ICS1 RAM is powered by voltage BAT 5 4 B so that data is not lost during power outages The RAM read write operations function as follows When the RAM chip select signal CS1L and the odd write enable signal WEO are LOW and the odd output enable signal OEO is HIGH the RAM stores the data on the odd data bus 00 D7 in the location specified by the address bus A1 A15 When the RAM chip select signal CS1L and the even write enable signal WEE are LOW and the even output enable signal OEE is HIGH the RAM stores the data on the even data bus D8 D15 in the location specified by the address bus A1 A15 When the RAM chip select signal CS1L is low and the odd write enable signal WEO are high and the odd output enable signal OEO is low the RAM supplies the odd data bus 00 07 with the data stored in the location specified by the address bus A1 A15 When the RAM chip select signal CS1L is low and the even write enable signal WEE are high and the even output enable signal OEE is low the RAM supplies the even data bus D8 D15 with the data stored in the location specified by th
111. ld N3 Ped Omit N6 Ped Omit N7 Ped Omit N8 Ped Omit Overlap A Yellow Overlap A Red N3 Check N3 Phase On N3 Phase Next Overlap D Red Preempt 6 Detector Overlap D Green N4 Ped Omit Free No Coord Max Il Selection Ring 2 Overlap A Green Pe DIE S a en N lt XS lt CHVOTVZZTrA IONnNMOOUD BB Overlap B Yellow CC Overlap Red DD Overlap Red EE Overlap D Yellow FF Overlap C Green GG Overlap B Green HH Overlap C Yellow CONNECTOR C 61 Pin Socket Type 24 61S PIN FUNCTION Status Bit A Ring 2 Status Bit B Ring 2 N8 Don t Walk N8 Red N7 Yellow N7 Red N6 Red N5 Red N5 Yellow N5 Ped Clear N5 Don t Walk N5 Phase Next N5 Phase On Vehicle Detector 5 Ped Detector 5 Vehicle Detector 6 Ped Detector 6 Ped Detector 7 Vehicle Detector 7 Ped Detector 8 N8 Hold Off Force Off Ring 2 Stop Time Ring 2 Inhibit Max Term Ring 2 Test C Status Bit C Ring 2 N8 Walk N8 Yellow N7 Green N6 Green N6 Yellow N5 Green N5 Walk N5 Check N5 Hold N5 Phase Omit N6 Hold N6 Phase Omit N7 Phase Omit N8 Phase Omit Vehicle Detector 8 Red Rest Mode Ring 2 Omit Red Clear Ring 2 N8 Ped Clear N8 Green N7 Don t Walk N6 Don t Walk N6 Ped Clear BB N6 Check CC N6 Phase On DD N6 Phase Next EE N7 Hold N8 Check GG Phase HH N6 Phase Next dero gd ocoocoN Xxz cHaoguzzrac crommoour JJ N7 Walk KK N7 Ped Clear LL N6 Walk MM N7 Check NN N7 Phase On
112. lines The LCD module uses a combination of signals LCDEN ILCDSEL 01 buffered by U39A 74HCT244 106 B and R W buffered by U39B on its inputs to transfer the data to its internal circuitry The IDMA uses the signal TCLK1 4 3 A to generate its data request signal DREQ 2 5 B Thus one byte is transferred for each cycle of TCLK1 The LCD module has a cycle time of 1 microsecond The processor has a cycle time of 271 nanoseconds The master I O chip select signal CS3 is generated using 6 wait states and sig LCDEN is stretched by 22 GAL16V8 10 5 D to accommodate this discrepancy Display LED Backlight The LCD module contains a matrix of yellow green LEDs used to backlight the display The backlight is enabled from the front panel The processor uses its PB2 output signal LCD B 2 5 B to activate the backlight The proces sor turns the backlight ON by setting PB2 HIGH LCD B is buffered before going to the User In terface module by U39B 74HCT244 10 5 B 2 19 THEORY OF OPERATION Processor Module DETAILED DESCRIPTION Keyboard Buzzer Keyboard The User Interface module keyboard consists of a matrix of conductive rubber switches The processor scans the matrix via J3 by reading specific addresses The lower nibble of the ad dress bus A01 A04 which generates the row strobes is buffered by U39A 74HCT244 10 5 B The column data is input by buffer U38 74HCT245 10 5 C Scan circuitry on the User Interface module
113. munica tions with U3 68HC68T 8 4 D the battery backed clock Signals included in this bus are se rial transmit data line SPTXD serial receive data line SPRXD synchronizing clock line SPCLK and slave select line SS 2 5 C Decode And Control This section takes the microprocessors address data strobe address strobe read write chip select and clock signals and combines them in various ways to generate the control bus signals required for proper interaction between devices on the Processor l O module and the User Interface panel These signals will be discussed below All signals starting with a slash character i e xxx are low only when active otherwise they are normally high CLKO 2 2 D outputs the 14 7456 MHz system clock IAS 2 3 B indicates when there is a valid address on the address bus AS is not used outside the processor chip in this design R W 2 3 B defines the data bus transfer as a read or write cycle It is HIGH during a read and LOW only during a write cycle UDS 2 3 B is the upper data strobe signal It controls the flow of data on data bus lines D8 D15 by specifying when valid data should be on the bus ILDS 2 3 B is the lower data strobe signal It controls the flow of data on data bus lines 00 07 by specifying when valid data should be on the bus CS0 CS3 2 3 A are the four system chip select signals 50 is the primary chip select for all EPROM accesses CS1 selects the RAM bank CS2 is
114. n disassembly visual inspection cleaning battery check and various adjustments Test equipment and connector cable assignment lists are included ASC 2S diagnostic tests the primary method for hardware verification and fault isolation are explained Section IV is a troubleshooting chart The chart outlines a series of possible hardware soft ware and programming problems with associated possible causes and suggested solutions Section V contains controller assembly parts lists It lists components cables and assemblies with both Econolite and manufacturer s part numbers Section VI contains schematics and assembly drawings Appendix A contains cable diagrams to be used when interfacing the ASC 2S to a printer or personal computer or for data transfer Appendix B contains pin lists for all connectors A D SDLC Terminal and Telemetry Appendix C describes standard system interconnection using Econolite telemetry interface boards and transient suppressors Appendix D is a guide to lease line installation used in Econolite system communication Appendix E lists and identifies loopback diagnostic error codes 1 3 SECTION 2 FUNCTIONAL DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION This section begins with a functional description of the ASC 2S modules Each module is then described in detail The circuit and signal descriptions are best understood when studied to gether with the block diagrams and system schematics T
115. n and off Use the cursor keys to position the cursor over the other output locations Verify proper operation of all the outputs 4 Press the NEXT PAGE F6 key to view and activate outputs on the remaining screens Push SUB MENU to exit this test If this test uncovers an output failure use the detailed description of the I O section of the Processor l O and the schematic included in the document to pinpoint the problem OUTPUT DIAGNOSTIC CONNECTORS A B amp C OUTPUT DIAGNOSTIC CONNECTOR D PHASE RED CYC CYC CYC SYNC OFT OFT OFT XSTR YELLOW 1 2 OUT 1 2 3 SYNC GREEN WALK DON T WALK PED CLEAR SPLT SPLT NIC NIC PMT PMT CMU CORD CHECK 1 2 SF SF2 1 2 STAT PHASE PHASE NEXT PRESS TOGGLE TO CHANGE PRESS TOGGLE TO CHANGE OUTPUT DIAGNOSTIC CONNECTORS A B amp C OUTPUT DIAGNOSTIC CONNECTOR D RING 1 STATUS RING 2 STATUS PMT PMT A B 3 5 6 OVERLAP SPARE OUTPUTS 4 5 6 RED YELLOW GREEN OUTPUT DIAGNOSTIC TELEMETRY CONNECTOR FLASHING LOGIC SF1 SF2 SF3 SF4 PRESS TOGGLE CHANGE PRESS TOGGLE TO CHANGE 3 15 MAINTENANCE ADJUSTMENTS AND TEST Diagnostics Menu Display Display 3 This menu provides a comprehensive set of functions for testing all aspects of the LCD module Perform the following steps 1 Select DISPLAY 3 from the DIAGNOSTICS SUBMENU When this is selected the controller beeps and displays a message saying that it will go in
116. nes BA1 BA3 are all LOW input DO pin 4 of input multi plexer 029 is selected The LOW state of signal 0 enables the multiplexer and causes the selected input to be inverted and output from Y pin 6 as I O module data bit BDO Input Buffers Input buffers U19A and U59 74HCT244 12 6 B C transfer local and external data to the data bus U59 receives its inputs from logic level translator RP23 U19A inputs a combination of ex ternal and local status inputs On an ASC 2S 2100 input buffer U30B 74HCT244 12 3 B C and U57 get their inputs from the 25 pin telemetry connector via logic level translators RP36 and RP35 respectively The buffers output their data onto the data bus when the proper chip select line Y4 Y8 goes low Among other signals U19A inputs the signal that tells the proces sor when low that the board is configured as an ASC 2S 2100 Overlap Program Inputs On the ASC 2S 2100 a NEMA overlap program card is optionally available for programming overlaps A D This plug in card is connected to optional connector J6 11 1 D Phase combi nations of the four programmable overlap phases A B C and D are programmed by installing jumpers on the card When the overlap card is installed the jumpers ground the 10K pull up resistors RP5 RP8 17 18 3 B D at the 74HC251 multiplexer inputs A ground at these inputs indicates that the associated phase is assigned to the overlap while an open circuit indicates that itis not Progr
117. ns processor Features of the system integration block that are used by the ASC 2 include the independent DMA controller a 19 level interrupt controller the dual port RAM area three programmable tim ers the four programmable chip select lines sixteen parallel I O lines the on chip clock genera tor and several other glue logic functions The communications processor provides the following functions the main controller RISC Processor three independent full duplex serial communications controllers SCC six serial DMA channels for the three SCCs and an SCP channel for synchronous peripheral communica tions The following is the microprocessor signal description All relevant information about the micro processor signals and their associated control circuits is discussed Clocks The system clock synchronizes the internal operations of the microprocessor and all external devices on the system busses Microprocessor timing is controlled by a 14 7456 MHz crystal attached to the on chip clock generator circuit through pins EXTAL and XTAL 2 2 B The system clock rate is 14 7456 MHz This system clock is output by the processor on the CLKO pin 2 2 B CLKO signal is divided by four by U21 GAL16V8 4 4 D to provide a 3 6864 Mhz clock to DUART U20 SCN2681 4 5 A 020 divides the 3 6864 MHz clock by 96 and out puts a 19 200 Hz clock 16 X 1200 baud on OP3 4 5 A for the external transmit clock inputs of SCC1 TCLK1 and SCC2
118. nsists of a custom weather and dust proof conductive rubber keyboard with numeric function and cursor keys and a high contrast 16 line by 40 character liquid crystal dis play with LED back lighting The Connector Interface panel contains two fuses 115 VAC 1 Amp and 24 VDC 0 75 Amp and various interface connectors The type of connectors de pends on the controller model The ASC 2S controller unit contains two main electronic modules and a power supply The first main module is the module which is installed directly in the enclosure This mod ule contains the MC68302 microprocessor which controls all ASC 2S operations and circuitry that transfers input and output signals between the I O connectors and the processor Also lo cated on the 1 module is a connector for installing a telemetry module The sec ond main module is the User Interface assembly mounted to the hinged front panel All versions of the ASC 2S controller use the same modules The model type is defined by the components installed on the 1 module The Processor l O and User Interface modules are inter connected by a ribbon cable located across the front panel hinge The Processor l O module together with the connector interface panel is held in place by two quarter turn fasteners and a card guide The User Interface panel is held in place by 3 nuts Both modules may be easily removed The ASC 2S power supply fu
119. onnector J15 pins 1 and 9 TXC and TXC are the differential transmit clock pair The processor transmits this serial data signal as TCLK3 from SCC3 2 5 C The signal is converted to a differential pair by U82 It is then output on connector J15 pins 3 and 11 RXD and RXD are the differential receive data pair These signals appear on pins 5 and 13 of connector O2P5 After conversion by U81 the single ended TTL signal is routed to SCC3 on the processor as RXD3 2 5 C RXC and RXC are the differential receive clock pair These signals appear on pins 7 and 15 of connector O2P5 After translation by U82 the single ended TTL signal is routed to SCC3 on the processor as RCLK3 2 5 C Terminal EIA 232 Interface The terminal interface circuit sends and receives its signals on the terminal bus All TTL to EIA 232 signal level translation is provided by U80 MAX214 7 2 C which contains three EIA 232 drivers and three EIA 232 receivers U80 uses capacitors C66 C67 C71 and C72 for its onboard positive and negative voltage generation circuits U80 also has an internal DCE DTE switch that is controlled by TERMCTRL 1 7 3 B Terminal signals are routed to the outside world via connector J13 DB25 7 1 C The ElA 232 level signals are protected against over voltage transients by transient voltage suppressors MMBZ15VDLT 1 7 1 B The interface contains the following sig nals TXD is the transmit data signal The processor outputs thi
120. or the off board RAM memory space This signal is gen erated by U13 GAL16V8 4 4 C by combining the RAM chip select signal from the processor ICS1 and A16 This signal utilizes the fact that GAL16V8 outputs float when power is removed This eliminates a current path out of the RAM chips during battery backup operation thus ex tending battery life ICSWE 4 3 C is the write enable signal for the data module This signal allows the processor to write data from the data bus into the device if the devices chip select line is active This sig nal is generated by U13 GAL16V8 4 4 C by combining input signals GR W A9 A13 and the input from the EEPROM write protect jumper JP3 4 4 B A9 A13 are used to differentiate be tween the write protected and non write protected areas of the module ISWAPCSO 4 4 C is used during flash EPROM download module 3 6864 4 3 D provides a 3 6864 Mhz clock signal to the DUART U20 SCN2681 4 6 A This signal is generated by 021 GAL 16V8 4 4 0 by dividing the system clock CLKO by four STOP HERE IDWEO 4 3 D is the write enable signal for DUART U20 SCN2681 4 6 A This signal allows the processor to write data from the data bus into the device if the devices chip select line is ac tive This signal is buffered version of WEO and is generated by 021 GAL16V8 4 4 0 IDOEO 4 3 D is the output enable signal for DUART U20 SCN2681 4 6 A This signal gates the data from the device onto the data b
121. ot on 1 120 Hz reference circuit 2 OPTO1 circuit Voltage monitor Fault monitor output FALSE 1 Power supply out of tolerance voltage or voltage monitor control circuit failed 2 a Preemptor phases programmed not IN USE when preemptor becomes active b Preemption active during power outage 1 1 0 secton failure Output circuitry for phase in I O Interface section failed One phase has no outputs 2 Phase omitted in configuration PROM programming Controller appears to be operating but all outputs are OFF 1 24 V EXT fuse F1 is blown 2 Processor section failure IPIOSL decode circuits failed 3 I O Interface module failure All outputs from one phase or one output does not 1 1 0 section failure Output driver failed turn ON All inputs inoperative 1 I O Interface section failure 2 Processor section failed A Check fuse F2 replace if necessary 2 A Verify that power is applied 3 B Check construction and seating of harnesses 4 Verify 24VDC output Return supply to Econolite for repair 1 A Remove replace Processor l O module B Check AC power monitor circuit interrupt operation U1 8 4 6 A 2 A Remove replace Processor I O module Check OPTO1 circuit 20 2 3 C CAUTION LETHAL VOLTAGES PRESENT IN THIS CIRCUIT 1 A Remove replace power supply B Check 24VDC and voltage monitor circuits 3 4 B 2 a Program preemption phases IN USE Recall data p
122. otects the RAM when power is removed 2 12 THEORY OF OPERATION Processor Module Decode and Control DETAILED DESCRIPTION 4 5 D is the output enable signal for the even addressed RAM and EPROM chips This signal gates the data from the device onto the data bus allowing the processor to read the data This signal is generated by U14C 74ALS32 4 6 D by ORing the upper data strobe UDS with the inverted read write line RW RW is generated by U15A by inverting the R W signal from the processor ICSOL 4 3 C is the chip select signal for the onboard flash EPROM chip This signal is gener ated by 013 GAL16V8 4 4 C by combining the main EPROM chip select line 0 from the processor with 20 CSOL is active for the address range 000000 0FFFFF ICSOH 4 3 C is the chip select signal for the off board flash EPROM memory space This sig nal is generated by 013 GAL16V8 4 4 C by combining the main EPROM chip select line ICS0 from the processor with A20 CSOH is active for the address range 100000 1FFFFF ICS1L 4 3 C is the chip select signal for the onboard RAM chips This signal is generated by U13 GAL16V8 4 4 C by combining the RAM chip select signal from the processor CS1 and A16 This signal utilizes the fact that GAL16V8 outputs float when power is removed This eliminates a current path out of the RAM chips during battery backup operation thus extending battery life ICS1L 4 3 C is the chip select signal f
123. rnishes 24VDC for controller unit operation It is mounted inter nally on the back panel of the enclosure The power supply is held in place four screws and is connected to the 55 module by two wire harnesses 5 25 2 1 5 25 2000 ASC 2S 1000 TYPE 2 WITH EXPANDED I O 5 25 2100 Figure 1 1 ASC 2S Family 1 2 INTRODUCTION PROGRAMMING MAINTENANCE MANUALS MANUALS Programming Manuals Programming of the ASC 2S controller unit is covered in the ASC 2S programming manual However maintenance information is provided for all ASC 2S family members in this manual Maintenance Manual This manual contains the information needed to understand the hardware functions of the 5 25 controller family Information about the circuitry general maintenance requirements installation and disassembly is included Fault isolation charts are provided to help the techni cian isolate problems or to at least provide a good starting point for troubleshooting Schemat ics and comprehensive parts lists are included as well as several appendices to supplement the hardware descriptions Section 11 contains the ASC 2S theory of operation beginning with a functional description of each module followed by a detailed description of circuit operation Section III is a collection of procedures and check lists that should be used as part of regular maintenance Included are procedures for installatio
124. s 2 10 System BUSSES oai dtu oH equa aie 2 11 Decode And 2 12 External Interrupt 2 15 Internal Interrupt Sources 2 15 Memory P 2 16 Voltage Monitor Control eek 2 17 Down Time Accumulator a 2 18 Local Voltage Reg latorS 2 18 Back Up ara e e e nieto n cara 2 19 Display E 2 19 Keyboard unu 2 20 lle 2 20 Parallel 2 21 Address BUS it vtt roto bor td eet eed ro eite 2 22 Data BUS RR 2 22 Logic Level Translators A A dl 2 22 Input 2 23 2 23 Overlap Program Inputs 2 01 202 020 249 004000000000 000000000000000000000000000 2 23 Output tern E 2 24 SDLC EIA 485 Interface e Re RAR an Rn 2 25 Terminal ElIA 232 Interface 2 25 Telemetry Interface euer 2 26 AGC POWSIN DUT E e Ey A
125. s of networking traffic control equipment Polling refers to the method in which a Master station addresses a particular local station anticipating a data response Upon comple tion of the data transaction the next local station is polled Econolite utilizes this method but employs full duplex communications whereby the Master station addresses the next local sta tion while simultaneously receiving data from a previously addressed station The system consists of a single Master station ASC 2M 1000 Zone Master or KMCE 10 000 Arterial Master and one to 24 local stations with any combination of the following controllers ASC 2 S family the CBD ASC 8000 ASC 8000RM KMCE 8000 KFT 18 2400 All transmis sions from the master station are simultaneously received by all local stations while all transmis sions from local stations are received only by the master Thus the master station controls the network and no interaction between the local stations occurs The following specifications define telephone company lease line requirements for Econolite Master Local station networking Econolite telemetry module modem design specifications are also enclosed to assist in telephone company circuit design Further assistance from Econolite is available upon request D 1 APPENDIX D GUIDE TO LEASE LINE INSTALLATION LEASE LINE SPECIFICATIONS Line Type Interconnect Method Drops Battery Voltage Data Signal Power Loss Variation Term
126. s serial signal from SCC2 as TXD2 2 5 C After translation it appears on pin 2 of J13 is the receive data signal This serial input signal appears on pin of 413 It is translated and routed to SCC2 of the processor as RXD2 2 5 C This signal is also routed to the DUART U20 4 5 B as RXDB CD is the Data Carrier Detect handshaking signal This input signal appears on pin 8 of J13 It is translated and routed to SCC2 of the processor as CD2 2 5 C CTS is the Clear To Send handshaking signal This input signal appears on pin 5 of J13 It is translated and routed to SCC2 of the processor as CTS2 2 5 C RTS is the Request To Send handshaking signal The processor outputs this serial signal from SCC2 as RTS2 2 5 C After translation it appears on pin 4 of J13 2 25 THEORY OF OPERATION Parallel I O Interface DETAILED DESCRIPTION SDLC Interface Telemetry Interface DTR is the Data Terminal Ready handshaking signal DUART U2 4 5 A outputs this serial sig nal from OP2 as DTRT After translation it appears on pin 20 of J13 Signals RTS CTS CD and DTR are handled under program control and are implemented only as required Communications with a printer utilize the XON XOFF software handshake proto col Telemetry Interface The Telemetry interface sends and receives its signals on the Telemetry bus The signals are routed to the telemetry module connector J4 7 5 B translated by the telemetry module and then rou
127. s with to the Telem etry bus via connector J4 Transmit and receive signals are interfaced through the Telemetry connector s on the front panel Transceiver Operation Communication between the local and master controllers is achieved over voice grade four wire two data channels type 3002 leased telephone lines or customer owned cable The telemetry data channel is made up of command master to local and readback local to master lines Additional lease line information is found in Appendix D Each local transceiver is assigned a unique telemetry address used by the master to identify the transceiver The address is as signed by either direct keyboard entry refer to the ASC 2S Programming Manual or by activat ing External Address Enable J14 15 and assigning the desired bit pattern to the appropriate D connector system inputs refer to Appendix E Devices connected to the local transceiver are identified by subaddresses assigned and used by the master The master generates command messages containing local telemetry address message type subaddress data and a horizontal parity word Command messages are transmitted to the lo cal transceiver in a predefined sequence The sequence begins with a zero address command which simultaneously transmits to all local controllers the system traffic program and four spe cial functions Local controllers do not respond to the zero address command Subsequent messages request the status of the dev
128. section The 24VEXT external output is applied to connector pin A B This output is rated at 500 mA and provides sufficient current for most traffic applications The 24 VDC has been fused with a 3 4 Amp SLO BLO fuse F1 to allow the controller to supply sufficient current for a controller test fixture using LED displays 20 mA per LED This higher current capability should only be used during testing Note that the 24 VDC load in the traffic control cabinet should never exceed 500 mA Inductor L2 20 4 A fil ters out noise induced on the logic ground FGND when it is run outside the controller 2 27 THEORY OF OPERATION FSK Telemetry Module DETAILED DESCRIPTION Modulator Transmitter Circuit FSK Telemetry Module The MODEM provides Frequency Shift Keying FSK modulation of data from TXDA to make the data compatible for transmission over telephone lines or twisted pair cable It also receives FSK signals and demodulates them to provide the RXD1 signal All signals going to or from the telemetry module are routed through connector 1 2 6 A D and others This connector interfaces with connector J4 on the 55 module Transmit Data TXDA The TXDA 3 6 B line carries TTL level serial data from the DUART on the processor module 34251 4 5 B to the analog multiplexer U2 74HC4051 3 3 C which is then routed to the FSK modulator The data rate is 1200 bits per second Receive Data RXD1 The RXD1 4 1 D line sends TTL
129. signal as RTSA 4 5 B It is routed to pin 8 of J4 EIA 232 telemetry modules output this signal on J17 pin 7 MDCTL1 and MDCTL2 are used to control various functions on the Telemetry module They are generated under program control by using two of the DUARTS parallel I O lines 4 5 A MDCTL2 is also routed to inverter driver 064 ULN2803A 19 5 B It is used on J14 as the KEY signal required by the radio interconnect is used to reset the telemetry module circuitry It is a buffered version of system RESET Signals RTS CTS and CD are handled under program control and are implemented only as re quired 2 26 Power Supply Module THEORY OF OPERATION AC Power Input DETAILED DESCRIPTION AC Power Input The AC line transient protection circuit consists of resistors R65 and R67 and varistors RV1 RV2 and RV3 The circuit receives a three wire 120 VAC 60 Hz input from the A connector J12 or J16 on the ASC 2S 1000 The three inputs are AC line AC neutral and earth ground AC line is over current protected by fuse F2 AC line and AC neutral are then routed to current limiting resistors R67 and R65 respectively Varistor RV1 RV2 and RV3 provide both common and differential mode transient protection This is accomplished by clamping transients occur ring between AC line and AC neutral with varistor RV2 Transients occurring between AC line or AC neutral and earth ground are clamped by RV1 and RV3 respectively The output of
130. sing 1 pps at 50 duty cycle NEMA defined input that is applied to Preemptor Call input 3 6 respectively PIN FUNCTION 43 SYSTEM COMMAND CYCLE BIT 1 OUTPUT 44 SYSTEM COMMAND CYCLE BIT 2 OUTPUT 29 SYSTEM COMMAND CYCLE BIT 3 OUTPUT 33 SYSTEM COMMAND OFFSET BIT 1 OUTPUT 42 SYSTEM COMMAND OFFSET BIT 2 OUTPUT 2 SYSTEM COMMAND OFFSET BIT 3 OUTPUT 21 SYSTEM COMMAND SPLIT BIT 1 OUTPUT 46 SYSTEM COMMAND SPLIT BIT 2 OUTPUT 53 SYSTEM COMMAND SYNC OUT 23 PREEMPTOR 1 ACTIVE 32 PREEMPTOR 2 ACTIVE 22 PREEMPTOR 3 ACTIVE 34 PREEMPTOR 4 ACTIVE 1 PREEMPTOR 5 ACTIVE 48 PREEMPTOR 6 ACTIVE 59 PREEMPT CMU INTERLOCK 1K PULL UP 27 COORD STATUS 5 CROSS STREET SYNC 28 NIC SPECIAL FUNCTION 1 8 NIC SPECIAL FUNCTION 2 24 NIC SPECIAL FUNCTION 3 SPARE OUTPUT 1 11 SPECIAL FUNCTION 4 SPARE OUTPUT 2 15 PREEMPTOR FLASH CONTROL 41 SPARE OUTPUT 4 45 SPARE OUTPUT 5 51 SPARE OUTPUT 6 52 SPARE OUTPUT 7 54 SPARE OUTPUT 8 PORTS 1 2 3 TYPE 1 POWER PORT 1 SDLC PIN FUNCTION 1 Tx Data 2 Logic Ground 3 TxClock 4 Logic Ground 5 Rx Data 6 Logic Ground 7 Rx Clock 8 Logic Ground 9 Tx Data 10 Port 1 Disable OVDC disable 11 Tx Clock 12 Chassis Ground 13 Rx Data 14 Reserved 15 Rx Clock PORT 2 TERMINAL PIN FUNCTION Vo Chassis Ground Transmit Data O Receive Data Request Send O Clear To Send Not Used Logic Ground Data Carrier Detect 9 19 Not Used 20 Data Terminal Ready 21 2
131. slated to logic levels to be used by the system The TRUE FALSE LOW HIGH states are then applied to input multiplexers The processor reads the input status by addressing the input and enabling the multiplexer thus transferring the input status onto the system data bus The processor uses output latches to control the external parallel signals It addresses a spe cific output and latches that output status from the data bus by enabling the latch The signal is then sent to external connectors A B or C In the event of a long power failure the latches are cleared to prepare for an orderly controller re start The Terminal bus signals interface with external equipment through Terminal connector J13 PORT 2 It is used to communicate with printers computer terminals or other controllers in the ASC family The SDLC bus signals interface with optional Bus Interface Units and or a Malfunction Man agement Unit via SDLC connector J15 PORT 1 The Telemetry bus signals attach to connector J4 and supply the signals required for FSK and EIA 232 fiber optic telemetry interconnects Once translated by the Modem module the signals interface with external signals via connectors J17 PORT 3 and J14 on the model ASC 2S 2100 VOLTAGE MONITOR CONTROL is generated by monitoring the power supply and battery volt ages and Processor signals It is output to external equipment as VOLTAGE MONITOR When the 1 module is configured as an A
132. t 6 id Mode Output 14 E Mode Input 7 FF Mode Output 24 GG Output 8 HH Mode Output 16 N xz c7 o oo0ogms so0 oocooo0ooN xz cHdomuzzrc ac crommoou JJ N7 Walk KK N7 Ped Clear LL N6 Walk MM Mode Output 23 NN Mode Output 7 PP Mode Output 15 Type 2 I O Modes MODE BITS 3 PER UNIT Mode Bit States State A ON ON ON NSNOUPOD OH ON B Names OFF OFF OFF TS 1 Compatible OFF OFF Hardwire Interconnect OFF ON OFF System Interface ON OFF Reserved OFF OFF ON Reserved OFF ON Reserved OFF ON ON Manufacturer Specific ON ON Manufacturer Specific Voltage Levels OFF 24 ON 0 MODE 0 INPUT OUTPUT FUNCTIONS Inputs Pin Function A h Phase 1 Hold A M Phase 2 Hold B i Phase 3 Hold B h Phase 4 Hold C m Phase 5 Hold C p Phase 6 Hold C EE Phase 7 Hold C X Phase 8 Hold B U Phase 1 Phase Omit B S Phase 2 Phase Omit B R Phase 3 Phase Omit B g Phase 4 Phase Omit C n Phase 5 Phase Omit C q Phase 6 Phase Omit C r Phase 7 Phase Omit C s Phase 8 Phase Omit A EE Phase 1 Ped Omit Phase 2 Ped Omit B j Phase 3 Ped Omit B T B k B m B n Phase 4 Ped Omit Phase 5 Ped Omit Phase 6 Ped Omit Phase 7 Ped Omit Phase 8 Ped Omit Outputs Pin A DD A e B s B e C N C CC C NN C GG B A B C B t B f C M C DD C PP C HH A u A d B r B K C k C BB C MM C FF Function Phase 1 Phase On Phase 2 Phase On Phase 3 Phase On Phase 4 Phase On
133. ted to the outside world via connectors J17 DE9P 7 3 B and J14 DB25P 7 4 A All TTL to FSK EIA 232 or EIA 485 signal level translation is provided by the telemetry module at tached to connector J4 The interface contains the following signals TXD is the transmit data signal The DUART U20 4 5 B outputs this serial signal to the telem etry module as TXDA After translation it is routed to J17 pins 1 and 2 and expansion connector J14 as signal pair XMIT and XMIT RXD is the receive data signal This serial input signal appears on pins 4 and 5 of J17 and ex pansion I O connector J14 as RECV and RECV then routed to It is translated by the Te lemetry module and routed to SCC1 of the processor as RXD1 2 5 D CD is the Data Carrier Detect handshaking signal This signal is generated by the FSK teleme try module and appears on 9 of It is routed to the DUART as CDA 4 5 B EIA 232 te lemetry modules input this signal form J17 pin 1 CTS is the Clear To Send handshaking signal This input signal generated by the telemetry module appears on pin 7 of J4 It is routed to the DUART as CTSA 32806 5 3 A This signal also serves as the MODEM PRESENT signal used by the processor to determine if a Telemetry module is present The Telemetry module will pull this signal low if present EIA 232 telemetry module input this signal from J17 pin 1 RTS is the Request To Send handshaking signal The DUART outputs this
134. the watchdog input Under normal conditions all three inputs are high thus maintaining Voltage Monitor Control VMC HIGH A flash condition is indicated by VMC LOW The LOW VMC signal is inverted again at the I O Interface and output as Voltage Monitor This signal can be used in conjunction with a conflict monitor to set the intersection in flash 2 17 THEORY OF OPERATION Processor Module DETAILED DESCRIPTION Down Time Accumulator Local Voltage Regulators Down Time Accumulator The Down Time Accumulator DTA is used to detect missing 120 Hz interrupts and to time the length of power outages The DTA consists of battery backed real time clock chip U3 68HC68T 8 4 0 and the processor chips internal Timer CAUTION Do not attempt to adjust the crystal oscillator C19 in the field This is a precision adjustment See maintenance section for proper adjustment procedure Timer 3 is used to determine whether the length of a power failure is less than or greater than 0 75 seconds This time was selected as the limit within NEMA range in determining the action to take after a short 0 75 or long gt 0 75 power failure If the power failure is less than 0 75 seconds the controller continues to operate If the power failure is greater than 0 75 sec onds the controller reverts to its start up sequence If power fails altogether the processor writes its internal RTC time out to U3 to keep accurate time until power is reappli
135. ther components of the traffic control cabinet The first model the ASC 2S 1000 provides an I O interface conforming to NEMA TS2 standard requirements for Type 1 controllers This interface controls all cabinet I O over a serial commu nications channel Port 1 This serial communications channel is used for data exchange with a Malfunction Management Unit MMU to retrieve vehicle detector data from detector racks and interface to Terminals and Facilities within the traffic control cabinet All I O functions are handled by one or more Bus Interface Units BIUs Each BIU controls up to 15 outputs 24 in put outputs 8 inputs and four optically coupled inputs Type 1 I O also includes EIA 232 com patible terminal Port 2 and telemetry Port 3 interfaces The second model of the ASC 2S family the ASC 2S 2000 has an I O interface that conforms to both NEMA TS1 and TS2 Type 2 controller requirements This interface controls I O functions through industry standard circular connectors A B amp C and includes the serial communications terminal and telemetry interfaces of the Type 1 interface TS1 operation allows the ASC 2 2000 to be used in existing traffic con trol cabinets without any cabinet changes The Type 2 I O operates in one of eight I O modes Each mode assigns specific functions to 24 input and output connections The first mode Mode 0 provides com patibility with the I O requirements of the NEMA TS1 standard This TS1 opera
136. tional mode is selected by setting the Type 2 I O mode to Mode 0 default and disabling the serial communications channel The serial communications channel of the Type 2 interface is used to communicate with a Mal function Management Unit and detector racks as with the Type 1 interface However a mini mum of 20 vehicle detectors can optionally be connected directly to the controller using one of the Type 2 I O modes The ASC 2S 2000 can also be programmed to operate as a Type 1 con troller In this mode external I O interface is disabled and all functions are handled over the serial communications channel This allows the ASC 2S 2000 to duplicate the operation of the ASC 2S 1000 The ASC 2S 2100 is the third model of the ASC 2S actuated controller family The ASC 2S 2100 Processor l O module includes components that add additional I O to the ASC 2S 2000 capabilities described above The expansion components include the D connector 25 pin telemetry connector and optionally the NEMA overlap card connector interfaces matching those of the ASC 8000 This allows the ASC 2S 2100 to be used as a replacement for an ASC 8000 or ASC 2 2100 in existing traffic control cabinets without any cabinet changes 1 1 INTRODUCTION ASC 2 FAMILY The ASC 2S family of actuated controllers are made of a formed aluminum enclosure Control ler fronts consist of the User Interface panel and the Connector Interface panel The User Inter face panel co
137. to flash when this test is started 2 When the DISPLAY SUBMENU is displayed select CURSOR ADDRESS 1 This will perform a test which causes the cursor to address every character location on the display Verify all positions are addressed Push SUB MENU F3 to exit this test 3 Select CHARACTER FONT 2 This test will display complete ASCII character set supported by the module Verify all characters are properly formed Push SUB MENU F3 to exit this test 4 DISPLAY ADJUST 3 The display adjust test does not work the 5 25 control ler 5 Select BACKLIGHTING 4 This test will continuously turn the display backlight on and the off Verify this operation Push SUB MENU F3 to exit this test 6 Select FULL SCREEN 5 This test fills the display with dark characters This should give the appearance of forty black columns each separated by a one white pixel Verify this operation Push SUB MENU to exit this test If this test pro duces a screen with missing pixels LCD module replacement may be required 7 ALL TESTS 6 automatically performs tests 1 5 above Push DISPLAY SUBMENU SUB MENU F3 to exit this test 1 CURSOR ADDRESS Please note There are no user serviceable parts on the User Interface module If it has 2 CHARACTER FONT been determined that a display problem is 3 DISPLAY ADJUST caused by the module please return it to Econolite 4 BACKLIGHTING 5 FULL SCREEN 6 ALL TESTS PRESS
138. uipment summarized below ENVIRONMENTAL OPERATION SPECIFICATIONS NEMA TS 2 SECTION 2 CATEGORY REQUIREMENT Input Power Line Voltage 89 to 135 VAC ASC 2S 1000 20 Watts Consumption 5 25 2100 25 Watts Ambient Operating Range 34EC to 74EC Temperature Storage Range 45EC to 85EC Humidity Relative humidity is not to exceed 95 over the temperature LEN IP EE Vibration The major units of the controller assembly maintain their programmed functions and physical integrity when subjected to a vibration of up to 0 5g at 5 to 30 cycles per second applied in each of the three mutually perpendicular planes Shock The major units of the controller assembly do not suffer either permanent mechanical deformation or any damage that renders the unit inoperable when subjected to a shock of 10G applied in each of the three mutually perpendicular planes 3 4 MAINTENANCE TEST EQUIPMENT TEST EQUIPMENT The following is a list of suggested test equipment to be used for fault isolation basic check out and general maintenance 1 100Mhz digital dual trace oscilloscope Used for observing signals and checking of time relationships of two waveforms where necessary 2 Digital Multimeter DMM Used for continuity testing diode and transistor checks and general voltage measurements The DMM should meet the following specifications PARAMETER RANGE ACCURACY INPUT IMPEDANCE DC VOLTS 200mV 1000V 0 25 of Input 10 MS AC VOLTS 20
139. us allowing the processor to read the data This signal is buffered version of OEO and is generated by U21 GAL16V8 4 4 D IDUART 4 3 D is the DUART chip enable line This signal is generated by 021 GAL 16V8 4 4 D by combining the system I O enable signal CS3 from the processor and address lines A17 A19 It is routed to U20 SCN2681 4 5 A DUART is active for the address range E00000 E1FFFF 2 13 THEORY OF OPERATION DETAILED DESCRIPTION Processor Module Decode and Control IPIOSL 4 3 0 is the parallel I O device enable line It is generated by 021 GAL16V8 4 4 D by combining the system I O enable signal CS3 from the processor and address lines A17 A19 This signal enables the I O data buffer U25 74HCT245 4 2 D and bank selector U23 13 6 D PIOSL is active for the address range E20000 E3FFFF GR W 4 3 C is the R W line from the processor combined with the PWRGOOD signal A write to a memory device can not be accomplished until PWRGOOD is asserted high IFPSEL 10 5 D is the User Interface buffer 038 74HCT245 10 5 C enable line This signal is generated by U22 GAL16V8 10 5 D by combining the system I O enable signal CS3 from the processor and address lines A17 A19 IKEYSEL 10 5 D is the keyboard input buffer enable line that is routed to the User Interface module connector J3 10 5 A This signal is generated by 022 GAL16V8 10 5 D by combin ing the system I O enable signal CS3 from the proc
140. y module connector Signals included in this bus are the receive data line RXD1 2 5 D which inputs serial data into SCC1 on the processor the transmit data line TXDA 4 5 B which trans mits data out of U20 and CTSA RTSA CDA MDCTL1 and MDCTL2 generated by U20 4 5 B which control communications handshaking and provide modem control Terminal Bus This bus contains the serial data and hand shaking signals which are routed to the Terminal Port PORT2 RS 232 interface chip U80 MAX214 7 2 C Signals included in this bus are the receive data line RXD2 which inputs serial data into SCC2 on the processor the transmit data line TXD2 which transmits data out of SCC2 CTS2 RTS2 CD2 generated by SCC2 4 6 C and DTRT generated by U20 4 5 A which control communications handshaking and provide modem control SDLC Bus This bus contains the serial data and clock signals which are routed to the SDLC Port PORT1 RS 485 interface chips U81 and U82 LT490 7 D 6 Signals included in this bus are the re ceive data line RXD3 which inputs serial data into SCC3 on the processor TXD3 which outputs serial data from SCC3 and transmit and receive clocks TCLK3 and RCLK3 2 5 C which are required to synchronize communications over the SDLC channel THEORY OF OPERATION Processor Module DETAILED DESCRIPTION System Busses Decode and Control SPI Bus This bus contains the serial data clock and handshake signals which are used for com
141. ymptoms may provide a starting point for trouble shooting Because of the modular design of the ASC 2S repair at the cabinet level should be limited to removal and replacement of bad modules and fuses Any in depth fault isolation should be done in a shop with the proper test equipment Personnel and equipment should be prop erly grounded to prevent damage due to static electricity Exercise caution so that the pro gramming integrity within the controller is maintained as intended for the particular intersection during removal and replacement of modules Therefore modules containing unique program ming for a specific intersection Processor module overlap program board Data module must not be used operationally anywhere other than at that intersection If a problem is found on the 1 module the customer has the option to either repair the equipment or return it to Econolite for service The User Interface and Power Supply mod ules should always be returned to Econolite for service In any case all information relevant to the failure must be recorded If a defective module or the complete controller is returned for service please send as much information as possible about the failure Note the nature of the malfunction and details about the conditions affecting the controller at the time of failure Try to reproduce the failure in a lab to determine the pattern if any Use these guidelines when documenting a failure

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