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GUERRERO_QUICHI - Repositorio Digital de Tesis PUCP

1. oot EE A I Len cai E pi LET UI AR z 0 2 0 3 0 5 0 1 100 AMPS Figure 37 Measurement Error 6 Reading 70 220 V PF 0 5 0 5 Frequency 50 Hz U 011111 SELL AM ETT 0 1 1 100 Figure 38 Measurement Error Reading Y 25 C 220 V PF 40 5 0 5 Frequency 50 Hz EMISSIONS TESTING EMC N55022 1994 At end of data sheet SUSCEPTIBILITY TESTING EMC EN 61000 4 2 EN 61000 4 3 EN 61000 4 4 ENV 50204 At end of data sheet ANSI C12 16 AND IEC1039 The ANSI standard governing Solid State Electricity Meters is ANSI C12 16 1991 Since this application note refers to the IEC 1036 specifications when explaining the design this section will explain some of those key IEC1036 specifications in terms of their ANSI equiva lents This should help eliminate any confusion caused by the different application of some terminology con tained in both standards AN 559 Class IEC1036 The class designation of an electricity meter under IEC1036 refers to its accuracy For example a Class 1 meter will have a deviation from reference performance of no more that 1 A Class 0 5 meter will have a maximum devia tion of 0 596 and so on Under ANSI C12 16 Class refers to the maximum current the meter can handle for rated accuracy The given classes are 10 20 100
2. D DIGITAL INTEGRATOR SIGN 26 MULTIPLIER CURRENT SIGNAL i t 0x2851EC 0x00 0xD7AE14 AVERAGE POWER SIGNAL P v D PHCAL 6 0 VOLTAGE SIGNAL v t 0x2852 000x 0xD7AE TIME nT AWATTOS 11 0 AWATTHR 15 0 5 0 anu 40 e TOTAL ACTIVE POWER IS ACCUMULATED INTEGRATED IN THE ACTIVE ENERGY REGISTER 04443 066 Figure 66 ADE7758 Active Energy Accumulation The ADE7758 achieves the integration of the active power signal by continuously accumulating the active power signal in the internal 41 bit energy registers The watt hr registers AWATTHR BWATTHR and represent the upper 16 bits of these internal registers This discrete time accumulation or summation is equivalent to integration in continuous time Equation 20 expresses the relationship Energy tdt Lim r 20 where n is the discrete time sample number T is the sample period Figure 66 shows a signal path of this energy accumulation The average active power signal is continuously added to the internal active energy register This addition is a signed operation Negative energy is subtracted from the active energy register Note the values shown in Figure 66 are the nominal full scale values that is the voltage and current inputs at the corresponding phase are at their full scale input level The average active power is divided by the content of the watt divider register
3. noise 2 Figure 34 Noise Coupling via Ground Return Impedance One common technique to overcome these kinds of problems is to use separate analog and digital return paths for the supply Also every effort should be made to keep the impedance of these return paths as low as possible In the PCB design for the AD7755 separate ground planes were used to isolate the noisy ground returns The use of ground plane also ensures the imped ance of the ground return path is kept as very low The AD7755 and sensitive signal paths are located in a quiet part of the board that is isolated from the noisy elements of the design like the power supply flashing LED etc Since the PSU is capacitor based a substan tial current approximately 32 mA at 220 V will flow in the ground return back to the phase wire system ground This is shown in Figure 35 By locating the PSU in the digital portion of the PCB this return current is kept away from the AD7755 and analog input signals This current is at the same frequency as the signals being measured and could cause accuracy issues crosstalk between the PSU as analog inputs if care is not taken with the routing of the return current Also part of the attenuation network for the Channel 2 volt age channel is in the digital portion of the PCB This helps to eliminate possible crosstalk to Channel 1 by ensuring analog signal amplitudes are kept as low as possible in the analog qui
4. 60Hz la mejor frecuencia para la distribuci n de corriente alterna CA y 240V el mejor voltaje para circuitos de larga distribuci n Muchas diferentes frecuencias se usaron en el s XIX y tempranamente en el s XX la mayor a de la potencia se produc a a 60Hz Norteam rica o 50Hz Europa mayor a de Asia En el Reino Unido diferentes frecuencias incluyendo 25Hz 40Hz y CC proliferaban y el est ndar 50Hz fue establecido luego de la segunda Guerra Mundial Toda Europa gran parte de frica y Asia usan 230V 10 96 mientras Jap n Norteam rica algunas partes de Sudam rica usan de 100 a 127V e Ruido el ctrico Se denomina ruido el ctrico a todas aquellas se ales de origen el ctrico no deseadas y que est n unidas a la se al principal o til de manera que la pueden alterar produciendo efectos que pueden ser m s o menos perjudiciales La principal fuente de ruido es la red que suministra la energ a el ctrica y lo es porque alrededor de los conductores se produce un campo magn tico a la frecuencia de 50 60Hz Adem s por estos conductores se propagan los par sitos o el ruido producido por otros dispositivos el ctricos o electr nicos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis p TENER E PONTIFICIA TESIS PUCP S CAT LICA DEL PERU 2 5 MODELO TE RICO Luego de analizar las respectivas tecnolog as para
5. Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis L PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU es EL MONTAJE DE LA ETAPA DE EXPANSION ACTUADORES Figura 3 26 Actuadores en la tarjeta de componentes Conector del 1 Regulador LM7805 TEMPUSVI Conector de actuadores 2 Rel s 5VDC Consideraciones de diseno e Esta etapa de expansi n present un primer inconveniente de dise o pues el rel al ser un dispositivo que consume mucha corriente en un largo periodo tanto como dure su funcionamiento no se pod a alimentar directamente con la fuente de los m dulos digitales pues se corr a el riesgo que la fuente se por sobre exigencia Entonces se dise una fuente de alimentaci n basada en el LM7805 con una consideraci n adicional la cual responde a la mejora del tiempo de vida del regulador y los componentes cercanos que pueden ser afectados por sobrecalentamiento Te ricamente un rel consume corriente s lo en uno de sus estados sin embargo en la pr ctica el rel llega a consumir corriente en cualquiera de sus dos estados siendo siempre un estado de mayor Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CATOLICA DEL PERU consumo que el otro Para limitar el funcionamiento y posterior calentamiento de
6. 11 Typical Performance Characteristics 12 TES TG WC a 17 ICD 18 PN E ens 18 Analog Inputs ada 18 Current Channel AD isti cavet ehe it 19 di dt Current Sensor and Digital Integrator 20 Peak Current D d otro PER RO EE 21 Overcurrent Detection Interrupt eese 21 Voltage Channel ADC 22 Zero Grossime DECO nd eiat 23 Phase Compensation 23 A ot RON DNI RM Dd MM 25 Line Voltage SAG Det ctlOn oom rtt get 25 SAG Level Seta distin inet re eae RR EMI MUR 26 Peak Voltage Detection oa s RO NUR 26 Phase Sequence Detection eese 27 Power Supply Monti NUN E USE 27 27 Temperature Measurement eese 28 Root Mean Square 28 Active Power Calculator tetitas 30 Reactive Power Calculation uni 35 Apparent Power Calculation eet treten 39 Energy Registers Scal Ino saisons ot Rp A PA BRE 41 Waveform Sampling Mode sees 41 Ca DE HEISE DISHES MEDIEN EIS 42 cos 55 ERAR 56 Using the Interrupts with an MCU sees 56 Interr pt TIMIDE ose po
7. Choosing the Filter 3 dB Frequency As well as having a magnitude response all filters also have a phase response The magnitude and phase response of a simple RC filter 1 C 33 nF are shown in Figures 6 and 7 From Figure 6 it is seen that the attenuation at 900 kHz for this simple LPF is greater than 40 dBs This is enough attenuation to ensure no ill effects due to aliasing 40 NO 60 10 100 1k 10k 100k FREQUENCY Hz Figure 6 RC Filter Magnitude Response REV A 10 100 1k 10k FREQUENCY Hz DEGREES Figure 7 RC Filter Phase Response As explained in the last section the phase response can introduce significant errors if the phase response of the LPFs on both Channel 1 and Channel 2 are not matched Phase mismatch can easily occur due to poor component tolerances in the LPF The lower the 3 dB frequency in the LPF antialias filter the more pronounced these errors will be at the fundamental frequency component or the line frequency Even with the corner frequency set at 4 8 kHz R 1 33 nF the phase errors due to poor component tolerances can be significant Figure 8 illus trates the point In Figure 8 the phase response for the simple LPF is shown at 50 Hz 1 1096 C 33 nF 10 Remember a phase shift of 0 2 can causes mea surement errors of 0 696 at low power factor This design uses resistors of 196 tolerance and capacitors of 1096 to
8. PONTIFICIA TESIS UNIVERSIDAD DEL PERU B TRANSFORMADOR DE CORRIENTE El transformador de corriente TC usa el principio de un transformador para convertir la alta corriente primaria a una corriente secundaria m s peque a El TC es com n entre los medidores de energ a de estado s lido de alta corriente Es un aparato pasivo que no necesita circuitos adicionales de control Adicionalmente el TC puede medir corrientes muy altas y consumir poca potencia El inconveniente con los TC se debe a su material ferr tico usado en el nucleo que se puede saturar cuando la corriente primaria es muy alta o cuando hay un componente importante de DC en la corriente Una vez magnetizado el n cleo contendr hist resis y SU precisi n se degradar a menos que ste se desmagnetice de nuevo C SENSOR DE EFECTO HALL Existen dos tipos principales de sensores de Efecto Hall anillo abierto open loop y anillo cerrado closed loop el segundo ofrece mejor precisi n y rangos din micos m s amplios pero a un costo mayor La mayor a de los sensores de Efecto Hall que se encuentran en medidores de energ a usan el disefio anillo abierto para lograr costos m s bajos El sensor de Efecto Hall tiene una excelente respuesta a la frecuencia y est capacitado para medir corrientes muy altas Sin embargo las desventajas incluyen un resultado con alta deriva por temperatura y la necesidad de circuitos externos de control Estos adicionado
9. THE OUTPUT WILL NOT BE FURTHER ATTENUATED 04443 041 Figure 41 Current Channel Signal Path Rev C Page 19 of 72 7758 di dt CURRENT SENSOR AND DIGITAL INTEGRATOR ic The di dt sensor detects changes in the magnetic field caused by the ac current Figure 42 shows the principle of a di dt current m 83 a MAGNETIC CREATED CURRENT DIRECTLY PROPORTIONAL TO CURRENT PHASE Degrees o A 4 AH ION ELECTROMOTIVE FORCE 90 T INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY di dt Jd Li 1k 10 100 FREQUENCY Hz 04443 042 md Figure 42 Principle of a di dt Current Sensor Figure 44 Combined Phase Response of the The flux density of a magnetic field induced by a current is Digital Integrator and Phase Compensator directly proportional to the magnitude of the current The changes in the magnetic flux density passing through a conductor loop generate an electromotive force EMF between the two ends of the loop The EMF is a voltage signal that is propor tional to the di dt of the current The voltage output from the di dt current sensor is determined by the mutual inductance between the current carrying conductor and the di dt sensor The current signal needs to be recovered from the di dt signal MAGNITUDE dB before it can be used An integrator is therefore necessary to restore the si
10. 1 This column specifies the read write capability of the register Read only register R W Register that can be both read and written Type decoder U unsigned S signed Rev C Page 63 of 72 7758 OPERATIONAL MODE REGISTER 0x13 The general configuration of the ADE7758 is defined by writing to the OPMODE register Table 18 summarizes the functionality of each bit in the OPMODE register Table 18 OPMODE Register Bit Bit Default Location Mnemonic Value Description 0 0 DISHPF The HPFs in all current channel inputs are disabled when this bit is set 1 DISLPF 0 The LPFs after the watt and VAR multipliers are disabled when this bit is set 2 DISCF 1 The frequency outputs APCF and VARCF are disabled when this bit is set 0 3to5 DISMOD By setting these bits ADE7758 s ADCs can be turned off In normal operation these bits should be left at Logic O DISMOD 2 0 Description 0 0 0 Normal operation 1 0 0 Redirect the voltage inputs to the signal paths for the current channels the current inputs to the signal paths for the voltage channels 0 0 1 Switch off only the current channel ADCs 1 0 1 Switch off current channel ADCs and redirect the current input signals to the voltage channel signal paths 0 1 0 Switch off only the voltage channel ADCs 1 1 0 Switch off voltage channel ADCs and redirect the voltage input signals to the current channel signal paths 0 1 1 Put the ADE7758 in sleep mode
11. 4 1 AUN ra gt y JA P ho os A gt T7 J ATI bea ri LN g gr e AST aue y gt Pa yt gh iu ES yO lt gt 4 4 Ru COR yd y E AN 559 NN VV Integrity Design amp Test 1 a gt Services Inc lt a gt Certificate of Compliance lt gt The following product was found to comply with the requirement stated below lt g gt when tested in accordance with the test procedures described in the accompanying test measurement report Reference report number 64567 c1 Manufacturer Analog Devices Inc a 804 Woburn Street Ce Wilmington MA 01887 Model Number Solid State Energy Meter Requirement EN 61000 4 2 1996 EN 61000 4 3 1996 ENV 50204 1993 and EN 61000 4 4 1995 pursuant to IEC 1036 1996 gt gt Applicable XXe Directive 89 336 EEC Approved By GER NET T SERV ON PTA TI ZEN lt a gt Christopher P Burch FERE 2 Immunity Section Manager wh Date E ces lt gt INTEGRITY JATEGRUIT ilit bs Lk Remarks Testing is performed using calibrated equipment traceable to the National Institute of Standards and Technology NIST p This certificate is valid for products tested as described in the accompanying test rep
12. 7758 REGISTERS COMMUNICATIONS REGISTER The data written to the communications register determines The communications register is an 8 bit write only register that whether the next operation is a read or a write and which controls the serial data transfer between the ADE7758 and the register is being accessed host processor All data transfer operations must begin with a cee Table 16 outlines the bit designations for the communications write to the communications register register Table 16 Commnumcayons Regist Bit Location Description 0106 AO to The seven LSBs of the communications register specify the register for the data transfer operation Table 17 lists the address of each ADE7758 on chip register 7 W R When this bit is a Logic 1 the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7758 When this bit is a Logic 0 the data transfer operation immediately following the write to the communications register is interpreted as a read operation DB2 Table 17 ADE7758 Register List Address Default A6 A0 R W Length Type Value Description 0x00 Reserved Reserved 0x01 AWATTHR Watt Hour Accumulation Register for Phase A Active power is accumulated over time in this read only register The AWATTHR register can hold a maximum of 0 52 seconds of active energy information with full scale analog inputs before i
13. CAL WATT AND VA GAIN ALL PHASES Q PF 1 CAL VAR GAIN ALL PHASES PF 0 INDUCTIVE CALIBRATE PHASE ALL PHASES PF 0 5 INDUCTIVE CALIBRATE ALL PHASES WATT OFFSET Imiy AND 1 CALIBRATE ALL PHASES VAR OFFSETS IMIN AND PF 0 INDUCTIVE 04443 080 Figure 80 Calibration Using Line Accumulation Rev C Page 48 of 72 Gain Calibration Using Line Accumulation Gain calibration is used for meter to meter gain adjustment APCF or VARCF output rate calibration and determining the Wh LSB VARh LSB and VAh LSB constant Step 0 Before performing the gain calibration the APCFNUM APCFDEN 0x45 0x46 and VARCFNUM VARCFDEN 0x47 0x48 values can be set to achieve the correct impulses kWh impulses kVAh or impulses kVARh using the same method outlined in Step 4 in the Gain Calibration Using Pulse Output section The calibration of x WG xVARG xVAG 0x2A through 0x32 is done with the line accumulation mode Figure 81 shows the steps involved in calibrating the gain registers using the line accumulation mode Step 1 Clear xWG xVARG and xVAG SET APCFNUM APCF DEN AND VARCFNUM VARCF DEN STEP 3 SET LYCMODE REGISTER STEP 4 SET ACCUMULATION TIME LINECYC STEP 5 SET MASK FOR LENERGY INTERRUPT SET UP SYSTEM FOR Vnom PF 1 CLEAR xWG xVAR xVAG SELECT PHASE FOR LINE PERIOD MEASUREMENT CONFIGURE FREQ 11 0 FORA LINE PERIOD MEASU
14. Consideraciones de diseno para los conectores externos e El plug de alimentaci n fue elegido por ser el m s adecuado para recibir una se al de 12VDC regulados y por consider rsele un est ndar dentro de la industria comercial e El conector RJ 45 se utiliz por ser el conector est ndar para la comunicaci n TCP IP Adem s de cumplir con las configuraciones recomendadas por la norma del protocolo 123458678 Oo OO nm fe o pa TEMPUS VI PARA LA COMUNICACION ETHERNET SE UTILIZO EL CONECTOR 45 Y CUMPLE EL ESTANDAR DE CONEXION CRUZADA ENTRE EQUIPO Y PC Figura 3 30 Conexi n a red EQUIPO PC Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD TESIS CATOLICA DEL PERU 12345678 12345678 CO E on 4 Lo TEMPUS VI HUB PARA LA COMUNICACION ETHERNET SE UTILIZO EL CONECTOR RJ 45 Y CUMPLE EL ESTANDAR DE CONEXION DIRECTA ENTRE EQUIPO Y ALGUN DISPOSITIVO REDIRECCIONADOR DE DATOS Figura 3 31 Conexi n a red EQUIPO HUB e C mo se mencion en la Secci n Etapa de expansi n P g 64 el sistema alimentar un equipo esclavo y se comunicar protocolo RS 485 Para cumplir con dichos requisitos se eligi el conector RJ 11 por su c modo manejo y facilidad de ensamblaje del conector a reo LOGICA PARA LA COMUNICACION 5 485 SE TIENE UN CONECTOR QUE PUEDE
15. Energy Accumulation Mode The active power accumulated in each watt hr accumulation register AWATTHR BWATTHR or CWATTHR depends on the configuration of the CONSEL bits in the COMPMODE register Bit 0 and Bit 1 The different configurations are described in Table 10 Table 10 Inputs to Watt Hr Accumulation Registers CONSEL 1 0 AWATTHR BWATTHR CWATTHR 00 VA x IA VC x IC 01 VA x IA IB VC x IC IB 10 VA x IA IB VC x IC 11 Reserved Reserved Reserved The contents of the watt hr accumulation registers are affected by both the current gain register IGAIN and the watt gain register of the corresponding phase IGAIN should not be used when using Mode 0 of CONSEL COMPMODE 1 0 Depending on the poly phase meter service the appropriate formula should be chosen to calculate the active energy The American ANSI C12 10 Standard defines the different configurations of the meter Table 11 describes which mode should be chosen in these different configurations Table 11 Meter Form Configuration ANSI Meter Form CONSEL d TERMSEL d 55 135 3 Wire Delta 0 3 5 0r 6 65 145 4 Wire Wye 1 7 85 155 4 Wire Delta 2 7 95 165 4 Wire Wye 0 7 ADE7 1758 Different gain calibration parameters are offered in the ADE7758 to cover the calibration of the meter in different configurations It should be noted that in CONSEL Mode 0d the IGAIN and WGAIN registers have the same effect on the end result However changing IGAIN
16. PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Medici n de potencia activa T ACTIVA EL VOLTAJE Y LA CORRIENTE SE DIGITALIZAN LUEGO SE MULTIPLICAN ENTRE SI Y FINALMENTE POR MEDIO DEL METODO DEL FPB SE OBTIENE LA Figura 3 4 Diagramas de bloques de la medici n de potencia activa e Medici n de potencia reactiva DESFASE DE 90 REACTIVA EL PROCESO ES SIMILAR AL APLICADO PARA DETERMINAR LA Pacriva CON LA DIFERENCIA QUE ANTES DE LA MULTIPLICACION DE SENALES EL VOLTAJE ES DESFASADO EN 90 Figura 3 5 Diagramas de bloques de la medici n de potencia reactiva e Medici n de potencia aparente FPB V VRMS Ref Bad LX FPB a gt 200 PARA EL CALCULO DE LA PAPARENTE SE HALLA PREVIAMENTE EL VALOR RMS DE LAS SE ALES DE VOLTAJE Y CORRIENTE PARA FINALMENTE MULTIPLICARLAS ENTRE Sl Figura 3 6 Diagramas de bloques de medici n de potencia aparente Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU En cuanto a su funcionamiento el ADE7758 realiza el c lculo de potencia mediante l gicas num rico matem ticas digitales en la Figura 3 7 se puede observar los pasos para el c lculo de la potencia activa FPA WATTHR 15 0 INTEGRADOR SENAL DE CORRIENTE DIGITAL D
17. amigos Gracias por ayudarme estar conmigo a lo largo de la carrera y aun despu s A Bobby Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis WARS TESIS PUCP ey UNIVERSID DEL PERU NDICE P g INTRODUCCI N X CAP TULO 1 LA ENERG A EN EL SECTOR DE CONSUMO ritenere tente tn tette testate tns ta rra 1 1 1 IMPORTANCIA DEL CONTROL DE LA ENERG A EL CTRICA 1 1 2 MEDIDORES DE PAR METROS EL CTRICOS 8 1 3 OBJETIVOS A _ _ 13 CAP TULO 2 TECNOLOG AS APLICABLES PARA LA MEDICI N DE LOS PAR METROS EL CTRICOS Y TRANSMISI N DE DATOS A 1 15 2 1 TECNOLOG AS PARA LA MEDICI N DE PAR METROS EL CTRICOS 15 2 2 EL M DULO DE CONTROL TARJETA TEMPUS VI 30 2 3 TECNOLOG AS PARA LA INTERCONEXI N ENTRE PERIF RICOS 91 24 CONCEPTUALIZACIONES GENERALES 33 2 5 MODELO TEORICO m 4 e un UE ___ 36 CAP TULO 3 DISENO E IMPLEMENTACI N DE LA INTERFAZ DIGITAL 28 3 1 ETAPA DE PRE PROCESAMIENTO DE DATOS mee 39 3 2 ETAPA DE VISUALIZACI N DE DAT
18. are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples For example the nominal maximum code of the voltage channel waveform samples with a full scale signal input at 60 Hz is 0x2748 see the Voltage Channel Sampling section Bit 13 to Bit 6 are Ox9D Therefore writing 0 9 to the SAG level register puts the SAG detection level at full scale and sets the SAG detection to its most sensitive value The detection is made when the content of the SAGLVL 7 0 register is greater than the incoming sample Writing 0x00 puts the SAG detection level at 0 The detection of a decrease of an input voltage is disabled in this case PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit Peak Voltage Detection Using the VPEAK Register The peak absolute value of the voltage waveform within a fixed number of half line cycles is stored in the VPEAK register Figure 58 illustrates the timing behavior of the peak voltage detection L2 L1 VOLTAGE WAVEFORM PHASE SELECTED BY PEAKSEL 2 4 IN MMODE REGISTER NO OF HALF LINE CYCLES SPECIFIED BY LINECYC 15 0 REGISTER CONTENT OF VPEAK 7 0 Figure 58 Peak Voltage Detection Using the VPEAK Register 04443 058 Note that the content of the VPEAK register is equivalent to Bit 6 to Bit 13 of the 16 bit voltage waveform sample At full scale analog input the voltage
19. 10V to 15V Enable INDUC Voltage VI 5 ans ed 5 5 V Continuous total power dissipation See Dissipation Rating Table Operating free air temperature range TA 22 0 C to 70 C Storage temperature Tange Teig saca e e a dr 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 All voltage values except differential input output bus voltage are with respect to network ground terminal DISSIPATION RATING TABLE TA lt 25 C DERATING FACTOR TA 70 C Ta 105 C PACKAGE POWERRATING ABOVET 25 C POWERRATING POWER RATING 725 mW 5 8 mW C 1100 mW 8 8 mW C 435 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 recommended operating conditions EL LLL MUN Supywdag Vogg a a v 200 bus terminal separately or common BI modos Vi
20. Criterios de selecci n Por efecto de ahorro de presupuesto se buscar un componente que permita la conexi n m s sencilla para los datos del UART del microcontrolador con una salida de datos infrarrojos en protocolo IrDA adem s de su disponibilidad en el mercado Componente seleccionado El componente seleccionado fue el MCP2120 Codificador Decodificador de infrarrojo de la compania Microchip Los datos de una UART est ndar se ingresan a este integrado el cual procesa los datos recibidos y los convierten en pulsos para enviar a un emisor de infrarrojos adicionalmente para la salida de datos se hace uso de un emisor receptor infrarrojo tambi n llamado transceptor ptico para el cual se ha seleccionado el IrDA transceiver de Sharp GP2W0110YPS Los datos recibidos por un receptor de infrarrojos como el elegido se ingresan al MCP2120 y son convertidos a datos para una UART est ndar Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP t lt UNIVERSIDAD CATOLICA DEL PERU La velocidad de transferencia en baudios o bits por segundo se define con unas entradas del integrado que permiten seleccionar entre un amplio rango de velocidades dependiendo tambi n de la frecuencia de reloj que se aplica al circuito B DISENO DE LA ETAPA Vcc 22pF 0 1uF GP2WO0110YPS VO BORA _ Generador de 22pF bau
21. Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU procesar mayores datos el ctricos por ejemplo el c lculo de arm nicos de la red y adicionalmente el efecto del ruido Flicker e el objetivo de comunicaci n con otros dispositivos se investig un modo de intercambio de datos infrarrojos denominado IrDA que actualmente se utiliza en PDAs y celulares La recomendaci n se enfoca en implementar el protocolo IrDA para utilizar las PALM a modo de control remoto especializado para el equipo Los datos de este modo de comunicaci n se explican en el Anexo B Comunicaci n IrDA Secci n Comunicaci n IrDA P g 3 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU CONCLUSIONES De la presente investigaci n se desprenden una serie de conclusiones relevantes no tan s lo enfocadas en temas de medici n de par metros el ctricos y comunicaciones sino que permiten reflexionar sobre situaciones planteamientos que en un principio no eran trascendentales y que finalmente afectaron la forma de ejecutar el trabajo mostrando as una forma de afrontar proyectos futuros como Ingeniero Electr nico e Se ha logrado desarrollar un sistema de control digital que a pesa
22. Test Severity Level 4 Test Voltage 8 kV 10 Discharges Very often no additional components are necessary to protect devices With a little care those components already required in the circuit can perform a dual role For example the meter must be protected from ESD events at those points where it comes in contact with the outside world e g the connection to the shunt Here the AD7755 is connected to the shunt via two LPFs anti alias filters which are required by the ADC see Antialias Filters section This RC filter can also be enough to protect against ESD damage to CMOS devices However some care must be taken with the type of components used For example the resistors should not be wire wound as the discharge will simply travel across them The resistors should also be physi cally large to stop the discharge arcing across the resistor In this design 1 8W SMD 1206 resistors were used in the antialias filters Two ferrite beads are also placed in series with the connection to the shunt A ferrite choke is particularly effective at slowing the fast rise time of an ESD current pulse The high frequency tran sient energy is absorbed in the ferrite material rather than being diverted or reflected to another part of the system The properties of ferrite are discussed later The PSU cir cuit is also directly connected to the terminals of the meter Here the discharge will be dissipated by the fer rite the line filter
23. this pin provides an output frequency that is directly proportional to the total reactive power The pulse width of VARPCF is 64 CLKIN if VARCFNUM and VARCFDEN are both equal If VARCFDEN is greater than VARCFNUM the pulse width depends on VARCFDEN The pulse width in this case is T x VARCFDEN 2 where is the period of the VARCF pulse and VARCFDEN 2 is rounded to the nearest whole number An exception to this is when the period is greater than 180 ms In this case the pulse width is fixed at 90 ms A digital to frequency converter DFC is used to generate the VARCE pulse output from the total reactive power The TERMSEL bits Bit 2 to Bit 4 of the COMPMODE register can be used to select which phases to include in the total reactive power calcu lation Setting Bit 2 Bit 3 and Bit 4 includes the input to the AVARHR BVARHR and CVARHR registers in the total reactive power calculation The total reactive power is signed addition However setting the SAVAR bit Bit 6 in the COMPMODE register enables absolute value calculation If the active power of that phase is positive no change is made to the sign of the reactive power However if the sign of the active power is negative in that phase the sign of its reactive power is inverted before summing and creating VARCF pulses This mode should be used in conjunction with the absolute value mode for active power Bit 5 in the COMPMODE register for APCF pulses The effects of setting t
24. voltaje anal gica sigue el mismo proceso de ajuste de ganancia y digitalizaci n siendo sus valores digitales a m xima escala 10322 o con signo y complemento a 2 0x2852 y OxD7AE para el m ximo y m nimo respectivamente que luego llega a una etapa en donde se puede hacer un ajuste de fase ante cualquier posible error inducido por los sistemas de baja potencia El FPA no est implementado en el canal de voltaje porque el FPA de la corriente es suficiente para eliminar el desplazamiento en DC Despu s las senales de corriente y voltaje se multiplican entre si para finalmente aplicar el m todo del filtro pasa bajos explicado el Cap tulo 2 Secci n Medidores de potencia activa digital P g 24 La acumulaci n del valor de la potencia activa total se almacena en un registro de 40 bits el cual es constantemente actualizado segun frecuencia del reloj del sistema sin embargo el valor entregado es el registro denominado WATTHR que contiene los 16 MSB del mencionado registro acumulador esta denominaci n la entrega el fabricante en su hoja de datos Anexo F Hojas t cnicas Hoja t cnica del ADE7758 Rev C Secci n Register P g 60 Sup ngase que se desea conocer cu l es el valor de energ a consumida en Watt hora cada vez que se llena el registro interno Para esto se necesita conocer con que valores de tensi n y corriente funcionar el dispositivo utilizando valores est ndar de medici n tensi n nominal de 220V corrien
25. 01 AVRMS x AIRMS 10 AVRMS x AIRMS 11 Reserved Reserved BVRMS x BIRMS AVRMS CVRMS 2 x BIRMS BVRMS x BIRMS ADE7 1758 CVAHR CVRMS x CIRMS CVRMS x CIRMS CVRMS x CIRMS Reserved 1 AVRMS BVRMS CVRMS are the rms voltage waveform and AIRMS BIRMS CIRMS are the rms values of the current waveform Energy Accumulation Mode The apparent power accumulated in each VA hr accumulation register AVAHR BVAHR or CVAHR depends on the con figuration of the CONSEL bits in the COMPMODE register Bit 0 and Bit 1 The different configurations are described in Table 14 The contents of the VA hr accumulation registers are affected by both the registers for the current gain IGAIN and rms voltage gain VRMSGAIN as well as the VAGAIN register of the corresponding phase IGAIN should not be used when using CONSEL Mode 0 COMPMODE 1 0 Apparent Power Frequency Output Pin 17 VARCF of the ADE7758 provides frequency output for the total apparent power By setting the bit Bit 7 of the WAVMODE register this pin provides an output frequency that is directly proportional to the total apparent power A digital to frequency converter DFC is used to generate the pulse output from the total apparent power The TERMSEL bits Bit 2 to Bit 4 of the COMPMODE register can be used to select which phases to include in the total power calculation Setting Bit 2 Bit 3 and Bit 4 includes the input to the AVAHR BVAHR and CVAHR regis
26. 3 7 L gica de funcionamiento del ADE7758 para el c lculo de potencia 43 3 8 Respuesta en frecuencia del filtro RC R 1 C 33 NF 46 3 9 FiltroI C Pasa DajOS exssknsztxiauotetezzizieven2zesexsaussaxbevestebudnnvex nue idad 46 3 10 Esquema circuital de la etapa de pre procesamiento de datos 47 3 11 Vista anterior y posterior de la etapa de pre procesamiento 48 3 12 Desacoplo magn tico con transformadores 50 3 13 Modo Lectura y Escritura desde el ADE7758 al microcontrolador 51 3 14 Esquema circuital la etapa de visualizaci n de datos 53 3 15 Visualizador AGC 16 2 I 7 REA o3 3 16 Vista anterior y posterior del m dulo de control _ 57 3 17 Microcontrolador ATmega128 Empaquetado TQFP64 58 3 18 Desarroll del software la plataforma _ 61 3 19 Diagrama de flujo del software 62 3 20 Esquema circuital de la etapa de ingreso de datos 63 3
27. 8 bits at a time with the most significant byte shifted out first Rev C Page 41 of 72 7758 The interrupt request output stays low until the interrupt routine reads the reset status register see the Interrupts section CALIBRATION reference meter or an accurate source is required to calibrate the ADE7758 energy meter When using a reference meter the ADE7758 calibration output frequencies APCF and VARCF are adjusted to match the frequency output of the reference meter under the same load conditions Each phase must be calibrated separately in this case When using an accurate source for calibration one can take advantage of the line cycle accumulation mode and calibrate the three phases simultaneously There are two objectives in calibrating the meter to establish the correct impulses kW hr constant on the pulse output and to obtain a constant that relates the LSBs in the energy and rms registers to Watt VA VAR hours amps or volts Additionally calibration compensates for part to part variation in the meter design as well as phase shifts and offsets due to the current sensor and or input networks Calibration Using Pulse Output The ADE7758 provides a pulsed output proportional to the active power accumulated by all three phases called Additionally the VARCF output is proportional to either the reactive energy or apparent energy accumulated by all three phases The following section describes
28. CVARHR represent the upper 16 bits of these internal registers This discrete time accumulation or summation is equivalent to integration in continuous time Equation 35 expresses the relationship Reactive Energy faldt Lim Daler r 35 T0 n 0 where n is the discrete time sample number T is the sample period Figure 72 shows the signal path of the reactive energy accumula tion The average reactive power signal is continuously added to the internal reactive energy register This addition is a signed operation Negative energy is subtracted from the reactive energy register The average reactive power is divided by the content of the VAR divider register before it is added to the corresponding VAR hr accumulation registers When the value in the VARDIV 7 0 register is 0 or 1 the reactive power is accumulated without any division VAROS 11 0 90 PHASE EEH HPF SHIFTING FILTER SIGN 26 LE mus LPF2 CURRENT SIGNAL i t 0x2851EC 0x00 0xD7AE14 VOLTAGE SIGNAL v t 0x2852 0x00 OxD7AE VARG 11 0 VARDIV 7 0 ADE7758 VARDIV is an 8 bit unsigned register that is useful to lengthen the time it takes before the VAR hr accumulation registers overflow Similar to reactive power the fastest integration time occurs when the VAR gain registers are set to maximum full scale that is OX7FF The time it takes before overflow can be scaled by writing to the VARDIV register and therefore it can be
29. DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 TYPICAL CHARACTERISTICS DRIVER DRIVER HIGH LEVEL OUTPUT VOLTAGE LOW LEVEL OUTPUT VOLTAGE VS VS HIGH LEVEL OUTPUT CURRENT LOW LEVEL OUTPUT CURRENT High Level Output Voltage V VoL Low Level Output Voltage V UN pw 0 20 40 60 80 100 120 High Level Output Current mA Low Level Output Current mA Figure 8 Figure 9 DRIVER RECEIVER DIFFERENTIAL OUTPUT VOLTAGE LOW LEVEL OUTPUT VOLTAGE vs VS OUTPUT CURRENT LOW LEVEL OUTPUT CURRENT Differential Output Voltage V VoL Low Level Output Voltage V 0 0 10 20 30 40 50 60 70 80 290 100 0 5 10 15 20 25 30 lo Output Current mA Low Level Output Current mA Figure 10 Figure 11 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 VoL Low Levcel Output Voltage V SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 TYPICAL CHARACTERISTICS RECEIVER RECEIVER LOW LEVEL OUTPUT VOLTAGE OUTPUT VOLTAGE VS VS FREE AIR TEMPERATURE ENABLE VOLTAGE Vip 0 2 V Load 8 to GND 5 25 V gt 5 5 5 4 75 5 5 O 0 0 0 5 1 1 5 2 2 5 3 TA Free Air Temperature C Vj Enable Voltage V Figure 12 Figure 13 RECEIVER OUTPUT VOLTAGE vs
30. ENABLE VOLTAGE VID 0 2V Load 1 to Vcc TA 25 Vo Output Voltage V 0 0 5 3 a es V Figure 14 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 9N75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 APPLICATION INFORMATION SN65176A SN65176A Up to 32 Transceivers e e NOTE A The line should be terminated at both ends in its characteristic impedance RT 20 Stub lengths off the main line should be kept as short as possible Figure 15 Typical Application Circuit 35 TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent 1 deems necessary to support this warranty Except where man
31. F 2mx RC R 1KOy 33 nF Se tiene una frecuencia de corte de y dise o l Entrada Salida Fe 3a x 1000 83x107 4822 877063Hz gt F 5Khz Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD TESIS CAT LICA DEL PERU C DISENO DE LA ETAPA CON CORRIENTE AVDD DVDD VBP VCP 4 CLKIN VM AVDD DVDD CON VOLTAJE SEGUN ANALOG DEVICES POR SEGURIDAD EL ADE7758 DEBE PRESENTAR FILTROS RC EN SUS ENTRADAS ANALOGICAS ADEMAS DE CIRCUITERIA EXTRA PARA ESTABILIZAR SU ALIMENTACION Y COMUNICACION SPI Figura 3 10 Esquema circuital de la etapa de pre procesamiento de datos El elemento b sico de sta etapa es el transductor de par metros el ctricos el 7758 Para el diseno se investig acerca de conexiones y topolog as de conexi n recomendadas por el fabricante en el Anexo F Hojas t cnicas AN 559 Application note Rev A Secci n Design goals P g 2 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis lt UNIVERSIDAD TESIS PUCP CATOLICA DEL PERU Posee tres entradas de corriente separadas en grupos de a dos un pin para la entrada positiva y un pin para la salida negativa de la corriente IAP IAN IBP IBN ICP ICN Para la medici n de los voltajes trifasicos el ADE7758 cuenta con t
32. For this example Iresr 10 A Vnom 220 V Veuttscate 500 V Truttscate 130 A 3200 impulses kWh Power Factor 1 and Frequency 50 Hz Clear APCFNUM 0x45 and write the calculated value to APCFDEN 0x46 to perform a coarse adjustment on the imp kWh ratio using Equation 45 through Equation 47 220 10 16 kHz x x 20 542 kHz NOMINAL 500 130 APCE 0 1 9556 H X COS 7 EXPECTED 1000 x 3600 542 Hz APCFDEN 1 9556 Hz With Phase A contributing to at Iresr Vnom and the unity power factor the example ADE7758 meter shows 2 058 Hz on the pulse output This is equivalent to a 5 2696 error from the reference meter value using Equation 49 2 058 Hz 1 9556 Hz 06 Error 19556Hz x 10096 5 2696 7 The AWG value is calculated to be 216 d using Equation 51 which means the value OxF28 should be written to AWG Rev C Page 45 of 72 7758 5 26 AWG 22 0 0244 2155 216 0xF28 Phase Calibration Using Pulse Output The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors Large phase errors should be compensated by adjusting the antialiasing filters The ADE77585 phase calibration is a time delay with different weights in the positive and negative direction see the Phase Compensation section Because a current transformer is a source of phase error a fixed nominal valu
33. PERCENT FULL SCALE CURRENT PERCENT FULL SCALE CURRENT Figure 12 APCF Error as a Percentage of Reading Gain 1 Figure 15 Reactive Energy Error as a Percentage of Reading Gain 1 with Internal Reference and Integrator Off over Temperature with External Reference and Integrator Off P t 0 25 ul E E te te 100 100 PERCENT T PERCENT FULL SCALE CURRENT Figure 13 Reactive Energy Error as a Percentage of Reading Gain 1 Figure 16 Reactive Energy Error as a Percentage of Reading Gain 1 over Temperature with Internal Reference and Integrator Off over Power Factor with External Reference and Integrator Off N 9 PF 0 25 C 3 0 4 0 866 25 em i E c cL m 0 866 40 C PF 0 866 25 0 01 0 1 10 100 PERCENT ane ate CURRENT LINE FREQUENCY Hz Figure 14 Reactive Energy Error as a Percentage of Reading Gain 1 Figure 17 Reactive Energy Error as a Percentage of Reading Gain 1 over Power Factor with Internal Reference and Integrator Off over Frequency with Internal Reference and Integrator Off Rev C Page 13 of 72 7758 0 10 0 3 0 08 0 2 0 06 5 ct 0 04 gt 0 1 o 0 02 c c t 2 02 0 0 E n y 2 0 02 O x D 0 1 a E 0 04 a 0 06 0 2 0 08 amp 0 10 5 0 3 5 0 01 0 1 1 10 100
34. PERCENT FULL SCALE CURRENT PERCENT FULL SCALE CURRENT Figure 24 Reactive Energy Error as a Percentage of Reading Gain 4 Figure 27 IRMS Error as a Percentage of Reading Gain 1 over Temperature with Internal Reference and Integrator On with Internal Reference and Integrator Off 72 2 E E te te 100 LINE FREQUENCY Hz PERCENT FULL SCALE CURRENT Figure 25 Active Energy Error as a Percentage of Reading Gain 4 Figure 28 IRMS Error as a Percentage of Reading Gain 4 over Frequency with Internal Reference and Integrator On with Internal Reference and Integrator On 2 mA E E te gt 100 LINE FREQUENCY Hz VOLTAGE V Figure 26 Reactive Energy Error as a Percentage of Reading Gain 4 Figure 29 VRMS Error as a Percentage of Reading Gain 1 over Frequency with Internal Reference and Integrator On with Internal Reference Rev C Page 15 of 72 7758 PERCENT ERROR 04443 030 PERCENT FULL SCALE CURRENT Figure 30 Apparent Energy Error as a Percentage of Reading Gain 1 over Temperature with Internal Reference and Integrator Off MEAN 5 55393 SD 3 2985 il CH 2 PhA GFESET mV 04443 031 6 8 10 12 Figure 31 Phase A Channel 1 Offset Distribution Rev C Page 16 of 72 HITS 12 CH a PhB Tm Figure 32 Phase B Channel 1 Of
35. and signal connections must cross this moat and Figure 22 shows how this can be safely achieved by using a ferrite bead Remember that fer rite offers a large impedance to high frequencies see Figure 21 ELECTRICAL FAST TRANSIENCE EFT BURST TESTING This testing determines the immunity of a system to conducted transients Testing is carried out in accordance with IEC1000 4 4 under well defined conditions The EFT pulse can be particularly difficult to guard against because the disturbance is conducted into the system via exter nal connections e g power lines Figure 23 shows the physical properties of the EFT pulse used in IEC1000 4 4 Perhaps the most debilitating attribute of the pulse is not its amplitude which can be as high as 4 kV but REV A AN 559 the high frequency content due to the fast rise times involved Fast rise times mean high frequency content which allows the pulse to couple to other parts of the system through stray capacitance etc Large differential signals can be generated by the inductance of PCB traces and signal ground These large differential sig nals could interrupt the operation of sensitive electronic components Digital systems are generally most at risk because of data corruption Analog elec tronic systems tend only to be affected for the duration of the disturbance TIME Figure 23 Single EFT Pulse Characteristics Another possible issue with conducted EFT is that the effects
36. and they must be corrected to perform accurate power calculations Rev C Page 23 of 72 7758 The errors associated with phase mismatch are particularly noticeable at low power factors The ADE7758 provides a means of digitally calibrating these small phase errors The ADE7758 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors The phase calibration registers APHCAL BPHCAL and CPHCAL are twos complement 7 bit sign extended registers that can vary the time advance in the voltage channel signal path from 153 6 us to 75 6 us CLKIN 10 MHz respectively Negative values written to the PHCAL registers represent a time advance and positive values represent a time delay One LSB is equivalent to 1 2 us of time delay or 2 4 us of time advance with a CLKIN of 10 MHz With a line frequency of 60 Hz this gives a phase resolution of 0 026 360 x 1 2 us x 60 Hz at the fundamental in the positive direction delay and 0 052 in the negative direction advance This corresponds to a total correction range of 3 32 to 1 63 at 60 Hz Figure 56 illustrates how the phase compensation is used to remove a 0 1 phase lead in IA of the current channel from the external current transducer To cancel the lead 0 1 in the current channel of Phase A a phase lead must be introduced into the corresponding voltage channel The resolution of the phase ad
37. www analog com techsupt application_notes ad7755 64567_c1 pdf A copy of the certification issued for the design is shown in the test results section of this application note PCB DESIGN Both susceptibility to conducted or radiated electromag netic disturbances and analog performance were considered at the PCB design stage Fortunately many of the design techniques used to enhance analog and mixed signal performance also lend themselves well to improving the EMI robustness of the design The key idea is to isolate that part of the circuit that is sensitive to noise and electromagnetic disturbances Since the AD7755 carries out all the data conversion and signal processing the robustness of the meter will be deter mined to a large extent by how protected the AD7755 is In order to ensure accuracy over a wide dynamic range the data acquisition portion of the PCB should be kept as quiet as possible i e minimal electrical noise Noise 14 will cause inaccuracies in the analog to digital conver sion process that takes place in the AD7755 One common source of noise in any mixed signal system is the ground return for the power supply Here high frequency noise from fast edge rise times can be coupled into the analog portion of the PCB by the common imped ance of the ground return path Figure 34 illustrates the mechanism ANALOG CIRCUITRY DIGITAL CIRCUITRY GROUND COMMON IMPEDANCE 2 t
38. 0 01 100 PERCENT FULL SCALE CURRENT PERCENT FULL SCALE CURRENT Figure 18 Reactive Energy Error as a Percentage of Reading Gain 1 Figure 21 Active Energy Error as a Percentage of Reading Gain 4 over Supply with Internal Reference and Integrator Off over Temperature with Internal Reference and Integrator On 0 3 0 5 0 4 0 2 0 3 S 01 02 5 C 04 0 0 v E E z uL A 0 1 s 0 3 2 0 4 TNS _ amp E d Nnm 0 3 5 0 5 5 0 01 100 0 01 0 1 1 10 100 PERCENT FULL SCALE CURRENT PERCENT FULL SCALE CURRENT Figure 19 Reactive Energy Error as a Percentage of Reading over Gain Figure 22 Active Energy Error as a Percentage of Reading Gain 4 with Internal Reference and Integrator Off over Power Factor with Internal Reference and Integrator On 0 2 ES _ 0 2 PF 0 866 25 C PF 0 866 25 C get S i PERCENT ERROR o PERCENT ERROR 95 o C 04 5 0 8 3 0 01 0 1 1 10 100 0 01 0 1 1 10 100 PERCENT FULL SCALE CURRENT 9 6 PERCENT FULL SCALE CURRENT Figure 20 VARCF Error as a Percentage of Reading Gain 1 Figure 23 Reactive Energy Error as a Percentage of Reading Gain 4 with Internal Reference and Integrator Off over Power Factor with Internal Reference and Integrator On Rev C Page 14 of 72 ADE7 1758 2 72 E E te te 0 01 0 1 1 10 100 0 100
39. 1 1 1 Put the ADE7758 in power down mode reduces Alpp to 1 mA typ 6 SWRST 0 Software Chip Reset A data transfer to the ADE7758 should not take place for at least 18 us after a software reset 7 RESERVED 0 This should be left at O MEASUREMENT MODE REGISTER 0x14 The configuration of the PERIOD and peak measurements made by the ADE7758 is defined by writing to the MMODE register Table 19 summarizes the functionality of each bit in the MMODE register Table 19 MMODE Register Bit Bit Default Location Mnemonic Value Description 0 to 1 FREOSEL 0 These bits are used to select the source of the measurement of the voltage line frequency FREQSEL1 FREQSELO Source 0 0 Phase 0 1 Phase B 1 0 Phase 1 1 Reserved 2to4 PEAKSEL 7 These bits select the phases used for the voltage and current peak registers Setting Bit 2 switches the IPEAK and VPEAK registers to hold the absolute values of the largest current and voltage waveform over a fixed number of half line cycles from Phase A The number of half line cycles is determined by the content of the LINECYC register At the end of the LINECYC number of half line cycles the content of the registers is replaced with the new peak values Similarly setting Bit 3 turns on the peak detection for Phase B and Bit 4 for Phase C Note that if more than one bit is set the VPEAK and IPEAK registers can hold values from two different phases that is the voltage and current peak are independent
40. 1 13 02 kSPS CLKIN 3 256 1 0 6 51 kSPS CLKIN 3 512 1 1 3 25 kSPS CLKIN 3 1024 7 Setting this bit to Logic 1 switches the VARCF output pin to an output frequency that is proportional to the total apparent power VA In the default state Logic 0 the VARCF pin outputs a frequency proportional to the total reactive power VAR Rev C Page 65 of 72 7758 COMPUTATIONAL MODE REGISTER 0x16 The computational method of the ADE7758 is defined by writing to the COMPMODE register Table 21 summarizes the functionality of each bit in the COMPMODE register Table 21 COMPMODE Register Bit Bit Default Location Mnemonic Value Description 0101 CONSEL These bits are used to select the input to the energy accumulation registers CONSEL 1 0 11 is reserved IB and IC are IB and IC phase shifted by 90 respectively Registers CONSEL 1 0 00 CONSEL 1 0 01 CONSEL 1 0 10 AWATTHR VA x IA VA x IA IB VA x IA IB BWATTHR VB x IB 0 0 CWATTHR VC x IC VC x IC IB VC x IC AVARHR VA x VA x IA IB VA x IA IB BVARHR VB x IB 0 0 CVARHR VC x IC VC x IC IB VC x IC AVAHR 5 X 5 VArms X 5 VArms X Arms BVAHR VBnus X 1 VArms VCnus 2 IBnus VArms X 1 CVAHR 5 X ICnus 5 X ICnus 5 X ICnus 2to4 TERMSEL These bits are used to select the phases to be included in the APCF and VARCF pulse outputs Setting Bit 2 selects Phase A the inpu
41. 21 Bus diferencial de datos SN75176 65 3 22 Esquema circuital de la comunicaci n RS 485 etapa de expansi n 66 3 23 Vista anterior y posterior de la comunicaci n RS 485 67 324 REIEHKI9F de gt 70 3 25 Esquema circuital de los actuadores Etapa de expansi n 70 3 26 Actuadores en la tarjeta de componentes 71 3 27 Transistor en modo Colector abierto 72 3 28 Vista y descripci n de los conectores externos 73 3 29 Vista y descripci n de los conectores internos 74 3 30 Conexi n a red EQUIPO memes nnne nns 74 3 31 Conexi n a red EQUIPO enne nn nnn nnns 75 3 32 Conector 11 externo e ence ee ne eee ene nehmen snas 75 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis TESIS PUCP Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura 3 33 Bloque Terminal a re
42. B and Phase zero crossings are respectively included when counting the number of half line cycles by setting ZXSEL 0 2 bits Bit 3 to Bit 5 in the LCYCMODE register Any combination of the zero crossings from all three phases can be used for counting the zero crossing Only one phase should be selected at a time for inclusion in the zero crossings count during calibration see the Calibration section The number of zero crossings is specified by the LINECYC register LINECYC is an unsigned 16 bit register The ADE7758 can accumulate active power for up to 65535 combined zero crossings Note that the internal zero crossing counter is always active By setting the LWATT bit the first energy accumulation result is therefore incorrect Writing to the LINECYC register when the bit is set resets the zero crossing counter thus ensuring that the first energy accumulation result is accurate At the end of an energy calibration cycle the LENERGY bit Bit 12 in the STATUS register is set If the corresponding mask bit in the interrupt mask register is enabled the IRQ output also goes active low thus the IRQ can also be used to signal the end of a calibration Because active power is integrated on an integer number of half line cycles in this mode the sinusoidal component is reduced to 0 eliminating any ripple in the energy calculation Therefore total energy accumulated using the line cycle accumulation mode is E t V
43. COMPMODE 1 0 Phase C Current Gain Register Not for use with Mode 0 of CONSEL COMPMODE 1 0 Phase A Watt Gain Register The range of the watt calculation can be adjusted by writing to this register It has an adjustment range of 50 with a resolution of 0 0244 LSB Phase B Watt Gain Register Phase C Watt Gain Register Phase A VAR Gain Register The range of the VAR calculation can be adjusted by writing to this register It has an adjustment range of 50 with a resolution of 0 0244 LSB Phase B VAR Gain Register Phase C VAR Gain Register Phase A VA Gain Register The range of the VA calculation can be adjusted by writing to this register It has an adjustment range of 50 with a resolution of 0 0244 LSB Phase B VA Gain Register Phase Gain Register Phase A Voltage RMS Offset Correction Register Phase B Voltage RMS Offset Correction Register Phase C Voltage RMS Offset Correction Register Phase A Current RMS Offset Correction Register Phase B Current RMS Offset Correction Register Phase C Current RMS Offset Correction Register Phase A Watt Offset Calibration Register Phase B Watt Offset Calibration Register Phase C Watt Offset Calibration Register Phase A VAR Offset Calibration Register Phase B VAR Offset Calibration Register Phase C VAR Offset Calibration Register Phase A Phase Calibration Register The phase relationship between the current and voltage channel can be adjusted by writing t
44. CONTENER INFORMACION Y ALIMENTACION Figura 3 32 Conector RJ 11 externo Se observa que el conector RJ 11 posee los pines de comunicaci n serial diferencial RS 485 ademas de un par de pines de denominados Vinput y GND que ser n la alimentaci n para el equipo a expandir Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD TESIS CATOLICA DEL PERU e Se eligieron los Bloques terminales para los conectores de pre procesamiento de actuadores pues constan de dos partes acoplables entre si una para la base de la tarjeta de componentes y una a rea esto otorga comodidad para la interconexi n de las etapas adem s de cumplir con requerimientos el ctricos del sistema PARA LA ETAPA DE PRE PROCESAMIENTO DE DATOS SE UTILIZARON UNOS CONECTORES DENOMINADOS BLOQUES TERMINALES CON LA FINALIDAD DE BRINDAR COMODIDAD AL USUARIO Figura 3 33 Bloque Terminal a reo y base Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Consideraciones de diseno para los conectores internos Los conectores internos del m dulo del sistema permiten comunicar las etapas de pre procesamiento de datos expansi n y conectores externos con el m dulo de control En la Figura 3 34 se puede observar los co
45. DEL MODULO DEL SISTEMA VISTA DE COMPONENTES EN BOTTOM DESARROLLADO EN ORCAD RELEASE 9 1 LAYOUT tu AUi FT har sa Tr ria 13 3 Manli ae B E M Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU ANEXO F HOJAS T CNICAS En esta secci n se presentan los res menes y p ginas m s importantes de las hojas t cnicas de los siguientes dispositivos y documentos e ADE7758 e 128 e SN75176 e AN 559 Antialias filter Las versiones completas de las hojas de datos y especificaciones se encuentran en el CD de tesis Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU FUENTES 1 MINISTERIO DE ENERG A Y MINAS PERU 2005 Compendio de normas del sub sector electricidad http www minem gob pe electricidad index asp 2 The ABB Group 2001 October ODIN Meter An electricity energy meter from ABB Technical documentation http www abb nl GLOBAL NLABB NLABB0O32 NSF viewunid 7209F451A86595 15C1256B82004C3D80 file Odin meter E pdf Consultado 25 Oct 2005 3 KARCZ ANDRES M 1977 Fundamentos de metrolog a electr nica Tomo 111 Potencia y energ a Ediciones T cnicas Marcombo S A Boixareu edit
46. Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Si la frecuencia de corte del filtro pasa bajos es mucho menor que la frecuencia fundamental esta soluci n realiza un movimiento de fase de 90 en toda frecuencia mayor a la frecuencia fundamental Y al hacer esto realiza una atenuaci n de esta frecuencia 20dB d cada Esta soluci n es susceptible a la variaci n de la frecuencia de l nea pero con una compensaci n de la atenuaci n de la ganancia con la frecuencia de l nea puede reducir el efecto desfavorable en el c lculo En la Figura 2 8 el segundo FPB se encuentra para eliminar cualquier inserci n de ruido en la medici n Medidores de potencia aparente anal gica Es posible calcular la energ a aparente si el factor de potencia es constante fdp a partir de los valores de Watts hora P y Var hora Q var Q Ecuaci n 4 1 oin embargo si el fdp no es constante este m todo puede producir errores oe han propuesto diversos dispositivos para la medici n directa de la energ a aparente En una clase est n aquellos en los que el fdp del medidor se hacer m s o menos igual al fdp de l nea esto se logra insertando un miembro m vil en la estructura del polo de la bobina de voltaje que desplaza el flujo resultante cuando cambia el fdp de l nea En otra se emplea autotransformadores con los elementos de voltaje para obtener un fdp en el m
47. El hecho de competir a llevado a diversas companias la mentalidad de dar mejores productos y o servicios tener mejores sistemas de producci n contar con personal id neo para la labor etc pero todo ello a bajos costos de producci n tal y como lo define CEDSAL Jas empresas han de buscar la manera de reducir los costos asociados con el uso de los recursos naturales y la energ a para lo que han de disefiar nuevos sistemas procesos y productos que reduzcan el impacto ambiental y agreguen valor para los consumidores y la sociedad Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Este proceso se fomenta mejor a trav s de una combinaci n de instrumentos econ micos y autorregulaci n Empresa privada y sentido com n 1996 Esta definici n muestra claramente que la realidad comercial no escapa al control eficiente de la energ a el ctrica la necesidad de cuantificar el consumo energ tico para facturar sus gastos en distintos periodos de producci n muestra lo importante de contar con un medidor de energ a Hay que tener presente que para este sector de consumo la versatilidad y exactitud de sus sistemas se vuelve b sico para la maximizaci n de beneficios por ello bucar n contar con equipos que se encuentren disenados acorde a sus necesidades y que puedan responder ante su cambiante mundo come
48. Figure 76 Calibration Using Pulse Output Gain Calibration Using Pulse Output For calibrating VAR gain the registers in Equation 50 through Gain calibration is used for meter to meter gain adjustment Equation 52 should be replaced by VARCENUM 0x47 APCF or output rate calibration and determining the VARCFDEN 0x48 and xVARG 0x2D to 0x2F For VAGAIN Wh LSB VARh LSB and VAh LSB constant The registers used they should be replaced by VARCFNUM 0x47 VARCFDEN for watt gain calibration are APCFNUM 0x45 APCFDEN 0x48 and xVAG 0x30 to 0x32 0x46 and x WG 0x2A to 0x2C Equation 50 through Equation 52 show how these registers affect the Wh LSB constant and the APCF pulses Figure 77 shows the steps for gain calibration of watts VA or VAR using the pulse outputs Rev C Page 43 of 72 7758 SELECT VAR FOR VARCF OUTPUT ALL PHASES VAR GAIN CALIBRATED SET UP PULSE OUTPUT FOR PHASE A B ORC SELECT PHASE A B OR C FOR LINE PERIOD MEASUREMENT VARCFNUM VARCFDEN SET TO CALCULATED VALUES ET VARCFNUM VARCFDEN TO CALCULATED VALUES SET UP SYSTEM FOR 0 INDUCTIVE CALCULATE AND WRITE TO xVARG ENABLE APCF AND VARCF PULSE OUTPUTS SELECT VA FOR VARCF OUTPUT CLEAR GAIN REGISTERS xWG xVAG xVARG o m v gt ALL PHASES VA AND WATT GAIN CAL SET UP PULSE OUTPUT FOR PHASE A
49. Generator IEC1000 4 5 Figure 31 shows the generator voltage and current out put waveforms The characteristics of the combination wave generator are Open Circuit Voltage 0 5 kV to at least 4 0 kV Waveform as shown in Figure 31 Tolerance on open circuit voltage is 10 Short Circuit Current 0 25 kA to 2 0 kA Waveform as shown in Figure 31 Tolerance on short circuit current is 10 Repetition rate of a least 60 seconds REV A N 3kV 1 5kA 2kV T 1 0kA T 0 5kA OV 0A Figure 31 Open Circuit Voltage Short Circuit Current The MOV is very effective in suppressing these kinds of high energy long duration surges Figure 32 shows the voltage across the MOV when it is connected to the gen erator as shown in Figure 30 Also shown are the current and instantaneous power waveform The energy absorbed by the MOV is readily estimated using the rectangle method as shown 1 0kV T2 0kA T 1 5MW 0 8kV 1 5kA 0 6kV 0 4kV 0 2kV OV 0A OW 0 50 100 150 200 250 300 Figure 32 Energy Absorbed by MOV During 4 kV Surge Derating the MOV Surge Current The maximum surge current and therefore energy absorbed that an MOV can handle is dependant on the number of times the MOV will be exposed to surges over its lifetime The life of an MOV is shortened every time it is exposed to a surge event The data sheet for an MOV device will list the maximum nonrepetitive surge curren
50. LA ETAPA DE VISUALIZACION Y LA ETAPA DE INGRESO DE DATOS Figura 3 43 Implementaci n f sica del proyecto de tesis EN LA FIGURA SE MUESTRA LA CONEXION DE TODO EL SISTEMA DE IZQUIERDA A DERECHA EL MODULO DEL SISTEMA DE CONTROL Y ETAPAS DE INGRESO SALIDA DE DATOS Figura 3 44 Implementaci n f sica del proyecto de tesis Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis CAP TULO 4 EVALUACI N DE RESULTADOS 4 1 DESARROLLO DEL PROTOTIPO De los m dulos considerados en el sistema de control digital para medici n e M dulo del sistema Investigado dise ado e implementado como proyecto de contiene la l gica para medici n expansi n y alimentaci n xs CER DN COMUNIBACION Me Li PRE PROCESAMIENTO DE DATOS PROCESAMIENTO COMUNICACION DE DATOS TCP IP temen EL MODULO DEL SISTEMA DESARROLLADO CON TODAS SUS ETAPAS PRESENTADO POR LAS VISTAS ANTERIOR Y POSTERIOR Figura 4 1 M dulo del sistema Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis tesis ae ME V ian EDT epum E PONTIFICIA m TESIS PUCP UNIVERSIDAD DEL PERU e Teclado y LCD Implementaci n partir de su dise o simple de conexi n M dulo de control Facilitado por la empresa Sistem
51. PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Medidores trif sicos Hace referencia a los medidores que son dise ados para calcular el consumo de par metros el ctricos en un sistema de distribuci n trif sico de 3 hilos 2 Fases y un Neutro y de 4 hilos 3 Fases y un Neutro LOS MEDIDORES TRIFASICOS PARA SISTEMAS DE 3 HILOS UTILIZAN EL METODO DE LOS DOS MEDIDORES PARA CALCULAR LA POTENCIA Figura 2 10 Conexi n de un medidor del tipo trif sico 3 fases LOS MEDIDORES TRIFASICOS PARA SISTEMAS DE 4 HILOS UTILIZAN TRES MEDIDORES MONOFASICOS PARA CALCULAR LA POTENCIA Figura 2 11 Conexi n de un medidor del tipo trif sico 3 fases 1 neutro Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP T UNIVERSIDAD DEL PERU 22 EL M DULO DE CONTROL TARJETA TEMPUS VI El proyecto de tesis contar con una etapa de control digital que estar cargo del m dulo de procesamiento de datos y comunicaciones TEMPUS VI desarrollada en el pa s por una empresa privada Actualmente este m dulo viene siendo aplicado en dispositivos de marcaci n de personal y control de acceso sin embargo por la versatilidad de su microcontrolador interno ATmega128 y por su capacidad de comunicaci n TCP IP se prev la capacidad de ser utilizada para multiples finalidades no contempladas en su actual funcionamiento LA APLICA
52. Renumbered Subsequent Figures 33 Changes to Reactive Power Frequency Output Section 37 Added Figure 73 Renumbered Subsequent Figures 38 Change to Gain Calibration Using Pulse Output Example 44 Changes to Equation 45 Changes to Example Phase Calibration of Phase A Using Pulse Output ento ERES CENT PRIOR EOM NW 45 Changes to Equations 56 and 57 sss 53 Addition to the ADE7758 Interrupts Section 54 Changes to Example Calibration of RMS Offsets 54 Addition 20e aee tn ante RU 66 1 04 Revision 0 Initial Version Rev C Page 3 of 72 7758 GENERAL DESCRIPTION continued from Page 1 The ADE7758 has a waveform sample register that allows access to the ADC outputs The part also incorporates a detection circuit for short duration low or high voltage variations The voltage threshold levels and the duration number of half line cycles of the variation are user programmable A zero crossing detection is synchronized with the zero crossing point of the line voltage of any of the three phases This information can be used to measure the period of any one of the three voltage inputs The zero crossing detection is used inside the chip for the line cycle energy accumulation mode This mode permits faster and more accurate calibration by synchronizing the energy accumulation with an integer number of
53. TESIS UNIVERSIDAD DEL PERU Respecto a la utilidad del proyecto sta se extiende al campo comercial puesto que la integraci n del proyecto de tesis como Sistema de control digital a un Sistema mayor de medici n de energ a el ctrica con comunicaci n en tiempo real dar versatilidad a los procesos industriales convirti ndose en un factor clave a nivel econ mico por el control eficiente del consumo el ctrico que posteriormente se ver reflejado en mejoras de los costos de producci n Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis Vr 2 PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU INDICE P g ANEXO A CONECTORES SENE 1 COMUNICACI N IRDA occccccccccccecsssssecccccccccccucceceeseneesssnccueccccesessusunuusesecsnccseceseesavauausessnnsenensusesueeenseneeess 3 TRANSDUCTOR IrDA anni 3 DISE O DE LA ETAPA amp amp 94 MEL E B ____ _ 4 PROGRAMACION PARA PDAS 5 ANEXO C TECNOLOGIAS PARA MEDICI N DE CORRIENTE 9 SHUNT DE CORRIENTE DE BAJA RESISTENCIA aaaea aaea Reese nere nnd 9 TRANSFORMADOR DE CORRIENTE 10 SENSOR DE REG OMA NENNEN cc 10 BOBINA GU QE ux QUU uU EE __ 11 ANEXO D DIAGRAMA DE FLUJO PARA EL DESARROLLO DEL SISTEMA ennemis 14 AN
54. TESIS PUCP UNIVERSIDAD DEL PERU e Opciones de control para el usuario configuraciones a nivel programador uso de niveles de seguridad textos a visualizar en el LCD control para los actuadores entre otras funcionalidades Respecto al diseno los pines que ser n necesarios del microcontrolador e Teclado 4x4 ingreso de datos 8 E S e LCD Visualizador 6 E S e Indicadores luminosos 4 E S temporizador opcional Comunicaci n SPI 4 MISO MOSI SCK SS e Interrupci n 1 Interrupci n externa IRQ e Comunicaci n serial RS 485 3 TX RX y E S e Manejo de actuadores 2 Open Collector Rel 1 y 2 e Comunicaci n TCP IP Conector RJ 45 8 pines Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados olvide citar esta tesis ENER aT iy PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU B L GICA DE CONTROL Descripci n En el proyecto de tesis se ha considerado la programaci n por ser un punto importante para el desarrollo del mismo esta l gica control se basa en un lenguaje de programaci n de bajo nivel tambi n denominado c digo assembler Por caracter sticas del software programador y por su dominio se trabaj con el programa que provee el fabricante del microcontrolador AVRstudio Consideraciones de diseno Como la tarjeta TEMPUS VI ya posee un firmware incorporado para agregar la nueva l gica de control s
55. UART 485 el SN75176 se puede conectar directamente a los pines de comunicaci n digital con el microcontrolador y a la salida del bus diferencial sin necesidad de contar con elementos resistivos o filtros de acoplo A excepci n del pin 6 A que posee un filtro para mejorar la recepci n por el bus Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU B ACTUADORES Descripci n Los actuadores ser n elementos o conjuntos de elementos cuya funci n ser realizar una funci n espec fica a partir de un comando recibido esto puede ser abrir o cerrar puertas activar o desactivar alarmas encender o apagar luminarias entre otros Criterios de selecci n Al dise arse un m dulo que recibe voltajes DC que pueden ser 5 o 12 voltios se hace l gico el uso de un componente que pueda trabajar con dichos voltajes de trabajo Con el fin del control de acceso el componente deber manejar dos estados encendido apagado soportar el paso de voltajes AC sobre sus pines de contacto y niveles de amperaje m ximos de Componente seleccionado De los criterios de selecci n el tipo de componente adecuado para el proyecto es el actuador de contacto tambi n conocido como Este es un dispositivo electromec nico que funciona como un interruptor controlado por un circuito el ctrico el que por med
56. an interrupt was caused by a SAG on the line voltage of the Phase B Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C Indicates a detection of a rising edge zero crossing in the voltage channel of Phase A Indicates a detection of a rising edge zero crossing in the voltage channel of Phase B Indicates a detection of a rising edge zero crossing in the voltage channel of Phase C In line energy accumulation indicates the end of an integration over an integer number of half line cycles LINECYC See the Calibration section Indicates that the 5 V power supply is below 4 V Enables a software reset of the ADE7758 and sets the registers back to their default values This bit in the STATUS or RSTATUS register is logic high for only one clock cycle after a reset event Indicates that an interrupt was caused when the selected voltage input is above the value in the VPINTLVL register Indicates that an interrupt was caused when the selected current input is above the value in the IPINTLVL register Indicates that new data is present in the waveform register Indicates that an interrupt was caused by a sign chang
57. and provides a means of quickly verifying meter functionality and accuracy in a production environment The meter is calibrated by varying the line voltage attenuation using the resistor network R5 to R14 AN 559 LOAD o y Vpp 73 K1 jets ES TO IMPULSE COUNTER 7 12 c13 STEPPER MOTOR 3 ml v e O O OK5 gt AVDD AC DC DVDD R20 C15 100 imp kWhr Ko mie P24 9 NC I R19 P23 S ME V1P p22 R18 CALIBRATION REVPQ P20 D1 LED 00 RESISTOR R2 La P18 Vpp CLKOUTQ E P7 Y1 E g CALIBRATION buon ON y Eis K7 NETWORK E17 ale rer Y 59935 IYA 3200 imp kWhr P8 I A bes 5G P9 nd PE o R14 J10 V C4 2 J13 PS2501 1 AE ma ey bus O O d aig a Q REFin ouT 12 C7 J3 R7 nio us y C5 C6 V y y 2 R6 U4 Y O o 99 jeng X ent fra 16 L O 1 _ 285 Rio J6 q EXTERNAL a NC NO CONNECT y 9 REFERENCE OPTIONAL I i or 1 JUMPERS USE 00 RESISTOR R15 R16 POWER SUPPLY NEUTRAL K3 C17 R21 D2 alu Vpp 7805 Y 5V PHASE C16 MOV1 D3 2 3 6 7 72 K4 Q 220V Figure 1 Simple Single Phase Watt Hour Meter Based on the AD7755 DESIGN EQUATIONS The AD7755 produces an output frequency that is pro portional to the time average value of the product of two voltage signals The input voltage signals are applied at V1 and V2 The detailed functionality of the AD7755
58. before it is added to the corresponding watt hr accumulation registers When the value in the WDIV 7 0 register is 0 or 1 active power is accumulated without division WDIV is an 8 bit unsigned register that is useful to lengthen the time it takes before the watt hr accumulation registers overflow Figure 67 shows the energy accumulation for full scale signals sinusoidal on the analog inputs The three displayed curves show the minimum time it takes for the watt hr accumulation register to overflow when the watt gain register of the corre sponding phase equals to 0x7FE 0x000 and 0x800 The watt gain registers are used to carry out a power calibration in the ADE7758 As shown the fastest integration time occurs when the watt gain registers are set to maximum full scale that is OX7FF This is the time it takes before overflow can be scaled by writing to the WDIV register and therefore can be increased by a maximum factor of 255 Note that the active energy register content can roll over to full scale negative 0x8000 and continue increasing in value when the active power is positive see Figure 66 Conversely if the active power is negative the energy register would under flow to full scale positive Ox7FFF and continue decreasing in value By setting the AEHF bit Bit 0 of the interrupt mask register the ADE7758 can be configured to issue an interrupt IRQ when Bit 14 of any one of the three watt hr accumulation registers has
59. calculation The total active power is signed addition However setting the ABS bit Bit 5 in the COMPMODE register enables the absolute only mode that is only the absolute value of the active power is considered The output from the DFC is divided down by a pair of frequency division registers before being sent to the APCF pulse output Namely APCFDEN APCFNUM pulses are needed at the DFC output before the APCF pin outputs a pulse Under steady load conditions the output frequency is directly proportional to the total active power The pulse width of APCF is 64 CLKIN if APCFNUM and APCFDEN are both equal If APCFDEN is greater than APCFNUM the pulse width depends on APCFDEN The pulse width in this case is T x APCFDEN 2 where T is the period of the APCF pulse and APCFDEN 2 is rounded to the nearest whole number An exception to this is when the period is greater than 180 ms In this case the pulse width is fixed at 90 ms Rev C Page 33 of 72 7758 The maximum output frequency APCFNUM 0x00 and APCFDEN 0x00 with full scale ac signals on one phase is approximately 16 kHz The ADE7758 incorporates two registers to set the frequency of APCF 11 0 and APCFDEN 11 0 These are unsigned 12 bit registers that can be used to adjust the frequency of APCF by 1 2 to 1 with a step of 1 2 For example if the output frequency is 1 562 kHz while the contents of APCFDEN are 0 0x000 then the output frequency
60. call SPI MasterInit HemoryLlazoa doeventz Hemorylaza VritesPI LeeParametro RegistroSPcr 0 out SPCR R16 LeeParametro RegistroSPCR 1 eut SPSR R16 j R165 SPSR Limpio SPIF 216 SPDR PORTE 0 RetardosPI F16 SPIcomando Big sn caeg Ox000000 0x007404 0506 11446 31952 131072 dseg 0x000100 Ox0010be 4050 4050 4096 eseg Ox000000 n 4096 Assenbly complete 0 errors 0 warnings 3 paid message S Find in Files Ml breakpoints and Tracepoints LA LOGICA DE CONTROL QUE EN EL MICROCONTROLADOR ATMEGA128 SE DESARROLLA EN LENGUAJE ASSEMBLER MEDIANTE UN ENTORNO VISUAL LLAMADO AVRSTUDIO 4 Figura 3 18 Desarroll del software en la plataforma AVRstudio e El diagrama de flujo de la Figura 3 19 es referencial pues el m dulo de control Tempos VI trabaja bajo un sistema denominado multitarea lo cual asegura que no correr en una sola funci n durante en un bucle infinito y secuencial sino que ejecutar diversas funciones de modo simult neo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Diseno del software INICIALIZA FIRMWARE INTEGRADO DEL TEMPUS Vl SENSA RELOJ EN TIEMPO REAL ACTUALIZA LCD SENSA TECLADO MATRICIAL CAMBIO OPCIONES DE ACTUALIZA DATAGRAMA USUARIO PIDE DATO Sl ANALIZ
61. capacitor C16 and the rectification diodes D2 and D3 The analog input V2P is protected by the large impedance of the attenuation network used for calibration Another very common low cost technique employed to arrest ESD events is to use a spark gap on the compo nent side of the PCB see Figure 19 However since the meter will likely operate in an open air environment and be subject to many discharges this is not recommended at sensitive nodes like the shunt connection Multiple REV A discharges could cause carbon buildup across the spark gap which could cause a short or introduce an imped ance that will in time affect accuracy A spark gap was introduced in the PSU after the MOV to take care of any very high amplitude fast rise time discharges 8kV ESD EVENT TO EXTERIOR CONNECTION TO CIRCUIT gt TRACE TRACK 6 9 MILS ESD DISCHARGED NO SOLDER 4 ACROSS SPARK GAP MASK SIGNAL GROUND Figure 19 Spark Gap to Arrest ESD Events ELECTROMAGNETIC HF FIELDS Testing is carried out according to IEC100 4 3 Suscepti bility of integrated circuits to RF tends to be more pronounced in the 20 MHz 200 MHz region Frequencies higher that this tend to be shunted away from sensitive devices by parasitic capacitances In general at the IC level the effects of RF in the region 20 MHz 200 MHz will tend to be broadband in nature 1 no individual frequency is more troublesome than another However t
62. case the Phase B voltage input should be wired to the VCP pin and the Phase C voltage input should be wired to the VBP pin VOLTAGE WAVEFORMS ZERO E L 1 CROSSINGS a S u y 55 SEQERR BIT OF STATUS REGISTER IS SET 65 120 a 1200 VOLTAGE WAVEFORMS 04443 060 ZERO i CROSSINGS y C B A C 5 SEQERR BIT OF STATUS REGISTER IS NOT SET Figure 60 Phase Sequence Detection POWER SUPPLY MONITOR The ADE7758 also contains an on chip power supply monitor The analog supply AVDD is monitored continuously by the ADE7758 If the supply is less than 4 V 5 the ADE7758 goes into an inactive state that is no energy is accumulated when the supply voltage is below 4 V This is useful to ensure correct device operation at power up and during power down The power supply monitor has built in hysteresis and filtering This gives a high degree of immunity to false triggering due to noisy supplies Figure 61 shows the behavior of the ADE7758 when the voltage of AVDD falls below the power supply monitor threshold The power supply and decoupling for the part should be designed such that the ripple at AVDD does not exceed 5 V 5 as specified for normal operation ADE7758 AVpp 5V 4V OV ADE7758 INTERNAL CALCULATIONS ACTIVE INACTIVE Figure 61 On Chip Power Supply Monitoring 04443 061 REFERENCE CIRCUIT The nominal reference voltage at the REFmy
63. changed indicating that the accumulation register is half full positive or negative Setting the RSTREAD bit Bit 6 of the LCYMODE register enables a read with reset for the watt hr accumulation registers that is the registers are reset to 0 after a read operation WATT GAIN Ox7FF WATT GAIN 0x000 WATT GAIN 0x800 CONTENTS OF WATT HR ACCUMULATION REGISTER Ox7FFF Ox3FFF 0x0000 0xC000 0 8000 04443 067 TIME Sec Figure 67 Energy Register Roll Over Time for Full Scale Power Minimum and Maximum Power Gain Rev C Page 32 of 72 Integration Time Under Steady Load The discrete time sample period T for the accumulation register is 0 4 us 4 CLKIN With full scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000 the average word value from each LPF2 is OxCCCCD see Figure 64 and Figure 66 The maximum value that can be stored in the watt hr accumulation register before it overflows is 2 1 or OX7FFF Because the average word value is added to the internal register which can store 2 1 or OxFF FFFF FFFF before it overflows the integration time under these conditions with WDIV 0 is calculated as OxFF FFFF FFFF Time x 0 4 us 0 524 sec 21 0xCCCCD When is set to a value different from 0 the time before overflow is scaled accordingly as shown in Equation 22 Time Time WDIV 0 x WDIV 7 0 22
64. con las cargas un par de bobinas de corriente conectadas en serie y un disco de aluminio gira libremente entre los polos devanado de la bobina de voltaje tiene muchas vueltas y es altamente inductivo de modo que el flujo del voltaje aplicado est retrasado en casi 90 mientras que los flujos en los polos de corriente est n en fase con la corriente Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis L PONTIFICIA TESIS UNIVERSIDAD DEL PERU DISCO ROTATORIO BOBINADO DE BOBINADO DE CORRIENTE VOLTAJE LINEAS DE ALIMENTA l OIM LA CORRIENTE CIRCULANTE POR LOS BOBINADOS GENERA FLUJOS ELECTROMAGNETICOS QUE HACEN GIRAR EL DISCO EL NUMERO DE VUELTAS INDICA LA POTENCIA CONSUMIDA Figura 2 6 Diagrama equivalente del medidor de potencia activa Seg n la intensidad de corriente que circule por el bobinado de corriente y seg n el voltaje que exista entre los bornes del bobinado de voltaje se generar n dos flujos en el nucleo quienes a su vez inducir n corrientes de Foucault en el disco las cuales conjuntamente con los dos flujos y gobernados por la Ley de Lenz producir n un momento de torsi n torque que finalmente ocasionar que el disco rotor de aluminio gire en una direcci n la cantidad de vueltas que d el disco ser la cantidad de Potencia Activa consumida e Medidores de potencia activa digital Para el c lculo dig
65. cumple con la extensi n del conector original para alimentaci n del m dulo de control el cual usa 4 pines 2 de ellos como alimentaci n VCC y GND y los otros 2 con el manejo de los actuadores para la etapa de expansi n MODULO DEL SISTEMA MODULO DE CONTROL V input INTERNO ACTUADORES Atmega128 Figura 3 36 Conector ACTUADORES interno Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CATOLICA DEL PERU e El conector SERIAL se encarga de traer los 5VDC regulados en el M dulo de control hasta la tarjeta de componentes desarrollada adem s de los pines de control desde el microcontrolador para la l gica RS 485 MODULO DEL SISTEMA MODULO DE CONTROL Figura 3 37 Conector SERIAL interno e EL conector TCP IP solo es una extensi n del RJ 45 que sale del m dulo de control La tarjeta de componentes desarrollada posee dos diferentes conectores para comodidad en las pruebas del prototipo MODULO DEL SISTEMA MODULO DE CONTROL TCP IP INTERNO Figura 3 38 Conector TCP IP interno Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 3 7 DISE O MECANICO DEL CHASIS La ltima etapa y no menos importante del proyecto fue el dise o del chasis cuya funci n ser
66. data sheet REV A 1 5 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R23 R18 R19 R20 R21 R22 C1 C2 C3 C4 C5 C13 REV A AN 559 Bill of Materials Details 1 1 1 8 W 300 kQ 5 1 2 W 200 V 150 5 1 2 W 200 V 75 5 1 8 W 200 V 39 5 1 16 W 50 V 18 5 1 16 W 50 V 9 1 576 1 16 W 50 V 5 1 5 1 16 W 50 V 2 2 576 1 16 W 50 V 1 2 5 1 16 W 50 V 560 Q 5 1 16 W 50 V 330 5 1 2 W 200 V 1 5 1 8 W 200 V 820 Q 5 1 8 W 200 V 20 Q 5 1 8 W 200 V 470 Q 5 1 W 10 Q 5 1 8 W 200 V 33 nF Multilayer Ceramic 1096 50 V X7R 10 uF 6 3 V Comments SMD 1206 Resistor Surface Mount Panasonic ERJ 8ENF1001 Digi Key No P 1K FCT ND SMD 2010 Resistor Surface Mount Panasonic ERJ 12ZY304 Digi Key No P 300K WCT ND SMD 1210 Resistor Surface Mount Panasonic ERJ 14YJ154 Digi Key No P 150K VCT ND SMD 1206 Resistor Surface Mount Panasonic ERJ 8GEYJ753 Digi Key No P 75K ECT ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ393 Digi Key No P 39K JCT ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ183 Digi Key No P 18K JCT N SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ912 Digi Key No P 9 1K JCT ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ512 Digi Key No P 5 1K JC
67. del consumo http neutron ing ucv ve Consultado 13 Nov 2006 25 ENERGY COMMISSION Energy Commission History http www a2gov org PublicServices SystemsPlanning Energy EnergyCommiss ionHistory html Consultado 16 Oct 2006 26 THE WORLD BANK www worldbank org Peru Data Profile http devdata worldbank org external CPProfile asp SelectedCountry PER amp C CODE PER amp CNAME Peru amp PT YPE CP Consultado 12 Ene 2007 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis ANALOG Poly Phase Multifunction Energy Metering IC DEVICES with Per Phase Information ADE 758 FEATURES GENERAL DESCRIPTION Highly accurate supports IEC 60687 IEC 61036 IEC 61268 IEC 62053 21 IEC 62053 22 and IEC 62053 23 Compatible with 3 phase 3 wire 3 phase 4 wire and other 3 phase services Less than 0 196 active energy error over a dynamic range of 1000 to 1 at 25 signal processing required to perform active reactive and The ADE7758 is a high accuracy 3 phase electrical energy measurement IC with a serial interface and two pulse outputs The ADE7758 incorporates second order X A ADCs a digital integrator reference circuitry a temperature sensor and all the Supplies active reactive apparent energy voltage rms apparent energy measurement and rms calculations current rms and sampled waveform data P The ADE7758 is suitable to
68. diseno El color final es negro para hacer referencia a la tonalidad est ndar de los productos comerciales Figura 3 41 Vista superior frontal y posterior del chasis Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CATOLICA DEL PERU 3 8 DISTRIBUCI N DE M DULOS La distribuci n de las tarjetas en el chasis y sus componentes es la siguiente TECLADO Y LCD MODULO DE CONTROL MODULO DEL SISTEMA Figura 3 42 Diagrama de bloques de las tarjetas del sistema M DULO DE TECLAL s 9 Conector de comunicaci n SPI Teclado y Display LCD M NI ADE7758 Conector hacia el teclado y LCD Conector de alimentaci n externo Microcontrolador ATmega128 Conector de TCP IP externo Integrado de comunicaci n a red Conector de expansi n y RS 485 Puerto de comunicaci n serial 1 Actuador 1 rel Puerto de comunicaci n serial 2 Actuador 2 rel Conector de TCP IP interno Conector para medici n de corriente Conector de alimentaci n interno Conector para medici n de voltaje Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis F sicamente la ubicaci n de los m dulos del sistema n e na d iu G br Aat PA 3 a EN LA FIGURA SE PUEDE OBSERVAR EL MODULO DE CONTROL TEMPUS VI CONECTADO CON
69. el firmware es el intermediario interfaz entre las rdenes externas que recibe el dispositivo y su electr nica ya que es el encargado de controlar a sta ultima para ejecutar correctamente dichas rdenes externas e Driver Un controlador de dispositivos o driver en el ingl s es un programa inform tico que permite al sistema operativo interactuar con un perif rico haciendo una abstracci n del hardware y proporcionando una interfaz para usarlo Se puede esquematizar como un manual de instrucciones que le indica c mo debe controlar y comunicarse con un dispositivo en particular Por tanto es una pieza esencial sin la cual no se podr a usar el hardware La diferencia con el firmware es que el driver se ejecuta sobre un sistema operativo y no directamente sobre la electr nica del dispositivo es decir el driver se encarga de indicar las respectivas instrucciones que utilizar el sistema operativo para controlar alg n dispositivo espec fico en tanto el firmware indica ejecuta y controla los dispositivos a los que se halla conectada la electr nica Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis ENER Y lt PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU Electricidad Voltajes y frecuencias El sistema de generaci n y distribuci n de corriente alterna trif sico fue inventado por Nikola Tesla en el s XIX El consider
70. el procesamiento digital y la comunicaci n entre dispositivos Este equipo recibir la se al el ctrica externa ya digitalizada la procesar con la l gica num rico matem tica de medici n adecuada y podr interactuar con el usuario mediante visualizadores luego podr enviarla mediante TCP IP hacia alguna interfaz remota El prototipo no llegar a realizar medici n alguna pero contendr el sistema de control digital para la medici n siendo esta etapa la m s compleja e innovadora del desarrollo En la Figura 2 15 se presentan las etapas denominadas como Acondicionamiento de datos e Interfaz remota con el usuario la cuales se encargan de convertir la se al el ctrica de 220VAC 380VAC 440VAC a valores adecuados para el procesamiento y la comunicaci n con el usuario final respectivamente cabe precisar que dichas etapas no ser n consideradas en el desarrollo del proyecto de tesis la primera por ser integramente el ctrica y la segunda por ser exclusivamente de programaci n Sin embargo se ha investigado al respecto y se presentan algunos alcances para su desarrollo en el Anexo B Comunicaci n IrDA Secci n Comunicaci n IrDA P g 3 y en el Anexo C Tecnolog as para medici n de corriente Secci n Tecnolog as para medici n de corriente P g 9 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP S CAT LI
71. futuro de los medidores de inducci n 1886 El profesor Forbes de Londres Inglaterra desarrolla el primer medidor para circuitos AC que utilizaba elementos calentadores unidos a un pequeno molino de viento conectado a un registro Lamentablemente este medidor era demasiado delicado para el uso comercial 1889 Thomson introdujo el primer vat metro tipo conmutador el cual muchas expresas adoptaron como modelo est ndar Aunque este medidor fuese disenado en un inicio para medici n AC tambi n dio bueno resultados con medici n DC e 1892 Duncan desarrolla el primer vatimetro de inducci n que usa un solo disco tanto para la conducci n como para el elemento de frenado este diseno nunca lleg a producirse 1893 Nikola Tesla saca una patente que cubre el principio del motor de inducci n propuesto por Ferrari y que m s tarde ser a compradas por Jorge Westinghouse Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis ENER Y lt PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 1894 Shallenberger desarrolla un pequeno motor de inducci n con el espiral de voltaje y corriente desfasados 90 el uno al otro Este concepto fue refinado dando paso al primer vat metro de inducci n comercial siendo este modelo uno de los m s pesados 41 libras y caros de su poca 1897 P Davis y Frank Conrad redisena
72. hasta el presente 27 Oct 2005 9 METERING INTERNATIONAL 2002 Magazine archive Isue 1 Measuring reactive power in energy meters http www metering com archive 021 52 1 htm Consultado 28 Oct 2005 10 METERING INTERNATIONAL 2003 Magazine archive Energy measurement ICs http www metering com archive 031 42 1 htm Consultado 28 Oct 2005 11 GERENCIA ADJUNTA DE REGULACI N TARIFARIA GART COMISI N DE TARIFAS EL CTRICAS 1997 Resoluci n de la comisi n de tarifas el ctricas No 024 97 P CTE http www cte org pe resoluciones pdf REO24 1997 Consultado 04 Nov 2005 12 Gobierno del Per Decreto Supremo N 016 2000 EM Fijan horas de regulaci n y probabilidad de excedencia mensual de centrales hidr ulicas horas punta del sistema el ctrico y margen de reserva a que se refiere el Reglamento de la Ley de Concesiones El ctricas Incluye modificaciones seg n Decreto Supremo N 032 2001 EM Decreto Supremo N 034 2001 EM y D S 055 2002 Art culo 2 Promulgado 13 Sep 2000 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 13 Gobierno del Per Decreto Supremo N 027 2003 EM Fijan horas de punta del Sistema El ctrico Interconectado Art culo 19 Promulgado 06 Ago 2003 14 JUAN LUIS HERNANDEZ 2004 Factor de Potencia FDP http endrin
73. increased by a maximum factor of 255 When overflow occurs the VAR hr accumulation registers content can rollover to full scale negative 0x8000 and continue increasing in value when the reactive power is positive Con versely if the reactive power is negative the VAR hr accumulation registers content can roll over to full scale positive 0x7FFF and continue decreasing in value By setting the REHF bit Bit 1 of the interrupt mask register the ADE7758 can be configured to issue an interrupt IRQ when Bit 14 of any one of the three VAR hr accumulation registers has changed indicating that the accumulation register is half full positive or negative Setting the RSTREAD bit Bit 6 of the LCYMODE register enables a read with reset for the VAR hr accumulation registers that is the registers are reset to 0 after a read operation VARHR 15 0 A o o TOTAL REACTIVE POWER IS ACCUMULATED INTEGRATED IN THE VAR HR ACCUMULATION REGISTERS 04443 072 Figure 72 ADE7758 Reactive Energy Accumulation Rev C Page 37 of 72 7758 Integration Time Under Steady Load The discrete time sample period T for the accumulation register is 0 4 us 4 CLKIN With full scale sinusoidal signals on the analog inputs a 90 phase difference between the voltage and the current signal the largest possible reactive power and the VAR gain registers set to 0x000 the average word value from each LPF2 is OxCCCCD The maximum v
74. input to the voltage channel Table 8 Settling Time for VRMS Measurement 63 100 100 ms 960 ms Voltage RMS Offset Compensation The ADE7758 incorporates a voltage rms offset compensation for each phase AVRMSOS BVRMSOS and CVRMSOS These are 12 bit signed registers that can be used to remove offsets in the voltage rms calculations An offset can exist in the rms calculation due to input noises and offsets in the input samples It should be noted that the offset calibration does not allow the contents of the VRMS registers to be maintained at 0 when no voltage is applied This is caused by noise in the voltage rms calculation which limits the usable range between full scale and 1 50th of full scale One LSB of the voltage rms offset is equivalent to 64 LSBs of the voltage rms register Assuming that the maximum value from the voltage rms calculation is 1 639 101d with full scale ac inputs then 1 LSB of the voltage rms offset represents 0 04296 of the measurement error at 1 10 of full scale VRMS VRMSo VRMSOS x 64 10 where VRMSo is the rms measurement without the offset correction Table 9 Approximate VRMS Register Values Frequency Hz Value d 50 1 678 210 60 1 665 118 Rev C Page 29 of 72 7758 Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers AVRMSGAIN BVRMSGAIN and CVRMSGAIN The gain of
75. is explained in the AD7755 data sheet Theory Of Opera tion section The AD7755 data sheet also provides an equation that relates the output frequency on F1 and F2 counter drive to the product of the rms signal levels at V1 and V2 This equation is shown here again for convenience and will be used to determine the correct signal scaling at V2 in order to calibrate the meter to a fixed constant 8 06 x V1 x V2 x Gain x FE 4 wu o 1 REF The meter shown in Figure 1 is designed to operate at a line voltage of 220 V and a maximum current Imax of Frequency 40 A However by correctly scaling the signals on Channel 1 and Channel 2 a meter operating of any line voltage and maximum current could be designed The four frequency options available on the AD7755 will allow similar meters i e direct counter drive with an Imax of up to 120 A to be designed The basic current Ib for this meter is selected as 5 A and the current range for accuracy will be 2 Ib to Imax or a dynamic range of 400 100 mA to 40 A The electromechanical register KWh will have a constant of 100 imp kWh i e 100 impulses from the AD7755 will be required in order to register 1 kWh IEC1036 section 4 2 11 specifies that electromag netic registers have their lowest values numbered in ten division each division being subdivided into ten parts Hence a display with a five plus one digits is used i e 10 000s 1 000s 100s 10s 1s 1 10s The meter cons
76. known the line period is available in the ADE77585 frequency register FREQ 0x10 To configure line period measurement select the phase for period measurement in the 1 0 and set LCYCMODE 7 Step 5 Calculate the value to be written to the x WATTOS registers according to the following equations Offset LINECYC xWATTHR Ly xWATTHR DN m s 1 MIN 1 73 Offset x 4 xWATTOS 11 0 x07 74 AccumTime x CLKIN ADE7 1758 where AccumTime is defined in Equation 58 xWATTAR is the value in the energy register at Iresr xWATTAR is the value in the energy register at Imm LINECYCium is the number of line cycles accumulated at LINECYCimax is the number of line cycles accumulated at Imax Step 6 Write to all xWATTOS registers 0x39 to Ox3B Step 7 Set the test system for Imm and zero power factor inductive to calibrate VAR gain Step 8 Repeat Steps 3 4 and 5 Step 9 Calculate the value written to the xVAROS registers according to the following equations Offset xVARHR I MIN LINECYC IVAR x Na Iun ITEST E Lrgsr 75 Offset x 4 FREQU1 0 xVAROS 11 0 AccumTime x CLKIN 202 x 27 76 where the FREQ 11 0 register is configured for line period readings Example Power Offset Calibration Using Line Accumulation This example only shows Phase A of the
77. offset from the VA calculation For this reason no VA offset register exists in the ADE7758 START SET CONFIGURATION REGISTERS FOR ZERO CROSSING ON ALL PHASES SET INTERRUPT MASK FOR ZERO CROSSING ON ALL PHASES TESTED YES ALL PHASES TESTED ALL CONDITIONS SET UP SYSTEM FOR VNOM SET UP SYSTEM FOR leui scALE 500 VruLLscALE 20 READ RMS REGISTERS WRITE TO xVRMSOS xIRMSOS The low pass filter used to obtain the rms measurements is not ideal therefore it is recommended to synchronize the readings with the zero crossings of the voltage waveform and to average a few measurements when reading the rms registers The ADE7758 IRMS measurement is linear over a 500 1 range and the VRMS measurement is linear over a 20 1 range To measure the voltage VRMS offset x V RMSOS measure rms values at two different nonzero current levels for example and Veuttscate 20 To measure the current rms offset IRMSOS measure rms values at two different nonzero current levels for example Iresr and Irutiscare 500 This translates to two test conditions Iresr and Vnom and Iruriscate 500 and VruscaLe 20 Figure 84 shows a flowchart for calibrating the rms measurements CHOOSE N n 0 CALCULATE THE AVERAGE OF N SAMPLES 04443 084 Figure 84 RMS Calibration Routine Rev C Page 54 of 72 Step 1 Set configuration registers for zero crossings on al
78. phase active power offset calibration Both active and reactive power offset for all phases can be calibrated simultaneously using the method explained in the Power Offset Calibration Using Line Accumulation section For this example Imn 50 mA Iresr 10 A Vnom 220 V Veutiscate 500 V Iruriscare 130 A 3200 impulses kWh Power Factor 1 Frequency 50 Hz and CLKIN 10 MHz Also LINECYCrresr 0x800 and LINECYCimm 0x4000 After accumulating over 0x800 line cycles for gain calibration at Irzsr the example ADE7758 meter shows 148044 in the AWATTHR 0x01 register At Imm the meter shows 592d in the AWATTHR register By using Equation 73 this is equivalent to 0 161 LSBs of offset therefore using Equation 61 and Equation 74 the value written to AWATTOS is 0d Offset 592x 10 x ZAN 0 05 0x800 de 0 05 10 Rev C Page 53 of 72 7758 4000 AccumTime Loro 54 64s 2x 3 2085x9 6x10 0 161x 4 x2 2 0 088 0 54 64 x 10 MHz AWATTOS Calibration of IRMS and VRMS Offset IRMSOS and VRMSOS are used to cancel noise and offset contributions from the inputs The calibration method is the same whether calibrating using the pulse outputs or line accumulation Reading the registers is required for this calibration because there is no rms pulse output The rms offset calibration should be performed before VAGAIN calibration The rms offset calibration also removes
79. power calculation However ADC offset in the voltage channels produces large errors in the voltage rms calculation and affects the accuracy of the apparent energy calculation Voltage Channel Sampling The waveform samples on the voltage channels can also be routed to the WFORM register However before passing to the WFORM register the ADC outputs pass through a single pole low pass filter LPF1 with a cutoff frequency at 260 Hz Figure 50 shows the magnitude and phase response of LPF1 This filter attenuates the signal slightly For example if the line frequency is 60 Hz the signal at the output of LPF1 is attenuated by 3 57596 The waveform samples are 16 bit twos complement data ranging between 0x2748 10 056d and 0xD8B8 10 056d The data is sign extended to 24 bit in the WFORM register 0 974 0 225 dB 3 PHASE Degrees GAIN dB 10 100 1k FREQUENCY Hz 04443 050 Figure 50 Magnitude and Phase Response of LPF1 Note that LPF1 does not affect the active and reactive energy calculation because it is only used in the waveform sampling signal path However waveform samples are used for the voltage rms calculation and the subsequent apparent energy accumulation The WAVSEL 2 0 bits in the WAVMODE register should be set to 001 binary to start the voltage waveform sampling The PHSEL 1 0 bits control the phase from which the samples are routed In waveform sampling mode one of four output sample r
80. reactive power over an integral number of line cycles n is given by the expression in Equation 31 nT q t dt V x Ix sin 0 31 nT 5 where T is the period of the line cycle Q is referred to as the average reactive power The instantaneous reactive power signal q t is generated by multiplying the voltage signals and the 90 phase shifted current in each phase The dc component of the instantaneous reactive power signal in each phase A B and C is then extracted by a low pass filter to obtain the average reactive power information on each phase This process is illustrated in Figure 71 The reactive power of each phase is accumulated in the corresponding 16 bit VAR hour register AVARHR BVARHR or CVARHR The input to each reactive energy register can be changed depending on the accumulation mode setting see Table 21 Rev C Page 35 of 72 7758 The frequency response of the LPF in the reactive power signal path is identical to that of the LPF2 used in the average active power calculation see Figure 65 INSTANTANEOUS REACTIVE POWER SIGNAL q t VRMS x IRMS x sin VRMS x IRMS x sin 2wt AVERAGE REACTIVE POWER SIGNAL VRMS IRMS x sin 8 VRMS IRMS x sin 0x00000 VOLTAGE v t 2 x VRMS x sin wt CURRENT i t 2 x IRMS x sin wt 04443 071 Figure 71 Reactive Power Calculation The low pass filter is nonideal so the reactive power signal has some
81. requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplitier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony Low Power www ti com lpw Video amp Imaging www ti com video Wireless Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
82. separate signal paths and filtering for calculation The differences in the datapaths can result in small differences in LSB weight between the active reactive and apparent energy registers measurements are internally compensated so that the scaling is nearly one to one The relationship between the registers is shown in Table 15 Table 15 Energy Registers Scaling Frequency 5 Integrator 1 004 x WATT 1 0054 x WATT VA 1 00058 x WATT 1 0085 x WATT Integrator On VAR 1 0059 x WATT 1 0064 x WATT VA 1 00058 x WATT 1 00845 x WATT WAVEFORM SAMPLING MODE The waveform samples of the current and voltage waveform as well as the active reactive and apparent power multiplier out puts can all be routed to the WAVEFORM register by setting the WAVSEL 2 0 bits Bit 2 to Bit 4 in the WAVMODE register The phase in which the samples are routed is set by setting the PHSEL 1 0 bits Bit 0 and Bit 1 in the WAVMODE register All energy calculation remains uninterrupted during waveform sampling Four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register DTRT 1 0 The output sample rate can be 26 04 kSPS 13 02 kSPS 6 51 kSPS or 3 25 kSPS see Table 20 By setting the WFSM bit in the interrupt mask register to Logic 1 the interrupt request output IRQ goes active low when a sample is available The 24 bit waveform samples are transferred from the ADE7758 one byte
83. ser cercano a los 5VDC y de bajo consumo de potencia Componente seleccionado oe ha elegido una pantalla LCD est ndar de 16 caracteres por 2 l neas LCD 16x2 que posee la caracter stica de programaci n en paralelo mediante pines del bus de datos adem s posee un pin anal gico a fin de acondicionar el contraste de la pantalla Al ser un display de configuraci n est ndar puede ser direccionable por s lo 4 pines de su bus de datos normalmente se hace con 8 de ellos esto con el objeto de reducir pines de control para el controlador principal del sistema Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis B DISENO DE LA ETAPA PARA EL DISENO DE ESTA ETAPA SE SIGUIERON LAS RECOMENDACIONES DADAS POR EL FABRICANTE Y SE UTILIZO LA LOGICA DENOMINADA DE 4 BITS Figura 3 14 Esquema circuital de la etapa de visualizaci n de datos Esta etapa gobernada por el visualizador LCD de 16x2 se maneja con la l gica denominada de 4 bits Es por ello que el microcontrolador est conectado nicamente a los Bits M s Significativos MSB del bus de datos del display DB7 DB6 DB5 y DB4 y los Bits Menos Significativos LSB est n conectados a tierra GND LA PANTALLA LCD ELEGIDA ES UNA DE 16 LINEAS POR 2 FILAS 16 x 2 QUE PERMITE MOSTRAR CARACTERES ALFANUMERICOS Figura 3 15 Visualizador LCD de 16x2 55 SOME RIGHTS RESERVED Algunos Derechos F VEN
84. statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated 1 product or service and is an unfair and deceptive business practice 1115 not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such u
85. substantially influence the meter The considered disturbances are 1 Electrostatic Discharge 2 Electromagnetic HF Fields 3 Fast Transience Burst of the precautions and design techniques e g ferrite beads capacitor line filters physically large SMD resis tors PCB layout including grounding contribute to a certain extent in protecting the meter electronics from each form of electromagnetic disturbance Some precau tions e g ferrite beads however play a more important role in the presence of certain kinds of disturbances e g RF and fast transience burst The following dis cuses each of the disturbances listed above and details what protection has been put in place REV A AN 559 ELECTROSTATIC DISCHARGE ESD Although many sensitive electronic components con tain a certain amount of ESD protection on chip it is not possible to protect against the kind of severe discharge described below Another problem is that the effect of an ESD discharge is cumulative i e a device may sur vive an ESD discharge but it is no guarantee that it will survive multiple discharges at some stage in the future The best approach is to eliminate or attenuate the effects of the ESD event before it comes in contact with sensitive electronic devices This holds true for all conducted electromagnetic disturbances This test is carried out according to IEC1000 4 2 under the fol lowing conditions Contact Discharge
86. the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright O 1995 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments e a Dn processing does not necessarily include vip EXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 Function Tables DRIVER n H L H X H L Vip 20 2 V 0 2 V lt Vip lt 0 2 V Vip 0 2 V X Open H high level L low level indeterminate X irrelevant Z high impedance off logic symbolt logic diagram positive logic T This symbol is in accordance with ANSI IEEE Std 91 1984 and IEC Publication 617 12 435 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF A AND B PORTS TYPICAL OF RECEIVER OUTPUT Vcc Vcc R eq NOM Enable inputs R eg 8 NOM Port R eq equivalent resistor absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage Vcc see Note 1 7V Voltage range at any bus terminal
87. to the LCYCMODE register Table 22 summarizes the functionality of each bit in the LCYCMODE register Table 22 LCYCMODE Register Bit Bit Default Location Mnemonic Value Description 0 1 2 3to5 6 RSTREAD 7 FREQSEL Setting this bit places the watt hour accumulation registers AWATTHR BWATTHR and CWATTHR registers into line cycle accumulation mode Setting this bit places the VAR hour accumulation registers AVARHR BVARHR and CVARHR registers into line cycle accumulation mode Setting this bit places the VA hour accumulation registers AVAHR BVAHR and CVAHR registers into line cycle accumulation mode These bits select the phases used for counting the number of zero crossings in the line cycle accumulation mode Bit 3 Bit 4 and Bit 5 select Phase A Phase B and Phase C respectively More than one phase can be selected for the zero crossing detection and the accumulation time is shortened accordingly Setting this bit enables the read with reset for all the WATTHR VARHR and VAHR registers for all three phases that is a read to those registers resets the registers to 0 after the content of the registers have been read This bit should be set to Logic 0 when the LWATT LVAR or bits are set to Logic 1 Setting this bit causes the FREQ 0x10 register to display the period instead of the frequency of the line input Rev C Page 67 of 72 7758 INTERRUPT MASK REGISTER 0x18 When an interrupt e
88. usados en cualquier frecuencia comercial de 25Hz a 133 Hz 1911 Las patentes de Tesla expiraron en diciembre de 1910 Sangamo introdujo un nuevo medidor de inducci n con un disco que giraba en sentido anti horario a diferencia de sus competidores que giraban sen sentido horario e Finales de los a os 1930 Los medidores polif sicos fueron dise ados para incorporar un disco laminado que permit a a los estatores ser colocados juntos sin actuar rec procamente el uno con el otro e los avances en la electr nica en los anos 1970 los fabricantes comenzaron a introducir registros electr nicos y medidores autom ticos de lectura e mediados de los anos 1980 los fabricantes ofrec an medidores h bridos con registros electr nicos montados sobre medidores de inducci n e principios de los a os 1990 con los avances de la electr nica los fabricantes comenzaron a producir medidores que eran totalmente electr nicos que ya no usaban ninguna etapa m vil aparte de los interruptores sol a tener acceso a varias funciones sobre los medidores Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis D PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU en d a con el auge de las telecomunicaciones la integraci n de los sistemas da nacimiento a una nueva tendencia en el manejo de energ a en las empresas o Sistema EEM Enterprise E
89. waveform sample at 60 Hz is 0x2748 The VPEAK at full scale input is therefore expected to be Ox9D In addition multiple phases can be activated for the peak detection simultaneously by setting multiple bits among the PEAKSEL 2 4 bits in the MMODE register These bits select the phase for both voltage and current peak measurements Note that if more than one bit is set the VPEAK and IPEAK registers can hold values from two different phases that is the voltage and current peak are independently processed see the Peak Current Detection section Note that the number of half line cycles is based on counting the zero crossing of the voltage channel The ZXSEL 2 0 bits in the LCYCMODE register determine which voltage channels are used for the zero crossing detection see Table 22 The same signal is also used for line cycle energy accumulation mode if activated Overvoltage Detection Interrupt Figure 59 illustrates the behavior of the overvoltage detection VOLTAGE PEAK WAVEFORM BEING MONITORED SELECTED BY PKIRQSEL 5 7 IN MMODE REGISTER VPINTLVL 7 0 PKV RESET LOW PKV INTERRUPT FLAG BIT 14 OF STATUS REGISTER gt gt e m m m gt m m e e m gt Md Rn CS ERE ad A LF WHEN RSTATUS REGISTER IS READ READ RSTATUS REGISTER 04443 059 Figure 59 AD
90. width does not include interlead flash Interlead flash shall not exceed 017 0 43 per side Reference JEDEC MS 012 variation AA NOTES Pu 5 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent 1 deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either expr
91. zero crossing timeout detection on Phase C Enables an interrupt when there is a zero crossing in the voltage channel of Phase A see the Zero Crossing Detection section Enables an interrupt when there is a zero crossing in the voltage channel of Phase B see the Zero Crossing Detection section Enables an interrupt when there is a zero crossing in the voltage channel of Phase C see the Zero Crossing Detection section Enables an interrupt when the energy accumulations over LINECYC are finished Reserved Enables an interrupt when the voltage input selected in the MMODE register is above the value in the VPINTLVL register Enables an interrupt when the current input selected in the MMODE register is above the value in the IPINTLVL register Enables an interrupt when data is present in the WAVEMODE register Enables an interrupt when there is a sign change in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register Enables an interrupt when there is a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register Enables an interrupt when the zero crossing from Phase A is followed not by the zero crossing of Phase C but with that of Phase B Rev C Page 68 of 72 ADE7 1758 INTERRUPT STATUS REGISTER 0x19 RESET INTERRUPT STATUS REGISTER 0x14 The interrupt status register is used to determine the source of an interru
92. 024 LSB The function of the VAGAIN registers is expressed mathematically as Average Apparent Power VAGAIN Register 40 LPF2 Output x 1 2 The output is scaled by 50 by writing 0x800 to the VAR gain registers and increased by 50 by writing Ox7FF to them These registers can be used to calibrate the apparent power or energy calculation in the ADE7758 for each phase Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value see the Current RMS Calculation section and the Voltage Channel RMS Calculation section The voltage and current rms values are then multiplied together in the apparent power signal processing As no additional offsets are created in the multiplication of the rms values there is no specific offset compensation in the apparent power signal processing The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement see the Calibration section Rev C Page 39 of 72 7758 Apparent Energy Calculation Apparent energy is defined as the integral of apparent power Apparent Energy S t dt 41 Similar to active and reactive energy the ADE7758 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in the internal 41 bit unsigned accumulation regi
93. 1 in the interrupt mask register the IRQ logic output goes active low see the Interrupts section Similar to peak level detection multiple phases can be activated for peak detection If any of the active phases produce waveform samples above the threshold the PKI flag in the interrupt status register is set The phase of which overcurrent is monitored is set by the PKIRQSEL 2 0 bits in the MMODE register see Table 19 Rev C Page 21 of 72 7758 CALIBRATION GAIN 6 5 x1 x2 x4 VN fap 260Hz ANALOG INPUT PHASE PHCAL 6 0 Hh 50Hz 0x2797 0x2852 RANGE 0xD869 SIN 0xD7AE 60Hz 0x2748 TO ACTIVE AND REACTIVE ENERGY CALCULATION O VOLTAGE RMS CALCULATION AND WAVEFORM SAMPLING LPF OUTPUT WORD RANGE LPF OUTPUT WORD RANGE 0x0 0xD8B8 04443 049 Figure 49 ADC and Signal Processing in Voltage Channel VOLTAGE CHANNEL ADC Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel The VB and VC channels have similar processing chains For active and reactive energy measurements the output of the ADC passes to the multipliers directly and is not filtered This solution avoids the much larger multibit multiplier and does not affect the accuracy of the measurement An HPF is not implemented on the voltage channel to remove the dc offset because the HPF on the current channel alone should be sufficient to eliminate error due to ADC offsets in the
94. 200 and 320 These correspond to a maximum meter current of 10 A 20 A 100 A 200 A and 320 A respectively Ibasic Ib IEC1036 The basic current Ib is a value of current with which the operating range of the meter is defined IEC1036 defines the accuracy class of a meter over a specific dynamic range e g 0 05 Ib lt 1 lt Imax It is also used as the test load when specifying the maximum permissible effect of influencing factors e g voltage variation and fre quency variation The closest equivalent in ANSI C12 16 is the Test Current The Test Current for each meter class maximum current is given below Class 10 2 5 A Class 20 2 5 A Class 100 15 A Class 200 30 A Class 320 50A 16 Imax 1EC1036 Imax 15 the maximum current for which the meter meets rated accuracy This would correspond to the meter class under ANSI C12 16 For example a meter with an Imax Of 20 A under IEC 1026 would be designated Class 20 under ANSI C12 16 NO LOAD THRESHOLD The AD7755 has on chip anticreep functionality The AD7755 will not produce a pulse on CF F1 or F2 if the output frequency falls below a certain level This feature ensures that the energy meter will not register energy when no load is connected IEC 1036 1996 09 section 4 6 4 specifies the start up current as being not more that 0 496 Ib at PF 1 For this design the start current is calculated at 7 8 mA or 0 16 Ib see No Load Thresh old section in the AD7755
95. 3 Chances to recia 27 Changes to Current RMS Calculation Section 28 Changes to Current RMS Offset Compensation Section and Voltage Channel RMS Calculation Section 29 Added Table 7 and Table 9 Renumbered Sequentially 29 Chances to Era 30 Changes to Active Power Offset Calibration Section 31 Changes to Reactive Power Frequency Output Section 38 Changes to Apparent Power Frequency Output Section and Waveform Sampling Mode Section sss Al Changes to Gain Calibration Using Line Aceuimiilation SOCOM usns neret ti 49 Changes to Example Power Offset Calibration Using Line AccurmslatioD Sectloli to oce 53 Changes to Calibration of IRMS and VRMS Offset Section 54 Chances to Table anti 64 Changes to Table 20 uiv Rd 65 11 05 Rev A to Rev B Changes to A RR EORNM UU 5 Changes to Figure 23 citare a RO GNE IK 14 Changes to Current Waveform Gain Registers Section 19 Changes to di dt Current Sensor and Digital Integrator SCC TION o mss atl etas us aout 20 Changes to Phase Compensation 23 hances EER 25 Changes to Eure 27 Changes to Temperature Measurement Section and Root Mean Square Measurement Section 28 A oun UR RM ELE 28 ADE7 175
96. 3A Ox3B Ox3C Ox3D Ox3E Ox3F 0x40 0x41 0x42 0x43 0x44 Default R W Length Type Value R 8 U 0 GAIN AVRMSGAIN BVRMSGAIN CVRMSGAIN AIGAIN BIGAIN CIGAIN AWG BVAG CVAG AVRMSOS BVRMSOS CVRMSOS AIRMSOS BIRMSOS CIRMSOS AWATTOS BWATTOS CWATTOS AVAROS BVAROS CVAROS APHCAL BPHCAL CPHCAL WDIV VARDIV VADIV mM mM mM mM Description Current Peak Register This register holds the value of the peak current waveform that has occurred within a fixed number of half line cycles The number of half line cycles is set by the LINECYC register PGA Gain Register This register is used to adjust the gain selection for the PGA in the current and voltage channels see the Analog Inputs section Phase A VRMS Gain Register The range of the voltage rms calculation can be adjusted by writing to this register It has an adjustment range of 50 with a resolution of 0 0244 LSB Phase B VRMS Gain Register Phase C VRMS Gain Register Phase A Current Gain Register The range of the current rms calculation can be adjusted by writing to this register It has an adjustment range of 50 with a resolution of 0 0244 LSB Adjusting this register also scales the watt and VAR calculation Not for use with Mode 0 of CONSEL COMPMODE 1 0 Phase B Current Gain Register Not for use with Mode 0 of CONSEL
97. 40 C to 85 24 Lead Wide Body SOIC W RW 24 EVAL ADE7758EB Evaluation Board Z Pb free part Rev C Page 70 of 72 ADE7 1758 NOTES Rev C Page 71 of 72 7758 NOTES 2006 Analog Devices Inc rights reserved Trademarks and registered trademarks are the property of their respective owners D04443 0 7 06 C ANALOG Rev C Page 72 of 72 ANALOG DEVICES AN 559 APPLICATION NOTE One Technology Way P O Box 9106 Norwood MA 02062 9106 781 329 4700 World Wide Web Site http www analog com A Low Cost Watt Hour Energy Meter Based on the AD7755 By Anthony Collins INTRODUCTION This application note describes a low cost high accuracy watt hour meter based on the AD7755 The meter described is intended for use in single phase two wire distribution systems However the design can easily be adapted to suit specific regional requirements e g in the United States power is usually distributed to residential customers as single phase three wire The AD7755 is a low cost single chip solution for elec trical energy measurement The AD7755 is comprised of two ADCs reference circuit and all the signal process ing necessary for the calculation of real active power The AD7755 also includes direct drive capability for elec tromechanical counters i e the energy register and has a high frequency pulse output for calibration and communications purposes This applic
98. 5 15C1256B82004C3D80 file Odin meter E pdf Consultado 25 Oct 2005 3 KARCZ ANDRES M 1977 Fundamentos de metrolog a electr nica Tomo 11 Potencia y energ a Ediciones T cnicas Marcombo S A Boixareu editores Barcelona Espa a 4 KINNARD ISAAC F 1958 Medidas el ctricas y sus aplicaciones Ediciones T cnicas Marcombo S A Barcelona Espa a 5 KARSA B LA E 1967 Electrical measuring instruments and measurements Ed Akad miai Kiad Villamos m r m szerek s m r sek Budapest Hungary Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP 5 CAT LICA DEL PERU 6 Instituto Nacional de Defensa de la Competencia y de la Protecci n de la Propiedad Intelectual INDECOPI 2005 Servicio Nacional de Metrolog a Metrolog a y calibraci n http www indecopi gob pe nuestrosservicios metrologiaycalibracion Consultado 27 Oct 2005 7 EL PERUANO diario oficial 2001 Ministerio de energ a y minas Direcci n general de Electricidad C digo nacional de electricidad suministro 2001 Resoluci n Ministerial 366 2001 EM VME http www editoraperu com pe normas Pdfs cod nc Elec pdf Consultado 27 Oct 2005 8 Gobierno del Peru Ley N 23560 Sistema Legal de Unidades de Medida del Peru SLUMP Promulgado 31 Dic 1982 Seg n Decreto Supremo N 026 93 ITINCI Vigente
99. 6 ns tt lt 6 ns ZQ 50 Q B Cj includes probe and jig capacitance Figure 5 Driver Test Circuit and Voltage Waveforms Generator see Note A CL 15 see Note B T TEST CIRCUIT VOLTAGE WAVEFORMS NOTES A The input pulse is supplied by a generator having the following characteristics PRR 1 MHz 50 duty cycle ty lt 6 ns tf 6 ns 202500 B Cj includes probe and jig capacitance Figure 6 Receiver Test Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 5V 1 5V 9 Generator see Note A CL 15 pF see Note B TEST CIRCUIT SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 O 5 1N916 or Equivalent cix D 1 5 V S1 to 1 5 V 0v E ead S2Closed S3 Open VoH 45V Output 1 5 V OV Output 1 5 V VOL S1 to 1 5 V S1 to 1 5 V S2 Closed S2 Closed S3 Closed S3 Closed 0V V 05V _ 1 3 V Output 4 1 3V VOL VOLTAGE WAVEFORMS NOTES The input pulse is supplied by a generator having the following characteristics PRR 1 MHz 50 duty cycle ty 6 ns tf 6 ns Zo 50 B includes probe and jig capacitance Figure 7 Receiver Test Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 SN75176A
100. 758 starts shifting in the register data on the next falling edge of SCLK remaining bits of register data are shifted in on the falling edge of the subsequent SCLK pulses see Figure 91 Rev C Page 57 of 72 7758 As explained earlier the data write is initiated by a write to the communications register followed by the data During a data write operation to the ADE7758 data is transferred to all on chip registers one byte at a time After a byte is transferred into the serial port there is a finite time duration before the content in the serial port buffer is transferred to one of the ADE7758 on chip registers Although another byte transfer to the serial port can start while the previous byte is being transferred to the destination register this second byte transfer should not finish until at least 900 ns after the end of the previous byte transfer This functionality is expressed in the timing specification ts see Figure 91 If a write operation is aborted during a byte transfer CS brought high then that byte is not written to the destination register Destination registers can be up to 3 bytes wide see the Accessing the On Chip Registers section Therefore the first byte shifted into the serial port at DIN is transferred to the most significant byte MSB of the destination register If the destination register is 12 bits wide for example a two byte data transfer must take place The data is always assumed to
101. 8 Changes to Current RMS Offset Compensation Section 29 ai sca Pm 29 Added Equation il 31 Changes to Energy Accumulation Mode Section 33 Changes to the Reactive Power Calculation Section 35 Added Equation La 36 Changes to Energy Accumulation Mode Section 38 Changes to the Reactive Power Frequency Output Section 38 Changes to the Apparent Energy Calculation Section 40 Changes to the Calibration Section sss 42 Changes to Figure 76 through Figure 84 43 54 Changes to Tablet ie 59 Changes to Tal OR R 63 Changes to Ordering nine 69 9 04 Rev 0 to Rev A Changed Hexadecimal Notation Universal Chances to Features sti 1 Changes to Specifications 5 Change to 16 Additions to the Analog Inputs Section 19 Added Figures 36 and 37 Renumbered Subsequent Figures 19 Changes to Period Measurement Section 26 Change to Peak Voltage Detection Section 26 Added Figure GO cot HERRERA USE NEP UE 27 Change to the Current RMS Offset Compensation Section 29 Edits to Active Power Frequency Output Section 33 Added Figure 68
102. 8v 10212 odOLl3W Nn ON _ ORO 9 2 9 2 9 5 Uv S31N35IA SY2IH12313 4801502 ap NOD uvin21v2 40d Mad je ug 501502 v1121v2 5 v1uv1noTv3 AN ZELLE ON isa SWHIA SSHO TVA NC ID TO 31N3IHHO2 A 3v E10A 30 S3HOTVA VSN3S 5 VONO WHOS 30 SISITENY A3dMWocgigaw NN NOIQVIN3SNITY 30 SIN l NQIMO A a4 ON LLLI IJ 05 I I L WLNW1d 30 318v 40d Oval 2373 ag OWNSNOD VINALSIS 13 OTIOYeAVS30 13 OFN Td VIAVeHS VIG OXANV Tesis publicada con autorizaci n del autor 2 S 2 5 2 E 2 e 2 2 al i 20 lt Me LLJ un e an m e cc c2 PONTIFICIA UNIVERSIDAD CAT LICA DEL PERU TESIS PUCP SOCIETE HVHILSON LANHSHLA SOY Tn Tw SOLIVC HYIAN3 HVHISON v NOMVIINNWOS 30 30d VAY TY VIHOWSMN Y NOLOIOV Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos R
103. 995 PARAMETER MEASUREMENT INFORMATION VID i tk do b Figure 1 Driver and Figure 2 Receiver and VoL MM Input 1 5 V 1 5 V L 50p RL 60 see Note B m Generator Output td OD Te gt e td OD see Note A l TEST CIRCUIT VOLTAGE WAVEFORMS NOTES A The input pulse is supplied by a generator having the following characteristics PRR 1 MHz 50 duty cycle lt 6 ns tf 6 ns Zo 50 Q B Cj includes probe and jig capacitance Figure 3 Driver Test Circuit and Voltage Waveforms Output 3y Input 15V 15V 0 V 0 5 V tpzH 4 1100 RAN Output 23V tpHz 7 Voff 0V TEST CIRCUIT VOLTAGE WAVEFORMS Generator CL 50 pF see Note B see Note NOTES The input pulse is supplied by a generator having the following characteristics PRR 1 MHz 50 duty cycle tr lt 6 ns t 6 ns ZCy DU B includes probe and jig capacitance Figure 4 Driver Test Circuit and Voltage Waveforms 435 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 Censmto see Note B 5 see Note A Output 2 3 V A VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES A The input pulse is supplied by a generator having the following characteristics PRR 1 MHz 50 duty cycle tp
104. A REGISTRO PEDIDO PREPARA CADENA DE LECTURA LEE REGISTRO PEDIDO DEL ADE7758 MEDIANTE 5 1 RECEPCION SPI EXITOSA 5 CARGA BUFFER CON DATO SENSADO PREPARA TRAMA FIN DE LA CONEXION DESCONECTA DE LA RED EL DIAGRAMA DE FLUJO DEL SISTEMA DE CONTROL SIGUE LA LOGICA PARA EL MANEJO DEL TRANSDUCTOR DE PARAMETROS ELECTRICOS Y SU POSTERIOR ENVIO DE INFORMACION Figura 3 19 Diagrama de flujo del software Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CAT LICA DEL PERU 3 4 ETAPA DE INGRESO DE DATOS Esta etapa consta b sicamente de un teclado matricial de 4x4 el cual ser el encargado de recibir las acciones del usuario y enviarlas al microcontrolador para su procesamiento A DISE O DE LA ETAPA TECLADO MATRICIAL DE 4x4 ESTA ETAPA COMPRENDE UN DISE O SIMPLE REALIZADO CON UNA LOGICA DE CONTACTORES QUE HABILITAN LAS DIVERSAS FILAS Y COLUMNAS AL CUAL SE HALLE CONECTADO Figura 3 20 Esquema circuital de la etapa de ingreso de datos Para esta parte no se requiere una gran descripci n como se puede observar en la Figura 3 20 se ha hecho uso de una etapa de ingreso de datos la cual est b sicamente conformada por un teclado de 4x4 que dar al usuario las teclas necesarias para la configuraci n del sistema Tesis publicada con autorizaci n del autor SOME RIGHTS RESER
105. ADE7758 can be used directly with a conventional current sensor such as a current transformer CT or a low resistance current shunt PEAK CURRENT DETECTION The ADE7758 can be programmed to record the peak of the current waveform and produce an interrupt if the current exceeds a preset limit Peak Current Detection Using the PEAK Register The peak absolute value of the current waveform within a fixed number of half line cycles is stored in the IPEAK register Figure 47 illustrates the timing behavior of the peak current detection L2 L1 CURRENT WAVEFORM PHASE SELECTED BY PEAKSEL 2 0 IN MMODE REGISTER LINECYC 15 0 REGISTER CONTENT OF IPEAK 7 0 04443 047 Figure 47 Peak Current Detection Using the IPEAK Register Note that the content of the IPEAK register is equivalent to Bit 14 to Bit 21 of the current waveform sample At full scale analog input the current waveform sample is 0x2851EC The IPEAK at full scale input is therefore expected to be OxA 1 In addition multiple phases can be activated for the peak detection simultaneously by setting more than one of the PEAKSEL 2 4 bits in the MMODE register to logic high These bits select the phase for both voltage and current peak measurements Note that if more than one bit is set the VPEAK and IPEAK registers can hold values from two different phases that is the voltage and current peak are independently processed see the Peak Current Detection sectio
106. B ORC CFNUM VARCFNUM SET TO CALCULATE VALUES SET UP SYSTEM FOR PF 1 SET CFNUM VARCFNUM AND CFDEN VARCFDEN TO CALCULATED VALUES MEASURE ERROR FOR APCF AND VARCF CALCULATE AND WRITE TO xWG xVAG CALCULATE Wh LSB AND VAh LSB CONSTANTS MEASURE ERROR FOR VARCF CALCULATE VARh LSB CONSTANT gt e st e Figure 77 Gain Calibration Using Pulse Output Step 1 Enable the pulse output by setting Bit 2 of the OPMODE register 0x13 to Logic 0 This bit enables both the APCF and pulses Step 1a VAR and VA share the pulse output WAV MODE 7 Address 0x15 should be set to choose between VAR or VA pulses on the output Setting the bit to Logic 1 selects VA The default is Logic 0 or VARCF pulse output Step 2 Ensure the xWG xVARG xVAG are zero Step 3 Disable the Phase B and Phase C contribution to the APCF and pulses This is done by the TERMSEL 2 4 bits of the COMPMODE register 0x16 Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs Select Phase A Phase B or Phase C for a line period measurement with the FREQSEL 1 0 bits in the MMODE register 0x14 For example clearing Bit 1 and Bit 0 selects Phase A for line period measurement Rev C Page 44 of 72 Step 4 Set APCFNUM 0x45 and APCFDEN 0x46 to t
107. CA DEL PERU CAP TULO 3 DISENO E IMPLEMENTACI N DE LA INTERFAZ DIGITAL El sistema de control digital para medici n consta b sicamente de 5 etapas Pre procesamiento de datos visualizaci n ingreso de datos expansi n control y comunicaci n La distribuci n de las mencionadas etapas es la siguiente PRE PROCESAMIENTO CONTROL Y COMUNICACION DE DATOS INGRESO DE DATOS EXPANSI N Figura 3 1 Diagramas de bloques de la interfaz digital Para el diseno de cada etapa se realiz una investigaci n respecto de componentes consideraciones de diseno acordes con la tecnolog a a aplicar Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA m TESIS PUCP 5 CAT LICA DEL PERU 3 1 ETAPA DE PRE PROCESAMIENTO DE DATOS A PRE PROCESADOR DE PARAMETROS EL CTRICOS Descripci n El pre procesador de par metros el ctricos se encarga de recibir la anal gica acondicionada de la red digitalizarla evaluarla y procesarla para convertirla en un dato que pueda ser entendido por un microcontrolador El tipo de pre procesador depender en gran parte de las caracter sticas de la red el ctrica a la cual se requiera conectar el dispositivo para ello el pre procesador podr ser del tipo monof sico o trif sico Criterios de selecci n Para el proyecto se seleccionar un pre procesador de par
108. CION COMERCIAL DEL MODULO TEMPUS VI ES EN EQUIPOS MARCADORES DE PERSONAL Y CONTROL DE ACCESO Figura 2 12 Aplicaci n actual de la tarjeta TEMPUS VI En el Cap tulo 3 Secci n Etapa de control y comunicaci n P g 55 se describe detalladamente la tecnolog a que contiene el m dulo adem s se presenta el estudio que se realiz para acondicionarlo al proyecto de tesis el cual innova su aplicaci n convirti ndolo en un sistema de control digital para medici n de energ a Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CAT LICA DEL PERU 2 3 TECNOLOG AS PARA LA INTERCONEXI N ENTRE PERIF RICOS La comunicaci n entre perif ricos electr nicos es el transporte informaci n enviadas mediante se ales anal gicas o digitales por un medio f sico El tipo de comunicaci n es diversa y en distintos niveles para el objeto que nos ocupa el proyecto se encargar de comunicar circuitos integrados dentro de una misma tarjeta o m dulos Para este fin quedar a analizar las diversas soluciones aplicables Por un lado tenemos a los circuitos integrados con l gicas de comunicaci n cuya aplicaci n genera mayores costos por el uso de hardware adicional sin embargo cuenta con gran flexibilidad en el transporte de datos y por otro lado tenemos las l gicas de buses seriales que no requieren hardware adicional por ende m s
109. CIRMS One LSB of the current rms register is equivalent to one LSB of the current waveform sample The update rate of the current rms measurement is CLKIN 12 AIRMSOS 11 0 225 224 223 217 216 215 0x2851EC 0x0 0x1D3781 0x00 0 07 14 i LPF3 2 CURRENT SIGNAL FROM HPF OR ela pio gt AIRMS 24 0 INTEGRATOR IF ENABLED i Figure 62 Current RMS Signal Processing With the specified full scale analog input signal of 0 5 V the ADC produces an output code that is approximately 2 642 412d see the Current Channel ADC section The equivalent rms value of a full scale sinusoidal signal at 60 Hz is 1 914 753 0x1D3781 The accuracy of the current rms is typically 0 596 error from the full scale input down to 1 500 of the full scale input Additionally this measurement has a bandwidth of 14 kHz It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability The IRQ can be used to indicate when a zero crossing has occurred see the Interrupts section Table 6 shows the settling time for the IRMS measurement which is the time it takes for the rms register to reflect the value at the input to the current channel Table 6 Settling Time for IRMS Measurement 10096 Integrator Off 960 ms Integrator On 1 68 sec Rev C Page 28 of 72 Current RMS Offset Compensation The ADE7758 incorporates a current rms offset compensation register for each phase AIRMSOS B
110. DR TAPE AND REEL BOX INFORMATION paca Se iens wi sean SN75176ADR 342 9 336 6 20 64 Pack Materials Page 2 MECHANICAL DATA MPDIOO1A JANUARY 1995 REVISED JUNE 1999 P R PDIP T8 PLASTIC DUAL IN LINE 0 400 10 60 0 355 9 02 0 260 6 60 0 240 6 10 E E 4 0 070 1 78 0 020 0 51 0 325 8 26 0 300 7 62 0 015 0 38 4 Gage Plane Y Seating Plane 0 010 0 25 NOM 0 125 3 18 MIN gt 0 430 10 92 0 200 5 08 0 078 038 10 010 0 25 5 0 015 0 38 4040082 D 05 98 NOTES A Alllinear dimensions are in inches millimeters B This drawing is subject to change without notice C Falls within JEDEC 5 001 For the latest package information go to http www ti com sc docs package pkg_info htm 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MECHANICAL DATA D R PDSO G8 PLASTIC SMALL OUTLINE PACKAGE 0 244 6 20 0 228 5 80 0 157 4 00 0 150 3 80 A Pin 1 Index Area 4 ess SUTTON E EA 310 004 0 10 seating Plane 0 016 0 40 4040047 2 H 11 2006 All linear dimensions are in inches millimeters This drawing is subject to change without notice Body length does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 006 0 15 per end Body
111. E E PONTIFICIA m TESIS PUCP UNIVERSIDAD DEL PERU Consideraciones de dise o La configuraci n de los pines del LCD 16x2 es est ndar para los fabricantes y se encuentra detallada en su hoja de datos e Los pines 4 E 6 RS van conectados al microcontrolador con el primero se habilita el uso del visualizador y con el segundo se indica el modo de acceso a sus registros internos Estas funciones se dan acorde a la l gica del microcontrolador e El pin 5 R W va conectado a tierra para encontrarse siempre en modo ESCRITURA pues no se requerir leer los registros internos del LCD e El pin 3 Vo es una entrada anal gica que maneja el contraste del LCD se le conecta a un potenci metro de 10K el cual podr hacerlo variar desde 0 a 5V en una escala adecuada e Los pines 15 BL 16 BL son opcionales de los LCDs de 16x2 que controlan iluminaci n backlight han sido considerados en el diseno pero no son limitantes para el correcto funcionamiento del equipo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 3 3 ETAPA DE CONTROL Y COMUNICACI N A M DULO DE CONTROL Y COMUNICACI N Descripci n Un m dulo de control como su nombre lo indica es un dispositivo encargado del control y manejo de otros dispositivos dentro del sistema Act a como un cerebro debido a q
112. E7758 e as pruebas del software realizadas con el hardware de medici n en lectura y escritura mediante SPI fueron satisfactorias Estableci ndose conexi n correctamente y obteniendo de los registros internos valores id nticos a los especificados en la hoja de datos del ADE7758 e as pruebas de comunicaci n ADE7758 ATmega128 no present errores salvo por fallas iniciales de sincronizaci n SPI e Se realizaron pruebas de las etapas de expansi n en conjunto con la lectura escritura de los registros internos del ADE7758 y los resultados fueron exitosos no encontr ndose retardos o fallas debidas al ruido Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS CATOLICA DEL PERU 4 3 AN LISIS DE COSTOS oe hizo un an lisis de costos en base al prototipo desarrollado y se le compar con algunos equipos comerciales A pesar que el prototipo no es un producto final y la comparaci n con los otros equipos no fue directa en base a los resultados obtenidos de diversos estudios se pudo constatar por que el prototipo posee buenos resultados ante productos comerciales y su desarrollo no va a conllevar a utilizar materiales costosos Entonces es requerido el uso de un sistema del tipo EEM que permita la medici n de diversos par metros el ctricos adem s de brindar comunicaci n Ethernet Existen ciertos requerimientos t
113. E7758 Overvoltage Detection Note that the content of the VPINTLVL 7 0 register is equivalent to Bit 6 to Bit 13 of the 16 bit voltage waveform samples therefore setting this register to 0x9D represents putting the peak detection at full scale analog input Figure 59 shows a voltage exceeding a threshold By setting the PKV flag Bit 14 in the interrupt status register the overvoltage event is recorded If the PKV enable bit is set to Logic 1 in the interrupt mask register the IRQ logic output goes active low see the Interrupts section Multiple phases can be activated for peak detection If any of the active phase produces waveform samples above the threshold the PKV flag in the interrupt status register is set The phase in which overvoltage is monitored is set by the PKIRQSEL 5 7 bits in the MMODE register see Table 19 Rev C Page 26 of 72 PHASE SEQUENCE DETECTION The ADE7758 has an on chip phase sequence error detection interrupt If the zero crossing of Phase A is not followed by Phase C but by Phase B the SEQERR bit Bit 19 in the STATUS register is set If SEQERR is set in the mask register the IRQ logic output goes active low see the Interrupts section Figure 60 depicts how the interrupt is issued in two different configurations Note that if it is desired to have the interrupt occur when Phase A is followed by Phase B and not Phase C then the analog inputs for Phase B and Phase C should be swapped In this
114. EF in out VN 2 Figure 5 Pin Configuration Table 4 Pin Function Descriptions Pin No Description 1 Active Power Calibration Frequency APCF Logic Output It provides active power information This output is used for operational and calibration purposes The full scale output frequency can be scaled by writing to the APCFNUM and APCFDEN registers see the Active Power Frequency Output section This provides the ground reference for the digital circuitry in the ADE7758 that is the multiplier filters and digital to frequency converter Because the digital return currents in the ADE7758 are small it is acceptable to connect this pin to the analog ground plane of the whole system However high bus capacitance on the DOUT pin can result in noisy digital current that could affect performance Digital Power Supply This pin provides the supply voltage for the digital circuitry in the ADE7758 The supply voltage should be maintained at 5 V 5 for specified operation This pin should be decoupled to DGND with a 10 uF capacitor in parallel with a ceramic 100 nF capacitor Analog Power Supply This pin provides the supply voltage for the analog circuitry in the ADE7758 The supply should be maintained at 5 V 596 for specified operation Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling The Typical Performance Characteristics show the power supply rejection performance This pin s
115. EQ register and is updated every four periods of the selected phase Bit 7 of the LCYCMODE selects whether the period register displays the frequency or the period Setting this bit causes the register to display the period The default setting is logic low which causes the register to display the frequency When set to measure the period the resolution of this register is 96 CLKIN per LSB 9 6 us LSB when CLKIN is 10 MHz which represents 0 0696 when the line frequency is 60 Hz At 60 Hz the value of the period register is 1737d At 50 Hz the value of the period register is 2084d When set to measure frequency the value of the period register is approximately 960d at 60 Hz and 800d at 50 Hz This is equivalent to 0 0625 Hz LSB LINE VOLTAGE SAG DETECTION The ADE7758 can be programmed to detect when the absolute value of the line voltage of any phase drops below a certain peak value for a number of half cycles Each phase of the voltage channel is controlled simultaneously This condition is illustrated in Figure 57 Figure 57 shows a line voltage fall below a threshold which is set in the SAG level register SAGLVL 7 0 for nine half cycles Because the SAG cycle register indicates a six half cycle threshold SAGCYC 7 0 2 0x06 the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register Bit 1 to Bit 3 in the interrupt status register If th
116. EXO E DISENO DEL SISTEMA 16 ANEXO F HOJAS TECNICAS Ma MEME 19 FUENTES Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU ANEXO A CONECTORES 9 40 x 23 70x 8 50 mm izq 13 30 x 23 70 x 10 50 mm der Nylon 66 TENSION NOMINAL DIMENSIONES LxAxH Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU DIMENSIONES LxAxH 20 57 x 15 88 x 13 60 mm Bronce 20 80 x 29 80 x 12 50 mm DIMENSIONES LxAxH Grey plastic Nylon MATERIAL Bronce 120V AC DC NIVELES DE TENSION 1 2A AC DC NIVELES DE CORRIENTE No se aplica CABLE PERMITIDO Gris COLOR 25 C 95 TEMPERATURA DIMENSIONES LxAxH 14 40 x 9 00 x 11 00 mm Bronce Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU ANEXO B COMUNICACI N IrDA A TRANSDUCTOR IrDA Descripci n Un transductor IrDA permite realizar conversi n de datos de una UART Universal asynchronous receiver transmitter o Receptor Transmisor Asincr nico Universal a la codificaci n IrDA que es el formato que utilizan las PDAs para realizar transmisi n por su puerto infrarrojo
117. GW h VENTAS DE ENERGIA 49 1 1 12451 14 14592 215546 16629 17 18375 19641 20701 217 ELECTRICA GW h 9 849 0 33 5 009 59 5546 16629 605 18375 196 0 70 53 COEFICIENTE DE ELECTRIFICACION 64 9 66 1 67 65 69 5 72 2 73 5 74 94 75 3 76 0 76 3 78 1 80 0 NACIONAL INDICADORES ENERGETICOS 23 345 23707 24073 24446 24824 25208 25598 25994 26396 26805 27219 27640 miles de habitantes Consumo de energ a el ctrica per c pita KW h hab Producci n de energ a el ctrica per c pita KW h hab Tabla 1 1 Evoluci n de indicadores del mercado el ctrico 1995 2006 Como se observa en la Figura 1 1 s lo en los ltimos 5 la energ a el ctrica producida Republica del Peru Ministerio de energ a y minas Direcci n general de electricidad Direcci n de promoci n y estudios 2006 medida en billones de vatio por horas GW h y la poblaci n INEI X Censo Nacional de Poblaci n 2005 del Peru Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis L PONTIFICIA TESIS UNIVERSIDAD DEL PERU afio 2006 medida en miles de habitantes muestran que la producci n de electricidad durante los ltimos 10 ha aumentado en un 58 3 mientras que el n mero habitantes s lo lo hizo en un 18 496 entonces si dividimos la cantidad de energ a el ctrica producida entre la poblaci n conseguimos la Figura 1 2 la
118. Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents Tl s knowledge and belief as of the date that it is provided Tl bases its knowledge and belief on information provided by third parties and makes no
119. IATION IRDA International organization that creates and promotes interoperable low cost infrared data interconnection www irda org Consultado 06 Jul 2006 24 LUIS ERNESTO BORGES Sistemas de lectura remota del consumo http neutron ing ucv ve Consultado 13 Nov 2006 25 ENERGY COMMISSION Energy Commission History http www a2gov org PublicServices SystemsPlanning Energy EnergyCommiss ionHistory html Consultado 16 Oct 2006 26 THE WORLD BANK www worldbank org Peru Data Profile http devdata worldbank org external CPProfile asp SelectedCountry PER amp C CODE PER amp CNAME Peru amp PT YPE CP Consultado 12 Ene 2007 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis TESIS PUCP PONTIFICIA UNIVERSIDAD CATOLICA DEL PERU Facultad de Ciencias e Ingenieria DISENO E IMPLEMENTACI N DE UN SISTEMA DE CONTROL DIGITAL CON CONEXI N A REDES DE DATOS PARA MEDICI N DE PAR METROS EL CTRICOS ANEXOS Presentado por Gerardo Manuel Guerrero Quichiz Lima Peru 2007 Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU RESUMEN La introducci n y continua mejora de elementos digitales en dispositivos que antes se consideraban ntegramente anal gicos han causado toda una revoluci n en los diverso
120. IGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Para hallar el valor de la potencia reactiva se puede aplicar la relaci n pitag rica activa _ 2 2 P ma m P Ecuacion 3 1 Este metodo otorga excelentes resultados con formas de onda puramente sinusoidales ideales pero notables errores aparecen ante la presencia de armonicos lo cual lo vuelve ineficiente ante senales reales adem s se requerir a conocer previamente los valores de Potencia Activa y Reactiva M todo del retardo de tiempo con filtro pasa bajos Un retardo de tiempo es introducido para mover una de las formas de onda en 90 de la frecuencia fundamental y finalmente multiplicar las dos formas de onda 1 Energia Re activa E v t dt Ecuaci n 3 2 0 Donde T es el periodo de la frecuencia fundamental Este m todo puede ser implementado por el retraso de muestreo de una de las entradas en un n mero de ciclos igual a un cuarto de ciclo de la frecuencia fundamental Pero se mediante el uso de un filtro pasa bajos de manera similar se consigue un desfase de 90 DESFASE DE 90 ACTA EL METODO DE RETARDO EN EL TIEMPO UTILIZA UN FPB PARA QUE REALICE UN DESFASE DE 90 EN LA SENAL DE VOLTAJE MUESTREADA Figura 2 8 Diagrama equivalente del m todo del retardo de tiempo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos
121. IGITAL 0x2851EC 0x00 REGISTRO DE OxD7AE14 POTENCIA ACTIVA TOTAL 40 0 CALIBRADOR SENAL DE VOLTAJE DIGITAL DE FASE 0x2852 xCCCCD E 0x00 xD7 AE LA LOGICA DE FUNCIONAMIENTO QUE SIGUE EL ADE7758 PARA EL CALCULO DE Pactiva ES INTEGRAMENTE DIGITAL Y SE DESPRENDE DE LAS ECUACIONES MOSTRADAS EN EL CAPITULO 2 Figura 3 7 L gica de funcionamiento del ADE7758 para el c lculo de potencia La senal de corriente anal gica ingresa y es ajustada por una Ganancia programable luego se le digitaliza siendo sus valores digitales a m xima escala 2642412 o con signo y complemento a 2 0x25851EC y 7 14 para el m ximo m nimo respectivamente despu s pasa por un filtro pasa altos FPA para remover algun posible desplazamiento en DC offset DC en ingl s luego se puede optar por la sefial acondicionada o pasarlo previamente por un integrador digital esta ultima opci n se aplica cuando la entrada de corriente pasa por una bobina de Rogowski esto se detalla en el Anexo C Tecnolog as para medici n de corriente Secci n Bobina Rogowski P g 11 y Anexo F Hojas t cnicas Hoja t cnica del ADE7758 Rev Secci n di dt current sensor and digital integrator P g 20 Por otro lado la se al de Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA m TESIS PUCP S CATOLICA D DEL PERU
122. ION FOR VADIV 7 0 ACTIVE POWER PHASE B APCFNUM 11 0 SEE PHASE A FOR DETAILED SIGNAL PATH VARONI WDIV 7 0 ACTIVE REACTIVE APPARENT ENERGIES AND VOLTAGE CURRENT RMS CALCULATION FOR ADE7758 REGISTERS AND APCFDEN 11 0 SERIAL INTERFACE PHASE C SEE PHASE A FOR DETAILED SIGNAL PATH AND PHASE C DATA 04443 001 DIN DOUT SCLK CS IRQ Figure 1 Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other _ rights of third parties that may result from its use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2006 Analog Devices Inc All rights reserved 7758 TABLE CONTENTS A TEM EDD EL E 1 General Descriptio aia ii 1 Functional Block Diagram suoni er erect 1 REVISION M 3 General Description 4 MD bt 5 Time Characters 6 A A 7 Absolute Maximum Ratings eese 8 8 Pin Configuration and Function 1 9 TEMNO P
123. IRMSOS and CIRMSOS These are 12 bit signed registers that can be used to remove offsets in the current rms calculations An offset can exist in the rms calculation due to input noises that are integrated in the dc component of I t Assuming that the maximum value from the current rms calculation is 1 914 753d with full scale ac inputs 60 Hz one LSB of the current rms offset represents 0 9496 of the measurement error at 60 dB down from full scale The IRMS measurement is undefined at zero input Calibration of the offset should be done at low current and values at zero input should be ignored For details on how to calibrate the current rms measurement see the Calibration section IRMS JIRMS 16384 x IRMSOS 9 where IRMS is the rms measurement without offset correction Table 7 Approximate IRMS Register Values Frequency Hz Integrator Off d Integrator On d 50 1 921 472 2 489 581 60 1 914 752 2 067 210 Voltage Channel RMS Calculation Figure 63 shows the details of the signal path for the rms calculation on Phase A of the voltage channel The voltage channel rms value is processed from the waveform samples after the low pass filter LPF1 The output of the voltage channel ADC can be scaled by 50 by changing VRMSGAIN 11 0 registers to perform an overall rms voltage calibration The VRMSGAIN registers scale the rms calculations as well as the apparent energy calculation because apparent power is the product of th
124. LK CLKIN and CS Input High Voltage Vinx Input Low Voltage Vint Input Current lin Input Capacitance Cin 2 4 0 8 3 10 mV max uA max kO min typ MHz max MHz min Rev C Page 5 of 72 Over a dynamic range of 1000 to 1 Line frequency 45 Hz to 65 Hz HPF on Phase lead 37 Phase lag 60 AVDD DVDD 5 V 175 mV rms 120 Hz VIP 2 V3P 100 mV rms AVDD DVDD 5V 250 mV dc VIP V2P V3P 100 mV rms Over a dynamic range of 500 1 Over a dynamic range of 20 1 See the Analog Inputs section Differential input Uncalibrated error see the Terminology section External 2 5 V reference Sampling CLKIN 128 10 MHz 128 78 1 kSPS See the Current Channel ADC section See the Voltage Channel ADC section 2 4 V 8 2 4 V 8 Nominal 2 4 V at REFinout pin All specifications CLKIN of 10 MHz DVDD 5 V 596 DVDD 5 V 596 Typical 10 nA 0 V to DVDD ADE7758 Parameter Specification Unit Test Conditions Comments LOGIC OUTPUTS 5 V 596 IRO DOUT and CLKOUT IRQ is open drain 10 pull up resistor Output High Voltage Vou Output Low Voltage APCF and VARCF Output High Voltage Vou Isource 5 mA 1 mA Isource 8 mA Output Low Voltage Isink 5 mA POWER SUPPLY For specified performance AVDD 5 V 596 5 V 5 DVDD 5 V 5 5 V 4 596 Alpp Typically 5 mA Dlpp Typically 9 mA 1 See the Typical Pe
125. METERING INTERNATIONAL 2003 Magazine archive Energy measurement ICs http www metering com archive 031 42 1 htm Consultado 28 Oct 2005 11 GERENCIA ADJUNTA DE REGULACI N TARIFARIA COMISI N DE TARIFAS EL CTRICAS 1997 Resoluci n de la comisi n de tarifas el ctricas No 024 97 P CTE http www cte org pe resoluciones pdf REO24 1997 Consultado 04 Nov 2005 12 Gobierno del Peru Decreto Supremo N 016 2000 EM Fijan horas de regulaci n y probabilidad de excedencia mensual de centrales hidr ulicas horas punta del sistema el ctrico y margen de reserva a que se refiere el Reglamento de la Ley de Concesiones El ctricas Incluye modificaciones seg n Decreto Supremo N 032 2001 EM Decreto Supremo 034 2001 EM y D S N 055 2002 EM Art culo 2 Promulgado 13 Sep 2000 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 13 Gobierno del Peru Decreto Supremo N 027 2003 EM Fijan horas de punta del Sistema El ctrico Interconectado Art culo 19 Promulgado 06 Ago 2003 14 JUAN LUIS HERNANDEZ 2004 Factor de Potencia http endrino cnice mecd es jhem0027 fdp fdp htm Consultado 28 Oct 2005 15 CRISTOPHER E STRANGIO 2005 The RS 232 standard CAMI Research Inc Lexington Massachusett USA http www camiresearch com Data Com B
126. N seconds The output from the temperature sensing circuit is connected to an ADC for digitizing The resultant code is processed and placed in the temperature register TEMP 7 0 This register can be read by the user and has an address of 0x11 see the Serial Interface section The contents of the temperature register are signed twos complement with a resolution of 3 C LSB The offset of this register may vary significantly from part to part To calibrate this register the nominal value should be measured and the equation should be adjusted accordingly Temp TEMP 7 0 Offset x 3 C LSB Ambient C 4 For example if the temperature register produces a code of 0x46 at ambient temperature 25 C and the temperature register currently reads 0x50 then the temperature is 55 C Temp 0x50 0x46 x 3 C LSB 25 55 C Depending on the nominal value of the register some finite temperature can cause the register to roll over This should be compensated for in the system master MCU The ADE7758 temperature register varies with power supply It is recommended to use the temperature register only in applications with a fixed stable power supply Typical error with respect to power supply variation is show in Table 5 Table 5 Temperature Register Error with Power Supply Variation 55V Register Value 219 216 214 211 208 ROOT MEAN SQUARE MEASUREMENT Root mean square rms is a fundament
127. No olvide citar esta tesis 3 PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Memoria Flash 128 Kbytes Memoria SRAM 4 096 bytes e Memoria EEPROM 4 Kbytes ABS ECC ASTI J 24 GEM MI IM eS ES hw J ADCA TCK PPS ADCE TMS T PES ADCE TDO J ADCZ TDI 7 GNG 51 D CADO O Pad AD 1 40 0 AD 4B 47 D 46 PAS ADS 46 E ADE 44 0 PAT AD 43 PGeLALE 42 PC A15 41 A14 40 POs 13 39 PC4 A12 38 11 STO 2 A10 36 PCI AG 35 0 PCO A8 34 0 PGAD m M TO Figura 3 17 Microcontrolador ATmega128 Empaquetado TQFP64 Dentro de sus consideraciones de software la tarjeta TEMPUS VI cuenta con e Logica de control del hardware para TCP IP y formacion de datagramas en la comunicaci n a red e Logica de manejo de pines digitales de Entrada Salida conversores analogos digitales ADC temporizadores internos UARTs buses de comunicaci n Reloj en Real TRC y espec ficamente control de la l gica SPI para comunicaci n con el pre procesador pantalla LCD para visualizaci n Teclado matricial de 4x4 para ingreso de datos actuadores comunicaci n serial por bus Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA
128. OS sssss 52 3 3 ETAPA DE CONTROL Y COMUNICACI N eme en nnne nennen 55 3 4 ETAPA DE INGRESO DE DATOS antaras 63 3 5 ETAPA DE EXPANSION eene Od 3 6 CONECTORES e HR 73 3 7 DISENO MECANICO DEL CHASIS 80 3 8 DISTRIBUCI N DE M DULOS e eme nnne nnne nnne nnn nene 82 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis re UNIVERSIDAD TESIS PUCP e UNIVERSID DEL PERU CAPITULO 4 EVALUACI N DE RESULTADOS 0occcccccoccccccnoncnccnncnnnonnn nora nn cnn 04 4 1 DESARROLLO DEL PROTOTIPO 84 4 2 EVALUACI N DE RESULTADOS 86 4 3 AN LISIS DE COSTOS nn 88 4 4 PRUEBAS DEL PROTOTIPO 90 4 5 RECOMBENDAGION FUENTES Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis TESIS PUCP LISTA DE FIGURAS Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis OS PONTIFICIA UNIVERSIDAD y CAT LICA DEL PERU P g CAP TULO 1 Figura 1 1 Comparaci n de la producci n de energ a el ctrica y la poblaci n en el Peru 2 Figura 1 2 Energ a el ctrica pr
129. OS Eg x x VRMS vu E V MIN VRMS vom 78 64 where Vmn is the full scale voltage 20 Vnom is the nominal line voltage ADE7 1758 VRMSvmn and VRMSvyou are the voltage rms register values without offset correction for the input and respectively Example Calibration of RMS Offsets For this example Irzsr 10 A Imax 100 A 220 V Veutiscate 500 V Power Factor 1 and Frequency 50 Hz Twenty readings are taken synchronous to the zero crossings of all three phases at each current and voltage to determine the average xIRMS and xVRMS readings At Irzsr and Vnom the example ADE7758 meter gets an average AIRMS 0x0A reading of 148242 2 and 744570 8 in the AVRMS 0x0D register Then the current is set to Imm Irvuscau 500 or 260 mA At Imm the average AIRMS reading is 3885 68 At Vruuscaiz 20 or 25 V the example meter gets an average AVRMS of 86362 36 Using this data 15d is written to AIRMSOS 0x36 and 31d is written to AVRMSOS 0x33 registers according to the Equation 77 and Equation 78 AIRMSOS 1 _ 10 x 3885 68 0 260 x 1482422 16384 0 260 10 14 8 15 O0xFF2 AVRMSOS 1 220 x 86362 36 25x 744570 8 ay 30 9 31 0 1 64 25 220 This example shows the calculations and measurements for Phase A only However all three xIRMS and xVRMS registers can be read simultaneously to compute the values for each
130. PSR measurement a reading at nominal supplies 5 V is taken A second reading is obtained with the same input signal levels when the power supplies are varied 5 Any error introduced is again expressed as a percentage of the reading ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs It means that with the analog inputs connected to AGND that the ADCs still see a dc analog input signal The magnitude of the offset depends on the gain and input range selection see the Typical Performance Characteristics section However when HPFs are switched on the offset is removed from the current channels and the power calculation is not affected by this offset Gain Error The gain error in the ADCs of the ADE7758 is defined as the difference between the measured ADC output code minus the offset and the ideal output code see the Current Channel ADC section and the Voltage Channel ADC section The difference is expressed as a percentage of the ideal code Gain Error Match The gain error match is defined as the gain error minus the offset obtained when switching between a gain of 1 2 or 4 It is expressed as a percentage of the output ADC code obtained under a gain of 1 Rev C Page 11 of 72 7758 TYPICAL PERFORMANCE CHARACTERISTICS PERCENT ERROR 04443 006 PERCENT FULL SCALE CURRENT Figure 6 Active Energy Error as a Percentage of Reading Gain 1 over Temperatur
131. REMENT FREQUENCY KNOWN STEP 9A CALIBRATE WATT STEP 8 RESET STATUS REGISTER READ ALL xWATTHR AND xVAHR AFTER STEP 10 WRITE TO xWG AND ADE7 1758 Step 2 Select Phase A Phase B or Phase C for a line period measurement with the FREQSEL 1 0 bits in the MMODE register 0x14 For example clearing Bit 1 and Bit 0 selects Phase A for line period measurement Step 3 Set up ADE7758 for line accumulation by writing OxBF to LCYCMODE This enables the line accumulation mode on the xWATTHR xVARHR and xVAHR 0x01 to 0x09 registers by setting the LVAR and LVA bits LCYCMODE 0 2 0x17 to Logic 1 It also sets the ZXSEL bits LEYCMODE 3 5 to Logic 1 to enable the zero crossing detection on all phases for line accumulation Additionally the FREQSEL bit LCYCMODE 7 is set so that FREQ 0x10 stores the line period When using the line accumulation mode the RSTREAD bit of LCYCMODE should be set to 0 to disable the read with reset mode Select the phase for line period measurement in MMODE 1 0 Step 4 Set the number of half line cycles for line accumulation by writing to LINECYC 0x1C SET UP TEST SYSTEM FOR PF 0 INDUCTIVE AND VA PF 1 STEP 12 RESET STATUS REGISTER READ ALL xVARHR AFTER LENERGY INTERRUPT STEP 14 CALCULATE xVARG LENERGY INTERRUPT CALCULATE Wh LSB VAh LSB
132. RESET STATUS REGISTER READ ALL xWATTHR REGISTERS AFTER LENERGY INTERRUPT CALCULATE xWATTOS FOR ALL PHASES WRITE TO ALL xWATTOS REGISTERS SET UP SYSTEM FOR lest Vnom O PF 0 INDUCTIVE REPEAT STEP 3 TO STEP 8 FOR xVARHR xVAROS CALIBRATION With Irzsr and 0 5 inductive power factor the example ADE7758 meter shows 7318d in the AWATTHR 0x01 register For unity power factor after gain calibration the meter shows 14804d in the AWATTHR register This is equivalent to 1 132 error 7318 14804 ER 05 14804 2 Error 0 01132 1 132 The Phase Error in degrees using Equation 66 is 0 374 0 01132 43 Using Equation 72 the value written to APHCAL Ox3F if at 50 Hz the FREQ 0x10 register 2085d is 17d Note that a PHCAL LSB Weight of 1 2 us is used because the Error is negative Phase Error Aresin 0 374 APHCAL 0 374 ue couse 17 0x11 12 360 FOR STEP 8 CALCULATE xVAROS FOR ALL PHASES FOR STEP 8 WRITE TO ALL xVAROS REGISTERS 04443 083 Figure 83 Power Offset Calibration Using Line Accumulation Rev C Page 52 of 72 Power Offset Calibration Using Line Accumulation Power offset calibration should be used for outstanding performance over a wide dynamic range 1000 1 Calibration of the power offset is done at or close to the minimum current The ADE7758 has power offset registers for watts and VAR xWATTOS 0x39 to 0x3B a
133. RMS x IRMS xt 26 where t is the accumulation time Note that line cycle active energy accumulation uses the same signal path as the active energy accumulation The LSB size of these two methods is equivalent Using the line cycle accumula tion to calculate the kWh LSB constant results in a value that can be applied to the WATTHR registers when the line accumulation mode is not selected see the Calibration section REACTIVE POWER CALCULATION A load that contains a reactive element inductor or capacitor produces a phase difference between the applied ac voltage and the resulting current The power associated with reactive elements is called reactive power and its unit is VAR Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase shifted by 90 ADE7 1758 Equation 30 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by 90 v t J2V sin wt 0 27 i t 42 I sin wt i t J2I 2 3 28 where rms voltage i rms current total phase shift caused by the reactive elements in the load Then the instantaneous reactive power q t can be expressed as q t v t x 70 29 q t VI cos 0 z VI cos 2wt 0 4 en where i t is the current waveform phase shifted by 90 Note that 1 can be rewritten as q t VI sin 0 VI sin 2wt 30 The average
134. RVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP E pe queries CAT LICA DEL PERU gt La Potencia activa ser la componente DC de la se al p t de la ecuaci n 2 3 Para eliminar la componente en AC de la ecuaci n y por ende hallar el valor de la potencia activa de manera pr ctica se aplica un Filtro Pasa Bajos FPB con frecuencia de corte menor a la frecuencia de la componente en AC P O Ya Ls Ecuaci n 2 4 e Medidores de potencia reactiva anal gica Por lo general son medidores de potencia activa ordinarios en los que la bobina de corriente se inserta en serie con la carga de la manera usual en tanto que la bobina de voltaje se arregla para recibir un voltaje en cuadratura con el voltaje de la carga e Medidores de potencia reactiva digital La implementaci n digital de la potencia reactiva se torna compleja en un sistema electr nico y m s a n a un costo razonable pues requiere un dedicado procesamiento digital de se ales DSP por sus siglas en ingl s para el desarrollo de la transformada de Hilbert con el objetivo de hallar la constante de la condici n de 90 por cada frecuencia Ante esta dificultad se han desarrollado diversas soluciones M todo del tri ngulo de potencia Este m todo est basado en el uso de las tres energ as aparente activa y reactiva Potencia Reactiva Q Potencia Activa P Tesis publicada con autorizaci n del autor SOME R
135. SPI POSEE UN FORMATO DE TRAMAS PARA LEER O ESCRIBIR SOBRE LOS DISPOSITIVOS A LOS QUE SE COMUNICA Figura 3 13 Modo Lectura y Escritura desde el ADE7758 al microcontrolador En donde el byte de comando se define como 7 DBS DB4 DBS 082 DBT DBO El valor de DB ser 1 para escritura W y ser 0 para lectura R Los valores de 0 6 indican un valor de registro interno del chip de medici n Esto se detalla en el Anexo F Hojas t cnicas Hoja t cnica del ADE7758 Rev C Secci n Communications register P g 60 Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 3 2 ETAPA DE VISUALIZACION DE DATOS A VISUALIZADOR Descripci n Dispositivo que se encarga de mostrar gr ficamente los datos enviados por el microcontrolador El visualizador especifico que se utilizar para este desarrollo es del tipo LCD Pantalla de Cristal Liquido por sus siglas en ingl s Liquid Cristal Display Criterios de selecci n En el proyecto se requiere visualizar los datos de la serial muestreada en valores discretos Por ello se plantea el criterio de elegir una pantalla LCD que cumpla con la caracter stica de mostrar valores alpha num ricos con capacidad de d gitos no mayor a 20 por l nea y con un m ximo de 2 l neas para visualizaci n Su voltaje de operaci n deber
136. T ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ222 Digi Key No P 2 2K JCT ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ122 Digi Key No P 1 2K JCT ND SMD 0402 Resistor Surface Mount Panasonic ERJ 2GEJ561 Digi Key No P 560 JCT ND SMD 2010 Resistor Surface Mount Panasonic ERJ 12ZY334 Digi Key No P 330K WCT ND SMD 1206 Resistor Surface Mount Panasonic ERJ 8GEYJ102 Digi Key No P 1K ECT ND SMD 1206 Resistor Surface Mount Panasonic ERJ 8GEYJ821 Digi Key No P 820 ECT ND Resistor Surface Mount Panasonic ERJ 8GEYJ200 Digi Key No P 20 ECT ND Through hole Panasonic Digi Key No P470W 1BK ND SMD 1206 Resistor Surface Mount Panasonic ERJ 8GEYJ100 Digi Key No P 10 ECT ND SMD 0805 Capacitor Surface Mount Panasonic ECJ 2VB1H333K Digi Key No PCC 1834 CT ND EIA size A Capacitor Surface Chip Cap Panasonic ECS TOJY106R Digi Key No PCS 1106CT ND 3 2 mm x 1 6 mm 559 C6 C7 C10 C12 100 nF Multilayer Ceramic SMD 0805 Capacitor Surface Mount C14 C15 C19 1096 16 V X7R Panasonic ECJ 2VB1E104K Digi Key No PCC 1812 CT ND C8 C9 22 pF Multilayer Ceramic 596 SMD 0402 Capacitor Surface Mount 50 V NPO Panasonic ECU E1H220JCO Digi Key No PCC 220COCT ND C11 6 3 V 220 uF Electrolytic Through hole Panasonic ECA OJFQ221 Digi Key P5604 ND D 6 3 mm H 11 2 mm Pitch 2 5 mm Dia 0 5 mm C16 10 nF 250 V Class X2 Metallized Polyester Film Through Hole Panasoni
137. TESIS PUCP PONTIFICIA UNIVERSIDAD CATOLICA DEL PERU Esta obra ha sido publicada bajo la licencia Creative Commons Reconocimiento No comercial Compartir bajo la misma licencia 2 5 Peru Para ver una copia de dicha licencia visite http creativecommons org licenses by nc sa 2 5 pe SOME RIGHTS RESERVED i lt PONTIFICIA QU UNIVERSIDAD CATOLICA DEL PER TESIS PONTIFICIA UNIVERSIDAD CATOLICA DEL PERU Facultad de Ciencias e Ingenieria DISENO E IMPLEMENTACI N DE UN SISTEMA DE CONTROL DIGITAL CON CONEXI N A REDES DE DATOS PARA MEDICI N DE PAR METROS EL CTRICOS Tesis para optar el titulo de ingeniero electr nico Presentado por Gerardo Manuel Guerrero Quichiz Lima Peru 2007 Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU RESUMEN La introducci n y continua mejora de elementos digitales en dispositivos que antes se consideraban ntegramente anal gicos han causado toda una revoluci n en los diversos campos de los sistemas electr nicos Dichos cambios han logrado integrar sistemas que hasta hace unos anos no se consideraban dentro de una misma rea tem tica El presente proyecto de tesis busca ampliar la aplicaci n de la electr nica digital fusionando el rea de Electricidad con la de Comunicaciones y desarrollando un oistema d
138. THR ewo _ 9 63 MEASURED Step 9b Calculate the values to be written to the xVAG registers according to the following equation VAHR EXPECTED 4x MCX Ippon X Vnom x AccumTime a VARCFDEN 1 1000 x 3600 VARCFNUM VADIV 64 VAG VAHR x22 VAHR mrasureD Step 10 Write to x WG and xVAG Step 11 Set the test system for Irzsr Vnom and zero power factor inductive to calibrate VAR gain Step 12 Repeat Step 7 Step 13 Read the xVARHR 0x04 to 0x06 after the LENERGY interrupt and store the values Step 14 Calculate the values to be written to the xVARG registers to adjust VARCF to the expected value 4x x Ig X X Sin O x AccumTime 1000 x 3600 VARCFDEN 1 VARDIV 65 VARHR gy pacrep VARHR MEASURED xVARG Step 15 Write to xVARG Step 16 Calculate the Wh LSB VARh LSB and VAh LSB constants Wh X Vnom x cos 0 x AccumTime 66 LSB 3600 x xWATTHR VAh X Vyoy X AccumTime 67 LSB 3600 x xVAHR VARh X Vnom X sin 0 x AccumTime 68 LSB 3600 x xVARHR Example Watt Gain Calibration Using Line Accumulation This example shows only Phase A watt calibration The steps outlined in the Gain Calibration Using Line Accumulation section show how to calibrate watt VA and VAR AII three phases can be calibrated simultaneously because t
139. VARh LSB 04443 081 xVAG Figure 81 Gain Calibration Using Line Accumulation Rev C Page 49 of 72 7758 Step 5 Set the LENERGY bit MASK 12 0x18 to Logic 1 to enable the interrupt signaling the end of the line cycle accumulation Step 6 Set the test system for Iresr Vnom and unity power factor calibrate watt and VA simultaneously and first Step 7 Read the FREQ 0x10 register if the line frequency is unknown Step 8 Reset the interrupt status register by reading RSTATUS 0x14 Step 9 Read all six xWATTHR 0x01 to 0x03 and xVAHR 0x07 to 0x09 energy registers after the LENERGY interrupt and store the values Step 9a Calculate the values to be written to x WG registers according to the following equations WA TTHARgxpecrep 4x MC x Ig X Vyoy X cos 0 x AccumTime 60 A A M x 1000 x 3600 APCFDEN 1 APCFNUM WDIV where AccumTime is LINECYC 15 0 2xLine Frequency x No of Phases Selected where MC is the meter constant 0 is the angle between the current and voltage Line Frequency is known or calculated from the FREQ 11 0 register With the FREQ 11 0 register configured for line period measurements the line frequency is calculated with Equation 62 1 E 62 FREQ 11 0 x9 6x10 62 Line Frequency No of Phases Selected is the number of ZXSEL bits set to Logic 1 in LCYCMODE 0x17 Then xWG is calculated as WAT
140. VED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 35 ETAPA DE EXPANSION A nivel de ingenier a los cambios se presentan de manera constante e inesperada por elo los proyectos deben de estar en capacidad de adaptarse r pidamente y sin inconvenientes la etapa de expansi n de este proyecto de tesis tiene como objeto permitir que el prototipo pueda ser adaptado a otros dispositivos o sistemas mayores oe ha implementado la l gica de comunicaci n por bus diferencial denominado RS 485 esta l gica permitir comunicar otros dispositivos que se ubiquen a grandes distancias Adicionalmente se ha desarrollado una etapa de actuadores externos de este modo busca aplicar la caracter stica de manejo de actuadores externos o control de acceso que presenta el m dulo TEMPUS VI A COMUNICACI N SERIAL RS 485 Descripci n Frecuentemente los microcontroladores cuentan con buses y puertos de comunicaci n serial los cuales son usados por los m dulos como puertos de comunicaci n con protocolo est ndar Criterios de selecci n En el caso de este proyecto se plantea hacer uso de un protocolo de comunicaci n por bus serial que permita transmitir datos a grandes distancias superiores a los 15m y que sea en lo posible insensible ante el ruido de campos electromagn ticos externos generados por algun equipo como un transformador o generador en donde se halle cercano el
141. a dashed line This is the objective of the compensation network CN 20 al 40 4 20dB HN 60 4 30dB HAAL 0 T 100 10 100 1k 10k FREQUENCY Hz Figure 13 Antialias Network Phase and Magnitude Response after Compensation The method of compensation works well when the pole due to shunt inductance is less than 25 kHz or so If zero is at a much higher frequency its effects may simply be eliminated by placing an extra RC on Channel 1 with a pole that is a decade greater than that of the antialias filter e g 100 O and 33 nF Care should be taken when selecting a shunt to ensure its parasitic inductance is small This is especially true of shunts with small values of resistance e g 200 uQ Note that the smaller the shunt resistance the lower the zero frequency for a given parasitic inductance Zero RsH1 Lsh1 POWER SUPPLY DESIGN This design uses a simple low cost power supply based on a capacitor divider network e C17 and C18 Most of the line voltage is dropped across C17 a 470 nF 250 V metalized polyester film capacitor The impedance of C17 dictates the effective VA rating of the supply How ever the size of C17 is constrained by the power consumption specification in IEC1036 The total power consumption in the voltage circuit including power sup ply is specified in section 4 4 1 1 of IEC1036 1996 9 The total power consumption in each phase is 2 W and 10 VA under nomina
142. a para calcular el voltaje o la corriente RMS de forma digital sigue la misma l gica de funcionamiento s lo diferenciadas por el tipo de se al de entrada Para calcular el valor RMS los instrumentos digitales utilizan dos m todos que se pueden definir como el m todo te rico y el m todo del filtro pasa bajos M todo te rico Consiste en aplicar el conocimiento te rico de la definici n RMS de ese modo el c lculo de una se al variable en el tiempo sera 1 2 fum at Ecuaci n 1 1 2 1 TI Si la se al ha sido muestreada previamente es decir se han tomado peque os valores en ciertos periodos de tiempo los cuales poseen una frecuencia de muestreo mucho mayor que la frecuencia de la variable en el tiempo la definici n vendr a a ser N Pus DX Ecuaci n 1 2 n l Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis lt UNIVERSIDAD TESIS PUCP CAT LICA DEL PERU M todo del filtro pasa bajos Es un m todo pr ctico para el c lculo del valor RMS y consiste que a partir de una se al muestreada como la presentada en la Ecuaci n 1 3 f t foa sen wt Ecuaci n 1 3 sea donde a 92 Frys sen wt gt Elevando al cuadrado la sefial muestreada sen 2wt Considerando la raz n trigonom trica 2 1 f 1 go Jn cos 2wt Ecua
143. ad di dt La salida de voltaje de la bobina depende solamente de los cambios en la corriente primaria Cuando se conecta a un circuito integrado con integrador digital incluido en el chip hacer un medidor con una bobina Rogowski es tan sencillo como usar sensores de corriente como el TC o el Shunt La bobina con nucleo de aire no tiene hist resis saturaci n o problemas de no linealidad Adem s tiene una capacidad extraordinaria para manejar altas corrientes donde el l mite superior te rico de la bobina es el voltaje de ruptura breakdown del mismo aire Dado que la salida de la bobina Rogowski es proporcional a la derivada del tiempo de la corriente es necesario usar un integrador para convertirlo al formato i t En el dominio de frecuencia esto es equivalente a una atenuaci n de 20 dB dec y un cambio constante de fase de 90 Las figuras muestran las respuestas de frecuencia de fase del integrador digital implementado para medici n de energ a en el circuito integrado ADE7758 de Analog Devices 5 55 60 FREQUENCY FREQUENCY Hz e TW e EI AH IST MDN 10 Ml al i a Mi NN GAIN dB e Figura Respuesta de frecuencia y fase del integrador digital del ADE7758 Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Como se puede ver
144. al measurement of the magnitude of an ac signal Its definition can be both practical and mathematical Defined practically the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load Mathematically the rms value of a continuous signal f t is defined as FRMS E FO dt 5 For time sampling signals rms calculation involves squaring the signal taking the average and obtaining the square root FRMS gt 6 The method used to calculate the rms value in the ADE7758 is to low pass filter the square of the input signal LPF3 and take the square root of the result see Figure 62 i t N2 x IRMS x sin wt 7 then i t IRMS IRMS x cos wt 8 The rms calculation is simultaneously processed on the six analog input channels Each result is available in separate registers While the ADE7758 measures nonsinusoidal signals it should be noted that the voltage rms measurement and therefore the apparent energy are bandlimited to 260 Hz The current rms as well as the active power have a bandwidth of 14 kHz Current RMS Calculation Figure 62 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel The current channel rms value is processed from the samples used in the current channel waveform sampling mode The current rms values are stored in unsigned 24 bit registers AIRMS BIRMS and
145. also changes all other calculations that use the current waveform In other words changing IGAIN changes the active reactive and apparent energy as well as the rms current calculation results IGAIN should not be used when using Mode 0 of CONSEL COMPMODE 1 0 Active Power Frequency Output Pin 1 APCF of the ADE7758 provides frequency output for the total active power After initial calibration during manufac turing the manufacturer or end customer often verifies the energy meter calibration One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency that is proportional to the energy or active power under steady load conditions This output frequency can provide a simple single wire optically isolated interface to external calibration equipment Figure 68 illustrates the energy to frequency conversion in the ADE7758 APCFNUM 11 0 INPUT TO AWATTHR REGISTER INPUT TO BWATTHR REGISTER gt U 2 INPUT TO CWATTHR REGISTER APCFDEN 11 0 Figure 68 Active Power Frequency Output 04443 068 A digital to frequency converter DFC is used to generate the APCF pulse output from the total active power The TERMSEL bits Bit 2 to Bit 4 of the COMPMODE register can be used to select which phases to include in the total power calculation Setting Bit 2 Bit 3 and Bit 4 includes the input to the AWATTHR BWATTHR and CWATTHR registers in the total active power
146. alue that can be stored in the reactive energy register before it overflows is 2 1 or 0 7 Because the average word value is added to the internal register which can store 2 1 or OxFE FFFF FFFF before it overflows the integration time under these conditions with VARDIV 0 is calculated as OxFF FFFF FFFF Time y 0 4 us 0 5243 sec 36 0xCCCCD When VARDIV is set to a value different from 0 the time before overflow are scaled accordingly as shown in Equation 37 Time Time VARDIV 0 x VARDIV 37 Energy Accumulation Mode The reactive power accumulated in each VAR hr accumulation register AVARHR BVARHR or CVARHR depends on the configuration of the CONSEL bits in the COMPMODE register Bit 0 and Bit 1 The different configurations are described in Table 13 Note that IA IB IC are the current phase shifted current waveform Table 13 Inputs to VAR Hr Accumulation Registers CONSEL 1 0 BVARHR CVARHR 00 VA x IA VC x IC 01 VA IA IB VC IC IB 10 IA IB VC x IC 11 Reserved Reserved Reserved The contents of the VAR hr accumulation registers are affected by both the current gain register IGAIN and the VAR gain register of the corresponding phase IGAIN should not be used when using Mode 0 of CONSEL COMPMODE 1 0 Reactive Power Frequency Output Pin 17 VARCF of the ADE7758 provides frequency output for the total reactive power Similar to
147. ante unos transductores de entrada llamados Conversores Anal gicos Digitales ADC luego dichos valores digitales ingresan a un m dulo de control dentro del equipo de medici n el cual se encarga de procesar los datos ingresados y dar como resultado un valor que ser equivalente al voltaje corriente o potencia seg n sea el algoritmo de control del dispositivo de medici n VISUALIZADOR PROCESADOR ANALOGICA DIGITAL INTERACCION CON EL USUARIO CONVIERTE LA SE AL DE ENTRADA EN SE AL DIGITAL Y LUEGO LA PROCESA CON SU COMPUTADOR INTERNO Figura 2 4 Diagrama b sico de un medidor digital Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 2 1 2 INSTRUMENTOS DE MEDICI N POR METODOLOG A e Medidores de voltaje y corriente rms anal gica Para medir los valores RMS tanto de voltaje como de corriente de manera anal gica los instrumentos de medici n son esencialmente electromec nicos Aprovechan el par til generado por la interacci n entre la corriente que circula por un bobinado interno del instrumento y el campo magn tico existente en el ambiente donde se encuentra dicho bobinado Este movimiento producido por el torque generado movimiento de D arsonval es usado para producir la deflexi n de la aguja del instrumento e Medidores de voltaje y corriente rms digital La metodolog
148. as Inteligentes S A C Todos los m dulos y etapas del sistema se encuentran funcionales De las etapas de programaci n en los diversos lenguajes e M dulo de medici n L gica realizada en codigo assembler utilizando para ello el software de programaci n y motor de compilaci n AVR Studio 4 Se desarroll una nueva rutina secuencial basada en la l gica multitareas del firmware original del TEMPUS VI l gica de interacci n con el ADE7758 manejo de teclado LCD comunicaci n a red Cabe destacar que el desarrollo del nuevo sistema requiri de un periodo ntegramente destinado al estudio de la tarjeta TEMPUS VI para manejar sus funciones y luego poder aplicarla como uno de los m dulos del proyecto de tesis Por pol ticas de confidencialidad de los productos de la empresa desarrolladora no tengo la autorizaci n de publicar los esquem ticos y o firmwares completos del equipo actual que ellos comercializan Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD TESIS PUCP CATOLICA DEL PERU 4 2 EVALUACI N DE RESULTADOS Para reconocer el establecimiento de conexi n se acondicion un software de comunicaci n PC TEMPUS VI llamado Winsock Winsock Tempus V Fomalo M ASCII Tipo de Cone n s HER Dente C Dec M o S Hosil 1281 1 51 Envi R
149. as specified by the IEC1000 4 4 i e ratio of peak pulse output unloaded and loaded 50 is 2 1 T 50A T100kW 40A 3kV 30A 2kV 20A 1kV 10A 0A 3 Figure 26 EFT Generator Output into 50 No Protection The plot in Figure 26 also shows the current and instantaneous power V x 1 delivered to the load The total energy is the integral of the power and can be approximated by the rectangle method as shown 15 approximately 4 mJ at 2 kV as per specification 2TA Figure 27 shows the generator output into 50 Q load with the MOV and some inductance 5 nH This is included to take into account stray inductance due to PCB traces and leads Although the simulation result shows that the EFT pulse has been attenuated 600 V and most of the energy being absorbed by the MOV only 0 8 mJ is delivered to the 50 Q load it should be noted that stray inductance and capacitance could ren der the MOV unless For example Figure 28 shows the same simulation with the stay inductance increased to 1 uH which could easily happen if proper care is not taken with the layout The pulse amplitude reaches 2 kV once again 800V T 20AT 8kW K N LEN aA 600V 6kW NA ALIE SS 3 00 3 04 08 3 12 3 16 3 20 TIME ws Figure 27 EFT Generator Output into 50 with MOV in Place 2kW VOLTS kV Figure 28 EFT Generator Output into 50 with MOV in Place and Stray Inductance of 1 uH Wh
150. asics RS232 standard html 16 THE MATHWORKS ACCELERATING THE PACE OF ENGINEERING AND SCIENCE 2005 Serial Port Interface Standard The MathWorks Inc USA http www mathworks com access helpdesk help toolbox instrument Consultado 28 Oct 2005 17 CISCO SYSTEMS INC 2005 Ethernet Technologies documentation http www cisco com univercd cc td doc cisintwk ito doc ethernet htm Consultado 28 Oct 2005 19 PROCOBRE Confiabilidad de Sistemas El ctricos http www procobreperu org c confiabelec pdf Consultado 30 Oct 2005 19 VIERA DE CARVALHO ARNALDO POVEDA MANUEL ZAK JUAN 1996 OLADE Diseno de Programas de Eficiencia energetica Revista Energ tica N 3 Septiembre Diciembre 1996 Pag 6 y 7 20 HANDHELD BASIC HB The best development enviroment for Palm Powered handhelds http www handheld basic com Consultado 06 Jul 2006 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 21 PALM ONE Welcome to palm http www palm com Consultado 06 Jul 2006 22 TEMPUS Tempus http www tempus com pe Consultado 06 Jul 2006 23 INFARED DATA ASSOCIATION IRDA International organization that creates and promotes interoperable low cost infrared data interconnection www irda org Consultado 06 Jul 2006 24 LUIS ERNESTO BORGES Sistemas de lectura remota
151. ates can be chosen by changing Bit 5 and Bit 6 of the WAVMODE register see Table 20 The available output sample rates are 26 0 kSPS 13 5 kSPS 6 5 kSPS or 3 3 kSPS By setting the WFSM bit in the interrupt mask register to Logic 1 the interrupt request output IRQ goes active low when a sample is available The 24 bit waveform samples are transferred from the ADE7758 one byte 8 bits at a time with the most significant byte shifted out first Rev C Page 22 of 72 The sign of the register is extended in the upper 8 bits The timing is the same as for the current channels as seen in Figure 40 ZERO CROSSING DETECTION The ADE7758 has zero crossing detection circuits for each of the voltage channels VAN VBN and VCN Figure 51 shows how the zero cross signal is generated from the output of the ADC of the voltage channel REFERENCE GAIN 6 5 x1 x2 x4 VAN A ZERO VBN z CROSSING VCN DETECTOR LPF1 f 260Hz ANALOG VOLTAGE VAN VBN OR VCN 1 0 LPF1 g 04443 051 b READ RSTATUS ____ Figure 51 Zero Crossing Detection on Voltage Channels The zero crossing interrupt is generated from the output of LPF1 LPF1 has a single pole at 260 Hz CLKIN 10 MHz As a result there is a phase lag between the analog input signal of the voltage channel and the output of LPF1 The phase response of this filter is shown in the Voltage Channel Sampling section The phase lag respons
152. atic 2 20 REV A Integrity Design amp Test Services Inc Y gt 3 gt e Certificate of Compliance The following product was found to comply with the requirement stated below when tested in accordance with the test procedures described in the accompanying test measurement report Reference report number 64567 el Manufacturer Analog Devices Inc 804 Woburn Street Wilmington MA 01887 Model Energy Meter AD7755 SS WE Requirement EN55022 1994 A1 1995 A2 1997 Class B ELT Applicable SCC Directive 89 336 EEC LAT Approved By 4 mc A Goyette 08 NVLAP Signatory Date Remarks Testing is performed using calibrated equipment traceable to the National Institute of Standards and Technology NIST This certificate is valid for products tested as described in ihe SE accompanying test report Specific modifications necessary to meet the above requirement recommended by Integrity Design amp ane Test Services Inc are described therein imum Integrity Design amp Test Services Inc is accredited by the National Voluntary Laboratory Accreditation Program NVLAP for Electromagnetic Emissions Testing Y i 1 AY i A Ti Pa tA ELI 5 E 4 R ES 1 d i nd 7 ie 34 J 3 TA F gt 4 NE Li e gt 97 5 Figure 45 Certificate 1 Emissions Testing REV A 21
153. ation due to the sin 2wt component see Figure 69 The ripple gets larger with larger loads Choosing a lower output frequency for APCF during calibration by using a large APCFDEN value and keeping APCFNUM relatively small can significantly reduce the ripple Averaging the output frequency over a longer period achieves the same results E t VIt Y VI le f enne x t Figure 69 Output Frequency Ripple 04443 069 Line Cycle Active Energy Accumulation Mode The ADE7758 is designed with a special energy accumulation mode that simplifies the calibration process By using the on chip zero crossing detection the ADE7758 updates the watt hr accumulation registers after an integer number of zero crossings see Figure 70 The line active energy accumulation mode for watt hr accumulation is activated by setting the LWATT bit Bit 0 of the LCYCMODE register The total energy accumu lated over an integer number of half line cycles is written to the watt hr accumulation registers after the LINECYC number of zero crossings is detected When using the line cycle accumulation mode the RSTREAD bit Bit 6 of the LCYCMODE register should be set to Logic 0 ACCUMULATE ACTIVE POWER FOR LINECYC NUMBER OF ZERO CROSSINGS WATT HR ACCUMULATION REGISTERS ARE UPDATED ONCE EVERY LINECYC NUMBER OF ZERO CROSSINGS WATTHR 15 0 04443 070 Figure 70 ADE7758 Line Cycle Active Energy Accumulation Mode Rev C Page 34 of 72 Phase A Phase
154. ation note should be used conjunction with the AD7755 data sheet The data sheet provides detailed information on the functionality of the AD7755 and will be referenced several times in this application note DESIGN GOALS The international Standard IEC1036 1996 09 Alternat ing Current Watt Hour Meters for Active Energy Classes 1 and 2 was used as the primary specification for this design For readers more familiar with the ANSI C12 16 specification see the section at the end of this applica tion note which compares the IEC1036 and ANSI C12 16 standards This section explains the key IEC1036 specifi cations in terms of their ANSI equivalents The design greatly exceeds this basic specification for many of the accuracy requirements e g accuracy at unity power factor and at low PF 0 5 power factor In addi tion the dynamic range performance of the meter has been extended to 500 The IEC1036 standard specifies accuracy over a range of 5 Ib to luAx see Table Typical values for Imax 40096 to 600 of Ib Table outlines the accuracy requirements for a static watt hour meter The current range dynamic range for accuracy is specified in terms of Ib basic current REV A Table l Accuracy Requirements Percentage Error Limits Class 1 Class 2 Current Value 0 05 Ib lt I lt 0 1 Ib 2 5 0 1 Ib lt lt IMAX 2 096 0 1 Ib 1 0 2 Ib 2 5 0 2 Ib lt lt IMAX 2 096 NOTES The cur
155. be right justified therefore in this case the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the ADE7758 would be the four MSBs of the 12 bit word Figure 92 illustrates this example LL gt t SCLK tz 4 PU LPL Ges Cos oo ADAC COMMAND BYTE MOST SIGNIFICANT BYTE 04443 091 LEAST SIGNIFICANT BYTE ui M s Figure 91 Serial Interface Write Timing Diagram impiis 63 ES 69 1 Cu Es nne Kon E MOST SIGNIFICANT BYTE 04443 092 LEAST SIGNIFICANT BYTE Figure 92 12 Bit Serial Write Operation DIN COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 04443 093 Figure 93 Serial Interface Read Timing Diagram Rev C Page 58 of 72 SERIAL READ OPERATION During a data read operation from the ADE7758 data is shifted out at the DOUT logic output on the rising edge of SCLK As was the case with the data write operation a data read must be preceded with a write to the communications register With the ADE7758 in communications mode and CS logic low an 8 bit write to the communications register takes place first The MSB of this byte transfer must be a 0 indicating that the next data transfer operation is a read The seven LSBs of this byte contain the address of the register that is to be read The ADE7758 starts shifting out of the register data on the next rising edge of SCLK see Figure 93 At t
156. by the ZXTOUTT 15 0 The ZXTOx detection bit of the corresponding phase in the interrupt status register is then switched on Bit 6 to Bit 8 An active low on the IRQ output also appears if the ZXTOx mask bit for the corresponding phase in the interrupt mask register is set to Logic 1 Figure 52 shows the mechanism of the zero crossing timeout detection when the Line Voltage A stays at a fixed dc level for more than 384 CLKIN x ZXTOUT 15 0 seconds 16 BIT INTERNAL REGISTER VALUE ZXTOUT 15 0 3 amp R AN VOLTAGE A CHANNEL A ZXTOA ES Ei DETECTION BIT b Rean RSTATUS 04443 052 Figure 52 Zero Crossing Timeout Detection PHASE COMPENSATION When the HPF in the current channel is disabled the phase error between the current channel IA IB or IC and the corresponding voltage channel VA VB or VC is negligible When the HPF is enabled the current channels have phase response see Figure 53 through Figure 55 The phase response is almost 0 from 45 Hz to 1 kHz The frequency band is sufficient for the requirements of typical energy measurement applications However despite being internally phase compensated the ADE7758 must work with transducers that may have inherent phase errors For example a current transformer CT with a phase error of 0 1 to 0 3 is not uncommon These phase errors can vary from part to part
157. c ECO U2A103MN Digi Key No P4601 ND C17 470 nF 250 V AC Metallized Polyester Film Through Hole Panasonic 6474 Digi Key No EF6474 NP C18 35 V 470 uF Electrolytic Through Hole Panasonic ECA 1VHG471 Digi Key P5554 ND U1 AD7755AN Supplied by ADI 24 Pin DIP Use Pin Receptacles P1 P24 U2 LM78L05 National Semiconductor LM78LO5ACM 50 8 Digi Key LM78LO5ACM ND U3 PS2501 1 Opto NEC Digi key No PS2501 1NEC ND UA AD780BRS Supplied by ADI 8 Pin SOIC D1 Low Current LED HP HLMP D150 Newark 06F6429 Farnell 323 123 D2 Rectifying Diode 1 W 400 V DO 41 1N4004 Digi Key 1N4004DICT ND D3 Zener Diode 15 V 1 W DO 41 1N4744A Digi Key 1N4744ADICT ND Z1 Z2 Ferrite Bead Cores Axial Leaded 15 mm x 3 8 mm 0 6 mm Lead Diameter Panasonic EXCELSA391 Digi Key P9818BK ND Z3 Z4 Ferrite SMD Bead SMD 1806 Steward 1806 E 151 R Digi Key 240 1030 1 ND Y1 3 579545 MHz XTAL Quartz Crystal HC 49 US ECS No ECS 35 17 4 Digi Key No X079 ND MOV1 Metal Oxide Varistors AC 275 V 140 Joules FARNELL No 580 284 Siemens S20K275 J1 J10 0 1 0 596 1 4 W 200 V SMD 1210 Resistor Surface Mount Panasonic ERJ 14RSJOR1 Digi Key PO 1SCT ND J11 J15 5 1 8 W 200 V SMD 1206 Resistor Surface Mount Panasonic ERJ 8GEYJ000 Digi Key No PO OECT ND P1 P24 Single Low Profile Sockets for U1 0 022 to 0 025 Pin Diameter ADI Stock 12 18 33 ADVANCE KS5100 85TG K1 K8 Pin Receptacles 0 037 to 0 043 Pin Diameter H
158. can be set to 6 103 Hz by writing OxFF to the APCFDEN register If 0 were written to any of the frequency division registers the divider would use 1 in the frequency division In addition the ratio APCFNUM APCFDEN should be set not greater than 1 to ensure proper operation In other words the APCF output frequency cannot be higher than the frequency on the DFC output The output frequency has a slight ripple at a frequency equal to 2x the line frequency This is due to imperfect filtering of the instantaneous power signal to generate the active power signal see the Active Power Calculation section Equation 14 gives an expression for the instantaneous power signal This is filtered by LPF2 which has a magnitude response given by Equation 23 an gt TE The active power signal output of the LPF2 can be rewritten as 23 VRMS x IRMS nA where fi is the line frequency for example 60 Hz p t VRMS x IRMS xcos Anft 24 ACTIVE POWER ZXSEL01 b ZERO CROSSING DETECTION PHASE A ZXSEL 11 ZERO CROSSING n DETECTION PHASE B ZXSEL21 ES 1ZXSEL 0 2 ARE BITS 3 TO 5 IN THE LCYCMODE REGISTER CALIBRATION __ CONTROL LINECYC 15 0 ZERO CROSSING DETECTION PHASE C OQ From Equation 24 E t equals VRMS x IRMS VRMS x IRMS x t x cos 4mf t 25 Anf 1 Qf y 92 From Equation 25 it can be seen that there is a small ripple the energy calcul
159. cas del cliente e Otro aspecto el cual no debe pasar por alto es la importancia del an lisis de costos ya que el xito en el desarrollo de proyectos incluye una adecuada planificaci n de todas las variables externas imprevistos disponibilidad de elementos y todos los incrementos que esto puede traer a un proyecto real pudiendo convertirlo en un fracaso o xito rotundo Lo anterior se resalta teniendo en cuenta que en el desarrollo del presente proyecto se presentaron situaciones que no fueron planificadas ni proyectadas a nivel de costos y que aumentaron el valor final del producto desarrollado pero precisamente ayuda a reflexionar sobre la importancia de la planificaci n y el an lisis previo de manera global e Finalmente por las diversas caracter sticas integradas en el sistema de control para medici n se concluye que se ha desarrollado un prototipo muy competitivo que cubre con todos los objetivos planteados Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU FUENTES 1 MINISTERIO DE ENERG A Y MINAS PERU 2005 Compendio de normas del sub sector electricidad http www minem gob pe electricidad index asp 2 The ABB Group 2001 October ODIN Meter An electricity energy meter from ABB Technical documentation http www abb nl GLOBAL NLABB NLABBO0O32 NSF viewunid 7209F451A8659
160. channel The source is selected by data bits in the mode register OxOB Phase B Current Channel RMS Register OxOC Phase C Current Channel RMS Register Phase A Voltage Channel RMS Register Rev C Page 60 of 72 ADE7 1758 Address Default A6 A0 d pud pe Description OxOE Phase B Voltage Channel RMS Register OxOF Phase C Voltage Channel RMS Register 0x10 Frequency of the Line Input Estimated by the Zero Crossing Processing It can also display the period of the line input Bit 7 of the LCYCMODE register determines if the reading is frequency or period Default is frequency Data Bit 0 and Bit 1 of the MMODE register determine the voltage channel used for the frequency or period calculation 0x11 Temperature Register This register contains the result of the latest temperature conversion Refer to the Temperature Measurement section for details on how to interpret the content of this register 0x12 Waveform Register This register contains the digitized waveform of one of the six analog inputs or the digitized power waveform The source is selected by Data Bit O to Bit 4 in the WAVMODE register 0x13 OPMODE Operational Mode Register This register defines the general configuration of the ADE7758 see Table 18 0x14 MMODE Measurement Mode Register This register defines the channel used for period and peak detection measurements see Table 19 0x15 WAVMODE Waveform Mode Register This register defines the chann
161. ci n 1 4 gt La Ecuaci n 1 4 posee dos partes una constante en el tiempo con el valor cuadr tico del RMS DC que es nuestro valor deseado y la otra parte variable en el tiempo AC que contiene una sefial cosenoidal no deseada Para eliminar el valor no deseado se aplica un Filtro Pasa Bajos FPB con una frecuencia de corte menor la frecuencia de la AC Luego del filtro pasa bajos f t is gt Finalmente se saca la ra z cuadrada al resultado de ese modo se obtiene el valor RMS de la Luego dela raiz cuadrada f Fas Ecuaci n 1 5 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Medidores de potencia activa anal gica Este tipo de medidores se basan en rotores de discos los cuales operan bajo el principio del electromagnetismo BOBINA DE VOLTAJE NUCLEO DE HIERRO LINEA DE ALIMENTACION LINEA DE ALIMENTACION wWON 353X 3333N 30 30 WANIMI DISCO ROTATORIO LOS MEDIDORES DE POTENCIA ACTIVA ANALOGICA CONSTAN BASICAMENTE DE UN DISCO ROTATORIO Y UN NUCLEO DE HIERRO SOLIDO SOBRE EL CUAL SE UBICAN LOS BOBINADOS DE CORRIENTE Y VOLTAJE Figura 2 5 Medidor de potencia activa anal gica Las caracter sticas esenciales se muestran en la Figura 2 5 el medidor posee una bobina de voltaje conectada en paralelo
162. ci n de componentes tomando consideraciones t cnicas para el diseno electr nico Adicionalmente se presenta el diseno industrial del chasis del prototipo el cual se ha desarrollado conforme a los requerimientos comerciales futuros del equipo final Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis L PONTIFICIA TESIS UNIVERSIDAD DEL PERU En el cuarto cap tulo se exponen los resultados obtenidos con el desarrollo del prototipo los logros alcanzados y una descripci n de las recomendaciones para su posterior desarrollo Finalmente el ultimo cap tulo menciona las conclusiones obtenidas a partir del proceso de desarrollo del proyecto de tesis y de los objetivos inicialmente planteados Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU CAP TULO 1 LA ENERG A EN EL SECTOR DE CONSUMO 1 1 IMPORTANCIA DEL CONTROL DE LA ENERG A EL CTRICA El control de la energ a el ctrica es una pieza clave en como proyectamos nuestro futuro tanto a nivel ambiental como a nivel industrial para resaltar su importancia se analizar n dos enfoques el primero mostrar el inminente impacto al ecosistema ante la creciente poblaci n mientras que en el segundo se analiza un hecho del mbito industrial en donde redu
163. cir costos significa maximizar beneficios 1 1 1 EL CONTROL DE LA ENERG A EL CTRICA A NIVEL AMBIENTAL Hoy en d a muchas personas asumen que se hace un buen trabajo conservando la electricidad y en efecto diversos artefactos utilizan mucho menos energ a que en d cadas anteriores Pero a pesar de nuestros esfuerzos para conservar la energ a la cantidad de electricidad consumida s lo en el Per ha ido en aumento con el pasar de los anos durante este tiempo la poblaci n tambi n se ha incrementado El Ministerio de energ a y minas del Per ha hecho unos interesantes estudios respecto a la relaci n Poblaci n Producci n de energ a el ctrica Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU FUENTE Ministerio de energ a y Minas 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 El Producci n de energ a el ctrica GW h Poblaci n miles de habitantes Figura 1 1 Comparaci n de la producci n de energ a el ctrica y la poblaci n en el Per FUENTE Ministerio de energ a y Minas INDICADORES 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 NUMERO DE CLIENTES 2492 2776 2964 3057 3217 3352 3463 3614 3727 3861 3977 4065 PRODUCCI N DE ENERGIA ELECTRICA 16880 17280 17953 18583 19050 19923 19923 21982 22923 22923 25510 26713
164. cnicos para la elaboraci n del prototipo los cuales se deben implementar para un desarrollo ptimo Cabe resaltar que los equipos aqu expuestos son actualmente comerciales y los datos son en general aproximados pero muy cercanos a la realidad Reliable Power 9610 Power ION 7550 Meters Multipoint OD4110 Prototipo 1949 Quality Meter FABRICANTE Schneider Electric Fluke Siemens TIPO DE SENAL Trif sico Monof sico Trif sico Trif sico Trif sico Trif sico MEDICI N DE VOLTAJE MEDICI N DE CORRIENTE Si 51 Si Si SI 51 Si Si Activa Activa Activa Reactiva Reactiva Activa Activa Reactiva Aparente Aparente Aparente CALCULO DE POTENCIAS Sobre voltajes Sobre corrientes Desfase de red ANALIZADOR Sobre voltajes Es Arm nicos DE ENERG A Sobre corrientes Armonicos Desfase de red TIPO DE Ethernet Ethernet Ethernet Ethernet COMUNICACI N RS 485 RS 485 RS 485 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis 3 PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU Costo ION 7550 Reliable Power 9610 Power Prototipo M eters Quality M eter Multipoint 1949 Figura 4 4 Comparaci n en los costos de los equipos Como se puede observar en la Figura 4 4 el precio del prototipo es inferior al resto de equipos comerciales con similares caracter sticas considerando que el proyecto de tesis es parte de un sistema mayor y
165. ctive power after the two are individually squared Equation 39 shows the calculation used in the vectorial approach S P 02 39 where is the apparent power P is the active power Q is the reactive power ADE7 1758 For a pure sinusoidal system the two approaches should yield the same result The apparent energy calculation in the ADE7758 uses the arithmetical approach However the line cycle energy accumulation mode in the ADE7758 enables energy accumula tion between active and reactive energies over a synchronous period thus the vectorial method can be easily implemented in the external MCU see the Line Cycle Active Energy Accumulation Mode section Note that apparent power is always positive regardless of the direction of the active or reactive energy flows The rms value of the current and voltage in each phase is multiplied to produce the apparent power of the corresponding phase The output from the multiplier is then low pass filtered to obtain the average apparent power The frequency response of the LPF in the apparent power signal path is identical to that of the LPF2 used in the average active power calculation see Figure 65 Apparent Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by 50 by writing to the phases VAGAIN register AVAG BVAG or CVAG The VAGAIN registers are twos complement signed registers and have a resolution of 0
166. ctive power frequency output see the Active Power Frequency Output section Rev C Page 38 of 72 Line Cycle Reactive Energy Accumulation Mode The line cycle reactive energy accumulation mode is activated by setting the LVAR bit Bit 1 in the LCYCMODE register The total reactive energy accumulated over an integer number of Zero crossings is written to the VAR hr accumulation registers after the LINECYC number of zero crossings is detected The operation of this mode is similar to watt hr accumulation see the Line Cycle Active Energy Accumulation Mode section When using the line cycle accumulation mode the RSTREAD bit Bit 6 of the LCYCMODE register should be set to Logic 0 APPARENT POWER CALCULATION Apparent power is defined as the amplitude of the vector sum of the active and reactive powers Figure 74 shows what is typically referred to as the power triangle APPARENT POWER REACTIVE POWER 04443 074 ACTIVE POWER Figure 74 Power Triangle There are two ways to calculate apparent power the arithmetical approach or the vectorial method The arithmetical approach uses the product of the voltage rms value and current rms value to calculate apparent power Equation 38 describes the arithmetical approach mathematically 5 VRMS x IRMS 38 where is the apparent power and VRMS and IRMS are the rms voltage and current respectively The vectorial method uses the square root of the sum of the active and rea
167. cual muestra que nuestros esfuerzos de conservaci n no han sido del todo satisfactorios pues no han logrado reducir la cantidad de electricidad que consumimos por persona S lo en el periodo comprendido entre los anos 1995 a 2006 ha ocurrido un aumento del 33 6 de la energ a el ctrica consumida por hora por cada persona peruana promedio FUENTE Ministerio de energ a y Minas PRODUCCI N DE ENERG A EL CTRICA PERC PITA 1995 2006 kW h habitante 500 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 Figura 1 2 Energ a el ctrica producida por persona en el Per Este gran incremento en el consumo energ tico se puede comprender por dos factores b sicos Primero los individuos consumen m s electricidad cada y segundo la poblaci n crece cada afio Seg n el INEI Instituto Nacional de Estad stica e Inform tica del Per 2006 s lo considerando los datos de Lima metropolitana y el Callao hay cuatro nacimientos cada 7 minutos y una muerte cada 8 minutos Considerando las emigraciones e inmigraciones tenemos un efecto neto que anadimos una persona a nuestra poblaci n total cada 2 minutos y medio Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CAT LICA DEL PERU En los siguientes 50 a os el Per tendr unos 10 5 millones de personas adicionales oi tomamos los dat
168. d ANTIALIAS FILTERS As mentioned in the previous section one possible source of external phase errors are the antialias filters on Channel 1 and Channel 2 The antialias filters are low pass filters that are placed before the analog inputs of any ADC They are required to prevent a possible distortion due to sampling called aliasing Figure 5 illustrates the effects of aliasing FREQUENCIES 0 2 450 900 FREQUENCY kHz Figure 5 Aliasing Effects REV A Figure 5 shows how aliasing effects could introduce inac curacies in an AD7755 based meter design The AD7755 uses two X A ADCs to digitize the voltage and current signals These ADCs have a very high sampling rate i e 900 kHz Figure 5 shows how frequency components arrows shown in black above half the sampling fre quency also know as the Nyquist frequency i e 450 kHz is imaged or folded back down below 450 kHz arrows shown dashed This will happen with all ADCs no mat ter what the architecture In the example shown it can be seen that only frequencies near the sampling frequency i e 900 kHz will move into the band of interest for meter ing i e 0 kHz 2 kHz This fact will allow us to use a very simple LPF Low Pass Filter to attenuate these high fre quencies near 900 kHz and so prevent distortion in the band of interest The simplest form of LPF is the simple RC filter This is a single pole filter with a roll off or attenuation of 20 dBs dec
169. d rate Habilitador 2Mhz 22pF MICROCONTROLADOR MCP2120 Figura Esquema del transductor IrDA La l gica de funcionamiento del MCP2120 es la siguiente Para codificaci n de UART a IrDA 16 Cycles 16 Cycles 16 Cycles 16 Cycles U 16XCLK Pa 16XCLK U TXD 123456 7 8 10 12 14 16 m Figura Diagrama de tiempos de la conversi n USART IrDA Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis ENER Y lt PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU El clock ingresado en los pines de BAUD se divide en 16 clocks de los cuales por cada bit 0 del UART el codificador cuenta 7 ciclos de este 16clock luego pone en alta la salida durante 3 ciclos de 16clock y finalmente lo env a nuevamente a cero hasta terminar los 16 clocks por cada bit en 1 mantiene su salida en un valor bajo Para decodificaci n de IrDA a UART 16XCLK 10 12 14 16 U RXD Figura Diagrama de tiempos de la conversi n IrDA USART El clock ingresado en los pines de BAUD se divide en 16 clocks de los cuales por cada bit 1 recibido por el puerto infrarrojo env a la salida del UART a cero con un pequefio de aproximadamente medio ciclo de 16clock por cada bit O recibido env a que la
170. dad de 18 registros de datos 6 de solo lectura y 12 de lectura y escritura accesible a trav s de la interfaz serial desde un registro maestro de comunicaciones Ancho de banda nominal de 14kHz Variaci n t pica en la frecuencia de salida del orden de 0 2 Entradas anal gicas de alta impedancia 390K O m nima capaces de aceptar senales hasta de 1 Opera con frecuencias de reloj desde 1MHz hasta 10MHz Entradas y salidas l gicas compatibles con TTL y CMOS Alimentaci n a partir de una fuente sencilla de 5VDC regulada Bajo consumo de potencia 15mW t pico Rango de temperaturas de desde 40 C hasta 85 C En el Cap tulo 2 Secci n Instrumentos de medici n por metodolog a Ecuaci n 1 5 P g 21 Ecuaci n 2 4 P g 25 Ecuaci n 3 2 P g 26 Ecuaci n 5 1 P g 28 se expusieron las teor as y f rmulas de medici n digital tecnolog a que usa el ADE7758 para sus c lculos por ello no se ahondar nuevamente en explicaciones al respecto y se mostrar n los diagramas de bloques para el pre procesamiento de datos Medici n RMS AJUSTE DE GANANCIA EL VOLTAJE ES AJUSTADO EN GANANCIA SE LE DIGITALIZA SE LE MULTIPLICA POR 51 MISMO LUEGO PASA POR EL METODO FPB Y FINALMENTE SE LE SACA LA RAIZ CUADRADA PARA OBTENER EL Vrms Figura 3 3 Diagramas de bloques de la medici n de voltaje RMS Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis
171. dated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice Tl is not responsible or liable for such altered documentation Resale of TI products or services with
172. de contener proteger y aislar las tarjetas de componentes del sistema con el exterior adem s de brindar comodidad para el manejo del sistema El material con el que se trabaj fue Hierro Fe de calidad 10 10 de grosor 1 20 pulgadas conocido como lata de aleaci n Se eligi dicho material por sus capacidades magn ticas y conductivas lo cual asegura un buen aislamiento a campos magn ticos externos para la parte interna de la caja del chasis conformando de ese modo la denominada Jaula de Faraday La protecci n Far dica evitar que el ruido el ctrico afecte en gran medida las se ales anal gicas sensadas por el sistema Las caracter sticas f sicas se determinaron respetando dimensiones de un rack est ndar con una altura de 2U 465mm x 625mm x 90mm aprox y se realiz con un disefio simple como se observa en la Figura 3 39 Figura 3 39 Disefio del chasis del equipo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis Para que los conectores de la tarjeta del sistema puedan comunicarse con el exterior se hicieron agujeros a medida en la parte Posterior del chasis del mismo modo en la parte Frontal se hicieron agujeros para la salida del teclado y del visualizador Adem s posee agujeros para sujeci n interna de las tarjetas encontrando una buena disposici n entre espacio y cableado POSTERIOR Figura 3 40 Vista frontal y posterior en
173. direction see the Phase Compensation section Because a current transformer is a source of phase error a fixed nominal value can be decided on to load into the xPHCAL 0x3F to 0x41 registers at power up During calibration this value can be adjusted for CT to CT error Figure 82 shows the steps involved in calibrating the phase using the line accumulation mode ADE7 758 SET LCYCMODE LINECYC AND MASK REGISTERS SET UP SYSTEM FOR ItEST VNOM PF 0 5 INDUCTIVE STEP 3 RESET STATUS REGISTER READ ALL xWATTHR REGISTERS AFTER LENERGY INTERRUPT CALCULATE PHASE ERROR IN DEGREES FOR ALL PHASES STEP 6 CALCULATE AND WRITE TO ALL xPHCAL REGISTERS 04443 082 Figure 82 Phase Calibration Using Line Accumulation Step 1 If the values were changed after gain calibration Step 1 Step 3 and Step 4 from the gain calibration should be repeated to configure the LCYCMODE and LINECYC registers Step 2 Set the test system for Iresr Vnom and 0 5 power factor inductive Step 3 Reset the interrupt status register by reading RSTATUS Ox1A Step 4 The xWATTHR registers should be read after the LENERGY interrupt Measure the percent error in the energy register readings AWATTHR BWATTHR and CWATTHR compared to the energy register readings at unity power factor after gain calibration using Equation 69 The readings at unity power factor should have been repeated after the gain calibration and stored for use
174. e SAG enable bit is set to Logic 1 for this phase Bit 1 to Bit 3 in the interrupt mask register the logic output goes active low see the Interrupts section The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers VAP VBP OR VCP FULL SCALE wl a 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 0 arden End 0 0x06 6 HALF CYCLES SAG EVENT RESET LOW WHEN VOLTAGE CHANNEL SAG INTERRUPT FLAG EXCEEDS SAGLVL 7 0 BIT 3 TO BIT 5 OF STATUS REGISTER READ RSTATUS REGISTER 04443 057 Figure 57 ADE7758 SAG Detection Figure 57 shows a line voltage fall below a threshold which is set in the SAG level register SAGLVL 7 0 for nine half cycles Because the SAG cycle register indicates a six half cycle threshold SAGCYC 7 0 0x06 the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register Bit 1 to Bit 3 in the interrupt status register If the SAG enable bit is set to Logic 1 for this phase Bit 1 to Bit 3 in the interrupt mask register the logic output goes active low see the Interrupts section The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers Rev C Page 25 of 72 7758 SAG LEVEL SET The contents of the single byte SAG level register SAGLVL 0 7
175. e can be decided on to load into the xPHCAL registers at power up During calibration this value can be adjusted for CT to CT error Figure 78 shows the steps involved in calibrating the phase using the pulse output ALL PHASES PHASE ERROR CALIBRATED YES SET UP PULSE OUTPUT FOR PHASE A B OR C AND ENABLE CF OUTPUTS SET UP SYSTEM FOR Vnom PF 0 5 INDUCTIVE MEASURE ERROR IN APCF SELECT PHASE STEP 41 FOR LINE PERIOD MEASUREMENT CALCULATE PHASE ERROR DEGREES CONFIGURE FREQ 11 0 FOR A LINE PERIOD MEASUREMENT PERIOD OF SYSTEM KNOWN NO YES STEP 5 MEASURE CALCULATE AND gt PERIOD USING 5 B FREQ 11 0 REGISTER xPHCAL i Figure 78 Phase Calibration Using Pulse Output Step 1 Step 1 and Step 3 from the gain calibration should be repeated to configure the ADE7758 pulse output Ensure the xPHCAL registers are zero Step 2 Set the test system for Iresr Vnom and 0 5 power factor inductive Step 3 Measure the percent error in the pulse output APCE from the reference meter using Equation 49 Step 4 Calculate the Phase Error in degrees by 53 Phase Error Ars 100 x 3 Step 5 Calculate xPHCAL xPHCAL 1 1 _1_ 54 Phase Error x x PHCAL_LSB_ Weight LinePeriod s 360 where PHCAL LSB Weight 15 1 2 us if the Error is negativ
176. e control digital basado en la tecnolog a del microcontrolador ATmega128 de la compafi a ATMEL y del circuito integrado ADE7758 de Analog Devices que adem s posea la l gica adecuada para la medici n trif sica de par metros el ctricos y permita la comunicaci n a redes de datos Con dicha aplicaci n ser la etapa principal y b sica de un sistema mayor encargado de la medici n digital de energ a el ctrica trif sica en media y baja tensi n con un bajo porcentaje de error que permita comunicaci n remota en tiempo real de los par metros el ctricos sensados Voltaje RMS Corriente RMS Potencia Activa Potencia Reactiva Potencia Aparente entre otros hacia un computador de la red La tesis comprender el desarrollo del sistema de control con la l gica adecuada para el procesamiento futuro de medici n y de comunicaci n contando con etapas de ingreso de datos pre procesamiento control visualizaci n comunicaci n y expansiones para mejoras futuras Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Respecto a la utilidad del proyecto sta se extiende al campo comercial puesto que la integraci n del proyecto de tesis como Sistema de control digital a un Sistema mayor de medici n de energ a el ctrica con comunicaci n en tiempo real dar versatilidad a los procesos industriales convirt
177. e in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register Indicates that an interrupt was caused by a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register Indicates that an interrupt was caused by a zero crossing from Phase A followed not by the zero crossing of Phase C but by that of Phase B Rev C Page 69 of 72 7758 OUTLINE DIMENSIONS 15 60 0 6142 15 20 0 5984 7 60 0 2992 7 40 0 2913 10 65 0 4193 10 00 0 3937 0 75 0 0295 2 65 0 1043 0 25 0 0098 0 30 0 0118 2 35 0 0925 e 0 10 0 0039 WINE yy COPLANARITY 4 le gt ke 0 10 1 27 0 0500 0 51 0 0201 N 0 33 0 0130 1 27 0 0500 BSC 0 31 0 0122 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013 AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 94 24 Lead Standard Small Outline Package SOIC W Wide Body RW 24 Dimensions shown in millimeters and inches 060706 A ORDERING GUIDE Model Package Option ADE7758ARW 40 C to 85 24 Lead Wide Body SOIC W RW 24 ADE7758ARWRL 40 C to 85 24 Lead Wide Body SOIC W RW 24 ADE7758ARWZ 40 C to 85 24 Lead Wide Body SOIC W RW 24 ADE7758ARWZRL
178. e of LPF1 results in a time delay of approximately 1 1 ms at 60 Hz between the zero crossing on the voltage inputs and the resulting zero crossing signal Note that the zero crossing signal is used for the line cycle accumulation mode zero crossing interrupt and line period frequency measurement When one phase crosses from negative to positive the corresponding flag in the interrupt status register Bit 9 to Bit 11 is set to Logic 1 An active low in the IRQ output also appears if the corresponding ZX bit in the interrupt mask register is set to Logic 1 Note that only zero crossing from negative to positive generates an interrupt The flag in the interrupt status register is reset to 0 when the interrupt status register with reset RSTATUS is read Each phase has its own interrupt flag and mask bit in the interrupt register ADE7 1758 Zero Crossing Timeout Each zero crossing detection has an associated internal timeout register not accessible to the user This unsigned 16 bit register is decreased by 1 every 384 CLKIN seconds The registers are reset to a common user programmed value that is the zero crossing timeout register ZX TOUT 15 0 Address 0x1B every time a zero crossing is detected on its associated input The default value of ZXTOUT is OxFFFF If the internal register decrements to 0 before a zero crossing at the corresponding input is detected it indicates an absence of a zero crossing in the time determined
179. e or 2 4 us if the Error is positive see the Phase Compensation section If it is not known the line period is available in the ADE7758 s frequency register FREQ 0x10 To configure line period measurement select the phase for period measurement in the MMODE 1 0 and set LEYCMODE 7 Equation 55 shows how to determine the value that needs to be written to xPHCAL using the period register measurement xPHCAL 9 6 us FREQ I1 0 55 Phase Error x PHCAL LSB Weight 360 Example Phase Calibration of Phase A Using Pulse Output For this example Iresr 10 A Vnom 220 V 500 V Iruiiscare 130 A 3200 impulses kWh Power Factor 0 5 inductive and Frequency 50 Hz With Phase A contributing to at Iresr Vnom and 0 5 inductive power factor the example ADE7758 meter shows 0 9668 Hz on the pulse output This is equivalent to 1 12296 error from the reference meter value using Equation 49 The Phase Error in degrees using Equation 53 is 0 3713 1 122 Phase Error Arcsin 0 J3 0 3713 If at 50 Hz the FREQ register 20834 the value that should be written to APHCAL is 17d or 0x11 using Equation 55 Note that a PHCAL LSB Weight of 1 2 us is used because the Error is negative 9 6 us 2083 1 205 360 APHCAL 0 3713 17 19 17 0x11 Power Offset Calibration Using Pulse Output Power offset calibrat
180. e requiere un sensor adecuado para efectos de medicion que es el Medidor de par metros el ctricos Siendo asi se presenta una breve resena hist rica de su evoluci n en el tiempo pasando desde la primera patente dada en 1872 por Samuel Gardiner hasta los ltimos desarrollos en los llamados sistemas EEM que introducen conceptos de telemetr a En este mismo cap tulo luego del an lisis de la problem tica y las tecnolog as de medidores que surgieron en el transcurso de los afios se establecen los objetivos que marcar n la investigaci n y desarrollo del prototipo digital La descripci n m s detallada de las diversas tecnolog as de medici n se presenta en el segundo capitulo dividi ndolos en tres grupos por mecanismos indicadores por metodolog a y por aplicaci n dando nfasis a los algoritmos digitales para los c lculos medici n Mas adelante se presenta la tarjeta TEMPUS VI que por sus caracter sticas se utiliza como m dulo de control y adicionalmente se exponen tecnolog as de comunicaci n serial entre perif ricos Despu s de estudiar las diversas alternativas para resolver los objetivos planteados se procede a hacer un an lisis te rico a fin de elegir las t cnicas y metodolog as m s adecuadas para este proyecto El tercer capitulo se concentra estrictamente en el diseno del sistema se mencionan las diversas etapas que la conforman para las cuales se hace un an lisis de requerimientos investigaci n y selec
181. e tuvo un periodo de estudio para conocer sus funciones y a partir de ello acondicionar el firmware disenado e l gica de control disenada incorpora las funcionalidades de lectura por SPI del ADE7758 y el uso de datagramas TCP IP para la comunicaci n a red Adem s de hacer uso de las opciones de configuraci n para datagramas reloj en tiempo real manejo de teclado y LCD entre otras funciones ya provistas por el TEMPUS VI e El firmware se desarroll en c digo assembler con el programa AVRstudio 4 provisto por la compania ATMEL El AVRstudio es de descarga y licencia libre utilizado para el diseno y programaci n de los microcontroladores AVR Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU EJ project Buld View Toole Debug Window Hep bira mie amp 9 10 E E cp ELE UB omm RIE gt NE EI lt lt lt lt lt lt lt DRIVER DE LECTURA DE DATOJ POR SPI La 2 Source Files SEED A A E IE E EE IED BEA BE A A E IDE BD E EII EA AE 2 tesis asm dseg 3 Included Files SPIconando byte 2 Labels SPIndat byte Lm SPIbufferWUR byte 43 Output SPIbuffmrRD byte Sy Object File HemoryDriver
182. e voltage and current rms values The voltage rms values are stored in unsigned 24 bit registers AVRMS BVRMS and CVRMS One LSB of a voltage waveform sample is approximately equivalent to 256 LSBs of the voltage rms register The update rate of the voltage rms measurement is CLKIN 12 With the specified full scale ac analog input signal of 0 5 V the LPF1 produces an output code that is approximately 63 of its full scale value that is 9 372d at 60 Hz see the Voltage Channel ADC section The equivalent rms value of a full scale ac signal is approximately 1 639 101 0x1902BD in the VRMS register The accuracy of the VRMS measurement is typically 0 596 error from the full scale input down to 1 20 of the full scale input Additionally this measurement has a bandwidth of 260 Hz It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability The IRQ can be used to indicate when a zero crossing has occurred see the Interrupts section ADE7 1758 VRMSOS 11 0 28 27 26 AVRMSGAIN 11 0 VAN AVRMS 23 0 50Hz VOLTAGE SIGNAL V t 50 2 LPF OUTPUT 0 193504 WORD RANGE 2797 GAIN D 0x0 0x0 60Hz 0xD869 0x1902BD 60Hz LPF OUTPUT 0x0 WORD RANGE 0x2748 0x0 0xD8B8 04443 063 Figure 63 Voltage RMS Signal Processing Table 8 shows the settling time for the VRMS measurement which is the time it takes for the rms register to reflect the value at the
183. e with Internal Reference and Integrator Off 0 2 e 0 5 25 1 25 PERCENT ERROR o 0 5 25 C 0 5 85 C 04443 007 0 01 0 1 1 10 100 PERCENT FULL SCALE CURRENT Figure 7 Active Energy Error as a Percentage of Reading Gain 1 over Power Factor with Internal Reference and Integrator Off 0 2 e PERCENT ERROR o 04443 008 0 01 0 1 1 10 100 PERCENT FULL SCALE CURRENT Figure 8 Active Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off Rev C Page 12 of 72 PERCENT ERROR 04443 009 0 01 0 1 1 10 100 PERCENT FULL SCALE CURRENT Figure 9 Active Energy Error as a Percentage of Reading Gain 1 over Temperature with External Reference and Integrator Off PERCENT ERROR WITH RESPECT TO 55Hz 04443 010 LINE FREQUENCY Hz Figure 10 Active Energy Error as a Percentage of Reading Gain 1 over Frequency with Internal Reference and Integrator Off PERCENT ERROR WITH RESPECT TO 5V 3A b b Ro o 04443 011 PERCENT FULL SCALE CURRENT 95 Figure 11 Active Energy Error as a Percentage of Reading Gain 1 over Power Supply with Internal Reference and Integrator Off 7758 E S 01 X ALL PHASES X 0 05 2 te 72 2 0 E E i i W 0 05 te te a 0 10 a 0 15 0 20 0 25 5 5 0 01 0 1 1 10 100 100
184. ecci n Serial Peripheral Interface P g 162 y Secci n Serial downloading P g 303 e Se colocaron dos conectores para voltaje y corriente que dan ingreso a las sefiales acondicionadas para el pre procesamiento los cuales CON CORRIENTE conectar n posteriormente en la etapa de acondicionamiento de datos v ase Figura 2 15 Se proyecta que en esta ultima etapa se disenara un sistema con desacoplo magn tico de tierras y debido a que se trabajar con senales el ctricas que pueden ser perjudiciales al usuario esta precauci n minimizar el riesgo de descargas el ctricas adem s asegura la estabilidad del equipo ante fluctuaciones de la red LA PROYECCION A FUTURO TIENE PREVISTO EL USO DE TRANSFORMADORES PARA DESACOPLO el ctrica Figura 3 12 Desacoplo magn tico con transformadores Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Para el dise o del software se tomar en consideraci n los modos de escritura y lectura de registros del pre procesador mediante l gica SPI MODO LECTURA OSA CON MN BYTEDECOMANDO Y M BYTE MAS SIGNIFICATIVO BYTE MENOS SIGNIFICATIVO DATOS MODO ESCRITURA _ _ R MN BYTE DE COMANDO Y BYTE MENOS SIGNIEICATIVOA DATOS LA LOGICA DE COMUNICACION
185. econ micas pero con cierta complejidad en programaci n Por la comodidad y econom a se optar por la comunicaci n por bus serial la cual puede ser Est ndares RS SPI lC 1 Wire 2 3 1 RECOMMENDED STANDARD 232 C RS 232 Inicialmente denominado ElA232C y renombrando como RS 232 C a inicios de 1990 Es la norma de comunicaci n serie as ncrona m s popular y aceptada por la industria Su conexi n de transmisi n es punto a punto es decir un emisor y un receptor utiliza la referencia a tierra para poder distinguir los valores de voltaje entre su comunicaci n TX TERMINAL 1 RX TERMINAL 2 GND LA COMUNICACION RS 232 SIMPLIFICADA SOLO HACE USO DE TRES PINES SE APLICA EN COMUNICACIONES DE BAJA VELOCIDAD Figura 2 13 Comunicaci n RS 232 de 3 hilos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 2 3 2 SPI SERIAL PERIPHERAL INTERFACE BUS El bus SPI algunas veces llamado spy es un est ndar de comunicaci n de datos serial sincrono disenado por Motorola que opera en modo full duplex Los dispositivos conectados se comunican en modo Maestro Esclavo siendo el dispositivo Maestro aquel que mantiene la sincronizaci n Es una comunicaci n multipunto es decir puede existir un Maestro y m ltiples Esclavos elegidos por medio de un selector SS SCLK AA A MOSI SPI PEA B Ed Ms
186. ecto que si bien no cumplen un rol determinante dentro del funcionamiento del equipo su elecci n es importante porque brinda funcionalidad al diseno Los conectores que se presentan en el Anexo A Conectores Secci n Conectores P g 1 se eligieron siguiendo los requerimientos de voltaje y corriente a los que ser sometido el equipo su disponibilidad en el mercado peruano comodidad de uso para el usuario adem s de brindar orden al diseno Aplicaci n Para la implementaci n de conectores se dividi la tarjeta de componentes en dos caras Conectores externos como se observa en la Figura 3 28 tiene los conectores que brindan comunicaci n con el usuario Conectores internos como se observa en la Figura 3 29 que tiene comunicaci n con los otros m dulos del sistema VISTA DE LOS CONECTORES EXTERNOS LOS CUALES TIENEN INTERACCION CON EL USUARIO SE ENCUENTRAN LOS CONECTORES DE ALIMENTACION COMUNICACION EXPANSION Y MEDICION DE PARAMETROS ELECTRICOS Figura 3 28 Vista y descripci n de los conectores externos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis gt PONTIFICIA TESIS PUCP CATOLICA D DEL PERU VISTA DE LOS CONECTORES INTERNOS LOS CUALES TIENEN INTERACCION CON LOS OTROS MODULOS DEL SISTEMA SE ENCUENTRAN LOS CONECTORES DE CONTROL EXPANSION Y COMUNICACION Figura 3 29 Vista y descripci n de los conectores internos
187. ed AN 559 e 7 73 R1 V1P O T V 1 1 QU 2 gt LOWZ HIGH 2 E K2 VIN ME WV 2 V ts uo 2 Figure 20 Antialias Filters Showing Parasitics Parasitics can be kept at a minimum by using physically small components with short lead lengths i e surface mount Because the exact source impedance conditions are not known this will depend on the source imped ance of the electricity supply some general precautions should be taken to minimize the effects of potential reso nances Resonances that result from the interaction of the source impedance and filter networks could cause insertion gain effects and so increase the exposure of the system to RF radiation at certain resonant frequen cies Lossy i e having large resistive elements components like capacitors with lossy dielectric e g Type X7R and ferrite are ideal components for reducing the Q of the input network The RF radiation is dissi pated as heat rather than being reflected or diverted to another part of the system The ferrite beads Z3 and Z4 perform very well in this respect Figure 21 shows how the impedance of the ferrite beads varies with frequency 250 LI 1806 B 1518 200 Z R X VS FREQUENCY 1 10 100 FREQUENCY MHz Figure 21 Frequency Response of the Ferrite Chips Z3 and Z4 in the A
188. edidor cercano al fdp de l nea se logra una exactitud de casi 1 con fdp que var an de la unidad hasta el 40 Otra clase surge de la suma vectorial de las energ as activa y reactiva se efect a ya sea por medios electromagn ticos o electromec nicos muchos de ellos muy ingeniosos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Medidores de potencia aparente digital Para el c lculo de la potencia aparente se utiliza el concepto que enuncia SHV as Ecuaci n 5 1 Para ello se hace referencia al m todo que nos permiti obtener el valor RMS en la Ecuaci n 1 5 Esto es hallar el valor RMS tanto para la de voltaje como de la corriente y finalmente se saca el producto de ambos valores RMS como lo expresa la Ecuaci n 5 1 2 1 3 INSTRUMENTOS DE MEDICI N POR APLICACI N e Medidores monofasicos Hace referencia a los medidores que son disenados para calcular el consumo de par metros el ctricos en un sistema de distribuci n monof sico de 2 hilos 1 Fase y un Neutro LOS MEDIDORES MONOFASICOS ESTAN DISENADOS PARA CONECTARSE EN SISTEMAS DE 2 HILOS FASE Y NEUTRO Figura 2 9 Conexi n de un medidor del tipo monof sico 1 fase 1 neutro Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis
189. effects of externally shorting the shunt are very much minimized Therefore the shunt should always be made as small as possible but this must be offset against the signal range on V1 0 mV 20 mV rms with a gain of 16 If the shunt is made too small it will not be possible to meet the IEC1036 accuracy requirements at light loads A shunt value of 350 uQ was considered a good compromise for this design REV A Design Calculations Design parameters Line voltage 220 V nominal Imax 40 A Ib 5 A Counter 100 imp kWh Meter constant 3200 imp kWh Shunt size 350 uQ 100 imp hour 100 3600 sec 0 027777 Hz Meter will be calibrated at Ib 5A Power dissipation at lb 220 V x5 A 1 1 kW Frequency on F1 and F2 at Ib 1 1 0 027777 Hz 0 0305555 Hz Voltage across shunt V1 at lb 5 A 350 uQ 1 75 mV To select the F _ frequency for Equation 1 see the AD7755 data sheet Selecting a Frequency for an Energy Meter Application section From Tables V and Vl in the AD7755 data sheet it can be seen that the best choice of fre quency for a meter with Imax 40 A is 3 4 Hz F2 This frequency selection is made by the logic inputs 50 and S1 see Table Il in the AD7755 data sheet The CF fre quency selection meter constant is selected by using the logic input SCF The two available options are 64 x F1 6400 imp kWh or 32 x F1 3200 imp kWh For this design 3200 imp kWh is selected by setting SCF logic low With a
190. el and sampling frequency used in the waveform sampling mode see Table 20 0x16 COMPMODE Computation Mode Register This register configures the formula applied for the energy and line active energy measurements see Table 22 0x17 LCYCMODE Line Cycle Mode Register This register configures the line cycle accumulation mode for WATT HR VAR HR and VA Hr see Table 23 0x18 MASK IRQ Mask Register It determines if an interrupt event generates an active low output at the IRQ pin see the Interrupts section 0x19 STATUS IRQ Status Register This register contains information regarding the source of the ADE7758 interrupts see the Interrupts section Ox1A RSTATUS IRQ Reset Status Register Same as the STATUS register except that its contents are reset to 0 all flags cleared after a read operation 0x1B ZXTOUT OxFFFF Zero Cross Timeout Register If no zero crossing is detected within the time period specified by this register the interrupt request line IRQ goes active low for the corresponding line voltage The maximum timeout period is 2 3 seconds see the Zero Crossing Detection section Ox1C LINECYC OxFFFF Line Cycle Register The content of this register sets the number of half line cycles that the active reactive and apparent energies are accumulated for in the line accumulation mode 0x1D SAGCYC SAG Line Cycle Register This register specifies the number of consecutive half line cycles where voltage channel input may fall be
191. el autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA m TESIS PUCP UNIVERSIDAD DEL PERU 45 RECOMENDACIONES Finalizado el proyecto de tesis luego de meses de intenso trabajo se procede a plantear las siguientes recomendaciones pues como se mencion el equipo desarrollado es parte de un sistema mayor de medici n de par metros el ctricos Las recomendaciones tienen por objetivo plantear las tareas a resolver para futuras investigaciones en este tema Ahondar en el estudio de corrientes y voltajes de las fuentes directas de alimentaci n industrial 220VAC 380VAC 440VAC etc para as desarrollar el ACONDICIONAMIENTO DE DATOS y se pueda hacer experimentaciones con senales el ctricas reales e Desarrollar un software sencillo para PC de interacci n con el usuario que en lo posible sea de manejo intuitivo y no presente datos a nivel programador e El ADE7758 presenta entre sus diversas configuraciones el modo de integrador para la corriente de entrada Una soluci n de mejorar y disminuir costos es utilizando la denominada bobina de Rogowski para la etapa de sensado corriente como se explica en el Anexo C Tecnolog as para medici n de corriente Secci n Bobina Rogowski P g 11 e De los par metros el ctricos registrados por el ADE7758 se puede encontrar aplicaciones futuras mejorando la l gica de control para que se encargue de
192. emote 3900 C Tempus Tempus Chote Prueba 3041 Origen de Dales Be Eraihia Externe pee soon en Teto 256 C Deci Escutura rban Esas EEPROM Inema Fecha Lectura Estaria pa jon Direccion Deci Bytes par Hora jo A 2 Lectura RAM Intema ne Lectura EEPROM Inteina Destino de Datos oca EPROM oe EJ gt Pec ee 1 ss Pracesar Mascaciones E Documents ard Se gt WINSOCK PROGRAMA DESARROLLADO POR LA EMPRESA FABRICANTE DEL TEMPUS VI Figura 4 2 Winsock Programa para comunicaci n con el TEMPUS VI La modificaci n del programa se puede observar en la Figura 4 3 esta modificaci n logra leer con un PC los registros internos del ADE7758 en el prototipo mediante la comunicaci n TCP IP El programa modificado contiene una secci n denominada Medidor de energ a en la cual figuran todos los registros que maneja el ADE7758 estos registros est n acondicionados como lectura y o escritura seg n se indica en el Anexo F Hojas t cnicas Hoja t cnica del ADE7758 Rev C Secci n Registers P g 60 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA PU rb res CATOLICA DEL PERU TESIS PUCP Tipo de Conexi n 068 Cliente Remote 92 168 1 82 Transmitir Remote Port cde 8000 C Tempu T
193. empus Connect Close CARAS bwatthr E H w byarhr em wavmode compmode kyemode mask status maus mauri RA ____ sage saglvl RAW vpeak peak gin ____ awmsgan bwmsgan cwmsgan cigain RAW ag bg ew I RW avag RAV bag avag bag RW wag avimsos byrmsos RAV cvrmsos RAV aimsos bimsos citmsos awatos bwato bvaros __ ama R W _bphcal ______ __ wdw vadv RAW vadiv ERN RA apcfnum RAW apdden varcfnum varcfden chksum version cwato RAW anode F agen ____ avaos mmode ____ bigain ____ SOFTWARE MODIFICADO A PARTIR DEL WINSOCK ESTE PROGRAMA ENLAZAR COMUNICACION ETHERNET Y LEER TODOS LOS REGISTROS INTERNOS DEL ADE7758 Figura 4 3 Winsock modificado para lectura de registros del AD
194. en the 10 nF Capacitor C16 is connected a low imped ance path is provided for differential EFT pulses Figure 29 shows the effect of connecting C16 Here the stray inductance L1 is left at 1 uH and the MOV is in place The plot shows the current through C16 and the voltage across the 50 load The capacitor C16 provides a low impedance path for the EFT pulse Note the peak current through C16 of 80 A The result is that the amplitude of the EFT pulse is greatly attenuated REV A d Ll 0A B 20 ACROSS 500 LOAD 100V 40A MI 100V L 80 Figure 29 EFT Generator Output into 50 with MOV in Place Stray Inductance of 1 uH and C16 10 nF in Place IEC1000 4 5 The purpose of IEC1000 4 5 is to establish a common reference for evaluating the performance of equipment when subjected to high energy disturbances on the power and interconnect lines Figure 30 shows a circuit that was used to generate the combinational wave hybrid pulse described in IEC1000 4 5 It is based on the circuit shown in Figure 1 of IEC1000 4 5 1995 02 Such a generator produces a 1 2 us 50 us open circuit voltage waveform and an 8 us 20 us short circuit current waveform which is why it is referred to as a hybrid gen erator The surge generator has an effective output impedance of 2 This is defined as the ratio of peak open circuit voltage to peak short circuit current Figure 30 Surge
195. energy GAIN dB 04443 065 e e e FREQUENCY Hz Figure 65 Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase Rev C Page 30 of 72 Active Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by 50 by writing to the phases watt gain register AWG BWG or CWG The watt gain registers are twos complement signed registers and have a resolution of 0 024 LSB Equation 16 describes mathematically the function of the watt gain registers Average Power Data Watt Gain Register 16 LPF2 Output x 14 2 The output is scaled by 5096 by writing 0x800 to the watt gain registers and increased by 50 by writing Ox7FF to them These registers can be used to calibrate the active power or energy calculation in the ADE7758 for each phase Active Power Offset Calibration The ADE7758 also incorporates a watt offset register on each phase AWATTOS BWATTOS and CWATTOS These are signed twos complement 12 bit registers that are used to remove offsets in the active power calculations An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed One LSB in the active power offset register is equivalent to 1 16 LSB in the act
196. ensation Network Figure 12 also gives an expression for the location of the poles of this compensation network The purpose of Pole 1 is to cancel the effects of the zero due to the shunt inductance Pole 2 will perform the function of the antialias filters as described in the Antialias Filters section The following illustrates a sample calculation for a shunt of 330 uQ with a parasitic inductance of 2 nH The location of the pole 1 is given as 3 1 1 X X 3 RC 4 330 uQ Lop 2 nH C 33 nF Rsm Lsm For Row R is calculated as approximately 480 use 470 Q The location of Pole 1 is 165 000 rads or 26 26 kHz This places the location of Pole 2 at 3 3 838 kHz 2 RC Y4 To ensure phase matching between Channel 1 and Channel 2 the pole at Channel 2 must also be positioned at this location With C 2 33 nF the new value of resistance for the antialias filters on Channel 2 is approximately 1 23 use 1 2 Figure 13 shows the effect of the compensation network on the phase and magnitude response of the antialias network in Channel 1 The dashed line shows the response of Channel 2 using practical values for the REV A newly calculated component values i e 1 2 and 33 nF The solid line shows the response of Channel 1 with the parasitic shunt inductance included Notice phase and magnitude responses match very closely with the ideal response shown as
197. ento ni que demande grandes y complejos conocimientos en el tema Adicionalmente el entorno de programaci n deb a soportar como m nimo compiladores para equipos de la compania PALM y que puedan generar instaladores para las diversas versiones de SO que provee dicha empresa Componente seleccionado Entre los entornos de programaci n investigados se hallaban SUPERWABA Entorno de programaci n basado en tecnolog a Java con manejo de objetos No genera c digo nativos de PALM sino que requiere la instalaci n una maquina virtual de Waba para la correcta ejecuci n de sus instaladores Para iniciar el modo de programaci n se requiere de otros Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis ENER Y lt PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU entornos en JAVA ECLIPSE NETBEAMS ente otros y su configuraci n inicial no es apta para principiantes en el tema de programaci n Es gratis y de descarga libre a sola suscripci n CODEWARRIOR Entorno de programaci n basado en lenguaje C es un c digo que lo provee la misma empresa PALM ONE para el desarrollo de programas para sus equipos Al no ser un c digo abierto de libre descarga se hace dif cil probarlo en todas sus funciones e HANDHELD BASIC HB El HandHeld Basic al igual que el CodeWarrior no es un entorno de programacion de libre acceso y
198. eservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD CATOLICA DEL PERU SID JYN LAVOI 1 6 ISV313Y avoso OOVTIOYYVSI0 VIN3 LSIS 130 OTNGOW 130 OOILVININOSI 1 E O 4 gt QU Y 0 N O 22 cam O iS Oo on v A 2 U ed a t 5 22 ie Z W e gt ie al u u 2 lt ca LLJ LLJ un Lid cc Rh cc uu VINALSIS 13 ON3SIG 3 OXANV E U gt u LLI H LV LnOAV1 1 6 38V313Y Na OOVTIOYYVSI0 INO LLOS8 SVLSId 30 VLSIA VNALSIS 130 OTNGOW 130 OQValnos 10M E LnOAV1 L6 3I8V313Y OOVTIOYYVSI0 SV1SId 30 VLSIA VNALSIS 130 OTNGOW OGVALNOY oe e 12 bd Z SOME RIGHTS RESERVED PONTIFICIA TESIS PUCP T UNIVERSIDAD DEL PERU 1 cI gt gt E10 Tor A P 31449 14403 uino cit Cla ROUTEADO DEL MODULO DEL SISTEMA VISTA DE COMPONENTES C C WA tier 11 01 20 902 210 gt 200 03 200 03 2 n3 07 N4f48 55 94 DESARROLLADO ORCAD RELEASE 9 1 LAYOUT ROUTEADO
199. ess or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in Tl data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated 1 product or service and is an unfair and deceptive business practice 1115 not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of t
200. et portion of the PCB Remember that with a shunt size of 350 uQ the voltage signal range on Channel 1 is 35 uV to 14 mV 2 Ib to 80096 Ib Figure 35 shows the PCB floor plan which was eventually adopted for the watt hour meter REV A AREAS ISOLATED WITH NO GROUND PRESENT ON ANY PLATE GROUNDS CONNECTED VIA FERRITE BEAD DIGITAL GROUND NOISY 32mA FROM PSU AD APPEARS AS PART OF THE COMMON MODE VOLTAGE FOR V1 NV Figure 35 AD7755 Watt Hour Meter PCB Design The partitioning of the power planes in the PCB design as shown in Figure 35 also allows us to implement the idea of a moat for the purposes of immunity to elec tromagnetic disturbances The digital portion of the PCB is the only place where both phase and neutral wires are connected This portion of the PCB contains the transience suppression circuitry MOV ferrite etc and power supply circuitry The ground planes are connected via a ferrite bead that helps to isolate the analog ground from high frequency disturbances see Design For Immunity to Electromagnetic Disturbances section METER ACCURACY TEST RESULTS 0 4 LEONE eres I 0 3 Hy X x ELE 811111 X ELE 811111 as LH ELIT 0 01 100 ANDS Figure 36 Measurement Error Reading 25 C 220 V PF 0 5 0 5 Frequency 50 Hz REV A 15 AN 559 0 5
201. ex Press Fit Mil Max no 0328 0 15 XX 34 XX 10 0 Digi Key ED5017 ND Counter 2 Phase Stepper 100 imp China National Electronics Import amp 18 Export Shaanxi Co No 11 A Jinhua northern Road Xi an China Email chenyf public xa sn cn Tel 86 29 3218247 3221399 Fax 86 29 3217977 3215870 REV A AN 559 Hz comma Own Kd db R17 O Ena Y PT AD77550 EJ 05 OENERGY METER o REVB 8 99 0 O O ka Figure 42 PCB Bottom Layer REV A 19 AN 559 Vop R1 R20 200 1k0 Co K5 23 VAL 1 R22 100 C15 Ki 1 2 0 033 pF l 0 1pF R2 C13 C12 C11 C10 74 VAL 1k0 0 11 F 0 11 F 2 L T z C14 C2 0 1uF R19 200 eee K6 1 24 DVDD F1 D1 SHEET 2 2 AD7755 F2 23 P d 1 4 R3 C3 AVDD cr 22 o CALHIGH CALLOW 1kQ 0 033uF NC1 DGND 21 218 HLMPD150 gt E dF V1P REVP 20 8200 C9 Co K8 9 viN 2 19 V 22 7 V2N CKLOUT 18 9 V2P CLKIN Y1 C8 RESET GO 22pF 0 15 G1 AGND 0 3 579545MHz R17 J15L 00 J15H 00 1k0 J15 J14L 00 J14H 00 DD 1 O J13L 00 J13H 00 J12L 00 J12H 00 An x C7 0 11F V OPTIONAL J11 E REFERENCES Y J11L 00 J11H 00 CALHIGH CALLOW SHEET 1 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 300kQ 150k0 75kQ 39k0 18k0 9 1kO 5 1k0 2 2kQ 1 2k0 5600 CALIBRATION NETWORK Figure 44 Schem
202. figured to issue an interrupt IRQ when the MSB of any one of the three VA hr accumulation registers has changed indicating that the accumulation register is half full Setting the RSTREAD bit Bit 6 of the LCYMODE register enables a read with reset for the VA hr accumulation registers that is the registers are reset to 0 after a read operation Integration Time Under Steady Load The discrete time sample period T for the accumulation register is 0 4 us 4 CLKIN With full scale 60 Hz sinusoidal signals on the analog inputs and the VAGAIN registers set to 0x000 the average word value from each LPF2 is 0xB9954 The maximum value that can be stored in the apparent energy register before it overflows is 2 1 or 0 As the average word value is first added to the internal register which can store 2 1 or 0x1FE FFFF FFFF before it overflows the integration time under these conditions with VADIV 0 is calculated as OxlFF FFFF FFFF Time gt x 0 4 us 1 157 sec 43 0xB9954 When VADIV is set to a value different from 0 the time before overflow is scaled accordingly as shown in Equation 44 Time Time VADIV 0 x VADIV 44 VARHR 15 0 APPARENT POWER IS ACCUMULATED INTEGRATED IN THE VA HR ACCUMULATION REGISTERS 04443 075 Figure 75 ADE7758 Apparent Energy Accumulation Rev C Page 40 of 72 Table 14 Inputs to Accumulation Registers CONSEL 1 0 BVAHR 00 AVRMS x AIRMS
203. fset Distribution MEAN 6 69333 SD 2 70443 2 4 6 8 10 12 14 CH 1 PhC OFFSET mV Figure 33 Phase C Channel 1 Offset Distribution 04443 032 04443 033 ADE7 1758 TEST CIRCUITS AA CURRENT 10uF 100nF TRANSFORMER Vp O cua Rm AVDD DVDD VARCF 1kO o 5 TO FREQ 6 IAN V 33nF 22pF y CLKOUT 26 E 10MHz SAME AS a lap lAN CLKIN 19 x 22pF 1MO CS 21 gt TO SPI BUS 220V Y 33nF d ve DIT CT TURN RATIO 1800 1 1kOQ 13 ES CHANNEL 2 GAIN 1 1 2 50 5 4 2 50 8 1 250 3 Figure 34 Test Circuit for Integrator Off 9 104F 100nF a Y Y AM 8250 MA PS2501 1 Q AVDD DVDD VARCF APCF IAP 1 ADE7758 COUNTER 33nF di d 22pF CLKOUT A V AS 7 10MHz V LAN G IBN CLKIN 19 Fa 22pF lap lAN 10 ICN SCLK 23 1 cs TO SPI BUS 16 VAP D 220V Y 1kQ 33nF DIN Q2 V V SAME AS Vap 15 VBP SAME AS Vap 14 VCP 400nF CHANNEL 1 GAIN 8 CHANNEL 2 GAIN 1 04443 035 L 33nF y Figure 35 Test Circuit for Integrator On Rev C Page 17 of 72 7758 THEORY OF OPERATION ANTIALIASING FILTER This filter prevents aliasing which is an artifact of all sampled systems Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a fre quency below half the sampling rate This
204. gnal to its original form The ADE7758 has a built in digital integrator to recover the current signal from the di dt sensor The digital integrator on Channel 1 is disabled by default when the ADE7758 is powered up Setting the MSB of the GAIN 7 0 register turns on the integrator Figure 43 to Figure 46 E EN CY Hz show the magnitude and phase response of the digital 04443 045 Figure 45 Combined Gain Response of the integrator Digital Integrator and Phase Compensator 40 Hz to 70 Hz RM NNI 89 80 5 lt 89 90 5 8 z 4 A 89 95 o 4 I a 90 00 EJE bi RUE 2 04443 043 04443 046 e x e 0 FREQUENCY Hz 40 45 50 55 60 65 7 FREQUENCY Hz e Figure 43 Combined Gain Response of the Digital Integrator and Phase Compensator Figure 46 Combined Phase Response of the Digital Integrator and Phase Compensator 40 Hz to 70 Hz Rev C Page 20 of 72 Note that the integrator has a 20 dB dec attenuation and approximately 90 phase shift When combined with a di dt sensor the resulting magnitude and phase response should be a flat gain over the frequency band of interest However the di dt sensor has a 20 dB dec gain associated with it and generates significant high frequency noise A more effective antialiasing filter is needed to avoid noise due to aliasing see the Theory of Operation section When the digital integrator is switched off the
205. hannel Figure 39 shows how the gain settings in PGA 1 current channel and PGA 2 voltage channel are selected by various bits in the gain register GAIN REGISTER CURRENT AND VOLTAGE CHANNEL PGA CONTROL 7 6 5 4 3 2 1 0 nm INTEGRATOR ENABLE J L PGA 1 GAIN SELECT 0 DISABLE 00 x1 1 ENABLE RESERVED x2 10 x4 2 GAIN SELECT 00 1 CURRENT INPUT FULL SCALE SELECT 012x2 00 0 5V 102x4 01 0 25V 10 0 125V 1REGISTER CONTENTS SHOW POWER ON DEFAULTS 04443 039 Figure 39 Analog Gain Register Rev C Page 18 of 72 Bit 7 of the gain register is used to enable the digital integrator in the current signal path Setting this bit activates the digital integrator see the DI DT Current Sensor and Digital Integrator section CURRENT CHANNEL ADC Figure 41 shows the ADC and signal processing path for the input IA of the current channels same for IB and IC In waveform sampling mode the ADC outputs are signed twos complement 24 bit data words at a maximum of 26 0 kSPS thousand samples per second With the specified full scale analog input signal of 0 5 V the ADC produces its maximum output code value see Figure 41 This diagram shows a full scale voltage signal being applied to the differential inputs IAP and IAN The ADC output swings between 0xD7AE14 2 642 412 and 0x2851EC 42 642 412 Current Waveform Gain Registers There is a multiplier in the signal path in the current chan
206. happens with all ADCs regardless of the architecture The combination of the high sampling rate X A ADC used in the ADE7758 with the relatively low bandwidth of the energy meter allows a very simple low pass filter LPF to be used as an antialiasing filter A simple RC filter single pole with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 833 kHz This is usually sufficient to eliminate the effects of aliasing ANALOG INPUTS The ADE7758 has six analog inputs divided into two channels current and voltage The current channel consists of three pairs of fully differential voltage inputs IAP and IAN IBP and IBN and ICP and ICN These fully differential voltage input pairs have a maximum differential signal of 0 5 V The current channel has a programmable gain amplifier PGA with possible gain selection of 1 2 or 4 In addition to the PGA the current channels also have a full scale input range selection for the ADC The ADC analog input range selection is also made using the gain register see Figure 38 As mentioned previously the maximum differential input voltage is 0 5 V However by using Bit 3 and Bit 4 in the gain register the maximum ADC input voltage can be set to 0 5 V 0 25 V or 0 125 V on the current channels This is achieved by adjusting the ADC reference see the Reference Circuit section Figure 36 shows the maximum signal levels on the current channel inputs The maximum common
207. he calculated value to perform a coarse adjustment on the imp kWh ratio For VAR VA calibration set VARCFNUM 0x47 and VARCFDEN 0x48 to the calculated value The pulse output frequency with one phase at full scale inputs is approximately 16 kHz A sample set of meters could be tested to find a more exact value of the pulse output at full scale in the user application To calculate the values for APCFNUM APCFDEN and VARCFNUM VARCFDEN use the following formulas V I 16 KHz x x BB 45 FULLSCALE I FULLSCALE x x NOM x cos 0 46 EXPECTED 1000 3600 APCFDEN mr 47 EXPECTED where MC is the meter constant Iresr is the test current Vnom is the nominal voltage at which the meter is tested Vrurrscare and Iruuscare are the values of current and voltage which correspond to the full scale ADC inputs of the ADE7758 0 is the angle between the current and the voltage channel APCFzxrzcrep is equivalent to the reference meter output under the test conditions APCFNUM is written to 0 or 1 The equations for calculating the VARCFNUM and VARCFDEN during VAR calibration are similar MCX Ligsr X V NOM sin 0 48 VARC Emp 1000 x 3600 CTED Because the APCFDEN and VARCFDEN values can be calculated from the meter design these values can be written to the part automatically during production calibration Step 5 Set the tes
208. he ABS and SAVAR bits of the COMPMODE register are as follows when ABS 1 and SAVAR I If watt gt 0 APCF Watts VARCF 4 VAR If watt 0 APCF VAR INPUT TO AVARHR REGISTER INPUT TO BVARHR 7 VARCFNUN 11 0 INPUT TO d REGISTER 4 P0 VARCF INPUT TO AVAHR REGISTER VARCFDEN 11 0 INPUT TO BVAHR _ REGISTER INPUT Seren VACF BIT BIT 7 OF WAVMODE REGISTER 04443 073 Figure 73 Reactive Power Frequency Output The output from the DFC is divided down by a pair of frequency division registers before sending to the VARCF pulse output Namely VARCFDEN VARCFNUM pulses are needed at the DFC output before the VARCF pin outputs a pulse Under steady load conditions the output frequency is directly proportional to the total reactive power Figure 73 illustrates the energy to frequency conversion in the ADE7758 Note that the input to the DFC can be selected between the total reactive power and total apparent power Therefore the VARCF pin can output frequency that is proportional to the total reactive power or total apparent power The selection is made by setting the VACF bit Bit 7 in the WAVMODE register Setting this bit switches the input to the total apparent power The default value of this bit is logic low Therefore the default output from the VARCF pin is the total reactive power All other operations of this frequency output are similar to that of the a
209. he Tl product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific Tl products are designated by TI as compliant with ISO TS 16949
210. he attenuation at 1 MHz is now only about 15 dB which could cause some repeatabil ity and accuracy problems in a noisy environment More importantly a phase mismatch may now exist between the current and voltage channels Assuming the network on Channel 2 has been designed to match the ideal phase response of Channel 1 there now exists a phase mismatch of 0 1 at 50 Hz Note that 0 1 will cause a 0 396 measurement error at PF 0 5 See Equation 2 Correct Phase Matching Between Channels 100 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 11 Effect of Parasitic Shunt Inductance on the Antialias Network The problem is caused by the addition of a zero into the antialias network Using the simple model for the shunt shown in Figure 10 the location of the zero is given as radians One way to cancel the effects of this additional zero in the network is to add an additional pole at or close to the same location The addition of an extra RC on each analog input of Channel 1 will achieve the additional REV A AN 559 pole required The new antialias network for Channel 1 is shown in Figure 12 To simplify the calculation and demonstrate the principle the Rs and Cs of the network are assumed to have the same value jo POLE 1 POLE 2 3 1 5 1 2 nc ZERO 1 R R 1 i C I C 5 S R C S3RC 1 Figure 12 Shunt Inductance Comp
211. here are nine energy registers For this example Iresr 10 A Vnom 220 V Power Factor 1 Frequency 50 Hz LINECYC 0x1C is set to 0x800 and MC 3200 imp kWhr Rev C Page 50 of 72 To set APCFNUM 0x45 and APCFDEN 0x46 to the calculated value to perform a coarse adjustment on the imp kW hr ratio use Equation 45 to Equation 47 220 10 16kHz x x 20 5415 kHz NOMINAL 500 130 3200 x 10 x 220 1000 x 3600 APCF EXPECTED x cos 0 1 956 Hz 541 5 Hz APCFDEN INT 277 1 956 Hz Under the test conditions above the AWATTHR register value is 15559d after the LENERGY interrupt Using Equation 60 and Equation 61 the value to be written to AWG is 199d OxF39 LINECYC 15 0 AccumTime 2x X No of Phases Selected FREQ 11 0 x9 6x10 0x800 AccumTime T 6 832128s 2x gr 2085x9 6x10 WA 4 3200 10 220 1 6 832 277 x x 1 14804 1000 x 3600 1 14804 G ES 198 87640 199 OxF39 15559 Using Equation 66 the Wh LSB constant is Wh 10 220 6 832 0 0002820 LSB 3600 x 14804 Phase Calibration Using Line Accumulation The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors Large phase errors should be compensated by adjusting the antialiasing filters The ADE77585 phase calibration is a time delay with different weights in the positive and negative
212. here may be higher sensitivity to certain frequencies due to resonances on the PCB These resonances could cause insertion gain at certain frequencies which in turn could cause problems for sensitive devices By far the greatest RF signal levels are those coupled into the system via cabling These connection points should be protected Some techniques for protecting the sys tem are 1 Minimize Circuit Bandwidth 2 Isolate Sensitive Parts of the System Minimize Bandwidth In this application the required analog bandwidth is only 2 kHz This is a significant advantage when trying to reduce the effects of RF The cable entry points can be low pass filtered to reduce the amount of RF radiation entering the system The shunt output is already filtered before being connected to the AD7755 This is to prevent aliasing effects that were described earlier By choosing the correct components and adding some additional components e g ferrite beads these antialias filters can double as very effective RF filters Figure 7 shows a somewhat idealized frequency response for the antialias filters on the analog inputs When considering higher frequencies e g 1 MHz the parasitic reactive ele ments of each lumped component must be considered Figure 20 shows the antialias filters with the parasitic elements included These small values of parasitic capaci tance and inductance become significant at higher frequencies and therefore must be consider
213. hey form a low resistance shunt and thus prevent any further rise in the voltage across the circuit being protected The overvoltage is essentially dropped across the source impedance of the overvoltage source e g the mains network source impedance Figure 24 illustrates the principle of operation uA SS OVERVOLTAGE SOURCE ELECTRONIC CIRCUIT TO BE PROTECTED LOAD LINE OF THE OVERVOLTAGE CHARACTERITIC CURVE OF MOV LEAKAGE SURGE CURRENT gt gt 0 CURRENT TAKEN FROM SIEMENS MATSUSHITA COMPONENTS SIOV METAL OXIDE VARISTOR CATALOG Figure 24 Principle of MOV Overvoltage Protection The plot in Figure 24 shows how the MOV voltage and current can be estimated for a given overvoltage and source impedance A load line open circuit voltage short circuit current is plotted on the same graph as the MOV characteristic curve Where the curves intersect the MOV clamping voltage and current can be read Note that care must be taken when determining the short circuit current The frequency content of the over voltage must be taken into account as the source impedance e g mains may vary considerably with fre quency A typical impedance of 50 is used for mains source impedance during fast transience high frequency pulse testing The next section discusses IEC1000 4 4 and IEC1000 4 5 which are transience and overvoltage EMC compliance tests IEC1000 4 4 and the 520 275 While the graph
214. his point the DOUT logic output switches from a high impedance state and starts driving the data bus All remaining bits of register data are shifted out on subsequent SCLK rising edges The serial interface enters communications mode again as soon as the read is completed The DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse ADE7758 The read operation can be aborted by bringing the CS logic input high before the data transfer is completed The DOUT output enters a high impedance state on the rising edge of CS When an ADE7758 register is addressed for a read operation the entire contents of that register are transferred to the serial port This allows the ADE7758 to modify its on chip registers without the risk of corrupting data during a multibyte transfer Note that when a read operation follows a write operation the read command that is write to communications register should not happen for at least 1 1 us after the end of the write operation If the read command is sent within 1 1 us of the write operation the last byte of the write operation can be lost ACCESSING THE ON CHIP REGISTERS All ADE7758 functionality is accessed via the on chip registers Each register is accessed by first writing to the communications register and then transferring the register data For a full description of the serial interface protocol see the Serial Interface section Rev C Page 59 of 72
215. hould be decoupled to AGND with a 10 pF capacitor in parallel with a ceramic 100 nF capacitor IAP IAN Analog Inputs for Current Channel This channel is used with the current transducer and is referenced in this IBP IBN document as the current channel These inputs are fully differential voltage inputs with maximum differential 0 ICP ICN input signal levels of 0 5 V 0 25 V and 0 125 V depending on the gain selections of the internal PGA see the Analog Inputs section All inputs have internal ESD protection circuitry In addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage This pin provides the ground reference for the analog circuitry in the ADE7758 that is ADCs temperature sensor and reference This pin should be tied to the analog ground plane or the quietest ground reference in the system This quiet ground reference should be used for all analog circuitry for example antialiasing filters current and voltage transducers To keep ground noise around the ADE7758 to a minimum the quiet ground plane should be connected to the digital ground plane at only one point It is acceptable to place the entire device on the analog ground plane 12 REFinyout This pin provides access to the on chip voltage reference The on chip reference has a nominal value of 2 4V 8 and a typical temperature coefficient of 30 ppm C An external reference source can also be connected at this pin In either ca
216. how to calibrate the gain offset and phase angle using the pulsed output information The equations are based on the pulse output from the ADE7758 APCF or VARCE and the pulse output of the reference meter Or Figure 76 shows a flowchart of how to calibrate the ADE7758 using the pulse output Because the pulse outputs are proportional to the total energy in all three phases each phase must be calibrated individually Writing to the registers is fast to reconfigure the part for calibrating a different phase therefore Figure 76 shows a method that calibrates all phases at a given test condition before changing the test condition Rev C Page 42 of 72 CALIBRATE IRMS OFFSET CALIBRATE VRMS OFFSET START MUST BE DONE BEFORE VA GAIN CALIBRATION ALL PHASES VA AND WATT GAIN CAL YES SET UP PULSE OUTPUT FOR A B ORC CALIBRATE WATT AND VA GAIN 1 YA Y WATT AND VA CAN BE CALIBRATED SIMULTANEOUSLY PF 1 BECAUSE THEY HAVE SEPARATE PULSE OUTPUTS CALIBRATE VAR GAIN O PF 0 INDUCTIVE SET UP PULSE OUTPUT FOR A B ORC CALIBRATE ALL PHASES PHASE VAR OFFSET PF 0 5 CAL INDUCTIVE SET UP PULSE OUTPUT FOR A B ORC ALL PHASES CALIBRATE WATT OFFSET VAR OFFSET CAL PF 0 INDUCTIVE YES SET UP PULSE OUTPUT FOR A B ORC CALIBRATE WATT OFFSET IMIN PF 21 04443 076
217. i ndose en un factor clave a nivel econ mico por el control eficiente del consumo el ctrico que posteriormente se ver reflejado en mejoras de los costos de producci n Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU A qui n sino a ti Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU AGRADECIMIENTOS Nunca un se present con tantas pruebas y obst culos con seguridad puedo decir que los aprendizajes obtenidos en este proceso marcar n mi camino de hoy en adelante oin duda los mayores agradecimientos ser n siempre para mis padres las dos personas m s especiales en mi vida porque sin ellos y sus no estar a aqu ni ser a quien soy ahora Mi m s amplio agradecimiento para el Ing Jan Leuridan Gerente General de la empresa Sistemas Inteligentes S A C cuyo invaluable y generoso apoyo e inter s hicieron posibles la realizaci n de este proyecto de tesis as como por brindarme su amistad compartir su conocimiento conmigo e inspirar en mi mucha admiraci n A mis familiares por su apoyo incondicional y porque s que est n orgullosos de m A aquellas personas que aparecieron en mi vida para quedarse y que denomino
218. ical technique just described is useful an even better approach is to use simulation to obtain a better understanding of MOV operation EPCOS Components provides SPICE models for all their MOVs and these are very useful in determining device operation under the various IEC EMC compliance tests For more informa tion on EPCOS SPICE models and their applications see http www epcos de int 70 e0000000 htm AN 559 The purpose of IEC1000 4 4 is to determine the effect of repetitive low energy high voltage fast rise time pulses on an electronic system This test is intended to simulate transient disturbances such as those originating from switching transience e g interruption of inductive loads relay contact bounce etc Figure 25 shows an equivalent circuit intended to repli cate the EFT test pulse as specified in IEC1000 4 4 The generator circuit is based on Figure 1 IEC1000 4 4 1995 01 The characteristics of operation are Maximum energy of 4 mJ pulse at 2 kV into 50 Source impedance of 50 2096 DC blocking capacitor of 10 nF Pulse rise time of 5 ns 30 Pulse duration 50 value of 50 ns 3096 Pulse shape as shown in Figure 23 Figure 25 EFT Generator The simulated output of this generator delivered to a purely resistive 50 load is shown in Figure 26 The open circuit output pulse amplitude from the generator is 4 kV Therefore the source impedance of the genera tor is 50
219. icos posee una l nea evolutiva desde sus inicios con medidores del tipo mec nicos hasta la actualidad con los medidores electr nicos o de estado s lido e Hacia el a o 1870 la medici n el ctrica se basaba en conocer el tiempo que fluy la corriente sobre las l mparas de arco conectadas en serie Dado que conoc an previamente el voltaje requerido por l mpara y la corriente era constante e 18 2 Samuel Gardiner saca la primera patente conocida sobre un medidor de electricidad Este era medidor DC de horas l mpara que ten a un electroim n que se encargaba de encender y apagar el mecanismo de un reloj e 1878 J B Fuller saca la patente de un medidor AC de horas l mpara que tenia un reloj operado por una armadura met lica que vibraba entre dos resortes de espiral Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 1882 homas Edison desarroll un medidor qu mico de ampere hora que consist a en una vasija contenedora de dos placas de zinc que se conectaban al circuito a medir Cada mes los electrodos eran pesados y la facturaci n del cliente era determinada por la diferencia de peso 1885 Galileo Ferrari de Tur n Italia hace el descubrimiento que dos campos de corriente alterna desfasados pueden hacer girar una armadura s lida Este descubrimiento estimular el desarrollo
220. in the phase calibration routine xWATTHR xWATTHR E 2 Error XWATTHR 69 2 Step 5 Calculate the Phase Error in degrees using the equation 70 E Phase Error Arsin NE Step 6 Calculate and write to the xPHCAL registers to 0x41 xPHCAL 1 1 1 7D PHCAL_LSB_Weight LinePeriod s 360 Phase Error x Rev C Page 51 of 72 7758 where PHCAL LSB Weight is 1 2 us if the is negative or 2 4 us if the Error is positive see the Phase Compensation section If it is not known the line period is available in the 77585 frequency register FREQ 0x10 To configure line period measurement select the phase for period measurement in the MMODE 1 0 and set LCYCMODE 7 Equation 72 shows how to determine the value that needs to be written to xPHCAL using the period register measurement xPHCAL 9 6 us FREQ 11 0 72 PHCAL LSB Weight 360 Phase Error x Example Phase Calibration Using Line Accumulation This example shows only Phase A phase calibration All three PHCAL registers can be calibrated simultaneously using the same method For this example Irzsr 10 A 220 V Power Factor 0 5 inductive and Frequency 50 Hz Also LINECYC 0x800 FOR STEP 8 READ ALL xVARHR AFTER LENERGY INTERRUPT SET MMODE LCYCMODE LINECYC AND MASK REGISTERS SET UP SYSTEM FOR Ivins PF 1
221. ing free air temperature unless otherwise noted VOH High level output voltage undi 400 pA VOL Low level output voltage El Sec IOL 8 mA l7 High impedance state output current Vo 0 4 V to 2 4 V ps Other input 0 V Vi 12V EMEN High level enable input current Vin 27 V Low level enable input current Vip 0 4 V LN Short circuit output current T All typical values are at 5 V TA 25 t The algebraic convention in which the less positive more negative limit is designated minimum is used in this data sheet for common mode input voltage and threshold voltage levels only NOTE 3 This applies for both power on and power off Refer to ANSI Standard EIA TIA 422 B for exact conditions lec Supply current total package switching characteristics Vcc 5 V 15 pF TA 25 PARAMETER TEST CONDITIONS MIN UNIT t Propagation delay time low to high level output 21 35 ns eo 4 i Vip 1 5Vto1 5V See Figure 6 tprHL Propagation delay time high to low level output tp7H Output enable time to high level See Figure 7 tpz X Output enable time to low level tpHz Output disable time from high level See Figure 7 tp 7 Output disable time from low level 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1
222. io de un electroim n acciona uno o varios contactos que permiten abrir O cerrar otros circuitos el ctricos independientes Luego de hacer un an lisis en el mercado peruano revisando precios y disponibilidad el componente seleccionado fue el rele HK19F de la compania HUI KE que cumple con lo requerido pues trabaja con valores de 5VDC y consume aproximadamente 200mA de corriente adem s maneja dos estados o Normalmente Abiertos NO por sus siglas en ingl s o Normalmente Cerrados NC Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP T UNIVERSIDAD DEL PERU IMAGEN GRAFICA Y ESQUEMATICA DEL ACTUADOR RELE DE 5VDC DE LA COMPANIA HUI KE Figura 3 24 Rel HK19F de 5VDC Las caracter sticas de este rel de baja potencia son e Tension de bobina 5VDC regulado e Corriente de conmutaci n 1A max 120VAC 30VDC e Consumo promedio de corriente 200mA e Dimensiones L 20 2x A 10 x H12 5 mm Dise o electr nico Vin 12VDC Vrele 5VDC 2 CON1 RELE 1N4001 ipee T Vrele 5VDC 1 1N4148 1N4148 1N4148 Vin 12VDC t CON TEMPUS CON2 RELE EL DISE O DE LA ETAPA DE EXPANSION ACTUADORES SE REALIZO TOMANDO LAS CONSIDERACIONES DEL MODULO AL QUE SE HALLA CONECTADO Y EL MODO DE EVITAR SOBRE CALENTAMIENTOS FUTUROS Figura 3 25 Esquema circuital de los actuadores Etapa de expansi n
223. ion should be used for outstanding performance over a wide dynamic range 1000 1 Calibration of the power offset is done at or close to the minimum current where the desired accuracy is required The ADE7758 has power offset registers for watts and VAR xWATTOS and xVAROS Offsets in the VA measurement are compensated by adjusting the rms offset registers see the Calibration of IRMS and VRMS Offset section Figure 79 shows the steps to calibrate the power offsets using the pulse outputs Rev C Page 46 of 72 ADE7 1758 ENABLE CF OUTPUTS CLEAR OFFSET REGISTERS xWATTOS xVAROS START ALL PHASES WATT OFFSET CALIBRATED YES SET UP APCF PULSE OUTPUT FOR PHASE A B ORC ALL PHASES VAR OFFSET CALIBRATED SET UP SYSTEM FOR Imin 1 SET VARCF PULSE OUTPUT FOR PHASE A B ORC MEASURE ERROR FOR APCF STEP 61 CALCULATE AND WRITE TO xWATTOS SELECT PHASE FOR LINE PERIOD MEASUREMENT CONFIGURE FREQ 11 0 FOR A LINE PERIOD MEASUREMENT STEP 7 REPEAT STEP 3 TO STEP 6 FOR xVAROS SET UP SYSTEM FOR Ivins PF 0 INDUCTIVE MEASURE ERROR FOR VARCF MEASURE PERIOD USING FREQ 11 0 REGISTER CALCULATE AND WRITE TO xVAROS 04443 079 Figure 79 Offset Calibration Using Pulse Output Step 1 Repeat Step 1 and Step 3 from the gain calibration to Step 4 Set the test system fo
224. is an 8 bit write only register The MSB determines whether the next data transfer operation is a read or a write The seven LSBs contain the address of the register to be accessed see Table 16 Figure 89 and Figure 90 show the data transfer sequences for a read and write operation respectively CS 7 COMMUNICATIONS REGISTER WRITE To ADDRESS _ DOUT MULTIBYTE READ DATA Figure 89 Reading Data from the 7758 via the Serial Interface 04443 089 cs yd _ ___ nnnnnnnnnnnnnnnn COMMUNICATIONS REGISTER WRITE 1 ADDRESS MULTIBYTE READ DATA Figure 90 Writing Data to the 7758 via the Serial Interface 04443 090 On completion of a data transfer read or write the ADE7758 once again enters into communications mode that is the next instruction followed must be a write to the communications register A data transfer is completed when the LSB of the ADE7758 register being addressed for a write or a read is transferred to or from the ADE7758 SERIAL WRITE OPERATION The serial write sequence takes place as follows With the ADE7758 in communications mode and the CS input logic low a write to the communications register takes place first The MSB of this byte transfer must be set to 1 indicating that the next data transfer operation is a write to the register The seven LSBs of this byte contain the address of the register to be written to The ADE7
225. ital se debe considerar un paso previo para muestrear y convertir a datos binarios los valores de las sefiales anal gicas de voltaje y corriente Y al igual que la l gica del c lculo RMS digital los instrumentos usan dos m todos el m todo te rico y el m todo del filtro pasa bajos Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU M todo te rico La definici n para el c lculo de la potencia activa se expresa de la siguiente manera activa E po VRMS x IRMS V us XL ps Vrus XI yug X cos 2 wt 0 Te ricamente la potencia activa ser la parte de la ecuaci n que no contiene componentes en frecuencia es decir la parte DC del producto entre corriente y voltaje M todo del filtro pasa bajos Este resulta el m todo m s pr ctico Para su demostraci n V t 42 Vays Sen wt Ecuaci n 2 1 i t Npa sen wt Ecuaci n 2 2 gt Por definici n te rica se multiplican ambas ecuaciones 2 1 y 2 2 P t v t i me ve dpe CONG Ecuacion 2 3 gt Graficado la ecuaci n 2 3 en funci n del tiempo Vans X RMS LA POTENCIA ACTIVA ES EL RESULTADO DEL PRODUCTO DE LAS SENALES DE VOLTAJE Y CORRIENTE RMS Figura 2 7 Gr fica de senales de la potencia activa Tesis publicada con autorizaci n del autor SOME RIGHTS RESE
226. ive power multiplier output At full scale input if the output from the multiplier is OxXCCCCD 838 861d then 1 LSB in the LPF2 output is equivalent to 0 0075 of measurement error at 60 dB down from full scale on the current channel At 60 dB down on full scale the input signal level is 1 1000 of full scale signal inputs the average word value from LPF2 is 838 861 838 861 1000 One LSB is equivalent to 1 838 861 16 x 100 0 0075 of the measured value The active power offset register has a correction resolution equal to 0 0075 at 60 dB Sign of Active Power Calculation Note that the average active power is a signed calculation If the phase difference between the current and voltage waveform is more than 90 the average power becomes negative Negative power indicates that energy is being placed back on the grid The ADE7758 has a sign detection circuitry for active power calculation ADE7758 The REVPAP bit Bit 17 in the interrupt status register is set if the average power from any one of the phases changes sign The phases monitored are selected by TERMSEL bits in the COMPMODE register see Table 21 The TERMSEL bits are also used to select which phases are included in the APCF and VARCF pulse outputs If the REVPAP bit is set in the mask register the IRQ logic output goes active low see the Interrupts section Note that this bit is set whenever there are sign changes that is the REVPAP bit is set for both a posit
227. ive to negative change or a negative to positive change of the sign bit The response time of this bit is approximately 176 ms for a full scale signal which has an average value of OxXCCCCD at the low pass filter output For smaller inputs the time is longer 225 x 17 Average Value CLKIN Response Time 160 ms The APCFNUM 15 13 indicate reverse power on each of the individual phases Bit 15 is set if the sign of the power on Phase A is negative Bit 14 for Phase B and Bit 13 for Phase C No Load Threshold The ADE7758 has an internal no load threshold on each phase The no load threshold can be activated by setting the NOLOAD bit Bit 7 ofthe COMPMODE register If the active power falls below 0 00596 of full scale input the energy is not accumulated in that phase As stated the average multiplier output with full scale input is OXCCCCD Therefore if the average multiplier output falls below 0x2A the power is not accumulated to avoid creep in the meter The no load threshold is implemented only on the active energy accumulation The reactive and apparent energies do not have the no load threshold option Active Energy Calculation As previously stated power is defined as the rate of energy flow This relationship can be expressed mathematically as Power dEnergy 18 dt Conversely Energy is given as the integral of power Energy t dt 19 Rev C Page 31 of 72 7758
228. justment allows the introduction of a phase lead of 0 104 The phase lead is achieved by introducing a time advance into VA A time advance of 4 8 us is made by writing 2 Ox7E to the time delay block APHCAL 6 0 thus reducing the amount of time delay by 4 8 us or equivalently 360 x 4 8 us x 60 Hz 0 104 at 60 Hz PHASE Degrees 04443 053 0 0 100 200 300 400 500 600 700 800 900 1k FREQUENCY Hz Figure 53 Phase Response of the HPF and Phase Compensation 10 Hz to 1 kHz PHASE Degrees 04443 054 40 45 50 55 60 65 70 FREQUENCY Hz Figure 54 Phase Response of the HPF and Phase Compensation 40 Hz to 70 Hz PHASE Degrees 04443 055 FREQUENCY Hz Figure 55 Phase Response of HPF and Phase Compensation 44 Hz to 56 Hz Rev C Page 24 of 72 RANGE OF PHASE CALIBRATION ADE7 1758 ACTIVE AND REACTIVE ENERGY CALCULATION 1 36 2 76 50Hz 0 022 0 043 1 63 3 31 60Hz 0 026 0 052 VA 4 8us IA 0 104 60Hz 4 Ox7E gt 60Hz je 04443 056 Figure 56 Phase Calibration on Voltage Channels VA APHCAL 6 0 o 153 6us TO 75 6us 20 1 H H gt 60Hz PERIOD MEASUREMENT The ADE7758 provides the period or frequency measurement of the line voltage The period is measured on the phase specified by Bit 0 to Bit 1 of the MMODE register The period register is an unsigned 12 bit FR
229. l phases by writing the value 0x38 to the LCYCMODE register 0x17 This sets all of the ZXSEL bits to Logic 1 Step 2 Set the interrupt mask register for zero crossing detection on all phases by writing OxE00 to the MASK 0 24 register 0x18 This sets all of the ZX bits to Logic 1 Step 3 Set up the calibration system for one of the two test conditions Iresr and Vnom and 1 lt 500 and Veuttscate 20 Step 4 Read the rms registers after the zero crossing interrupt and take an average of N samples This is recommended to get the most stable rms readings This procedure is detailed in Figure 84 Steps 4a through 4e Step 4a Choose the number of samples N to be averaged Step 4b Reset the interrupt status register by reading RSTATUS Ox1A Step 4c Wait for the zero crossing interrupt When the zero crossing interrupt occurs move to Step 44 Step 4d Read the xIRMS and xVRMS registers These values will be averaged in Step 4e Step Average the N samples of xIRMS and xVRMS The averaged values will be used in Step 5 Step 5 Write to the x VRMSOS 0x33 to 0x35 and xIRMSOS 0x36 to 0x38 registers according to the following equations XIRMSOS A uns ARMS pr 77 16384 CUN NET where Imm is the full scale current 500 Iresr is the test current IRMS mn and IRMSrssr are the current rms register values without offset correction for the inputs Imn and Iresr respectively xVRMS
230. l regulador LM7805 se coloc un juego de diodos que conectan a tierra con la sefial del microcontrolador y que lo deja trabajar s lo en el momento que l microcontrolador necesite que los rel s cambien a estado activo Mise 12VDC Atmega128 TEMPUS VI MODULO DE CONTROL LOGICA DE TRANSISTOR CON COLECTOR ABIERTO QUE CONTIENE EL TEMPUS VI Figura 3 27 Transistor en modo Colector abierto Como se observa en la Figura 3 27 los pines que env an la sefial desde el microcontrolador en el m dulo TEMPUS VI constan de un transistor en modo Colector Abierto el cual se satura cuando recibe un 1 l gico del microcontrolador y llega al corte cuando recibe un l gico dando de ese modo el paso de la energ a que se necesita para activar al rel al que se halle conectado e Enelrel los pines 1 16 4 13 6 11 y 8 9 fueron cortocircuitados pues si bien se conoce que cada rel de los elegidos posee 2 contactores se prefiri utilizarlos como uno solo pues se busca la mejor precisi n de contacto a trav s de un largo periodo de funcionamiento del equipo V ase Anexo E Diseno del sistema Secci n Diseno del sistema P g 16 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CATOLICA DEL PERU 3 6 CONECTORES Esta seccion contiene una breve descripcion de los conectores elegidos para el desarrollo del proy
231. l conditions The nominal VA rating of the supply in this design is 7 VA The total power dissi pation is approximately 0 5 W Together with the power dissipated in the shunt at 40 A load the total power con sumption of the meter is 1 06 W Figure 14 shows the basic power supply design AN 559 220V Figure 14 Power Supply The plots shown in Figures 15 16 17 and 18 show the PSU performance under heavy load 50 A with the line voltage varied from 180 V to 250 V By far the biggest load on the power supply is the current required to drive the stepper motor which has a coil impedance of about 400 This is clearly seen by looking at V1 voltage on C18 in the plots below Figure 16 shows the current drawn from the supply Refer to Figure 14 when review ing the simulation plots below C18 VOLTAGE DROP DUE TO STEPPER MOTOR DRIVE VOLTS 4 6 TIME s Figure 15 Power Supply Voltage Output at 220 V and 50 A Load 24 20 TIME s Figure 16 Power Supply Current Output at 220 V and 50 A Load VOLTS TIME 5 Figure 17 Power Supply Voltage Output at 180 V and 50 A Load 4 6 TIME s Figure 18 Power Supply Voltage Output at 250 V and 50 A Load DESIGN FOR IMMUNITY TO ELECTROMAGNETIC DISTURBANCE In Section 4 5 of IEC1036 it is stated that the meter shall be designed in such a way that conducted or radiated electromagnetic disturbances as well as electrostatic dis charge do not damage nor
232. l input current Vj 20 4 V 400 Vo 7V 250 2 5 no P Outputs enabled 35 50 upply current total package o loa pply idis Outputs disabled T All typical values are at Voc 5 V and TA 25 A Vopl and AlVoc the changes in magnitude of Vop and respectively that occur when the input is changed from a high level to a low level 9 In ANSI Standard EIA TIA 422 B Voc which is the average of the two output voltages with respect to GND is called output offset voltage Vos NOTE 3 This applies for both power on and off refer to ANSI Standard EIA TIA 422 B for exact conditions los Short circuit output current Vo Vcc switching characteristics Vcc 5 V TA 25 C PARAMETER TEST CONDITIONS MIN UNIT td OD _ Differential output delay time 40 60 RL 600 Differential output transition time 65 95 tPZH Output enable time to high level RL 1100 See Figure 4 R See Figure 3 L 55 tPZL Output enable time to low level 2110 6 See Figure 5 30 50 tPH7 Output disable time from high level RL 110 9 See Figure 4 85 tPLZ Output disable time from low level RL 1100 See Figure 5 435 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 RECEIVER SECTION electrical characteristics over recommended ranges of common mode input voltage supply voltage and operat
233. las respuestas de fase y magnitud del integrador digital son muy cercanas a lo ideal El beneficio adicional de la implementaci n digital es la mayor estabilidad durante los cambios en el tiempo y fen menos ambientales Esto es muy importante en las aplicaciones de medici n de energ a dadas las condiciones de operaci n hostiles durante la larga vida operacional del medidor Haciendo un an lisis de las tecnolog as para la medici n de corriente se presenta el siguiente cuadro comparativo Costo Muy Bajo Bajo Linealidad en el rango de la Muy Buena Muy Buena medici n Capacidad de medici n de alta monte Muy Pobre Muy Buena Consumo de Potencia Alto Bajo Problema de Saturaci n de Corriente DC Variaci n de la Salida con respecto a la Temperatura No Muy Bajo Problema Offset de DC Problema de saturaci n e hist resis No Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD CAT LICA DEL PERU TENESp Y 4 ET U gt u H 904 73 Vivid d04 13 SOMVSAIIIN SOINITYO S32NOIN3 507 YYZITW33 o a ON 4 SOLWO is HVZIIVNSIA WAILOWaY VIOS3N3 viuvinaTv2A H OOOLSW Nn ON ap osaug eqsar afeyon aiqos agog LHVINHNCTVT V EH3N3 EWAILDV WWW TW WALLOW v1
234. lerance for the antialias filters to reduce the pos sible problems due to phase mismatch Alternatively the corner frequency of the antialias filter could be pushed out to 10 kHz 15 Hz However the corner frequency should not be made too high as this could allow enough high frequency components to be aliased and so cause accuracy problems in a noisy environment 50Hz 0 481 LAE 9000 C ee 50Hz 0 594 i 1kQ C 33nF DEGREES 50Hz 0 718 R 1 1kO 36 3nF FREQUENCY Hz Figure 8 Phase Shift at 50 Hz Due to Component Tolerances AN 559 Note that this is also why precautions were taken with the design of the calibration network on Channel 2 volt age channel Calibrating the meter by varying the resistance of the attenuation network will not vary the 3 dB frequency and hence the phase response of the network on Channel 2 see Calibrating the Meter sec tion Shown in Figure 9 is a plot of phase lag at 50 Hz when the resistance of the calibration network is varied from 660 J1 J10 closed to 1 26 J1 J10 open 0 591 0 592 J1 J10 CLOSED 50Hz 0 59308 UY 0 593 a 0 594 J1 J10 OPEN 50Hz 0 59348 0 595 49 9 50 0 50 1 FREQUENCY Hz Figure 9 Phase Shift Due to Calibration COMPENSATING FOR PARASITIC SHUNT INDUCTANCE When used at low frequencies a shunt can be considered a purely resistive elemen
235. libre de descarga Sin embargo los limites de la version libre a comparacion de la version profesional solo radican en un mensaje de alerta que indica que el software es libre sin limitaci n de funciones o librer as para funciones complejas Es un entorno que ha sido desarrollado bas ndose en Visual Basic y Visual convirti ndose un lenguaje muy gr fico Finalmente se seleccion el entorno del por la comodidad de su c digo por su entorno tan visual que no difiere de las versiones de VISUAL BASIC adem s posee diversos ejemplos de programas en donde se pueden apreciar los c digos de programaci n que realiz la propia empresa Otra de las ventajas de este entorno de programaci n para PDAs es que permite crear instaladores en c digo nativo para PALMs casi todas las versiones existentes de SO que tiene PALM en el mercado Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP T UNIVERSIDAD DEL PERU Private Zub updateNavigator i if popViev ListIndex 0 then Classes cPrevious Visible2 not ucCalendarl Ccontroly EHD Modules cNext Visible not ucCalendarl Controlyear 53 User Controls elseif popView ListIndex 1 then i 53 Image Families cPrevious Visibleructalendari IsbateValid iu Es String Lists cNext Visibleruccalendari IsdateValid uecal ey Binary Resources End if E tg Packages End S
236. line cycles Data is read from the ADE7758 via the SPI serial interface The interrupt request output IRQ is an open drain active low logic output The IRQ output goes active low when one or more interrupt events have occurred in the ADE7758 A status register indicates the nature of the interrupt The ADE7758 is available in a 24 lead SOIC package Rev C Page 4 of 72 SPECIFICATIONS ADE7 1758 AVDD DVDD 5 V 5 AGND DGND 0 V on chip reference CLKIN 10 MHz XTAL Tmn to Tmax 40 C to 85 Specification Unit Test Conditions Comments Table 1 Parameter ACCURACY Active Energy Measurement Error per Phase Phase Error Between Channels PF 0 8 Capacitive PF 0 5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Active Energy Measurement Bandwidth IRMS Measurement Error IRMS Measurement Bandwidth VRMS Measurement Error VRMS Measurement Bandwidth ANALOG INPUTS Maximum Signal Levels Input Impedance DC ADC Offset Error Gain Error WAVEFORM SAMPLING Current Channels Signal to Noise Plus Distortion Bandwidth 3 dB Voltage Channels Signal to Noise Plus Distortion Bandwidth 3 dB REFERENCE INPUT Input Voltage Range Input Capacitance ON CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS DIN SC
237. los recursos de la sociedad en la que se halla inmersa Debido a la pluralidad de los recursos existentes las soluciones planteadas para afrontar una problem tica espec fica son diversas e innovadoras entre ellas En la actualidad a modo de preservar nuestro medio ambiente nos enfrentamos al hecho de controlar eficientemente la energ a el ctrica as como su correcto control en el sector industrial que asegurar una mejor producci n sin elevar costos Ambos enfoques generan una necesidad la medici n eficiente del consumo de energ a el ctrica Para dicho objetivo desde hace algunos se vienen realizando estudios utilizando diferentes tecnolog as para la determinaci n de los diversos par metros que contempla la energ a el ctrica Los desarrollos han ido evolucionando a la par con los avances Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU cient ficos de la poca logr ndose equipos vers tiles y eficientes desde los antiguos equipos medidores mec nicos que s lo sensaban la potencia activa hasta los equipos medidores digitales de hoy en d a que sensan una variedad de par metros el ctricos con una considerable exactitud siendo estos ltimos los m s costosos y eficientes Con el objetivo de mejorar el control de los sistemas de medici n nace una nueva tendencia q
238. low a threshold level This register is common to the three line voltage SAG detection The detection threshold is specified by the SAGLVL register see the Line Voltage SAG Detection section Ox1E SAGLVL SAG Voltage Level This register specifies the detection threshold for the SAG event This register is common to all three phases line voltage SAG detections See the description of the SAGCYC register for details Ox1F VPINTLVL Voltage Peak Level Interrupt Threshold Register This register sets the level of the voltage peak detection Bit 5 to Bit 7 of the MMODE register determine which phases are to be monitored If the selected voltage phase exceeds this level the PKV flag in the IRQ status register is set 0x20 IPINTLVL Current Peak Level Interrupt Threshold Register This register sets the level of the current peak detection Bit 5 to Bit 7 of the MMODE register determine which phases are to be monitored If the selected current phase exceeds this level the PKI flag in the IRQ status register is set 0x21 Voltage Peak Register This register contains the value of the peak voltage waveform that has occurred within a fixed number of half line cycles The number of half line cycles is set by the LINECYC register Rev C Page 61 of 72 7758 Address A6 A0 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 Ox2A Ox2B Ox2C Ox2D Ox2E Ox2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 Ox
239. ly processed see the Peak Current Detection section 5 to 7 PKIROSEL 7 These bits select the phases used for the peak interrupt detection Setting Bit 5 switches on the monitoring of the absolute current and voltage waveform to Phase A Similarly setting Bit 6 turns on the waveform detection for Phase B and Bit 7 for Phase C Note that more than one bit can be set for detection on multiple phases If the absolute values of the voltage or current waveform samples in the selected phases exceeds the preset level specified in the VPINTLVL or IPINTLVL registers the corresponding bit s in the STATUS registers are set see the Peak Current Detection section Rev C Page 64 of 72 ADE7 1758 WAVEFORM MODE REGISTER 0x15 The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register Table 20 summarizes the functionality of each bit in the WAVMODE register Table 20 WAVMODE Register Bit Bit Default Location Mnemonic Value Description 0 to 1 These bits are used to select the phase of the waveform sample PHSEL 1 0 Source 0 0 Phase A 0 1 Phase B 1 0 Phase 1 1 Reserved 2to4 WAVSEL These bits are used to select the type of waveform WAVSEL 2 0 Source 0 0 0 Current 0 0 1 Voltage 0 1 0 Active Power Multiplier Output 0 1 1 Reactive Power Multiplier Output 1 0 0 VA Multiplier Output Others Reserved 5to6 These bits are used to select the data rate DTRT 1 0 Update Rate 0 0 26 04 kSPS CLKIN 3 128 0
240. measure active reactive and Two pulse outputs one for active power and the other selectable between reactive and apparent power with M P contiguralions m programmable frequency WYE or DELTA services with both three and four wires The ADE7758 provides system calibration features for each phase Digital power phase and rms offset calibration that is rms offset correction phase calibration and power On chip user programmable thresholds for line voltage SAG and overvoltage detections calibration The APCF logic output gives active power An on chip digital integrator enables direct interface to information and the VARCF logic output provides instantaneous current sensors with di dt output reactive or apparent power information continued on Page 4 A PGA in the current channel allows direct interface to shunts and current transformers U S patents pending An SPI compatible serial interface with IRQ Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Reference 2 4 V drift 30 ppm C typical with external overdrive capability Single 5 V supply low power 70 mW typical FUNCTIONAL BLOCK DIAGRAM AVDD REFijiout AGND O Q POWER E ee kE e TEASE Pwer AIGAIN 11 0 M SHIFTING FILTER DFC VARCFDEN 11 0 ADE7758 PHASE B APHCAL 6 0 AWATTOS 11 0 ACTIVE REACTIVE APPARENT ENERGIES AND VOLTAGE CURRENT RMS CALCULAT
241. medici n de par metros el ctricos presentadas la alternativa adecuada a los requerimientos del sistema de control resulta ser la tecnolog a digital que permite la mejor adaptaci n entre m dulos y la capacidad necesaria para realizar el procesamiento matem tico Adem s es importante que el Equipo de medici n trif sica de par metros el ctricos comprende dos partes b sicas El Acondicionamiento de datos y el Sistema de control digital siendo esta ltima la m s importante por ser el n cleo del equipo Como se observa en la Figura 2 15 la uni n del Equipo de medici n trif sica con la Interfaz remota da origen a un Sistema mayor de medici n trif sica de par metros el ctricos conformando de esta manera un Punto de Medici n y control que tiene todo Sistema EEM v ase Capitulo 1 Secci n Medidores de par metros el ctricos P g 12 EQUIPO DE MEDICION TRIFASICA INTERFAZ REMOTA CON EL USUARIO PC REMOTA wm 1 EDS DEDATOS PDA IrDA OTRAS COMUNICACIONES Figura 2 15 Diagrama del sistema de medici n trif sica Tesis publicada con autorizacion del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Este proyecto de tesis busca desarrollar la parte m s importante del Equipo de medici n trif sica el Sistema de control digital el mismo que contendr toda la l gica de control para realizar
242. meter constant of 3200 imp kWh and a maximum current of 40 A the maximum frequency from CF is 7 82 Hz Many calibration benches used to verify meter accuracy still use optical techniques This limits the maximum frequency that can be reliably read to about 10 Hz The only remaining unknown from equation 1 is V2 or the signal level on Channel 2 the voltage channel From Equation 1 on the previous page 8 06 1 75 mV xV2x16x 3 4 Hz 2 5 V2 248 9 mV rms 0 030555 Hz Therefore in order to calibrate the meter the line volt age needs to be attenuated down to 248 9 mV CALIBRATING THE METER From the previous section it can be seen that the meter 15 simply calibrated by attenuating the line voltage down to 248 9 mV The line voltage attenuation is carried out by a simple resistor divider as shown in Figure 3 The attenuation network should allow a calibration range of at least 30 to allow for shunt tolerances and the on chip reference tolerance of 8 see AD7755 data sheet In addition the topology of the network is such that the phase matching between Channel 1 and Channel 2 is preserved even when the attenuation is being adjusted see Correct Phase Matching Between Channels section 248 9 J5 J4 3 287 ie 5 86 815 R16 gt gt R4 f_aqq 1 2 7 R4 C4 J2 3dB J1 220V v Figure 3 Attenuation Network As can be seen from Figure 3 the 3 dB frequency of this netw
243. metros el ctricos que pueda cubrir los requerimientos f sicos y el ctricos del sistema a desarrollar Como nuestro tipo de red el ctrica ser trif sica ser necesario el uso de un dispositivo que pueda sensar valores trif sicos en sus diversas configuraciones delta y estrella Y El equipo llegar a ser m s ptimo en cuanto permita sensar la mayor cantidad de par metros el ctricos de la red entre los cuales los que ocupan nuestro campo de inter s ser n Medici n de energ as Potencia activa reactiva y aparente medici n RMS de voltajes y corrientes Se espera que el mismo pueda ser reconfigurado y recalibrado para efectos de pruebas y o experimentaciones Considerando que este elemento pre procesador ser un dispositivo que actuar como Esclavo Slave por su nombre en ingl s de un controlador principal ser muy til que cuente con una interfaz de programaci n e intercambio de datos c moda y fiable esto con el objetivo de reducci n de pines en el Maestro Master por su nombre en ingl s Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU Seg n los modos de comunicaci n estudiados en el Capitulo 2 Secci n Tecnolog as para la interconexi n entre perif ricos P g 31 se elegir n dispositivos que cuenten con el protocolo de comunicaci n sincr nica SPI Co
244. mode signal is 25 mV as shown in Figure 37 V4 Va 500 IAP IBP DIFFERENTIAL INPUT OR ICP V4 V 500mV MAX PEAK 5 v4 o VcM COMMON MODE 25 MAX e VcM IAN IBN OR ICN Y 500mV 1 Figure 36 Maximum Signal Levels Current Channels Gain 1 The voltage channel has three single ended voltage inputs VAP VBP and VCP These single ended voltage inputs have a maximum input voltage of 0 5 V with respect to VN Both the current and voltage channel have a PGA with possible gain selections of 1 2 or 4 The same gain is applied to all the inputs of each channel Figure 37 shows the maximum signal levels on the voltage channel inputs The maximum common mode signal is 25 mV as shown in Figure 36 V2 500mV VAP VBP OR VCP O SINGLE ENDED INPUT 500mV MAX lt 2 Wy Vem V AGND VcM COMMON MODE 25mV 500mV 04443 037 Figure 37 Maximum Signal Levels Voltage Channels Gain 1 The gain selections are made by writing to the gain register Bit 0 to Bit 1 select the gain for the PGA in the fully differential current channel The gain selection for the PGA in the single ended voltage channel is made via Bit 5 to Bit 6 Figure 38 shows how a gain selection for the current channel is made using the gain register GAIN 7 0 GAIN K SELECTION IAP IBP ICP IAN IBN ICN 04443 038 Figure 38 PGA in Current C
245. mple rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register DTRT 1 0 The output sample rate can be 26 04 kSPS 13 02 kSPS 6 51 kSPS or 3 25 kSPS By setting the WFSM bit in the interrupt mask register to Logic 1 the interrupt request output IRQ goes active low when a sample is available The timing is shown in Figure 40 The 24 bit waveform samples are transferred from the ADE7758 one byte 8 bits at a time with the most significant byte shifted out first READ FROM WAVEFORM oe a AN DOUT 04443 040 CURRENT CHANNEL DATA 24 BITS Figure 40 Current Channel Waveform Sampling The interrupt request output IRQ stays low until the interrupt routine reads the reset status register see the Interrupts section CURRENT RMS IRMS GAIN 7 CALCULATION WAVEFORM SAMPLE DIGITAL REGISTER ACTIVE AND REACTIVE POWER CALCULATION CHANNEL 1 CURRENT WAVEFORM DATA RANGE AFTER INTEGRATOR 50 2 50 2 AND AIGAIN 11 0 0x000 0x34D1B8 VIN CHANNEL 1 0x000000 CURRENT WAVEFORM 0 5V GAIN COERENT 0 25V GAIN OxCB2E48 0 125V GAIN 0 2851 ov CHANNEL 1 CURRENT WAVEFORM 0x000000 60Hz _ RANGE AFTER INTEGRATOR 60Hz AND AIGAIN 11 0 0x000 OxD7AE14 0x2BE893 ANAL eu AE ORANG WORD RANGE RANGE 0x000000 1WHEN DIGITAL INTEGRATOR IS ENABLED FULL SCALE OUTPUT DATA IS ee ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A 20dB DECADE FREQUENCY RESPONSE WHEN DISABLED
246. mponente seleccionado De las companias fabricantes de estos dispositivos de medici n se ha elegido un integrado de la familia ADE de Analog Devices cuyo c digo es ADE7758 que cumple con los criterios de selecci n requeridos adem s de poseer caracter sticas adicionales como la de muestrear la sefial sensada es decir muestrear los valores de voltaje corriente potencia activa reactiva y aparente para que puedan ser graficados en funci n del tiempo medici n de la frecuencia de la se al de la red detector de sobre tensiones de la red indicador de desbalance de voltaje sensor de la temperatura del dispositivo as tambi n cumple con est ndares internacionales de la Comisi n Electrot cnica Internacional IEC por sus siglas en ingl s que son IEC 60687 IEC 61036 IEC 61268 IEC 62053 21 IEC 62053 22 y IEC 62053 23 V ase Anexo F Hojas t cnicas Hoja t cnica del ADE7758 Rev C Secci n Features P g 1 EE da m B LE I M ADE7758 ELKI ARW0433 511341 1 REFiwouT Figura 3 2 Pre procesador ADE7758 Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis UNIVERSIDAD DEL PERU Como dispositivo el ADE7758 posee interfaz serial de cuatro hilos compatible con SPI que permite la comunicaci n entre microcontroladores Sensor de temperatura incorporado Disponibili
247. n ADE7758 Note that the number of half line cycles is based on counting the zero crossing of the voltage channel The ZXSEL 2 0 bits in the LCYCMODE register determine which voltage channels are used for the zero crossing detection The same signal is also used for line cycle energy accumulation mode if activated see the Line Cycle Accumulation Mode Register 0x17 section OVERCURRENT DETECTION INTERRUPT Figure 48 illustrates the behavior of the overcurrent detection CURRENT PEAK WAVEFORM BEING MONITORED SELECTED BY PKIRQSEL 2 0 IN MMODE REGISTER ema OW T PKI RESET LOW WHEN RSTATUS REGISTER IS READ PKI INTERRUPT FLAG BIT 15 OF STATUS REGISTER READ RSTATUS REGISTER gt gt a e m m m M mum omm mm TA m ae gt A nm gt A e 04443 048 Figure 48 ADE7758 Overcurrent Detection Note that the content of the IPINTLVL 7 0 register is equivalent to Bit 14 to Bit 21 of the current waveform sample Therefore setting this register to 0 1 represents putting peak detection at full scale analog input Figure 48 shows a current exceeding a threshold The overcurrent event is recorded by setting the PKI flag Bit 15 in the interrupt status register If the PKI enable bit is set to Logic
248. n el medidor de Shallenberger creando un peque o ligero 12 libras y econ mico medidor conocido como Tipo redondo siendo tan popular como el Thomson lo fuese a os antes 1897 General Electric introduce al mercado su primer medidor de inducci n el Thomson Induction Wattmeter Este medidor utilizaba un rotor para el elemento conductor y un disco separado para el freno e 1899 GE introduce al mercado su primera tentativa de un medidor polif sico conocido como Thomson Polyphase Wattmeter Al mismo tiempo Paul McGahan un ingeniero de Westinghouse diseha un medidor polif sico que integraba el uso de dos medidores monof sicos Este ultimo diseno fue adoptado todos los fabricantes y construido en varias formas hasta 1969 1899 GE crea un nuevo concepto el medidor prepago con su nueva versi n del vat metro de Thomson e 1903 GE presenta el medidor Tipo para AC primer producido en serie y que a su vez fue considerado como el primer medidor moderno Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e 1904 Sangamo Electric Company desarrolla una nueva l nea basada en amper metros con n cleo de mercurio ampliamente desarrollados en Inglaterra en esos tiempos No eran tan exactos como los de tipo de inducci n pero f cilmente pod an ser
249. n el tema del control de la energ a la Planta ser n nuestros sectores de consumo energ tico a nivel mundial y el Sensor ser n los dispositivos tales que nos permitan cuantificar dicho consumo de energ a el ctrica en todas sus variables esto hace surgir la necesidad de contar con medidores eficientes para que el sistema tambi n pueda ser eficiente dichos medidores son los denominados medidores de energ a Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 1 1 2 EL CONTROL DE LA ENERG A EL CTRICA A NIVEL INDUSTRIAL El uso de la energ a el ctrica en el sector de consumo se divide segun el siguiente esquema FUENTE FIDE ENERGIA ELECTRICA 100 INDUSTRIAL DOMESTICO COMERCIAL Y SERV MUNICIPAL AGRICOLA 61 23 T 4 5 4 3 36 Hada a mv evo a 10 MEM ILUMINACION MOTORES REFRIGERACION AIRE ACONDICIONADO 16 15 15 8 DE LOS SECTORES DE CONSUMO EL SECTOR INDUSTRIAL HACE EL MAYOR USO DE LA ENERGIA ELECTRICA PRODUCIDA 61 Y DE LOS EQUIPOS CONECTADOS LOS MOTORES SON LOS DE MAYOR CONSUMO 45 Figura 1 4 Diagrama de distribuci n el ctrica en el sector de consumo observa que el sector industrial es el que hace mayor uso de la energ a el ctrica producida este a su vez es uno de los sectores m s competitivos y con alto grado tecnol gico entre los considerados
250. n embargo la lectura de la corriente es un problema bastante m s complejo de resolver No solamente el sensor de corriente exige un rango de medici n mucho mayor sino que ste tambi n necesita manipular un rango de frecuencias mucho m s amplio dado el rico contenido de arm nicas en la onda de corriente A SHUNT DE CORRIENTE DE BAJA RESISTENCIA El modelo de sta tecnolog a es el de una resistencia es la soluci n de m s bajo costo actualmente disponible y ofrece una lectura sencilla con excelente precisi n Cuando se est n practicando mediciones de corriente de alta precisi n se debe tener en cuenta la inductancia par sita del Shunt y aunque sta afecta la magnitud de la impedancia a frecuencias relativamente altas su efecto sobre la fase a las frecuencias de la l nea es suficiente para causar un error notable a bajo factor de potencia Un desfase de 0 1 llevar a un error de 0 3 aprox a un factor de potencia de 0 5 El bajo costo y la alta confiabilidad hacen del Shunt de corriente de baja resistencia una soluci n popular para la medici n de corriente Sin embargo dado que el Shunt es fundamentalmente un elemento resistivo la p rdida de potencia es proporcional al cuadrado de la corriente que pasa por la resistencia y consecuentemente es inusual entre los medidores de energ a de alta corriente Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis
251. na calibraci n casi lineal El shunt magn tico que altera la intensidad del campo se emplea para la calibraci n e Instrumentos electrodinamome tricos ESCALA CALIBRADA LINEAS DE MEDICION FUENTE DE ALIMENTACION INSTRUMENTO DE MAGNETO PERMANENTE Y BOBINA MOVIL USUALMENTE LLAMADO INSTRUMENTO DE SISTEMA D ARSONVAL Figura 2 2 Mecanismo b sico de un instrumento dinamom trico Un instrumento dinamom trico es muy similar al sistema D Arsonval pero en lugar de utilizar un im n permanente posee una bobina m vil que gira en el campo establecido por la corriente de una bobina de campo que la rodea tal y como se observa en la Figura 2 2 La escala de estos dispositivos tiene una relaci n cuadr tica el momento Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU de torsi n es proporcional al producto de los amperes vuelta de la bobina m vil y los amperes vuelta de la bobina de campo La conexi n de las bobinas de campo y de la bobina m vil en serie brinda la respuesta en t rminos del cuadrado de la corriente haciendo del dinam metro un instrumento de lectura RMS para corriente o voltaje e Instrumentos de hierro m vil Este tipo de instrumentos se emplean ampliamente a frecuencias de la red Operan por medio de la corriente en la bobina que rodea dos aletas magn ticas una fija y
252. nd xVAROS 0x3C to 0x3E Offsets in the measurement are compensated by adjusting the rms offset registers see the Calibration of IRMS and VRMS Offset section More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration For example if a current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles one LSB variation in this reading represents an 0 896 error This measurement does not provide enough resolution to calibrate out a 196 offset error However if the active energy is accumulated over 37 500 half line cycles one LSB variation results in 0 0596 error reducing the quantization error Figure 83 shows the steps to calibrate the power offsets using the line accumulation mode Step 1 If the values change after gain calibration Step 1 Step 3 and Step 4 from the gain calibration should be repeated to configure the LCYCMODE LINECYC and MASK registers Select Phase A Phase or Phase for a line period measure ment with the FREQSEL 1 0 bits in the MMODE register 0x14 For example clearing Bit 1 and Bit 0 selects Phase A for line period measurement Step 2 Set the test system for Ium Vnom and unity power factor Step 3 Reset the interrupt status register by reading RSTATUS Ox1A Step 4 Read all xWATTHR energy registers 0x01 to 0x03 after the LENERGY interrupt and store the values Step 4a If it is not
253. ne receiver both of which operate from a single 5 V power supply The driver and receiver have active high and active low enables respectively that can be externally connected together to function as a direction control The driver differential outputs and the receiver differential inputs are connected internally to form differential input output bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or 0 These ports feature wide positive and negative common mode voltage ranges making the device suitable for party line applications The driver is designed to handle loads up to 60 mA of sink or source current The driver features positive and negative current limiting and thermal shutdown for protection from line fault conditions Thermal shutdown is designed to occur at a junction temperature of approximately 150 C The receiver features a minimum input impedance of 12 an input sensitivity of 200 mV and a typical input hysteresis of 50 mV The SN75176A can be used in transmission line applications employing the SN75172 and SN751 74 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers The SN75176A is characterized for operation from 0 C to 70 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at
254. nectores de los m dulo de control y del sistema que se interconectan entre si MODULO DE CONTROL MODULO DE CONTROL 1 Conector serial 1 2 Conector serial 2 3 interno 4 Alimentaci n interno 5 SPI interno MODULO DEL SISTEMA 1 TCP IP 2 Serial 3 Actuadores 4 SPI 5 Plug 6 RJ 459 T RJ 11 8 Actuadores 9 Pre procesamiento Mini MODULO DEL SISTEMA PARA LA COMUNICACION ENTRE LOS MODULOS INTERNOS DEL SISTEMA SE COLOCARON CONECTORES INTERNOS DE DIVERSOS TIPOS Figura 3 34 Distribuci n de los conectores internos e El conector SPI es un molex de 6 pines que se encarga de recibir la se al SPI desde la tarjeta TEMPUS VI para distribuirla hacia el pre procesador ADE7758 N tese que de los 6 pines s lo se da uso a 5 de ellos no se eligi usar un molex de 9 pines por su escasa disponibilidad en el mercado peruano y como se necesitaban caracter sticas comerciales un molex de 6 pines result m s viable que uno de 5 pines Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis gt PONTIFICIA TESIS PUCP CATOLICA DEL PERU MODULO DEL SISTEMA MODULO DE CONTROL m o Atmega128 LA COMUNICACION ENTRE EL ADE7758 Y EL MICROCONTROLADOR SE REALIZA POR MEDIO DE LA LOGICA SPI SERIAL PERIPHERAL INTERFACE POR SU NOMBRE EN INGLES Figura 3 35 Conector SPI interno e El conector denominado ACTUADORES es un molex que
255. nel for each phase The current waveform can be changed by 50 by writing a twos complement number to the 12 bit signed current waveform gain registers AIGAIN 11 0 BIGAIN 11 0 and CIGAIN 11 0 For example if 0x7FF is written to those registers the ADC output is scaled up by 50 To scale the input by 50 write 0x800 to the registers Equation 2 describes mathematically the function of the current waveform 2 Changing the content of AIGAIN 11 0 BIGAIN 11 0 or CIGAIN 11 0 affects all calculations based on its current that is it affects the phases active reactive apparent energy as well as gain registers Current Waveform Content of Current Gain Register ADC Output x 515 GAIN 4 3 2 42V 1 21V 0 6V GAIN 1 0 REFERENCE AIGAIN 11 0 IAP x1 x2 x4 O ex lt ac OS O IAN INTEGRATOR ADE7758 its current rms calculation In addition waveform samples are also scaled accordingly IGAIN should not be used when using Mode 0 of CONSEL COMPMODE 1 0 Current Channel Sampling The waveform samples of the current channel can be routed to the WFORM register at fixed sampling rates by setting the WAVSEL 2 0 bit in the WAVMODE register to 000 binary see Table 20 The phase in which the samples are routed is set by setting the PHSEL 1 0 bits in the WAVMODE register Energy calculation remains uninterrupted during waveform sampling When in waveform sample mode one of four output sa
256. nergy Management por sus siglas en ingl s El sistema EEM es una colecci n de software en red medidores de par metros el ctricos inteligentes y dispositivos de control Un grupo de medidores son localizados en puntos clave dentro de las fuentes de energ a para el consumidor tales como subestaciones equipos cargas etc v ase Figura 1 5 Su conexi n es sobre toda una red de comunicaciones la cual puede incluir Internet g reles tel fono entre otros Sobre esta red los medidores intercambian informaci n en tiempo real el software autom ticamente se actualiza y con la informaci n hist rica de consumo la env a a una o m s centrales para su proceso Planta de energ a Planta de energia Consumidor een comercial Operador regional entre P Generador E Consumidor comercial Gene rador FE de In situ transmisi n Subestaci n de distribuci n Consumidor industrial M Punto de medici n y control FUENTE Power Measurement LOS NUEVOS SISTEMAS DE MEDICION DE ENERGIA SE CONFORMAN POR UNA SERIE DE MEDIDORES INTELIGENTES QUE INTERACTUAN EN TIEMPO REAL A TRAVES DE UNA RED DE COMUNICACIONES Figura 1 5 Medidores en un sistema EEM Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA m TESIS PUCP UNIVERSIDAD DEL PERU 1 3 OBJETIVOS 1 3 1 OBJETIVO GENERAL Desarrollar un sistema de contr
257. nsmisi n y Control y Protocolo de Internet o TCP e IP por sus siglas en ingl s respectivamente Su aplicaci n es la de enlazar computadoras que utilizan diferentes sistemas operativos incluyendo PC minicomputadoras y computadoras centrales sobre redes de rea local y rea extensa Transformada de Hilbert Definici n utilizada en matem ticas y en procesamiento de se ales la transformada de Hilbert H es una herramienta til para describir la envolvente compleja de una serial modulada por una portadora real Su definici n es fa mmm LN p oe ey Aa Donde h t La transformada de Hilbert produce el efecto de desplazar la componente de frecuencias negativas de s t en 90 y las parte de frecuencias positivas en 90 Es el concepto teorico base para el calculo de potencia reactiva Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Firmware El Firmware es un bloque de instrucciones de programa usualmente grabado en un microcontrolador cuya funci n es establecer la l gica de m s bajo nivel que controla los circuitos electr nicos de un dispositivo de cualquier tipo Al estar integrado en la electr nica del dispositivo es en parte hardware pero tambi n es software ya que proporciona l gica y se dispone en alg n tipo de lenguaje de programaci n Funcionalmente
258. nsumo el ctrico per c pita los pa ses de la regi n y Estados Unidos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Estos datos y resultados dan pie a examinar detalladamente los pasos de control que se realiza para maximizar la eficiencia del consumo de la energ a el ctrica Todo sistema de control consta de 3 etapas o partes b sicas El actuador la planta y el sensor los cuales se comunican como se observa en la Figura 1 3 ENTRADA DE REFERENCIA SALIDA ACTUADOR EN LOS SISTEMAS DE CONTROL REALIMENTADOS Y SU CICLO CONTINUO LA ETAPA CLAVE ES EL SENSADO QUE MIDE LA SENAL EN LA SALIDA DE LA PLANTA Y LUEGO LA REALIMENTA AL ACTUADOR QUE LA CONTROLA Figura 1 3 Diagrama de bloques de un sistema de control b sico Un Actuador que ser el encargado de contener la l gica de control para el manejo eficiente la Planta que es la etapa a controlar y que a su vez ser receptora de las acciones elegidas por el actuador y la etapa pero no menos importante el Sensor cuyo objetivo ser el de medir el desempeno de la Planta ante las acciones determinadas por el Actuador para luego realimentar al sistema y de ese modo el proceso de control continue su normal desarrollo En el caso que nos ocupa el Actuador ser el contenedor de las decisiones y l gicas tomadas por los especialistas e
259. nt the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR When the MCU interrupt flag is cleared a read from the reset interrupt status register with reset is carried out This causes the IRQ line to be reset logic high t see the Interrupt Timing section The reset interrupt status register contents are used to determine the source of the interrupt s and hence the appropriate action to be taken If a subsequent interrupt event occurs during the ISR ts that event is recorded by the MCU external interrupt flag being set again On returning from the ISR the global interrupt mask bit is cleared same instruction cycle and the external interrupt flag uses the MCU to jump to its ISR once again This ensures that the MCU does not miss any external interrupts The reset bit in the status register is an exception to this and is only high for one clock cycle after a reset event INTERRUPT TIMING The Serial Interface section should be reviewed before reviewing this section As previously described when the IRQ output goes low the MCU ISR must read the interrupt status register to determine the source of the interrupt When reading the interrupt status register contents the IRQ output is set high on the last falling edge of SCLK of the first byte transfer read interrupt status register command The IRQ output is held high until the last bit of the next 8 bit transfer is shifted out in
260. ntialias Filter From Figure 21 it can be seen that the ferrite material becomes predominately resistive at high frequencies Note also that the impedance of the ferrite material _10 increases with frequency causing only high RF fre quencies to be attenuated Isolation The shunt connection is the only location where the AD7755 is connected directly via antialias filters to the outside world The system is also connected to the phase and neutral lines for the purpose of generating a power supply and voltage channel signal V2 The ferrite bead Z1 and line filter capacitor C16 should signifi cantly reduce any RF radiation on the power supply Another possible path for RF is the signal ground for the system A moating technique has been used to help iso late the signal ground surrounding the AD7755 from the external ground reference point K4 Figure 22 illus trates the principle of this technique called partitioning or moating MOAT NO POWER OR GROUND PLANE CONNECTION NE LOS SS Figure 22 High Frequency Isolation of I O Connections Using a Moat POWER CONNECTION MADE USING FERRITE BEAD ON LEAD Sensitive regions of the system are protected from RF radiation entering the system at the I O connection An area surrounding the I O connection does not have any ground or power planes This limits the conduction paths for RF radiation and is called a moat Obviously power ground
261. o Esclavo1 SPI SPI Maestro Esclavo eet SPI Mso Esclavo2 55 SPI PUNTO PUNTO MISO Esclavo3 55 EL ESTANDAR SPI USA COMUNICACION SERIAL SINCRONIZADA Y EL MODO DE CONTROL MAESTRO ESCLAVO Figura 2 14 Protocolo SPI 2 3 3 La comunicaci n de Circuitos Inter Integrados I C por sus siglas en ingl s fue desarrollada y patentada por Philips El s lo usa dos hilos para transmitir la informaci n uno para los datos y otro para la se al de sincronizaci n Tambi n es necesaria una tercera l nea la referencia Se les denomina multimaestros pues no necesariamente el maestro debe ser el mismo dispositivo 2 3 4 1 WIRE Protocolo disenado por Dallas Semiconductor provee datos a baja velocidad senales y alimentaci n sobre una nica l nea una l nea de tierra tambi n es necesaria Su C 2 i i T concepto es similar al del I C pero con menores velocidades de comunicaci n y a un costo m s bajo Pero complejo de implementar Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 2 4 CONCEPTUALIZACIONES GENERALES TCP IP Es un protocolo DARPA siglas en ingl s de la Agencia de Investigaci n de Defensa de Proyectos Avanzados que proporciona transmisi n fiable de paquetes de datos sobre redes recibe el nombre por la uni n de dos definiciones Protocolo de Tra
262. o Pila de Litio o Reloj en tiempo real RTC Real Time Clock o Memoria flash externa de 1MB e Conector IDC de 2x20 para o LCD de 16x2 o Teclado matricial de 4x4 4 LEDs de control e Reloj del sistema Cristal de 16Mhz e Consumo m ximo de corriente 100 mA e Temperatura de trabajo 5 70 C Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis 3 PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU ue h Pi Lx a 0 ke A ha P uL vans ra DN d oa 7 Y 2 pr Fii ANTERIOR POSTERIOR ESTA ETAPA SE HALLA GOBERNADA POR LA TARJETA CONTROL Y COMUNICACION TEMPUS VI LA CUAL MUESTRA SER LO SUFICIENTEMENTE VERSATIL PARA ADECUARLA AL PROYECTO DE TESIS Figura 3 16 Vista anterior y posterior del m dulo de control Microcontrolador Conector de ATmega128 TQFP alimentaci n Conector IDC 2x20 Conector TCP IP Conector SPI Buzzer Conector SPI Pila de litio Conector Serial 1 Conector Serial 2 00000 o El TEMPUS VI posee como coraz n un microcontrolador de la familia AVR de ATMEL el ATmega128 en empaquetado TQFP e Frecuencia 1 16 MHz e Pines I O m ximo 53 pines Canales PWM 1 8 canales e Canales ADC 8 canales de 10 bits e Temporizadores 2 temporizadores de 16 bits Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados
263. o cnice mecd es jhem0027 fdp fdp htm Consultado 28 Oct 2005 15 CRISTOPHER E STRANGIO 2005 The RS 232 standard CAMI Research Inc Lexington Massachusett USA http www camiresearch com Data Com Basics RS232 standard html 16 THE MATHWORKS ACCELERATING THE PACE OF ENGINEERING AND SCIENCE 2005 Serial Port Interface Standard The MathWorks Inc USA http www mathworks com access helpdesk help toolbox instrument Consultado 28 Oct 2005 17 CISCO SYSTEMS INC 2005 Ethernet Technologies documentation http www cisco com univercd cc td doc cisintwk ito doc ethernet htm Consultado 28 Oct 2005 18 PROCOBRE Confiabilidad de Sistemas El ctricos http www procobreperu org c confiabelec pdf Consultado 30 Oct 2005 19 VIERA DE CARVALHO ARNALDO POVEDA MANUEL ZAK JUAN 1996 OLADE Diseno de Programas de Eficiencia energ tica Revista Energ tica N 3 Septiembre Diciembre 1996 Pag 6 y 7 20 HANDHELD BASIC HB The best development enviroment for Palm Powered handhelds http www handheld basic com Consultado 06 Jul 2006 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU 21 PALM ONE Welcome to palm http www palm com Consultado 06 Jul 2006 22 TEMPUS Tempus http www tempus com pe Consultado 06 Jul 2006 23 INFARED DATA ASSOC
264. o la misma senal DC a los cuales se les ha agregado unos filtros para minimizar el ruido de la fuente e Todos los pines de alimentaci n deben tener un condensador de 100nF y 10uF con referencia a tierra que act en como filtros El condensador se debe colocar lo m s cerca posible a estos dos pines del integrado alimentaci n y tierra para evitar introducir ruido de fuente motivo por el cual en la Figura 3 2 el ADE7758 posee los pines de alimentaci n DVDD y tierra digital seguidos uno de otro e El pin 12 REFiyour que hace referencia la se al para conversi n ADC es inhabilitado pues se utilizan las senales de referencia interna de 2 42V Anexo Hojas t cnicas Hoja t cnica del ADE7758 Rev C Secci n Reference circuit P g 27 e Los pines de corriente IAP IAN IBP IBN ICP ICN y voltaje VAP VBP VCP VN se dirigen hacia su respectivo conector mediante el filtro RC dise ado Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Un detalle importante es que para la comunicaci n SPI los pines DOUT DIN y SCLK pines 24 22 y 23 respectivamente deben contar con un resistor de 1KO para evitar conflictos con la programaci n del microcontrolador quien usa los mismos pines SPI para programarse Anexo F Hojas t cnicas Hoja t cnica del ATmega128 Rev C S
265. o this signed 7 bit register see the Phase Compensation section Phase B Phase Calibration Register Phase C Phase Calibration Register Active Energy Register Divider Reactive Energy Register Divider Apparent Energy Register Divider Rev C Page 62 of 72 ADE7 1758 Address Default A6 A0 R W od pe us Description 0x45 APCFNUM Active Power CF Scaling Numerator Register The content of this register is used in the numerator of the APCF output scaling calculation Bits 15 13 indicate reverse polarity active power measurement for Phase A Phase B and Phase C in order that is Bit 15 is Phase A Bit 14 is Phase B and so on 0x46 APCFDEN Active Power CF Scaling Denominator Register The content of this register is used in the denominator of the APCF output scaling 0x47 VARCFNUM Reactive Power CF Scaling Numerator Register The content of this register is used in the numerator of the VARCF output scaling Bits 15 13 indicate reverse polarity reactive power measurement for Phase A Phase B and Phase C in order that is Bit 15 is Phase A Bit 14 is Phase B and so on 0x48 VARCFDEN Reactive Power CF Scaling Denominator Register The content of this register is used in the denominator of the VARCF output scaling Ox49to RESERVED Reserved Ox7D Ox7E CHKSUM Checksum Register The content of this register represents the sum of all the ones in the last register read from the SPI port Ox7F VERSION Version of the Die
266. o y base 3 34 Distribuci n de los conectores internos 3 35 Conector SPI interno 3 36 Conector ACTUADORES interno 3 37 Conector SERIAL interno 3 38 Conector TCP IP interno 3 39 Disefio del chasis del equipo 3 40 Vista frontal y posterior en dise o 3 41 Vista superior frontal y posterior del chasis 3 42 Diagrama de bloques de las tarjetas del sistema 3 43 Implementaci n f sica del proyecto de tesis 3 44 Implementaci n f sica del proyecto de tesis CAP TULO 4 Figura Figura Figura Figura Figura Figura Figura 4 1 M dulo del sistema 4 2 Winsock Programa para comunicaci n con el TEMPUS 4 3 Winsock modificado para lectura de registros del ADE7758 4 4 Comparaci n en los costos de los equipos 4 5 Pruebas del prototipo 4 6 Pruebas del prototipo 4 7 Pruebas del prototipo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA UNIVERSIDAD y CAT LICA DEL PERU PONTIFICIA TESIS UNIVERSIDAD DEL PERU INTRODUCCI N El desarrollo tecnol gico al igual que toda rea de actividad humana ha buscado satisfacer las necesidades ya sean individuales o colectivas de los miembros de su comunidad Particularmente la tecnolog a en su finalidad de soluci n ha dado cabida al desarrollo de nuevos sistemas empleando para dicho fin
267. oducida por persona en el Per 3 Figura 1 3 Diagrama de bloques de un sistema de control b sico 5 Figura 1 4 Diagrama de distribuci n el ctrica en el sector de CONSUMO _ 6 Figura 1 5 Medidores en un sistema EEM 0 ccc cece cence cece eee eee Imm mnn 12 CAPITULO 2 Figura 2 1 Mecanismo b sico de un medidor con magneto permanente y bobina movil 16 Figura 2 2 Mecanismo b sico de un instrumento dinamome trico 17 Figura 2 3 Mecanismo b sico de un medidor de hierro m vil 18 Figura 2 4 Diagrama b sico de un medidor digital 19 Figura 2 5 Medidor de potencia activa anal gica 22 Figura 2 6 Diagrama equivalente del medidor de potencia activa 23 Figura 2 7 Gr fica de se ales de la potencia activa 24 Figura 2 8 Diagrama equivalente del m todo del retardo de tiempo 26 Figura 2 9 Conexi n de un medidor del tipo monof sico 1 fase 1 neutro 28 Figura 2 10 Conexi n de un medidor del tipo trif sico 3 fases 29 Figura 2 11 Cone
268. of energy at low power factor CORRECT PHASE MATCHING BETWEEN CHANNELS The AD7755 is internally phase matched over the fre quency range 40 Hz to 1 kHz Correct phase matching is important in an energy metering application because any phase mismatch between channels will translate into significant measurement error at low power fac tor This is easily illustrated with the following example Figure 4 shows the voltage and current waveforms for an inductive load In the example shown the current lags the voltage by 60 PF 0 5 Assuming pure sinu soidal conditions the power is easily calculated as V rms x rms x cos 60 If however a phase error e is introduced externally to the AD7755 e g in the antialias filters the error is cal culated as 5 6 60 5 6 x 100 2 See Note on Table Where is the phase angle between voltage and current and o is the external phase error With a phase error of 0 2 for example the error at PF 0 5 60 is calculated as 0 696 As this example demonstrates even a very small phase error will pro duce a large measurement error at low power factor INSTANTANEOUS REAL POWER SIGNAL INSTANTANEOUS PF 1 POWER SIGNAL CURRENT y VOLTAGEN N y N Y INSTANTANEOUS INSTANTANEOUS REAL 0 5 VOLTAGE POWER SIGNAL POWER SIGNAL V I COS 60 2 CURRENT Figure 4 Voltage and Current Inductive Loa
269. of the radiation will like ESD generally be cumu lative for electronic components The energy in an EFT pulse can be as high as 4 mJ and deliver 40 A into a 50 Q load see Figure 26 Therefore continued exposure to EFT due to inductive load switching etc may have impli cations for the long term reliability of components The best approach is to protect those parts of the system that could be sensitive to EFT The protection techniques described in the last section Electromagnetic HF Fields also apply equally well in the case of EFT The electronics should be isolated as much as possible from the source of the disturbance through PCB layout i e moating and filtering signal and power connections In addition a 10 nF capacitor C16 placed across the mains provides a low imped ance shunt for differential EFT pulses Stray inductance due to leads and PCB traces will mean that the MOV will not be very effective in attenuating the differential EFT pulse The MOV is very effective in attenuating high energy relatively long duration disturbances e g due to lighting strikes etc The MOV is discussed in the next section MOV Type S20K275 The MOV used in this design was of type S20K275 from Siemens An MOV is basically a voltage dependant resistor whose resistance decreases with increasing voltage They are typically connected in parallel with the REV A 11 device or circuit being protected During an overvoltage event t
270. ol digital que posea la l gica adecuada para la medici n trif sica de par metros el ctricos adem s de permitir la comunicaci n a redes de datos 1 3 2 OBJETIVOS ESPEC FICOS Desarrollar la etapa b sica de un equipo que contemple los principios de un sistema EEM fusionando el rea de potencia medici n de par metros el ctricos con el rea de las comunicaciones conexi n a redes de datos Estudiar las diversas tecnolog as para medici n de par metros el ctricos destacando el an lisis l gico y num rico matem tico que pueda ser implementado en sistemas electr nicos digitales Elaborar un equipo con capacidad de comunicaci n que le permita conexi n a una red local por medio del protocolo TCP IP Al ser un sistema que conformar la etapa principal y b sica de un sistema mayor se le disenara para adaptarse y expandirse respecto a necesidades futuras previo an lisis e investigaci n de las posibles aplicaciones Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Desarrollar un equipo con caracter sticas comerciales por lo cual se tomar n consideraciones Para el chasis Y Dimensiones Deben ser adecuadas para que se acondicione a los equipos o soportes ya existentes rack paneles tableros el ctricos etc Y Material Al trabajarse con energ a el ct
271. olador que env a la data mediante sus pines de comunicaci n TX y RX del puerto UART y que a la vez maneja un pin I O para diferenciar entre el env o y recepci n de datos seg n especificaci n de las tablas presentadas para la l gica de comunicaci n EL MONTAJE DE LA ETAPA DE EXPANSION CON LA COMUNICACION RS 485 SE HIZO EN DOBLE CAPA COLOCANDO EL INTEGRADO SN75176 EN LA CARA INTERIOR DE LA TARJETA Figura 3 23 Vista anterior y posterior de la comunicaci n RS 485 O Bus diferencial de 1 Conector serial UART datos SN75176 2 Conector de comunicaci n RS 485 Consideraciones de dise o e Los pines 2 RE y 3 DE est n cortocircuitados pues su funcionamiento es contrario el uno con el otro por la negaci n del pin 2 Cuando el microcontrolador env a un 1 l gico por su pin I O el SN75176 se encuentra en modo emisor transfiriendo toda data que le llega por el pin 1 R hacia sus pines Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis TENES py E PONTIFICIA m TESIS PUCP UNIVERSIDAD DEL PERU diferenciales A y cuando el microcontrolador env a un 0 l gico por el I O el SN75176 se encuentra en modo recepci n transfiriendo toda la informaci n que lega a sus pines diferenciales hacia el pin 4 D V ase las tablas l gicas presentadas del bus diferencial e Al estar dise ado f sicamente para la conversi n
272. om 23 Apr 2007 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty SN75176AD ACTIVE SOIC D 8 75 Green ROHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br SN75176ADE4 ACTIVE SOIC D 8 75 Green RoHS amp NIPDAU Level 1 260C UNLIM no Sb Br SN75176ADG4 ACTIVE SOIC D 8 75 Green ROHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br SN75176ADR ACTIVE SOIC D 8 2500 Green ROHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br SN75176ADRE4 ACTIVE SOIC D 8 2500 Green RoHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br SN75176ADRG4 ACTIVE SOIC D 8 2500 Green ROHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br SN75176AP ACTIVE PDIP P 8 50 Pb Free CU NIPDAU N A for Pkg Type ROHS SN75176APE4 ACTIVE PDIP P 8 50 Pb Free CU NIPDAU N A for Pkg Type ROHS U The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE 1 has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or
273. oncernientes a la medici n de par metros el ctricos Luego se presentar la tecnolog a del m dulo de control digital para analizar si es el adecuado a las presentadas para medici n cabe resaltar que el m dulo posee integrada la etapa de comunicaci n a redes de datos con lo cual se cubre una de las caracter sticas del proyecto Finalmente para la comunicaci n entre los m dulos del equipo se expondr n las tecnolog as de interconexi n entre perif ricos 2 1 TECNOLOG AS PARA LA MEDICI N DE PAR METROS EL CTRICOS La medici n de par metros el ctricos se efect a mediante medidores o contadores dicha medici n resulta de inter s para calcular la cantidad de energ a facturable a los consumidores y tambi n para conocer la cantidad de energ a a trav s de las redes de distribuci n que no son traducidas precisamente en trabajo util por falta de Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU compensaci n de cargas reactivas atr s la comercializaci n de la energ a el ctrica se efectuaba de manera muy simple porque se facturaba en funci n de la unidad de energ a vigente sin embargo con el permanente desarrollo industrial y la consecuente busqueda del abaratamiento de la producci n por parte de las f bricas se hizo necesaria la aplicaci n de tarifas m s complejas La com
274. or Vic uisu 0 v input voltage Vy _ D DEadRE V _ ma ias a High level output current lop Receiver O uA Driver _________ 60 Low level output current IOL Receiver 8 Operating free air temperature TA NOTE 2 Differential input output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted MIN TYPt MAX PARAMETER TEST CONDITIONS VIK Input clamp voltage l 18 mA 1 5 T VIH 2 V 0 8 V VOH High level output voltage 33 mA VIH S2 V VIL 0 8 V VOL Low level output voltage 33 mA Differential output voltage RL 100 0 See Figure 1 IVop2l Differential output voltage RL 54 0 See Figure 1 A Vop Change in magnitude of differential output voltage RL 54 Q or 100 Voc Common mode output voltage Seo Figure Change in magnitude of common mode output voltage t Output disabled lo Output current See Note 3 0 2 3 0 2 NH High level input current V 2 4 V 20 50 00 3 7 1 1 Vo 7V no no Po RIN Low leve
275. ores Barcelona Espana 4 KINNARD ISAAC F 1958 Medidas el ctricas y sus aplicaciones Ediciones T cnicas Marcombo S A Barcelona 5 KARSA B LA E 1967 Electrical measuring instruments and measurements Ed Akad miai Kiad amp Villamos m r m szerek s m r sek Budapest Hungary Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP 5 CAT LICA DEL PERU 6 Instituto Nacional de Defensa de la Competencia y de la Protecci n de la Propiedad Intelectual INDECOPI 2005 Servicio Nacional de Metrolog a Metrolog a y calibraci n http www indecopi gob pe nuestrosservicios metrologiaycalibracion Consultado 27 Oct 2005 7 EL PERUANO diario oficial 2001 Ministerio de energ a y minas Direcci n general de Electricidad C digo nacional de electricidad suministro 2001 Resoluci n Ministerial 366 2001 EM VME http www editoraperu com pe normas Pdfs cod nc Elec pdf Consultado 27 Oct 2005 8 Gobierno del Ley N 23560 Sistema Legal de Unidades de Medida del Peru SLUMP Promulgado 31 Dic 1982 Segun Decreto Supremo N 026 93 ITINCI Vigente hasta el presente 27 Oct 2005 9 METERING INTERNATIONAL 2002 Magazine archive Isue 1 Measuring reactive power in energy meters http www metering com archive 021 52 1 htm Consultado 28 Oct 2005 10
276. ork is determined by R4 and Even with all the jumpers closed the resistance of R15 330 and R16 330 is still much greater than R4 1 Hence vary ing the resistance of the resistor chain R5 to R14 will have little effect on the 3 dB frequency of the network The network shown in Figure 3 allows the line voltage to be attenuated and adjusted in the range 175 mV to 333 mV with a resolution of 10 bits or 154 uV This is achieved by using the binary weighted resistor chain R5 to R14 This will allow the meter to be accurately cali brated using a successive approximation technique Starting with J1 each jumper is closed in order of ascendance e g J1 J2 J3 etc If the calibration fre quency on CF i e 32 x 100 imp hr 0 9777 Hz is exceeded when any jumper is closed it should be opened again All jumpers are tested J10 being the last jumper Note jumper connections are made with 0 Q fixed resistors which are soldered into place This approach is preferred over the use of trim pots as the stability of the latter over time and environmental conditions is questionable Since the AD7755 transfer function is extremely linear a one point calibration Ib at unity power factor is all that is needed to calibrate the meter If the correct precau tions have been taken at the design stage no calibration will be necessary at low power factor PF 0 5 The next section discusses phase matching for correct calcu lation
277. ort Specific modifications necessary to meet the above requirement recommended by Integrity Design amp AX Test Services Inc are described therein 482 W 4 4 4 4 4 4 I Figure 46 Certificate 2 Susceptibility 22 REV A E3742 2 5 6 00 rev A 01017 PRINTED IN U S A SN75176A DIFFERENTIAL BUS TRANSCEIVER SLLS100A JUNE 1984 REVISED MAY 1995 o Bidirectional Transceiver D OR P PACKAGE Meets or Exceeds the Requirements of ANSI Standards EIA TIA 422 B and ITU Recommendation V 11 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments 3 State Driver and Receiver Outputs Individual Driver and Receiver Enables e Wide Positive and Negative Input Output Bus Voltage Ranges Driver Output Capability 60 mA Thermal Shutdown Protection Driver Positive and Negative Current Limiting Receiver Input Impedance 12 Min Receiver Input Sensitivity 200 mV Receiver Input Hysteresis 50 mV Typ Operates From Single 5 V Supply Low Power Requirements description The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bus transmission lines It is designed for balanced transmission lines and meets ANSI Standard EIA TIA 422 B and ITU Recommendation V 11 The SN75176A combines a 3 state differential line driver and a differential input li
278. os de consumo energ tico recopilados y asumimos el mismo ndice de crecimiento tendr amos que considerar unos 1300 KWh de consumo de energ a el ctrica para cada una de aquellas personas Esto nos da un valor ascendente a 13 7 mil millones de KWh extras que se requerir an producir para satisfacer la demanda de energ a el ctrica peruana los pr ximos 50 anos Una planta generadora mediana puede producir 1 000 KWs de poder Electric Power Monthly Marzo 2002 Si consideramos un funcionamiento al 8596 por todos los d as y las noches durante un ario esta podr producir 7 45 millones de KWh Dividiendo los 13 7 mil millones de kWh que necesitar a la poblaci n adicional entre 7 45 millones de KWh que una central el ctrica puede producir encontramos que se deber a construir unas 20 centrales el ctricas medianas en los pr ximos cincuenta para as abastecer a toda la poblaci n Si usamos las mismas fuentes productoras de energ a que alimentan a nuestras plantas generadoras actuales se producir un dano irreversible al ecosistema por el impacto directo sobre el ambiente adem s de producir gases de invernadero y emisiones de azufre si bien por un lado se busca reducir ambos nuestra propia demanda energ tica los ocasionar a Y segun el The World Bank Group World Development Indicators database Abril 2007 otros pa ses dentro de la regi n y Estados Unidos presentan consumos mayores al nuestro Tabla 1 2 Co
279. ovr pin is 2 42 V This is the reference voltage used for the ADCs in the ADE7758 However the current channels have three input range selections full scale is selectable among 0 5 V 0 25 V and 0 125 V This is achieved by dividing the reference internally by 1 and The reference value is used for the ADC in the current channels Note that the full scale selection is only available for the current inputs The REFmovr pin can be overdriven by an external source for example an external 2 5 V reference Note that the nominal reference value supplied to the ADC is now 2 5 V and not 2 42 V This has the effect of increasing the nominal analog input signal range by 2 5 2 42 x 10096 396 or from 0 5 V to 0 5165 V The voltage of the ADE7758 reference drifts slightly with temperature see the Specifications section for the temperature coefficient specification in ppm C The value of the temperature drift varies from part to part Because the reference is used for all ADCs any x drift in the reference results in a 2x deviation of the meter accuracy The reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter Alternatively the meter can be calibrated at multiple temperatures Rev C Page 27 of 72 7758 TEMPERATURE MEASUREMENT The ADE7758 also includes an on chip temperature sensor temperature measurement is made every 4 CLKI
280. p GEHE ile EEUU 56 Serial trace e 56 Serial Write ODGLAUON c teet Glas wt rem dora mad tie 57 Read 59 Accessing the On Chip Registers esses 59 oe 60 Communications Register 60 Operational Mode Register 0x13 64 Measurement Mode Register 0x14 64 Waveform Mode Register 0x15 sess 65 Computational Mode Register 0 16 66 Line Cycle Accumulation Mode Register 0x17 67 Interrupt Mask Register 0x18 sess 68 Interrupt Status Register 0x19 Reset Interrupt Status Reoister A nan 69 Outline Dinero tono p ep d 70 Ordering Guide sieut UEM 70 Rev C Page 2 of 72 REVISION HISTORY 7 06 Rev B to Rev C Updated se ertet tette toe ret tetro toc antreten Universal Changes to FIG Los osos OR ERE 1 Changes to Table Dana 6 Chanees to Tablas 9 Changes to Figure 34 and Figure 35 sess 17 Changes to Current Waveform Gain Registers Section and Current Channel Sampling Section 19 Changes to Voltage Channel Sampling Section 22 Changes to Zero Crossing Timeout Section 2
281. perature Soldering Vapor Phase 60 sec Infrared 15 sec ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features Rating 0 3Vto 7 V 0 3 V to 7 V 0 3 V to 0 3 V 6 V to 6 V 0 3 V to AVDD 0 3 V 0 3 V to DVDD 0 3 V 0 3 V to DVDD 0 3 V 40 C to 85 C 65 C to 150 150 C 88 mW 53 C W 215 C 220 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Ser Athe electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev C Page 8 of 72 ADE7 1758 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF 24 DOUT DGND 2 23 SCLK DVDD 22 DIN AVDD 4 cs IAP 5 ADE7758 CLKOUT IAN 6 TOP VIEW CLKIN Not to Scale IBP IRQ IBN 8 VARCF ICP 9 ICN VBP AGND VCP R
282. plejidad de las tarifaciones ha logrado consecuentemente que los equipos medidores tambi n sean m s complejos La tecnolog a de los medidores expondr y dividir por mecanismos indicadores por metodolog as de medici n y por aplicaci n 2 1 1 MECANISMOS INDICADORES e Instrumentos de magneto permanente y bobina m vil ESCALA CALIBRADA MOVIMIENTO D ARSONVAL LINEAS DE MEDICION SHUNT EXTERNO FUENTE DE CARGA ALIMENTACION INSTRUMENTO DE MAGNETO PERMANENTE Y BOBINA MOVIL USUALMENTE LLAMADO INSTRUMENTO DE SISTEMA D ARSONVAL Figura 2 1 Mecanismo b sico de un medidor con magneto permanente y bobina m vil La Figura 2 1 puede apreciarse un sistema m vil de este tipo usualmente llamado Instrumento d Arsonval Utiliza una bobina que termina en un par de resortes Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU antag nicos en espiral a trav s de los cuales circula la corriente a medir La bobina est dentro del campo magn tico casi homog neo que produce un im n permanente y se desplaza con un movimiento giratorio El ngulo de rotaci n es proporcional a la corriente que circula por la bobina Una aguja indica la posici n de ste sobre una escala calibrada en t rminos de corriente o voltaje Este mecanismo indicador s lo responde a la corriente continua y presenta u
283. ponent of the instantaneous power signal p t in Equation 14 that 15 VRMS x IRMS This is the relationship used to calculate the active power in the ADE7758 for each phase The instantaneous power signal p t is generated by multiplying the current and voltage signals in each phase The dc component of the instantaneous power signal in each phase A B and C is then extracted by LPF2 the low pass filter to obtain the average active power information on each phase Figure 64 shows this process The active power of each phase accumulates in the corresponding 16 bit watt hour register AWATTHR BWATTHR or CWATTHR The input to each active energy register can be changed depending on the accumulation mode setting see Table 22 INSTANTANEOUS POWER SIGNAL p t VRMS x IRMS VRMS x IRMS cos 2wt 0x19999A REAL POWER SIGNAL VRMS x IRMS VRMS x IRMS 0xCCCCD 0x00000 m ad CURRENT e i t V2 x IRMS sin wt Ax _ VOLTAGE v t 2 2 x VRMS x sin wt 04443 064 Figure 64 Active Power Calculation Because LPF2 does not have an ideal brick wall frequency response see Figure 65 the active power signal has some ripple due to the instantaneous power signal This ripple is sinusoidal and has a frequency equal to twice the line frequency Because the ripple is sinusoidal in nature it is removed when the active power signal is integrated over time to calculate the
284. pt event When an interrupt event occurs in the ADE7758 the corresponding flag in the interrupt status register is set The IRQ pin goes active low if the corresponding bit in the interrupt mask register is set When the MCU services the interrupt it must first carry out a read from the interrupt status register to determine the source of the interrupt the interrupts in the interrupt status register stay at their logic high state after an event occurs The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read Table 24 Interrupt Status Register Interrupt Default Flag Value Event Description Bit Location 14 15 16 17 18 19 AEHF REHF VAEHF SAGA SAGB SAGC ZXTOA ZXTOB ZXTOC ZXA ZXB ZXC LENERGY RESET PKV PKI WFSM REVPAP REVPRP SEQERR O OOo ooo ocoococoO Indicates that an interrupt was caused by a change in Bit 14 among any one of the three WATTHR registers that is the WATTHR register is half full Indicates that an interrupt was caused by a change in Bit 14 among any one of the three VARHR registers that is the VARHR register is half full Indicates that an interrupt was caused by a 0 to 1 transition in Bit 15 among any one of the three VAHR registers that is the VAHR register is half full Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A Indicates that
285. que aun se encuentra en desarrollo en la Tabla 4 1 se ha asumido un costo igual al doble de lo invertido en el desarrollo actual A continuaci n se muestra una tabla con los precios aproximados de las diversas partes del prototipo realizado Tabla 4 2 Sistema de control digital de par metros el ctricos Costo M dulo TEMPUS VI Etapa de Pre procesamiento de datos Etapa de Visualizaci n de datos Etapa de control y comunicaci n Etapa de expansi n Chasis Disefio e implementaci n 8 meses Tabla 4 2 Costo del Sistema de Presi n Negativa Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis 44 PRUEBAS DEL PROTOTIPO CONEXION DEL MODULO DEL SISTEMA LA ALIMENTACION FUERA DEL CHASIS PARA INICIAR LAS PRUEBAS DEL EQUIPO PRUEBAS DEL PROTOTIPO DESARROLLADO EQUIPO CONECTADO A LA ALIMENTACION Y AL COMPUTADOR PARA COMPROBAR COMUNICACION ENTRE DISPOSITIVOS Figura 4 6 Pruebas del prototipo Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PROTOTIPO DESARROLLADO DENTRO DEL CHASIS MODULOS DEL SISTEMA Y DE CONTROL CONECTADOS LA ETAPA DE VISUALIZACION E INGRESO DE DATOS FUE REEMPLAZADA POR OTRO VISUALIZADOR POR LAS COMODIDADES EN LAS PRUEBAS Figura 4 7 Pruebas del prototipo Tesis publicada con autorizaci n d
286. r VAR Gain M 32 512 LPF2 Output x The output is scaled by 5096 by writing 0x800 to the VAR gain registers and increased by 50 by writing Ox7FF to them These registers can be used to calibrate the reactive power or energy calculation in the ADE7758 for each phase Reactive Power Offset Calibration The ADE7758 incorporates a VAR offset register on each phase AVAROS BVAROS and CVAROS These are signed twos complement 12 bit registers that are used to remove offsets in the reactive power calculations An offset can exist in the power calculation due to crosstalk between channels on the or in the chip itself The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed The offset registers resolution is the same as the active power offset registers see the Apparent Power Offset Calibration section Sign of Reactive Power Calculation Note that the average reactive power is a signed calculation As stated previously the phase shift filter has 90 phase shift when the integrator is enabled and 490 phase shift when the integrator is disabled Table 12 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation The ADE7758 has a sign detection circuit for the reactive power calculation REVPRP bit Bit 18 in the interrupt status register is
287. r Ium and unity power factor configure the ADE7758 pulse output For Step 6 set the test system for Ium Vnom and zero power factor inductive Step 2 Clear the x WATTOS and xVAROS registers Step 5 Measure the percent error in the pulse output APCF or Step3 Disable the Phase B and Phase C contribution to the APCF VARCE from the reference meter using Equation 49 and pulses This is done by the TERMSEL 2 4 bits of the COMPMODE register 0x16 Setting Bit 2 to Logic 1 and Step 6 Calculate x WATTOS using Equation 56 for xVAROS Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in use Equation 57 the pulse outputs Select Phase A Phase B or Phase C for a line xWATTOS period measurement with the FREQSEL 1 0 bits in the MMODE register 0x14 For example clearing Bit 1 and Bit 0 selects x 2 x AEGEDEN 26 Phase for line period measurement 100 Q Rev C Page 47 of 72 7758 xVAROS 6 VARCF 4 100 VARCFDEN VARCFNUM 4 x VARCE x a x 57 where Q is defined in Equation 58 and Equation 59 For xWATTOS CLKIN 1 1 X 58 i 254 58 For xVAROS CLKIN 1 202 1 Pru C 59 Q 4 Luc 4 4 where the FREQ 0x10 register is configured for line period measurements Step 7 Repeat Step 3 to Step 6 for xVAROS calibration Example Offset Calibration of Phase A Using Pulse Output For thi
288. r de ser la etapa inicial posee caracter sticas avanzadas tal cual las presentan equipos comerciales Adem s de lograr la base para un sistema EEM el prototipo posee un bajo costo y puede ser ntegramente desarrollado en el pa s Como elemento clave del sistema se destaca el dispositivo ADE7758 que aunque present dificultades para la manipulaci n representa una herramienta muy poderosa y econ mica para la medici n de par metros de calidad de energ a Contemplando las multiples alternativas y opciones de medici n que ofrece el dispositivo se considera que puede ser la base para desarrollar equipos de gesti n Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU de par metros de energ a a nivel domiciliario por lo que recomiendo promover su profundizaci n para desarrollo de futuros trabajos de grado pesar de haber sido desarrollada para otro fin la tarjeta TEMPUS VI ha mostrado ser lo suficientemente vers til para cumplir con la funci n de control y c lculo de par metros el ctricos e Se considera significativo resaltar la importancia del montaje f sico para todo proyecto y lo atractivo de una interfaz gr fica en el desarrollo de software Desde el punto de vista comercial es fundamental tener en cuenta cada detalle en lo referente al montaje y condiciones espec fi
289. rcial Luego de haber presentado el an lisis desde ambos enfoques se llega a la conclusi n que en cualquiera de las perspectivas ya sea para el ecosistema a futuro como para el sector privado surge la necesidad de contar con un equipo medidor de energ a el ctrica Ahondando un poco m s si bien el medidor de energ a cumple la funci n de cuantificar la energ a consumida se vuelve m s til un equipo que adem s de cuantificar dicho par metro tambi n pueda cubrir los otros par metros de la electricidad como son voltajes corrientes y los diversos tipos de potencias con ello surge el denominado medidor de par metros el ctricos Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU 1 2 MEDIDORES DE PAR METROS EL CTRICOS El medidor de par metros el ctricos como su nombre lo indica es un dispositivo encargado de la medici n de par metros el ctricos Potencia activa potencia reactiva potencia aparente voltaje corriente entre otros Miden el consumo de dichos par metros dentro de un circuito servicio o sistema el ctrico al cual se hallen conectados Segun su construcci n pueden ser mec nicos electro mec nicos o electr nicos y seg n su modo de conexi n a la red el ctrica puede ser monof sicos o trif sicos Como toda tecnolog a el desarrollo de medidores de par metros el ctr
290. recomendaciones V 11 de la ITU Anexo F Hojas t cnicas Hoja t cnica del SN75176 Secci n Description P g 1 Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA UNIVERSIDAD TESIS CATOLICA DEL PERU e Impedancia de entrada del receptor 12KQ min e Sensitividad de entrada del receptor i 200 mV e Hist resis de entrada del receptor 50 Voltaje de operaci n 5VDC 10 e Bajos requerimientos de potencia Para la l gica de comunicaci n para env o y recepci n de datos el SN75176 sigue EMISOR RECEPTOR VipZ 0 2 V 0 2 V lt Vo lt 0 2 V Vip S 0 2 V Donde X Nivel Alto L Nivel Bajo E 2 Indeterminado Abierto X 7 Irrelevante Z Alta impedancia Tabla 3 1 L gica de funcionamiento del SN75176 Diseno electr nico MICROCONTROLADOR EL DISENO ESQUEMATICO DE ESTA ETAPA COMPRENDE LA TOMA DE DATOS DEL MICROCONTROLADOR Y LA POSTERIOR TRANSMISION SERIAL DIFERENCIAL Figura 3 22 Esquema circuital de la comunicaci n RS 485 etapa de expansi n Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis TENEO ir PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU Esta comunicaci n se encuentra b sicamente realizada por el bus diferencial SN75176 el cual est gobernado por el microcontr
291. rent ranges for specified accuracy shown in Table are expressed in terms of the basic current Ib The basic current is defined in IEC1036 1996 09 section 3 5 1 1 as the value of current in accordance with which the relevant performance of a direct connection meter is fixed Imax is the maximum current at which accuracy is maintained Power Factor PF in Table relates the phase relationship between the fundamental 45 Hz to 65 Hz voltage and current waveforms PF in this case can be simply defined as PF cos 0 where is the phase angle between pure sinusoidal current and voltage Class index is defined in IEC1036 1996 09 section 3 5 5 as the limits of the permissible percentage error The percentage error is defined as ey m x T True Energy x 10094 The schematic in Figure 1 shows the implementation of a simple low cost watt hour meter using the AD7755 A shunt is used to provide the current to voltage conver sion needed by the AD7755 and a simple divider network attenuates the line voltage The energy register kWh is a simple electromechanical counter that uses a two phase stepper motor The AD7755 provides direct drive capability for this type of counter The AD7755 also provides a high frequency output at the CF pin for the meter constant 3200 imp kWh Thus a high frequency output is available at the LED and opto isolator output This high frequency output is used to speed up the calibration process
292. representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties Tl has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals Tl and Tl suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 j PACKAGE MATERIALS INFORMATION TEXAS INSTRUMENTS 16 Jun 2007 www ti com Carrier tope design is defined largely by the component lentgh width and thickness Dimension designed to accommodate the component width H Dimension designed to accommodate the camponent length Dirnension designed te accommodate the component thickness W Overall width of the carrier taps Fitch between successive cavity centers Ac EE O 4D XX Y oprocket Holes Pocket Quadrants TAPE AND REEL INFORMATION Pack Materials Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 16 Jun 2007 Device Package Reel Reel mm BO mm KO mm P1 Pin1 Diameter Width mm UA Quadrant z SN75176A
293. res pines destinados para ello VBP VCP cuya referencia a negativo es el pin denominado como VN Adem s utiliza sus pines DOUT DIN SCLK CS e IRQ para comunicaci n SPI en modo Esclavo recepci n y env o de datos Pre procesador D Filtro Filtro 2 Conector SPI Conector SPI Conectores de pre procesamiento Consideraciones de diseno La descripci n de cada uno de los pines del ADE7758 se encuentra detallada en el Anexo F Hojas t cnicas Hoja t cnica del 7758 Rev C Secci n Pin Configuration and Function Description P g 9 Sin embargo se tomaron en cuenta ciertos aspectos al desarrollar el m dulo de procesamiento de datos los cuales no son descritos en la hoja de datos Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU e Los pines 1 APCF y 17 VARCF son salidas usadas para la calibraci n de potencia activa y reactiva respectivamente Para el proyecto se prefiere la calibraci n mediante registros del software por lo que se procedi a su deshabilitaci n e Los pines 2 y 11 pertenecen a la misma sefial a tierra GND No se requiere de un GND independiente para alguna de ellas pues el desacoplo de se ales se realiza por los transformadores de voltaje y corriente que acondicionar n la de entrada e Los pines 3 y 4 se encuentran alimentados baj
294. rformance Characteristics See the Terminology section for a definition of the parameters See the Analog Inputs section TIMING CHARACTERISTICS AVDD DVDD 5 V 5 AGND DGND 0 V on chip reference CLKIN 10 MHz XTAL Tmn to Tmax 40 C to 85 C Table 2 Parameter Specification Unit Test Conditions Comments WRITE TIMING ti CS falling edge to first SCLK falling edge t2 SCLK logic high pulse width t3 SCLK logic low pulse width t4 Valid data setup time before falling edge of SCLK ts Data hold time after SCLK falling edge te Minimum time between the end of data byte transfers t7 Minimum time between byte transfers during a serial write CS hold time after SCLK falling edge READ TIMING to Minimum time between read command that is a write to communication register and data read tio Minimum time between data byte transfers during a multibyte read ti Data access time after SCLK rising edge following a write to the communications register t2 Bus relinquish time after falling edge of SCLK t13 Bus relinquish time after rising edge of CS 1 Sample tested during initial release and after any redesign or process change that may affect this parameter All input signals are specified with tr tf 5 ns 10 to 90 and timed from a voltage level of 1 6 V 2 See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section 3 Minimum time between read command and data read for all registers except wavefo
295. rica el material de construcci n del chasis debe considerar precauciones para evitar al equipo y o usuarios Color Con finalidad comercial el color debe guardar relaci n a otros equipos Para las tarjetas de componentes Y Dimensiones Basado en la distribuci n de componentes y conectores respetando las consideraciones de diseno Y Material Al ser la base para los componentes electr nicos su material de construcci n debe soportar corrientes de trabajo exposici n al ambiente etc Y Dise o electr nico Se deben respetar conceptos te ricos de conexi n para el routeo de las pistas m scara de componentes adem s de consideraciones para evitar ruido electr nico corrientes par sitas efectos capacitivos etc v Elecci n de componentes Esta elecci n estar sujeta a la disponibilidad comercial de los componentes la facilidad de conseguirse dentro del pa s o de importarse adem s de tomar consideraciones de precios Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU CAP TULO 2 TECNOLOG AS APLICABLES PARA LA MEDICI N DE LOS PAR METROS EL CTRICOS Y TRANSMISI N DE DATOS La investigaci n de las tecnolog as aplicables para el desarrollo del proyecto de tesis se ha dividido en tres grupos los cuales son consecuentes uno del otro Primero se expondran las tecnolog as c
296. ripple This ripple is sinusoidal and has a frequency equal to 2x the line frequency Because the ripple is sinusoidal in nature it is removed when the reactive power signal is integrated over time to calculate the reactive energy The phase shift filter has 90 phase shift when the integrator is enabled and 90 phase shift when the integrator is disabled In addition the filter has a nonunity magnitude response Because the phase shift filter has a large attenuation at high frequency the reactive power is primarily for the calculation at line frequency The effect of harmonics is largely ignored in the reactive power calculation Note that because of the magnitude characteristic of the phase shifting filter the LSB weight of the reactive power calculation is slightly different from that of the active power calculation see the Energy Registers Scaling section The ADE7758 uses the line frequency of the phase selected in the FREQSEL 1 0 bits of the MMODE 1 0 to compensate for attenuation of the reactive energy phase shift filter over frequency see the Period Measurement section Reactive Power Gain Calibration The average reactive power from the LPF output in each phase can be scaled by 50 by writing to the phases VAR gain register AVARG BVARG or CVARG The VAR gain registers are twos complement signed registers and have a resolution of 0 024 LSB The function of the VAR gain registers is expressed by Average Reactive Powe
297. rm register which is to 500 ns min Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0 8 V or 2 4 V Derived from the measured time taken by the data outputs to change 0 5 V when loaded with the circuit in Figure 2 The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor This means that the time quoted here is the true bus relinquish time of the part and is independent of the bus loading Rev C Page 6 of 72 ADE7 1758 TIMING DIAGRAMS TO OUTPUT PIN 04443 002 Figure 2 Load Circuit for Timing Specifications tg E t gt ts lt ee t2 Le gt t4 1 t5 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 04443 003 Figure 3 Serial Write Timing DIN COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 04443 004 Figure 4 Serial Read Timing Rev C Page 7 of 72 7758 ABSOLUTE MAXIMUM RATINGS Ta 25 unless otherwise noted Table 3 Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND IAP IAN IBP IBN ICP ICN VAP VBP VCP VN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Industrial Range Storage Temperature Range Junction Temperature 24 Lead SOIC Power Dissipation Oja Thermal Impedance Lead Tem
298. rrespective of the state of the mask bits To determine the source of the interrupt the MCU should perform a read from the reset interrupt status register with reset This is achieved by carrying out a read from RSTATUS Address 0x1A The IRQ output goes logic high on completion of the interrupt status register read command see the Interrupt Timing section When carrying out a read with reset the ADE7758 is designed to ensure that no interrupt events are missed If an interrupt event occurs just as the interrupt status register is being read the event is not lost and the IRQ logic output is guaranteed to go logic high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt Note that the reset interrupt bit in the status register is high for only one clock cycle and it then goes back to 0 USING THE INTERRUPTS WITH AN MCU Figure 86 shows a timing diagram that illustrates a suggested implementation of ADE7758 interrupt management using an MCU At time ti the IRQ line goes active low indicating that one or more interrupt events have occurred in the ADE7758 The IRQ logic output should be tied to a negative edge triggered external interrupt on the MCU On detection of the negative edge the MCU should be configured to start executing its interrupt service routine ISR On entering the ISR all interrupts should be disabled using the global interrupt mask bit At this poi
299. s al relativo alto costo hacen de los sensores de Efecto Hall algo raros comparados con los TC Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU D BOBINA ROGOWSKI Un modelo sencillo de la bobina Rogowski es un inductor con inductancia mutua con la corriente primaria Corriente i t N vueltas n cleo de aire bobinado rectangular Figura Modelo basico de conduccion Si una corriente i t pasa a traves de un largo conductor en el eje z el campo magn tico en un punto aleatorio p que tiene las coordenadas r q z en coordenadas cil ndricas es gil 27 La fuerza electromotriz EMF generada por el campo magn tico en cualquier rea en el espacio puede ser calculada usando la ecuaci n de Maxwell Electromotive Force 25 15 t Asumiendo que hay N vueltas en la bobina rectangular con n cleo de aire dispuestas en sentido perpendicular al campo magn tico la EMF de la bobina en esta disposici n ay bJdt Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP El t rmino constante M se llama la inductancia mutua de la bobina Rogowski y tiene una unidad Henry Esta indica el nivel de se al de la salida de la bobina por unid
300. s campos de los sistemas electr nicos Dichos cambios han logrado integrar sistemas que hasta hace unos anos no se consideraban dentro de una misma rea tem tica El presente proyecto de tesis busca ampliar la aplicaci n de la electr nica digital fusionando el rea de Electricidad con la de Comunicaciones y desarrollando un oistema de control digital basado en la tecnolog a del microcontrolador ATmega128 de la compafi a ATMEL y del circuito integrado ADE7758 de Analog Devices que adem s posea la l gica adecuada para la medici n trif sica de par metros el ctricos y permita la comunicaci n a redes de datos Con dicha aplicaci n ser la etapa principal y b sica de un sistema mayor encargado de la medici n digital de energ a el ctrica trif sica en media y baja tensi n con un bajo porcentaje de error que permita comunicaci n remota en tiempo real de los par metros el ctricos sensados Voltaje RMS Corriente RMS Potencia Activa Potencia Reactiva Potencia Aparente entre otros hacia un computador de la red La tesis comprender el desarrollo del sistema de control con la l gica adecuada para el procesamiento futuro de medici n y de comunicaci n contando con etapas de ingreso de datos pre procesamiento control visualizaci n comunicaci n y expansiones para mejoras futuras Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA
301. s example Ium 50 mA 220 V Veuttscate 500 V Iruttscate 130 A MC 3200 impulses kWh Power Factor 1 Frequency 50 Hz and CLKIN 10 MHz With Ium and unity power factor the example ADE7758 meter shows 0 009789 Hz on the APCF pulse output When the power factor is changed to 0 5 inductive the VARCF output is 0 009769 Hz This is equivalent to 0 119896 for the watt measurement and 0 0860 for the VAR measurement Using Equation 56 through Equation 59 the values 0 and 0x3 should be written to AWATTOS 0x39 and AVAROS 0x3C respectively AWATTOS 0 23 2 C 0 008778 x 2 8 3 0xFFD 100 0 01863 1 0 08609 24 277 AVAROS Sm x 0 008778 x x 22 623 10096 0 01444 1 For AWATTOS E _10 6 x Lx 0 01863 4 2 4 For AVAROS 10E6 1 202 1 2083 4 Calibration Using Line Accumulation Line cycle accumulation mode configures the nine energy registers such that the amount of energy accumulated over an integer number of half line cycles appears in the registers after the LENERGY interrupt The benefit of using this mode is that the sinusoidal component of the active energy is eliminated Figure 80 shows a flowchart of how to calibrate the ADE7758 using the line accumulation mode Calibration of all phases and energies can be done simultaneously using this mode to save time during calibration START CAL IRMS OFFSET CAL VRMS OFFSET
302. salida del UART sea uno C PROGRAMACION PARA PDAs Entre las diversas PDAs existentes en el mercado he elegido trabajar con los dispositivos m viles de la compa a PALM ONE por su disponibilidad en el mercado peruano actual En la investigaci n de lenguajes y entornos de programaci n para PALMs he tratado de cubrir la mayor a de Sistemas Operativos SO que posee esta firma Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Descripci n Un entorno de programaci n para PALMs es un programa que se ubica en una PC denominada como PC de programaci n en la cual se desarrollar un c digo espec fico basado en un lenguaje de medio o alto nivel Los entornos de programaci n luego que han recibido el c digo en un lenguaje de programaci n determinado se encargan de procesar los datos ingresados y los convierten en c digos de lenguaje m quina los cuales pueden a su vez generar ejecutables o instaladores Criterios de selecci n Para la selecci n del entorno de programaci n adecuado primero se realiz un an lisis de las limitaciones que poseo como programador pues la programaci n en lenguajes de alto nivel no es un rea que nos llegue a competir a los estudiantes de electr nica entonces la primera caracter stica que deb a poseer el entorno de programaci n es que sea de c modo entendimi
303. se this pin should be decoupled to AGND with a 1 uF ceramic capacitor 13 14 VN VCP Analog Inputs for the Voltage Channel This channel is used with the voltage transducer and is referenced as 15 16 VBP the voltage channels in this document These inputs are single ended voltage inputs with the maximum signal level of 0 5 V with respect to VN for specified operation These inputs are voltage inputs with maximum input signal levels of 0 5 V 0 25 V and 0 125 V depending on the gain selections of the internal PGA see the Analog Inputs section All inputs have internal ESD protection circuitry and in addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage Rev C Page 9 of 72 7758 m Description Pin No 17 18 19 20 21 22 23 24 CLKOUT Reactive Power Calibration Frequency Logic Output It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register This output is used for operational and calibration purposes The full scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers see the Reactive Power Frequency Output section Interrupt Request Output This is an active low open drain logic output Maskable interrupts include an active energy register at half level an apparent energy register at half level and waveform sampling up
304. se of TI products which has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific Tl products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplitier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Low Power www ti com lpw Telephony www ti com telephony Wireless Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti c
305. set if the average reactive power from any one of the phases changes The phases monitored are selected by TERMSEL bits in the COMPMODE register see Table 21 If the REVPRP bit is set in the mask register the IRQ logic output goes active low see the Interrupts section Note that this bit is set whenever there is a sign change that is the bit is set for either a positive to negative change or a negative to positive change of the sign bit The response time of this bit is approximately 176 ms for a full scale signal which has an average value of OxCCCCD at the low pass filter output For smaller inputs the time is longer 25 4 ResponseTime 160 ms gt 33 AverageValue CLKIN Table 12 Sign of Reactive Power Calculation Sign of Reactive Power Between 0 to 90 Off Positive Between 90 to 0 Negative Between 0 to 90 On Positive Between 90 to 0 On Negative is defined as the phase angle of the voltage signal minus the current signal that is is positive if the load is inductive and negative if the load is capacitive Rev C Page 36 of 72 Reactive Energy Calculation Reactive energy is defined as the integral of reactive power Reactive Energy a tyat 34 Similar to active power the ADE7758 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in the internal 41 bit accumulation registers VAR hr registers AVARHR BVARHR and
306. sistema Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Adem s el dispositivo deber contar con la capacidad de modelar los voltajes diferenciales adecuados para la comunicaci n exitosa a partir de valores digitales entregados por los pines de comunicaci n serial del microcontrolador principal Componente seleccionado El dispositivo seleccionado fue el Bus Diferencial de Transmisi n SN75176 de la compa a Texas Instruments el cual contiene la l gica de comunicaci n RS 485 de transmisi n serial diferencial la cual permite comunicaci n a distancias de hasta 1000m adem s de ser inmunes al ruido electromagn tico externo La elecci n en cuanto a costos se dio porque ste dispositivo es uno de los m s econ mico en el mercado y en cuanto a funcionalidades electr nicas resaltan sus caracter sticas de convertir datos digitales del UART en valores para RS 485 y viceversa IMAGEN GRAFICA Y ESQUEMATICA DEL BUS TRES ESTADOS CON CAPACIDAD PARA REALIZAR COMUNICACION R5 485 Figura 3 21 Bus diferencial de datos SN75176 Las caracter sticas del dispositivo son Transmisi n bidireccional Driver tres estados de recepci n capacidad de salida por bus de datos de 60 mA M x protecci n termal ante aparici n de sobrevoltaje cumple con requerimientos del est ndar ANSI EIA TIA 422 y las
307. sters The VA hr registers AVAHR BVAHR and represent the upper 16 bits of these internal registers This discrete time accumulation or summation is equivalent to integration in continuous time Equation 42 expresses the relationship Apparent Energy s t dt Lim Y s nT x r 42 t 0 where is the discrete time sample number T is the sample period Figure 75 shows the signal path of the apparent energy accumu lation The apparent power signal is continuously added to the internal apparent energy register The average apparent power is divided by the content of the VA divider register before it is added to the corresponding VA hr accumulation register When the value in the VADIV 7 0 register is 0 1 apparent power is accumulated without any division VADIV is an 8 bit unsigned register that is useful to lengthen the time it takes before the VA hr accumulation registers overflow IRMS M MULTIPLIER CURRENT RMS SIGNAL 0x1C82B 9 DHR 0x00 VRMS VOLTAGE RMS SIGNAL 50 2 0 0 0 174 60 2 0 0 VAG 11 0 Similar to active or reactive power accumulation the fastest integration time occurs when the VAGAIN registers are set to maximum full scale that is OxX7FF When overflow occurs the content of the VA hr accumulation registers can roll over to 0 and continue increasing in value By setting the VAEHF bit Bit 2 of the mask register the ADE7758 can be con
308. t for an 8 us 20 us current pulse If the current pulse is of longer duration and if it occurs more than once during the life of the device this maximum current must be derated Figure 33 shows the derating curve for the S20K275 Assuming exposures of 30 us duration and a peak current as shown in Figure 32 the maximum number of surges the MOV can handle before it goes out of specification is about 10 After repeated loading 10 times in the case just described the MOV voltage will change After initially increasing it will rapidly decay AN 559 SIOV S20K275 107 103 102 10 LW gt Imax 109 WL 10 t SIEMENS MATSUSHITA COMPONENTS Figure 33 Derating Curve for S20K275 EMC Test Results The reference design has been fully tested for EMC at an independent test house Testing was carried out by Integrity Design amp Test Services Inc Littleton MA 01460 USA The reference design was also evaluated for Emissions EN 55022 Class B pursuant to IEC 1036 1996 requirements A copy of the test report can be obtained from the Analog Devices website at http www analog com techsupt application notes ad7755 64567 e1 pdf The design was also evaluated for susceptibility to elec trostatic discharge ESD radio frequency interference RFI keyed radio frequency interference and electrical fast transients EFT pursuant to IEC 1036 1996 require ments The test report is available at http
309. t overflows see the Active Energy Calculation section Bit 0 and Bit 1 of the COMPMODE register determine how the active energy is processed from the six analog inputs 0x02 BWATTHR Watt Hour Accumulation Register for Phase B 0x03 CWATTHR Watt Hour Accumulation Register for Phase C 0x04 AVARHR VAR Hour Accumulation Register for Phase A Reactive power is accumulated over time in this read only register The AVARHR register can hold a maximum of 0 52 seconds of reactive energy information with full scale analog inputs before it overflows see the Reactive Energy Calculation section Bit 0 and Bit 1 of the COMPMODE register determine how the reactive energy is processed from the six analog inputs 0x05 BVARHR VAR Hour Accumulation Register for Phase B 0x06 CVARHR VAR Hour Accumulation Register for Phase C 0x07 AVAHR VA Hour Accumulation Register for Phase A Apparent power is accumulated over time in this read only register The AVAHR register can hold a maximum of 1 15 seconds of apparent energy information with full scale analog inputs before it overflows see the Apparent Energy Calculation section Bit O and Bit 1 of the COMPMODE register determine how the apparent energy is processed from the six analog inputs 0x08 VA Hour Accumulation Register for Phase B 0x09 VA Hour Accumulation Register for Phase C Phase A Current Channel RMS Register The register contains the rms component of the Phase A input of the current
310. t system for Iresr Vnom and the unity power factor For VAR calibration the power factor should be set to 0 inductive in this step For watt and VA the unity power factor should be used VAGAIN can be calibrated at the same time as WGAIN because VAGAIN can be calibrated at the unity power factor and both pulse outputs can be measured simultaneously However when calibrating VAGAIN at the same time as WGAIN the rms offsets should be calibrated first see the Calibration of IRMS and VRMS Offset section Step 6 Measure the percent error in the pulse output APCF and or VARCE from the reference meter ADE7 1758 APCF CF px 96 Error x 10096 49 F REF where CFrer the pulse output of the reference meter Step 7 Calculate xWG adjustment One LSB change in xWG 12 bits changes the WATTHR register by 0 024496 and therefore APCF by 0 024496 The same relationship holds true for VARCF EXPECTED 11 0 xWG 11 0 50 AL nominar APCFDEN 11 0 TQ Error 51 0 0244 When is calibrated the xWATTHR registers have the same Wh LSB from meter to meter if the meter constant and the APCFNUM APCFDEN ratio remain the same The Wh LSB constant is Wh 1 52 LSB MC APCFDEN 1 x x 1000 WDIV Return to Step 2 to calibrate Phase B and Phase C gain Example Watt Gain Calibration of Phase A Using Pulse Output
311. t with no significant reactive ele ments However under certain situations even a small amount of stray inductance can cause undesirable effects when a shunt is used in a practical data acquisition sys tem The problem is very noticeable when the resistance of the shunt is very low in the order of 200 uO Shown below is an equivalent circuit for the shunt used in the AD7755 reference design There are three connections to the shunt One pair of connections provides the cur rent sense inputs V1P and V1N and the third connection is the ground reference for the system The shunt resistance is shown as Rs 350 is the resistance between the V1N input terminal and the system ground reference point The main parasitic ele ments inductance are shown as Loy and 5 Figure 10 also shows how the shunt Is connected to the AD7755 inputs V1P and V1N through the antialias filters The function of the antialias filters is explained in the previ ous section and their ideal magnitude and phase responses are shown in Figures 6 and 7 Figure 10 Equivalent Circuit for the Shunt Canceling the Effects of the Parasitic Shunt Inductance The effect of the parasitic shunt inductance is shown in Figure 11 The plot shows the phase and magnitude response of the antialias filter network with and without dashed a parasitic inductance of 2 nH As can be seen from the plot both the gain and phase response of the network are affected T
312. tant for calibration and test is selected as 3200 imp kWh REV A AN 559 Figure 2 Final Implementation of the AD7755 Meter AD7755 Reference The schematic in Figure 1 also shows an optional reference circuit The on chip reference circuit of the AD7755 has a temperature coefficient of typically 30 However on A Grade parts this specification is not guaranteed and may be as high as 80 ppm C At 80 ppm C the AD7755 error at 20 C 60 C could be as high as 0 65 assuming a calibration at 25 C Shunt Selection The shunt size 350 uQ is selected to maximize the use of the dynamic range on Channel V1 current channel However there are some important considerations when selecting a shunt for an energy metering application First minimize the power dissipation in the shunt The maximum rated current for this design is 40 A therefore the maximum power dissipated in the shunt is 40 x 350 uQ 560 mW IEC1036 calls for a maximum power dissipation of 2 W including power supply Secondly the higher power dissipation may make it difficult to manage the thermal issues Although the shunt is manufactured from Manganin material which is an alloy with a low temperature coefficient of resistance high temperatures may cause significant error at heavy loads A third consideration is the ability of the meter to resist attempts to tamper by shorting the phase circuit With a very low value of shunt resistance the
313. te en el Anexo F Hojas t cnicas AN 559 Application note Rev A Secci n Antialias filter P g 4 Para digitalizar las se ales de voltaje y corriente el ADE7758 usa ADCs de alta velocidad de muestreo alrededor de los 900kHz por lo tanto posee una banda de inter s entre O y 2 kHz que se desea proteger del ruido el ctrico pues la se al de 900kHz se refleja en frecuencia a los 450kHz Adicionalmente el fabricante asegura que no se opte por un filtro de gran precisi n recomendando el filtro RC Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU Componentes seleccionados Los valores de diseno recomendados por Analog Devices para el Filtro RC son 1kO C 33 nF cuya respuesta en magnitud y fase se presenta en la Figura 3 8 Se puede ver que la atenuaci n a los 900kHz para este simple FPB es mayor los 4088 lo cual representa la suficiente atenuaci n para asegurar que no se presentar n efectos de ruido MAGNITUD RU 1 LA RESPUESTA EN MAGNITUD Y FASE DEL FILTRO RC RECOMENDADO POR ANALOG DEVICES MUESTRA QUE UN FILTRO SIMPLE PODRA ATENUAR LOS EFECTOS DEL RUIDO DE LA SENAL Figura 3 8 Respuesta en frecuencia del filtro RC R 1 C 33 nF y con los valores de diseno 1 Adicionalmente por la ecuaci n del filtro RC
314. te nominal de 10A y corriente m xima de 50A Entonces calculando con se al m xima se obtiene 220 x50A4211000W Con sefial sinusoidal m xima en las entradas anal gicas el valor digital promedio de la potencia activa es OXCCCCD ver Figura 3 7 El m ximo valor que puede almacenarse en el registro antes que sobresature es 27 1 OxFF FFFF FFFF el tiempo de integraci n calculado en estas condiciones cumplir la Ecuaci n 6 1 Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU _ OxFF FFFF FFFF y 4 OXCCCCD frec de clock Ecuaci n 6 1 Considerando que en nuestro caso se utiliz un oscilador de 10MHz se tiene 4 1 E 11000W x x 10Mhz 3600s 1 60Wh Por lo tanto cada vez que se llene el registro interno se habra consumido una cantidad de energia igual a 1 6Watt hora B FILTROS PASIVOS DE SENAL Descripcion Encargados de separar la senal el ctrica de los efectos del ruido de la red Criterios de seleccion Se sabe por cuestiones teoricas que los valores entre los cuales oscila la energia el ctrica segun la zona estan entre 50 y 60Hz mientras que el ruido el ctrico se encuentra a frecuencias superiores entonces los filtros a utilizar ser n del tipo Pasa bajos que dejar n pasar la el ctrica e impedir n el paso del ruido no deseado oegun el fabrican
315. terrupt status register contents as shown in Figure 87 If an interrupt is pending at this time the IRQ output goes low again If no interrupt is pending the IRQ output remains high SERIAL INTERFACE The ADE7758 has a built in SPI interface The serial interface of the ADE7758 is made of four signals SCLK DIN DOUT and CS The serial clock for a data transfer is applied at the SCLK logic input This logic input has a Schmitt trigger input structure that allows slow rising and falling clock edges to be used All data transfer operations are synchronized to the serial clock Data is shifted into the ADE7758 at the DIN logic input on the falling edge of SCLK Data is shifted out of the ADE7758 at the DOUT logic output on a rising edge of SCLK The CS logic input is the chip select input This input is used when multiple devices share the serial bus A falling edge on CS also resets the serial interface and places the ADE7758 in communications mode The CS input should be driven low for the entire data transfer operation Bringing CS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state The CS logic input can be tied low if the ADE7758 is the only device on the serial bus However with CS tied low all initiated data transfer operations must be fully completed The LSB of each register must be transferred because there is no other way of bringing the ADE7758 back into communica
316. ters in the total apparent power calculation A pair of frequency divider registers namely VARCFDEN VARCFNUM can be used to scale the output frequency of this pin Note that either VAR or apparent power can be selected at one time for this frequency output see the Reactive Power Frequency Output section Line Cycle Apparent Energy Accumulation Mode The line cycle apparent energy accumulation mode is activated by setting the LVA bit Bit 2 in the LCYCMODE register The total apparent energy accumulated over an integer number of Zero crossings is written to the VA hr accumulation registers after the LINECYC number of zero crossings is detected The operation of this mode is similar to watt hr accumulation see the Line Cycle Active Energy Accumulation Mode section When using the line cycle accumulation mode the RSTREAD bit Bit 6 of the LCYCMODE register should be set to Logic 0 Note that this mode is especially useful when the user chooses to perform the apparent energy calculation using the vectorial method By setting and LVAR bits Bit 0 and Bit 1 of the LCYCMODE register the active and reactive energies are accumulated over the same period Therefore the MCU can perform the squaring of the two terms and then take the square root of their sum to determine the apparent energy over the same period ENERGY REGISTERS SCALING The ADE7758 provides measurements of active reactive and apparent energies that use
317. the voltage waveforms before is adjusted by writing twos complement 12 bit words to the voltage rms gain registers Equation 11 shows how the gain adjustment is related to the contents of the voltage gain register Content of VRMS Register 11 Nominal RMS Values Without Gain x Qn yA For example when Ox7FF is written to the voltage gain register the RMS value is scaled up by 5096 Ox7FF 20474 2047 2 0 5 Similarly when 0x800 which equals 2047d signed twos complement is written the ADC output is scaled by 50 ACTIVE POWER CALCULATION Electrical power is defined as the rate of energy flow from source to load It is given by the product of the voltage and current waveforms The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time The unit of power is the watt or joules sec Equation 14 gives an expression for the instantaneous power signal in an ac system v t N2 x VRMS x sin wt 12 i t N2 x IRMS x sin wt 13 where VRMS rms voltage and IRMS rms current p t v t x i t p t IRMS VRMS VRMS cos 2wt 14 The average power over an integral number of line cycles n is given by the expression in Equation 15 nT p p dt VRMS IRMS 15 0 where t is the line cycle period P is referred to as the active or real power Note that the active power is equal to the dc com
318. tions mode without resetting the entire device that is performing a software reset using Bit 6 of the OPMODE 7 0 register Address 0x13 The functionality of the ADE7758 is accessible via several on chip registers see Figure 88 The contents of these registers can be updated or read using the on chip serial interface After a falling edge on CS the ADE7758 is placed in communications mode In communications mode the ADE7758 expects the first communication to be a write to the internal communications register The data written to the communications register contains the address and specifies the next data transfer to be a read or a write command Therefore all data transfer operations with the ADE7758 whether a read or a write must begin with a write to the communications register Rev C Page 56 of 72 PROGRAM CLEAR MCU INTERRUPT SEQUENCE FLAG ADE7 758 MCU INTERRUPT t a FLAG SET 3 ISR RETURN GLOBAL INTERRUPT MASK RESET 04443 086 Figure 86 ADE7758 Interrupt Management DIN DOUT READ STATUS REGISTER COMMAND IRQ t42 DOI STATUS REGISTER CONTENTS 04443 087 Figure 87 ADE7758 Interrupt Timing COMMUNICATIONS REGISTER DOUT O REGISTER NO 1 REGISTER NO 2 REGISTER REGISTER NO 3 ADDRESS DECODE IN REGISTER NO n 1 OUT IN REGISTER NO n OUT 04443 088 Figure 88 Addressing ADE7758 Registers via the Communications Register The communications register
319. to 26 kSPS see the Interrupts section Master Clock for ADCs and Digital Signal Processing An external clock can be provided at this logic input Alternatively a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7758 The clock frequency for specified operation is 10 MHz Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit Refer to the crystal manufacturer s data sheet for the load capacitance requirements A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7758 The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used Chip Select Part of the 4 wire serial interface This active low logic input allows the ADE7758 to share the serial bus with several other devices see the Serial Interface section Data Input for the Serial Interface Data is shifted in at this pin on the falling edge of SCLK see the Serial Interface section Serial Clock Input for the Synchronous Serial Interface All serial data transfers are synchronized to this clock see the Serial Interface section The SCLK has a Schmidt trigger input for use with a clock source that has a slow edge transition time for example opto isolator outputs Data Output for the Serial Interface Data is shifted out at this pin on the rising edge of SCLK This logic ou
320. tput is normally in a high impedance state unless it is driving data onto the serial data bus see the Serial Interface section Rev C Page 10 of 72 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by Measurement Error Energy Registered by ADE7758 True Energy 1 M M x 10096 True Energy Phase Error Between Channels The high pass filter HPF and digital integrator introduce a slight phase mismatch between the current and the voltage channel The all digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within 0 1 over a range of 45 Hz to 65 Hz and 0 2 over a range of 40 Hz to 1 kHz This internal phase mismatch can be combined with the external phase error from current sensor or component tolerance and calibrated with the phase calibration registers Power Supply Rejection PSR This quantifies the ADE7758 measurement error as a percentage of reading when the power supplies are varied For the ac PSR measurement a reading at nominal supplies 5 V is taken second reading is obtained with the same input signal levels when an ac signal 175 mV rms 100 Hz is introduced onto the supplies Any error introduced by this ac signal is expressed as a percentage of reading see the Measurement Error definition ADE7 1758 For the dc
321. ts to AWATTHR and AVARHR registers to be included Bit 3 and Bit 4 are for Phase B and Phase C respectively Setting all three bits enables the sum of all three phases to be included in the frequency outputs see the Active Power Frequency Output and the Reactive Power Frequency Output sections Setting this bit places the APCF output pin in absolute only mode Namely the APCF output frequency is proportional to the sum of the absolute values of the watt hour accumulation registers AWATTHR BWATTHR and CWATTHR Note that this bit only affects the APCF pin and has no effect on the content of the corresponding registers Setting this bit places the VARCF output pin in the signed adjusted mode Namely the VARCF output frequency is proportional to the sign adjusted sum of the VAR hour accumulation registers AVARHR BVARHR and CVARHR The sign of the VAR is determined from the sign of the watt calculation from the corresponding phase that is the sign of the VAR is flipped if the sign of the watt is negative and if the watt is positive there is no change to the sign of the VAR Note that this bit only affects the VARCF pin and has no effect on the content of the corresponding registers 7 NOLOAD Setting this bit activates the no load threshold in the ADE7758 Rev C Page 66 of 72 ADE7 1758 LINE CYCLE ACCUMULATION MODE REGISTER 0x17 The functionalities involved the line cycle accumulation mode in the ADE7758 are defined by writing
322. ub Bt H1 Properties Private Sub ucCalendari_Click ByVal d Date IrmMain Fom dim f as new frm dd Mame man Segment nt if lRendezVousi Dag d lt gt 1 then Extends Feu t LookupUniqueID LRendezVous Day d Left 0 e0ith t zWith F bExist true Width 160 Height 120 f dStarrDate DateSerial 1904 1 1 Hour t dDa DIA Enabled Resize f dEndDate DateSerial 1904 1 1 Hour t EndDa Fake E Show hbFormModal hbFormPopup hbFormA Align _ BaweBehind False if f sVith lt gt then Caption X Help E 1 ms 8 Ln 90 Col 9 Figura Ventana de programaci n del entorno Adem s para hacer las respectivas pruebas y compilaciones en tiempo real hace uso del emulador para PALM que provee como libre descarga la compania PALM ONE Figura Emulador provisto por PALM ONE Tesis publicada con autorizaci n autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis E PONTIFICIA m TESIS PUCP 5 CAT LICA DEL PERU ANEXO C TECNOLOG AS PARA MEDICI N DE CORRIENTE Los modernos medidores de energ a de estado s lido contienen elementos sensores tanto de voltaje como de corriente La lectura del voltaje se consigue t picamente al dividir el voltaje de la l nea por medio de un divisor con resistencias o un transformador de potencial cuando se necesita aislamiento de la l nea Si
323. ue contiene toda la l gica necesaria para el funcionamiento adecuado de las otras partes del sistema Incluye en su interior las tres funcionalidades de un computador Microprocesador memoria y unidades de Entrada Salida La caracter stica b sica de estos sistemas es su capacidad de re configuraci n pues sin alterar de modo alguno su entorno electr nico s lo mediante programaci n puede realizar funciones muy diferentes a las iniciales Tarjeta TEMPUS VI Como se defini en el Cap tulo 2 para el desarroll del proyecto de tesis se hace uso de la tarjeta de control TEMPUS VI Cuyos datos t cnicos Nombre TEMPUS VI Rev 2 1 P N 030006 e Microcontrolador ATmega128 empaquetado TQFP e Voltaje de alimentaci n o 12 20 VDC regulado o Conector RJ11 para alimentaci n externa Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP UNIVERSIDAD DEL PERU Capacidad de programaci n in situ ISP o Conector IDC de 3x2 para programaci n o En la hoja de datos del microcontrolador ATmega128 ATMEL provee informaci n del software y hardware necesario para programaci n Secci n Serial downloading P g 303 e Interfaz de comunicaci n o 2 conectores molex con comunicaci n RS 232C o 1 conector RJ 45 con comunicaci n TCP IP o 1 conector con comunicaci n SPI e Recursos de la tarjeta o Buzzer
324. ue integra el rea de electricidad con la de telecomunicaciones creando para ello un sistema de medici n de par metros el ctricos con la capacidad de comunicaci n en tiempo real Esta investigaci n e implementaci n constituye el primer paso para lograr este objetivo puesto que la presente tesis desarrolla un Sistema de control digital para medici n de par metros el ctricos con conexi n a redes de datos El prototipo no realiza medici n alguna pero posee la l gica adecuada para esta finalidad y para la comunicaci n mediante TCP IP Para la evaluaci n del sistema se ha acondicionado un software a fin de verificar la correcta interconexi n entre el sistema de medici n y la red de datos adem s de dar lectura a registros internos del prototipo y de esta manera comprobar su correcto funcionamiento El presente documento se encuentra dividido en cuatro capitulos principales y las respectivas conclusiones en el primer cap tulo se hace una revisi n de la problem tica actual de la energ a el ctrica y se expone la necesidad de contar con un control eficiente de la energ a el ctrica tanto a nivel ambiental para la preservaci n del Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS PUCP CATOLICA DEL PERU ecosistema como a nivel industrial para reducir costos sin afectar la produccion Para realizar dicho control s
325. una que puede rotar de modo que aumente el espaciamiento entre ellas La corriente en la bobina ocasiona que las aletas se magneticen de manera similar y que de esa forma se repelan entre s El momento de torsi n producido por la aleta m vil es proporcional al cuadrado de la corriente y es independiente de su polaridad Esto brinda las bases para la operaci n de y para la indicaci n RMS mediante una escala adecuada RESORTE Y PIVOTE LAS PALETAS DE HIERRO DULCE SE REPELEN PALETA ROTATORIA Y AGUJA MONTADA Figura 2 3 Mecanismo b sico de un medidor de hierro m vil Tesis publicada con autorizaci n del autor SOME RIGHTS RESERVED Algunos Derechos Reservados No olvide citar esta tesis PONTIFICIA TESIS UNIVERSIDAD DEL PERU e Instrumentos digitales multifuncionales Un instrumento digital multifuncional es un dispositivo electr nico que puede hacer mediciones de voltaje corriente y o resistencia esto lo consigue al convertir la se al de entrada anal gica en una representaci n digital la cual puede ser muestreada como una lectura digital por el instrumento Los avances en la tecnolog a han hecho que los instrumentos digitales puedan ser capaces de obtener una gran precisi n en la medici n de voltajes corrientes y resistencias alrededor de su rango de trabajo En cuanto a su modo de funcionamiento las se ales de entradas anal gicas AC son convertidas a se ales equivalentes digitales medi
326. vent occurs in the ADE7758 the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register The IRQ logic output is reset to its default collector open state when the RSTATUS register is read Table 23 describes the function of each bit in the interrupt mask register Table 23 Function of Each Bit in the Interrupt Mask Register Bit Location 12 13 14 15 16 17 18 19 REHF VAEHF SAGA SAGB SAGC ZXTOA ZXTOB ZXTOC ZXA ZXB ZXC LENERGY RESERVED PKV PKI WFSM REVPAP REVPRP SEQERR Interrupt Default Flag Value Description Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers that is the WATTHR register is half full Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers that is the VARHR register is half full Enables an interrupt when there is a O to 1 transition in the MSB of any one of the three VAHR registers that is the VAHR register is half full Enables an interrupt when there is a SAG on the line voltage of the Phase A Enables an interrupt when there is a SAG on the line voltage of the Phase B Enables an interrupt when there is a SAG on the line voltage of the Phase C Enables an interrupt when there is a zero crossing timeout detection on Phase A Enables an interrupt when there is a zero crossing timeout detection on Phase B Enables an interrupt when there is a
327. xIRMSOS and xVRMSOS register CHECKSUM REGISTER The ADE7758 has a checksum register CHKSUM 7 0 0x7E to ensure the data bits received in the last serial read operation are not corrupted The 8 bit checksum register is reset before the first bit MSB of the register to be read is put on the DOUT pin During a serial read operation when each data bit becomes available on the rising edge of SCLK the bit is added to the checksum register In the end of the serial read operation the contents of the checksum register are equal to the sum of all the 15 in the register previously read Using the checksum register the user can determine if an error has occurred during the last read operation Note that a read to the checksum register also generates a checksum of the checksum register itself CONTENT OF REGISTERS N BYTES O DOUT CHECKSUM Figure 85 Checksum Register for Serial Interface Read 04443 085 Rev C Page 55 of 72 7758 INTERRUPTS The ADE7758 interrupts are managed through the interrupt status register STATUS 23 0 Address 0x19 and the interrupt mask register MASK 23 0 Address 0x18 When an interrupt event occurs in the ADE7758 the corresponding flag in the interrupt status register is set to a Logic 1 see Table 24 If the mask bit for this interrupt in the interrupt mask register is Logic 1 then the logic output goes active low The flag bits in the interrupt status register are set i
328. xi n de un medidor del tipo trif sico 3 fases 1 neutro 29 Figura 2 12 Aplicaci n actual de la tarjeta TEMPUS __ 30 Figura 2 13 Comunicaci n RS 232 de 3 hilos oococcccoccccccccccnnconcnconnncnnnco 31 2 14 PrROlOCOIO ____________ ______ __ 32 Figura 2 15 Diagrama del sistema de medici n trif sica 36 CAP TULO 3 Figura 3 1 Diagramas de bloques de la interfaz digital 38 Figura 3 2 Pre procesador ADET7798 isc cc es ea ERA TRUE RES dU ERE Gd cda 40 2 PONTIFICIA TESIS PUCP 5 UNIVERSIDAD CAT LICA DEL PERU Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura Figura 3 3 Diagramas de bloques de la medici n de voltaje RMS 41 3 4 Diagramas de bloques de la medici n de potencia activa 42 3 5 Diagramas de bloques de la medici n de potencia reactiva _ 42 3 6 Diagramas de bloques de la medici n de potencia aparente 42

GUERRERO_QUICHI - Repositorio Digital de Tesis PUCP

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