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GRABADOR DE EPROMs AUT~NOMO

1. Port A One 8 bit data output latch butter and one 8 bit data input latch RESET Port B One 8 bit data input output latch buffer and one 8 bit data input buffer Reset A high on this input clears the control reg ister and all ports A B C are set to the input mode Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode Group A and Group B Controls control Each 4 bit port contains a 4 bit latch and can be used for the control signal outputs and status The functional configuration of each port is pro signal inputs in conjunction with ports A and B grammed by the systems software In essence the CPU outputs a control word to the 8255A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 8255A 3 102 DEC TIONAL DATA BUS j Ej Las 52 NS 7 7 1 mean d ware CONTRO a COMTAOL maser es Pin Configuration 1 2 pas a vas pao e var ogs wa RUET gt A 0 o 1 reer 0 lo eal 19 ocr C oar wot rss rag rss I AT 3 227 pee em 7 ni ra 231308 5 231308 4 Figure 4 8225A Block Diagram Showing Group A and Group B Contr
2. CONTROL WORD 8 09 0 0 D Dy 0 D Dy C PB 231308 16 107 CONTROL WORD 5 CONTROL WORD 9 0 0 D D D 0 0 0 D D Pa PB 231308 17 231308 18 CONTROL WORD 26 0 04 0 0 0 Ds CONTROL WORD 10 DER PC 8 Pa PB 231308 19 231308 20 CONTROL WORO 87 CONTROL WORD 11 Dj Og 0 0 D D D D D D 0 D D D 0 D 0p Dy Dy PCy PCo 8 PB PB 231308 21 231308 22 3 108 CONTROL WORD 12 0 0 7 0 0 0 D i 0 00 PC PC PB PBS 231308 23 CONTROL WORD 14 0 0 0 0 0 0 0 0 0 0 m 231308 24 CONTROL WORO 13 0 0 0 D 0 0 D D PA PC PC 0 0 PC PCy 8 PB P8 231308 25 Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring 1 data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 port A and port B use the lines on port C to generate or accept these handshaking signals Mode 1 Basic Functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port e The 8 bit data port can be either input or output Both inputs
3. RECIBE RECIBE Fi TOTAL DE BYTES DE CODIGO 0024 0112 FB MOV R3 A 0025 011331 2 ACALL RECIBE R3 CONTIENE BYTE ALTO 0026 0115 FA MOV 2 R2 CONTIENE BY TE BAJO 0027 0115 0028 0115 0029 0116 31 2C LOOPCAP RECIBE RECIBE 2 BYTES DE DIRECCION 0030 0115 F583 MOV DPH A 0031 0114 312C ACALL RECIBE 0032 0112 F582 MOV DPL A 0033 011 0034 0115 312C ACALL RECIBE RECIBE DAT gt 0035 0126 0036 0120 FO MOVX DPTR A 0037 012 0038 012 1A DEC R2 0039 0122 FF F1 CJNE R2 4 0FFH LOOPCAP 0040 012 1B DEC R3 0041 0125 FF ED CJNE R3 0FFH LOOPCAP 0042 0125 0043 0129 02 20 00 LUMP 2000H 0044 0120 0045 01 7 30 98 FD RECIBE JNB SCON O RECIBE 0046 01 C2 98 CLR SCONO 0047 012 E599 MOV A SBUF 0048 0155 22 RET 0049 0134 0050 0135 ORG 1 OBLIGA AL ENSAM3LADOR A GENERAR 0051 015 00 01 RUN word INICIO POR SEPARAL O UNA LINEA DE CODIGO 0052 012 END PARA LA DIRECCION JE ARRANQUE tasm Nun ver of errors O PROYECTO TERMINAL __ _C AABADOR DE EPROMs AUT NOMO ESTE PROGRAMA ES EL ENCARGADC DE MANDAR INFOFMACION UTILIZANDO EL PUERTO SERIE 1 DE LA PC TRABAJA EN CONJUNTO CON EL CARGADOR ASM PROGRAM LEEOBJ USES CRT DOS VAR NL TE PC CB BE EC NB I J INTEGEF NOMBRE ARCH LINEA TBS PCS CBS STRING 80 F FE TE XT PKK AK Yc Ye c Tc Te KR ik Pic c dc Tc Tc KK A KA KA RE KKK RRR KK KAI AAA AAA k K AAA 277265 FUNCTION HEXA N INTEGER STRING VAR LINE STRING 16 BEGIN L
4. intel 27512 READ OPERATION D C CHARACTERISTICS Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for TD27512 Parameter 1027512 Mn Max Standby Current ma 50 0 rmac as Active Current at High Temperature mA Test Conditions OE Vpp CE Vu Tambient 85 NOTE Ais Binary sequence from Ag to A15 231088 3 OE Vpp 5V R 1 Voc 5V Vss GND CE GND Burn in Bias and Timing Diagrams 27512 ADOR FIAST LOCATION PROGRAM ONE 1 msec PULSE PROGRAM ONE PULSE OF 3X msec DURATION COMPARE ALL BYTES OMIGIMAL Data Figure 5 inteligent Programming Flowchart inteligent Programming Algorithm The inteligent Programming Algorithm programs Intel EPROMs using an efficient and reliable method particularly suited to the production programming environment Typical programming time for individu al devices are on the order of six minutes Actual programming times may vary due to differences in programming equipment Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed A flow shart of the intgligent Programming Algorithm is shown in Figure 4 The intgligent Programming Algorithm utilizes two different pul
5. mm 1 IK RARA RA deje Re Rhe k kc kk fk i k IK AK K K ici PROCE BUFF BEGIN MENG 3 WINDE 35 3 53 6 EPRj IMPRIM 1 1 EDITAR 9 1 0 E IMPRIM 1 2 IMPRIMIR 9 07 DIRS EADKEY CLE Si CAVE RS OF e E BEGIN ND 14 T S AHILE T S OR T2 s DO 3EGIN EDT VAL DIRE DIR ZC j PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO DIR DIR 80 STR DIR DIRE TEXTCOLOR 7 TEXTBACKGRCOUNDIO CLRSCR END IAPR ELSE END CLRSCF END WKAR ARR orn kk RIKKI AKKA IA ARA A k cik kc k kc k A ARK KA kk k SEREA PROCE URE ACQ BEGIN TEXTCOLOR O TEXTEACKGROUND 2 WIND 2W 20 10 70 16 GOTIC Y 1 1 WRIT GRABADOR DE EPROMS PARA EL PROYECTO TERMINAL 2 5 GOTO Y 1 2 WRITE GOTOXY 1 3 WRITE OCTUBRE DE 1996 y GEIE Y 1 4 WRIT pr GOTE Y 1 5 WRITE DERECHOS RESERVADOS b DELA 1500 END ec IC RT PROCE CURE MAN BEGIN GCTC Y 1 4 WE T NCSI SIRVE EL MANUAL DELA 1000 CLRS END ORTI OD ento dae dato gie toot nod PROCE CURE AYUD BEGIN MENU 4 WIN 4 52 3 75 6 1 1 1 DE 13 1 0 A S 1 2 MANUAL 13 10 M DIRS EADKEY CLPS CASE RS OF GE m 58 ELSE END TEX DLOR 7 TE ZKGROUND 0 PROC TO TERMINAL CRABADOR
6. Figure 7 Bit Set Reset Format when Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports interrupt Control Functions When the 8255A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The in terrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C MODE 0 BASIC INPUT This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is set Interrupt enable BIT RESET INTE s RESET Interrupt disable NOTE All Mask flip flops are automatically reset during mode selection and device Reset Operating Modes MODE 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports e Any port can be input or output e Outputs are latched e Inputs are not latched 16 different Input Output configurations are pos Sible in this M
7. FIGURA 2 CIRCUITO BASE PARA CONTROLAR PINES DEL SOCKET 30V 100F 35V R2 2210 R1a 66522 OV 5V 12 5V 21V 25V HABILITA 5V HABILITA 12 5V HABILITA 21V HABILITA 25V HABILITA 0V Vout Vref 1 R1x R2 ladjR1x Vout 1 25 1 R1x 221 00005 R1x Los pines 20 y 27 utilizan un circuito combinacional mas sencillo que puede observarse en el circuito de la figura 3 FIGURA 3 CIRCUITO COMBINACIONAL PARA CONTROL DE PINES 20 Y 27 PIN 27 DEL SOCKET e PIN 20 DEL 5 6 PA2 B De esta forma para activar algun voltaje del circuito de control de voltajes basta mandar un cero l gico y para activar cero volts se precisa de un uno l gico lo cual hace posible su control desde el programa principal Para llevar acabo dicho control se precisa de un circuito que organice todo el funcionamiento es aqu donde se hace necesario el uso de un microcontrolador entre los circuitos considerados est n 8031 8051 8032 8052 todos ellos de Intel Una de la caracter sticas para decidir entre ellos fueron los requerimientos de memoria ROM P GINA 9 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO interna externa o ambas que se tienen en el proyecto adem s del costo y la existencia de ellos en el mercado Como la programaci n se realizar en lenguaje ensamblador no se necesita de ning n interprete dentro del micro adem s de que algunas
8. 3 BECIN T2E 22764 V DEF V21 025 8191 S uon ESCRIBE 3 ENT A BF CIN 2 2 2764 V DEF V12 U3S 8191 S ESCRIBE 4 EN 5 BEC IN T2z 227128 VLEF sV24 216383 2 E SRIBE 5 EN 6 BES IN T n 727128A VIEF V12 UE 216383 SR qus PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO SCRIBE 9 T BEGIN TPE 27256 VE EF V12 U 32767 S15 EZCRIBE 7 8 BEGIN 7 22 27512 VE EF V12 UE 6550 S ESCRIBE 8 ELSE END FIN DEL CASE IF IND C THEN VOLT JES CASE S OF 1 ES 2 0 2 ES ZRIBE 1 S E ZRIBE 2 END FIN DEL CASE DE S TEXTC LOR 7 TEXTE CKGROUND O0 END PWIA I LARA AAA A KARA k CR KK e ARK KARA k k KA KARA ver PROCECURE VERIF BEGIN GOTOXY 1 4 WRITE N SI SIRVE LA VERIFICACION DELAY 1000 CLRSCR END BRA A K o ico ief K K k K K KAR KK KA Re e Roe fc e he je fcfc A X Kok n 4 PROCE URE CARG BEGIN GOTO Y 1 4 WRITELN SI SIRVE LA CARGA DELA 1000 CLRSC 3 END PRIA s A A A t K kk RA KKK KEKE kiki AAA AR KA A ARK kikk PROCEDURE IMPR BEGIN GOTO Y 1 4 WRITE N SI SIRVE LA IMPRESION DELA 1000 CLRS 2 END PROVE TERMINAL _ GRABADOR DE EPROMs AUT NOMO FERRO KI RD IIIA IIIA BCA ACSIA IIA IAL KIARA IIA kk kikik
9. Al encender el grabador enviara un mensaje de inicio HOLA al usuario y pondr en el display un signo de interrogaci n gt Esperara que se presione PB2 y estar en modo INDEPENDIENTE despliega I Al presionar nuevamente PB2 se ira a modo DEPENDIENTE despliega d Estar oscilando en ese men mientras se presione PB1 Si se desea trabajar en modo INDEPENDIENTE se debe presionar PB1 cuando este la 4 en el display de 7 segmentos en ese momento se entrar al men del modo INDEPENDIENTE Si lo que se desea es trabajar en modo DEPENDIENTE se tendra que presionar PB1 cuando la d este en el display y se entrara al men del modo DEPENDIENTE El proceso anterior se describe en el diagrama de flujo 1 que muestra adem s las acciones que se realizan v a software P GINA 38 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO El men del modo INDEPENDIENTE se describe a continuaci n gt Indica grabar de EPROM a EPROM gt Indica comparar el contenido de la EPRON con el buffer del grabador gt Es una se al generalizada que indicara sai r al menu anterior en todos los men s y submen s Para realizar cualquiera de las acciones anteriores se debe de seleccionar con el PB2 y despu s arrancar el proceso con el PB1 Este proceso lo observamos en el diagrama de flujo 2 Cada una de las opciones del modo INDEPENDIENTE nos lleva a una rutina La rutina para GR
10. AK k k KK AK EA ES PROCE JRE VOLTAJES BEGIN WINDE 25 10 65 14 TEXTC OR 0 TEXTE SKGROUND 2 IND 0 GOTO 1 1 WRITE N VOLTAJE DE PROGRAMACION PROPUESTO VDEF GOTO 1 2 WRITE 4 e GOTO 1 3 WRITE NUEVO VOLTAJE WRITE N S N 3 16 3 RES ADKEY CASE S OF S siEr SIN Y REOL YTOXY 1 1 REOL i PRIME 2 1 1 12 5V 1230 9 RIME 15 1 2 21 0V 12 16 0 2 PRIME 28 1 3 25 0V 0 29 1 3 C 2TOXY 16 3 READKEY ASE S OF NV zVA2 NV V21 NV V25 END FIN DEL CASE DE S gt RSCR E X FIN DEL BEGIN Y VDEF ELSE JR END FIN DEL CASE END ries ti ORR ecc k o K deck eR ook RA HA RA KA gt lt A KA RARA e Re Re RC Re KR SIDON PROCE CONF BEGIN WINDC 23 4 43 18 TEXTC OR 0 TEXTB CKGROUND 2 IMPRIME 1 2 0 2716 12 30 0 IMPRIME 1 3 1 2732 71230 7 PROYE O TERMINAL DE EPROMs AUT NOMO IMPRIME 1 4 2 2732A 12 30 127 IMPRIME 1 5 3 2764 123023 IMPRIME 1 6 4 2764 12 30 4 IMPRIME 1 7 5 27128 12305 IMPRIME 1 8 6 27128 12 30 6 IMPRIME 1 9 7 27256 12307 1 10 8 27512 12 3 0 8 T READKEY CLRSC gt IND 0 CASE OF O BEGIN T z z2716 VIZR V25 UE 2047 Gea ESCRIBE 0 END 1 BEGIN OrEEPT32 v EF V25 U 4095 S 3 E SCRIBE 1 ENC 2 BEUGIN E 3cRIBE 2
11. AH 0 AL X INTR S14 REG end end PRI AIK IK IRR deed de ke Yc fe he fe Re Bee de khe ke ehe Ke JAEN EO PROCEDURE LEE VAR X BYTE var Reg Ro jisters begin with Rey Jo begin DX 0 2 INTR S14 REG X AL end end FAH ARIK AAA a PROCEDURE INITPORT var Reg Reyisters begin with Rey do begin Dx 0 AH 0 AL 83 INTR S 4 REG end end PARRA Umen PROCEDIMIENTO IMPRIME XY POS CION PLC POSICION DE LETRA CAMBIADA TT TAMA O DEL TEXTO BS INDICADOR LC LETRA CAMBIADA okk ok ok A AA IRONIA ke W Pe Ree Re Be he he he KICK eR IKI KKK KIKI Kee MR k k k hee fe KK KAKI AHA AY PROCECURE IMPRIME X Y INTESSER TEXTO STRING TT PLC E 3 INTEGER LC CHAR IIA ek Kc jede HAKKAR kk ha i TERMINAL GRABADOR DE EPROMs AUT NOMO BEGIN TEXTCCLOR O0 TEXTBACKGROUND 2 GOTOX X Y WRITE EXTO GOTOX PLC Y TEXTCCLOR 4 WRITE LC GOTOX TT Y IF BS lt gt 0 THEN WRITELN TEXTCCLOR TEXTBACKGROUND O END PAINT ICA amp IK IIAAIIA KR ARIAS A ISK AKER RK il Pu iS Y FUNCTION LEE BYTE DIR WORD BYTE VAR OP_COD BYTE BEGIN ESCRIBE 3 ESCRIBE HI DIR ESCRIE LO DIR LEF OF COD LEE BY TE ZOP COD END ad amo PROCEDIMIENTO MENUE KK KKRKKKK KIA KK KA Ts
12. C for zA7RS40PV OC for 4 785400 and A7RSAOPC 20 C for 785400 79 40 2 Fc supply voltages iess nan 30 V the maximum differential input voltaye Ero and Op Amp 5 equai to the supply voltuza vec Op Amp D v Ta Tto ma unless ctherwise noted Symbol Min Typ Max E 50VI 36 _ 40 Be e a ti eS Supply Current Vcc Connected I Vee s 5 0 40 Nee 40V 55 REFERENCE Reference Voltage tiret gt 1 0 mA Reference Voltage Line Regulation 130 V lt 40 V iret 1 0 mA Ta gt 25 Reference Voltage t Regulation 11 0 mA s lreg lt 10 MA TA 25 MOTOROLA LINEAR INTERFACE DEVICES pA78S40 FIGURE 5 STEP DOWN CONVERTER Use externa RAR DE FIGURE 6 STEP UP CONVERTER per Losse ator L Vout 28 V 175 mA Use eterna recite tu increase cucut afficenzy MOTOROLA LINEAR INTERFACE DEVICES 3 394 S321A30 FIVIYILNIYVINIY VIOYOLOW LEE uonvuniojut 194140 20 ZUOZENV SION ees wonein as pue ays 123449 LA 92UIS INJEA MO 01 1095 pinoys ojddu ayi NOAL pue 15 SIHIS s JONIRALI INP Oi paau INPA pasejnojes aui ul add INd no yead o1 4e
13. OUTPUT ENABLE PROG LOGIC OUTPUT BUFFERS CHIP ENABLE Y GATING 65 536 CELL MATRIX ADORESS INPUTS 290000 1 Shaded Areas represent the 87C64 version Figure 1 Block Diagram intel 27C64 87C64 Pin Names ESSES ADORA CHIP NO CONNECT 27C64 87C64 P27C64 P87C64 NOTE Intel Universal Site Compatible EPROM Pin Configurations are shown in the adjacent blocks to 27C64 Pins Shaded Areas gt represent the 87064 version Figure 2 Pin Configuration 32 PIN PLCC 9 0 450 X 0 550 25 11 430 X 13 970 MILLIMETERS TOP VIEW gt T amp Te Tl gt E Ma DE Mo Te 2 e ile teii Ueli i Me fe III oz fone fou os Figure 3 PLCC N Lead Configuration 290000 11 intel 27 64 87 64 Extended Temperature Express EXPRESS EPROM Product Family EPROMs The Intel EXPRESS EPROM family is a series of PRODUCT DEFINITIONS electrically programmable read only memories which Operating have received additional processing to enhance Temperature C Burn in 125 C hr product characteristics EXPRESS processing is available for several densities of EPROM allowing Oto 70 the choice of appropriate memory size to match sys 40 to 85 tem applications EXPRESS EPROM products are available with 16
14. cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temperature range is 0 C to 70 C Extended op erating temperature range 40 C to 85 EX PRESS products are available Like all Intel EPROMs the EXPRESS EPROM family is inspected to 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing READ OPERATION D C CHARACTERISTICS Electrical Parameters of EXPRESS EPROM prod ucts are identical to standard EPROM parameters except for TD2732A LD2732A Test Min Max Conditions Vcc Standby Vin Current mA Vit Voc Active 1 Voc Active OE CE Vi Current at High Vcc Temperature mA TAmbient 85 C NOTE 1 Maximum current value is with outputs Oo to O7 unloaded OE Vpp 5V R 1KM Voc 5V Vss GND CE GND 2732A EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITONS Operating Temperature Q 0 C to 70 C 40 C to 85 C 40 C to 85 C Burn in 125 C hr EXPRESS OPTIONS 2732A Versions Packaging Options Speed Versions L _ s Ort O A11 290081 4 Binary Sequence from Ao to A4 intel 2732A every eight devices The bulk capacitor should be located near where the power supply is connected to the array The purpose of the bulk capacitor is to overcome the voitage droop caused b
15. data is desired from a particular memory device Programming Initially and after each erasure all bits of the 2716 are in the 1 state Data is introduced by selectively programming O s into the desired bit locations Al though only O s will be programmed both 173 and O s can be presented in the data word The only way to change a 0 to a 41 is by ultraviolet light erasure The 2716 is in the programming mode when the Vpp power supply is at 25V and is at Vi The data to be programmed is applied 8 bits in parallel to the data output pins The levels required for the address and data inputs are TTL When the address and data are stable a 50 ms active high TTL program pulse is applied to the C input A pulse must be applied at each address loca tion to be programmed You can program any loca tion at any time either individually sequentially or at random The program pulse has a maximum width of 55 ms The 2716 must not be programmed with a DC signal applied to the C input Table 1 Mode Selection Vin Output Disable Vit Standby Program Pulsed Vi to Vin Program Inhibit NOTE 1 X can be Vi or Vin intel 2716 Programming of multiple 2716s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements Like in puts of the paralleled 2716s may be connected to gether when they a
16. 40 OA CJNE A 040H SAL_IND checa con pb2 20C3 2003 20C3B480D2 INICIO GRAB CJNE A 080H MENU_IND 20C6 01 D2 AJMP GRABAR IND 20C8B480 CD INICIO COMP A 080H MENU_IND 20CB 21 25 AJMP COMPR IND 20CD B480C8 SAL IND CJNE A O80H MENU IND 200001 1B AJMP INDP 20D2 2002 75 29 FF GRABAR IND TIPO 4OFFH 2005 0529 PROX TIPO INC TIPO 20D7 E5 29 MOV ATIPO 20D9 71 AB ACALL GET7SC 20DB 71 F6 ACALL LED 20DD 71 66 ACALL CHECK PBS 20DF B4 40 07 CJNE A OSCH START PB2 20E2 ES 29 MOV ATIPC 20E4 B4 08 CJNE A BOSF PROX TIPO 20E7 01 D2 AJMP GRABAR IND 20E9 20E9 20E9B480E9 START CJNE A 08CH PROX TIPO PB1 20EC 31 28 INI BUFF INICIALIZAR EL Bur ER DE LA RAM EN 20EE 74 71 FUENTE MOV A XF 20FO 71 BE ACALL IMPRIME P GINA 27 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO 20F2 71 F6 ACALL LED 20F4 31 A7 ACALL PWEDWN 20F6 71 66 ACALL CHEZK PBS 20F8 B4 80 F3 CJNE A 0SOH FUENTE PB1 20FB 71 E3 ACALL LED 20FD 71 81 ACALL DELAYX 20FF 31 4B ACALL CCMD CARGAR EL CONTENIDO DE LA EPROM EN LA RAM 2101 743E DESTINO MOV A XD 2103 71 BE ACALL IMPRIME 2105 31 A7 ACALL PWRDWN 2107 71 66 CHECK PBS 2109 B4 80 0C CJNE A 0304 SALIR_DEST 210C 71 E3 LELI 210E 51 16 PCMD PROGRAMAR LA EPROM ON EL CONTENIDO DE LA RAM 2110 E5 29 MOV ATIPO 211271 AB GET7SC 21147181 ACALL DELAYX 21162101 AJMP DESTINO 21187430 SALIR DEST A
17. AUT NOMO 0063 0064 0065 0100 0101 0102 0103 0105 0106 0107 0108 0109 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 0130 0131 0132 0133 0134 2000 2000 90 60 03 INICIO MOV DPTRPCTRL2 CONFIGURACION DE LA PPI B 2003 74 88 MOV A 88H PARA MODOS DE 27 2005 FO MOVX QDPTRA HOJAS 2006 90 40 03 MOV DPTR HPCTRL1 CONFIGURAGION DE LA PPI A 2009 74 80 MOV A 80H 200B FO MOVX DPTRA 200 31 A7 ACALL PWRDWN 200E 7129 REGRESO HOLA 2010 74 B3 MOV A XINT DESPLIEGA SIGNO DE INTERROGACION 201271 BE ACALL IMPRIME 20147166 PB2 CHECK PBS MONITOREA PB PARA SELECCIONAR 2016 B4 40 FB CJNE A 4040H MON_PB2 EL MODO DE TRABAJO 2019 80 00 SJMP MOD_INDP 2018 A 201 7450 MOD INDP MOV A XI MONITOREA PB1 PARA COMENZAR 201D 71 BE ACALL IMPRIME INDEPEND EHTE O PB2 PARA 201F 7166 CHK1 ACALL CHECK PBS CAMBIAR A DEPENDIENTE 2021 B4 4002 CJNE A 040H CHK2 2024 01 2B AJMP MOD DEP 2026B480F6 CHK2 CJNE 8 1 202901 98 AJMP MENU IND 202B paqna suspa noon 2028 743E DEP MOV A XD MONITOREA PB1 PARA COMENZAR CON 202D 71 BE ACALL IMPRIME MODO DEPENDIENTE O PB2 PARA 202 7166 CHECK ACALL CHECK PBS CAMBIAR A MOCC DEPENDIENTE 2031 B4 4002 C
18. DE EPROMs AUT NOMO CLR3 amp END ik ke kk KARA NAAA A KIRA AA K K A fcfc fc k A fc cfc Tc KA KK A AAA PROCEDURE INITPC BEGIN ESCRIBE 6 END db PROCEDURE INIT BEGIN TEX COLOR 7 TE gt L CKGROUND O CLEDES MENG 0 ESTACO END AKA 2 Ar ARA AAA PROGRAMA PRINCIPAL ek koko I ANI NOI NOMBRE DEL ARCHIVO TPE TIPO DE EPROM NV _ DE PROGRAMAC ON FRI RIK IKI IRR IIR IKI 9 K K IK IK Heth AA BEGIN NOMAR OBJ 2716 NV 55V REF FLUSH i NPUT S RE DKEY 5 OF 1 RCH E JFF Y y UD 41210028 AAA BRK fc e x e K fc ic o e k Ac kk Kok IPRA K feci h IIA k ik ee Bede AKA id ERE CR O ES ac x UNT CHR 13 96 Bus
19. IIL on the data sheet because of the internal pullups Port 2 emits the high order address byte during fetches from external Program Memory and during accesses to extemal Data Memory that use 16 bit addresses MOVX GDPTA this application it uses strong internal pullups when emitting 15 During accesses to external Data Memory that use 8 bit ad dresses MOVX Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high order address bits dur ing programming of the EPROM parts and during program verification of the ROM and EPROM parts Port 3 Port 3 is an 8 bit bidirectional VO port with internal pullups The Port 3 output buffers can sink source 4 LS TTL inputs Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are extemally being pulled low will source current IIL on the data sheet because of the pullups Port 3 also serves the functions of various special features of the MCS 51 Family as listed below serial input port TXD serial output port INTO external interrupt 0 INT1 external interrupt 1 TO Timer O external input T1 Timer 1 external input WR external data memory write strobe AD external data memory read strobe 8255A 8255A 5 PROGRAMMABLE PERIPHERAL INTERFACE MCS 85 Compatible 8255A 5 m Direct Bit Set Reset Capability
20. SYMBOL PARAMETER UMITS Turn Off Delay Input to Output Turn On Delay Input to Output Voc MAX Vy 2 7 V Voc MAX Vy 10V Voc gt MAX Vy 04 V Vcc MAX Voy OV Voc MAX Inputs Open Vcc MAX Vy 7 OV NOTES 1 For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable device type 2 are at 50 V 25 C 3 Nor more than one Output should be shorted at time 8 T54LS51 T74LS51 PART NUMBERS TEMPERATURE 7541 551 55 C to 125 C T74LS51X 0 Cto 70 C X peckage type D for Ceramic Dip B for Plastic Dip See Packaging Information Section for packages availeble on this product DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS Note 1 Input HIGH Voltage Guaranteed input HIGH Voltage o 4 ME Vit input LOW Voltage Guaranteed Input LOW Voltage 74 input Clamp Diode Voliage Output HIGH Voltage Output LOW Input HIGH Current Input LOW Current Output Short Circuit Current Note 3 Supply Current HIGH Supply Current LOW AC CHARACTERISTICS TA 25 C See Page 273 for Waveforms Voc MIN Iy 18 mA Voc MIN igu 400 pA Viy V gt Vec MIN lot 4 0 mA Viy gt 20V Vec MIN lg 80 mA Viy 20V Voc gt MAX Vin 27 V Voc Vi
21. Single 5 Supply The 512566 is 32768 word by 8 bit CMOS static RAM fabricated using CMOS Silicon Gate process When the Chip Select is brought high the device assumes a standby mode in which the standby current is reduced to 100 uA max The device has data retention mode that guarantees that data will remain valid at minimum Vcc of 2 0V Functionai Block Diagram Pin Connections 1024 x 256 MEMORY ARRAY DECODER 1 01 1 08 240572 2 z i f Er j Pa sess E CIRCUIT Address 240572 1 WE x GE ouput Enable lt intel Device Operation The 51256S has two control inputs Chip Select CS and Write Enable WE CS is the power control pin used for device operation WE is the data control pin used to gate data at the 1 0 pins Out Enable OE is used for precise control of the outputs ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Vin 0 3V to 7V Storage Temperature Tsra 55 C to 150 C Power Dissipation Pp 1 0W DC Continuous Output Current los 50 mA 51256S L Table 1 Mode Selection Truth Table yo Active Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at
22. Voc MIN lo 80 mA Vy 20 V 27N input HIGH Current MAX Vin Input LOW Current Output Short Current Note 3 Supply Current HIGH Supply Current LOW Voc MAX Inputs Open TEST CONDITIONS Turn On Delay Input Io Output For condu ons shown as MIN or MAX use the appropriate value specified under recommended operating conditions lor the applicable device type 2 Typical homi are at VCC 5 0 V TA 25 C 3 Not more thas one Output should be shorted at time TE4LSOB8 T74LS08 QUAD 2 INPUT AND GATE Yee PART NUMBERS T74LS08X TEMPERATURE 55 C to 126 C 0 70 X package type D for Ceramic Dip B for Plastic Dip Seq Packaging informaron Section for packages avaitable on this product DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE unless otherwise specified SYMBOL PARAMETER Input HIGH Voltage Vi Input LOW Voltage Vco Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage TEST CONDITIONS Note 1 Guarantead Input HIGH Voltage Guaranteed input LOW Voltage Vcc MIN in Voc MIN 400 uA Vin Ving Voc MIN Ig 40 mA Vin V Vec MIN ig 80 mA Viy Vip Input HIGH Current input LOW Current Output Short Ciecuit Current Note 3 lect Suppty Current LOW ss a lela Ula o mn AC CHARACTERISTICS Ta 25 See Page 273 for Waveforms
23. a 5V only 524 288 bit ultraviolet Erasable and Electrically Programmable Read Only Memo ry EPROM organized as 64K words by 8 bits This ensures compatibility with high performance microproces Sors such as the Intel 8 MHz iAPX 286 allowing full speed operation without the addition of performance de grading WAIT states The 27512 is also directly compatible with Intel s 8051 family of microcontrollers The 27512 enables implementation of new advanced systems with firmware intensive architectures The combination of the 27512 s high density cost effective EPROM storage and new advanced microprocessors having megabyte addressing capability provides designers with opportunities to engineer user friendly high re liability high performance systems The 27512 s large storage capability of 64 K bytes enables it to function as a high density software carrier Entire operating systems diagnostics high level language programs and specialized application software can reside in a 27512 EPROM directly on a system s memory bus This permits immediate microprocessor access and execution of software and eliminates the need for time consuming disk accesses and downloads Two line control and JEDEC approved 28 pin packaging are standard features of all intel high density EPROMs This assures easy microprocessor interfacing and minimum design efforts when upgrading adding or choosing between nonvolatile memory alternatives The 27512 is manufactured using
24. a trav s de un RS232 que es una interfaz por el puerto serial En un grabador convencional se pueden realizar varias operaciones entre las mas elementales est n CARGAR El programador acepta un archivo en c digo HEX y lo carga en su buffer de memoria DESPLEGAR Se despliega el contenido del buffer de memoria del programador en la pantalla de la PC COPIAR Se lee el contenido de la EPROM y se almacena en el buffer de memoria del programador PROGRAMAR Se almacena el contenido del buffer de memoria del programador en el arreglo de memoria de la EPROM COMPARAR Se compara el contenido de la EPROM con el contenido del buffer de memoria del programador VERIFICAR Se examina el contenido de la EPROM y se determina si esta ha sido borrada TIPO Se selecciona el tipo de EPROM que ser insertada en el socket del programador EDITAR Se puede alterar el contenido del buffer de memoria del programador GRABAR Comprende los procesos de COPIAR y PROGRAMAR Cada que se requiere realizar alguna de estas operaciones por fuerza es necesario hacer uso de una computadora en la cual este instalado el software y el hardware del grabador pero que pasa si necesitamos nicamente realizar varias copias del contenido de una misma EPROM o si queremos comparar el contenido de una EPROM con el contenido de la otra En estos casos usar una PC nicamente para este prop sito es un desperdicio podemos entonces pensar en el dise o de un grabador
25. additional processing to enhance product characteristics EXPRESS processing is available for several densities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are available with 168 8 hour 125 C dynamic burn in using Intel s standard bias configuration This pro cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temperature range is 0 C to 70 C Extended op erating temperature range 40 C to 85 C EX PRESS products are available Like all Intel EPROMs the EXPRESS EPROM family is inspected to 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITONS Operating Temperature Burn in 125 C hr 0 C to 70 C 168 8 40 C to 85 C 44 EXPRESS OPTIONS 2716 Versions intel 2716 DEVICE OPERATION The six modes of operation of the 2716 are listed in Table 1 it should be noted that inputs for all modes are TTL levels The power supplies required are a 5V Vcc and a Vpp The Vpp power supply must be at 25V during the three programming modes and must be at 5V in the other three modes Read Mode The 2716 has two control functions both of which must be logically satisfied in order to obtain data at the outputs Chip Enable CE is the power control and should be used for device sele
26. and outpu s are latched The 4 bit port is used for contro and status of the 8 bit data port CONTROL WORD 15 0 D D D 0 D D Do D Dy PC PCy PB PB 231308 26 Input Control Signal Definition STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is one It is reset by the falling edge of RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port 3 109 5164S L 8K x 8 BIT CMOS STATIC RAM 51645 10 100 100 55 51645 12 Address Access Time taa Chip Select Access Time tacs Output Enable Access Time tog m Static Operation m Power Down Mode No Clock Retresh Required m TTL Compatible m Equal Access and Cycle Times Simplifies System Design m Single 5V Supply m Common Data Input and Output m High Reliability 28 Pin 600
27. between non volatile memory alternatives HMOS is a patented process of Intel Corporation v DATA OUTPUTS cc 0 0 Vee OE e OUTPUT ENABLE POM CHIP ENABLE 12 ADORESS INPUTS Figure 1 Block Diagram intel 2764A Pin Names CmipEmable OE OutputEnabie Outputs NC Vec Poli s Pe Ae Ao s Ay DE Aro Aro TE TE TE gt gt gt o Os o o Os Os Os 0 Os O O NOTE Intel Universal Site Compatible EPROM pin configurations are shown in the blocks adjacent to the 2764A pins Figure 2 Cerdip Pin Configuration intel EXTENDED TEMPERATURE EXPRESS EPROMs The intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics EXPRESS processing is available for several densities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS T ewctoresc L READ OPERATION D C CHARACTERISTICS 2764A available with 168 8 hour 125 C dynamic burn in using Intel s standard bias configuration This pro cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temp
28. each erasure all bits of the EPROM are in the 1 state Data is introduced by selectively programming 05 into the desired bit lo cations Although only Os will be programmed both 1s and Os can be present in the data word The only way to change a 0 to a 1 is by ultravio let light erasure The device is in the programming mode when Vpp is raised to its programming voltage See Table 2 and CE and are both at TTL low and OE Vi The data to be programmed is applied 8 bits in paral lei to the data output pins The levels required for the address and data inputs are TTL Program Inhibit Programming of multiple EPROMs in parallel with different data is easily accomplished by using the Program Inhibit mode A high level CE or PGM input inhibits the other devices from being programmed Except for CE all like inputs including of the parallel EPROMs may be common A TTL low level pulse applied to the PGM input with Vpp at its pro gramming voltage and CE Vi will program the selected device 27 128 ADDRESS FIRST LOCATION Vec 6 25 Vpp 12 75V PROGRAM ONE 100 jus PULSE ONE BYTE INCREMENT ADDRESS DEVICE FAILED Voc Vpp 5 0 290127 9 Figure 5 Quick Pulse Programming M Algorithm Quick Pulse ProgrammingTM Algorithm Intel s 27 128 EPROM is programmed using the Quick Pulse Programming Algorithm developed by Intel to substantially reduce the thr
29. existe un error se debera presionar el PB1 para reiniciar el proceso Si no existi ning n error el grabador checar si la EPROM ha sido copiada en su totalidad solo para EPROMs 27512 que son de 64K y si es as el grabador regresara al inicio del proceso mostrando el tipo de EPROM seleccionado de lo P GINA 39 PROYECTO TERMINAL o GR ABADOR DE EPROMs AUT NOMO contrario se pedir al usuario que inserte la EPROM fuente nuevamente y todo el proceso anterior se repetir hasta copiar completamente contenido de la EPROM El hecho de que solo se use un socket se debe a la intenci n de ahorrar espacio y tiempo ya que todo lo que se lograr a con 2 sockets es posible realizarlo con uno solo aunque para mayor comodidad del usuario seria mejor imp ementar un segundo socket pero esto queda para mejoras posteriores Si se eligi en el men principal la opci n de trabaja en modo dependiente se mostrara una E que indica E spera un caracter del puerto serial En este momento se deber correr el programa para inrtefazar la P lt con el grabador Este programa muestra un men con las opciones de ARCHIVO Abrir i Guardar como Cargar al buffer EPROM Programar Verificar copia Cargar a buffer Imprimir BUFFER Editar Imprimir AYUDA Acerca de Manual La opci n Abrir del men ARCHIVO abre un archivo con informaci n en HEX y lo alista para Cargario al buffer del grabador
30. initial PGM pulse s is one millisec ond which will then be followed by a longer overpro gram pulse of length 3X msec X is an iteration coun ter and is equal to the number of the initial one milli second pulses applied to a particular location be fore a correct verify occurs Up to 25 one millisec ond pulses per byte are provided for before the over program pulse is applied The entire sequence of program pulses and byte verifications ls performed at Vcc 6 0V and Vpp 12 5V When the inteligent Programming cy cle has been completed ail bytes should be com pared to the original data with Vcc Vpp 5 0V A intel 27 64 87 64 64K 8K x 8 CHMOS PRODUCTION AND UV ERASABLE PROMS m CHMOS Microcontroller and m High Performance Speeds Microprocessor Compatible 150 ns Maximum Access Time 87C64 Integrated Address Latch 8 New Quick Pulse Programming Universal 28 Pin Memory Site 2 line Algorithm 1 second programming Control m Available in 28 Pin Cerdip and Plastic m Low Power Consumption DIP Package and 32 Lead PLCC 100 LA Maximum Standby Current Package m Noise Immunity Features See Packaging Spec Order 231369 110 Vcc Tolerance Maximum Latch up Immunity Through EPI Processing Intel s 27C64 and 87C64 CHMOS EPROMs are 64K bit 5V only memories organized as 8192 words of 8 bits They employ advanced CHMOS 11 E circuitry for systems requiring low power high perf
31. pines De la relaci n anterior se observa que para los pines 20 y 27 no existe un problema complicado para las diferentes se ales seg n el tipo de EPROM en comparaci n con los pines restantes Para estos ltimos fue necesario dise ar un circuito que pudiera P GINA 7 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO ser controlado directamente por el programa para proporcionar la se al necesaria por lo cual se desarrollo el circuito de la figura 1 en base a el circuito de la figura 2 en el cual se observan las consideraciones de corriente y de voltaje que utilizan reguladores de voltaje LM317 entre otros elementos FIGURA 1 CIRCUITO PARA CONTROLAR LOS PINES DEL SOCKET 12V 28 DEL SOCKET 2210 li Tr 34800 7407 lt E z PB3 B e 2222 282907 4700 furl PIN 26 DEL SOCKET tof 22142 12V 282222 A aay 2 2N2907 4700 I CP 2 1 4V 1200 sf 1VF do s PIN 1 DEL SOCKET 7407 lt PB0 E 19600 7407 PR1 B 3 i 34800 7407 z PB2 B 2N 2222 282907 4700 Cp T PB7A 22 DEL SOCKET 5V Hm H 0 010F iain 66511 7407 x 0 1500H 1860 7407 34800 7407 T 13 PC2 B 41201 7407 5 3 292222 2907 lt 2N 4709 Cut Y PIN 23 DEL SOCKET 22142 T 0 019F 66512 7407 lt PB4 B 41200 7407 lt lt PR6 B 282222 lt 2N2907 4700 Er eT P GINA 8 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO
32. se encuentran localizadas las instrucciones que permitir n que dicho sistema realice las funciones para las cuales fue dise ado dicho lugar es una memoria Debido a que seria muy costoso mantener el sistema siempre funcionando con su programa en una memoria RAM Random Access Memories ya que estas pierden su informaci n al dejar de existir un voltaje de alimentaci n surgen memorias que permiten mantener informaci n aun sin que exista alguna se al de alimentaci n dichas memorias son llamadas EPROM Erasable Programmable Read Only Memories Estas memorias como ya se comento mantienen datos en ellas aun sin voltaje de alimentaci n presente permitiendo apagar el sistema cuando no se est utilizando en contraste con lo anterior la forma en la cual se les introduce la informaci n es diferente que en una RAM convencional Para grabar informaci n en una memoria EPROM se hace necesario un sistema especial que nos ayude a realizar esta tarea llamado GRABADOR o tambi n PROGRAMADOR Para grabar las memorias EPROM se hace necesario mandarle no solo direcciones y datos sino tambi n otras se ales de control tales como Chip Enable CE Output Enable OE y Programming Pulse Voltage Vpp siendo este ltimo un voltaje alto normalmente 25 V o 21 V o 12 5 V seg n el tipo de EPROM comparado con l gica TTL 0 V y 5 V Los grabadores de EPROM mas conocidos son aquellos que dependen de una computadora funciones del microprocesador memo
33. these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability RECOMMENDED OPERATING CONDITIONS Voltage referenced to Vss Ta to 70 C Ground input High Voltage input Low Voltage NOTE Vit Min 3 0V for 20 ns pulse CAPACITANCE T 25 C f 1 0 MHz Input Capacitance Vin OV Output Capacitance NOTE 0V This parameter is sampled and not 100 tested intel 2716 16K 2K x 8 UV ERASABLE PROM g Fast Access Time m Pin Compatible to Intel Universal Site 2716 1 350 ns Max EPROMs 2716 2 390 ns Max 2716 450 ns Max m Simple Programming Requirements Single Location Programming m Single 5V Power Supply Programs with One 50 ms Pulse m Low Power Disslpation B inputs and Outputs TTL Compatible Active Power 525 mW Max During Read and Program Standby Power 132 mW Max Completely Static The Intel 2716 is a 16 384 bit ultraviolet erasable and electrically programmable read only memory EPROM The 2716 operates from a single 5 volt power supply has a static standby mode and features fast single address programming It makes designing with EPROMs fast easy and economical The 2716 with its single 5 volt supply and with an access time up to 350 ns is ideal for use with
34. v put LOW Volt oL Vec MIN lo 8 0 mA Viy 20V lt o 4 B a MAX V 27V Voc MAX Viy 10 V he Input LOW Current Vec MAX Vy 0 4 V Output Short Circuit Current Note 3 Voc MAX Vout 0 V Supply Current HIGH Vec MAX Vin OV Supply Current LOW Vec MAX inputs Open AC CHARACTERISTICS TA 25 See Page 273 for Wavetorms TEST CONDITIONS SYMBOL PARAMETER 50 15 pF NOTES 1 For conditions shown es MIN or MAX use the appropriate value specified under recommended operating condinons tor the applicable device type 2 Typical limits are at Voc 50 V 25 C 3 Not more than one output should be shorted at a ime 541 504 7741 504 INVERTER PART NUMBERS TEMPERATURE T54LSO4X 559 to 125 C T74LSO4X 0 C to 70 C X package type D for Ceramic Dip B for Plastic Dip See Packaging Information Section for packagesavailabla on this product DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE unless otherwise specified SYMBOL PARAMETER DM TEST CONDITIONS Note 1 Input HIGH Voltage Guaranteed Input HIGH Voltage Input LOW Voltage Guaranteed Input LOW Voltage Input Clamp Diode Voltage Vcc MIN AN 18 mA Output HIGH Voltage Vcc MIN toy 7400 pA Viy YiL MIN Ig 40 Vy 20V Output LOW Vol Q ses A
35. 0 0 Os 04 O7 sun 1 4 12 ABSOLUTE MAXIMUM RATINGS above which the usetul may be impaired Storage Temperature 65 C to 150 C Temperature Ambient Under Bias 55C to 125 C GND Pinto Pin Potential to Ground Pin 9 5 V to 7 0 V input Voltage dc u5V to 15V input Current de 30 mA to 5 0 mA CONNECTION Voltage Applied to Outputs Output HIGH 0 5 Vto 10V Output Current dc Output LOW 50 mA Either Input Vokage limit or input Current hmat sufficient to protect the inputs PINNAMES LOADING Note a Do D Data Inputs 0 5 UL 0 25 ULL LE Latch Enable Active HIGH 0501 0 25 U L input OE Output Enable Active LOW 0501 0 25 1 input Oo Or Outputs Note b 65 25 UL 15 7 5 UL NOTES a V TTL Unit Load U L lt 40 4A HIGH 1 6 mA LOW b The output LOW drive factor is 7 5 U L for Military 154 and 25 U L for Commercial 174 Temperature Ranges The Output HIGH drive factor is 25 U L for Military 54 and 65 UL for Commercial 74 Temperature Ranges LOGIC DIAGRAM Pin Numbers MOTOROLA SEMICONDUCTOR A TECHNICAL DATA UNIVERSAL SWITCHING REGULATOR SUBSYSTEM UNIVERSAL SWITCHING REGULATOR SUBSYSTEM The A73S46 is monolithic swilcinng regulator subsystem providing al active functions necessary for a switching regulator SILI
36. 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing EXPRESS OPTIONS 27128A Versions Packaging Options SpesdVersioe Cerdp D o 5 0 eee 1 Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for Voc Standby Current mA Voc Active Current at High Temperature mA 230849 10 Voc 5 GNO R 1tkn Vss GND LEE Voc Active Curontima t Vi OE CE Va Vep Voc 85 C Ais 230849 11 Binary Sequence from Ag to A413 Burn in Blas and Timing Diagrams Quick Pulse ProgrammingTM Algorithm For Plastic EPROMs Intel s Plastic EPROMs can now be programmed us ing the Quick Pulse Programming Algorithm devel Oped by Intel to substantially reduce the throughput time in the production programming environment This algorithm allows Plastic devices to be pro grammed in under two seconds almost a hundred fold improvement over previous algorithms Actual programming time is a function of the PROM pro grammer being used The Quick Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri fication to determine when the address byte has ADORESS FIRST LOCATION Voc 6 25 Vpp 12 75V PROGRAM ONE 100 4s PULSE INCREMENT X 27128A 230849 9 Figure 4 Quick Pulse P
37. 0008 MOV POP A MOVX DFETRA MOV A OFEH CJNE AD 2NEXT MOV CJNE CNEXT P GINA 28 PROYECTO TERMINAL GRABADOR DE EPROMs AUTONOMO 0279 2169 22 RET 0280 216A 0281 216A CNEXT INC DPTR 0282 216B E583 MOV ADFH 0283 216D 54 CF ANL A 11 C1111B 0284 216F F583 MOV 0285 2171 2152 AJMP CREAL 0286 2173 22 RET 0287 2174 0288 2174 este procedimiento inicializa los vol a es que se mandan al socket 0289 2174 5 volts 0290 2174906000 PWRUP MOV DPTREeFPAS 0291 21777480 MOV A amp C 0292 2179 FO MOVX DFTRA 0293 217A 90 40 01 MOV DPIX PB1 0294 217D 7417 MOV 0295 217F FO MOVX DPTRA 0296 2180 90 60 01 MOV DPTR PB2 0297 2183 74 A6 MOV A OASH 0298 2185 MOVX DFIRA 0299 2186 90 60 02 MOV DPTS PC2 0300 2189 740E MOV AHOE 0301 218B FO MOVX DPTRA 0302 218C 7590 FF MOV 5 0303 218 31 92 ACALL DL O 0304 2191 22 RET 0305 2192 id id RETARDO DE 50 milisegundos PARAR RARA te A Akk 0306 2192 7B 32 DLYSO MOV R3 32K 0307 219431 99 DLSO DELAY1 0308 2196 DB FC DJNZ R3D G 0309 2198 22 RET 0310 2199 0311 2199 pr retardo de 1 milisegundo trees 0312 2199 7400 DELAY1 MOV 0313 219 05 DL1 DJNZ A DL1 0314 219 05 DL2 DJNZ 12 0315 21 1 22 RET 0316 21A2 031 7 21 A2 oli RETARDO LE X microsegundos dede e kaa 0318 21 2 7 DLY20 MOV R3 H0A t 0319 21A4DB FE DLY
38. 0160 0161 0162 0163 0164 0165 0166 GRABADOR DE EPROMs AUT NOMO 2075 EO LOOPE MOVX A DPTR 2076 71 4A ACALL TRANS 2078 A3 INC DPTR SIGUIENTE DATO 2079 D9 FA DJNZ R1 LOOPE 207 01 3B MENU_DEP 207D 2070 ces 207D RECIBE EL CONTENIDO DE UN PROGRAMA DE LA PC AL BUFFER DEL KIT 2070 7158 PROG ACALLRECIBE RECIBE EL TOTAL DE BYTES DE CODIGO 207F FB MOV R3A 2080 71 58 ACALLRECIBE CONTIENE BYTE ALTO 2082 FA MOV R2A R2 CONTIENE BYTE BAJO 2083 20837158 LOOPCAP ACALLRECIBE RECIBE 2BYTES DE DIRECCION 2085 F5 83 MOV 2087 71 58 ACALL RECIBE 2089 F5 82 MOV 208B 71 58 ACALL RECIBE RECIBE DATO 208D FO MOVX DPTR A 208E 1A DEC R2 208F BA FF F1 CJNE R2 HOFFH LOOPCAP 2092 1B DEC R3 2093 BB FF ED CJNE R3 A0FFH LOOPCAP 2096 01 3B AJMP MENU DEP WRRS 2098 2008 M 2098 RUTINA DE MENU EN MODO INDEPENDIENTE 209851ED MENU IND CONF ESCR 209A 31 A7 ACALL PWRDWN 209C 74 6F MOV A XG 209E 71 BE ACALL IMPRIME 20A0 71 F6 ACALL LED 20A2 31 A7 PWRDWN 20A4 71 66 ACALL CHECK_PBS 20A6 B4 40 1A CJNE A 80 0H iNICIO GRAB 20A9 7459 MOV A XCMAY 20AB 71 BE ACALL IMPRIME 20AD 71 F6 ACALL LED 20AF 31 A7 ACALL PWRDWN 20B1 71 66 ACALL CHECK PBS 20B3 B4 40 12 CJNE A 040H INICIO_COMP 20B6 74 3C MOV 20B8 71 BE ACALL IMPRIME 20BA 71 ACALL LED 20BC 31 A7 ACALL PWRDWN 20BE 71 66 ACALL CHECK PBS 20C0 B4
39. 201 DJNZ RS3DL O320 21A622 RET O321 21A7 0322 21 POWER DO JARA ook OI RON K o ROCA ERE 0323 21A7 aqui se mandan voltajes de O volts asi como datos y direcciones tanibien 0324 214794000 PWRDWN MOV DPTR HPA1 0325 21AA 7400 MOV A J 0326 21AC FO MOVX 0327 21AD 90 60 02 MOV DPT amp PC2 0328 21BO 740E MOV AHOE 0329 21B2 FO MOVX QU 0330 21B390 60 01 MOV PB2 0331 21 674 6 MOV A OAS 3 0332 21B8 FO MOVX DF RA 0333 21B9 90 40 01 MOV DPT PB1 0334 21 74 8 MOV 254 0335 21 FO MOVX DF RA 0336 21BF 90 60 00 MOV DPT PAD 0337 21 2744 MOV A 4Eii 0338 21 4 MOVX QLITRA 0339 21C5 22 RET 0340 21C6 0341 21C6 CAMARERA ERAS RUTINA PARA LE PROM A cansa LLLI 0342 21C6 ESTA RUTINA LEE EL CONTE CO DE UNA LOCALIDAD 0343 21C6 EL DPTR CONTIENE LA LOCA LIGADA SER LEIDA 0344 21C6 EL RESULTADO ES REGRESA C EN EL ACC 0345 21C6 0346 2106858332 MOV ADR1 4 0347 21C9858231 MOV 22 0348 21CC 0349 21 21 AJMP RD64 0350 21CE P GINA 29 PROYECTO TERMINAL 0351 21CE 0352 21CE 0353 21 5 32 RD64 0354 21 0 2 5 0355 2102 20 0356 2105 0357 2105 90 4001 11164 0358 2108 D2 E3 0359 21DA 543 0360 21DC FO 0361 2100 21 E7 0362 21DF 0363 210 90 4001 A11H64 0364 21 2 2 0365 21E4543F 0366 21 6 0367 21E7 0368 21E790
40. 3 223 22 0414 223F 0415 223 74 76 PERR 0416 2241 71 BE 0417 224371 81 0418 2245 71 81 0419 2247 7486 0420 2249 71 BE 0421 224B 71 81 0422 224D 71 81 MOV STAR MOV STA MOV DPL i ARTO MOV DPH ART1 ACALL CONF SCR ACALL TDF MOVX A L TR ACALL WR 3OM JB STATO PERR MOV Ado CJNE ADF 2NEXT MOV CJNE A Di EXT ACALL PW WN RET MOV ACALL IMP HE ACALL DE ACALL lt MOV ACALL x gt DE GRABADOR DE EPROMs AUT NOMO P GINA 30 PROYECTO TERMINAL 0423 224F 71 66 ACALL CHE PBS 0424 2251 B480 CJNE 0 gt PERR 0425 225422 0426 2255 0427 2255 INC DPTR 0428 2256 41 26 AJMP PAG 7 0429 2258 22 RET 0430 2259 0431 2259 RARAS RUTINA PARA ESC i R EPROM AA 0432 2259 ESTA RUTINA ESCRIBE EL IDO DEL BUFFER A UNA OCALIDAD 0433 2259 EL DPTR CONTIENE LA LOCAL LA SER ESCRITA 0434 2259 EL VALOR A ESCRIBIRSE ESTA EL 0435 2259 0436 2250858332 WRPROM MOVADR1 0437 225C 858231 MOV Di 0438 225F F539 MOV 0439 2261 0440 2261 41 63 AJMP WR64 0441 2263 0442 2063 RH 0443 2263906000 WRG64A MOV DPTR amp E 0444 2266 7481 MOV 08 0445 2268 MOVX QDF 0446 2269 90 6001 MOV DPTR amp 32 0447 226C 742D MOV 20 0448 226E FO MOVX DP 0449 226F 90 6002
41. 4000 RDNX64 0369 21EA ES 31 0370 21EC FO 0371 21ED 90 60 02 0372 21 0740 0373 21F2FO 0374 21F390 60 01 0375 21F6 74 26 0376 21 8 0377 21F990 60 00 0378 21 7483 0379 21FE FO 0380 21FF 90 4002 ARRRA RAM NAAA RA RRA RARA EPROM 27 MOV A ADR1 SETBAS JB AB AIS MOV DPTR FS ANL 001 11B MOVX QDP i RDIN 54 MOV DPTR 4P2 CLR A3 ANL A amp 001 1 11B MOVX DP MOV DPTR i MOV A ADF MOVX MOV DPTR st 2 MOV MOVX DP F MOV DPTR 2032 MOV A 26 MOVX QDP FA MOV DPTR A2 MOV 83 MOV 51 0381 220231 2 ACALL DLYZ 0382 2204 EO MOVX 07 78 0383 2205 CO EO PUSH 0384 2207 90 6000 MOV DPTR FA2 0385 220A 7481 MOV A 81 0386 220C 0387 2200 DO EO 0388 220 85 32 83 MOV 2 2 0389 22128531 82 MOV DPL 0 0390 2215 22 RET 0391 2216 0392 2216 0393 2216 ESCRIBE DEL BUFFER A LA EPROM 5555 0394 2216 PROGRAMA EL SOCKET SEGL i EPROM 0395 221651 ED ACALL CONF 52 28 0396 2218 31 74 ACALL PW 0397 221A 753300 PCMD1 0398 2210 753400 0399 2220 85 33 82 0400 2223 85 3483 0401 2226 0402 222651 ED PAGAIN 0403 2228 71 13 0404 222A 0405 2228 71 1E 0406 22205159 0407 222F 2001 0408 2232 74 FF 0409 2234B5821E 0410 2237 740F 0411 2239 BS 83 19 0412 223C 31 7 041
42. 5 El led 1 se ha colocado en consideraci n a que existiera a conexi n al puerto serial de una PC Computadora Personal para indicar en cual de los dos modos se est operando modo local Copia de EPROM a EPROM sin necesidad de una PC Modo Remoto Copia de un archivo en c digo maquina en una PC a EPROM v a el puerto serial de la PC Los otros dos leds Contrapuestos indicar n al usuario i momento en que se estan aplicando los voltajes necesarios a la EPROM para evitar que est sea removida en ese momento el led rojo indicara que se esta leyendo o escribiendo a la EPROM y el led verde indicara el momento en el que se puede quitar o poner la EPROM El PB2 Push Botton 2 y el PB1 servir n como teclado para que el usuario realice la selecci n del tipo de EPROM asi como el proceso de programaci n El PB2 servir como selector en los men s y submenus y el PB1 una se al para aceptar la opci n elegida por PB2 ENTER El display indicar en cada momento al usuario las diferentes etapas que conforman el proceso de grabar EPROMs desde seleccionar el modo de trabajo Dependiente o Independiente Si se esta en modo independiente seleccionar el tipo de EPROM con la que se va a trabajar y el estado en el que se encuentre el proceso de copia Selecci n lectura programaci n verificaci n errores etc FUNCIONAMIENTO En base a la explicaci n de los bloques principales a continuaci n se bosqueja el funcionamiento
43. 5V to 12 5V on address line A9 of the EPROM Two identifier bytes may then be se quenced from the device outputs by toggling ad dress line AO from Vi to All other address lines must be held at Vi during the intgligent Identifier Mode Byte 0 AO Vj represents the manufacturer code and byte 1 AO Vi the device identifier code These two identifier bytes are given in Table 1 intel 2764A 64K 8K x 8 UV ERASABLE PROMs Fast Access Time HMOS Il E m inteligent Identifier Mode 180 ns Cerdip D2764A 1 Industry Standard Pinout JEDEC m Moisture Resistant Approved 28 Lead Package m Two line Control See Packaging Spec Order 231369 The Intel 2764A is a 5V only 65 536 bit electrically programmabie read only memory EPROM The 2764A is fabricated with intel s HMOSII E technology which significantly reduces die size and greatly improves the device s performance power consumption reliability and producibility The 2764A provides access times to 180 ns 2764A 1 This is compatible with high performance microproces sors such as Intel s 8 MHz APX 186 allowing full speed operation without the addition of WAIT states The 2764A is also directly compatible with the 12 MHz 8051 family Two line control and JEDEC approved 28 pin packaging are standard features of intel higher density EPROMs This assures easy microprocessor interfacing and minimum design efforts when upgrading adding or choosing
44. 631 2395 82 DISPLAY PUSH DPL ESCRIBE EN EL DISPLAY EL CONTENIDO DEL 0632 2397 C083 PUSH DPH AC IMULADOR EN DIGITOS HEXADECIMALES 0633 2399 CO EO PUSHA 0634 2398 540F ANL A OFH 0685 239D 71 AB ACALL GET 7 Sc ESCRIBE EL BYTE BAJO O636 239F DO EO POPA 0637 23A1 C4 SWAP A 0638 23A2540F ANL A amp OF Hi P GINA 33 PROYECTO TERMINAL 0639 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 0670 0700 0701 0702 0703 0704 0705 0706 0707 0708 0709 0710 GRABADOR DE EPROMs AUT NOMO 23A4 71 AB ACALL GET7SC SE ESCRIBE EL BYTE ALTO 23A6 DO 83 POP DPH 2348 DO 82 POP DPL 23AA 22 RET 23AB MORA k k k de e c e e e FORO RRA AR RON AAA amp k A RO OOOO OOO e si e e ice e e oe e e e 23AB REGRESA EL CODIGO DE SEGMENTOS DEL ACUMULADOR 23AB 23AB 82 GET7SC PUSH DPL 23AD CO 83 PUSH DPH 23AF CO FO PUSH B 23B1 90 24 09 MOV DPTR TABLA 23B4 93 MOVC A A DP TR GARGA DATO DE 7 SEGMENTOS 23B5 71 BE ACALL IMPRIME 23B7 DO FO POP B 23B9 DO 83 DPH 23BB DO 82 POP DPL 23BD 22 RET 23BE 23BE 23BE SANS AREAS ek deck dodo tert ee eK A AAA OR OOOO CIO ere ek 23BE manda al display el contenido del acumulador cargado antes de llamar 23BE este procedimiento normalmente con algun codigo establecido en ia 23BE etiquetas 23 82 PUSH DPL 23C0 CO 83 PUSH DPH 23C2 CO EO PUSH A 23C4 90 60 00 MOV DPTR 4PA2 23C7 78 0
45. 7128A is a 5V only 131 072 bit ultraviolet erasable and electrically programmable read only memo ry EPROM The 271284 is fabricated with Intel s HMOSII E technology which significantly reduces die size and greatly improves the device s performance reliability and manufacturability The 27128A is currently available in two different package types CERDIP packages provide flexibility in prototyping and R amp D environments where reprogrammability is required Plastic DIP EPROMS provide opti mum cost effectiveness in production environments Intel s new Quick Pulse Programming Algorithm enables these Plastic EPROMS to be programmed within two seconds Programming equipment that takes advantage of this innovation will electronically identity the EPROM with the help of the intgligent Identifier and rapidly program it using a superior programming method The intgligent Programming Algorithm may be utilized in the absence of such equipment and is used to program CERDIP devices The 271284 is available in fast access times including 150 ns 27128A 1 This ensures compatibility with high performance microprocessors such as intel s 8 MHz 80186 allowing full speed operation without the addition of WAIT states The 271284 is also directly compatible with the 12 MHz 8051 family HMOS is a patented process of Intel Corporation y DATA OUTPUTS cc o gt 0 0 Veep o jyhNissHs OUTPUT ENABLE POM CHIP ENABL
46. 8 8 hour 125 C dynamic burn in using Intel s stan dard bias configuration This process exceeds or EXPRESS Options meets most industry specifications of burn in The standard EXPRESS EPROM operating temperature 27 64 87 64 Versions range is O C to 70 C Extended operating tempera Packaging Options ture range 40 to 85 C EXPRESS products are also available Like all Intel EPROMs the EX Speed PLCC PRESS EPROM family is inspected to 0 1 electri Versions cal AQL This may allow the user to reduce or elimi nate incoming inspection testing READ OPERATION D C CHARACTERISTICS Electrical Parame of EXPRESS EPROM products are identical to standard EPROM parameters except for Parameter Voc Standby Current mA Vcc Active Current mA Vcc Active Current at TTL High Temperature NOTE 1 See notes 4 and 6 of Read Operation D C Characteristics 7 22 27064 67 64 a 290000 14 Binary Sequence from Ag to A12 290000 13 OR 50 R 1K 5V Vpp 45V GND 0V CE 33 3 KHz 5 Burn in Bias and Timing Diagrams INCREMENT ADDRESS ADORESS FIRST LOCATION Vec 6 25V Vpp 12 75V PROGRAM ONE 100 us PULSE INCREMENT X 27 64 87 64 DEVICE FAILED Figure 5 Quick Pulse Programming Algorithm Quick Pulse ProgrammingTM Algorithm Intel s 27C64 and 87C64 EPROMs can now be pro grammed
47. 8 MOV 23C9 F5 FO ETQ4 MOV BA 23CB 54 80 ANL A 4EOH 23CD 03 RR 23CE 03 RR A 23CF 44 10 ORL 23D1 FO MOVX DPTRA 23D2 54 EF ANL A O0EFH 23D4 FO MOVX DPTRA 23D5 ES FO MOV AB 23D7 23 RL A 23D8 D8 EF DJNZ RCET 4 23DA 7400 MOV A HOOF 23DC DO EO POP A 23DE DO 83 POP DPH 23E0 DO 82 DPL 23E2 22 RET 23E3 EARNER ION RR ODER IE 23E3 rutina que permite encender a led rojo 23E3 CO EO LED1 PUSH A 23 5 CO 82 PUSH DPL 23E7 CO 83 PUSH DPH 23E9 90 60 00 MOV DPF R PA2 23EC 7480 MOV 5 80 23EE FO MOVX DF TRA 23EF 83 23F DO 82 POP DPL 23F3 DO EO POP 23F5 22 RET 23F6 QE AP SM KA 4 Be He BT RTT IIS RARA A AAA a 4 amp amp e K fk 9 dk Yc sc ie fe he fe KKM ee Zar rutina para encender led 2 led verd 23F6 CO EO LED2 PUSH A 23F5 082 PUSH DPL 23FA CO 83 PUSH DPH 23FC 90 60 00 MOV DPTR PA2 23FF 74 40 MOV 4 2401 FO MOVX DPTRA 2462 DO 83 2404 0082 GF 2406 DO EO POP A 240 22 RET 2405 DUERME e Sra P RAEE 2409 TABLAS DE DATOS 2409 gfedcba 2409 DF TABLA BYTE 110111118 P GINA 34 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO 0711 240A 86 BYTE 100001198 i 0712 2408 BYTE 1011 01 B 2 0713 240C AF BYTE 10101111B 3 0714 240D EG BYTE 11100110B 4 0715 240E ED BYTE 111011018 5 0716 240F FD BYT
48. 9 4 MOV RIA 0041 203 54 80 A 80H 0042 202 03 0043 2035 03 RR A 0044 2055 44 10 ORL A iOH 0045 205 FO MOVX DPTR A 0046 2039 54 EF ANL A CEFH 0047 2038 MOVX DPTRA 0048 2022 E9 MCV AR1 0049 20 0 23 RL A 0050 203 D8 F1 DINZ RO ETQ4 0051 204 22 RE 0052 204 0053 204 FO MOVX DPTRA 0054 204222 RET 0055 204 0056 204 1 ORG 1 OBLIGA AL ENSAMB ADOR GENERAR 0057 204 00 20 RUN WORD INICIO POR SEPARADO UNA LINEA DE CODIGO 0058 204 END PARA LA DIRECCION DE ARRANQUE 0059 204 0060 2045 tasm Nun ver of errors PROYECT TERMINAL GRABADOR DE EPROMs AUT NOMO PROGRAMA QUE MANDA LAS PALAE RAS DE CONTROL A LOS 0001 000 PUERTOS DE LAS PPIs 0002 0000 PARA MONITOREAR LOS VOLTAJES NECESARIOS PARA PROGRAMACION DE EPROM 0003 0006 INCLUDE C EQUS TXT 0162 0020 LIST 0004 LIST 0005 0000 0006 2060 ORG 2000H 0007 200 0008 2000906003 INICIO MOV DPTR PCTRL2 0009 206 74 88 MOV A 88H 0010 20 FO MOVX DPTR A 0011 2005 90 40 03 MOV DPTR PCTRL1 0012 2009 74 80 MOV A 80H 0013 2003 FO MOVX DPTR A 0014 20 0015 2008 0016 20C 74 DF REGRESO MGV A XCERO 0017 206 11 48 ACALL IMPRIME 0018 2019 0019 201 90 60 02 ETE MOV DPTR PC2 0020 2015 EO MOVX A DPTR 0021 2014354 CO ANL A OCOH 0022 20 B4 80 12 CJNE A 080H 5 0023 201 74 86 MCV A XUNO 0024 2018 11 48 ACALL IMPRIME 0025 2010 74 AA MOV 0 0026 207 90 40 00 MOV DPTR
49. ABAR se muestra en el diagrama de flujo 4 A continuaci n de detalla el proceso de GRABAR Al iniciar el proceso de programacion el usuario debera establecer el tipo de EPROM con la que va a trabajar esto se realiza en base a una tabla de equivalencia la cual se selecciona con el PB2 esta tabla inicia con el tipo 0 y va aumentando hasta agotarla y vuelve a iniciar en forma c clica la tabia es la siguiente selecci n EPROM selecci n EPROM Vpp 2716 5 271128 21V 2732 6 27128 12 5 2732 7 27256 125V 2764 8 27512 125V 2764 Despu s de elegir el tipo de EPROM se presiona el para iniciar el proceso en este punto se pedira que se cargue la EPROM fuente mediante la aparici n de una se al en el display F a continuaci n se vuelve a presionar el PB1 y el grabador leer datos de la EPROM fuente segun el tama o de la EPROM durante este proceso estar encendido el led rojo Una vez lleno el buffer aparecera otra se al en el display d indicando que se cargue la EPROM destino existiendo la posibilidad de elegir la opci n de salir presionando PB2 para elegir c y despu s 1 para salir Si se elige d y ya se cargo la EPROM destino se presiona nuevamente el PB1 el grabador proceder a cargarla con la informaci n del buffer mientras vuelve a encender led rojo Si existiera un error el display mostrara alternadamente una y un n mero 1 el cual indicara que
50. BUS 4 PO PC PC PC PC PAPA MODE 1 8 A 1 0 a o PB PB CONTROL CONTROL PA PAS OR o OA 1 0 MODE 2 8 A 1 0 8 8 DIRECTIONAL PB 8 PA PA CONTROL 231208 6 Figure 5 Basic Mode Definitions and Bus Interface CONTROL WORD PORT CILOWER Y INPUT 0 OUTPUT PORTS Y INPUT O OUTPUT MOOE SELECTION 0 MODE 0 1 MODE 1 PORT C UPPER 125 INPUT 0 OUTPUT PORTA INPUT 9 OUTPUT MODE O MODE SELECTION oo SET FLAG ACTIVE 231308 7 Flgure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical I O approach will surface The design of the 8255A has taken into account things such as etfi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the max mut use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C cam be Set or Reset using a single OUTput instruction This feature ro duces software requirements in Control based appt cations 3 104 CONTROL WORD BiT SET RESET 0 1 0111011 011186 010101311 BIT SET RESET FLAG 1 O ACTIVE 231308 8
51. CON MONOLITHIC system The device consists of a temperature compensated vo t INTEGRATED CIRCUIT reference contralted duty cycre oscillator with an active cur rent limit circuit compararar hgh current and high voitage out put switch capable of 1 5 A and 42 V pinned out power dinde and an uncommitted operational aruplifier which be powered up or down independent of the supp y The switching output 1 t SUFFIX can drive external NPN or PNP transistors when voltages greater CERAMIC PACKAGE than 40 V ar currents excess of 1 5 A are required Some of CASE 620 the features are wide supply voltage ranqa tow standby current niah etf iciency and low drift The 4A78S40 is available in corn mercial 0 C to 70 automotive 40 C to 85 C and militiey 55 tu 125 C temperature ranges Some of the applications include use in step up step down SUFFIX PLASTIC PACKAGE and inverting regulators with extremely good results obtained in CASE 648 hattery operated systems e Outp Adjustabte from 1 25 V to 40 V e Pek Output Current of 1 5 A Without Externa Transistor e 80 d3 Line and Load Regulation e Operation Irom 2 5 V to 40 v Supply PIN CONNECTIONS e Low Standby Current Drain High Gain Hign Output Current Uncommitted Amo BLOCK DIAGRAM Timing lok Driver Swich Gad Capacitor VCC Sense Collector Collect Copa tor Nor rp Compras Na v
52. DC a DC lo usamos para generar los 30 volts que necesitan en la entrada de los reguladores LM317 Adem s de los circuitos integrados mencionados anteriormente se utilizaran algunas compuertas l gicas tales como inversores NAND OR etc cuya elecci n depender del uso inmediato que se proyecte as como algunos otros componentes de acuerdo a la hoja de especificaciones para el buen funcionamiento e os circuitos intel PRELIMINARY MCS 51 8 BIT CONTROL ORIENTED MICROCOMPUTERS 8031 8051 8031AH 6051AH 8032AH 8052AH 8751 8751 12 8751 88 a High Performance HMOS Process Boolean Processor internal Timers Event Counters Bit Addressable RAM 8 2 Level interrupt Priority Structure Programmable Full Duplex Serial Channel e 32 I O Lines Four 8 Bit Ports m 111 Instructions 64 Single Cycle a 64K Program Memory Space m 64K Data Memory Space Security Feature Protects EPROM Parts Against Software Piracy The MCS 51 products are optimized for control applications Byte processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM The instruction set provides a convenient menu of 8 bit arithmetic instructions including multiply and divide in structions Extensive on chip support is provided for one bit variables as a separate data type allowing direct bit manipulation and testing in control and logic systems that require Boolean proce
53. DEL BUFFER DEL GRABADOR RECIBE UN ARCHIVO Y LO CARGA EN EL BUFFER COPIA EL CONTENIDO DEL BUFFER ALA EPROM COPIA EL CONTENIDO DE LA EPROM AL BUFFER COMPARA EL CONTENIDO DE LA EPROM CON Ei BUFFER CHECA SI LA EPROM ESTA BORRADA GRABADOR DE EPROMs AUT NOMO P GINA 20 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO DIAGRAMA DE FLUJO 4 RUTINA PARA GRABAR EN MODO INDEPENDIENTE habilitar hardware pitipo pedir EPROM fuente EPROM borrada escribir en EPROM DIFERENTES IGUALES P GINA 21 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO Las rutinas de grabado para cada uno de los tipos de EPROMs permitidos en este grabador se obtuvieron de algunos diagramas de flujo propuestos en el manual de INTEL de MEMORY en el diagrama de flujo 5 se muestra un algoritmo de grabaci n QUICK PULSE el cual funciona de la siguiente manera Seleccionar direcci n para grabar poner voltajes de programaci n poner datos a grabarse inicializar una variable en 0 se da un pulso de programaci n de 100 microsegundos Se incrementa la variable se lee el dato grabado en la EPROM se verifica que se haya grabado correctamente si es as se monitorea si es la ltima direcci n y en caso positivo se ponen todos los voltajes en 5 volts y se realiza una comparaci n completa En caso de que no se haya grabado correctamente se checa si la variab
54. DO BEGIN CBS C PY LINEA 8 1 2 2 VAL CBS CB EC PCS HE XA PC GOTO 11 6 WRITEL N ESCRIBIENDO 1 PC ESCRIB LO PC ESCRIBE LO CB INC PC END END READLN LINEA GOTOXY 1 8 CBS PCS WRITELN DIRECCION DE ARRANQUE COPY LINEA 12 2 COPY LINEA 10 2 CLOSE F GOTOXY 1 11 WRITELT SE ESCRIBIERON HEXA BE BYTES END TERMINAL _GRABADOR DE EPROMs AUT NOMO 0001 este programa regresa el caracter que se intruiuce desde el teclado de la 0002 000 PC de de un emulador de terminal configuraco para transmitir por el 0003 puerto serie 1 0004 002 INCLUDE C EQUS TXT 0162 0000 LIST 0005 0000 LIST 0006 0000 0007 200 ORG 2000h 0008 2000 74 50 INICiO MOV A 50H PROGRAMA PUERTO SERIE EN MODO 1 0009 2027 F5 98 MOV SCON A 0010 20 0011 200 74 F4 MOV CARGA DE BAUDRATE 0012 2006 F5 8D MOV TH1 A 0013 200 4 0014 206 74 20 MOV A 20H PROGRAMA TIMER 1 EN MODO 2 0015 20 5 89 MOV TMOD A 0016 20 0017 200 74 40 MOV A 40H ARRANCA TIMER 1 0018 20CE F5 88 MOV TCON A 0019 20 C298 CLR SCON O 0020 20 0021 20 1124 RECNB ACALL RECIBE RECIBE E YTE 0022 20 0023 20 lt F599 MOV SBUF A 0024 20 5 30 99 FD WTBH JNB SCON 1 WTBH TRANSMITE ECO 0025 20 2 99 CLR SCON 1 0026 20 F599 MOV SBUF A 0027 20 3099FD WTBH1 JNB 3CON 1 WTBH1 TRANSMITE EC
55. E ce ROA LOGIC OUTPUT BUFFERS oecooer 3 vemwo L ADDRESS INPUTS 131 072 DECODER CELL MATRIX 230849 1 Figure 1 Block Diagram intel 27128A 27128 27128 2764A 2764 7 27084 2732 2716 2732A 27084 pde 52 87084 87084 230849 2 NOTE Intel Universal Site Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the 27128A Pins Figure 2 Cerdip D Plastic P DIP Pin Configurations intel EXTENDED TEMPERATURE EXPRESS EPROMS The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics EXPRESS processing is available for several densities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS ese T socto eso Noe READ OPERATION D C CHARACTERISTICS 27128A available with 168 8 hour 125 C dynamic burn in using Intel s standard bias configuration This pro cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temperature range is 0 C to 70 C Extend op erating temperature range 40 C to 85 C EX PRESS products are available Like all Intel EPROMSs the EXPRESS EPROM family is inspected to
56. E 11111101B 6 0717 241087 BYTE 100001118 0718 2411 FF BYTE 111111118 8 0719 2412 EF BYTE 111011118 0720 2413 77 BYTE 011161118 0721 2414 7C BYTE 011111008 0722 241559 BYTE 0O101 0C1B C 0723 24163E BYTE 0O0111 CB 0724 2417 79 BYTE 01111001B E 0725 2418 71 BYTE 011100018 0726 2419 0727 2419 0728 241A ORG 1 OBLIGA AL El SAMBLADOR A GENERAR 0729 241A 00 20 RUN WORD INICIO OR SEPARADO UNA LINEA DE CODIGO 0730 241C END PARA LA DIRECCION DE ARRANQUE 0731 241C 0732 241C 0733 241C tasm Number of errors O P GINA 35 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO RESULTADOS En relaci n a los avances obtenidos en el presente proyecto podemos establecer que Es posible simular la lectura y escritura al socket es decir se pueden enviar se ales para datos direcciones y control de voltajes tanto para leer como para escribir de la EPROM Se dice simular por el hecho de que no se han logrado realizar dichas funciones en forma efectiva cuando se coloca una EPROM en el socket nicamente se han verificado con una punta l gica y un mult metro Para los voltajes de control se sigue la siguiente t cnica Si se quiere tener un voltaje X en el pin Y del socket se debe enviar un O l gico a la l nea correspondiente al voltaje X del pin Y y 1 s en las dem s l neas de voltajes Esta t cnica es v lida en los pines 1 22 23 26 y 28 Por ejemplo si queremos que en el pin 22 se obtengan v
57. ERG4 MOV A X 0499 22CD 90 60 00 MOV DPTF 42 0500 22D0 7485 MOV A 85 0501 22D2FO MOVX DF 0502 22D3 90 60 00 MOV DPTE 2 0503 22D6 7481 MOV A H8S 0504 2208 FO MOVX DF 0505 2209 C201 CLR STATE 0506 22DB 85 32 83 MOV DPH lt lt S 0507 22DE 8531 82 MOV DPLe 0 0508 22E1 22 RET 0509 22 241 4 PERRGA AJMP PGMER 0510 22 4 0511 22E4 RUTINA DE EN PROGRAMACION FRO OIR RARA 0512 22E4D201 PGMERR SETB STATC 0513 22E6 85 32 83 MOV DPR X 0514 22E9 85 31 82 MOV DPL 3C 0515 22EC 22 RET 0516 22ED 0517 22ED CONFIG PPI A fu A ESCRITURA HOH 518 22ED en especial puerto C de la 1 0519 22ED CO CONF_ESCR PUSH A 0520 22EF CO83 PUSH DPH 0521 22F1 CO 82 PUSH DPL 0522 22F3 90 40 03 MOV DPTR C TRL1 0523 22F6 7480 MOV A 80 0524 22F8 FO DF A 0525 22F9 D082 POP DPL 0526 22FB DO 83 POP DPH 0527 22FD DO EO POPA 0528 22FF 22 RET 0529 2300 0530 2300 VEKERRRERNERSAR CONFIG PPLA fa LECTURA teen sna 0531 2300 especial puerto C de la PPi 0532 2300 CO EO CONF LECT PUSH A 0533 2302 C083 PUSH 0534 2304 C082 PUSH DPL 0535 2306 90 40 03 MOV DPTR r 2TRL1 0536 2309 74 89 MOV 0537 230B FO MOVX QDF 0538 230C DO 82 POP DPL 0539 230E DO 83 POP DPH 0540 2310 00 EO POPA 0541 231222 RET 0542 2313 0543 2313 a TRANSFORMA Dir EPROM A RAM RRA RRR A OSA 0544 2313 para efectos d
58. Easing Wy 24 Programmable 1 0 Pins Control Application Interface Completely TTL Compatible g Reduces System Package Count m Fully Compatible with Inte Improved DC Driving Capability Microprocessor Families m Available In EXPRESS Standard Temperature Range Extended Temperature Range 40 Pin DIP Package or 44 Lead PLCC See Intel Packaging Order Number 231369 Improved Timing Characteristics The Intel 8255A is a general purpose programmable 1 device designed for use with Intel microprocessors It has 24 1 0 pins which may be individually programmed 2 groups of 12 and used 3 major modes of operation In the first mode MODE 0 each group of 12 1 0 pins may be programmed in sets of 4 to be input or output In MODE 1 the second mode each group may be programmed to have 8 lines of input or output Of the remaining 4 pins 3 are used for handshaking and interrupt control signals The third mode of operation MODE 2 is a bidirectional bus mode which uses 8 lines for a bidirectional bus and 5 lines borrowing one from the other group for handshaking OWES Toma DATA BUT Dre 231308 2 Figure 2 Pin Configuration 231308 Figure 1 8255A Block Diagram November 1067 3 100 Order Number 231308 002 8255A FUNCTIONAL DESCRIPTION General The B255A is a programmable peripheral interface device designed for use in intel microcomput
59. GOT O2 60 1 WRITE GOT OXY 69 1 WRITE lt END prem RARAS FU N gt ON E R RO R DAKAR KKK KARA AAA RIKER LS PROCEDURE ERROR BEGIN SOUND 1000 DELAY 500 NCSOUND IND 5 ENC PROYECTOTERMINAL i4 ABADOR DE EPROMs AUT NOMO artes ARKRKKKK PROCEDI Mi ENTO SARGA kkkikkikkkkkki AKKKAKA HA MANDA AL BUFFER EL ARCHIVO SELECCIONADO SANASA KK ic cy k AAA AA KK KA KARA il PROCEDURE CARGA BEGIN CLRSC BE 0 NL 0 INITPORT ASSIGN F NOMAR RESET F WHILE NOT EOF F DO BEGIN READLA F LINEA VAL COPY LINEA 2 2 TB TE NB INC N END TBS HEXA TB ESCRIBE HI TB ESCRIE LO TB RESET PF FOR J TO NL DO BEGIN READ N F LINEA VAL 3 SOPY LINEA 2 2 NB EC VAL COPY LINEA 4 4 WINDOW 20 8 70 15 TEXTCOLOR O TEXTE CKGROUND 2 FOR TONB DO BEGIN CBS COPY LINEA 8 1 2 2 VAL CBS CB EC PCS HEXA PC GOTC Poe WRITLLN ESCRIBIENCO CBS A PCS esco A PC ESCR SE LO PC ESCR 3E LO CB INC B INC P END END VAL S COPY LINEA 12 2 MANDA DPH ESC CB CLOSE GOTO 1 5 WRITE N SE ESCRIBIERON HEXA BE BYTES y PROYE TERMINAL GRABADOR DE EPROMs AUT NOMO END PARRES REO PROCEDIMIENTO ARCHI kick coo c e k ofc o
60. INDIC NDICA SI YA SE ACTIVO LA OPCION O NO Y CUAL DE ELLAS delcicick kde ok ook sedeo hc hocce hehehe Be he hh RR IA KDE EO PROCELURE MENUE INDIC INTESER BEGIN HIGHVIDEO WINDOW 1 2 80 2 TEXTBACKGROUND O0 TEXTCOLOR 2 IF INDIc 1 THEN TEXTEACKGROUND 2 ELSE TEXTEACKGROUND O WRITE TEXTCOLOR 7 WRITE RCHIVO gt TEXTBACKGROUND 0 CLREOL IF INDIC 2 THEN TEXTBACKGROUND 2 ELSE TEXTBACKGROUND O TEXTCOLOR 2 WRITE E TEXTCOLOR 7 WRITE PROM 5 TEXTBACKGROUND O IF INDIC 3 THEN TEXTBACKGROUND 2 ELSE TEXTBACKGROUND O PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO TEXTCOLOR 2 WRITE B TEXT COLOR 7 WRITE UFFER y TEXTBACKGROUND O CLREOL IF INDIC 4 THEN BEGIN TEXTBACKGROUND 2 WRITECAD END ELSE BEGIN TEXTBACKGROUND 0 WRITECA END TEXTCOLOR 2 WRITE Y TEXTCOLOR WRITE UDA 9 TEXTBACKGROUND O CLREOL END PROCEDIMIEN O ESTADO EXARKKKARA KA K KK KA KA AAA MANEJA LA BARRA DE ESTADO AARAA ck KHARIARKA AAA RARA KIA KARA PROCEDURE ESTADO BEGIN WINDOW 1 25 80 25 GOTOXY 1 1 WRITE ARCHIVO CLREOL GOT OXY 10 1 WRITE NOMAR GOTO 25 1 WRITE TIPO DE EPROM CLREO GOTOXY 39 1 WRITE TPE GOT Ox 50 1 WRITE VOLTAJE CLREC
61. INE 0123456789ABCDEF HEXA L NE HI N DIV 16 4 LINE HI N MOD 16 1 LINE LO DIV 16 1 LINE LO N MOD 16 1 END ree e ESTE PROCEDIMIENTO MANDA LA INFORMACION CONTENIDA EN EL REGISTRO AL POR EL PUERTO SERIE HACIENDO USO DE LA INTERRUPCION 14 DEL DOS PAA dc A cde f che ehe Bee ee e A KA hc dic sfc ic dc k KK A ko dk KA KA e e e dic fc IR A KK KA PROCEDURE ESCRIBE X BYTE var Reg Reuisters begin with Reg uo begin DX 0 INTR 14 REG end end sarao ESTE PROCEDIMIENTO ESTABLECE LA CONFIGURACION DEL PUERTO PARA QUE TRABAJE A LA VELOCIDAD DE BAUD RATE ADECUADA EN BASE AL CRISTAL QUE MANEJA EL SI ST E MA ces ce eee k ke PROCEDURE INITPORT var Reg Re usters begin with Reg 10 begin DX 0 AH 0 AL 04 INTR S7 i REG end end BEGIN PROGRAMA PRINCIPAL CLRSCR NL 0 INITPORT WRITELN WRITE HOMBRE DEL ARCHIVO OBJETO READLN NOMBRE 1 NOMBRE ARCH t OBJ WRITELN PROYECTO TERMINAL RABADOR DE EPROMs AUT NOMO ASSIGN F NOMBRE_AP ZH RESET iE TB 3 NL 2 WHILE NOT EOF F DO BEGIN READLNi LINEA VAL COPY 2 NB EC TB TB ivB INC NL END ESCRIBE HI TB ESCRIBE LO TB RESET F FOR TO NL DO BEGIN READLN F LINEA VAL COPY LINEA 2 2 NB EC VAL COPY LINEA 4 4 1 FOR TO NB
62. ION EFFECTS 4 FULLY TTL AND CMOS COMPATIBLE Mec Pinta GND Pin 7 CONNECTION DIAGRAM DI TOP VIEW LOADING Note ai PIN NAMES HIGH LOW 8 Data Inputs 05UL 0250 Clock Active HIGH Going 05U t 025 U L Edge input MR Master Reset Active LOW Input 0 5 UL 0 25 91 10 UL 512 5 U L Qo Q7 Outputs Note b NOTES VTTL Unit Load U C 40 yA HIGH 1 5 LOW b The Output LOW drive factor s 2 5 Ut toe Mibtary 54 and 5 U L for Commercial 74 Ranges DIAGRAM Yoo Pie 14 GNO Pin 7 j Pin Numbers Y o sewa as aq T54LS373 T74LS373 OCTAL TRANSPARENT LATCH WITH 3 STATE OUTPUTS DESCRIPTION The T54LS T74LS373 consists of eight latches with 3 state outputs tor bus organized system applications The tlip flops appeat transparent to the data data changes asynchronously when Latch Enable LE is HIGH When LE is LOW the data that_meets the set up times is latched Data appears on the bus when the Output Enable is LOW When is HIGH the bus outputs is in the high impedance state LOGIC SYMBOL O EIGHT LATCHES IN A SINGLE PACKAGE 9 3 5TATE OUTPUTS FOR AUS INTERFACING O HYSTERESIS ON LATCH ENABLE O INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS FULLY CMOS AND TTL COMPATABLE D Le Dr
63. Ie 8 14 13 19 000 9 PIN NAMES LOADING Note a HIGH LOW Ag Ag Address Inputs 0 5 U L 0 25 U L E E Enable Active LOW Inputs 0 5 U L 0 2504 E3 z Enable Active HIGH Input 0 5 ULL 0 25 0 1 Pin 16 00 0 Active LOW Outputs Note b 10 UL 5 2 5 U L GNO Pin 8 NOTES V TTL Unit Loed U L 40 uA HIGH 1 6 mA LOW b The Output LOW drive facior i 2 5 U L for Military 154 5 U L for Commercial 74 Temperature Ranges CONNECTION DIAGRAM DIP TOP VIEW LOGIC OIAGRAM vec Pin 16 GND Pin 8 O Pan Numbers n vnen ieme ra w T54LS 164 T74LS 164 SERIAL IN PARALLEL OUT SHIFT REGISTER DESCRIPTION The T54LS164 T74LS164 is a high speed 8 Bit Serial in Parallel Out Shift Register Serial data is entered through 2 Input AND gate synchronous with the LOW to HIGH transition of the clock The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all SGS ATES TTL products 15164 BRIT Sh T REGISTER cr MA 09 Q Q 0 0 0 0 3 4 0n 12 TYPICAL SHIFT FREQUENCY OF 35 MHz ASYNCHRONOUS MASTER RESET GATED SERIAL DATA INPUT FULLY SYNCHRONOUS DATA TRANSFERS INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINAT
64. JEXCMIN 211A 71 BE ACALL IMPRIME 211C 31 A7 PWRDWN 211E 71 66 ACALL CHECK PBS 2120 B480 DE CJNE A 80H DESTINO 212301 98 AJMP IND 2125 2125 ere INICIALIZAR BUFFER LON CEROS Y CARGAR RAM tffe 21253128 IND BUFF 212731 4B ACALL CCMC 212901 98 AJMP MENU IND 2128 21 2B Aid INICIALIZA EL BUFFE amp R DEL KIT EN 00H JOOOOOOOOOO he ORO 2128 21280083 PUSH DPH 2120 C082 PUSH DPL 212F CO EO PUSH A 2131 90 30 00 MOV DPTR 3000H 21347400 MOV A amp 00H 2136 FO MOVX QDPTRA 2137 74 FE A OFEH 2139 B5 82 0C AJDPL PROX CERO 213C 74 3F MOV AJG43FH 213E B5 83 07 CJNE A DPHPROX CERO 2141 DO EO POP A 2143 DO 82 POP DPL 2145 DO 83 POP DPF 2147 22 RET 2148 2148 A3 PROX CERO INC DPTR 2149 21 34 AJMP PONGERO 214B 214B iia COPIA DATOS DE L PROM AL BUFER koc e dedo s JA 214B LEE EL CONTENIDO DE UN RANGO DE LA EPROM ESPECIF CADO POR EL USUARIO 2148 Y ES PUESTO EN LA MEMORIA 2E BUFFER USANDO LA 5 DIRECCION 214B 214B CCMD MOV DPTR PCTPL1 214B MOV A 89H 214B MOVX ODPTR A 214B 31 74 ACALL PWRUP 214D 71 00 ACALL CONF 214F 900000 CCMD1 2152 2152 31 C6 CREAD 2154 CO EO 2156 ES 83 2158 44 30 215A F583 215C DO EO 215E FO 215F 74 FF 2161 B582 06 2164 74 3F 2166 B5 83 01 MOV DPTR 0000H PUSH A MOV ORL A 4OC 10
65. JNE A O040H CHECK2 203401 1B AJMP NDP 2036 B480 F6 2 CJNE A 080H CHECK1 2039 01 3B AJMP MENU DEP 208B 203B ai MARIO OOOO OCIO ORAR III A 208B 7479 DEP MOV A XE 208D 71 BE ACALL IMPRIME 208F 7450 MOV A 50H PROGRAMA PUERTO SERIE Eli MODO 1 2041 F5 98 MOV SCONA 2043 2043 74 F4 MOV AHOF4H CARGA VALOR DE BAUDRATE 2045 F5 8D MOV TH1 A 2047 2047 74 20 MOV A 20H PROGRAMA TIMER 1 EN MODO 2 2049 F5 89 MOV TMOD A 2048 204B 74 40 MOV AH40H ARRANCA TIMER 1 2040 F5 88 MOV 204F 204F 204F 204F RUTINA DE MENU EN MODO DEPENDIENTE 204F 906002 WRRS MOV DPTR APC2 2052 74 MOV A 0FH 2054 FO MOVX DPTRA 2055 CO EO PUSH A 2057 71 58 ACALL RECIBE 2059 B4 01 04 CJNE A 01 ESF2 205 DO POP A 205E 01 6B AJMP MEM_PROG 2060 B40204 ESF2 CJNE A 02 ESSAL 2063 DO EO POP A 2065 01 7D AJMP PROG_MEM 2067 DOEO 55 POP A 2069 01 2B AJMP MOD_DEP 206B TEO RR RA 206B MANDA 80 BYTES DEL CONTENIDO DEL BUFFER DE LA RAM DEL KIT A PC 2068 7158 MEM PROG RECIBE RECIBE BYTE ALTO DE DPTR 206D F5 83 MOV DPH A 206F 7158 WRDL ACALL RECIBE RECIBE BYTE UPTR 2071 F582 MOV 2073 2073 7980 MOV R1 480H 2075 PAGINA 26 PROYECTO TERMINAL 0135 0136 0137 0138 0139 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 0150 0151 0152 0153 0154 0155 0156 0157 0158 0159
66. JO PRESO AUT ees Casa abertaaltiempo PLANTEL IZTAPALAPA c 2 75 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO REALIZADO POR JOS IGNACIO FLORES TAPIA N STOR S NCHEZ G MEZ CON ASESOR A DE MIGUEL NGEL RU Z S NCHEZ PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO PROLOGO El proyecto presente se dividi para su an lisis y dise o en tres bloques principales que son 1 HARDWARE 2 SOFTWARE 3 MANUAL DE USUARIO Para el bloque de HARDWARE tenemos An lisis En esta etapa se analizan los requerimientos del sistema grabador y en base a estos se proponen varias soluciones y alternativas Dise o Aqu se realiza un bosquejo en el cual se proporciona una descripci n de los diferentes circuitos utilizados de acuerdo a los requerimientos de la etapa anterior Se parte de la configuraci n de los pines de las EPROMs despu s se analizan los circuitos de control para cada uno de los pines a continuaci n se describen los componentes para la interfaz con los anteriores y por ltimo se analiza el microcontrolador usado y los perif ricos que son memoria externa RAM y ROM as como los latch buffers y decodificadores para el control de los perif ricos Implementaci n En esta parte se proporciona una lista de los principales circuitos integrados que se requerir n para el grabador con una descripci n y una justificaci n de porque se usaron Adem s del diagrama final simb lico y un diagrama con la distribuci
67. La opci n Editar del men BUFFER carga a la RAM de la PC 80 bytes de c digo HEX a partir de una direcci n especificada por el usuario y los despliega en la pantalla Las opciones marcadas con son las que est n impismentadas en el programa ITFC PAS P GINA 40 PROYECTO TERMINAL BIBLIOGRAF A GF s ADOR DE EPROMs AUT NOMO e Intel MICROCONTROLLER HANDBOOK Familia MCS 51 Capitulo 7 Architecture MCS 51 Capitulo 8 MCS 51 Programmer s Guide anu Instruction Set Capitulo 9 Data Sheets Capitulo 10 MCS 51 Aplication Notes e Intel MEMORY Capitulo 3 Dinamic and Static RAMs Access Memories 51256 pag 3 80 5164 pag 3 37 Capitulo 4 EPROMs Erasable Programmable Read Only Memories 2716 pag 4 1 2732 pag 4 9 2764 pag 4 18 27128 pag 4 42 27256 pag 463 27512 pag 4 111 Algoritmo de programaci n Quic Pulse pag 4 397 e Intel DISPOSITIVOS PERIF RICOS PP Programmable Peripherical Interface 6255 Pags 3 100 a 3 119 e SGS DATABOOK LOW POWER SCHOTTKY TTL ICs C I 74373 74245 74138 7400 7404 7408 7407 7415151 e William G Houghton MASTERING DIGITAL DEVICE CONTROL Capitulo 1 The Intel 8051 Family Capitulo 2 External Program Memory Expansion Capitulo 3 External Data Memory Expansion Capitulo 4 Expanding 1 Capitulo 8 Adding An RS 232 Port e Motorola SEMICONDUCTOR TECHNICAL DATA MUA78840 pag 3 330 LM317 pag 3 21 LM337 pag 3 43 e Int
68. M PRODUCT FAMILY PRODUCT DEFINITIONS Operating Temperature 125 C hr Q oto 70 C 40 Cto 85 C 40 10 85 C Burn in READ OPERATION D C CHARACTERISTICS 27256 available with 168 8 hour 125 C dynamic burn in using Intel s standard bias configuration This pro cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temperature range is 0 C to 70 C Extended op erating temperature range 40 C to 85 C EX PRESS products are available Like all Intel EPROMs the EXPRESS EPROM family is inspected to 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing EXPRESS OPTIONS 27256 VERSIONS Packaging Optlons Speed Versions Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for Parameter Isa Veg Standby Current mA ice Vgc Active Current mA NOTE TD27256 LD27256 Mn Ma Test Conditions 1 The maximum current value is with outputs Oo to Oy unloaded DE 5v Vep 5V A 1kN V Vss GNO Ara Binary Sequence from Ao to Aja 290097 10 Burn in Bias and Timing Diagrams 27256 ADOR FIAST LOCATION Voc 0 Vpp 12 PROGRAM ONE PULSE OF JU DURATION COMPARE ALL BYTES TO O
69. MOV DPTR amp 0450 2272 740E MOV A OE 0451 2274 FO MOVX 0452 2275 7432 MOV 0453 2277 02 5 SETBAS 0454 2279 20 JB s O455 227C 0456 227C 904001 W 1L6A MOV DPTR gt 0457 227F D2 E3 SETBA3 0458 2281 543F ANL 00 IB 0459 2283 FO MOVX 0460 2284 41 8E AJMP WNXS i 0461 2286 0462 2286904001 W11H6A MOV DPTR 0463 2289 C2 CLR A3 0464 228B 543F ANL 0011 1118 0465 228D FO MOVX DF 4 0466 228E 0467 228E 904000 WNX64A DPTR 2 0468 2291E531 MOV AADF 0469 2203 FO MOVX GDF 0470 229490 40 02 MOV DPTR 0471 229731 2 ACALL DLY 0472 229931 2 DL Y 0473 220B 31 A2 ACALL DL Y O474 229D 31 A2 ACALL Div O475 229F 753F 00 MOV 0 0476 22A2E539 AGNG4 MOV A FILLKV 0477 22A4FO MOVX 0478 22 5 90 6000 MOV DPTR A2 0479 22A8 7485 MOV 8 0480 22AA FO MOVX DF 0481 22 CO EO PUSH A 0482 22AD 31 2 ACALL DLY 0483 22AF 31 2 ACALL DL Y 0484 22B1 31 A2 ACALL Dt Y O485 22B331 A2 ACALL DL v 0486 22B5 DO EO POP A 0487 22B7053F INC X 0488 22B9 0489 22B9E53F NOV64A MOV A X 0490 22BB CO EO PUSH A 0491 22BD 90 60 00 MOV DPTR e A2 O492 22CO 7481 MOV AB 0493 22C2 FO MOVX 0 A 0494 220390 4002 MOV DPTR 221 GRABADOR DE EPROMs AUT NOMO P GINA 31 PROYECTO TERMINAL GRABADOR DE EPROMs AUTONOMO 0495 22C6 DO EO POP A 0496 2268 B4 20 D7 CUNE 25 64 0497 22 0498 22CB ES3F OV
70. Mil PDIP Package The 51645 is a 8192 word by 8 bit CMOS static RAM fabricated using CMOS Silicon Gate process The 51645 is placed a standby or reduced power consumption mode by asserting either CS input CS 52 false When in standby mode the device is deselected and the outputs are in a high impedance state independent of the WE input When device is deselected standby current is reduced to 100 A max The device will remain in standby mode until both pins are asserted true again The device has a data retention mode that guarantees that data will remain valid at minimum Vcc of 2 0V Block Diagram Pin Connections O Ye 4 OG6ND 256 x 256 Memory 7 al V N ru A LALA 240570 1 240570 2 Pin Names intel 5164S L Device Operation The 51645 has three control inputs Two Chip Se tects C54 CS2 and Write Enable WE WE is the data control pin and should be used to gate data at the 1 0 pins A write cycle starts at the lowest tran sition of CS4 low WE or high CS and ends at the earliest transition ot 65 high WE or low 52 Out Enable OE is used for precise control of the out puts The availability of active high and active low chip enable pins provides more system design flexibility than single chip enable devices Table 1 Mode Selection Truth Table vo e bm ABSOLUTE MAXIMUM RATINGS Voltage o
71. O 0028 20 C299 CLR SCON 1 0029 20 80EE SJMP RECNB 0030 202 0031 20 0032 20 3098FD RECIBE JNB SCON O RECIBE 0033 20 C298 CLR SCON O 0034 20 E5 99 MOV A SBUF 0035 20 22 RET 0036 20 0037 20 1 OBLIGA AL ENSAIV GLADOR A GENERAR 0038 20 00 20 RUN word INIZIO SEPARADO UNA LINEA DE CODIGO 0039 202 END PARA LA DIRECCION DE ARRANQUE tasm Nui ver of errors O PROYEC gt TERMINAL RABADOR DE EPROMs AUT NOMO 0001 0000 ESTE PROGRAMA PERMITE LOS PBS DE INTERFAZ CON EL USUARIO 0002 0000 ASI COMO DESPLEGAR DATOS EN EL DISPLAY 0003 0000 INCLUDE C EQUS TXT 0162 0000 LIST 0005 002 LIST 0007 2002 ORG 2090H 0009 2000 90 60 03 INICIO MOV DPTR PCTRL2 0010 2003 74 88 MOV A 88H 0011 2005 FO MOVX DPTR A 0012 200 90 40 03 MOV DPTR PCTRL1 0013 20 74 80 MOV 0014 20 3 FO MOVX QOPTR A 0017 2008 74 DF REGRESO MOV A XCERO 0018 200 112C ACALL IMPRIME 0020 2012906002 ETS MOV DPTR PC2 0021 2012 EO MOVX A DPTR 0022 20154 CO ANL 0023 2015 B4 80 04 CJNE A 080H ET5 0024 201 74 86 MOV A XUNO 0025 2018 11 2C ACALL IMPRIME 0026 2017 0027 20 906002 ETS MOV DPTR PC2 0028 20 EO MOVX A DPTR 0029 20 54 CO ANL A KOCOH 0030 20 5 4 40 EA CJNE A ZO4O0H ET6 0031 2025 74 BB MOV A XDOS 0032 202 112C ACALL IMPRIME 0033 2024 0034 202401 10 AJMP ETG 0038 2027906000 IMPRIME MOV DPTR PA2 0039 202 78 08 MOV 08 0040 2031 F
72. PA1 0027 202 11 5D ACALL DATO 0028 20217417 MOV A 017H 0029 20 590 40 01 MCV DPTRHPE 0030 2029 11 5D ACALL DATO 0031 2023 0032 2028 90 60 02 ET5 MOV DPTR PC2 0033 2022 A DPTF 0034 202 54 0 ANL A OCOH 0035 202 B4 40 DC CJNE A 040H ET6 0036 2024 74 BB MOV A XDOS 0037 2056 11 48 ACALL IMPRIME 0038 2025 74 55 MOV A 055H 0039 22214904000 MOV DPTRAPA1 0040 20 0 11 5D DATO 0041 205 74 00 A O0H 0042 2041 90 40 01 MCV DPTRHPB1 0043 2044 11 5D ACALL DATO 0044 2045 0045 2045 01 10 AJMP ET6 0046 2243 0047 22 3 0048 2223 0049 2043906000 IMPRIME MOv DPTR PA2 0050 2048 78 08 Mov RO 08 0051 2042 ETQ4 MOV R1 A 0052 204E 5480 A 8 H 0053 20 203 RR A 0054 20 1 03 RR A 0055 2052 44 10 ORL A 10H PROYE TERMINAL 0056 0057 0058 2054 FO MOVX QoPTRA 2025 54 EF A ACEFH 2057 FO MOVX DPTR A 2058 E9 MOV AFt1 2059 23 RL A 205A D8 F1 DINZ RO ETQ4 2050 22 205D 2050 FO DATO MOVX DP 205E 22 205F 2050 ORG 1 OBLIGA AL ENSAME ADOR A GENERAR 2000 00 20 RUN VWORD INICIO POR SEPARADO UNA LINEA DE CODIGO 2002 END PARA LA DIRECCION CE ARRANQUE 2002 2062 of errors 0 DE EPROMs AUT NOMO PROYECTO TERMINAL __ GRABADOR DE EPROMs AUT NOMO EL NOMBRE DE ESTE PROGRAMA ES TFCPAS QUE ES EL QUE SE ENCARGA DE INTERFAZAR LA PC CON EL GRABADOR CUANDO SE ESTA TRABAJANDO EN MODO DEPENDIENTE PROGRAM GRABA USES C
73. RECC ONADO 0586 2355 C299 CLR SCON 1 0587 235722 RET 0588 2358 mee AA 0589 2358 30 98 FD RECIBE JNB 5 ES RECIBE ECO DE TERMINAL 0590 235B C298 CLR SCON O 0591 2350 E599 MOV A SBUF 0592 235F CO EO PUSH A 0593 2361 71 95 ACALL DISPLAY 0594 2363 DO EO POP A 0595 2365 22 RET 0596 2366 0597 2366 ANA SE CHAAR ESSE DIR II IOI AR III AIA AAAI 0598 2366 monitorea los botones de controi i 51 Y PB2 y no regresa hasta que no 0599 2366 se haya presionado uno de los 7 0600 2366 CO 83 CHECK_PBS PUSH DPH 0601 2368 CO 82 PUSH 0602 236A 90 60 02 DPF 2 0603 2360 7400 CHECA MOV A O00r 0604 236F EO 0605 2370 54 MOVX A QUPTR ANL 0606 237230 E6 05 JNB PBS 0607 237530E702 JNB A I PBS 0608 2378 61 6D AJMP CHECA DELAY 0609 237A 71 81 FIN_PBS 0610 237C DO 82 POP CP 0611 237E DO 83 POP DPF 0612 238022 RET 0613 2381 0614 2381 E RARA 0615 2381 0616 2381 7960 DELAYX MOV R1 860r RETARDO 0617 2383 0901 DELAYO DJNZ R1 DELAYS 0618 2385 22 RET 0619 2386 0620 2386 78 00 DELAY3 0621 2388 D8 FE RETA1 0622 238A D8 FE RETA2 0623 238C D8 FE 0624 238E D8 FE RETA4 0625 2390D8FE RETAS MOV DJNZ RO RETA DJNZ RO RETA2 DJNZ DJNZ RO RE A4 DJNZ RO RETAS 0626 239261 83 AJMP DELAYG 0627 2394 22 RET 0628 2395 0629 2305 0630 2395 ESCRIBE EN EL DISPLAY EL CO ITENIDO DEL ACUMULADOR EN DOS DIGITOS HEXA 0
74. RIGINAL DEVICE FAKED Figure 4 inteligent Programming Flowchart inteligent Programming Algorithm The intgligent Programming Algorithm has been a standard in the industry for the past few years A flowchart of the intgligent Programming Algorithm is shown in Figure 4 The intgligent Programming Algorithm utilizes two different pulse types initial and overprogram The duration of the initial CE pulse s is one millisecond which will then be followed by a longer overprogram pulse of length 3X msec X is an iteration counter and is equal to the number of the initial one millisec ond pulses applied to a particular location before a correct verify occurs Up to 25 one millisecond puls es per byte are provided for before the overprogram pulse is applied The entire sequence of program pulses and byte verifications is performed at Vcc 6 0V and Vpp 12 5V When the intgligent Programming cy cle has been completed all bytes should be com pared to the original data with Voc Vpp 5 0V intel 27512 512K 64K x 8 PRODUCTION AND UV ERASABLE PROM Software Carrier Capability 8 Low Power 170 ns Maximum Access Time 125 mA max Active 40 mA max Standby m inteligent Programming Algorithm Two Line Control inteligent Identifier Mode Automated Programming Operations H Available in 28 PIn Cerdip See packaging spec order 231369 m TTL Compatible The Intel 27512 is
75. RT DOS CONS V12 12 5V 21 21 0V V25 25 0V DIRES 8000 TOPE 65500 var AR_INSTS STRING LINEA STRING DIRE STRING 4 NNOMAR NOMAR STRING 13 VDEF NV TPE STRINGIT T S DIRS RES CHAR OP CCD C BYTE SEG IND INTEGER NL TB PC CB BE EC NBI J INTEGER UB N E COL REN DIR INTEGER TBS PCS CBS STRINGI8O TEXT CONT3UF ARRAY 1 TOPE OF WORD x RORO ROACH IK IK IAAP AIA A IIIA AA ACK ORAR FUNCTION HEXAB N BYTE STRING VAR LINE STRING 16 BEGIN LINE 0123456789ABCDEF HEXAB LINE DIV 16 1 LINE MOD 16 1 END o dai ea FUNCTION HEXA N INTESER STRING VAR LINE STRING 16 BEGIN LINE 0123456789ABCDEF HEXA LINE HI N DIV 16 1 LINE HI N MOD 16 1 LINE LO N DIV 16 1 LINE LO N MOD 6 1 END A O FUNCTION HEXAW N WORD STRING VAR LINE STRING 16 BEGIN LINE 0123456789ABCDEF HEXAW HEXAB HI N HEXAB O N END A FUNCTION BUSCA OP_CIDE BYTE INTEGER VAR L INTEGER OP S KING 2 PROYEC 1 TERMINAL BEGIN 0 CODE INC l UNTIL COPY AR INSTSII 1 2 OR 12242 BUSCA END PDI kick KA s AAAI AK KA KA AAA CA ARA AAA PROCEDURE ESCRIBE X BYTEj var Reg Reisters begin with Rey do begin DX 0
76. S OUTPUT A PIN Vig ADJUST 3 Vout ORDERING INFORMATION Tested Operating Temperature Range Package 4 Matal Can S5Cto 150 IA Power TEEN Metal Can LM117H LM117K 1M217H 1M217K MEN LM317K Tj OCto 11250 Metat Power 3177 Plastic Power UM317BT 40C to 125C Power Automotive temperature range selections are avadable with special test conditions and additional tests Contact your iocal Motoro a sales off ce lor informaron MOTOROLA LINEARANTERFACE DEVICES 3 21 PROYECTO TERMINAL u GRABADOR DE EPROMs AUT NOMO ANEXO 2 LISTADOS DE PROGRAMAS DE PRUEBA PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO DESCRIPCI N Debido a la necesidad de estar desarrollando innumerables pruebas para evaluar el funcionamiento de cada etapa del sistema grabador se precisa una forma gil y segura para tal efecto una forma segura pero poco gil es el uso de memorias EPROM para realizar las pruebas ya que se requiere tener un grabador y un borrador de EPROM as como de un cierto tiempo para que las memorias se borren lo cual entorpecer a el avance del proyecto Tomando en cuenta io anterior asi como la proyecci n que se da al grabador para poder trabajar mediante el puerto serie de la PC se realizaron programas con tal fin y adaptando nuestro sistema para aceptar memorias EEPROM Electrically Erasable and Reprogrammable Only Memories en lugar de las EPROM para
77. WR inputs con tro the selection of one of the three ports or the control word registers They are normally connected to the least significant bits of the address bus Ag and A4 231308 3 Figure 3 8255A Block Diagram Showing Data Bus Buffer and Read Write Contro Logic Functions 3 101 Each of the Control blocks Group A and Group 8255A BASIC OPERATION accepts commands from the Read Write fit Ao RD WR CS Input Operation READ Logic receives control words from the interna z data bus and issues the proper commands to its ag 0 1 0 Pon A Data Bus sociated ports 0 1 0 Port B Data Bus 9 1 0 PortC Data Bus E qn Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO Output Operatlon WRITE The Control Word Register can Only be written into 0 DataBus gt PortA EAE NO allowed e 1 0 DataBus Port C Ports A B and C 0 The 8255A contains three 8 bit ports A and All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 8255A 1 1 1 0 Data Bus Contro Disable Function E x Xx 1 f Data Bus 3 State LL illegal Condition X 1 1 Data Bus 3 State
78. ad d dj lddu a 0 pue UIA 20 sanien ayy 12 ouanbaJ Guiyoums indino 143 49 INDINO passe ino ty BuniaAu 10 1004 dn dois pue umop dars soj 1 821 179 indino Poa ouu Dunsaaul pue dn dais 107 YIWNUIA pue umop d31s 10 XCU IU A asn vaya jueisuoo 100 Si siya j indui U A u8s0q5 eq JENW Apjddns eu 39171241 0 dorm 258105 A PAS ININA JO VONLINES adda 86 moi weu uo j REX HATO VPO ia i U s ISA SIN TT EU nui n TEN LM t 0 ETT EES 255 WS om gt euro z Y MOLINO e noy US ene 1 5 Cw CQ xv eu nic inc EYE 5 wu 7 ESA Iunius 7007 T uuu 7 A mo 4 j me 76 TFR x Bureau umog dais UONE 31071 VINWYOI NDIS30 L Ase al sape HPO YALBSANOD ONILU3ANI 3UNDIS ovsszy MOTOROLA SEMICONDUCTOR ws TECHNICAL DATA THREE TERMINAL ADJUSTABLE OUTPUT NEGATIVE VOLTAGE REGULATORS The LM137 237 337 are adjustable 3 terminal negative voltage regulators capable of supplying in excess of 1 5 A over an output volt
79. age range of 1 2 V to 37 V These voltage regulators are exceptionally easy to use and require onty two external resistors to set the output voltage Further they employ internal current limiting thermal shutdown and safe area compensation making them essentially blow out proof The LM137 series serve a wide variety of applications including local on card regulation This device can also be used to make a programmabie output regulator or by connecting a fixed re sistor between the adjustment and output the M137 series can be used as a precision current regulator Output Current in Excess of 1 5 Ampere in K and T Suffix Packages Output Current in Excess of 0 5 Ampere in H Suffix Package e Output Adjustable Between 1 2 V and 37 V e internal Therms Overload Protection 9 Internal Short Circuit Current Limiting Constant with Temperature e Output Transistor Safe Area Compensation e Floating Operation for High Voltage Applications Standard 3 Lead Transistor Packages e Eliminates Stocking Many Fixed Voltages STANDARD APPLICATION Cin 15 required if regulator is located more than 4 inches from power supply hiter A 1 uF solid tantalum or 10 aluminum electrolytic is ccommoended Cois necessary for stability A 1 uF solid tantalum or tO uF aluminum electro is recommended Vout 1 25 V 1 82 ote temperature range selections are evailabie with special test conditions and 7 7 onal tests Con
80. agilizar las pruebas se desarrollaron los programas CARGADOR ASM Y CARGAD PAS El programa CARGADOR ASM se grabo en una EEPROM y este contiene el c digo necesario para cargar un programa que le llega dei puerto serial enviado por el programa CARGAD PAS a la RAM del grabador y despu s ejecutarlo Esto es lo que hizo mas agiles las pruebas En base al hecho de que se debiera tener intercomunicaci n del sistema con la PC v a puerto serie se implemento un programa que mostrara dicha intercomunicaci n el cual recibe un caracter de teclado de la PC lo transmite al grabador y este lo regresa para volver a aparecer en la pantalla dos veces dicho programa lleva por nombre ECOP ASM Una vez aprobada la intercomunicaci n se desarrollan programas para probar y poner a punto la interfaz con el usuario en modo de trabajo independiente botones y display surgiendo as el programa CHKPBS ASM permitiendo tambi n el monitoreo de las l neas de datos y direcciones manejando palabras que permitieran examinar el cambio de valor l gico de O a 1 y viceversa por lo cua se manejaron dos palabras complementarias AA y 55 as como los voltajes de programaci n que se van a manejar creando el archivo CHKVTJS ASM Ya teniendo control de todo lo anterior se implementa un programa que adem s de integrarlo presenta la interfaz con el usuario asi como ios mensajes necesarios para ir llevando al usuario al buen uso de su programador los cua
81. apability of 32 K bytes enables it to function as a high density software carrier Entire operating systems diagnostics high level language programs and specialized application software can reside in a 27256 EPROM directly on a system s memory bus This permits immediate microprocessor access and execution of software and elminates the need for time consuming disk accesses and downloads Two line control and JEDEC approved 28 pin packaging are standard features of all Intel high density EPROMs This assures easy microprocessor interfacing and minimum design efforts when upgrading adding or choosing between nonvolatile memory alternatives The 27256 is manufactured using Intel s advanced HMOS II E technology HMOS is a patented process of intel Corporation 290097 1 Figure 1 Block Diagram 27256 Pin Names Chip Enable 27256 P27256 Intel Universal Site Compatible EPROM pin configurations are shown the blocks adjacent to the P27256 pins Figure 2 Cerdip Piastic DIP Pin Configuration intel EXTENDED TEMPERATURE EXPRESS EPROMs The inte EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics EXPRESS processing is available for several dansities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are EXPRESS EPRO
82. ario que el microcontrolador a usar posea memoria ROM interna Para la parte de la interfaz con el usuario se propone el uso de un display de 7 segmentos ser el que desplegara mayor informaci n del estado de los procesos que se realicen en el grabador un par de leds que indicaran cuando se puede remover una EPROM del socket y cuando no adem s de un tercero que indicara si se esta trabajando en modo dependiente o en modo dependiente y un par de botones El primer bot n PB2 se usar para navegar en todos los men s y submenus El segundo bot n PB1 ser para iniciar el proceso seleccionado por PB2 El circuito propuesto para esta parte se muestra en la figura 5 Cabe se alar que para la interfaz de usuario se podr a haber usado un n mero mayor de displays y mas botones o inclusive un LCD y un teclado controlados por un 8279 en este proyecto no se realizo de esa manera pero queda abierto para posteriores modificaciones ademas de que podria servir muy bien para efectos de un sistema de desarrollo del microcontrolador 8031 realizando las modificaciones pertinentes P GINA 10 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO Con lo que se ha descrito hasta este momento el grabador de EPROMs funcionar de forma aut noma pero si se quiere usar de forma dependiente es decir como un grabador convencional debemos de considerar algunos aspectos extras como son C mo se implementar la comunicaci n entre el grabad
83. ction Output En able is the output control and should be used to gate data from the output pins independent of device selection Assuming that addresses are sta ble address access time tacc is equal to the delay from CE to output Data is available at the out puts tog after the falling edge of OE assuming that CE has been low and addresses have been stable for at least tacc toe Standby Mode The 2716 has a standby mode which reduces the maximum active power dissipation by 75 from 525 mW to 132 mW The 2716 is placed in the standby mode by applying a TTL high signal to the CE input When in standby mode the outputs are in a high impedance state independent of the OE in put Output OR Tieing Because 2716s are usually used in larger memory arrays intel has provided a 2 line control function that accommodates this use of multiple memory connections The two line control function allows for a the lowest possible memory power dissipation and b complete assurance that output bus contention will not occur To use these two control lines most efficiently CE pin 18 should be decoded and used as the primary device selecting function while OE pin 20 should be made a common connection to all devices in the array and connected to the READ line from the sys tem control bus This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when
84. de EPROMs que sea aut nomo de una PC y que nos sirva para estos prop sitos con la ventaja de que en cualquier momento que se requiera realizar alguna operaci n adicional a estas podemos conectar el grabador a una PC cualquiera y v a puerto serial llevar acabo nuestros prop sitos P GINA 4 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO Objetivo Dise ar e implementar un grabador de EPROMs aut nomo Que copie de EPROM a EPROM adem s de PC a EPROM Caracteristicas El grabador tiene capacidad para grabar EPROMs de hasta 64Kb que es mucho mas de las necesidades cotidianas en un laboratorio de Sistemas Digitales esto es grabar EPROMs de la forma 27XXX que va desde la 2716 2Kb hasta la 27512 64Kb Se pueden hacer copias m ltiples de una sola EPROM es decir el contenido de la EPROM fuente se vac a en la RAM del sistema y despu s el contenido de la RAM se puede vaciar el contenido en las NEPROMs destino que se deseen Para realizar lo anterior se contar con un solo socket y el programa ir pidiendo al usuario la EPROM fuente y la EPROM destino cuando sean requeridas El sistema grabador funcionara tanto en forma aut noma para realizar copias como es forma dependiente interfazarse con un PC a trav s de un puerto serial P GINA 5 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO INTRODUCCI N En los sistemas digitales capaces de trabajar independientemente tales como una PC existe un lugar donde
85. de control para direcciones e Tres entradas de habilitaci n e Ocho salidas posibles E uso de este circuito se basa en las necesidades de poder controlar hasta ocho dispositivos con solo tres l neas para habilitarlos Interface perif rica programable e 3 buses de 8 bits Control de lectura Control de Escritura Control de selecci n Buses con estado de alta impedancia Linea de reset PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO 2 l neas de selecci n de bus Este circuito integrado nos permite realizar la comunicaci n entre la parte que maneja el usuario y el socket del grabador con el microcontrolador 2764 Capacidad para 8Kb x 8bits CHMOS compatible con microprocesadores y microcontroladores Latch de direcciones integrados Tama o universal de 28 pines con dos l neas de control Bajo consumo de potencia 100 microA m ximo Caracter sticas de inmunidad al ruido Alta velocidad de respuesta Esta memoria tipo EPROM tiene las caracter sticas necesarias para adaptarla a nuestro sistema y almacenara el programa principal BIOS del sistema grabador 6264 Capacidad para 8Kb x 8bits Operaci n est tica Tiempos iguales de acceso para lectura y escritura 5 volts de alimentaci n Compatible con TTL Datos comunes de entrada y salida Esta memoria tipo RAM tiene la usamos nicamente con prop sitos de desarrollo del sistema pruebas 62256 es decir sirve como al
86. e donde solo se tienen las opciones de GRABAR DE EPROM A EPROM de COMPARAR EL CONTENIDO DE LA EPROM CON EL CONTENIDO DEL BUFFER y la opci n de salir que se maneja con una c min scula El men para modo de trabajo dependiente se muestra en el diagrama de flujo 3 en este modo se tienen algunas otras opciones adem s de las que permite el modo independiente En este modo ya no se hace uso de los botones para manipular el flujo de la informaci n ahora se manipula el programa por medio de se ales n meros que le manda un programa que estar corriendo en la PC ITFC EXE a la que est conectado el grabador por medio del puerto serie entonces el programa est monitoreando el puerto serial y ejecutar la opci n de acuerdo al caracter le do El diagrama de flujo 4 explica la rutina de GRABAR en modo independiente P GINA 13 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO DIAGRAMA DE FLUJO 1 MEN PRINCIPAL INICIALIZACION HOLA 2 DESPLEGAR d SI MENU MODO MENU MODO INDEPEND DEPENDIENTE P GINA 19 PROYECTO TERMINAL DIAGRAMA DE FLUJO 2 MEN EN MODO INDEPENDIENTE desplegar 5 5 desplegar RUTINA PARA GRABAR RUTINA PARA COMPARAR DIAGRAMA DE FLUJO 3 MEN EN MODO DEPENDIENTE seleccionar el tipo de EPROM con la cual se va a trabajar desplegar E y espera caracter por puerto serial ENVIA EL CONTENIDO
87. e EPROMs en la figura 8 hay una lista de todos los circuitos y componentes usados y en el ANEXO 1 se proporciona una breve justificaci n para cada uno adem s de las hojas t cnicas de los Circuitos Integrados mas importantes A continuaci n se presentan los diagramas correspondientes a los bloques de la figura 4 que son los circuitos con los cuales se implemento el grabador FIGURA 7 DISTRIBUCI N F SICA DE LOS COMPONENTES 200 me 229 OC P GINA 13 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO LISTA DE LOS COMPONENTES USADOS N MERO ID DESCRIPCI N 8031 Microcontrolador de 8 bits 8255 A Interfaz perif rica programable 8255 B Interfaz perif rica programable 62256 RAM de 32kb x 8bits 6264 RAM de 8Kb x 8bits 2764 EPROM de 8Kb x 8bits 7415373 Latch 8 bits 74LS245 A Buffer bidireccional de 8 bits 74LS245 B Buffer bidireccional de 8 bits 7415138 Decodificador de 3 a 8 741504 Compuertas l gicas 74LS08 Compuertas logicas AND 7407 Buffers para DC mayor a TTL 7407 Buffers para DC mayor a TTL 74LS00 Compuertas logicas NAND MUA78S40 Convertidor de DC a DC 1488 Convertidor de TTL a RS232 1489 Convertidor de RS232 a TTL 74LS51 Compuerta AND OR NEGADA con dos compuertas de dos y tres entradas 74LS164 Registro de entrada serie salida paralela 7409 Display de 7 segmentos LM337 Regulador de Voltaje LM317 Regulador de Voltaje 2N2222 Transistores 2N2902 Trans
88. e grabar apartir de a ccalidad 3000h 0545 2313COEO TDPB PUSH A 0546 2315 E583 MOV A DP 0547 2317 4430 ORL A HOC 0548 2319 5 83 MOV DPR 0549 2318 DO EO POPA 0550 231022 0551 231E 0552 234E ex TRANSFORMA t E RAM A EPROM FEISS Q idiot ae tio 0553 231E grabar apartir de la direccion Oh de la EPROM destino 0554 231 PUSH A 0555 2320 5 83 MOV 0556 232254 CF ANL Ag 111B 0557 2324F583 MOV DPr 0558 2326 DO EO POPA 0559 2328 22 RET 0560 2329 0561 239 0562 2329 PORRA A ARO AAA IMPRIME A PPP TORT RTA ELI 563 23297476 HOLA MOV A 76h 0564 2328 71 BE ACALL IMP o6 0565 232D 7181 Dt 0566 232F 71 81 ACALL DEL P GINA 32 PROYECTO TERMINAL ABADOR DE EPROMs AUT NOMO 0567 2331 745F MOV 0568 2333 71 BE ACALL IMF gt 1E 0569 2335 71 81 0570 2337 71 81 ACALL DEL X 0571 2339 7458 MOV AJHOSH 0572 233B 71 ACALL IMPF 12 0573 2330 71 81 ACALL DEL 4 0574 233F 71 81 DELA 575 23417477 MOV 0576 2343 71 BE ACALL IMP 0577 2345 71 81 ACALL DE 0578 2347 71 81 ACALL DELA X 0579 2349 22 RET 0580 234A ORO OON OE ECHO A 0581 234A F5 99 TRANS MOV SBUF A 0582 234C CO EO PUSH A 0583 234E 7195 ACALL DISPLAY 0584 2350 DO EO POP A 0585 23523099FD WTB JNB SCON 1W E TRANSMITE BYTE DI
89. er systems Its function is that of a general purpose I O component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 8255A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 8255A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the BI DIRECTIONAL DATA BUS 9 0 i CONTROL CPU Address and Control busses and in turn issues commands to both of the Contro Groups CS Chip Select A low on this input pin enables the communication between the 8255A and the CPU RD Read A low on this input pin enables the 8255A to send the data or status information to the CPU on the data bus In essence it allows the CPU to read from the 8255A WR Write A low on this input pin enables the CPU to write data or control words into the 82554 Ag and 44 Port Select 0 and Port Select 1 These input sig nals in conjunction with the RD and
90. erature range is 0 C to 70 C Extended op erating temperature range 40 C to 85 C EX PRESS products are available Like all Intel EPROMs the EXPRESS EPROM family is inspected to 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing EXPRESS OPTIONS 2764A VERSIONS Packaging Options Speed Versions Gedp o o or j Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for Vcc Standby Current mA loc UU Vcc Active Current at High Temperature mA NOTE TD2764A LD2764A Test Conditlons we E we amp wecwenm we 1 The maximum current value is with outputs Oo to untoaded DE 5v R 1KN Vo Vpp 5V Vss GND GND PGM 5V 12 230884 10 Binary Sequence from Ag to Ara Burn in Bias and Timing Diagrams A ee eR COMPARE AMA BYTES TO ORIGINAL DATA 2764A Figure 3 inteligent Programming Flowchart inteligent Programming Algorithm The intgligent Programming Algorithm a standard in the industry for the past few years is required for all of Intei s 12 5V CERDIP EPROMs Plastic EPROMs may also be programmed using this method A flow chart of the intgligent Programming Algorithm is shown in Figure 3 The intgligent Programming Algorithm utilizes two different pulse types initial and overprogram The duration of the
91. ere Cr pix i i input Osciiator 5 Top View 125V Reference i _ORDERING INFORMATION i I Temperature Ref inv Noninv Vcc Outpul Switch Diode Diode gt Passer Output input Input Op Amp Emitter Anode Cathode 78 40 40 C to 85 C Plastic 97 Cirad wen ee lue tom View 4 AJ8S40DC Cto 7C C V j MAIBSADM 55 Cto 1250 7854090 55 to 125 C Ceram MOTOROLA LINEAR INTERFACE DEVICES 3 390 11478540 Amp Power Supply Voltage VcCiOp Amp 40 i Common Move input Range VICA i 0 3 to v Corparaior and Op Amph P H Diiterential Input Voltage Note 2 ne E Output Short Carcuit Duration Amp Reference Output Currant Voltage fram Switch Collectors to Gnd Vonage fram Switch Emitters to Switch Collectors to Emuter pa Current through Power Switch Current through Power iode L IL Power Diss pation and Thermal Characteristics Piastic Package Ta 25 C Derate above 25 Note 1 Ceramic Package Ta 25 v i Derate above 25 C Note 11 REA ee Storage Temperature Range c Tstg i 8510 150 Operating Temperature Range TA r AaA 8S40M 55 to 125 i i A78S40V 40 to 85 85400 0 0 2 Oto 70 Notes Y Teu 60 55 C lor wA7BS400M Thigh 128 C for uA78S40DM AOL for pA78S400 V 85
92. erificar la sincronizaci n adecuada de dichas se ales as como verificar los tiempos y la implementaci n de los algoritmos de programaci n Debido a los constantes problemas de hardware chips quemados en particular PPIs se aconseja revisar la implementaci n de la fuente de 5 V coloc ndola fuera de la tarjeta para evitar conflictos en la transferencia de informaci n en los voltajes de alimentaci n por exceso de temperatura Cabe se alar que para la interfaz de usuario se podr a haber usado un n mero mayor de displays y mas botones o inclusive un LCD y un teclado controlados por un 8279 en este proyecto no se realiz de esa manera pero queda abierto para posteriores modificaciones adem s de que podr a servir muy bien para efectos de un sistema de desarrollo del microcontrolador 8031 realizando las modificaciones pertinentes programas para la PC programas para el sistema y alg n hardware adicional El hecho de que solo se use un socket se debe a la intenci n de ahorrar espacio y tiempo ya que todo lo que se lograr a con 2 sockets es posible realizarlo con uno solo aunque para mayor comodidad del usuario ser a mejor implementar un segundo socket pero esto queda para mejoras posteriores P GINA 37 PROYECTO TERMINAL GR ABADOR DE EPROMs AUT NOMO MANUAL DE USUARIO Interfaz con el usuario En este bloque se localizan los push bottons 1 y 2 as como el display y los leds de acuerdo al circuito de la figura
93. fc fc amp kkh A KE zL MENU DE ARCHIVO NOMAR TIENE EL NOMSRE DEL ARCHIVO Vekefeekckck amp NOKIA k kok k AK K k k K Kk KAKI ii PROCE JRE ARCHI BEGIN WINDC vv 1 3 20 7 IMPRINE 1 1 ABRIR 15 1 0 A IMPRIA 1 2 GUARDAR COMO 15 1 0 G 1 3 CARGAR A BUFFER 15 1 0 C DIRS ADKEY CLRSC WIND 2 4 33 5 CASE 38 OF GIN IPRIME 1 1 NOMBRE DEL ARCHIVO OBJ 30 28 1 y ITOXY 28 1 READKEY E XTCOLOR O XTBACKGROUND 2 JTOXY 21 1 REOL ADLN IMAR NNOMAR OBJ 3SIGN F NOMAR SET F OSE F 2 SIN PRIME 1 1 GUARDAR COMO OBJ 30 28 1 y lt 2 28 1 READKEY I XTCOLOR O0 XTBACKGROUND 2 lt 2 15 1 REOL EADLN NNOMAR OMAR NNOMAR 2EWRITE NOMAR oe ob 2 ss ion EN gt T p Z G g uu GIN vINDOW 34 14 38 16 RSCR XTCOLOR O EXTBACKGROUND 2 DTOXY 2 2 5 9 READKEY EXTCOLOR 7 XTBACKGROUND O L RSCR T S THEN CARGA 2 PROYE O TERMINAL ELSE ERF UR END TEXTC _OR 7 TEXTB ZKGROUND O CLRSC END REKKKKKK A PROL EDI MI ENTO VOLTAJES ke feci KA AA Ahi A OPCION DE VOLTAJES DE PROGRAMACION VDEF RESENTA EL VOLTAJE POR DEFAULT NV VOLTAJE DE PROGRAMACION KKKKEKKKHA r RAK cik ici KA K k kk cik k
94. funciones extras que se presentan en los micros 8051 8032 y 8052 como son las interrupciones no ser n usados en el presente proyecto Tomando en cuenta una breve investigaci n de mercado se obtuvo como resultado que el microcontrolador 8031 es mas barato que el 8051 casi en una tercera parte y que el 8052 es un micro que esta discontinuado por lo cual se resuelve utilizar el microcontrolador 8031 para el grabador El microcontrolador se encargar de proporcionar las se ales para leer la EPROM fuente grabar la EPROM destino etc Para llevar acabo esta entrega de se ales de precisa de algunos pasos intermedios como lo es almacenar los datos fuentes en la memoria RAM del sistema adem s de realizar el direccionamiento de los datos poner los datos en las localidades de memoria correctas Entre los posibles circuitos auxiliares a utilizar se encuentran algunos buffers unas PPls Programmable Periferical Interfaz las cuales ser n las encargadas de proporcionar los mensajes adecuados al socket y para la interfaz con el usuario se precisar de circuiter a como son decodificadores displays de 7 segmentos y circuiter a combinacional y secuencial para control y manipulaci n del grabador Un diagrama inicial de lo que ser el grabador de EPROMs se observa en la figura 4 Para el grabador se tiene proyectado usar una EPROM que sea la encargada de almacenar el software propio del grabador debido a esto no se hace neces
95. he 27C128 has two control functions both of which must be logically active in order to obtain data at the outputs Chip Enable CE is the power control and should be used for device selection Output Enable is the output control and should be used to gate data from the output pins independent of de vice selection Assuming that addresses are stable the address access time tacc is equal to the delay from CE to output Data is available at the out uts after the delay of tog from the falling edge of assuming that has been low and addresses have been stable for at least tacc toe STANDBY MODE EPROMs can be placed in standby mode which re duces the maximum current of the device by apply ing a TTL high signal to the CE input When in stand by mode the outputs are in a high impedance state independent of the input Two Line Output Control Because EPROMs are usually used in larger memo ry arrays Intel has provided 2 control lines which accommodate this muitiple memory connection The two control lines allow tor a the lowest possible memory power dissipation and b complete assurance that output bus contention will not occur To use these two control lines most efficiently CE should be decoded and used as the primary device selecting function while DE should be made a com mon connection to all devices in the array and con nected to the READ line from the system control bus This assures that a
96. he code bytes during program ming of the EPROM parts and outputs the code bytes during program verification of the ROM and EPROM parts External pullups are required during program verification Port 1 Port 1 is an 8 bit bidirectional 1 0 port with internal pullups The Port 1 output buffers can sink source 4 LS TTL inputs Port 1 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current NL on the data sheet because of the internal pullups Port 1 also receives the low order address bytes dur ing programming of the EPROM parts and during program verification of the ROM and EPROM parts 8052 8032 ONLY 28 D P2 7 15 27 J P2 6A14 260 P2 5 A13 250 P2 4 A12 240 P2 3 Alt 23 D P2 2 A10 21 7 P2 0 8031 8051 8031AH 8051AH 8032 8052 e 8751 8751 12 8751 88 PRELIMINARY Figure 2 MCS 51 Connections in the 8032AH and 8052AH Port 1 pins P1 0 and P1 1 also serve the T2 and T2EX functions respec tively Port 2 Port 2 is an 8 bit bidirectional port with internal pullups The Port 2 output buffers can sink source 4 LS TTL inputs Port 2 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current
97. high performance 5V microprocessors such as Intel s 8085 and 8086 Selected 2716 5 2716 68 are also available for slower speed applications The 2716 also has a static standby mode which reduces power consumption without increasing access time The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW a 75 savings The 2716 uses a simple and fast methdd for programming a single TTL level pulse There is no need for high voltage pulsing because all programming controls are handled by TTL signals Programming of any location at any time either individually sequentially or at random is possible with the 2716 s single address program ming Total programming time for all 16 384 bits is only 100 seconds DATA OUTPUTS Veo oe 09 0 GNO eae 0 PROGRAM RISI Pin Names BE AND L CE LOGIC Chip Enable Y Y GATING 7 Aso DECODER ME OE Output Enable ADDRESS NPUTS x 00 07 DECODER 16 384 BIT CELL MATRIX 210310 1 Figure 1 Block Diagram NOTE 2716 2764A 27064 87064 Voc PGN 210310 2 intel Universal Site compatible EPROM configurations are shown the blocks adjacent to the 2716 pins Figure 2 Cerdip Pin Configuration EXTENDED TEMPERATURE EXPRESS EPROMs The intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received
98. i koko k li PROCEDURE EPR BEGIN MENUE 2 WINDO V 18 3 44 18 IMPRINM z 1 1 PROGRAM AR 16 1 C P IMPRIM 1 2 VERIFICAF COPIA 16 1 0 V IMPRIM 1 3 CARGAR BUFFER 16 1 0 C IMPRIM 1 4 IMPRIMIR 16 101 DIRS EADKEY CASE IRS OF p PEz SIN Ci SCR CONF ENC SIN Ci SCR Vt RIE EN CC Bi SIN C RSCR WE N C RSCR IN EN ELSE BEGIN ER OR OLE SCR END END FIN DEL CASE END dal 1k fee fc IA RICA RARA A K K N K Kk A AAA KA KK KA KARA KK KA AA CARG JF BEGIN 4T ESCR E 1 VAL S DIRE DIR EC DIRE 4EXAW DIR ESCR E HI DIR ESCR E LO DIR FOR REN 0 TO UB DC BEGIN X CON BUF REN 1 C END END PROCE URE EDT BEGIN WIND VV 19 4 60 21 TE T 2 LOR O TE JT CKGROUND 2 PROYE O TERMINAL GRABADOR DE EPROMs AUT NOMO GOTO Y 1 1 WRIT N DIRECCION GOTG Y 12 1 READ N DIRE LOW DEO INITP T ESOR 1 2 DIRE DIR EC DIRE 4EXAW DIR ESCR SE HI DIR ESCR E LO DIR FOR FEN 0 TO 1 DO BEGIN LOW VIDEO GOTC XY 1 REN 2 WRIT amp HEXAVV DIR HISHVIDEO FOR OL 0 TO 7 DO BEGIN LEE 2 WR E HEXAB C iF COL lt 15 THEN WRITE END WARE D OIR 8 END GOTC 1 20 WRITE SALIR lt REPET T R ADKEY CASE T OF ZH i13yIND 710 ELSE ER OR Ent UNTIL ND 10
99. intel s advanced HMOS 11 technology HMOS is a patented process of Intel Corporation 231088 1 Figure 1 Block Diagram 27512 Pin Names Addresses Chip Enable Outputs Enable Vpp D U Don t Use 27512 231088 2 Figure 2 Pin Configurations EXTENDED TEMPERATURE EXPRESS EPROMs The Intei EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics EXPRESS processing is available for several densities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are available with 168 8 hours 125 C dynamic burn in using Intel s standard bias configuration This pro cess exceeds or meets most industry specifications of burn in The standard EXPRESS EPROM operat ing temperature range is 0 C to 70 C Extended op erating temperature range 40 C to 85 EX PRESS products are available Like all intel E ROMSs the EXPRESS EPROM family is inspected to 0 1 electrical AQL This may allow the user to reduce or eliminate incoming inspection testing EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS Operating Temperature Burn in 125 C hr OCto 70 C 168 8 40 C to 5 40 C to 85 168 8 EXPRESS OPTIONS 27512 VERSIONS Packaging Optlons Speed Versions STD 25 30
100. iolet Erasable Cerdip plastic production P27256 electrically programmable read only memory EPROM Organized as 32K words by 8 bits individual bytes can be ac cessed in less than 170 ns 27256 1 This is compatible with high performance microprocessors such as the Intel iAPX 186 allowing full speed operation without the addition of performance degrading WAIT states The 27256 is also directly compatible with Intel s 8051 family of microcontrollers The Plastic P27256 is ideal for high volume production environments where code flexibility is crucial Plastic packaging is also well suited to auto insertion equipment in cost effective automated assembly lines Intel s new Quick Pulse Programming Algorithm enables the P27256 to be programmed within four seconds plus programmer overhead Programming equipment which takes advantage of this innovation will electronically identify the EPROM with the help of the inteligent Identifier and rapidly program it using a superior program ming method The inteligent Programming Algorithm may be utilized in the absence of such equipment The 27256 enables implementation o new advanced systems with firmware intensive architectures The combination of the 27256 s high density cost effective EPROM storage and new advanced microprocessors having megabit addressing capability provides designers with opportunities to engineer user friendly high reliability high performance systems The 27256 s large storage c
101. istores 47K Resistencias de 4 7K para efectos de PULL OP Varios Resistencias varias Varios Capacitores varios 20K Potenci metro de precisi n de 20K led Leds 11 0592mhz Cristal para velocidad del KIT 150 microH Bobina de Miller P GINA 14 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO FIGURA 9 BLOQUE PARA EL MICROCONTROLADOR LOS BUFFERS EL LATCH Y EL DECODIFICADOR 7408 Ee 1 ds S 2 REF gt 8 PAGINA 15 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO FIGURA 10 CONEXIONES PARA LA RAM LA EPROM Y LAS PPIs RESET PPLB PPI A RAM 8K ROM PAOB PAIB 2 4 5 A6 B 7 PBO B B1 B B2 B B3 B A15 4 14 5 A13 BEB A12 B7B A11 A10 99 C18 C2 B 2 C3 B pasce E 5 7 idem 5 x 5 bs i 04 T i8 x 02 2 o En DO m s A WR P GINA 16 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO FIGURA 11 SOCKET DEL GRABADOR Vpp A15 12 A6 AS A4 AS A2 Al AO DO D1 D2 NOTA Los pines marcados con 9 son los pines que van a estar controlados por los circuitos de las figuras 1 y 3 P GINA 17 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO AN LISIS Y DISE O DEL SOFTWARE Para obtener un buen dise o del software tenemos que analizar varias cosas primero como son 1 Forma en la que se va a utilizar el grabador Dependiente o Independien
102. ithout the addition of WAIT states An important 2732A feature is Output Enable DE which is separate from the Chip Enable CE control The OE control eliminates bus contention in microprocessor systems The is used by the 27324 to place it in a standby mode CE which reduces power consumption without increasing access time The standby mode reduces the current requirement by 6596 the maximum active current is reduced from 100 mA to a standby current of 35 mA HMOS is a patented process of Intel Corporation DATA OUTPUTS vec Ao 07 TO GNO gt Pin Names n Addressee CE Chip Enable AQ A11 DE Vpp Output Enable Vpp 22 788 8 CELL MATA 290081 1 Figure 1 Block Diagram 27512 27128 DOM 27C512 27C128 87064 290081 2 intel Universa Site compatible EPROM configurations are shown in the blocks adjacent to the 2732A pins Figure 2 Cerdip Pin Configuration intel EXTENDED TEMPERATURE EXPRESS EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics EXPRESS processing is available for several densities of EPROM allowing the choice of appropriate memory size to match sys tem applications EXPRESS EPROM products are available with 168 8 hour 125 C dynamic burn in using Intel s standard bias configuration This pro
103. l ANEXO 2 se incluyen listados de programas que fueron usados para probar el sistema por partes 0001 0000 0002 0000 0003 0000 0110 0000 0004 0000 PORRO IR RI IORI CA ROO PORRO IOI SOS IOI A AA LISTA DE INCLUDE EQUS TXT LIST LIST PCTRL2 PCTRL1 PA2 PA1 PB2 PB1 PC2 PC1 DIRBUFF TIPO TIPO 3 STATO O STATO 1 ADRO ADR1 STARTO START1 ENDO END1 TEMP1 FILLK FILLKW CHKSUM NBYTES RTYPE TEMP2 VBYTE X XCERO XUNO XDOS XTRES XCUATRO XCINCO XSEIS XSIETE XOCHO XNUEVE XA XB XCMAY XCMIN XD XE XG ETIQUETAS EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 3EH 3FH ODFH O86H OBBH OAFH OE6H OEDH OFDH 087H OFFH OEFH O7 7H 07 OS9H O3CH O79H O71H O6FH 076H O50H 058H O6DH O5EH OGEH OB3H PALABRAS DE DIRECCION DE ACCESO PARA CONFIGURAR LAS PPis PALABRAS DE DIRECCION PARA ACCESAR A LOS PUERTOS DE CADA PP SE USARA 1 PARA PPI A Y 2 PARA LA PPI B VARIABLES USADA EN EL PROGRAMA CARACTERES QUE SE que se despiieguen el dispiay d ORG 2000H DIRECCION DE INICIO DE 2ROGRAMA P GINA 25 PROYECTO TERMINAL GRABADOR DE EPROMs
104. l with the same data can be easily accomplished due to the simplicity of the programming requirements Like in puts of the paralleled 2732As may be connected to gether when they are programmed with the same data A low level TTL pulse applied to the CE input programs the paralleled 2732As Program Inhibit Programming of multiple EPROMs in parallel with different data is easily accomplished by using the Program Inhibit mode A high level CE input inhibits the other EPROMs from being programmed Except for CE all like inputs including OE Vpp of the par allel EPROMs may be common TTL low level pulse applied to the CE input with DE Vpp at 21V will program that selected device Program Verify A verify Read should be performed on the pro grammed bits to determine that they have been cor rectly programmed The verify is performed with OE Vpp and at V4 Data should be verified toy after the falling edge of CE inteligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro grammed with its corresponding programming algo rithm This mode is functional in the 25 C 5 C am bient temperature range that is required when pro gramming the device To activate this mode the programming equipment must force 11
105. le es igual a 25 si es igual a 25 se verifica el byte si es correcto se checa si es la ltima direcci n y se procede de la forma anterior si no es correcto se manda un mensaje de error Cuando la variable es menor que 25 se vuelve a dar un pulso de programaci n de 100 microsegundos y se procede de la misma manera En el diagrama de flujo 6 se muestra un algoritmo de programaci n INTELIGENTE La forma de operar de este algoritmo es similar al QUIK PULSE excepto por que manda un pulso extra de duraci n 3 veces el valor de la variable tratando de asegurar que la grabaci n sea correcta y para disminuir el tiempo de grabaci n Para cada tipo de EPROM las direcciones de fin varian de acuerdo a la capacidad y los voltajes de programaci n tambi n Se recomienda el uso del algoritmo de programaci n QUICK PULSE para aquellos tipos de EPROMs que usen voltajes de 21V y de 25V y del algoritmo INTELIGENTE para los tipos que usen voltajes de 12 5 V P GINA 22 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO DIAGRAMA DE FLUJO 5 Algoritmo de programaci n QUICK PULSE P GINA 23 PROYECTO TERMINAL _ GRABADOR DE EPROMs AUT NOMO DIAGRAMA DE FLUJO 6 Algoritmo de programaci n INTELIGENTE P GINA 24 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO IMPLEMENTACI N DEL SOFTWARE A continuaci n se presenta el c digo fuente del programa principal implementado nicamente para EPROMs 2764A En e
106. les se comentan en el manual de usuario v mostrando un esqueleto del programa final este enfocado al tipo de EPROM 2764A surge el programa GRAB64 ASM que se ve precedido por todos los anteriores y otros muchos programas de prueba al igual que los arriba mencionados Para el modo de trabajo dependiente se desarrollo programa que permitiera el manejo de las opciones del grabador en este modo y haciendo uso de algunos de los programas desarrollados en el modo independiente tales como el cargad pas etc se implementa el programa ITFC PAS PROYECTO TERMINAL __ RABADOR DE EPROMs AUT NOMO Los c digos fuentes ya compilados y funcionando se presentan a continuaci n 0001 0000 RRA este programa permite cargar un programa en la direccion 0002 0000 establecido con el primer ORG y lo comienza a ejecutar en la direccion 0003 0000 propuesta en ei segundo ORG 0004 0000 HINCLUDE EQUS TXT 0108 0000 0005 0000 LIST 0006 0000 0007 0000 ORG 0000h 0008 0000 21 00 AJMP INICIO 0009 0002 0010 0100 ORG 0100H 0011 0100 74 50 INICIO MOV A 50H PROGRAMA PUERTO SERIE EN MODO 1 0012 0102 F5 98 MOV SCON A 0013 0104 0014 0104 74 F4 MOV CARGA VALOR DE BAUDRATE 0015 0105 F5 8D MOV TH1A 0016 0108 0017 0108 74 20 MOV A 20H PROGRAMA TIMER 1 EN MODO 2 0018 010A F589 MOV TMCD A 0019 010 0020 010 74 40 MOV A 40H ARRANCA TIMER 1 0021 010E 5 88 MOV TCON A 0022 0110 0023 0110 31 2C
107. lications including local on card regulation This device can also be used to make a programmable output regulator or by connecting a fixed resis tor between the adjustment and output the LM117 series can be used as a precision current regulator Output Current in Excess of 1 5 Ampere in K and T Suffix Packages Output Current in Excess of 0 5 Ampere in H Suffix Package Output Adjustable between 1 2 V and 37 V e internal Thermal Overload Protection internai Short Circuit Current Limiting Constant with Temperature Output Transistor Safe Area Compensation Floating Operation for High Voltage Apolications Standard 3 iead Transistor Packages Fi minautes Stocking Many Fixed Voltages Cin i required if regulator is located an appreciable distance from power supply filter Co is nct needed for stability however it does improve transient response R Vout 125 V 1 RO ladj R2 tice tagj is controlled to less than 100 A the error associated with this negligible in most applications THREE TERMINAL ADJUSTABLE POSITIVE VOLTAGE REGULATORS SILICON MONOLITHIC INTEGRATED CIRCUIT K SUFFIX METAL PACKAGE Bottom View CASE 18 OUTPUT Pins 1 and 2 electrically isolated from cose Case iard electrical connection T SUFFIX PLASTIC PACKAGE CASE 221A PIN 1 ADJUST 2 Vout 3 Vin Hestsink surface connected In Pin 2 H SUFFIX METAL PACKAGE CASE 79 Di Bottom View CASE fry I
108. ll deselected memory devic es are in their low power standby mode and that the output pins are active onty when data is desired from a particular memory device SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re quire careful decoupling of the devices The supply current cc has three segments that are of interest to the system designer the standby current level the active current level and the transient current peaks that are produced by the falling and rising edges of Chip Enable The magnitude of these tran sient and inductive current peaks is dependent on the output capacitive and inductive loading of the device The associated transient voltage peaks can be suppressed by complying with Intel s Two Line Control and by properly selected decoupling capaci tors It is recommended that a 0 1 pF ceramic ca pacitor be used on every device between Vcc and GND This should be a high frequency capacitor for low inherent inductance and should be placed as close to the device as possible tn addition a 4 7 uF bulk electrolytic capacitor should be used between Voc and GND for every eight devices The bulk ca pacitor should be located near where the power sup ply is connected to the array The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board traces PROGRAMMING MODES Caution Exceeding 14V on Vpp will permanently damage the device Initially and after
109. lta del puerto C como salidas y la parte baja del puerto C como entrada durante todo el desarrollo del programa el hecho de que la parte baja del puerto C PCO PC3 se programe como entrada es por que son las l neas que controlan los botones PB1 y PB2 y estos proporcionan siempre una entrada al sistema El sistema ya cuenta con el prototipo de todo el programa en el cual ya est n establecidos todos los mensajes necesarios para la comunicaci n con el usuario tanto en forma independiente mediante el display los leds y el reconocimiento de los botones PB1 y PB2 como en forma dependiente mediante el display y a comunicaci n serial Como consecuencia de esto ya existe completa comunicaci n entre el sistema y cualquier computadora a trav s del puerto serie y mediante rutinas mostradas en el anexo 2 Dentro de estas rutinas existen algunas para leer el contenido de memoria de cualquier parte del sistema rutinas para escribir en cualquier parte de la memoria RAM del sistema rutinas para verificar los distintos voltajes en los pines de control etc Al existir un prototipo del programa principal nicamente restar a hacer un llamado a la rutina correspondiente en el lugar indicado implementando la funci n llamada en alg n otro lugar del programa Se lograron mandar las se ales de control datos y direcciones tanto para lectura como para escritura al socket pero al momento de insertar la EPROM no funcionaban por lo cual se sugiere v
110. mac n temporal del programa principal para realizar ya terminado el sistema no ser necesario su uso Capacidad para 32Kb x 8bits Operaci n est tica Tiempos iguales de acceso para lectura y escritura 5 volts de alimentaci n Compatible con TTL Datos comunes de entrada y salida Esta memoria tipo RAM tiene la finalidad de servir como bu fer del sistema grabador es decir sera donde se almacenen los datos del programa a en la EPROM LM337 Corriente de salida mayor a 1 5 Salida ajustable entre 1 2V y 37V Protecci n t rmica interna Corriente constante con la temperatura Operaci n flotante para aplicaciones de alto voiia e Este regulador de voltaje lo usamos para proporcionar a ics transistores que controlan los voltajes un voltaje de 1 4V PROYECTO TERMINAL _ GR SADOR DE EPROMs AUT NOMO LM317 e Corriente de salida mayor 1 5 A e Salida ajustable entre 1 2V y 37V Protecci n t rmica interna e Corriente constante con la temperatura Operaci n flotante para aplicaciones de alto volta e Este regulador de voltaje lo usamos para proporcionar a los pines del socket los voltajes de programaci n adecuados controlados por los transistores MUA78S40 e Corriente de salida de 1 5 A sin transistor de salida e Salida ajustable entre 1 5V y 40V e L nea de 80dB y protecci n de carga e Soporta desde 2 5V hasta 40V de entrada e Alta ganancia Este convertidor de
111. n OV MAX Vy 0 4 V ELS a E E CEI E Vec MAX Vour 0 V MAX Viy OV MAX Inputs Open SYMBOL PARAMETER AE Ts EST CONOITIONS Turn Delay Input to Output 80 ms 50 Turn On Delay Input to Output 80 n Cy 15 pF NOTES 1 For conditions shown as MIN MAX use the appropriate value specified under recommended operating conditions for the applicable device type 2 imas are t Vec 5 0 V TA 25 3 Not more than one output should he shorted at a time 7541 5 138 T74LS 138 1 8 DECODER DEMULTIPLEXER DESCRIPTION The LSTTL MSI TALETID TIALS IAR ine aged aia Decodar De nultipiexer This device is ideally suited tar high bipolar memory chip select address decoding The multipte input enables allow parallel expansion to a 1 0f 24 decoder using just three 1 5138 devices or to 1 06 32 decoder using four LS138s and one inverter The S138 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all SGS ATES TTL families LU DEMULTIPLEXING CAPABILITY MULTIPLE INPUT ENABLE FOR EASY EXPANSION TYPICAL POWER DISSIPATION OF 32 mW ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS FULLY TTL AND CMOS COMPATIBLE Uy G 9 O 04
112. n Any Pin Relative to Ground Vin Vout 0 3V to 7V Storage Temperature 55 to 150 C Power Dissipation Pp 1 0W DC Continuous Output Current 105 50 mA H H H Read HighZ Ace Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability RECOMMENDED OPERATING CONDITIONS Voltage referenced to Vss Ta 0 C to 70 C Symbol ViH Vin Input High Voltage Iv Input Low Voltage NOTE 1 During transitions the inputs may undershoot to 3 5V for periods less than 20 ns CAPACITANCE T 25 C f 1 0 MHz Parameter NOTE Output Capacitance Vout RE 0v This parameter is sampled and not 100 tested 51256S L 32K x 8 BIT CMOS STATIC RAM Address Access Time taa Chip Select Access Time tacs 100 120 ouput Enable Access Time og s0 079 B Static Operation g Power Down Mode No Clock Refresh Required m TTL Compatible m Equal Access and Cycle Times Common Data Input and Output Simplifies System Design m High Rellability 28 Pin 600 Mil PDIP m
113. n f sica Para el bloque de SOFTWARE tenemos An lisis Para llevar acabo esta etapa se toma en cuenta el bloque anterior en el cual se analizan las necesidades y las posibles formas de cubrirlas Dise o Se proyectan soluciones en diagramas de flujo en base a las diferentes funciones que ser capaz de desarrollar el sistema grabador Implementaci n Aqu se proporciona una relaci n de los c digos fuentes para dar soluci n a cada una de las funciones del grabador En el bloque del MANUAL DE USUARIO se proporciona una gu a paso a paso de c mo debe ser operado el grabador por el usuario P GINA 2 PROYECTO TERMINAL CONTENIDO JUSTIFICACI N OBJETIVO CARACTER STICAS INTRODUCCI N AN LISIS Y DISE O DE HARDWARE IMPLEMENTACI N DE HARDWARE AN LISIS Y DISE O DE SOFTWARE IMPLEMENTACI N DE SOFTWARE RESULTADOS MANUAL DE USUARIO Interfaz de usuario Funcionamiento BIBLIOGRAF A Justificaci n y hojas t cnicas de los 1 5 Listados de programas de prueba Descripci n C digos GRABADOR DE EPROMs AUT NOMO 13 18 25 36 38 38 38 41 ANEXO 1 ANEXO 2 ANEXO 2 ANEXO 2 P GINA 3 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO Justificaci n En el presente proyecto se realizar el dise o de un sistema grabador de EPROMs aut nomo de una PC Esto es que pueda grabar de EPROM a EPROM sin que se tenga que hacer uso de una PC adem s de que tambi n se podr usar para grabar de una PC a una EPROM
114. ode I i INPUT C a1 A0 231308 9 3 105 MODE 0 BASIC OUTPUT MODE 0 PORT DEFINITION 231308 10 A B Group A Group B 7 Fa Port C Port C D D D D Port A PortB 4 3 1 E Upper 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 OUTPUT OUTPUT OUTPUT 0 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 OUTPUT INPUT 5 OUTPUT INPUT T s 0 1 OUTPUT INPUT 6 INPUT OUTPUT L 4 0 OUTPUT INPUT 7 INPUT INPUT INPUT OUTPUT 8 OUTPUT OUTPUT INPUT OUTPUT 9 OUTPUT INPUT INPUT OUTPUT 10 INPUT OUTPUT OUTPUT Hi INPUT i INPUT INPUT 12 OUTPUT OUTPUT T T INPUT INPUT 13 OUTPUT INPUT cmd EN INPUT INPUT 14 INPUT OUTPUT vs t AS ENERO INPUT INPUT 15 INPUT INPUT 3 106 MODE CONFIGURATIONS CONTROL WORD 0 o 0 D D 0 D D pp 0 0 0 D 0 D O x 231308 12 CONTROL WORD 1 D 0 Of D D D D 231308 13 CONTROL WORD 4 D Dg O D 0 D 0 D PA PA PC PC PCy yo PB PB 231208 15 A 3 CONTROL WORD 43 0 0 D 0 0 D 0 D PB PB 231308 14
115. ol Functions Pin Names Data Bus Bi Directional Reset Input Port Address Port B BIT Port C PB7 PB0 PC7 PC0 8255A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software 3 103 Mode 0 Basic Input Output Mode Strobed Input Output Mode 2 3i Directional Bus When the reset input goes high all ports will be set to the input mode i e all 24 lines will be in the high impedance state After the reset is removed the 8255A can remain in the input mode with no addi tional initialization required During the execution of the system program any of the other modes may be selected using a single output instruction This al lows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any 1 structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis AOORESS
116. oltajes de 21 Volts y de O Volts respectivamente tendremos las siguientes asignaciones a PCO B 1 PC1 B 1 PC2 B 0 PC3 B 1 PA1 B 0 b PCO B X PC1 B X PC2 B X PC3 B X PA1 B 1 donde la X significa cualquier valor 1 o 0 Para los pines 20 y 27 funciona de la siguiente manera El PB6 B para el pin 27 y el PB6 B para el pin 20 tienen la funci n de selectores es decir estas l neas establecen si la salida cambia respecto a una PA2 B si PB6 B esta en 1 u otra PB6 A si PB6 B esta en O l nea de contro estos valores son para el pin 27 del socket para el pin 20 funciona de la misma forma el valor obtenido en la salida ser la entrada seleccionada invertida Por ejemplo si queremos que en el pin 27 se obtenga primero un 1 y despu s un O proporcionados por PA2 B tendremos las siguientes asignaciones a PB6 B 1 PB6 A X PA2 B 0 b PB6 B 1 PB6 A X PA2 B 1 donde la X significa cualquier valor 1 o O Las 8255 est n programadas seg n las hojas t cnicas ver anexo 1 de la siguiente manera PPI A se programa con todos los puertos de salida en la fase de escritura de la EPROM en el socket y se programa con los puertos A y B de salida y el puerto C de entrada en la fase de lectura de la EPROM en el socket esto es por que el puerto C de la PPI A maneja los datos P GINA 36 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO PPI B se programa con los puertos A B y la parte a
117. or y la PC C mo debe de ser el programa que controle al grabador y C mo ser el programa que controle a la PC Para responder a estas preguntas de debe de analizar con que es con lo que se cuenta en cuanto a hardware y en cuanto a software y ver si con esto es suficiente o si necesitamos implementar algo mas Evidentemente para solucionar el problema de comunicaci n entre la PC y el grabador dadas las caracter sticas del microcontrolador que cuenta con las salidas adecuadas para este fin TXD y RXD se puede usar un RS232 que es una interfaz serial Lo que se debe de hacer entonces es implementar el hardware necesario en la figura 6 se muestran las conexiones para este prop sito FIGURA 4 DIAGRAMA INICIAL DEL GRABADOR P GINA 11 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO FIGURA 5 CIRCUITO PROPUESTO PARA INTERFAZ CON EL USUARIO em PA4 B LED 1 naranja Modo depend Indep PA6 B LED 3 rojo No remover 3300 LED 3 verde remover PA7 B V PB1 ENTER PC6 B z PB2 Selector PC7 7 FIGURA 6 Interfaz serial 232 CONECTOR DB9 P GINA 12 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO IMPLEMENTACI N DEL HARDWARE Despu s de todo este an lisis ya se puede decidir que componentes se utilizar n para llevar acabo el proyecto En la figura 7 se presenta la distribuci n f sica de estos en el grabador d
118. ormance speeds and immunity to noise The 87C64 has been optimized for multiplexed bus microcontroller and microprocessor compatibility while the 27C64 has a non multiplexed addressing interface and is plug compatible with the standard Intel 2764A HMOS II E The 27C64 and 87 64 are offered in both a ceramic Plastic DIP and Plastic Leaded Chip Carrier PLCC Packages Cerdip packages provide flexibility in prototyping and R amp D environments whereas Plastic DIP and PLCC EPROMS provide optimum cost effectiveness in production environments A new Quick Pulse Program ming Algorithm is employed which can speed up programming by as much as one hundred times The 87C64 incorporates an address latch on the address pins to minimize chip count in multiplexed bus systems Designers can eliminate an external address latch by tieing address and data pins of the 87C64 directy to the processor s multiplexed address data pins On the falling edge of the ALE input ALE CE address information at the address inputs 42 of the 87C64 is latched internally The address inputs are then ignored as data information is passed on the same bus The highest degree of protection against latch up is achieved through Intel s unique EPI processing Preven tion of latch up is provided for stresses up to 100 mA on address and data pins from 1V to Voc 1V HMOS and CHMOS are patented processes of Intel Corporation DATA OUTPUTS 99 9
119. ortwave ultraviolet light which has a wavelength of 2537 Angstroms A The integrated dose i e UV intensity x exposure time for erasure should be a minimum of 15 Ws cm2 The erasure time with this dosage is approximately 15 to 20 min utes using an ultraviolet lamp with 12000 u W cm power rating The 2716 should be placed within 1 inch of the lamp tubes during erasure ADORESS FIRST LOCATION Vec 5 0 Vpp 25 0 PROGRAM ONE 50 PULSE INCREMENT ADDRESS YES Voc Vpp 5 0 DEVICE FAILED 210310 3 Figure 3 Standard Programming Flowchart intel 2732A 32K 4K x 8 UV ERASABLE PROMS 200 ns 2732A 2 Maximum Access m Low Current Requirement Time HMOS E Technology 100 mA Active m Compatible with High Speed 35 mA Standby Microcontrollers and Microprocessor m intelligent identifier Mode Zero WAIT State Automatic Programming Operation Two Line Control m industry Standard Pinout JEDEC 10 Vcc Tolerance Avallabie Approved 24 Pin Ceramic Package See Packaging Spec Order 231369 The Intel 2732A is a 5V only 32 768 bit ultraviolet erasable cerdip Electrically Programmable Read Only Memory EPROM The standard 2732A access time is 250 ns with speed selection 2732A 2 available at 200 ns The access time is compatible with high performance microprocessors such as the 8 MHz iAPX 186 In these systems the 2732A allows the microprocessor to operate w
120. oughput time in the production environment This algorithm allows the device to be programmed in under two seconds almost a hundred fold improvement over previous algorithms Actual programming time is a function of the PROM programmer being used ne Quick Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri fication to determine when the address byte has been successfully programmed Up to 25 100 us pulses per byte are provided before a failure is rec ognized A flowchart of the Quick Pulse Program ming Algorithm is shown in Figure 5 For the Quick Pulse Programming Algorithm the en tire sequence of programming pulses and byte verifi cations is performed at Vcc 6 25V and Vpp at 12 75V When programming of the EPROM has been completed all bytes should be compared to the original data with Vcc Vpp 5 0V a intel 27256 256K 32K x 8 PRODUCTION AND UV ERASABLE PROMS New Quick Pulse Programming m Plastic Production P27256 is Algorithm for Plastic P27256 Compatible with Auto Insertion 4 Second Programming Equipment inteligent Programming Algorithm m Moisture Resistant Compatible Fast Access Time 170 ns D27256 1 200 ns P27256 2 m intgligent IdentifierTM Mode m Industry Standard Pinout JEDEC Approved 28 Lead Cerdip and Plastic Package See Packaging Spec Order 231369 The Intel 27256 is a 5V only 262 144 bit Ultrav
121. re programmed with the same data A low level TTL pulse applied to the CE input programs the paralleled 2716s Program Inhibit Programming of multiple 2716s in parallel with differ ent data is also easily accomplished Except for CE all like inputs including OE of the parallel 2716s may be common A TTL level program pulse applied to a 2716 s C input with Vpp at 25V will program that 2716 A low level CE input inhibits the other 2716 from being programmed Verify A verify should be performed on the programmed bits to determine that they were correctly pro grammed The verify may be performed with Vpp at 25V Except during programming and program veri fy Vpp must be at 5V ERASURE CHARACTERISTICS The erasure characteristics of the 2716 are such that erasure begins to occur upon exposure to light with wavelengths shorter than aproximately 4000 Angstroms A It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 4000 range Data show that constant exposure to room level fluorescent lighting could erase the typical 2716 in approximately 3 years while it would take approximately 1 week to cause erasure when exposed to direct sunlight If the 2716 is to be exposed to these types of lighting conditions tor extended periods of time opaque labels should be placed over the window to prevent unintentional erasure x The recommended erasure procedure for the 2716 is exposure to sh
122. ria RAM etc pero en el presente proyecto se intentara el dise o de un grabador aut nomo P GINA 6 PROYECTO TERMINAL GRABADOR DE EPROMs AUT NOMO AN LISIS Y DISE O DEL HARDWARE Dado que lo que se necesita es dise ar un grabador de EPROMs lo primero que se debe de analizar es la configuraci n de los pines para cada una de estas memorias En base a un an lisis de las terminales que presentan los diferentes modelos de EPROMs con los cuales se podr trabajar que van desde la 2716 hasta la 27512 se observ que existen 7 terminales que difieren tal como se observa en la siguiente tabla Como puede observarse algunos modelos son de 28 pines y otros de 24 Analizando la figura se obtiene la siguiente relaci n de voltajes en la que podemos observar de acuerdo al tipo de EPROM que voltaje necesita para cada uno de los pines en los cuales se aplica alg n voltaje 21 12 5 5 12 5 5 Vcc 6 5 5 6 NC A13 5 0 11 5 0 A11 5 0 A11 5 0 A11 5 0 A11 5 0 OE 5 0 5 0 CE OE Vpp 5 0 5 0 CE 5 0 NOTA En la columna del PIN se observan expresiones para dos n meros diferentes de pines esto es porque los pines son diferentes dependiendo si son EPROMs de 24 o de 28 pines Los n meros entre par ntesis de las dem s columnas se refieren a los diferentes voltajes que se necesitan en esos
123. rogramming Algorithm been successfully programmed Up to 25 100 us pulses per byte are provided before a failure is rec ognized A flow chart of the Quick Pulse Program ming Algorithm is shown in Figure 4 For the Quick Pulse Programming Algorithm the en tire sequence of programming pulses and byte verifi cations is performed at Vcc 6 25V and Vpp at 12 75V When programming of the EPROM has been completed ali bytes should be compared to the original data with Voc Vpp 5 0V In addition to the Quick Pulse Programming Algo rithm Plastic EPROMs are also compatible with In tel s intgligent Programming Algorithm a O O O DO O DO O NN intel 270128 128K 16K x 8 CHMOS PRODUCTION AND UV ERASABLE PROMs m CHMOS Microcontroller and _ W High Performance Microprocessor Compatible 150 ns Access Time 8 Low Power Consumption m Quick Pulse Programming Algorithm 100 LA Maximum Standby Current Allows Rapid Automated Programming m Maximum Latch Up Immunity Through 2 Second Throughput Processing m Available in 28 Pin Cerdip and 32 Lead 1V Input Protection PLCC Packages 14V Vpp Protection See Packaging Spec Order 231369 Intel s 27C128 CHMOS EPROM is a 128K bit 5V only memory organized as 16 384 words of 8 bits each The 27 128 is ideal for systems requiring low power high performance and noise immunity due to its CHMOS II E processing and it is pin compatible
124. ronics inc INTRODUCING TO EPROM PROGRAMER 1 11 41 PROYECTO TERMINAL GH DE EPROMs AUT NOMO ANEXO 1 JUSTIFICACI N Y HOJAS T CNICAS DE CIRCUITOS INTEGRADOS PROYECTO TERMINAL Gk 4DOR DE EPROMs AUT NOMO 8031 e microcontrolador de 8 bits e 4 puertos de 8 bits cada uno e Memoria RAM interna de 128 x 8 bits 2 timers de 16 bits e Interrupciones Tecnologia HMOS El uso de este chip se basa en la existencia y prec o que de el se obtuvo en el mercado as como de contar con las terminales necesarias para manejar informaci n de 8 bits y direcciones de 16 bits aue son caracteristicas del grabador 74245 e Buffer bidireccional octal de tres estados e Terminal para habilitar salidas e Control para transmisi n y recepci n e Canal bidireccional de 8 bits e Estado de alta impedancia Este circuito debido a sus 8 bits y a sus tres estado permite el intercambio de informaci n en este caso del microcontrolador con ei resto del grabador e Latch octal con salida en tercer estado Control de entradas al latch Control de salidas del latch e Canal de 8 bits para datos de entrada Canal de 8 bits para datos de salida en tercer amp s ado Para este circuito se toma en cuenta su capacidad ara el manejo de 8 bits y su estado de alta impedancia 74138 8255 e Decoficicador y demultiplexor de tres a ocho e res entradas
125. se types initial and overprogram The duration of the initial pulse s is one millisecond which will then be followed by a longer overprogram pulse of length 3X msec X is an iteration counter and is equal to the number of the initial one millisec ond pulses applied to a particular location before a correct verify occurs Up to 25 one millisecond puls es per byte are provided for before the overprogram pulse is applied The entire sequence of program pulses and byte verifications is performed at Vcc 6 0V When the inteligent Programming cy cle has been completed all bytes should be com pared to the original data with Vcc 5 0V A et 91 T54LS00 T74LS00 QUAD 2 INPUT NAND GATE GUARANTEED OPERATING RANGES TEMPERATURE PART NUMBERS MIN 55 to 125 C 0 C to 70 C T54LS00X 45 V T74LSOOX 475v X package type D for Ceramic Dip B for Plastic Dip See Packaging information Section tor packages available on this product OC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE unless otherwise specified LIMITS SYMBOL PARAMETER UNITS TEST CONDITIONS Note 1 Guaranteed Input HIGH Voltage Input HIGH Voltage 414 Vi Input LOW Voltage Guaranteed Input LOW Voltage Veo Input Clamp Diode Voltage MIN Un 718 mA Output HIGH Voltage Vec 7 MIN 400 yA Ving Vi 7 54 74 Voc MIN Igy 40 mA 20
126. ssing 8K x 8 ROM 256 x 8 RAM 4K x 8 ROM 128 x 8 RAM 4K x 8 ROM 128 x 8 RAM none 256 x 8 RAM none 128 x 8 RAM none 128 x 8 RAM 4K x 8 EPROM 128 x 8 RAM 4K x 8 EPROM 128 x 8 RAM 8751H 88 4K x 8 EPROM 128 x 8 RAM 2x 2x 3x 2 2 2 2 2x The 8751H is an EPROM version of the 8051AH that is the on chip Program Memory can be electrically programmed and can be erased by exposure to ultraviolet light It is fully compatible with its predecessor the 8751 8 but incorporates two new features a Program Memory Security bit that can be used to protect the EPROM against unauthorized read out and a programmable baud rate modification bit SMOD SMOD is not present in the 8751H 12 or the 8751H 88 The 8751H 88 also only operates up to 8 MHz 8031 8051 8031AH 8051 AH 8032AH 8052AH e 8751H 8751H 12 8751H 88 PRELIMINARY Figure 1 MCS 51 Block Diagram PIN DESCRIPTIONS Supply voltage vss Circuit ground Port 0 Port 0 is an 8 bit open drain bidirectional port As an output port each pin can sink 8 LS TTL inputs Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external Program and Data Memory this application it uses strong inter nal pullups when emitting 1s and can source and sink 8 LS TTL inputs Port 0 also receives t
127. tact your iocal Motorola sales office lor information THREE TERMINAL ADJUSTABLE NEGATIVE VOLTAGE REGULATORS SILICON MONOLITHIC INTEGRATED CIRCUIT K SUFFIX METAL PACKAGE CASE 1 Bottom View CASE IS INPUT Pins 1 and 2 electrically isolated from cate Case 1 third electrical connection T SUFFIX PLASTIC PACKAGE CASE 221A PIN 1 ADJUST 2 Vin 3 Vout Heatsink surfac connected 10 Ping H SUFFIX METAL PACKAGE CASE 79 Bottom View CASE IS INPUT PIN 1 ADJUST 2 OUTPUT 3 1NPUT ORDERING INFORMATION Tj 55 150 C Mets Can T LUMIX Meta Power 237 IT 25 C to 150 1 Meta Can M232K wd Power 1 LM337H Meta Can LM337K OC to 125 C Metai Power LM337T 52 j Plastic Power 1M337BT8 40 io 125 C Prastic Power MOTOROLA LINEAR INTERFACE DEVICES 3 43 la MOTOROLA SEMICONDUCTOR E E e TECHNICAL DATA THREE TERMINAL ADJUSTABLE OUTPUT POSITIVE VOLTAGE REGULATORS The 117 217 317 are adjustable 3 terminal positive voltage regulators capable of supplying in excess of 1 5 A ove an output voltage range of 1 2 V to 37 V These voltage regulators are ex ceptionaliy easy to use and require only two external resistors to set the output voltage Further they employ internal current lim Ming thermal shutdown and safe area compensation making them essentially blow out proof The LM117 series serve a wide variety of app
128. te 2 Determinar las funciones que tendr el grabador en base a el modo de trabajo elegido En el caso de que sea de modo aut nomo se podr n realizar las operaciones de GRABAR y COMPARAR En el caso de que sea en modo dependiente se podr n realizar las operaciones de CARGAR DE PC A BUFFER CARGAR DE BUFFER A PC COPIAR BUFFER A EPROM COPIAR EPROM A BUFFER COMPARAR EPROM CON BUFFER VERIFICAR SI EPROM BORRADA y SELECCIONAR TIPO las cuales ya han sido descritas anteriormente 3 Implementar cada una de las funciones en base al modo de trabajo elegido Antes de la implantaci n del software se dise aron algunos diagramas de flujo principales que nos marcan la forma en la que tienen que funcionar los programas En el diagrama de flujo 1 se muestra lo que ser a el men principal con el cual podemos elegir el modo de trabajo Notamos claramente lo que se menciono acerca de las funciones de los botones PB1 y PB2 donde PB2 nos sirve para desplazarnos en los men s y PB1 para aceptar la opci n escogida por PB2 Al inicio se espera a que se pulse PB2 para iniciar despu s se desplaza a modo Independiente y modo d ependiente en forma alternada mientras se este presionando PB2 Si estando en d se presiona PB1 entonces nos iremos al men del modo dependiente y si estamos en se presiona PB1 nos iremos al men del modo independiente En el diagrama de flujo 2 observamos el men del modo de trabajo independient
129. using the Quick Pulse Programming Algo rithm developed by Intel to substantially reduce the throughput time in the production environment This algorithm allows these devices to be programmed in under one second almost a hundred fold improve ment over previous algorithms Actual programming time is a function of the PROM programmer being used The Quick Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri fication to determine when the address byte has been successfully programmed Up to 25 100 us pulses per byte are provided before a failure is rec ognized A flowchart of the Quick Pulse Program ming Algorithm is shown in Figure 5 For the Quick Pulse Programming Algorithm the en tire sequence of programming pulses and byte verifi cations is performed at Vcc 6 25V and Vpp at 12 75V When programming of the EPROM has been completed all bytes should be compared to the original data with Vcc Vpp 5 0V intel 27128A 128K 16K x 8 PRODUCTION AND UV ERASABLE PROMs m Fast 150 nsec Access Time m New Quick Pulse Programming HMOS 11 E Technology Algorithm Used on Plastic DIP Low Power 100 mA Maximum Ave elena Algorithm 40 mA Maximum Standby Compatible inteligent identifier Mode m 10 Vcc Tolerance Available Automated Programming Operations m Available in 28 Pin Cerdip and Plastic 2 Packages See Packaging Spec Order 231369 The Intel 2
130. with the standard Intel 27128A The 27C128 is offered in Ceramic DIP and Plastic Leaded Chip Carrier PLCC Packages Cerdip packages provide flexibility in prototyping and R amp D environments while the PLCC package is most cost effective in production environments The Quick Pulse ProgrammingTM Algorithm improves programming speed by as much as one hundred times over older algorithms further reducing costs for system manufacturers Intel s unique EPI processing provides excellent latch up immunity Prevention of latch up is guaranteed for stresses up to 100 mA on address and data pins from 1V to Vcc 1V and for Vpp voltage overshoot up to 14V HMOS and CHMOS are patented processes of Intel Corporation v DATA OUTPUTS cc Oo Oo 0 GNO pr rs Vee gt OE OUTPUT ENABLE PGM CHIP ENABLE AND CE PROG LOGIC OUTPUT BUFFERS ma AODRESS x INPUTS 131 072 B1T CELL MATRIX 1 290127 1 Figure 1 Biock Diagram inter 270128 Pin Names NOTE Intel Universal Site Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the 27C 126 Pins Figure 2 Cerdip D Pin Configurations 32 PIN PLCC BIBIEIBIEITIBIBIE E 0 450 0 550 11 430 X 13 970 MILLIMETERS TOP VIEW ox Tou e To os Figure 3 PLCC N Lead Configuration v 127 3 intel 270128 READ MODE T
131. y the inductive affects of PC board traces ADORESS FIRST LOCATION PROGRAM ONE 50 ms PULSE INCREMENT Y NO ADDRESS Figure 3 Standard Programming Flowchart PROGRAMMING MODES CAUTION Exceeding 22V on DE Vpp will perma nently damage the device Initially and after each erasure cerdip EPROMs all bits of the EPROM are in the 1 state Data is intro duced by selectively programming 08 into the bit locations Although only Os will be programmed both 18 and Os be present in the data word The only way to change a 0 to a 1 in cerdip EPROMs is by ultraviolet light erasure The device is in the programming mode when the OE Vpp input is at 21V it is required that a 0 1 uF capacitor be placed across OE Vpp and ground to suppress spurious voltage transients which may damage the device The data to be programmed is applied 8 bits in parallel to the data output pins The levels required for the address and data inputs are TTL When the address and data are stable a 20 ms 50 ms typical active low TTL program pulse is ap plied to the CE input A program pulse must be ap plied at each address location to be programmed see Figure 3 Any location can be programmed at any time either individually sequentially or at ran dom The program pulse has a maximum width of 55 ms The EPROM must not be programmed with a DC signal applied to the CE input Programming of multiple 2732As in paraile

GRABADOR DE EPROMs AUT~NOMO

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