KEK-AMS-TDC-VME 取扱説明書（User`s Manual）
Contents
1. 7 other 1 P19 Dual Port RAM M S select 1 4 open U35 master busy output 1 4 short U35 slave busy input b 1 4 open U37 master Dusy output 1 4 short U37 slave busy input 2 P14 15 16 17 1 2 3 4 connector GND P14 short 1 connector GND b P15 short 2 connector GND P16 short 3 connector GND d J P17 short 4 connector GND 3Front Panel P21 SCI connector JP18 EVNTBUNCHRST input D5 DSPLED D3 VMELED D4 measurement LED 15 START input LEMOConnecter 00000 STOPinput LEMOConnecter 00000 7 TRGinput LEMOConnecter 00000 18 SYNCoutput LEMOConnecter 00000 3 51 External Reset HHHHHHH HHHECLorLVDS 00000000 1 No 1pin 1 No 32pin 40 4 15 G 0 1 15 16 31 16 31 12 J3 G 32 47 G 32 47 48 63 6 48 63 4 4 J3 2 11 1 4 VME Connector 00 bust Pin J1A1 181 J1C1 2A1 1281 1261 1 DO BBSY D8 45V 2 D1 BCLR D9 GND 3 D2 ACFAIL D10 4 D3 BGOIN D11 A24 5 D4 8 00 D12 A25 6 D5 BG1IN D13 A26 7 D6 BG1OUT 014 27 8 7 BG2IN2. Pagel 7 4000 FFFF DATAHHHH 4000 EFFFHHHHHHHHHHHHH ProgramHHHH 4000 7FFFHHHHHHHHHHHHH DATAHHHHH 00 0 0 RAM 0 4000 7 D U 12 Data 0000 Internal RAM 4000 Dual Port RAM 16K X 16 Program 0 0 0 000 8000 Dual Port RAM 28K X 16 22000 F 000 F 000 AMTO DATA mm AMT1 DATA F 004 AMT2 DATA F 006 F007 AMT3 DATA 42400 F 400 AMTO Internal REG sF500 F 800 REG Flash ROM Boot ROM F 600 F 700 F 800 AMT2 Internal REG Internal REG Page0 Program 7 Program Internal RAM Dual Port RAM Data 00000 16K x 16 Flash ROM 48K X 16 Flash ROM 28K X 16 13 6 1 Control CPLD Internal Register Base Address FE00 SP REG 15 14 113 1 7 66 4 6 4 3 2 1 CNTR VCNTR VSTR 0 1 STAR 2 3 4 STPCR Start mode measurement time Note DSP DSP bus offset 1 Control Register CNTR R W Bit15 5 enable
3. 0 16 Dual port RAM DP map DSP Add VME add 31 contents 0 Direction 8F 80 DPtop Module Control parameters VME gt 8Dword 1 Reserved 0040 Offset table VME gt 1 64word Reserved 8FF0 00E0 AMT Board Monitor Data lt AMT 3DWord Reserved 9000 50100 Recording data buffer lt AMT Fix length Max8K DWord Dptop VME BASE 11F00 HHHHHHHIFHHHHHHHHHHHDSPHHHHHHHHHH 17 Module Control parameter gt DSP Add VME add 31 contents 0 8F 80 DPtop Pcount 1 Parameter counter 16bit 6 82 0004 RunStatus bitmap BitO not used Bit1 start measurement 1 start defult 0 Bit2 Common start stop 1 stop mode defult Bit3 4 Edge detection dedge 0 rising defult rising and falling 2 falling 3 rising and width Bit5 6 Subtract offset dsuboff 0 don t subtract defult input data 2 subtract using offset table 3 don t subtract Bit7 measurement control 0 TRG measurement defult 1 Nomal measurement Bit28 30 width select 0 7 defult O 8F84 50008 Time range count dcount 1266 Rectime 25ns x dcount 8F 86 000C Module ID 8F88 0010 CH_Enable 81 MSB 0 LSB 8F 8A 0014 CH_Enable 53 MSB 32 15 8F8C 50016 Number of partitions 1266 450018 lcount Inpu
4. 20 Common start stop time D31 028 D24 023 D22 D20 019 018 017 016 1 1 0 ModulelD 0 Width select Edge MC Common detection 1 start stop time D15 DO Common start stop time 17bit 1 measurement control Hit data D31 D28 D25 D20 519 D16 0 0 0 F R 66 0 63 HIT time data F R Edgedirection Falling 2L Rising 0 CH Refer Appendix A Module Ch assignment D15 DO HIT time data 20bit offset from common start stop ti ming Error Report if exists D31 D28 D24 D23 D18 D17 D16 0 1 1 ModulelD Unused OVR ERR D15 D13 DO Error Flag Refer AMT1 amp 2 User s Manual 8 2 10 21 End of data II End of data 5555 D15 DO Event AppendixA Ch assignment AMT ChChip Ch M odule AMTO to 23 3 0 to 23 AMT1 0 23 24 to 47 AMT2 40 to 415 48 to 63 0 Start Stop 22 80000 HHTRGHHHHHH RedtHHHH COMMONSTART startlHHHHHHHHHHHHHH HHHHHHHH0 7
5. D15 A28 9 GND BG2OUT GND A29 10 SYSCLK BG3IN A30 11 GND BG3OUT BERR Z A31 12 DS1 880 RESET GND 13 50 BR1 LWORD 5V 14 WRITE BR2 AM5 D16 15 GND 883 23 D17 16 A22 D18 17 GND AM1 A21 D19 18 AS AM2 A20 D20 19 GND AM3 A19 D21 20 IACK GND A18 D22 21 IACKIN SERCLK A17 D23 22 IACKOUT SERDAT 16 GND 23 GND A15 D24 24 7 IRO7 A14 D25 25 IRO6 A13 D26 26 5 IRO5 A12 D27 27 4 IRO4 A11 D28 28 IRO3 A10 D29 29 2 IRO2 A9 D30 30 IRO1 A8 D31 31 GND 32 45V 5V 5V 5V 5 VME memory 10000000 xxxFFFFF xxx7F FFF Dual Port RAM 32K x32 64K x 160 xxx60000 xxx5F F 08 Internal Register xxx5FF 00 FLASHROM 160K x 16 xxx50000 xxx00000 1 flash rom word access 0 LI bytelong word access Time out bus err boot program xxx1F 000 xxx1FF FE 2 Dual Port ram word long word access 60000 7FFFE DSPHHHHHHHH 68000 7DFFE DSP 4000 EFFFT 10 3 CPLD Internal Register Base Address 5FF 00 DSP VME REG Bit7 Bit6 8 5 8 4 Bit3 Bit2 Bit1 BitO X 0 VECTR Vector cord 2 2 VCNTR FWE HE RE VEN IRQ IEN BRST 3 4 VSTR IRO VEN RST X 6 ADCNTR Start address X 8 DCNTR Data size Notes DSP DSP bus offset VME VME bus
6. disable 000 Bit14 ENCNT enable enable disable Bit13 notuse Bit12 notuse Bit11 INTO enable enable disable Bit10 not use Bit9 INT1enable enable disable 100 Bit8 100us output enable enabld disable 000 Bit7 00000 COMSTOP COMSTART Bit6 0000 START STOP 100 Bit5 TRGO nomale 100 Bit4 CLKO enable enable disable Bit3 BUNCHRST enable disable 40M 1000000 00000 90000000 Bit2 EVENTRST enable disable 40M 1000000 readH 10000 bt8HHHHHHH Bit1 UART RST enable disable 40M 1000000 00000 070000000 AMTRESET enable disable 40M 1000000 read 000 10000 070000000 14 2 Status Register STAR Read only Bit15 Bit14 External bit13 External read bit12 External 1 100000000 stop status read Start status trg status read bit11 P23 1 4 status Bit10 JP23 2 3 status Bit9 read EVE
7. 6 CIk mode x 15 PII x 10 PII x5 PII x2 PII x 1 1 2 pll disabled 0 1 1 4 pll disabled 4 AMT a 1 J P4 AMT2 U2 ASD mode select 1 2 short ASD mode 2 3 short parallel data output 2 P6 AMT2 U5 ASD mode select 1 2 short ASD mode 2 3 short parallel data output 3 AMT2 U6 ASD mode select 1 2 short ASD mode 2 3 short parallel data output a 4 P10 AMT2 U7 ASD mode select 1 2 short ASD mode 2 3 short parallel data output 1 P2 AMT2 U2 serial data connector 2 AMT2 U5 serial data connector b 3 P7 AMT2 U 6 serial data connector b 4 PS AMT2 U 7 serial data connector P3 AMT2 TAG connector 5 SCI interface 1 HHHHHHHHHHHHHH 1 20 1 2 short JP22 2 3 short 100000000000 JP20 2 3 short JP22 L2 short 6 CPLD P1 ISP connector 2 P23 program select open 1 short 0 2 3 1 4 ProgramHHHHHHHHHH 0 0 DSP 82000 FFFF VME xxx30400 5 xx3FF F E 0 1 DSP page2 82000 FFFF VMEH 1 0 DSP 82000 FFFF VMEH LH 1 1 DSP page4 82000 FFFF VMEH 1000 00000000 4 L programi
8. EAHHHHHH Time range counter 125 0000000 258 COMMONSTOP stopHHHHHHHHHHHH 7EAHHHHHHHHHHHHHH 00 00000 COMMON START start 00000000000000 HHHHHHHH0 FFEHHHHHH Time range counter 125 25 COMMONSTOP HHHHHHHHHHHHH coarsecounter1HH 2HHHHHHHHHH 0000 10 5 23
9. KEK AM TDC Hl erS Manual 2001 Oct O9th Rev0 1 2001 Od 18th Rev0 2 2001 Deg28 Rew0 3 2002 F eb 28th Rev0 4 2002 Mar 22th Rev0 5 AMSC Co Ltd Development Section ndex 1 2 3 2 1 AM WE unper Sw tch Front Panel VME Connect or VME nap nap 6 1 Control CPLDInternal Regi ster Dual Port RAM For nat 1 100 64ch AMT VME Module 1ns bit TMC304 VME TDC AMT2 6U 64ch VME 32bit 16bit DSP TMS320VC5402 AMT2 32bit DualPortM emory 32bit Dual Port M emory KEK AMS TDC VM E User s Manual 2 AMT VME I I 0 KEK AMS TDC VME User s Manual 2 1 Junper Swtch 1 Menary Mappi ng WE Address HHHHHHHHHHHH 5 8 S
10. M Register Address Sel ect 9 8 A31 24 select oyoff 0 1 SW 1 on 1 A31 2 A30 8 24 SM 23 19 select on off 0 1 2 3 22 6 19 2 HHHHHHHH JP30 WE Bus IRO Level Sel ect MEBusHHHHH IROHHHHHHHHHHHHHHHHHHHHHHH shortHHHHH 2 I RO 34 5 6 78 9 10 11 12 R 13 14 8 b SV IRQ Level Select WE Gortroler PLD US se 0000 10000000000000 Q df on 2 off of 3 1 e df df on 6 3 J P13 DSP TAG 1 P12 Microprocessor microcomputer mode select lf active low at reset microcomputer mode is selected and the internal program ROM is mapped into the upper 4K words of program memory space If the pin is driven high during reset microprocessor mode is selected and the on chip ROM is removed from program space This pin is only sampled at reset and the MP MC bit of the processor mode status PMST register can override the mode that is selected at reset short open 20 1 11 05 Mode Select short open 0 1 Clock mode setting at reset 1 3 4 5
11. NTRES Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 00 read 5 read DSP DSPLED AMTHHH 10 AMTLED AMT1 3 AMT1 2 AMT1 1 AMT1 0 HIT HIT HIT START STOP 1 0 hit not hit 21 0 hit not hit 21 0 hit not hit 21 0 Reset not reset 21 0 Reset not reset 21 0 Reset not reset 21 0 ERR not ERR 1 0 1 0 000 170 HIT Empty 1 0 HIT Empty 1 0 HIT Empty 1 0 HIT Empty 1 0 15 3 VME Control Register VCNTR R W bit3 DSP HOLD bit0 Interrupt enable bit1 Interrupt signal from DSP to VME clear after IACK disable bit0 Board Reset We most disable after enable 4 VME status Register VSTR Read only bit3 Interrupt status clear after read bit2 action status VME LED bit1 board reset status clear after read bit0 DSP HOLD acknowledge 5 STOP Counter Register STP CR R W 12bit 0000 measurement time 0ns 100us 25 enable di sable 1 0 enable di sable 1 0 enable di sable 1 0 enable di sable 1 0 1 0 1 0 reset not reset 1 0 hold not hold
12. offset a Vector register VECR R W Vector code for interrupt b control Register CNTR R W bit7 Flash access enable enable disable 1 0 bit6 HOLD enable enable disable 1 0 bit5 Board reset enable enable disable 1 0 bit4 action enable disable 1 0 bit3 DSP HOLD enable disable 1 0 bit2 Interrupt enable enable disable 1 0 bit1 Interrupt signal from DSP to VME enable di sable 1 0 Not Automatic disable bit0 Board Reset enable disable 1 0 Not Automatic disable C status Register STR Read only bit3 Interrupt status 21 0 dear after read bit2 VME action status 21 0 VME LED bit1 board reset status clear after read bit0 DSP HOLD acknowledge reset not reset 21 0 hold not hold 21 0 11 6 DSP Memory MAP 1 Flash 10000 ROM F800 FFFF 411111 111 10111 Program FlashROMHHHHHHHHHHH 2 Dual Port RAM 3 AMT 4 UART AMT O 3 Register DATA 0 SF400 F 7FF 0 0 0 512word 1 BHO B BLU B 7 D AMT O 3 DATA DATA 0 F 000 F 007 2word LI LI 1000000000 01000 00 4000 50000 000000000000 5 Control CPLD Internal Register 01 00000 page0 8000 5EFFF Boot program
13. t counter 16bit 18 Offset table gt DSP Add VME add 31 contents 0 Dptop Offset 0 16bit signed Offset 16bit signed 0040 8FA2 0044 Offset 2 16bit signed Offset 16bit signed 8FDE 007C Offset 62 16bit signed Offset 1463 16bit signed RunStatus 65 60 00 0000000000000 2000000000000 0000000000000 Offset chxx 000000000000 AMT Board Monitor Data AMT VME DSP Add VME add 31 contents 0 8FFO Dptop EchoPcount 16bit Copy of 00E0 Parameter counter 8FF2 00E4 AMT Status 0 wait l running 2 end 1 error 8FF4 00E 8 Scount Save counter 16bit 19 data buffer AMT VME variable length DSP Add VME add 31 contents 0 9000 Dptop Recodin9 0100 Data Block 0 Recoding Data Block 1 IlcountH HHHHHH Recoding Data Block n EFFF BFFC Scount 0 0 0000 Recoding Data Block 31 contents 0 Recording data Status Common start stop time Hit datax Error Report if exists End of data 000 Recording data Status D31 D28 D16 1 1 Total recording data tntotal include header amp footer unit DWord D15 DO Event
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