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8x931AA, 8x931HA Universal Serial Bus Peripheral

1. Address amp Data Input Output USB Name Pin Name Pin Name Pin AD6 P0 6 KSI6 1 P3 0 OVRI 10 PLLSEL 32 AD5 P0 5 KSI5 2 P3 1 SOF 11 ECAP 42 AD4 P0 4 KSI4 3 P3 2 INTO 12 43 AD3 P0 3 KSI3 4 P3 3 INT1 13 44 AD2 PO0 2 KSI2 5 P3 4 TO KSO16 14 FSSEL UPWEN 50 AD1 P0 1 KSI1 6 P3 5 T1 KSO17 15 OVRI 10 ADO PO 0 KSIO 7 P3 6 WR KSO18 16 Dpot 36 A15 P2 7 KSO15 56 P3 7 RD KSO19 17 35 A14 P2 6 KSO14 57 P1 0 T2 KSOO 18 Dp3 38 A13 P2 5 KSO13 58 P1 1 T2EX KSO1 19 Du3t 37 A12 P2 4 KSO12 59 P1 2 KSO2 20 Dp4 48 A11 P2 3 KSO11 60 P1 3 KSO3 21 Dy4 47 A10 P2 2 KSO10 61 P1 4 KSO4 22 Dps 46 A9 P2 1 KSO9 62 P1 5 KSO5 23 Dust 45 A8 P2 0 KSO8 63 P1 6 RXD KSO6 24 AD7 P0 7 KSI7 64 P1 7 TXD KSO7 25 Processor Control Power amp Ground Bus Control amp Status Name Pin Name Pin Name Pin XTAL1 28 Vcc 9 PSEN 51 XTAL2 29 AVcc 30 ALE 52 RST 81 Vss 39 55 EA 53 P3 2 INTO 12 Voce 40 54 WR 16 P3 3 INT1 13 Vssp 8 RD 17 41 49 t Specific to the 8x931AA tt Specific to the 8x931HA 8x931AA 8x931HA USER S MANUAL Table B 7 Signal Description Sheet 1 of 3 intel Signal Name Type Description Alternate Function A15 8 AD7 0 ALE AVcc VO PWR VO Address Lines Upper byte of external memory address Address Data Lines Lower byte of external memory address multiplexed with data Address Latch Enable A
2. enne nnne nennen nnn B 6 64 pin SDIP Pin Assignment sssesseeeeeeeeneneee nennen nennen nnn B 7 64 QFP Pin Assignment RR RERO ERR B 8 68 PLCC Signal Assignments Arranged by Functional Category B 9 64 pin SDIP Signal Assignments Arranged by Functional Category B 10 64 pin QFP Signal Assignments Arranged by Functional B 11 Signal Desctiptiori 3 eat UE B 12 8x991 MA SFR Map edo nece etre data C 2 Core Ate esses die E TA C 3 Interrupt System SFR Sp urere re Pellet ete ee cine ee ein C 3 VO Port atii Ea eL Re Le Ga RS eR C 4 Seral VO SFR Ce EE C 4 USB Function 5 E inn eid Ov e e e nex a C 4 Uis clu E 5 Timer Co nter SFRS 2 lanes iene late deine ain ae iene C 5 Non isochronous Transmit Data D 1 Isochronous Transmit Data Flow in Dual packet D 5 Non isochronous Receive Data Flow in Single packet Mode RXSPM 1 D 8 XV 8x931AA 8x931HA USER S MANUAL intel D 4 1 2 4 xvi Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 D 11
3. 11 11 11 6 3 3 Timer 2 Generated Baud Rates Modes 1 3 11 12 11 6 3 4 Selecting Timer 2 as the Baud Rate Generator 11 12 CHAPTER 12 KEYBOARD CONTROL 121 SOVERBVIEW icu ie erc c Dion ts oreste cuite ta te ts 12 1 12 2 KEYBOARD SCAN IMPLEMENTATION eseeeeneenenneneeen enne 12 2 12 2 4 Keyboard Interrupt Logic senem enne enne 12 3 12 3 EED DRIVERS aiuti RE RD READ UD 12 4 CHAPTER 13 MINIMUM HARDWARE SETUP 13 1 MINIMUM HARDWARE SETUP sse eene nenne nennen enne 13 1 13 2 ELECTRICAL ENVIRONMENT eseseseseeeeneeenneen enemies 13 1 13 24 Power and Ground Pins 5 3 Rem eve eae neta 13 2 13 22 Unused Pins eiii necat n OI mda 13 2 13 2 8 Noise Considerations esessssssssesesseeeeeeennee neret nnne enne nnne enn nne 13 2 13 3 CLOCK SOURCES zit eto re t Dee te iad etre de Edd 13 2 13 3 1 On chip Oscillator Crystal essen 13 2 13 8 2 On chip Oscillator Ceramic Resonator sese 13 3 13 3 3 External Clock nee i e Ce c eatin 13 3 1944 cuelga ets 13 5 viii intel E CONTENTS 19 4 1 Externally initiated Resets eese nnne nnne 13 5 13 4 2 USEB initiated Resets esses a aeara Ea REK EaR nennt 13 5 13 4 2 1 USB Reset Separat
4. Operation MOV lt Ri MOV A Rn Bytes States 6 Cycles 1 Encoding 1110 irrr Operation MOV A Rn MOV dir8 A Bytes 2 States 6 Cycles Encoding 1111 0101 direct addr Operation MOV dir8 lt A MOV QRi A Bytes States 6 Cycles Encoding 1111 011i Operation MOV Ri lt A MOV Rn A Bytes States 6 Cycles Encoding 1111 111r Operation MOV Rn lt A A 38 intel INSTRUCTION SET REFERENCE MOV lt dest bit gt lt src bit gt Function Description Flags Example Variations MOV bit CY Bytes States Cycles Operation MOV CY bit Bytes States Cycles Operation Move bit data Copies the Boolean variable specified by the second operand into the location specified by the first operand One of the operands must be the CY flag the other may be any directly addressable bit Does not affect any other register CY AC OV 3 The CY flag is set input Port 3 contains 11000101B and output Port 1 contains 35H 00110101B After executing the instruction sequence MOV P1 3 CY MOV CY P3 3 MOV P1 2 CY the CY flag is clear and Port 1 contains 39H 00111001B 2 12 2 Encoding 1001 0010 bit addr MOV bit51 lt CY 2 1 Encoding 1010 0010 bit addr MOV CY lt bitb1 MOV DPTR data16 Function Description Flags Load data pointer with
5. 8 28 Port tand Port S SIUCIUFe s coro tte e tue cre re Den esc ne a 9 3 Port O Structure s eee c ete cea rere envi vies 9 3 Port 2 SIr Ctlle id ete te RHEINE RR 9 4 Internal Pullup Configurations 9 6 Basic Logic of the Timer Counters sssssesseeeeeeeeneeee nennen 10 3 Timer 0 1 in Mode 0 and Mode 1 sse 10 4 Timer 0 1 in Mode 2 Auto reload ccccccccccccecccesssseseceeceeeeeceeaeeesseceseeeeeeeeeeneaansnss 10 5 Timer 0 in Mode 3 Two 8 bit TiMers cccccccccccssssssseeeeeececeeeseeeuaeseseeeeeeeeeeneneeaes 10 6 TMOD Timer Counter Mode Control Register sese 10 7 TCON Timer Counter Control Register 10 8 Timer 2 Capture etc ice Le Beet ie reU 10 11 Timer 2 Auto reload Mode 0 10 12 Timer 2 Auto reload Mode 1 10 13 Timer 2 Clock Qut ettet e tete cepa scettr 10 15 T2MOD Timer 2 Mode Control Register 10 16 T2CON Timer 2 Control Register sese 10 17 Serial Port Block Diagram 11 3 SCON Serial Port Control Register esssseeeeeenneene n 11 4 intel 11 3 11 4 11 5 2 Mod O Timing e eiit aee ee b a RR ON REGERE CSS 11 6 Data Frame
6. sssssssssseeeeeenenneenneeneee nnn 7 18 HPSC Hub Port Status Change 7 21 HPINDEX Hub Port Index Register n nmn 7 24 Resume Connectivity eret cente Fre RR Ro Re Ro ER EE gegen 7 26 HPPWR Hub Port Power Control sess 7 28 Program cicero eite Dette ded En 8 1 High level View of Transmit Operations seen 8 6 Pre transmit ISR Non Isochronous seeeeeneeeennenenee nnne 8 7 Post transmit ISR Non isochronous essen 8 8 Post transmit ISR Isochronous sessssseeeeneeneeen ener 8 9 High level View of Receive Operations sesseeeeeeeneneeen 8 11 Post receive ISR Non isochronous seseeeeeeeeeeenenennn 8 12 Receive SOF ISR Isochronous 8 13 Post receive ISR ecu te Dade 8 15 Hardware Operations for SOF Token sse 8 16 Hub to Host Port Status Communication esee 8 24 GetPortStatus Request aei fee ted c ueri Det eb 8 25 Firmware Response to GetPortStatus sssssseeeeeeeeeeneneee nene 8 26 SetPortFeature PORT SUSPEND Routine sess 8 27 SetPortFeature PORT RESET Routine
7. sesssseeeeeeeeeneee nennen 2 10 Endpoint Pairs Tor 8X99 1 5 reti tede tiet e Dec tre 2 12 The Effects of Instructions on the PSW Flags sese 4 3 Addressing Modes for Data Instructions in the MCS 51 Architecture 4 4 List of MCS 51 Arithmetic Instructions c scssssssessessssssesssesessesseesssssessecsessecsseeeeesesses 4 5 List of MCS 51 Logical Instructions 4 6 List of MCS 51 Data Transfer Instructions nnne tentes 4 8 Transfer Instructions for Accessing External Data Memory Space 4 11 MCS 51 Read Instructions ccsccscssssesssesseseseesseesesssesessesssesssesessessessesesesseesessessees 4 11 MGS 51 soot te tette teet dac tr ined 4 12 Unconditional Jumps in MCS 51 Devices ssssssse 4 14 Conditional Jumps in MCS 51 Devices ssssseeees 4 16 Interrupt System Input Signals essen 5 1 Interrupt System Special Function Registers sssssseeeee 5 4 8x931AA HA Interrupt Control Matrix essen nennen 5 6 8x931 USB Hub Interrupt Control Matrix eeeeeeeeeeeeeeneneeneeen nes 5 7 Level of Priority vec uos oe deett eite etie ete reste Fue creda te ate 5 26 Interrupt Priority Within 5 26 Function and Hub FIFO Configurations cccccccecsceseeceeeeeeeeeeeeeseeeeeaeeeneeeeeesneeeeneeeaees
8. Figure 11 2 SCON Serial Port Control Register intel SERIAL I O PORT SCON Continued Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode Select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Y Number Mnemonic Function 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 SM2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 SM2 set Set or cleared by hardware to reflect the ninth data bit received 1 TI Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by firmware 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by firmware Figure 11 2 SCON Serial Port Control Register Continued 8x931AA 8x931HA USER S MANUAL intel Transmit POP uu ESN Tg PL S3P1 S6P1 Write to SBUF si MEE sn S6P2 Shift T J n S6P2 S6P2 S6P2 S6P2 RxD yD S6P2 S6P2 TI MIENNE ps Receive wc o LESE qeu dur Es S3P1 S6P1 Write to REN CI RI SCON Set Clear S6P2 Shift 5 Ll 1D S6P2 S6P2 S6P2 S6P2 DO D1 D6 D7 S6P2 S6P2 S5P2 RI l S1P1 A4124 02 Figure 11 3 Mode 0 Timing Data Byte C Start Bit Ninth Data Bit Modes 2 and 3
9. 9 5 Instructions for External Data eem 9 7 External Signals ga etes ete ec flees 10 2 Timer Counter and Watchdog Timer SFRS 10 3 Timer 2 Modes of Operation ennemi 10 15 intel 11 1 11 2 11 3 11 4 11 5 11 6 12 1 14 1 15 1 15 2 16 1 16 2 16 3 16 4 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 B 1 B 3 B 4 B 5 B 6 B 7 C 1 C 2 4 C 5 C 7 C 8 D 1 D 2 D 3 Serial Pott Signals atttem eb na eee e ponent eae 11 1 Serial Port Special Function Registers sessssseeeneeeneenens 11 2 Summary of Baud Ra tes 3 ttem LR pee on 11 10 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 11 12 Selecting the Baud Rate Generator s 11 13 Timer 2 Generated Baud Rates sssssssssssssseseeeeennnen nennen 11 14 Keyboard Control Sigrials 2 ttai Een Lordi erected 12 2 Pin Conditions in Various Modes ssseeeeeeneeeenneeneeeen nennen 14 6 External Memory Interface Signals 15 2 Port 0 and Port 2 Pin Status In Normal Operating 15 5 Signal Descriptions Verify Mode nennen 16 2 Verily pt ete nr eR UR ECRIRE 1
10. 4 4 4 1 2 5 CONSTANTS 4 4 4 1 2 6 INDEXED ADDRESSING sssssseeseeeneneeeeneenneen nennen nennen nennen nre 4 4 4 1 3 Arithirmetic nstr ctlOris aseo iren fete ct t dehet me ni et y ete ec ert ne 4 5 45 4 EogicalInstr ctlons D ER ER ee es 4 7 4 1 5 Data Vransters o EE hu eee Rae X eae 4 8 4 1 5 1 Internal RAM sore te rte heir e ce Y eee a onset eoe 4 8 41 5 2 7 External hard e mente exe it epa Ios e tg 4 10 4 1 5 8 Lookup Tables nicae repre tecti Sida 4 11 41 6 1 amp 61 amp bcd tenent ep coa ats 4 12 43 6 1 Relative Offset casas metae dee dating hada 4 13 44 4 Jump Instr ctions cie Pt RERO DRE MESE 4 14 CHAPTER 5 INTERRUPT SYSTEM 5 1 OVERVIEW titer acetum at b etd uidi 5 1 5 2 INTERR PT SOURGES 1 boi eesti ieee Ee een eei en Se 5 5 5 2 1 External Interrupts 5 2 rt 5 6 5 2 2 Timer Interru pts eerte teta tpi reet tbe sevice 5 7 5 2 3 Keyboard Scan Interrupt 5 7 5 2 4 Serial Portlnterr pt 2e ele dette De ai dee ple ee ele 5 8 5 2 5 USB Function 3e nean UBRO 5 8 5 2 6 USB Start of frame Interrupt eesssssssseeeneeeeeneneeeen nennen 5 11 527 USB Hub lritermpt aie ERROR aue UR RUE RE 5 15
11. 14 13 14 5 2 Exiting Low clock Mode eene 14 13 14 6 ON CIRCUIT EMULATION ONCE 14 13 14 61 Entering ONCE Mode eme Res wal e Le neo ean 14 13 14 6 2 Exiting ONGE MOde D RR REESE REIR 14 13 CHAPTER 15 EXTERNAL MEMORY INTERFACE 153 OVERVIEW iae tede e n er eee Eds eee 15 1 15 2 EXTERNAL BUS CYCLE aute eet ei dd ui ERR Ec DR Eaei 15 2 15 24 B s Cycle Definitions ree e RN OI RONDE maiis 15 3 15 3 2 STATUS nennen nennen ennt enne enne 15 5 15 3 1 Porto and Port Z Pili Status aii than erue OR 15 5 15 4 EXTERNAL MEMORY DESIGN EXAMPLES sese 15 6 15 4 1 Example 1 11 bit Bus External RAM 2222 15 6 15 4 2 Example 2 16 bit Bus External ROM sss 15 7 15 4 8 Example 3 16 bit Bus External EPROM and RAM 15 8 CHAPTER 16 VERIFYING NONVOLATILE MEMORY 46 1 83931 MEMORY iiio IB RED ERO 16 1 8x931AA 8x931HA USER S MANUAL intel 16 2 NONVOLATIEE MEMORY er nen ion RE tha es 16 1 16 3 VERIFYING ON CHIP NONVOLATILE MEMORY eeeenmeeen 16 1 16 3 1 Verify MOd6eS ae eto i M e UR TRE E E LER Re 16 2 16 3 2 General Setup hee teeaqate eiii oe dee dice ardere 16 2 16 3 3 Verify Algoritlim ui re Uo Pto 16 3
12. Encoding 1011 0101 direct addr rel addr 8x931AA 8x931HA USER S MANUAL Operation PC PC IF A dir8 THEN PC relative offset IF A lt dir8 THEN CY 1 ELSE CY 0 CJNE Ri data rel 011i immed data rel addr PC PC relative offset Bytes 3 States 12 Cycles 2 Encoding 1011 Operation PC PC IF Ri data THEN IF Ri lt data THEN CY 1 ELSE CY 0 CJNE Rn data rel 101 1 tirrr immed data rel addr PC PC relative offset Bytes 3 States 12 Cycles 2 Encoding Operation PC PC IF Rn data THEN IF Rn lt data THEN lt 1 ELSE CY 0 CLRA Function Clear accumulator Description Clears the accumulator i e resets all bits to zero intel Flags Example Bytes States Cycles Operation CLR bit Function Description Flags Example Variations CLR bit Bytes States Cycles Operation CY AC INSTRUCTION SET REFERENCE OV The accumulator contains 5CH 01011100B The instruction CLRA clears the accumulator to OOH 00000000B Encoding CLR 0 Clear bit 1110 0100 Clears the specified bit CLR can operate on the CY flag or any directly addressable bit Only for instructions with CY as the operand CY AC OV
13. 15 7 Bus Diagram for Example 3 8 931 15 8 Setup for Verifying Nonvolatile Memory esesseeeeeeeenneneneenn 16 3 8x931HA 68 pin PLCC Package sssssssseeeeeeeeee nennen nennen nnne B 1 8x931HA 64 SDIP Package B 2 8x931HA 64 pin QFP Package B 3 8x931AA 64 pin QFP Package B 4 8x931AA 68 pin PLCC Package B 5 8x931AA 64 pin Package sssessesseeneeeeneneneen nennen nennen E 3 8X99T1AA 68 pit PL GG itin ottiene eec beet pec ere te es oce E E 4 xiii TABLES 1 1 2 1 2 2 2 3 2 4 2 5 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 5 1 5 2 5 3 5 4 5 5 5 6 6 1 6 2 6 3 6 4 6 5 6 6 6 7 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 8 1 8 2 9 1 9 2 9 3 10 1 10 2 10 3 Intel Application Support ServiCes ceccecceceeeeeeeeeeeeeeeeeseeeeeeeeaeseaeeseeeeeeeeneeeeeeeeaeees 1 7 8x931 Memory Options 2 3 USB Peripheral Controller Feature Summary and 2 4 8x931HA Operating Frequency eessesseseseeseeeenene nne nnne 2 9 8x931AA Operating Frequencies
14. 2 12 2 Encoding 0110 0000 rel addr JZ PC PC 2 IF A 0 THEN PC lt PC rel Long call Calls a subroutine located at the specified address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first The stack pointer is incremented by two The high and low bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the 64 Kbyte region of memory where the next instruction is located CY AC OV A 33 8x931AA 8x931HA USER S MANUAL intel Example The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the stack pointer contains 09H on chip RAM locations 08H and 09H contain 01H and 26H and the PC contains 1234H Bytes 3 States 12 Cycles 2 Encoding 0001 0010 addr15 addr7 addro 8 Operation LCALL PC PC 3 SP SP 1 SP lt PC 7 0 SP SP 1 SP lt PC 15 8 lt addr 15 0 LJMP addr16 Function Long Jump Description Causes an unconditional branch to the specified address by loading the high and low bytes of the PC
15. Port Q From Port Latch Input Data Read Port Pin A2242 01 Figure 9 4 Internal Pullup Configurations 9 6 intel INPUT OUTPUT PORTS 9 7 PORT LOADING Output buffers of port 1 port 2 and port 3 can each sink 1 6 mA at logic zero see Vo specifi cations in the 8x931 data sheet These port pins can be driven by open collector and open drain devices Logic zero to one transitions occur slowly as limited current pulls the pin to a logic one condition Figure 9 4 on page 9 6 A logic zero input turns off pFET 3 This leaves only pFET 2 weakly in support of the transition In external bus mode port 0 output buffers each sink 3 2 mA at logic zero see Vo the 8x931 data sheet However the port 0 pins require external pullups to drive external gate inputs See the latest revision of the 8x931 datasheet for complete electrical design information External circuits must be designed to limit current requirements to these conditions 9 8 EXTERNAL MEMORY ACCESS Port 2 outputs the upper address byte the lower address byte and the data are multiplexed on port 0 Port 0 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the lower address byte and the data Port 0 is in a high impedance state for data input Port 2 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address byte There are two types of e
16. ode eee Hee eid E 9 E6 8X031AA SER MAP uti e ie et t etes E 10 GLOSSARY INDEX intel FIGURES 2 1 8x93 Tina USB SySIem a sin RR d bee 2 1 2 2 Functional Block Diagram of the 8 931 2 2 2 3 8x931HA USB Module Block Diagram eene 2 7 2 4 8x991 Clock Circuits oec sp Whee n nS 2 9 2 5 8x931 Clocking Definitions nosne e ai E eene nennen nennen 2 10 3 1 51 PregiamMelporyi aceasta cis econ tO Sed i Corse Uri teste aset 3 2 3 2 8x931 Memory Structure esses eene nnne nennen enne 3 3 3 3 Intern l Data Memory epe ie e pet ro mn duse eae 3 4 3 4 Upper and Lower 128 Bytes of Internal RAM sseeee 3 4 3 5 SFR Space e 3 5 4 1 Program Status Word ReQiSter ceccceesceeseeseeeeeeeeeeeeseeeeseeeseneeeeeeseaeesaeessaeeseesseenaees 4 2 4 2 Shifting BCD Number Two Digits Right 4 9 4 3 Shifting BCD Number One Digit Right 4 10 5 1 Interrupt Control System 5 3 5 2 Bits of the Interrupt ce ED rti rmt er 5 5 5 3 FIE USB Function Interrupt Enable Register 5 9 5 4 FIFLG USB Function Interrupt Flag Register 5 11 5 5 SOFH Start of frame High Register 5 12 5 6 SOFL Start of frame Low Register sessssssssseeee
17. 3 Port 1 contains 5DH 01011101B After executing the instruction CLR P1 2 port 1 contains 59H 01011001B 2 6 1 Encoding CLR bitb1 0 1100 0010 Bit addr 8x931AA 8x931HA USER S MANUAL CLR CY Bytes States Cycles Operation CPLA Function Description Flags Example Bytes States Cycles Operation CPL bit Function Description Flags A 20 Encoding 1100 0011 CLR 0 Complement accumulator Logically complements each bit of the accumulator one s complement Clear bits are set and set bits are cleared CY AC OV The accumulator contains 5CH 01011100B After executing the instruction CPLA the accumulator contains 1010001 1B Encoding 1111 0100 CPL lt A Complement bit Complements the specified bit variable A clear bit is set and a set bit is cleared CPL can operate on the CY or any directly addressable bit Note When this instruction is used to modify an output pin the value used as the original data is read from the output data latch not the input pin Only for instructions with CY as the operand CY AC OV 3 intel Example Variations CPL bit Bytes States Cycles Operation CPL CY Bytes States Cycles Operation DAA Function Description I
18. 5 IPHO 5 Timer 2 Overflow Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 External Interrupt 0 Priority Bit High C 27 8x931AA 8x931HA USER S MANUAL intel IPLO Address B8H Reset State x000 0000B Interrupt Priority Low Control Register 0 IPLO together with IPHO assigns each interrupt in IENO a priority level from 0 lowest to 3 highest IPHOx IPLOx Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Bit Bit x Function Number Mnemonic unctio 7 6 Reserved Write zeros to these bits 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt 0 Priority Bit Low C 28 IPH1 Address Reset State Interrupt Priority High Control Register 1 IPH1 together with IPL1 assigns each interrupt in IEN1 a priority level from 0 lowest to 3 highest REGISTERS B3H 0000 0000B IPH1 x IPL1 x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPH1 7 IPH1 2 IPH1 1 IPH1 0 Bit Bit Fun
19. 0023H Interrupt _ 001BH Locations 8 Bytes 0013H 000BH 0003H RESET 0000H 4480 01 Figure 3 1 MCS 51 Program Memory The interrupt service locations are spaced at 8 byte intervals 0003H for External Interrupt 0 000BH for Timer 0 0013H for External Interrupt 1 001BH for Timer 1 etc If an interrupt ser vice routine is short enough as is often the case in control applications it can reside entirely within that 8 byte interval Longer service routines can use a jump instruction to skip over sub sequent interrupt locations if other interrupts are in use The lowest 8K bytes of Program Memory can be either in the on chip ROM or in an external ROM This selection is made by strapping the EA External Access pin to either Voc or Vss In the 8K byte ROM devices EA V oc selects addresses 0000H through 1FFFH to be internal and addresses 2000H through FFFFH to be external If the EA pin is strapped to V then all program fetches are directed to external ROM The ROMless parts must have this pin externally strapped to to enable them to execute properly The read strobe to external ROM PSEN is used for all external program fetches PSEN is not activated for internal program fetches Program Memory addresses are always 16 bits wide even though the actual amount of Program Memory used may be less than 64K bytes External program execution sacrifices two of the 8 bit ports POand P2
20. Encoding 1010 0000 bit addr Operation ORL lt CY bit51 POP dir8 Function Pop from stack A 46 intel Description Flags Example Bytes States Cycles Operation PUSH dir8 Function Description Flags Example Bytes States INSTRUCTION SET REFERENCE Reads the contents of the on chip RAM location addressed by the stack pointer then decrements the stack pointer by one The value read at the original RAM location is transferred to the newly addressed location which can be 8 bit or 16 bit CY AC OV The stack pointer contains 32H and on chip RAM locations 30H through 32H contain 01H 23H and 20H respectively After executing the instruction sequence POP DPH POP DPL the stack pointer contains 30H and the data pointer contains 0123H After executing the instruction POP SP the stack pointer contains 20H Note that in this special case the stack pointer was decremented to 2FH before it was loaded with the value popped 20H 2 12 2 Encoding 1101 0000 direct addr POP dir8 lt 5 SP SP 1 Push onto stack Increments the stack pointer by one The contents of the specified variable are then copied into the on chip RAM location addressed by the stack pointer CY AC OV On entering an interrupt routine the stack pointer contains 09H and the data pointer contains 0123H After executin
21. Figure 13 2 CHMOS On chip Oscillator 13 3 3 External Clock To operate the 8x931 from an external clock connect the clock source to the XTALI1 pin as shown in Figure 13 3 Leave the XTAL2 pin floating The external clock driver can be a CMOS gate If the clock driver is a TTL device its output must be connected to Vec through a 4 7 KQ pullup resistor For external clock drive requirements see the device data sheet Figure 13 4 shows the clock drive waveform The external clock source must meet the minimum high and low times Tec and and the maximum rise and fall times Tg and Taye to minimize the effect of ex ternal noise on the clock generator circuit Long rise and fall times increase the chance that ex ternal noise will affect the clock circuitry and cause unreliable operation The external clock driver may encounter increased capacitance loading at XTAL1 when power is applied due to the interaction between the internal amplifier and its feedback capacitance 1 e the Miller effect Once the input waveform requirements are met the input capacitance remains under 20 pF 13 3 8x931AA 8x931HA USER S MANUAL intel External Clock gt CMOS Clock Driver N C Note If TTL clock driver is used connect 4 7kQ pullup resistor from driver output to Vec A4142 03 Figure 13 3 External Clock Connection for the 8x931 A4119 01 Figure 13 4 External Clock Drive Wavefo
22. 2 Enable the hub endpoint 0 transmit done and receive done interrupts individually a To enable the receive done interrupt set the HRXEO bit in the Hub Interrupt Enable SFR HIE as shown in Figure 5 7 b To enable the transmit done interrupt set the HTXEO bit in HIE NOTE The 8x931Ax microprocessor does not support hub operations or a hub interrupt Specific details of the 8x931Ax are covered in Appendix E 8x931AA Design Considerations HIE Address A1H Reset State Xxxx xx00B Hub Interrupt Enable Register Enables and disables the receive and transmit done interrupts for hub endpoint 0 7 0 NM HRXEO HTXEO LAUR Function 7 2 Reserved Write zeros to these bits 1 HRXEO HRXEO Enable the hub endpoint 0 receive done interrupt HRXDO 0 HTXEO HTXEO Enable the hub endpoint 0 transmit done interrupt HTXDO A 1 means the interrupt is enabled and will cause an interrupt to be signaled to the microcontroller A 0 means the associated interrupt source is disabled and cannot cause an interrupt even though its value is still reflected in the HIFLG register Figure 5 7 HIE Hub Interrupt Enable Register The USB Hub Interrupt Flag Register HIFLG is shown in Figure 5 8 This register is used to indicate pending hub interrupts For all bits in HIFLG a 1 indicates that an interrupt is actively pending a 0 indicates that the interrupt is not active
23. 2 0 TS10 8 Time stamp received from host TS10 8 are the upper three bits of the 11 bit frame number issued with an SOF token This time stamp is valid only if the SOFACK bit is set If an artificial SOF is generated the time stamp remains at its previous value and it is up to firmware to update it These bits are set and cleared by hardware Figure 5 5 SOFH Start of frame High Register Continued SOFL Address D2H Reset State 0000 0000B Start of frame Low Register Contains the lower eight bits of the 11 bit time stamp received from the host Bit Number Bit Mnemonic Function 7 0 TS7 0 Time stamp received from host This time stamp is valid only if the SOFACK bit in the SOFH register is set TS7 0 are the lower eight bits of the 11 bit frame number issued with an SOF token If an artificial SOF is generated the time stamp remains at its previous value and it is up to firmware to update it These bits are set and cleared by hardware Figure 5 6 SOFL Start of frame Low Register 5 13 8x931AA 8x931HA USER S MANUAL intel The 8x931 uses the SOF interrupt to signal either of two complementary events 1 When transmitting The next isochronous data packet needs to be retrieved from memory and loaded into the transmit FIFO in preparation for transmission in the next frame or 2 When receiving An isochronous packet has been received in the previous frame and needs to be retrieved from
24. Function Logical AND for bit variables 0101 011i 0101 1rrr 8x931AA 8x931HA USER S MANUAL intel Description Flags Example ANL CY bit Bytes States Cycle Operation ANL CY bit Bytes States Cycles Operation If the Boolean value of the source bit is a logical 0 clear the CY flag otherwise leave the CY flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected Only direct addressing is allowed for the source operand CY AC OV 3 Set the CY flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV CY P1 0 carry with input pin state ANL CY ACC 7 AND carry with accumulator bit 7 ANL CY OV AND with inverse of overflow flag 2 12 2 Encoding 1000 0010 bit addr ANL CY lt CY A bit51 2 12 2 Encoding 1011 0000 bit addr ANL CY lt CY A bit CJNE lt dest gt lt src gt rel Function Description Compare and jump if not equal Compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction If the unsigned integer value of lt dest by
25. NOTE The 8x931A A microcontroller does not support hub operations Specific details of the 8x931AA are covered in Appendix E 8x931AA Design Considerations 2 3 8x931AA 8x931HA USER S MANUAL 21 3 Keyboard Control Interface intel The 8x931 contains a keyboard control interface with a 20 bit by 8 bit scan capability and four LED drivers Chapter 12 Keyboard Control describes this further Table 2 2 USB Peripheral Controller Feature Summary and Comparison 8x931Hx 8x931Ax 8x930Hx 8x930Ax General Features On chip ROM 0 8 Kbytes 0 8 Kbytes 0 8 or 16 0 8 or 16 Kbytes Kbytes On chip RAM 256 bytes 256 bytes 1024 bytes 1024 bytes On chip peripherals Timer counters 3 3 3 3 Serial I O port Yes Yes Yes PCA Hardware Watchdog Timer No No Yes Code compatible with MCS 51 Microcontrollers Yes Yes Yes Code compatible with MCS 251 Microcontrollers No No Yes Keyboard control interface Yes Yes No General USB Features Complete Universal Serial Bus Specification Yes Yes Yes Rev 1 0 compatibility On chip USB transceivers Yes Yes Yes Automatic transmit receive FIFO management Yes Yes Yes Time base crystal PLL 12 MHz 12 MHz 12 MHz USB rate full speed 12 Mbps 12 Mbps 12 Mbps Low clock mode Yes Yes Yes Suspend resume Yes Yes Yes USB interrupt vectors hub function and Yes Yes Yes suspend resume Reset Separation Yes Yes Yes 6 Endpoint Pair Option No No Yes USB Function Features Function endpoin
26. ie date tees 10 4 10 3 2 Mode 1 16 bit Timer enit tian ita 10 4 10 3 3 Mode 2 8 bit Timer With Auto reload see em 10 5 10 3 4 Mode 3 Two 8 bit Timers sssseeeennn mene enne 10 5 10 4 TIMER e ete eie ox aite didis b neret riego 10 6 10 4 1 Mode 0 13 bit Timer eene 10 9 10 42 Mode 1 16 bit Timer 5 iet ette PRU RR RR 10 9 10 4 8 Mode 2 8 bit Timer with Auto reload em 10 9 10 4 4 Modes Halt cretese Bee een a aired p 10 9 10 5 TIMER 0 1 APPLICATIONG ssesssssseeeeenereneen nennen nnne nnne nnne rene nnns 10 9 10 5 1 Auto reload Setup Example sse nennen ener 10 9 10 5 2 Pulse Width Measurements sse eene eene 10 10 10 6 TIMER Erit aod cde eene eet ot 10 10 10 64 Capture Mode 2 nete Rebus d ete dte di e re 10 11 10 6 2 Atitozreload Mode dtt e cline dni 10 12 10 6 2 1 Up Counter Operation sessesssseseeeenennee nnne nnne nnne nns 10 12 10 6 3 Up Down Counter Operation sese 10 13 10 6 4 Baud Rate Generator Mode sse nennen nene 10 14 10 6 5 Glock ouUt Mode tpm Wee ia e ettet aide e Ferri iuter dag eden 10 14 vii 8x931AA 8x931HA USER S MANUAL intel CHAPTER 11 SERIAL I O PORT 113 OMERNIBW niei AEE A A E 11 1 11 2
27. intel REGISTERS IENO Address A8H Reset State 0000 0000B Interrupt Enable Register 0 IENO contains two types of interrupt enable bits The global enable bit EA enables disables all of the interrupts including those in IEN1 The remaining bits enable disable the other individual interrupts 7 0 EA ET2 ES 1 1 Bit Bit Function Number Mnemonic unco 7 Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by the other bits of this register as well as the interrupts enabled by the bits in the IEN1 SFR Clearing this bit disables all interrupts except the TRAP interrupt which are always enabled 6 Reserved Write a zero to this bit 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 EX1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 External Interrupt 0 Enable Setting this bit enables external interrupt 0 NOTE Note that because the IENO appears in the first SFR column it is a bit addressable SFR C 25 8x9
28. 8 21 8x931AA 8x931HA USER S MANUAL intel Table 8 2 Firmware Action for Hub Class Specific Requests Continued USB Requests Feature Selector Type Index Firmware Action Required ClearPortFeature PORT_ENABLE Requests port disable 1 Load xxxB into HPINDEX2 0 where xxx is the binary representation of the port index 2 Write 000 to bits 2 0 of the port s HPCON SFR Figure 7 9 on page 7 15 For hub port 1 this will disable address and endpoint decoding for the embedded function PORT SUSPEND Requests port resume 1 Load xxxB into HPINDEX2 0 where xxx is the binary representation of the port index 2 Write 100 to bits 2 0 of the port s HPCON SFR Figure 7 9 on page 7 15 If port 1 is specified firmware must also resume any non hub functionality associated with the embedded function prior to writing to port 1 s HPCON This requires taking any external device hardware out of a low power suspend mode Request port power off If any port other than port 1 is specified Clear bit x of HPPWR where x is the port specified in the PORT POWER request index field Port power off is not supported for port 1 If port 1 is specified 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage Request to clear port connect status change C_PORT_ 1 Load xxxB into HPINDEX2 0 where xxx is the binary CONNECTION representat
29. Bytes 3 States 12 Cycles 2 Encoding 0100 0011 direct addr immed data Operation ORL dir8 lt dir8 V data ORL A data Bytes 2 States 6 Cycles Encoding 0100 0100 immed data Operation ORL lt A V data ORL A dir8 Bytes 2 States 6 Cycles Encoding 0100 0101 direct addr Operation ORL A lt A V dir8 ORL A Ri Bytes States 6 Cycles Encoding Operation ORL lt A V Ri ORL A Rn Bytes States 6 0100 011i A 45 8x931AA 8x931HA USER S MANUAL intel Cycles 1 Encoding 0100 irrr Operation ORL lt A V Rn ORL CY lt src bit gt Function Logical OR for bit variables Description Sets the CY flag if the Boolean value is a logical 1 leaves the CY flag in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected Flags CY AC OV 3 Set the CY flag if and only if P1 0 1 ACC 7 1 or OV 0 MOV CY P1 0 LOAD CARRY WITH INPUT PIN P10 ORL CY ACC 7 OR CARRY WITH THE ACC BIT 7 ORL CY OV CARRY WITH THE INVERSE OF OV Variations ORL CY bit Bytes 2 States 12 Cycles 2 Encoding 0111 0010 bit addr Operation ORL CY CY V bit51 ORL CY bit Bytes 2 States 12 Cycles 2
30. Endpoint indexed E2H 0000 0000B Address Reset State Endpoint Receive Status Register Contains the current endpoint status of the receive FIFO specified by EPINDEX 7 0 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Bit Number Mnemonic Function 1 RXERR Receive Error read only t RXACK Set when an error condition has occurred with the reception Complete or partial data has been written into the receive FIFO No handshake is returned The error can be one of the following conditions 1 Data failed CRC check 2 Bit stuffing error 3 A receive FIFO goes into overrun or underrun condition while receiving This bit is updated by hardware at the end of a valid SETUP or OUT token transaction non isochronous or at the next SOF on each valid OUT token transaction isochronous The corresponding FRXDx bit of FIFLG is set when active This bit is updated with the RXACK bit at the end of data reception and is mutually exclusive with RXACK Receive Acknowledged read only This bit is set when data is received completely into a receive FIFO and an ACK handshake is sent This read only bit is updated by hardware at the end of a valid SETUP or OUT token transaction non isochronous or at the next SOF on each valid OUT token transaction isochronous The corresponding FRXDx bit of FIFLG is set when active This bit is updated with the RXERR bit at the end of data reception
31. MODES OF OPERATION teen eA cade ds 11 2 11 2 1 Synchronous Mode Mode 0 ceeeeseeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeseeeeeeeeeaees 11 2 11 2 1 1 Transmission Mode 0 nennen nnne 11 2 11 2 1 2 Reception Mode 0 11 2 11 2 2 Asynchronous Modes Modes 1 2 and 3 11 7 11 2 2 1 Transmission Modes 1 2 3 simi nrnna i 11 7 11 2 2 2 Reception Modes 1 2 3 nece teed teens tee rette 11 7 11 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 11 7 11 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 11 8 11 5 AUTOMATIC ADDRESS RECOGNITION essere eene 11 8 11 521 GivemAddress nme itt eite t teste 11 9 11 52 Broadcast Address too eee OPEP RP EE 11 9 11 5 9 Reset Addresses ix nne teet e beet eed next aa aaa 11 10 11 6 uites RARE REM RE PRA RU 11 10 11 6 1 Baud Rate for Mode 0 isoissa naain aaa nnne tenen 11 10 11 6 2 Baud Rates for Mode 2 5 11 11 11 6 3 Baud Rates for Modes 1 and 3 11 11 11 6 3 1 Timer 1 Generated Baud Rates Modes 1 3 11 11 11 6 3 2 Selecting Timer 1 as the Baud Rate Generator
32. P0 3 KSI3 Reserved NC AD2 P0 2 KSI2 AD1 P0 1 KSI1 ADO P0 0 KSIO ECAP Vssp VssP ris er SS DIRE View of componentas P B Reeves 1 P3 3 INT1 E 13 mounted on PC board Reserved NC P3 4 TO KSO16 14 Reserved NC LEDO LED1 RST amp 31 PLLSEL 32 e I Q o gt lt LED3 9 26 LED2 amp 27 XTAL1 28 XTAL2 Ey 29 A5347 02 Figure E 1 8x931AA 64 pin QFP Package E 3 8x931AA 8x931HA USER S MANUAL intel NC NC 3 A8 P2 0 KSO8 8 F A9 P2 1 KSO9 7 H A10 P2 2 KSO10 6 A A11 P2 3 KSO11 5 A A12 P2 4 KS012 4 El A13 P2 5 KSO13 3 A A14 P2 6 KSO14 2 H A15 P2 7 KS015 e1 A Vss 68 H Vcce 67 5 66 65 B1 PSEN 64 FSSEL 63 F Vssp 62 Reserved 61 Fa Reserved AD7 P0 7 KSI7 E 10 Reserved NC AD6 P0 6 KSI6 E 11 Reserved NC AD5 P0 5 KSI5 E 12 Reserved NC AD4 P0 4 KSl4 E 13 Reserved NC AD3 P0 3 KSI3 E 14 56 F AD2 P0 2 KSI2 E 15 AD1 P0 1 KSI 8x931Ax ADO 0 KSIO ECAP Vssp Vssp ve 0 O i SS P3 1 SOr El 21 View of component as Reserved NC P3 2 INTO 5 22 mounted on PC board Reserved NC P3 3 INT1 E 23 Vssp P3 4 T0 KSO16 E 24 Reserved NC P3 5 T1 KSO17 E 25 Reserved NC P3 6 WR KSO18 26 LEDO P3 7 RD KSO19 27 P1 0 T2 KSO0 28 P1 1 T2EX KSO1 amp
33. Received 00 1 0 0 0 0 0 Set Time out FIFO is reset SETUP receive automatically and token but interrupt FIFO data is timed out invalid 2 waiting for data NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints intel DATA FLOW MODEL Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event ut ERR ACK Void Setup m yid pes Response Comments Received 00 1 0 0 1 0 0 Set Time out Write pointer SETUP receive reversed RXIE token data interrupt or RXSTL has no CRC or bit effect 2 stuff error RXSETUP will be dual packet set control mode not endpoints only recommende d Received 00 1 0 0 1 1 0 Set Time out RXIE or RXSTL SETUP receive NAK has no effect 2 token FIFO interrupt future RXSETUP will be error occurs transaction set control S endpoints only Received 01 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token with interrupt automatically FIFO error forcing new already SETUP to be existing received RXIE or RXSTL has no effect 2 RXSETUP will be set control endpoints only CPU reads 00 None NAK FI
34. S MANUAL intel IPLO Address B8H Reset State x000 0000B Interrupt Priority Low Control Register 0 IPLO together with IPHO assigns each interrupt in IENO a priority level from 0 lowest to 3 highest IPHOx IPLOx Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Bit Bit i Function Number Mnemonic 7 6 Reserved Write zeros to these bits 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt 0 Priority Bit Low Figure 5 13 IPLO Interrupt Priority Low Register 0 5 28 intel INTERRUPT SYSTEM Address B3H Reset State xxxx x000B IPH1 Interrupt Priority High Control Register 1 IPH1 together with IPL1 assigns each interrupt in IEN1 a priority level from 0 lowest to 3 highest IPH1 x IPL1 x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPH1 7 IPH1 3 IPH1 2 IPH1 1 IPH1 0 Bit Bit Function Number Mnemonic uneto Keyboard Scan Interrupt Priority Bit High 6 3 Reserved Write zeros to these bits 2 Global Suspend Resume Reset Interrupt Priority Bit High 1 IPH1 1 USB Function Interrupt Priority Bit High 0 IPH1 0 USB Hub
35. Setting this bit forces the internal clock distributed to the CPU and peripherals but not the USB module to 3 MHz This bit is automatically set after a reset Clearing this bit through firmware returns Fo to the normal clock frequency 4 Power Off Flag Set by hardware on the rising edge of Vcc set or cleared by software This flag allows detection of a reset caused by a power failure Vcc must remain above 3 volts to retain this bit 3 General Purpose Flag Set or cleared by firmware One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 General Purpose Flag Set or cleared by firmware One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 Powerdown Mode Bit When set activates powerdown mode This bit should only be set if the GSUS bit is also set Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL and PD are both set PD takes precedence Figure 14 1 PCON Power Control Register 14 3 8x931AA 8x931HA USER S MANUAL intel PCON1 Address DFH Reset State x000B USB Power Control Register Facilitates the control and status relating to global suspend and resume USB reset separation and remote wake up of the 8x931 7 0 URDIS URST RWU GRSM GSUS Bit Bit Numb
36. The PUSH instruction first increments the Stack Pointer SP then copies the byte into the stack PUSH and POP use only direct addressing to identify the byte being saved or restored but the stack itself is accessed by indirect addressing using the SP register This means the stack can go into the Upper 128 if they are implemented but not into SFR space In devices that do not implement the Upper 128 if the SP points to the Upper 128 PUSHed bytes are lost and POPped bytes are indeterminate The Data Transfer instructions include a 16 bit MOV that can be used to initialize the Data Point er DPTR for look up tables in Program Memory or for 16 bit external Data Memory accesses The XCH A byte instruction causes the Accumulator and addressed byte to exchange data The XCHD A Ri instruction is similar but only the low nibbles are involved in the exchange To see how XCH and XCHD can be used to facilitate data manipulations consider first the prob lem of shifting an 8 digit BCD number two digits to the right Figure 4 2 shows how this can be done using direct MOVs and for comparison how it can be done using XCH instructions To aid in understanding how the code works the contents of the registers that are holding the BCD num ber and the content of the Accumulator are shown alongside each instruction to indicate their sta tus after the instruction has been executed 4 8 intel PROGRAMMING CONSIDERATIONS After the routine
37. USB Function For hub endpoint 1 EPINDEX 1000 0001 the only endpoint SFR implemented is TXDAT A separate TXDAT register definition table is provided for this endpoint see Figure 6 8 on page 6 16 NOTE descriptions for more details C 2 d in the SFR reset value denotes configuration operation dependence Refer to specific SFR FF F7 EF E7 DF D7 CF C7 BF B7 AF AT 9F 97 8F 87 intel REGISTERS C 1 SFRS BY FUNCTIONAL CATEGORY Table C 2 Core SFRs Mnemonic Address Accumulator EOH B Register FOH Data Pointer 2 bytes Low Byte of DPTR 82H High Byte of DPTR 83H Keyboard Control F8H Power Control 87H USB Power Control DFH Program Status Word DOH SP Stack Pointer 81H Table C 3 Interrupt System SFRs Mnemonic Description Address FIE USB Function Interrupt Enable Register A2H FIFLG USB Function Interrupt Flag Register COH HIE Hub Interrupt Enable Register A1H HIFLG Hub Interrupt Flag Register E8H IENO Interrupt Enable Register 0 A8H IEN1 Interrupt Enable Register1 B1H IPLO Interrupt Priority Low Register O B8H IPHO Interrupt Priority High Register 0 B7H IPL1 Interrupt Priority Low Register 1 B2H IPH1 Interrupt Priority High Register 1 B3H KBCON Keyboard Control Register F8H SOFH Start of Frame High Register D3H SOFL Start of Frame Low Register D2H C 3 8x931AA
38. latest overcurrent indicator and OVISC HSTAT 3 hub overcurrent status change bits OVI indicates if the overcurrent bit is presently asserted 0 or de asserted 1 OVISC indicates whether the overcurrent status has changed since this bit was initially cleared by firmware i e this bit acts as a sticky bit which must be cleared in firm ware Another fact to consider about the overcurrent condition is that all external ports are placed in the powered off state This is true for both bus powered and self powered ports even though self powered ports may still be powered This condition will remain until the host enables power to the ports via one of the HPPWR5 2 bits To disable OVRI pin clear OVRIEN HSTAT 7 overcurrent detect enable bit 7 7 3 Ganged Power Enable The 8x931HA uses a ganged power enable scheme to enable power to the external downstream ports This means that a single output pin UPWEN should be used at the board level to switch power to all of the downstream ports The state of this power enable pin is controlled in two ways by the collective ORed value of bits 5 2 of the HPPWR SFR Figure 7 14 under control of firmware and by the present state of the overcurrent sense input pin OVRI If any of the HPPWR bits are set then the UPWEN signal will be asserted to a 0 as long as the OVRI signal is not asserted 1 e OVRI 1 If the OVRI signal is asserted 0 o
39. to this bit has no effect on TXSEQ This bit always returns 0 when read 2 TXVOID Transmit Void read only ttt A void condition has occurred in response to a valid IN token Transmit void is closely associated with the NAK STALL handshake returned by the function after a valid IN token due to the conditions that cause the transmit FIFO to be unenabled or not ready to transmit Use this bit to check any NAK STALL handshake returned by the function This bit does not affect the FTXDx TXERR or TXACK bits This bit is updated by hardware at the end of a non isochronous transaction in response to a valid IN token For isochronous transactions this bit is not updated until the next SOF Under normal operation this bit should not be modified by the user The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface For additional information on the operation of these bits see Appendix D Data Flow Model Figure 6 4 TXSTAT Transmit FIFO Status Register 6 9 8x931AA 8x931HA USER S MANUAL intel TXSTAT Continued Address F2H Endpoint indexed Reset State 0xx0 0000B Endpoint Transmit Status Register Contains the current endpoint status of the transmit FIFO specified by EPINDEX 7 0 TXSEQ TXFLUSH TXSOVW TXVOID TXERR TXACK Bit Bit Number Mnemonic Function 1 TXERR Transmit Error r
40. 16 3 4 Verifying On chip Program Memory sese 16 4 16 3 5 Veritying the Lock Bits tient nite 16 4 16 3 6 Verifying the Signature Bytes ceeeeeeeeseeeeeeeneeeeeeeeeeeseeeeeeeeseeseaeeeeeessaeesaeeseaeeaas 16 4 164 ENGRYPTION ARRAY i ndn re EH REED OREMUS n 16 5 16 5 CONSIDERATIONS FOR ON CHIP PROGRAM CODE MEMORY 16 5 APPENDIX A INSTRUCTION SET REFERENCE A 1 NOTATION FOR INSTRUCTION OPERANDS essen A 2 A2 QPCODE MAP ota T TT A 3 A 3 INSTRUCTION SET SUMMARY cecceecceeseeeeeeeteeeseaeeeeeeseaeeeaeeeeaeeeaeeseaeeeaeeseaeenaeenees A 4 A 3 1 Instruction SumMaries meteo os 4 4 INSTRUCTION DESCRIPTIONS essen nennen nene n nnne nennen A 9 APPENDIX B PIN DESCRIPTIONS APPENDIX C REGISTERS C 1 SFRS BY FUNCTIONAL CATEGORY ssssssssssseeeeeeeeteet trennen ere teen nennen C 3 2 SFRDESGCRIPTIONS nm tae ee LR tee Ue Re Ld C 6 APPENDIX D DATA FLOW MODEL APPENDIX E 8X931AA DESIGN CONSIDERATIONS E 1 DIFFERENCES BETWEEN THE 8X931AA AND THE 8 931 E 1 E2 8X931AA ENUMERATION PROCESS sese E 2 8 9 1 PIN E 3 E 4 8X931AA SIGNAL DESCRIPTIONS sse nnne E 6 E5 OPERATING FREQUENCIES
41. 2 The current polling cycle is not the final cycle in the execution of the instruction in progress 3 The instruction in progress is RETI or any write to the IENx or IPx registers Any of these three conditions will block the generation of the LCALL to the interrupt service rou tine Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write to IENx or IPx then at least one more instruction will be executed before any interrupt is vectored to 5 30 intel INTERRUPT SYSTEM The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle If the interrupt flag for a level sensitive ex ternal interrupt is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new The polling cycle LCALL sequence is illustrated in Figure 5 17 Note that if an interrupt of a higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 5 17 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction of the lower priority routine having been
42. 5 2 8 USB Global Suspend Resume Interrupt seeeeneenennen 5 17 5 2 8 1 Gllobal Suspernd aree REDE RUE 5 17 5 2 8 2 Global Resume epe eei teet teeth dde 5 17 5 2 8 3 5 1 nennen ennt nnns 5 17 5 2 9 USB Reset Separation us oe A ge De 5 17 intel 5 2 9 1 Initialization Required for USB Reset 5 18 5 2 9 2 USB Reset Hardware Operations 5 21 5 2 9 3 USB Reset ISR niue dei a ie crece cres pe oreet de 5 21 5 2 9 4 Main Routine Considerations ssssssseeeeeneenneneeneeneen nen 5 22 5 3 INTERRUPT ENABLE ea eter eed p e RED b 5 24 5 4 INTERRUPT PRIORIMES zi e eed RR me e s 5 26 5 5 INTERRUPT HANDEING D ERRARE PD Red 5 30 5 6 RESPONSE TIME seina e dtt eo ae Lp atte rs 5 32 CHAPTER 6 USB FUNCTION 6 1 e ee RU RU EUR es 6 1 6 1 1 Function EndpoiritPalrs 5 nee et e erae 6 1 6 1 2 Function FIFOS tr biete en o oe velas eed 6 1 6 1 3 Endpoint indexed SFERS e tee pete RR RR RARE 6 5 61 4 Endpoint Selection eie erdt D el ele xe tta 6 5 6 2 USB F NGTION RR ET 6 7 6 3 TRANSMIT FIEOS 3 neta eae et e e ar a 6 14 6 3 1 Transmit AFO REGISters 6 15 6 3 2 Transmit FIFO Da
43. 5 4 5 30 C 3 C 32 bit definitions 5 26 Isochronous RX dataflow Dual packet mode D 18 Isochronous TX dataflow Dual packet mode D 5 ISR See Interrupts service routine J JB instruction A 8 JBC instruction A 8 JC instruction A 8 JMP instruction A 8 JNB instruction A 8 JNC instruction A 8 JNZ instruction A 8 JZ instruction A 8 K KBCON 12 1 Key bytes See Encryption array Keyboard control signals 12 2 Keyboard interrupt logic 12 3 Keyboard scan 12 2 interrupt 5 6 5 7 interrupt enable bit 5 25 C 28 matrix 12 2 L LED drivers 12 2 12 4 LJMP instruction 8 Lock bits protection types 16 4 verifying 16 1 Logical instructions 4 7 table of 4 6 A 5 Low clock mode 14 1 14 13 entering 14 13 exiting 14 13 M MCS 51 1 1 architecture features 2 5 2 6 Microcontroller core 2 6 Miller effect 13 3 INDEX instruction 6 for bits 7 MOVC instruction A 6 Move instructions table of A 6 instruction 6 Noise reduction 13 2 13 3 Non isochronous RX dataflow dual packet mode D 11 single packet mode D 8 Non isochronous TX dataflow D 1 Nonvolatile memory verifying 16 1 16 6 NOP instruction A 8 On chip code memory idle mode 14 6 setup for verifying 16 2 16 3 top eight bytes 16 5 On chip oscillator hardware setup 13 1 On chip RAM idle mode 14 6 reset 13 6 ONCE mode 14 1 entering 14 13 exiting 14 13 Opcodes map A 3 ORL inst
44. 5 SOFIE SOF Interrupt Enable When this bit is set setting the ASOF bit causes an interrupt request to be generated if the interrupt channel is enabled Hardware reads but does not write this bit 4 FTLOCK Frame Timer Locked read only When set this bit indicates that the frame timer is presently locked to the USB bus frame time When cleared this bit indicates that the frame timer is attempting to synchronize to the frame time 3 SOFODIS SOF Pin Output Disable When set the SOF pin will be disabled and will respond like a port pin The SOF pin will be driven to 1 when SOFODIS is set When this bit is clear setting the ASOF bit causes the SOF pin to be toggled with a low pulse for eight To s 2 0 TS10 8 Time stamp received from host TS10 8 are the upper three bits of the 11 bit frame number issued with an SOF token This time stamp is valid only if the SOFACK bit is set If an artificial SOF is generated the time stamp remains at its previous value and it is up to firmware to update it These bits are set and cleared by hardware C 49 8x931AA 8x931HA USER S MANUAL intel SOFL Address D2H Reset State 0000 0000B Start of Frame Low Register Contains the lower eight bits of the 11 bit time stamp received from the host 7 0 TS7 0 Bit Bit Function Number Mnemonic unct 7 0 TS7 0 Time stamp received from host This time stamp is valid only if the SOFACK bit in the SOFH r
45. 8 17 8 23 firmware responses 8 17 8 22 full speed device attach 7 6 ganged power enable 7 29 GET CONFIGURATION request 8 18 GET DESCRIPTOR request 8 18 GET INTERFACE request 8 18 GET STATUS request 8 18 GetBusState request 8 20 GetHubDescriptor request 8 20 GetHubsStatus request 8 20 GetPortStatus request 8 20 8 23 GetPortStatus request firmware 8 25 8 26 global suspend and resume 7 25 7 27 interrupt 5 7 low speed device attach 7 7 monitoring port status 7 20 7 23 operation 8 17 8 22 8 23 8 28 overcurrent detection 7 29 port control 7 14 7 16 port control commands 7 16 port indexing 7 23 port power switching 7 27 7 28 port states 7 4 7 5 port status change communication 8 23 8 28 power distribution 7 27 SET ADDRESS request 8 18 SET CONFIGURATION request 8 18 V tel SET_DESCRIPTOR request 8 18 SET_FEATURE request 8 17 SET_INTERFACE request 8 18 SetHubDescriptor request 8 20 SetHubFeature request 8 20 SetPortFeature PORT_RESET firmware 8 27 SetPortFeature PORT_SUSPEND firmware 8 26 SetPortFeature request 8 21 signaling connectivity 7 6 7 7 status 7 9 7 10 C 23 C 26 status and configuration 8 17 status change communication 7 13 SYNCH FRAME request 8 18 idle state 8 1 8 3 interrupts function 5 7 5 8 5 11 global suspend resume 5 7 5 17 hub 5 7 5 15 start of frame 5 11 5 14 module 2 2 2 11 block diagram 2 7 power control
46. C 39 Register file and reset 13 6 rel A 2 Reset 13 5 13 7 cold start 13 5 entering ONCE mode 14 13 exiting idle mode 14 7 exiting powerdown mode 14 9 externally initiated 13 5 need for 13 7 operation 13 6 power on reset 13 1 13 7 timing sequence 13 6 13 7 USB initiated 13 5 warm start 13 5 RET instruction A 8 RETI instruction 5 1 A 8 RL instruction A 5 RLC instruction 5 RR instruction A 5 RRC instruction A 5 RST 13 5 13 6 ONCE mode 14 13 RXCNTL 6 26 C 40 RXD 9 1 11 1 mode 0 11 2 modes 1 2 3 11 7 RXDAT 6 26 C 42 RXFLG 6 31 C 43 RXSTAT 6 11 C 45 S SADDR 11 2 11 9 11 10 C 4 C 48 SADEN 11 2 11 9 11 10 C 4 C 48 SBUF 11 2 11 3 C 4 C 48 SCON 11 2 11 4 11 7 C 4 C 49 bit definitions 11 1 Security 16 1 intel Serial I O port 11 1 11 13 asynchronous modes 11 7 automatic address recognition 11 8 11 10 baud rate generator 10 7 baud rate mode 0 11 2 11 10 baud rate modes 1 2 3 11 7 11 11 11 13 broadcast address 11 9 data frame modes 1 2 3 11 7 framing bit error detection 11 7 full duplex 11 7 given address 11 9 half duplex 11 2 interrupts 11 1 11 8 mode 0 11 2 11 3 modes 1 2 3 11 7 multiprocessor communication 11 8 SFRs 11 1 11 2 C 4 synchronous mode 11 2 timer 1 baud rate 11 11 11 12 timer 2 baud rate 11 12 11 13 timing mode 0 11 6 SETB instruction A 7 SetHubDescriptor 8 20 SFR memory map C 1 SFRs idle mo
47. Clear this bit to select level triggered active low 1 Interrupt O Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt 0 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low C 53 8x931AA 8x931HA USER S MANUAL intel TMOD Address 89H Reset State 0000 0000B Timer Counter Mode Control Register Contains mode select run control select and counter timer select bits for controlling timer 0 and timer 1 7 0 GATE1 C T1 M11 M01 GATEO C TO amp M10 Moo Bit Bit 7 ion Number Mnemonic Functio 7 GATE1 Timer 1 Gate When GATE1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 MO1 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode3 Timer 1 halted Retains count 3 GATEO T
48. Firmware should always check TXOVF before write ONT 01 10 Received IN 00 0 1 0 no no None Send data No ACK time token data chg chg out for ISO transmitted with Read marker or without advanced transmission error Received IN 00 1 0 0 no 1 None Send CRC Only underrun token data chg with bit FIFO error can transmitted stuff error occur here FIFO error Read marker occurs advanced NOTES 1 These are sticky bits which must be cleared by firmware 2 TXFIF TXOVF and TXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF TXOVF Since overrun can only be caused by firmware TXOVF is updated immediately TXURF Since underrun can only be caused by USB TXURF is updated at SOF TXFIF TXFIF is incremented by firmware and decremented by USB Therefore writes to TXCNT will increment TXFIF immediately However a successful USB transaction anytime in a frame will only decrement TXF IF at SOF TXERR TXACK and TXVOID can only be caused by USB thus they are updated at the end of every valid transaction 3 NOTE This table assumes TXEPEN ATM are enabled D 5 8x931AA 8x931HA USER S MANUAL intel Table D 2 Isochronous Transmit Data Flow in Dual packet Mode Continued New at next SOF TX TX TX TX TXFIF USB 1 0 Event m TX TX TX am abe
49. Flags Example Bytes States Cycles Operation JMP A DPTR Function Description Flags Example A 30 CY AC OV The CY flag is clear After the instruction sequence JC LABEL1 CPL CY JC LABEL 2 the CY flag is set and program execution continues at label LABEL2 2 12 2 Encoding 0100 0000 rel addr JC PC PC 2 IF CY 1 THEN lt PC rel Jump indirect Add the 8 bit unsigned contents of the accumulator with the 16 bit data pointer and load the resulting sum into the lower 16 bits of the program counter This is the address for subsequent instruction fetches The contents of the accumulator and the data pointer are not affected CY AC OV The accumulator contains an even number from 0 to 6 The following sequence of instruc tions branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR AJMP LABELO JMECTBES AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator contains 04H at the start this sequence execution jumps to LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address intel INSTRUCTION SET REFERENCE Bytes 1 States 12 Cycles 2 Encoding 0111 0011 Operation JMP PC 15 0 A DPTR JNB bit rel Function Jump if bit not set Description If the sp
50. Interrupt sources for the 8x931 include external interrupts timer interrupts a keyboard scan in terrupt USB function transmit and receive interrupts a USB start of frame interrupt a USB glo bal suspend and resume interrupt and a separate USB only reset interrupt These interrupts are described in the following subsections 5 5 8x931AA 8x931HA USER S MANUAL intel 5 2 4 External Interrupts External interrupts INTO and INT 1 INTx pins may each be programmed to be level trig gered or edge triggered dependent upon bits ITO and IT1 in the TCON register see Figure 10 6 on page 10 8 If ITx 0 INTx is triggered by a detected low at the pin If ITx 1 INTx is negative edge triggered External interrupts are enabled with bits EXO and EX1 EXx in the IENO register see Figure 5 10 on page 5 24 Events on the external interrupt pins set the inter rupt request flags IEx in TCON These request bits are cleared during the hardware vector to the service routine only if the interrupt is negative edge triggered If the interrupt is level triggered the interrupt service routine must clear the request bit External hardware must deassert INTx before the service routine completes or an additional interrupt is requested External interrupt pins must be deasserted for at least four state times prior to a request External interrupt pins are sampled once every six state times a frame length of 1 us at 6 MHz A level triggered inter
51. KSEN of KBCON to activate the KSI pullups and enable the keyboard scan interrupt flag IE2 of KBCON If KSEN is set the IE2 flag may be set even if the hardware interrupt is disabled 1 EX2 0 Additionally the Interrupt 2 Type control bit IT2 of KBCON must be set or cleared to specify whether the interrupt will be triggered on negative edge or level 0 12 3 8x931AA 8x931HA USER S MANUAL intel 12 3 LED DRIVERS The LED drivers enable external LEDs to be connected directly between V o and the LED driver pins without the need for external resistors The current each driver is capable of sinking is given as Vo in the datasheet NOTE The KSEN keyboard scan enable bit must be set to activate the LED drivers Power Supply A5321 01 Figure 12 3 LED Driver Application 12 4 intel 13 Minimum Hardware Setup intel CHAPTER 13 MINIMUM HARDWARE SETUP This chapter discusses the basic operating requirements of the 8x931 and describes a minimum hardware setup Topics covered include power ground clock source and device reset For pa rameter values refer to the device data sheet 13 1 MINIMUM HARDWARE SETUP Figure 13 1 shows a minimum hardware setup that employs the on chip oscillator for the system clock and provides power on reset Control signals Ports 0 3 and the USB ports are not shown See Clock Sources on page 13 2 and Power on Reset on page 13 7 PLLSEL selects
52. PCON1 Continued Address DFH Reset State x000B USB Power Control Register Facilitates the control and status relating to global suspend and resume USB reset separation and remote wake up of the 8x931 0 URDIS URST RWU GRSM GSUS 1 GRSM Global Resume Bit 1 resume Set by hardware when a global resume is detected on the USB lines This bit is ORed with GSUS to generate the interrupt Cleared by firmware when servicing the global suspend resume interrupt This bit can also be set cleared by firmware for testability This bit is not set if remote wakeup is used see RWU See Figure 14 3 on page 14 11 0 GSUS Global Suspend Bit 1 suspend This bit is set by hardware when global suspend is detected on the USB lines This bit is ORed with the GRSM bit to generate the interrupt t During the global suspend ISR firmware should set the PD bit to enter the suspend mode Cleared by hardware when a resume occurs See Figure 14 3 on page 14 11 Firmware should prioritize GRSM over GSUS if both bits are set simultaneously Figure 14 2 PCON1 USB Power Control Register Continued 14 5 8x931AA 8x931HA USER S MANUAL intel 14 3 IDLE MODE Table 14 1 Pin Conditions in Various Modes Idle Mode Powerdown Mode Once Mode Pin Internal External Internal External Program Memory Program Memory Memory Memory ALE Weak Hig
53. Post Transmit tim 2 Routine 0 Adjust FIFO read marker and read pointer RETI 4262 02 8 6 Figure 8 2 High level View of Transmit Operations intel USB PROGRAMMING MODELS 8 22 Pre transmit Operations Transmitted data originates in the embedded function which might be a keyboard mouse joy stick scanner etc In event control applications the end function signals the availability of data with an interrupt request for the pre transmit interrupt service routine ISR The ISR should pre pare the data for transmission and initiate the transmission process The flow chart in Figure 8 3 illustrates a typical pre transmit ISR For the case of isochronous data the interrupt is triggered by the USB function in response to a start of frame SOF packet Start Non ISO Vacancy in Transmit FIFO TXFIF1 0 z 11 in Dual packet Mode TXFIF1 0 00 in Single packet Mode Yes Transfer Packet to Transmit FIFO through TXDAT Error in Transmit FIFO TXOVF 1 overflow Error Recovery Write Packet Size to TXCNT RETI A5071 01 Figure 8 3 Pre transmit ISR Non Isochronous 8 7 8x931AA 8x931HA USER S MANUAL intel 8 23 Post transmit Operations Transmission status is updated at the end of data transmission based on the handshake received from the host non isochronous data or based on the transmission process itself isochronous data
54. Setting this bit causes the 8x931 to trigger a hardware interrupt when a keyboard scan interrupt occurs but only if the KSEN bit in the KBCON register is also set 6 3 Reserved Write zeros to these bits 2 Enable Suspend Resume Reset USB global suspend resume reset interrupt enable bit 1 EF Enable Function Transmit Receive Done interrupt enable bit for non isochronous USB function endpoints 0 ESOF Enable USB Hub Start of Frame Any start of frame interrupt enable for isochronous endpoints or USB hub interrupt enable Figure 5 11 IEN1 USB Interrupt Enable Register 5 25 8x931AA 8x931HA USER S MANUAL intel 5 4 INTERRUPT PRIORITIES The 8x931 interrupt sources may be individually programmed to one of four priority levels This is accomplished with the IPHX x IPLX x bit pairs in the interrupt priority high IPHI IPHO in Fig 5 12 and 5 14 and interrupt priority low IPL1 IPLO registers Figures 5 13 and 5 15 Spec ify the priority level as shown in Table 5 5 using IPHO x or IPH1 x as the MSB and IPLO x or IPL1 x as the LSB Table 5 5 Level of Priority Priority Level IPH1 x IPL1 x IPHO x IPLO x 0 Lowest Priority 00 00 1 01 01 2 10 10 3 Highest Priority 11 11 A low priority interrupt is always interrupted by a higher priority interrupt but not by another in terrupt of equal or lower priority The highest priority interrupt is not interrupted by any other interrupt
55. The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins Flags CY AC OV Example The on chip RAM locations 40H 50H and 60H contain 01H 70H and 15H respectively After executing the following instruction sequence DJNZ 40H LABEL1 DJNZ 50H LABEL2 DJNZ 60H LABEL3 on chip RAM locations 40H 50H and 60H contain 00H 6FH and 14H respectively and program execution continues at label LABEL2 The first jump was not taken because the result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPLP1 7 DJNZ R2 TOGGLE toggles P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse lasts three machine cycles two for DJNZ and one to alter the pin Variations DJNZ dir8 rel Bytes 3 States 12 Cycles 2 Encoding 1101 0101 direct addr rel addr A 25 8x931AA 8x931HA USER S MANUAL intel Operation DJNZ Rn rel Bytes States Cycles Operation INC lt Byte gt Function Description Flags Example Variations INCA Bytes States Cycles A 26 DJNZ PC PC 2 dir8 lt d
56. be either binary or hexadecimal depending on the context For example 2xAFH hex indicates that bits 11 8 are unknown 10xx in binary context indicates that the two LSBs are unknown Assert and Deassert The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low Instructions Instruction mnemonics are shown in upper case to avoid confusion When writing code either upper case or lower case may be used Logic 0 Low An input voltage level equal to or less than the maximum value of Vj an output voltage level equal to or less than the maximum value of Vor See data sheet for values Logic 1 High An input voltage level equal to or greater than the minimum value of an output voltage level equal to or greater than the minimum value of Voy See data sheet for values 1 3 8x931AA 8x931HA USER S MANUAL intel Numbers Register Access Register Bits Register Names Reserved Bits Set and Clear Signal Names Units of Measure 1 4 Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H Decimal and binary
57. bit is cleared to allow proper data management for the transmit and receive FIFOs from the previous transaction IN or OUT tokens are NAKed even if the endpoint is stalled RXSTL or TXSTL to allow a control transaction to clear a stalled endpoint Clear this bit upon detection of a SETUP token after the firmware is ready to complete the status stage of a control transaction Start Overwrite Flag read only Set by hardware upon receipt of a SETUP token for any control endpoint to indicate that the receive FIFO is being overwritten with new SETUP data When set the FIFO state FIF and read pointer resets and is locked for this endpoint until EDOVW is set This prevents a prior ongoing firmware read from corrupting the read pointer as the receive FIFO is being cleared and new data is being written into it This bit is cleared by hardware at the end of handshake phase transmission of the setup stage This bit is used only for control endpoints Under normal operation this bit should not be modified by the user For additional information on the operation of these bits see Appendix D Data Flow Model The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface C 43 8x931AA 8x931HA USER S MANUAL intel RXSTAT Continued Endpoint indexed Address E2H Reset State 0000 0000B Endpoint Receive Status Register Contains the current
58. bus which transmits a 16 bit address multiplexed with eight data bits Ports P1 and P3 carry bus control and peripheral signals See Table B 7 Signal Description on page B 12 The MCS 51 architecture has two power saving modes In idle mode the CPU clock is stopped while clocks to the peripherals continue to run In global suspend mode powerdown the on chip oscillator is stopped and the chip enters a static state In addition to idle and powerdown the 8x931 has a special power saving mode low clock mode which it enters following a device re set Refer to Chapter 14 Special Operating Modes for details on power saving modes 2 2 MICROCONTROLLER CORE The microcontroller core contains the central processor unit CPU the clock and reset unit the interrupt handler the bus interface and the peripheral interface Figure 2 2 2 2 1 CPU The CPU contains the ALU program counter instruction decoder data memory interface gen eral purpose registers RO R7 and special function registers ACC B stack pointer SP and data pointer DPTR The CPU executes the instruction set of the MCS 51 architecture The instruction set is optimized for control operations It provides fast addressing modes to facilitate byte operations on small data structures and extensive support for one bit variables as a separate data type For information on the instruction set refer to the MCS 51 Microcontroller Family User s Manual and the M
59. dirrr Operation ADDC A A CY Rn AJMP addr11 Function Absolute jump Description Transfers program execution to the specified address which is formed at run time by concatenating the upper five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2 Kbyte page of program memory as the first byte of the instruction following AJMP Flags CY AC OV Example The label JMPADR is at program memory location 0123H After executing the instruction AJMP JMPADR at location 0345H the PC contains 0123H Bytes 2 States 12 Cycles 2 Encoding a10 a9 a8 0 0001 a7 a6 a5 a4 a3 a2 a1 a0 Operation AJMP 2 10 0 lt page address ANL dest src Function Logical AND 8x931AA 8x931HA USER S MANUAL intel Description Flags Example Variations ANL dir8 A Bytes States Cycles Operation ANL dir8 data Performs the bitwise logical AND A operation between the specified variables and stores the results in the destination variable The two operands allow 10 addressing mode combinations When the destination is the register or accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When
60. flags before and after reads from the receive FIFO and the setting of RXFFRC in RXCON NOTE To simplify firmware development it is recommended that you utilize control endpoints in single packet mode only gt lt gt lt X lt X lt 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits RXEMP Receive FIFO Empty Flag read only Hardware sets this flag when the write pointer is at the same location as the read pointer and the write pointer equals the write marker and neither pointer has rolled over Hardware clears the bit when the empty condition no longer exists This is not a sticky bit and always tracks the current status of the receive FIFO regardless of ISO or non ISO mode When set all transmissions are NAKed C 41 8x931AA 8x931HA USER S MANUAL intel RXFLG Continued Endpoint indexed Address E5H Reset State 00xx 1000B Receive FIFO Flag Register These flags indicate the status of data packets in the receive FIFO specified by EPINDEX 7 RXFIF1 RXFIFO RXEMP RXFULL RXURF RXOVF Bit Number Bit Mnemonic Function RXFULL Receive FIFO Full Flag read only Hardware sets this flag when the write pointer has rolled over and equals the read pointer Hardware clears the bit when the full condition no longer exists This is not a sticky bit and always tracks the current status of the receive FIFO
61. if change is detected in the over current status even if the condition goes away before it is detected by firmware Cleared via a USB ClearFeature request with C HUB OVER CURRENT feature selector Cleared to 0 if no change Reserved The value read from this bit is indeterminate Write a zero to this bit Bits 1 and3 are returned in response to a Get Hub Status request from the USB host This response is a four byte field with zero padding MSB at left 0000 0000 0000 00 3 0 0000 0000 0000 00 1 0 C 23 8x931AA 8x931HA USER S MANUAL intel HSTAT Continued Address AEH Reset State 0000 0000B Hub Status and Configuration Register This SFR contains bits for remote wake up request status and status change indicators for over current and hub endpoint 1 stall and enable 7 OVRIEN HRWUPE EP1STL EP1EN OVISC OVI Bit Bit Number Mnemonic Function 1 OVI Latest Over current Indicator read only Hardware sets and clears this bit via the OVRI input pin 1 indicates an over current condition 0 indicates normal power operation 0 Reserved The value read from this bit is indeterminate Write a zero to this bit Bits 1 and 3 are returned in response to a Get Hub Status request from the USB host This response is a four byte field with zero padding MSB at left 0000 0000 0000 00 3 0 0000 0000 0000 00 1 0 C 24
62. must clear this bit when the interrupt is serviced 6 Reserved Write a zero to this bit 5 KSEN Keyboard Scan Enable Setting this bit enables the pullup resistors on the KSI input lines enables the keyboard scan interrupt INT2 and enables the LED drivers NOTE The EX2 bit in the IENO SFR must also be set to enable the KSI external interrupt 4 IT2 Interrupt 2 Type Control Bit If set a negative edge detect on any of the KSI pins causes IE2 to be set When clear IE2 acts as a level 0 triggered interrupt 3 0 LED3 0 LED Driver Control Clearing one of these bits turns on the associated LED Setting a bit turns off the associated LED NOTE The KSEN Keyboard Scan Enable bit must be set in order to activate the LED drivers After reset the LED driver control bits are cleared This means that when KSEN is set the LEDs will turn on Firmware must set the LED driver control bits to turn off the LEDs C 31 8x931AA 8x931HA USER S MANUAL intel PO Address 80H Reset State 1111 1111B Port 0 PO is the SFR that contains data to be driven out from the port 0 pins Read modify write instructions that read port 0 read this register The other instructions that read port 0 read the port 0 pins When port 0 is used for an external bus cycle the CPU always writes FFH to PO and the former contents of PO are lost 7 0 PO Contents Bit Bit Number Mnemonic Function 7 0 P0 7 0 Po
63. regardless of ISO or non ISO mode Receive FIFO Underrun Flagt Hardware sets this bit when an additional byte is read from an empty receive FIFO or RXCNT Hardware does not clear this bit so you must clear it in firmware When the receive FIFO underruns the read pointer will not advance it remains locked in the empty position In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since underrun can only be caused by firmware RXURF is updated immediately You must check the RXURF flag after reads from the receive FIFO before setting the RXFFRC bit in RXCON NOTE When this bit is set the FIFO is in an unknown state It is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register Receive FIFO Overrun Flagt This bit is set when the FIU writes an additional byte to a full receive FIFO or writes a byte count to RXCNT with FIF1 0 11 This is a sticky bit that must be cleared through firmware although it can be cleared by hardware if a SETUP packet is received after an RXOVF error had already occurred t When this bit is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register When the receive FIFO overruns the write pointer will not advance it r
64. the UART outputs a clock signal on the TXD pin and sends and receives messages on the RXD pin Figure 11 1 The SBUF register which holds re ceived bytes and bytes to be transmitted actually consists of two physically different registers To send firmware writes a byte to SBUF to receive firmware reads SBUF The receive shift reg ister allows reception of a second byte before the first byte has been read from SBUF However if firmware has not read the first byte by the time the second byte is received the second byte will overwrite the first The UART sets interrupt bits TI and RI on transmission and reception respec tively These two bits share a single interrupt request and interrupt vector The serial port control SCON register Figure 11 2 configures and controls the serial port Table 11 1 Serial Port Signals Function Multiplexed Description With TXD O Transmit Data In mode 0 TXD transmits the clock signal In P1 7 modes 1 2 and 3 TXD transmits serial data Receive Data In mode 0 RXD transmits and receives serial P1 6 data In modes 1 2 and 3 RXD receives serial data 8x931AA 8x931HA USER S MANUAL intel Table 11 2 Serial Port Special Function Registers Mnemonic Description Address SBUF Serial Buffer Two separate registers accessed with same address 99H comprise the SBUF register Writing to SBUF loads the transmit buffer reading SBUF accesses the rece
65. there is a carry out of bit 3 AC the AC flag is set When adding unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit 8x931AA 8x931HA USER S MANUAL intel Four source operand addressing modes are allowed register direct register indirect and immediate Flags CY AC OV 3 3 3 Example The accumulator contains 11000011B register 0 contains OAAH 10101010B and the CY flag is set After executing the instruction ADDC A RO the accumulator contains 6EH 01101110B the AC flag is clear and the CY and OV flags are set Variations ADDC A data Bytes 2 States 6 Cycles Encoding 0011 0100 immed data Operation ADDC A A CY data ADDC A dir8 Bytes 2 States 6 Cycles Encoding 0011 0101 direct addr Operation ADDC A A CY dir8 ADDC A QRi Bytes States 6 Cycles Encoding 0011 011i Operation ADDC lt CY Ri intel ADDC A Rn Bytes States 6 Cycles 1 INSTRUCTION SET REFERENCE Encoding 0011
66. true bidirec tional pin The pin floats when configured as input Resets write logical one to all port latches If logical zero is subsequently written to a port latch it can be returned to input conditions by a logical one written to the latch For additional electrical information refer to the current 8x931 datasheet NOTE Port latch values change near the end of read modify write instruction cycles Output buffers and therefore the pin state update early in the instruction after the read modify write instruction cycle Logical zero to one transitions in port 1 port 2 and port 3 utilize an additional pullup to aid this logic transition see Figure 9 4 This increases switch speed The extra pullup briefly sources 100 times the normal internal circuit current The internal pullups are field effect transistors rather than linear resistors Pullups consist of three p channel FET pFET devices A pFET is on when the gate senses logical zero and off when the gate senses logical one pFET 1 is turned on for two oscillator periods immediately after a zero to one transition in the port latch A logic one at the port pin turns on pFET 3 a weak pullup through the inverter This inverter and pFET pair form a latch to drive logic one pFET 2 is a very weak pullup switched on whenever the associ ated nFET is switched off This is a traditional CMOS switch convention Current strengths are 1 10 that of pFET 3 2 Osc Periods Voc Voc Voc
67. written to this register 7 0 Transmit Data Byte Bit Bit Number Mnemonic Function 7 0 TXDAT 7 0 Transmit Data Byte write only To write data to the transmit FIFO write to this register The write pointer is incremented automatically after a write For hub endpoint 1 TXDAT is used in a different manner See Figure 7 7 on page 7 12 C 58 intel REGISTERS TXDAT For hub endpoint 1 only EPINDEX 81H Address F3H Reset State xxxxB 7 0 TXDATS TXDAT4 TXDAT3 TXDAT2 TXDAT1 TXDATO Bit Bit Number Mnemonic Function 7 6 Reserved Values read from this bit s are indeterminate 5 0 TXDAT5 0 Hub Endpoint 1 Status Change read only Hardware communicates status changes to the host by setting the appropriate bit TXDATO hub status change TXDAT1 port 1 status change TXDAT2 port 2 status change TXDATS port 3 status change TXDAT4 port 4 status change TXDATS port 5 status change A 1 indicates a status change and 0 indicates no status change When endpoint 1 is addressed via an IN token the entire byte is sent if at least one bit is a 1 If all bits are zero a NAK handshake is returned TXDAT SFRs are also used for function and hub endpoint 0 data transmission EPINDEX 0xH or 80H In that case the bits are defined differently as shown in Figure 6 8 on page 6 16 Bits 5 1 can be set indirectly by firmware
68. yet check TXOVF before write CNT NOTE no TXERR but TXOVF set 11 Received IN 10 01 0 1 0 no no Set Send data ACK token data chg chg transmit received so transmitted interrupt no errors host ACKs Read marker advanced Received IN 11 1 0 0 no no Set Send data SIE times out token data chg chg transmit Read pointer transmitted interrupt reversed no ACK time out Received IN 11 0 0 1 no no None NAKs Received token but chg chg future Setup token RXSETUP transactions or transmit 1 or disabled so TXOE 0 IN tokens are NAKed 2 Received IN 11 1 0 0 no 1 Set Send data Only FIFO token data chg transmit with bit underrun transmitted interrupt stuff error error can FIFO error future occur here occurs transactions Read pointer reversed NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes TXEPEN and ATM are enabled 2 Future transactions are NAKed even if the transmit endpoint is stalled when RXSETUP 1 D 3 8x931AA 8x931HA USER S MANUAL intel Table D 1 Non isochronous Transmit Data Flow Continued New TX TX TX TXFIF TX TX TX USB Event TXFIF OVF Inter Comments 1 0 1 0 ERR ACK Void 1 1 rupt Response Received IN 11 1 0 1 no 1 None NAK Treated like a token with no no chg no void existing chg chg chg condition FIFO error and TXERR s
69. 0 Structure 9 3 8x931AA 8x931HA USER S MANUAL intel Address Voc Control Read Internal Latch Internal Bus Write to Latch Read Pin A2240 01 Figure 9 3 Port 2 Structure When port 0 and port 2 are used for an external memory cycle an internal control signal switches the output driver input from the latch output to the internal address data line External Memory Access on page 9 7 discusses the operation of port 0 and port 2 as the external address data bus NOTE Port 0 and port 2 are precluded from use as general purpose I O ports when used as address data bus drivers Port 0 internal pullups assist the logic one output for memory bus cycles only Except for these bus cycles the pullup FET is off All other port 0 outputs are open drain 9 4 intel INPUT OUTPUT PORTS 9 5 READ MODIFY WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data The latch based instructions read the data modify the data and then rewrite the latch These are called read modify write in structions Table 9 2 contains a complete list of these special instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin Table 9 2 Read Modify Write Instructions Instruction Description ANL logical AND e g ANL P1 A ORL logical OR e g ORL P2 A XRL logical EX OR e g XRL P3
70. 1 byte 5 Time elapsed from when the power on sequence begins on a port until power is good on that port bHubContrCurrent 1 byte 6 Maximum current requirements of the hub controller DeviceRemovable 1 byte 7 Indicates if a port has a removable device attached PortPwrCtriMask 1 byte Variable Indicates if a port is affected by a gang mode power control request 7 2 2 Hub Address Register HADDR During bus enumeration the host PC communicates a unique address for the hub through hub endpoint 0 using the set address command Device firmware must interpret and write this hub ad dress to the Hub Address register HADDR as shown in Figure 7 5 This procedure is outlined in Enumeration on page 8 2 HADDR Address 97H Reset State 0000 0000B Hub Address Register This SFR holds the address for the hub device During bus enumeration it is written with a unique value assigned by the host 7 0 Hub Address Bit Number Function 7 Reserved Write a zero to this bit 6 0 Hub address register Updated using a SET ADDRESS USB host request This address is used by the HIU to perform token decoding Figure 7 5 HADDR Hub Address Register 7 8 intel USB HUB 73 HUB STATUS Status and configuration of the USB hub function is performed by both standard and hub class specific USB requests These requests generated by the host PC manage and configure the status of the hub and
71. 12 2 4 2 Hub Interface ee eni 2 13 2 4 3 Hub Repeater 5 ieee a eae eed Rae ene 2 13 2 4 4 Serial Bus Interface Engine SIE sess 2 13 2 4 5 Hub Interface Unit 2 13 274 6 H b EIEOS etna tee io eteii meds 2 13 2 5 2 tete pre 2 14 2 5 1 Timer Gouriers 5 nutem Cea easi 2 14 2 5 2 Serial l O Pott cui nee eu Ue 2 14 2 6 OPERATING CONDITIONS reote tri RR Ha egit 2 14 8x931AA 8x931HA USER S MANUAL intel CHAPTER 3 ADDRESS SPACES 3 1 MEMORY ORGANIZATION IN 8x931 DEVICES eene 3 1 3 1 1 Logical Separation of Program and Data Memory 3 1 3 1 2 Program Memoty 5 nene REO EH E EORR 3 1 3 1 3 Data Memory intet ie er ge dundee deed dic ceo Doa Reden 3 3 3 2 SPECIAL FUNCTION REGISTERS SFRS sse 3 5 CHAPTER 4 PROGRAMMING CONSIDERATIONS 4 1 THE 51 INSTRUCTION SET nrc b b pn e n dob d 4 1 4 1 1 Progr m Status Word ui eed ene ignei e i e idee 4 1 44 2 Addressing nonet ce DON ee REPREHENE 4 3 4 1 2 1 DIRECT ADDRESSING 4 3 4 1 2 2 INDIRECT 5 51 4 3 4 1 2 3 REGISTER INSTRUCTIONS essen nnne nennen entren 4 3 4 1 2 4 REGISTER SPECIFIC INSTRUCTIONS 2
72. 14 7 powerdown 14 8 programming models 8 1 receive FIFOs 6 24 write marker 6 24 8 10 write pointer 6 24 8 10 remote wake up 5 17 14 10 requests ClearPortFeature 7 14 SetPortFeature 7 14 reset separation 5 17 5 23 transaction dataflow model 6 1 D 1 transmit FIFOs read marker 6 15 8 5 read pointer 6 15 8 5 unenumerated state 8 1 Vcc 13 2 during reset 13 5 power on reset 13 7 powerdown mode 14 8 Verifying nonvolatile memory 16 1 Vss 13 2 INDEX W WAIT 9 1 World Wide Web 1 7 WR 9 1 X XCH instruction A 7 XCHD instruction A 7 XTAL2 13 2 capacitance loading 13 3 Index 7
73. 5 Set and cleared by hardware after sampling the connect state at EOF2 near the end of the present frame 1 device is present on port x 0 device is not present This bit will be set if either a physical connection is detected or during a hub reset when a downstream device is already connected This bit will be cleared if a disconnect is detected Port 1 Hard wired to 1 since the internal function is permanently connected NOTES Firmware returns the bits of this register in the first word of the 8x931 response to the host s GetPortStatus request See GetPortStatus Request Firmware on page 8 25 Overcurrent indication is not represented on a per port basis because the 8x931 supports ganged power control and overcurrent indication Figure 7 10 HPSTAT Hub Port Status Register Continued 7 19 8x931AA 8x931HA USER S MANUAL intel 7 5 8 Monitoring Port Status Change Using HPSC When firmware changes the status of a port there may be a delay between the time firmware re quests the status change using the HPCON register as described in Controlling a Port Using HPCON on page 7 14 and the time hardware actually changes the state This occurs because some port changes require hardware to perform auxiliary functions such as driving a state down stream for up to 20ms Additionally some status changes are initiated by hardware Firmware can determine when a port status change has occurred by
74. 5 TMOD Timer Counter Mode Control Register 10 7 8x931AA 8x931HA USER S MANUAL intel TCON Address S 88H Reset State 0000 0000B Timer Counter Control Register Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1 7 0 1 TRI TFO TRO IE1 IT1 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by firmware to turn timer 1 on off 5 TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 Timer 0 Run Control Bit Set cleared by firmware to turn timer 0 on off 3 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 Interrupt O Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt 0 Ty
75. 51 instruction set is presented below with a brief description of how certain instructions might be used References to the assembler in this discussion are to Intel s MCS 51 Macro Assembler ASM51 More detailed information on the instruction set can be found in the MCS 51 Macro Assembler User s Guide Order No 9800937 for ISIS Systems Or der No 122752 for DOS Systems 4 1 1 Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU The PSW shown in Figure 4 1 resides in SFR space It contains the Carry bit the Auxil iary Carry for BCD operations the two register bank select bits the Overflow flag a Parity bit and two user definable status flags The Carry bit other than serving the functions of a Carry bit in arithmetic operations also serves as the Accumulator for a number of Boolean operations The bits RSO and RSI are used to select one of the four register banks shown in Figure 3 4 on page 3 4 A number of instructions refer to these RAM locations as RO through R7 The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS1 at execution time The Parity bit reflects the number of 1s in the Accumulator 1 if the Accumulator contains an odd number of 1s and P 0 if the Accumulator contains an even number of 1s Thus the number of 15 in the Accumulator plus P is always even Two bits in the PSW a
76. 6 2 Non hub USB Signal Descriptions esseeeeeneeeen eene 6 2 USB Function SFRS cic Ascher ente detiene cite teas 6 3 Writing to the Byte Count Register sssssssseeeeeeneenenneen nennen 6 17 Truth Table for Transmit FIFO Management sese 6 18 Status of the Receive FIFO Data Sets 6 27 Truth Table for Receive FIFO Management sse 6 28 USB Hub SERS it dirt cioe ea e Peer eed estet ett Ete 7 3 8 931 Descriptors irm Sarg es ete 7 7 H b Descriptors sos oco entere eee Tto ser eee crei Ye gastos 7 8 Hub Endpoint Configuration 7 11 USB Requests Ignored by Hardware by Port State 7 14 Encoded Hub Port Control Commands seen 7 16 UPWEN Pin State Truth Table 7 30 Signal Descriptioris nente ete cm tette c en ir t e aeta 7 30 Firmware Actions for USB Requests Sent to 8 17 Firmware Action for Hub Class Specific 8 20 Input Output Port Pin Descriptions seseeeeenenennennnennen nennen 9 1 Read Modify Write Instructions
77. CONSIDERATIONS Table E 3 8x931AA Operating Frequencies a aa FSSEL LC Bit E MESES Frequency Comment in Pin 1 MHz 2 Ferk Mhz 0 0 6 LS 3 PLL Off 0 1 6 LS 3 PLL Off 1 0 0 12 LS 6 PLL Off 1 0 1 12 LS 3 PLL Off 1 1 0 12 FS 6 PLL On 1 1 1 12 FS 3 PLL On NOTES 1 Reset and power up routines set the LC bit in PCON to put the 8x931AA in low clock mode core frequency 3 MHz for lower lec prior to device enumeration Following completion of device enumeration firmware should clear the LC bit to exit the low clock mode The user may switch the core frequency back and forth at any time as needed 2 USB rates Low speed 1 5 Mbps Full speed 12 Mbps The USB sample rate is 4X the USB rate E 9 8x931AA 8x931HA USER S MANUAL intel E 6 8x931AA SFR MAP The 8x931AA SFR map Table E 4 on page E 10 is identical to the 8x931HA SFR map except the 8x931AA has no hub related SFRs Table E 4 8x931AA SFR Map 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7IF F8 KBCON FF 0xx00000 FO B EPINDEX TXSTAT TXDAT TXCON TXFLG TXCNTL F7 t 00000000 1xxxxx00 0 00000 XXXXXXXX Oxxx0100 00xx1000 XXXXXXXX E8 EF Eo acc EPCON RXSTAT RXCON RxFLG RXCNTL E7 00000000 00d10dOd 00000000 XXXXXXXX 0xx00100 00xx1000 XXXXXXXXT D8 PCON1 DF XXxxx000 D0 PSW SOFL SOFH D7
78. Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event Vt ERR ACK Void Setup m yid pes Response Comments Received 01 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token no interrupt automatically errors dual forcing new packet mode SETUP to be not received 2 recommende RXSETUP will be set control endpoints only Received 11 1 0 0 0 0 0 Set Time out FIFO is reset SETUP receive automatically and token but interrupt FIFO data is timed out invalid 2 waiting for data Received 00 1 0 0 1 0 0 Set Time out Write pointer SETUP receive reversed RXIE token data interrupt or RXSTL has no CRC or bit effect 2 stuff error dual packet mode not recommende d Received 00 1 0 0 1 1 0 Set Time out RXIE or RXSTL SETUP receive NAK has no effect 2 token FIFO interrupt future RXSETUP will be error dual transaction set control packet mode S endpoints only not recommende d Received 01 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token with interrupt automatically FIFO error forcing new already SETUP to be existing received 2 RXSETUP will be set control endpoints only CPU reads 10 01 no no no no no no None None FIFO sets chg chg chg chg chg RXFFRC NOTES 1 These are sticky bits which must be cleared by firmware
79. Description Performs the bitwise logical OR operation V between the specified variables storing the results in the destination operand The destination operand can be an accumulator or direct address The two operands allow six addressing mode combinations When the destination is the accumulator the source can be register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins Flags CY AC OV Example The accumulator contains 11000011B and RO contains 55H 01010101B After executing the instruction ORL A RO the accumulator contains 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be a constant data value in the instruction or a variable computed in the accumulator at run time After executing the instruction ORL P1 00110010B sets bits 5 4 and 1 of output Port 1 ORL dir8 A Bytes 2 States 6 Cycles Encoding 0100 0010 direct addr Operation ORL dir8 lt dir8 V A A 44 intel ORL dir8 data INSTRUCTION SET REFERENCE
80. Directs program memory accesses to on chip or off chip code memory For EA strapped to ground all program memory accesses are off chip For EA strapped to Vec program accesses on chip ROM if the address is within the range of the on chip ROM otherwise the access is off chip The value of EA is latched at reset For devices without on chip ROM EA must be strapped to ground PSEN Program Store Enable Read signal output Asserted for read accesses to external program memory RD Read Read signal output Asserted for read accesses to external P3 7 KSO19 data memory WR O Write Write signal output to external memory P3 6 KSO18 15 2 EXTERNAL BUS CYCLES This section describes the bus cycles the 8x931 executes to fetch code read data and write data in external memory NOTE For simplicity the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information For bus cycle timing parameters refer to the 8x931A A 8x931HA datasheet order number 273108 01 An inactive external bus exists when the 8x931 is not executing external bus cycles This occurs under any of the three following conditions Bus Idle The chip is in normal operating mode but no external bus cycles are executing Thechip is in idle mode Thechip is in powerdown mode 15 2 intel EXTERNAL MEMORY INTERFACE 15 2 1 Bus Cycle Definitions There are three types of bus c
81. FIFO sets chg chg chg chg chg Time out RXFFRC CPU reads 00 no no no no 1 None None Firmware FIFO causes chg chg chg chg Time out should check FIFO error RXURF bit before writing RXFFRC 11 Received OUT 11 no no 1 no no None None FIFO not ready token chg chg chg chg Time out but data must be taken This situation should never happen Received SOF no up up up up no None None Error condition indication chg dated dated dated dated chg SOF Time out not handled by up interrupt hardware dated Firmware should not allow this condition CPU reads 10 None None FIFO sets 01 chg chg chg chg chg Time out RXFFRC CPU reads 11 no no no no 1 None None Firmware FIFO causes chg chg chg chg Time out should check FIFO error RXUREF bit RXFFRC not before writing set yet RXFFRC CPU reads 10or no no no no 1 None None Firmware FIFO causes 01 chg chg chg chg Time out should check FIFO error Set RXUPF bit RXFFRC before writing RXFFRC NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 RXFIF RXOVF and RXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF RXURF Since underrun can only be caused by firmware RXURF is updated immediately RXOVF Since overrun can only be caused by USB RXOVF is updated at SOF RXFI
82. Function USB Hub SOF Suspend Resume Non Isochronous Isochronous and USB Reset Endpoint Endpoint Bit Name in IEN1 Register ESR EF ESOF Interrupt Priority Within Level 11 Low Priority i 19 1 High Priority Bit Names IPH1 IPH1 2 IPH1 1 IPH1 0 IPL1 IPL1 2 IPL1 1 IPL1 0 Mica Request ELIE FIFLG SOFH ASOF 9 GRSM FTXDx FRXDx HIFLG URST x 0 1 2 HTXDO HRXDO Interrupt Request Flag Cleared by No No No Hardware ISR Vector Address 0053H 004BH 0043H 5 2 2 Timer Interrupts Two timer interrupt request bits TFO and TF1 see TCON register Figure 10 6 on page 10 8 are set by timer overflow The exception is Timer 0 in Mode 3 see Figure 10 4 on page 10 6 When a timer interrupt is generated the bit is cleared during the hardware vector to the interrupt service routine Timer interrupts are enabled by bits ETO and ETI in the IENO register see Figure 5 10 on page 5 24 Timer 2 interrupts are generated by a logical OR of bits TF2 and 2 in register T2CON Nei ther flag is cleared by a hardware vector to a service routine In fact the interrupt service routine must determine if TF2 or EXF2 generated the interrupt and then clear the bit Timer 2 interrupt is enabled by ET2 in register IENO Figure 5 10 5 2 3 Keyboard Scan Interrupt The keyboard scan interrupt INT2 is actually an external interrupt similar to INTO and INTI except that it is based on the ANDed inputs KSI7 0 When any one of the KSI7 0 signa
83. MANUAL signal descriptions 10 2 TMOD 10 1 10 3 10 4 10 6 10 7 11 11 C 5 C 56 TXCNTL 6 16 C 58 TXCON 6 19 C 59 TXD 11 1 mode 0 11 2 modes 1 2 3 11 7 TXDAT 6 16 7 12 C 61 TXFLG 6 21 C 62 TXSTAT 6 9 C 64 U UART 11 1 UD flag 4 2 C 39 UPWEN pin 7 29 USB configuration descriptor 8 3 E 2 device descriptor 8 3 endpoint selection 6 5 endpoint indexed SFRs 6 5 FIFO byte capacity 2 12 function bus unenumeration 8 2 post receive operations 8 11 post transmit operations 8 8 pre transmit operations 8 7 receive done interrupt 5 9 receive operations 8 10 receive routine 8 3 receive SOF routine 8 16 resume interrupt 5 17 setup routines 8 14 suspend and resume 14 1 transmit done interrupt 5 10 transmit operations 8 4 transmit routine 8 3 function endpoint pairs 6 1 function FIFOs 6 1 function interface 6 1 function routines overview 8 1 receive SOF 8 1 setup 8 1 global resume 14 9 global suspend 14 7 hub Index 6 a intel bus enumeration 7 7 CLEAR_FEATURE request 8 17 ClearHubFeature request 8 20 ClearPortFeature request 8 22 8 23 configuration 7 9 7 10 C 6 C 26 descriptors 7 7 7 8 device signals 7 30 embedded function 7 24 remote wake up 7 25 reset 7 24 empedded function suspend and resume 7 26 endpoint 1 7 11 endpoints 7 10 7 13 examining port status 7 17 7 19 C 6 C 24 firmware examples 8 24 firmware response tor USB requests
84. MOV A data Bytes States 6 Cycles 1 Encoding 0111 0100 immed data Operation MOV A data MOV dir8 data Bytes 3 States 12 Cycles 2 Encoding 0111 0101 direct addr immed data Operation MOV dir8 lt data A 35 8x931AA 8x931HA USER S MANUAL MOV Ri data Bytes States 6 Cycles 1 Encoding Operation MOV Ri lt data MOV Rn data Bytes 2 States 6 Cycles Encoding Operation MOV Rn data MOV dir8 dir8 Bytes 3 States 12 Cycles 0111 011i immed data 0111 irrrr immed data 2 Encoding 1000 0101 direct addr direct addr Operation MOV dir8 lt dir8 MOV dir8 Ri Bytes 2 States 12 Cycles 2 Encoding Operation MOV dir8 lt Ri MOV dir8 Rn Bytes 2 States 12 A 36 1000 011i direct addr Cycles 2 Encoding 1000 irrr direct addr Operation MOV dir8 Rn MOV Ri dir8 Bytes 2 States 12 Cycles 2 Encoding 1010 011i direct addr Operation MOV Ri dir8 MOV 8 Bytes 2 States 12 Cycles 2 Encoding 1010 irrr direct addr Operation MOV Rn dir8 MOV 8 Bytes 2 States 6 Cycles 1 Encoding 1110 0101 direct addr Operation MOV A dir8 MOV A Ri Bytes States 6 Cycles 1 Encoding 1110 011i INSTRUCTION SET REFERENCE A 37 8x931AA 8x931HA USER S MANUAL
85. Memory space The AJMP instruction encodes the destination address as an 11 bit constant The instruction is 2 bytes long consisting of the opcode which itself contains 3 of the 11 address bits followed by another byte containing the low 8 bits of the destination address When the instruction is execut ed these 11 bits are simply substituted for the low 11 bits in the PC The high 5 bits stay the same Hence the destination has to be within the same 2K block as the instruction following the AJMP In all cases the programmer specifies the destination address to the assembler in the same way as a label or as a 16 bit constant The assembler will put the destination address into the correct format for the given instruction If the format required by the instruction will not support the dis tance to the specified destination address a Destination out of range message is written into the List file The JMP A DPTR instruction supports case jumps The destination address is computed at ex ecution time as the sum of the 16 bit DPTR register and the Accumulator Typically DPTR is set up with the address of a jump table and the Accumulator is given an index to the table In a 5 way branch for example an integer 0 through 4 is loaded into the Accumulator The code to be executed might be as follows MOV DPTR ZJUMP TABLE MOV A INDEX NUMBER intel PROGRAMMING CONSIDERATIONS RL A JMP A DPTR The RL A instruction converts the index nu
86. Mode Bit 2 Firmware writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 Receiver Enable Bit To enable reception set this bit To disable reception clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 firmware writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 C 47 8x931AA 8x931HA USER S MANUAL intel SCON Continued Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode Select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Function Number Mnemonic unco 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 SM2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 SM2 set Set or cleared by hardware to reflect the ninth data bit received 1 TI Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by firmware 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by firmware C 48 SOFH Start of frame High Register Contains isochronous data transfer enable and interrupt b
87. Modes 1 2 and 3 eene 11 6 Timer 2 in Baud Rate Generator Mode 11 14 KBCON Keyboard Control Register essen 12 1 Keyboard Scan Matrix Application essen 12 3 LED Driver AppliGations 2 cea beet etre radius 12 4 Minimu tri Set p oie ete ree Up De Lett d eb ees trice e 13 1 CHMOS On chip OScillatOr 3 out t tiri ete ERE A oes en ttd 13 3 External Clock Connection for the 8x931 sse 13 4 External Clock Drive Waveforms ssssseeseeeeneenneenen nennen nnn 13 4 Reset Timing Seguente iienaa ieina nennen nennen nennen nennen nennen 13 7 PCON Power Control Register sess 14 3 PCON 1 USB Power Control Register ssesssseeeeeeeneeneeenen 14 4 Suspend Resume Program with without Remote Wake up 14 11 Suspend Resume Program with without Remote Wake up Continueq 14 12 Bus SlI ctule nene nme emet tet ctn 15 1 External Gode Fethi coit ttu a ce tette igs redd 15 3 External Data Read eem E RUE Lee LEG 15 4 External Data Wille b bh iae ei ets 15 4 Bus Diagram for Example 1 8 931 15 6 Bus Diagram for Example 2 8 931
88. RAM as shown in Figure 5 without having to sacrifice all of Port 2 All of these instructions execute in 2 us with a 12 MHz clock 4 10 intel PROGRAMMING CONSIDERATIONS Table 4 6 Transfer Instructions for Accessing External Data Memory Space Address 1 Execution Width Mnemonic Operation Time us Read external 8 bits MOVX A Ri RAM Ri 2 Write external 8 bits MOVX Ri A RAM Ri 2 16 bits MOVXA DPTR Read external 2 DPTR Write external 16 bits MOVX DPTR A RAM DPTR 2 NOTE In all external Data RAM accesses the Accumulator is always either the destination or source of the data The read and write strobes to external RAM are activated only during the execution of aMOVX instruction Normally these signals are inactive and in fact if they re not going to be used at all their pins are available as extra I O lines 4 1 5 3 Lookup Tables Table 4 7 shows the two instructions that are available for lookup tables in Program Memory Since these instructions access only Program Memory the lookup tables can only be read not updated The mnemonic is MOVC for move constant If the table access is to external Program Memory then the read strobe is PSEN Table 4 7 MCS 51 Read Instructions Execution Mnemonic Operation Time us MOVC A A DPTR Read Pgm Memory at A DPTR 2 MOVC A A PC Read Pgm Memory at A PC 2 The first MOVC instruct
89. RXFFRC Unchanged Set RXFFRC Unchanged Set RXFFRC Unchanged Rev WP X Unchanged Unchanged When the receive FIFO is programmed to operate in single packet mode RXSPM set in EPCON valid RXFIF states are 00 and 01 only In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF RXFIF is incremented by the USB and decremented by firmware Therefore setting RXFFRC decrements RXFIF immediately However a successful USB transaction within a frame increments RXFIF only at SOF For traceability you must check the RXFIF flags before and after reads from the receive FIFO and the setting of RXFFRC in RXCON NOTE To simplify firmware development it is recommended that you utilize control endpoints in single packet mode only 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits When set all transmissions are NAKed Figure 6 16 RXFLG Receive FIFO Flag Register 6 31 8x931AA 8x931HA USER S MANUAL intel RXFLG Continued Endpoint indexed Address Reset State E5H 00xx 1000B Receive FIFO Flag Register These flags indicate the status of data packets in the receive FIFO specified by EPINDEX 7 RXFIF1 RXFIFO RXEMP RXFULL RXURF RXOVF Number Bit Mnemonic Function RXEMP Receive F
90. Register Contains the run control bits overflow flags 88H interrupt flags and interrupt type control bits for timer 0 and timer 1 TMOD Timer 0 1 Mode Control Register Contains the mode select bits 89H counter timer select bits and external control gate bits for timer 0 and timer 1 T2CON Timer 2 Control Register Contains the receive clock transmit clock and C8H capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 T2MOD Timer 2 Mode Control Register Contains the timer 2 output enable and C9H down count enable bits RCAP2L Timer 2 Reload Capture Registers RCAP2L RCAP2H Provide values CAH RCAP2H to and receive values from the timer registers TL2 TH2 CBH 10 3 8x931AA 8x931HA USER S MANUAL intel 10 3 TIMER 0 Timer 0 functions as either a timer or event counter in four modes of operation Figures 10 2 10 3 and 10 4 show the logical configuration of each mode Timer 0 is controlled by the four low order bits of the TMOD register Figure 10 5 and bits 5 4 1 and 0 of the TCON register Figure 10 6 The TMOD register selects the method of timer gating GATEO timer or counter operation and mode of operation M10 and M00 The TCON register provides timer 0 control functions overflow flag run control TRO inter rupt flag IEO and interrupt type control TTO For no
91. SOF NOTE For normal operation set the ATM bit in TXCON Hardware will automatically control the read pointer and read marker and track the TXFIF bits NOTE To send a status stage after a control write or no data control command or a null packet write 0 to TXCNTL 6 18 TXCON 7 Endpoint indexed USB FUNCTION Address Reset State F4H 0100B USB Transmit FIFO Control Register Controls the transmit FIFO specified by EPINDEX TXCLR TXISO ATM ADVRM REVRP Bit Number Bit Mnemonic Function TXCLR Transmit Clear Setting this bit flushes the transmit FIFO resets all the read write pointers and markers sets the EMPTY bit in TXFLG and clears all other bits in TXFLG After the flush hardware clears this bit Setting this bit does not affect the ATM TXISO and FFSZ bits or the TXSEQ bit in the TXSTAT register 6 4 Reserved Values read from this bit are indeterminate Write zeros to these bits Transmit Isochronous Data Firmware sets this bit to indicate that the transmit FIFO contains isochronous data The FIU uses this bit to set up the handshake protocol at the end of a transmission This bit is not reset when TXCLR is set and must be cleared by firmware Automatic Transmit Management Setting this bit the default value causes the read pointer and read marker to be adjusted automatically as indicated TXISO TX Status Read P
92. The interrupt status is shown in the HIFLG register regardless of the state of the corresponding interrupt enable bit in the HIE register Figure 5 7 8x931AA 8x931HA USER S MANUAL intel NOTE For the 8x931HA the hub interrupt shares an interrupt vector with the SOF interrupt When this interrupt is triggered firmware must examine the HIFLG SFR to determine that it was the hub interrupt that was triggered and not the SOF interrupt HIFLG Hub Interrupt Flag Register Address Reset State E8H Xxxx xx00B Contains the hub s transmit and receive done interrupt flags for hub NOTES 1 Note that because the HIFLG appears in the first SFR column it is a bit addressable SFR All bits are set in hardware and cleared by firmware Firmware can also set these bits for test purposes allowing the interrupt to be generated by firmware 2 For both HRXDO and HTXDO a 1 indicates that an interrupt is actively pending 0 indicates that the interrupt is not active The interrupt status is shown regardless of the state of the corresponding interrupt enable bit in the HIE endpoint 0 7 0 A HRXDO HTXDO Bit Bit Number Mnemonic Function 7 2 Reserved Write zeros to these bits 1 HRXDO Hub Receive Done Endpoint 0 Hardware sets this bit to indicate that there is either 1 valid data waiting to be serviced in the receive data buffer for hub endpoint
93. To minimize noise and waveform distortion follow good board layout techniques Use sufficient decoupling capacitors and transient absorbers to keep noise within acceptable limits Connect 0 1 uF bypass capacitors between V oc AV cc and each Vg pin Place the capacitors close to the device to minimize path lengths Multi layer printed circuit boards with separate and ground planes help minimize noise For additional information on noise reduction see Application Note AP 125 Designing Microcon troller Systems for Electrically Noisy Environments 13 3 CLOCK SOURCES The 8x931 can use an external clock Figure 13 3 an on chip oscillator with crystal or ceramic resonator Figure 13 2 or an on chip phase locked oscillator locked to the external clock or the on chip oscillator as its clock source For USB operating rates see Table 2 3 on page 2 9 13 3 1 On chip Oscillator Crystal This clock source uses an external quartz crystal connected from XTALI1 to XTAL2 as the fre quency determining element Figure 13 2 The crystal operates in its fundamental mode as an inductive reactance in parallel resonance with capacitance external to the crystal Oscillator de sign considerations include crystal specifications operating temperature range and parasitic board capacitance Consult the crystal manufacturer s data sheet for parameter values With high quality components C1 C2 30 pF is adequate for this application Pins XTAL1 an
94. To preserve the secrecy of the encryption key byte se quence the encryption array cannot be verified Program code verification is performed as usual except as each byte of program code is read it is exclusive NORed XNOR with the corresponding key byte from the encryption array If the encryption array is programmed with key bytes the program code is encrypted during verifica tion and can not be used without knowledge of the key byte sequence If the encryption array is not programmed still all 1s the program code is placed on the data bus in its original unencrypt ed form CAUTION If the encryption feature is implemented the portion of the on chip program code memory that does not contain program code should be filled with random byte values other than FFH to prevent the encryption key sequence from being revealed 16 5 CONSIDERATIONS FOR ON CHIP PROGRAM CODE MEMORY On chip nonvolatile code memory is located at the lowest addresses of program memory address space The first instruction following device reset is fetched from OOOOH It is recommended that user program code start at address 0100H Use a jump instruction to 0100H to begin execution of the program For information on address spaces see 8x93 1 Memory on page 2 11 Addresses outside the range of on chip code memory access external memory With EA and both on chip and external code memory implemented you can place program code at the highest on chip memo
95. Transmit FIFOs are writ ten by the CPU and then read by the FIU for transmission on the USB Receive FIFOs are written by the FIU following reception from the host PC then read by the CPU All transmit FIFOs have the same architecture and all receive FIFOs have the same architecture Table 6 1 shows the FIFO size and configuration for the hub and function endpoint pairs 6 1 8x931AA 8x931HA USER S MANUAL intel Table 6 1 Function and Hub FIFO Configurations RXFIFO TXFIFO Endpoint Control Bulk Interrupt Isochronous Dual packet Size Size Hub EPO Yes No No No No 8 bytes 8 bytes Hub EP1 No No Yes No No N A 1 byte Function Yes No No No No 8 bytes 8 bytes EPO Function Yes Yes Yes Yes Yes 16 bytes 16 bytes EP1 Function Yes Yes Yes No No 8 bytes 8 bytes EP2 The USB signals discussed in this chapter are described in Table 6 2 The pinout diagrams for the 8x931 appear in Appendix B Pin Descriptions Table 6 2 Non hub USB Signal Descriptions Signal Alternate Name Type Description Function PLLSEL Phase locked Loop Select For normal operation connect PLLSEL to logic high PLLSEL 0 is used for factory test see Table 2 3 on page 2 9 SOF Start of Frame The SOF pin is asserted for eight states when an SOF token is received Dpo lO USB Port 0 and D are the data plus and data minus lines of differential USB upstream p
96. addition of two BCD bytes Table 4 4 List of MCS 51 Logical Instructions Addressing Modes Operation Times Dir Ind Reg Imm H ANL A byte A AND byte X X 1 ANL lt byte gt A lt byte gt lt byte gt AND A 1 ANL lt byte gt data lt byte gt lt byte gt AND data 2 ORL A lt byte gt A lt byte gt X X 1 ORL lt bvte gt A ORL lt byte gt data byte byte OR A A byte XRL lt byte gt A XJ X X X XXIX x lt lt byte gt lt byte gt OR data A A XOR lt byte gt X byte byte XOR A XRL byte data lt byte gt lt byte gt XOR data CLRA A 00H Accumulator only Accumulator only CPLA A Accumulator only 1 RLA Rotate ACC Left 1 bit Accumulator only 1 RLC A Rotate Left through Carry Accumulator only 1 RRA Rotate ACC Right 1 bit Accumulator only 4 6 Rotate Right through Carry Swap Nibbles in A Accumulator only intel PROGRAMMING CONSIDERATIONS 4 1 4 Logical Instructions Table 4 4 shows the list of MCS 51 logical instructions The instructions that perform Boolean operations AND OR Exclusive OR NOT on bytes perform the operation on a bit by bit basis That is if the Accumulator contains 00110101B and byte contains 01010011B then ANL A byte will leave
97. additional information on the operation of these bits see Appendix D Data Flow Model C 62 intel REGISTERS TXSTAT Continued Address F2H Endpoint indexed Reset State 0xx0 0000B Endpoint Transmit Status Register Contains the current endpoint status of the transmit FIFO specified by EPINDEX 7 0 TXSEQ TXFLUSH TXSOVW TXVOID TXERR TXACK Bit Bit Number Mnemonic Function 1 TXERR Transmit Error read only An error condition has occurred with the transmission Complete or partial data has been transmitted The error can be one of the following 1 Data transmitted successfully but no handshake received 2 Transmit FIFO goes into underrun condition while transmitting The corresponding transmit done bit FTXDx in FIFLG or FIFLG1 8x930Ax with 6EPP is set when active For non isochronous transactions this bit is updated by hardware along with the TXACK bit at the end of the data transmission this bit is mutually exclusive with TXACK For isochronous transactions this bit is not updated until the next SOF 0 TXACK Transmit Acknowledge read only Data transmission completed and acknowledged successfully The corresponding transmit done bit FTXDx FIFLG or FIFLG1 8x930Ax with 6EPP is set when active For non isochronous transactions this bit is updated by hardware along with the TXERR bit at the end of data transmission this bit is mutually ex
98. and is mutually exclusive with RXERR Under normal operation this bit should not be modified by the user For additional information on the operation of these bits see Appendix D Data Flow Model t The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface Figure 6 5 RXSTAT Receive FIFO Status Register Continued 6 13 8x931AA 8x931HA USER S MANUAL intel FADDR Address 8FH Reset State 0000 0000B Function Address Register This SFR holds the address for the USB function During bus enumeration it is written with a unique value assigned by the host 7 0 Function Address Bit Bit Number Mnemonic Function 7 Reserved Write a zero to this bit 6 0 A6 0 7 bit Programmable Function Address This register is programmed through the commands received via endpoint 0 on configuration which should be the only time the firmware should change the value of this register This register is hardware read only Figure 6 6 FADDR Function Address Register 6 3 TRANSMIT FIFOS The 8x931 has a transmit FIFO for each function endpoint pair In this manual the term transmit FIFO refers to the transmit FIFO associated with the current endpoint pair specified by the EPINDEX register 8x931 FIFOs are listed in Table 2 4 The transmit FIFOs are circulating data buffers with the following features e
99. and the function address register FADDR contain the default value 00H The host PC performs bus enumeration at system start up or whenever a new USB device is attached to the host or to a hub s downstream port During bus enumeration the host identifies and addresses devices attached to the bus During enumeration a unique address assigned by the host is written to HADDR and FADDR NOTE Since the 8x931A A microcontroller does not support a hub interface and hence has no HADDR SFR or downstream ports its enumeration process is simpler The 8x931AA enumeration process is given in Appendix E 8x931AA Enumeration Process on page E 2 An example enumeration for the hub and downstream ports is given here 1 Get device descriptor The host requests and reads the device descriptor to determine maximum packet size 2 Set address The host sends the 8x931HA s hub address in a data packet using hub endpoint 0 Device firmware interprets the data and instructs the CPU to write the hub address to HADDR See The Hub Address Register HADDR on page 7 8 3 Get device descriptor The host requests and reads the device descriptor to determine such information as device class USB specification compliance level maximum packet size for endpoint 0 vendor id product id etc For additional information on the 8x931HA descriptors see Hub Descriptors on page 7 7 4 Get configuration descriptor The host requests and reads the device s c
100. as the number of interfaces and endpoints endpoint transfer type packet size and direction power source maximum power etc For detailed information on configuration descriptors see the Device Framework chapter in Universal Serial Bus Specification When the host requests the configuration descriptor all related interface and endpoint descriptors are returned d Set configuration The host assigns a configuration value to the device to establish the current configuration Devices can have multiple configurations 11 The external ports must go through steps 8 through 10 8 1 2 Idle State Following bus enumeration the USB function enters the idle state In this state the 8x931 exe cutes application code associated with the embedded function Upon receipt of a token with the assigned address the module enters the designated routine The 8x931 remains in the idle state when not processing USB transmissions 8 1 3 Transmit and Receive Routines When the 8x931 is sending and receiving packets in the transmit and receive modes its operation depends on the type of data that is transferred isochronous or non isochronous and the adjust ment of the FIFO markers and pointers automatic or manual These differences affect both the 8x931 firmware and the operation of the 8x931 hardware For isochronous data a failed transfer is not retried lossy data For non isochronous data a failed transfer can be repeated Data that 8 3
101. assemble as accumulator specific opcodes 4 1 2 5 IMMEDIATE CONSTANTS The value of a constant can follow the opcode in Program Memory For example MOV A 100 loads the Accumulator with the decimal number 100 The same number could be specified in hex digits as 64H 4 1 2 6 INDEXED ADDRESSING Only Program Memory can be accessed with indexed addressing and it can only be read This addressing mode is intended for reading look up tables in Program Memory A 16 bit base reg ister either DPTR or the Program Counter points to the base of the table and the Accumulator is setup with the table entry number The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer Another type of indexed addressing is used in the case jump instruction In this case the desti nation address of a jump instruction is computed as the sum of the base pointer and the Accumu lator data Table 4 2 Addressing Modes for Data Instructions in the MCS 51 Architecture Address Range of Assembly Language Mode Operand Reference comments RO R7 Register DOHESTEH Bank selected by PSW Immediate Operand in Instruction data OOH FFH 00H 7FH dir8 00H 7FH On chip RAM Direct dir8 80H FFH vere or SFR mnemonic SFR adoress Accesses on chip RAM or the 00H FFH ORO R1 lowest 256 bytes of external data memory MOVX Indirect 0000H FFFFH DPTR A DPTR Accesses external data
102. auto reload mode A rollover in the TH2 register reloads registers TH2 and TL2 with the 16 bit value in registers RCAP2H and RCAP2L which are preset by firmware The timer 2 baud rate is expressed by the following formula Timer 2 Overflow Rate Serial I O Modes 1 and 3 Baud Rate 16 11 6 3 4 Selecting Timer 2 as the Baud Rate Generator To select timer 2 as the baud rate generator for the transmitter and or receiver program the RCLCK and TCLCK bits in the T2CON register as shown in Table 11 5 You may select differ ent baud rates for the transmitter and receiver Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode Figure 11 5 In this mode a rollover in the TH2 register does not set the TF2 bit in the T2CON register Also a high to low transition at the T2EX pin sets the EXF2 bit in the T2CON register but does not cause a reload from RCAP2H RCAP2L to TH2 TL2 Youcan use the T2EX pin as an additional external interrupt by setting the EXEN2 bitin T2CON NOTE Turn the timer off clear the TR2 bit in the T2CON register before accessing registers TH2 TL2 RCAP2H and RCAP2L You may configure timer 2 as a timer or a counter In most applications it is configured for timer operation i e the C T2 bit is clear in the T2CON register 11 12 intel SERIAL I O PORT Table 11 5 Selecting the Baud Rate Generator s RCLCK TCLCK Receiver Transmitter Bit Bit Baud Rate Generator Baud Rat
103. by firmware Reverse write pointer Received OUT 11 1 0 None None Only OVF FIFO token FIFO Time out error can occur error occurs requires firmware intervention Received OUT 01 10 no no None None Treated like a token with chg chg Time out void condition FIFO error already existing NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 RXFIF RXOVF and RXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF RXURF Since underrun can only be caused by firmware RXURF is updated immediately RXOVF Since overrun can only be caused by USB RXOVF is updated at SOF RXFIF RXFIF is incremented by USB and decremented by firmware Therefore setting RXFFRC will decrement RXFIF immediately However a successful USB transaction anytime in a frame will only increment RXFIF at SOF RXERR RXACK and RXVOID can only be caused by USB thus they are updated at the end of transaction 8x931AA 8x931HA USER S MANUAL intel Table D 5 Isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued RXFIF Pae ove URF inte USB c t 1 0 vent 1 0 RX RX RX aa aa Response omments 2 ERR ACK Void 12 2 rup CPU reads 00 no no no no no None None
104. by firmware when serving the USB reset interrupt 2 RWU Remote Wake up Bit 1 wake up This bit is used by the USB function to initiate a remote wake up Set by firmware to drive resume signaling on the USB lines to the host or upstream hub Cleared by hardware when resume signaling is done NOTE Do not set this bit unless the USB function is suspended GSUS 1 and GRSM 0 See Figure 14 2 on page 14 4 Firmware should prioritize GRSM over GSUS if both bits are set simultaneously C 35 8x931AA 8x931HA USER S MANUAL intel PCON1 Continued Address DFH Reset State x000B USB Power Control Register Facilitates the control and status relating to global suspend and resume USB reset separation and remote wake up of the 8x931 7 0 URDIS URST RWU GRSM GSUS 1 GRSM Global Resume Bit 1 resume Set by hardware when a global resume is detected on the USB lines This bit is ORed with GSUS to generate the interrupt Cleared by firmware when servicing the global suspend resume interrupt This bit can also be set cleared by firmware for testability This bit is not set if remote wakeup is used see RWU See Figure 14 2 on page 14 4 0 GSUS Global Suspend Bit 1 suspend This bit is set by hardware when global suspend is detected on the USB lines This bit is ORed with the GRSM bit to generate the interrupt During the global suspend ISR firm
105. by writing to a ports HPSC SFR Setting any bit in port x s HPSC results in the hardware setting bit xin TXDAT TXDAT bits can be cleared indirectly in firmware by clearing all bits in that port s HPSC C 59 8x931AA 8x931HA USER S MANUAL TXFLG Endpoint indexed Address Reset State F5H 00xx 1000B Transmit FIFO Flag Register These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX 7 TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF Bit Number Bit Mnemonic 7 6 TXFIF1 0 Function FIFO Index Flags read only These flags indicate which data sets are present in the transmit FIFO The FIF bits are set in sequence after each write to TXCNT to reflect the addition of a data set Likewise TXFIF1 and TXFIFO are cleared in sequence after each advance of the read marker to indicate that the set is effectively discarded The bit is cleared whether the read marker is advanced by firmware setting ADVRM or automatically by hardware ATM 1 The next state table for the TXFIF bits is shown below TXFIF1 0 Operation Wr TXCNT Wr TXCNT Flag Next TXFIF1 0 Next Flag Unchanged Unchanged Wr TXCNT Wr TXCNT Adv RM Adv RM Adv RM Unchanged TXOVF 1 Unchanged Unchanged Unchanged Adv RM Unchanged Rev RP X Unchanged In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change imm
106. byte X X X X 1 ADDOA lt byte gt A A lt byte gt C 1 SUBB A lt byte gt A A lt byte gt C 1 INCA A A 1 Accumulator only 1 INC lt byte gt lt byte gt lt byte gt 1 X X X 1 INC DPTR DPTR DPTR 1 Data Pointer only 2 DEC A 1 Accumulator only 1 DEC lt byte gt byte byte 1 X X X 1 MUL AB B A Bx A ACC and B only 4 DIV AB A Int A B B MOd A B ACC and B only 4 DA A Decimal Adjust Accumulator only 1 4 5 8x931AA 8x931HA USER S MANUAL intel The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8 bit quotient in the Accumulator and the 8 bit remainder in the B register Oddly enough DIV AB finds less use in arithmetic divide routines than in radix conversions and programmable shift operations An example of the use of DIV AB in a radix conversion will be given later In shift operations dividing a number by 2 shifts its n bits to the right Using DIV AS to perform the division completes the shift in 4 us and leaves the B register holding the bits that were shifted out The DA A instruction is for BCD arithmetic operations In BCD arithmetic ADD and ADDC in structions should always be followed by a DA A operation to ensure that the result is also in BCD NOTE DA A will not convert a binary number to BCD The DA A operation produces a meaningful result only as the second step in the
107. can use a baud rate of 1 32 or 1 64 of the oscillator frequency In mode 3 you can use the over flow from timer 1 or timer 2 to determine the baud rate In its asynchronous modes modes 1 3 the serial port can operate as a slave in an environment where multiple slaves share a single serial line It can accept a message intended for itself or a message that is being broadcast to all of the slaves and it can ignore a message sent to another slave 2 6 OPERATING CONDITIONS The 8x931 is designed for a commercial operating environment and to accommodate the operat ing rates of the USB interface For detailed specifications refer to the current 8 931 8 931 Universal Serial Bus Peripheral Controller datasheet order number 273108 001 For USB module operating rates see Clock and Reset Unit on page 2 7 2 14 intel Address Spaces intel CHAPTER 3 ADDRESS SPACES 3 4 MEMORY ORGANIZATION IN 8x931 DEVICES 3 1 1 Logical Separation of Program and Data Memory 8x931 devices have separate address spaces for Program and Data Memory as shown in Figure 3 2 The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8 bit addresses which can be more quickly stored and manipulated by an 8 bit CPU Never theless 16 bit Data Memory addresses can also be generated through the DPTR register Program Memory can only be read not written to There can be up to 64K bytes of Program Memory In t
108. clock is running When a reset is detected the CPU responds by triggering the internal reset routine The reset rou tine loads the SFRs including the ACC B stack pointer and data pointer registers with their reset values see Table C 1 on page C 2 Reset does not affect on chip data RAM or the register file However following a cold start reset these are indeterminate because V has fallen too low or has been off Following a synchronizing operation the CPU vectors to address 0000 Fig ure 13 5 shows the reset timing sequence While the RST pin is high ALE PSEN and the port pins are weakly pulled high After RST is pulled low it will take 1 to 2 machine cycles for ALE and PSEN to start clocking For this rea son other devices can not be synchronized to the internal timings of the 8x931 13 6 intel MINIMUM HARDWARE SETUP NOTE Externally driving the ALE and or PSEN pins to 0 during the reset routine may cause the device to go into an indeterminate state Powering up the 8x931 without a reset may improperly initialize the program counter and SFRs and cause the CPU to execute instructions from an undetermined memory location 13 4 4 Power on Reset To automatically generate a reset when power is applied connect the RST pin to the Voc pin through a 0 3 uF capacitor as shown in Figure 13 1 on page 13 1 When Vec is applied the RST pin rises to Vec then decays exponentially as the capacitor charg es The time consta
109. control endpoints for non setup tokens However the response of a control endpoint is different when it receives a setup token USB protocol specifies that setup tokens must be received and ACKed Following receipt of a setup token a control endpoint flushes the contents of the receive FIFO before writing it with re ceived setup data This may create an error condition in the FIFO due to the asynchronous nature of FIFO reads by the CPU and simultaneous writes by the function interface To prevent this STOVW and EDOVW are used to track when an overwrite is occurring When the overwrite is complete the user must clear EDOVW to read the SETUP packet If EDOVW is not cleared user firmware will only be able to read the first byte of the SETUP packet Figure 8 9 illustrates the operations of a typical post receive routine for a control endpoint intel USB PROGRAMMING MODELS Start Receive Done ISR Identify Interrupt Endpoint check FRXDx bits in the FIFLG register Clear Interrupt Flag Yes RXSETUP 1 Setup Token Received Clear EDOVW Read Data Packet OUT Token Received STOVW 0 and EDOVW 0 Receive FIFO Overwrite Yes STOVW 1 or EDOVW 1 Error in Yes RXURF 1 Receive FIFO Overwrite Completed Unlock Current Packet from Receive FIFO set RXFFRC bit in RXCON Yes STOVW 0 and EDOVW 1 Error Recovery STOVW 0 a
110. current port state If the port is in a state where the request will be ignored by hardware instead of performing the action given in Table 8 2 firmware must respond to the host by sending a STALL during the transaction status stage to indicate the command was not completed Table 7 6 on page 7 16 depicts the state related USB requests and the port states for which they are ignored See Controlling a Port Using HPCON on page 7 14 for additional information 8 19 8x931AA 8x931HA USER S MANUAL intel Table 8 2 Firmware Action for Hub Class Specific Requests USB Requests Feature Selector Type Index Firmware Action Required SetHubFeature Unsupported request since there are no current feature selectors to match this request in the initial version of USB 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage ClearHubFeature C_HUB_OVER_ Clear HSTAT SFR bit OVISC hub over current status change CURRENT bit HSTAT is shown in Figure 7 6 on page 7 9 Unsupported request C LOCAL 1 Load 80H into EPINDEX for hub endpoint 0 POWER 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage GetBusState Port number Transfer the port bus signal values D and D to the host for diagnostic purposes 1 Load xxxB into HPINDEX2 0 where xxx is the binary representation of the port index 2 Transfer the DPSTAT and DMSTA
111. data pointer DPTR Instructions in the MCL 51 architecture use DPTR for data moves code moves and for a jump instruction JMP A DPTR See also DPL 7 0 DPH Contents Bit Bit Function Number Mnemonic 7 0 DPH 7 0 Data Pointer High Bits 8 15 of the data pointer DPL Address 82H Reset State 0000 0000B Data Pointer Low DPL is the low byte of the 16 bit data pointer DPTR Instructions in the MCS 51 architecture use the 16 bit data pointer for data moves code moves and for a jump instruction JMP A DPTR See also DPH 7 0 DPL Contents Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Low Bits 0 7 of the data pointer C 7 8x931AA 8x931HA USER S MANUAL intel EPCON Endpoint indexed Address E1H Reset State Endpoint 0 0011 0101B Function Endpoints 1 2 0001 0000B Endpoint Control Register This SFR configures the operation of the endpoint specified by EPINDEX 7 0 RXSTL TXSTL CTLEP RXSPM RXIE RXEPEN TXOE TXEPEN Bit Number Bit Mnemonic Function 7 RXSTL Stall Receive Endpoint Set this bit to stall the receive endpoint Clear this bit only when the host has intervened through commands sent down endpoint 0 When this bit is set and RXSETUP is clear the receive endpoint will respond with a STALL handshake to a valid OUT token When this bit is set and RXSETUP is set the receive endpoi
112. equal to 01H it returns with 77H in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead Variations MOVC A A PC Bytes 1 States 12 A 40 INSTRUCTION SET REFERENCE Cycles 2 Encoding 1000 0011 Operation MOVC PC PC 1 lt A PC MOVC A A DPTR Bytes 1 States 12 Cycles 2 Encoding 1001 0011 Operation MOVC lt A DPTR MOVX lt dest gt lt srce gt Function Description Flags Example Move external Transfers data between the accumulator and a byte in external data RAM There are two types of instructions One provides an 8 bit indirect address to external data RAM the second provides a 16 bit indirect address to external data RAM In the first type of MOVX instruction the contents of RO or R1 in the current register bank provides an 8 bit address on port 0 Eight bits are sufficient for external I O expansion decoding or for a relatively small RAM array For larger arrays any port pins can be used to output higher address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the data pointer generates a 16 bit address Port 2 outputs the upper eight address bits from DPH while port 0 output
113. executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine The hardware generated LCALL pushes the con tents of the Program Counter onto the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being vectored to Execution proceeds from that location until the RETI instruction is encountered The RETI in struction informs the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted pro gram continues from where it left off Note that a simple RET instruction would also have returned execution to the interrupted pro gram but it would have left the interrupt control system thinking interrupt was still in progress Note that the starting addresses of consecutive interrupt service routines are only 8 bytes apart That means if consecutive interrupts are being used and for example and and if the first interrupt routine is more than 7 bytes long then that routine will have to ex ecute a jump to some other memory location where the service routine can be completed without overlapping the starting address of the next interrupt routine 0 4 X n eM Interrupts are Long call to interrupt Interrupt Interrupt latched polled vector address routine In
114. from 0 to 5 Volts POF can also be set or cleared by software This allows the user to distinguish between a cold start reset and a warm start reset A cold start reset is one that is coincident with the Vcc being turned on to the device after it was turned off A warm start reset occurs while V is still applied to the device and could be gener ated for example by an exit from Power Down 14 1 8x931AA 8x931HA USER S MANUAL intel Immediately after reset the user s software can check the status of the POF bit POF 1 would indicate a cold start The software then clears POF and commences its tasks POF 0 immediate ly after reset would indicate a warm start NOTE must remain above 3 volts for POF to retain a 0 14 2 PCON SPECIAL OPERATING MODES Address 87H Reset State 001X 0000B Power Control Register Contains the power off flag POF and bits for enabling the idle and powerdown modes and two general purpose flags 7 0 SMOD1 SMODO LC POF GF1 GFO PD IDL Bit Bit Number Mnemonic Function 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 11 10 6 SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 are to the SMO bit See the SCON register Figure 11 2 on page 11 4 5 Low clock Mode Enable
115. given SFR are retained when other endpoints are selected Only SFRs necessary for device operation are implemented For example since hub endpoint 1 is transmit only RXDAT for that endpoint is not implemented 6 1 4 Endpoint Selection The most significant bit of the endpoint index register EPINDEX Figure 6 2 selects hub or function The low order bits EPINX 1 0 indicate the endpoint and serve as an index value for se lecting the SFR bank To specify the endpoint pair write a value of the form Zxxx xYY YB or Zxxx xxYYB to EPINDEX where Z specifies hub or function and Y Y Y and Y Y specify the end point number It is recommended that programmers set the contents of EPINDEX once at the start of each rou tine instead of writing the EPINDEX register prior to each access of an endpoint indexed SFR This means that interrupt service routines must save the contents of the EPINDEX register at the start of the routine and restore the contents at the end of the routine to prevent the EPINDEX reg ister from being corrupted 6 5 8x931AA 8x931HA USER S MANUAL EPINDEX Endpoint Index Register This register identifies the endpoint pair Its contents select the transmit and Address receive FIFO pair and serve as an index to endpoint specific SFRs F1H Reset State 1 xx00B 7 0 HORF EPINX1 EPINXO Bit Bit Number Mnemonic Function 7 HORF Hub Function Bit 1 Hub Sel
116. has been executed the Accumulator contains the two digits that were shifted out on the right Doing the routine with direct MOVs uses 14 code bytes and 9 us of execution time assuming a 12 MHz clock The same operation with XCHs uses less code and executes almost twice as fast To right shift by an odd number of digits a one digit shift must be executed Figure 4 3 shows a sample of code that will right shift a BCD number one digit using the XCHD instruction Again the contents of the registers holding the number and of the Accumulator are shown alongside each instruction MOV MOV MOV MOV MOV a Using direct MOVs CLR XCH XCH XCH XCH b Using XCHs 9 bytes 5 us A 2EH 2EH 2DH 2DH 2CH 2CH 2BH 2BH 0 A A 2BH A 2CH A 2DH A 2EH 2A 2B 00 12 00 12 00 12 00 12 00 00 14 bytes 9 us 2A 2B 00 12 00 00 00 00 00 00 00 00 2 34 34 34 12 12 2 34 34 12 12 12 2D 56 56 34 34 34 2D 56 56 56 34 34 2E 78 56 56 56 56 2E 78 78 78 78 56 ACC 78 78 78 78 78 ACC 00 12 34 56 78 Figure 4 2 Shifting BCD Number Two Digits Right 4 9 8x931AA 8x931HA USER S MANUAL intel 2 2B 2 2D 2E ACC MOV R1 2EH 00 12 34 56 78 XX MOV RO 2DH 00 12 34 56 78 XX loop for R1 2EH LOOP MOV A R1 00 12 34 56 78 78 XCHD A RO 00 12 34 58 78 76 SWAP A 00 12 34 58 78 67 MOV R1 A 00 12 34 58 67 67 DEC R1 00 12 34 5
117. host command detect a device connection and then become enabled via host command pri or to propagating USB packet traffic Hub port 1 is an internal downstream port that is always powered on and always physically connected It functionally supports port enabling That is the downstream port connectivity will not be enabled unless a port enable has been received from the host 7 5 8x931AA 8x931HA USER S MANUAL intel 7 1 2 Per packet Signaling Connectivity The hub repeater establishes connectivity between ports for upstream and downstream traffic on a per packet basis Packet signaling connectivity for downstream upstream and idle traffic is il lustrated in Figure 7 4 While the host can communicate with all the downstream ports simulta neously as shown in the downstream connectivity illustration in Figure 7 4 only one port can communicate with the host at one time as shown in the Upstream Connectivity illustration of the same figure The host selects one of the downstream ports for upstream communication Root Port Root Port Root Port Port 1 Internal Port 1 Internal Port 1 Internal Disabled Disabled Disabled Port 2 Port3 Port 4 Port 5 Port2 Port3 Port4 Port 5 Port 2 Port3 Port4 Port 5 Downstream Upstream Idle Connectivity Connectivity A5258 01 Figure 7 4 Packet Signaling Connectivity Connections made by the repeater also depend on whether the port is attached to a full s
118. in an n type material The mode in which a device or component recognizes a falling edge high to low transition a rising edge low to high transition or a rising or falling edge of an input signal as the assertion of that signal See also level triggered An array of key bytes used to encrypt user code as it is read from code memory protects against unauthorized access to user s code A uniquely identifiable portion of a USB device that is the source or sink of information in a commun ication flow between the host and the device Endpoint pair See endpoint A 16 bit address presented on the device pins The address decoded by an external device depends on how many of these address bits the external system uses See also internal address Fox FET FIFO FIU Fosc frame function handshake packet HIU host hub idle mode input leakage integer internal address interrupt handler interrupt latency interrupt response time GLOSSARY Microcontroller internal clock frequency distributed to the CPU and on chip peripherals Field effect transistor First in first out data buffer Each USB endpoint pair has a transmit FIFO and a receive FIFO Function Interface Unit Its function is to manage the data transaction that goes between the 8x931 and the USB host based on the transfer type and the FIFOs condition Frequency at pin XTAL1 The frequency of the on chip oscillator or external sourc
119. interrupt bits SOFH Start of Frame High Register Contains isochronous data D3H page 5 12 transfer enable and interrupt bits and the upper three bits of the 11 bit time stamp received from the host SOFL Start of Frame Low Register Contains the lower eight bits of D2H page 5 13 the 11 bit time stamp received from the host NOTE Other SFRs are described in their respective chapters and in Appendix C Registers 5 4 INTERRUPT SYSTEM 7 0 FIE FRXIE2 FTXIE2 FRXIE1 FTXIE1 FRXIEO FTXIEO FIFLG FRXD2 FTXD2 FRXD1 FTXD1 FRXDO FTXDO HIE um m E HRXEO HTXEO HIFLG v HRXDO HTXDO IENO EA ET2 ES 1 EE IEN1 EX2 E ESOF IPLO IPLO5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O IPHO IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 IPHO O IPL1 IPL1 7 IPL1 2 IP IPL1 0 IPH1 IPH1 7 Es IPH1 2 IPH1 1 IPH1 0 KBCON IE2 KSEN IT LED3 LED2 LED1 LEDO PCON1 URDIS URST RWU GRSM Gsus SOFH sorAcK ASOF SOFIE FTLOCK SOFODIS TS10 TS9 TS8 SOFL TS7 0 Figure 5 2 Bits of the Interrupt SFRs Many 8x931 interrupts are similar to the interrupts of other MCS 51 microprocessors These in terrupts are shown in Table 5 4 Particulars of the USB and hub interrupts are given in Table 5 6 5 2 INTERRUPT SOURCES
120. is functionally identical to RET Table 4 10 shows the list of conditional jumps available to the MCS 51 user All of these jumps specify the destination address by the relative offset method and so are limited to a jump distance of 128 to 127 bytes from the instruction following the conditional jump instruction Important to note however the user specifies to the assembler the actual destination address the same way as the other jumps as a label or a 16 bit constant 4 15 8x931AA 8x931HA USER S MANUAL intel Table 4 10 Conditional Jumps in MCS 51 Devices Mnemonic Operation TE SG e Dir Ind Reg Imm JZ rel Jump if A 0 Accumulator only 2 JNZ rel Jump if A not equal to 0 Accumulator only 2 DJNZ bytes rel Decrement and jump if not zero X X 2 CJNE A byte rel Jump if A not equal to byte X X 2 CJNE byte data rel Jump if byte not equal to data X X 2 There is no Zero bit in the PSW The JZ and JNZ instructions test the Accumulator data for that condition The DJNZ instruction Decrement and Jump if Not Zero is for loop control To execute a loop N times load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop as shown below for N 10 MOV COUNTER 10 LOOP begin loop end loop DJNZ COUNTER LOOP continue The CJNE instruction Compare and Jump if Not Equal can also be used for loop c
121. its downstream ports These USB requests are listed and explained in Hub Status and Configuration on page 8 17 The hub has an internal downstream port port 1 which operates differently than the external downstream ports Because this port is physically connected to the embedded function and is powered on at all times USB requests intended for the internal downstream port are handled dif ferently than similar requests to the other downstream ports The management of the individual hub ports is discussed in USB Hub Ports on page 7 14 The host PC may request that firmware check and change bits of the HSTAT SFR Figure 7 6 See Table 8 1 on page 8 17 for a list of USB requests and their associated firmware actions HSTAT Address AEH Reset State 0000 0000B Hub Status and Configuration Register This SFR contains bits for remote wake up request status and status change indicators for over current and hub endpoint 1 stall and enable 7 0 OVRIEN HRWUPE EP1STL EP1EN OVISC OVI Bit Bit Number Mnemonic Function 7 OVRIEN Overcurrent Detect Enable Bit This bit is used to gate off the overcurrent input detect which is multiplexed with P3 0 When set a low on P3 0 OVRI pin will trigger over current detection logic When this bit is 0 the over current detection logic is disabled 6 HRWUPE Hub Remote Wake up Enable Bit Set if the device is currently enabled to request remote w
122. memory MOVX Accesses code memory 0000H FFFFH A DPTR A PC MOVC 4 4 intel 4 1 3 Arithmetic Instructions PROGRAMMING CONSIDERATIONS The menu of arithmetic instructions is listed in Table 4 3 The table indicates the addressing modes that can be used with each instruction to access the lt byte gt operand For example the ADD A lt byte gt instruction can be written as ADD A 7FH direct addressing ADD A RO indirect addressing ADD A R7 register addressing ADD A 127 Gmmediate constant The execution times listed in Table 4 3 assume a 12 MHz clock frequency All of the arithmetic instructions execute in lus except the INC DPTR instruction which takes 2 us and the Multiply and Divide instructions which take 4 us NOTE Any byte in the internal Data Memory space can be incremented or decremented without going through the Accumulator One of the INC instructions operates on the 16 bit Data Pointer The Data Pointer is used to gen erate 16 bit addresses for external memory so being able to increment it in one 16 bit operation is a useful feature The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16 bit product into the concatenated B and Accumulator registers Table 4 3 List of MCS 51 Arithmetic Instructions Mnemonic Operation ae Ge Dir Ind Reg Imm ADD A lt byte gt
123. modes 1 2 and 3 P1 1 P1 7 UPWEN USB Power Enable A low signal on this pin applies power to the external downstream ports PWR PWR Supply Voltage Connect this pin to the 5V supply voltage Supply Voltage for I O buffers Connect this pin to the 5V supply voltage GND Circuit Ground Connect this pin to ground GND Circuit Ground for I O buffers Connect this pin to ground Write Write signal output to external memory P3 6 KSO19 Oscillator Amplifier Input When implementing the on chip oscillator connect the external crystal or ceramic resonator across XTAL1 and XTAL2 If an external clock source is used connect it to this pin XTAL2 Oscillator Amplifier Output When implementing the on chip oscillator connect the external crystal or ceramic resonator across XTAL1 and XTAL2 If an external oscillator is used leave XTAL2 unconnected intel Registers APPENDIX C REGISTERS This appendix contains reference information regarding the 8x931 special function registers SFRs The SFR memory map in Table C 1 gives the address of each SFR and its contents fol lowing chip reset An x indicates the bit value following chip reset is indeterminate Blank locations in Table C 1 are not implemented i e no register exists If an instruction at tempts to write to an unimplemented SFR location the instruction executes but nothing is actu ally written If a
124. monitoring the HPSC register Figure 7 11 NOTE Firmware initiated port status changes are not reflected in HPSC until the next end of frame The 8x931HA uses the 1 byte TXDAT register associated with endpoint 1 to communicate a port status change to the host Figure 7 7 on page 7 12 Bits in this register are set by the 8x931HA hardware to indicate which ports or the hub itself have changed status After receiving notification of a port status change through endpoint 1 the host may request ad ditional information regarding the status change using a GetPortStatus request 8x931HA firm ware must respond to the GetPortStatus request by transmitting the contents of the HPSTAT and HPSC registers to the host in a two word format This process is described in GetPortStatus Re quest Firmware on page 8 25 The HPSC register Figure 7 11 indicates which port feature has changed status Port features whose status changes are reflected by HPSC include reset suspend enable and connect 7 20 USB HUB HPSC Indexed by HPINDEX Address Reset State D5H xxx0 0000B Hub Port Status Change Register This register indicates a change in status for a port including over current reset suspend low speed device enable and connect status 7 RSTSC E PSSC PESC PCSC Bit Number Bit Mnemonic Function Reserved Write zeros to these bits Reset Status Change read clear only This
125. must play a dual role The ISR must first check PCON1 s URST bit to ensure that this interrupt is indeed a USB reset interrupt If URST 0 then this interrupt must be a global suspend resume interrupt and the ISR must branch to service that type of interrupt See USB Global Suspend Resume Interrupt on page 5 17 for a description of this portion of the ISR If the URST bit is set to 1 then this interrupt is a USB reset interrupt The ISR must perform the following procedure See Figure 5 9 1 Clear PCON1 s URST bit to indicate that the USB reset interrupt has been serviced 2 Set the user flag USB RST FLG that was cleared as part of your initialization routine This flag is discussed in Initialization Required for USB Reset on page 5 18 Setting this flag is necessary to inform your firmware routines that a USB reset has occurred and that USB initialization must be performed 3 Bus powered devices must set the LC bit of PCON Figure 14 1 on page 14 3 in order to operate at 3 MHz This ensures that the device meets the Universal Serial Bus Specification s 100 mA current limit during enumeration 4 Restore any register values and return from interrupt The rest of the USB reset procedure will be initiated by a USB initialization routine that can be called from the main routine subroutines or other ISRs 5 21 8x931AA 8x931HA USER S MANUAL intel 5 2 9 4 Main Routine Considerations Althoug
126. next FIFO location to be read by the 8x931 The read pointer increments by one automati cally following a read FIU Writes to FIFO Write Pointer From USB Interface Data Set 1 Read Pointer 1 Write Marker CPU Reads FIFO Data Set 0 Byte Count Register RXCNTL A5306 01 Figure 6 12 Receive FIFO When a good reception is completed the write marker can be advanced to the position of the write pointer to set up for writing the next data set When a bad reception is completed the write pointer When operating in dual packet mode the maximum packet size should be at most half the FIFO size to ensure that both packets will simultaneously fit in the FIFO see the Endpoint description in the Universal Serial Bus Specification 6 24 intel USB FUNCTION can be reversed to the position of the write marker to enable the FIU to rewrite the last data set after receiving the data again The write marker advance and write pointer reversal can be accom plished two ways explicitly by firmware or automatically by hardware as specified by bits in the receive FIFO control register The 8x931 should not read data from the receive FIFO before all bytes are received and success fully acknowledged because the reception may be bad The FIU can monitor the FIFO full flag RXFULL bit in RXFLG to avoid overwriting data in the receive FIFO In the single packet mode 8x931 can monitor the FIF
127. no no no no no 1 None Time out Firmware FIFO chg chg chg chg chg NAK should check causes FIFO future RXUREF bit error transactio before writing RXFFRC not ns RXFFRC set yet CPU reads 00 no no no no no 1 None Time out Firmware FIFO chg chg chg chg chg NAK should check causes FIFO future RXUREF bit error Set transactio before writing RXFFRC ns RXFFRC NOTE 1 These are sticky bits which must be cleared by enabled 2 STOVW is set after a valid SETUP token is rece handshake phase firmware Also this table assumes RXEPEN and ARM are ived and cleared during handshake phase EDOVW is set during Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 New RX RX RX FIF RX RX RX RX USB Event FIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void Setup 1 1 rupt Response 00 Received 00 no no 1 no no no None NAK FIFO not ready OUT token chg chg chg chg chg but RXIE 0 Received 00 no no 1 no no no None None FIFO not loaded OUT token chg chg chg chg chg Write pointer but timed out reversed waiting for data Received 01 0 1 0 0 no no Set ACK Received no OUT token chg chg receive errors advance no errors interrupt write marker NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is re
128. of code space since register instructions are shorter than instructions that use direct addressing I Accessible Accessible Upper by indirect by direct 128 Micra addressing only 80H 80H Accessible Ports Lower by direct Status and control bits 128 and indirect Special Timer addressing function Registers registers Stack pointers accumulator etc A 4477 01 Figure 3 3 Internal Data Memory The next 16 bytes above the register banks form a block of bit addressable memory space The MCS 51 instruction set includes a wide selection of single bit instructions and the 128 bits in this area can be directly addressed by these instructions The bit addresses in this area are 00H through 7FH All of the bytes in the Lower 128 can be accessed by either direct or indirect ad dressing The Upper 128 can only be accessed by indirect addressing No bit addressable spaces Available as stack space in devices with 256 bytes RAM Bit addresseable space Bank select Bit addresses 0 7F bits in PSW 4 Banks of 8 registers RO R7 Reset value of stack pointer A 4476 01 Figure 3 4 Upper and Lower 128 Bytes of Internal RAM 8 4 intel ADDRESS SPACES 3 2 SPECIAL FUNCTION REGISTERS SFRS The special function registers SFRs reside in the microcontroller core the USB module and the on chip peripherals Memory maps showing the location of all the 8x931H
129. point near the end of frame due to hardware events only e g the port was disabled due to babble Port Connect Status Change read clear only This bit is cleared by firmware via a USB host request ClearPortFeature with C_PORT_CONNECTION feature selector 1 indicates connect status change 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware at the EOF2 point near the end of a frame due to hardware connects and disconnects Port 1 This bit is set by hardware at the next EOF2 after completion of a hub reset since the internal port is always connected NOTE Bits are returned as part of the second word 2 bytes in response to a Get Port Status request from the USB host The upper 11 MSbs are reserved and always 0 per USB 1 0 0000 0000 000 4 3 2 1 0 MSB at left C 20 intel REGISTERS HPSTAT Address D7H Indexed by HPINDEX Reset State 100d 0000B Hub Port Status Register This register indicates the current status for a port including power reset suspend low speed device enable connect Dp and Dy status 7 0 DPSTAT DMSTAT LSSTAT PPSTAT PRSTAT PSSTAT PESTAT PCSTAT Bit Bit Function Number Mnemonic unctio 7 DPSTAT D Status read only Value of D for port x at end of last frame Firmware must return this bit in response to a GetBusState request from the host Port x x 2 3 4 5 Set and cleared by hardware at the EOF2 poi
130. register Figure 14 1 NOTE The device reset routine sets the LC bit placing the 8x931 in low clock mode 14 5 2 Exiting Low clock Mode To switch the clock of the CPU and the peripherals to the hardware selected clock rate clear the LC bit in the PCON register Figure 14 1 The hardware clock rate selection determines the high est operating clock rate for the 8x931 14 6 ON CIRCUIT EMULATION ONCE MODE The on circuit emulation ONCE mode permits external testers to test and debug 8x931 based systems without removing the chip from the circuit board A clamp on emulator or test CPU is used in place of the 8x931 which is electrically isolated from the system 14 6 4 Entering ONCE Mode To enter the ONCE mode 1 Assert RST to initiate a device reset 2 While holding RST asserted apply and hold logic levels to I O pins as follows PSEN high ALE low and EA high 3 Deassert RST then remove the logic levels from PSEN and ALE These actions cause the 8x931 to enter the ONCE mode The pins of parallel ports 0 3 ALE and PSEN pins are floating Table 14 1 on page 14 6 Thus the device is electrically isolated from the remainder of the system which can then be tested by an emulator or test CPU Note that in the ONCE mode the device oscillator remains active 14 6 2 Exiting ONCE Mode To exit ONCE mode reset the device 14 13 intel 15 External Memory Interface intel CHAPTER 15 EXTERNAL MEMORY IN
131. register TXCON Figure 6 10 on page 6 19 have a major influence on transmit operation The TXISO bit TXCON 3 determines whether the transmission is for isochronous data TXISO 1 or non isochronous data TXISO 0 For non isochronous data only the function interface receives a handshake from the host toggles or does not toggle the sequence bit and generates a transmission done interrupt Figure 8 2 Also for non isochronous data the post transmit routine is an ISR for isochronous data the post transmit routine is an ISR initiated by an SOF token The ATM bit TXCON 2 determines whether the FIFO read marker and read pointer managed automatically by the FIFO hardware ATM 1 or manually by the second firmware routine ATM 0 Use of the ATM mode is recommended The ADVRM and REVRP bits which control the read marker and read pointer when ATM 0 are used primarily for test purposes See bit definitions in TXCON Figure 5 12 8 5 8x931AA 8x931HA USER S MANUAL intel Firmware Hardware SIE FIU FIFOs Interrupt keyboard joystick modem ISR Pre transmit EEEO Routine Write data to transmit Write TXCNT IN Token Send data over USB elf ATM 1 Adjust FIFO read marker and read pointer If TXISO 0 TXISO 0 Transmit done interrupt Receive host handshake TXISO 1 SOF interrupt Manage TXSEQ bit Generate transmit done interrupt or SOF interrupt ISR
132. register required for bus enumeration is provided in the following subsections 7 2 1 Hub Descriptors The 8x931 has five descriptors as shown in Table 7 2 All are standard USB descriptors except the hub descriptor which is class specific There is no descriptor for endpoint 0 A hub has only one valid configuration and interface The actual descriptor field values are given in the section of Universal Serial Bus Specification referenced in the table The host reads the hub descriptors during bus enumeration The host uses the values within the descriptors to determine device configuration The hub descriptor is divided into several parts which are shown in Table 7 3 Table 7 2 8x931 Descriptors Descriptor Size specification Reference Device 18 bytes Section 9 7 1 Configuration 9 bytes Section 9 7 2 Interface 9 bytes Section 9 7 3 Endpoint 7 bytes Section 9 7 4 Hub 9 bytes Section 11 11 2 7 7 8x931AA 8x931HA USER S MANUAL intel Table 7 3 Hub Descriptors Field Size Offset Description bDescLength 1 byte 0 Number of bytes in this descriptor including this byte bDescriptorType 1 byte 1 Descriptor Type bNbrPorts 1 byte 2 Number of downstream ports this hub supports wHubCharacteristics 2 bytes 3 Determines power switching mode identifies device as a compound device and describes the over current protection mode used by the device bPwrOn2PwrGood
133. request will include one of the following feature selectors a C PORT CONNECTION to clear HPSC PCSC b C PORT ENABLE to clear HPSC PESC c C PORT SUSPEND to clear HPSC PSSC d C PORT RESET to clear HPSC RSTSC 8x931HA firmware responds to each ClearPortFeature request by performing the actions shown in Table 8 2 on page 8 20 Finally the host must perform any actions necessitated by the status change 8 23 8x931AA 8x931HA USER S MANUAL intel Status Change Communication 8X930Hx communicates change in port status to host via hub endpoint 1 Host inquires into status change viaa GetPortStatus command Firmware responds through the GetPortStatus request routine Host clears bits of HPSC one at a time through ClearPortFeature commands Firmware clears HPSC bits through ClearPortFeature routines Host performs any actions necessitated by status change End A5207 01 Figure 8 11 Hub to Host Port Status Communication 8 6 8 Hub Firmware Examples Several of the firmware routines given in Table 8 2 have been selected as examples The remain ing routines should be coded similarly The following subsections contain a flowchart and an ad ditional explanation for these routines 8 24 intel USB PROGRAMMING MODELS GetPortStatus Port Index SetPortFeature PORT SUSPEND SetPortFeature PORT RESET 8 6 3 1 GetPortStatus Request Firmware Firmware responds to a GetPo
134. selects the method of timer gating GATE1 timer or counter operation T C1 and mode of operation M11 and M01 The TCON register provides timer 1 control functions overflow flag TF1 run control TR1 inter rupt flag IE1 and interrupt type control IT1 Timer 1 operation in modes 0 1 and 2 is identical to timer 0 Timer 1 can serve as the baud rate generator for the serial port Mode 2 is best suited for this purpose For normal timer operation GATEI 0 setting TR1 allows timer register TL1 to be increment ed by the selected input Setting GATEI and TR1 allows external pin INT 1 to control timer op eration This setup can be used to make pulse width measurements See Pulse Width Measurements on page 10 10 Timer 1 overflow count rolls over from all 1s to all Os sets the TF1 flag generating an interrupt request 10 6 intel TIMER COUNTERS When timer 0 is in mode 3 it uses timer 1 5 overflow flag TF1 and run control bit TR1 For this situation use timer only for applications that do not require an interrupt such as a baud rate generator for the serial interface port and switch timer 1 in and out of mode 3 to turn it off and on TMOD Address S 89H Reset State 0000 0000B Timer Counter Mode Control Register Contains mode select run control select and counter timer select bits for controlling timer 0 and timer 1 7 0 GATE1 C T1 M11 M01 GATEO C TO M10 M00 Bit Mnemonic GATE
135. setting bits in the PCON register Program execution halts but resumes when the mode is exited by an interrupt While in idle or powerdown modes the Vec pin is the input for backup power Following chip reset the 8x931 operates in low clock mode wherein the CPU and on chip pe ripherals are clocked at a reduced rate until bus enumeration is accomplished This reduces to meet the 100 mA USB requirement Suspend and resume are low current modes used when the USB bus is idle The 8x931 enters sus pend when there is a continuous idle state on the bus lines for more than 3 0 msec When a device is in suspend state it draws less than 500 uA from the bus Once a device is in the suspend state its operation can be resumed by receiving resume signaling on the bus ONCE is a test mode that electrically isolates the 8x931 from the system in which it operates Table 14 1 on page 14 6 lists the condition of the out pins for the various operating modes 14 2 POWER CONTROL REGISTERS The PCON special function register Figure 14 1 provides bits for selecting the idle low clock and powerdown modes the power off flag and two general purpose flags The PCONI SFR Figure 14 2 provides USB power control including the USB global sus pend resume and USB function suspend The PCONI SFR is discussed further in USB Power Control on page 14 7 14 2 1 Power Off Flag The Power Off Flag POF located at PCON 4 is set by hardware when V rises
136. signal output Asserted for read accesses to external program memory RD Read Read signal output Asserted for read accesses to P3 7 KSO19 external data memory RXD Receive Serial Data RXD sends and receives data in serial P1 6 mode 0 and receives data in serial I O modes 1 2 and 3 RST Reset Reset input to the chip Holding this pin high for 64 8x931AA 8x931HA USER S MANUAL Table B 7 Signal Description Sheet 3 of 3 intel Signal Name Type Description Alternate Function SOF Start of Frame Start of frame pulse Active low Asserted for 8 states when frame timer is locked to USB frame timing and SOF token or artificial SOF is detected P3 1 T1 0 Timer 1 0 External Clock Input When timer 1 0 operates as a counter a falling edge on the T1 0 pin increments the count P3 5 4 KSO17 16 T2 VO Timer 2 Clock Input Output For the timer 2 capture mode this signal is the external clock input For the clock out mode it is the timer 2 clock output P1 0 T2EX TXD Timer 2 External Input In timer 2 capture mode a falling edge initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction 1 up 0 down Transmit Serial Data TXD outputs the shift clock in serial I O mode 0 and transmits serial data in serial
137. since it resides in the PSW register which is bit address able Note that the Boolean instruction set includes ANL and ORL operation but not the XRL Exclu sive OR operation An XRL operation is simple to implement in software Suppose for example it is required to form the Exclusive OR of two bits C bitl XRL bit2 The software to do that could be as follows MOV C bitl JNB bit2 OVER CPL C OVER continue First 6101 is moved to the Carry If bit2 0 then C now contains the correct result That is bit1 XRL bit2 bitl if bit2 0 On the other hand if bit2 1 C now contains the complement of the correct result It need only be inverted CPL C to complete the operation This code uses the JNB instruction one of a series of bit test instructions which execute a jump if the addressed bit is set JC JB JBC or if the addressed bit is not set JNC JNB In the above case bit2 is being tested and if bit2 0 the CPL C instruction is jumped over JBC executes the jump if the addressed bit is set and also clears the bit Thus a flag can be tested and cleared in one operation All the PSW bits are directly addressable so the Parity bit or the general purpose flags for ex ample are also available to the bit test instructions 4 1 6 1 Relative Offset The destination address for these jumps is specified to the assembler by a label or by an actual address in Program Memory However the destination address ass
138. table 2 9 CLR instruction A 5 A 7 Core 2 6 SFRs C 3 CPL instruction A 5 A 7 CPU 2 6 Crystal on chip oscillator 13 2 CY flag 4 2 C 39 D DA instruction A 5 Data Transfer 4 8 instructions table of 4 8 A 7 Datasheets on WWW 1 7 DEC instruction A 4 Descriptors bDescLength 7 8 bDescriptorType 7 8 bHubContrCurrent 7 8 bNbrPorts 7 8 bPwrOn2PwrGood 7 8 DeviceRemovable 7 8 PortPwrCtrlMask 7 8 wHubCharacteristics 7 8 dir8 A 2 DIV instruction A 5 DJNZ instruction A 8 Documents ordering 1 7 related 1 6 DPH DPL C 7 as SFRs C 3 E Encryption 16 1 Encryption array 16 1 key bytes 16 5 EPCON 6 7 C 8 EPINDEX 6 6 C 10 External bus inactive 15 2 Index 1 8x931AA 8x931HA USER S MANUAL pin status 15 4 External bus cycles 15 2 15 4 nonpage mode 15 3 External code memory idle mode 14 6 powerdown mode 14 8 External Interrupts 5 6 See Interrupts External interrupt 2 enable 5 25 C 28 External memory design examples 15 6 15 8 External RAM 4 10 example 15 8 exiting idle mode 14 7 F FO flag 4 2 C 39 FADDR 6 14 C 11 FaxBack service 1 7 FIE 5 4 5 9 6 3 C 3 C 12 FIFLG 5 4 5 11 6 3 C 3 C 13 C 14 Frame timer 5 11 G Given address See Serial I O port Global suspend interrupt 5 17 H HADDR 7 7 7 8 8 2 Help desk 1 7 HIE 5 4 5 15 C 3 C 15 HIFLG 5 4 5 16 C 3 C 16 HPCON 7 15 C 17 HPINDEX 7 24 C 18 HPPWR 7 28 C 19
139. the USB If the data packet is not ready for transmission 8x931 hardware responds to the IN token with a NAK The post transmit routine checks the transmission status and performs data manage ment tasks Completion of data transmission is indicated by a handshake returned by the host This is then used to generate a transmit done interrupt to signal the end of data transmission to the CPU The interrupt can also be used for activity tracking and fail safe management Fail safe management permits recovery from lockups that can only be cleared by firmware Because a transmit done interrupt is generated regardless of transmission errors this condition means either The transmit data has been transmitted and the host has sent an acknowledgment to indicate that is was successfully received or 2 Atransmit data error occurred during transmission of the data packet which requires servicing by firmware to be cleared You must check for these conditions and respond accordingly in the ISR 8 4 intel USB PROGRAMMING MODELS For ISO data transmission the cycle is similar The significant differences are the cycle is initi ated by a start of frame SOF interrupt there is no handshake associated with ISO transfer and a transmit done interrupt is not generated For ISO data transfers the transaction status is updated at the end of the USB frame The 8x931 supports one ISO packet per frame per endpoint Two bits in the transmit FIFO control
140. the USB operating rate Refer to Table 2 4 on page 2 10 8X931 Microcontroller Voc AVocc RST Vcc ROM Vss ROMIess 1uF l A4452 01 Figure 13 1 Minimum Setup 13 2 ELECTRICAL ENVIRONMENT The 8x931 is a high speed CHMOS device To achieve satisfactory performance its operating environment should accommodate the device signal waveforms without introducing distortion or noise Design considerations relating to device performance are discussed in this section See the device data sheet for voltage and current requirements operating frequency and waveform tim ing 13 1 8x931AA 8x931HA USER S MANUAL intel 13 2 1 Power and Ground Pins Power the 8x931 from a well regulated power supply designed for high speed digital loads Use short low impedance connections to the power Voc and ground Vss pins 13 2 2 Unused Pins To provide stable predictable performance connect unused input pins to Vs or Vec Untermi nated input pins can float to a mid voltage level and draw excessive current Unterminated inter rupt inputs may generate spurious interrupts For the 8x931HA if the USB downstream ports are not used the two data lines are still required to be pulled low externally using 15K pulldown resistors so inputs are not floating 13 2 3 Noise Considerations The fast rise and fall times of high speed CHMOS logic may produce noise spikes on the power supply lines and signal outputs
141. the following nonvolatile memory functions on the 83931 ROM device on chip program memory 8 Kbytes lock bits 3 bits signature bytes 3 bytes The 83931 is verified in the same manner as MCS 51 microcontrollers Verify operations differ from normal device operation Verify operations are performed with the device installed in a ROM or EPROM programmer The CPU does not execute instructions Memory accesses are made one byte at a time using addresses externally applied to ports P3 4 5 P2 0 5 and P1 See Table 16 2 on page 16 3 for pin usage during verify operations For a complete list of device sig nal descriptions see Appendix B To preserve the security of on chip program code the encryption array cannot be verified 16 1 8x931AA 8x931HA USER S MANUAL Table 16 1 Signal Descriptions Verify Mode Signal Alternate Name Type Description Function P0 7 0 Port 0 Eight bit open drain bidirectional I O port For verify operations use as the data port See Table 16 2 and Figure 16 1 Port 1 Eight bit bidirectional I O port with internal pullups For verify operations use for low byte of address See Table 16 2 and Figure 16 1 Port 2 Eight bit bidirectional I O port with internal pullups For verify operations use P2 5 0 as A8 13 and P2 6 and P2 7 to ground See Table 16 2 and Figure 16 1 P3 7 0 l Port 3 Eight bit bidirectional I O port with internal pullups For verify o
142. the hub or function endpoints the LSbs of EPINDEX are used to con trol which endpoint s registers are accessed For additional information on how to use EPINDEX see Endpoint Selection on page 5 4 7 4 2 Hub Endpoint Control Hub endpoint 1 of the 8x931 is controlled primarily by hardware with these exceptions Firmware can read endpoint 1 s TXDAT SFR Firmware can stall hub endpoint 1 in response to a Set Feature ENDPOINT STALL request from the host by setting the EPISTL bit in HSTAT Figure 7 6 Firmware can also clear this bit in response to a Clear Feature request Firmware can enable hub endpoint 1 in response to a Set Configuration request from the host by setting the EPIEN bit in HSTAT Figure 7 6 on page 7 9 Firmware can control hub endpoint 0 through its EPCON register when EPINDEX has previ ously been set to 80H Hub endpoint control for endpoint 0 behaves identically to function end point control except that hub endpoint 0 is always a single packet control endpoint Therefore the corresponding bits CTLEP and RXSPM of its EPCON SFR are hardwired to 1 8x931AA 8x931HA USER S MANUAL intel 7 4 3 Hub Endpoint Transmit and Receive Operations The 8x931 hardware uses hub endpoint 1 s TXDAT register Figure 7 7 to transmit a port status change interrupt to the host Figure 7 8 shows how a hub or port status change is reflected in TX DAT TXDAT is cleared by firmware upon a ClearPortFeature reque
143. the receive FIFO Since the SOF packet could be corrupted there is a chance that a new frame could be started with out successful reception of the SOF packet For this reason an artificial SOF is provided The frame timer signals a time out when an SOF packet has not been received within the allotted amount of time In this fashion the 8x931 generates an SOF interrupt reliably once each frame within 1 us of accuracy except when this interrupt is suspended or when the frame timer gets out of sync with the USB bus frame time In summary to use the USB start of frame functionality for isochronous data transfer the follow ing must all be true The global enable bit must be set That is the EA bit must be set in the IENO register Figure 5 10 The isochronous endpoint Any SOF interrupt must be enabled That is the ESOF bit must be set in the IENI register Figure 5 11 The SOF interrupt must be enabled That is the SOFIE bit must be set in the SOFH Register Figure 5 5 NOTE The SOF interrupt is brought out to an external pin SOF in order to provide a 1 ms pulse subject to the accuracy of the USB start of frame This pin is enabled by clearing the SOFODIS bit in the SOFH register intel INTERRUPT SYSTEM 5 2 7 USB Hub Interrupt The USB hub interrupt is used to signal a receive done or transmit done for hub endpoint 0 To enable the hub interrupt 1 Set the global enable bit EA in the IENO register Figure 5 10
144. the timer 2 overflow flag TF2 and generates an interrupt request The overflow also causes the 16 bit value in RCAP2H and RCAP2L to be load ed into the timer registers TH2 and TL2 When T2EX is low timer 2 counts down Timer underflow occurs when the count in the timer registers TH2 TL2 equals the value stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and reloads FFFFH into the timer registers The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count When timer 2 operates as an up down counter EXF2 does not generate an interrupt This bit can be used to provide 17 bit resolution Down Counting Reload Value Interrupt Request TH2 TL2 f Bits 1 8 Bits Count Direction 1 Up 0 Down RCAP2H RCAP2L Up Counting Reload Value A5203 01 Figure 10 9 Timer 2 Auto reload Mode DCEN 1 10 13 8x931AA 8x931HA USER S MANUAL intel 10 6 4 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port Select this mode by setting the RCLK and or TCLK bits in T2CON See Table 10 3 For details regarding this mode of operation refer to Baud Rates on page 13 10 10 6 5 Clock out Mode In the clock out mode timer 2 functions as a 50 duty cycle variable frequency clock Figure 10 10 The generated clock signal appears on pin T2 The input clock increments TLO at the in terna
145. this bit reverses the read pointer to point to the origin of the last data set the position of the read marker so that the FIU can reread the last set for retransmission Hardware clears this bit after the read pointer is reversed This bit is effective only when the ADVRM ATM and TXCLR bits are all clear ATM mode is recommended ADVRM and REVRP which control the read marker and read pointer when ATM 0 are used for test purposes Figure 6 10 TXCON Transmit FIFO Control Register Continued 6 20 intel USB FUNCTION TXFLG Endpoint indexed Address F5H Reset State 00xx 1000B Transmit FIFO Flag Register These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX 7 0 TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF Bit Number Bit Mnemonic Function 7 6 TXFIF1 0 FIFO Index Flags read only These flags indicate which data sets are present in the transmit FIFO The FIF bits are set in sequence after each write to TXCNTL to reflect the addition of a data set Likewise TXFIF1 and TXFIFO are cleared in sequence after each advance of the read marker to indicate that the set is effectively discarded The bit is cleared whether the read marker is advanced by firmware setting ADVRM or automatically by hardware ATM 1 The next state table for the TXFIF bits is shown below TXFIF1 0 Operation Flag Next TXFIF1 0 Next Flag 00 Wr TXC
146. this time frame to initialize the em bedded function 8 28 intel Input Output Ports intel CHAPTER 9 INPUT OUTPUT PORTS The 8x931 has four 8 bit input output I O ports for general purpose I O external memory op erations and specific alternate functions see Table 9 1 This chapter describes the ports and pro vides information on port loading read modify write instructions and external memory accesses Chapter 16 External Memory Interface contains additional information about exter nal memory operations 9 1 INPUT OUTPUT PORT OVERVIEW All four 8x931 I O ports are bidirectional Each port contains a latch an output driver and an in put buffer Port 0 and port 2 output drivers and input buffers facilitate external memory opera tions Port 0 drives the lower address byte onto the parallel address bus and port 2 drives the upper address byte onto the bus The data is multiplexed with the lower address byte on port 0 Port and port 3 provide both general purpose I O and special alternate functions Table 9 1 Input Output Port Pin Descriptions m Type eu end Alternate Description dim P0 7 0 VO AD7 0 KSI7 0 Address Data Lines Keyboard Scan Input VO P1 0 VO T2 KSO0 Timer 2 Clock Input Output Keyboard Scan Output y o P1 1 VO T2EX KSO1 Timer 2 External Input Keyboard Scan Output VO P1 5 2 VO KSO5 2 Keyboard Scan Output 1 6 VO RXD KSO6 Receive Serial Data Keyboar
147. transmit done interrupt for endpoint 0 FTXDO NOTE For all bits a 1 means the interrupt is enabled and will cause an interrupt to be signaled to the microcontroller A 0 means the associated interrupt source is disabled and cannot cause an interrupt even though the interrupt bit s value is still reflected in the FIFLG register Figure 5 3 FIE USB Function Interrupt Enable Register The USB function generates a receive done interrupt for an endpoint x x 0 2 by setting the FRXDx bit in the FIFLG register Figure 5 4 Only a non isochronous transfer can cause a re ceive done interrupt Receive done interrupts are generated only when all of the following are true A valid SETUP or OUT token is received to function endpoint x Endpoint x is enabled for reception RXEPEN in EPCON 1 Receive is enabled RXIE 1 STALL is disabled RXSTL 0 for OUT tokens or the token received is a SETUP token A data packet is received with no time out regardless of transmission errors CRC bit stuffing or FIFO errors overrun underrun 5 9 8x931AA 8x931HA USER S MANUAL intel There is no data sequence PID error Because the FRXDx bit is set and a receive done interrupt is generated regardless of transmis sion errors this condition means either Valid data is waiting to be serviced in the receive FIFO for function endpoint x and that the data was received without er
148. 0 KSO8 8 F A9 P2 1 KSO9 7 H A10 P2 2 KSO10 6 FA A11 P2 3 11 5E A12 P2 4 KSO12 4 EA A13 P2 5 KSO13 3 FA A14 P2 6 KSO14 2 A15 P2 7 KSO15 e 1 A Vss 68 F Vccp 67 F EA 66 65 PSEN 64 B FSSEL 63 Vssp 62 Reserved 61 Fa Reserved AD7 P0 7 KSI7 E 10 Reserved NC AD6 P0 6 KSI6 E 11 Reserved NC ADS P0 5 KSI5 E 12 Reserved NC AD4 P0 4 KSIA E 13 Reserved NC AD3 P0 3 E 14 Voc AD2 P0 2 KSI2 E 15 AD1 P0 1 KSI1 ADO P0 0 KSIO ECAP Vssp Vssp Vcc Voce P5 1 Ser E 21 View of component as Ho NC P3 2 INTO EY 22 mounted on PC board Reserved NC P3 3 INT1 E 23 Vesp P3 4 TO KSO16 5 24 Reserved NC P3 5 T1 KSO17 E 25 Reserved NC P3 6 WR KSO18 F1 26 LEDO P3 7 RD KSO19 Q 27 P1 0 T2 KSO0 28 P1 1 T2EX KSO1 amp 29 P1 2 KSO2 30 P1 3 KSO3 31 P1 4 KSO4 32 P1 5 KSO5 Q 33 P1 6 KSO6 34 P1 7 TXD KSO7 35 LED3 rj 36 LED2 amp 37 XTAL1 38 XTAL2 39 AVcc 9 40 RST Ej 41 PLLSEL amp 42 LED1 amp 43 Note Reserved pins must be left unconnected A5348 02 Figure B 5 8x931AA 68 pin PLCC Package B 5 8x931AA 8x931HA USER S MANUAL Table B 1 68 pin PLCC Pin Assignment Specific to the 8x93
149. 0 and that the data was received without error and has been acknowledged or 2 that data was received with a FIFO error requiring firmware intervention to be cleared 0 HTXDO Hub Transmit Done Endpoint 0 Hardware sets this bit to indicate that one of two conditions exists in the transmit data buffer for hub endpoint 0 1 the transmit data has been transmitted and the host has sent acknowledgment which was successfully received or 2 a FIFO related error occurred during transmission of the data packet which requires servicing by firmware to be cleared 5 16 Figure 5 8 HIFLG Hub Interrupt Status Register intel INTERRUPT SYSTEM 5 2 8 USB Global Suspend Resume Interrupt The 8x931 supports USB power control through firmware The USB power control register PCONI as shown in Figure 9 2 on page 9 3 facilitates USB power control of the 8x931 includ ing global suspend resume and USB function resume 5 2 8 1 Global Suspend When a global suspend is detected by the 8x931 the global suspend bit GSUS of PCONI is set and the global suspend resume interrupt is generated if IENO 7 EA and IEN1 2 are set Global suspend is defined as bus inactivity for more than 3 ms on the USB lines For additional informa tion see Global Suspend Mode on page 14 7 5 2 8 2 Global Resume When a global resume is detected by the 8x931 the global resume bit GRSM of PCON 1 is set and the global suspend resume interrupt is generated i
150. 00000000 00000000 00001000 C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF 00000000 xxxx xx00 00000000 00000000 00000000 00000000 CO FIFLG C7 xx000000 B8 IPLO SADEN BF x0000000 00000000 IEN1 IPL1 IPH1 IPHO B7 11111111 00000000 00000000 00000000 00000000 8 IENO SADDR AF 00000000 00000000 A0 P2 FIE A7 11111111 xx000000 98 SCON SBUF 9F 00000000 XXXXXXXX 90 P1 97 11111111 88 TCON TMOD TLO TL1 THO TH1 FADDR 8F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80 PO SP DPL DPH PCON 87 11111111 00000111 00000000 00000000 001d0000 0 8 1 9 2 A 3 B 4 5 0 6 7IF MCS 51 microcontroller SFRs Endpoint indexed SFRs For EPCON TXCON TXDAT TXCNTL and RXCNTL the reset value depends the endpoint pair selected Refer to the register definition tables in Appendix C or Chapter 6 USB Function NOTE in the SFR reset value denotes configuration operation dependence Refer to the specific SFR description for more details intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Guide to this Manual on page 1 1 discusses notational conventions and general terminol ogy data datal6 ACK accumulator addr11 addr16 ALU assert big endien form bit bit operand bit stuffing bulk transfer bus enumeration byte An 8 bit constant that
151. 1 Number Function Timer 1 Gate When GATE1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 MO1 Timer 1 Mode Select M11 M01 0 0 ModeO 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow Mode 3 Timer 1 halted Retains count Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input Timer 0 Counter Timer Select C TO 0 selects timer operation timer 0 counts the divided down system clock 1 selects counter operation timer 0 counts negative transitions on external pin TO Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescalar TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode 3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits 1 0 M10 MOO Figure 10
152. 1 7 Select timer mode 0 3 by programming the M1 and MO bits in the TMOD register In most applications timer 1 is configured as a timer in auto reload mode high nibble of TMOD 0010B The resulting baud rate is defined by the following expression SMOD1 Fosc Serial I O Modes 1 and Baud Rate 2 x 382 x 12x 256 THT Timer 1 can generate very low baud rates with the following setup Enable the timer 1 interrupt by setting the bit in the IENO register Configure timer to run as a 16 bit timer high nibble of TMOD 0001B e Use the timer 1 interrupt to initiate a 16 bit firmware reload Table 11 4 lists commonly used baud rates and shows how they are generated by timer 1 11 11 8x931AA 8x931HA USER S MANUAL intel Table 11 4 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 Baud eke SMOD1 Rate Fosc C T Mode Reload 62 5 Kbaud Max 12 0 MHz 1 2 FFH 19 2 Kbaud 11 059 MHz 1 ole FDH 9 6 Kbaud 11 059 MHz 0 2 FDH 4 8 Kbaud 11 059 MHz 0 2 FAH 2 4 Kbaud 11 059 MHz 0 2 1 2 Kbaud 11 059 MHz 0 2 137 5 Baud 11 986 MHz 0 2 1DH 110 0 Baud 6 0 MHz 0 2 72H 110 0 Baud 12 0 MHz 0 1 FEEBH 11 6 3 3 Timer 2 Generated Baud Rates Modes 1 and 3 Timer 2 may be selected as the baud rate generator for the transmitter and or receiver Figure 11 5 The timer 2 baud rate generator mode is similar to the
153. 11 0X0X Given 1111 00X1 Slave B SADDR 11110011 SADEN 1111 1001 Given 1111 OXX1 The SADEN byte is selected so that each slave may be addressed separately For Slave A bit 0 the LSb is a don t care bit for Slaves B and C bit 0 is a 1 To communicate with Slave A only the master must send an address where bit 0 is clear e g 1111 0000 For Slave A bit 1 is a 0 for Slaves B and bit 1 is a don t care bit To communicate with Slaves B and C but not Slave A the master must send an address with bits 0 and 1 both set e g 1111 0011 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is a 0 To communicate with Slaves A and B but not Slave C the master must send an address with bit O set bit 1 clear and bit 2 set e g 1111 0101 To communicate with Slaves A B and C the master must send an address with bit 0 set bit 1 clear and bit 2 clear e g 1111 0001 11 5 2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 0101 0110 SADEN 1111 1100 SADDR OR SADEN 1111111X The use of don t care bits provides flexibility in defining the broadcast address however in most applications a broadcast address is OFFH 8x931AA 8x931HA USER S MANUAL intel The following is an example of using broadcast addresses Slave A SADDR 11110001 Slave C SADDR 11110010 SADEN 11111010 SADEN 11
154. 111101 Broadcast 1111 1X11 Broadcast 11111111 Slave B SADDR 11110011 SADEN 1111 1001 Broadcast 1111 1X11 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is set To communicate with all of the slaves the master must send an address FFH To communicate with Slaves A and B but not Slave C the master can send an address FBH 11 5 3 Reset Addresses On reset the SADDR and SADEN registers are initialized to 00H that is the given and broadcast addresses are xxxx xxxx all don t care bits This ensures that the serial port is backwards com patible with MCS 51 microcontrollers that do not support automatic address recognition 11 6 BAUD RATES You must select the baud rate for the serial port transmitter and receiver when operating in modes 1 2 and 3 The baud rate is preset for mode 0 In its asynchronous modes the serial port can transmit and receive simultaneously Depending on the mode the transmission and reception rates can be the same or different Table 11 3 summarizes the baud rates that can be used for the four serial I O modes NOTE Setting the low clock PCON 5 bit forces the internal clock frequency distributed to the CPU and peripherals to 3MHz This bit is automatically set after a reset Clearing this bit through firmware returns to the normal clock frequency Fosc 2 11 6 1 Baud Rate for Mode 0 The baud rate for mode 0 is fixed at Fogc 12 Table 11 3 Su
155. 16 6 10 TXCON Transmit FIFO Control Register 6 19 6 11 TXFLG Transmit FIFO Flag Register 6 21 6 12 Receive FIFO arii inh doti RoW eke ante Ghee ae 6 24 6 13 RXDAT Receive FIFO Data 6 26 6 14 RXCNTL Receive FIFO Byte Count Register sese 6 26 6 15 RXCON Receive FIFO Control Register essseeeeeeneeenennenen 6 29 6 16 RXFLG Receive FIFO Flag Register esseeeeeeeneeneenne 6 31 xi 8x931AA 8x931HA USER S MANUAL intel 7 1 7 3 7 4 7 6 7 7 7 9 7 10 7 11 7 12 7 13 7 14 8 1 8 3 8 4 8 6 8 7 8 9 8 10 8 11 8 12 8 13 8 14 8 15 xii 8x931HA Hub Functional Diagram 7 2 Bits of the USB H b SFHRS 2 eec eet tee Dre 7 3 Hub State FlOW alee eli pe e Atle ee a Lee elias 7 5 Packet Signaling Connectivity ecceeeeceeeeeeeeeeeteneeeeeeeeeecaeeseaeesaeeeeaeeeaeeseneesieeeeeeeaes 7 6 HADDR Hub Address Register nennen 7 8 HSTAT Hub Status and Configuration 7 9 TXDAT Hub Transmit Data Buffer Endpoint 1 7 12 Status Change Communication To Host 7 13 HPCON Hub Port Control Register ssssseeeeeeneenneeneen nn 7 15 HPSTAT Hub Port Status Register
156. 1AA tt Specific to the 8x931HA Pin Name Pin Name Pin Name 1 Vss 24 P3 4 TO KSO16 47 2 A15 P2 7 KSO15 25 P3 5 T1 KSO17 48 Reserved 3 A14 P2 6 KSO14 26 49 D 3tt 4 A13 P2 5 KSO13 27 P3 7 RD KSO19 50 Vas 5 A12 P2 4 KSO12 28 P1 0 T2 KSOO0 51 6 A11 P2 3 KSO11 29 P1 1 T2EX KSO1 52 Vsgp 7 A10 P2 2 KSO10 30 P1 2 KSO2 53 ECAP 8 A9 P2 1 KSO9 31 P1 3 KSO3 54 9 A8 P2 0 KSO8 32 P1 4 KSO4 55 10 AD7 P0 7 KSI7 33 P1 5 KSO5 56 Voc 11 AD6 P0 6 KSI6 34 P1 6 KSO6 RXD 57 Reserved Dust 12 AD5 P0 5 KSI5 35 58 Reserved Dpstt 13 AD4 P0 4 KSI4 36 LED3 59 Reserved Dyyqt 14 AD3 P0 3 KSI3 37 LED2 60 Reserved 15 AD2 PO 2 KSI2 38 XTAL1 61 Reserved NC 16 AD1 P0 1 KSI1 39 XTAL2 62 Reserved NC 17 ADO P0 0 KSIO 40 63 Vssp 18 Vase 41 RST 64 FSSEL UPWEN t 19 Vec 42 PLLSEL 65 PSEN 20 P3 0 OVRI 43 66 ALE 21 P3 1 SOF 44 67 EA 22 P3 2 INTO 45 Reserved Dyot 68 23 P3 3 INT1 46 Reserved intel PIN DESCRIPTIONS Table B 2 64 pin SDIP Pin Assignment Pin Name Pin Name Pin Name 1 Voc 23 45 EA 2 P3 0 OVRI 24 PLLSEL 46 Voce 3 P3 1 SOF 25 LEDi 47 Ves 4 P3 2 INTO 256 48 A15 P27 KSO15 5 P3 3 INT1 27 DM2 49 A14 P2 6 KSO14 6 P3 4 TO KSO16 28 DP2 50 A13 P2 5 KSO13 7 P3 5 T1 KSO17 29 DM3 51 A12 P2 4 KSO12 8 P3 6 WR KSO18 30 DP3 5
157. 2 A11 P2 3 KSO11 9 P3 7 RD KSO19 31 Ves 53 A10 P2 2 KSO10 10 P1 0 T2 KSO0 32 Voce 54 A9 P2 1 KSO9 11 P1 1 T2EX KSO1 33 Vssp 55 A8 P2 0 KSO8 12 P1 2 KSO2 34 ECAP 56 AD7 P0 7 KSI7 13 P1 3 KSO3 35 57 AD6 P0 6 KSI6 14 P1 4 KSO4 36 58 AD5 PO 5 KSI5 15 P1 5 KSO5 37 Diis 59 AD4 P0 4 KSI4 16 P1 6 RXD KSO6 38 60 AD3 P0 3 KSI3 17 P1 7 TXD KSO7 39 Di 61 AD2 P0 2 KSI2 18 LED3 40 62 AD1 P0 1 KSI1 19 LED2 41 6 ADO PO 0 KSIO 20 XTAL1 42 UPWEN 64 Vesp 21 XTAL2 43 22 AVCC 44 ALE B 7 8x931AA 8x931HA USER S MANUAL Table B 3 64 pin QFP Pin Assignment Pin Name Pin Name Pin Name 1 AD6 P0 6 KSI6 23 P1 5 KSO5 45 Reserved NC Dyg 2 AD5 P0 5 KSI5 24 P1 6 RXD KSO6 46 Reserved NC Dps 3 AD4 P0 4 KSI4 25 P1 7 TXD KSO7 47 Reserved NC Dy4 4 AD3 P0 3 KSI3 26 LED3 48 Reserved NC Dp4 5 AD2 PO 2 KSI2 27 LED2 49 Vssp 6 AD1 P0 1 KSI1 28 XTAL1 50 FSSEL UPWEN 7 ADO PO 0 KSIO 29 XTAL2 51 PSEN 8 Vssp 30 AVcc 52 ALE 9 Vec 31 RST 53 EA 10 P3 0 OVRI 32 PLLSEL 54 Vccp 11 P3 1 SOF 33 LED1 55 Vss 12 P3 2 INTO 34 LEDO 56 A15 P2 7 KSO15 13 P3 3 INT1 35 Reserved 57 A14 P2 6 KSO14 14 P3 4 TO KSO16 36 Reserved NC Dps 58 A13 P2 5 KSO13 15 P3 5 T1 KSO17 3f Reserved NC Dys 59 A12 P2 4 KSO12 16 P3 6 WR KSO18 38 Reserved NC Dp3i 60 A11 P2 3 KSO11 17 P3 7 RD K
158. 29 Encoding 1101 0100 DA Contents of accumulator are BCD IF A 3 0 gt 9 V AC 1 THEN A 3 0 lt A 3 0 6 AND IF A 7 4 gt 9 V CY 1 THEN A 7 4 A 7 4 6 Decrement Decrements the specified byte variable by 1 An original value of 00H underflows to OFFH Four operands addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins intel INSTRUCTION SET REFERENCE Flags CY AC OV Example Register 0 contains 7FH 01111111B On chip RAM locations 7EH and 7FH contain 00H and 40H respectively After executing the instruction sequence DEC QRO DEC RO DEC RO register 0 contains 7EH and on chip RAM locations 7EH and 7FH are set to OFFH and 3FH respectively Variations DECA Bytes States 6 Cycles Encoding 0001 0100 Operation DEC e 1 DEC 8 Bytes 2 States 6 Cycles Encoding 0001 0101 dir addr Operation DEC dir8 lt dir8 1 DEC Ri Bytes States 6 Cycles Encoding 0001 011i Operation DEC Ri lt Ri 1 A 23 8x931AA 8x931HA USER S MANUAL intel DEC Rn Bytes States Cycles Operation DIV AB Function Description Flags Example Bytes States Cycles
159. 29 P1 2 KSO2 rj 30 P1 3 KSO3 amp 31 P1 4 KSO4 32 P1 5 KSO5 33 P1 6 RXD KSO6 EY 34 P1 7 TXD KSO7 EF 35 LED3 36 LED2 amp 37 XTAL1 amp 38 XTAL2 39 AVcc E 40 RST 41 PLLSEL Q 42 LED1 amp 43 Note Reserved pins must be left unconnected A5348 02 Figure E 2 8x931AA 68 pin PLCC E 4 8X931AA DESIGN CONSIDERATIONS Table E 1 8x931AA Signals Arranged by Functional Category Address and Data Input Output USB AD7 0 yo P0 7 0 y o 15 8 P1 7 0 y o Dpo VO P2 7 0 Keyboard Scan I O P3 7 0 VO KSO19 0 TO PLLSEL KSI7 0 T1 SOF FSSEL LED Drivers Processor Control LED3 0 Power amp Ground INTO AVcc PWR Bus Control INT1 l Voc PWR ALE RST PWR PSEN XTAL1 Vss GND RD XTAL2 Vase GND WR 5 8x931AA 8x931HA USER S MANUAL 4 8x931AA SIGNAL DESCRIPTIONS Table E 2 8x931AA Signal Descriptions intel Signal Name Type Description Alternate Function A15 8 Address Lines Upper byte of external memory address P2 7 0 KSO15 7 AD7 0 VO Address Data Lines Lower byte of external memory address multiplexed with data P0 7 0 KSI7 0 ALE Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0
160. 3 TXEMP Transmit FIFO Empty Flag read only Hardware sets this bit when the write pointer has not rolled over and is at the same location as the read pointer Hardware clears this bit when the pointers are at different locations Regardless of ISO or non ISO mode this bit always tracks the current transmit FIFO status 2 TXFULL Transmit FIFO Full Flag read only Hardware sets this bit when the write pointer has rolled over and equals the read marker Hardware clears this bit when the full condition no longer exists Regardless of ISO or non ISO mode this bit always tracks the current transmit FIFO status Check this bit to avoid causing a TXOVF condition When set all transmissions are NAKed Figure 6 11 TXFLG Transmit FIFO Flag Register Continued 6 22 intel USB FUNCTION TXFLG Continued Endpoint indexed Address F5H Reset State 00xx 1000B Transmit FIFO Flag Register These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX 7 TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF Bit Number Bit Mnemonic Function TXURF Transmit FIFO Underrun Flag read clear Hardware sets this flag when an additional byte is read from an empty transmit FIFO or TXCNTL This is caused when the value written to TXCNTL is greater than the number of bytes written to TXDAT This is a sticky bit that must be cleared through f
161. 31AA 8x931HA USER S MANUAL intel IEN1 Address B1H Reset State 0000 0000B Interrupt Enable Register 1 Contains the enable bits for the USB interrupts 7 EX2 ESR EF ESOF Bit Bit Number Mnemonic Function 7 2 External Interrupt 2 Enable Keyboard Scan Setting this bit enables the external interrupt used for the keyboard scan NOTE Setting this bit causes the 8x931 to trigger a hardware interrupt when a keyboard scan interrupt occurs but only if the KSEN bit in the KBCON register is also set 6 3 Reserved Write zeros to these bits 2 ESR Enable Suspend Resume USB global suspend resume interrupt enable bit Enable Function Transmit Receive Done interrupt enable bit for non isochronous USB function endpoints 0 ESOF Enable USB Hub Start of Frame Any start of frame interrupt enable for isochronous endpoints or USB hub interrupt enable C 26 intel REGISTERS IPHO Address B7H Reset State x000 0000B Interrupt Priority High Control Register 0 IPHO together with IPLO assigns each interrupt in IENO a priority level from 0 lowest to 3 highest IPHOx IPLOx Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 IPHO 0 Bit Bit Function Number Mnemonic uneto 7 6 Reserved Write zeros to these bits
162. 57H 11 14 intel 12 Keyboard Control intel CHAPTER 12 KEYBOARD CONTROL This chapter describes the 8x931 keyboard control interface 12 1 OVERVIEW The 8x931 keyboard control interface consists of 20 keyboard scan output lines eight keyboard scan input lines and four LED drivers The output lines input lines and LEDs are controlled by the KBCON SFR shown in Figure 12 2 below KBCON Address F8H Reset State 0xx0 0000B Keyboard Control Register This register controls the keyboard scan input and output activity enables and configures the keyboard scan interrupt and drives the keyboard LEDs 7 0 IE2 KSEN IT2 LED3 LED2 LED1 LEDO Bit Bit Number Mnemonic Function 7 IE2 Interrupt 2 Flag Set when external interrupt 2 is detected if the KSEN bit is set Firmware must clear this bit when the interrupt is serviced 6 Reserved Write a zero to this bit 5 KSEN Keyboard Scan Enable Setting this bit enables the pullup resistors on the KSI input lines enables the keyboard scan interrupt INT2 and enables the LED drivers NOTE The EX2 bit in the IENO SFR must also be set to enable the KSI external interrupt 4 IT2 Interrupt 2 Type Control Bit If set a negative edge detect on any of the KSI pins causes IE2 to be set When clear IE2 acts as a level 0 triggered interrupt 3 0 LED3 0 LED Driver Control Clearing one of these bits turns on the asso
163. 6 3 Lock Bit Vai nig 16 4 Contents of the Signature Bytes ssssssssssssseeeeeeeeneen enne 16 4 Notation for Register 5 A 2 Notation for Direct Addresses enne A 2 Notation for Immediate A 2 Notation for Bit A 2 Notation for Destinations in Control Instructions A 2 Instructions for 8x931 Peripheral Controllers sese A 3 Summary of Add and Subtract Instructions sseseeeneees A 4 Summary of Increment and Decrement Instructions A 4 Summary of Multiply Divide and Decimal adjust Instructions A 5 Summary of Logical Instructions sesssseeeeeeeeenenenennen nennen A 5 Summary of Move Instructions essssesseseee enne nennen nennen A 6 Summary of Exchange Push and Pop 5 A 7 Summary of Bit INStUCTIONS ice toni rh n PEU DPA eR A 7 Summary of Control Instructions sesssssseseeeneneeeennen nennen nenne A 8 Flag Symbols ec ele A 9 68 pin PLCC Pin
164. 68 P3 6 WR KSO18 26 P3 3 INT1 23 Voc 19 56 P3 7 RD KSO19 27 RST 41 AVcc 40 PSEN 65 XTAL1 38 Vss 1 50 ALE 66 XTAL2 39 18 47 EA 67 52 63 B 9 8x931AA 8x931HA USER S MANUAL intel Table B 5 64 pin SDIP Signal Assignments Arranged by Functional Category Address amp Data Input Output USB Name Pin Name Pin Name Pin A15 P2 7 KSO15 48 P1 0 T2 KSOO 10 PLLSEL 24 A14 P2 6 KSO14 49 P1 1 T2EX KSO1 35 A13 P2 5 KSO13 50 P1 2 KSO2 36 A12 P2 4 KSO12 51 P1 3 KSO3 Dus 37 A11 P2 3 KSO11 52 P1 4 KSO4 Dps 38 A10 P2 2 KSO10 53 P1 5 KSO5 Due 27 A9 P2 1 KSO9 54 P1 6 RXD KSO6 Dpo 28 A8 P2 0 KSO8 55 P1 7 TXD KSO7 Dus 29 AD7 P0 7 KSI7 56 P3 0 OVRI Dp3 30 AD6 P0 6 KSI6 57 P3 1 SOF ECAP 34 AD5 P0 5 KSI5 58 P3 2 INTO UPWEN 42 AD4 P0 4 KSI4 59 P3 3 INT1 OVRI 2 AD3 P0 3 KSI3 60 P3 4 TO KSO16 Dua 39 AD2 PO0 2 KSI2 61 P3 5 T1 KSO17 Dp4 40 AD1 P0 1 KSI1 62 P3 6 WR KSO18 ADO PO 0 KSIO 63 P3 7 RD KSO19 Processor Control Power amp Ground Bus Control amp Status Name Pin Name Pin Name Pin P3 2 INTO 4 Voc 1 P3 6 WR KSO18 8 P3 3 INT1 5 Voce 32 46 P3 7 RD KSO19 9 RST 23 AVcc 22 PSEN 43 XTAL1 20 Vss 31 47 ALE 44 XTAL2 21 Vise ML EA 45 intel PIN DESCRIPTIONS Table B 6 64 pin QFP Signal Assignments Arranged by Functional Category
165. 7 0 T20E DCEN Tee Ud Function 7 2 Reserved Values read from these bits are indeterminate Write zeros to these bits 1 T20E Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter C 52 TCON Timer Counter Control Register Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1 REGISTERS Address 88H Reset State 0000 0000B 7 0 1 TR1 TFO TRO Et 171 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by firmware to turn timer 1 on off 5 TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 Timer 0 Run Control Bit Set cleared by firmware to turn timer 0 on off 3 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1
166. 7 6 2 2 Connectivity Due Physical Connect Disconnect 7 26 7 6 2 3 Embedded Function Suspend and Resume 7 26 7 7 HUB POWER DISTRIBUTION detenis aseapua noari ei aasien aa aaa 7 27 7 7 1 Port Power Switching do mH DERI 7 27 2 Overcurrent Detection auc eren dee need ce e nete i hh a 7 29 73 Ganged Power Ernable 4 uie iHe EP HRS 7 29 7 8 HUB DEVIGE SIGNALES 2 1 7 peu edet nS e Sat ee ee dhe eee 7 30 CHAPTER 8 USB PROGRAMMING MODELS 8 1 OVERVIEW OF PROGRAMMING MODELS eene 8 1 8 1 1 Enumieraltlor 3 e th Ree He RR ERE 8 2 9 1 2 Adle State sss i ie Ba ee ER iius 8 3 8 1 3 Transmit and Receive Routines 0 0 eee eeeseeeeseeeeeeeeeeseneeeeeeeeeeaeeeeseaeeeeeeeeneeeeeneees 8 3 8614 USB Interrupts caine eine aie ed 8 4 8 2 TRANSMIT OPERATIONS 8 4 8 2 1 OVGIVIeW asin none Rep uh et ee a ete a 8 4 8 2 2 Pre transmit Operations tr HERR Ret RR Rs 8 7 8 2 3 Post transmit Operations tenente nennen nns 8 8 8 3 HEGEIVE OPERATIONS bun REDDE 8 10 8 3 1 QVetVIeW xccl sete Bt eite ete 8 10 8 3 2 Operations arainn e eaae ta raa a nnnm etre Sa nennen ens 8 11 8 4 SETUP TOKEN fs iie ERE te e Ed EIE IE Ed 8 14 8 5 START OF FRAME SOF TOKEN eseeeesseeeeee nenne
167. 8 67 67 DEC RO 00 12 34 58 67 67 CJNE R1 2AH LOOP loop for R1 A 2DH 00 12 38 45 67 45 loop for R1 A 2CH 00 18 23 45 67 23 loop for R1 A 2BH 08 01 23 45 67 01 CLR A 08 01 23 45 67 00 XCH A 2AH 00 01 23 45 67 08 Figure 4 3 Shifting BCD Number One Digit Right First pointers R1 and RO are set up to point to the two bytes containing the last four BCD digits Then a loop is executed which leaves the last byte location 2EH holding the last two digits of the shifted number The pointers are decremented and the loop is repeated for location 2DH The CJNE instruction Compare and if Not Equal is a loop control that will be described later The loop is executed from LOOP to CJNE for R1 2EH 2DH 2CH and 2BH At that point the digit that was originally shifted out on the right has propagated to location 2AH Since that loca tion should be left with Os the lost digit is moved to the Accumulator 4 1 5 2 External RAM Table 4 6 shows a list of the Data Transfer instructions that access external Data Memory Only indirect addressing can be used The choice is whether to use a one byte address Ri where Ri can be either RO or R1 of the selected register bank or a two byte address DPTR The disad vantage to using 16 bit addressees if only a few K bytes of external RAM are involved is that 16 bit addresses use all 8 bits of Port 2 as address bus On the other hand 8 bit addresses allow one to address a few K bytes of
168. 8FH page 6 14 for the device The host PC assigns the address and informs the device via endpoint 0 FIE USB Function Interrupt Enable Register Enables and disables A2H page 5 9 the receive and transmit done interrupts for the function endpoints FIFLG USB Function Interrupt Flag Register Contains the USB COH page 5 11 function s transmit and receive done interrupt flags for non isochronous endpoints RXCNTL Receive FIFO Byte Count Low Register Stores the byte count E6H page 6 26 for the data packets received in the receive FIFO specified by EPINDEX RXCON Receive FIFO Control Register Controls the receive FIFO E4H page 6 29 specified by EPINDEX RXDAT Receive FIFO Data Register Receive FIFO data is read from E3H page 6 26 this register specified by EPINDEX RXFLG Receive FIFO Flag Register These flags indicate the status of E5H page 6 31 data packets in the receive FIFO specified by EPINDEX RXSTAT Endpoint Receive Status Register Contains the endpoint E2H page 6 11 status of the receive FIFO specified by EPINDEX TXCNTL Transmit Count Low Register Stores the byte count for the F6H page 6 16 data packets in the transmit FIFO specified by EPINDEX TXCON Transmit FIFO Control Register Controls the transmit FIFO F4H page 6 19 specified by EPINDEX TXDAT Transmit FIFO Data Register Transmit FIFO data is written to F3H page 6 16 this register specified by EPINDEX TXFLG Transmit Flag Register These flags indicate the status o
169. 8x931AA 8x931HA Universal Serial Bus Peripheral Controller User s Manual September 1997 Information in this document is provided in connection with Intel products No license express or implied by estoppel or oth erwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 7641 Mt Prospect IL 60056 764 or call 1 800 879 4683 Copyright Intel Corporation 1997 Third party brands and names are the property of their respective owners intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANWAL CONTENTS nre eere HR ERR RU A REPRE RR RR 1 1 1 2 NOTATIONAL C
170. 8x931AA 8x931HA USER S MANUAL intel can be repeated is considered lossless data Automatic adjustment of the FIFO markers and point ers is accomplished by the function interface hardware Manual adjustment is accomplished by the 8x931 firmware 8 1 4 USB Interrupts For an explanation of the USB global suspend resume function hub and SOF interrupts see Chapter 5 Interrupt System 8 2 TRANSMIT OPERATIONS 8 2 4 Overview A transmit operation occurs in three major steps Pre transmit data preparation by firmware 2 Data packet transmission by function interface hardware 3 Post transmit management by firmware These steps are depicted in a high level view of transmit operations Figure 8 2 The pre trans mit and post transmit operations are executed by the two firmware routines shown on the left side of the figure Function interface hardware right side of the figure transmits the data packet over the USB line Details of these operations are described in Pre transmit Operations on page 8 7 and Post transmit Operations on page 8 8 Transmit operations for non isochronous data begin with an interrupt request from the embedded function e g a keyboard entry The pre transmit routine ISR for the function writes the data from the function to the transmit FIFO where it is held until the next IN token Upon receipt of the next valid IN token the function interface shifts the data out of the FIFO and transmits it over
171. 8x931HA USER S MANUAL Table C 4 I O Port SFRs Mnemonic Name Address PO Port 0 80H P1 Port 1 90H P2 Port 2 AOH P3 Port 3 BOH Table C 5 Serial SFRs Mnemonic Name Address SCON Serial Control 98H SBUF Serial Data Buffer 99H SADEN Slave Address Mask B9H SADDR Slave Address A9H Table C 6 USB Function SFRs Mnemonic Name Address EPCON Endpoint Control Register E1H EPINDEX Endpoint Index Register F1H FADDR Function Address Register 8FH RXCNTL Receive FIFO Byte Count Low Register E6H RXCON Receive FIFO Control Register E4H RXDAT Receive FIFO Data Register E3H RXFLG Receive FIFO Flag Register E5H RXSTAT Endpoint Receive Status Register E2H TXCNTL Transmit Count Low Register F6H TXCON Transmit FIFO Control Register F4H TXDAT Transmit FIFO Data Register F3H TXFLG Transmit Flag Register F5H TXSTAT Endpoint Transmit Status Register F2H 4 REGISTERS Table C 7 USB Hub SFRs Mnemonic Name Address HADDR Hub Address Register 97H HPCON Hub Port Control CFH HPINDEX Hub Port Index Register D4H HPPWR Hub Port Power Control 9AH HPSC Hub Port Status Change D5H HPSTAT Hub Port Status D7H HSTAT Hub Status and Configuration AEH Table C 8 Timer Counter SFRs Mnemonic Name Address TLO Timer Counter 0 Low Byte 8AH THO Timer Counter 0 High Byte 8CH TL1 Tim
172. 931HA USER S MANUAL intel TXCON Continued Address F4H Endpoint indexed Reset State 0100B USB Transmit FIFO Control Register Controls the transmit FIFO specified by EPINDEX 7 0 TXCLR TXISO ATM ADVRM REVRP Bit Bit Function Number Mnemonic unctio 1 ADVRM Advance Read Marker Control non ATM mode only Setting this bit prepares for the next packet transmission by advancing the read marker to the origin of the next data packet the position of the read pointer Hardware clears this bit after the read marker is advanced This bit is effective only when the REVRP ATM and TXCLR bits are all clear 0 REVRP Reverse Read Pointer Control non ATM mode only In the case of a bad transmission the same data stack may need to be available for retransmit Setting this bit reverses the read pointer to point to the origin of the last data set the position of the read marker so that the FIU can reread the last set for retransmission Hardware clears this bit after the read pointer is reversed This bit is effective only when the ADVRM ATM and TXCLR bits are all clear ATM mode is recommended ADVRM and REVRP which control the read marker and read pointer when ATM 0 are used for test purposes TXDAT Address F3H Endpoint indexed Reset State xxxxB USB Transmit FIFO Data Register Data to be transmitted by the FIFO specified by EPINDEX is first
173. 9H Reset State XXXX xxxxB Serial Data Buffer Writing to SBUF loads the transmit buffer of the serial I O port Reading SBUF reads the receive buffer of the serial I O port 7 0 Data Sent Received by Serial I O Port Bit Bit Number Mnemonic 7 0 SBUF 7 0 Function C 46 intel REGISTERS SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode Select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Functio 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by firmware not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Firmware writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 Serial Port Mode Bit 1 Firmware writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART 64 or Fog 32 1 1 3 9 bit UART Variable Fog Oscillator frequency Select by programming the SMOD1 bit in the PCON register see section Baud Rates on page 11 10 5 Serial Port
174. A 8x931HA USER S MANUAL intel 7 5 USB HUB PORTS In addition to the root port port 0 and the embedded function addressed by port 1 the hub con tains four external downstream ports ports 2 3 4 and 5 7 5 4 Controlling a Port Using HPCON You can change a port s status by writing an encoded hub port control command to the hub port control register HPCON as shown in Figure 7 9 All ports can be controlled by HPCON using the HPINDEX SFR for indexing See Hub Port Indexing Using HPINDEX on page 7 23 for a description of how port indexing works Table 7 6 on page 7 16 gives a complete description of the encoded hub port control commands The 8x93 1 hardware can also change the status of a port and some port features i e low speed full speed and connect disconnect can only be changed by hardware 8x931 hardware ignores certain USB port requests if the request has no meaning within the con text of the current port state For example there is no need to activate power to a port that is en abled disabled or suspended because a port in one of these states already has power applied An activate power request SetPortFeature with port power feature selector is supported for a given port only when that port is in the powered off state For all other states the request is ignored by hardware Table 7 5 depicts the state related USB requests and the port states for which they are ignored Upon receipt of a state related USB reque
175. A JBC jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL E PX Y move carry bit to bit Y of port X CLR PX Y clear bit Y of port X SETB PX Y set bit Y of port x It is not obvious that the last three instructions in Table 9 2 are read modify write instructions These instructions read the port all eight bits modify the specifically addressed bit and write the new byte back to the latch These read modify write instructions are directed to the latch rath er than the pin in order to avoid possible misinterpretation of voltage and therefore logic levels at the pin For example a port bit used to drive the base of an external bipolar transistor cannot rise above the transistor s base emitter junction voltage a value lower than V With a logic one written to the bit attempts by the CPU to read the port at the pin are misinterpreted as logic zero A read of the latch rather than the pin returns the correct logic one value 9 5 8x931AA 8x931HA USER S MANUAL intel 9 6 QUASI BIDIRECTIONAL PORT OPERATION Port 1 port 2 and port 3 have fixed internal pullups and are referred to as quasi bidirectional ports When configured as an input the pin impedance appears as logic one and sources current see the 8x93 1 datasheet in response to an external logic zero condition Port 0 is a
176. A SFRs are presented in Appendix C Registers 8 931 SFRs are shown in Appendix E 8x931AA Design Con siderations The content of each register following device reset is given An x indicates the bit value following reset is indeterminate Figure 3 5 gives a brief look at the Special Function Register SFR space SFRs include the Port latches timers peripheral controls etc These registers can only be accessed by direct addressing FFH EOH ACC Register mapped ports Addresses that end in P OH or 8H are also BOH ort 3 Bit addressable Port Pins PSW 90H Port 1 etc 80H Port 0 Figure 3 5 SFR Space Blank locations in the SFR map are unimplemented i e no register exists If an instruction at tempts to write to an unimplemented SFR location the instruction executes but nothing is actu ally written If an unimplemented SFR location is read it returns an unspecified value Endpoint indexed SFRs are implemented as banks of registers There is a set or bank of registers for each endpoint pair Endpoint indexed SFRs are accessed by means of the SFR address and an index value The EPINDEX register specifies hub function and the endpoint number which serves as the index value See Endpoint indexed SFRs on page 6 5 and Hub Endpoint Index ing Using EPINDEX on page 7 11 Port indexed SFRs HPCON HPSC and HPSTST are implemented in a similar manner The
177. Address CFH Reset State xxxx x000B Hub Port Control Register Firmware writes to this register to disable enable reset suspend and resume a port 7 0 HPCON2 HPCON1 HPCONO Bit Bit Number Mnemonic Ponetion 7 3 Reserved Write zeros to these bits 2 0 HPCON 2 0 Encoded Hub Port Control Commands All bits should be set and cleared by firmware after receiving the USB requests ClearPortFeature and SetPortFeature from the host The bits are encoded as follows all other bit combinations are ignored by the hardware 000 Disable port 001 Enable port 010 Reset and enable port 011 Suspend port 100 Resume port See Table 7 6 on page 7 16 for a complete description of the encoded hub port control commands intel REGISTERS HPINDEX Address D4H Reset State x000B Hub Port Index Register This register contains the binary value of the port whose HPSC HPSTAT and HPCON registers are to be accessed 7 0 aes aoe HPIDX2 HPIDX1 HPIDXO Bit Bit Number Mnemonic Function 7 3 Reserved Write zeros to these bits 2 0 HPIDX 2 0 Port Index Select Used to select the port to be indexed by the following registers HPSC HPSTAT and HPCON This register is hardware read only The ports are addressed using the following HPIDX2 0 bit combinations Port 1 001 internal port P
178. Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints D 16 intel DATA FLOW MODEL Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB Event FIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void Setup 1 1 rupt Response CPU reads 11 no no no no no 1 None NAKs Firmware should FIFO chg chg chg chg chg future check RXURF bit causes FIFO transaction before writing error S FFRC RXFFRC not written yet CPU reads 10 01 no no no no no 1 None NAKs Firmware should FIFO chg chg chg chg chg future check bit causes FIFO transaction before writing error Set S FFRC RXFFRC NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints 8x931AA 8x931HA USER S MANUAL intel Table D 5 Isochronous Receive Data Flow in Dual packet Mode RXSPM 0 New at next SOF RX RX RX FIF R
179. An external latch can use ALE to demultiplex the address from the address data bus AVcc PWR VO Analog Vec A separate Ve input for the phase locked loop circuitry USB Port 0 and Dy are the data plus and data minus lines of USB port 0 the upstream differential port These lines do not have internal pullup resistors For low speed devices provide an external 1 5 KQ pullup resistor at Dyo For full speed devices provide an external 1 5 KQ pullup resistor at Dpo NOTE For the 8x931AA either or Dy must be pulled high Otherwise a continuous SEO USB reset will be applied to these inputs causing the 8 931 to stay in reset EA External Access Directs program memory accesses to on chip or off chip code memory For EA strapped to ground all program memory accesses are off chip For EA strapped to Voc program accesses on chip ROM if the address is within the range of the on chip ROM otherwise the access is off chip The value of EA is latched at reset For devices without on chip ROM EA must be strapped to ground ECAP FSSEL External Capacitor Connect a 1 uF or larger capacitor between this pin and Vas to ensure proper operation of the differential line drivers Full speed Select See Table E 3 on page E 9 INT1 0 KSI7 0 External Interrupts 0 and 1 These inputs set the IE1 0 interrupt flags in the TCON register Bits IT1 0 in TCON select the triggering
180. At S6P2 of the following cycle hardware shifts the LSb DO onto the RXD pin At S3PI of the next cycle the TXD pin goes low for the first clock signal pulse Shifts continue every peripheral cycle In the ninth cycle after the write to SBUF the MSB D7 is on the RXD pin At the beginning of the tenth cycle hardware drives pin high and asserts TI SIP1 to indicate the end of the transmission 11 2 1 2 Reception Mode 0 To start a reception in mode 0 write to the SCON register Clear bits SMO SM1 and RI and set the REN bit Hardware executes the write to SCON in the last phase S6P2 of a peripheral cycle Figure 11 3 In the second peripheral cycle following the write to SCON TXD goes low at S3P1 for the first intel SERIAL I O PORT clock signal pulse and the LSb DO is sampled on the RXD pin at S5P2 The DO bit is then shift ed into the shift register After eight shifts at S6P2 of every peripheral cycle the LSb D7 is shift ed into the shift register and hardware asserts RI S1P1 to indicate a completed reception Firmware can then read the received byte from SBUF IB Bus Transmit Interrupt Request RI TI Serial I O Control SUN Figure 11 1 Serial Port Block Diagram A4123 01 8x931AA 8x931HA USER S MANUAL intel SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode Select bits and t
181. B devices Any 8 bit unit of data Glossary 1 8x931AA 8x931HA USER S MANUAL intel clear code memory control transfer dir8 DPTR deassert device address doping edge triggered encryption array endpoint EPP external address Glossary 2 The term clear refers to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value See program memory One of four USB transfer types Control transfers support configuration command status type communications between client and function An 8 bit direct address This can be a memory address or an SFR address The 16 bit data pointer The term deassert refers to the act of making a signal inactive disabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The address of a device on the Universal Serial Bus The device address is the default address when the USB device is first powered or reset Hubs and functions are assigned a unique device address by USB firmware The process of introducing a periodic table Group or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results
182. BUILDER firmware hypertext manuals and datasheets firmware drivers firmware upgrades application notes and utilities and quality and reliability data Any customer with a PC and modem can access the BBS The system provides automatic config uration support for 1200 through 19200 baud modems Use these modem settings no parity 8 data bits and stop bit N 8 1 To access the BBS just dial the telephone number see Table 1 1 on page 1 7 and respond to the system prompts During your first session the system asks you to register with the system oper ator by entering your name and location The system operator will set up your access account within 24 hours At that time you can access the files on the BBS NOTE In the U S and Canada you can get a BBS user s guide a master list of BBS files and lists of FaxBack documents by calling 1 800 525 3019 Use these modem settings no parity 8 data bits and 1 stop bit N 8 1 1 8 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW The 8x931AA and 8x931HA are PC peripheral controllers for Universal Serial Bus USB appli cations These peripheral controllers provide the means for connecting PC peripherals such as monitors keyboards joysticks telephones and modems to USB equipped personal computers For keyboard applications both devices include an on chip keyboard control interface The USB material in this document relies heavily on the Unive
183. DEX is first written to this register 7 0 Transmit Data Byte Bit Bit Number Mnemonic Function 7 0 TXDAT7 0 Transmit Data Byte write only To write data to the transmit FIFO write to this register The write pointer is incremented automatically after a write For hub endpoint 1 TXDAT is used in a different manner See Figure 7 7 on page 7 12 Figure 6 8 TXDAT Transmit FIFO Data Register 6 3 3 Transmit FIFO Byte Count Register TXCNTL The transmit FIFO byte count register is used as a five bit ring buffer as shown in Figure 6 9 TXCNTL Address F6H Endpoint indexed Reset States xxxxB Transmit FIFO Byte count Register Ring buffer used to store the byte count for the data packets in the transmit FIFO specified by EPINDEX 7 0 BC4 BC3 BC2 BC1 BCO bero FHBODOU 7 5 Reserved Write zeros to these bits 4 0 BC4 0 Transmit Byte Count write conditional read Five bit ring buffer Stores transmit byte count for endpoints 0 and 2 Byte count registers not implemented for hub endpoint 1 tt Read these bits only if TXFIF1 0 0 otherwise underrun errors may occur Figure 6 9 TXCNTL Transmit FIFO Byte Count Register 6 16 USB FUNCTION intel TXCNTL stores the number of bytes in either of the two data sets data set 0 050 and data set 1 ds1 The FIFO logic for maintaining the data sets assum
184. EN Program Store Enable Read signal output Asserted for read a accesses to external program memory RD Read Read signal output Asserted for read accesses to P3 7 KSO19 external data memory RST Reset Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device The port pins are driven to their reset conditions when a voltage greater than Vj is applied whether or not the oscillator is running This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation RXD lO Receive Serial Data sends and receives data in serial P1 6 mode 0 and receives data in serial I O modes 1 2 and 3 SOF Start of Frame Start of frame pulse Active low Asserted for 8 P3 1 states see Table 2 3 on page 2 9 when frame timer is locked to USB frame timing and SOF token or artificial SOF is detected T1 0 Timer 1 0 External Clock Input When timer 1 0 operates asa P3 5 4 KSO17 16 counter a falling edge on the T1 0 pin increments the count T2 lO Timer 2 Clock Input Output For the timer 2 capture mode P1 0 this signal is the external clock input For the clock out mode it is the timer 2 clock output E 7 8x931AA 8x931HA USER S MANUAL Table E 2 8x931AA Signal Descriptions Contin
185. ET Firmware This USB request resets the downstream ports The number of the port to be reset is included in the request from the host To implement this routine firmware must write 010 to bits 2 0 of the port s HPCON SER The flowchart in Figure 8 15 illustrates the process Refer to Section 11 6 2 of the Universal Serial Bus Specification for a detailed description of this USB command 8 27 8x931AA 8x931HA USER S MANUAL intel SetPortFeature PortReset Write xxxB to HPINDEX xxx port number to select the port Shut down application code Is Reset peripherals etc for port 4 for embedded function Write 010B to HPCON to reset the port A5167 01 Figure 8 15 SetPortFeature PORT RESET Routine If port 4 is specified firmware must reset all non hub functionality in the microcontroller Firm ware must gracefully shut down the application code peripherals etc prior to writing to port 4 s HPCON Upon writing to port 4 s HPCON SFR a hardware reset is applied to the FIU and function FIFOs When this reset is applied the embedded function s EPCON FIFLG FIE TXSTAT RXSTAT TXCON RXCON FADDR and PCONI SFRs are reset to their default values as are the SO FACK ASOF SOFIE and SOFODIS bits of SOFH The EPINDEX and SOFL SFRs remain un changed These SFRs are reset immediately after the write to HPCON however bus traffic to the embedded function remains inactive for 15 ms You may use
186. F RXFIF is incremented by USB and decremented by firmware Therefore setting RXFFRC will decrement RXFIF immediately However a successful USB transaction anytime in a frame will only increment RXFIF at SOF RXERR RXACK and RXVOID can only be caused by USB thus they are updated at the end of transaction D 20 intel 8x931AA Design Considerations APPENDIX E 8x931AA DESIGN CONSIDERATIONS This appendix describes the differences between the hubless 8x931AA and the 8x931HA The 8x931HA is described in the rest of this document E 1 DIFFERENCES BETWEEN THE 8x931AA AND THE 8x931HA The 8x931AA differs from the 8x931HA in many ways including The 8x931AA does not support hub operations and has no hub interface hub repeater or hub FIFOs These features included in the 8x931HA only are discussed in Universal Serial Bus Module on page 2 11 and Hub Operation on page 8 17 The 8x931AA has no hub interrupt The 8x931HA hub interrupt is discussed in USB Hub Interrupt on page 5 15 Because there is no on chip hub Chapter 7 USB Hub does not apply to the 8x931AA The 8x931AA has no Hub Address Register HADDR so its enumeration process is simpler than the 8x931HA enumeration process given in Enumeration on page 8 2 The 8x931AA enumeration process is given in 8x931AA Enumeration Process on page E 2 The hub programming models described in Hub Operation on page 8 17 do not apply t
187. FO Byte Count Registers RXCNTL The receive FIFO byte count register RXCNTL is used as five bit ring buffer to accommodate packet sizes of 0 to 16 bytes This format is shown in Figure 6 14 RXCNTL Address E6H Endpoint indexed Reset State xxxxB Receive FIFO Byte count Low Register Ring buffer used to store the byte count for the data packets received in the receive FIFO specified by EPINDEX 7 0 BC4 BC3 BC2 BC1 BCO Bit Bit Number Mnemonic Function 7 5 Reserved Write zeros to these bits 4 0 BC4 0 Receive Byte Count Five bit ring buffer Stores receive byte count Not implemented for hub endpoint 1 Figure 6 14 RXCNTL Receive FIFO Byte Count Register RXCNTL stores the number of bytes in either of the two data sets data set 0 450 and data set 1 ds1 The FIFO logic for maintaining the data sets assumes that data is written to the FIFO in the following sequence 6 26 intel USB FUNCTION 1 The USB interface writes the received data packet into the receive FIFO 2 USB interface writes the number of bytes written into the receive FIFO to the byte count register RXCNTL The CPU reads the byte count register to determine the number of bytes in the set The receive byte count register has a read write index that allows it to access the byte count for either of the two data sets This is similar to the methodology used for the transmit by
188. FO was empty FIFO future when read causes FIFO transaction Should always error S check RXFIF bits before reading 01 10 Received 01 10 None NAK FIFO not reagy OUT token but RXIE 0 Received 01 10 None None FIFO not loaded OUT token chg chg chg chg chg Write pointer but timed out reversed waiting for data Received 11 0 1 0 0 no no Set ACK Received no OUT token chg chg receive errors advance no errors interrupt write marker NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints 8x931AA 8x931HA USER S MANUAL intel Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event bee ERR ACK Void Setup ri yd pes Response Comments Received 01 10 1 0 0 0 no no Set Time out Write pointer OUT token chg chg receive reversed data CRC or interrupt Possible to have bit stuff error RXERR cleared by hardware before seen by firmware Received 01 10 1 0 0 0 1 no Set Time out Only RXOVF OUT token chg receive NAK FIFO error can FIFO error interrupt future occur requires occurs transaction firmware S inte
189. For a non isochronous transfer the function interface generates a transmit done interrupt The purpose of the post transmit service routines is to manage the transmitter s state and to ensure data integrity for the next transmission For isochronous data the post transmit routine should be embedded within the transfer request routine because both are triggered by an SOF The flow of operations of typical post transmit ISRs is illustrated in Figure 8 4 non isochronous data and Figure 8 5 isochronous data Start Transmit Done ISR Identify Interrupt and Endpoint check FTXDx bits in FIFLG register Clear Interrupt Flag FTXDx Bit Read Transaction Status TXSTAT Register TXERR 1 Failed CRC Bit stuffing or Timeout from Host No No TXACK 1 Underrun Flag 21 Error in Transmit FIFO Data Error recovery Advance Transmit FIFO to Reverse Transmit FIFO to Next Packet Transmit Current Packet Retry RETI Buffer Segmentation Management Executed automatically by hardware based on transaction status if ATM bit in TXCON is set A5072 01 Figure 8 4 Post transmit ISR Non isochronous 8 8 intel USB PROGRAMMING MODELS Start SOF ISR For Each Endpoint Read Transaction Status TXSTAT Transmit Error TXACK 1 No Yes TXERR 1 Failed CRC Bit Stuffing or Timeout from Host Error in Transmi
190. H1 7 0 High byte of the timer 1 timer register TL1 7 0 Low byte of the timer 1 timer register C 55 8x931AA 8x931HA USER S MANUAL intel TH2 TL2 Address TH2 CDH TL2 CCH Reset State 0000 0000B TH2 TL2 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 2 7 0 High Low Byte of Timer 2 Register Bit Bit Number Mnemonic Function 7 0 TH2 7 0 High byte of the timer 2 timer register TL2 7 0 Low byte of the timer 2 timer register TXCNTL Address F6H Endpoint indexed Reset States xxxxB Transmit FIFO Byte count Register Ring buffer used to store the byte count for the data packets in the transmit FIFO specified by EPINDEX 7 0 BC4 BC3 BC2 BC1 BCO Bit Bit i Number Mnemonic Function 7 5 Reserved Write zeros to these bits 4 0 BC4 0 Transmit Byte Count write conditional read Five bit ring buffer Stores transmit byte count for endpoints 0 and 2 Byte count registers are not implemented for hub endpoint 1 Read these bits only if TXFIF1 0 0 otherwise underrun errors may occur C 56 REGISTERS TXCON Endpoint indexed Address F4H Reset State 0100B USB Transmit FIFO Control Register Controls the transmit FIFO specified by EPINDEX 7 TXCLR 0 TXISO ATM ADVRM REVRP Bit Number Bit Mnemonic Function 7 6 4 TXCLR T
191. HPSC 7 21 C 21 HPSTAT 7 18 C 23 HSTAT 7 9 C 25 Hub See USB hub l T O ports 9 1 9 8 external memory access 9 7 latches 9 2 loading 9 7 pullups 9 6 quasi bidirectional 9 6 Index 2 intel See also Ports 0 3 Idle mode 2 6 14 1 14 6 14 7 entering 14 6 exiting 13 5 14 7 external bus 15 2 IENO 5 4 5 6 5 24 11 11 14 9 C 3 C 27 5 4 5 25 C 3 C 28 INC instruction A 4 Instruction set MCS 51 architecture A 1 A 58 INTI 9 1 INT1 0 5 1 9 1 10 1 10 2 pulse width measurements 10 10 INT2 interrupt 5 6 Intel Architecture Labs 1 8 Interrupt request 5 1 cleared by hardware 5 6 5 7 Interrupt service routine exiting idle mode 14 7 exiting powerdown mode 14 8 Interrupts 5 1 5 32 detection 5 6 edge triggered 5 6 enable disable 5 24 exiting idle mode 14 7 exiting powerdown mode 14 8 external INT1 0 5 1 5 6 14 9 global enable 5 24 global resume 5 17 global resume GRSM 14 5 14 7 C 38 global suspend GSUS 14 5 14 7 C 38 handler 2 11 hub 5 7 keyboard scan 5 6 5 7 level triggered 5 6 priority 5 1 5 4 5 6 5 7 5 26 5 29 C 3 priority within level 5 26 request See Interrupt request sampling 5 6 service routine ISR 5 6 5 7 sources 5 2 timer counters 5 7 vectors 5 6 5 7 IPHO 5 4 5 27 C 3 C 29 bit definitions 5 26 IPHI 5 4 5 29 C 3 C 31 bit definitions 5 26 IPLO 5 4 5 28 C 3 C 30 intel bit definitions 5 26
192. Hub Descriptors heic ER pete et rtt eni ides 7 7 7 2 2 Hub Address Register HADDR senem 7 8 8x931AA 8x931HA USER S MANUAL intel 7 3 HUB STATUS ei enenatis m etenim 7 9 7 4 USB HU B ENDPOINITS 2 m cR Ee ced ee 7 10 7 4 1 Hub Endpoint Indexing Using EPINDEX 7 11 7 42 H b Endpoint erred etin f EE HERI aede res 7 11 7 4 8 Hub Endpoint Transmit and Receive Operations 7 12 7 5 USBHU B PORTS pene cetera d tuii s Ete m eee 7 14 7 5 1 Controlling a Port Using HPCON eene nennen nennen nnne 7 14 7 5 2 Examining a Port s Status Using HPSTAT seen 7 17 7 5 8 Monitoring Port Status Change Using HPSC 7 20 7 5 4 Hub Port Indexing Using HPINDEX sssseeenn emen 7 23 7 5 5 Embedded Functl n iuit E REPRE ERROR 7 24 7 5 5 1 Embedded Function Reset 7 24 7 5 5 2 Embedded Function Remote Wake up e 7 25 7 6 SUSPEND AND RESUME ede eder ute qe etr e Lade ta Tae lei ace 7 25 7 6 1 Hub Global Suspend and Resume sse 7 25 7 6 2 Remote Connectivity a a ea a aana AEE EaR Rai 7 25 76 21 Resume CONNECTIVITY 7 25
193. IE decodes and takes care of all packet types and packet fields mentioned in Protocol Lay er chapter of Universal Serial Bus Specification The FIU communicates data information and handshaking instructions to the SIE Programmers should consult the Interconnect Description USB Devices and USB Host chapters of Universal Serial Bus Specification for detailed in formation on how the host and function communicate 6 6 SETUP TOKEN RECEIVE FIFO HANDLING SETUP tokens received by a control endpoint must be ACKed even if the receive FIFO is not empty When a SETUP token is detected by the FIU the FIU sets the STOVW bit of RXSTAT and then flushes the receive FIFO by hardware setting the RXCLR bit of RXCON The STOVW indicates a SETUP initiated over write flush is in progress After the SETUP transaction is completed i e ACK handshake the FIU clears STOVW and sets EDOVW indicating the re ceive FIFO over write is complete and FIFO contents are stable Reception of any SETUP packet regardless of whether the receive FIFO is full or empty always sequences through the STOVW EDOVW sequence described above Note that if the receive FIFO flush occurs in the middle of an 8x931 CPU data read cycle from a previous USB transaction the receive FIFO could underrun thus setting the RXURF bit of RXFLG and positioning the read pointer in an unknown state To prevent this STOVW resets and locks the read pointer The read pointer will remain
194. IFO Empty Flag read only Hardware sets this flag when the write pointer is at the same location as the read pointer and the write pointer equals the write marker and neither pointer has rolled over Hardware clears the bit when the empty condition no longer exists This is not a sticky bit and always tracks the current status of the receive FIFO regardless of ISO or non ISO mode RXFULL Receive FIFO Full Flag read only Hardware sets this flag when the write pointer has rolled over and equals the read pointer Hardware clears the bit when the full condition no longer exists This is not a sticky bit and always tracks the current status of the receive FIFO regardless of ISO or non ISO mode When set all transmissions are NAKed 6 32 Figure 6 16 RXFLG Receive FIFO Flag Register Continued intel USB FUNCTION RXFLG Continued Address E5H Endpoint indexed Reset State 00xx 1000B Receive FIFO Flag Register These flags indicate the status of data packets in the receive FIFO specified by EPINDEX 7 0 RXFIF1 RXFIFO RXEMP RXFULL RXURF RXOVF Bit Mnemonic RXURF Function Number Receive FIFO Underrun Flagt Hardware sets this bit when an additional byte is read from an empty receive FIFO or RXCNTL Hardware does not clear this bit so you must clear it in firmware When the receive FIFO underruns the read p
195. IMER COUNTERS Interrupt Request T2EX 7 EXEN2 A5204 01 Figure 10 10 Timer 2 Clock Out Mode Table 10 3 Timer 2 Modes of Operation Mode RCLK OR TCLK CP RL2 2 2 in T2CON in T2MOD Auto reload Mode 0 0 0 Capture Mode 0 1 0 Baud Rate Generator Mode 1 X X Programmable Clock Out X 0 1 10 15 8x931AA 8x931HA USER S MANUAL intel T2MOD Address S C9H Reset State xx0OB Timer 2 Mode Control Register Contains the timer 2 down count enable and clock out enable bits for timer 2 7 0 Es m T20E DCEN Tm Function 7 2 Reserved Values read from these bits are indeterminate Write zeros to these bits 1 T20E Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter Figure 10 11 T2MOD Timer 2 Mode Control Register 10 16 intel TIMER COUNTERS T2CON Timer 2 Control Register Contains the receive clock transmit clock and capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 Address S C8H Reset State 0000 0000B 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit gt Number M
196. Interrupt Enable Setting this bit enables all interrupts that are individually enabled by the other bits of this register as well as the interrupts enabled by the bits in the IEN1 SFR Clearing this bit disables all interrupts except the TRAP interrupt which are always enabled Reserved Write a zero to this bit ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt ET1 ETO Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt External Interrupt 1 Enable Setting this bit enables external interrupt 1 Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt External Interrupt 0 Enable Setting this bit enables external interrupt 0 NOTE Note that because IENO appears in the first SFR column it is a bit addressable SFR 5 24 Figure 5 10 IENO USB Interrupt Enable Register 0 INTERRUPT SYSTEM IEN1 Interrupt Enable Register 1 Contains the enable bits for the USB interrupts Address B1H Reset State xxxx x000B 7 0 EX2 ESR EF ESOF Bit Bit Number Mnemonic Function 7 EX2 External Interrupt 2 Enable Keyboard Scan Setting this bit enables the external interrupt used for the keyboard scan NOTE
197. Isochronous Receive Data Flow in Dual packet Mode RXSPM 0 D 18 8x931AA Signals Arranged by Functional Category E 5 8x931AA Signal Descriptions E 6 8x931AA Operating Frequencies cccccscceesscceeseeeeeeeceeseeeeeeaeeeessaeeeseneeessneeeesnees E 9 8x99 TAA SFERUCMAaD 5 te beeen rede Tp e reco cate ce ore E 10 intel Guide to this Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8x931 microcontroller for universal serial bus USB applications This manual is intended for use by both firmware and hardware designers familiar with the prin ciples of microcontroller architecture 1 1 MANUAL CONTENTS This chapter provides an overview of the manual with brief summaries of the chapters and appen dices It also explains the terminology and notational conventions used throughout the manual provides references to related documentation and tells how to contact Intel for additional infor mation Chapter 2 Architectural Overview provides an overview of device hardware It covers core functions CPU clock and reset unit and interrupts I O ports on chip memory the USB module and on chip peripherals timer counters and serial I O port Chapter 3 Address Spaces describes the three address spaces of the 8x931 memo
198. KEUP Configuration on page 8 17 Cancel stall for the specified endpoint See Hub Endpoint Control on page 7 11 CLEAR_FEATURE Endpoint 0 specified ENDPOINT_STALL 1 Load 80H into EPINDEX for hub endpoint 0 2 Clear RXSTL and TXSTL bits of EPCON SFR Endpoint 1 specified Clear EP1STL bit of HSTAT SFR 8x931AA 8x931HA USER S MANUAL Table 8 1 Firmware Actions for USB Requests Sent to Hub Continued USB Request Feature Selector Firmware Action Required Type 1 Store hub endpoint 1 configuration value from value field in memory SET_CONFIGURATION N A 2 Set EP1EN bit of HSTAT SFR Figure 7 6 on page 7 9 after the Status stage if 2 byte configuration value 0001H Read configuration value one byte from memory and GET_CONFIGURATION N A sendic the h st Device Read device descriptor from memory and transmit to GET_DESCRIPTOR GET_INTERFACE GET_STATUS USB host through hub endpoint 0 Configuration N A Device Read configuration interface endpoint and hub descriptors from memory and transmit to USB host through hub endpoint 0 Optional request for hubs which is not supported 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage Read HSTAT SFR bit HRWUPE Figure 7 6 on page 7 9 and power configuration from memory and transmit to USB host using hub endpoint 0 Interface Load 2 byte
199. L XRL XRL XRL addri1 dir8 A dir8 data A data A dir8 A Ri 7 JNZ ACALL JMP MOV MOV MOV MOV rel addr11 A DPTR A data dir8 Ri data_ Rn data data 8 SJMP AJMP MOVC DIV MOV MOV MOV rel addr11 A A PC AB dir8 dir8 dir8 Ri dir8 Rn 9 MOV ACALL MOVC SUBB SUBB SUBB SUBB DPTR addr11 A A DPTR A data A dir8 A Ri A Rn data16 A ORL AJMP INC MUL Reserved MOV MOV CY bit addr11 DPTR AB Ri dir8 Rn dir8 B ANL ACALL CPL CJNE CJNE CJNE CJNE CY bit addr11 CY A data rel A dir8 rel Ri data Rn data rel rel C PUSH AJMP CLR SWAP XCH XCH XCH dir8 addr11 CY A dir8 A Ri A Rn D ACALL DJNZ XCHD DJNZ addr11 dir8 rel A Ri Rn rel E MOV MOV MOV addr11 A dir8 A Ri A Rn F ACALL MOV MOV MOV adar1 1 dir8 A Ri A Rn A A 3 8x931AA 8x931HA USER S MANUAL intel INSTRUCTION SET SUMMARY This section contains tables that summarize the instruction set For each instruction there is a short description its length in bytes and its execution time in states and machine cycles A 3 1 Instruction Summaries Table A 7 Summary of Add and Subiract Instructions Add ADD lt dest gt lt sre gt dest opnd lt dest opnd src opnd Add with Carry ADDC lt dest gt lt src gt lt A src carry bit Subtract with Borrow SUBB lt dest gt lt sre gt A A src opnd carry bit Mnemonic lt dest gt lt src gt Notes Bytes Stat
200. LE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus Analog Voc A separate Vcg input for the phase locked loop circuitry USB Port 0 Root port Upstream port to the host PC Dpo and are the differential data plus and data minus signals of USB port 0 These lines do not have internal pullup resistors Provide an external 1 5 pullup resistor at Deo so the device indicates to the host that it is a full speed device NOTE low AND low signals an SEO USB reset causing the 8x931 to stay in reset P2 7 0 KS08 15 P0 7 0 KSIO 7 Dez Dus Dua Dp4 Des VO USB External Downstream Ports 2 3 4 5 These pins are the differential data plus and data minus lines for the four USB external downstream ports These lines do not have internal pulldown resistors Provide an external 15 KQ pulldown resistor at each of these pins If a port is not used it is still required to pull these 2 pins low externally similar to a disconnect so that the inputs are not floated EA External Access Directs program memory accesses to on chip or off chip code memory For EA strapped to ground all program memory accesses are off chip For EA strapped to Voc Program accesses on chip ROM if the address is within the range of the on chip ROM o
201. Marker X ACK Unchanged Advanced 0 NAK Reversed Unchanged 1 NAK Unchanged Advanced When this bit is set setting REVWP or ADVWM has no effect Hardware neither clears nor sets this bit This is a sticky bit that is not reset when RXCLR is set NOTE This bit should always be set except for testing ARM mode is recommended ADVWM and REVWP which control the write marker and write pointer when ARM 0 are used for test purposes Figure 6 15 RXCON Receive FIFO Control Register 6 29 8x931AA 8x931HA USER S MANUAL intel RXCON Continued Address E4H Endpoint indexed Reset State 0xx0 0100B Receive FIFO Control Register Controls the receive FIFO specified by EPINDEX 7 0 RXCLR RXFFRC RXISO ARM ADVWM REVWP Bit Bit Function Number Mnemonic unctio 1 ADVWM Advance Write Marker For non ARM mode only Set this bit to advance the write marker to the origin of the next data set Advancing the write marker is used for back to back receptions Hardware clears this bit after the write marker is advanced Setting this bit is effective only when the REVWP ARM and RXCLR bits are clear 0 REVWP Reverse Write Pointer For non ARM mode only Set this bit to return the write pointer to the origin of the last data set received as identified by the write marker The FIU can then receive the last data packet again and write to the receive FIFO starting from the same orig
202. NSTRUCTION SET REFERENCE Port 1 contains 5BH 01011101B After executing the instruction sequence CPL P1 1 CPL P1 2 port 1 contains 5BH 01011011B Encoding 1011 0010 bit addr CPL bit lt O bit Encoding 1011 0011 CPL CY CY Decimal adjust accumulator for addition Adjusts the 8 bit value in the accumulator that resulted from the earlier addition of two variables each in packed BCD format producing two 4 bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine XXXX1010 XXXX1 111 or if the AC flag is set six is added to the accumulator producing the proper BCD digit in the low nibble This internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all higher bits but it does not clear the CY flag otherwise If the CY flag is now set or if the upper four bits now exceed nine 1010XXXX 1111XXXX these four bits are incremented by six producing the proper BCD digit in the high nibble Again this sets the CY flag if there was a carry out of the upper four bits but does not clear the carry The CY flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition The OV flag is not affected All of this occurs during one instruction cycle Essentially this instruction performs the decimal conversion by ad
203. NTL 01 Unchanged 01 Wr TXCNTL 11 Unchanged 10 Wr TXCNTL 11 Unchanged 11 Wr TXCNTL 11 TXOVF 1 00 Adv RM 00 Unchanged 01 Adv RM 00 Unchanged 11 Adv RM 10 01 Unchanged 10 Adv RM 00 Unchanged XX Rev RP X Unchanged Unchanged In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF TXFIF is incremented by firmware and decremented by the USB Therefore writes to TXCNTL increment TXFIF immediately However a successful USB transaction any time within a frame decrements TXFIF only at SOF You must check the TXFIF flags before and after writes to the transmit FIFO and TXCNTL for traceability See the TXFLUSH bit in TXSTST NOTE To simplify firmware development configure control endpoints in single packet mode x lt lt lt KKK OK 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits When set all transmissions are NAKed Figure 6 11 TXFLG Transmit FIFO Flag Register 6 21 8x931AA 8x931HA USER S MANUAL intel TXFLG Continued Endpoint indexed Address Reset State F5H 00xx 1000B Transmit FIFO Flag Register These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX 7 0 TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF Bit Bit Number Mnemonic Function
204. O empty flag RXEMP bit in RXFLG to avoid reading a byte when the FIFO is empty 6 4 1 Receive FIFO Registers There are five registers directly involved in the operation of the receive FIFOs RXDAT the receive FIFO data register RXCNTL the receive FIFO byte count register RXCON the receive FIFO control register RXFLG the receive FIFO flag register These registers are endpoint indexed i e they are used as a set to control the operation of the receive FIFO associated with the current endpoint specified by the EPINDEX register Figures 6 13 through 6 15 beginning on page 6 26 describe the receive FIFO registers and provide bit definitions 6 4 1 1 Receive FIFO Data Register RXDAT Received data bytes are written to the receive FIFO via the receive FIFO data register RXDAT 6 25 8x931AA 8x931HA USER S MANUAL intel RXDAT Address E3H Endpoint indexed Reset xxxxB Receive FIFO Data Register Receive FIFO data specified by EPINDEX is stored and read from this register 7 0 Receive Data Byte Bit Bit Function Number Mnemonic uncuo 7 0 RXDAT7 0 Receive Data Byte To write data to the receive FIFO the FIU writes to this register To read data from the receive FIFO the 8x931 reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively Figure 6 13 RXDAT Receive FIFO Data Register 6 4 1 2 Receive FI
205. ONVENTIONS AND TERMINOLOGY 1 3 1 3 RELATED DOCUMENTS ir bd ep Rp ke 1 6 1 3 1 Data Sheet x suede eene 1 6 1 3 2 Application Notes ne een ERI DUE 1 6 1 4 APPLICATION SUPPORT SERVICES sssssseseeenennen nennen nennen 1 6 1 4 1 World Wide Web nip e REOR GRE RAM RR Piin 1 7 13 42 iesu uiis 1 7 1 4 3 Bulletin Board System BBS sssessssesseeeeeeeeeeeeee nennen nnne 1 8 CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 PRODUCT OVERVIEW rho HERRERA UA RERUM hat 2 2 2 1 1 SXOSTAA Features p eta 2 3 21 2 BXOSTHA Features PO Ue HEURE n EINE 2 3 2 1 3 Keyboard Control Interface sse nnne nennen nnne nnne nnn 2 4 214 5 51 Architecture Features rte rere tete ee eda 2 5 2 2 MIGROGONTROELEER GORE tI ttr rio dee cd ce s 2 6 2 2 1 GR innu est D RR Le RE MEE EAR Deu 2 6 2 2 2 QOlockand Reset Unit eee Ree LE pe e ete DP RR 2 7 2 2 2 1 State Time and Machine Cycles essen 2 8 2 22 2 USB Operating Rate ele ges e d eis 2 8 2 2 2 3 Eow clock Mode euro eae OM HER 2 8 2 2 2 4 BesetUnit Eds eued epis 2 8 2 2 3 Interrupt Handler eee 2 11 2 3 8x931T MEMORY iue BAL lec RIGEN ES 2 11 2 4 UNIVERSAL SERIAL BUS MODULE essen nennen 2 11 2 4 1 USB Operation i een LH eet tdeo 2
206. Operation A 24 Encoding 0001 irrr DEC Rn lt Rn 1 Divide Divides the unsigned 8 bit integer in the accumulator by the unsigned 8 bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The CY and OV flags are cleared Exception if register B contains 00H the values returned in the accumulator and register B are undefined the CY flag is cleared and the OV flag is set CY AC OV 0 3 For division by zero CY AC OV 0 1 The accumulator contains 251 OFBH or 11111011B and register contains 18 12H or 00010010B After executing the instruction DIV AB the accumulator contains 13 ODH or 00001101B register B contains 17 11H or 00010001B since 251 13 X 18 17 and the CY and OV flags are clear 1 24 4 Encoding 1000 0100 DIV A quotient A B B lt remainder A B intel INSTRUCTION SET REFERENCE DJNZ lt byte gt lt rel addr gt Function Decrement and jump if not zero Description Decrements the specified location by 1 and branches to the address specified by the second operand if the resulting value is not zero An original value of 00H underflows to OFFH The branch destination is computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction
207. Port connect status cannot be changed through HPCON This port feature is controlled by physically connecting or disconnecting a device from the port HPCON Address CFH Indexed by HPINDEX Reset State x000B Hub Port Control Register Firmware writes to this register to disable enable reset suspend and resume a port 7 0 HPCON2 HPCON1 HPCONO Bit Bit Number Mnemonic Function 7 3 Reserved Write zeros to these bits 2 0 HPCON2 0 Encoded Hub Port Control Commands All bits should be set and cleared by firmware after receiving the USB requests ClearPortFeature and SetPortFeature from the host The bits are encoded as follows all other bit combinations are ignored by the hardware 000 Disable port 001 Enable port 010 Reset and enable port 011 Suspend port 100 Resume port See Table 7 6 on page 7 16 for a complete description of the encoded hub port control commands Figure 7 9 HPCON Hub Port Control Register Port 1 represents the internal downstream port and differs from the external downstream ports The internal downstream port is always connected and cannot be disconnected Hub port control commands have a different effect on port 1 than they do on the external downstream ports as shown in Table 7 6 below 8x931AA 8x931HA USER S MANUAL Table 7 6 Encoded Hub Port Control Commands Code Co
208. Programming Models describes the operation of function interface on the 8x931 USB microcontroller A data flow model for USB transactions intended to bridge the hardware and firmware layers of the 8x931 is presented in truth table form in Appendix D Data Flow Model The model de scribes 8x931 behavior in response to a particular USB event given a known state configuration The SFRs described in this chapter are listed in Table 6 3 The SFR definition tables that appear in this chapter also appear in alphabetical order in Appendix C Registers 6 1 FUNCTION INTERFACE The function interface provides a USB interface capability for one USB function The main com ponents of the function interface are the serial bus interface engine SIE and the function inter face unit FIU Refer to the block diagram in Figure 2 3 on page 2 7 The operation of the function interface is discussed in section 2 4 Universal Serial Bus Module pg 2 11 On the 8x931HA the hub accesses the function interface through the internal downstream port 6 1 1 Function Endpoint Pairs The endpoint pairs implemented on the 8x931 are listed in Table 2 5 on page 2 12 The EPIN DEX register selects the endpoint pair for any given data transaction The 8x931HA supports three function endpoint pairs and two hub endpoint pairs See USB Hub Endpoints on page 7 10 6 1 2 Function FIFOs The 8x931 provides a transmit receive FIFO pair for each endpoint pair
209. RL lt A v Ri Encoding lt A Rn 0110 011i 0110 1rrr intel B Pin Descriptions APPENDIX B PIN DESCRIPTIONS This appendix provides reference information regarding the external signals of the 8x931 The 8x93 1 is available in dual in line 64 pin S DIP 8x93 1HA only quad flatpack 64 pin QFP and plastic leaded chip carrier 68 pin PLCC packages See Figures B 1 through B 5 Tables B 4 through B 6 list the signals by functional category Table B 7 describes each of the signals It lists the signal type input output power or ground and the alternative functions of multi function pins NC NC 3 A8 P2 0 KSO8 61 Reserved 8 F A9 P2 1 KSO9 7 H A10 P2 2 KSO10 6 A A11 P2 3 KSO11 5 A A12 P2 4 KSO12 4 A13 P2 5 KSO13 3 F A14 P2 6 KS014 2 H A15 2 7 KS015 62 Reserved 07 P0 7 KSI7 E 10 AD6 P0 6 KSI6 AD5 P0 5 KSI5 AD4 P0 4 514 E AD3 P0 3 KSI3 56 AD2 P0 2 KSI2 Dpo AD1 PO 1 KSI1 E 8x931Hx ADO P0 0 KSIO rj ECAP Vssp amp 52 Vssp P3 0 OVRI E 20 50 F Vss P3 1 SOF4 El 21 View of component as Des P3 2 INTO E 22 mounted on PC board P3 3 INT1 E 23 47 Vssp P3 4 TO KSO16 24 P3 5 T1 KSO17 Q 25 P3 6 WR KSO18 E 26 P3 7 RD KSO19 r
210. SO19 39 Vss 61 A10 P2 2 KSO10 18 P1 0 T2 KSOO 40 Vccp 62 A9 P2 1 KSO9 19 P1 1 T2EX KSO1 41 Vssp 63 A8 P2 0 KSO8 20 P1 2 KSO2 42 ECAP 64 AD7 PO 7 KSI7 21 P1 3 KSO3 43 22 P1 4 KSO4 44 Dpo Specific to the 8x931AA tt Specific to the 8x931HA intel Table B 4 68 pin PLCC Signal Assignments Arranged by Functional Category PIN DESCRIPTIONS t Specific to the 8x931AA tt Specific to the 8x931HA Address amp Data Input Output USB Name Pin Name Pin Name Pin A15 P2 7 KSO15 2 P1 0 T2 KSOO 28 PLLSEL 42 A14 P2 6 KSO14 3 P1 1 T2EX KSO1 29 54 A13 P2 5 KSO13 4 P1 2 KSO2 30 55 A12 P2 4 KSO12 5 P1 3 KSO3 31 Reservedt Dysi 57 A11 P2 3 KSO11 6 P1 4 KSO4 32 Dpsit 58 A10 P2 2 KSO10 7 P1 5 KSO5 33 Reservedt Dyu2tt 45 A9 P2 1 KSO9 8 P1 6 KSO6 34 Reserved 46 A8 P2 0 KSO8 9 P1 7 KSO7 35 Reserved Dygit 48 AD7 P0 7 KSI7 10 P3 0 OVRI 20 49 AD6 P0 6 KSI6 11 P3 1 SOF 21 ECAP 53 AD5 P0 5 KSI5 12 P3 2 INTO 22 59 4 4 514 13 P3 3 INT1 23 Reserved 60 AD3 P0 3 KSI3 14 P3 4 T0 KSO16 24 FSSELt UPWEN 64 AD2 PO0 2 KSI2 15 P3 5 T1 KSO17 25 OVRI 20 AD1 P0 1 KSI1 16 P3 6 WR KSO18 26 ADO PO 0 KSIO 17 P3 7 RD KSO19 27 Processor Control Power amp Ground Bus Control amp Status Name Pin Name Pin Name Pin P3 2 INTO 22 Voce 51
211. SOF Interrupt Priority Bit High Figure 5 14 IPH1 Interrupt Priority High Register 1 5 29 8x931AA 8x931HA USER S MANUAL intel IPL1 Address B2H Reset State xxxx x000B Interrupt Priority Low Control Register 1 IPL1 together with IPH1 assigns each interrupt in IEN1 a priority level from 0 lowest to 3 highest IPH1 x IPL1 x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPL1 7 IPL1 2 IPL1 1 IPL1 0 Bit Bit x Function Number Mnemonic unctio Keyboard Scan Interrupt Priority Bit Low 6 3 Reserved Write zeros to these bits 2 Global Suspend Resume Reset Interrupt Priority Bit Low 1 IPL1 1 USB Function Interrupt Priority Bit Low 0 IPL1 0 USB Hub SOF Interrupt Priority Bit Low Figure 5 15 IPL1 Interrupt Priority Low Register 1 5 5 INTERRUPT HANDLING The interrupt flags are sampled at S5P2 of every machine cycle The samples are polled during the following machine cycle The Timer 2 interrupt cycle is slightly different as described in the Response Time section If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority level is already in progress
212. T Transmit Error RXACK 1 No Advance Receive FIFO to Next Packet Read Data Packet Yes RXERR 1 Failed CRC or Bit Stuffing No Advance Receive FIFO to Next Packet Receive Error in Receive FIFO Receive FIFO Error Recovery Error in Receive FIFO Data Reconstruction Yes by Application for RXURF 1 Lost Data Receive FIFO Error Recovery POA eee Unlock Current Packet y Application for from Receive FIFO Lost Data set RXFFRC bit in RXCON Unlock FIFO set RXFFRC RETI Buffer Segmentation Management Executed automatically by hardware at the end of a data transaction if ARM bit in TXCON is set For isochronous transactions there is no retry of current packet regardless of transaction status A5074 01 Yes RXOVF 1 Figure 8 8 Receive SOF ISR Isochronous 8 13 8x931AA 8x931HA USER S MANUAL intel 8 4 SETUP TOKEN An endpoint must be configured as a control endpoint in order to respond to SETUP tokens This will only be endpoint 0 since it must serve as a control endpoint Refer to the Protocol Layer section of the Universal Serial Bus Specification for details of SETUP token transactions and pro tocol A control data transfer is initiated by a valid SETUP token i e the token PID received is good Receive data transfer operations for a control endpoint are very similar to data transfers on non
213. T bits of HPSTAT Figure 7 10 on page 7 18 to the transmit buffer of hub endpoint 0 Transmit these bits in a single byte with DMSTAT as bit 0 DPSTAT as bit 1 and bits 2 7 as 0 GetHubDescriptor N A Read hub descriptor from memory and transmit to USB host using hub endpoint 0 SetHubDescriptor N A Optional request for hubs which is not supported 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage GetHubStatus GetPortStatus 8 20 N A Port number Communicate the hub over current status change local power status change current overcurrent indicator and current local power status to the host Load HSTAT bits OVISC and OVI into transmit buffer with LPS as the LSb The HSTAT SFR is shown in Figure 7 6 on page 7 9 Load the indicated port s HPSTAT and HPSC SFRs into the transmit buffer See GetPortStatus Request Firmware on page 8 25 for additional information including bit ordering and a flowchart intel USB PROGRAMMING MODELS Table 8 2 Firmware Action for Hub Class Specific Requests Continued USB Requests Feature Selector Type Index Firmware Action Required SetPortFeature PORT_ENABLE Enables address and endpoint decoding for the downstream ports For hub port 1 this enables address and endpoint decoding for the embedded function 1 Load xxxB into HPINDEX2 0 where xxx is th
214. TERFACE This chapter covers various aspects of the external memory interface It describes the signals as sociated with external memory operations and external bus cycle timing This chapter also gives the status of the pins for ports PO and P2 during bus cycles and bus idle and includes several ex ternal memory design examples 15 1 OVERVIEW The 8x931 interfaces with a variety of external memory devices Data transfer operations 8 bits are multiplexed on the lower address bits A7 0 The external memory interface comprises the external bus ports 0 and 2 and the bus control sig nals described in Table 15 1 Figure 15 1 shows the structure of the external address bus Microcontroller RAM EPROM Flash A15 8 AD7 0 A7 0 p Figure 15 1 Bus Structure A7 0 A5358 01 15 1 8x931AA 8x931HA USER S MANUAL Table 15 1 External Memory Interface Signals intel Signal ae Alternate Name Type Description Function A15 8 Address Lines Upper byte of external memory address P2 7 0 KSO15 8 AD7 0 lO Address Data Lines Lower byte of external memory address P0 7 0 KSI7 0 multiplexed with data ALE Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus AD7 0 EA External Access
215. TFx in the TCON or T2CON register Setting the run control bit does not clear the THx and TLx timer registers The timer registers can be accessed to obtain the current count or to enter preset values Timer 0 and timer 1 can also be controlled by external pin INTx to facilitate pulse width measurements The C Tx control bit selects timer operation or counter operation by selecting the divided down system clock or external pin Tx as the source for the counted signal For timer operation C Tx 0 the timer register counts the divided down system clock The timer register is incremented once every peripheral cycle once every six states That is at the internal clock frequency divided by six 6 or at the external oscillator frequency Fosc 12 Exceptions are the timer 2 clock out and baud rate modes in which the timer register is incre mented at the internal clock rate Ferg See Clock and Reset Unit on page 2 7 Table 2 5 on page 2 12 and Figure 2 5 on page 2 10 show the relationship between Fo state times and peripheral cycles Also see the 8x931 clock circuit block diagram in Figure 2 4 on page 2 9 10 1 8x931AA 8x931HA USER S MANUAL intel NOTE The timing calculations in this chapter are based on the value of Ferg Fos 2 Setting the low clock PCON 5 bit forces the internal clock distributed to the CPU and peripherals to 3MHz This bit is automatically set after a reset Clearing this bit th
216. The 8x931 enters idle mode upon execution of the instruction that sets the IDL bit The instruction that sets the IDL bit is the last instruction executed CAUTION If the IDL bit and the PD bit are set simultaneously the 8x931 enters powerdown mode 14 6 intel SPECIAL OPERATING MODES 14 3 2 Exiting Idle Mode There are two ways to exit idle mode Generate an enabled interrupt Hardware clears the PCON register IDL bit which restores the clocks to the CPU Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated idle mode The general purpose flags GF1 and GFO in the PCON register may be used to indicate whether an interrupt occurred during normal operation or during idle mode When idle mode is exited by an interrupt the interrupt service routine may examine GF1 and GFO Reset the chip A logic high on the RST pin clears the IDL bit in the PCON register directly and asynchronously This restores the clocks to the CPU Program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8x931 and vectors the CPU to address 0000 NOTE During the time that execution resumes the internal RAM cannot be accessed h
217. UAL Operation Variations XCHD A Ri Function Description Flags Example Bytes States Cycles Operation XCH A gt lt Rn Exchange digit Exchanges the low nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the on chip RAM location indirectly addressed by the specified register Does not affect the high nibble bits 7 4 of either register CY AC OV RO contains the address 20H the accumulator contains 36H 00110110B and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCHD A GRO on chip RAM location 20H contains 76H 01110110B and 35H 00110101B in the accumu lator Encoding 1101 011i XCHD A 3 0 gt lt Ri 3 0 XRL lt dest gt lt src gt Function Description Flags A 56 Logical Exclusive OR for byte variables Performs the bitwise logical Exclusive OR operation V between the specified variables storing the results in the destination The destination operand can be the accumulator a register or a direct address The two operands allow six addressing mode combinations When the destination is the accumulator the source addressing can be register direct register indirect or immediate when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an outpu
218. WP Reverse Write Pointer For non ARM mode only Set this bit to return the write pointer to the origin of the last data set received as identified by the write marker The FIU can then receive the last data packet again and write to the receive FIFO starting from the same origin when the host re sends the same data packet Hardware clears this bit after the write pointer is reversed Setting this bit is effective only when the ADVWM ARM and RXCLR bits are all clear REVWP is used when a data packet is bad When the function interface receives the data packet again the write starts at the origin of the previous bad data set ARM mode is recommended ADVWM and REVWP which control the write marker and write pointer when ARM 0 are used for test purposes RXDAT Address E3H Endpoint indexed Reset xxxxB Receive FIFO Data Register Receive FIFO data specified by EPINDEX is stored and read from this register 7 0 RXDAT 7 0 Bit Bit r Function Number Mnemonic uneto 7 0 RXDAT 7 0 To write data to the receive FIFO the FIU writes to this register To read data from the receive FIFO the 8x931 reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively C 40 intel REGISTERS RXFLG Endpoint indexed Address E5H Reset State 00xx 1000B Receive FIFO Flag Register These flags indicate th
219. XFIF USB 1 0 Event 1 0 RX RX RX ae r Response Comments 2 ERR voia 2 2 rup 00 Received OUT 00 no no 1 no no None None FIFO not ready token but RXIE chg chg chg chg Time out or timed out 0 waiting for data packet but no NAK sent Received OUT 00 no no no no no None None FIFO not loaded token but chg chg chg chg chg Time out timed out waiting for data Received OUT 01 0 1 0 no no None None Received no token no errors chg chg Time out errors advance write marker Received OUT 01 1 0 None None Bad data still token data Time out loaded into CRC or bit stuff FIFO error Received OUT 01 1 0 None None Only RXOVF token FIFO Time out FIFO error can error occurs occur requires firmware intervention Received OUT 00 1 0 1 1 no None None Treated like a token with no no no chg Time out void condition FIFO error chg chg chg already existing CPU reads 00 no no no no 1 None None FIFO was FIFO causes chg chg chg chg Time out empty when FIFO error read Should always check RXFIF bits before reading NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 RXFIF RXOVF and RXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF RXURF Since underrun can only be caused by firmware RXURF is updated immediately R
220. XISO Transmit Clear Setting this bit flushes the transmit FIFO resets all the read write pointers and markers sets the EMPTY bit in TXFLG and clears all other bits in TXFLG After the flush hardware clears this bit Setting this bit does not affect the ATM TXISO and FFSZ bits or the TXSEQ bit in the TXSTAT register Reserved Values read from this bit are indeterminate Write zeros to these bits Transmit Isochronous Data Firmware sets this bit to indicate that the transmit FIFO contains isochronous data The FIU uses this bit to set up the handshake protocol at the end of a transmission This bit is not reset when TXCLR is set and must be cleared by firmware ATM Automatic Transmit Management Setting this bit the default value causes the read pointer and read marker to be adjusted automatically as indicated TXISO TX Status Read Pointer Read Marker X ACK Unchanged Advanced 1 0 NAK Reversed 2 Unchanged 1 NAK Unchanged Advanced 1 1 to origin of next data set 2 to origin of the data set last read This bit should always be set except for test purposes Setting this bit disables ADVRM and REVRP This is a sticky bit that is not reset when TXCLR is set but can be set and cleared by firmware Hardware neither clears nor sets this bit ATM mode is recommended ADVRM and REVRP which control the read marker and read pointer when ATM 0 are used for test purposes C 57 8x931AA 8x
221. XOVF Since overrun can only be caused by USB RXOVF is updated at SOF RXFIF RXFIF is incremented by USB and decremented by firmware Therefore setting RXFFRC will decrement RXFIF immediately However a successful USB transaction anytime in a frame will only increment RXFIF at SOF RXERR RXACK and RXVOID can only be caused by USB thus they are updated at the end of transaction intel Table D 5 Isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued DATA FLOW MODEL RXFIF Ove huge Mte USB c t 1 0 vent 1 0 RX RX RX aa Response omments 2 ERR ACK Void 12 2 rup Receive SOF no up up up up no None None Flags are indication chg up dated dated dated dated chg SOF Time out updated at dated interrupt SOF Firmware must check for RXFIF 00 condition to detect no ISO packet received this frame 01 10 Received OUT 01 10 no no 1 no no None None FIFO not ready token but RXIE chg chg chg chg Time out 0 Received OUT 01 10 no no no no no None None FIFO not loaded token but chg chg chg chg chg Time out timed out waiting for data Received OUT 11 0 1 None None Received no token no errors Time out errors advance write marker Received OUT 11 1 0 None None Possible to token data Time out have RXERR CRC or bit stuff cleared by error hardware before seen
222. XOVF Since overrun can only be caused by firmware TXOVF is updated immediately e TXURF Since underrun can only be caused by SIE TXURF is updated at SOF TXFIF TXFIF is incremented by firmware and decremented by hardware Therefore writes to TXCNTL will increment TXFIF immediately However a successful USB transaction anytime in a frame will only decrement TXFIF at SOF The following bits do not follow the above rule TXEMP TXFULL These always reflect the current status of the FIFO 6 35 8x931AA 8x931HA USER S MANUAL intel TXFLUSH Firmware can detect a flush by monitoring this bit 6 7 2 Receive FIFO ISO Data Management For firmware traceability of FIFO status flags some flags are updated immediately while others are updated only at SOF RXOVF RXURF and RXFIF are handled using the following rule firmware events cause status change immediately while USB events only cause status change at SOF For example e RXURE Since underrun can only be caused by firmware RXURF is updated immediately RXOVE Since overrun can only be caused by SIE RXOVF is updated at SOF RXFIF RXFIF is incremented by hardware and decremented by firmware Therefore setting RXFFRC will decrement RXFIF immediately However a successful USB transaction anytime in a frame will only increment RXFIF at SOF RXEMP RXFULL The rule does not apply to the RXEMP and RXFULL flags which always refle
223. a 16 bit constant Loads the 16 bit data pointer DPTR with the specified 16 bit constant The high byte of the constant is loaded into the high byte of the data pointer DPH The low byte of the constant is loaded into the low byte of the data pointer DPL CY AC OV A 39 8x931AA 8x931HA USER S MANUAL intel Example After executing the instruction MOV DPTR 1234H DPTR contains 1234H DPH contains 12H and DPL contains 34H Bytes 3 States 12 Cycles 2 Encoding 1001 0000 data hi data low Operation MOV DPTR data16 MOVC A A lt base reg gt Function Move code byte Description Loads the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned 8 bit accumulator contents and the contents of a 16 bit base register which may be the 16 LSBs of the data pointer or PC In the latter case the PC is incremented to the address of the following instruction before being added with the accumulator otherwise the base register is not altered Sixteen bit addition is performed Flags CY AC OV Example The accumulator contains a number between 0 and 3 The following instruction sequence translates the value in the accumulator to one of four values defined by the DB define byte directive RELPC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator
224. a and to set up the USB Interface to handle an isochronous data transfer This bit is not reset when the RXCLR bit is set it must be cleared by firmware 2 Auto Receive Management When set the write pointer and write marker are adjusted automatically based on the following conditions RXISO RX Status Write Pointer Write Marker X ACK Unchanged Advanced 0 NAK Reversed Unchanged 1 NAK Unchanged Advanced When this bit is set setting REVWP or ADVWM has no effect Hardware neither clears nor sets this bit This is a sticky bit that is not reset when RXCLR is set NOTE This bit should always be set except for testing ARM mode is recommended ADVWM and REVWP which control the write marker and write pointer when ARM 0 are used for test purposes C 39 8x931AA 8x931HA USER S MANUAL intel RXCON Continued Address E4H Endpoint indexed Reset State 0xx0 0100B Receive FIFO Control Register Controls the receive FIFO specified by EPINDEX 7 0 RXCLR RXFFRC RXISO ARM ADVWM REVWP Bit Bit Function Number Mnemonic unctio 1 ADVWM Advance Write Marker For non ARM mode only Set this bit to advance the write marker to the origin of the next data set Advancing the write marker is used for back to back receptions Hardware clears this bit after the write marker is advanced Setting this bit is effective only when the REVWP ARM and RXCLR bits are clear 0 REV
225. able Function Address This register is programmed through the commands received via endpoint 0 on configuration which should be the only time the firmware should change the value of this register This register is read only by hardware 8x931AA 8x931HA USER S MANUAL intel FIE Address A2H Reset State xx00 0000B Function Interrupt Enable Register Enables and disables the receive and transmit done interrupts for the three function endpoints 7 0 FRXIE2 FTXIE2 FRXIE1 FTXIE1 FRXIEO FTXIEO Bit Bit Number Mnemonic Function 7 6 Reserved Write zeros to these bits 5 FRXIE2 Function Receive Interrupt Enable 2 Enables the receive done interrupt for endpoint 2 FRXD2 4 FTXIE2 Function Transmit Interrupt Enable 2 Enables the transmit done interrupt for endpoint 2 FTXD2 3 FRXIE1 Function Receive Interrupt Enable 1 ENSE Enables the receive done interrupt for endpoint 1 FRXD1 2 FTXIE1 Function Transmit Interrupt Enable 1 Enables the transmit done interrupt for endpoint 1 FTXD1 1 FRXIEO Function Receive Interrupt Enable 0 Enables the receive done interrupt for endpoint 0 FRXDO 0 FTXIEO Function Transmit Interrupt Enable 0 Enables the transmit done interrupt for endpoint 0 FTXDO NOTE For all bits a 1 means the interrupt is enabled and will cause an interrupt to be signaled to the microcontroller A 0 means the associated interru
226. above the bit position NOTE The HPSTAT bits are not directly mapped into the port status field Firmware must clear bit three of byte one to indicate that power is normal not overcurrent for the port This is done because the 8x93 1HA indicates overcurrent on a ganged not per port basis Port Status Field Port Change Field Byte 2 Byte 4 Byte 3 0 8 Get 9 Reserved Status 2 43210 a HPSC A5117 01 Figure 8 13 Firmware Response to GetPortStatus 8 6 3 2 SetPortFeature PORT SUSPEND Firmware This USB request suspends the downstream ports The number of the port to be suspended is in cluded in the request from the host If hub port 4 is specified firmware must also suspend any non hub functionality associated with the embedded function and place any external device hard ware into low power suspend mode prior to writing to hub port 4 s HPCON SFR To implement this routine firmware must write O11 to bits 2 0 of the port s HPCON SFR The flowchart in Figure 8 14 illustrates the process 8 26 intel USB PROGRAMMING MODELS SetPortFeature PortSuspend Write xxxB to HPINDEX port number to select the port Place embedded function and its Is Suspend external device for port 4 hardware into low power suspend mode Write 011B to HPCON to suspend the port A5166 01 Figure 8 14 SetPortFeature PORT_SUSPEND Routine 8 6 3 3 SetPortFeature PORT_RES
227. ag is set your code should branch to the USB initialization routine to initialize the USB related SFRs and flush the FIFOs If this is done the only potential opportunity for misprocessing would be if the USB reset interrupt occurs between the test of USB_RST_FLG and the branch to the USB initialization routine NOTE Because of the risk of misprocessing however slight it is recommended that applications that will not substantially benefit from a separate USB reset disable this option by leaving the URDIS bit in PCONI cleared to simplify firmware coding and ensure a robust chip level reset 5 23 8x931AA 8x931HA USER S MANUAL intel 5 3 INTERRUPT ENABLE Each interrupt source may be individually enabled or disabled by the appropriate interrupt enable bit in the IENO register at A8H see Figure 5 10 or the IENI register at B1H see Figure 5 11 Note IENO also contains a global disable bit EA If EA is set interrupts are individually enabled or disabled by bits in IENO and IENI If EA is clear all interrupts are disabled IENO Interrupt Enable Register 0 IENO contains two types of interrupt enable bits The global enable bit EA enables disables all of the interrupts including those in IEN1 The remaining bits enable disable the other individual interrupts 7 Address A8H Reset State 0000 0000B EA ET2 ES ET1 EX1 ETO EXO Bit Number Bit Mnemonic Function EA Global
228. agnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instructions update the parity bit The parity bit is set or cleared by instructions that change the contents of the accumulator ACC Figure 4 1 Program Status Word Register 4 2 intel PROGRAMMING CONSIDERATIONS Table 4 1 The Effects of Instructions on the PSW Flags Flags Affected 1 4 Instruction Type Instruction n AC 2 ADD ADDC SUBB X X X CMP Arithmetic INC DEC MUL DIV 3 0 X DA X ANL ORL XRL CLR A Logical CPL A RL RR SWAP RLC RRC X CJNE X Program Control DJNZ NOTES 1 X the flag can be affected by the instruction 0 the flag is cleared by the instruction 2 The AC flag is affected only by operations on 8 bit operands 3 If the divisor is zero the OV flag is set and the other bits are meaningless 4 The parity bit PSW 0 is set or cleared by instructions that change the contents of the accumulator ACC 4 1 2 Addressing Modes The addressing modes in the MCS 51 inst
229. ake up This bit is modified through the SetFeature and ClearFeature requests using the DEVICE REMOTE WAKEUP feature selector When 0 the hub blocks resume signaling for connect disconnect and resume events detected on downstream ports NOTE Donotset this bit until after the hub is enumerated and the host issues a SET FEATURE command with a DEVICE REMOTE WAKEUP feature selector Bits 1 and 3 are returned in response to a Get Hub Status request from the USB host This response is a four byte field with zero padding MSB at left 0000 0000 0000 00 3 0 0000 0000 0000 00 1 0 Figure 7 6 HSTAT Hub Status and Configuration Register 7 9 8x931AA 8x931HA USER S MANUAL intel HSTAT Continued Address AEH Reset State 0000 0000B Hub Status and Configuration Register This SFR contains bits for remote wake up request status and status change indicators for over current and hub endpoint 1 stall and enable 7 0 OVRIEN HRWUPE EP1STL EP1EN OVISC OVI Bit Bit Function Number Mnemonic 5 EP1STL Hub Endpoint 1 Stall Field Set to 1 via the USB SetFeature request with endpoint stall feature selector When 1 will force a stall response when endpoint 1 is addressed Reset with USB ClearFeature request with endpoint stall feature selector 4 EP1EN Hub Endpoint 1 Enable Set to 1 upon receipt of a USB SetConfiguration request value o
230. aling arising from a reset request A disabled port does not propagate upstream signaling if the hub is awake but will detect disconnects and initiate resume signaling to the root port if the hub is suspended enabled Port propagates all downstream and upstream signaling suspended When suspended the port will not stop propagating in the middle of a transaction If hub is awake no upstream or downstream connectivity can propagate through the port except for downstream directed reset signaling If hub is suspended idle to resume is propagated The transitions between these states are shown in Figure 7 3 7 4 intel USB HUB PORT_POWER OFF or Reset on root port Connect Detect Disconnect Detect PORT_DISABLE or Frame error Disconnect Detect PORT_RESUME or PORT_RESET or Remote wakeup Disconnect Detect A5121 01 Figure 7 3 Hub State Flow These port states are tracked and managed in the hub repeater based on hardware events e g physical connection disconnection of a device on a port and firmware execution of host com mands Normal packet traffic is allowed to propagate through ports that are in the enabled state only as described in Per packet Signaling Connectivity on page 7 6 The root port is the only upstream port it is permanently powered on and enabled Hub ports 2 3 4 and 5 are external downstream ports They are power switched ports that must be powered on by
231. ar its value is 0 clearing a bit gives it a 0 value Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number Port pins are represented by the port abbrevi ation a period and the pin number e g P0 0 PO 1 A pound symbol appended to a signal name identifies an active low signal The following abbreviations are used to represent units of measure A amps amperes DCV direct current volts Kbyte kilobytes KQ kilo ohms mA Mbyte MHz mW ns pF uA uF us uw GUIDE TO THIS MANUAL milliamps milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps microamperes microfarads microseconds microwatts 1 5 8x931AA 8x931HA USER S MANUAL intel 1 3 RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the 8x931 To order documents please call Intel Literature Fulfillment 1 800 548 4725 in the U S and Canada 44 0 793 431155 in Europe Embedded Microcontrollers Order Number 270646 Embedded Processors Order Number 272396 Embedded Applications Order Number 270648 Packaging Order Number 240800 Universal Serial Bus Specification Order Number 272904 MCS 51 Microcontroller Family User s Manual Order Number 272383 1 3 1 Data Sheet The data sheet is included in Emb
232. ation Support Services Service U S and Canada Asia Pacific and Japan Europe World Wide URL http www intel com URL http www intel com URL http www intel com Web World Wide URL http www intel com URL http www intel com URL http www intel com Web design usb design usb design usb FaxBack 800 525 3019 503 264 6835 44 0 1793 496646 916 356 3105 BBS 503 264 7999 503 264 7999 44 0 1793 432955 916 356 3600 916 356 3600 Help Desk 800 628 8686 Please contact your local Please contact your local 916 356 7999 distributor distributor Literature 800 548 4725 708 296 9333 44 0 1793 431155 81 0 120 47 88 32 England 44 0 1793 421777 France 44 0 1793 421333 Germany 1 4 4 World Wide Web We offer a variety of technical and product information through the World Wide Web URL ht tp www intel com design usb Also visit Intel s Web site for financials history news and USB information at www intel com design 1 4 2 FaxBack Service The FaxBack service is an on demand publishing system that sends documents to your fax ma chine You can get product announcements change notifications product literature device char acteristics design recommendations and quality and reliability information from FaxBack 24 hours a day 7 days a week Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to t
233. be enabled The USB Function Interrupt Flag register FIFLG as shown in Figure 5 4 is used to indicate pending function interrupts for a given endpoint For all bits in FIFLG a 1 indicates that an in terrupt is actively pending for that endpoint a 0 indicates that the interrupt is not active The interrupt status is shown in the FIFLG register regardless of the state of the corresponding inter rupt enable bit in the FIE register Figures 5 3 5 8 intel INTERRUPT SYSTEM FIE Address A2H Reset State xx00 0000B Function Interrupt Enable Register Enables and disables the receive and transmit done interrupts for the three function endpoints 7 0 FRXIE2 FTXIE2 FRXIE1 FTXIE1 FRXIEO FTXIEO Bit Bit Function Number Mnemonic 7 6 Reserved Write zeros to these bits 5 FRXIE2 Function Receive Interrupt Enable 2 Enables the receive done interrupt for endpoint 2 FRXD2 4 FTXIE2 Function Transmit Interrupt Enable 2 Enables the transmit done interrupt for endpoint 2 FTXD2 3 FRXIE1 Function Receive Interrupt Enable 1 Enables the receive done interrupt for endpoint 1 FRXD1 2 FTXIE1 Function Transmit Interrupt Enable 1 Enables the transmit done interrupt for endpoint 1 FTXD1 1 FRXIEO Function Receive Interrupt Enable 0 Enables the receive done interrupt for endpoint 0 FRXDO 0 FTXIEO Function Transmit Interrupt Enable 0 Enables the
234. bit is cleared in firmware via the USB host request ClearPortFeature with a C PORT RESET feature selector 1 indicates reset of port complete 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware approximately 10 msec after receipt of a port reset and enable command SetPortFeature with PORT RESET feature selector Port 1 This bit is set by hardware at the EOF2 point near the end of a frame after completion of the hardware timed reset due to firmware execution of a port reset and enable command SetPortFeature with PORT RESET feature selector Reserved Write a zero to this bit Port Suspend Status Change read clear only This bit is cleared by firmware upon a USB host request ClearPortFeature with C PORT SUSPEND feature selector 1 resume process complete 0 no change The resume process is initiated by firmware upon reception of a SetPortFeature request with a PORT SUSPEND feature selector Port x x 2 3 4 5 This bit is set by hardware upon completion of the firmware initiated resume process Port 1 This bit is set by hardware 20 msec after the next EOF2 point after completion of the resume process NOTE Bits are returned as part of the second word 2 bytes in response to a Get Port Status request from the USB host The upper 11 MSbs are reserved and always 0 per USB 1 0 0000 0000 000 4 3 2 1 0 MSB at left Figure 7 11 HPSC Hub Port Status Change Registe
235. bles results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instructions update the parity bit The parity bit is set or cleared by instructions that change the contents of the accumulator ACC C 37 8x931AA 8x931HA USER S MANUAL intel RCAP2H RCAP2L Address RCAP2H CBH RCAP2L CAH Reset State 0000 0000B Timer 2 Reload Capture Registers This register pair stores 16 bit values to be loaded into or captured from the timer register TH2 TL2 in timer 2 7 0 High Low Byte of Timer 2 Reload Capture Value Bit Bit Number Mnemonic Function 7 0 RCAP2H 7 0 High byte of the timer 2 reload recapture register RCAP2L 7 0 Low byte of the timer 2 reload recapture register RXCNTL Address E6H Endpoint indexed Reset State xxxxB Receive FIFO Byte count Low Register Ring buffer used to store the byte count for the data packets received in the receive FIFO specified by EPINDEX 7 0 BC4 BC3 BC2 BC1 BCO Bit Bit Numbe
236. c tions Appendix E 8x931AA Design Considerations 4describes the differences between the hub less 8x931AA and the 8x931HA Glossary a glossary of terms has been provided for reference of technical terms Index an index has been included for your convenience 1 2 intel GUIDE TO THIS MANUAL 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used in this manual The Glossary defines other terms with special meanings The pound symbol has either of two meanings depending on the context When used with a signal name the symbol means that the signal is active low When used with an instruction mnemonic the symbol prefixes an immediate value in immediate addressing mode italics Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register Px y x represents the variable 1 4 that identifies the specific port and y represents the register bit variable 7 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals XXXX xxxx Uppercase X no italics and lowercase x no italics represent unknown values or a don t care states or conditions The value may
237. can generate an embedded port reset command to the hub to reset the 8x93 1HA embedded function When this command is received the embedded function s EPCON FIFLG FIE TXSTAT RXSTAT TXCON RXCON FADDR and PCONI SFRs are reset to their de fault values as are the SOFACK ASOF SOFIE and SOFODIS bits of SOFH The EPINDEX and SOFL SFRs remain unchanged These SFRs are reset immediately after the write to HPCON however bus traffic to the embedded function remains inactive for 15 ms You may use this time frame to initialize the embedded function After an embedded function reset the internal function must be re enumerated by the host This procedure is given in Enumeration on page 8 2 7 24 intel USB HUB 7 5 5 2 Embedded Function Remote Wake up The HRWUPE bit in HSTAT Figure 7 6 on page 7 9 must be set in order for any downstream port to initiate resume signaling This includes hub port 1 the internal downstream port This port must be suspended and the HRWUPE bit in HSTAT must be set before the embedded function can initiate a remote wake up This is done by setting the RWU bit in PCONI Figure 14 2 on page 14 4 7 6 SUSPEND AND RESUME 7 6 1 Hub Global Suspend and Resume USB requirements state that a USB device must be capable of being placed in a low power sus pend mode in which the device draws less than 500 uA from the USB lines The hub and the em bedded function are placed in suspend mode when a continuous idl
238. ce level maximum packet size for endpoint 0 vendor id product id etc Get configuration descriptor The host requests and reads the device configuration descriptor to determine such information as the number of interfaces and endpoints endpoint transfer type packet size and direction power source maximum power etc For detailed information on configuration descriptors see the Device Framework chapter in Universal Serial Bus Specification When the host requests the configuration descriptor all related interface and endpoint descriptors are returned Set configuration The host assigns a configuration value to the device to establish the current configuration Devices can have multiple configurations intel E 3 8x931AA PIN DESCRIPTIONS 8X931AA DESIGN CONSIDERATIONS 64 AD7 0 7 KSI7 63 A8 P2 0 KSO8 62 A9 P2 1 KSO9 61 E A10 P2 2 KSO10 60 2 A11 P2 3 KSO11 59 E A12 P2 4 KSO12 58 A13 P2 5 KSO13 57 F A14 P2 6 KSO14 56 15 P2 7 KSO15 P3 5 T1 KSO17 15 P3 6 WR KSO18 16 P1 5 KSO5 23 P1 6 RXD KSO6 Ej 24 P1 2 KSO2 20 P1 3 KSO3 r3 21 P1 4 KSO4 22 P1 7 TXD KSO7 25 P1 0 T2 KSO0 18 P3 7 RD KSO19 17 P1 1 T2EX KSO1 E 19 Notes Reserved pins must be left unconnected AD6 P0 6 KSI6 1 Reserved NC AD5 P0 5 KSI5 6 2 Reserved NC AD4 P0 4 KSI4 Reserved NC
239. ceive FIFO at frame n is pre buffered to be read out in frame 1 This guarantees that data from the host is always available to the function every frame Isochronous data transfer is always guaranteed if the OUT or IN tokens from the host are not cor rupted When IN or OUT tokens to a function are corrupted the host does not re send the token Function firmware needs to recognize this error condition and reconfigure the endpoints accord ingly 6 7 1 Transmit FIFO ISO Data Management When an IN token is corrupted the data to be transmitted from the transmit FIFO for an isochro nous endpoint in the current frame will be flushed Due to latency concerns this is handled by hardware This error condition can be detected by checking TXFIF1 0 11 at SOF When this occurs the oldest data packet will be flushed and the transmit FIFO read pointers and read mark ers will be advanced to the start address of the second data packet The TXFIF will also be up dated Therefore the second packet will be ready to be transmitted for the next frame The first data packet is lost The transmit flush bit TXFLUSH in TXSTAT is also set when this occurs For firmware traceability of FIFO status flags some flags are updated immediately while others are updated only at SOF TXOVF TXURF and TXFIF are handled using the following rule firmware events cause status change immediately while USB events only cause status change at SOF For example T
240. ceived and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints 8x931AA 8x931HA USER S MANUAL intel Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event ut ERR ACK Void Setup a yd peo Response Comments Received 00 1 0 0 0 no no Set Time out Write pointer OUT token chg chg receive reversed data CRC or interrupt Possible to have bit stuff error RXERR cleared by hardware before seen by firmware Received 00 1 0 0 0 1 no Set Time out Only RXOVF OUT token chg receive NAK FIFO error can FIFO error interrupt future occur requires occurs transaction firmware S intervention Received 00 1 0 1 0 1 no None NAK Considered to be OUT token no no no chg a void with FIFO chg chg chg condition Will error already NAK until existing firmware clears condition Received 00 no no no no no no None ACK Last ACK OUT token chg chg chg chg chg chg corrupted so but data send again but sequence ignore the data mismatch Received 01 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token no interrupt automatically errors dual forcing new packet mode SETUP to be not received RXIE recommende or RXSTL has no effect 2 RXSETUP will be set control endpoints only
241. ciated LED Setting a bit turns off the associated LED NOTE The KSEN Keyboard Scan Enable bit must be set in order to activate the LED drivers After reset the LED driver control bits are cleared This means that when KSEN is set the LEDs will turn on Firmware must set the LED driver control bits to turn off the LEDs Figure 12 1 KBCON Keyboard Control Register 12 1 8x931AA 8x931HA USER S MANUAL Table 12 1 Keyboard Control Signals intel Signal Multiplexed Name Type Description With KSO19 Keyboard Scan Output Quasi bidirectional ports with weak P3 7 RD KSO18 internal pullup resistors used for the output side of the keyboard P3 6 WR KSO17 16 scan matrix P3 5 4 T1 0 KSO15 8 A15 8 P2 7 0 KSO7 0 P1 7 0 KSI7 0 Keyboard Scan Input Schmitt trigger inputs with firmware AD7 0 P0 7 0 enabled internal pullup resistors used for the input side of the keyboard scan matrix LED3 0 LED Drivers These drive LEDs connected directly to Voc The current each driver is capable of sinking is given as Vo in the datasheet NOTE Other signals are defined in their respective chapters and in Appendix B Pin Descriptions 12 2 KEYBOARD SCAN IMPLEMENTATION The keyboard scan matrix supports up to 160 keys using 20 keyboard scan outputs KSO and eight keyboard scan inputs KSI The KSOs are implemented as quasi bidirectional ports with weak internal pullup resistors To re
242. clusive with TXERR For isochronous transactions this bit is not updated until the next SOF Under normal operation this bit should not be modified by the user The SIE will handle all sequence bit tracking This bit should only be used when initializing a new configuration or interface For additional information on the operation of these bits see Appendix D Data Flow Model C 63 intel D Data Flow Model APPENDIX D DATA FLOW MODEL This appendix describes the data flow model for the 8x931 USB transactions This data flow mod el presented in truth table form is intended to bridge the hardware and firmware layers of the 8x931 It describes the behavior of the 8x931 in response to a particular USB event given a known state configuration The types of data transfer supported by the 8x931 are Non isochronous transfer interrupt bulk sochronous transfer Control transfer Table D 1 Non isochronous Transmit Data Flow New TX TX TX TXFIF TX TX TX USB Event TXFIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void 1 1 rupt Response 00 Received IN 00 no no 1 no no None NAK No data was token but no chg chg chg chg loaded so data or NAK 0 Received IN 00 no no 1 no no None NAK Control token chg chg chg chg endpoint only RXSETUP Endpoint will 1 when RXSETUP 1 even if TXSTL 1 Data loade
243. cordingly in the ISR NOTE Setting an endpoint interrupt s bit in the Function Interrupt Enable register FIE as shown in Figure 5 3 means that the interrupt is enabled and will cause an interrupt to be signaled to the microcontroller Clearing a bit in the FIE register disables the associated interrupt source which can no longer cause an interrupt even though its value will still be reflected in the FIFLG register Figure 5 4 5 10 intel INTERRUPT SYSTEM FIFLG Address COH Reset State xx00 0000B Function Interrupt Flag Register Contains the USB function s transmit and receive done interrupt flags for non isochronous endpoints 7 0 FRXD2 FTXD2 FRXD1 FTXD1 FRXDO FTXDO Tea TUIS Function 7 6 Reserved Write zeros to these bits 5 FRXD2 Function Receive Done Flag Endpoint 2 4 FTXD2 Function Transmit Done Flag Endpoint 2 3 FRXD1 Function Receive Done Flag Endpoint 1 2 FTXD1 Function Transmit Done Flag Endpoint 1 0 FTXDO Function Transmit Done Flag Endpoint 0 NOTES 1 For all bits in the Interrupt Flag Register a 1 indicates that an interrupt is actively pending a 0 indicates that the interrupt is not active The interrupt status is shown regardless of the state of the corresponding interrupt enable bit in the FIE 2 Bits are set only by hardware and clearable in firmware Firmware can also set the bits for test purposes allowing the inter
244. cs 51 Macro Assembler User s Guide To provide fast context switching the 8x931 implements registers RO R7 as four banks of eight registers with the active bank selected by the program status word PSW The register banks oc cupy the lowest 32 bytes of RAM memory in the data memory address space 2 6 intel ARCHITECTURAL OVERVIEW USB External Downstream Ports fan SO USB Upstream Port Hs Hub Root Port Transceiver Duis Des ae Transceiver Repeater pem foam Dps Serial Bus Interface Engine SIE Hub Function Interface Interface Unit Unit Control Control A5247 01 Figure 2 3 8x931HA USB Module Block Diagram 2 2 2 Clock and Reset Unit The waveform at XTAL is the 8x931 system clock It can be supplied by an external source con nected to XTALI or generated by an on chip oscillator which has its resonant circuit crystal or ceramic resonator connected across XTAL1 and XTAL2 See Figure 2 4 for the 8x931 clock cir cuit 2 7 8x931AA 8x931HA USER S MANUAL intel 2 2 2 1 State Time and Machine Cycles The basic unit of time for 8x931 peripheral controller is the state time or state States are divided into two phases identified as phase 1 and phase 2 The 8x931 machine cycle equals six states See Figure 2 5 on page 2 10 for 8x931 clocking definitions A specific time within a machine cycle is denoted by its state and phase F
245. ct the current status of the FIFO 6 36 intel USB Hub intel CHAPTER 7 USB HUB This chapter describes the operation of the Intel Universal Serial Bus USB on chip hub as im plemented in the 8x931HA This chapter introduces on chip hub operation and includes informa tion on bus enumeration hub endpoint status and configuration hub port control hub suspend and resume and hub power control To see how the hub fits in the 8x931HA architecture see Chapter 2 Architectural Overview NOTE The 8x931AA microcontroller does not support hub operations Specific details of the 8x931AA are covered in Appendix E 8x931AA Design Considerations 7 1 HUB FUNCTIONAL OVERVIEW The on chip hub provides an electrical interface between the USB host and the downstream ports In many cases this relationship exists as an interface between a USB host and other discrete USB devices Besides serving as a control interface between the host and the downstream ports the hub is also a USB device and must respond to the standard USB requests and hub class specific requests described in the Universal Serial Bus Specification The functionality between the PC host and the downstream ports that is handled by the hub in cludes Connectivity management Downstream device connect disconnect detection Power management including suspend and resume functions Bus fault detection and recovery Full and low speed device support The
246. ction Description Flags Example Variations JBC bit rel Bytes States Cycles INSTRUCTION SET REFERENCE JB lt PC 3 IF bitb1 1 THEN PC lt rel Jump if bit is set and clear bit If the specified bit is one branch to the specified address otherwise proceed with the next instruction The bit is not cleared if it is already a zero The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incre menting the PC to the first byte of the next instruction Note When this instruction is used to test an output pin the value used as the original data is read from the output data latch not the input pin CY AC OV The accumulator contains 56H 01010110B After the instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 the accumulator contains 52H 01010010B and program execution continues at label LABEL2 12 Encoding 0001 0000 bit addr rel addr Operation JC rel Function Description JBC lt PC 3 IF bit 1 THEN bit 0 lt PC rel Jump if carry is set If the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice A 29 8x931AA 8x931HA USER S MANUAL
247. ction Number Mnemonic Keyboard Scan Interrupt Priority Bit High 6 3 Reserved Write zeros to these bits 2 Global Suspend Resume Interrupt Priority Bit High 1 IPH1 1 USB Function Interrupt Priority Bit High 0 IPH1 0 USB Hub SOF Interrupt Priority Bit High C 29 8x931AA 8x931HA USER S MANUAL intel Address B2H Reset State 0000 0000B IPL1 Interrupt Priority Low Control Register 1 IPL1 together with IPH1 assigns each interrupt in IEN1 a priority level from 0 lowest to 3 highest IPH1 x IPL1 x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPL1 7 IPL1 2 IPL1 1 IPL1 0 Bit Bit x Function Number Mnemonic unctio Keyboard Scan Interrupt Priority Bit Low 6 3 Reserved Write zeros to these bits 2 Global Suspend Resume Interrupt Priority Bit Low 1 IPL1 1 USB Function Interrupt Priority Bit Low 0 IPL1 0 USB Hub SOF Interrupt Priority Bit Low C 30 KBCON Keyboard Control Register This register controls the keyboard scan input and output activity enables and configures the keyboard scan interrupt and drives the keyboard LEDs REGISTERS Address F8H Reset State 0xx0 0000B 7 0 IE2 KSEN IT2 LED3 LED2 LED1 LEDO Bit Bit z Number Mnemonic Function 7 IE2 Interrupt 2 Flag Set when external interrupt 2 is detected if the KSEN bit is set Firmware
248. cumulator not zero Description If any bit of the accumulator is set branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified Flags CY AC OV Example The accumulator contains OOH After executing the instruction sequence JNZ LABEL1 INC A JNZ LABEL2 the accumulator contains 01H and program execution continues at label LABEL2 Bytes 2 States 12 Cycles 2 Encoding 0111 0000 rel addr A 32 a intel Operation JZ rel Function Description Flags Example Bytes States Cycles Operation LCALL addr16 Function Description Flags INSTRUCTION SET REFERENCE JNZ PC PC 2 IF A 0 THEN PC lt PC rel Jump if accumulator zero If all bits of the accumulator are clear zero branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified CY AC OV The accumulator contains 01H After executing the instruction sequence JZ LABEL1 DECA JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2
249. d low clock mode machine cycle maskable interrupt MSB multiplexed bus n channel FET n type material nonmaskable interrupt npn transistor NRZI p channel FET p type material PC Glossary 4 intel ISR The firmware routine that services an interrupt One of four USB transfer types Interrupt transfer characteristics are small data non periodic low frequency bounded latency device initiated communication typically used to notify the host of device service needs Isochronous A stream of data whose timing is implied by its delivery rate One of four USB transfer types isochronous transfers provide periodic continuous communication between host and device The mode in which a device or component recognizes a high level logic one or a low level logic zero of an input signal as the assertion of that signal See also edge triggered The default mode upon reset low clock mode ensures that the Icc drawn by the 8x931 is less than one unit load Fc 3MHz One machine cycle equals six state times An interrupt that can be disabled masked by its individual mask bit in an interrupt enable register Most significant bit of a byte or most significant byte of a word A bus on which the data is time multiplexed with some of the address bits A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have a
250. d 01 no no no no no None N A Firmware into FIFO chg chg chg chg chg should always from CPU check TXFIF CNT written bits before loading and TXOVF after loading Data loaded 00 no no no 1 no None NAKs Only overrun into FIFO chg chg chg chg future FIFO error can FIFO error transactions occur here occurs Firmware should always check TXOVF before write CNT NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes TXEPEN and ATM are enabled 2 Future transactions are NAKed even if the transmit endpoint is stalled when RXSETUP 1 D 1 8x931AA 8x931HA USER S MANUAL Table D 1 Non isochronous Transmit Data Flow Continued New TX TX TX TXFIF TX TX TX USB Event TXFIF OVF Inter Comments 1 0 1 0 ERR ACK Void 1 1 rupt Response 01 10 Received IN 00 0 1 0 no no Set Send data ACK token data chg chg transmit received so transmitted interrupt no errors host ACKs Read marker advanced Received IN 01 10 1 0 0 no no Set Send data SIE times out token data chg chg transmit Read pointer transmitted interrupt reversed no ACK time out Received IN 01 10 no no 1 no no None NAK NAKs Received token but chg chg chg chg future Setup token RXSETUP transactions or transmit 1 except disabled so TXOE 0 SETUP IN tokens are NAKed 2 Received IN 01 10 1 0 0 no 1 Set Send
251. d lt dest opnd V src opnd Clear CLRA 0 Complement CPLA Ai lt Ai Rotate RXX A 1 SWAP A A3 0 o A7 4 Mnemoni dest r Notes Bytes States Machine emonic lt dest gt lt src gt yt Cycles A Rn Reg to acc 1 6 1 A dir8 Dir byte to acc 2 6 1 ANL A Ri Indir addr to acc 1 6 1 ORL XBL A data Immediate data to acc 2 6 1 dir8 A Acc to dir byte 2 dir8 data Immediate data to dir byte 3 CLR A Clear acc 1 6 CPL A Complement acc 1 6 RL A Rotate acc left 1 6 RLC A Rotate acc left through the carry 1 6 RR A Rotate acc right 1 6 RRC A Rotate acc right through the carry 1 6 SWAP A Swap nibbles within the acc 1 6 NOTES 1 See Instruction Descriptions on page A 9 A 5 8x931AA 8x931HA USER S MANUAL Table A 11 Summary of Move Instructions Move 1 Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt sre gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX lt dest gt lt src gt destination lt src lt code byte external mem lt A lt source in external mem A 6 Mnemonic lt dest gt lt src gt Notes Bytes States godes A Rn Reg to acc A dir8 Dir byte to acc A Ri Indir RAM to acc A data Immediate data to acc Rn A Acc to reg Rn dir8 Dir byte to reg Rn data Immediate data to reg dir8 A Acc to dir byte dir8 Rn Re
252. d Scan Output y o P1 7 VO TXD KSO7 Transmit Serial Data Keyboard Scan Output 2 7 0 VO A15 8 KSO15 8 Address Lines Keyboard Scan Output P3 0 VO OVRI Overcurrent Sense Input l P3 1 SOF Start of Frame 2 VO INTO External Interrupt 0 l P3 3 VO INT1 External Interrupt 1 4 VO TO KSO16 Timer 0 Input Keyboard Scan Output VO P3 5 VO T1 KSO17 Timer 1 Input Keyboard Scan Output VO P3 6 VO WR KSO19 Write Signal to External Memory Keyboard Scan Output P3 7 VO RD KSO18 DR Signal to External Memory Keyboard Scan utput 9 1 8x931AA 8x931HA USER S MANUAL intel 9 2 I O CONFIGURATIONS Each port SFR operates via type D latches as illustrated in Figure 9 1 for ports 1 and 3 A CPU write to latch signal initiates transfer of internal bus data into the type D latch A CPU read latch signal transfers the latched Q output onto the internal bus Similarly a read pin signal transfers the logical level of the port pin Some port data instructions activate the read latch sig nal while others activate the read pin signal Latch instructions are referred to as read modify write instructions see Read Modify Write Instructions on page 9 5 Each I O line may be in dependently programmed as input or output 9 3 PORT 1 AND PORT 3 Figure 9 1 shows the structure of ports 1 and 3 which have internal pullups An external source can pull the pin low Each port pin can be configured e
253. d XTAL2 are protected by on chip electrostatic discharge ESD devices D1 and D2 which are diodes parasitic to the R FETs They serve as clamps to Vcc and V amp Feedback resistor Ry in the inverter circuit formed from paralleled n and p channel FETs permits the PD bit in the PCON register Figure 14 1 on page 14 3 to disable the clock during powerdown Noise spikes at XTAL1 and XTAL2 can disrupt microcontroller timing To minimize coupling between other digital circuits and the oscillator locate the crystal and the capacitors near the chip and connect to XTALI XTAL2 and with short direct traces To further reduce the effects of noise place guard rings around the oscillator circuitry and ground the metal crystal case 13 2 intel MINIMUM HARDWARE SETUP For a more in depth discussion of crystal specifications ceramic resonators and the selection of C1 and C2 see Application Note AP 155 Oscillators for Microcontrollers in the Embedded Applications handbook See Table 1 3 on page 1 6 for the order number 13 3 2 On chip Oscillator Ceramic Resonator In cost sensitive applications you may choose a ceramic resonator instead of a crystal Ceramic resonator applications may require slightly different capacitor values and circuit configuration Consult the manufacturer s data sheet for specific information To Internal Timing Circuit External Quartz Crystal or Ceramic Resonator D1 A4143 03
254. data Only token data chg transmit with bit underrun FIFO transmitted interrupt stuff error error can FIFO error NAKs occur here occurs future Read pointer transactions reversed Received IN 01 10 1 0 1 Treated like a token with no void existing chg chg condition FIFO error and TXERR set Received IN 00 0 1 0 no no Set Send data Data is token chg chg transmit retransmitted without interrupt TXACK is set existing and TXERR is FIFO error cleared The but TXERR TXERR was set data set by retransmitte previous d host transaction ACKs when host time out NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes TXEPEN and ATM are enabled 2 Future transactions are NAKed even if the transmit endpoint is stalled when RXSETUP 1 D 2 intel DATA FLOW MODEL Table D 1 Non isochronous Transmit Data Flow Continued New TX TX TX TXFIF TX TX TX USB Event TXFIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void 1 1 rupt Response Data loaded 11 no no no no no None N A Firmware into FIFO chg chg chg chg chg should always from CPU check TXFIF CNT written bits before loading and TXOVF after loading Data loaded 01 10 no no no 1 no None NAKs future Only overrun into FIFO chg chg chg chg transactions FIFO error can FIFO error occur here occurs CNT Firmware not written should always
255. de 14 6 powerdown mode 14 8 reset initialization 13 6 unimplemented 3 5 C 1 Signal descriptions multi function pins B 1 Signature bytes values 16 4 verifying 16 1 16 4 SJMP instruction 8 SOF interrupt 5 7 SOF pin 5 14 SOFH 5 12 C 51 SOFL 5 13 C 52 Solutions OEM 1 8 SP C 3 C 52 Special function registers See SFRs State time 2 8 SUBB instruction A 4 SWAP instruction A 5 INDEX T 1 9 1 T1 0 9 1 10 2 T2 9 1 10 2 T2CON 10 1 10 3 10 10 10 17 11 12 C 53 baud rate generator 11 12 T2EX 9 1 10 2 10 11 11 12 T2MOD 10 1 10 3 10 10 10 16 C 54 TCON 10 1 10 3 10 4 10 6 10 8 C 5 C 55 interrupts 5 1 Tech support 1 7 TH2 TL2 baud rate generator 11 12 11 13 THx TLx x 0 1 2 10 3 C 5 C 57 C 58 Timer 0 10 4 10 8 applications 10 9 auto reload 10 5 interrupt 10 4 mode 0 10 4 mode 1 10 4 mode 2 10 5 mode 3 10 5 pulse width measurements 10 10 Timer 1 applications 10 9 auto reload 10 9 baud rate generator 10 6 interrupt 10 6 mode 0 10 6 mode 1 10 9 mode 2 10 9 mode 3 10 9 pulse width measurements 10 10 Timer 2 10 10 10 17 auto reload mode 10 12 baud rate generator 10 14 capture mode 10 11 clock out mode 10 14 interrupt 10 11 mode select 10 15 Timer counters 10 1 10 17 external input sampling 10 2 internal clock 10 1 interrupts 10 1 overview 10 1 10 2 registers 10 3 SFRs C 5 Index 5 8x931AA 8x931HA USER S
256. de memory EA ALE A4463 01 Figure 15 5 Bus Diagram for Example 1 8x931AA HA 15 6 intel EXTERNAL MEMORY INTERFACE 15 4 2 Example 2 16 bit Bus External ROM The hardware configuration for external program execution is shown in Figure 15 6 below Note that the 16 I O lines ports 0 and 2 are dedicated to bus functions during external Program Mem ory fetches Port 0 PO in Figure 15 6 serves as a multiplexed address data bus It emits the low byte of the Program Counter PCL as an address and then goes into a float state awaiting the arrival of the code byte from the Program Memory During the time that the low byte of the Pro gram Counter is valid on PO the signal ALE Address Latch Enable clocks this byte into an ad dress latch Meanwhile port 2 P2 in Figure 15 6 emits the high byte of the Program Counter PCH Then PSEN strobes the EPROM and the code byte is read into the microcontroller Microcontroller without on chip code memory A5005 01 Figure 15 6 Bus Diagram for Example 2 8x931AA HA 15 7 8x931AA 8x931HA USER S MANUAL intel 15 4 3 Example 3 16 bit Bus External EPROM and RAM In this example an 8x931AA HA operates with a 16 bit external address bus interfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM Figure 15 7 The 8x931 AA HA will assert RD and WR signals as needed during external RAM accesses The read strobe to external EPROM PSEN is used for external pr
257. dicate that the receive FIFO is being overwritten with new SETUP data When set the FIFO state FIF and read pointer resets and is locked for this endpoint until EDOVW is set This prevents a prior ongoing firmware read from corrupting the read pointer as the receive FIFO is being cleared and new data is being written into it This bit is cleared by hardware at the end of handshake phase transmission of the setup stage This bit is used only for control endpoints Under normal operation this bit should not be modified by the user For additional information on the operation of these bits see Appendix D Data Flow Model t The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface Figure 6 5 RXSTAT Receive FIFO Status Register 8x931AA 8x931HA USER S MANUAL intel RXSTAT Continued Address E2H Endpoint indexed Reset State 0000 0000B Endpoint Receive Status Register Contains the current endpoint status of the receive FIFO specified by EPINDEX 7 0 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Bit Number Mnemonic 4 EDOVW End Overwrite Flag This flag is set by hardware during the handshake phase of a SETUP stage It is set after every SETUP packet is received and must be cleared prior to reading the contents of the FIFO When set the FIFO state FIF and read pointer remains locked for this end
258. ding 00H 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction A 21 8x931AA 8x931HA USER S MANUAL intel Flags Example Bytes States Cycles Operation DEC byte Function Description A 22 CY AC OV The accumulator contains 56H 01010110B which represents the packed BCD digits of the decimal number 56 Register 3 contains 67H 01100111B which represents the packed BCD digits of the decimal number 67 The CY flag is set After executing the instruction sequence ADDC A R3 DAA the accumulator contains OBEH 10111110 and the CY and AC flags are clear The Decimal Adjust instruction then alters the accumulator to the value 24H 00100100B indicating the packed BCD digits of the decimal number 24 the lower two digits of the decimal sum of 56 67 and the carry in The CY flag is set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum of 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the accumulator contains 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DAA leaves the CY flag set and 29H in the accumulator since 30 99 129 The low byte of the sum can be interpreted to mean 30 1
259. duce overall system cost each KSI is implemented as a Schmitt trigger input incorporating an on chip pullup resistor that may be enabled or disabled through firmware A typical implementation of the keyboard scan matrix is shown in Figure 12 2 Note that the pul lup resistors are inactive until the pullup enable bit KSEN in KBCON is set 12 2 intel KEYBOARD CONTROL Keyboard Data and Interrupt KBCON 5 8x931Hx A5319 01 Figure 12 2 Keyboard Scan Matrix Application 12 2 1 Keyboard Interrupt Logic Firmware must perform the keyboard scan polling operation by generating a running 0 through the KSO outputs The sampling operation is interrupt driven using external interrupt 2 INT2 All KSI inputs are ANDed together so that a negative edge or level 0 on any of the KSI inputs causes INT2 to be generated setting KBCON s IE2 bit When this interrupt occurs firmware must read the KSI inputs to determine which one s caused the interrupt In order for the keyboard scan interrupt to work properly the following bits must be set in KBCON Figure 12 1 and IEN1 Figure 5 11 on page 5 25 The global interrupt enable bit must be set EA of IENO to allow the maskable interrupts to be individually enabled The enable bit for external interrupt 2 INT2 must be set EX2 of to allow an interrupt to be triggered in hardware The keyboard scan enable bit must be set
260. dynamically A typical interrupt event chain occurs as follows 1 An internal or external device initiates an interrupt request signal This signal connected to an input pin see Table 5 1 and periodically sampled by the 8x931 latches the event into a flag buffer 2 The interrupt handler compares the priority of the flag to the priority of other interrupts A high priority causes the handler to set an interrupt flag This signals the instruction execution unit to execute a context switch 3 This context switch breaks the flow of the instruction sequence The execution unit completes the current instruction prior to a save of the program counter PC and reloads the PC with the start address of a firmware service routine 4 The firmware service routine executes assigned tasks and as a final activity performs a RETI return from interrupt instruction 5 The RETI instruction signals completion of the interrupt resets the interrupt in progress priority and reloads the program counter 6 Program operation then continues from the original point of interruption Table 5 1 Interrupt System Input Signals Signal Tn Multiplexed Name Type Description With INT1 0 l External Interrupts 0 and 1 These inputs set bits IE1 0 in the P3 3 2 TCON register If bits IT1 0 in the TCON register are set bits IE1 0 are controlled by a negative edge trigger on INT1 INTO If bits IT1 0 are clear bits IE1 0 are controlled by a low level trig
261. e The time from the start of one SOF token to the start of the subsequent SOF token 1 msec consists of a series of transactions A USB device that provides a capability to the host For example an ISDN connection a digital microphone or speakers A packet that acknowledges or rejects a specific condition For examples see ACK and NACK Hub Interface Unit The host computer system where the USB host controller is installed This includes the host hardware platform CPU bus etc and the operating system in use A Universal Serial bus device that provides additional connections to the Universal Serial Bus The power conservation mode that freezes the core clocks but leaves the peripheral clocks running Current leakage from an input pin to power or ground Any member of the set consisting of the positive and negative whole numbers and zero The 16 bit address that the device generates See also external address The module responsible for handling interrupts that are to be serviced by user written interrupt service routines The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution The time delay between an interrupt request and the resulting break in the current instruction stream Glossary 3 8x931AA 8x931HA USER S MANUAL interrupt service routine interrupt transfer ISO isochronous data isochronous transfer level triggere
262. e 8x931 core and peripherals will not reset when a USB reset signal is detected After an 8x931 with URDIS set detects a USB reset signal it resets all the USB blocks including the USB SFRs sets the URST bit in PCONI and generates a USB reset interrupt For a complete description of the optional USB reset for the 8x93 1 see USB Re set Separation on page 5 17 13 4 3 Reset Operation When a reset is initiated whether externally or over the bus the port pins are immediately forced to their reset condition as a fail safe precaution whether the clock is running or not The external reset signal and the USB initiated reset signals are combined internally For an ex ternal reset the voltage on the RST pin must be held high for at least two machine cycles after the oscillator and on chip PLL stabilize approximately 5 ms For USB initiated resets a five bit counter in the reset logic maintains the signal for the required time Refer to Table 2 3 on page 2 9 The external reset signal is asynchronous to the internal clock The RST pin is sampled during State 5 Phase 2 of every machine cycle ALE and PSEN will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin that is for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin The port pins are driven to their reset state as soon as a valid high is detected on the RST pin regardless of whether the
263. e Generator 0 Timer 1 Timer 1 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 Note that timer 2 increments every state time 2T when it is in the baud rate generator mode In the baud rate formula that follows RCAP2H RCAP2L denotes the contents of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Fosc Serial I O Modes 1 and Baud Rate 32 x165536 RCAP2H RCAP2L NOTE When timer 2 is configured as a timer and is in baud rate generator mode do not read or write the TH2 or TL2 registers The timer is being incremented every state time and the results of a read or write may not be accurate In addition you may read but not write to the RCAP2 registers a write may overlap a reload and cause write and or reload errors Table 11 6 lists commonly used baud rates and shows how they are generated by timer 2 11 13 8x931AA 8x931HA USER S MANUAL EXEN2 Note availability of additional external interrupt Timer 1 Overflow Interrupt Request TCLCK A5205 01 Figure 11 5 Timer 2 in Baud Rate Generator Mode Table 11 6 Timer 2 Generated Baud Rates Oscillator Baud Rate Frequency RCAP2H RCAP2L Fosc 375 0 Kbaud 12 MHz FFH FFH 9 6 Kbaud 12 MHz FFH D9H 4 8 Kbaud 12 MHz FFH B2H 2 4 Kbaud 12 MHz FFH 64H 1 2Kbaud 12 MHz FEH C8H 300 0 baud 12 MHz FBH 1EH 110 0baud 12 MHz F2H AFH 300 0 baud 6 MHz FDH 8FH 110 0 baud 6 MHz F9H
264. e binary representation of the port index 2 Write 001 to bits 2 0 of the ports HPCON SFR Figure 7 9 on page 7 15 PORT_SUSPEND PORT_RESET Write 011 to bits 2 0 of the port s HPCON SFR If hub port 1 is specified the user cannot suspend the embedded function without also suspending the hub Firmware must suspend any non hub functionality associated with the embedded function prior to writing to HPCON This is done by placing any external device hardware into a low power suspend mode See SetPortFeature PORT SUSPEND Firmware on page 8 26 for additional information and a flowchart Write 010 to bits 2 0 of the ports HPCON SFR If port 1 is specified firmware needs to reset all non hub functionality in the microcontroller Upon writing to the embedded function s HPCON SFR a hardware reset is generated for the FIU and function FIFOs Firmware must gracefully shut down the application code peripherals etc prior to writing to port 1 s HPCON Once written the reset will be active in hardware for 10 11 ms See SetPortFeature PORT RESET Firmware on page 8 27 for additional information and a flowchart PORT POWER Set bit x of HPPWR where x is the port specified in the request index field Port power on is also supported for port 1 but only for reasons of port compatibility since power for the embedded function cannot be switched i e writing bit 1 of HPPWR does not affect any hardware
265. e pin arrangement Table B 7 contains the signal descriptions for all pins 64 FE AD7 P0 7 KSI7 63 DJ A8 P2 0 KSO8 62 F A9 P2 1 KSO9 61 A A10 P2 2 KSO10 60 A11 P23 KSO11 59 8 A12 P2 4 KSO12 58 F A13 P2 5 KSO13 57 F A14 P2 6 KSO14 56 F 15 P27 KSO15 AD6 P0 6 KSI6 E 1 Reserved NC AD5 P0 5 KSI5 Ej 2 Reserved NC 04 P0 4 KSI4 Reserved NC P0 3 KSI3 Reserved NC AD2 P0 2 KSI2 Dpo AD1 P0 1 KSI1 ADO P0 0 KSIO ECAP Vggp Vesp Vcc VocP P3 0 Vss P3 1 SOF Reserved NC P3 2 INTO View of component as Reserved NC P3 3 INT1 E 13 mounted on PC board Reserved NC P3 4 TO KSO16 0 14 Reserved NC P3 5 T1 KSO17 15 P3 6 WR KSO18 E 16 LEDO LED1 RST amp 31 PLLSEL 32 o e Q o gt lt P1 5 KSO5 23 P1 6 RXD KSO6 24 LED3 26 LED2 rj 27 XTAL1 E 28 XTAL2 E 29 P1 4 KSO4 22 P1 7 TXD KSO7 25 P1 0 T2 KSO0 18 P1 2 KSO r3 20 P1 3 KSO3 rJ 21 P3 7 RD KSO19 17 P1 1 T2EX KSO1 19 Notes Reserved pins must be left unconnected A5347 02 Figure B 4 8x931AA 64 pin QFP Package B 4 intel PIN DESCRIPTIONS Figure B 5 illustrates a diagram of the 8x931AA PLCC package Table B 1 and Table B 4 contain indexes of the pin arrangement Table B 7 contains the signal descriptions for all pins NC NC 3 A8 P2
266. e registers in the transmit FIFO SFR set are TXDAT TXCON TXFLG and TXCNTL These registers are defined in Figures 6 8 through 6 11 beginning on page 6 16 The registers in the receive FIFO SFR set are RXDAT RXCON RXFLG and RXCNTL These registers are defined in Figures 6 13 through 6 16 beginning on page 6 26 The transmit SFR set the receive SFR set EPCON TXSTAT and RXSTAT are endpoint in intel USB FUNCTION CAUTION Unless otherwise noted in the bit definition SFRs can be read and written by firmware All SFRs should be written using read modify write instructions only due to the possibility of simultaneous writes by hardware and firmware These instructions are listed in Read Modify Write Instructions on page 9 5 6 1 3 Endpoint indexed SFRs As indicated in the SFR memory maps in Table C 1 on page C2 certain USB SFRs are endpoint indexed These SFRs are implemented as banks of registers Endpoint indexed SFRs are accessed by means of the SFR address and the current contents of the EPINDEX register which selects the appropriate bank With the exception of hub endpoint 1 there is a bank of SFRs TXDAT TXCON TXFLG etc for each hub and function endpoint pair Thus the 8x931 with three function endpoint pairs plus hub endpoint 0 has four TXCON registers When EPINDEX 0000 0001 the function endpoint 1 TXCON is accessed When EPINDEX 0000 0010 the function endpoint 2 TXCON is access ed The contents of a
267. e state of more than 3 0 msec is detected on the hub root port For an in depth discussion of 8x931 suspend and resume see USB Power Control on page 14 7 Once the suspend has been detected the GSUS bit in the PCONI SFR is set and a microcontroller interrupt is generated See Firmware services the global suspend interrupt by setting the PD bit of the PCON SFR This shuts off the device s clocks and crystal oscillator placing the hub and embedded function in a USB suspend mode A resume event can be signaled in any of three ways 1 The hub repeater asynchronously detects a resume state due to resume signaling or a connect disconnect on the bus 2 The hub repeater detects a reset state on the bus root port 3 Anexternal interrupt powers up the entire device with a resume sequence initiated in firmware by setting the RWU bit in the PCONI SFR Figure 14 2 on page 14 4 7 6 2 Remote Connectivity During the suspend state of the hub logical connectivity can also be established if a physical con nection disconnection is made on one of the downstream ports or if a resume condition is sig naled on a port as shown in Figure 7 13 on page 7 26 7 6 2 1 Resume Connectivity The HRWUPE bit must be set in the HSTAT register Figure 7 6 on page 7 9 before the connect or disconnect of a downstream device can initiate a remote wake up If this bit is not set the downstream connect or disconnect will be ignored as a remote wake up e
268. e status of data packets in the receive FIFO specified by EPINDEX 7 0 RXFIF1 RXFIFO RXEMP RXFULL RXURF RXOVF Bit Number Bit Mnemonic Function 7 6 RXFIF1 0 Receive FIFO Index Flags read only These read only flags indicate which data packets are present in the receive FIFO see Table 6 6 on page 6 27 The RXFIF bits are updated after each write to RXCNT to reflect the addition of a data packet Likewise the RXFIF bits are cleared in sequence after each setting of the RXFFRC bit The next state table for RXFIF bits is shown below for operation in dual packet mode RXFIF1 0 Operation Flag Next RXFIF1 0 Next Flag 00 Adv WM X 01 Unchanged 01 Adv WM X 01 Unchanged 10 Adv WM X 11 Unchanged 00 Set RXFFRC 01 Set RXFFRC 00 Unchanged 00 Unchanged 11 Set RXFFRC 10 01 Unchanged 10 Set RXFFRC 00 Unchanged XX Rev WP X Unchanged Unchanged When the receive FIFO is programmed to operate in single packet mode RXSPM set in EPCON valid RXFIF states are 00 and 01 only In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF RXFIF is incremented by the USB and decremented by firmware Therefore setting RXFFRC decrements RXFIF immediately However a successful USB transaction within a frame increments RXFIF only at SOF For traceability you must check the RXFIF
269. e tens digit in the low nibble of the Accumulator and the ones digit in the B register The SWAP and ADD instructions move the tens digit to the high nib ble of the Accumulator and the ones digit to the low nibble 4 7 8x931AA 8x931HA USER S MANUAL intel 41 5 Data Transfers 4 1 5 1 Internal RAM Table 4 5 shows the menu of instructions that are available for moving data around within the internal memory spaces and the addressing modes that can be used with each one With a 12 MHz clock all of these instructions execute in either 1 or 2 us The MOV dest src instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator Remember the Upper 128 bytes of data RAM can be accessed only by indirect addressing and SFR space only by direct addressing Table 4 5 List of MCS9 51 Data Transfer Instructions Mnemonic Operation so pretiu Dir Ind Reg Imm MOV A src A src X X X MOV dest A dest A X X X MOV dest src dest src X X X MOV DPTR data16 dptr 16 bit immediate constant X 2 PUSH src INC SP MOV QSP src X 2 POP dest MOV dest SP DEC SP X 2 XCH A byte ACC and lt byte gt exchange data X X X 1 XCHD A Qi ACC and Ri exchange low nibbles X 1 NOTE In all MCS 51 devices the stack resides in on chip RAM and grows upwards
270. ead only An error condition has occurred with the transmission Complete or partial data has been transmitted The error can be one of the following 1 Data transmitted successfully but no handshake received 2 Transmit FIFO goes into underrun condition while transmitting The corresponding transmit done bit FTXDx in FIFLG is set when active For non isochronous transactions this bit is updated by hardware along with the TXACK bit at the end of the data transmission this bit is mutually exclusive with TXACK For isochronous transactions this bit is not updated until the next SOF 0 TXACK Transmit Acknowledge read only Data transmission completed and acknowledged successfully The corresponding transmit done bit FTXDx in FIFLG is set when active For non isochronous transactions this bit is updated by hardware at the end of data transmission along with the TXERR bit this bit is mutually exclusive with TXERR For isochronous transactions this bit is not updated until the next SOF Under normal operation this bit should not be modified by the user The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface For additional information on the operation of these bits see Appendix D Data Flow Model Figure 6 4 TXSTAT Transmit FIFO Status Register Continued 6 10 intel USB FUNCTION RXSTAT Address E2H Endpoi
271. eceipt of prevents the port from any USB traffic Firmware should SetPortFeature with propagating USB traffic suspend port 1 only after doing any PORT_SUSPEND necessary processing i e putting feature selector any external components in a low power state to place the embedded function into a suspended state 100 Resume Firmware should Causes port x to Places port 1 into the enabled state port write 100 to immediately drive a after 20 ms Firmware should HPCON upon state downstream for resume port 1 only after doing any receipt of at least 20 msec necessary processing to take the ClearPortFeature with PORT_SUSPEND feature selector followed by a low speed EOP and then places the port back in the enabled state embedded function out of the suspended low power state 7 16 intel USB HUB 7 5 2 Examining a Port s Status Using HPSTAT You can examine a port s status using the hub port status register HPSTAT as shown in Figure 7 10 on page 7 18 The HPSTAT SFR can show the status for any of the ports by using the HPINDEX SFR for indexing See Hub Port Indexing Using HPINDEX on page 7 23 for a de scription of how this indexing works HPSTAT gives the current D and D values for the selected port these implement the Get Bus State diagnostic aid to facilitate system debug See the Universal Serial Bus Specification HP STAT contains a bit that indicates when a low speed device is a
272. ecial Operating Modes 2 2 2 4 Reset Unit The reset unit resets the 8x931 to a known state A chip reset is initiated by asserting the RST pin or by a USB initiated reset For information on resets refer to Chapter 13 Minimum Hardware Setup NOTE The 8x931 can be programmed so a USB initiated reset does not cause a chip reset For additional information see USB Reset Separation on page 5 17 2 8 ARCHITECTURAL OVERVIEW Internal Clock Ferk XTAL1 Clock XTAL2 Generator On chip Peripherals PCON 1 PCON 5 0 Powerdown Low clock Mode Idle Mode 5324 01 Figure 2 4 8x931 Clock Circuit Table 2 3 8x931HA Operating Frequency XTAL1 Internal XTAL1 Clocks per PLLSEL Frequency AS State Comments Fosc 2 Tosc state 3 0 4 1 12 MHz 12 Mbps 6 MHz 3 2 PLL On Full Speed NOTES 1 The sampling rate is 4 times the USB rate 2 The internal frequency Ferk 1 is the clock signal distributed to the CPU and the 3 on chip peripherals Following device reset the CPU and on chip peripherals operate in low clock mode MHz until the LC bit in the PCON register is cleared In low clock mode there are four Togo periods per state Low clock mode does not affect the USB rate PLLSEL 0 is used during factory test only 2 9 8x931AA 8x931HA USER S MANUAL intel Table 2 4 8x931AA Operat
273. ecified bit is clear branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified Flags CY AC OV Example Input port 1 contains 11001010B and the accumulator contains 56H 01010110B After executing the instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 program execution continues at label LABEL2 Variations JNB bit rel Bytes 3 States 12 Cycles 2 Encoding 0011 0000 bit addr rel addr Operation JNB PC PC 3 IF bit 0 THEN PC lt PC rel JNC rel Function Jump if carry not set A 31 8x931AA 8x931HA USER S MANUAL intel Description If the CY flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The CY flag is not modified Flags CY AC OV zz Example The CY flag is set The instruction sequence JNC LABEL1 CPL CY JNC LABEL2 clears the CY flag and causes program execution to continue at label LABEL2 Bytes 2 States 12 Cycles 2 Operation JNC 2 IF CY 0 THEN lt PC rel JNZ rel Function Jump if ac
274. ect the mode with the SMO and SM1 bits and clear the REN bit For modes 2 and 3 also write the ninth bit to the TB8 bit 2 Wirite the byte to be transmitted to the SBUF register This write starts the transmission 11 2 2 2 Reception Modes 1 2 3 To prepare for a reception set the REN bit in the SCON register The actual reception is then ini tiated by a detected high to low transition on the RXD pin 11 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 Framing bit error detection is provided for the three asynchronous modes To enable the framing bit error detection feature set the SMODO bit in the PCON register see Figure 15 1 on page 15 3 When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found the hardware sets the FE bit in the SCON register see Figure 11 2 Firmware may examine the FE bit after each reception to check for data errors Once set only firmware or a reset can clear the FE bit Subsequently received frames with valid stop bits cannot clear the FE bit 11 7 8x931AA 8x931HA USER S MANUAL intel 11 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 Modes 2 and 3 provide a ninth bit mode to facilitate multiprocessor communication To enable this feature set the SM2 bit in the SCON register see Figure 11 2 When the multiproces
275. ects USB hub FIFOs and SFRs 0 Function Selects USB function FIFOs and SFRs 6 2 Reserved 1 0 EPINX1 0 Write zeros to these bits Endpoint Index EPINDEX EPINDEX Oxxx xx00 Function Endpoint 0 1xxx xx00 Hub Endpoint 0 Oxxx xx01 Function Endpoint 1 1xxx xx01 Hub Endpoint 1 Oxxx xx10 Function Endpoint 2 The EPINDEX register identifies the endpoint pair and selects the associated transmit and receive FIFO pair The value in this register plus SFR addresses select the associated bank of endpoint indexed SFRs TXDAT TXCON TXFLG TXCNTL RXDAT RXCON RXFLG RXCNTL EPCON TXSTAT and RXSTAT 6 6 Figure 6 2 EPINDEX Endpoint Index Register intel USB FUNCTION 6 2 USB FUNCTION SFRS This section contains the special function registers SFRs used by the 8x931 USB function EPCON Endpoint indexed Address E1H Reset State Endpoint 0 0011 0101B Function Endpoints 1 2 0001 0000B Endpoint Control Register This SFR configures the operation of the endpoint specified by EPINDEX 7 0 RXSTL Bit Number TXSTL Bit Mnemonic CTLEP RXSPM RXIE RXEPEN TXOE TXEPEN Function RXSTL TXSTL Stall Receive Endpoint Set this bit to stall the receive endpoint Clear this bit only when the host has intervened through commands sent down endpoint 0 When this bit is set and RXSETUP is clear the receive endpoint will respond with a STALL handshake to a valid OUT t
276. ed If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit Four source operand addressing modes are allowed register direct register indirect and immediate CY AC OV The accumulator hods 0C3H 11000011B and register 0 holds OAAH 10101010B The instruction ADD A RO will leave 6DH 01101101B in the accumulator with the AC flag cleared and both the carry flag and OV set to 1 6 1 Encoding 0010 0100 immed data ADD lt A data intel INSTRUCTION SET REFERENCE ADD A dir8 Bytes States 6 Cycles 1 Encoding 0010 direct addr Operation ADD A A dir8 ADD A Ri Bytes States 6 Cycles Encoding 0010 011i Operation ADD lt A Ri ADD A Rn Bytes States 6 Cycles 1 Encoding 0010 1 Operation ADD lt A Rn ADDC A lt src gt Function Add with carry Description Simultaneously adds the specified byte variable the CY flag and the accumulator contents leaving the result in the accumulator If there is a carry out of bit 7 CY the CY flag is set if
277. ed when the USB bus is idle The 8x931 enters suspend when there is a constant idle state on the bus lines for more than 3 0 msec When a device is in suspend state it draws less than 500 uA from the bus See also resume token packet A type of packet that identifies what transaction is to be performed on the bus USB Universal Serial Bus An industry standard extension to the PC architecture with a focus on Computer Telephony Integration consumer and productivity applications Glossary 6 intel Index A 15 8 9 1 A16 9 1 AC flag 4 2 C 39 ACALL instruction A 8 A 9 ACC C 3 C 6 AD7 0 9 1 ADD instruction A 4 ADDC instruction A 4 addrll A 2 addrl6 2 Address spaces See also Memory space SFRs Register file External file Compatibility AJMP instruction A 8 ALE caution 13 7 idle mode 14 6 ANL instruction for bits A 7 ANL instruction for bits A 7 Application notes 1 6 Arithmetic instructions 4 5 table of A 4 A 5 B B register C 6 as SFR C 3 Baud rate See Serial I O port Timer 1 Timer 2 bit51 A 2 Boolean Instructions 4 12 Broadcast address See Serial I O port Bulletin board service BBS 1 7 1 8 Bus cycles See External bus cycles C Capacitors bypass 13 2 CEX3 9 1 CJNE instruction A 8 Clock external 13 3 idle and powerdown modes 14 7 idle mode 14 6 on chip crystal 2 7 INDEX PLLSEL 2 9 PLLSEL2 0 13 1 powerdown mode 14 8 sources 13 2 USB rates
278. edded Microcontrollers and is also available individually 8x931AA 8x931HA Universal Serial Bus Microcontroller Order Number 273108 1 3 2 Application Notes The following MCS 51 microcontroller application notes also apply to the 8x931 AP 70 Using the Intel MCS 51 Boolean Processing Capabilities Order Number 203830 AP 223 8051 Based CRT Terminal Controller Order Number 270032 AP 252 Designing With the 80C51BH Order Number 270068 AP 425 Small DC Motor Control Order Number 270622 AP 410 Enhanced Serial Port on the 83C51FA Order Number 270490 AP 476 How to Implement PC Serial Communication Order Number 272319 Using Intel MCS9 51 Microcontrollers 1 4 APPLICATION SUPPORT SERVICES You can get up to date technical information from a variety of electronic support systems the World Wide Web the FaxBack service and Intel s Brand Products and Applications Support 1 6 intel GUIDE TO THIS MANUAL bulletin board service BBS These systems are available 24 hours a day 7 days a week provid ing technical information whenever you need it In the U S and Canada technical support representatives are available to answer your questions between 5 a m and 5 p m Pacific Standard Time PST Outside the U S and Canada please contact your local distributor You can order product literature from Intel literature centers and sales offices Table 1 1 lists the information you need to access these services Table 1 1 Intel Applic
279. ediately while USB events cause status change only at SOF TXFIF is incremented by firmware and decremented by the USB Therefore writes to TXCNT increment TXFIF immediately However a successful USB transaction any time within a frame decrements TXFIF only at SOF You must check the TXFIF flags before and after writes to the transmit FIFO and TXONT for traceability See the TXFLUSH bit in TXSTST NOTE To simplify firmware development configure control endpoints in single packet mode KKK Unchanged Reserved Values read from these bits are indeterminate Write zeros to these bits Transmit FIFO Empty Flag read only Hardware sets this bit when the write pointer has not rolled over and is at the same location as the read pointer Hardware clears this bit when the pointers are at different locations Regardless of ISO or non ISO mode this bit always tracks the current transmit FIFO status When set all transmissions are NAKed C 60 intel REGISTERS TXFLG Continued Endpoint indexed Address F5H Reset State 00xx 1000B Transmit FIFO Flag Register These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX 7 TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF Bit Number Bit Mnemonic Function TXFULL Transmit FIFO Full Flag read only Hardware sets this bit when the write pointer has rolled
280. egister is set TS7 0 are the lower eight bits of the 11 bit frame number issued with a SOF token If an artificial SOF is generated the time stamp remains at its previous value and it is up to firmware to update it These bits are set and cleared by hardware Address 81H Reset State 0000 0111B Stack Pointer The Stack Pointer register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the stack pointer is initialized to 07h after reset This causes the stack to begin at location 08h 7 0 SP Contents Bit Bit Number Mnemonic Function 7 0 SP 7 0 Stack Pointer Bits 0 7 of the stack pointer C 50 REGISTERS T2CON Address C8H Reset State 0000 0000B Timer 2 Control Register Contains the receive clock transmit clock and capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 EI Bit Function Number Mnemonic 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by firmware TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX sets EFX2 EXF2 does not cause an interrupt
281. egisters 8 8 40 40 Core interrupt vectors INTO INT1 TO T1 2 and Serial I O Yes Yes Yes Yes Keyboard INT2 Yes Yes No No PCA No No Yes Yes Parallel I O ports 4 4 4 4 Powerdown and idle power saving modes Yes Yes Yes Yes INT2 0 are external interrupts T2 0 are timer counter interrupts 2 1 4 MCS 51 Architecture Features The 8x931 retains the basic features of and is code compatible with the MCS 51 microcontroller Features of the MCS 51 architecture are discussed in the following paragraphs and summarized in Table 2 2 The MCS 51 architecture has separate program memory and data memory addresses spaces A sixteen bit address bus permits the 8x931 to address 64 Kbytes of program memory up to 8 Kbytes of on chip ROM and the remainder in external program memory and 64 Kbytes of data memory 256 bytes of on chip RAM and the remainder in external data memory The general purpose registers four banks of RO R7 and the special function registers SFRs are located in the data memory address space Refer to Chapter 3 Address Spaces for a description of the ad dress modes The MCS 51 architecture has four 8 bit parallel I O ports The pins of these ports can be individ ually programmed to provide an external bus to support special functions keyboard scanning timer counter interrupts etc or for general I O use Ports PO and P2 comprise a 16 line external 2 5 8x931AA 8x931HA USER S MANUAL intel
282. emains locked in the full position In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since overrun can only be caused by the USB RXOVF is updated only at the next SOF regardless of where the overrun occurred during the current frame T When set all transmissions are NAKed C 42 intel REGISTERS RXSTAT Endpoint indexed Address E2H Reset State 0000 0000B Endpoint Receive Status Register Contains the current endpoint status of the receive FIFO specified by EPINDEX Endpoint indexed SFR 7 0 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Bit Number Mnemonic Function 7 RXSEQ Receiver Endpoint Sequence Bit read conditional write This bit will be toggled on completion of an ACK handshake in response to an OUT token This bit will be set or cleared by hardware after reception of a SETUP token This bit can be written by firmware if the RXSOVW bit is set when written along with the new RXSEQ value NOTE Always verify this bit after writing to ensure that there is no conflict with hardware which could occur if a new SETUP token is received 6 RXSETUP 5 STOVW Received Setup Token This bit is set by hardware when a valid SETUP token has been received When set this bit causes received IN or OUT tokens to be NAKed until the
283. embles to a relative offset byte This is a signed two s complement offset byte which is added to the PC in two s complement arithmetic if the jump is executed The range of the jump is therefore 128 to 127 Program Memory bytes relative to the first byte following the instruction 4 13 8x931AA 8x931HA USER S MANUAL intel 4 1 7 Jump Instructions Table 4 9 shows the list of unconditional jumps Table 4 9 Unconditional Jumps in MCS 51 Devices Mnemonic Operation sate JMP addr Jump to addr 2 JMP A DPTR Jump to A DPTR 2 CALL addr Call subroutine at addr 2 RET Return from subroutine 2 RETI Return from interrupt 2 NOP No operation 1 The table lists a single JMP addr instruction but in fact there are three SJMP LJMP and AJMP which differ in the format of the destination address JMP is a generic mnemonic which can be used if the programmer does not care which way the jump is encoded The SJMP instruction encodes the destination address as a relative offset as described above The instruction is 2 bytes long consisting of the opcode and the relative offset byte The jump distance is limited to a range of 128 to 127 bytes relative to the instruction following the SJMP The LJMP instruction encodes the destination address as a 16 bit constant The instruction is 3 bytes long consisting of the opcode and two address bytes The destination address can be any where in the 64K Program
284. en For isochronous transactions it is not updated until the next SOF Under normal operation For additional information on the operation of these bits see Appendix D Data Flow Model The SIE will handle all sequence bit tracking This bit should be used only when initializing a new this bit should not be modified by the user configuration or interface C 44 intel REGISTERS RXSTAT Continued Address E2H Endpoint indexed Reset State 0000 0000B Endpoint Receive Status Register Contains the current endpoint status of the receive FIFO specified by EPINDEX Endpoint indexed SFR 7 0 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Bit Number Mnemonic Function 1 RXERR Receive Error read only Set when an error condition has occurred with the reception Complete or partial data has been written into the receive FIFO No handshake is returned The error can be one of the following conditions 1 Data failed CRC check 2 Bit stuffing error 3 A receive FIFO goes into overrun or underrun condition while receiving This bit is updated by hardware at the end of a valid SETUP or OUT token transaction non isochronous or at the next SOF on each valid OUT token transaction isochronous The corresponding FRXDx bit of FIFLG or FIFLG1 8x930Ax with 6EPP is Set when active This bit is updated with the RXACK bit at the end of data reception and is mutually exclusive w
285. en port using a Set Feature request with a Port Power feature selector The 8x931 firmware must respond to this port power request by setting or clearing the appropriate bit in the HPPWR SFR Figure 7 14 An exception to this is the internal downstream port port 1 which is statically powered on The host PC may inquire about a port s power status using Get Feature Port Power Firmware must respond to this inquiry by checking and reporting on the PPSTAT bit bit 4 of HPSTAT see Section 7 5 2 Examining a Port s Status Using HPSTAT 7 27 8x931AA 8x931HA USER S MANUAL intel HPPWR Hub Port Power Control Register This register is used to control power to the hub s downstream ports Address 9AH Reset State xxx0 001xB 7 0 HPPWR5 HPPWR4 HPPWRS3 HPPWR2 HPPWR1 Bit Bit Number Mnemonic Function 7 6 Reserved Write zeros to these bits 5 2 HPPWRS5 2 Port Power Control for USB Ports 5 2 HPPWR1 Bit 5 is power control for port 5 bit 4 for port 4 bit 3 for port 3 and bit 2 for port 2 These bits are set and cleared by firmware via a USB host request SetPortFeature with the PORT POWER feature selector These bits will also be cleared by hardware upon detection of an over current condition This is done to prevent oscillation of the UPWEN pin during an over current condition with bus powered devices A value of 1 enables power to the downstream port and put
286. endpoint 0 7 0 HRXDO HTXDO Bit Bit Function 7 2 Reserved Write zeros to these bits 1 HRXDO Hub Receive Done Endpoint O Hardware sets this bit to indicate that there is either 1 valid data waiting to be serviced in the receive data buffer for hub endpoint 0 and that the data was received without error and has been acknowledged or 2 that data was received with a FIFO error requiring firmware intervention to be cleared 0 HTXDO Hub Transmit Done Endpoint 0 Hardware sets this bit to indicate that one of two conditions exists in the transmit data buffer for hub endpoint 0 1 the transmit data has been transmitted and the host has sent acknowledgment which was successfully received or 2 a FIFO related error occurred during transmission of the data packet which requires servicing by firmware to be cleared NOTES 1 Note that because the HIFLG appears in the first SFR column it is a bit addressable SFR All bits are set in hardware and cleared by firmware Firmware can also set these bits for test purposes allowing the interrupt to be generated by firmware 2 For both HRXDO and HTXDO a 1 indicates that an interrupt is actively pending a 0 indicates that the interrupt is not active The interrupt status is shown regardless of the state of the corresponding interrupt enable bit in the HIE 8x931AA 8x931HA USER S MANUAL HPCON Indexed by HPINDEX
287. endpoint 1 supports up to two separate data sets of variable sizes abyte count register to store the number of bytes in the data sets protection against overwriting data in a full FIFO capability to retransmit the current data set All transmit FIFOs have the same architecture Figure 6 7 The transmit FIFO and its associated logic can manage up to two data sets data set 0 dsO and data set 1 ds1 The ability to have two data sets in the FIFO supports back to back transmissions When operating in dual packet mode the maximum packet size should be at a maximum half the FIFO size to ensure both packets will simultaneously fit in the FIFO see the Endpoint description in the Universal Serial Bus Specification 6 14 intel USB FUNCTION CPU Writes to FIFO Wits Pom Data Set 1 FIU Reads FIFO To USB Interface ADVRM Po Read Pointer Data Set 0 REVRP D Read Marker Byte Count Register TXONTL A5305 01 Figure 6 7 Transmit FIFO Outline The transmit process uses a write pointer as well as a read pointer and a read marker The CPU writes to the FIFO location specified by the write pointer which automatically increments by one after a write The read marker points to the first byte of data written to a data set and the read pointer points to the next FIFO location to be read by the function interface The read pointer au tomatically increments by one after a read When a good t
288. endpoint status of the receive FIFO specified by EPINDEX Endpoint indexed SFR 7 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Number Bit Mnemonic Function EDOVW End Overwrite Flag This flag is set by hardware during the handshake phase of a SETUP stage It is set after every SETUP packet is received and must be cleared prior to reading the contents of the FIFO When set the FIFO state FIF and read pointer remains locked for this endpoint until this bit is cleared This prevents a prior ongoing firmware read from corrupting the read pointer after the new data has been written into the receive FIFO This bit is only used for control endpoints NOTE Make sure the EDOVW bit is cleared prior to reading the contents of the FIFO RXSOVW Receive Data Sequence Overwrite Bit Write a 1 to this bit to allow the value of the RXSEQ bit to be overwritten Writing a 0 to this bit has no effect on RXSEQ This bit always returns 0 when read RXVOID Receive Void Condition read only This bit is set when no valid data is received in response to a SETUP or OUT token due to one of the following conditions 1 The receive FIFO is still locked 2 The EPCON registers RXSTL bit is set This bit is set and cleared by hardware For non isochronous transactions this bit is updated by hardware at the end of the transaction in response to a valid OUT tok
289. endpoints The hub handles control transfers using endpoint 0 with a maximum packet size of eight bytes 7 10 intel USB HUB Hub endpoint 1 supports interrupt transfers only and has no endpoint receive buffer Endpoint 1 is used to inform the host of a hub or port status change Figure 7 8 on page 7 13 illustrates the format used to transmit status change information to the host Since endpoint 1 transmits a single byte of information TXDAT Figure 7 7 on page 7 12 serves as the data buffer Endpoint op erations are primarily controlled by hardware and do not involve firmware except for the EPISTL and EPIEN bits in HSTAT Figure 7 6 Table 7 4 Hub Endpoint Configuration Hub Max Packet Endpoint Size Transfer Type Implementation 0 8 bytes Control Firmware controlled 1 1 byte Status Change Hardware Interrupt controlled 7 4 1 Endpoint Indexing Using EPINDEX The 8x931 hub endpoint 0 uses the same communication registers TXCNTL RXCNTL TX DAT RXDAT TXFLG RXFLG TXSTAT RXSTAT TXCON and RXCON as the embedded USB function endpoints The EPINDEX register used to access the registers of the USB func tion endpoints is also used to access the registers for hub endpoints To access the communication SFRs for the hub endpoints first write 1 to bit 7 of EPINDEX To access the internal USB function s registers write 0 to EPINDEX bit 7 Regardless of whether you are accessing
290. er 00H FFH in internal data RAM or an SFR Bits 00H 7FH are the 128 bits in byte locations 20H 2FH in the on chip RAM Bits 80H FFH are the 128 bits in the 16 SFR s with addresses that end in or 8H 80H 88H 90H FOH F8H Table A 5 Notation for Destinations in Control Instructions Destination Description Address a rel A signed two s complement 8 bit relative address The destination is 128 to 127 bytes relative to first byte of the next instruction addr11 An 11 bit destination address The destination is in the same 2 Kbyte block of memory as the first byte of the next instruction addr16 A 16 bit destination address A destination can be anywhere within the same 64 Kbyte region as the first byte of the next instruction intel 2 OPCODE MAP INSTRUCTION SET REFERENCE Table A 6 Instructions for 8x931 Peripheral Controllers Bin 0 1 2 3 4 5 6 7 8 F 0 NOP AJMP LUMP RR INC INC INC INC addr11 addri6 A dir8 Ri Rn 1 JBC ACALL LCALL RRC DEC DEC DEC DEC bit rel addr11 addri6 A A dir8 Ri Rn 2 JB AJMP RET RL ADD ADD ADD ADD bit rel addr11 A A data A dir8 A Ri A Rn 3 JNB ACALL RETI RLC ADDC ADDC ADDC ADDC bit rel addr11 A A data A dir8 A Ri A Rn 4 AJMP ORL ORL ORL ORL ORL 11 dir8 A dir8 data A data A dir8 A Ri 5 ACALL ANL ANL ANL ANL ANL 11 dir8 A dir8 data A data A dir8 A Ri 6 XRL XR
291. er Counter 1 Low Byte 8BH TH1 Timer Counter 1 High Byte 8DH TL2 Timer Counter 2 Low Byte CCH TH2 Timer Counter 2 High Byte CDH TCON Timer Counter 0 and 1 Control 88H TMOD Timer Counter 0 and 1 Mode Control 89H T2CON Timer Counter 2 Control C8H T2MOD Timer Counter 2 Mode Control C9H RCAP2L Timer 2 Reload Capture Low Byte CAH RCAP2H Timer 2 Reload Capture High Byte CBH C 5 8x931AA 8x931HA USER S MANUAL intel C 2 SFR DESCRIPTIONS This section contains descriptions of all 8x931 SFRs They are presented in alphabetical order NOTE SFR bits are firmware read write unless otherwise noted in the bit definition SFRs may be accessed only as bytes they may not be accessed as words ACC Address EOH Reset State 0000 0000B Accumulator ACC provides SFR access to the accumulator Instructions in the MCS 51 architecture use the accumulator as both source and destination for calculations and moves 7 0 Accumulator Contents Bit Bit Number Mnemonic Function 7 0 ACC 7 0 Accumulator B Address FOH Reset State 0000 0000B B Register The B register is used during multiply and divide operations For other instructions it can be treated as another scratch pad register 7 0 B Register Contents Bit Bit Number Mnemonic Function 7 0 B 7 0 B Register C 6 intel REGISTERS DPH Address 83H Reset State 0000 0000B Data Pointer High DPH is the upper byte of the 16 bit
292. er Mnemonic Function 7 5 Reserved Write zeros to these bits 4 URDIS USB Reset Disable When cleared by firmware a chip reset occurs upon receiving of a USB reset signal This resets the MCS 51 microcontroller core USB blocks and all peripherals When set by firmware the core and peripherals will not reset when a USB reset signal is detected Upon detecting a USB reset signal the 8x931 resets all the USB blocks FIFOs FIU SIE and transceiver sets the URST bit and generates a USB reset interrupt refer to the description of URST 3 URST USB Reset Flag This flag will be set by hardware when a USB reset occurs regardless of whether the ESR bit in the IEN1 register is enabled or disabled The URST also serves as the interrupt bit ORed with GRSM and GSUS bits to generate an interrupt Should be cleared by firmware when serving the USB reset interrupt 2 RWU Remote Wake up Bit 1 wake up This bit is used by the USB function to initiate a remote wake up Set by firmware to drive resume signaling on the USB lines to the host or upstream hub Cleared by hardware when resume signaling is done NOTE not set this bit unless the USB function is suspended GSUS 1 and GRSM 0 See Figure 14 3 on page 14 11 Firmware should prioritize GRSM over GSUS if both bits are set simultaneously Figure 14 2 PCON1 USB Power Control Register 14 4 intel SPECIAL OPERATING MODES 7
293. ercurrent input detect which is multiplexed with P3 0 When set a low on P3 0 OVRI pin will trigger over current detection logic When this bit is 0 the over current detection logic is disabled HRWUPE Hub Remote Wake up Enable Bit Set if the device is currently enabled to request remote wake up This bit is modified through the SetFeature and ClearFeature requests using the DEVICE REMOTE WAKEUP feature selector When 0 the hub blocks resume signaling for connect disconnect and resume events detected on downstream ports NOTE Donotset this bit until after the hub is enumerated and the host issues a SET FEATURE command with a DEVICE REMOTE WAKEUP feature selector EP1STL EP1EN Hub Endpoint 1 Stall Field Set to 1 via the USB SetFeature request with endpoint stall feature selector When 1 will force a stall response when endpoint 1 is addressed Reset with USB ClearFeature request with endpoint stall feature selector Hub Endpoint 1 Enable Set to 1 upon receipt of a USB SetConfiguration request value of 0001H Endpoint 1 cannot respond unless this bit is set Bit is reset upon receipt of configuration value other than 0001H or a system or USB reset NOTE This bit must be set in order for the UPWEN pin to enable power to the downstream ports Downstream power cannot be applied until this is done OVISC Hub Over current Indicator Status Change read clear only Set to 1
294. es Machine y Cycles A Rn Reg to acc 1 6 1 A dir8 Dir byte to acc 2 6 1 ADD A Ri Indir addr to acc 1 6 1 A data Immediate data to acc 2 6 1 A Rn Reg to from acc with carry 1 6 1 ADDC A dir8 Dir byte to from acc with carry 2 6 1 SUBB A Ri Indir RAM to from acc with carry 1 6 1 A data Immediate data to from acc with carry 2 6 1 Increment INC DPTR DPTR DPTR 1 Increment INC byte byte lt byte 1 Decrement DEC byte byte byte 1 Machine Cycles Mnemonic lt dest gt lt src gt States INC A acc 1 6 1 DEC Reg 6 dir8 Dir byte 2 6 Ri Indir RAM 1 6 DPTR Data pointer 1 12 2 INSTRUCTION SET REFERENCE Table A 9 Summary of Multiply Divide and Decimal adjust Instructions Multiply Divide Decimal adjust ACC for Addition BCD MUL AB DIV AB DAA B A AxB A Quotient B Remainder 1 Machine Mnemonic lt dest gt lt src gt Notes Bytes States Cycles MUL AB Multiply A and B 1 24 4 DIV Divide A by B DA Decimal adjust acc NOTES 1 See Instruction Descriptions on page A 9 Table A 10 Summary of Logical Instructions Logical AND ANL lt dest gt lt src gt dest dest A src Logical OR ORL lt dest gt lt src gt dest opnd lt dest opnd V src opnd Logical Exclusive OR XRL lt dest gt lt src gt dest opn
295. es that data is written to the FIFO in the following sequence 1 The CPU writes data bytes to TXDAT 2 The CPU writes the number of bytes that were written to TXDAT to the byte count register TXCNTL TXCNTL must be written after the write to TXDAT to guarantee data integrity The function interface reads the byte count register to determine the number of bytes in the set 6 3 4 Transmit Data Set Management Two read only data set index bits FIF1 0 in the TXFLG register indicate which data sets dsO and or ds1 have been written into the FIFO and are armed ready for transmission See the left side of Table 6 4 FIFx 1 indicates that data set x has been written and is armed Following reset FIF1 0 00 signifying an empty FIFO FIF1 0 also determine which data set is written next Note that FIFO specifies the next data set to be written except for the case of FIF1 0 11 In this case further writes to TXDAT or TXCNTL are ignored NOTE To simplify firmware development it is recommended that you utilize control endpoints in single packet mode only Two events cause the data set index bits to be updated Anew data set is written to the FIFO The 8x931 writes bytes to the FIFO via TXDAT and writes the number of bytes to TXCNTL The data set index bits are updated after the write to TXCNTL This process is illustrated in Table 6 4 A data set in the FIFO is successfully transmitted The function interface reads a data set fro
296. escription Flags Example Bytes States INSTRUCTION SET REFERENCE Multiply Multiplies the unsigned 8 bit integers in the accumulator and register B The low byte of the 16 bit product is left in the accumulator and the high byte is left in register B If the product is greater than 255 OFFH the OV flag is set otherwise it is clear The CY flag is always clear CY AC OV 0 3 The accumulator contains 80 50H and register B contains 160 OAOH After executing the instruction MUL AB which gives the product 12 800 3200H register B contains 32H 00110010B the accumulator contains 00H the OV flag is set and the CY flag is clear 1 24 4 Encoding 1010 0100 MUL lt low byte of A X B lt high byte of A X B No operation Execution continues at the following instruction Affects the PC register only CY AC OV You want to produce a low going output pulse on bit 7 of Port 2 that lasts exactly 11 states A simple CLR SETB sequence generates an one cycle pulse so four additional cycles must be inserted You can insert the four additional cycles if no interrupts are enabled with the following instruction sequence CLR P2 7 NOP NOP NOP NOP SETB P2 7 A 43 8x931AA 8x931HA USER S MANUAL intel Cycles 1 Encoding 0000 0000 Operation NOP PC lt PC 1 ORL dest src Function Logical OR for byte variables
297. eset State 001d 0000B Power Control Register Contains the power off flag POF and bits for enabling the idle and powerdown modes and two general purpose flags 7 0 SMOD1 SMODO LC POF GF1 GFO PD IDL Bit Bit Function Number Mnemonic 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 11 10 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 are to the SMO bit See the SCON register Figure 11 2 on page 11 4 5 Low clock Mode Enable Setting this bit forces the internal clock Fg distributed to the CPU and peripherals but not the USB module to 3 MHz This bit is automatically set after a reset Clearing this bit through firmware returns Fo to the normal clock frequency 4 Power Off Flag Set by hardware on the rising edge of Vcc set or cleared by software This flag allows detection of a reset caused by a power failure Vcc must remain above 3 volts to retain this bit 3 General Purpose Flag Set or cleared by firmware One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 General Purpose Flag Set or cleared by firmware One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 Powe
298. essful USB transaction anytime in a frame will only decrement TXFIF at SOF TXERR TXACK and TXVOID can only be caused by USB thus they are updated at the end of every valid transaction 3 NOTE This table assumes TXEPEN are enabled D 6 DATA FLOW MODEL Table D 2 Isochronous Transmit Data Flow in Dual packet Mode Continued New at next SOF TX TX TX TX TXFIF USB 1 0 Event m TX TX TX poi a Hee Response Comments ps ERR voia 52 2 rup Received IN 10 01 1 0 0 no 1 None Send data Only a FIFO token data chg with underrun error transmitted bitstuffing can occur FIFO error error here Read occurs marker advanced Received IN 11 1 0 1 no 1 None Timeout Treated like a token with no no chg no void condition existing FIFO chg chg chg error Received IN 11 0 0 1 no no None Timeout Endpoint not token but TXOE chg chg enabled for 0 transmit but no NAK for ISO Receive SOF 10 01 no no no no no None None Host never read indication chg chg chg chg chg SOF last frame s interrupt ISO packet set Read marker ASOF and pointer set advanced oldest packet is flushed from FIFO Data loaded into 11 no no no 1 no None N A CNT written FIFO from CPU chg chg chg chg when CNT written TXFIF 11 will set TXOVF bit Firmware should always check TXFIF bits before loading NOTES 1 These are sticky bits
299. et Received IN 10 01 0 1 0 no no Set Send data Data is token chg chg transmit retransmitted without interrupt TXACK is set existing and TXERR is FIFO error cleared The but TXERR TXERR was set data set by retransmitte previous d host transaction ACKs when host time out Data loaded 11 no no no 1 no None N A Writing into into FIFO chg chg chg chg CNT when from CPU TXFIF 11 CNT written sets TXOVF bit Firmware should always check TXFIF bits before loading NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes TXEPEN and ATM are enabled 2 Future transactions are NAKed even if the transmit endpoint is stalled when RXSETUP 1 D 4 DATA FLOW MODEL Table D 2 Isochronous Transmit Data Flow in Dual packet Mode New at next SOF TX TX TX TX TXFIF USB 1 0 Event 16 TX TX TX a aes Hk Response Comments oy ERR ACK Void 12 12 rup 00 Received IN 00 no no 1 no no None Timeout No data was token but no chg chg chg chg loaded so data or TXOE 0 timeout i e no response This event should never happen Data loaded into 01 no no no no no None N A Firmware FIFO from CPU chg chg chg chg chg should always CNT written check TXFIF bits before loading and TXOVF after loading Data loaded into 00 no no no 1 no None N A Only overrun FIFO FIFO chg chg chg chg FIFO error can error occur here
300. et of the MCS 51 architec ture A functional block diagram of the 8x931 is shown in Figure 2 2 The 8x931 contains a microcon troller core a USB module a keyboard control interface on chip ROM optional and RAM four 8 bit parallel ports and on chip peripherals timer counters and serial port The USB module op erates in conjunction with the CPU to provide the capabilities of a USB device It supports all four types of USB data transfers control isochronous interrupt and bulk Dedicated pinouts are provided for USB signals The 8x931 is available in ROMless and factory programmed ROM versions in 64 pin S DIP 64 pin QFP and 68 pin PLCC packages See Appendix B for package diagrams pin assignments and signal descriptions Table 2 1 lists the on chip RAM and ROM memory options 2 2 intel ARCHITECTURAL OVERVIEW Table 2 1 8x931 Memory Options On chip Memory 8x931AA 8x931HA Hubless Hub ROM RAM Kbytes Bytes 80931AA 80931HA 0 256 83931AA 83931HA 8 256 The 8x931 provides a rich set of microcontroller features The following sections describe the major features Table 2 2 on page 2 4 summarizes these features and provides an item by item comparison of the 8x930Hx and 8x93 1 and the 8 930 and 8x931Ax The 8x931 is based on the MCS 51 architecture whereas the 8 930 is based on the MCS 251 architecture For detailed description of the 8xC51Fx hardware programmer s model a
301. et the RI bit in the SCON register to generate an interrupt This ensures that the CPU is not interrupted by command frames addressed to other devices If desired you may enable the automatic address recognition feature in mode 1 In this configu ration the stop bit takes the place of the ninth data bit The RI bit is set only when the received command frame address matches the device s address and is terminated by a valid stop bit NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 1 setting the SM2 bit in the SCON register in mode 0 has no effect To support automatic address recognition a device is identified by a given address and a broad cast address intel SERIAL I O PORT 11 5 1 Given Address Each device has an individual address that is specified in the SADDR register the SADEN reg ister is a mask byte that contains don t care bits defined by zeros to form the device s given ad dress These don t care bits provide the flexibility to address one or more slaves at a time To address a device by its individual address the SADEN mask byte must be 1111 1111 The follow ing example illustrates how a given address is formed SADDR 01010110 SADEN 11111100 Given 0101 01XX The following is an example of how to use given addresses to address different slaves Slave A SADDR 11110001 Slave C SADDR 11110010 SADEN 11111010 SADEN 11111101 Given 11
302. f 0001H Endpoint 1 cannot respond unless this bit is set Bit is reset upon receipt of configuration value other than 0001H or a system or USB reset NOTE This bit must be set in order for the UPWEN pin to enable power to the downstream ports Downstream power cannot be applied until this is done 3 OVISC Hub Over current Indicator Status Change read clear only Set to 1 if change is detected in the over current status even if the condition goes away before it is detected by firmware Cleared via a USB ClearFeature request with C HUB OVER CURRENT feature selector Cleared to 0 if no change 2 Reserved The value read from this bit is indeterminate Write a zero to this bit 1 Latest Over current Indicator read only Hardware sets and clears this bit via the OVRI input pin 1 indicates an over current condition 0 indicates normal power operation 0 Reserved The value read from this bit is indeterminate Write a zero to this bit Bits 1 and 3 are returned in response to a Get Hub Status request from the USB host This response is a four byte field with zero padding MSB at left 0000 0000 0000 00 3 0 0000 0000 0000 00 1 0 Figure 7 6 HSTAT Hub Status and Configuration Register Continued 74 USB HUB ENDPOINTS Table 7 4 gives the packet size transfer type and implementation of the 8x931 hub endpoints Bulk and isochronous transfers are not supported by the hub
303. f IENO 7 EA and IENI 2 are set As soon as resume signaling is detected on the USB lines the oscillator is restarted After executing the resume interrupt service routine the 8x931 resumes operation from where it was when it was in terrupted by the suspend interrupt For additional information see Global Resume Mode on page 14 9 5 2 8 3 USB Remote Wake up The 8x931 can also initiate resume signaling to the USB lines through remote wake up of the USB function while it is in powerdown idle mode While in powerdown mode remote wake up has to be initiated through assertion of an enabled external interrupt The external interrupt has to be enabled and it must be configured with level trigger and with higher priority than a suspend re sume interrupt An external interrupt restarts the clocks to the 8x931 and program execution branches to the external interrupt service routine Within this external interrupt service routine you must set the remote wakeup bit RWU in PCONI to drive resume signaling on the USB lines to the host or upstream hub After executing the external ISR the program continues execution from where it was put into powerdown mode and the 8x931 resumes normal operation For additional information see USB Remote Wake up on page 14 10 5 2 9 USB Reset Separation The 8x931 features an optional USB reset that functions independently from the chip reset When the PCON1 SFR s URDIS bit is set the 8x931 core and periphera
304. f a SetPortFeature request with a PORT SUSPEND feature selector Port x x 2 3 4 5 This bit is set by hardware upon completion of the firmware initiated resume process Port 1 This bit is set by hardware 20 msec after the next EOF2 point after completion of the resume process NOTE Bits are returned as part of the second word 2 bytes in response to a Get Port Status request from the USB host The upper 11 MSbs are reserved and always 0 per USB 1 0 0000 0000 000 4 3 2 1 0 MSB at left 8x931AA 8x931HA USER S MANUAL intel HPSC Continued Indexed by HPINDEX Address D5H Reset State xxx0 0000B Hub Port Status Change Register This register indicates a change in status for a port including over current reset suspend low speed device enable and connect status 7 RSTSC PSSC PESC PCSC Bit Number Bit Mnemonic Function PESC PCSC Port Enable Disable Status Change read clear only This bit s status does not change due to USB requests This bit is cleared by firmware via the USB host request ClearPortFeature with a C_PORT_ENABLE feature selector 1 indicates port enabled disabled status change 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware due to hardware events only this bit indicates the port was disabled due to babble physical disconnects or overcurrent Port 1 This bit is set by hardware at the EOF2
305. f data F5H page 6 21 packets in the transmit FIFO specified by EPINDEX TXSTAT Endpoint Transmit Status Register Contains the endpoint FAH page 6 9 status of the transmit FIFO specified by EPINDEX 6 3 8x931AA 8x931HA USER S MANUAL EPCON EPINDEX FADDR FIE FIFLG RXCNTL RXCON RXDAT RXFLG RXSTAT TXCNTL TXCON TXDAT TXFLG TXSTAT 7 0 RXSTL TXSTL CTLEP RXSPM RXIE RxEPEN TXOE TXEPEN HORF EPINX1 EPINXO Function Address ES FRXIE2 FTXIE2 FRXIE1 FTXIE1 FRXIEO FTXIEO FRXD2 FTXD2 FRXD1 FTXD1 FRXDO FTXDO T E BC4 BC3 BC2 BC1 BCO RXCLR us Rxiso ARM ADVWM REVWP Receive Data Byte RXFIF1 RXFIFO ne RXEMP RXFULL RXURF RXOVF RXSEQ RXSETUP srovw EDOVvW Rxsovw nxvoip RXERR RXACK BC4 BC3 BC2 BC1 BCO TXCLR TXISO AbvRM REVRP Transmit Data Byte TXFIF1 TXFIFO TXEMP TXFULL TXURF TXOVF TXSEQ TXFLUSH sow TXVOID TXERR TXACK dexed 6 4 Figure 6 1 Bits of the USB Function SFRs The registers in the FIU SFR set are EPINDEX EPCON TXSTAT RXSTAT SOFL SOFH and FADDR The SOFH and SOFL SFRs are defined in Figure 5 5 on page 5 12 and Figure 5 6 on page 5 13 The remaining registers are defined in Figures 6 2 through 6 6 Th
306. f the other conditions mentioned above however Specific details of the 8x931AA are covered in Appendix E 8x931AA Design Considerations Upon detection of a resume condition the 8x931 applies power to the USB transceivers the crys tal oscillator and the PLL although the PLL output is still gated off The device begins timing two different time points T1 and T2 as described in Chapter 11 of the Universal Serial Bus Spec ification After the clocks are restarted the CPU program continues execution from where it was when the device was put into powerdown mode The device then services the resume interrupt service rou tine After executing the resume ISR the 8x931 continues operation from the point where it was interrupted by the suspend interrupt 14 9 8x931AA 8x931HA USER S MANUAL intel 14 4 3 USB Remote Wake up The 8x931 can initiate resume signaling to the USB lines through remote wake up of the USB function while it is in powerdown mode While in powerdown mode remote wake up has to be initiated through assertion of an enabled external interrupt The external interrupt has to be en abled and it must be configured with level trigger and with higher priority than a suspend resume interrupt A function resume restarts the clocks to the 8x931 and program execution branches to an external interrupt service routine Within this external interrupt service routine you must ensure GRSM 0 If GRSM is clear set the remote wa
307. firmware intervention to be cleared 8x931AA 8x931HA USER S MANUAL intel HADDR Address 97H Reset State 0000 0000B Hub Address Register This SFR holds the address for the hub device During bus enumeration it is written with a unique value assigned by the host 7 0 Hub Address Bit Number Function 7 Reserved Write a zero to this bit 6 0 Hub address register Updated using a SET_ADDRESS USB host request This address is used by the HIU to perform token decoding HIE Address A1H Reset State Xxxx xx00B Hub Interrupt Enable Register Enables and disables the receive and transmit done interrupts for hub endpoint 0 7 0 E HRXEO HTXEO Se TUS Function 7 2 Reserved Write zeros to these bits 1 HRXEO HRXEO Enable the hub endpoint 0 receive done interrupt HRXDO 0 HTXEO HTXEO Enable the hub endpoint 0 transmit done interrupt HTXDO For both bits 1 means the interrupt is enabled and will cause an interrupt to be signaled to the microcontroller A 0 means the associated interrupt source is disabled and cannot cause an interrupt even though its value is still reflected in the HIFLG register intel REGISTERS HIFLG Address E8H Reset State Xxxx xx00B Hub Interrupt Flag Register Contains the hub s transmit and receive done interrupt flags for hub
308. for transmission upon reset For hub endpoint 0 EPINDEX 1000 0000 bits 5 and 4 are hard wired to 1 since hub endpoint 0 is always a control endpoint 6 8 Figure 6 3 EPCON Endpoint Control Register Continued TXSTAT Endpoint indexed USB FUNCTI Address Reset State F2H 0xx0 0000B Endpoint Transmit Status Register Contains the current endpoint status of the transmit FIFO specified ON by EPINDEX 7 0 TXSEQ TXFLUSH TXSOVW TXVOID TXERR TXACK Bit Bit Number Mnemonic Function 7 Transmitter s Current Sequence Bit read conditional write t This bit will be transmitted in the next PID and toggled on a valid ACK handshake This bit is toggled by hardware on a valid SETUP token This bit can be written by firmware if the TXSOVW bit is set when written together with the new TXSEQ value 6 5 Reserved Write zeros to these bits 4 TXFLUSH Transmit FIFO Packet Flushed read only When set this bit indicates that hardware flushed a stale ISO data packet from the transmit FIFO due to a TXFIF1 0 11 at SOF To guard against a missed IN token in ISO mode if with TXFIF1 0 11 no IN token is received for the current endpoint hardware automatically flushes the oldest packet and decrements the TXFIF1 0 value 3 TXSOVW Transmit Data Sequence Overwrite Bit t Write a 1 to this bit to allow the value of the TXSEQ bit to be overwritten Writing a 0
309. g the instruction sequence PUSH DPL PUSH DPH the stack pointer contains OBH and on chip RAM locations OAH and OBH contain 01H and 23H respectively 2 12 A 47 8x931AA 8x931HA USER S MANUAL intel Cycles Operation RET Function Description Flags Example Bytes States Cycles Operation RETI Function Description Flags A 48 2 Encoding 1100 0000 direct addr PUSH SP lt SP SP lt dir a Return from subroutine Pops the high and low bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address which normally is the instruction immediately following ACALL or LCALL CY AC OV The stack pointer contains OBH and on chip RAM locations OAH and OBH contain 01H and 23H respectively After executing the instruction RET the stack pointer contains 09H and program execution continues at location 0123H 1 12 2 Encoding 0010 0010 Return from interrupt RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16 bit return address The stack pointer is decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed Program execution continues at the ret
310. g to dir byte dir8 dir8 Dir byte to dir byte dir8 Ri Indir RAM to dir byte dir8 data Immediate data to dir byte Ri A Acc to indir RAM Ri dir8 Dir byte to indir RAM Ri data Immediate data to indir RAM DPTR data16 Load Data Pointer with a 16 bit const A A DPTR Code byte relative to DPTR to acc A A PC Code byte relative to PC to acc A Ri External mem 8 bit addr to acc A DPTR External mem 16 bit addr to acc Ri A Acc to external mem 8 bit addr DPTR A Acc to external mem 16 bit addr NOTES 1 Instructions that move bits are in Table A 13 intel INSTRUCTION SET REFERENCE Table A 12 Summary of Exchange Push and Pop Instructions Clear Bit Set Bit Mnemonic Exchange Contents lt dest gt lt src gt A src opnd Exchange Digit XCHD dest src A3 0 lt on chip RAM bits 3 0 Push PUSH src SP lt SP 1 SP src Pop POP dest dest lt SP SP lt SP 1 Mnemonic lt dest gt lt src gt Notes Bytes States Machine Y y Cycles A Rn Acc and reg 1 XCH A dir8 Acc and dir addr 2 A Ri Acc and on chip RAM 8 bit addr 1 A Ri Acc and low nibble in on chip RAM 1 ACHE 8 bit addr PUSH dir8 Push dir byte onto stack POP Dir8 Pop dir byte from stack Table A 13 Summary of Bit Instructions Complement Bit AND Carry with Bit AND Carry with Complement of Bit OR Carry with Bit ORL Carry with Complement of Bit Move Bit to Ca
311. ger on INT1 0 KSI7 0 l Keyboard Scan Input Schmitt trigger inputs with firmware AD7 0 enabled internal pullup resistors used for the input side of the P0 7 0 keyboard scan matrix NOTE Cther signals are defined in their respective chapters and in Appendix B Pin Descriptions 5 1 8x931AA 8x931HA USER S MANUAL intel Figure 5 1 illustrates the interrupt control system The 8x931 has ten maskable interrupt sources These include two external interrupts INT0 and INT1 three timer interrupts timers 0 1 and 2 a serial port interrupt a keyboard scan interrupt and three USB interrupts one of which dou bles as a hub interrupt Each interrupt has an interrupt request flag which can be set by firmware as well as by hardware see Table 5 6 on page 5 26 For some interrupts hardware clears the request flag when it grants the interrupt Firmware can clear any request flag to cancel an impend ing interrupt There are three types of USB interrupts as shown in Figure 5 1 The USB function interrupt used to control the flow of non isochronous data the hub any start of frame interrupt SOF used to signal a hub interrupt or to monitor the transfer of isochronous data and the global suspend re sume interrupt used to allow USB power control and to provide a USB reset separation interrupt These interrupts are enabled using the IEN1 register See Table 5 6 on page 5 26 and Figure 5 11 5 2 Interrupt Enable P
312. h 1 1 0 0 Float PSEN Weak High 1 1 0 0 Float Port 0 Pins Float Float Float Float Port 1 Pins Weak High Data Data Float Port 2 Pins Weak High Weak High Weak High Float Port 3 Pins Weak High Data Data Float SOF Weak High Weak High Float Weak High Float Data Data Float Float Float 5 2 Float Data Data Float Float Float Dus 2 Float Data Data Float Float Float UPWEN Weak High Data Data Data Data Float Idle mode is a power reduction mode that reduces power consumption to approximately 40 of normal In this mode program execution halts Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked Figure 2 4 on page 2 9 The CPU status be fore entering idle mode is preserved That is the program counter program status word register and register file retain their data for the duration of idle mode The contents of the SFRs and RAM are also retained The status of the port pins depends upon the location of the program memory Internal program memory the ALE and PSEN pins are pulled high and the ports 0 1 2 and 3 pins are driving the port SFR value Table 14 1 External program memory the ALE and PSEN pins are pulled high the port 0 pins are floating and the pins of parallel ports 1 and 3 are driving the port SFR value Table 14 1 port 2 pins are weakly pulled high 14 3 1 Entering Idle Mode To enter idle mode set the PCON register IDL bit
313. h the USB related SFRs were reset by the USB reset ISR they must also be initialized by a special USB initialization routine called by the main routine Since the USB reset interrupt can occur at any time the only way the main routine will know that a USB reset occurred is to periodically check the USB reset flag USB_RST_FLG This is the firmware flag that was set in Step 2 of the USB Reset ISR on page 5 21 When a set reset flag is detected the main routine branches to a USB initialization routine which performs the following tasks See Figure 5 9 1 Clear the user flag USB_RST_FLG Clearing this flag indicates that USB initialization is not required Clear this flag first in case a second USB reset occurs during this initialization routine rendering this initialization invalid 2 Initialize the USB related SFRs to the values required by your program If your application requires any other SFRs to be initialized upon USB reset e g SCON now is the time to do so Restore any USB related user flags specific to your application 4 Flush all USB FIFOs This is done by setting RXCLR in RXCON and TXCLR in TXCON This must be done for each function endpoint 5 Return to the calling routine At this point the main routine can resume normal processing Eventually the host PC will trans mit a SETUP token This will trigger an interrupt that will perform USB enumeration NOTE USB specifications require that all devices m
314. has two endpoint pairs Hub endpoint 0 supports only control data transfers Hub endpoint 1 is used to transmit hub status change information to the host PC 8x93 1HA USB hub operations fall into two categories hub repeater operations and hub controller operations The hub controller is split among four modules the serial bus interface engine the hub interface unit the hub endpoint 0 transmit and receive FIFOs and the 8 93 CPU See Chapter 7 USB Hub The following subsections discuss the role of each module 2 4 8 Hub Repeater The repeater is the connectivity manager for the 8x931HA It detects the connection or discon nection of devices on the external downstream ports and manages the upstream downstream con nectivity for data packets It keeps track of hub port status manages connectivity and performs power management for external downstream ports The repeater supports both full speed 12 Mbps and low speed 1 5 Mbps data traffic The repeater also controls bus fault detection and recovery Downstream port control is managed primarily by the HIU 2 4 4 Serial Bus Interface Engine SIE The SIE is the USB communication protocol interpreter It places data on and accepts data from the bus On the 8x931HA the hub interface and the function interface share the SIE This is pos sible because the host communicates with only one USB device during any given transaction The internal downstream port is permanently attached t
315. he 8x931HA response to the host s GetPortStatus request See GetPortStatus Request Firmware on page 8 25 Overcurrent indication is not represented on a per port basis because the 8x931HA supports ganged power control and overcurrent indication C 21 8x931AA 8x931HA USER S MANUAL intel HPSTAT Continued Indexed by HPINDEX Address D7H Reset State 100d 0000B Hub Port Status Register This register indicates the current status for a port including power reset suspend low speed device enable connect Dp and Dy status 7 0 DPSTAT DMSTAT LSSTAT PPSTAT PRSTAT PSSTAT PESTAT PCSTAT Bit Bit Number Mnemonic Function 3 PRSTAT Port Reset Status read only Port x x22 3 4 5 Set and cleared by hardware as a result of initiating a port x reset by writing to HPCON 1 reset signaling is currently asserted for port x 0 reset signaling is not asserted Sampled only at the EOF2 point near end of frame Port 1 Same as port x 2 PSSTAT Port Suspend Status read only Port x x 2 3 4 5 Set and cleared by hardware as controlled by firmware via HPCON 1 port x is currently suspended 0 not suspended Sampled only at the EOF2 point near end of frame Port 1 Same as port x 1 PESTAT Port Enable Disable Status read only Port x x 2 3 4 5 Set and cleared by hardware as controlled by firmware via HPCON 1 port x is current
316. he ROM version the lowest 8K bytes of Program Memory are provided on chip Refer to Table 2 1 on page 2 3 for the amount of on chip ROM on each device In the ROMless versions all Program Memory is external The read strobe for external Program Memory is the signal PSEN Program Store Enable Data Memory occupies a separate address space from Program Memory Up to 64K bytes of ex ternal RAM can be addressed in the external Data Memory space The CPU generates read and write signals RD and WR as needed during external Data Memory accesses External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program Data memory 3 1 2 Program Memory Figure 3 1 shows a map of the lower part of the Program Memory After reset the CPU begin execution from location 0000H As shown in Figure 3 1 each interrupt is assigned a fixed location in Program Memory The in terrupt causes the CPU to jump to that location where it commences execution of the service rou tine External Interrupt 0 for example is assigned to location 0003H If External Interrupt 0 is going to be used its service routine must begin at location 0003H If the interrupt is not going to be used its service location is available as general purpose Program Memory 3 1 8x931AA 8x931HA USER S MANUAL intel _ 002BH
317. he interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Functio 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by firmware not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Firmware writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 Serial Port Mode Bit 1 Firmware writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART Fogc 647 or Fog 321 1 1 3 9 bit UART Variable TFosc Oscillator frequency t Select by programming the SMOD bit in the PCON register see section Baud Rates on page 11 10 5 Serial Port Mode Bit 2 Firmware writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 Receiver Enable Bit To enable reception set this bit To disable reception clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 firmware writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1
318. he next EOF2 after completion of a hub reset since the internal port is always connected NOTE Bits are returned as part of the second word 2 bytes in response to a Get Port Status request from the USB host The upper 11 MSbs are reserved and always 0 per USB 1 0 0000 0000 000 4 3 2 1 0 MSB at left Figure 7 11 HPSC Hub Port Status Change Register Continued 7 22 intel USB HUB NOTE While the HPSC register indicates which port features have changed status it does not show the current status of any feature Firmware must examine the HPSTAT register to determine if a given port is currently reset suspended powered on or off connected or disconnected enabled or disabled See Examining a Port s Status Using HPSTAT on page 7 17 for details 7 5 4 Port Indexing Using HPINDEX A port indexing scheme is used for port specific SFRs for reasons similar to those described in Endpoint Selection on page 5 4 for endpoint specific registers Three sets of SFRs have been mapped into the port indexed scheme HPSC HPSTAT and HPCON Ports 1 4 are indexed by the binary value of the two lower bits of HPINDEX Figure 7 12 Port 0 is reserved for the root port but it is not indexed by HPINDEX since there are no port specific SFRs for the root port CAUTION Firmware writers may choose to set the contents of HPINDEX once at the start of each routine instead of writing to HPINDEX prior to each access of a por
319. he post receive routine can be a normal subroutine or ISR initiated by an SOF token The ARM bit RXCON 2 determines whether the FIFO write marker and write pointer are managed automatically by the FIFO hardware ARM 1 or manually by the firmware routine ARM 0 Use of the ARM mode is recommended The ADVWM and REVWP bits which control the write marker and write pointer when ARM 0 are used primarily for test purposes See bit definitions in RXCON Figure 6 15 on page 6 29 8 10 intel USB PROGRAMMING MODELS Hardware SIE FIU FIFOs OUT Token Send data over USB lf ARM 1 Firmware Adjust FIFO write marker and write pointer RXISO 0 Receive done interrupt If ISO 0 RXISO 1 SOF interrupt Send host handshake Adjust RXSEQ bit Generate receive done interrupt or SOF interrupt ISR Post Receive Check status and read data Routine 0 Adjust FIFO write marker and write pointer 4265 02 Figure 8 6 High level View of Receive Operations 8 8 2 Post receive Operations Reception status is updated at the end of data reception based on the handshake received from the host non isochronous data or based on the transmission process itself isochronous data For a non isochronous transfer the function interface generates a receive done interrupt FRXDx The purpose of the post receive service routine is to manage the receiver s state to en
320. he same as hardware the external pin will be driven with an inverted ASOF value for eight T s This bit also serves as the SOF interrupt flag This interrupt is only asserted in hardware if the SOF interrupt is enabled SOFIE set and the interrupt channel is enabled 5 SOFIE SOF Interrupt Enable When this bit is set setting the ASOF bit causes an interrupt request to be generated if the interrupt channel is enabled Hardware reads but does not write this bit 4 FTLOCK Frame Timer Locked read only When set this bit indicates that the frame timer is presently locked to the USB bus frame time When cleared this bit indicates that the frame timer is attempting to synchronize to the frame time Figure 5 5 SOFH Start of frame High Register intel INTERRUPT SYSTEM SOFH Continued Address Reset State D3H 0000 1000B Start of frame High Register Contains isochronous data transfer enable and interrupt bits and the upper three bits of the 11 bit time stamp received from the host 7 0 SOFACK ASOF SOFIE FTLOCK SOFODIS TS10 TS9 TS8 Bit Bit Number Mnemonic Function 3 SOFODIS SOF Pin Output Disable When set the SOF pin will be disabled and will respond like a port pin The SOF pin will be driven to 1 when SOFODIS is set When this bit is clear setting the ASOF bit causes the SOF pin to be toggled with a low pulse for eight To s
321. he system prompts After you select a doc ument the system sends a copy to your fax machine 1 7 8x931AA 8x931HA USER S MANUAL intel Each document is assigned an order number and is listed in a subject catalog The first time you use FaxBack you should order the appropriate subject catalogs to get a complete listing of doc ument order numbers Catalogs are updated twice monthly In addition daily update catalogs list the title status and order number of each document that has been added revised or deleted dur ing the past eight weeks The daily update catalogs are numbered with the subject catalog number followed by a zero For example for the complete microcontroller and flash catalog request doc ument number 2 for the daily update to the microcontroller and flash catalog request document number 20 The following catalogs and information are available at the time of publication 1 Solutions OEM subscription form Microcontroller and flash catalog Development tools catalog Systems catalog Multimedia catalog Multibus and iRMX firmware catalog and BBS file listings Microprocessor PCI and peripheral catalog Quality and reliability and change notification catalog Sen 190 1 ON APS DS iAL Intel Architecture Labs technology catalog 1 4 8 Bulletin Board System BBS Intel s Brand Products and Applications Support bulletin board system BBS lets you download files to your PC The BBS has the latest Ap
322. his bit does not affect a valid SETUP token A valid SETUP token and packet override this bit if it is cleared and place the receive data in the FIFO For hub endpoint 0 EPINDEX 1000 0000 bits 5 and 4 are hard wired to 1 since hub endpoint 0 is always a control endpoint Figure 6 3 EPCON Endpoint Control Register 6 7 8x931AA 8x931HA USER S MANUAL intel EPCON Continued Endpoint indexed Address E1H Reset State Endpoint 0 0011 0101B Function Endpoints 1 2 0001 0000B Endpoint Control Register This SFR configures the operation of the endpoint specified by EPINDEX 7 RXSTL TXSTL 0 CTLEP RXSPM RXIE RXEPEN TXOE TXEPEN Bit Number Bit Mnemonic Function 2 RXEPEN Receive Endpoint Enable Set this bit to enable the receive endpoint When disabled the endpoint does not respond to a valid OUT or SETUP token This bit is hardware read only and has the highest priority among RXIE and RXSTL Note that endpoint 0 is enabled for reception upon reset TXOE Transmit Output Enable This bit is used to enable the data in TXDAT to be transmitted If cleared the endpoint returns a NAK handshake to a valid IN token if the TXSTL bit is not set TXEPEN Transmit Endpoint Enable This bit is used to enable the transmit endpoint When disabled the endpoint does not respond to a valid IN token This bit is hardware read only Note that endpoint 0 is enabled
323. his case Port 2 pins can be used to page the external data memory 9 7 8x931AA 8x931HA USER S MANUAL intel In either case the low byte of the address is time multiplexed with the data byte on Port 0 The ADDRESS DATA signal drives both FETs in the Port 0 output buffers Thus in external bus mode the Port 0 pins are not open drain outputs and do not require external pullups During any access to external memory the CPU writes OFFH to the Port 0 latch the special func tion register thus obliterating the information in the Port 0 SFR NOTE Avoid MOV instructions for external memory accesses These instructions can corrupt input code bytes at port 0 External signal ALE address latch enable facilitates external address latch capture The address byte is valid after the ALE pin drives V For write cycles valid data is written to port 0 just prior to the write WR pin asserting Vo Data remains valid until WR is deactivated For read cycles data returned from external memory must appear at port 0 before the read RD pin is deactivated refer to the 8x931 datasheet for specifications 9 8 intel 10 Timer Counters intel CHAPTER 10 TIMER COUNTERS This chapter describes the timer counter peripherals on the 8x931 When operating as a timer a timer counter runs for a programmed length of time then issues an interrupt request When op erating as a counter a timer counter counts negative transitions on an ex
324. hm on page 16 3 using the verify lock bit mode Table 16 2 Table 16 3 Lock Bit Function Program Lock Bits Protection Type LB1 LB2 LB3 1 U U U No program lock features enabled Code verify will still be encrypted by the encryption array if programmed 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched upon reset 3 P P U Same as 2 verify disabled 4 P P P Same as 3 external execution is disabled P Programmed U Unprogrammed Any other combination of the Lock Bits is undefined 16 3 6 Verifying the Signature Bytes The 83931 contains factory programmed signature bytes These bytes are located in nonvolatile memory outside the program and data memory address space at 30H 31H 60H To read the sig nature bytes perform the procedure described in Verify Algorithm on page 16 3 using the ver ify signature mode Table 16 2 Signature byte values are listed in Table 16 4 Table 16 4 Contents of the Signature Bytes ADDRESS CONTENTS DEVICE TYPE 30H 89H Indicates Intel devices 31H 59H Indicates 51Fx USB core product 60H 1AH Indicates 83931 AA HA device 16 4 intel VERIFYING NONVOLATILE MEMORY 16 4 ENCRYPTION ARRAY The 83931 includes a 64 byte encryption array located in nonvolatile memory outside the pro gram and data memory address spaces
325. ht bits in the accumulator and the CY flag one bit to the left Bit 7 moves into the CY flag position and the original state of the CY flag moves into bit 0 position Flags CY AC OV 3 Example The accumulator contains OC5H 11000101B and the CY flag is clear After executing the instruction RLC A the accumulator contains 8AH 10001010B and the CY flag is set Bytes States 6 Cycles Encoding 0011 0011 Operation RLC 1 lt A a A 0 CY CY lt A 7 RRA Function Rotate accumulator right Description Rotates the 8 bits in the accumulator one bit to the right Bit 0 is moved into the bit 7 position Flags CY AC OV Example The accumulator contains OC5H 11000101B After executing the instruction RRA the accumulator contains OE2H 11100010B and the CY flag is unaffected Bytes States 6 Cycles 1 Encoding 0000 0011 Operation RR A 50 intel RRC A Function Description Flags Example Bytes States Cycles Operation SETB lt bit gt Function Description Flags Example SETB bit Bytes States INSTRUCTION SET REFERENCE Rotate accumulator right through carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the right Bit 0 moves into the CY flag position the original value of the CY flag moves into the bit 7 position CY AC OV 3 The accum
326. hub functionality can be divided into two sub functions the hub repeater and the hub con troller The hub architecture is described in Universal Serial Bus Module on page 2 11 The hub controller function is split among four modules Hub interface unit HIU Serial bus interface engine SIE Transmit and receive FIFOs for hub endpoint 0 and endpoint 1 e 8x931HA CPU 7 1 8x931AA 8x931HA USER S MANUAL intel A functional diagram of the hub is shown in Figure 7 1 on page 7 2 The diagram shows the root port which is the upstream port port 0 the repeater which is responsible for managing connec tivity on a per packet basis the hub controller which provides status and control and permits host access to the hub four external downstream ports which provide a means of expanding the USB by permitting the connection of additional PC peripherals and the internal downstream port which provides an interface to the embedded function Root Port Hub Controller Hub Endpoint 0 Endpoint 1 Function Interface Internal Downstream Port Hub Repeater ia Function Endpoints External Downstream Ports A5255 02 Figure 7 1 8x931HA Hub Functional Diagram Refer to chapter 11 of Universal Serial Bus Specification for a more detailed description of the hub and its functionality For a description of the transceiver see the Driver Characteristics and Receiver Characteristics sections of the Universal Se
327. ile general purpose RAM in this address range is accessed by indirect addressing 2 4 UNIVERSAL SERIAL BUS MODULE The 8x931HA USB module operates in conjunction with the CPU to provide both USB function and USB hub capabilities The block diagram in Figure 2 3 on page 2 7 shows the main compo nents of the 8x931HA USB module and how they interface with the CPU The hub provides the electrical interface between the host PC and downstream devices connected to the USB The repeater and the hub interface which is made up of the Serial Bus Interface Unit SIE the Hub Interface Unit HIU and the hub FIFOs provide the hub capability Figure 2 3 The USB function interface manages communications between the host PC and the embedded function The function interface is made up of the SIE the function interface unit FIU the func tion FIFOs Figure 2 3 The 8x931HA USB module communicates with the host PC by means of an upstream data port USB port 0 The USB module communicates with devices attached to the USB by means of an internal downstream port USB port 1 and the four external downstream ports 8x931HA only See Figure 2 3 and Figure 7 1 on page 7 2 for a hub block diagram For USB port descriptions and pin assignments see Appendix B The external USB ports are differential data ports that are 2 11 8x931AA 8x931HA USER S MANUAL intel fully compliant with the Universal Serial Bus Specification The 8x931HA provides on chip tran
328. ime Add and Subtract Instructions Table A 7 on page A 4 Increment and Decrement Instructions Table A 8 on page A 4 Multiply Divide and Decimal adjust Instructions Table A 9 on page A 5 Logical Instructions Table A 10 on page A 5 Move Instructions Table A 11 on page A 6 Exchange Push and Pop Instructions Table A 12 on page A 7 Bit Instructions Table A 13 on page A 7 Control Instructions Table A 14 on page A 8 Instruction Descriptions on page A 9 contains a detailed description of each instruction A 1 8x931AA 8x931HA USER S MANUAL intel A 1 A 2 NOTATION FOR INSTRUCTION OPERANDS Table A 1 Notation for Register Operands Register Notation Ri 8 bit internal data RAM location OOH FFH addressed indirectly via byte register RO or R1 Rn Byte register RO R7 of the currently selected register bank n Byte register index n 0 7 rrr Binary representation of n Table A 2 Notation for Direct Addresses Direct Description Address P dir8 An 8 bit internal data address This can be internal data RAM 00H 7FH or an SFR address 80H FFH Table A 3 Notation for Immediate Addressing immediate Description Data data An 8 bit constant that is immediately addressed in an instruction data16 A 16 bit constant that is immediately addressed in an instruction Table A 4 Notation for Bit Addressing Bit m Address Description bit A directly addressed bit bit numb
329. imer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 C TO Timer 0 Counter Timer Select C TO 0 selects timer operation timer 0 counts the divided down system clock 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 M00 Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescalar TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits C 54 intel REGISTERS THO TLO Address THO8CH TLO8AH Reset State 0000 0000B THO TLO Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 0 or separately as 8 bit timer counters 7 0 High Low Byte of Timer 0 Register Bit Bit Number Mnemonic Function 7 0 THO 7 0 High byte of the timer 0 timer register TLO 7 0 Low byte of the timer 0 timer register TH1 TL1 Address TH18DH TL1 8BH Reset State 0000 0000B TH1 TL1 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 1 or separately as 8 bit timer counters 7 0 High Low Byte of Timer 1 Register Bit Bit Function Number Mnemonic T
330. in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 Timer 2 Run Control Bit Setting this bit starts the timer 1 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 C 51 8x931AA 8x931HA USER S MANUAL intel T2MOD Address C9H Reset State xx00B Timer 2 Mode Control Register Contains the timer 2 down count enable and clock out enable bits for timer 2
331. in when the host re sends the same data packet Hardware clears this bit after the write pointer is reversed Setting this bit is effective only when the ADVWM ARM and RXCLR bits are all clear REVWP is used when a data packet is bad When the function interface receives the data packet again the write starts at the origin of the previous bad data set ARM mode is recommended ADVWM and REVWP which control the write marker and write pointer when ARM 0 are used for test purposes Figure 6 15 RXCON Receive FIFO Control Register Continued 6 30 intel USB FUNCTION RXFLG Endpoint indexed Address E5H Reset State 00xx 1000B Receive FIFO Flag Register These flags indicate the status of data packets in the receive FIFO specified by EPINDEX 7 0 RXFIF1 RXFIFO RXEMP RXFULL RXURF RXOVF Bit Bit Number Mnemonic Function 7 6 RXFIF 1 0 Receive FIFO Index Flags read only These read only flags indicate which data packets are present in the receive FIFO The RXFIF bits are updated after each write to RXCNTL to reflect the addition of a data packet Likewise the RXFIF bits are cleared in sequence after each setting of the RXFFRC bit The next state table for RXFIF bits is shown below for operation in dual packet mode RXFIF1 0 Operation Flag Next RXFIF1 0 Next Flag 00 Adv WM X 01 Unchanged 01 Adv WM X 01 Unchanged 10 Adv WM X Unchanged Set RXFFRC Unchanged Set
332. ine or enable AEH page 7 9 remote wake up stall feature endpoint 1 over current status and local power status 7 0 HADDR Hub Address HIE HRXEO HTXEO HIFLG z m HRXDO HTXDO HPCON HPCON2 HPCONO HPINDEX HPIDX2 HPIDX1 HPIDXO HPPWR meewss HPpPwra 2 HPPWRI HPSC RSTSC Pssc PESC PCSC HPSTAT DPSTAT DMSTAT PPSTAT LSSTAT PRSTAT PSSTAT PESTAT PCSTAT HSTAT OVRIEN HRWUPE EP1STL EP1EN OVISC OVI Figure 7 2 Bits of the USB Hub SFRs 7 3 8x931AA 8x931HA USER S MANUAL intel 7 1 4 Port Connectivity States In addition to the root port port 0 the hub contains four external downstream ports ports 2 3 4 and 5 and one internal downstream port port 1 Hub downstream ports may be in one of five possible states powered off Power switched ports are a USB option supported by the 8x931 A powered off port supplies no power downstream ignores all upstream directed bus activity on the port and its signal output buffers are placed in the high impedance state disconnected Initial state upon power up or reset the port cannot propagate any upstream or downstream signaling The port can detect a connect event which causes it to transition to the disabled state disabled Port can only propagate downstream directed sign
333. ing Frequencies puser esse icen Frequency commen in Pin 1 MHz 2 Fox Mhz 0 0 0 6 LS 3 PLL Off 0 0 1 6 LS 3 PLL Off 1 0 0 12 LS 6 PLL Off 1 0 1 12 LS 3 PLL Off 1 1 0 12 FS 6 PLL On 1 1 1 12 FS 3 PLL On NOTES 1 Reset and power up routines set the LC bit in PCON to put the 8x931AA in low clock mode core frequency 3 MHz for lower lec prior to device enumeration Following completion of device enumeration firmware should clear the LC bit to exit the low clock mode The user may switch the core frequency back and forth at any time as needed 2 USB rates Low speed 1 5 Mbps Full speed 12 Mbps The USB sample rate is 4X the USB rate Phase 2 P2 Phase 1 P1 XTAL1 Cu 2 Tosc State Time State 1 State 2 State 3 State 4 State 5 State 6 P1 P2 P2 PT P2 P2 P2 P41 P2 Machine Cycle A5325 01 Figure 2 5 8x931 Clocking Definitions 2 10 intel ARCHITECTURAL OVERVIEW 2 2 3 Interrupt Handler The interrupt handler processes interrupt requests from maskable interrupt sources USB module keyboard control interface timer counters and external When the interrupt handler grants an in terrupt request the CPU discontinues the normal sequence of instruction execution and branches to aroutine that services the interrupt source You can enable or disable the interrup
334. int Table 2 5 lists the hub and function endpoint pairs available on the 8x931 along with the associated transmit and receive FIFO data buffers For any given data trans fer operation the EPINDEX register specifies the endpoint pair involved and the HPINDEX reg ister specifies the downstream port Table 2 5 Endpoint Pairs for 8x931 Device EPINDEX Endpoint Pair Transmit Receive USB Data Transfer FIFOs FIFOs Types 8x931AA HA 0000 0000 Function Endpoint 0 8 bytes 8 bytes Control 0000 0001 Function Endpoint 1 16 bytes 16 bytes Control Interrupt BASTA Bulk Isochronous 8x931 AA HA 0000 0010 Function Endpoint 2 8 bytes 8 bytes a Interrupt 8x931HA 1000 0000 Hub Endpoint 0 8 bytes 8 bytes Control 8x931HA 1000 0001 Hub Endpoint 1 1 N A N A Interrupt NOTES 1 Hub endpoint 1 assembles status change information in a buffer register TXDAT and transmits it to the host PC Hub endpoint 1 does not require FIFOs intel ARCHITECTURAL OVERVIEW The CPU runs the firmware associated with the operation of the hub and the function interface It also reads the receive FIFOs loads the transmit FIFOs and decodes and executes USB requests for the hub Control transaction stages are tracked by firmware 2 4 2 Hub Interface Hub operation is implemented by reading and writing the hub SFRs The repeater the SIE the hub interface unit HIU and the hub FIFOs provide the hub capability The hub interface
335. inter SETUP receive reversed RXIE token data interrupt or RXSTL has no CRC or bit effect 2 stuff error dual packet mode not recommende d Received 00 1 0 0 1 1 0 Set Time out RXIE or RXSTL SETUP receive NAK has no effect 2 token FIFO interrupt future RXSETUP will be error occurs transaction set control S endpoints only Received 01 10 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token with interrupt automatically FIFO error forcing new already SETUP to be existing received 2 RXSETUP will be set control endpoints only CPU reads 00 no None None FIFO sets chg RXFFRC CPU reads 01 10 1 None Time out Firmware should FIFO NAK check RXURF bit causes FIFO future before writing error transaction RXFFRC RXFFRC not S set yet CPU reads 00 1 None Time out Firmware should FIFO NAK check RXURF bit causes FIFO future before writing error Set transaction RXFFRC RXFFRC S 11 Received 11 no None NAK FIFO not ready OUT token chg chg chg chg chg So data is ignored CRC or FIFO error not possible NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints 8x931AA 8x931HA USER S MANUAL intel Table D 4 Non isochronous Receive
336. inter by one A 16 bit increment modulo 216 is performed an overflow of the low byte of the data pointer DPL from OFFH to 00H increments the high byte of the data pointer DPH by one An overflow of the high byte DPH does not increment the high word of the extended data pointer DPX DR56 CY AC OV A 27 8x931AA 8x931HA USER S MANUAL intel Example Registers DPH and DPL contain 12H and OFEH respectively After the instruction sequence INC DPTR INC DPTR INC DPTR DPH and DPL contain 13H and 01H respectively Bytes 1 States 12 Cycles 2 Encoding 1010 0011 Operation INC DPTR lt DPTR 1 JB bit rel Function Jump if bit set Description If the specified bit is a one jump to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified Flags CY AC OV Example Input port 1 contains 11001010B and the accumulator contains 56 01010110B After the instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 program execution continues at label LABEL2 Variations JB bit rel Bytes 3 States 12 Cycles 2 Encoding 0010 0000 bit addr rel addr Hex Codein Binary Mode Encoding A 28 Source Mode Encoding intel Operation JBC bit rel Fun
337. ion Figure 7 10 HPSTAT Hub Port Status Register 7 18 intel USB HUB HPSTAT Continued Indexed by HPINDEX Address D7H Reset State 100d 0000B Hub Port Status Register This register indicates the current status for a port including power reset suspend low speed device enable connect Dp and Dy status 7 0 DPSTAT DMSTAT LSSTAT PPSTAT PRSTAT PSSTAT PESTAT PCSTAT Bit Bit Number Mnemonic Function 3 PRSTAT Port Reset Status read only Port x x22 3 4 5 Set and cleared by hardware as a result of initiating a port x reset by writing to HPCON 1 reset signaling is currently asserted for port x 0 reset signaling is not asserted Sampled only at the EOF2 point near end of frame Port 1 Same as port x 2 PSSTAT Port Suspend Status read only Port x x 2 3 4 5 Set and cleared by hardware as controlled by firmware via HPCON 1 port x is currently suspended 0 not suspended Sampled only at the EOF2 point near end of frame Port 1 Same as port x 1 PESTAT Port Enable Disable Status read only Port x x 2 3 4 5 Set and cleared by hardware as controlled by firmware via HPCON 1 port x is currently enabled 0 port is disabled Sampled only at the EOF2 point near end of frame Port 1 Same as port x 0 PCSTAT Port Connect Status read only Port x connect status from previous frame time Port x x 2 3 4
338. ion in Table 4 7 can accommodate a table of up to 256 entries numbered 0 through 255 The number of the desired entry is loaded into the Accumulator and the Data Pointer is set up to point to beginning of the table Then MOVC A A DPTR copies the desired table entry into the Accumulator The other MOVC instruction works the same way except the Program Counter PC is used as the table base and the table is accessed through a subroutine First the number of the desired entry is loaded into the Accumulator and the subroutine is called MOV A ENTRY_NUMBER 8x931AA 8x931HA USER S MANUAL intel CALL TABLE The subroutine TABLE would look like this TABLE MOVC A A PC RET The table itself immediately follows the RET return instruction in Program Memory This type of table can have up to 255 entries numbered 1 through 255 Number 0 can not be used because at the time the MOVC instruction is executed the PC contains the address of the RET instruction An entry numbered 0 would be the RET opcode itself 4 1 6 Boolean Instructions MCS 51 devices contain a complete Boolean single bit processor The internal RAM contains 128 addressable bits and the SFR space can support up to 128 other addressable bits All of the port lines are bit addressable and each one can be treated as a separate single bit port The in structions that access these bits are not just conditional branches but a complete menu of move set clear co
339. ion of the port index 2 Clear PCSC bit of HPSC SFR Figure 7 11 on page 7 21 Request to clear hardware initiated port enable disable status C PORT change ENABLE 1 Load xxxB into HPINDEX2 0 where xxx is the binary representation of the port index 2 Clear PESC bit of HPSC SFR Figure 7 11 on page 7 21 Request to clear port suspend status change C_PORT_ 1 Load xxxB into HPINDEX2 0 where xxx is the binary SUSPEND representation of the port index 2 Clear PSSC bit of HPSC SFR Figure 7 11 on page 7 21 Unsupported request to clear port over current status change The 8x931HA implements over current detection on a hub wide C_PORT_ basis not on a per port basis If received OVERCURRENT 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage C_PORT_RESET Request to clear port reset status change 1 Load xxxB into HPINDEX2 0 where xxx is the binary representation of the port index 2 Clear RSTSC bit of HPSC SFR Figure 7 11 on page 7 21 8 22 intel USB PROGRAMMING MODELS 8 6 2 Port Status Change Communication The flowchart in Figure 8 11 shows how the hub communicates a change in port status to the host This process involves 8x931HA hardware 8x931HA firmware and PC host firmware The flow chart illustrates the complete process at a high level The process contains the following steps 1 Any change in a port s reset suspend enable
340. ion oo a e aa aa Eaa a a aaae o ia aaa iaa nieni sie 13 6 13 4 3 Reset Operation nininini TREO ER REGI e 13 6 19 44 Power on Reset usce TE 13 7 14 SPECIAL OPERATING MODES 14 31 OVERVIEW wees 14 1 14 2 POWER CONTROL REGISTERS 14 1 14 211 Power Off Flag emet o Roe OE ete 14 1 143 JDEE MODE iere e et orn e e Ee D a ened ea LHHEERES 14 6 14 8 1 Entering lde Mode o ete e eit ee e eH 14 6 14 3 2 Exiting Idle Mode 14 7 144 USB POWER CONTROL ener gimp UU en 14 7 14 4 1 Global Suspend Mode sse nennen nennen entretenir 14 7 14 4 1 1 Powerdown Suspend Mode cecceesceeeeeeeceeseeeeeeeeseeeseeeeeaeeeeeseeeeeeeeneeseaeenaes 14 8 14 4 1 2 Entering Powerdown Suspend Mode see 14 8 14 4 1 3 Exiting Powerdown Suspend Mode eese 14 8 14 4 2 Global Resume Mode 14 9 14 4 8 USB Remote Wake up essssssssesseseeeeseeneee nennen nenne nnne nennen nnne 14 10 14 5 Stirp rosdi nen erret ctetu ete pha totu as eee ia uet 14 13 14 5 1 Entering
341. ir8 1 IF dir8 gt or dir8 lt 0 THEN lt PC rel 2 12 2 Encoding 1101 irrr rel addr DJNZ PC PC 2 Rn lt Rn 1 IF Rn gt 0 or Rn lt 0 THEN PC rel Increment Increments the specified byte variable by 1 An original value of FFH overflows to OOH Three addressing modes are allowed for 8 bit operands register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV Register 0 contains 7EH 011111110B and on chip RAM locations 7EH and 7FH contain OFFH and 40H respectively After executing the instruction sequence INC RO INC RO INC RO register 0 contains 7FH and on chip RAM locations 7EH and 7FH contain 00H and 41H respectively Encoding 0000 0100 intel Operation INC dir8 Bytes States Cycles Operation INC GRi Bytes States Cycles Operation INC Rn Bytes States Cycles Operation INC DPTR Function Description Flags INSTRUCTION SET REFERENCE INC A lt A 1 6 1 Encoding 0000 0101 direct addr INC dir8 lt dir8 1 Encoding 0000 011i INC Ri lt Ri 1 Encoding 0000 1 Rn lt Rn 1 Increment data pointer Increments the 16 bit data po
342. irmware When this flag is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in your error management routine using the TXCLR bit in TXCON When the transmit FIFO underruns the read pointer will not advance it remains locked in the empty position If the byte count in TXCNTL does not agree with the data hardware sets TXURF This indicates that the transmitted data was corrupted by a bit stuffing or CRC error In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since underrun can only be caused by USB TXURF is updated at the next SOF regardless of where the underrun occurs in the frame TXOVF Transmit FIFO Overrun Flag This bit is set when an additional byte is written to a full FIFO or full TXCNTL with TXFIF1 0 11 This is a sticky bit that must be cleared through firmware When this bit is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in your error management routine using the TXCLR bit in TXCON When the receive FIFO overruns the write pointer will not advance it remains locked in the full position Check this bit after loading the FIFO prior to writing the byte count register In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change immediately while USB event
343. is immediately addressed in an instruction A 16 bit constant that is immediately addressed in an instruction Acknowledgment Handshake packet indicating a positive acknowledgment Instructions in the MCS 51 architecture use the accumulator as both source and destination for calculations and moves An 11 bit destination address The destination can be anywhere in the same 2 Kbyte block of memory as the first byte of the next instruction A 16 bit destination address The destination can be anywhere within the same 64 Kbyte region as the first byte of the next instruction Arithmetic logic unit The part of the CPU that processes arithmetic and logical operations The term assert refers to the act of making a signal active enabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high Method of storing data that places the most significant byte at lower storage addresses A binary digit An addressable bit in the 8x931 architecture Insertion of a 0 bit into a data stream to cause an electrical transition on the data wires allowing a PLL to remain locked Non periodic large bursty communication typically used for a transfer that can use any available bandwidth and can also be delayed until bandwidth is available Detecting and identifying US
344. is preset by firmware When the interrupt re quest is serviced hardware clears TFO The reload leaves THO unchanged See Auto reload Set up Example on page 10 9 Interrupt Overflow Request 5199 01 Figure 10 3 Timer 0 1 in Mode 2 Auto reload 10 3 4 Mode 3 Two 8 bit Timers Mode 3 configures timer 0 such that registers TLO and THO operate as separate 8 bit timers Fig ure 10 4 This mode is provided for applications requiring an additional 8 bit timer or counter TLO uses the timer 0 control bits C TO and GATEO in TMOD and TRO and TFO in TCON in the normal manner THO is locked into a timer function counting 6 and takes over use of the timer 1 interrupt TF1 and run control TR1 bits Thus operation of timer 1 is restricted when timer 0 is in mode 3 See the last paragraph of Timer 1 on page 10 6 and Mode 3 Halt on page 10 9 10 5 8x931AA 8x931HA USER S MANUAL intel Interrupt Overflow Request Interrupt Overflow Request A5200 01 Figure 10 4 Timer 0 in Mode 3 Two 8 bit Timers 10 4 TIMER 1 Timer 1 functions as either a timer or event counter in three modes of operation Figures 10 2 and 10 3 show the logical configuration for modes 0 1 and 2 Timer 1 s mode 3 is a hold count mode Timer 1 is controlled by the four high order bits of the TMOD register Figure 10 5 and bits 7 6 3 and 2 of the TCON register Figure 10 6 The TMOD register
345. ith RXACK 0 RXACK Receive Acknowledged read only This bit is set when data is received completely into a receive FIFO and an ACK handshake is sent This read only bit is updated by hardware at the end of a valid SETUP or OUT token transaction non isochronous or at the next SOF on each valid OUT token transaction isochronous The corresponding FRXDx bit of FIFLG or FIFLG1 8x930Ax with 6EPP is Set when active This bit is updated with the RXERR bit at the end of data reception and is mutually exclusive with RXERR Under normal operation this bit should not be modified by the user For additional information on the operation of these bits see Appendix D Data Flow Model The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface C 45 8x931AA 8x931HA USER S MANUAL intel SADDR Address AQH Reset State 0000 0000B Slave Individual Address Register SADDR contains the device s individual address for multiprocessor communication 7 0 Slave Individual Address Bit Bit Number Mnemonic Function 7 0 SADDR 7 0 SADEN Address B9H Reset State 0000 0000B Mask Byte Register This register masks bits in the SADDR register to form the device s given address for multiprocessor communication 7 0 Mask for SADDR Bit Bit Function Number Mnemonic sa 7 0 SADEN 7 0 SBUF Address 9
346. ither for general purpose I O or for its al ternate input or output function Table 9 1 To use a pin for general purpose output set or clear the corresponding bit in the Px register x 1 3 To usea pin for general purpose input set the bit in the Px register This turns off the output driver FET To configure a pin for its alternate function set the bit in the Px register When the latch is set the alternate output function signal controls the output level Figure 9 1 The operation of ports 1 and 3 is discussed further in Quasi bidirectional Port Operation on page 9 6 9 4 PORT 0 AND PORT 2 Ports 0 and 2 are used for general purpose I O or as the external address data bus Port 0 shown in Figure 9 2 differs from the other ports in not having internal pullups Figure 9 3 on page 9 4 shows the structure of port 2 An external source can pull a port 2 pin low To use a pin for general purpose output set or clear the corresponding bit in the Px register x 0 2 To use a pin for general purpose input set the bit in the Px register to turn off the output driver FET 9 2 intel INPUT OUTPUT PORTS Alternate Read Output Latch Function Internal Bus Write to Latch Read Alternate Pin Input Function A2239 01 Figure 9 1 Port 1 and Port 3 Structure Address Read Data Control Vcc Latch Internal Bus Write to Latch Read Pin A2238 01 Figure 9 2 Port
347. its and the upper three bits of the 11 bit time stamp received from the host REGISTERS Address D3H Reset State 0000 1000B 7 0 SOFACK ASOF SOFIE FTLOCK SOFODIS TS10 TS9 TS8 Bit Bit Number Mnemonic Function 7 SOFACK SOF Token Received without Error read only When set this bit indicates that the 11 bit time stamp stored in SOFL and SOFH is valid This bit is updated every time an SOF token is received from the USB bus and it is cleared when an artificial SOF is generated by the frame timer This bit is set and cleared by hardware 6 ASOF Any Start of Frame This bit is set by hardware to indicate that a new frame has started The interrupt can result either from reception of an actual SOF packet or from an artificially generated SOF from the frame timer This interrupt is asserted in hardware even if the frame timer is not locked to the USB bus frame timing When set this bit is an indication that either an actual SOF packet was received or an artificial SOF was generated by the frame timer This bit must be cleared by firmware or inverted and driven to the SOF pin The effect of setting this bit by firmware is the same as hardware the external pin will be driven with an inverted ASOF value for eight s This bit also serves as the SOF interrupt flag This interrupt is only asserted in hardware if the SOF interrupt is enabled SOFIE set and the interrupt channel is enabled
348. ive buffer Serial Port Control Selects the serial port operating mode SCON enables 98H and disables the receiver framing bit error detection multiprocessor communication automatic address recognition and the serial port interrupt bits SADDR Serial Address Defines the individual address for a slave device 9 SADEN Serial Address Enable Specifies the mask byte that is used to define the B9H given address for a slave device 11 2 MODES OF OPERATION The serial I O port can operate in one synchronous and three asynchronous modes 11 2 1 Synchronous Mode Mode 0 Mode 0 is a half duplex synchronous mode which is commonly used to expand the I O capabil ities of a device with shift registers The transmit data TXD pin outputs a set of eight clock puls es while the receive data RXD pin transmits or receives a byte of data The eight data bits are transmitted and received least significant bit LSb first Shifts occur in the last phase S6P2 of every peripheral cycle which corresponds to a baud rate of Fosc 12 Figure 11 3 on page 11 6 shows the timing for transmission and reception in mode 0 11 2 1 1 Transmission Mode 0 Follow these steps to begin a transmission 1 Write to the SCON register clearing bits SMO SM1 and REN 2 Wirite the byte to be transmitted to the SBUF register This write starts the transmission Hardware executes the write to SBUF in the last phase S6P2 of a peripheral cycle
349. j 27 P1 0 T2 KSO0 28 P1 1 T2EX KSO1 amp 29 P1 2 KSO2 30 P1 3 KSO3 31 P1 4 KSO4 32 P1 5 KSO5 33 P1 6 RXD KSO6 Ej 34 P1 7 TXD KSO7 35 LED3 rj 36 LED2 rj 37 XTAL1 38 XTAL2 rj 39 AVcc E 40 RST 41 PLLSEL amp 42 LED1 9 43 Note Reserved pins must be left unconnected A5340 02 Figure B 1 8x931HA 68 pin PLCC Package B 1 8x931AA 8x931HA USER S MANUAL intel Figure B 2 illustrates a diagram of the 8x931HA SDIP package Table B 2 and Table B 5 contain indexes of the pin arrangement Table B 7 contains the signal descriptions for all pins Voc 1 Vgsp P3 0 OVRI 2 ADO P0 0 KSIO P3 1 SOF E13 AD1 P0 1 KSH P3 2 INTO 4 4 AD2 P0 2 KSI2 P3 3 INT1 4 5 AD3 P0 3 KSI3 P3 4 T0 KSO16 4 6 AD4 P0 4 5 4 P3 5 T1 KS017 04 7 8x931Hx ADS P0 5 KSI5 P3 6 WR KSO18 4 8 AD6 P0 6 KSI6 P3 7 RD KSO19 AD7 P0 7 KSI7 P1 0 T2 KSO0 A8 P2 0 KSO8 P1 1 T2EX KSO1 A9 P2 1 KSO9 P1 2 KSO2 A10 P2 2 KSO10 P1 3 KSO3 A11 P2 3 KSO11 P1 4 KSO4 A12 P2 4 KSO12 P1 5 KSO5 View of A13 P2 5 KSO13 P1 6 RXD KSO6 component A14 P2 6 KSO14 P1 7 TXD KSO7 as mounted 15 P2 7 KSO15 o PC board Vss LED2 on VocP XTAL1 EA XTAL2 ALE AVoc PSEN RST UPWEN PLLSEL Vssp LED1 Dp4 LEDO Dye Dps Dp Dus Dus Vss ECAP Vssp A5249 02 Figure B 2 8x931HA 64 pin SDIP Pac
350. kage B 2 intel Figure B 3 illustrates a diagram of the 8x931HA QFP package Table B 3 and the pin arrangement Table B 7 contains the signal descriptions for all pins PIN DESCRIPTIONS able B 6 contain indexes of 64 AD7 PO 7 KSI7 63 A8 P2 0 KSO8 62 A9 P2 1 KSO9 61 A10 P2 2 KSO10 60 A11 P2 3 KSO11 59 E A12 P2 4 KSO12 58 A13 P2 5 KSO13 57 A A14 P2 6 KSO14 56 A15 P2 7 5015 AD6 P0 6 KSI6 E 1 AD5 P0 5 KSI5 E12 04 P0 4 KS14 4 AD3 P0 3 KSI3 6 4 AD2 PO 2 KSI2 5 AD P0 1 KSI1 66 ADO PO 0 KSIO E17 Vssp E18 Vcc H9 P3 0 OVRI E 10 P3 1 SOF E 11 P3 2 INTO 12 P3 3 INT1 E 13 P3 4 TO KSO16 E 14 P3 5 T1 KSO17 E 15 P3 6 WRit KSO18 E 16 View of component as mounted on PC board RST amp 31 PLLSEL 32 e L Q o gt lt P3 7 RD KSO19 17 P1 0 T2 KSO0 18 P1 1 T2EX KSO1 amp 19 1 2 502 20 P1 3 KSO3 r3 21 P1 4 KSO4 22 P1 5 KSO5 23 P1 6 RXD KSO6 24 P1 7 TXD KSO7 25 LED3 9 26 LED2 rj 27 XTAL1 28 XTAL2 Q 29 Figure B 3 8x931HA 64 pin QFP Package Dp4 Dm4 Dp5 Dus Dpo Vssp Vss Dm3 Dp2 Dm2 LEDO LED1 A5342 02 B 3 8x931AA 8x931HA USER S MANUAL intel Figure B 4 illustrates a diagram of the 8x931AA QFP package Table B 3 and Table B 6 contain indexes of th
351. ke up bit RWU in PCON1 Figure 14 2 to drive resume signaling on the USB lines to the host or upstream hub and to the enabled downstream ports After executing the ex ternal ISR the program continues execution from where it was put into powerdown mode and the 8x931 resumes normal operation 14 10 SPECIAL OPERATING MODES Remote Wake up using an external interrupt Host sends Suspend Hold external interrupt pin down USB INTO INT1 or INT2 low until oscillator stabilizes Normally 10ms or less Suspend Command Suspend is detected by USB device setting GSUS and causing interrupt External ISR entered External ISR serviced Suspend ISR should shut down all external peripherals RETI from external ISR Suspend ISR sets PD bit GSUS must not be cleared Program returns to command immediately following the setb PD command in the original Setting PD bits causes Suspend ISR USB device to enter powerdown mode Entire function must draw less than 500 pA from USB Suspend Mode Entered t If GSUS is cleared the USB device will not be able to detect resume signaling from the host Resume Command from Host Host sends Resume down USB USB device detects resume hardware sets GRSM clears GSUS and starts oscillator When oscillator stabilizes program begins execution at location immediately following the setb PD command A5307 01 Figure 14 3 Sus
352. l clock frequency The timer repeatedly counts to overflow from a preloaded value At overflow the contents of the RCAP2H and RCAP2L registers are loaded into TH2 TL2 In this mode timer 2 overflows do not generate interrupts The formula gives the clock out frequen cy as a function of Table 2 4 on page 2 10 and the value in the RCAP2H and RCAP2L registers Fc LK Clock out Frequency 77755535 RCAP2H For a 12MHz system clock Fo 6 MHz timer 2 has a programmable frequency range of 45 8 Hz to 3 MHz Timer 2 is programmed for the clock out mode as follows 1 Set the T2OE bit in T2MOD This gates the timer register overflow to the 2 counter 2 Clear the C T2 bit in T2CON to select Fox as the timer input signal This also gates the output of the 2 counter to pin T2 3 Determine the 16 bit reload value from the formula and enter in the RCAP2H RCAP2L registers 4 Enter a 16 bit initial value in timer register TH2 TL2 This can be the same as the reload value or different depending on the application 5 start the timer set the TR2 run control bit in T2CON Operation is similar to timer 2 operation as a baud rate generator It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously For this configuration the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers 10 14 intel T
353. le 16 2 A4520 01 Figure 16 1 Setup for Verifying Nonvolatile Memory 16 3 3 Verify Algorithm Use this procedure to verify program code signature bytes and lock bits stored in nonvolatile memory on the 83931 To preserve the secrecy of the encryption key byte sequence the encryp tion array cannot be verified Verification can be performed on a block of bytes The procedure for verifying the 83931 is as follows 1 Setup the microcontroller for operation in the appropriate mode according to Table 16 2 2 Input the 16 bit address on ports and P2 0 P2 5 and P3 4 5 3 Wait for the data on port PO to become valid Ta yay 48 clock cycles then compare the data with the expected value 4 Repeat steps 1 through 3 until all memory locations are verified 16 3 8x931AA 8x931HA USER S MANUAL intel 16 3 4 Verifying On chip Program Memory To verify that on chip program memory is correctly programmed perform the procedure de scribed in Verify Algorithm on page 16 3 using the verify on chip program memory mode Ta ble 16 2 For information about using on chip program memory see Considerations for On chip Program Code Memory on page 16 5 16 3 5 Verifying the Lock Bits The 8x931 provides lock bits for protecting program code stored in the on chip program memory from unauthorized access To verify that the lock bits are correctly programmed perform the pro cedure described in Verify Algorit
354. lect 256 byte pages in external memory 15 3 1 Port 0 and Port 2 Pin Status The port pins have the same signals as those on the 8XC51FX For an external memory instruc tion using a 16 bit address the port pins carry address and data bits during the bus cycle How ever if the instruction uses an 8 bit address e g MOVX Ri the contents of P2 are driven onto the pins These pin signals can be used to select 256 bit pages in external memory During a bus cycle the CPU always writes FFH to PO and the former contents of PO are lost A bus cycle does not change the contents of P2 When the bus is idle the port 0 pins are held at high impedance and the contents of P2 are driven onto the port 2 pins 15 5 8x931AA 8x931HA USER S MANUAL intel 15 4 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8x931 systems Many designs are pos sible The examples apply for both 8x931AA and 8x931HA devices 15 4 1 Example 1 11 bit Bus External RAM Figure 15 5 shows a hardware configuration for accessing up to 2K bytes of external RAM The CPU in this case is executing from internal ROM Port 0 serves as a multiplexed address data bus to the RAM 3 lines of port 2 are being used to page the RAM If the Program Memory is internal the other bits of P2 are available as input output The CPU generates RD and WR signals as needed during external RAM accesses E P1 Microcontroller with on chip co
355. led the EP1EN bit in the HSTAT SFR Figure 7 6 on page 7 9 must be set See Section 11 9 of the Universal Serial Bus Specification 7 8 HUB DEVICE SIGNALS Table 7 8 lists device signals associated with the hub Pin assignments are shown in Appendix B Table 7 8 Signal Descriptions Signal Name Dpo Dpo Due Dp3 Dug 0 4 Dus 7 30 Type VO VO Description USB Upstream Port 0 and Dyo are the data plus and data minus lines of USB port 0 These lines do not have internal pullup resistors For low speed devices provide an external 1 5 KQ pullup resistor at Dyo For full speed devices provide an external 1 5 KQ pullup resistor at Dp NOTE For the 8x931HA provide an external 1 5 KQ pullup resistor at so the device indicates to the host that it is a full speed device USB Downstream Ports 2 3 4 5 These pins are the data plus and data minus lines for the four USB external downstream ports You must supply an external 15 KQ pulldown resistor for these lines If the USB downstream ports are not used the two data lines are still required to be pulled low externally similar to a disconnect so that the inputs are not left floating Alternate Function intel USB Programming Models intel CHAPTER 8 USB PROGRAMMING MODELS This chapter describes the programming models of the USB function interface and the hub inter face It provides flow charts of fir
356. lementations Avoid any firmware dependence on these bits In the 8x931 the value read from a reserved bit is indeterminate do not write a 1 to a reserved bit Once a device is in the suspend state its operation can be resumed by receiving non idle signaling on the bus See also suspend Real time A USB hub directly attached to the host controller This hub is attached to the host tier 0 The upstream port on a hub Single ended zero This is a reference to the USB reset signal which is defined as both Dpo and Dy below their threshold voltage Serial Bus Interface Engine Handles the communications protocol of the USB The term set refers to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value A special function register that resides in its associated on chip peripheral or in the 8x931 core Current flowing into a device to ground Always a positive value Start of Frame The SOF is the first transaction in each frame SOF allows endpoints to identify the start of frame and synchronize internal endpoint clocks to the host Glossary 5 8x931AA 8x931HA USER S MANUAL intel source current Current flowing out of a device from Vec Always a negative value SP Stack pointer state time or state The basic time unit of the device With XTAL1 12 MHz and two Tosc periods per state one state 166 7 ns suspend A low current mode us
357. llator periods while the oscillator is running Reset can be accomplished automatically at the time pow er is applied by capacitively coupling RST to Vcc see Figure 13 1 on page 13 1 and Power on Reset on page 13 7 The RST pin has a Schmitt trigger input and a pulldown resistor 13 4 2 USB initiated Resets The 8x931 can be reset by the host or upstream hub if a reset signal is detected by the SIE This reset signal is defined as an SEO held longer than 2 5 us A USB initiated reset will reset all of the 8x931 hardware even if the device is suspended in which case it would first wake up then reset See USB Power Control on page 14 7 for additional information about USB related sus pend and resume A peripheral that is reset must be re enumerated This procedure is given in Enumeration on page 8 2 NOTE You must ensure that the time from connection of this USB device to the bus until the entire reset process is complete including firmware initialization of 13 5 8x931AA 8x931HA USER S MANUAL intel the 8x931 is less than 10 ms After 10 ms the host may attempt to communicate with the 8x931 to set its device address If the 8x931 firmware cannot respond to the host at this time the host may disable the device after three attempts to communicate 13 4 2 1 USB Reset Separation The 8x931 features an optional USB reset that functions independently from the chip reset When the PCON1 SFR s URDIS bit is set th
358. locked until both the STOVW and EDOVW bits are cleared CAUTION For SETUP packets only firmware must clear EDOVW prior to reading data from the FIFO If this is not done data read from the FIFO will be invalid After processing a SETUP packet firmware should always check the STOVW and EDOVW flags before setting the RXFFRC bit When a SETUP packet either has been or is being received setting RXFFRC has no effect if either STOVW or EDOVW is set It is up to the user to clear EDOVW which disables the RXFFRC blocking mechanism Also note that the RXSETUP 1 condition causes IN and OUT tokens to be NAKed automatically until RXSETUP is cleared This 6 34 intel USB FUNCTION is true even if the transmit and or receive endpoint is stalled TXSTL 1 RXSTL 1 and is done to allow the clearing of a stall condition on a control endpoint NOTE To simplify firmware development it is recommended that you utilize control endpoints in single packet mode only 6 7 ISO DATA MANAGEMENT ISO data management must always be performed in dual packet mode Interrupts are not gener ated when an ISO transmit or receive cycle is completed ISO protocols should always be syn chronized to the SOF interrupt When transmitting data written into the transmit FIFO at frame n is pre buffered to be transmit ted in frame n 1 This guarantees that data is always available to the host when requested anytime in a frame When receiving data written into the re
359. lows an external waveform at pin INTx to turn the timer on and off This setup can be used to measure the width of a positive going pulse present at pin INTx Pulse width measurements using timer 0 in mode can be made as follows 1 Program the four low order bits of the TMOD register Figure 10 5 to specify mode 1 for timer 0 C TO 0 to select 6 as the timer input and GATEO 1 to select INTO as timer run control 2 Enter an initial value of all zeros in the 16 bit timer register THO TLO or read and store the current contents of the register 3 Set the TRO bit in the TCON register Figure 10 6 to enable INTO 4 Apply the pulse to be measured to pin INTO The timer runs when the pulse waveform is high 5 Clear the TRO bit to disable INTO 6 Read timer register THO TLO to obtain the new value 7 Calculate pulse width 6T x new value initial value 8 Example Fg 12 MHz Fc 6 MHz Terg 0 16667 us If the new value 10 000 counts and the initial value 0 the pulse width 6 0 16667 x 10 000 0 1 us x 10 000 10 ms 10 6 TIMER 2 Timer 2 is a 16 bit timer counter The count is maintained by two 8 bit timer registers TH2 and TL2 connected in cascade The timer counter 2 mode control register T2MOD as shown in Fig ure 10 11 on page 10 16 and the timer counter 2 control register T2CON as shown in Figure 10 12 on page 10 17 control the operation of timer 2 Timer 2 provides the followi
360. ls drops to 0 the keyboard scan interrupt is triggered This can happen on either a level 0 or the neg ative edge of a KSI7 0 signal depending on the value of IT2 in KBCON Figure 12 1 on page 12 1 If the keyboard scan enable bit is set KSEN in KBCON the keyboard scan interrupt flag called the Interrupt 2 Flag and represented by the IE2 bit in KBCON is set when one of the KSI7 0 sig 5 7 8x931AA 8x931HA USER S MANUAL intel nals becomes zero If external interrupt 2 is enabled by setting EX2 in IEN1 a hardware inter rupt is triggered and program control vectors to 003BH See Keyboard Interrupt Logic on page 12 3 for additional information 5 2 4 Serial Port Interrupt Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register Nei ther flag is cleared by a hardware vector to the service routine The service routine resolves RI or TI interrupt generation and clears the serial port request flag The serial port interrupt is enabled by bit ES in the IENO register see Figure 5 10 5 2 5 USB Function Interrupt The USB function generates two types of interrupts to control the transfer of non isochronous da ta the receive done interrupt and the transmit done interrupt Individual USB function interrupts in the 8x931 are enabled by setting the corresponding bits in the FIE register Figure 5 3 NOTE To use any of the USB function interrupts the EF bit in the IEN1 register must
361. ls will not reset when a USB reset signal is detected After an 8x931 with URDIS set detects a USB reset signal it resets all the USB blocks including the USB SFRs sets the URST bit in PCONI and generates a USB reset interrupt USB reset signals can originate only from the host PC or upstream hub NOTE The use of a separate USB reset is recommended only for applications where the device is required to be operated continually even when the PC is powered off as is the case with Computer Telephony Integration CTI All 5 17 8x931AA 8x931HA USER S MANUAL intel other applications are advised against using the separate USB reset Leaving the URDIS bit clear will ensure a robust chip level reset The USB reset must be implemented partially in firmware including an initialization routine as part of chip start up To ensure compliance with USB specified timing constraints and minimize the potential for data corruption you must implement flag checking as part of your main routine subroutines and ISRs These requirements increase the complexity of your firmware code If the 8x93 1 is in powerdown or suspend mode when the separate USB reset interrupt is generat ed the device will wake up from powerdown or suspend mode upon receiving the USB reset sig nal The ISR of a bus powered device must set the LC bit of PCON Figure 14 1 on page 14 3 in order to operate at 3 MHz This ensures that the device meets the 100 mA current limit duri
362. ly enabled 0 port is disabled Sampled only at the EOF2 point near end of frame Port 1 Same as port x 0 PCSTAT Port Connect Status read only Port x connect status from previous frame time Port x x 2 3 4 5 Set and cleared by hardware after sampling the connect state at EOF2 near the end of the present frame 1 device is present on port x 0 device is not present This bit will be set if either a physical connection is detected or during a hub reset when a downstream device is already connected This bit will be cleared if a disconnect is detected Port 1 Hard wired to 1 since the internal function is permanently connected NOTES Firmware returns the bits of this register in the first word of the 8x931HA response to the host s GetPortStatus request See GetPortStatus Request Firmware on page 8 25 Overcurrent indication is not represented on a per port basis because the 8x931HA supports ganged power control and overcurrent indication C 22 HSTAT Hub Status and Configuration Register This SFR contains bits for remote wake up request status and status change indicators for over current and hub endpoint 1 stall and enable 7 REGISTERS Address AEH Reset State 0000 0000B OVRIEN HRWUPE EP1STL EP1EN OVISC OVI Bit Number Bit Mnemonic Function 7 OVRIEN Overcurrent Detect Enable Bit This bit is used to gate off the ov
363. m the FIFO and when a good transmission is acknowledged the read marker is advanced to the read pointer The data set index bits are updated after the read marker is advanced Note that in ISO mode this happens at the next start of frame SOF Table 6 4 Writing to the Byte Count Register ee Data Sets Written Set for Next Write Write bytes c ds1 450 to TXCNTL to TXDAT 0 0 No No Empty 050 gt Write byte gt 0 1 0 1 No Yes 1 set ds1 NIIS 1 1 1 0 Yes No 1set dsO 1 1 1 1 Yes Yes 2 sets Write ignored 1 1 6 17 8x931AA 8x931HA USER S MANUAL Table 6 5 summarizes how the actions following a transmission depend on the TXISO ATM TXACK and TXERR bits intel Table 6 5 Truth Table for Transmit FIFO Management TXISO ATM TXERR TXACK TXCON 3 TXCON 2 TXSTAT 1 TXSTAT 0 Action at End Transtar Cycle X X 0 0 No operation X 0 0 1 Read marker read pointer and TXFIF bits remain unchanged Managed by firmware X 0 1 0 Read marker read pointer and TXFIF bits remain unchanged Managed by firmware 0 1 0 1 Read marker advanced automatically The TXFIF bit for the corresponding data set is cleared 0 1 1 0 Read pointer reversed automatically The TXFIF bit for the corresponding data set remains unchanged 1 1 X X Read marker advanced automatically The TXFIF bit for the corresponding data set is cleared at the
364. mber Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes register direct register indirect or immediate Flags CY AC OV 3 3 3 Example The accumulator contains OC9H 11001001B register 2 contains 54H 01010100B and the CY flag is set After executing the instruction SUBB A R2 the accumulator contains 74H 01110100B the CY and AC flags are clear and the OV flag is set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the CY borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR CY instruction Variations SUBB A data Bytes 2 States 6 Cycles Encoding 1001 0100 immed data Operation SUBB lt A CY data 8 Bytes 2 A 53 8x931AA 8x931HA USER S MANUAL intel States 6 Cycles Encoding 1001 0101 direct addr Operation SUBB lt A CY dir8 SUBB A Ri Bytes States 6 Cycles 1 Encoding 1001 011i Operation SUBB lt A CY Ri SUBB A Rn Bytes States 6 Cycles Encoding 1001 irrr Operation SUBB lt A CY Rn SWAPA Function Swap nibbles within the accumulator De
365. mber 0 through 4 to an even number on the range 0 through 8 because each entry in the jump table is 2 bytes long JUMP_TABLE AJMP 0 AJMP I AJMP CASE 2 AJMP CASE 3 AJMP CASE 4 Table 4 9 shows a single CALL addr instruction but there are two of them LCALL and ACALL which differ in the format in which the subroutine address is given to the CPU CALL is a generic mnemonic which can be used if the programmer does not care which way the address is encoded The LCALL instruction uses the 16 bit address format and the subroutine can be anywhere in the 64K Program Memory space The ACALL instruction uses the 11 bit format and the subrou tine can be anywhere in the 64K Program Memory space The ACALL instruction uses the 11 bit format and the subroutine must be in the same 2K block as the instruction following the ACALL In any case the programmer specifies the subroutine address to the assembler in the same way as a label or as a 16 bit constant The assembler will put the address into the correct format for the given instructions Subroutines should end with a RET instruction which returns execution to the instruction follow ing the CALL RETI is used to return from an interrupt service routine The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done If there is no interrupt in progress at the time RETI is executed then the RETI
366. method edge triggered high to low or level triggered active low INT1 0 also serves as external run control for timer1 0 when selected by GATE1 0 in TCON Keyboard Scan Input Schmitt trigger inputs with firmware enabled internal pullup resistors used for the input side of the keyboard scan matrix P3 3 2 AD7 0 P0 7 0 KSO19 KSO18 KSO17 16 KSO15 8 KSO7 0 Keyboard Scan Output Quasi bidirectional ports with weak internal pullup resistors used for the output side of the keyboard scan matrix P3 7 RD P3 6 WR P3 5 4 T1 0 A15 8 P2 7 0 P1 7 0 E 6 8X931AA DESIGN CONSIDERATIONS Table E 2 8x931AA Signal Descriptions Continued Signal Alternate Name Type Description Function LED3 0 LED Drivers Designed to drive LEDs connected directly to Voc The current each driver is capable of sinking is given as Voi2 P0 7 0 Port 0 Eight bit open drain bidirectional I O port Port 0 pins AD7 0 KSI7 0 have Schmitt trigger inputs P1 7 0 lO Port 1 Eight bit quasi bidirectional I O port with internal KSO7 0 pullups P2 7 0 lO Port 2 Eight bit quasi bidirectional I O port with internal A15 8 KSO15 8 pullups P3 0 lO Port 3 Eight bit quasi bidirectional I O port with internal P3 1 pullups SOF P3 2 INTO P3 3 INT1 P3 4 TO KSO16 P3 5 T1 KSO17 P3 6 WR KSO18 P3 7 RD KSO19 PLLSEL l Phase locked Loop Select See Table E 3 on page E 9 PS
367. mmand Condition Dr x Results Port 1 000 Disable Firmware should Places port in the Same port write 000 to disabled state the next HPCON upon time the bus is idle receipt of a ClearPortFeature with a PORT_ENABLE feature selector 001 Enable Firmware should Places port in the port write 001 to enabled state the next HPCON upon time the bus is idle receipt of a SetPortFeature with a PORT ENABLE feature selector 010 Resetand Firmware should Causes port x to Causes an internal hardware reset of enable write 010 to immediately drive an the FIU and FIFO circuitry relating to port HPCON upon SEO downstream for at the embedded function Certain receipt of least 15 msec and then embedded function SFRs are reset SetPortFeature with places the port in the to their default values as listed in PORT RESET enabled state Embedded Function Reset on page feature selector 7 24 After at least 15 ms hardware automatically places the port in the enabled state Firmware should handle reset of any other firmware and hardware features relating to the embedded function immediately after initiating the reset and enable through this SFR must be complete by 15 ms from start of reset 011 Suspend Firmware should Places the port in an Suspends the embedded function s port write 011 to idle J state the next port the next time the bus is idle HPCON upon time the bus is idle and preventing port 1 from generating r
368. mmary of Baud Rates Mode No of Send and Receive Send and Receive Baud Rates at the Same Rate at Different Rates 0 N A N A 1 Many Yes Yes 2 2 Yes No 3 Many Yes Yes Baud rates are determined by overflow of timer 1 and or timer 2 11 10 intel SERIAL I O PORT 11 6 2 Baud Rates for Mode 2 Mode 2 has two baud rates which are selected by the SMOD1 bit in the PCON register Figure 15 1 on page 15 3 The following expression defines the baud rate F Serial Mode 2 Baud Rate 29MOD y uu 11 6 3 Baud Rates for Modes 1 and 3 In modes 1 and 3 the baud rate is generated by overflow of timer 1 default and or timer 2 You may select either or both timer s to generate the baud rate s for the transmitter and or the receiv er 11 6 3 1 Timer 1 Generated Baud Rates Modes 1 and 3 Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3 The baud rate is determined by the timer 1 overflow rate and the value of SMOD as shown in the following formula SMOD1 Timer 1 Overflow Rate Serial I O Modes 1 and 3 Baud Rate 2 35 11 6 3 2 Selecting Timer 1 as the Baud Rate Generator To select timer as the baud rate generator Disable the timer interrupt by clearing the ETI bit in the IENO register Figure 6 12 on page 6 25 Configure timer 1 as a timer or an event counter set or clear the C T bit in the TMOD register Figure 11 5 on page 1
369. mplement OR and AND instructions These kinds of bit operations are not easily obtained in other architectures with any amount of byte oriented software Table 4 8 MCS 51Boolean Instructions Mnemonic Operation Tine Qus ANL C bit C C AND bit 2 ANL C bit C C AND NOT bit 2 ORL C bit C C OR bit 2 ORL C bit C OR NOT bit 2 MOV C bit C bit 1 MOV bit C bit 2 CLRC 0 1 CLR bit bit 0 1 SETBC C21 1 SETB bit bit 0 1 CPLC C NOT C 1 CPL bit bit NOT bit 1 JC rel Jump if C 1 2 JNC rel Jump if C 2 0 2 JB bit rel Jump if bit 1 2 JNB bit rel Jump if bit 0 2 JBC bit rel Jump if bit 2 1 CLR bit 2 intel PROGRAMMING CONSIDERATIONS The instruction set for the Boolean processor is shown in Table 4 8 All bit accesses are by direct addressing Bit addresses 00H through 7FH are in the Lower 128 and bit addresses 80H through FFH are in SFR space Note how easily an internal flag can be moved to a port pin MOV C FLAG MOV P1 0 C In this example FLAG is the name of any addressable bit in the Lower 128 or SFR space An I O line the LSB of Port 1 in this case is set or cleared depending on whether the flag bit is 1 or 0 The Carry bit in the PSW is used as the single bit Accumulator of the Boolean processor Bit instructions that refer to the Carry bit as C assemble as Carry specific instructions CLR C etc The Carry bit also has a direct address
370. mware routines needed to perform data transfers between the host PC and the embedded function as well as routines needed to handle hub oriented USB re quests It also describes briefly how the firmware interacts with the USB module hardware during these operations Data operations refer to data transfers over the USB whereas event operations are hardware operations such as attach and detach For a description of the USB function interface as well as its FIFOs and special functions registers SFRs refer to Chapter 6 USB Function For further information about the USB hub interface see Chapter 7 USB Hub For details on data flow in USB transactions refer to Appendix D Data Flow Model Initialization Enumeration Idle Application Code Transmit Receive SOF A4260 02 Figure 8 1 Program Flow 8 1 OVERVIEW OF PROGRAMMING MODELS The USB function interface employs four types of routines receive transmit setup and receive SOF Program flow is depicted in Figure 8 1 along with the type of token associated with each routine Following device reset the USB function enters the unenumerated state and after enu meration by the host the idle state From the idle state it can enter any of the four routines 8 1 8x931AA 8x931HA USER S MANUAL intel 8 1 4 Enumeration Following device reset the USB hub and function enter the unenumerated state Initially the hub address register HADDR
371. n response to a GetBusState request from the host Port x x 2 3 4 5 Set and cleared by hardware at the EOF2 point near the end of a frame used for diagnostics Port 1 Hard wired to 0 since there is no Dy signal for the embedded port 5 LSSTAT Low speed Device Attach Status read only Port x x 2 3 4 5 Set and cleared by hardware upon detection of the presence or absence of a low speed device at the EOF2 point near end of frame 1 low speed device is attached to port x 0 full speed device is attached to port x Port 1 Hard wired to 0 full speed since port 1 is permanently attached to the embedded USB function 4 PPSTAT Port Power Status read only Port x x 2 3 4 5 Set and cleared by hardware based on the present power status of the port as controlled either by firmware using the HPPWR register or by an overcurrent condition in hardware 1 port x is powered on 0 port x is powered off The port x power status is only sampled at the EOF2 point near end of frame Port 1 Hard wired to 1 since the internal function is always powered on NOTES Firmware returns the bits of this register in the first word of the 8x931 response to the host s GetPortStatus request See GetPortStatus Request Firmware on page 8 25 Overcurrent indication is not represented on a per port basis because the 8x931 supports ganged power control and overcurrent indicat
372. n excess of negatively charged carriers An interrupt that cannot be disabled masked A transistor consisting of one part p type material and two parts n type material Non Return to Zero Invert A method of encoding serial data in which ones and zeroes are represented by opposite and alternating high and low voltages where there is no return to zero reference voltage between encoded bits Eliminates the need for clock pulses A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter intel phase locked loop PID PLL program memory powerdown mode rel reserved bits resume RT root hub root port SEO SIE set SFR sink current SOF GLOSSARY A circuit that acts as a phase detector to keep an oscillator in phase with an incoming frequency Packet ID A field in a USB packet that identifies the type of packet and hence its format See phase locked loop A part of memory where instructions can be stored for fetching and execution The power conservation mode that freezes both the core clocks and the peripheral clocks A signed two s complement 8 bit relative destination address The destination is 128 to 127 bytes relative to the first byte of the next instruction Register bits that are not used in this device but may be used in future imp
373. n nnne nennen ennt ennt 8 16 8 6 HUB OPERATION eet EU irte ence deret TR d de dene dt dte 8 17 8 6 1 Hub Status and Configuration ssssseseeeeeneeeen rennen 8 17 vi intel E CONTENTS 8 6 2 Port Status Change Communication 8 23 8 6 3 Hub Firmware Examples 8 24 8 6 3 1 GetPortStatus Request Firmware seseeseeeneeeneennenen nenne 8 25 8 6 3 2 SetPortFeature PORT SUSPEND Firmware 8 26 8 6 8 8 SetPortFeature PORT RESET Firmware sse 8 27 CHAPTER 9 INPUT OUTPUT PORTS 9 1 INPUT OUTPUT PORT OVERVIEW nennen enn 9 1 9 2 VO CONFIGURATION bote Pipe 9 2 9 3 PORT TAND PORT 9t heec Fh en na ten ee 9 2 9 4 PORT O AND PORT 2 ie eei metere ee oneal eee 9 2 9 5 READ MODIFY WRITE INSTRUCTIONS essere 9 5 9 6 QUASI BIDIRECTIONAL PORT OPERATION sese eene 9 6 9 7 PORT LOADING Ie dE EM 9 7 9 8 EXTERNAL MEMORY ACCESS sse nennen n nnen neret nennen 9 7 CHAPTER 10 TIMER COUNTERS 10 1 TIMER COUNTER OVERVIEW eseseeeeeeeeneneneen eene nennen ener nnne tenen 10 1 10 2 TIMER COUNTER OPERATION nennen entere nnn nennen nnne 10 1 10 3 TIMER Quiere trot inet sian ete ended ee ceri Ree gs 10 4 10 331 Mode O 13 bit Timer cit Aad
374. n progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruc tion in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or write to IENx or IPx the additional wait time cannot be more than 5 cycles a maximum of one or more cycles to complete the instruction in progress plus 4 cycles to com plete the next instruction if the instruction is MUL or DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles CAUTION It is recommended that programmers set the contents of EPINDEX and or HPINDEX once at the start of each routine instead of writing to the EPINDEX register prior to each access of an endpoint indexed SFR and to HPINDEX prior to each access of a port indexed SFR This means that interrupt service routines must save the contents of the EPINDEX and HPINDEX registers at the start of the routine and restore the contents at the end of the routine to prevent the EPINDEX and HPINDEX registers from being corrupted 5 32 intel USB Function intel CHAPTER 6 USB FUNCTION This chapter describes the FIFOs and special function registers SFRs associated with the USB function interface This chapter along with Chapter 2 Architectural Overview and Chapter 8 USB
375. n unimplemented SFR location is read it returns an unspecified value SFRs shown with double borders are endpoint indexed Endpoint indexed SFRs are implemented as banks of registers similar to registers RO R7 There is a set or bank of registers for each end point pair Endpoint indexed SFRs are accessed by means of the SFR address and an index value The EPINDEX register specifies hub function and the endpoint number which serves as the in dex value See Endpoint indexed SFRs on page 6 5 and Hub Endpoint Indexing Using EPIN DEX on page 7 11 SFRs shown with bold borders are port indexed Port indexed SFRs are implemented as banks of registers similar to registers RO R7 There is a set or bank of port indexed SFRs for each USB downstream port Port indexed SFRs are accessed by means of the SFR address and an index val ue The HPINDEX register contains the port number which serves as the index value See Hub Port Indexing Using HPINDEX on page 7 23 NOTE The 8x931HA uses a different SFR map than the 8x931AA See Table E 4 on page E 10 for the 8x931AA SFR map Tables C 2 through C 6 list the SFRs by functional category Register definition tables which de scribe the SFRs and define the bits can be found arranged alphabetically in SFR Descriptions on page C 6 C 1 8x931AA 8x931HA USER S MANUAL 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F F8 KBCON 0xx00000 FO B EPINDEX TXSTAT TXDAT TXCON A TXFLG TXCNTL 00000000 1xxx
376. nd EDOVW 0 Clear Overwrite Bit EDOVW STOVW 1 or EDOVW 1 Overwrite Completed STOVW 0 and EDOVW 1 Clear Overwrite Bit EDOVW Yes Inhibited in hardware if STOVW or EDOVW are asserted Clear Firmware Setup Flag RXERR 1 RETI Normal Error Handling A5075 01 Figure 8 9 Post receive ISR Control 8 15 8x931AA 8x931HA USER S MANUAL 8 5 START OF FRAME SOF TOKEN intel Figure 8 10 illustrates the hardware operations performed by the function interface for a start of frame SOF token The host issues an SOF token at a nominal rate of once every 1 0 ms An SOF token is valid if the PID is good The SOF token is not endpoint specific it should be received by every node on the bus Valid SOF Token oris Sansor of Transfer Yes SOFH 7 Set SOFACK SOF token received without error Write SOF Registers Generate SOF Pulse by Asserting SOF Pin Done SOFH SOFL SOFH 7 A4267 02 Figure 8 10 Hardware Operations for SOF Token 8 16 intel USB PROGRAMMING MODELS 8 6 HUB OPERATION The primary objective of the programming model suggested here is to explain the linkage be tween the hardware and firmware of the 8x931HA in operation NOTE Since the 8x931AA microprocessor does not support a hub interface the programming models in this section are unnecessa
377. nd external clock sources Chapter 14 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode This chapter also describes the power control PCON special function register and lists the status of the device pins during the special modes Chapter 15 External Memory Interface describes the external memory signals and bus cycles and provides examples of external memory design It also provides waveform diagrams for the bus cycles Chapter 16 Verifying Nonvolatile Memory provides instructions for verifying on chip program memory signature bytes and lock bits Appendix A Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the bits in the program status word register PSW shows the relationships between instructions and PSW flags and lists hexadecimal opcodes in struction lengths and execution times Appendix B Pin Descriptions describes the function s of each device pin Descriptions are listed alphabetically by signal name This appendix also provides a list of the signals grouped by functional category Appendix C Registers accumulates for convenient reference copies of the register defi nition figures that appear throughout the manual Appendix D Data Flow Model describes the data flow model for the 8x931 USB transa
378. nd instruction set see the MCS 51 Microcontroller Family User s Manual order number 272383 For further information on the 8x931 see Microcontroller Core on page 2 6 and Universal Serial Bus Module on page 2 11 2 1 4 8x931AA Features The 8x931AA provides a USB interface for one PC peripheral The 8x931AA function interface provides three function endpoint pairs with corresponding transmit receive FIFO pairs Function endpoint 0 supports control data transfers only while function endpoints 1 and 2 support control interrupt and bulk data transfers Function endpoint 1 which has 16 byte FIFOs also supports isochronous data transfers See Table 2 5 on page 2 12 for endpoint pair information 2 1 2 8x931HA Features The 8x931HA also provides a USB hub capability permitting the connection of additional PC peripherals or hubs In addition to an upstream port to the host PC USB root port the 8x931HA provides four external downstream ports with ganged power switching and an internal down stream port for the embedded function The 8x931HA provides on chip transceivers for each of the external USB ports The 8x931HA has two hub endpoint pairs endpoint 0 which supports 8 byte control data trans fers and endpoint 1 which transmits a status change byte to the host PC See Table 2 2 for a sum mary of USB features and Table 2 5 on page 2 12 for endpoint pair information See Figure 2 3 for the 8x931HA USB module block diagram
379. nee Response Comments o ERR ACK Voia 2 12 Received IN 01 10 1 0 1 no 1 None Timeout Treated like a token with no no chg no void condition existing FIFO chg chg chg error Received IN 01 10 0 0 1 no no None Timeout Endpoint not token but TXOE chg chg enabled for 0 transmit but no NAK for ISO Data loaded into 11 no no no no no None N A Firmware FIFO from CPU chg chg chg chg chg should always CNT written check TXFIF bits before loading and TXOVF after loading Data loaded into 01 10 no no no 1 no None N A Only overrun FIFO FIFO error chg chg chg chg FIFO error can occurs occur here Firmware should always check TXOVF before write CNT Note no TXERR but TXOVF set 11 Received IN 10 01 0 1 0 no no None Send data No ACK time token data chg chg out for ISO transmitted with Read marker or without advanced transmission error NOTES 1 These are sticky bits which must be cleared by firmware 2 TXFIF TXOVF and TXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF TXOVF Since overrun can only be caused by firmware TXOVF is updated immediately TXURF Since underrun can only be caused by USB TXURF is updated at SOF TXFIF TXFIF is incremented by firmware and decremented by USB Therefore writes to TXCNT will increment TXFIF immediately However a succ
380. nemonic Function 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by firmware TF2 is not set if RCLK 1 or TCLK 1 6 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflo
381. neneneeeennennen 5 13 5 7 HIE Hub Interrupt Enable Register 5 15 5 8 HIFLG Hub Interrupt Status 5 16 5 9 USB Reset Separation Operating Model eene 5 20 5 10 IENO USB Interrupt Enable Register 0 sene 5 24 5 11 IEN1 USB Interrupt Enable Register esseeeeeneeeneenen 5 25 5 12 IPHO Interrupt Priority High Register e 5 27 5 13 IPLO Interrupt Priority Low Register 0 5 28 5 14 IPH1 Interrupt Priority High Register 1 5 29 5 15 IPL1 Interrupt Priority Low Register 1 5 30 5 16 Interrupt Response Timing 5 31 6 1 Bits of th USB Function SERS ce o me e ies 6 4 6 2 EPINDEX Endpoint Index Register 6 6 6 3 EPCON Endpoint Control Register esssesssseeeeeenneeneen nennen 6 7 6 4 TXSTAT Transmit FIFO Status Register sssseeeeneenenenn 6 9 6 5 RXSTAT Receive FIFO Status Register sssssseeneeeennene 6 11 6 6 FADDR Function Address Register 6 14 6 7 Transmit FIFO OUIRE assesoires ain rr ideato creen nena t petere trei 6 15 6 8 TXDAT Transmit FIFO Data Register sse 6 16 6 9 TXCNTL Transmit FIFO Byte Count Register ssseeeenn 6
382. ng enumeration as required by the Universal Serial Bus Specification Self powered devices i e devices drawing less than 100mA from the USB wires may choose not to switch to Low Clock mode after detecting the USB reset NOTE If desired your firmware can handle the separate USB reset without using an ISR To do this you must clear the ESR bit in the IENI SFR The USB reset hardware operations will still take place but the ISR will not be called That is step 1 and step 2 under USB Reset Hardware Operations on page 5 21 will still occur but step 3 will not Your firmware must poll the URST flag periodically to detect the USB reset and take the appropriate action Since the global suspend and global resume interrupts share the same interrupt vector as USB reset your firmware must also poll the GRSM and GSUS bits in PCONI to detect global suspend or resume If instead you choose to implement a separate USB reset using an ISR follow the procedure out lined in the following subsections and displayed in Figure 5 9 5 2 9 1 Initialization Required for USB Reset Because USB reset implementation depends heavily on firmware your code must perform the following initialization prior to execution of the main routine See Figure 5 9 1 To enable the USB reset interrupt on the 8x931 your initialization routine must set the following bits to 1 a the EA bit of IENO Figure 5 10 b the ESR bit of IEN1 Figure 5 11 c the URDIS bi
383. ng operating modes capture mode auto reload mode baud rate gen erator mode and programmable clock out mode Select the operating mode with T2MOD and TCON register bits as shown in Table 10 3 on page 10 15 Auto reload is the default mode Set ting RCLK and or TCLK selects the baud rate generator mode Timer 2 operation is similar to timer 0 and timer 1 C T2 selects the divided down system clock timer operation or external pin T2 counter operation as the timer register input Setting TF2 allows TL2 to be incremented by the selected input The operating modes are described in the following paragraphs Block diagrams in Figures 10 7 through 10 10 show the timer 2 configuration for each mode 10 10 intel TIMER COUNTERS 10 6 1 Capture Mode In the capture mode timer 2 functions as a 16 bit timer or counter Figure 10 7 An overflow condition sets bit TF2 which you can use to request an interrupt Setting the external enable bit EXEN allows the RCAP2H and RCAP2L registers to capture the current value in timer registers TH2 TL2 in response to 1 0 0 transition at external input T2EX The transition at 2 also sets bit EXF2 in T2CON The EXE2 bit like TF2 can generate an interrupt Overflow FOLK gt TH2 TL2 8 Bits 8 Bits Interrupt Request T2EX 7 2 5201 01 Figure 10 7 Timer 2 Capture Mode 10 11 8x931AA 8x931HA USER S MANUAL intel 10 6 2 Auto
384. nly at the next SOF regardless of where the overrun occurred during the current frame T When set all transmissions are NAKed Figure 6 16 RXFLG Receive FIFO Flag Register Continued 6 33 8x931AA 8x931HA USER S MANUAL intel 6 5 SIE DETAILS The USB employs differential data signaling refer to the signaling levels table in the Electrical chapter of Universal Serial Bus Specification The specification defines differential 1 differen tial 0 idle P state non idle K state start of packet end of packet disconnect connect re set and resume The USB employs NRZI data encoding when transmitting packets Refer to Data Encoding Decoding in the Universal Serial Bus Specification for a description of NRZI data encoding and decoding To ensure adequate signal transitions bit stuffing is employed by the SIE when transmitting data The SIE also performs bit unstuffing when receiving data Con sult the Flow Diagram for Bit Stuffing figure in the Bit Stuffing section of the Electrical chapter for more information on bit stuffing Bits are sent out onto the bus least significant bit LSb first followed by the next LSb and so on Bytes are sent out onto the bus least significant byte LSB first followed by the next LSB and so on The serial bus interface engine SIE ensures that the LSb is first but the 8x931 pro grammer must ensure the order of the bytes The S
385. nous data begin when the 8x931 receives a valid OUT token from the host The received data is written to a data buffer FIFO The 8x931 indicates completion of data received by returning a handshake to the host At the end of the receive cycle the 8x931 generates a receive done interrupt to notify the CPU that a receive operation has occurred Program execution branches to the interrupt service routine and transfers the data packet from the receive FIFO to its destination The interrupt can also be used for fail safe management and activity tracking For isochronous data receive cycles are somewhat different Data transactions are initiated by an OUT token At the end of the OUT transaction the 8x931 does not return handshake to the host and the receive done interrupt is not generated Instead the SOF interrupt is used for post receive management The data reception status is updated at the next SOF The 8x931 supports one ISO packet per frame per endpoint Two bits in the receive FIFO control register RXCON Figure 6 15 on page 6 29 have a major influence on receive operation The ISO bit RXCON 3 determines whether the reception is for isochronous data ISO 1 or non isochronous data ISO 0 For non isochronous data only the function interface sends a handshake to the host checks the sequence bit and generates a receive done FRXDx interrupt Also for non isochronous data the post receive routine is an ISR for isochronous data t
386. nt indexed Reset State 0000 0000B Endpoint Receive Status Register Contains the current endpoint status of the receive FIFO specified by EPINDEX 7 0 RXSEQ RXSETUP STOVW EDOVW RXSOVW RXVOID RXERR RXACK Bit Bit Function Number Mnemonic 7 RXSEQ Receiver Endpoint Sequence Bit read conditional write This bit will be toggled on completion of an ACK handshake in response to an OUT token This bit will be set or cleared by hardware after reception of a SETUP token This bit can be written by firmware if the RXSOVW bit is set when written along with the new RXSEQ value NOTE Always verify this bit after writing to ensure that there is no conflict with hardware which could occur if a new SETUP token is received 6 RXSETUP Received Setup Token This bit is set by hardware when a valid SETUP token has been received When set this bit causes received IN or OUT tokens to be NAKed until the bit is cleared to allow proper data management for the transmit and receive FIFOs from the previous transaction IN or OUT tokens are NAKed even if the endpoint is stalled RXSTL or TXSTL to allow a control transaction to clear a stalled endpoint Clear this bit upon detection of a SETUP token after the firmware is ready to complete the status stage of a control transaction 5 STOVW Start Overwrite Flag read only Set by hardware upon receipt of a SETUP token for any control endpoint to in
387. nt must be such that RST remains high above the turn off threshold of the Schmitt trigger long enough for the oscillator to start and stabilize plus two machine cycles At power up Vcc should rise within approximately 10 ms Oscillator start up time is a function of the crystal frequency During power up the port pins are in a random state until forced to their reset state by the asynchronous logic Reducing V quickly to 0 causes the RST pin voltage to momentarily fall below 0 V This voltage is internally limited and does not harm the device lt 12 Osc Periods 9 55 se st 82 sa 54 ss se 51 se 5 84 55 se 81 se ss sa RST Pa Sample RST Sample RST Internal reset signal PSEN c am 11 Osc Periods 4 4 19 Osc Periods A4457 01 Figure 13 5 Reset Timing Sequence 13 7 intel 14 Special Operating Modes intel CHAPTER 14 SPECIAL OPERATING MODES This chapter describes the idle powerdown low clock and on circuit emulation ONCE device operating modes and the USB function suspend and resume operations The SFRs associated with these operations PCON and PCON1 are also described 14 4 OVERVIEW The idle low clock and powerdown modes are power reduction modes for use in applications where power consumption is a concern User instructions activate these modes by
388. nt near the end of a frame used for diagnostics Port 1 Hard wired to 1 since there is no D signal for the embedded port 6 DMSTAT Dy Status read only Value of Dy for port x at end of last frame Firmware must return this bit in response to a GetBusState request from the host Port x x 2 3 4 5 Set and cleared by hardware at the EOF2 point near the end of a frame used for diagnostics Port 1 Hard wired to 0 since there is Dy signal for the embedded port 5 PPSTAT Port Power Status read only Port x x 2 3 4 5 Set and cleared by hardware based on the present power status of the port as controlled either by firmware using the HPPWR register or by an overcurrent condition in hardware 1 port x is powered on 0 port x is powered off The port x power status is only sampled at the EOF2 point near end of frame Port 1 Hard wired to 1 since the internal function is always powered on 4 LSSTAT Low speed Device Attach Status read only Port x x 2 3 4 5 Set and cleared by hardware upon detection of the presence or absence of a low speed device at the EOF2 point near end of frame 1 low speed device is attached to port x 0 full speed device is attached to port x Port 1 Hard wired to 0 full speed since port 1 is permanently attached to the embedded USB function NOTES Firmware returns the bits of this register in the first word of t
389. nt will NAK This bit does not affect the reception of SETUP tokens by a control endpoint TXSTL CTLEP Stall Transmit Endpoint Set this bit to stall the transmit endpoint This bit should be cleared only when the host has intervened through commands sent down endpoint 0 When this bit is set and RXSETUP is clear the receive endpoint will respond with a STALL handshake to a valid IN token When this bit is set and RXSETUP is set the receive endpoint will NAK Control Endpoint Set this bit to configure the endpoint as a control endpoint Only control endpoints are capable of receiving SETUP tokens RXSPM RXIE Receive Single Packet Mode Set this bit to configure the receive endpoint for single data packet operation When enabled only a single data packet is allowed to reside in the receive FIFO NOTE For control endpoints CTLEP 1 this bit should be set for single packet mode operation as the recommended firmware model However it is possible to have a control endpoint configured in dual packet mode as long as the firmware handles the endpoint correctly Receive Input Enable Set this bit to enable data from the USB to be written into the receive FIFO If cleared the endpoint will not write the received data into the receive FIFO and at the end of reception but will return a NAK handshake on a valid OUT token if the RXSTL bit is not set This bit does not affect a valid SETUP token A valid SETUP t
390. numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter is added for clarity All register bits support read write access unless noted otherwise in the bit description Other types of access include read only write only read conditional write etc Bit locations are indexed by 7 0 for byte registers 15 0 for word registers and 31 0 for double word dword registers where bit O is the least significant bit and 7 15 or 31 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example PCON 4 is bit 4 of the power control register In some discussions bit names are used For example the name of PCON 4 is POF the power off flag Register names are shown in upper case For example PCON is the power control register If a register name contains a lowercase character it represents more than one register For example CCAPMx represents the five registers CCAPMO through CCAPM4 Some registers contain reserved bits These bits are not used in this device but they may be used in future implementations Do not write a 1 to a reserved bit The value read from a reserved bit is indeter minate The terms set and clear refer to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value If a bit is cle
391. o the 8x931AA Since the 8x931AA peripheral controller does not support a hub interface there are no downstream ports to signal a resume condition A resume condition can still be signalled by any of the other conditions described in Global Resume Mode on page 14 9 The 8x931HA SFR map given in Appendix C Registers does not apply to 8x931AA The 8x931AA SFRs are given in 8x931AA SFR Map on page E 10 The 8x931AA pin and signal descriptions differ from those described in Appendix B Pin Descriptions See 8x931AA Pin Descriptions page E 3 and 8x931AA Signal Descriptions on page E 6 The 8x931AA allows operating frequency selection using the FSSEL pin See Operating Frequencies on page E 9 E 1 8x931AA 8x931HA USER S MANUAL intel 2 8 931 ENUMERATION PROCESS The 8x931AA enumeration process is simpler than the 8x931HA bus enumeration process given in Enumeration on page 8 2 The 8x931AA enumeration process has four steps 1 2 Get device descriptor The host requests and reads the device descriptor to determine maximum packet size Set address The host sends the 8x931 s function address in a data packet using function endpoint 0 Device firmware interprets the data and instructs the CPU to write the function address to FADDR Get device descriptor The host requests and reads the device descriptor to determine such information as device class USB specification complian
392. o the SIE The SIE provides serial to par allel conversion for data transfers from the host and parallel to serial conversion for data transfers to the host For additional information on the SIE see SIE Details on page 6 34 2 4 5 Hub Interface Unit HIU The HIU uses special function registers SFRs to control the operation of the hub and to maintain the status of the hub and its downstream ports Control SFRs are set by firmware in response to USB requests Status SFRs are set by the repeater hardware Refer to Chapter 7 USB Hub and Chapter 8 USB Programming Models for a discussion on the use of the HIU SFRs 2 4 6 Hub FIFOs Hub FIFOs operate in the same manner as the function interface FIFOs See Chapter 6 USB Function for a detailed description of their operation Hub endpoint 0 handles only control data transfers It is implemented with 8 byte transmit and receive FIFO data buffers The maximum packet size for hub control data transfers is eight bytes Data received from the USB for endpoint 2 13 8x931AA 8x931HA USER S MANUAL intel 0 is stored in the receive FIFO for reading by firmware Data to be sent to the host from hub end point 0 is loaded into the transmit FIFO Hub endpoint transmits single byte interrupt tokens to the host and does not have FIFO data buffers 2 5 ON CHIP PERIPHERALS The on chip peripherals reside outside the microcontroller core They perform specialized func tions in ha
393. ogram fetches Microcontroller EPROM RAM without on chip 64 Kbytes 64 Kbytes code memory EA CE CE D7 0 WR RD PSEN OE WE A4287 03 15 8 Figure 15 7 Bus Diagram for Example 3 8x931AA HA intel 1 6 Verifying Nonvolatile Memory intel CHAPTER 16 VERIFYING NONVOLATILE MEMORY This chapter discusses the 83931 on chip memory and provides the procedure for verifying on chip nonvolatile memory 16 1 83931 MEMORY The MCS 51 architecture provides separate 64 Kbyte address spaces for program memory and data memory see 8x931 Memory on page 2 11 Table 2 1 on page 2 3 lists the available on chip ROM and RAM memory options for the 83931 16 2 NONVOLATILE MEMORY For ROM devices 83931 on chip program memory is located at the lowest addresses of the pro gram memory address space ROM devices also make provision for storing signature bytes an encryption array and lock bits in on chip nonvolatile memory outside the program and data memory address spaces In some applications it is desirable that program code be secure from unauthorized access The 83931 offers two types of protection for on chip program code On chip program code is encrypt ed when read out for verification if the encryption array is programmed Lock bits restrict external access to on chip program memory 16 3 VERIFYING ON CHIP NONVOLATILE MEMORY This section provides instructions for verifying the contents of
394. ointer Read Marker X ACK Unchanged Advanced 1 0 NAK Reversed 2 Unchanged 1 NAK Unchanged Advanced 1 1 to origin of next data set 2 to origin of the data set last read This bit should always be set except for test purposes Setting this bit disables ADVRM and REVRP This is a sticky bit that is not reset when TXCLR is set but can be set and cleared by firmware Hardware neither clears nor sets this bit ATM mode is recommended ADVRM and REVRP which control the read marker and read pointer when ATM 0 are used for test purposes Figure 6 10 TXCON Transmit FIFO Control Register 6 19 8x931AA 8x931HA USER S MANUAL intel TXCON Continued Address F4H Endpoint indexed Reset State 0100B USB Transmit FIFO Control Register Controls the transmit FIFO specified by EPINDEX 7 0 TXCLR TXISO ATM ADVRM REVRP Bit Bit Function Number Mnemonic 1 ADVRM Advance Read Marker Control non ATM mode only Setting this bit prepares for the next packet transmission by advancing the read marker to the origin of the next data packet the position of the read pointer Hardware clears this bit after the read marker is advanced This bit is effective only when the REVRP ATM and TXCLR bits are all clear 0 REVRP Reverse Read Pointer Control non ATM mode only In the case of a bad transmission the same data stack may need to be available for retransmit Setting
395. ointer will not advance it remains locked in the empty position In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since underrun can only be caused by firmware RXURF is updated immediately You must check the RXURF flag after reads from the receive FIFO before setting the RXFFRC bit in RXCON NOTE When this bit is set the FIFO is in an unknown state It is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register RXOVF Receive FIFO Overrun Flagt This bit is set when the FIU writes an additional byte to a full receive FIFO or writes a byte count to RXCNTL with FIF1 0 11 This is a sticky bit that must be cleared through firmware although it can be cleared by hardware if a SETUP packet is received after an RXOVF error had already occurred t When this bit is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register When the receive FIFO overruns the write pointer will not advance it remains locked in the full position In ISO mode RXOVF RXURF and RXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since overrun can only be caused by the USB RXOVF is updated o
396. oken When this bit is set and RXSETUP is set the receive endpoint will NAK This bit does not affect the reception of SETUP tokens by a control endpoint Stall Transmit Endpoint Set this bit to stall the transmit endpoint This bit should be cleared only when the host has intervened through commands sent down endpoint 0 When this bit is set and RXSETUP is clear the receive endpoint will respond with a STALL handshake to a valid IN token When this bit is set and RXSETUP is set the receive endpoint will NAK CTLEP Control Endpoint Set this bit to configure the endpoint as a control endpoint Only control endpoints are capable of receiving SETUP tokens RXSPM Receive Single Packet Mode Set this bit to configure the receive endpoint for single data packet operation When enabled only a single data packet is allowed to reside in the receive FIFO NOTE For control endpoints CTLEP 1 this bit should be set for single packet mode operation as the recommended firmware model However it is possible to have a control endpoint configured in dual packet mode as long as the firmware handles the endpoint correctly RXIE Receive Input Enable Set this bit to enable data from the USB to be written into the receive FIFO If cleared the endpoint will not write the received data into the receive FIFO and at the end of reception but will return a NAK handshake on a valid OUT token if the RXSTL bit is not set T
397. oken and packet override this bit if it is cleared and place the receive data in the FIFO For hub endpoint 0 EPINDEX 1000 0000 bits 5 and 4 are hard wired to 1 since hub endpoint 0 is always a control endpoint C 8 a intel REGISTERS EPCON Continued Address E1H Endpoint indexed Reset State Endpoint 0 0011 0101B Function Endpoints 1 2 0001 0000B Endpoint Control Register This SFR configures the operation of the endpoint specified by EPINDEX 7 RXSTL TXSTL 0 CTLEP RXSPM RXIE RXEPEN TXOE TXEPEN Bit Number Bit Mnemonic Function 2 RXEPEN Receive Endpoint Enable Set this bit to enable the receive endpoint When disabled the endpoint does not respond to a valid OUT or SETUP token This bit is hardware read only and has the highest priority among RXIE and RXSTL Note that endpoint 0 is enabled for reception upon reset TXOE Transmit Output Enable This bit is used to enable the data in TXDAT to be transmitted If cleared the endpoint returns a NAK handshake to a valid IN token if the TXSTL bit is not set TXEPEN Transmit Endpoint Enable This bit is used to enable the transmit endpoint When disabled the endpoint does not respond to a valid IN token This bit is hardware read only Note that endpoint 0 is enabled for transmission upon reset For hub endpoint 0 EPINDEX 1000 0000 bits 5 and 4 are hard wired to 1 since hub end
398. onfiguration descriptor to determine such information as the number of interfaces and endpoints endpoint transfer type packet size and direction power source maximum power etc When the host requests the configuration descriptor all related interface endpoint descriptors are returned For additional information on the 8x931HA descriptors see Hub Descriptors on page 7 7 NOTE Some versions of the operating system send a Get string descriptor at this point in the enumeration process 5 Set configuration The host assigns a configuration value to the device to establish the current configuration 6 Get hub descriptor The host requests and reads the hub descriptor to determine such information as number of downstream ports hub characteristics controller current removable devices etc For additional information see Table 7 3 Hub Descriptors 7 Next the hub downstream ports start the state flow shown in Figure 7 3 on page 7 5 The host issues a SetPortPowerFeature request to the downstream ports that were declared in the hub descriptor This moves the hub downstream ports to the disconnect state 8 2 intel USB PROGRAMMING MODELS 8 As connect detects occur the host is notified through hub endpoint 1 status change endpoint The host then issues a GetPortStatus command retrieving the contents of HPSTAT and HPSC to determine the change for a specific downstream port The host then issues a ClearPortConnectionFeatu
399. only Sd Stop Bit A2261 01 Figure 11 4 Data Frame Modes 1 2 and 3 intel SERIAL I O PORT 11 2 2 Asynchronous Modes Modes 1 2 and 3 The serial port has three asynchronous modes of operation e Mode 1 Mode 1 is a full duplex asynchronous mode The data frame Figure 11 4 consists of 10 bits one start bit eight data bits and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin When a message is received the stop bit is read in the 8 bit in the SCON register The baud rate is generated by overflow of timer 1 or timer 2 see Baud Rates on page 11 10 Modes 2 and 3 Modes 2 and 3 are full duplex asynchronous modes The data frame Figure 11 4 consists of 11 bits one start bit eight data bits transmitted and received LSb first one programmable ninth data bit and one stop bit Serial data is transmitted on the TXD pin and received on pin On receive the ninth bit is read from the RB8 bit in the SCON register On transmit the ninth data bit is written to the TB8 bit in the SCON register Alternatively you can use the ninth bit as a command data flag In mode 2 the baud rate is programmable to 1 32 or 1 64 of the oscillator frequency Fosc In mode 3 the baud rate is generated by overflow of timer 1 or timer 2 11 2 2 1 Transmission Modes 1 2 3 Follow these steps to initiate a transmission 1 Write to the SCON register Sel
400. ontrol as in Figure 4 3 Two bytes are specified in the operand field of the instruction The jump is executed only if the two bytes are not equal In the example of Figure 4 3 the two bytes are the data in and the constant 2AH The initial data in is 2EH Every time the loop is executed is dec remented and the looping is to continue until the R1 data reaches 2AH Another application of this instruction is in greater than less than comparisons The two bytes in the operand field are taken as unsigned integers If the first is greater than or equal to the sec ond then the Carry bit is cleared 4 16 intel Interrupt System intel CHAPTER 5 INTERRUPT SYSTEM 5 1 OVERVIEW The 8x93 1 like other control oriented microcontroller architectures employs a program interrupt method This operation branches to a subroutine and performs some service in response to the interrupt When the subroutine completes execution resumes at the point where the interrupt oc curred Interrupts may occur as a result of internal 8x931 activity e g timer overflow or at the initiation of electrical signals external to the microcontroller e g keyboard scan In all cases in terrupt operation is programmed by the system designer who determines priority of interrupt ser vice relative to normal code execution and other interrupt service routines All of the interrupts are enabled or disabled by the system designer and may be manipulated
401. or connect status is communicated to the host via hub endpoint 1 s TXDAT register as shown in Figure 7 8 on page 7 13 The information passed through hub endpoint 1 is sufficient to indicate which port or the hub itself changed status but it does not indicate which status value changed or the current value of any status indicator Firmware has no involvement with USB communication to hub endpoint 1 status change endpoint 1 This communication is handled completely in hardware and is discussed in USB Hub Endpoints on page 7 10 After the host receives notice of a change in port status through hub endpoint 1 host firmware can determine which status value changed and the current value of all the port s status indicators by transmitting a GetPortStatus request through hub endpoint 0 This request includes a Port Index to tell the 8x931HA which port is of interest to the host See the Universal Serial Bus Specification for additional information The host s GetPortStatus request triggers the 8x931HA GetPortStatus routine The firmware response to the GetPortStatus request provides the host with the port s current status along with an indication of any status changes that have occurred See GetPortStatus Request Firmware on page 8 25 for a complete description of this routine The host resets the port status change indicators by issuing a separate ClearPortFeature request for each bit in HPSC that showed a change Each ClearPortFeature
402. or example when a timer counter counts external events the external input is sampled during state 5 phase 2 S5P2 of every machine cycle The 8x931 executes single cycle instructions in one machine cycle With 12 MHz crystal Fc 6 MHz and the duration of a machine cycle is 1 us Instruction execution begins in state 1 of a machine cycle when the opcode is latched into the instruction register Execution is complete at the end of state 6 On chip peripherals such as the timer counter also operate on a machine cycle 2 2 2 2 USB Operating Rate Because of its hub capability the 8x931HA including the embedded function always operates as a full speed 12 Mbps USB device Root port data transfers with the host PC are always full speed Data transfer rates on the external downstream ports are matched to the type of USB device attached i e full speed or low speed 1 5 Mbps For full speed operation the PLL provides the 4X USB sampling rate The 8x931AA can operate as a full speed 12Mbps or low speed 1 5Mbps device 2 2 2 3 Low clock Mode Low clock mode is a special power reduction mode in which the CPU and the on chip peripher als operate at 3 MHz following device reset To exit low clock mode clear the LC bit in the PCON register During low clock mode Ferg 3 MHz so the timing definitions in Figure 2 5 do not apply to the CPU and on chip peripherals Low clock mode does not affect the USB rate Also see Chapter 14 Sp
403. ors forcing new SETUP to be received RXIE or RXSTL has no effect 2 RXSETUP will be set control endpoints only Received 01 1 0 0 0 0 0 Set Time out FIFO is reset SETUP receive automatically token but interrupt and FIFO data timed out is invalid 2 waiting for data Received 00 1 0 0 1 0 0 Set Time out Write pointer SETUP receive reversed RXIE token data interrupt or RXSTL has CRC or bit no effect 2 stuff error RXSETUP will be set control endpoints only Received 00 1 0 0 1 1 0 Set Time out 2 control SETUP receive NAK endpoints only token FIFO interrupt future error occurs transactio ns Received 01 Set Causes FIFO SETUP receive to reset token with interrupt automatically FIFO error forcing new already SETUP to be existing received RXIE or RXSTL has no effect 2 RXSETUP will be set control endpoints only CPU reads 00 FIFO sets RXFFRC NOTE 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase intel DATA FLOW MODEL Table D 3 Non isochronous Receive Data Flow in Single packet Mode RXSPM 1 Continued New RX RX RX FIF RX RX RX RX USB Event FIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void Setup 1 1 rupt Response CPU reads 01
404. ort 0 These lines do not have internal pullup resistors For low speed devices provide an external 1 5 KO pullup resistor at Dyo For full speed devices provide an external 1 5 KO pullup resistor at Dog NOTE Provide an external 1 5 KO pullup resistor at Dpg so the device indicates to the host that it is a full speed device ECAP External Capacitor Must be connected to a 1 uF capacitor or larger to ensure proper operation of the differential line driver The other lead of the capacitor must be connected to Vss The FIU controls operations through the use of four sets of special functions registers SFRs the FIU SFRs the transmit FIFO SFRs the receive FIFO SFRs and the USB interrupt SFRs Table 6 3 lists the SFRs described in this chapter Figure 6 1 provides a quick reference to the bit as signments in the SFRs USB interrupt SFRs are described in Chapter 5 Interrupt System Table C 1 on page C 2 shows a memory map of all the 8x931HA SFRs Table E 4 on page E 10 shows a memory map of all the 8x931AA SFRs 6 2 Table 6 3 USB Function SFRs USB FUNCTION Mnemonic Description Address Page EPCON Endpoint Control Register Configures the operation of the E1H page 6 7 endpoint specified by EPINDEX EPINDEX Endpoint Index Register Selects the appropriate endpoint pair F1H page 6 6 FADDR Function Address Register Stores the USB function address
405. ort 2 010 Port 3 011 Port 4 100 Port 5 101 NOTE Port 0 000 the root port and all other combinations not shown above are not valid port indexes and are ignored 8x931AA 8x931HA USER S MANUAL intel HPPWR Hub Port Power Control Register This register is used to control power to the hub s downstream ports Address 9AH Reset State xx00 001x 7 0 HPPWR5 HPPWR4 HPPWRS3 HPPWR2 HPPWR1 Bit Bit Number Mnemonic Function 7 6 Reserved Write zeros to these bits 5 2 HPPWR5 2 Port Power Control for USB Ports 5 2 HPPWR1 Bit 5 is power control for port 5 bit 4 for port 4 bit 3 for port 3 and bit 2 for port 2 These bits are set and cleared by firmware via a USB host request SetPortFeature with the PORT POWER feature selector These bits will also be cleared by hardware upon detection of an over current condition This is done to prevent oscillation of the UPWEN pin during an over current condition with bus powered devices A value of 1 enables power to the downstream port and puts the port in a disconnected state A value of 0 turns the downstream port power off NOTE The UPWEN pin is set to 1 only if all port power enable bits are 0 due to the use of a ganged shared power enable scheme Port Power Control for USB Port 1 read only Port 1 is an internal port and is always powered on Thi
406. over and equals the read marker Hardware clears this bit when the full condition no longer exists Regardless of ISO or non ISO mode this bit always tracks the current transmit FIFO status Check this bit to avoid causing a TXOVF condition TXOVF Transmit FIFO Underrun Flag Hardware sets this flag when an additional byte is read from an empty transmit FIFO or TXCNT This is caused when the value written to TXCNT is greater than the number of bytes written to TXDAT This is a sticky bit that must be cleared through firmware When this flag is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in your error management routine using the TXCLR bit in TXCON When the transmit FIFO underruns the read pointer will not advance it remains locked in the empty position If the TXCNT doesn t agree with the data hardware sets TXURF This indicates that the transmitted data was corrupted by a bit stuffing or CRC error In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since underrun can only be caused by USB TXURF is updated at the next SOF regardless of where the underrun occurs in the frame Transmit FIFO Overrun Flag This bit is set when an additional byte is written to a full FIFO or full TXCNT with TXFIF1 0 11 This is a sticky bit that must be cleared
407. ower to their downstream components and are re sponsible for reporting their power distribution capabilities to the host during enumeration Hubs may be either locally powered bus powered or a combination of the two The distinction is made depending on how the user implements the power scheme at the board level which should be in dicated in the value of the bmAttributes field of the configuration descriptor A hub can only supply power in a downstream direction and must never drive power upstream Bus powered hubs must have port power switching for the downstream ports and are required to power off all downstream ports when the hub comes out of power up or when it receives a reset on its root port Port power can also be switched on or off under control of the host PC Port power switching is optional for self powered devices NOTE Port power switching and over current detection discussed in the following subsections are mutually exclusive Over current detection is required only for self powered hubs while port power switching is required only for bus powered hubs 7 7 1 Port Power Switching Port power switching is only supported on a ganged basis therefore there is only one output pin used to enable power to the downstream devices From a USB perspective power can be enabled on a per port basis but the power enable is active if any of the ports are powered on by the host The host PC can selectively switch power on or off for a giv
408. owerdown mode stops the oscillator and freezes all clocks at known states Figure 2 4 on page 2 7 The CPU status prior to entering powerdown mode is preserved i e the program counter program status word regis ter and register file retain their data for the duration of powerdown mode In addition the SFRs and RAM contents are preserved The status of the port pins depends on the location of the pro gram memory Internal program memory the ALE and PSEN pins are pulled low and the pins of parallel ports 0 3 are driving the port SFR value Table 14 1 on page 14 6 External program memory the ALE and PSEN pins are pulled low the port 0 pins are floating and the pins of ports 1 and 3 are reading data and Port 2 pins are weakly pulled high Table 14 1 NOTE Vcc may be reduced to as low as 2 during powerdown to further reduce power dissipation Take care however that V is not reduced until power down is invoked 14 4 1 2 Entering Powerdown Suspend Mode To enter powerdown mode set the PCON register PD bit The 8x931 enters powerdown mode upon execution of the instruction that sets the PD bit The instruction that sets the PD bit is the last instruction executed CAUTION Do not put the 8x931 into powerdown mode unless the USB suspend signal is detected on the USB lines GSUS 1 Otherwise the device will not be able to wake up from powerdown mode by a resume signal sent through the USB lines See USB Power Cont
409. owever it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external RAM 14 4 USB POWER CONTROL The 8x931 supports USB power control through firmware including global suspend resume and remote wake up For flow charts of these operations see Figure 14 3 on page 14 11 14 4 4 Global Suspend Mode When a global suspend is detected by the 8x931 the global suspend bit GSUS in is set and the global suspend resume interrupt is generated Global suspend is defined as bus inactivity for more than 3 ms on the USB root port A device that is already in suspend mode will not change state Hardware does not invoke any particular power saving mode on detection of a global sus pend You must implement power control through firmware within the global suspend resume ISR NOTE Firmware must set the PD bit PCON 1 in Figure 14 1 on page 14 3 For global suspend on a bus powered device firmware must put the 8x931 into powerdown mode to meet the USB limit of 500 uA For self powered devices there is no hard requirement to put the 8x931 into powerdown mode To reduce power consumption idle mode and low clock mode can be used instead 14 7 8x931AA 8x931HA USER S MANUAL intel 14 4 1 1 Powerdown Suspend Mode The powerdown mode places the 8x931 in a very low power state P
410. pe Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low Figure 10 6 TCON Timer Counter Control Register 10 8 intel TIMER COUNTERS 10 4 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as 13 bit timer which is set up as an 8 bit timer register with a modulo 32 prescalar implemented with the lower five bits of the TL1 register Figure 10 2 The upper three bits of the TL1 register are ignored Prescalar overflow increments the TH1 reg ister 10 4 2 Mode 1 16 bit Timer Mode 1 configures timer 1 as a 16 bit timer with TH1 and TL1 connected in cascade Figure 10 2 The selected input increments TL1 10 4 3 Mode 2 8 bit Timer with Auto reload Mode 2 configures timer 1 as an 8 bit timer TL1 register with automatic reload from the TH1 register on overflow Figure 10 3 Overflow from TL1 sets overflow flag TF1 in the TCON reg ister and reloads TL1 with the contents of TH1 which is preset by firmware The reload leaves TH1 unchanged See Auto reload Setup Example on page 10 9 10 4 4 Mode 3 Halt Placing timer 1 in mode 3 causes it to halt and hold its count This can be used to halt timer 1 when the run control bit is not available 1 when timer 0 is in mode 3 See the final para graph of Timer 1 on page 10 6 10 5 TIMER 0 1 APPLICATIONS Timer 0 and timer 1 are general pur
411. peed or low speed device and whether the USB packet is a full speed or low speed packet Low speed packets are identified by a PREamble token Connections are made by the repeater using asyn chronous control logic in order to meet the USB signal propagation requirements 7 1 2 1 Connectivity to Downstream Ports Attached With Full speed Devices Downstream connectivity is established upon detection of a start of packet SOP transmitted on the root or upstream port by the USB host As shown in Figure 7 4 the connection is made from the root port port 0 to all enabled downstream ports attached with full speed devices ports 2 and 3 in this case Connectivity is not established to any enabled ports attached with low speed devices Upon detection of the end of packet EOP the repeater terminates the connectivity re verting to the idle state as shown in Figure 7 4 Upstream connectivity is established upon detection of a SOP transmitted on any enabled down stream port The connection is only made between a single downstream port and the root port by the repeater as shown in upstream connectivity in Figure 7 4 The USB protocol does not allow packets to be transmitted by more than one downstream port simultaneously but in an error sce nario where this happens the repeater would choose only one downstream port to connect up stream Once again upon detection of an EOP the connectivity is terminated 7 6 intel USB HUB 7 1 2 2 Connec
412. pend Resume Program with without Remote Wake up 14 11 8x931AA 8x931HA USER S MANUAL In continued continued GRSM bit 0 t Software sets RWU bit Global Resume already applied by host f RSM GSUS cleared by Software clears GRS hardware No need to send Remote Wake up to host Hardware clears GSUS bit RWU will clear automatically when RESUME signaling is done Software enables external peripherals RETI from suspend ISR Check to see if host has driven a resume onto the bus before function drives resume onto bus Figure 14 4 Suspend Resume Program with without Remote Wake up Continued 14 12 intel SPECIAL OPERATING MODES 14 5 LOW CLOCK MODE Low clock mode is the default operation mode for the 8x931 upon reset After reset the CPU and peripherals excluding the USB module default to a 3 MHz clock rate The USB module always runs at full speed Low clock mode ensures that the drawn by the 8x931 while in the unenu merated state following chip reset is less than one unit load 100 mA After USB enumeration and given that the request for more than one unit load of I is granted firmware can clear the LC bit in PCON to clock the CPU and on chip peripherals at the normal rate 14 5 1 Entering Low clock Mode Low clock mode can be invoked through firmware anytime the device is unconfigured by the host PC To invoke low clock mode set the LC bit in the PCON
413. perations use P3 4 and P3 5 as A14 and A15 P3 3 to ground For P3 6 and P3 7 see Table 16 2 and Figure 16 1 ALE l Address Latch Enable For verify operations connect this pin to Voc EA External Enable For verify operations connect this pin to Vec PSEN Program Store Enable For verify operations connect this pin to Vas RST Reset For verify operations connect this pin to Vec 16 3 1 Verify Modes Table 16 2 lists the verify modes and provides details about the setup The encryption array lock bits and signature bytes reside in nonvolatile memory outside the program and data memory ad dress spaces 16 3 2 General Setup Figure 16 1 shows the general setup for verifying nonvolatile memory on the 83931 The control ler must be running with an oscillator frequency of 4 MHz to 6 MHz Set up the controller as shown in Table 16 2 to verify on chip program memory signature bytes and lockbits Data ap pears on port 0 Connect RST ALE and EA s to V oc and PSEN to ground 16 2 intel VERIFYING NONVOLATILE MEMORY Table 16 2 Verify Modes Verify Modes RST PSEN EA ALE P3 7 3 P2 7 0 P1 7 0 Verify On chip Program Memory 1 0 1 1 11AA0 00AAAAAA AAAAAAAA Verify Signature Bytes 1 0 1 1 00 0 00 AAAAAAAA Verify Lock bit 1 0 1 1 10 0 00 ead gory 5V Address 16 Bits P2 0 P2 5 P3 4 P3 5 XTAL2 4 MHz too Co 6 MHz Control Signals see Tab
414. point 0 is always a control endpoint C 9 8x931AA 8x931HA USER S MANUAL EPINDEX Endpoint Index Register This register identifies the endpoint pair Its contents select the transmit and receive FIFO pair and serve as an index to endpoint specific SFRs 7 Address Reset State F1H 1xxx xx00B 0 HORF EPINX1 EPINXO Bit Bit gt Function Number Mnemonic uneto 7 HORF Hub Function Bit 1 Hub Selects USB hub FIFOs and SFRs 0 Function Selects USB function FIFOs and SFRs Oxxx xx10 Function Endpoint 2 6 2 Reserved Write zeros to these bits 1 0 EPINX1 0 Endpoint Index EPINDEX EPINDEX Oxxx xx00 Function Endpoint 0 1xxx xx00 Hub Endpoint 0 Oxxx xx01 Function Endpoint 1 1xxx xx01 Hub Endpoint 1 The EPINDEX register identifies the endpoint pair and selects the associated transmit and receive FIFO pair The value in this register plus SFR addresses select the associated bank of endpoint indexed SFRs TXDAT TXCON TXFLG TXCNTL RXDAT RXCON RXFLG RXCNTL EPCON TXSTAT and RXSTAT intel REGISTERS FADDR Address 8FH Reset State 0000 0000B Function Address Register This SFR holds the address for the USB function During bus enumeration itis written with a unique value assigned by the host 7 0 ce A6 0 Bit Bit Number Mnemonic Euneon 7 Reserved Write a zero to this bit 6 0 7 bit Programm
415. point status and configuration hub port control hub suspend and resume and hub power control Chapter 8 USB Programming Models describes the programming models of the 8x931 USB function interface This chapter provides flow charts of suggested firmware routines for us ing the transmit and receive FIFOs to perform data transfers between the host PC and the embed ded function and describes how the firmware interacts with the USB module hardware 1 1 8x931AA 8x931HA USER S MANUAL intel Chapter 9 Input Output Ports describes the four 8 bit I O ports ports 0 3 and discusses their configuration for general purpose I O This chapter also discusses external memory access es ports 0 2 and alternative special functions Chapter 10 Timer Counters describes the three on chip timer counters and discusses their application Chapter 11 Serial I O Port describes the full duplex serial I O and explains how to pro gram it to communicate with external peripherals This chapter also discusses baud rate genera tion framing error detection multiprocessor communications and automatic address recognition Chapter 12 Keyboard Control describes the 8x931 keyboard control interface including the keyboard scan output lines the keyboard scan input lines and the LED drivers Chapter 13 Minimum Hardware Setup describes the basic requirements for operating the 8x931 in a system It also discusses on chip a
416. point until this bit is cleared This prevents a prior ongoing firmware read from corrupting the read pointer after the new data has been written into the receive FIFO This bit is only used for control endpoints NOTE Make sure the EDOVW bit is cleared prior to reading the contents of the FIFO 3 RXSOVW Receive Data Sequence Overwrite Bit t Function Write a 1 to this bit to allow the value of the RXSEQ bit to be overwritten Writing a 0 to this bit has no effect on RXSEQ This bit always returns 0 when read ttt 2 RXVOID Receive Void Condition read only This bit is set when no valid data is received in response to a SETUP or OUT token due to one of the following conditions 1 The receive FIFO is still locked 2 The EPCON register s RXSTL bit is set This bit is set and cleared by hardware For non isochronous transactions this bit is updated by hardware at the end of the transaction in response to a valid OUT token For isochronous transactions it is not updated until the next SOF Under normal operation this bit should not be modified by the user For additional information on the operation of these bits see Appendix D Data Flow Model t The SIE will handle all sequence bit tracking This bit should be used only when initializing a new configuration or interface Figure 6 5 RXSTAT Receive FIFO Status Register Continued intel USB FUNCTION RXSTAT Continued
417. pose timers that can be used in a variety of ways The timer applications presented in this section are intended to demonstrate timer setup and do not repre sent the only arrangement nor necessarily the best arrangement for a given task These examples employ timer 0 but timer 1 can be set up in the same manner using the appropriate registers 10 5 1 Auto reload Setup Example Timer 0 can be configured as an eight bit timer TLO with automatic reload as follows 1 Program the four low order bits of the TMOD register Figure 10 5 to specify mode 2 for timer 0 C TO 0 to select 6 as the timer input and GATEO 0 to select TRO as the timer run control 2 Enter an eight bit initial value no in timer register TLO so that the timer overflows after the desired number of peripheral cycles 3 Enter an eight bit reload value ng in register THO This can be the same as no or different depending on the application 4 Set the TRO bit in the TCON register Figure 10 6 to start the timer Timer overflow occurs after FFH 1 ng peripheral cycles setting the TFO flag and loading n into TLO from THO When the interrupt is serviced hardware clears TFO 10 9 8x931AA 8x931HA USER S MANUAL intel 5 The timer continues to overflow and generate interrupt requests every FFH 1 ng peripheral cycles 6 To halt the timer clear the TRO bit 10 5 2 Pulse Width Measurements For timer 0 and timer 1 setting GATEx and TRx al
418. pt source is disabled and cannot cause an interrupt even though the interrupt bit s value is still reflected in the FIFLG register intel REGISTERS FIFLG Address COH Reset State xx00 0000B Function Interrupt Flag Register Contains the USB function s transmit and receive done interrupt flags for non isochronous endpoints 7 0 FRXD2 FTXD2 FRXD1 FTXD1 FRXDO FTXDO Bit Bit Number Mnemonic 7 6 Reserved EN CREE 5 FRXD2 Function Receive Done Flag Endpoint 2 4 Function Transmit Done Flag Endpoint 2 3 2 Function FRXD1 Function Receive Done Flag Endpoint 1 FTXD1 Function Transmit Done Flag Endpoint 1 1 FRXDO Function Receive Done Flag Endpoint 0 0 FTXDO Function Transmit Done Flag Endpoint 0 NOTES 1 For all bits in the Interrupt Flag Register a 1 indicates that an interrupt is actively pending a 0 indicates that the interrupt is not active The interrupt status is shown regardless of the state of the corresponding interrupt enable bit in the FIE 2 Bits are set only by hardware and clearable in firmware Firmware can also set the bits for test purposes allowing the interrupt to be generated in firmware This SFR is bit addressable 3 A set bit indicates either Valid data waiting to be serviced in the RX FIFO for the indicated endpoint and that the data was received without error and has been acknowledged or Data was received with a Receive Data Error requiring
419. puts set the IE1 0 interrupt flags in P3 3 2 the TCON register TCON bits IT1 0 select the triggering method IT1 0 1 selects edge triggered high to low IT1 0 0 selects level triggered active low INT1 0 also serves as external run control for timer 1 0 when selected by TCON bits GATE1 0 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as a P3 5 4 counter a falling edge on the T1 0 pin increments the count 10 2 intel TIMER COUNTERS FcLK Interrupt Request THx TLx Overflow 8 Bits 1 8 Bits Tx x 0 1 or2 TRx A5197 01 Figure 10 1 Basic Logic of the Timer Counters Table 10 2 Timer Counter and Watchdog Timer SFRs Mnemonic Description Address TLO Timer 0 Timer Registers Used separately as 8 bit counters or in cascade 8AH THO as a 16 bit counter Counts an internal clock signal with frequency Fc 6 8CH timer operation or an external input event counter operation TL1 Timer 1 Timer Registers Used separately as 8 bit counters or in cascade 8BH TH1 as a 16 bit counter Counts an internal clock signal with frequency 6 6 8DH timer operation or an external input event counter operation TL2 Timer 2 Timer Registers TL2 and TH2 connect in cascade to provide a CCH TH2 16 bit counter Counts an internal clock signal with frequency F 6 timer CDH operation or an external input event counter operation TCON Timer 0 1 Control
420. r 7 21 8x931AA 8x931HA USER S MANUAL intel HPSC Continued Address D5H Indexed by HPINDEX Reset State xxx0 0000B Hub Port Status Change Register This register indicates a change in status for a port including over current reset suspend low speed device enable and connect status 7 0 rstsc PSSC PESC PCSC Bit Bit _ Function Number Mnemonic Basie 1 PESC Port Enable Disable Status Change read clear only This bit s status does not change due to USB requests This bit is cleared by firmware via the USB host request ClearPortFeature with a C PORT ENABLE feature selector 1 indicates port enabled disabled status change 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware due to hardware events only this bit indicates the port was disabled due to babble physical disconnects or overcurrent Port 1 This bit is set by hardware at the EOF2 point near the end of frame due to hardware events only e g the port was disabled due to babble 0 PCSC Port Connect Status Change read clear only This bit is cleared by firmware via a USB host request ClearPortFeature with C PORT CONNECTION feature selector 1 indicates connect status change 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware at the EOF2 point near the end of a frame due to hardware connects and disconnects Port 1 This bit is set by hardware at t
421. r Mnemonic Function 7 5 Reserved Write zeros to these bits 4 0 BC4 0 Receive Byte Count Five bit ring buffer Stores receive byte count Not implemented for hub endpoint 1 C 38 intel REGISTERS RXCON Address E4H Endpoint indexed Reset State 0xx0 0100B Receive FIFO Control Register Controls the receive FIFO specified by EPINDEX 7 0 RXCLR RXFFRC RXISO ARM ADVWM REVWP Bit Bit Number Mnemonic Function 7 RXCLR Clear the Receive FIFO Set this bit to flush the entire receive FIFO All flags in RXFLG revert to their reset states RXEMP is set all other flags clear The ARM RXISO and RXWS bits in this register and the RXSEQ bit in the RXSTAT register are not affected by this operation Hardware clears this bit when the flush operation is completed 6 5 Reserved Values read from this bit are indeterminate Write zero to this bit 4 RXFFRC FIFO Read Complete Set this bit to release the receive FIFO when a data set read is complete Setting this bit clears the RXFIF bit in the RXFLG register corresponding to the data set that was just read Hardware clears this bit after the RXFIF bit is cleared All data from this data set must have been read NOTE FIFO Read Complete only works if STOVW and EDOVW are cleared 3 Isochronous Data Type Set this bit to indicate that the receive FIFO is programmed to receive isochronous dat
422. r Receive FIFO Management RXISO ARM RXERR RXACK RXCON 3 RXCON 2 RXSTAT 1 RXSTAT 0 Action at Engel Transfer Cycle X X 0 0 No operation X 0 0 1 Write marker write pointer and RXFIF bits remain unchanged Managed by firmware X 0 1 0 Write marker write pointer and RXFIF bits remain unchanged Managed by firmware 0 1 0 1 Write marker advanced automatically The RXFIF bit for the corresponding data set is set 0 1 1 0 Write pointer reversed automatically The RXFIF bit for the corresponding data set is cleared 1 1 X X Write marker advanced automatically If data was written to the receive FIFO the RXFIF bit for the corresponding data set is set NOTE For normal operation set the ARM bit in RXCON hardware will automatically control the write pointer and write marker and track the RXFIF bits CAUTION Do not read RXCNTL to determine if data is present in the receive FIFO Always read the FIF bits in the RXFLG register RXCNTL contains random data during a receive operation A read attempt to RXCNTL during the time the receive FIFO is empty causes the RXURF flag in RXFLG to be set Always read the FIF bits to determine if data is present in the receive FIFO The RXFLG FIF bits are updated after RXCNTL is written at the end of the receive operation 6 28 intel USB FUNCTION RXCON Address E4H Endpoint indexed Reset State 0xx0 0100B Receive FIFO Control Regi
423. r USB_RST_FLG Initialize USB related SFRs Flush USB FIFOs Continue with Main Routine A5206 01 5 20 Figure 5 9 USB Reset Separation Operating Model intel INTERRUPT SYSTEM 5 2 9 2 USB Reset Hardware Operations When the host initiates a USB reset signal the following series of events is performed by the 8x931 hardware See Figure 5 9 1 Upon detecting a USB reset signal the 8x931 hardware resets all the USB blocks 1 the FIFOs the SIU the SIE and the USB transceiver As aresult of this process all USB related SFRs are reset to their default reset states This includes EPINDEX EPCON SOFL SOFH FIE FIFLG FADDR TXSTAT TXDAT TXCON TXFLG TXCNTL TXCNTH RXSTAT RXDAT RXCON RXFLG RXCNTL RXCNTH and PCONI Note that PCONI is only partially reset the URDIS and URST bits retain their original values Because of this hardware reset any USB related operations e g MOV TXDAT A will not provide valid data 2 The 8x931 sets the PCONI URST bit to indicate a USB reset to the ISR 3 Ifthe ESR bit in IENI is set the 8x931 generates a USB reset interrupt which causes branch to the interrupt service routine whose vector is located at FF 0053H This ISR services both the USB reset interrupt and the global suspend resume interrupt 5 2 9 3 USB Reset ISR Because the USB reset interrupt shares an interrupt vector with the USB global suspend resume interrupt the interrupt service routine
424. r if all of the power enable bits in HPPWR are cleared then the UPWEN signal will be deasserted to a 1 Table 7 7 describes the state of the UPWEN signal for all conditions of the HPPWR5 2 signals and the OVRI pin Port power enable bits in the HPPWR SFR Figure 7 14 on page 7 28 are set via the SetPortFeature PORT POWER request from the USB host They are cleared via the ClearPortFeature PORT POWER request or by hardware upon detection of an overcurrent con dition 7 29 8x931AA 8x931HA USER S MANUAL Table 7 7 UPWEN Pin State Truth Table HPPWR5 HPPWR4 HPPWR3 HPPWR2 OVRI UPWEN 0 disabled 0 disabled 0 disabled 0 disabled 1 disabled 1 disabled X X X X X 1 X 1 X 1 X X X X X Since a single power enable output is used for all downstream ports the value of the correspond ing HPPWR bit does not necessarily reflect the actual state of the port power since all HPPWR bits must be disabled for power to be disabled Similarly 1 bit in the HPPWR SFR might not reflect that power is actually enabled to any devices in the event of an overcurrent condition Note that the power enable signal for the internal port HPPWR1 does not affect the state of the UPWEN pin Also note that bus powered devices must use the UPWEN signal to switch pow er to downstream ports however port power switching for self powered devices is optional NOTE Before the UPWEN pin can be enab
425. ransmission is completed the read marker can be advanced to the position of the read pointer to set up for reading the next data set When a bad transmission is completed the read pointer can be reversed to the position of the read marker to enable the function interface to re read the last data set for retransmission The read marker advance and read pointer reversal can be accomplished two ways explicitly by firmware or automatically by hardware as specified by bits in the transmit FIFO control register TXCON 6 3 1 Transmit FIFO Registers There are five registers directly involved in the operation of the transmit FIFOs TXDAT the transmit FIFO data register TXCNTL the transmit FIFO byte count register TXCON the transmit FIFO control register TXFLG the transmit FIFO flag register These registers are endpoint indexed This means they are used as a set to control the operation of the transmit FIFO associated with the current endpoint as specified by the EPINDEX register Figures 6 8 through 6 11 beginning on page 6 16 describe the transmit FIFO registers and pro vide bit definitions 6 15 8x931AA 8x931HA USER S MANUAL intel 6 3 2 Transmit FIFO Data Register TXDAT Bytes are written to the transmit FIFO via TXDAT the transmit FIFO data register Figure 6 8 TXDAT Address F3H Endpoint indexed Reset State xxxxB USB Transmit FIFO Data Register Data to be transmitted by the FIFO specified by EPIN
426. rdown Mode Bit When set activates powerdown mode This bit should only be set if the GSUS bit is also set Cleared by hardware when an interrupt or reset occurs 0 Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL and PD are both set PD takes precedence C 34 intel REGISTERS PCON1 Address DFH Reset State x000B USB Power Control Register Facilitates the control and status relating to global suspend and resume USB reset separation and remote wake up of the 8x931 7 0 URDIS URST RWU GRSM GSUS Bit Bit Number Mnemonic Function 7 5 Reserved Write zeros to these bits 4 URDIS USB Reset Disable When cleared by firmware a chip reset occurs upon receiving of a USB reset signal This resets the MCS 51 microcontroller core USB blocks and all peripherals When set by firmware the core and peripherals will not reset when a USB reset signal is detected Upon detecting a USB reset signal the 8x931 resets all the USB blocks FIFOs FIU SIE and transceiver sets the URST bit and generates a USB reset interrupt refer to the description of URST 3 URST USB Reset Flag This flag will be set by hardware when a USB reset occurs regardless of whether the ESR bit in the IEN1 register is enabled or disabled The URST also serves as the interrupt bit ORed with GRSM and GSUS bits to generate an interrupt Should be cleared
427. rdware Firmware controls the peripherals via their special function registers SFRs The 8x931 has two peripherals the timer counter unit and the serial I O port 2 5 1 Timer Counters The timer counter unit has three programmable 16 bit timer counters They can be clocked by the divided down system clock or an external timebase timer operation or by external events counter operation They can be set up as 8 bit 13 bit or 16 bit timer counters You can program them for special applications such as capturing the time of an event on an external pin outputting a programmable clock signal on an external pin or generating a baud rate for the serial I O port Timer counter events generate interrupt requests 2 5 2 Serial I O Port The serial I O port provides one synchronous and three asynchronous communication modes The synchronous mode mode 0 is half duplex the serial port outputs a clock signal on one pin and transmits or receives data on another pin The asynchronous modes modes 1 3 are full duplex i e the port can send and receive simul taneously Mode 1 uses a serial frame of 10 bits a start bit 8 data bits and a stop bit The baud rate is generated by the overflow of timer 1 or timer 2 Modes 2 and 3 use a serial frame of 11 bits a start bit eight data bits a programmable ninth data bit and a stop bit The ninth bit can be used for parity checking or to specify that the frame contains an address and data In mode 2 you
428. re is a set or bank of these registers for each USB downstream port Port indexed SFRs are accessed by means of the SFR address and an index value The HPINDEX register contains the port num ber which serves as the index value See Hub Port Indexing Using HPINDEX on page 7 23 Individual SFRs are presented in alphabetical order in Appendix C Tables listing the SFRs by functional category are also given in Appendix C 3 5 intel Programming Considerations intel CHAPTER 4 PROGRAMMING CONSIDERATIONS The instruction set for the 8x931 supports the instruction set for the MCS 51 architecture This chapter describes the addressing modes and summarizes the instruction set which is divided into data instructions bit instructions and control instructions The program status word register is also described Appendix A Instruction Set Reference contains an opcode map and a detailed description of each instruction 4 1 THE MCS 51 INSTRUCTION SET All members of the MCS 51 family execute the same instruction set The MCS 51 instruction set is optimized for 8 bit control applications It provides a variety of fast addressing modes for ac cessing the internal RAM to facilitate byte operations on small data structures The instruction set provides extensive support for one bit variables as a separate data type allowing direct bit ma nipulation in control and logic systems that require Boolean processing An overview of the MCS
429. re command which should cause the firmware to clear the PCSC bit in the HPSC register This will indirectly clear the appropriate bit in TXDAT for hub endpoint 1 This moves the hub downstream port to the disabled state 9 The host sends a SetPortResetFeature request for the specified downstream port The host receives a response through hub endpoint status change endpoint The host issues a GetPortStatus command retrieving the contents of HPSTAT and HPSC to determine the change for the specified downstream port The host then issues a ClearPortResetFeature command causing firmware to clear the RSTSC bit in the HPSC register This moves the hub downstream port to the enabled state 10 At this point the downstream ports go through the function enumeration process beginning with the embedded function a Get descriptor The host requests and reads the device descriptor to determine such information as device class USB specification compliance level maximum packet size for endpoint 0 vendor id product id etc For detailed information on device descriptors see the Device Framework chapter in Universal Serial Bus Specification b Set address The host sends the function address in a data packet using function endpoint 0 Device firmware interprets the data and instructs the CPU to write the function address to FADDR c Get configuration The host requests and reads the device configuration descriptor to determine such information
430. re uncommitted and may be used as general purpose status flags Table 4 1 shows the effects of instructions on the PSW flags 4 1 8x931AA 8x931HA USER S MANUAL intel PSW Address S DOH Reset State 0000 0000B 0 CY AG FO RS1 RSO OV UD Function 7 Carry Flag The carry flag is set by an addition instruction ADD ADDC if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by logical bit bit move multiply decimal adjust and some rotate and shift instructions see Table 4 1 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 4 1 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 51 RSO Bank Address 0 0 0 00 07 0 1 1 O8H OFH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the m
431. reload Mode The auto reload mode configures timer 2 as a 16 bit timer or event counter with automatic reload The timer operates an as an up counter or as an up down counter as determined by the down counter enable bit DCEN At device reset DCEN is cleared so in the auto reload mode timer 2 defaults to operation as an up counter 10 6 2 1 Up Counter Operation When 0 timer 2 operates as an up counter Figure 10 8 The external enable bit EXEN2 in the T2CON register provides two options Figure 10 12 If EXEN2 0 timer 2 counts up to FFFFH and sets the TF2 overflow flag The overflow condition loads the 16 bit value in the re load capture registers RCAP2H RCAP2L into the timer registers TH2 TL2 The values in RCAP2H and RCAP2L are preset by firmware If EXEN2 1 the timer registers are reloaded by either a timer overflow or a high to low tran sition at external input T2EX This transition also sets the EXF2 bit in the T2CON register Either TF2 or EXF2 bit can generate a timer 2 interrupt request Overflow Interrupt Request EXEN2 A5202 01 Figure 10 8 Timer 2 Auto reload Mode DCEN 0 10 12 intel TIMER COUNTERS 10 6 3 Up Down Counter Operation When DCEN 1 timer 2 operates as an up down counter Figure 10 9 External pin T2EX con trols the direction of the count Table 10 1 on page 10 2 When T2EX is high timer 2 counts up The timer overflow occurs at FFFFH which sets
432. respectively with the second and third instruction bytes The destination may therefore be anywhere in the 64 Kbyte memory region where the next instruction is located Flags CY AC OV Example The label JMPADR is assigned to the instruction at program memory location 1234H After executing the instruction LJMP JMPADR at location 0123H the program counter contains 1234H Bytes 3 States 12 Cycles 2 Encoding 0000 0010 addr15 7 8 Operation LJMP A 34 PC lt addr 15 0 intel MOV lt dest gt lt src gt INSTRUCTION SET REFERENCE Function Move byte variable Description Copies the byte variable specified by the second operand into the location specified by the first operand The source byte is not affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Flags CY AC OV Example On chip RAM location 30H contains 40H on chip RAM location 40H contains 10H and input port 1 contains 11001010B 0CAH After executing the instruction sequence MOV RO 30H RO lt MOV A RO A lt 40H MOV R1 A R1 lt 40H MOV B R1 B lt 10H MOV R1 P1 RAM 40H lt 0CAH MOV P2 P1 P2 40CAH register 0 contains 30H the accumulator and register 1 contain 40H register B contains 10H and on chip RAM location 40H and output port 2 contain OCAH 11001010B Variations
433. rial Bus Specification s Electrical chap ter For electrical characteristics and data signal timing see the Bus Timing Electrical Charac teristics and Timing Diagram sections of the same chapter SFRs used to control and access USB hub functionality are listed in Table 7 1 Figure 7 2 shows the bits contained in the hub SFRs 7 2 a intel USB HUB Table 7 1 USB Hub SFRs Mnemonic Name Address Page HADDR Hub Address Register Used by the HIU to perform token 97H page 7 8 address decoding HIE Hub Interrupt Enable Register Contains the hub interrupt A1H page 5 15 enable bits HIFLG Hub Interrupt Flag Register Contains the hub interrupt E8H page 5 16 status flags HPCON Hub Port Control Enables disables resets suspends and CFH page 7 15 resumes the hub ports USB port indexed using HPINDEX HPINDEX Hub Port Index Register Provides port indexing into the D4H page 7 24 HPSC HPSTAT and HPCON registers HPPWR Hub Port Power Control Controls power to the 9AH page 7 28 downstream ports HPSC Hub Port Status Change Indicates a change in reset D5H page 7 21 suspend enable disable or connect status USB port indexed using HPINDEX HPSTAT Hub Port Status Provides Dp Dy low speed device D7H page 7 18 power reset suspend enable and disable status for the hub ports USB port indexed using HPINDEX HSTAT Hub Status and Configuration Used to exam
434. riority Select Highest IENO IPHO IPL Priority External 0 i gt 2 FLO Interrupt INTO TCON 0 liz Timer External 0 1 yr IV _ px ry a Ly A A wt E eR er Url ae E Timer 1 Serial Port Receive gt SCON O Transmit SCON 1 Timer 2 TF2 T2CON 7 g T2Ex 3 T2CON 6 EN 8 0 1 1 IPH1 IPL1 o S SOFIE SOFH 6 SOFH 5 USB Hub E Receive MEAE 5 HIFLG Transmit HTXDO HTXEO USB Function Receive FRXDx FIFLG FRXIEx Transmit FTXDx FTXIEx IGRSM E SB 1 Suspend GSUS PCON1 0 USB Reset URST URDIS Separation PCON1 3 PCON1 4 Keyboard Scan INT2 IT KBCON 4 2 KBCON 5 KSI7 0 KBCON 7 Lowest Priority Interrupt A5538 01 Figure 5 1 Interrupt Control System 5 3 8x931AA 8x931HA USER S MANUAL intel SFRs used by the interrupt system are listed in Table 5 2 Figure 5 2 shows the bits contained in the interrupt SFRs Table 5 2 Interrupt System Special Function Registers Mnemonic Description Address Page FIE USB Function Interrupt Enable Register Enables and A2H page 5 9 disables the receive and transmit done interrupts for the function endpoints FIFLG USB Function Interrupt Flag Register Contains the USB COH page 5 11 function s transmit and receive done interrupt flags for non isochronous endpoints HIE Hub Interrupt Enable Register Contains the hub inte
435. rmal timer operation GATEO 0 setting TRO allows TLO to be incremented by the se lected input Setting GATEO and TRO allows external pin INTO to control timer operation This setup can be used to make pulse width measurements See Pulse Width Measurements on page 10 10 Timer 0 overflow count rolls over from all 1s to all Os sets the TFO flag generating an interrupt request 10 3 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as a 13 bit timer which is set up as an 8 bit timer THO register with a modulo 32 prescalar implemented with the lower five bits of the TLO register Figure 10 2 The upper three bits of the TLO register are indeterminate and should be ignored Prescalar overflow increments the THO register 10 3 2 Mode 1 16 bit Timer Mode 1 configures timer 0 as a 16 bit timer with THO and TLO connected in cascade Figure 10 2 The selected input increments TLO Interrupt Request THx i TLx Overflow 8 Bits 8 Bits TRX Mode 0 13 bit Timer Counter Mode 1 16 bit Timer Counter GATEx x 0or1 INTx A5198 01 Figure 10 2 Timer 0 1 in Mode 0 and Mode 1 10 4 intel TIMER COUNTERS 10 3 3 Mode 2 8 bit Timer With Auto reload Mode 2 configures timer 0 as an 8 bit timer TLO register that automatically reloads from the THO register Figure 10 3 TLO overflow sets the timer overflow flag in the TCON register and reloads TLO with the contents of THO which
436. rms 13 4 intel MINIMUM HARDWARE SETUP 13 4 RESET A device reset initializes the 8x931 and vectors the CPU to address OOOOH A reset is a means of exiting the idle and powerdown modes or recovering from firmware malfunctions and could be a USB reset initiated by the host or upstream hub NOTE A reset is required after applying power To achieve a valid reset must be within its normal operating range see device data sheet and the reset signal must be maintained for at least two machine cycles 24 oscillator periods af ter the oscillator has stabilized Device reset is initiated in two ways externally by asserting the RST pin over the bus by a USB initiated reset These reset mechanisms are ORed to create a single reset signal for the 8x931 The power off flag POF in the PCON register indicates whether a reset is a warm start or a cold start A cold start reset POF 1 is a reset that occurs after power has been off or Vec has fallen below 3 V so the contents of volatile memory are indeterminate POF is set by hardware when Voc rises from less than 3 V to its normal operating level See Power Off Flag on page 14 1 A warm start reset POF 0 is a reset that occurs while the chip is at operating voltage for exam ple an external reset used to terminate the idle or powerdown modes 13 4 1 Externally initiated Resets To reset the 8x931 hold the RST pin at a logic high for at least two machine cycles 24 osci
437. rol on page 14 7 14 4 1 3 Exiting Powerdown Suspend Mode CAUTION If Vcc was reduced during the powerdown mode do not exit powerdown until V is restored to the normal operating level There are two ways other than USB signaling to exit the powerdown mode 1 Generate an enabled external interrupt including the keyboard scan interrupt The interrupt signal must be held active long enough for the oscillator to restart and stabilize normally less than 10 ms Hardware clears the PD bit in the PCON register which starts the oscillator and restores the clocks to the CPU and peripherals Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated powerdown mode 14 8 intel SPECIAL OPERATING MODES To enable an external interrupt set the IENO register and or EX1 bit s The external interrupt used to exit powerdown mode must be configured as level sensitive and must be assigned the highest priority Holding the interrupt pin INTO INT 1 or the keyboard scan interrupt INT2 low restarts the oscillator and bringing the pin high completes the exit The duration of the interrupt signal must be long enough to allow the oscillator to stabilize normally less than 10 ms 2 Generate a reset A logic high on the RST pin clears the PD bit in the PCON register directly and asynchrono
438. ror and has been acknowledged Data was received with a receive data error and requires firmware intervention to be cleared This could be either a transmission error or a FIFO related error You must check for these conditions and respond accordingly in the interrupt service routine ISR The USB function generates a transmit done interrupt for an endpoint x x 2 0 2 by setting the FTXDx bit in the FIFLG register Figure 5 4 Only a non isochronous transfer can cause a trans mit done interrupt Transmit done interrupts are generated only when all of the following are true A valid IN token is received to function endpoint x Endpoint is enabled for transmission TXEPEN 1 Transmit is enabled TXIE 1 and STALL is disabled TXSTL 0 A data packet byte count has been loaded in the transmit FIFO and was transmitted in response to the IN token regardless of whether or not a FIFO error occurs An ACK is received from the host or there was a time out in the SIE Because the FTXDx bit is set and a transmit done interrupt is generated regardless of transmis sion errors this condition means either The transmit data has been transmitted and the host has sent an acknowledgment to indicate that is was successfully received Atransmit data error occurred during transmission of the data packet which requires servicing by firmware to be cleared You must check for these conditions and respond ac
439. rough firmware returns to the normal clock frequency Fos 2 For counter operation C Tx 1 the timer register counts the negative transitions on the Tx ex ternal input pin The external input is sampled during every S5P2 state Clock and Reset Unit on page 2 9 describes the notation for the states in a peripheral cycle When the sample is high in one cycle and low in the next the counter is incremented The new count value appears in the register during the next S3P1 state after the transition was detected Since it takes two peripheral cycles to recognize a negative transition the maximum count rate 15 12 There are no restric tions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full peripheral cycle Table 10 1 External Signals Signal Name Alternate Type Description Function T2 lO Timer 2 Clock Input Output This signal is the external clock input P1 0 for the timer 2 capture mode and it is the timer 2 clock output for the clock out mode T2EX Timer 2 External Input In timer 2 capture mode a falling edge 1 1 initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction high up low down INT 1 0 External Interrupts 1 0 These in
440. rrupt A1H page 5 15 enable bits HIFLG Hub Interrupt Flag Register Contains the hub interrupt status E8H page 5 16 flags IENO Interrupt Enable Register 0 Enables individual programmable A8H page 5 24 interrupts Also provides a global enable for the programmable interrupts The reset value for this register is zero interrupts disabled IEN1 Interrupt Enable Register1 Enables individual programmable B1H page 5 25 interrupts for the USB interrupts The reset value of this register is zero interrupts disabled IPLO Interrupt Priority Low Register 0 Establishes relative priority B8H page 5 28 for programmable interrupts Used in conjunction with IPHO IPHO Interrupt Priority High Register 0 Establishes relative priority B7H page 5 27 for programmable interrupts Used in conjunction with IPLO IPL 1 Interrupt Priority Low Register 1 Establishes relative priority B2H page 5 30 for programmable interrupts Used in conjunction with IPH1 IPH1 Interrupt Priority High Register 1 Establishes relative priority B3H page 5 29 for programmable interrupts Used in conjunction with IPL1 KBCON Keyboard Control Register This register controls the F8H page 12 1 keyboard scan input and output activity enables and configures the keyboard scan interrupt and drives the keyboard LEDs PCON1 USB Power Control Contains USB global suspend and DFH page 14 4 resume interrupt bits Also contains the USB reset separation enable and
441. rry Move Bit from Carry lt src gt lt dest gt CLR bit SETB bit CPL bit ANL CY bit ANL CY bit ORL CY bit ORL CY bit MOV CY bit MOV bit CY bit 0 bit 1 bit Obit CY A bit CY CY Obit CY V bit CY V Obit CY lt bit bit CY Machine Bytes States Cycles CY Clear carry CLR bit Clear dir bit CY Set carry SETB bit Set dir bit 2 CY Complement carry 1 CPL bit Complement dir bit ANL CY bit AND dir bit to carry ANL CY bit AND complemented dir bit to carry CY bit CY bit OR dir bit to carry CY bit OR complemented dir bit to carry Move dir bit to carry 2 2 2 2 2 bit CY Move carry to dir bit N N A 7 8x931AA 8x931HA USER S MANUAL A 8 Table A 14 Summary of Control Instructions Machine Mnemonic lt dest gt lt src gt Notes Bytes States Cycles ACALL Absolute subroutine call LCALL Long subroutine call 2 RET Return from subroutine 2 RETI Return from interrupt 2 AJMP addr11 Absolute jump 2 LUMP addr16 Long jump 2 SJMP rel Short jump relative addr 2 JMP A DPTR Jump indir relative to the DPTR 1 2 JC rel Jump if carry is set 2 2 JNC Jump if carry not set 2 12 2 JB Jump if dir bit is set 3 12 2 JNB bit rel Jump if dir bit is not set 3 12 2 JBC bit rel Jump if dir bit is
442. rsal Serial Bus Specification which provides a detailed description of the USB system In the language of the USB specification the 8 931 is a USB device USB device can serve as a function by providing an interface for a PC peripheral and it can serve as a hub by pro viding USB ports for additional PC peripherals The 8x931AA is a hubless USB peripheral controller which serves as a USB function The 8x931HA serves as both a USB function and as a hub it supports one embedded function and provides four external downstream ports Figure 2 1 depicts the 8x931 in an example USB sys tem Host PC USB Hub 8x931Hx Keyboard O LI O LI em USB Function 8x930Ax 8x931Ax 8x930Ax 8x931Ax Digital Camera Speakers Telephone USB Function USB Function USB Function USB Function A4519 01 Figure 2 1 8x931 in a USB System T 8x931AA 8x931HA USER S MANUAL intel Data Program Address lt Address Register Register Program Upstream Counter Port USB Module Stack Pointer Mere Downstream Ports Data Pointer A4518 01 Figure 2 2 Functional Block Diagram of the 8x931 2 4 PRODUCT OVERVIEW The 8x931 employs the architecture of the MCS 51 microcontroller family Specifically it is derived from the 8xC51Fx core which is optimized for control operations with extensive boolean processing capabilities The 8x931 executes the standard instruction s
443. rt 0 Register Write data to be driven onto the port 0 pins to these bits P1 Address 90H Reset State 1111 1111B Port 1 P1 is the SFR that contains data to be driven out from the port 1 pins Read modify write instructions that read port 1 read this register Other instructions that read port 1 read the port 1 pins 7 0 P1 Contents Bit Bit Number Mnemonic Function 7 0 P1 7 0 Port 1 Register Write data to be driven onto the port 1 pins to these bits C 32 intel REGISTERS P2 Address AOH Reset State 1111 1111B Port 2 P2 is the SFR that contains data to be driven out from the port 2 pins Read modify write instructions that read port 2 read this register Other instructions that read port 2 read the port 2 pins 7 0 P2 Contents Bit Bit Number Mnemonic Function 7 0 P2 7 0 Port 2 Register Write data to be driven onto the port 2 pins to these bits P3 Address BOH Reset State 1111 1111B Port 3 P3 is the SFR that contains data to be driven out from the port 3 pins Read modify write instructions that read port 3 read this register Other instructions that read port 3 read the port 3 pins 7 0 P3 Contents Bit Number Bit Mnemonic Function 7 0 P3 7 0 Port 3 Register Write data to be driven onto the port 3 pins to these bits C 33 8x931AA 8x931HA USER S MANUAL intel PCON Address 87H R
444. rtStatus call by returning four bytes to the host using the flowchart procedure shown in Figure 8 12 The four bytes are arranged into a two byte port status field and a two byte port change field containing the contents of the HPSTAT and HPSC SFRs respective ly Figure 8 13 shows the relationship between the four bytes returned by firmware and the con tents of the HPSTAT and HPSC registers Start GetPortStatus Request Write 80H to EPINDEX to access hub endpoint 0 s TX registers Write xxxB to HPINDEX xxx port number to access port s HP registers Transfer HPSTAT to TXDAT using two byte format Transfer HPSC to TXDAT using two byte format Put 04H in TXCNTL to indicate 4 bytes ready to transmit End A5208 01 Figure 8 12 GetPortStatus Request 8 25 8x931AA 8x931HA USER S MANUAL intel Transferring the contents of HPSTAT and HPSC into TXDAT requires additional code not shown in the flowchart The bits of HPSTAT must be converted into a two byte port status field as shown in Figure 8 13 and transmitted to the host LSB first The bits of HPSC must also be transmitted in a two byte format called the port change field The bit names are given in Figure 8 13 along with their position in the register shown below the bit name and their position in the transmitted two byte field shown above the bit names Firm ware must transmit the four bytes to the host in the byte order indicated
445. ruction for bits A 7 ORL instruction for bits A 7 Oscillator atstartup 13 7 ceramic resonator 13 3 during reset 13 5 on chip crystal 2 7 13 2 ONCE mode 14 13 powerdown mode 14 8 verifying nonvolatile memory 16 2 OV bit 4 2 C 39 Overflow See OV bit OVRI pin 7 29 Index 3 8x931AA 8x931HA USER S MANUAL P bit 4 2 C 39 PO 9 2 C 4 C 34 Pl 9 2 C 4 C 34 P2 9 2 C 4 C 34 P3 9 2 C 4 C 35 Page mode bus cycles See External bus cycles page mode PCON 11 7 14 3 14 4 14 7 C 3 C 36 C 37 idle mode 14 6 powerdown mode 14 8 14 9 reset 13 5 PCONI 5 4 14 7 C 3 Phase 1 and phase 2 2 8 Phone numbers customer support 1 7 Pin conditions 14 6 Pins unused inputs 13 2 POP instruction A 7 Port 0 9 2 structure 9 3 Port 1 9 2 structure 9 3 Port 2 9 2 structure 9 4 Port 3 9 2 structure 9 3 Ports at power on 13 7 exiting idle mode 14 7 exiting powerdown mode 14 8 verifying nonvolatile memory 16 3 Power supply 13 2 Powerdown mode 2 6 14 1 14 8 14 9 accidental entry 14 6 entering 14 8 exiting 13 5 14 8 external bus 15 2 PSEN caution 13 7 idle mode 14 6 PSW 4 2 A 9 C 39 PSW PSWI C 3 effects of instructions on flags 4 3 Pullups ports 1 2 3 9 6 Index 4 intel Pulse width measurements 10 10 PUSH instruction A 7 R RCAP2H RCAP2L 10 3 11 12 C 40 RD 9 1 Read modify write instructions 9 2 9 5 Register banks selection bits RS1 0 4 2
446. ruction set are as follows 4 1 2 1 DIRECT ADDRESSING In direct addressing the operand is specified by an 8 bit address field in the instruction Only in ternal Data RAM and SFRs can be directly addressed 4 1 2 2 INDIRECT ADDRESSING In indirect addressing the instruction specifies a register which contains the address of the oper and Both internal and external RAM can be indirectly addressed The address register for 8 bit addresses can be RO or R1 of the selected register bank or the Stack Pointer The address register for 16 bit addresses can only be the 16 bit data pointer register DPTR 4 1 2 3 REGISTER INSTRUCTIONS The register banks containing registers RO through R7 can be accessed by certain instructions which carry a 3 bit register specification within the opcode of the instruction Instructions that access the registers this way are code efficient since this mode eliminates an address byte When the instruction is executed one of the eight registers in the selected bank is accessed One of four banks is selected at execution time by the two bank select bits in the PSW 4 3 8x931AA 8x931HA USER S MANUAL intel 4 1 2 4 REGISTER SPECIFIC INSTRUCTIONS Some instructions are specific to a certain register For example some instructions always oper ate on the Accumulator or Data Pointer etc so no address byte is needed to point to it The op code itself does this Instructions that refer to the Accumulator as A
447. rupt pin held low or high for any five state time period guarantees detec tion Edge triggered external interrupts must hold the request pin low for at least seven state times This ensures edge recognition and sets interrupt request bit EXx The CPU clears EXx au tomatically during service routine fetch cycles for edge triggered interrupts Table 5 3 8x931AA HA Interrupt Control Matrix Interrupt Keyboard Serial Scan Timer 2 Port Timer 1 INT1 Timer 0 INTO INT2 Biramo IM TEND ET2 ES ETI EX1 ETO EX0 Register Bit Name in IEN1 Register Interrupt Priority Within Level 11 Low Priority 1 High Priority Bit Names in IPHO IPH1 7 IPHO 5 IPHO 4 IPHO 3 2 1 IPHO 0 IPLO IPL1 7 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Programmable for Negative edge Yes No No No Yes No Yes triggered or Level triggered Detect Interrupt Request TCON SCON TCON TCON Flag in TCON or IE2 TF2 RI IE1 TFO IEO KBCON Register EXF2 TI Interrupt Request Edge Edge Flag Cleared by No No No Yes Yes Yes Yes Hardware Level No Level No ISR Vector Address 003BH 002BH 0023H 001BH 0013H 000BH 0003H Additional interrupts specific to USB and USB hub operation appear in Table 5 11 5 6 intel INTERRUPT SYSTEM Table 5 4 8x931 USB Hub Interrupt Control Matrix Interrupt Name USB Global USB
448. rupt to be generated in firmware This SFR is bit addressable 3 Asetbit indicates either Valid data waiting to be serviced in the RX FIFO for the indicated endpoint and that the data was received without error and has been acknowledged or Data was received with a Receive Data Error requiring firmware intervention to be cleared Figure 5 4 FIFLG USB Function Interrupt Flag Register 5 2 0 USB Start of frame Interrupt The USB start of frame interrupt SOF is used to control the transfer of isochronous data The 8x931 frame timer attempts to synchronize with the host frame time automatically When the frame timer is locked to the USB frame time hardware sets the FTLOCK bit in SOFH Figure 5 5 To enable the SOF interrupt set the SOFIE bit in SOFH The 8x931 generates an SOF interrupt whenever a start of frame packet is received from the USB lines or whenever a start of frame packet should have been received 1 an artificial SOF The 8x931 generates an SOF interrupt by setting the ASOF bit in the SOFH SFR When an SOF in terrupt occurs the 8x931 loads the current value of the 11 bit frame number issued with an SOF token into the SOFH SOFL registers Figures 5 5 and 5 6 If an artificial SOF is generated the time stamp remains at its previous value leaving it up to the firmware for updating 8x931AA 8x931HA USER S MANUAL intel NOTE For the 8x931HA the start of frame interrupt shares an interrupt vector with the h
449. rvention Received 01 10 1 0 1 0 1 no None NAK Considered to be OUT token no no no chg a void with FIFO chg chg chg condition Will error already NAK until existing firmware clears condition Received 01 10 no no no no no no None ACK Last ACK OUT token chg chg chg chg chg chg corrupted so but data send again but sequence ignore the data mismatch Received 01 10 0 1 0 1 0 0 Set ACK Causes FIFO to SETUP receive reset token no interrupt automatically errors dual forcing new packet mode SETUP to be not received RXIE recommende or RXSTL has no d effect 2 RXSETUP will be set control endpoints only Received 01 10 1 0 0 0 0 0 Set Time out FIFO is reset SETUP receive automatically token but interrupt forcing new timed out SETUP to be waiting for received 2 data NOTES 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase 3 NOTE Dual packet mode is NOT recommended for control endpoints intel DATA FLOW MODEL Table D 4 Non isochronous Receive Data Flow in Dual packet Mode RXSPM 0 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event ut ERR ACK Void Setup m yid pes Response Comments Received 00 1 0 0 1 0 0 Set Time out Write po
450. ry Specific details of the 8x931AA are covered in Appendix E 8x931AA Design Considerations 8 6 1 Hub Status and Configuration USB communication with the USB hub function is performed via the standard and hub class spe cific USB requests These requests contro status management and configuration of the hub and its downstream ports Since the hub is part of a compound device it has an internal downstream port port 1 which is unique from the external downstream ports This is because port is phys ically connected to the embedded function and is powered on at all times Thus several USB re quests intended for internal downstream port 1 are handled differently from similar requests to the other downstream ports as shown in Table 7 6 on page 7 16 Table 8 1 is a summary of firmware actions required for standard USB requests sent to hub end point 0 Table 8 1 Firmware Actions for USB Requests Sent to Hub Feature Selector USB Request Firmware Action Required Type DEVICE_REMOTE Set the HRWUPE bit of the HSTAT SFR See Hub _WAKEUP Status on page 7 9 Stall the endpoint specified in the Setup PID See Hub Endpoint Control on page 7 11 SET_FEATURE Endpoint 0 specified ENDPOINT STALL 1 Load 80H into EPINDEX for hub endpoint 0 2 Set RXSTL and TXSTL bits of EPCON SFR Endpoint 1 specified Set EP1STL bit of HSTAT SFR DEVICE REMOTE Clear HRWUPE bit of HSTAT SFR See Hub Status and _WA
451. ry ad dress space special function register SFR space and the register file It also provides a map of the SFR space showing the location of the SFRs and their reset values and explains the mapping of the address spaces relative to the MCS 51 architecture into the address spaces of the 8x931 Chapter 4 Programming Considerations provides an overview of the instruction set It describes each instruction type control arithmetic logical etc and lists the instructions in tab ular form This chapter also discusses the addressing modes bit instructions and the program sta tus words Appendix A Instruction Set Reference provides a detailed description of each instruction Chapter 5 Interrupt System describes the 8x931 interrupt circuitry which provides ten maskable interrupts three external interrupts three timer interrupts a serial port interrupt and three USB interrupts This chapter also discusses the interrupt priority scheme interrupt enable interrupt processing and interrupt response time Chapter 6 USB Function describes the FIFOs and special function registers SFRs asso ciated with the USB function interface This chapter describes the operation of function interface on the 8x931 USB microcontrollers Chapter 7 USB Hub describes the operation of the Intel Universal Serial Bus USB on chip hub This chapter introduces on chip hub operation and includes information on bus enumer ation hub end
452. ry addresses When the highest on chip address is exceeded during execution pro gram code fetches automatically rollover from on chip memory to external memory With EA 1 and only on chip program code memory multi byte instructions and instructions that result in call returns or prefetches should be located a few bytes below the maximum address to avoid inadvertently exceeding the top address CAUTION Execution of program code located in the top few bytes of the on chip memory may cause prefetches from the next higher addresses i e external memory External memory fetches make use of port 0 and port 2 and may disrupt program execution if the program uses port 0 or port 2 for a different purpose 16 5 intel Instruction Set Reference APPENDIX A INSTRUCTION SET REFERENCE This appendix contains reference material for the 8x931 instruction set which is identical to in struction set for the MCS 51 architecture The appendix includes an opcode map a detailed de scription of each instruction and the following tables that summarize notation addressing instructions types instruction lengths and execution times Tables A 1 through 4 describe the notation used for the instruction operands Table 5 describes the notation used for control instruction destinations Table 6 on page A 3 contains the opcode map for the instruction set The following tables list the instructions giving length in bytes and execution t
453. s cause status change only at SOF Since overrun can only be caused by firmware TXOVF is updated immediately Check the TXOVF flag after writing to the transmit FIFO before writing to TXCNTL When set all transmissions are NAKed Figure 6 11 TXFLG Transmit FIFO Flag Register Continued 6 23 8x931AA 8x931HA USER S MANUAL intel 6 4 RECEIVE FIFOs The 8x931 has a receive FIFO for each function endpoint pair In this manual the term receive FIFO refers to the receive FIFO associated with the current endpoint pair specified by the EPIN DEX register 8x931 FIFOs are listed in Table 2 4 The receive FIFOs are circulating data buffers with the following features endpoint 1 supports up to two separate data sets of variable sizes abyte count register that accesses the number of bytes in the data sets flags to signal a full FIFO and an empty FIFO capability to re receive the last data set Figure 6 12 illustrates a receive FIFO A receive FIFO and its associated logic can manage up to two data sets data set 0 dsO and data set 1 ds1 The ability to have two data sets in the FIFO supports back to back receptions In many ways the receive FIFO is symmetrical to the transmit FIFO The FIU writes to the FIFO location specified by the write pointer which increments by one automatically following a write The write marker points to the first byte of data written to a data set and the read pointer points to the
454. s bit is hard wired to 4 Reserved Write a zero to this bit intel REGISTERS HPSC Address D5H Indexed by HPINDEX Reset State xxx0 0000B Hub Port Status Change Register This register indicates a change in status for a port including over current reset suspend low speed device enable and connect status 7 0 xs E RSTSC PSSC PESC PCSC Bit Bit Function Number Mnemonic 7 5 Reserved Write zeros to these bits 4 Reset Status Change read clear only This bit is cleared in firmware via the USB host request ClearPortFeature with a C_PORT_RESET feature selector 1 indicates reset of port complete 0 indicates no change Port x x 2 3 4 5 This bit is set by hardware approximately 10 msec after receipt of a port reset and enable command SetPortFeature with PORT_RESET feature selector Port 1 This bit is set by hardware at the EOF2 point near the end of a frame after completion of the hardware timed reset due to firmware execution of a port reset and enable command SetPortFeature with PORT_RESET feature selector 3 Reserved Write a zero to this bit 2 PSSC Port Suspend Status Change read clear only This bit is cleared by firmware upon a USB host request ClearPortFeature with C PORT SUSPEND feature selector 1 resume process complete 0 no change The resume process is initiated by firmware upon reception o
455. s of zero into transmit buffer and transmit to USB host These bits are reserved in the initial version of USB Endpoint Endpoint 0 specified Load transmit buffer with value of zero if endpoint 0 is not stalled No data can be returned if endpoint 0 is stalled since STALL will be transmitted instead Endpoint 1 specified Load value of EP1STL bit of HSTAT SFR into transmit buffer Figure 7 6 on page 7 9 SET_ADDRESS N A Read address value contained in request value field and store in HADDR SFR Figure 7 5 on page 7 8 after successful completion of control transaction status stage SET_DESCRIPTOR N A Optional request for hubs which is not supported 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage SET_INTERFACE N A Optional request for hubs which is not supported 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage SYNCH FRAME N A Optional request for hubs which is not supported 1 Load 80H into EPINDEX for hub endpoint 0 2 Set TXSTL bit of EPCON SFR so STALL is sent during status stage 8 18 intel USB PROGRAMMING MODELS Table 8 2 summarizes firmware action for hub class specific USB requests NOTE Upon receipt of a state related USB request i e SetPortFeature ClearPortFeature firmware must examine the HPSTAT SFR to determine the
456. s the lower eight address bits from DPL For both types of moves the data is multiplexed with the lower address bits on port 0 It is possible in some situations to mix the two MOVX types A large RAM array with its upper address lines driven by P2 can be addressed via the data pointer or with code to output upper address bits to P2 followed by a MOVX instruction using RO or R1 CY AC OV An external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM I O Timer is connected to port 0 Port provides control lines for the external RAM ports 1 and 2 are used for normal I O RO and R1 contain 12H and 34H Location 34H of the external RAM contains 56H After executing the instruction sequence MOVX A R1 MOVX R0 A the accumulator and external RAM location 12H contain 56H A 41 8x931AA 8x931HA USER S MANUAL intel Variations MOVX A DPTR Bytes 1 States 12 Cycles 2 Encoding 1110 0000 Operation MOVX lt DPTR MOVX A Ri Bytes 1 States 12 Cycles 2 Encoding 1110 001i Operation MOVX lt Ri MOVX DPTR A Bytes 1 States 12 Cycles 2 Encoding 1111 0000 Operation MOVX DPTR lt A MOVX Ri A Bytes 1 States 12 Cycles 2 Encoding 1111 001i Operation MOVX Ri lt A A 42 intel MUL AB Function Description Flags Example Bytes States Cycles Operation NOP Function D
457. s the port in a disconnected state A value of 0 turns the downstream port power off NOTE The UPWEN pin is set to 1 only if all port power enable bits are 0 due to the use of a ganged shared power enable scheme Port Power Control for USB Port 1 read only Port 1 is an internal port and is always powered on This bit is hard wired to 4 Reserved Write a zero to this bit 7 28 Figure 7 14 HPPWR Hub Port Power Control intel USB HUB 7 7 2 X Overcurrent Detection The OVRI pin is an input pin that indicates when an overcurrent condition has been detected on one of the downstream devices at the board level OVRI is enabled by setting HSTAT 7 and is used to asynchronously disable the UPWEN output pin which switches power off to all external ports When the overcurrent condition is removed the OVRI pin is deasserted to a 1 state however the UPWEN signal remains inactive since the HPPWR5 2 bits are reset when an over current condition is detected unless firmware has asserted one or more of these bits since the time the overcurrent was first detected Due to the asynchronous nature of this signal the user must be careful to guarantee that the OVRI input is not glitchy or noisy since glitches on this signal could have a detrimental impact on the system The state of the OVRI pin can be read by the USB host via firmware using the HSTAT Figure 7 6 on page 7 9 OVI HSTAT 1
458. sceivers for each external USB port and ganged switched port power on the external down stream ports A complete description of the USB can be found in Universal Serial Bus Specification For a de scription of the transceiver see the Driver Characteristics and Receiver Characteristics sec tions of the Electrical chapter of the Universal Serial Bus Specification For electrical characteristics and data signal timing see the Bus Timing Electrical Characteristics and Tim ing Diagram sections of the same chapter NOTE The 8x931AA microprocessor does not support a hub interface Specific details of the 8x931AA are covered in Appendix E 8x931AA Design Considerations 2 4 4 USB Operation Operation of the USB module is controlled through the use of special function registers SFRs SFRs associated with the USB module are described in Chapter 5 USB Function Chapter 6 USB Hub and Chapter 4 Interrupt System Register definition tables in these chapters de scribe register usage and define the register bits The register definition tables also appear in Ap pendix C in alphabetical order A memory map of the 8x931 SFRs is presented in Chapter 3 Address Spaces and Table C 1 on page C 2 Data transfers with the host are made to from endpoint pairs EPPs on the USB module The 8x931HA provides three function endpoint pairs a hub control endpoint pair and a transmit only hub status change endpo
459. scription Interchanges the low and high nibbles 4 bit fields of the accumulator bits 3 0 and bits 7 4 This operation can also be thought of as a 4 bit rotate instruction Flags CY AC OV Example The accumulator contains OC5H 11000101B After executing the instruction SWAP the accumulator contains 5CH 01011100B Bytes States 6 Cycles Encoding 1100 0100 A 54 intel INSTRUCTION SET REFERENCE Operation SWAP A 3 0 2 A 7 4 XCH A lt byte gt Function Exchange accumulator with byte variable Description Loads the accumulator with the contents of the specified variable at the same time writing the original accumulator contents to the specified variable The source destination operand can use register direct or register indirect addressing Flags CY AC OV Example RO contains the address 20H the accumulator contains 3FH 00111111B and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCH A RO RAM location 20H contains 3FH 00111111B and the accumulator contains 75H 01110101B Variations XCH A dir8 Bytes States 6 Cycles 1 Encoding 1100 0101 direct addr Operation XCH A 2 lt dir8 XCH A Ri Bytes States 6 Cycles Encoding 1100 011i Operation XCH A gt lt Ri XCH A Rn Bytes States 6 Cycles 1 Encoding 1100 irrr A 55 8x931AA 8x931HA USER S MAN
460. se the bits are defined differently as shown in Figure 6 8 on page 6 16 Bits 5 1 can be set indirectly by firmware by writing to a port s HPSC SFR Setting any bit in port x s HPSC results in the hardware setting bit xin TXDAT TXDAT bits can be cleared indirectly in firmware by clearing all bits in that port s HPSC Figure 7 7 TXDAT Hub Transmit Data Buffer Endpoint 1 intel USB HUB Host PC Hub Endpoint 1 deleted TXDAT OVI PATE u AE M NN pu ORed HPSC HPSC Ports 2 3 4 5 Port 1 A5256 01 Figure 7 8 Status Change Communication To Host The remaining hub transmit and receive registers communicate control information between the host and either the internal function or the downstream ports The 8x931 communicates this con trol information through endpoint 0 using procedures identical to those outlined for the function control endpoint function endpoint 0 in Transmit FIFOs on page 6 14 and Receive FIFOs on page 6 24 NOTE Hub endpoint 0 s transmit SFRs e g TXDAT TXCNTL TXFLG and TXSTAT behave identically to their function counterparts For example when firmware writes to endpoint 0 s TXDAT hardware automatically transfers the byte into the transmit FIFO before the next write to TXDAT Placing the byte count into hub endpoint 0 s TXCNTL prepares the bytes to be transmitted from the FIFO through hub endpoint 0 at the next IN token 7 13 8x931A
461. set amp clear bit 3 12 2 JZ rel Jump if acc is zero 2 12 2 JNZ rel Jump if acc is not zero 2 12 2 A dir8 rel Compare dir byte to acc and jump 3 12 2 if not equal A data rel Compare immediate to acc and 3 12 2 jump if not equal CJNE Rn data rel Compare immediate to reg and 3 12 2 jump if not equal Ri data rel Compare immediate to indir and 3 12 2 jump if not equal Rn rel Decrement reg and jump if not 2 12 2 zero DJNZ dir8 rel Decrement dir byte and jump if not 3 12 2 zero NOP No operation 1 6 1 intel INSTRUCTION SET REFERENCE A 4 INSTRUCTION DESCRIPTIONS This section describes each instruction in the 8x931 architecture Table A 15 defines the symbols 3 1 0 used to indicate the effect of the instruction on the flags in the PSW register For a conditional jump instruction indicates that a flag influences the decision to jump Table A 15 Flag Symbols Description The instruction does not modify the flag The instruction sets or clears the flag as appropriate The instruction sets the flag The instruction clears the flag The instruction leaves the flag in an indeterminate state For a conditional jump instruction The state of the flag before the instruction executes influences the decision to jump or not jump ACALL lt addr11 gt Function Absolute call Description Unconditionally calls a subroutine at the specified address The ins
462. sor communication feature is enabled the serial port can differentiate between data frames ninth bit clear and address frames ninth bit set This allows the microcontroller to function as a slave processor in an environment where multiple slave processors share a single serial line When the multiprocessor communication feature is enabled the receiver ignores frames with the ninth bit clear The receiver examines frames with the ninth bit set for an address match If the received address matches the slave s address the receiver hardware sets the RB8 bit and the RI bit in the SCON register generating an interrupt NOTE The ES bit must be set in the IENO register to allow the RI bit to generate an interrupt The IENO register is described in Chapter 8 Interrupts The addressed slave s firmware then clears the SM2 bit in the SCON register and prepares to re ceive the data bytes The other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses 11 5 AUTOMATIC ADDRESS RECOGNITION The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled i e the SM2 bit is set in the SCON register Implemented in hardware automatic address recognition enhances the multiprocessor communi cation feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address does the receiver s
463. source Higher priority interrupts are serviced before lower priority interrupts The re sponse to simultaneous occurrence of equal priority interrupts i e sampled within the same four state interrupt cycle is determined by a hardware priority within level resolver see Table 5 6 Table 5 6 Interrupt Priority Within Level Priority Number Interrupt Name 1 Highest Priority INTO 2 Timer 0 3 INT1 4 Timer 1 5 Serial Port 6 Timer 2 7 Keyboard Scan INT2 8 9 USB Hub SOF 10 USB Function 11 Lowest Priority USB Global Suspend Resume 5 26 intel INTERRUPT SYSTEM IPHO Address B7H Reset State x000 0000B Interrupt Priority High Control Register 0 IPHO together with IPLO assigns each interrupt in IENO a priority level from 0 lowest to 3 highest IPHOx IPLOx Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 IPHO 0 Bit Bit Function Number Mnemonic uneto 7 6 Reserved Write zeros to these bits 5 IPHO 5 Timer 2 Overflow Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 External Interrupt 0 Priority Bit High Figure 5 12 IPHO Interrupt Priority High Register 0 5 27 8x931AA 8x931HA USER
464. sserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation Signal ee Alternate Name Type Description Function KSO19 Keyboard Scan Output Quasi bidirectional ports with weak P3 7 RD KSO18 internal pullup resistors used for the output side of the keyboard P3 6 WR KSO17 16 scan matrix P3 5 4 T1 0 KSO15 8 A15 8 P2 7 0 KSO7 0 P1 7 0 LED3 0 LED Drivers Designed to drive LEDs connected directly to Voc The current each driver is capable of sinking is given as in the datasheet OVRI Overcurrent Sense Sense input to indicate an overcurrent P3 0 condition for a bus powered USB device on an external down stream port Active low with an internal pullup P0 7 0 lO Port 0 Eight bit open drain bidirectional I O port Port O pins AD7 0 KSI7 0 have Schmitt trigger inputs P1 7 0 lO Port 1 Eight bit quasi bidirectional I O port with internal KSO7 0 pullups P2 7 0 lO Port 2 Eight bit quasi bidirectional I O port with internal A15 8 KSO15 8 pullups P3 0 lO Port 3 Eight bit quasi bidirectional I O port with internal OVRI P3 1 pullups SOF P3 2 INTO P3 3 INT1 P3 4 TO KSO16 P3 5 T1 KSO17 P3 6 WR KSO18 P3 7 RD KSO19 PLLSEL l Phase locked Loop Select For normal operation using the 8x931HA connect PLLSEL to logic high PLLSEL 0 is used for factory test see Table 2 3 on page 2 9 For 8x931AA operation see Table E 3 on page E 9 PSEN Program Store Enable Read
465. st In Port 2 P2 7 0 or A15 8 from DPH A15 8 from PCH 15 4 A5360 01 Figure 15 3 External Data Read ALE PSEN WR Port 0 A7 0 from RI or DPL Data Out A7 0 from PCL Inst In Port 2 P2 7 0 or A15 8 from DPH A15 8 from PCH A5361 01 Figure 15 4 External Data Write intel EXTERNAL MEMORY INTERFACE 15 3 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus A more comprehensive description of the ports and their use is given in Chapter 9 Input Output Ports When port 0 and port 2 are used as the external memory bus the signals on the port pins can orig inate from three sources the 8x931 CPU address bits data bits the port SFRs PO and P2 logic levels anexternal device data bits The port 0 pins but not the port 2 pins can also be held in a high impedance state Table 15 2 lists the status of the port 0 and port 2 pins when the chip in is the normal operating mode and the external bus is idle or executing a bus cycle Table 15 2 Port 0 and Port 2 Pin Status In Normal Operating Mode 8 bit 16 bit Port Addressing Bus Cycle Bus Idle Port 0 8or16 AD7 0 1 High Impedance 8 P2 2 2 Port 2 16 A15 8 2 NOTES 1 During external memory accesses the CPU writes FFH to the PO register and the register contents are lost 2 The P2 register can be used to se
466. st firmware must examine the HPSTAT SFR to determine the current port state If the port is in a state where the request will be ignored by hardware firmware must respond to the host by sending a STALL during the transaction status stage to indicate the command was not completed Port states are discussed in Port Connectivity States on page 7 4 and shown in Figure 7 3 on page 7 5 Table 7 5 USB Requests Ignored by Hardware by Port State Response by Port State as indicated by the given bit in HPSTAT USB Request Powered Off Disconnected Disabled Enabled Suspended PPSTAT 0 PCSTAT 0 PESTAT 0 PESTAT 1 PSSTAT 1 SetPortFeature Port Power Ignored Ignored Ignored Ignored ClearPortFeature Port Power Ignored SetPortFeature Port Enable Ignored Ignored Ignored Ignored ClearPortFeature Port Enable Ignored Ignored Ignored Ignored SetPortFeature Port Reset Ignored Ignored SetPortFeature Port Suspend Ignored Ignored Ignored Ignored ClearPortFeature Port Suspend Ignored Ignored Ignored Ignored intel USB HUB After you request a port status change through HPCON it may take the 8x931 hardware a period of time to affect the change depending on the current state of the hub port and its current opera tion You can check the HPSC SFR to see that your latest change has taken effect as described in Monitoring Port Status Change Using HPSC on page 7 20 NOTE
467. st from the host See Monitoring Port Status Change Using HPSC on page 7 20 for a description of how firmware interacts with the host to communicate a change in port status NOTE Although the bits of hub endpoint l s TXDAT SFR are firmware read only bits 5 1 of TXDAT can be cleared indirectly by writing to a port s HPSC SFR Clearing all bits in a port s HPSC causes hardware to clear the bit associated with that port in hub endpoint 1 s TXDAT Hub endpoint 1 s TXDAT 0 can be cleared indirectly by clearing HSTAT s OVISC bit TXDAT For hub endpoint 1 only EPINDEX 81H Address F3H Reset State xxxxB 7 0 TXDATS TXDAT4 TXDAT3 TXDAT2 TXDAT1 TXDATO Bit Bit Number Mnemonic Function 7 6 Reserved Values read from this bit s are indeterminate 5 0 TXDAT5 0 Hub Endpoint 1 Status Change read only Hardware communicates status changes to the host by setting the appropriate bit TXDATO hub status change TXDAT1 port 1 status change TXDAT2 port 2 status change TXDATS port 3 status change TXDAT4 port 4 status change TXDATS port 5 status change A 1 indicates a status change and 0 indicates no status change When endpoint 1 is addressed via an IN token the entire byte is sent if at least one bit is a 1 If all bits are zero a NAK handshake is returned TXDAT SFRs are also used for function and hub endpoint 0 data transmission EPINDEX 0xH or 80H In that ca
468. ster Controls the receive FIFO specified by EPINDEX 7 0 RXCLR RXFFRC RXISO ARM ADVWM REVWP Bit Bit Number Mnemonic Function 7 RXCLR Clear the Receive FIFO Set this bit to flush the entire receive FIFO All flags in RXFLG revert to their reset states RXEMP is set all other flags clear The ARM RXISO and RXWS bits in this register and the RXSEQ bit in the RXSTAT register are not affected by this operation Hardware clears this bit when the flush operation is completed 6 5 Reserved Values read from this bit are indeterminate Write zero to this bit 4 RXFFRC FIFO Read Complete Set this bit to release the receive FIFO when a data set read is complete Setting this bit clears the RXFIF bit in the RXFLG register corresponding to the data set that was just read Hardware clears this bit after the RXFIF bit is cleared All data from this data set must have been read NOTE FIFO Read Complete only works if STOVW and EDOVW are cleared 3 Isochronous Data Type Set this bit to indicate that the receive FIFO is programmed to receive isochronous data and to set up the USB Interface to handle an isochronous data transfer This bit is not reset when the RXCLR bit is set it must be cleared by firmware 2 Auto Receive Management When set the write pointer and write marker are adjusted automatically based on the following conditions RXISO RX Status Write Pointer Write
469. sure data integ rity and latency for the next reception The post receive routine also transfers the data in the re ceive FIFO to the end function For isochronous data the post receive routine should be called by the SOF ISR Flow diagrams for typical post receive routines are presented in Figure 8 7 non isochronous da ta and Figure 8 8 isochronous data 8x931AA 8x931HA USER S MANUAL intel Start Receive Done ISR Identify Function Interrupt and Endpoint Check FRXDx Bits in FIFLG Register Clear Interrupt Flag Check RXSTAT for Receive Error RXACK 1 No Yes RXERR 1 Advance Receive FIFO to next packet RXOVF 1 Error in Receive FIFO No Failed CRC or Bit Stuffing Reverse Receive FIFO to current packet retry Check for Another Packet in Receive FIFO RXFIF1 0 z 00 in Dual Port Mode Yes RXOVF 1 Read Data Packet s Receive FIFO Error Recovery Error in Receive FIFO Yes RXURF 1 Receive FIFO Error Recovery Unlock Current Packet from Receive FIFO set RXFFRC Bit in RXCON RETI Buffer Segmentation Management Executed automatically by hardware at the end of a data transaction if ARM bit in RXCON is set A5070 01 Figure 8 7 Post receive ISR Non isochronous intel USB PROGRAMMING MODELS Start SOF ISR For Each Endpoint Read Transaction Status RXSTA
470. t indexed SFR Because of this interrupt service routines must save the contents of the HPINDEX register at the start of the routine and restore the contents at the end of the ISR This will prevent HPINDEX from being corrupted 7 23 8x931AA 8x931HA USER S MANUAL intel HPINDEX Address D4H Reset State x000B Hub Port Index Register This register contains the binary value of the port whose HPSC HPSTAT and HPCON registers are to be accessed 7 0 aes aoe HPIDX2 HPIDX1 HPIDXO Bit Bit Number Mnemonic Function 7 3 Reserved Write zeros to these bits 2 0 HPIDX 2 0 Port Index Select Used to select the port to be indexed by the following registers HPSC HPSTAT and HPCON This register is hardware read only The ports are addressed using the following HPIDX2 0 bit combinations Port 1 001 internal port Port 2 010 Port 3 011 Port 4 100 Port 5 101 NOTE Port 0 000 the root port and all other combinations not shown above are not valid port indexes and are ignored Figure 7 12 HPINDEX Hub Port Index Register 7 5 5 Embedded Function The following subsections discuss considerations involved with the embedded function on inter nal downstream port 1 See Embedded Function Suspend and Resume on page 7 26 for addi tional embedded function information 7 5 5 1 Embedded Function Reset The USB host
471. t FIFO Advance Transmit FIFO to next packet Check TXFLUSH error tracking Yes TXURF 1 Transmit FIFO Error Recovery Advance Transmit FIFO to Next Packet Write Next Packet to Transmit FIFO Write Next Packet to Transmit FIFO Overflow Error in Transmit FIFO Yes 1 Overflow Error in Transmit FIFO Write Packet Size to TXCNT Write Packet Size to TXCNT RETI Buffer Segmentation Management Executed automatically by hardware at the end of a data transaction if ATM bit in TXCON is set For isochronous transactions there is no retry of current packet regardless of transaction status A5073 02 Figure 8 5 Post transmit ISR ISochronous 8 9 8x931AA 8x931HA USER S MANUAL intel 8 3 RECEIVE OPERATIONS 8 3 1 Overview A receive operation is always initiated by the host which sends an OUT token to the 8x931 The operation occurs in two major steps 1 Data packet reception by the function interface hardware 2 Post receive management by firmware These steps are depicted in a high level view of the receive operations in Figure 8 6 The post receive operations are executed by the firmware routine shown on the left side of the figure For details see Post receive Operations on page 8 11 Function interface hardware right side of fig ure receives the data packet over the USB line Receive operations for non isochro
472. t of PCONI Figure 14 2 on page 14 4 2 Use bit 2 of IPHI IPL to set the priority of the USB reset interrupt See Interrupt Priorities on page 5 26 5 18 intel INTERRUPT SYSTEM NOTE It is recommended that you set the USB reset interrupt to the highest priority 3 After enabling the USB reset interrupt and assigning it a priority your initialization routine should clear the USB_RST_FLG flag This flag is a global variable declared in your firmware not a bit in an SFR This flag an indicator that a USB reset has occurred will be examined at various points in your main routine subroutines and ISRs 5 19 8x931AA 8x931HA USER S MANUAL intel Loop continuously Initialization Routine USB Reset Set IENO EA Hardware 27 USB Rese 0 USB Reset Set IEN1 ESR Set PCON1 URDIS Global Suspend Resume ISR Set Interrupt Priority USB RST 0 Reset all USB blocks Main Routine Set PCON1 URST Check normal processing Generate USB Reset PCON1 URST until interrupt occurs Interrupt USB reset triggered Perform Global Main Routine i uti Suspend Resume ISR Bus Powered Set PCON LC 1 1 1 1 1 Periodically Test USB_RST_FLG Clear PCON1 URST USB_RST_FLG 1 1 1 USB_RST_FLG 1 ISR Complete I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Continue with 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Clea
473. t pairs 3 3 4 or 6 Transmit receive FIFO sizes Endpoint 0 8 bytes 8 bytes 16 bytes 16 bytes Endpoint 1 16 bytes 16 bytes 0 1024 bytes 0 1024 bytes or 256 bytes Endpoint 2 8 bytes 8 bytes 16 bytes 16 or 32 bytes Endpoint 3 16 bytes 16 or 32 bytes Endpoint 4 32 bytes Endpoint 5 16 bytes USB Hub Features Internal downstream port USB port 1 USB port 4 USB rate full speed 12 Mbps 12 Mbps INT2 0 are external interrupts T2 0 are timer counter interrupts 2 4 intel ARCHITECTURAL OVERVIEW Table 2 2 USB Peripheral Controller Feature Summary and Comparison Continued 8x931Hx 8x931Ax 8x930Hx 8x930Ax USB Hub Features cont External downstream ports 4 USB ports 4 USB ports 2 3 4 5 1 2 3 5 USB rate full speed low speed 12 Mbps 12Mbps 1 5 Mbps 1 5 Mbps Hub endpoint 0 transmit receive FIFOs 8 bytes 16 bytes Hub endpoint 1 one transmit data buffer register 1 byte 1 byte Core Microcontroller Features Architecture MCS 51 MCS 51 MCS 251 MCS 251 Accumu Accumu Register Register lator based lator based based based Address spaces Program memory 64 Kbytes 64 Kbytes Single 256 Single 256 Data memory 64 Kbytes 64 Kbytes Kbyte Kbyte address address space space External bus multiplexed Address 16 bits 16 bits 16 17 or 18 16 17 or 18 bits bits Data 8 bits 8 bits 8 bits 8 bits Number of R
474. t port the value used as the original port data is read from the output data latch not the input pins CY AC OV intel INSTRUCTION SET REFERENCE Example The accumulator contains 11000011B and RO contains OAAH 10101010B After executing the instruction XRL A RO the accumulator contains 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be comple mented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B complements bits 5 4 and 0 of output Port 1 Variations XRL dir8 A Bytes 2 States 6 Cycles 1 Encoding 0110 0010 direct addr Operation XRL dir8 dir8 v A XRL dir8 data Bytes 3 States 12 Cycles 2 Encoding 0110 0011 direct addr immed data Operation XRL dir8 lt dir8 v data XRL A data Bytes 2 States 6 Cycles Encoding 0110 0100 immed data Operation XRL lt A v data XRL A dir8 Bytes 2 A 57 8x931AA 8x931HA USER S MANUAL States Cycles Operation XRL A Ri Bytes States Cycles Operation XRL A Rn Bytes States Cycles Operation A 58 Encoding 0110 0101 direct addr XRL lt A V dir8 Encoding X
475. t stuff error have RXERR cleared by hardware before seen by firmware Received 00 Set Time out Only RXOVF OUT token chg receive NAK FIFO error can FIFO error interrupt future occur requires occurs transactio firmware ns intervention Received 00 1 0 1 0 1 no None NAK Considered to OUT token no no no chg be a void with FIFO chg chg chg condition Will error already NAK until existing firmware clears condition Received 00 no no 1 no no no None ACK Last ACK OUT token chg chg chg chg chg corrupted so but data send again but sequence ignore the data mismatch Received 01 0 1 0 1 0 0 Set ACK RXIE or RXSTL SETUP receive has no effect 2 token no interrupt RXSETUP will errors be set control endpoints only NOTE 1 These are sticky bits which must be cleared by enabled 2 STOVW is set after a valid SETUP token is rece handshake phase D 8 firmware Also this table assumes RXEPEN and ARM are ived and cleared during handshake phase EDOVW is set during intel DATA FLOW MODEL Table D 3 Non isochronous Receive Data Flow in Single packet Mode RXSPM 1 Continued New RX RX RX FIF RX RX RX RX USB Event FIF OVF URF Inter Comments 1 0 1 0 ERR ACK Void Setup 1 1 rupt Response Received 00 1 0 0 0 0 0 Set Time out FIFO is reset SETUP receive automatically token but interrupt and FIFO data timed out is in
476. ta Register TXDAT sse 6 16 6 3 8 Transmit FIFO Byte Count Register TXONTL sse 6 16 6 3 4 Transmit Data Set Management sse ennemis 6 17 6 4 RECEIVE FIEOS mea BL DH 6 24 6 4 1 Receive FIFO Registers detenido ete cete eec eser re ANAE led 6 25 6 4 1 1 Receive FIFO Data Register RXDAT 6 25 6 4 1 2 Receive FIFO Byte Count Registers RXCNTL 6 26 6 4 Receive FIFO Data Set Management sss 6 27 6 5 SIE DETAIIES 3 itii ut e epe ient e e tae eS 6 34 6 6 SETUP TOKEN RECEIVE FIFO HANDLING eene 6 34 6 7 ISO DATA MANAGEMENT esses enne nnne rnnt nennt nent rennen nenne 6 35 6 7 1 Transmit FIFO ISO Data Management sesesssseeeeneeneeneennns 6 35 6 7 2 Receive FIFO ISO Data Management sse 6 36 CHAPTER 7 USB HUB 7 1 HUB FUNCTIONAL OVERVIEW 7 1 7 1 1 Port Connectivity States cn crs eer eee PA pectet 7 4 7 1 2 Per packet Signaling Connectivity sse 7 6 7 1 2 1 Connectivity to Downstream Ports Attached With Full speed Devices 7 6 7 1 2 2 Connectivity to Downstream Ports attached with Low speed Devices 7 7 7 2 BYS ENU ME RATON Iun Gelbe D eui HEREDES 7 7 7 2 1
477. te count register After reset the read write index points to data set 0 Thereafter the following logic de termines the position of the read write index After a read of RXCNTL the read write index RXFIF is unchanged e After a write of RXCNTL the read write index RXFIF is toggled The position of the read write index can also be determined from the data set index bits FIF1 0 see Receive FIFO Data Set Management on page 6 27 CAUTION Do not read RXCNTL to determine if data is present in the receive FIFO A read attempt to RXCNTL during the time the receive FIFO is empty causes the RXUREF flag in RXFLG to be set Always read the RXFIF bits in RXFLG to determine if data is present in the receive FIFO The RXFIF bits are updated after RXCNTL is written at the end of the receive operation and at the SOF for ISO data 6 4 2 Receive FIFO Data Set Management As in the transmit FIFO the receive FIFO uses a pair of bits FIF1 0 in the RXFLG register to indicate which data sets are present in the receive FIFO see Table 6 6 Table 6 6 Status of the Receive FIFO Data Sets Data Sets Written FIF1 0 ds1 ds0 0 No Empty 1 No Yes 1 set 1 0 Yes No 1 set 1 1 Yes Yes 2 sets 6 27 8x931AA 8x931HA USER S MANUAL intel Table 6 7 summarizes how the actions following a reception depend on the RXISO bit the ARM bit and the handshake issued by the 8x931 Table 6 7 Truth Table fo
478. te gt is less than the unsigned integer value of lt src byte gt the CY flag is set Neither operand is affected The first two operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant intel INSTRUCTION SET REFERENCE Flags CY AC OV Example The accumulator contains 34H and R7 contains 56H After executing the first instruction in the sequence CJNE R7 60H NOT_EQ MUS Lo R7 60H NOT EQ JC REQ LOW IF R7 60H R7 gt 60H the CY flag is set and program execution continues at label NOT_EQ By testing the CY flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then executing the instruction WAIT CJNE A P1 WAIT clears the CY flag and continues with the next instruction in the sequence since the accumulator does equal the data read from P1 If some other value was being input on P1 the program loops at this point until the P1 data changes to 34H Variations CJNE A data rel Bytes 3 States 12 Cycles 2 Encoding 1011 0100 immed data rel addr Operation PC IF A data THEN PC relative offset IF A lt data THEN lt 1 ELSE CY 0 CJNE A dir8 rel Bytes 3 States 12 Cycles 2
479. ternal pin After a preset number of counts the counter issues an interrupt request 10 1 TIMER COUNTER OVERVIEW The 8x931 contains three general purpose 16 bit timer counters Although they are identified as timer 0 timer 1 and timer 2 you can independently configure each to operate in a variety of modes as a timer or as an event counter Each timer employs two 8 bit timer registers used sep arately or in cascade to maintain the count The timer registers and associated control and capture registers are implemented as addressable special function registers SFRs Four of the SFRs pro vide programmable control of the timers as follows Timer counter mode control register TMOD and timer counter control register TCON control timer 0 and timer 1 Timer counter 2 mode control register T2MOD and timer counter 2 control register T2CON control timer 2 Table 10 1 describes the external signals referred to in this chapter Table 10 2 briefly describes the SFRs referred to in this chapter For a map of the SFR address space see Table C 1 on page C 2 10 2 TIMER COUNTER OPERATION The block diagram in Figure 10 1 depicts the basic logic of the timers Here timer registers THx and TLx x 0 1 and 2 connect in cascade to form a 16 bit timer Setting the run control bit TRx turns the timer on by allowing the selected input to increment TLx When TLx overflows it increments THx when THx overflows it sets the timer overflow flag
480. terrupt goes active Note This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or write IE or IP A4462 01 Figure 5 16 Interrupt Response Timing Diagram 5 31 8x931AA 8x931HA USER S MANUAL intel 5 6 RESPONSE TIME The INTO and INT 1 levels are inverted and latched into the Interrupt Flags and IE1 at S5P2 of every machine cycle Similarly the Timer 2 flag EXF2 and the serial Port flags RI and TI are set at S5P2 The values are not actually polled by the circuitry until the next machine cycle The Timer 0 and Timer 1 flags and TFI are set at S5P2 of the cycle in which the timers over flow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles elapses between activation of an external interrupt request and the beginning of execution of the service routine s first in struction Figure 5 16 shows interrupt response timing A longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already i
481. the Accumulator holding 00010001B The addressing modes that can be used to access the byte operand are listed in Table 4 4 Thus the ANL A byte instruction may take any of the forms ANL A 7FH direct addressing ANL A GRI indirect addressing ANL A R6 register addressing ANL A 53H immediate constant All of the logical instructions that are Accumulator specific execute in 1 us using a 12 MHz clock The others take 2 ps Note that Boolean operations can be performed on any byte in the lower 128 internal Data Mem ory space or the SFR space using direct addressing without having to use the Accumulator The XRL byte gt data instruction for example offers a quick and easy way to invert port bits as in XRL PLZ0FFH If the operation is in response to an interrupt not using the Accumulator saves the time and effort to stack it in the service routine The Rotate instructions RL amp RLC A etc shift the Accumu lator 1 bit to the left or right For a left rotation the MSB rolls into the LSB position For a right rotation the LSB rolls into the MSB position The SWAP A instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in BCD manipulations For example if the Accumulator contains a binary number which is known to be less than 100 it can be quickly converted to BCD by the following code MOV B 10 DIV AB SWAP A ADD A B Dividing the number by 10 leaves th
482. therwise the access is off chip The value of EA is latched at reset For devices without on chip ROM EA must be strapped to ground ECAP External Capacitor Connect a 1 uF or larger capacitor between this pin and Vss to ensure proper operation of the differential line drivers FSSEL Full Speed Select Applies to the 8x931AA only If this pin is high full speed USB data rate is selected 12Mbps If pin is low low speed USB data rate is selected 1 5 Mbps Refer to Table E 3 on page E 9 INT1 0 KSI7 0 External Interrupts 0 and 1 These inputs set the IE1 0 interrupt flags in the TCON register Bits IT1 0 in TCON select the triggering method edge triggered high to low or level triggered active low INT1 0 also serves as external run control for timer1 0 when selected by GATE1 0 in TCON Keyboard Scan Input Schmitt trigger inputs with firmware enabled internal pullup resistors used for the input side of the keyboard scan matrix P3 3 2 AD7 0 P0 7 0 PIN DESCRIPTIONS Table B 7 Signal Description Sheet 2 of 3 oscillator periods while the oscillator is running resets the device The port pins are driven to their reset conditions when a voltage greater than Vi is applied whether or not the oscillator is running This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and Vec A
483. this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV If the accumulator contains 11000011B and register 0 contains 55H 01010101B After executing the instruction ANL A RO Accumulator 1 contains 41H 01000001B When the destination is a directly addressed byte this instruction clears combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be an immediate constant contained in the instruction or a value computed in the register or accumulator at run time The instruction ANL P1 01110011B clears bits 7 3 and 2 of output port 1 Encoding 0101 0010 direct addr ANL dir8 lt dir8 A A Bytes 3 States 12 Cycles 2 Encoding 0101 0011 direct addr immed data Operation ANL dir8 lt dir8 A data intel ANL A data Bytes States 6 Cycles 1 INSTRUCTION SET REFERENCE Encoding 0101 0100 immed data Operation ANL A A A data ANL A dir8 Bytes 2 States 6 Cycles Encoding 0101 0101 direct addr Operation ANL A A dir8 ANL A Ri Bytes States 6 Cycles Encoding Operation ANL lt A A Ri ANL A Rn Bytes States 6 Cycles Encoding Operation ANL lt A A Rn ANL CY src bit
484. through firmware When this bit is set the FIFO is in an unknown state thus it is recommended that you reset the FIFO in your error management routine using the TXCLR bit in TXCON When the receive FIFO overruns the write pointer will not advance it remains locked in the full position Check this bit after loading the FIFO prior to writing the byte count register In ISO mode TXOVF TXURF and TXFIF are handled using the following rule Firmware events cause status change immediately while USB events cause status change only at SOF Since overrun can only be caused by firmware TXOVF is updated immediately Check the TXOVF flag after writing to the transmit FIFO before writing to TXCNT When set all transmissions are NAKed C 61 8x931AA 8x931HA USER S MANUAL intel TXSTAT Address F2H Endpoint indexed Reset State 0xx0 0000B Endpoint Transmit Status Register Contains the current endpoint status of the transmit FIFO specified by EPINDEX 7 0 TXSEQ TXFLUSH TXSOVW TXVOID TXERR TXACK Bit Bit _ Function Number Mnemonic une 7 Transmitter s Current Sequence Bit read conditional write t This bit will be transmitted in the next PID and toggled on a valid ACK handshake This bit is toggled by hardware on a valid SETUP token This bit can be written by firmware if the TXSOVW bit is set when written together with the new TXSEQ value 6 5 Reserved Write zeros to these bi
485. tion at program memory location 0123H The instruction SJMP RELADR assembles into location 0100H After executing the instruction the PC contains 0123H Note In the above example the instruction following SUMP is located at 102H Therefore the displacement byte of the instruction is the relative offset 0123H 0102H 21H Put another way an SUMP with a displacement of OFEH would be a one instruction infinite loop 2 12 2 Encoding 1000 0000 rel addr SJMP lt PC 2 lt PC rel intel INSTRUCTION SET REFERENCE SUBB A lt src byte gt Function Subtract with borrow Description SUBB subtracts the specified variable and the CY flag together from the accumulator leaving the result in the accumulator SUBB sets the CY borrow flag if a borrow is needed for bit 7 and clears CY otherwise If CY was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the CY flag is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative nu
486. tivity to Downstream Ports attached with Low speed Devices Downstream connectivity is established in the same fashion for low speed packets as for full speed packets with the following exceptions 1 Downstream low speed packets are routed to all enabled ports including ports attached with low speed and full speed devices 2 Downstream low speed packets contain a low speed PREamble field which is recognized by the SIE Upon detection of the PREamble the repeater establishes the connection to all enabled low speed downstream ports 3 Packet data is inverted at the ports attached to low speed devices for both upstream and downstream traffic Upstream connectivity is established in the same fashion for low speed packets as for full speed packets with the exception that no PREamble is propagated prior to low speed packets The root port propagates low speed packets upstream using full speed signaling edge rates 7 2 BUS ENUMERATION The USB host manages bus enumeration at system start up or whenever a new USB device is at tached to the host or to a hub s downstream port Initially the USB hub is in the unenumerated state and the hub address register HADDR contains the default value 00 The host PC per forms bus enumeration in which it identifies and addresses devices attached to the bus During enumeration a unique address assigned by the host is written to the HADDR of every hub device Information on descriptors and the HADDR
487. to the function of addressing the Program Memory 3 2 intel ADDRESS SPACES 3 1 3 Data Memory Figure 3 2 shows the internal and external Data Memory spaces available to the 8x931 user Program Memory Data Memory Read Only Read Write FFFFH FFFFH External External EA 0 EA 1 External Internal 0 N PSEN RD WR A 4475 01 Figure 3 2 8x931 Memory Structure Internal Data Memory is mapped in Figure 3 3 The memory space is shown divided into three blocks which are generally referred to as the Lower 128 the Upper 128 and SFR space Internal Data Memory addresses are always one byte wide which implies an address space of only 256 bytes However the addressing modes for internal RAM can in fact accommodate 384 bytes us ing a simple trick Direct addresses higher than 7FH access one memory space and indirect ad dresses higher than 7FH access a different memory space Thus Figure 3 3 shows the Upper 128 and SFR space occupying the same block of addresses 80H through FFH although they are phys ically separate entities The Lower 128 bytes of RAM are present in all MCS 51 devices as mapped in Figure 3 4 The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these regis ters as RO through R7 Two bits in the Program Status Word PSW select which register bank is 3 3 8x931AA 8x931HA USER S MANUAL in use This allows more efficient use
488. truction increments the 3 byte PC twice to obtain the address of the following instruction then pushes bytes 0 and 1 of the result onto the stack byte 0 first and increments the stack pointer twice The destination address is obtained by successively concatenating bits 15 11 of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2 Kbyte page of the program memory as the first byte of the instruction following ACALL Flags CY AC OV Example The stack pointer SP contains 07H and the label SUBRTN is at program memory location 0345H After executing the instruction ACALL SUBRTN at location 0123H SP contains 09H on chip RAM locations 08H and 09H contain 01H and 25H respectively and the PC contains 0345H Bytes 2 States 12 Cycles 2 Encoding a10 a9 a8 1 0001 a7 a6 a5 a4 a3 a2 a1 a0 A 9 8x931AA 8x931HA USER S MANUAL intel Operation ACALL ADD lt A gt lt src byte gt Function Description Flags Example Variations ADD A data Bytes States Cycles Operation Add Adds the source operand to the accumulator leaving the result in the accumulator If there is a carry out of bit 7 CY the CY flag is set If byte variables are added and if there is a carry out of bit 3 AC the AC flag is set For addition of unsigned integers the CY flag indicates that an overflow occurr
489. ts 4 TXFLUSH Transmit FIFO Packet Flushed read only When set this bit indicates that hardware flushed a stale ISO data packet from the transmit FIFO due to a TXFIF1 0 11 at SOF To guard against a missed IN token in ISO mode if with TXFIF1 0 11 no IN token is received for the current endpoint hardware automatically flushes the oldest packet and decrements the TXFIF1 0 value 3 TXSOVW Transmit Data Sequence Overwrite Bit t Write a 1 to this bit to allow the value of the TXSEQ bit to be overwritten Writing a 0 to this bit has no effect on TXSEQ This bit always returns 0 when read 2 TXVOID Transmit Void read only A void condition has occurred in response to a valid IN token Transmit void is closely associated with the NAK STALL handshake returned by the function after a valid IN token due to the conditions that cause the transmit FIFO to be unenabled or not ready to transmit Use this bit to check any NAK STALL handshake returned by the function This bit does not affect the FTXDx TXERR or TXACK bits This bit is updated by hardware at the end of a non isochronous transaction in response to a valid IN token For isochronous transactions this bit is not updated until the next SOF Under normal operation this bit should not be modified by the user The SIE will handle all sequence bit tracking This bit should only be used when initializing a new configuration or interface For
490. ts individually and you can assign one of four priority levels to each interrupt Refer to Chapter 5 Interrupt Sys tem for a detailed description 2 3 8x931 MEMORY The 8x931 has separate 64 Kbyte program memory and data memory address spaces A sixteen bit address bus permits the 8x931 to address 64 Kbytes of program memory up to 8 Kbytes of on chip ROM and the remainder in external program memory and 64 Kbytes of data memory 256 bytes of on chip RAM and the remainder in external data memory See Table 2 1 for 8x931 memory options The 8x931 is available with 8 Kbytes of on chip ROM memory located at the lowest addresses of program memory or without ROM Program memory is read only Following chip reset the first instruction is fetched from location 0000H in program memory For ROM devices this will be from on chip program memory and EA should be tied to Vec For devices without on chip ROM all instruction fetches are from external memory and EA should be tied to ground The 8x931 has 256 bytes of on chip RAM located at the lowest addresses of the data memory Data memory locations can be accessed with direct and indirect addressing Sixteen of these lo cations 20H 2FH are bit addressable The general purpose registers four banks of RO R7 re side at data memory locations 00H 1FH Special functions registers SFRs are also located in the data memory space at locations 80H FFH SFRs are accessed by direct addressing wh
491. ttached to a port HPSTAT also shows a given port s reset status and whether the port is powered on or off connected or discon nected enabled or disabled or suspended NOTE Firmware initiated port status changes are not reflected in HPSTAT until the next end of frame The HPSTAT SER is read only To change the status of a port feature you must do so indirectly using the HPCON SFR The 8x931HA hardware can also change the status of a port and some features can only be changed by hardware See Controlling a Port Using HPCON on page 7 14 7 17 8x931AA 8x931HA USER S MANUAL intel HPSTAT Address D7H Indexed by HPINDEX Reset State 100d 0000B Hub Port Status Register This register indicates the current status for a port including power reset suspend low speed device enable connect Dp and Dy status 7 0 DPSTAT DMSTAT LSSTAT PPSTAT PRSTAT PSSTAT PESTAT PCSTAT Bit Bit Function Number Mnemonic unctio 7 DPSTAT D Status read only Value of D for port x at end of last frame Firmware must return this bit in response to a GetBusState request from the host Port x x 2 3 4 5 Set and cleared by hardware at the EOF2 point near the end of a frame used for diagnostics Port 1 Hard wired to 1 since there is no D signal for the embedded port 6 DMSTAT Dy Status read only Value of Dy for port x at end of last frame Firmware must return this bit i
492. ub interrupt When this interrupt is triggered firmware must examine the ASOF bit in the SOFH SFR to determine that it was the start of frame interrupt that was triggered and not the hub interrupt SOFH Address D3H Reset State 0000 1000B Start of frame High Register Contains isochronous data transfer enable and interrupt bits and the upper three bits of the 11 bit time stamp received from the host 7 0 SOFACK ASOF SOFIE FTLOCK SOFODIS TS10 TS9 TS8 Bit Bit Function Number Mnemonic ungt 7 SOFACK SOF Token Received without Error read only When set this bit indicates that the 11 bit time stamp stored in SOFL and SOFH is valid This bit is updated every time an SOF token is received from the USB bus and it is cleared when an artificial SOF is generated by the frame timer This bit is set and cleared by hardware 6 ASOF Any Start of Frame This bit is set by hardware to indicate that a new frame has started The interrupt can result either from reception of an actual SOF packet or from an artificially generated SOF from the frame timer This interrupt is asserted in hardware even if the frame timer is not locked to the USB bus frame timing When set this bit is an indication that either an actual SOF packet was received or an artificial SOF was generated by the frame timer This bit must be cleared by firmware or inverted and driven to the SOF pin The effect of setting this bit by firmware is t
493. ued intel oscillator connect the external crystal or ceramic resonator across XTAL1 and XTAL2 If an external oscillator is used leave XTAL2 unconnected Signal Alternate Name Type Description Function T2EX Timer 2 External Input In timer 2 capture mode a falling edge P1 1 initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction 1 up O down TXD Transmit Serial Data TXD outputs the shift clock in serial I O P1 7 mode 0 and transmits serial data in serial I O modes 1 2 and 3 Voc PWR Supply Voltage Connect this pin to the 5V supply voltage Voce PWR Supply Voltage for I O buffers Connect this pin to the 5V ae supply voltage Vas GND Circuit Ground Connect this pin to ground Vsp GND Circuit Ground for I O buffers Connect this pin to ground WR Write Write signal output to external memory P3 6 KSO19 XTAL1 Oscillator Amplifier Input When implementing the on chip oscillator connect the external crystal or ceramic resonator across XTAL1 and XTAL2 If an external clock source is used connect it to this pin XTAL2 Oscillator Amplifier Output When implementing the on chip E 8 intel E 5 OPERATING FREQUENCIES 8x93 1AA operating frequencies and USB rates are shown in Table E 3 8X931AA DESIGN
494. ulator contains OC5H 11000101 and the CY flag is clear After executing the instruction RRCA the accumulator contains 62 01100010B and the CY flag is set Encoding 0001 0011 RRC lt 1 7 lt lt 0 Set bit Sets the specified bit to one SETB can operate on the CY flag or any directly addressable bit No flags are affected except the CY flag for instruction with CY as the operand CY AC OV 3 The CY flag is clear and output Port 1 contains 34H 00110100B After executing the instruction sequence SETB CY SETB P1 0 the CY flag is set and output Port 1 contains 35H 00110101B A 51 8x931AA 8x931HA USER S MANUAL intel Cycles Operation SETB CY Bytes States Cycles Operation SJMP rel Function Description Flags Example Bytes States Cycles Operation A 52 1 Encoding 1101 0010 bit addr SETB bit51 lt 1 Encoding 1101 0011 SETB CY 1 Short jump Program control branches unconditionally to the specified address The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it CY AC OV The label RELADR is assigned to an instruc
495. urn address which normally is the instruction immediately after the point at which the interrupt request was detected If an interrupt of the same or lower priority is pending when the RETI instruction is executed that one instruction is executed before the pending interrupt is processed CY AC OV intel Example Bytes States Cycles Operation RLA Function Description Flags Example Bytes States Cycles Operation RLCA Function INSTRUCTION SET REFERENCE The stack pointer contains OBH An interrupt was detected during the instruction ending at location 0122H On chip RAM locations OAH and OBH contain 01H and 23H respectively After executing the instruction RETI the stack pointer contains 09H and program execution continues at location 0123H 1 12 2 Encoding 0011 0010 RETI PC 15 8 SP lt SP 1 7 0 SP SP 1 SP PC SP Rotate accumulator left Rotates the eight bits in the accumulator one bit to the left Bit 7 is rotated into the bit 0 position CY AC OV The accumulator contains OC5H 11000101B After executing the instruction RLA the accumulator contains 8BH 1000101 1B the CY flag is unaffected Encoding 0010 0011 RL 1 lt A a A 0 lt 7 Rotate accumulator left through the carry flag A 49 8x931AA 8x931HA USER S MANUAL intel Description Rotates the eig
496. usly This starts the oscillator and restores the clocks to the CPU and peripherals Program execution momentarily resumes with the instruction immediately following the instruction that activated powerdown and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8x931 and vectors the CPU to address 0000 NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated the powerdown mode should not write to a port pin or to the external RAM 14 4 2 Global Resume Mode Upon detection of a global resume the 8x931 sets the global resume bit GRSM of PCONI clears the global suspend bit GSUS of PCON1 and generates the global suspend resume inter rupt The 8x931 restarts the oscillator as soon as resume signaling is detected on the USB lines A resume condition is defined as a J to anything transition This could be a K transition or reset signaling on the root port A resume condition could be an enabled downstream port or con nect disconnect of a downstream port in the disconnected disabled or suspended states NOTE Since the 8x931AA microcontroller does not support a hub interface there are no downstream ports to signal a resume condition A resume condition can still be caused by any o
497. ust be able to accept a device address via a SET ADDRESS command no later than 10 ms after the reset is removed It is recommended that you ensure that the total time required for the following is less than 10ms 1 The time to complete and exit from the USB reset ISR accounting for latency see Response Time on page 5 32 2 The time for the maximum number of instructions that could execute before your code recognizes that a USB reset has occurred by checking USB_RST_FLG and calls your USB initialization routine 3 The time to execute your USB initialization routine This time constraint may require you to check USB_RST_FLG at multiple points in your code and within any ISRs that may take longer than 10ms to perform By inserting this checkpoint your program can branch from a routine or ISR after the USB reset without having to complete the routine or ISR Your program can continue the interrupted routine after ensuring that the device is ready for USB enumeration 5 22 intel INTERRUPT SYSTEM CAUTION If a USB reset interrupt occurs during execution of a USB receive ISR e g receive done or start of frame the 8x931 will reset the USB hardware This will render invalid any data received during the USB transfer If this is not detected by your firmware misprocessing can occur The risk of USB reset related misprocessing can be reduced if your USB receive transmit ISRs check USB_RST_FLG before returning If this fl
498. valid 2 waiting for data Received 00 1 0 0 1 0 0 Set Time out Write pointer SETUP receive reversed 2 token data interrupt CRC or bit stuff error Received 00 1 0 0 1 1 0 Set Time out 2 SETUP receive NAK token FIFO interrupt future error occurs transactio ns Received 01 0 1 0 1 0 0 Set ACK Causes FIFO SETUP receive to reset token with interrupt automatically FIFO error forcing new already SETUP to be existing received RXIE or RXSTL has no effect 2 RXSETUP will be set control endpoints only CPU reads 00 NAK FIFO was FIFO future empty when causes FIFO transactio read Should error ns except always check SETUP RXFIF bits before reading 01 Received 01 FIFO not ready OUT token chg chg chg chg chg so data is ignored CRC or FIFO error not possible NOTE 1 These are sticky bits which must be cleared by firmware Also this table assumes RXEPEN and ARM are enabled 2 STOVW is set after a valid SETUP token is received and cleared during handshake phase EDOVW is set during handshake phase D 9 8x931AA 8x931HA USER S MANUAL intel Table D 3 Non isochronous Receive Data Flow in Single packet Mode RXSPM 1 Continued New RX RX RX FIF RX RX RX RX USB 1 0 Event D ERR ACK Void Setup an vi st Response Received 01 0 1 0 1 0 0 Set ACK Causes FIFO SETUP receive to reset token no interrupt automatically err
499. ve suspend is initiated on a downstream port when a SetPortFeature suspend command is received from the host via the USB bus Individual external ports or the internal port can be suspended by USB command however the hub cannot be suspended by command Refer to Universal Serial Bus Specification for more detail on the behavior of selective suspend in the USB system USB requirements state that the host can suspend the embedded function by issuing a SetPort Feature PORT SUSPEND request to the hub s port 1 Since the hub and function share hard 7 26 intel USB HUB ware such as the SIE it is not possible to simply shut off the clock to all circuitry associated with the function when the hub is to remain operational When placed into the suspended state the embedded function must behave as if it were connected to a hub whose actual downstream port was suspended This means that the embedded function must not respond to SOFs or any normal bus traffic This is done automatically by hardware Firmware should place any external circuitry associated with the embedded function in a low power state if one exists The embedded function should remain in this suspended state until the host initiates a ClearPortFeature PORT_SUSPEND or a SetPortFeature PORT_RESET re quest to the hub or until a remote wake up is signaled by the embedded function via an external interrupt 7 7 HUB POWER DISTRIBUTION USB hubs can supply a specified amount of p
500. vent If a remote wake up device signals a resume on a downstream port when the hub is in the suspend state see Figure 7 13 the following process occurs 1 The resume signaling causes the hub to wake up 7 25 8x931AA 8x931HA USER S MANUAL intel 2 The repeater then establishes a connection from the port with the resume signal to the root port and all other enabled downstream ports 3 The connectivity is then changed to downstream only from the root port to all enabled downstream ports This allows the host to drive the resume signaling downstream to the rest of the USB bus NOTE The 8x931HA hub cannot request a remote wake up although its embedded function can For this to happen the HRWUPE bit must be set in HSTAT and the embedded function must be enabled The embedded function triggers the remote wake up by setting the RWU bit in PCONI Root Port Root Port Root Port g 2 2 E a a Disabled Disabled Disabled Port2 Port3 Port 4 Port 5 Port 2 Port3 Port4 Port 5 2 Port3 Port 4 Port 5 Suspended Hub Resume Downstream with Resume Port 2 Connectivity Port 2 Connectivity A5257 01 Figure 7 13 Resume Connectivity 7 6 2 2 Connectivity Due to Physical Connect Disconnect If a disconnect is made to a disabled port and the hub is in a global suspend state a resume state is signaled as described in Resume Connectivity on page 7 25 7 6 2 3 Embedded Function Suspend and Resume Selecti
501. w if RCLK 1 or TCLK 1 Figure 10 12 T2CON Timer 2 Control Register 10 17 intel 1 1 Serial I O Port intel CHAPTER 11 SERIAL I O PORT The serial input output port supports communication with modems and other external peripheral devices This chapter provides instructions for programming the serial port and generating the se rial I O baud rates with timer and timer 2 11 1 OVERVIEW The serial I O port provides both synchronous and asynchronous communication modes It oper ates as a universal asynchronous receiver and transmitter UART in three full duplex modes modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates The UART supports framing bit error detection multiprocessor communi cation and automatic address recognition The serial port also operates in a single synchronous mode mode 0 The synchronous mode mode 0 operates at a single baud rate Mode 2 operates at two baud rates Modes 1 and 3 operate over a wide range of baud rates which are generated by timer 1 and timer 2 Baud rates are detailed in Baud Rates on page 11 10 The serial port signals are defined in Table 11 1 and the serial port special function registers are described in Table 11 2 Figure 11 1 is a block diagram of the serial port For the three asynchronous modes the UART transmits on the TXD pin and receives on the RXD pin For the synchronous mode mode 0
502. ware should set the PD bit to enter the suspend mode Cleared by hardware when a resume occurs See Figure 14 2 on page 14 4 Firmware should prioritize GRSM over GSUS if both bits are set simultaneously C 36 REGISTERS PSW Address DOH Reset State 0000 0000B 7 0 CY AC FO RS1 RSO OV UD P Bit Bit Number Mnemonic Function 7 CY Carry Flag The carry flag is set by an addition instruction ADD ADDC if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by logical bit bit move multiply decimal adjust and some rotate and shift instructions 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00 07 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed varia
503. which must be cleared by firmware 2 TXFIF TXOVF and TXURF are handled with the following golden rule Firmware events cause status change immediately while USB events only cause status change at SOF TXOVF Since overrun can only be caused by firmware TXOVF is updated immediately TXURF Since underrun can only be caused by USB TXURF is updated at SOF TXFIF TXFIF is incremented by firmware and decremented by USB Therefore writes to TXCNT will increment TXFIF immediately However a successful USB transaction anytime in a frame will only decrement TXF IF at SOF TXERR TXACK and TXVOID can only be caused by USB thus they are updated at the end of every valid transaction 3 NOTE This table assumes TXEPEN are enabled D 7 8x931AA 8x931HA USER S MANUAL Table D 3 Non isochronous Receive Data Flow in Single packet Mode RXSPM 1 New RX RX RX FIF RX RX RX RX USB 1 0 Event i D ERR ACK Void Setup r Kod peo Response Comments 00 Received 00 no no 1 no no no None NAK FIFO not ready OUT token chg chg chg chg chg but RXIE 0 Received 00 FIFO not OUT token loaded Write but timed out pointer waiting for reversed data Received 01 Set Received no OUT token receive errors advance no errors interrupt write marker Received 00 Set Time out Write pointer OUT token receive reversed data CRC or interrupt Possible to bi
504. xternal memory accesses external program memory and external data memory see Chapter 15 External Memory Interface External program memories utilize sig nal PSEN as a read strobe Accesses to external data memory use RD read or WR write to strobe the memory During instruction fetches external program memory transfer instructions with 16 bit addresses External data memory transfers use an 8 bit or 16 bit address bus depending on the instruction Table 9 3 lists the instructions that can be used for these bus widths Table 9 3 Instructions for External Data Moves Bus Width Instructions 8 MOVX Ri A MOVX A Qi 16 MOVX DPTR A MOVX A DPTR Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle The Port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This occurs when the MOVX DPTR instruction is executed During this time the Port 2 latch the special function register does not have to contain 1s and the contents of the Port 2 SFR are not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cycle If an 8 bit address is being used MOVX Ri the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle In t
505. xx00 0xx00000 XXXXXXXX Oxxx 0100 00xx1000 XXXX XXXX E8 HIFLG XXXXxx00 EO ACC EPCON RXSTAT RXDAT RXCON RXFLG RXCNTL 00000000 00d1 OdOd 00000000 XXXXXXXX Oxx0 0100 00xx1000 XXXX XXXX D8 PCON1 x000 DO PSW SOFL SOFH HPINDEX HPSC HPSTAT 00000000 00000000 00001000 Xxxxx000 xxx00000 100d 00007 C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 HPCON 00000000 Xxxx 00 00000000 00000000 00000000 00000000 XXxxx000 CO FIFLG xx00 0000 B8 IPLO SADEN x0000000 00000000 IEN1 IPL1 IPH1 IPHO 11111111 0000 0000 0000 0000 0000 0000 x0000000 A8 IENO SADDR HSTAT 00000000 00000000 0000 0000 Table C 1 8x931HA SFR Map AO P2 HIE FIE 11111111 XXXxxx00 xx00 0000 98 SCON SBUF HPPWR 0000 0000 xxxxxxxx xx00001x 90 P1 HADDR 11111111 00000000 88 TMOD TLO TL1 THO TH1 FADDR 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80 PO SP DPL DPH PCON 11111111 00000111 00000000 00000000 001d 0000 0 8 1 9 E For EPCON TXCON TXDAT TXCNTL and RXCNTL the reset value depends on the endpoint pair 2 A 3 B MCS 51 microcontroller SFRs Endpoint indexed SFRs 4 C 5 D 6 E 7 Port indexed SFRs selected Refer to the register definition tables in Appendix C or Chapter 5
506. ycles code fetch data read and data write The external bus struc ture is the same as for MCS 51 microcontrollers The upper address bits A15 8 are on port 2 and the lower address bits A7 0 are multiplexed with the data D7 0 on port 0 Normally two program fetches are generated during each machine cycle even if the instruction being executed doesn t need more code bytes the CPU simply ignores the extra fetch and the Program Counter is not incremented If the Program Memory is external then the Program Memory read strobe PSEN is normally activated twice per machine cycle If access to external Data Memory occurs two PSEN s are skipped This is a result of the address bus and data bus being used for Data Memory access NOTE A Data Memory bus cycle takes twice as much time as a Program Memory bus cycle When the CPU is executing from internal Program Memory PSEN is not activated and pro gram addresses are not emitted However ALE continues to be activated twice per machine cycle and is available as a clock output signal Note that one ALE is skipped during the execution of the MOVX instruction ALE oo BE e M __ Port 0 7 0 INSTRIN A7 0 Port 2 A15 8 A15 8 A5359 01 Figure 15 2 External Code Fetch 15 3 8x931AA 8x931HA USER S MANUAL intel ALE PSEN RD Port 0 A7 0 from RI or DPL ey Datan A7 0 from PCL In

8x931AA, 8x931HA Universal Serial Bus Peripheral

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