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Nios II Embedded Evaluation Kit, Cyclone III Edition User Guide

1. Table 1 1 List of Example Applications Part 2 of 2 Demonstration Vendor uC GUI Demonstration Micrium Photo Frame PlanetWeb PlanetWeb SpectraWorks GUI Demonstration by PlanetWeb PlanetWeb DAVE 2D Graphics Demonstration TES Altia Red HMI Altia Altia Blue HMI Altia Imagem aPhone Imagem Imagem 2 D Demonstration Imagem Imagem Instrumentation Imagem SLS uClinux SLS PlanetWeb Menu PlanetWeb This user guide describes how to start using the Altera Nios IT Embedded Evaluation Kit including unpacking the kit installing required software and running the Application Selector utility and other design examples This user guide addresses the following topics W How to set up power up and verify correct operation of the Nios II Embedded Evaluation board W Nios II standard processor system for the Embedded Evaluation board How to install the Nios II Embedded Evaluation Kit Cyclone III Edition How to install the Altera Quartus II Web Edition software How to start and run the Application selector utility Design examples Taking the next step Frequently asked questions For a full description of the development boards and their design and use refer to the Cyclone III FPGA Starter Board Reference Manual and LCD Multimedia HSMC Reference Manual This user guide provides an overview of some of the applications For more information about key hardware components and the structure of the app
2. it inspects the flash file on the SD Card If the flash file contains an SO record on its first line which contains a 32 bit ASCII encoded number it is considered to be a valid timestamp tag The Application Selector then scans the flash catalog for entries which contain a matching timestamp If a matching timestamp value is found then it means the desired hardware image is already stored in flash and can be used to directly reconfigure the FPGA without first copying it from the SD Card into the flash For details on the flash catalog refer to the section below titled Flash Hardware Image Catalog Flash Hardware The flash hardware image catalog is a simple database which keeps track of what application hardware images are currently stored cached in Image Catalog flash The flash catalog is located in sector 1 of the flash at offset 0x8000 and is 0x8000 32K bytes long The catalog mechanism uses a scheme referred to as Zero Spent F Available or ZSFA This scheme avoids erasing entire flash sectors when only a few words need to be written to the flash Using ZSFA a word in the flash which is 0x0 is considered spent and cannot be used to store data A word which is OxFFFFFFFF is available since it is in its erased state Every other value is considered a valid entry in the catalog The way ZSFA works is that whenever a catalog entry needs to be read the sector is scanned from its lowest address until the first OXFF
3. Application Selector sse C 1 Rebuilding the Application Selector from Source Files Boot COG 5 25s lille nio eed d Ee EOS Hardware Image Catalog Application Selector Hardware Image Application Selector Software Image Combining factory recovery image files i Appendix D Frequently Asked Questions Whyismy SOF time limited i eene tet tete citi tetra rt ee Lema esee da co ad D 1 What are Ready to Run Demonstrations iii Where can I find Ready to Run Demonstrations What is in a ready to run demonstration ii D 2 How do ready to run demonstrations get loaded from the SD card to the FPGA D 2 Where can I get more ready to run demonstrations iii D 2 Where can I get full Quartus II projects and source code for ready to run demonstrations sist tstes tentantan renra etin etin e tenere nenne eins sense rn nennt D 2 Altera Corporation iv July 2010 Contents Why do I get the error Can t find valid feature line for core SD MMC SPI CORE EC11 0002 in current license Error Error 10003 Can t open encrypted VHDL or Verilog HDL file when I try to re generate the Nios II Standard hardware design sss D 3 Where can I get the SD Card Controller IP License see How do I add pictures
4. important such as the steps listed in a procedure Mee Bullets are used in a list of items when the sequence of the items is not important Y The checkmark indicates a procedure that consists of one step only Is The hand points to information that requires special attention A A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or the user s work A A warning calls attention to a condition or possible situation that can cause injury WARNING to the user e The angled arrow indicates you should press the Enter key Sa The feet direct you to more information on a particular topic Info iii Altera Corporation July 2010 Additional Information Typographic Conventions Altera Corporation Info iv
5. in system update using SD Card remote system update using Ethernet IP licenses required to ship design W SD MMC SPI Core IP with FAT file system from El Camino W Triple Speed Ethernet MAC Core license from Altera W Nios IT IP evaluation license with Nios II EDS shipping license from Altera E DDR SDRAM memory controller core shipping license from Altera comes free with Quartus II Subscription edition About the Nios Il 3C25 Video Processor CPU Platform The CPU platform for the Nios II Standard System consists of Nios II f cpu core JTAG Debug Port 32KB Instruction Cache 32KB Data Cache Altera Corporation 3 4 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Where to find the Nios Il Processor Systems System Functions PLL The PLL accepts the global input clock source from the 50 MHz on board oscillator and generates the following clocks e 100 MHz CPU Clock 100 MHz SSRAM Clock 66 5 MHz DDR SDRAM Clock 60 MHz Peripheral Clock slow peripherals 40 MHz Remote System Update Clock System Clock Timer General purpose system timer Performance Counter Counter used for debug and system performance analysis System ID Used to sync the hardware system generation with the software generation tools Remote System Update Block Used for automatic configuration at boot time from the on board active parallel flash The Nios II processor writes reset address of the hardware system stored in flash f
6. the next section describes what is necessary to support a 5 6 5 pixel format For more information about the video pipeline and LCD controller refer to AN527 Implementing an LCD Controller The Nios II Standard System is designed to use a 32 bit 0 R G B data format Suppose you wanted to change the entire display subsystem to work with 16 bit 5 6 5 pixels instead of 32 bit 0 R G B pixels This can be accomplished with a few simple steps 1 Copy the Nios II Standard System into your own project directory 2 Create a new Verilog module called pixel converter 565 starting from the Verilog in altera avalon pixel converter v modify this Verilog so it has a 16 bit data in port and a 24 bit data out port AII the other ports remain the same You create the data out value by inserting 8 new bits 3xR 2xG and 3xB at the right points in the 16 bit word to pad it to a 24 bit word You can use either zero or LSB padding 3 Import your Verilog module into SOPC Builder using the Component Editor 4 From an Nios II Standard System replace the existing Pixel Format Converter with your new pixel converter 565 component A 2 Nios Il Embedded Evaluation Kit Cyclone III Edition Creating a new 5 6 5 Pixel Format component 5 Edit the data format adapter named lcd_64_to_32_bits_dfa Change its Output Interface Parameters Data Symbols Per Beat from 4 to 2 e This changes its width adaptation from 64 gt 32 to 64 716 e Rename it
7. Application Selector Menu Cyclone III Embedded Evaluation Kit Application Selector L Altera Picture Viewer X Altera Mandelbrot c2H X Altera Web Server Altera Spinning Cube 5 Imagem Taquin Game toed J stow into Hot Connected E ter fi le _ UE ERE Think Embedded 2 Select the Pic Viewer option by touching it in the application selector menu 3 Touch the Load button located on the bottom left corner of the Touch Screen to load the Pic Viewer application You will see the progress bar on the screen See Figure 5 2 5 3 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples Figure 5 2 Loading the Picture Viewer Application Cyclone III Embedded Evaluation Kit Application Selector EX IL 3 3 7 N 4 After loading the Pic Viewer application you will see the a slide show of pictures stored on the SD card Figures 5 4 shows the first image stored on the SD card The miniature view on the bottom right corner shows the next image of the slide show Figure 5 3 Running the Picture Viewer Application Displaying First Image 5 The next image will be displayed after the delay period See Figure 5 4 Altera Corporation 5 4 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Picture Viewer Application Figure 5 4 Running the Picture Viewer Application Show Hide Buttons Reverse Decrease Increase Sec S
8. Camino B NiosILIP from Altera BH DDRSDRAM memory controller core from Altera Design Examples Altera Corporation July 2010 Software and middleware licenses required to ship design n MicroC OS II real time operating system from Micrium LS For more information on how to obtain evaluation or shipping licenses for the above refer to Licensing the IP on page 1 11 The picture viewer application takes JPEG images or bitmaps stored on the SD Card and displays them on the LCD Touch Panel The Nios II CPU decodes the images and stores the pixels in a video buffer in DDR SDRAM A Scatter Gather DMA is used to transfer pixel data from the video buffer to the video pipeline LS You can customize the picture viewer application s image selection by adding your own images in to the folder on the SD Card entitled images Operation The Picture Viewer application displays a new picture on the LCD screen after a settable delay 1 2 3 4 5 10 15 20 seconds If decoding the image takes longer than this delay time then the image is displayed as soon as it has been decoded The image is scaled to optimally fit the LCD screen The operation of Picture Viewer application is explained below 1 Power on the board by pressing the switch SW1 You will see the Application Selector menu on the LCD Touch Screen Display See Figure 5 1 5 2 Nios Il Embedded Evaluation Kit Cyclone III Edition Picture Viewer Application Figure 5 1
9. Cyclone III FPGA starter development board includes integrated USB Blaster circuitry for FPGA programming IS The USB Blaster driver software is provided with the Quartus II software installation Communication between the host computer and the development board requires that the USB Blaster driver software be set up Power U p the To power up the development board perform the following steps Deve l op ment 1 Ensure that the red on off switch SW1 on the back side of the Board development board is in the OFF position up 2 Connect the USB Blaster cable from the host computer to the USB Blaster port on the development board 3 Connect the 12 V DC adapter to the development board and to a power source Only use the supplied 12 V power supply Power regulation circuitry on the board could be damaged by supplies greater than 12 V CAUTION 4 Press the Power Switch SW1 5 A Welcome screen appears as shown in Figure 2 1 Altera Corporation 2 2 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Power Up the Development Board Figure 2 1 Development Board Setup Welcome Screen Cyclone Ill 2 ter CO ee p s Think Embedded 2 3 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Development Board Setup Altera Corporation 2 4 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition N DTE RYA 3 Nios Il Processor Systems The board in
10. II C to Hardware C2H acceleration tool was used to take working software code and automatically generate the hardware accelerators that provide this performance improvement There are two processes at play here 1 The calculation of the Mandelbrot Set to generate pixel data 2 The rendering of the pixel data on the LCD screen Traditional processors will perform these functions purely in software Options available to increase throughput once the processor and clock frequency are selected are extremely limited The unfortunate trade off of porting the entire application to a faster processor is the increase in cost and power The Nios II Embedded Evaluation kit features not a traditional processor but a Nios II based FPGA and using automated hardware acceleration The Nios II C to Hardware C2H Acceleration Compiler takes standard ANSI C code in this case the Mandelbrot algorithm and automatically generates hardware accelerators In the hardware accelerated version of the design the Nios II processor handles common video functions such as the rendering the image panning zooming etc The hardware accelerator concentrates on generating the pixels by computing the Mandelbrot function all in time for the next frame You can use the demonstration to observe the differences between a general purpose processor executing software and a group of hardware accelerators performing the same functionality When comparing the software only version
11. Install Directory examples application selector application utilities app selector boot code 3 Runthe command make This section discusses the parts of the Application Selector you can modify in order to tailor the utility to your needs Changing the CFI flash map If your application needs to use the CFI flash in a particular manner which is not compatible with the Application Selector s default flash layout you can modify the way some things are mapped in flash fairly easily General Guidelines If you choose to modify the flash map take great care in ensuring that you leave enough space in each block for the data you intend to store there Otherwise you may overlap sections and the Application Selector utility may overwrite important data and cause a failure Also it is a good idea to completely erase the flash before altering the flash map This will prevent stale unused data from accidentally causing errors in the Application Selector Utility Application Selector Hardware Image One of the flash layout restrictions with the Application Selector is that the Application Selector hardware image itself must reside at byte offset 0x20000 in flash It cannot be changed This is because the Cyclone III FPGA always performs its first configuration after reset from offset 0x20000 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Altera Corporation July 2010 Application Hardware
12. Mandelbrot Application unici alia 5 6 Altera Corporation iii July 2010 Contents Contents Using the Mandelbrot application s sies aiaiai 5 7 Operation Application Selector siii i aaa nl 5 13 About the Embedded Web Server seen nnne e nennen 5 14 Appendix A Video Pipeline Data Flow Introduction isso ai EE A LIA LEA ei reina ioni A 1 Get the full LCD controller Application Note iii A 2 Creating a new 5 6 5 Pixel Format component iii A 2 Appendix B Application Selector Details SD Card isla B 1 Application Files 4 entente ea B 1 SD Card Directory Structure sioni iie ect eli B 1 CFI Flash Hardware IMaAgES mrsa aaa aaa Software Images axis ccs osse te ii rei n tere oie vost tres ie beiden bee tienes Application Boot Code Hash Hardware Image Catalog pere ite teet irt etes cui B 3 Hardware Image Caching derriere eter i i dette a EE EYED RARE RU NT Sea N Flash Hardware Image Catalog Creating Your Own Loadable Applications i B 6 Rebuilding the Application Selector ii B 7 Create a BSP Build the project ila Build the boot code nennen asioita ra nns e rhet rn erstens tense t nnt nn nennen Modifying the Application Selector Changing the CFI flash map eee Appendix C Restoring the Factory Image Restoring the Original Flash Image
13. Nios Il Embedded Evaluation Kit Cyclone III Edition 4 Application Selector Utility JN DERYA Overview Running the Application Selector Altera Corporation July 2010 The application selector is the default utility that boots up on power on and allows users to quickly select load and run different ready to run applications or demonstrations stored on an SD Card using the LCD touch panel An application consists of a FPGA hardware image and an application software image When you select an application the application selector copies these images from the SD Card to the Flash memory and reconfigures the FPGA with your selection Ready to Run SD Card Demonstrations In addition to the prepackaged ready to run SD Card demonstration applications which come with the Nios II Embedded Evaluation Kit Cyclone III Edition more are available from Altera or through third party vendors I gt You can find several ready to run SD Card demonstrations in your SD Card as well as in the lt install dir gt factory_recovery sdcard_contents altera_eek_applications folder Even more ready to run SD Card demonstrations and designs examples are available form the Nios II Embedded Evaluation Kit User Community Wiki page Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications on page B 6 This section describes the general op
14. and shift these up to the new decimal offset ci ci lt lt 28 cr cr lt lt 28 while xsqr ysqr lt 0x0400000000000000LL amp amp iter lt max_iter xsqr x x ysqr y y y 2 x y ci gt gt 28 x xsqr ysqr cr gt gt 28 iter t return iter Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples The implementation is fixed point with all values pre scaled by 0x10000000 The loop will continue until the number of iterations reaches max_iter or x y converges to the value of 4 This function is called for each pixel so for this design that would be 384000 times since the screen resolution is 800x480 The value of iter is used as the index into the color palette which picks the color of the pixel displayed on the screen Even though the main processor supports dynamic branch prediction and contains cache memory this operation of filling the screen can be very time consuming The approach taken for the C2H accelerated version is to offload this algorithm to pipelined and parallel hardware Each Mandelbrot engine contains dedicated multiply addition and subtraction logic to perform multiple operations in parallel Each Mandelbrot accelerator operates on a quarter of the frame and is only called once per frame The workload is distributed on a pixel basis so each accelerator handles every fourth pixel Figu
15. drive chiptrip gdf file Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier Altera Corporation Info ii Typographic Conventions Visual Cue Meaning 1 2 3 and Numbered steps are used in a list of items when the sequence of the items is a b c etc
16. gt _hw flash These are the application files you will put on the SD Card 6 Now create file named info txt in the same directory Is This is the file which will be displayed in the Application Selector when the Show Info button is pressed for your application Fill info txt with some descriptive text about your applications operation 7 Create anew subdirectory and name it what you would like the title of your application to be shown as in the application selector 8 Copy both flash files and info txt into the new directory 9 Using an SD Card reader copy the directory onto an SD Card into a directory named Altera_EEK_Applications The directory structure on the SD Card should look like this Altera_EEK_Applications lt Name of Application gt lt elf name gt _sw flash lt sof_name gt _hw flash info txt 10 Place the SD Card in the Nios II Embedded Evaluation Kit Cyclone III Edition board and switch on the power The Application Selector will start up and you will now see your application appear as one of the selections This section describes how to rebuild the Application Selector utility from source code using the Nios II Software Build Tools If you are new to developing software on the Nios II processor it is recommended that you first go through the tutorial My First Nios II Software Tutorial This will walk you through compiling a simple project that runs on the Nios ITS Throughout this documen
17. of Nios II Embedded Evaluation Kit Why is my SOF time limited Several IP cores in the example designs Nios II processor core DDR SDRAM memory core TSE MAC core are evaluation versions available as OpenCore Plus IP cores OpenCore Plus hardware evaluation supports the following two modes of operation e Tethered requires a JTAG connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely Untethered the design runs for a limited time To generate non time limited SOF files you will need to purchase shipping licenses for any OpenCore Plus IP cores in your system Contact your local sales offices to purchase the license http www altera com corporate contact con index html What are Ready to Run Demonstrations Ready to run demonstrations are binary flash files of processor systems that can be programmed to flash or selected and loaded from the LCD touch panel Ready to run demonstrations provide a quick and easy way to evaluate Nios II based processor systems built for applications such as automotive graphics industrial controls consumer graphic user interfaces and more Most ready to run demonstrations have been provided by Altera s partners and showcase IP operating systems and software tools Where can find Ready to Run Demonstrations For the Nios II Embedded Evaluation Kit NEEK there are
18. or SLS s port of uC Linux for Nios II a particular IP core for example SD Card core or high performance vector graphics engine middleware libraries for example Networks Stacks Graphics Library or graphics development tools for example PlanetWeb SpectraWorks Altia Design then the ready to run demonstrations help you make your evaluation process easy Ready to run demonstrations are provided in binary format only flash full Quartus II projects source code and IP licensing and can be obtained by contacting the provider of the ready to run demonstrations You can locate these demonstrations on your SD Card Alternatively you can download the latest ready to run demonstrations from the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page To add ready to run demonstrations to your SD Card download the demonstration and copy it to your SD Card in the Altera_EEK_applications folder Table 1 1 list ready to run demonstration applications Table 1 1 List of Example Applications Part 1 of 2 Demonstration Vendor Application Selector Web Server Altera Altera Picture Viewer Altera Altera Mandelbrot C2H Altera Altera Spinning Cube Altera Imagem Tacquin Game Imagem Imagem Watch Imagem Imagem Avionics Imagem Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Getting Started About this User Guide Altera Corporation July 2010
19. pins so that the pixel stream appears on the display The DMA controller fetches pixel data from the in memory frame buffer and drives itin row major raster order on its streaming output port and through the video subsystem pipeline to the sync generator termination The system has a FIFO because all systems like this always have FIFOs It s there to take up the slack and keep the display fed even when the DDR SDRAM memory is unavailable due to contention refresh etc Get the full LCD controller Application Note Creating a new 5 6 5 Pixel Format component Altera Corporation July 2010 The Pixel Format Converter subsystem assumes that the frame buffer is storing 32 bit pixel values in 0 R G B 8 8 8 8 format The sync generator however accepts 24 bit values So the Pixel Format Converter takes in a stream of 32 bit 0 R G B pixels and produces a stream of 24 bit R G B values This is done by throwing away the unused 8 bits Once the Pixel Format Converter has produced a stream of 24 bit 8 8 8 R G B values the data format adapter serializes the data into a stream of 8 bit R then G then B values This is the input to the sync generator block which produces the horizontal and vertical timing signals The video pipeline used in the Nios II Standard System is just one implementation for video systems FPGAs give you the power of flexibility to change this with just a few lines of code For example
20. so the Picture Viewer Application can find them D 3 How do I add my own design so the Application Selector can find and run it D 4 Where do I go to get more designs for the Nios II Embedded Evaluation Kit How do I open a design example in the Nios II IDE sse How do I restore the factory image ssssssssseeeeneeeeneneenenen eene How do I re build the factory image sse nennen nnne D 5 Additional Information Further Information e iti v Altera Corporation July 2010 Contents Contents Altera Corporation vi July 2010 N E RYAN 1 Getting Started introduction The Altera Nios II Embedded Evaluation Kit Cyclone III Edition includes a full featured FPGA development board LCD Multimedia High Speed Mezzanine Card HSMC hardware and software development tools documentation and accessories needed to begin embedded and system on a programmable chip SOPC designs using FPGAs The development board includes an Altera Cyclone III FPGA and comes preconfigured with an FPGA hardware reference design stored in flash memory as well as several ready to run demonstration applications stored on the SD Card Flash provided Hardware designers can use the FPGA reference design as a platform to build complex embedded systems Software developers can use the hardware reference design plus sample software applications a
21. to lcd 64 to 16 bits dfa 6 Regenerate your system Your software application is now responsible for filling the frame buffer with aligned 16 bit 5 6 5 pixel data and the firmware which controls the DMA must be modified to understand the different memory buffer size implications of 16 bit instead of 32 bit pixels A 3 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone Ill Edition July 2010 Altera Corporation A 4 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Appendix B Application JN OS RYA Selector Details SD Card Application Files SD Card Directory Structure Altera Corporation July 2010 This section describes some details about the operation of the Application Selector The Application Selector uses the SD Card for storing applications and data used by these applications such as the pictures used by the picture viewer or the HTML pages used by the Web Server application The SD Card must be formatted with the FAT 16 file system and can be any capacity up to 2GB Long file names are supported Each loadable application consists of two flash files and an optional text file all stored on an SD Card The first flash file represents the software portion of the example and must be derived from an ELF file as described in the section of this document titled Creating Your Own Loadable Applications This flash file can be named anything supported by the FAT16 file system t
22. up web pages to enable the remote system update capability The way this works is as follows WB When your kit is connected to a network the application will serve up a web page US The HTTP server looks for content contained in the webserver html directory at the top level of the SD card Though default content is provided the server will read any valid files that are placed into this directory m If DHCP is available the application will attempt to obtain an IP address from a DHCP server Otherwise a static IP address defined in web server h will be assigned after a time out M The server can process basic requests to serve HTML JPEG and GIF files from the Altera FAT file system on an SD card The embedded web server is in no way a complete implementation of a full featured HTTP server This example uses the sockets interface To learn more about the application selector with embedded web server refer to the source code and design example in the install dir examples application selector folder A good introduction to sockets programming is the book Unix Network Programming by Richard Stevens Additionally the text Sockets in C by Donahoo amp Calvert is a concise and inexpensive text for getting started with sockets programming Altera Corporation 5 14 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Appendix A Video Pipeline ANO E RYA E Data Flow Introduction Altera Corporation July
23. with the software plus hardware accelerators you should expect to see a 250 times speed improvement between the software and hardware in the image rendering Using the Mandelbrot application The Mandelbrot application utilizes the LCD and touchscreen for all user interactions When the application starts you will be prompted with a blue welcome screen that you must touch to continue The operation of Mandelbrot application is explained below 1 Power on the board SW1 You will see the Application Selector menu on the LCD Touch Screen Display 5 7 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples 2 Select Manelbrot Application by choosing it in the application selector menu via the LCD touchscreen 3 Touch the button marked Load The LCD Touch panel display begins loading the Mandelbrot C2H application as shown in Figure 5 5 Figure 5 5 Loading the Mandelbrot Application Cyclone III Embedded Evaluation Kit Application Selector bra Viowrar O 5 Imagem Taquin Game v ogo EZB 4 After complete loading of application you will see a welcome screen as shown in Figure 5 6 Altera Corporation 5 8 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Mandelbrot Application Figure 5 6 Welcome Screen of Mandelbrot Application Press anywhere on the screen to c e menu to make operation mode changes 5 When you tap the touchscreen t
24. 2010 The video display subsystem embodied in the Nios II Embedded Evaluation Kit designs was intentionally designed to be modular amp flexible to make customizing a snap The design style used for the video pipeline highlights the use of several simple microcores which can be configured or customized for other video applications The video subsystem consists of these operational components in roughly logical order A frame buffer which happens to reside in DDR SDRAM memory A memory to stream DMA controller which reads memory 64 bits at a time and produces a stream of 64 bit data values A width data format adapter to break the 64 bit stream into sequential 32 bit pixel values A FIFO A Pixel Format Converter Another Data Format Adapter to produce a stream of 8 bit values A sync generator which you could think of as an LCD display PHY BERN w If you actually look at the design there are several other Avalon Streaming components in this flow These have been omitted from this discussion for clarity because they are not operational They are just timing adapters which allow the operational pieces to fit together properly Starting from the end of the chain The sync generator just takes a stream of 8 bit wide data values on its streaming input Three consecutive 8 bit values make a single color pixel R G B R G B An start of packet SOP pulse marks the start of each frame The sync generator drives external
25. 324 device should be detected fai If the device is not detected make sure your hardware is setup for USB Blaster using the Hardware Setup button 4 Double click on the File field and browse to Altera lt version gt kits cycloneIII_3c25_niosII factory_ recovery flash contents cyclonelII embedded evaluation kit ap plication selector sof I gt The SRAM Object File SOF contains a Nios II CPU which can access and program the on board flash 5 Clickon the Program Configure checkbox and press Start IS You will see a Successfully performed operation info message when the configuration is complete 6 Launch a Nios II Command Shell from Start gt All Programs gt Altera gt Nios II EDS lt version gt Nios II lt version gt Command Shell Rebuilding the Application Selector from Source Files Boot Code Altera Corporation July 2010 7 From the Nios II Command Shell change directory to altera version gt kits cycloneIll_3c25_niosII factory_recovery flash_contents 8 From the Nios II Command Shell program the factory image into flash by typing the command Nios2 flash programmer base 0x04000000 restore_cycloneIII_3c25 flash L gt Ifyou get the error message No CFI table found at address lt address gt Leaving target processor paused then check that either the address is correct i e hex four million six zeros after the 4 or that you have tow characters before the base 9 You should now
26. FFFFFF value is encountered Every non zero value encountered along the way is a valid catalog entry When a catalog entry needs to be written the sector is scanned until the first OXFFFFFFFF value is found and the new catalog entry is written to that offset To erase a catalog entry you scan for it in the sector then write 0x0 to it to mark it as spent The sector s containing the ZSFA catalog only need to be erased once enough data has been stored there that there are no more available entry spots available Each flash catalog entry consists of two sequential 32 bit words The first word is the 32 bit timestamp value of a hardware image which is currently in flash The second word is the 32 bit flash offset of the image itself Entries are always created and erased as whole units two 32 bit words at a time B 5 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Creating Your Own Loadable Applications Altera Corporation July 2010 It is easy to convert your own Nios II design into an application which is loadable by the Application Selector utility All you need is a hardware image a Cyclone III 3C25 SOF file and a software image which runs on that hardware a Nios II ELF file The only restrictions are 1 The SOF file must contain a CFI flash component 2 The SOF file must contain a Nios II CPU whose reset address is set to CFI Flash at offset 0x00000000 3 Thesize of the softwar
27. II Edition N E RYAN 2 Development Board Setup Featu res The Nios II Embedded Evaluation Kit features m Cyclone II Starter Board e Cyclone III EP3C25F324 FPGA e Configuration e Embedded USB Blaster circuitry includes an Altera EPM3128A CPLD allowing download of FPGA configuration files via the users USB port e Power and analog devices from Linear Technology e Memory e 256 Mbit DDR SDRAM e 1 Mbyte Synchronous SRAM e 16 Mbytes Intel P30 P33 flash e Clocking e 50 MHzon board oscillator e Switches and indicators e Six push buttons total 4 user controlled e Four user controlled LEDs W LCD Daughtercard e LCD Touch screen Display e 800 X 480 pixel size 10 bit VGA DAC Video Decoder 24 bit Audio Codec RS232 transceiver SD Flash 10 100 Mbps Ethernet Controller PHY Connectors e VGA Output Composite Video in Serial connector RS 232 DB9 port PS 2 Ethernet Connector RJ 45 SD Card Socket Altera Corporation 2 1 July 2010 Development Board Setup Re q u i reme nts If not already installed you should Mm Install the Quartus II Web Edition software on the host computer For more information refer to Installing the Ouartus II Web Edition Software on page 1 9 W Install the Nios II Embedded Evaluation Kit Cyclone III Edition For more information refer to Installing the Nios II Embedded Evaluation Kit Cyclone III Edition on page 1 7 M Install the USB Blaster driver software on the host computer The
28. Images The section of flash which is used to hold and cache loadable application hardware images can be adjusted The adjustments can be made by editing the file lt Install Directory gt examples application_selector software_examples app application_selector src app_selector h Edit the lines define AS_HW_IMAGE_OFFSET_START 0X640000 define AS HW IMAGE OFFSET END 0xDC0000 to reflect what section of flash you would like to use to hold and cache application hardware images Note that one hardware image consumes 0xC0000 bytes 6 flash sectors so ensure that AS_HW_IMAGE_OFFSET_END AS_HW_IMAGE_OFFSET_START is always greater than or equal to 0xC0000 The Application Selector will cache as many images in this section as it is able to fit For instance the default section is 0x780000 bytes in size 60 flash sectors so it is able to cache up to 10 loadable application hardware images Application Selector Software Image The default location of the Application Selector software image is flash offset 0x100000 This is necessary because flash offset 0x100000 is the reset address of the Nios II CPU in the Application Selector hardware image It s recommended that you do not change the location of the Application Selector software image because it also requires changing the reset vector of the Nios II CPU in the Application Selector hardware image and recompiling that design in Quartus II Applica
29. Nios Il Embedded Evaluation Kit Cyclone Ill Edition User Guide ANU S n AN 101 Innovation Drive San Jose CA 95134 www altera com P25 36209 03 Document Date July 2010 2010 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX are Reg U S Pat amp Tm Off and or trademarks of Altera Corporation in the U S and other countries All other trademarks and service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device speci fications before relying on any published information and before placing orders for products or services LS EN ISO 9001 Part Number UG 01025 1 2 ii Altera Corporation Nios Il Embedded Evaluation Kit Cyclone Ill Edition User Guide July 2010 N D TE PYN Contents Chapter 1 Getting Started Introduction Kit Contents About the Nios II Processor About the Nios II Standard Design About this User Gu
30. aluation Kit Cyclone III Edition Mandelbrot Application 5 11 e When hardware rendering is selected the benchmark data is updated every 5 frames e When software rendering is selected the benchmark data is updated every frame The benchmark data is displayed in the bottom right of the screen and it represents the instantaneous frames per second being rendered and displayed Consider the implications of what you have observed What one would traditionally do with an expensive power hungry GHz processor was just accomplished using an inexpensive Cyclone III FPGA running at 100 MHz Such is the power of hardware acceleration using FPGAs Operation The design performs panning and zooming on the complex plane which gives a video like effect Every time a new frame is rendered a new set of coordinates must be calculated These coordinates contain a center point zoom factor and maximum number of iterations Knowing the center point and zoom factor the top left point of the screen is then determine and passed to the Mandelbrot algorithm The maximum number of iterations is used to determine how much effort is spent per pixel before it is determined that the point is included in the Mandelbrot set these points appear as black pixels The pixel calculation is based on the following software segment inline int int_mandelbrot long long cr long long ci int max_iter long long xsqr 0 ysqr 0 x 0 y 0 int iter 0 go ahead
31. ard Figure B 1 SD Card Directory Structure C3 Altera EEK Applications gt My First Application my first_sw flash my first_hw flash info txt i My Second Application my_second_sw flash my_second_hw flash info txt The Application Selector uses the on board CFI flash to store several different things Table B 1 shows a map of how the different sections of flash are used by the Application Selector Hardware images CFI flash is used to store both the hardware image of the Application Selector itself as well as up to 10 hardware images of applications which are being loaded The Application Selector hardware image is permanently stored in flash at offset 0x20000 Hardware images for the applications being loaded get written to flash at load time to an offset between 0x580000 and 0xD00000 depending on caching Hardware image caching is described in more detail in the section titled Hardware Image Caching Software Images CFI flash is used to store the software images of both the Application Selector utility itself as well as software images of applications being loaded All software images used by the application selector contain a boot copier which is pre ended by the elf2flash utility during file conversion process described in the Creating Your Own Loadable Applications section The boot copier copies the software code to program memory before running it B 2 Nios II Embed
32. ard Processor System in the lt install dir gt examples standard folder Description Simple general purpose Nios II processor system targeted for the Nios II Embedded Evaluation Kit Cyclone III Edition to be used as a starting point for your embedded system development IP licenses required to ship design W Nios IT IP evaluation license with Nios II EDS shipping license from Altera MI DDR SDRAM memory controller core shipping license from Altera comes free with Quartus II Subscription edition as part of Altera IP Base Suite LS For more information on how to obtain evaluation or shipping licenses for the above refer to Licensing the IP on page 1 11 About the Nios Il 3C25 Standard Processor The Nios II 3C25 Standard processor is a general purpose processor system to be used as a starting point for your system design and contains Nios II f CPU PLL DDR SDRAM Memory Controller SSRAM Memory Controller CFI Flash Controller JTAG UART Remote System Update Performance Counter System Clock Timer High Resolution Timer LED PIO Button PIO Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Nios Il Processor Systems Nios Il 3C25 Video Processor System Location You can locate the Nios II 3C25 Video Processor System in the lt install dir gt examples video folder Description Video Ethernet and SD Card controller based processor system for LCD Color touch panel control
33. arious applications such as imaging graphics networking etc To aid in the learning process of software developer several design examples have been provided in source code form in the examples directory in the Nios II Embedded Evaluation Kit These designs are B Altera Picture Viewer B Altera Mandelbrot C2H W Altera Application Selector For each of these applications a basic overview and discussion of operation is given However much more detailed information can be found in the source code which is loaded after installing the Nios II Embedded Evaluation Kit The Nios II Embedded Evaluation Kit also contains more applications provided from third party vendors to showcase available graphics libraries and middleware that have been ported to the Nios II processor but these designs are shipped in binary format as ready to run demonstrations Full designs for the ready to run demonstrations may be obtained by directly contacting the provider of the demonstration in the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page Picture Viewer The picture viewer application is based on the Nios II 3C25 Video Processor System You can locate this application in the lt install dir gt demos picture_viewer folder Description Video and SD Card controller based processor system for LCD Color touch panel control for displaying JPEG and BMP images IP licenses required to ship design W SD MMC SPI Core IP with FAT file system from El
34. at i e in the form of application APP and board support package BSP D 4 Nios Il Embedded Evaluation Kit Cyclone III Edition If you would like to open these Nios II Software Build flow projects to the Nios II IDE for debugging purposes then you will import the app and bsp projects into the Nios IL IDE For step by step instructions on importing a Nios II Software Build flow project in to the Nios II IDE refer to the software tutorial My First Nios II Software Application in the documents tutorials software_tutorials folder of the Nios II Embedded Evaluation kit directory How do restore the factory image To restore the factory image perform the following steps 1 Using the Quartus II Programmer configure the FPGA with the SOF file altera version gt kits cycloneIII_3c25_niosII examples application_selector cycloneIII_embedded_ evaluation_kit_applicatoin_selector sof 2 Open a Nios II Command Shell and change to the directory altera lt version gt kits cycloneIII_3c25_niosII factory_recovery flash_cont ents 3 In the Nios II Command Shell program the factory image into flash with the command nios2 flash programmer base 0x04000000 restore cycloneIII 3c25 flash I gt Ifyou get the error message No CFI table found at address address Leaving target processor paused Check that either the address is correct hex four million i e 6 zeroes after the 4 or that you have two charact
35. ated SOPC Builder systems featuring the Nios II processor for example standard 2 System Design Examples These build upon hardware design examples and include applications and source codes that show examples of software device drivers operating system usage and application selector Demonstrations located in Install Dir Ndemos directory are pregenerated SOPC Builder systems for evaluation purposes only and are not guaranteed to be updated with each release of the Quartus II software When source code is provided recompiling a demonstration application from this directory may or may not work with the Quartus II 1 4 Nios Il Embedded Evaluation Kit Cyclone III Edition Kit Contents 1 5 version that was pointed to by the development kit documentation Any source code provided should be viewed as diagramatic but not necessarily functional Ready to run demonstrations are binaries that provide a quick and easy way to demonstrate and evaluate operating systems middleware IP and software tools for your Nios II processor system These demonstrations are easily selected and loaded using the application selector on your LCD touch panel These demonstrations are implementations of applications such as automotive graphics consumer GUI industrial control that are provided for demonstration and evaluation purposes by Altera and third party vendors If you want to select a suitable operating system for example Micriums uC OS II
36. be able to reset the board to start the application selector This section describes the process of rebuilding the factory recovery image from source files You may wish to modify and rebuild the factory recovery image you ve modified the application selector or boot code and would like a single recovery file which includes your modifications Keep in mind that any modifications you make to the application selector or boot code may make them incompatible with existing applications Each portion of the factory recovery image is described below with instructions on how to create it and program it to flash The last section here titled Combining factory recovery image files includes instructions for creating a single factory recovery image that you can program into flash at any time to restore the factory configuration of the Embedded Evaluation Kit board To perform the tasks illustrated in this section you must first open a Nios II command shell The first portion of the factory recovery image is the application boot code located at flash offset 0x0 Appendix B describes the functionality of the boot code and how to rebuild it from the source files Building the boot code produces a file named app_selector_boot_code srec This file can be directly programmed to flash using nios2 flash programmer in the Nios II command shell 1 From the Nios II Command Shell navigate to altera version gt cyclonellI 3c25 niosII examples app
37. ctor s Quartus II project directory The command needed to create the application selector hardware portion of the factory recovery image is From the Nios II Command Shell navigate to altera version gt kits cycloneIIl_3c120_niosII devNexamples application selector From the Nios II Command Shell type sof2flash activeparallel offset 0x20000 input cycloneIII_ embedded evaluation kit application selector sof output appsel hw flash The command above converts the application selector SOF file to hardware flash image To program this flash file to flash run the command nios2 flash programmer base 0x4000000 appsel hw flash Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Application Selector Software Image Combining factory recovery image files Altera Corporation July 2010 The final portion of the factory recovery image is the application selector software image This section is located at flash offset 0x100000 The Nios II processor resets to this address and runs this code every time the FPGA gets configured with the application selector hardware image The file you will need to create this portion of the factory recovery image is named ext_flash flash and is located in the application selector software project directory You need to run the following command from the application selector software project directory to create ext_flash flash if it does not already e
38. cumentation and design examples for the kit To install the Nios II Embedded Evaluation Kit Cyclone III Edition follow these steps 1 Download the Nios II Embedded Evaluation Kit Cyclone III Edition installer from the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page of the Altera website Alternatively you can request a development kit DVD from the Development Kits Daughter Cards amp Programming Hardware page of the Altera website 1 7 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone Ill Edition July 2010 Getting Started Altera Corporation July 2010 2 Follow the on screen instructions to complete the installation process The installation program creates the Nios II Embedded Evaluation Kit Cyclone III Edition directory structure shown in Figure 1 1 Figure 1 1 Nios Il Embedded Evaluation Kit Installed Directory Structure lt install dir gt The default Windows installation directory is C altera lt version gt kits cyclonelll_3c25_niosll board_design_files demos documents examples factory_recovery Table 1 2 lists the file directory names and a description of their contents Table 1 2 Installed Directory Contents Part 1 of 2 Directory Name Description of Contents board_design_files Contains schematic layout assembly and bill of material board design files demos Contains a repository of example designs that may be useful for demonstrat
39. ded Evaluation Kit Cyclone III Edition CFI Flash B 3 The Application Selector software image is permanently stored in flash at offset 0x100000 Software images for the applications being loaded get written to flash at load time to offset 0x180000 Software images must be smaller than 4MB or they will overwrite the application HW images located at offset 0x580000 Application Boot Code All applications which are loaded by the application selector must contain a Nios II CPU whose reset address is set to CFI flash at offset 0x0 For this reason a generic bit of boot code is permanently programmed at offset 0x0 in the CFI Flash as part of the factory recovery image This boot code is very small and only performs the following functions B Flushes the Nios II instruction cache W Flushes the Nios II instruction pipeline B Branches to offset 0x180000 Offset 0x180000 is where the application software image is located after being loaded by the Application Selector so when the FPGA is reconfigured the Nios II CPU executes this boot code which branches to the boot copier of the actual application software image which then copies the application to program memory then runs the application Il The Application Selector relies on a feature of the Cyclone III family of FPGAs called remote update The remote update feature allows the Nios II CPU to force the FPGA to reconfigure from a specific location in a parallel flash memory such as t
40. e design of choice using the application selector Details of the application selector can be found in the readme txt located in the application selector folder under examples in the Nios II Embedded Evaluation Kit directory To convert your own Nios II design into an application which is loadable by the Application Selector utility you will need the following 1 Ahardware image a Cyclone III 3C25 SOF file 2 Asoftware image which runs on that hardware a Nios II ELF file 3 AnSD Card reader For a step by step instructions refer to section in Appendix B of this document entitled Creating Your Own Loadable Applications Where do go to get more designs for the Nios Il Embedded Evaluation Kit For more information about the latest demonstrations available for download to your Nios IT Embedded Evaluation kit refer to the Nios II Embedded Evaluation NEEK Cyclone III Edition page You will be able to download the designs to your local drive and add them to your SD Card by placing them in the SD Card folder entitled Altera_EEK_Appliations The application selector should automatically detect these new designs and load them on to your kit How do open a design example in the Nios Il IDE Several example applications have been provided to you in source code form so that you can use them to learn how to develop your own software applications The example applications have been provided in the Nios II Software Build flow form
41. e image must be no larger than 4MB LS If you require a software image larger than 4MB refer to the section of this document titled Modifying the Application Selector Once you have your working SOF and ELF file pair perform the following steps to convert them to a loadable application selector compatible application 1 Copy both the SOF and ELF files into a common directory of your choosing This directory is where you will convert the files 2 Copy the script examples application selector application utilities flash file conversion script to the directory where you copied your SOF and ELF files Optionally copy it to a directory in the Nios II Command Shell search path i e lt nios2 install gt bin 3 Open a Nios II Command Shell and change to the directory where you copied the SOF and ELF files 4 Convert the ELF and SOF files by running the script eek sh lt elf file gt elf lt sof file gt sof The eek sh script runs the Nios II Command Line utilities sof2flash and elf2flash to convert the SOF and ELF files to application selector compatible FLASH files TS Feel free to open eek sh in a text editor to see the exact commands which are run B 6 Nios II Embedded Evaluation Kit Cyclone III Edition Rebuilding the Application Selector Rebuilding the Application Selector B 7 5 You will now see two new files in the directory lt elf file gt _sw flash and lt sof file
42. ec Play Stop Slide Show You can control the slide show as explained below 5 5 To display the next image before the delay time is finished touch the Forward button located at the right center of the touch panel To display the previous image touch the Reverse W button located at the left center of the touch panel To play or stop the slide touch the Play e Stop button On the top center of touch panel you will see the Delay period in Sec You can increase or decrease the delay period by touching the Plus d or Minus BW buttons respectively The maximum delay period you can set is 20 seconds The minimum is 1 second The default delay period is 5 seconds Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples Mandelbrot Application Altera Corporation July 2010 e Youcanhide the control buttons by clicking on the Hide button located at the top left corner of the touch screen To show the control buttons again touch anywhere on the LCD Touch panel e On the bottom right corner you will see the miniature view of the next picture being decoded in the background 6 Theslide show continues until you tap the Stop button 7 To return to the Application Selector menu press the Reconfigure push button switch on Cyclone III Starter Board This application is based on the C2H_Mandelbrot processor system You can locate this application in the
43. ed programming files and flash programming files Contact your local Altera representative or use the Altera Tools Support to order today You do not need a license if you are developing software with the Nios II IDE NicheStack TCP IP Stack Nios II Edition You can develop software for any of the Nios II development kits using the NicheStack TCP IP Stack Nios II Edition evaluation To generate software to run on other boards and or ship in a product you must obtain a license ordering code IPSW TCP IP NIOS Contact your local Altera representative or Altera Tools Support to order today Micrium MicroC OS II RTOS You can develop software for any of the Nios II development kits using the Micrium MicroC OS II RTOS To generate software to run on other boards ship in a product or both you must obtain a license To obtain a license for the Micrium MicroC OS II RTOS contact Micrium today Altera IP Base Suite A high performance memory controller for the on board DDR SDRAM memory is available from Altera Finite Impulse Response FIR Compiler Fast Fourier Transform FFT Compiler Numerically Controlled Oscillator NCO Compiler DDR SDRAM Controller DDR SDRAM High Performance Controller DDR2 SDRAM Controller DDR2 SDRAM High Performance Controller DDR3 SDRAM High Performance Controller QDRII SRAM Controller RLDRAM II Controller SerialLite II To help shorten your design time Altera provides some of its most popular inte
44. er W Multi port memory controllers 1 3 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Getting Started Altera Corporation July 2010 E Communication Interface controllers About the Nios Il System Designs A Nios II system design builds upon a Nios II processor system by including a software application that runs on the processor system Software developers can use system designs to see examples of software drivers for the hardware peripherals Nios II Embedded Evaluation kit contains several system design examples M Altera Application Selector B Altera Picture Viewer B Altera Mandelbrot C2H L Designs are located in the altera version gt kits cycloneIII_3c25_niosII in either the examples or demonstrations directory You can also find more system designs from the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page About the Demonstrations In the Nios II I Embedded Evaluation Kit directory there is a demos folder refer to Figure 1 1 on page 1 8 This is a repository of pre built example Nios II based processor systems that have been provided for demonstration and evaluation purposes only How are the demonstrations different from design examples Design examples located in the lt Install Dir gt examples folder are prebuilt processor systems that can be used as a starting point for your design 1 Hardware Design Examples Quartus II projects with pre gener
45. era IP and Software DVD Request Form page of the Altera website 2 Follow the on screen instructions to complete the installation process E f you have difficulty installing the Quartus II software refer to Quartus II Installation amp Licensing for Windows and Linux Workstations The Quartus II Web Edition software includes the following items Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Getting Started M The Quartus II software The Quartus II software including the SOPC Builder system development tool provides a comprehensive environment for system on a programmable chip SOPC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools eur lo compare the Quartus II subscription and web editions refer to Altera Quartus II Software Subscription Edition vs Web Edition The kit also works with the subscription edition W MegaCoreIP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions with the OpenCore Plus feature to do the following tasks e Simulate behavior of a MegaCore function in your system e Verify functionality of your design and quickly and easily evaluate its size and speed e Generatetime limited device programming files for designs that include MegaCore functions e Program a device and verify your design in hardware Le The OpenCore Pl
46. eration of the Application Selector utility There are a couple of ways the application selector can update your board E In system update via the on board SD Card E Remote System Update via Ethernet Application Selector Utility In system Update using SD Card In order to run the application selector and load and view demonstrations stored on the SD Card in system update follow the instructions below 1 Connect power to the Nios II Embedded Evaluation Kit board Cyclone III Edition 2 Switch on the power SW1 US If the board is already powered reset the board by pressing the button labeled RECONFIGURE The application selector will boot from flash and a splash screen will appear while the application selector searches for applications on the SD Card see Figure 4 1 3 Touch the application to highlight your selection IS If there are more than five applications on the SD Card you can scroll through the list by touching the scroll up and scroll down buttons on the right hand side of the screen 4 View Information about an application To get more information about a particular application highlight the application by touching it then touching the button labeled Show Info cS If there is additional information available for the application you highlighted a scrollable text window will appear To return to the main menu touch the button labeled OK 5 Load and Run an application When you ve selected t
47. ers before base 4 You should now be able to reset the board to start the Application Selector How do re build the factory image To re build the factory image refer to Appendix C Restoring the Factory Image D 5 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Altera Corporation D 6 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition NE Additional Information Revision Histo y The table below displays the revision history for the chapters in this user guide Chapter Date Version Changes Made All July 2010 1 2 e Removed Licensing the Quartus II Software section e Updated Figure 1 1 on page 1 8 e Updated Installing the Nios Il Embedded Evaluation Kit Cyclone III Edition on page 1 7 e Updated Installing the Quartus Il Web Edition Software on page 1 9 e Updated Further Information on page iii e Updated Table B 1 on page B 4 e Updated Application Hardware Images on page B 10 and Application Software Image on page B 10 e Updated Copyright information All August 2008 1 1 e Second publication All November 2007 1 0 e First publication How to Contact For the most up to date information about Altera products refer to the following table Altera Information Type Contact Vote 1 Technical support www altera com mysupport Technical training www altera com training Technical traini
48. erver html From any PC you can view this web page by simply typing the correct IP address on a web browser By following the instructions displayed on the HTTP forms on the web page you can browse to and load a design stored on the local PC and program it to the flash on your board You can then reset the FPGA on your board and the FPGA should reconfigure from the newly downloaded Flash image 4 3 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Application Selector Utility Altera Corporation July 2010 Requirements 1 A host PC with a connection to a working Ethernet port 2 A separate working Ethernet port to connect your board to 3 Flash files for hardware and software image to update the board with These must be present on your host PC Several flash files examples are provided in the altera lt version gt kits cyclonelII 3c25 niosII examples application selector remote system update folder ILS x The flash file format is an SREC file with addressing offset from the base address of your flash device For this application the ext flash device is used For information on how to create these file refer to the section Creating Flash files for Remote System update Please note that flash files from SD Card content directories cannot be used for remote system update as the web reconfiguration interface expects to see a hardware image at 0xe00000 upon reset Operating Instr
49. feature allows us to reconfigure the FPGA from anywhere in flash so we can benefit by persistently holding caching a certain number of frequently used application hardware images in flash to avoid having to copy them from the SD Card every time the application is loaded The Application Selector utility can cache up to 10 application hardware images in CFI flash When the user chooses an application to load from the SD Card using the Application Selector the Application Selector first scans through its catalog of hardware images currently stored in CFI flash to see if any of them match the hardware image being requested If one of the images cached in CFI flash does match the Application Selector reconfigures from the offset of that cached hardware image instead of copying the image from SD Card to flash This significantly reduces the load time Caching the hardware images requires the application selector to be able to quickly tell if an image in CFI flash is the same as one on the SD Card To determine whether a hardware image in flash matches a hardware image on the SD Card a 32 bit timestamp value is used as a tag During the file conversion process the sof2flash utility inserts a 32 bit timestamp in the hardware image flash file as an S0 type record on the first line of the file When the Application Selector is about to load a hardware image B 4 Nios Il Embedded Evaluation Kit Cyclone III Edition Flash Hardware Image Catalog
50. he on board CFI flash The way the Application Selector is able to reconfigure itself with a new hardware image is by using Nios II to read the hardware image from the SD Card program it to some location in CFI flash then force the FPGA to reconfigure from that location using the remote update feature Flash Hardware Image Catalog The CFI flash holds up to 10 of the most recently loaded application hardware images to speed the load times of applications which are loaded often To keep track of which hardware images are currently Altera Corporation Nios Il Embedded Evaluation Kit Cyclone Ill Edition July 2010 Hardware Image Caching Altera Corporation July 2010 stored in flash a flash image catalog is kept in CFI flash at offset 0x8000 The implementation details of this catalog are described in the Hardware Image Caching section below Table B 1 Memory Map of CFI Flash Flash Size Flash Contents 0x000000 0x007FFF 32K Application Boot Code 0x008000 Ox00FFFF 32K HW Image Catalog 0x010000 Ox01FFFF 64K Unused 0x020000 OxOFFFFF 896K Selector HW Image 0x100000 0x17FFFF 512K Selector SW Image 0x240000 0x63FFFF 4M Application SW 0x640000 0xDBFFFF 7 5M Application HW Images 0xD00000 0xFFFFFF 3M Unused Copying data from the SD Card to flash is slow due to both the read speed from the SD Card in SPI mode and the write speed of the CFI flash However the remote update
51. he application you want to load touch the button labeled Load S amp S The application will begin loading and a small window will be displayed showing the progress Loading will take between 2 and 30 seconds depending on the size of the application and whether it was previously cached in on board flash memory Altera Corporation 4 2 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Remote System Update using Ethernet Figure 4 1 View of the Application Selector User Interface Cycione III Embedded Evaluation Kit Application Selector 1 Altera Picture Viewer Altera Mandelbrot c2H 3 Altera Web Server ic Altera Spinning Cube S imagem Taquin Game For more detailed information about the Application Selector Utility see Appendix B Application Selector Details Remote System About Remote System Update Update u sing In the previous example the FPGA was configured from designs stored Ethernet on the SD Card But imagine you are working at your desk and your system is physically located elsewhere such as in the lab or manufacturing facility or even a customer site Having remote reconfiguration capability in your FPGA allows you to update your system with a new FPGA image so long as there is a persistent Ethernet connection The way this works is that when your kit is connected to a network it serves up a web page The contents of this web page are stored in the SD Card in a folder entitled webs
52. he hardware accelerated version of the Mandelbrot application will begin running changing co ordinates and zooming in and out of the complex space See Figure 5 7 Figure 5 7 Running the Mandelbrot Application 5 9 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples lt The default mode used in the design uses hardware acceleration 6 To change modes color palettes or pause the design simply tap the touch panel to bring up the menu 7 The menuwill offer you the choice of using hardware or software rendering To select software rendering press the Software button followed by the Continue button See Figure 5 8 gt gt Itisimportantto note that software rendering can be very slow so you may have to wait a long time for a single frame to be displayed Figure 5 8 Mandelbrot Application Menu Hardware Select next color palette Continue Press to continue 8 To change the color palette used in the final image simply press the Color button followed by the Continue button See Figure 5 8 While the menu is being displayed all rendering will be paused as well If you opened the menu and wish to continue without changing any settings press the Continue button Whether the design is rendering data using hardware or software benchmark data is being collected and displayed to the screen Altera Corporation 5 10 July 2010 Nios Il Embedded Ev
53. he only restriction being that the name must end with _sw flash The second flash file represents the hardware portion of the example and must be derived from a SOF file as described in the section of this document titled Creating Your Own Loadable Applications This file can be named anything supported by the FAT 16 file system the only restriction being that the name must end with _hw flash The optional info txt file contains additional information about the application In the application selector utility touching the Show Info button while your application is highlighted brings up a window showing the text contained in this file The name of this text file must be info txt or the application selector will not recognize it All loadable applications on the SD Card must be located in a top level directory named Altera EEK Applications Under the Altera EEK Applications directory each application is located in its own subdirectory The name of that subdirectory is important because the application selector utility uses that name as the title of the application when displaying it in the main menu The name of the subdirectory is the title that will be displayed for your application in the menu The subdirectory names can be anything so long as they adhere to the FAT file system long file name rules Spaces are permitted CFI Flash Altera Corporation July 2010 Below is an example of how applications are organized on the SD C
54. ide ndun M MH Sottware Installation sr ela Aia Installing the Nios II Embedded Evaluation Kit Cyclone III Edition Installing the Quartus II Web Edition Software sese Licensing the IP lalla NO Ep ere ten UI eri se ia Licensing the EL Camino SD Card Core i Chapter 2 Development Board Setup Features tell 2 1 Requirements illa e nia 2 2 Power Up the Development Board cs iii 2 2 Chapter 3 Nios Il Processor Systems Where to find the Nios II Processor Systems uiiiii 3 3 Nios II 3C25 Standard Processor System ii 3 3 Nios IL 3C25 Video Processor System necis ertet neret dirae te tite eese tertie te rane 3 4 Chapter 4 Application Selector Utility QS call nunnien HH 4 1 Ready to Run SD Card Demonstrations essent nnne 4 1 Running the Application Selector Insystem Update ising 5D Cardi tese teneo iiti de nitide tenti teen Deco 4 2 Remote System Update using Ethernet ui 4 3 About Remote System Update Requirements ilaele arnie Operating Instructions eil Creating Flash files for Remote System update ui eee 4 6 Chapter 5 Design Examples About Design Examples 5 1 Picture Viewer A pplication iucrii e ia 5 1 Picture Viewer usc M
55. install dir gt demos mandelbrot_c2h folder This application is also a video based processor system with custom hardware acceleration engine for calculation of Mandelbrot algorithm IP licenses required to ship design W Nios II IP from Altera Ordering Code IP NIOS MI DDR SDRAM memory controller core from Altera Available free with Quartus II Subscription as part of Altera IP Base Suite Software and middleware licenses required to ship design None Software tools required to ship your hardware accelerators W NiosII C2H Compiler Ordering Code IPT C2H NIOS Ls For more information on how to obtain evaluation or shipping licenses for the above refer to Licensing the IP on page 1 11 The Mandelbrot set is a mathematical set of complex numbers that form a fractal The Mandelbrot set is generated from a surprisingly simple formula involving only multiplication and addition to produce a shape of great organic beauty and infinite subtle variation Though the Mandelbrot set is intriguing in itself the Mandelbrot C2H demonstration on the Nios II Embedded Evaluation kit showcases a powerful solution to a common engineering problem by increasing the performance of a system bound by processing throughput 5 6 Nios Il Embedded Evaluation Kit Cyclone III Edition Mandelbrot Application This example design shows a greater than 100x improvement in performance between software only and software with hardware accelerators The Nios
56. ion or evaluation 1 8 Nios Il Embedded Evaluation Kit Cyclone III Edition Software Installation 1 9 Table 1 2 Installed Directory Contents Part 2 of 2 Directory Name Description of Contents documents Contains the Nios Il Embedded Evaluation Kit Cyclone III Edition documentation including hardware and software tutorials examples Contains design examples for the Nios Il Embedded Evaluation Kit Cyclone III Edition Application Selector Utility and Nios II Embedded Evaluation Standard hardware system factory recovery Contains ready to run demonstrations stored on the SD Card as well as Flash image files required to restore the factory default state presentations and Web page content served up by the board Installing the Quartus Il Web Edition Software The Quartus II Web Edition software provides the necessary tools for developing hardware and software for Altera FPGAs Included in the Quartus II Web Edition software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including SOPC Builder and the Nios II EDS are the primary FPGA development tools for creating the reference designs in this kit To install the Quartus II Web Edition software follow these steps 1 Download the Quartus II Web Edition software from the Quartus II Web Edition Software page of the Altera website Alternatively you can request a DVD from the Alt
57. iption edition as part of Altera IP Base Suite Software and middleware licenses required to ship design B NicheStack TCP IP Network Stack Nios II Edition free evaluation license available with Nios II EDS shipping license from Altera Ordering Code IPSW TCP IP NIOS W MicroC OS II real time operating system free evaluation license available with Nios II EDS shipping license to be purchased from Micrium s For more information on how to obtain evaluation or shipping licenses for the above refer to Licensing the IP on page 1 11 The full design example for the application selector utility is available in your Nios II Embedded Evaluation kit installed under the examples directory The application selector design examples illustrates several aspects of developing designs and using software device drivers for the Nios II Embedded Evaluation Kit M Interfacing to the LCD touch panel W Interfacing to the SD Card using the FAT file system WB Implementing a HTTP web server application using the sockets interface of NicheStack TCP IP Network Stack Nios II Edition WB Implementing remote system update over Ethernet E Managing multiple FPGA configurations from Flash W Using the MicroC OS II real time operating system 5 13 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Design Examples About the Embedded Web Server The application selector also features an embedded web server which serves
58. lication selector application utilities application selector boot code c 2 Nios Il Embedded Evaluation Kit Cyclone III Edition Hardware Image Catalog Hardware Image Catalog Application Selector Hardware Image C 3 2 From the Nios II Command Shell type nios2 flash programmer base 0x4000000 The hardware image catalog section of flash is located at offset 0x8000 This section holds the locations of the currently cached hardware images in flash Any time a factory recovery is performed this section of flash should be erased to ensure no stale catalog entries exist To erase this section of flash enter the command nios2 flash programmer base 0x4000000 erase 0x8000 0x8000 After erasing this section you may wish to read back the erased contents into a file so that you can combine this file into the final factory recover image The command to read back this section into a file named catalog srec is nios2 flash programmer base 0x4000000 read catalog flash read bytes 0x8000 0x8000 The application selector hardware image section contains the FPGA hardware image for the application selector utility This section is located at flash offset 0x20000 The FPGA gets configured with this image upon power up and after a board reset The file you will need to create this portion of the factory recovery image is named cyclonellI embedded evaluation kit application selector sof and is located in the application sele
59. lication selector utility refer to Appendix A Video Pipeline Data Flow Appendix B Application Selector Details Appendix C Restoring 1 6 Nios Il Embedded Evaluation Kit Cyclone III Edition Software Installation the Factory Image and Appendix D Frequently Asked Questions However we opted to provide extensive source code comments rather than formal documentation regarding the other applications IS We are interested in knowing if this structure for the documentation is adequate for you to be able to develop your applications If you have comments or suggestions on what we can do to improve the user experience through our documentation contact us through nios_docs altera com To ensure that you have the most up to date information on this product refer to the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page Before You Begin Before proceeding check the contents of the kit B Nios II Embedded Evaluation Board W Cables and accessories Software This section describes the following procedures Installation W Installing the Nios II Embedded Evaluation Kit Cyclone III Edition W Installing the Quartus II Web Edition Software on page 1 9 m Licensing the IP on page 1 11 m Licensing the EL Camino SD Card Core on page 1 13 Installing the Nios Il Embedded Evaluation Kit Cyclone III Edition The license free Nios II Embedded Evaluation Kit Cyclone III Edition installer includes all the do
60. line signals to the LCD T Nios Il Processor Systems Touch panel The video pipeline signals have been multiplexed inside the FPGA and de multiplexed by the MAX II CPLD to provide a full range of functionality on the daughter card over a limited number of pins on the HSMC connector see the LCD Multimedia Daughtercard Reference Manual for details Within the FPGA is the Nios II Video Processor System It is a pre generated Nios II processor based hardware system that can be used as a starting point for embedded application development The components in this embedded microprocessor system are shown in Figure 3 2 Figure 3 2 Nios Il Processor System Block Diagram Nios Il Embedded Evaluation Standard Hardware Memory Interface CPU Platform Communications hterf ace 256 Mbit Nios Il JTAG JTAG DOR C Debug UART SDRAM o pr ak 123 MB 32KB 32 KB SD Card E x Cache D Cache System Functions Video Fipdine UART 10 100 Bhernet Button Perfrom PIO for PIO ance LCD l2c n Counter Interface Remote Touch Update panel SPI Interface Altera Corporation 3 2 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Where to find the Nios Il Processor Systems Where to find the Nios Il Processor Systems 3 3 There are two pre generated processor systems that target the Nios II Embedded Evaluation Kit Nios Il 3C25 Standard Processor System Location You can locate the Nios II 3C25 Stand
61. llectual property IP cores with the Altera IP Base Suite which is completely free with a Quartus II subscription For more information about obtaining the Altera IP Base Suite refer to the Free IP Base Suite Licenses With Active Quartus II Subscription page Altera Corporation 1 12 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Software Installation 1 13 Licensing the EL Camino SD Card Core The Nios II Standard hardware design contains the SD MMC SPI CORE which is a component that has been provided by a third party vendor El Camino To compile this core in your SOPC Builder system you must obtain a license from El Camino However ifyour particular application has no need to access the SD Card then you do not need to include the SD Card core in your system Simply uncheck this core or delete it and regenerate the system You should now be able to rebuild the hardware system without error If your design requires access to the on board SD Card then you can request an evaluation license or purchase the SD Card Controller IP drivers and FAT File system from El Camino El Camino GmbH Landshuter Str 1 D 84048 Mainburg Germany Tel 49 8751 8787 0 Fax 49 8751 842876 Web www elcamino de E mail info elca de Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Getting Started Altera Corporation 1 14 July 2010 Nios Il Embedded Evaluation Kit Cyclone I
62. m involves four elements 1 Adding and configuring of the core processor and memory 2 Adding peripherals such as memory interfaces I O or interfaces to external devices such as the LCD Display 3 Connecting the I O pins of the processor in the FPGA to the external devices 4 Writing C C software application for your custom processor with the Nios II Embedded Design Suite In the vast majority of cases hardware design can be accomplished using drop down menus and drag and drop operations in SOPC Builder The sophistication of Altera s designs tools brings creating custom hardware processor systems within the reach of embedded developers About the Nios Il Standard Design The starter reference design for the board entitled standard is located in the altera version gt kits cycloneIII_3c25_niosII examples folder The Nios II standard is a SOPC Builder system featuring the Nios II processor and common peripherals that has been put together for you Hardware designers can accelerate their SOPC Builder system development by using the Nios II Standard design example as a starting point The board boots up with this pre built design so software developers can use it for software development without having to concern themselves with the details of generating the FPGA hardware system The Nios II Standard System is a pre generated hardware system that includes W Nios II core 32 bit soft processor Application m LCD Controll
63. many ready to run demonstrations available on the sd card A menu listing all the demonstrations stored on the SD Card appears when the NEEK is first powered up The ready to run demonstrations that you see on the Altera Corporation July 2010 display of the Nios II Embedded Evaluation Kit can be found in the kit installation directory at Install Dir gt factory_recovery sdcard_contents Altera_EEK_Applications What is in a ready to run demonstration A ready to run demonstration consists of the following files E Binary image flash format containing the FPGA hardware image E Binary image flash format containing the software application W Optional info txt file containing a brief description of the demonstration How do ready to run demonstrations get loaded from the SD card to the FPGA When you select one of these demonstrations from main menu on the LCD screen the default design called application selector copies these images from the SD Card to the Flash memory and reconfigures the FPGA with your chosen demonstration application Where can get more ready to run demonstrations To get more information about the ready to run demonstrations 1 For usage instructions use the LCD Touch Screen to highlight the demonstration and press the Info button 2 Inaddition to the prepackaged ready to run SD Card demonstration applications which come with the Nios II Embedded Evaluation Kit Cyclone III Edition more are a
64. mote then it consist of a Flash image for the software application To create the Syste mu pd ate flash files you must have the Nios II EDS and Quartus II FPGA design software installed on your PC Altera Corporation July 2010 A hardware SRAM object file SOF must have the cpu reset address configured from the Flash device at offset 0x0 Create the software Executable link format file ELF in the standard fashion On your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version tt EDS gt Nios II Command Shell From the command shell navigate to where your SOF file is located and create your hardware Flash image using the following command sof2flash activeparallel input your SOF sof output your SOF flash offset RECONFIG ADDRESS From the command shell navigate to where your ELF file is located and create your software Flash image using the following command elf2flash base 0x04000000 end 20x04FFFFFF reset 0x04240000 input vour ELF efl output your FLASH flash boot SOPC KIT NIOS2 components altera nios2 boot loader cfi srec 4 6 Nios Il Embedded Evaluation Kit Cyclone III Edition N D TE RYA 5 Design Examples About Design Examples Picture Viewer Application Altera Corporation July 2010 The Nios II Embedded Evaluation kit comes with several applications that showcase the versatility of the Nios II processor in v
65. ng services custrain altera com Product literature www altera com literature Product literature services literature altera com FTP site ftp altera com Note to table 1 You can also contact your local Altera sales office or sales representative Altera Corporation Info i July 2010 Additional Information Further Information Further Information Typographic Conventions For other related information refer to the following websites For More Information About Refer to Cyclone III handbook www altera com literature lit cyc3 jsp Cyclone Ill reference designs www altera com products devkits altera kit cyc3 embedded html eStore if you want to purchase devices www altera com buy devices buy devices html Cyclone III Orcad symbols www altera com support software download pc b pcbpcb index html www altera com technology embedded emb index html Nios II 32 bit embedded processor solutions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d
66. or reconfiguration LED PIO Output only control block for LED1 LED4 Pushbutton PIO Input only control block for the on board pushbuttons PIO for ID EEPROM I2C Used to communicate with the EEPROM ID chip which stores information about the board including the touch panel calibration data and Ethernet MAC address s The I2C interface is implemented using software and general purpose I Os connected to the Nios II Standard System Memory Interface There are four different types of on board memory or storage devices The memory controllers for three of these devices are provided as part of Altera s IP Suite and include BH SSRAM Controller BH DDRSDRAM Controller B CFI Flash Controller E SD Card I gt The controller API and FAT File System for the SD Card used 3 5 in the Nios II Standard System is provided under license agreement by El Camino http www elcamino de Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Nios Il Processor Systems Altera Corporation July 2010 For technical details on the components in standard hardware system refer to Quartus II Handbook Volume 5 Embedded Peripherals Communication Interfaces There are several communication interfaces included in the Nios II Standard System JTAG UART Used for Serial communication and debugging Nios II applications via the on board USB Blaster circuitry UART Serial communication link for general pur
67. our design in hardware OpenCore Plus hardware evaluation supports the following two modes of operation Tethered requires a JTAG connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely Untethered the design runs for a limited time To ship designs with the Nios II IP Core you need to obtain a license for the Nios IL IP IP NIOS To obtain a license you can 1 Contact your local Altera representative at www altera com corporate contact con index html 2 Use the Altera Tools Support at www altera com corporate contact info con phone html to order today Nios II Processor To obtain a non time limited use license file for the Nios II processor you must purchase a stand alone Nios II processor core license ordering code IP NIOS Contact your local Altera representative or Altera Tools Support to order today Nios II C2H Compiler You can create compile and generate time limited Nios II processor systems and hardware accelerators generated by the Nios II C2H Compiler without obtaining a license file with the OpenCore Plus evaluation feature You must obtain a license for the Nios II processor core ordering code IP NIOS and Nios II C2H Compiler ordering code IPT C2H NIOS to generate non time limited 1 11 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Getting Start
68. pose communications and debug SPI Used to communicate with the touch panel portion of the LCD Touchscreen 10 100 Ethernet Controller The Ethernet controller uses the Triple speed Ethernet MAC to communicate with the PHY on the LCD Multimedia Daughtercard Video Pipeline The video pipeline outputs the appropriate pixel data and sync signals to the LCD Touch Panel It provides high bandwidth memory access that allows for flicker free display on the color LCD A more detailed description of the data flow for the video pipeline can be found in Appendix A The video pipeline is comprised of e PIO for LCD I C Controller The PC pins are used to configure the LCD panel for brightness and set the gamma correction curves e SPI Touch Panel Controller Used to communicate with the touch panel ADCs e Pixel Converter Logic block that converts parallel 32 bit R G B 0 data to an 8 bit data stream This is required because of the pin limitation placed on the system by the HSMC connector The video data stream is multiplexed in the FPGA on the Cyclone III Starter Board and de multiplexed in the MAX II device on the LCD Multimedia Daughtercard e Sync Generator Generates the horizontal and vertical sync signals for each frame displayed on the LCD touch screen 7 For more information on the video pipeline pixel converter and Video Sync Generator and GPIO components refer to Quartus II Handbook Chapter 5 Embedded Peripherals 3 6
69. re 5 9 Mandelbrot Engine Pixel Interleaving 480 Rows 800 Calumns O eececec s E O O O O essere OOO D LOTITO Altera Corporation July 2010 While the hardware accelerators are calculating a frame the coordinates of the next frame are prepared by the main i e the Nios II processor The hardware accelerators contain a C pragma that instructs the compiler to implement non blocking accelerators which allows both the main processor and Mandelbrot hardware accelerators to operate in parallel The main processor polls the hardware accelerator to determine if the entire frame has been rendered 5 12 Nios Il Embedded Evaluation Kit Cyclone III Edition Application Selector App lication This application is based on the Application Selector processor system Se I ector You can locate this application in the lt install dir gt examples application_selector folder Description Video Ethernet and SD Card controller based processor system for LCD Color touch panel control in system update using SD Card remote system update using Ethernet IP licenses required to ship design E SD MMC SPI Core IP with FAT file system from El Camino W TripleSpeed Ethernet MAC Core license from Altera Ordering code IP TRIETHERNET W Nios IT IP evaluation license with Nios II EDS shipping license from Altera Ordering Code IP NIOS MI DDR SDRAM memory controller core shipping license from Altera comes free with Quartus II Subscr
70. rting points to accelerate hardware development e Nios II Standard Processor System Standard e Nios II Video Based Embedded Processor System Video Pre built embedded applications with source code to serve as examples for software device driver development e Altera Application Selector with embedded Web Server e Altera Picture Viewer e Altera Mandelbrot Hardware and Software Tutorials to learn the embedded development flows e My first FPGA design e My first Nios II Software tutorial Ready to Run Demonstration applications from Altera s partners e IP SD Card Controller El Camino Graphics Engines TES Imagem PlanetWeb e Operating systems MicroC OS II Micrium Evaluation Licenses uC Linux SLS e Middleware Filesystems El Camino Micrium SLS Graphics Libraries Micrium Altera Evaluation IP license cores and software packages for embedded development Nios II IP Core Evaluation Core DDR SDRAM Memory IP Core Evaluation Core TSE MAC IP Core Evaluation Core NicheStack TCP IP Network Stack Nios II Edition Evaluation Core 1 2 Nios Il Embedded Evaluation Kit Cyclone III Edition Kit Contents About the Nios Il Processor Nios II is a fully configurable 32 bit processor optimized for use in Altera s FPGA The embedded processor system is easily customized for a particular application using the SOPC Builder feature of the Quartus II FPGA design software Assembling a microprocessor syste
71. ry gt examples application_selector software_examples app application_selector src app_selector h 2 Edit the lines define AS_FLASH_IMAGE_CATALOG_OFFSET 0x8000 define AS_FLASH_IMAGE_CATALOG_SIZE 0x8000 to reflect the flash offset where you would like to put flash catalog US You will need to rebuild the boot code for these changes to take effect B 12 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Appendix C Restoring the ANO E RYA Factory Image Restoring the Original Flash Image Application Selector Altera Corporation July 2010 The Nios II Embedded Evaluation kit is programmed from the factory to configure the FPGA from flash to the application selector In the course of your development you may need to replace the factory image with your own flash image To restore the original Flash contents of the Factory Image i e the application selector perform the following steps 1 Make sure you have a APC with Nios II Embedded Evaluation Kit Quartus II version 7 2 or later FPGA design software and Nios II EDS version 7 2 or later b A USB cable One should be provided with your kit 2 Connect your board to the PC by connecting a USB cable from USB connector J3 on your board to a USB port on your PC 3 Tools menu in Quartus II software launch the Quartus II Programmer and click Auto Detect The EP3C25F
72. s a starting point for their own applications Success for an embedded system start rights from the evaluation stage Choosing the right platform development tools operating systems may be the difference between success and failure The Altera Nios II Embedded Evaluation Kit Cyclone III Edition is an evaluation kit that enables you to make these critical decisions with minimal investment The Nios II Embedded Evaluation Kit Cyclone III Edition makes evaluating Altera s embedded solutions easy Processor systems targeting the low cost low power Cyclone III FPGA can be evaluated by simply using the LCD Color Touch Panel to scroll through and load your demonstration of choice These processor systems showcase the unique benefits of FPGA based processors such as reducing BOM costs by integrating powerful graphics engines within the FPGA reducing operating costs by upgrading your system over the Internet or increasing system performance while reducing power using C to Hardware C2H acceleration Altera Corporation 1 1 July 2010 Getting Started Kit Conte nts The Nios II Embedded Evaluation kit will acquainting you with the Nios II processor the hardware and software development flows and the robust embedded ecosystem of operating systems middleware IP and third party offerings that support the Nios II processor To this end the kit features Altera Corporation July 2010 Pre built embedded processor systems that serve as sta
73. t we will refer to the lt Install Directory gt which is altera lt version gt kits cyclonelII_3c25_niosII Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Create a BSP The first thing that s needed to build the software project is a board support package BSP To create a BSP perform these steps 1 Opena Nios II Command Shell 2 Change to the directory Install Directory examples application selector software examples bsp hal application selector 3 Run the command create this bsp Build the project The next step is to build the Application Selector project To build the project perform these steps 1 Inthe Nios II Command Shell change to the directory Install Directory examples application selector software examples app application selector 2 Runthe command make all a For more information about BSPs and the Nios II Software Build Tools refer to the Getting Started from the Command Line chapter in volume 2 of the Nios II Software Developer s Handbook Altera Corporation B 8 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Modifying the Application Selector Modifying the Application Selector B 9 Build the boot code To rebuild the boot code which runs when an application is loaded and run from the Application Selector perform these steps 1 Opena Nios II Command Shell 2 Change to the directory
74. ted to the remote configuration instruction page Carefully read the instructions for remote configuration 7 Click on the Left hand side of the web page you will see a CFI Flash Upload section Click Browse button and browse to the hardware Flash image on your PC and click Open 5 Browse to the altera lt version gt kits cycloneIII_3c25_niosII examples application_selector remote_system_update folder choose an application e g mandelbrot and click on C2H_Mandelbrot_hw flash 8 On the web page click Upload c Please wait while the hardware Flash image is uploaded to your board When this is done you will be directed to another web form entitled Program CFI Flash 9 Click on the Program Flash Button to program the on board flash with the uploaded Flash image 10 If your remote update system has a software Flash image then click on Return to Instructions and repeat the previous three steps to upload and program the software Flash Upon completion you will be directed to a form entitled Reset System 11 Click on the Reset System button The FPGA should now reconfigure from the newly programmed contents of the Flash file 4 5 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Application Selector Utility Cre ating Flash The image required for remote system update consists of a Flash image gt for FPGA configuration and if your system has a software application fi I es for Re
75. the Nios II Embedded Evaluation kit is comprised of the components shown in the Figure 3 1 below Figure 3 1 Block Diagram of Nios Il Embedded Evaluation Kit Cyclone III Edition Cyclone Ill FPGA Starter Board Buttons LEDs DDR SDRAM CFI Flash d i Cyclone Ill FPGA Processor LCD Multimedia Daughtercard 1 MAX Il CPLD 24 Bit Audio Codec 10 bit VGA Video DAC Video Decoder PS 2 amp RS 232 Ports Touch Panel Module 10 100 Ethernet PHY n SD Card SHEONSGSGNOESESERORONSGEEZNKUEE 12C EEPROM I Altera Corporation July 2010 If you examine your Nios II Embedded Evaluation Kit Cyclone III Edition you will find that it is comprised of 2 boards the Cyclone III FPGA Starter Board and the LCD Multimedia Daughtercard On the Cyclone III FPGA Starter board resides the Cyclone III 3c25 FPGA which configures from flash with the Nios II Standard Processor System on startup gt The HSMC Connector shown in Figure 3 1 is actually a flex extension cable with HSMC connectors on each end going between the two boards This detail was removed for simplicity On the LCD Multimedia Daughtercard resides a MAX II CPLD whose function is to relay data and control signals to the various peripheral devices as shown in the Figure 3 1 The MAX II CPLD performs voltage translation and de multiplexing of video pipe
76. tion Software Image The application software image can be relocated in flash by performing the following steps 1 Ina text editor open the file B 10 Nios Il Embedded Evaluation Kit Cyclone III Edition Modifying the Application Selector lt install Directory gt examples application_selector application_utilities app_selector_boot_code app_selector_boot_code s 2 Edit the line define SW_APP_CODE 0x240000 to reflect the flash offset where you would like to put the loadable application software images Ensure that there is enough space allocated at that offset to hold your application software images 3 Ina text editor open the file lt install Directory gt examples application_selector software_examples app application_selector src app_selector h 4 Edit the line define AS SW IMAGE OFFSET 0x240000 to reflect the flash offset where you would like to put the loadable application software images Ensure that there is enough space allocated at that offset to hold your application software images a You will need to rebuild both the boot code and the application selector utility for these changes to take effect Flash Catalog The flash catalog can be relocated in flash and size adjusted by performing the following steps 1 Inatexteditor open the file B 11 Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 lt Installed Directo
77. uctions 1 Apply power to the board by plugging in the power cable and pressing switch SW1 TS The application selector will appear on the LCD Screen On the bottom right you will see a button that should say Not Connected You may click on the button to view the instructions for remote system update and click OK to return to the main screen 2 Using an Ethernet cable connect the Ethernet RJ 45 jack on the LCD Multimedia HSMC to a working Ethernet port Ls The connection to Ethernet port will be detected by the application which will try to acquire a suitable IP address During this time you will see the message Connecting on the LCD screen Please wait while the web server application establishes a connection to the internet and acquires an IP Address via DHCP On completion the IP Address will be displayed on the LCD Screen 4 4 Nios Il Embedded Evaluation Kit Cyclone III Edition Remote System Update using Ethernet 4 On your host PC ensure that it is connected to a working Ethernet port and launch a web browser 5 In the web browser window type the IP address displayed on the LCD screen e g 168 57 231 12 and hit Enter c You should now see a web page displayed on the web browser which is being served up by the board from the contents of the webserver_html directory on the SD Card 6 On the upper left hand side on the web form click on the link under Go to instructions You will be direc
78. uild the hardware system without error When your hardware and software image is ready you can add your design to be loadable by the application selector by following the steps listed in the FAQ How do I add my own design so the Application Selector can find and run it Where can get the SD Card Controller IP License If your design requires access to the on board SD Card then you can request an evaluation license or purchase the SD Card Controller IP drivers and FAT File system from El Camino El Camino GmbH Landshuter Str 1 D 84048 Mainburg Germany Tel 49 8751 8787 0 Fax 49 8751 842876 Web www elcamino de E mail info elca de How do add pictures so the Picture Viewer Application can find them 1 Connect the SD Card reader provided in the Nios II Embedded Evaluation Kit to your PC via a USB port 2 Remove the SD Card and place in the SD Card Reader 3 Add any JPEG or BMP file to the images folder on the SD Card Altera Corporation Nios Il Embedded Evaluation Kit Cyclone III Edition July 2010 Altera Corporation July 2010 4 Re insert the SD Card in the Nios II Embedded Evaluation Kit board The next time you run the Picture Viewer application these new files will be found How do add my own design so the Application Selector can find and run it The Nios II Embedded Evaluation Kit provides an elegant way to add designs such that a user can scroll through and select th
79. us hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions W Nios II Embedded Design Suite EDS A full featured tool set that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Licensing Considerations The Quartus II Web Edition software is license free and supports Cyclone III devices without any additional licensing requirement This kit also works with the Quartus II Subscription Edition software after you obtain the proper license file To purchase a subscription contact your Altera sales representative Altera Corporation 1 10 July 2010 Nios Il Embedded Evaluation Kit Cyclone III Edition Software Installation Licensing the IP After installing the Quartus II Web Edition software you will have installed an OpenCore Plus evaluation of the Nios II IP core Any designs you create operate in Altera s OpenCore Plus evaluation mode and allow you to do the following 1 Simulate the behavior of the Nios II processor IP in your system 2 Verify the functionality of your design as well as evaluate its size and speed quickly and easily 3 Generate time limited device programming files for designs that include a Nios II processor 4 Program a device and verify y
80. vailable from Altera or through third party vendors For more information about ready to run SD Card demonstration applications refer to the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page 3 For more information refer to the Nios II Embedded Evaluation Kit NEEK Cyclone III Edition User Guide Where can get full Quartus Il projects and source code for ready to run demonstrations Altera s partners can provide full Quartus II projects source code development tools and even design services to get you up and running developing products You will find links to partners from Nios II Embedded Evaluation Kit NEEK Cyclone III Edition page D 2 Nios Il Embedded Evaluation Kit Cyclone III Edition D 3 Why do get the error Can t find valid feature line for core SD_MMC_SPI_CORE EC11_0002 in current license Error Error 10003 Can t open encrypted VHDL or Verilog HDL file when try to re generate the Nios Il Standard hardware design The Nios II Standard hardware design contains the SD MMC SPI CORE which is a component that has been provided by a third party vendor El Camino To compile this core in your SOPC Builder system you will need to get a license from El Camino However if your particular application has no need to access the SD Card then you do not need to include the SD Card core in your system Simply uncheck this core or delete it and re generate the system You should now be able to reb
81. xist make flash Once ext_flash flash is created you can program it into flash with the following command nios2 flash programmer base 0x4000000 ext_flash flash Once you ve created flash or srec files for all the sections of the factory recovery image you can combine them all into one file using the cat command cat app_selector_boot_code srec catalog flash appsel_hw flash ext_flash flash gt temp_restore flash However you are still not done Some of the individual files we combined contained non data records in them Some non data records such as S0 records cannot appear anywhere in an SREC file except for the beginning so you want to remove all the non data records from the final factory recovery image Data record types are S1 S2 and S3 so you want to remove all the other types of records S0 S5 87 S8 and S9 You can use the command sed to perform this task Use the following command to remove all non data records from the new factory recovery image file sed S 05789 d temp restore flash restore cycloneIII _3c25 flash You can now restore the Embedded Evaluation Kit board to its factory state by running the command nios2 flash programmer base 0x4000000 restore_cycloneIII _3c25 flash C 4 Nios Il Embedded Evaluation Kit Cyclone III Edition NE E Appendix D Frequently L ERA Asked Questions Altera Corporation July 2010 This section below explains the frequently asked questions

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