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SOPC Builder User Guide

1. CPU1 System Interconnect Fabric WoO E E lalo 888 ars gu EE ll B E S 9 9j o ojo 9 9 9 Salg gss Sisis gss Pee ggg ppp PBE I gl lt gt A A A oj SS gl Sg S S99 gele Qr mr cc oc ccc ggg ggg zzz zal g SS 33 3 328 m 0 a aaja a aaa modc sx 3 d d S 3 diss B d a s sss 3 c SSj Oo oO c a a 8S E aia ajaja 3 3 8 3 3 gs 3 la 38 lt lt lt Q 8 lt lt lt cm la e lal oo zI o ziaja 5 E 2 EX SISE 5 E n arua a a jaja a cana D 0 0 o O Of 0 O 0 o o OOo ojojo y Yy y Yy Tristate Bridge DDR SDRAM Message Buffer Message Buffer to External Controller RAM Mutex SRAM M Avalon MM Master Port S Avalon MM Slave Port Figure 11 4 and Figure 11 5 show how inserting bridges can affect the generated logic For example if the DDR SDRAM controller can run at 166 MHz and the CPUs accessing it can run at 120 MEZ inserting an Avalon MM clock crossing bridge between the CPUs and the DDR SDRAM has the following benefits m Allows the CP
2. Avalon MM Bridge Address Translation span 0x800 0x1000 0x1000 Ox7FF 0x1000 Ox17FF Slave Addr Space Ox7FF Slave2 0x1400 Ox5FF Slave2 span 0x200 range 0x400 Ox5FF 0x400 Slave1 0x1000 l ii 1FF 0x100 x span 0x l l sevel 0x100 range 0x100 0x1FF 0x000 0x000 Tools for Visualizing the Address Map The Base Address column of the System Contents tab displays the base address offset of the Avalon MM slave relative to the base address of the Avalon MM bridge to which it is connected You can see the absolute address map for each master in the system by clicking Address Map on the System Contents tab Differences between Avalon MM Bridges and Avalon MM Tristate Bridges You use Avalon MM bridges to control topology and separate clock domains for on chip components You use tristate bridges to connect to off chip components and to share pins decreasing the overall pin count of the device Tristate bridges are transparent meaning that they do not affect the addresses of the components to which they connect For more information about the Avalon MM tristate bridge refer to Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Avalon MM Pipeline Bridge SOPC Builder User Guide This section describes the hardware structure and functionality of the Avalon MM pipeline bridge component December 2010 Altera Corporation Chapter 11 Avalo
3. A 1 L S m e a SDRAM Y Y Controller S S A Ethernet Flash i MAC PHY Memory 1 Chip Chip y SDRAM Chip M Avalon MM Master Port S Avalon MM Slave Port SOPC Builder User Guide SOPC Builder supports components with multiple Avalon MM interfaces such as the processor component shown in Figure 2 1 Because SOPC Builder can create system interconnect fabric to connect components with multiple interfaces you can create complex interfaces that provide more functionality than a single Avalon MM interface For example you can create a component with two different Avalon MM slaves each with an associated interrupt interface System interconnect fabric can connect any combination of components as long as each interface conforms to the Avalon Interface Specifications It can for example connect a system comprised of only two components with unidirectional dataflow between them Avalon MM interfaces are suitable for random address transactions such as to memories or embedded peripherals December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 3 Fundamentals of Implementation Generating system interconnect fabric is SOPC Builder s primary purpose In most cases you are not required to modify the generated HDL however a basic understanding of how HDL works can help you optimize your system For example knowledge of the arbitration algorithm can help designers of mu
4. Merit Main validation elaboration and compose Usage Set module assignment name value Returns None name The name whose value is being set Arguments value The value of the name argument Example set module assignment embedded sw CMacro colorSpace CMYK get files This command returns a list of all the files that have been added to the module get files Mens Main validation elaboration generation and editor Usage get files Returns List of strings Arguments None Example set list of files get files SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference add_file 7 19 This command adds a synthesis simulation or TimeQuest constraints file to the module Files added in the main program cannot be removed Adding files in the generation callback allows the included files to be a function of the parameter set or to be a result of generation Files added in callbacks are in addition to any files added in the main program add_file S TS Main and generation Usage add file filename fileProperties Returns String filename The file name to be added relative to the directory containing the _hw tel file Files support the following 3 properties Arguments m SIMULATION File for simulation fileProperties m SYNTHESIS File for synthesis m Spc TimeQuest constraints SDC
5. Sender irq Priority Encoded Interrupt Scheme In the priority encoded interrupt scheme in the event that multiple slaves assert their IRQs simultaneously the system interconnect fabric provides the interrupt receiver with a 1 bit interrupt signal and the number of the highest priority active interrupt An IRQ of lesser priority is undetectable until all IRQs of higher priority have been serviced December 2010 Altera Corporation SOPC Builder User Guide 2 16 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Reset Distribution Using priority encoded interrupts the interrupt controller can handle up to 64 slave IRQ signals The interrupt controller generates a 1 bit irg signal to the receiver signifying that one or more senders have generated an IRQ The controller also generates a 6 bit irqnumber signal which outputs the encoded value of the highest pending IRQ See Figure 2 13 Figure 2 13 IRQ Mapping Using Hardware Priority Sender irq Interrupt 1 Controller Sender irq 2 Sender i d 3 Receiver Sender irq a irgnumber 5 0 irq2 gt irq3 gt irg4 Priority irgS Encoder irg6 gt irg63 y Assigning IRQs in SOPC Builder You specify IRQ settings on the System Contents tab of SOPC Builder After adding all components to the system you make IRQ settings for all interrupt senders
6. Channel Signal Width bits 16 channels The maximum width of the channel signal is eight bits Set to 0 if channels are not used Max Channel Type the maximum number of channels that the interface supports Valid values are 0 255 Data Bits Per Symbol Type the number of bits per symbol Data Symbols Per Beat Type the number of symbols per active transfer Turn this option on if the interfaces supports a packet protocol including the startofpacket endofpacket and empty signals Turn this option on if the cycle that includes the endofpacket signal can Include Empty Signal include empty symbols This signal is not necessary if the number of symbols per beat is 1 Include Packet Support December 2010 Altera Corporation SOPC Builder User Guide 12 10 Chapter 12 Avalon Streaming Interconnect Components Installation and Licensing Installation and Licensing The Avalon ST interconnect components are included in the Altera MegaCore IP Library which is part of the Quartus II software installation After you install the MegaCore IP Library SOPC Builder recognizes these components and can instantiate them into a system You can use the Avalon ST components without a license in any design that targets an Altera device Hardware Simulation Considerations The Avalon ST interconnect components do not provide a simulation testbench for simulating a stand alone instance of the component However you can use the sta
7. PCB Nios Il Processor DMA Controller Parallel Flash 8 bit word addr 19 0 A 81 0 A 19 0 D 81 0 P D 7 0 CEn Ethernet 16 bit word Tristate Bridge addr 20 1 A 26 0 A 19 0 D 31 0 D 15 0 CEn SSRAM 32 bit word addr 26 2 A 24 0 data 31 0 D 31 0 CEn LM p CEn A 26 0 D 31 0 Example Design with SRAM and Flash Memory SOPC Builder User Guide This section demonstrates adding a 1 MByte SRAM and an 8 MByte flash memory to the example design These memory devices connect to the system interconnect fabric through an Avalon MM tristate bridge Adding the Avalon MM Tristate Bridge In the Avalon MM Tristate Bridge configuration wizard turn on the Registered inputs and outputs option to maximize system fmax which increases the read latency by two for both the SRAM and flash memory December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory Adding the Flash Memory Interface The flash memory is 8M x 8 bit which requires 23 address bits and 8 data bits Table 9 2 gives the Flash Memory Common Flash Interface settings for the example 9 21 design Table 9 2 Flash Memory Interface CFI Parameter Value Attributes Presets AMD29LV065D12R Address Width bits 23 Data Width bits 8 Timing Setup 40 Wait
8. provide an icon for the sound group add display item icon Speaker speaker image speaker png add parameter sound string 0 0 add parameter volume control boolean 0 0 add parameter separate control string 0 O Setup display names for the parameters Set parameter property sound DISPLAY NAME Audio Set parameter property volume control DISPLAY NAME Include Volume Control Interface Set parameter property separate control DISPLAY NAME Treble Bass Controls Display all parameters in the Speaker group add display item Speaker sound parameter add display item Speaker volume control parameter add display item Speaker separate control parameter There are 4 choices for the sound parameter Strings with internal spaces require double quotes Set parameter property sound ALLOWED RANGES 0 No Audio 1 Monophonic 2 Stereo 4 Quadraphonic set parameter property separate control ALLoWED RANGES No Control Single Control Dual Controls Specify how parameters should be displayed Set parameter property volume control DISPLAY HINT boolean Set parameter property separate control DISPLAY HINT radio Figure 7 1 shows the GUI that the Tcl commands in Example 7 13 produces Figure 7 1 Parameter GUI for Audio Component Audio Quadraphonic W Speaker Include Volume Control Interface Treble Bass Controls O No Control O Single Control Dual Controls Overriding Default Behaviors You can override eac
9. DDR SDRAM DDR2 SDRAM SOPC Builder User Guide You can use double data rate DDR SDRAM devices for a broad range of applications such as embedded processor systems image processing storage communications and networking In addition the universal adoption of DDR SDRAM in PCs makes DDR SDRAM memory a solution for high bandwidth applications DDR SDRAM is a lt 2n gt prefetch architecture where the internal data bus is twice the width of the external data bus and data transfers occur on both clock edges It uses a strobe DOS which is associated with a group of data pins DQ for read and write operations Both the DOS and DQ ports are bidirectional Address ports are shared for write and read operations Double data rate DDR2 SDRAM is the second generation of double data rate DDR SDRAM technology with features such as lower power consumption higher data bandwidth enhanced signal quality and on die termination DDR2 SDRAM brings higher memory performance to a broad range of applications such as PCs embedded processor systems image processing storage communications and networking It is a lt 4n gt pre fetch architecture with two data transfers per clock cycle The memory uses a strobe DQS associated with a group of data pins DQ for read and write operations Both the DQ and DQS ports are bidirectional Address ports are shared for write and read operations For more information refer to Literature External Memory Interfa
10. m Ifthe component defines the TOP LEVEL HDL MODULE property SOPC Builder creates a Verilog HDL or VHDL wrapper module to instantiate the top level module and applies the parameters as selected by the user of your component SOPC Builder does not apply parameters in the wrapper if they are not declared in the underlying HDL file or m Ifthe component does not define the TOP_LEVEL_HDL_MODULE property but instead sets the INSTANTIATE IN SYSTEM MODULE module property to false the module is not instantiated inside the SOPC Builder system and a wrapper file is not created Rather the interface to the module is exported to the top level of the SOPC Builder system and the module must be connected outside the system Edit Phase Behavior SOPC Builder s default editor phase behavior is to use all of the parameter definitions to display the parameter editor The properties of the parameters guide SOPC Builder when it builds the default GUI Table 7 4 on page 7 23 lists the properties of parameters December 2010 Altera Corporation SOPC Builder User Guide 7 8 Chapter 7 Component Interface Tcl Reference Overriding Default Behaviors You can place parameters in logical groups and provide images and text to create a custom GUI for your component Example 7 7 defines four parameters and illustrates the use of the add display item command and the DISPLAY HINT and ALLOWED RANGES parameters Example 7 7 Defining and Customizing GUI Parameters
11. Figure 11 5 shows the system interconnect fabric that SOPC Builder creates for the system in Figure 11 4 Figure 11 5 is the same system that is pictured in Figure 11 3 with bridges to control system topology Figure 11 5 Example System with a Bridge System Interconnect Fabric CPUS Addr Data BursiReq Re BursiRe CPU1 Addr Data Burs CPU2 Addr Data CPU1 Adbr Data BursiReq CPU2 Ad r Data BurstReq CPUS Addr Data BurstReq rddata cgut rddata cpgu2 rddata_cpu3 CPU2 Addr Data BurstReq CPU1 Addr Data BurstReq L q S Avalon MM S4 Pipeline Bridge S Avalon MM Clock Crossing Bridge Tristate Bridge to External M SRAM M System Interconnect Fabric DDR Message Message JTAG JTAG JTAG SDRAM Buffer Buffer Debug Debug Debug Cntl RAM Mutex CPU1 CPU2 CPUS M Avalon MM Master Port S Avalon MM Slave Port Address Mapping for Systems with Avalon MM Bridges An Avalon MM bridge has an address span and range that are defined as follows m The address span of an Avalon MM bridge is the smallest power of two size that encompasses all of its slave s ranges SOPC Builder User Guide December 2010 Altera Corporation
12. Interrupts Interrupts In systems where components have interrupt request IRQ sender interfaces the system interconnect fabric includes interrupt controller logic A separate interrupt controller is generated for each interrupt receiver The interrupt controller aggregates IRQ signals from all interrupt senders and maps them to user specified values on the receiver inputs For further information refer to the Interrupt Interfaces chapter in the Avalon Interface Specifications Individual Requests IRQ Scheme In the individual requests IRQ scheme the system interconnect fabric passes IRQs directly from the sender to the receiver without making any assumptions about IRQ priority In the event that multiple senders assert their IRQs simultaneously the receiver logic presumably under software control determines which IRQ has highest priority then responds appropriately Using individual requests the interrupt controller can handle up to 32 IRQ inputs The interrupt controller generates a 32 bit signal irq 31 0 to the receiver and simply maps slave IRQ signals to the bits of irg 31 0 Any unassigned bits of irq 31 0 are disabled Figure 2 12 shows an example of the interrupt controller mapping the IRQs on four senders to irq 31 0 on a receiver Figure 2 12 IRQ Mapping Using Software Priority Sender irq 1 Interrupt Controller Sender irq Receiver Sender irq gt gt
13. The number of pipeline stages in the clock crossing logic in the issuing master to target slave direction Increasing this value leads to a larger meantime between failures MTBF You can determine the MTBF for a given design can be determined by running a TimeQuest timing analysis Master domain synchronizer length The number of pipeline stages in the clock crossing logic in the issuing master to target slave direction Increasing this value leads to a larger meantime between failures MTBF You can determine the MTBF for a given design can be determined by running a TimeQuest timing analysis urst settings Allow bursts On Off Includes logic for the bridge s master and slaves to support bursts You can use this option to restrict the minimum depth for the slave to master FIFO Maximum burst size 2 4 8 16 32 64 128 256 512 1024 Determines the maximum length of bursts for the bridge to support when you turn on Allow bursts Clock Domain Crossing Logic SOPC Builder generates CDC logic that hides the details of interfacing components operating in different clock domains The system interconnect fabric upholds the Avalon MM protocol with each port independently and therefore masters do not need to incorporate clock adapters in order to interface to slaves on a different domain The system interconnect fabric logic propagates transfers across clock domain boundaries automatically D
14. 0 ccc cc eee hls 9 5 On Chip KRAM and ROM coded holed eger aei ebd e and o p UM e ead bende ee 9 6 Component Level Design for On Chip Memory s sss eh 9 6 SOPC Builder System Level Design for On Chip Memory ssssseseeeeeeeee 9 8 Simulation for On Chip Memory iissss e en 9 8 Quartus II Project Level Design for On Chip Memory ssseeeee eee 9 8 Board Level Design for On Chip Memory sssssss nn 9 8 Example Design with On Chip Memory ssss nnn 9 8 EPCS Serial Configuration Device ususse israr icr iro ne n 9 9 Component Level Design for an EPCS Device ssssss nee 9 9 SOPC Builder System Level Design for an EPCS Device sessseeee 9 9 Simulation for an EPCS Device 0 eee rele 9 9 Quartus II Project Level Design for an EPCS Device 0000 e eee eee eee 9 10 Board Level Design for an EPCS Device 0 0 6 nee eens 9 10 Example Design with an EPCS Device lssssseessees eens 9 10 S RSDRAM oases cette Bede tec cio E E cates deen waticonnets at eedreden eo cuae uta tara mate c 9 11 Component Level Design for SDRAM ssssessseels en 9 11 SOPC Builder System Level Design for SDRAM 2 6 9 11 Simulation tor SDRAM eco Ep aded d eaa ed i ded owe eee d e E duce 9 11 Quartus II Project Level Design for SDRAM ssssssssss e 9 12 Board Level Design for SDRAM sssssssss e eee 9 12 December 2010 Alter
15. Chapter 11 Avalon Memory Mapped Bridges 11 7 Structure of a Bridge m The address range of an Avalon MM bridge is a numerical range from its base address to its base address plus its span 1 Equation 11 1 range base adaress base_address span 1 SOPC Builder follows several rules in constructing an address map for a system with Avalon MM bridges 1 The address span of each Avalon MM slave is rounded up to the nearest power of two 2 Each Avalon MM slave connected to a bridge has an address relative to the base address of the bridge This address must be a multiple of its span See Figure 11 6 Figure 11 6 Avalon MM Master and Slave Addresses valon MM Master1 sees Slave1 at Addr 0x1100 valon MM Master1 sees Slave2 at Addr 0x1400 Aad eng r Ox ra r 3J S Slave2 Addr 0x1000 Master1 Avalon MM isi S Bridge M IA M Avalon MM Master Port S Slave1 Addr 0x100 S Avalon MM Slave Port December 2010 Altera Corporation SOPC Builder User Guide 11 8 Chapter 11 Avalon Memory Mapped Bridges Avalon MM Pipeline Bridge 3 In the example shown in Figure 11 6 if the address span of Slave 1 is 0x100 and the address span of Slave 2 is 0x200 Figure 11 7 illustrates the address span of the Avalon MM bridge Figure 11 7 The Address Span of an Avalon MM Bridge Master Address Space
16. The HDL language to generate Is either verilog or vhdl lowercase If enum the module cannot generate the specified language generating in the other language is acceptable The location in which files must be generated The filename components in the directory name are separated with forward slashes output_name OUTPUT_NAME iS module 0 and the HDL LANGUAGE s verilog the file string module_0 v or module O sv must be generated and must contain the module module 0 get generation property This command returns the value of a single generation property get generation property eran oman Usage get generation property lt propertyName gt Returns String boolean Or units depending on property refer to Table 7 4 on page 7 23 One of the 3 generation properties Arguments propertyName DAC EE m OUTPUT DIRECTORY m OUTPUT NAME Example get generation property OUTPUT DIRECTORY December 2010 Altera Corporation SOPC Builder User Guide 7 40 Chapter 7 Component Interface Tcl Reference Deprecated Commands and Properties Deprecated Commands and Properties Table 7 9 lists commands and properties that were available in previous versions of the Quartus II software and the command that have replaced them Table 7 9 Deprecated Commands and Properties Deprecated Command add clock interface lt name gt Replacement add interface lt name gt clock input add port to
17. input 31 0 avs s1 writedata output 31 0 avs s1 readdata output ins irq0 irg Insert your logic here endmodule Templates for Interfaces to External Logic You can use the Create HDL Template to generate an HDL template for the component Then you connect these signals outside of the SOPC Builder system If your component uses an Avalon interface to interface outside of SOPC Builder you can use the Templates menu in the component editor to add typical interface signals to your signal list There are templates for the following interfaces m Avalon MM Slave m Avalon MM Slave with Interrupt m Avalon MM Master m Avalon MM Master with Interrupt m Avalon ST Source m Avalon ST Sink After adding a typical Avalon interface using a template you can add or delete signals to customize the interface December 2010 Altera Corporation SOPC Builder User Guide 6 6 Chapter 6 Component Editor Interfaces Tab Interfaces Tab The Interfaces tab allows you to configure the interfaces on your component and specify a name for each interface The interface name identifies the interface and appears in the SOPC Builder connection panel The interface name is also used to uniquely identify any signals that are ports on the top level SOPC Builder system The Interfaces tab allows you to configure the type and properties of each interface For example an Avalon MM slave interface has timing parameters that you must set appropriately
18. 22 0 tri state bridge address synthesis ALTERA ATTRIBUTE FAST OUTPUT REGISTER ON Board Level Design for SRAM and Flash Memory CAUTION SOPC Builder User Guide Memory requirements determine the board level configuration of the SRAM and flash memory device or devices You can lay out memory devices in any configuration as long as the resulting interface can be described with Avalon MM signals Special consideration is required when connecting the Avalon MM address signal to the address pins on the memory devices The SOPC Builder system presents the smallest number of address lines required to access the largest off chip memory which is usually less than 32 address bits Not all memory devices connect to all address lines December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory Aligning the Least Significant Address Bits The Avalon MM tristate address signal always presents a byte address Each address location in many memory devices contains more than one byte of data In this case the memory device must ignore one or more of the least significant Avalon MM address lines For example a 16 bit memory device must ignore Avalon MM address 0 which is a byte address and connect Avalon MM address 1 to the least significant address line 9 19 Table 9 1 shows the relationship between Avalon MM address lines and off chip address pin
19. A generation callback is defined by setting the GENERATION CALLBACK module property to be the name of the generation callback function as Example 7 10 illustrates Generation callbacks typically retrieve the current value of the component s parameters and the generation properties that guide the generation process and then generate the HDL files and supporting files in Tcl or by calling an external program The callback procedure also reports the required files to SOPC Builder with the add file command Any files added in the generation callback are in addition to the files added in the main body of the hw tcl file The generation callback must write output name v or sv for Verilog or output name vhd for VHDL to the specified output directory This file is a parameterized instance of the component Other supporting files such as hex files to initialize memory may be written to output directory These file names must begin with output name If the supporting files are the same for all parameterizations of the component you add them from the main program rather than the generation SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 11 Overriding Default Behaviors callback If your system includes multiple instantiations of a component with different parameterizations you must add the supporting files from the main program to prevent failures If a static supportin
20. A nizer address readdata readdata SOPC Builder User Guide The synchronizer blocks in Figure 11 12 use multiple stages of flipflops to eliminate the propagation of metastable events on the control signals that enter the handshake FSMs The CDC logic works with any clock ratio Altera tests the CDC logic extensively on a variety of system architectures both in simulation and in hardware to ensure that the logic functions correctly The typical sequence of events for a transfer across the CDC logic is described as follows December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 19 Clock Domain Crossing Logic 1 Master asserts address data and control signals 2 The master handshake FSM captures the control signals and immediately forces the master to wait La The FSM uses only the control signals not address and data For example the master simply holds the address signal constant until the slave side has safely captured it 3 Master handshake FSM initiates a transfer request to the slave handshake FSM 4 The transfer request is synchronized to the slave clock domain 5 The slave handshake FSM processes the request performing the requested transfer with the slave 6 When the slave transfer completes the slave handshake FSM sends an acknowledge back to the master handshake FSM 7 The acknowledge is synchronized back to the master
21. Address address S 0 Ed ao TM Master Decoding 8 bit Port Logic read write clave address T 2 Fan 2 32 bit In SOPC Builder the user configurable aspects of address decoding logic are controlled by the Base setting in the list of active components on the System Contents tab as shown in Figure 2 3 Figure 2 3 Base Settings in SOPC Builder Control Address Decoding Module Name Description Base End IRQ El cpu Nios Il Proces instruction master Master port data_master Master port IRQO IRQ 31 jtag debug mod Slave port ee PL Ox021 207 FF ext_flash ext_ram ext_ram_bus button_pio high_res_timer Flash Memory IDT 1V416 S Avalon Tri St PIO Parallel l O Interval timer 0x00000000 0x02000000 0x02120860 0x02120820 OxO07FFFFF OxO020FFFFF 0x021 2086F 0x0212083F pasear Datapath Multiplexing SOPC Builder User Guide Datapath multiplexing logic in the system interconnect fabric drives the writedata signal from the granted master to the selected slave and the readdata signal from the selected slave back to the requesting master December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 5 Wait State Insertion Figure 2 4 shows a block diagram of the datapath multiplexing logic for one master and two slaves SOPC Builder generates separate datapath multiplexing logic for every maste
22. Name Type Description std_logic indicates the type of a VHDL port The default value auto selects vhdl type Std logic vector std logic if the width is fixed at 1 and std 1ogic vector auto otherwise width integer The width of the port in bits The width expression of a port Setting the width and width expr properties have the same effect they both update the effective width expression The width width expr properties can be set to an integer atany time They can only be set to arithmetic expressions width expr string in the main program The values of the width and width expr properties behave differently when get port property is used width always returns the current integer width of the port width expr always returns the unevaluated width expression get port property This command returns the value of single port property for the specified port get port property Callback Main validation elaboration generation and editor availability Usage get port property portName propertyName Returns Depends on the type of the property portName The name of the port Arguments y DL propertyName One of the supported properties described in Table 7 7 Example get port property rdata WIDTH set port property This command sets a single port property set port property Mee Main program elaboration and generation Usage set port property lt portName
23. Software Design sidere neiti er gasses dace DICEPUCOF re oa Rea 10 6 Veritying the Component cess ee ppetees ete V etadi HOP PERRA HORA e I beans acp ee 10 6 Sharing Components i cite q eer dude be grep acea eec natant es 10 7 System Information Files sopcinfo 2 0 6 nnn 10 7 Chapter 11 Avalon Memory Mapped Bridges Structure of a Bridge soc e dt bs reir ee tad eae pud be eT ae Made Ree entera quus 11 2 Reasons for Using a Bridge 0 6 nnn eens 11 2 Address Mapping for Systems with Avalon MM Bridges 0000 c cece eee eee 11 6 Avalon MM Pipeline Bridge 0 0 0 0 ccc nee Hn 11 8 Component OVerVIew csset eheu e qp Ron cen nr ER end edo om e Ree ng 11 9 P nctional Description cce et ee epe RU e etd ee Hee eese e dee a tate 11 10 Clock Crossing Bridge s heec eeebee rex XUebR HERES RR epicurei te en a pee edet ai 11 12 Choosing Clock Crossing Methodology sssssssseeeeee eee 11 13 Functional Deseriptior oec eeeeRes Cer EDO RE RH ERE ERE E TRU e COR UR RR obama 11 13 Instantiating the Avalon MM Clock Crossing Bridge in SOPC Builder 11 17 Clock Domain Crossing LOGIC ci eese espe ek eU ace eho al AH e ER MR AR he E SERE ER Qe n 11 17 Description of Clock Domain Adapter ssssssssssseeeee eee 11 18 Location of Clock Domain Adapter lssssesssesseeeeee e 11 19 Duration of Transfers Crossing Clock Domains ssssseeeeeeeeeeee 1
24. The Interfaces tab displays waveforms that illustrate the timing that you specified If you update the timing parameters the waveforms automatically update to illustrate the new timing The waveforms are available for the following interface types m Avalon Memory Mapped m Avalon Memory Mapped tristate m Avalon Streaming m Interrupts If you convert a component from a class ptf toa hw tcl file you may require three interfaces a clock input the Avalon slave and an interrupt sender A parameter in the interrupt sender must be set to reference the Avalon slave HDL Parameters Tab SOPC Builder User Guide You specify the parameters that users of your component can set to configure your component on the HDL Parameters tab The Parameters table included on this tab displays Verilog HDL parameters or VHDL generics that you declared in the top level HDL module Using the Parameters table you can specify the following information about each parameter Default value Whether or not it is user editable Type Group Tool tip Click Preview the Wizard at any time to see how the component GUI appears The following rules apply to HDL parameters exposed via the component GUI m Editable parameters cannot contain computed expressions m Ifa parameter lt N gt defines the width of a signal the signal width must be of the form lt N 1 gt 0 m Whena VHDL component is used in a Verilog HDL SOPC Builder system or vice versa numeric param
25. The following sections describe both the bottom up and top down approaches to component design Bottom Up Design SOPC Builder User Guide You can use the HDL Files tab to specify Verilog HDL or VHDL files that describe the component logic Files are provided to downstream tools such as the Quartus II software and ModelSim in the same order as they appear in the table December 2010 Altera Corporation Chapter 6 Component Editor 6 3 Signals Tab CAUTION You can also use the component editor to define the interface to components outside the SOPC Builder system In this case you do not provide HDL files Instead you use the component editor to interactively define the hardware interface After you specify an HDL file the component editor analyzes the file by invoking the Quartus IT Analysis and Elaboration module The component editor analyzes signals and parameters declared for all modules in the top level file If the file is successfully analyzed the component editor s Signals tab lists all design modules in the Top Level Module list If your HDL contains more than one module you must select the appropriate top level module from the Top Level Module list All files are managed in a single table with options for Synth and Sim You can select the Top option to select the top level file for synthesis When the top level module is changed the component editor performs best effort signal matching against the existing port defin
26. http mydomain com datasheets my memory controller html To specify a file in your company s file system you begin you path with file for Linux and file for Windows for example file company_server datasheets my memory controller pdf For handwritten _hw tcl files you can specify documentation using the add documentation link Tcl command St For more information refer to the add documentation link command in Chapter 7 Component Interface Tcl Reference Saving a Component You can save the component by clicking Finish on any of the tabs or by clicking Save on the File menu Based on the settings you specify in the component editor the component editor creates a component description file with the file name lt class name gt _hw tcl The component editor saves the file in the same directory as the HDL file that describes the component s hardware interface If you did not specify an HDL file you can save the component description file to any location you choose You can relocate component files later For example you could move component files into a subdirectory and store it in a central network location so that other users can instantiate the component in their systems The hw tcl file contains relative paths to the other files so if you move the hw tcl file you should move all the HDL and other files associated with it K Altera recommends that you store hw tcl files for a project is in the ip lt class name
27. m Amemory map showing the address of each Avalon MM slave with respect to each Avalon MM master to which it is connected m All parameter assignments for each component m A functional test bench for the SOPC Builder system and ModelSim simulation project files December 2010 Altera Corporation SOPC Builder User Guide Chapter 1 Introduction to SOPC Builder SOPC Builder Design Flow m SOPC information file sopcinfo that describes all of the components and connections in your system This file is a complete system description and is used by downstream tools such as the Nios II tool chain It also describes the parameterization of each component in the system consequently you can parse its contents to get requirements when developing software drivers for SOPC Builder components m A Quartus IL IP File qip that provides the Quartus II software with all required information about your SOPC Builder system The qip file includes references to the following information m HDL files used in the SOPC Builder system m TimeQuest Timing Analyzer Synopsys Design Constraint sdc files m Component definition files for archiving purposes After you generate the SOPC Builder system you can compile it with the Quartus II software or you can instantiate it in a larger FPGA design Creating a Memory Map for Software Development When your SOPC Builder system includes a Nios II processor SOPC Builder generates a header file cpu h that prov
28. must be completely described For example all port widths must have positive values B Generation Generation creates all the information that the Quartus II software and HDL simulator require The required files typically include VHDL or Verilog HDL files simulation models timing constraints and other information m Editor After an instance of your component has been added to an SOPC Builder system allows the user of your component to edit the GUI that displays the parameterization You can change the appearance of the default editor to make it easier to use Writing a Hardware Component Description File This section provides detailed information about hw tcl files and describes the default behavior of a component in all phases The following example uses a simple UART with some simple parameterization SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 3 Writing a Hardware Component Description File Providing Basic Information A typical _hw tcl file first declares basic information such as the name location and the files it includes The first command in a hw tcl file should specify the version of the hw tcl API to use with the following Tcl command package require exact sopc version The version number is a Quartus II release version such as 10 0 SOPC builder guarantees that a valid _hw tcl file that requests a particular sopc package behaves identically in
29. you might want to create separate groups for the component s timing size and simulation parameters A component displays the groups and parameters in the order that you specify the display items for them in the hw tcl file m Youcan create multi column tables to present a component s parameters Refer to Example 7 12 on page 7 22 for an example that illustrates multi column tables m You can specify an image to provide a pictorial representation of a parameter or parameter group December 2010 Altera Corporation SOPC Builder User Guide 7 30 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference m You can create a button by adding a display item of type action The display item includes the name of the callback to run when the action is performed You create a display group by adding display items to it add_display_item ain Malt program Usage add display item groupName id type lt additionalInfo gt Returns String groupName Specifies the group to which a display item belongs Specifies the parameter or icon to be displayed in a group Each display item aa associated with a component must have a different ID Specifies the category of the display item The following types are defined m icon a gif jpg or png file m parameter a parameter in the instance m text a block of text type m group a group if the groupName is also defined the new group is a child of the groupN
30. 2 and Later For information about upgrading components refer to Upgrading Your Component with SOPC Builder Component Editor Version 7 2 and Later For information about the use of the component editor see the following sections m Starting the Component Editor on page 6 2 HDL Files Tab on page 6 2 Signals Tab on page 6 3 Interfaces Tab on page 6 6 HDL Parameters Tab on page 6 6 Saving a Component on page 6 7 Editing a Component on page 6 8 Component Parameterization on page 6 8 St For more information about components refer to Chapter 7 Component Interface Tcl Reference For more information about the Avalon MM interface refer to the Avalon Interface Specifications Component Hardware Structure The component editor creates components with the following characteristics December 2010 Altera Corporation SOPC Builder User Guide 6 2 Chapter 6 Component Editor Starting the Component Editor m A component has one or more interfaces Typically an interface means an Avalon Memory Mapped Avalon MM master or slave or an Avalon Streaming Avalon ST source or sink You can also specify exported component signals that appear at the top level of the SOPC Builder system which can be connected to logic outside the SOPC Builder system The component editor lets you build a component with any combination of Avalon interfaces which include m Avalon MM master and slave m Avalon ST source and s
31. 201 385 40 198 241 40 4 7 139 n 253 285 56 159 416 56 161 427 56 4 8 198 n 311 281 40 190 247 40 198 257 40 4 15 160 n 259 370 121 165 733 121 149 697 121 4 16 36 n 227 255 105 391 93 0 146 491 105 Instantiating the Data Format Adapter in SOPC Builder You can use the Avalon ST configuration wizard in SOPC Builder to specify the hardware features Table 12 6 describes the options available on the Parameter Settings page of the configuration wizard Table 12 6 Data Format Adapter Parameters Input Interface Parameters Parameter Description Data Symbols Per Beat Type the number of symbols transferred per active cycle Turn this option on if the cycle that includes the endofpacket signal can Include the empty signal include empty symbols This signal is not necessary if the number of symbols per beat is 1 SOPC Builder User Guide December 2010 Altera Corporation Chapter 12 Avalon Streaming Interconnect Components Channel Adapter 12 7 Table 12 6 Data Format Adapter Parameters Input Interface Parameters Parameter Description Output Interface Parameters Data Symbols Per Beat Type the number of symbols transferred per active cycle Include the empty signal Turn this option on if the cycle that includes the endofpacket signal can include empty symbols This signal is not necessary if the number of symbols per beat is 1 Common to Input
32. 23 0 address to the ext ram 19 0 be n to the ext ram 3 0 read n to the ext flash read n to the ext ram select n to the ext flash select n to the ext ram lristate bridge data 31 0 write n to the ext flash werite n to the ext ram December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory 9 23 Figure 9 10 shows the pin assignments in the Quartus II Assignment Editor for some of the SRAM and flash memory pins The correct pin assignments depend on the target board Figure 9 10 Pin Assignments for SRAM and Flash Memory I O Standard General Function Special Function SRAM BE No PINMi8 a LVTTL Column 1 0 Q sram BENG Pnr 8 lvrr Column 1 0 IQ snaw p M2 PIN 218 E vrr Column 110 RUP3 Psramece N3 Pwu 5 ivr Column 1 0 CLKISn SRAM CS N PIN B24 3 LVTTL Column 1 0 DQST4 QQ sRAM_OE_N PN B6 3 LVTTL Column 1 0 DQST QQ snam we N lPN c24 a TTL Column 1 0 DQS9T Connecting FPGA Pins to Devices on the Board Table 9 3 shows the mapping between the Avalon MM address lines and the address pins on the SRAM and flash memory devices Table 9 3 FPGA Connections to SRAM and Flash Memory AAEE ae SM B bit Data 256K x 32 bit data tri state bridge address 0 A0 No connect tri state br
33. 3 inclusive 1 2 3 7 10 1 2 3 or 7 through 10 inclusive Elaboration Phase Behavior SOPC Builder User Guide If the main program does not explicitly define the widths of all ports to constant values or to an expression then SOPC Builder s default elaboration process calls quartus map to determine the correct port widths If you define all port widths in the main program quartus_map is not called Automatic Port Widths When port widths are not specified or have a value of 1 quartus_map is used to determine port widths as a function of the parameter set While this process makes authoring a component easier SOPC Builder can end up spending a lot of time calling quartus map When using automatic port widths you can indicate that a certain parameter does not affect any port widths or interfaces by setting that parameter s affects elaboration property to false meaning that quartus map is not called when the parameter s value is changed by your user Be careful with this indicating that a parameter does not affect elaboration when it really does can lead to problems that are mysterious and difficult to debug As an alternative to the automatic port widths you can set port widths to simple HDL expressions using the width expr property width expris a string that holds an expression describing the port width By using the width expr property you can define port widths as an expression that is evaluated without needing
34. 8 Software Assignments ceo b cese ei e db VP eee CRI dee Se e Eee St de bob ee et 6 8 Component Parameterization ssssssseeee nennen 6 8 Chapter 7 Component Interface Tcl Reference Information in a Hardware Component Description File sseeslseseeeeeeeee 7 1 Component PHASES eee met tee peer dee emp e a puc FR e puoe a ty edere br eoe e e a ug 7 2 Writing a Hardware Component Description File lsssseeeeeeeee eene 7 2 Providing Basic Information 0 2 6 nn 7 3 Declaring Param eters 55e ier did aed esses ecb Het e Ier Sed eg Poe cedar deed ae deg 7 3 Declaring Interfaces ee cte cene eee teer senem noh epe te e Ree en aee e e pen 7 5 Adding Files and Guiding Generation 0 ccc nen teens 7 5 SOPC Builder User Guide December 2010 Altera Corporation Contents iii Default BehaviOrs 4 2c be ERE ones sb aredoa re eethdaw RENS eae stead op AER 7 6 Validation Phase Behavior 00 ccc ccc ee RR e els 7 6 Elaboration Phase Behavior 0 cece cc eee en nent le 7 6 Generation Phase Behavior 00s ccc een een cette res 7 7 Edit Phase BeliaviOt iet bE nmr gash Beare e ERETOUPE EAD ERA GUY YI A eA 7 7 Overriding Default Behaviors sssessee e en 7 8 Validation Callback i ER REEL eee pee UE EE ED e ee es 7 9 Elaboration Callback seeeeeeeeeee RR RR RR 3e uc etes 7 9 Generation Callback 4v ERRRE EP CEUE LERS4 ervuca 34 EE RACE R3 EAR e E a 7 10
35. A tristate bridge connects off chip devices to the system interconnect fabric The tristate bridge creates I O signals for the SOPC Builder system which you must connect to FPGA pins in the top level Quartus II project The tristate bridge creates address and data pins that can be shared by multiple off chip devices This feature lets you conserve FPGA pins when connecting the FPGA to multiple devices with mutually exclusive access You must use a tristate bridge in either of the following cases m The off chip device has bidirectional data pins m Multiple off chip devices share the address data or both address and data buses In SOPC Builder you instantiate a tristate bridge by instantiating the Avalon MM Tristate Bridge component The Avalon MM Tristate Bridge configuration wizard has a single option To register incoming to the FPGA signals or not m Registered This setting adds registers to all FPGA input pins associated with the tristate bridge outputs from the memory device m NotRegistered This setting does not add registers between the memory device output pins and the system interconnect fabric The Avalon MM tristate bridge automatically adds registers to output signals from the tristate bridge to off chip devices Registering the input and output signals shortens the register to register delay from the memory device to the FPGA resulting in higher system fmax performance However the registers add one additional cyc
36. Builder can generate a generic SDRAM simulation model and include the model in the system testbench To use the generic SDRAM simulation model you must turn on a setting in the SDRAM controller configuration wizard You can provide memory initialization contents for simulation in the file lt Quartus II project directory gt lt SOPC Builder system name gt _sim lt Memory component name gt dat Alternatively you can provide a specific vendor memory model for the SDRAM In this case you must manually wire up the vendor memory model in the system testbench Me For further details refer to Simulation Considerations on page 9 5 and the SDRAM Controller Core chapter in the Embedded Peripherals IP User Guide December 2010 Altera Corporation SOPC Builder User Guide 9 12 SOPC Builder User Guide Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough SDR SDRAM Quartus Il Project Level Design for SDRAM SOPC Builder generates a SOPC Builder system with top level I O signals associated with the SDRAM controller In the Quartus II project you must connect these I O signals to FPGA pins which connect to the SDRAM device on the board In addition you might have to accommodate clock skew issues Connecting and Assigning the SDRAM Related Pins After generating the system with SOPC Builder you can find the names and directions of the I O signals in the top level HDL file for the SOPC Builder system The file has the name lt
37. Component Interface Tcl Reference 7 21 Hardware Tcl Command Reference send_message This command sends a message to the user of the component The message text is normally interpreted as HTML The lt b gt element can be used to provide emphasis If you do not want the message text to be interpreted as HTML then pass a list like info text as the message level send message Mere Main validation elaboration generation and editor Usage send message messageLevel messageText Returns None The following 4 message levels are supported m Error provides an error message The SOPC Builder system cannot be generated while there are error messages Arguments cae aa Warning provides a warning message m Info provides an informational message m Debug provides messages when debug mode is enabled messageText The text of the message Example Send message Error b paraml b must be greater than param2 Parameters Parameters allow users of your component to affect its operation in the same manner as Verilog HDL parameters or VHDL generics add parameter This command adds a parameter to your component Most of the parameter types are self explanatory because they are used in the C programming language or HDL However the string list and integer list parameters that are used to create tables in GUIs require some explanation m When you use the add_parameter command with a string_list
38. Editor Callback bU re hb e gr Rea E ORR ER ORR ae DE RRR aad e bad s 7 11 Hardware Tcl Command Reference llle nen ene n ene e nes 7 12 Module Definition 4 5 eR rg beEEELEIARRLETERERCIGIER E Gud DERE ORES UG ais 7 14 Parameters 2x2 erre be ERE RAE Opa S PA ted ERA EIER RR sede ERA a 7 21 Display Items ire serie Meee ru ede ex ea eee eee ee Hee ee Cee de ees cee kee eae ee weed 7 29 Intertaces and Potts 2 2 odes c bY td eb ba CN eu ReE dele ae My ae nV Vedu 7 32 Generallon iiosaesriaesc pear D C3 bee Pr RPPcU EAR GaU Hae eh I pU RE e 7 38 Deprecated Commands and Properties 0 0 6 6c ccc eee 7 40 Chapter 8 Archiving SOPC Builder Projects Dxmitatotis zc estat ate ie ete dus RA e DUE LUE UI E comes tae ennai 8 1 Required Piles pisessi esee e bh eect RR ELE Orbe CEP rp ede UR pe he pi PEE E 8 2 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Example Design 2t ast e wud aie ge la Auer ole een ne na urere istae tente tete d EE 9 1 Example Design Starting Point n 9 3 Hardware and Software Requirements ssssssss nnn 9 3 Design FOW c wn 9 4 Component Level Design in SOPC Builder sssssssseeeeeeee 9 4 SOPC Builder System Level Design ssse nn 9 4 eJ ag EU I iOm ae ER T EE NENNEN ROUTE 9 5 Quartus II Project Level Design ssssssese nn 9 5 Board Level Desi ens udo tede nde ete me date d ated angi ect diy locale cl e e ia d ati 9 5 Simulation Considerations
39. Level Design for On Chip Memory SOPC Builder User Guide InSOPC Builder you instantiate on chip memory by clicking On chip Memory RAM or ROM from the list of available components The configuration wizard for the On chip Memory RAM or ROM component has the following options Memory type Size and Read latency Memory Type The Memory type options define the structure of the on chip memory m RAM writable This setting creates a readable and writable memory m ROM read only This setting creates a read only memory m Dual port access This setting creates a memory component with two slaves which allows two masters to access the memory simultaneously A If two masters access the same address simultaneously in a dual port memory undefined results will occur Concurrent accesses are only a problem for two writes A read and write to the same location will read out the old data and store the new data m Block type This setting directs the Quartus II software to use a specific type of memory block when fitting the on chip memory in the FPGA December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 7 On Chip RAM and ROM A The MRAM blocks do not allow the contents to be initialized during power up The M512s memory type does not support dual port mode where both ports support both reads and writes Because of the constraints on some memory types it is frequently best to use
40. Memory The SOPC Builder output for simulation depends on the type of memory components in the system m Flash Memory Common Flash Interface component This component provides a generic simulation model You can provide memory initialization contents for simulation in the file Quartus II project directory gt lt SOPC Builder system name sim Flash memory component name gt dat m Custom memory interface created with the component editor In this case you must manually connect the vendor simulation model to the system testbench SOPC Builder does not automatically connect simulation models for custom memory components to the SOPC Builder system December 2010 Altera Corporation SOPC Builder User Guide 9 18 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory m Altera provided interfaces to memory devices Altera provides simulation models for these interface components You can provide memory initialization contents for simulation in the file lt Quartus II project directory gt lt SOPC Builder system name gt _sim lt Memory component name gt dat Alternately you can provide a specific vendor simulation model for the memory In this case you must manually wire up the vendor memory model in the system testbench For further details see Simulation Considerations on page 9 5 Quartus II Project Level Design for SRAM and Flash Memory SOPC Builder generates an SOPC Builder
41. Memory Subsystem Development Walkthrough On Chip RAM and ROM The generic memory models store memory initialization files such as Data dat and Hexadecimal hex files in a directory named lt Quartus II project directory gt lt SOPC Builder system name gt _sim When generating a new system SOPC Builder creates empty initialization files You can manually edit these files to provide custom memory initialization contents for simulation Vendor Specific Memory Models You can also manually connect vendor specific memory models to the SOPC Builder system In this case you must manually edit the testbench and connect the vendor memory model You might also need to edit the vendor memory model slightly for time delays The SOPC Builder testbench assumes zero delay On Chip RAM and ROM Altera FPGAs include on chip memory blocks that can be used as RAM or ROM in SOPC Builder systems On chip memory has the following benefits for SOPC Builder systems m On chip memory has fast access time compared to off chip memory m SOPC Builder automatically instantiates on chip memory inside the SOPC Builder system so you do not have to make any manual connections m Certain memory blocks can have initialized contents when the FPGA powers up This feature is useful for example for storing data constants or processor boot code m On chip memories support dual port accesses allowing two master to access the same memory concurrently Component
42. N DTE RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01096 1 0 SOPC Builder User Guide Li Subscribe 2010 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX are Reg U S Pat amp Tm Off and or trademarks of Altera Corporation in the U S and other countries All other trademarks and service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard Warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information qproduet or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services QUALITY 150 9001 2008 NSAI Certified SOPC Builder User Guide December 2010 Altera Corporation N DTE RYN Contents Chapter 1 Introduction to SOPC Builder Architecture of SOPC Builder Systems e rereeririkadrriieiaiei eee tenn nee 1 1 SOPC Builder Modules iiiszic e hk bx y Ras RE RARE RR RAE AREE DUCES 12 Functions of SOPC Builder eed aes nts eae E ES
43. OFFSET 3 OFFSET 2 BASE 0x8 word 2 0x0000 0FFSET 2 OFFSET 5 OFFSET 4 BASE 0xC word 3 0x0000 0FFSET 3 OFFSET 7 OFFSET 6 BASE AN word N 0x0000 0FFSET N OFFSET 2N 1 OFFSET 2N When connecting a wide master to a narrow slave port that uses native addressing the following addressing formula should be used to determine what address to SOPC Builder User Guide present to the system interconnect fabric master address gt slave base address slave word offset master data width in bytes For example a 64 bit master needs to write to the second word of a 32 bit slave that uses native addressing the formula would reduce to master address slave base address 1 8 December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 9 Arbitration for Multimaster Systems SOPC Builder generates appropriate address alignment logic based on the properties of the master and slaves in the system When configuring a system in SOPC Builder there are no settings that directly control the address alignment in the system interconnect fabric Arbitration for Multimaster Systems System interconnect fabric supports systems with multiple master components Ina system with multiple masters such as the system pictured in Figure 2 1 on page 2 2 the system interconnect fabric provides shared access
44. Port S S Avalon MM Slave Port External SRAM December 2010 Altera Corporation SOPC Builder User Guide Chapter 11 Avalon Memory Mapped Bridges Clock Domain Crossing Logic 11 17 Instantiating the Avalon MM Clock Crossing Bridge in SOPC Builder Table 11 1 describes the options available on the Parameter Settings page of the Table 11 1 Avalon MM Clock Crossing Bridge Parameters Master to slave FIFO instead of memory blocks Parameter Value Description FIFO depth 8 16 32 Determines the depth of the FIFO When you turn on this option the FIFO uses registers as Construct FIFO with registers On Off storage instead of embedded memory blocks This can considerably increase the size of the bridge hardware and lower the fmax Slave to master FIFO FIFO depth 8 16 32 64 128 256 512 1024 Determines the depth of the FIFO Construct FIFO with registers instead of memory blocks On Off When you turn on this option the FIFO uses registers as storage instead of embedded memory blocks This can considerably increase the size of the bridge hardware and lower the fmax Common options Data width 8 16 32 64 128 256 512 1024 Determines the data width of the interfaces on the bridge and affects the size of both FIFOs For the highest bandwidth set Data width to be as wide as the widest master connected to the bridge Slave domain synchronizer length
45. Quartus II project directory gt lt SOPC Builder system name gt v or lt Quartus II project directory gt lt SOPC Builder system name gt vhd You must connect these signals in the top level Quartus II design file You must assign a pin location for each I O signal in the top level Quartus II design to match the target board Depending on the performance requirements for the design you might have to assign FPGA pins carefully to achieve the required performance Accommodating Clock Skew As SDRAM frequency increases so does the possibility that you must accommodate skew between the SDRAM clock and I O signals This issue affects all synchronous memory devices including SDRAM To accommodate clock skew you can instantiate an ALTPLL megafunction in the top level Quartus IT design to create a phase locked loop PLL clock output You use a phase shifted PLL output to drive the SDRAM clock and reduce clock skew issues The exact settings for the ALTPLL megafunction depend on your target hardware You must experiment to tune the phase shift to match the board a For details refer to the ALTPLL Megafunction User Guide Board Level Design for SDRAM Memory requirements largely dictate the board level configuration of the SDRAM device or devices The SDRAM controller core can accommodate various configurations of SDRAM on the board including multiple banks and multiple devices Example Design with SDR SDRAM This section demonstrates addi
46. System Contents tab of SOPC Builder You define the input clocks to the system with the Clock Settings table Clock sources can be driven by external input signals to the SOPC Builder system or by PLLs inside the SOPC Builder system Clock domains are differentiated based on the name of the clock You may create multiple asynchronous clocks with the same frequency To specify which clock drives which components you must display the Clock column in the System Contents tab By default clock names are not displayed To display clock names in the Module Name column and the clocks in the Clock column in the System Contents tab right click in the Module Name column and click Show All To connect a clock to follow these steps 1 Click in the Clock column next to the clock port A list of available clock signals appears 2 Select the appropriate signal from the list of available clocks Figure 11 13 illustrates this step Figure 11 13 Assigning Clocks to Components Module Name Description Clock Base End IRQ Lis wvu wuscpeeuy ETNA ANE LN APIA Nee IR AE 1e VV BAUS Te high_res_timer Interval timer clk v 0x02120820 0x0212083F 3 seven seg pio PIO Parallel 10 m 0x02120890 0x021 2089F reconfig request pio PIO Parallel I O teste W 0x021208A0 0x021208AF uart1 UART RS 232 serial port c 0x02120840 0x0212085F 4 sysid System ID Peripheral clk 0x021208B8 0x021 208BF sdram ISDRAM Controller clk 0x01000000 Ox01FFFFFF dma 0 DDM
47. Timing Analyzer SOPC Builder User Guide December 2010 Altera Corporation N DTE 84AN 6 Component Editor The SOPC Builder component editor provides a GUI to support the creation and editing of the Hardware Component Description File _hw tcl file that describes a component to SOPC Builder You use the component editor to do the following m Specify the Verilog HDL or VHDL files that describe the modules in your component hardware m Conversely create an HDL template for a component by first defining its interface using the HDL Files tab of the component editor m Specify the signals for each of the component s interfaces and define the behavior of each interface signal m Specify relationships between interfaces such as determining which clock interface is used by a slave interface m Declare any parameters that alter the component structure or functionality and define a user interface to let users parameterize instances of the component St For information about using the component editor in a development flow refer to the following pages on the Altera website SOPC Builder Component Development Flow Using the Component Editor Overview For information about Avalon component interfaces refer to Avalon Component Interfaces Supported in the Component Editor Version 7 2 and Later For examples of changes to typical Avalon interfaces refer to Examples of Changes to Typical Avalon Interfaces for the Component Editor Version 7
48. a blank initialization file in the Quartus II project directory for each on chip memory that can power up with initialized contents The name of this file is lt name of memory component gt hex Simulation for On Chip Memory At system generation time SOPC Builder generates a simulation model for the on chip memory This model is embedded inside the SOPC Builder system and there are no user configurable options for the simulation testbench You can provide memory initialization contents for simulation in the file lt Quartus II project directory gt lt SOPC Builder system name gt _sim lt Memory component name gt dat Quartus Il Project Level Design for On Chip Memory The on chip memory is embedded inside the SOPC Builder system and there are no signals to connect to the Quartus II project To provide memory initialization contents you must fill in the file lt name of memory component gt hex The Quartus II software recognizes this file during design compilation and incorporates the contents into the configuration files for the FPGA For the memory to be initialized you then must compile the hardware in the Quartus II software for the SRAM Object File sof to pick up the memory initialization files All memory types with the exception of MRAMs support this feature Board Level Design for On Chip Memory The on chip memory is embedded inside the SOPC Builder system and there is nothing to connect at the board level Example
49. avoid paying a latency penalty for each transfer the master can issue multiple reads that are queued in the FIFO The slave of the bridge asserts readdatavalid when it drives valid data and asserts waitrequest when it is not ready to accept more reads For write transfers the master to slave FIFO causes a delay between the master to bridge transfers and the corresponding bridge to slave transfers Because Avalon MM write transfers do not require an acknowledge from the slave multiple write transfers from master to bridge might complete by the time the bridge initiates the corresponding bridge to slave transfers December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 15 Clock Crossing Bridge Burst Support The bridge optionally supports bursts with configurable maximum burst length When configured to support bursts the bridge propagates bursts between master slave pairs up to the maximum burst length Not having burst support is equivalent to a maximum burst length of one In this case the system interconnect fabric automatically breaks master to bridge bursts into a sequence of individual transfers When you configure the bridge to support bursts you must configure the slave to master FIFO depth deeply enough to capture all burst read data without overflowing The masters connected to the bridge could potentially fill the master to slave FIFO with read burst requests therefore the minimum slave to master FIFO
50. beat and the output error is the logical OR of the input error signal December 2010 Altera Corporation SOPC Builder User Guide 12 6 Chapter 12 Avalon Streaming Interconnect Components Data Format Adapter Resource Usage and Performance Resource utilization for the data format adapter depends upon the function that it performs Table 12 5 provides estimated resource utilization for numerous configurations of the data format adapter Table 12 5 Data Format Adapter Estimated Resource Usage and Performance 8 Bits per Symbol Input Output Number Static eX Cyclone II Sia Syma Symbol of f ee parana LEs ene Approximate LEs s per sper Channel t Beat Beat S fmax ALM Memor fmax Logic Memor fmax Logic Memor MHz Count y Bits MHz Cells y Bits MHz Cells y Bits 1 2 1 y 500 96 0 391 93 0 375 105 0 4 1 1 y 459 106 0 311 97 0 306 76 0 4 2 1 y 500 118 0 343 107 0 326 85 0 4 8 1 y 437 326 0 346 370 0 303 330 0 4 16 1 y 357 930 0 264 1005 0 231 806 0 1 2 188 y 321 110 15 187 137 15 209 153 15 4 1 105 y 244 125 2 148 183 2 150 137 2 4 2 105 y 277 101 2 172 134 2 173 108 2 4 8 130 y 322 255 41 175 279 41 187 262 41 4 16 30 y 268 341 106 166 563 106 153 471 106 4 1 105 n 269 107 2 177 185 2 167 99 2 4 2 54 n 290 109 1 193 203 1 176 91 1 4 3 10 n 249 149 18 189 251 16 159 217 18 4 5 222 n 281 300 40 199 381 40 182 316 40 4 6 30 n 312 184 40
51. building memory subsystems with SOPC Builder which is similar to other SOPC Builder designs After starting a Quartus II project and an SOPC Builder system there are five steps to completing the system as shown in Figure 9 2 1 2 3 4 5 Figure 9 2 Design Flow Starta poer Quartus gt Builder project system Component level design in SOPC Builder SOPC Builder system level design Simulation Quartus II project level design Board level design Y Add memory component 1 Y Add memory component 2 n Add memory component N l Add other components ee Component Level Design 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i ge Simulation Connect components amp generate SOPC Builder system Ee uie SOPC Builder System level design Connect SOPC Assign FPGA Connect Builder system p pins amp compile FPGA pins module to Quartus II to memory Quartus II project project chips e eee euer edm Quartus II Project Level Design Board Level Design Component Level Design in SOPC Builder In this step you specify which memory components to use and configure each component to meet the needs of the system All memory components are available from the Memory and Memory Controllers category in the list of available components in SOPC Builder SOPC Builder System Level Design In this step you connect components together and configure the SOPC Builder
52. can be a logical device that is entirely contained within the SOPC Builder system such as the processor component shown in Figure 1 1 Alternately a component can act as an interface to an off chip device such as the DDR2 interface component in Figure 1 1 In addition to the Avalon interface a component can have other signals that connect to logic outside the SOPC Builder system Non Avalon signals can provide a special purpose interface to the SOPC Builder system such as the PIO in Figure 1 1 These non Avalon signals are described in Conduit Interface chapter in the Avalon Interface Specifications Available Components Altera and third party developers provide ready to use SOPC Builder components including m Microprocessors such as the Nios II processor m Microcontroller peripherals such as a Scatter Gather DMA Controller and timer m Serial communication interfaces such as a UART and a serial peripheral interface SPI m General purpose I O m Communications peripherals such as a 10 100 1000 Ethernet MAC m Interfaces to off chip devices Custom Components You can import HDL modules and entities that you write using Verilog HDL or VHDL into SOPC builder as custom components You use the following design flow to integrate custom logic into an SOPC Builder system 1 Determine the interfaces used to interact with your custom component 2 Create the component logic using either Verilog HDL or VHDL 3 Use the SOPC Builder c
53. channel adapter Data Format Adapter Pa Timing j Ethernet ade Bins Adapter Sg pins ae Core fal Avalon Streaming Interconnect Components Avalon Streaming Core The control and status signals for the components containing source or sink interfaces can be mapped to a slave interface which is then accessible in the global Avalon address space Timing Adapter The timing adapter has two functions SOPC Builder User Guide December 2010 Altera Corporation uonejodjo2 ejeyy OLOZ Jequie eq p n9 Jesf Jepiing 9dOS m Itadapts source and sink interfaces that support the ready signal and those that do not m Itadapts source and sink interfaces that support the valid signal and those that do not m It adapts source and sink interfaces that have different ready latencies The timing adapter treats all signals other than the ready and valid signals as payload and simply drives them from the source to the sink Table 12 1 outlines the adaptations that the timing adapter provides Table 12 1 Timing Adapter Condition The source has ready but the sink does not Adaptation In this case the source can respond to backpressure but the sink never needs to apply it The ready input to the source interface is connected directly to logical 1 The source does not have ready but the sink does The sink may apply backpressure but the source is unable to respond to it There is no log
54. clock interface name role interface add interface port interface name role 1 add port to interface interface name role add interface port interface name role input 1 direction width get generation setting properly get generation property property get list of ports direction get interface ports set module name set module property name lt name gt set module description description set module property description description set port direction and width lt name gt set port property name direction direction set port property name width width set source file lt file gt set module property top level hdl file file get project property To determine device family use the following commands In the main program add parameter DEVICE FAMILY string unknown set parameter property DEVICE FAMILY SYSTEM INFO device family In the validation generation callback read it using the following command get parameter value DEVICE FAMILY Deprecated Module Properties datasheet url use add documentation link command libraries Unnecessary class name name module file name top level hdl file preview I callback n callback Deprecated Parameter Properties affects port widths affects elaboration GROUP Use add display
55. cycle during the response phase of the transaction The total latency is 2 lt x gt where x refers to the latency of the DDR SDRAM high performance memory controller Using the clock crossing bridge for this same purpose would impose approximately 12 cycles of additional latency Figure 11 15 Avalon MM DDR Memory Half Rate Bridge Block Diagram DDR2 3 High Half Rate Bridge Performance Controller Ur ECT Cmd 1 DDR2 3 Memory Instantiating the Core in SOPC Builder Use the MegaWizard Plug In Manager for the Avalon MM Half Rate Bridge core in SOPC Builder to specify the core s configuration Table 11 4 describes the parameters that can be configured for the Avalon MM Half Rate Bridge core Table 11 4 Configurable Parameters for Avalon MM DDR Memory Half Rate Bridge Core Parameters Value Description 8 16 32 64 s Data Width 128 256 512 The width of the data signal in the master interface Address Width 1 32 The width of the address signal in the master interface Table 11 5 describes the parameters that are derived based on the Data Width and Address Width settings for the Avalon MM Half Rate Bridge core Table 11 5 Derived Parameters for Avalon MM DDR Memory Half Rate Bridge Core Parameter Description Master interface s Byte Enable Width Slave interface s Data Width The width of the data signal in the slave interface Slave interface s Address Width The widt
56. design files and the hw tcl file m component name hw tcl the component description file m component name gt v or vhd the HDL file that contains the top level module m component name sw tcl the software driver configuration file This file specifies the paths for the c and h files associated with the component m lt software gt a directory that contains software drivers or libraries related to the component if any Altera recommends that the software directory be subdirectory of the directory that contains the _hw tcl file St For information on writing a device driver or software package suitable for use with the Nios II IDE design flow refer to the Hardware Abstraction Layer section of the Nios II Software Developer s Handbook The Nios II Software Build Tool Reference chapter of the Nios II Software Developer s Handbook describes the commands you can use in the Tcl script Component Versioning You can create and maintain multiple versions of the same component using one of the following options m Define the module property version in your _hw tcl file St For more information refer to the Chapter 7 Component Interface Tel Reference December 2010 Altera Corporation SOPC Builder User Guide 4 10 Chapter 4 SOPC Builder Components Classic Components in SOPC Builder m If multiple versions of the component are defined in your component libraries you can add a different the version of a co
57. future versions of the tool Because of differences between versions of the Quartus II software you cannot assume that an HDL file that works with one sopc package automatically works with other versions of the package This chapter describes the behavior of components that request the sopc 10 0 package For earlier releases refer to the documentation for that release UT An excellent source of information about Tcl syntax is the Tcl Developer Xchange website Example 7 1 Basic Information for hw tcl File The package command must be the first command in the file package require exact sopc 10 0 The name and version of the component Set module property NAME example uart set module property VERSION 1 0 The name of the component to display in the library Set module property DISPLAY NAME Example Component The component s description set module property DESCRIPTION An Example Component The component library group that component belongs to set module property GROUP Examples Declaring Parameters By including configuration parameters in your _hw tcl file you allow users of your component to parameterize it in different ways Each parameter has a number of properties such as its name type display name and default value that can be used to control how the parameter is displayed and used Example 7 2 illustrates the use of parameters that can be configured by users of your component Example 7 2 Declaring Parame
58. gt lt propertyName gt value Returns String boolean Or units depending on property refer to Table 7 4 on page 7 23 portName The name of the port Arguments propertyName One of the supported properties described in Table 7 7 value The value to set Example set port property rdata WIDTH 32 December 2010 Altera Corporation SOPC Builder User Guide 7 38 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference get_interface_assignments This command returns the value of all interface assignments for the specified interface get_interface_assignments Meri Main validation and elaboration Usage get interface assignments lt interfaceName gt Returns String Arguments interfaceName The name of the Avalon interface whose assignment is being retrieved Example get interface assignments s1 get interface assignment This command returns the value of the specified name for the specified interface get interface assignment an Main validation and elaboration Usage get_interface_assignments lt interfaceName gt lt name gt Returns String interfaceName The name of the Avalon interface whose assignment is being retrieved es name The assignment whose value is being retrieved Example get interface assignment s1 embeddedsw configuration isFlash set interface assignment This command sets the value of the specified assignment for the spec
59. interconnect fabric for memory mapped interfaces supports the following items m Anynumber of master and slave components The master to slave relationship can be one to one one to many many to one or many to many On chip components Interfaces to off chip devices Master and slaves of different data widths Components operating in different clock domains Components using multiple Avalon MM ports December 2010 Altera Corporation SOPC Builder User Guide 2 2 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces High Level Description Figure 2 1 shows a simplified diagram of the system interconnect fabric in an example memory mapped system with multiple masters Ka All figures in this chapter are simplified to show only the particular function being discussed In a complete system the system interconnect fabric might alter the address data and control paths beyond what is shown in any one particular figure Figure 2 1 System Interconnect Fabric Example System Processor Instruction Data Control DMA Controller Read Write System Interconnect Fabric Arbiter Arbiter Tri State Bridge S E Instruction Data Memory Memory J Write Data amp Control Signals Mtem p Read Data Interface to Off Chip Device
60. ipx m relative vars lt value gt Optional Causes the output file to include references relative to the specified variable or variables where possible You can specify multiple variables as a comma separated list m thorough descent lt true false gt Optional If set a component or ipx file in a directory does not prevent subdirectories from being searched m message before lt value gt Optional A message to print to stdout when indexing begins m message after lt value gt Optional A message to print to stdout when indexing completes m help Show help for this command Understanding IPX File Syntax An px file is an XML file whose top level element is library with a path subelements are path and component December 2010 Altera Corporation SOPC Builder User Guide 4 8 Chapter 4 SOPC Builder Components Component Structure A lt path gt element contains a single attribute also called path and may reference a directory with a wildcard or reference a single file Two asterisks designate any number of subdirectories A single asterisk designates a match to a single file or directory In searching down the designated path the following three types of files are identified m ipx additional index files m _hw tcl SOPC Builder component definitions m _sw tcl Nios II board support package BSP software component definitions A component element contains several attrib
61. is being set value The value to set set display item property my action DISPLAY NAME Click Me Example set display item property my action DESCRIPTION clicking this button runs the click me callback proc in the hw tcl file Interfaces and Ports You can use the interface and port commands to define interfaces and ports and retrieve their properties add interface This command adds an interface to your module As the component author you choose the name of the interface By default interfaces are enabled You can set the interface property ENABLED to false to disable a component interface If an interface is disabled it is hidden and its ports are automatically terminated to their default values Signals that you designate as active low by appending a _n are terminated to 1 All other signals are terminated to 0 SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 33 Hardware Tcl Command Reference St The properties available for each interface type are different The common properties ENABLED and ASSOCIATED CLOCK apply to all interface types Refer to the Avalon Interface Specifications for a description of other properties add interface erint Main program and elaboration Usage add interface lt interfaceName gt interfaceType direction lt associatedClock gt 1 Returns String interfaceName A name that you choose to ident
62. is not set GENERATION CALLBACK String Main program The name of the generation callback The component group that the module belongs oid perang Main program such as Example Components ICON PATH String Main program A path to an icon to display in the module s parameter editor December 2010 Altera Corporation SOPC Builder User Guide 7 16 Table 7 3 Module Properties Part 2 of 2 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference Property Name Tee Can Be Set Description When false the instances of the module are not included in the generated system INSTANTIATE IN SYSTEM MODULE Boolean Main program interconnect fabric Instead interfaces to the module are exported out of the top level of the SOPC Builder system The directory containing the _hw tcl file All tan oniba relative file names within the Tcl file are MODULE DIRECTORY String read Me set resolved relative to this directory This i directory is set as the current directory when running the main program or a callback Can only be MODULE TCL FILE String read not set The path to the _hw tel file The name of the module such as NAME String Main program my sopc component Indicates which of the files added by the TOP LEVEL HDL FILE String Main program add file command contains the module s top level HDL Indicates the name of the top level module TOP LEVEL HDL MO
63. it is granted access to a slave December 2010 Altera Corporation SOPC Builder User Guide 2 6 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Pipelined Read Transfers SOPC Builder generates wait state insertion logic based on the properties of all slaves in the system Pipelined Read Transfers The Avalon MM interface supports pipelined read transfers allowing a pipelined master to start multiple read transfers in succession without waiting for the prior transfers to complete Pipelined transfers allow master slave pairs to achieve higher throughput even though the slave requires one or more cycles of latency to return data for each transfer SOPC Builder generates system interconnect fabric with pipeline management logic to take advantage of pipelined components wherever possible based on the pipeline properties of each master slave pair in the system Regardless of the pipeline latency of a target slave SOPC Builder guarantees that read data arrives at each master in the order requested Because master and slaves often have mismatched pipeline latency system interconnect fabric often contains logic to reconcile the differences Many cases of pipeline latency are possible as shown in Table 2 1 Table 2 1 Various Cases of Pipeline Latency in a Master Slave Pair Master Slave Pipeline Management Logic Structure No pipeline No pipeline The system interconnect fabric does not instantiate logic to
64. items Returns List of strings Arguments None Example get display items GET DISPLAY ITEM properties This command returns a list of names of the properties of display items that are part of the parameterization GUI get display item properties valli wam Usage get_display_item properties Returns List of strings Arguments None Example get_display_item properties GET DISPLAY ITEm property This command returns the value of specific property of a display item that is part of the parameterization GUI get display item property Callback availability Main Usage get display item property itemName propertyName Returns String itemName The item whose property value is being retrieved Arguments PEER 7 propertyName The property whose value is being retrieved Example set my label get display item property my action DISPLAY NAME December 2010 Altera Corporation SOPC Builder User Guide 7 32 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference sET DISPLAY ITEm property This command sets the value of specific property of a display item that is part of the parameterization GUI set display item property Mer Main Usage set display item property itemName propertyName value Returns String itemName The item whose property value is being set Arguments propertyName The property whose value
65. of the bridge is byte aligned the address width is set to 25 bits 5 Connect altmemddr_auxhalf to the slave clock interface clk_s1 of the Half Rate Bridge 6 Connect altmemddr sysclk to the master clock interface clk_m1 of the Half Rate Bridge 7 Remove all connections between Nios II processor and the memory controller if there are any 8 Connect the master interface m1 of the Avalon MM DDR Memory Half Rate Bridge to the memory controller slave interface 9 Connect the slave interface s1 of the Avalon MM DDR Memory Half Rate Bridge to the Nios II processor data master interface 10 Connect altmemddr auxhalf to Nios II processor clock interface SOPC Builder User Guide December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges Device Support Device Support Altera device support for the bridge components is listed in Table 11 6 Table 11 6 Device Family Support 11 25 c Avalon MM Clock Device Family MS uir Pige Avalon ea Rate Aria GX Ful ful Ful Arria Il GX Full Full Full Stratix Full Full Full Stratix II Full Full Full Stratix II GX Full Full Full Stratix II Full Full Full Stratix IV Full Full Full Stratix V Full Full Full Stratix IV Full Full Full Cyclone II Full Full Full Cyclone III Full Full Full Cyclone IV Full Full Full Hardcopy Full Full Full HardCopy II Full Full Full HardCopy III Full Full Full HardCop
66. of the data address and control paths The arbiter logic multiplexes all address data and control signals from a master to a shared slave Figure 2 7 Detailed View of Multimaster Connections M1 Address M1 Write Dat ies Request Control Master 1 Write Data M2 Address M2 Write Data Request Control WERGEA Slave Read Data Arbiter Details SOPC Builder generates an arbiter for every slave based on arbitration parameters specified in SOPC Builder The arbiter logic performs the following functions for its slave m Evaluates the address and control signals from each master and determines which master if any gains access to the slave next W Grants access to the chosen master and forces all other requesting masters to wait m Uses multiplexers to connect address control and datapaths between the multiple masters and the slave December 2010 Altera Corporation SOPC Builder User Guide 2 12 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Arbitration for Multimaster Systems Figure 2 8 shows the arbiter logic in an example multimaster system with two masters each connected to two slaves Figure 2 8 Block Diagram of Arbiter Logic S1 Read Data amp Control M1 wait M2 wait Master Select Data Path Multiplexing Logic Slave 1 Arbiter Master 1 M1 M1 Address Write Data amp Control Data
67. pipeline bridge s1 mi El message buffer ram si E message buffer mu s1 E ext ssram bus avalon slave tristate master E ext ssram s1 Nios Il Processor Avalon Master Avalon Master Avalon Slave Nios Il Processor Avalon Master Avalon Master Avalon Slave Nios Il Processor Avalon Master Avalon Master Avalon Slave Avalon MM Clock Crossing Bridge Avalon Slave Avalon Master DDR SDRAM Controller MegaCore Fun Avalon Slave Avalon MM Pipeline Bridge Avalon Slave Avalon Master On Chip Memory RAM or ROM Avalon Slave Mutex Avalon Slave Avalon MM Tristate Bridge Avalon Slave Avalon Tristate Master Cypress CY7C1380C SSRAM Avalon Tristate Slave clk clk clk clk clk clk clk clk clk clk clk IRQ O 003400800 IRQ O 0 x03000800 IRQ O 0 03001000 0x02000000 0x00001000 0x03200000 use Connections Module Name Description cock Bee ema me Iv IRQ 31 OxO03400fft IRQ 316 Oxosoooftt IRQ 31 OxO030017ff OxOlffffff OxOlffffff OxO2OO0lfff OxOOOOOfff 0x00001007 OxO33fffff a gt Ifan orange triangle appears next to an address in Figure 11 4 it indicates that the address is an offset value and is not the true value of the address in the address map December 2010 Altera Corporation SOPC Builder User Guide 11 6 Chapter 11 Avalon Memory Mapped Bridges Structure of a Bridge
68. processor DSP data The interconnect components that you add to an SOPC Builder system insert logic between a source and sink interface enabling that interface to operate correctly This chapter describes four Avalon ST interconnect components also called adapters m Timing Adapter on page 12 2 adapts between sinks and sources that have different characteristics such as ready latencies m Data Format Adapter on page 12 5 adapts source and sink interfaces that have different data widths m Channel Adapter on page 12 7 adapts source and sink interfaces that have different settings for the channel signal m Error Adapter on page 12 9 ensures that per bit error information recorded at the source is correctly transferred to the sink All of these interconnect components adapt initially incompatible Avalon ST source and sink interfaces so that they function correctly facilitating the development of high speed low latency datapaths Interconnect Component Usage Interconnect components can adapt the data or control signals of the Avalon ST interface Typical adaptations to control signals include m Adding pipeline stages to adjust the timing of the ready signal m Tying signals that are not used by either the source or sink to 0 or 1 Typical adaptations to data signals include m Changing the number of symbols words that are driven per cycle m Changing the number of channels driven December 2010 Altera Corpor
69. provided by Altera Figure 4 2 illustrates this approach Figure 4 2 User Library Included In Subdirectory of IP ROOTDIR 23 install dir fi quartus Tip fix altera library ipx components L component1 componenti hw tcl Bj user components component1 v Ll component2 component2_hw tcl component2 v In Figure 4 2 the circled numbers identify three steps of the algorithm that SOPC follows during initialization These steps are explained in the following paragraphs 1 SOPC Builder recursively searches the lt install_dir gt ip directory by default It finds the file in the altera subdirectory which tells it about all of the Altera components library ipx includes listings for all components found in its subdirectories The recursive search stops when SOPC Builder finds this ipx file 2 As part of its recursive search SOPC Builder also looks in the adjacent user_components directory One level down SOPC Builder finds the component1 directory which contains component1_hw tcl When SOPC Builder finds that component the recursive descent stops so that no components in subdirectories of componenti are found 3 SOPC Builder then searches in the adjacent component2 directory which includes component2 hw tcl If SOPC Builder finds that component the recursive descent stops La Ifyou save your hw tcl file in the lt install_dir gt ip directory SOPC Builder finds your _hw tcl fil
70. single master forcing all other masters to wait Figure 2 6 illustrates the bus architecture for a traditional processor system Access to the shared system bus becomes the bottleneck for throughput only one master has access to the bus at a time which means that other masters are forced to wait and only one slave can transfer data at a time Figure 2 6 Bus Architecture in a Traditional Microprocessor System Master 1 Master 2 Masters GENS DMA System CPU Controller Arbiter t lt __ Bottleneck System Bus f d d Program Data Slaves UART PIO Moon MERO Slave Side Arbitration SOPC Builder User Guide The system interconnect fabric uses multimaster architecture to eliminate the bottleneck for access to a shared bus Multiple masters can be active at the same time simultaneously transferring data with independent slaves For example Figure 2 1 on page 2 2 demonstrates a system with two masters a CPU and a DMA controller sharing a slave an SDRAM controller Arbitration is performed at the SDRAM slave the arbiter dictates which master gains access to the slave if both masters initiate a transfer with the slave in the same cycle December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 11 Arbitration for Multimaster Systems Figure 2 7 focuses on the two masters and the shared slave and shows additional detail
71. system as a whole Like the process of adding non memory SOPC Builder components you use the System Contents tab to do the following SOPC Builder User Guide m Rename the component instance optional December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 5 Design Flow m Connect the memory component to masters in the system Each memory component must be connected to at least one master m Assign a base address m Assign a clock domain A memory component can operate on the same or different clock domain as the master s that access it Simulation In this step you verify the functionality of the SOPC Builder system For systems with memories this step depends on simulation models for each of the memory components in addition to the system testbench generated by SOPC Builder Refer to Simulation Considerations for more information Quartus II Project Level Design In this step you integrate the SOPC Builder system with the rest of the Quartus II project which includes connecting the SOPC Builder system to FPGA pins connecting wiring the SOPC Builder system to other design blocks such as other HDL modules in the Quartus II project 5 Inthe example design in this chapter the SOPC Builder system comprises the entire FPGA design There are no other design blocks in the Quartus II project Board Level Design In this step you connect the physical FPGA pins to memor
72. the Auto setting Auto allows the Quartus IT software to choose a type and the other settings direct the Quartus II software to select a particular type Size The Size options define the size and width of the memory m Data width This setting determines the data width of the memory The available choices are 8 16 32 64 128 256 512 or 1024 bits Assign Data width to match the width of the master that accesses this memory the most frequently or has the most critical throughput requirements For example if you are connecting the on chip memory to the data master of a Nios II processor you should set the data width of the on chip memory to 32 bits the same as the data width of the Nios II data master Otherwise the access latency could be longer than one cycle because the Avalon interconnect fabric performs width translation m Total memory size This setting determines the total size of the on chip memory block The total memory size must be less than the available memory in the target FPGA m Minimize memory block usage may impact fmax Minimize memory block usage may impact fmax This option is only available for devices that include M4K memory blocks If selected the Quartus II software divides the memory by depth rather than width so that fewer memory blocks are used This change may decrease fmax Read Latency On chip memory components use synchronous pipelined Avalon MM slaves Pipelined access improves fmax perfo
73. the host processor can perform other tasks such as preparing another buffer for transmission The interrupt is asserted after the buffer checksum is calculated The host processor can be interrupted by the hardware accelerator to notify it that a checksum result has been calculated The host processor can then read the checksum value and clear the interrupt by writing to the status register via the accelerator slave interface Figure 10 1 Checksum Component with Avalon MM Master and Slaves clk clk n Clock Input reset Interface reset master address 31 0 E master readdata 31 0 oo transform readdata 31 0 master read Checksum SS NS Avalon MM Master Transform fanciounresd REEE master_byteenable 3 0 transform data available d master waitrequest 9 master readdatavalid 5 transform byte lanes lt lt G LL Dd A A z 5 E zm C 2 2 5 Q e qe al al S 2 il es Ss 8 8 m 9 o slave_address 2 0 o gt op slave_writedata 31 0 slave write Avalon MM Slave slave readdata 31 0 Interface ee checksum result 15 0 checksum invert slave read checksum clear slave byteenable 3 0 control irq Interrupt Slave irq Interface Checksum Accelerator December 2010 Altera Corporation SOPC Builder Us
74. the list of SDRAM related I O signals that must be connected to FPGA pins Example 9 1 shows these pins Example 9 1 1 0 Signals Connected to FPGA Pins output 11 0 zs addr from the sdram output 1 0 zs ba from the sdram output zs cas n from the sdram output zs cke from the sdram output zs cs n from the sdram inout 31 0 zs dq to and from the sdram output 3 0 zs dqm from the sdram output zs ras n from the sdram output zs we n from the sdram As shown in Figure 9 5 toplevel design bdf uses an instance of sdram p11 to phase shift the SDRAM clock by 63 degrees Degrees are relative to clock frequency If you change the clock speed you must change the phase shift You should parameterize the PLL with 3 5 ns because the compensation is for the round trip delays and clock to I O delays toplevel design bdf also uses a subdesign delay reset block to insert a delay on the reset nsignal for the SOPC Builder system This delay is necessary to allow the PLL output to stabilize before the SOPC Builder system begins operating December 2010 Altera Corporation SOPC Builder User Guide 9 14 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough DDR SDRAM Figure 9 6 shows pin assignments in the Quartus II Assignment Editor for some of the SDRAM pins The correct pin assignments depend on the target board Figure 9 6 Pin Assignments for SDRAM spRAM A 0 PIN AE4 3
75. this option on if the interfaces supports a packet protocol including the startofpacket endofpacket and empty signals You can use this signal to specify the number of empty symbols in the Include Empty Signal cycle that includes the endofpacket signal This signal is not necessary if the number of symbols per beat is 1 Type the width of the error signal Valid values are 0 31 bits Type o if you do not need to send error values Type the description for each of the error bits Separate the description fields by semicolons For a connection to be made the description of the Include Packet Support Error Signal Width bits Error Signal Description error bits in the source and sink must match Refer to Error Adapter on page 12 9 for the adaptations that can be made when the bits do not match SOPC Builder User Guide December 2010 Altera Corporation Chapter 12 Avalon Streaming Interconnect Components 12 9 Error Adapter Error Adapter The error adapter ensures that per bit error information provided by source interfaces is correctly connected to the sink interface s input error signal The adaptations are described in Table 12 9 Instantiating the Error Adapter in SOPC Builder You can use the Avalon ST configuration wizard in SOPC Builder to specify the hardware features Table 12 9 describes the options available on the Parameter Settings page of the configuration wizard Table 12 9 Avalon ST
76. to slaves using a technique called slave side arbitration Slave side arbitration moves the arbitration logic close to the slave such that the algorithm that determines which master gains access to a specific slave in the event that multiple masters attempt to access the same slave at the same time The multimaster architecture used by system interconnect fabric offers the following benefits m Eliminates having to create arbitration hardware manually m Allows multiple masters to transfer data simultaneously Unlike traditional host side arbitration architectures where each master must wait until it is granted access to the shared bus multiple Avalon MM masters can simultaneously perform transfers with independent slaves Arbitration logic stalls a master only when multiple masters attempt to access the same slave during the same cycle m Eliminates unnecessary master slave connections The connection between a master and a slave exists only if it is specified in SOPC Builder If a master never initiates transfers to a specific slave no connection is necessary and therefore SOPC Builder does not waste logic resources to connect the two ports m Provides configurable arbitration settings and arbitration for each slave is specified independently For example you can grant one master more arbitration shares than others allowing it to gain more access cycles to the slave The arbitration share settings are defined for each slave independentl
77. with respect to a slave One share represents permission to perform one transfer For example assume that two masters continuously attempt to perform back to back transfers to a slave Master 1 is assigned three shares and Master 2 is assigned four shares In this case the arbiter grants Master 1 access for three transfers then Master 2 for four transfers This cycle repeats indefinitely Figure 2 10 demonstrates this case showing each master s transfer request output wait request input which is driven by the arbiter logic and the current master with control of the slave Figure 2 10 Arbitration of Continuous Transfer Requests from Two Masters clk M1_transfer_request A I l l l l l I I l l l M1_waitrequest l l l i M2_transfer_request E 1 1 1 1 1 1 1 1 1 1 1 J M2_waitrequest J ED Current Master 4 Master Y Maser2 Y Master Y Master2 Y Master If a master stops requesting transfers before it exhausts its shares it forfeits all its remaining shares and the arbiter grants access to another requesting master Refer to Figure 2 11 After completing one transfer Master 2 stops requesting for one clock cycle As a result the arbiter grants access back to Master 1 which gets a replenished supply of share
78. zero Multiplexer Examples You can combine these adapters with streaming components to create datapaths whose input and output streams have different properties The following sections provide examples of datapaths constructed using SOPC Builder in which the output stream is higher performance than the input stream m The first example shows an output with double the throughput of each interface with a corresponding doubling of the clock frequency m Thesecond example doubles the data width m The third example boosts the frequency of a stream by 10 by multiplexing input data from two sources December 2010 Altera Corporation SOPC Builder User Guide 3 6 Chapter 3 System Interconnect Fabric for Streaming Interfaces Multiplexer Examples Example to Double Clock Frequency Figure 3 5 illustrates a datapath that uses the dual clock version of the on chip FIFO memory and Avalon ST channel multiplexer to merge the 100 MHz input from two streaming data sources into a single 200 MHz streaming output As Figure 3 5 illustrates this example increases throughput by increasing the frequency and combining inputs Figure 3 5 Datapath that Doubles the Clock Frequency On Chip FIFO Data Source Memory Dual Clk input mo MHz Im TIT On Chip FIFO Memory Dual Clk input ES MHz LEM TIE Data Source Example to Double Data Width and Maintain Frequency Figure 3 6 illustrates a datap
79. 1 19 Implementing Multiple Clock Domains in SOPC Builder ssseleslseeseeess 11 20 Avalon MM DDR Memory Half Rate Bridge 2 0 0c ene eens 11 20 Resource Usage and Performance sics sese pieren trine ne 11 21 Punctional Description esee eae eet Heer dd Cte Ed ee Eee E eee ees 11 22 Instantiating the Core in SOPC Builder ssssseeeeeeeee ee 11 23 Exatmple Syster 4a igi debe d AGI EC e Sed e eb e Oe n HE Sce due Edid 11 24 Deyice SUpport cest teness e ee or pee Eee nde equ Rer Rn E RR OR D ne Mle e tlle tel eoa 11 25 Hardware Simulation Considerations 6 ccc een eee eee 11 25 Software Programming Model 60 6 enn 11 25 Chapter 12 Avalon Streaming Interconnect Components Interconnect Component Usage sssssssss n 12 1 Address Mapping isis eoe eei pr PE ERES Uer etr e p teda Ete pud er pe aet get ts 122 Timing Adapter eret ERIEIE RR REPE Edo eO Re REL dee Pte deste dente tt een 12 2 SOPC Builder User Guide December 2010 Altera Corporation Contents Resource Usage and Performance ssscsssesipressrieiyise spese nee enn nents 12 4 Instantiating the Timing Adapter in SOPC Builder 006 c ccc nee eee 12 4 Data Format Adapter si 2 ct reri tiunu oe eh E ae eee PEE eee Ee ee ae Ew e a Ee 12 5 Resource Usage and Performance 6 066 c cee ene E 12 6 Instantiating the Data Format Adapter in SOPC Builder 0 12 6 Channel Adapter i costes rae Nie Pe
80. 160 Hold 40 Units ns Adding the SRAM Interface The SRAM device is 256K x 32 bit which requires 18 word address bits and 32 data bits The example design uses a custom memory interface created with the SOPC Builder component editor SOPC Builder System Contents Tab Figure 9 8 shows the SOPC Builder system after adding the Tristate bridge and memory interface components and configuring them appropriately on the System Contents tab Figure 9 8 represents the complete example design in SOPC Builder Figure 9 8 SOPC Builder System with SRAM and Flash Memory Target Clock Settings Device Fanily Stratix I GX Name Source Mir Add clk External isys clik pli c Use Connectio Module Name Description Base End instruction master Avalon Master sys_cik a data master Avalon Master IR 0 IM jteg_debug_module Avalon Slave 000000000 0x000007 F B jtag_uart JTAG UART avalon Jtag_slave Avalon Slave sys clk 0x00000800 0x00000807 v E onchip ram On Chip Memory RAM or ROM si Avalon Slave sys clk 0x00001000 0x00001 ff 2 B epes controller EPCS Serial Flash Controller epcs contro pot Avalon Slave sys clk 0x00002000 0x000027 f v E tristate bridge Avalon MM Tristate Bridge if Avalon Slave 0x00000000 0x00000000 tristate_master Avalon Tristate Master F B ext ram sram 255k x 32b avalon tristate slave 0 Avalon Tristate Stave 0x00100000 Ox001fffff F B ext flash Flash Memory CF
81. A fastclk 000800000 oxoo80001F T read buffer On Chip Memory RAM fastclk 0x00801 000 0x00801 FFF write_buffer On Chip Memory RAM fastclk 0x00802000 Ox00802FFF Avalon MM DDR Memory Half Rate Bridge SOPC Builder User Guide The Avalon Memory Mapped MM Half Rate Bridge core is a special purpose clock crossing bridge intended for CPUs that require low latency access to high speed memory The core works under the assumption that the memory clock is twice the frequency of the CPU clock with zero phase shift between the two It allows high speed memory to run at full rate while providing low latency interface for a CPU to December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 21 Avalon MM DDR Memory Half Rate Bridge access it by using lightweight logic that translates one single word request into a two word burst to a memory running at twice the clock frequency and half the width For systems with a 8 bit DDR interface using the Half Rate DDR Bridge in conjunction with a DDR SDRAM high performance memory controller creates a datapath that matches the throughput of the DDR memory to the CPU This half rate bridge provides the same functionality as the clock crossing bridge but with significantly lower latency 2 cycles instead of 12 The core s master interface is designed to be connected to a high speed DDR SDRAM controller and thus only supports bursting Because the slave interface is de
82. DH 1 1 Data in setup time DS 2 Data out High Z time Data out Low Z time Data out hold time The mapping of external memory timing to FPGA I O delays is shown in Table 5 1 This table also shows whether the minimum or maximum PCB routing delay should be used which must be added to the FPGA delay constraints Table 5 1 External Memory Timing Memory Timing FPGA Timing PCB Routing Max clock to out Max input delay Max Min clock to out Min input delay Min Min setup Max output delay Max Min hold Min output delay ve Min Note to Table 5 1 1 The constraint for minimum output delay is actually 0 Min hold December 2010 Altera Corporation SOPC Builder User Guide 5 6 Chapter 5 Using SOPC Builder with the Quartus Il Software TimeQuest Timing Analyzer You can use the set input delay and set output delay commands to set the I O constraints In the following examples a common PCB routing delay of 0 5ns 0 1 ns is used which adds a 0 4 ns or 0 6 ns delay to the paths Example 5 2 illustrates the use of these commands Example 5 2 set input delay and set output delay commands Set input delay clock sdram clk pin max expr 5 5 0 6 ports Set input delay clock sdram clk pin min expr 2 5 0 4 ports set output delay clock sdram clk pin max expr 2 0 0 6 ports Set output delay clock sdram clk pin min expr 1 0 4 lt ports gt
83. DULE String Main program which must be defined in the module s top level HDL file The name of the validation callback This VALIDATION CALLBACK String Main program callback is run in addition to the default validation VERSION String Main program The module s version such as 8 1 The INSTANTIATE IN SYSTEM MODULE TOP LEVEL HDL MODULE and GENERATION CALLBACK commands are used to select the type of generation used by the component You must set only one of these in the main program of your file get module property This command returns the value of a single module property get module property Sabi Main validation elaboration generation and editor Usage get module property propertyName Returns String boolean Or file Arguments propertyName One of the properties listed in Table 7 3 on page 7 15 Example set my name get module property NAME SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 17 Hardware Tcl Command Reference set_module_property This command allows you to set the values for module properties set_module_property Callback availability Main program Usage set_module property lt propertyName gt lt propertyValue gt Returns None propertyName One of the properties listed in Table 7 3 on page 7 15 Arguments propertyValue The new value of the property Example set_module property V
84. Design with On Chip Memory SOPC Builder User Guide This section demonstrates adding a 4 KByte on chip RAM to the example design This memory uses a single slave interface with a read latency of one cycle For demonstration purposes Figure 9 3 shows the result of generating the SOPC Builder system at this stage In a normal design flow you generate the system only after adding all system components Figure 9 3 SOPC Builder System with On Chip Memory sope memory system December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 9 EPCS Serial Configuration Device Because the on chip memory is contained entirely within the SOPC Builder system sopc_memory_system has no I O signals associated with onchip_ram Therefore you do not need to make any Quartus II project connections or assignments for the on chip RAM and there are no board level considerations EPCS Serial Configuration Device Many systems use an Altera EPCS serial configuration device to configure the FPGA Altera provides the EPCS device controller core which allows SOPC Builder systems to access the memory contents of the EPCS device This feature provides flexible design options m The FPGA design can reprogram its own configuration memory providing a mechanism for remote upgrades m The FPGA design can use leftover space in the EPCS as nonvolatile storage Physically the EPCS device is a serial flash me
85. ERSION 10 0 get_module_ports This command returns a list of the names of all the ports which are currently defined get_module_ports pee Main validation elaboration generation and editor Usage get module ports Returns String Arguments None Example get module ports get module assignments This command returns names of the module assignment variables get module assignments Mem Main validation elaboration and compose Usage get module assignments Returns String Arguments None Example get module assignments December 2010 Altera Corporation SOPC Builder User Guide 7 18 Chapter 7 Component Interface Tcl Reference get_module_assignment This command returns the value of the specified argument You can use the get module assignment and set module assignment and theget interface assignment and set interface assignment commands to transfer information about hardware components to embedded software tools and applications Hardware Tcl Command Reference get module assignment Sabi Main validation elaboration and compose Usage get module assignment lt name gt Returns String Arguments name The name whose value is being retrieved Example get module assignment embedded sw CMacro colorSpace set module assignment This command sets the value of the specified argument set module assignment
86. Error Adapter Parameters Parameter Description Input Interface Parameters Type the width of the error signal Valid values are 0 31 bits Type o if the error signal is not used Type the description for each of the error bits Separate the description fields by commas For a connection to be made the description of the Error Signal Width bits Error Signal Description error bits in the source and sink must match Refer to Error Adapter on page 12 9 for the adaptations that can be made when the bits do not match Output Interface Parameters Type the width of the error signal Valid values are 0 31 bits Type o if you do not need to send error values Type the description for each of the error bits Separate the description fields by semicolons For a connection to be made the description of the Error Signal Width bits Error Signal Description error bits in the source and sink must match Refer to Error Adapter on page 12 9 for the adaptations that can be made when the bits do not match Common to Input and Output Interfaces Support Backpressure with the ready signal Turn on this option to add the backpressure functionality to the interface Ready Latency When the ready signal is used the value for xeady latency indicates the number of cycles between when the ready signal is asserted and when valid data is driven Type the width of the channel signal A channel width of 4 allows up to
87. I st Avalon Tristate Slave sys clk 0x08000000 0x087tfttf Vv El pil PLL BH si Avalon Slave elk 0x00000820 0x0000003 is Trj Remove Edt A Move Up Y Move Down Address Map Filter December 2010 Altera Corporation SOPC Builder User Guide 9 22 SOPC Builder User Guide Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory After generating the system the top level SOPC Builder system file sopc memory system v contains the list of I O signals for SRAM and flash memory that must be connected to FPGA pins as shown in Example 9 3 Example 9 3 1 0 Signals for SRAM and Flash Memory output address to the ext flash 23 0 output address to the ext ram 19 0 output be n to the ext ram 3 0 output read n to the ext flash output read n to the ext ram output read n to the ext ram output select n to the ext flash output select n to the ext ram bidirectional tristate bridge data 31 0 output write n to the ext flash output write n to the ext ram The Avalon MM tristate bridge signals that can be shared are named after the instance of the tristate bridge component such as tri state bridge data 31 0 Connecting and Assigning Pins in the Quartus Il Project Figure 9 9 shows the result of generating the SOPC Builder system for the complete example design Figure 9 9 Top Level System with SRAM and Flash Memory address to the ext flash
88. In this example ports represent a list of I O ports for the relevant constraints as shown in Example 5 3 Example 5 3 ports Set output delay clock sdram clk pin max expr 2 0 1 2 get ports cas n ras n cs n we n addr You can use multiple set input delay and set output delay commands to set different delays for different I O Analyzing Tristate Bridges and Asynchronous Devices This section discusses the timing constraints associated with the Avalon tristate bridge and asynchronous external devices such as the CFI Flash and user tristate components These components typically have slower performance requirements compared with the FPGA and SOPC Builder generates logic within the interface to control timing across multiple clock cycles You define the tristate component s timing parameters by entering data for setup wait and hold times For the interface types previously discussed the timing is controlled by a state machine that is generated based on setup wait and hold settings you specify in the component editor Because data sheet values for the FPGA are used in calculating the timing the constraints simply ensure the data sheet timing is met Adding these constraints ensures that issues associated with data sheet misinterpretation and fitting problems that affect I O timing are captured The TimeQuest Timing Analyzer uses constraints that are based upon the timing of the external device St For fur
89. LUE SYSTEM INFO UNITS String String Main program Main program Allows you to assign information about the instantiating system to a parameter that you define SYSTEM INFO requires a keyword argument specifying the type of information requested lt info type gt lt info type may also take an argument The syntax of the Tcl command is Set parameter property my parameter SYSTEM INFO lt info type gt arg The following values for info type are predefined m CLOCK RATE m CLOCK DOMAIN m RESET DOMAIN m ADDRESS WIDTH m ADDRESS MAP m MAX SLAVE DATA WIDTH m INTERRUPTS USED m DEVICE FAMILY m DEVICE FEATURES Sets the units of the parameter The following values are possible picoseconds nanoseconds microseconds milliseconds seconds hertz kilohertz megahertz gigahertz address bits bytes kilobytes megabytes gigabytes bitspersecond kilobitspersecond megabitspersecond gigabitspersecond For example set parameter property frequency UNITS gigahertz VISIBLE Boolean tr ue Main program validation and elaboration callbacks Indicates whether or not to display the parameter in the parameterization GUI Note to Table 7 4 1 The AFFECTS ELABORATION property was called AFFECTS PORT WIDTHS before version 9 0 of the Quartus I software December 2010 Altera Corporation SOPC Builder User Guide 7 26 Chapter 7 Component Interface Tcl Reference Ha
90. M high performance memory controller in a series of embedded applications The performance improvement is 62 2 based on the Dhrystone benchmark and 87 7 when accessing memory bypassing the cache For memory systems that use the Half Rate bridge in conjunction with DDR2 3 High Performance Controller the data throughput is the same on the Half Rate Bridge master and slave interfaces The decrease in memory latency on the Half Rate Bridge slave interface results in higher performance for the processor Table 11 2 shows the resource usage for Stratix II and Stratix III devices in version 9 1 of the Quartus II software with a data width of 16 bits an address span of 24 bits Table 11 2 Resource Utilization Data for Stratix Il and Stratix IIl Devices Combinational Embedded Device Family ALUTs ALMs Logic Register Memory Stratix II 61 134 153 Stratix III 60 138 153 Table 11 3 lists the resource usage for a Cyclone III device Table 11 3 Resource Utilization Data for Cyclone Ill Devices Logic Cells Logic Register only LUT Register Embedded LC Register UT onlyLC LC Les Memory Functional Description SOPC Builder User Guide The Avalon MM DDR Memory Half Rate Bridge works under two constraints m Its memory side master has a clock frequency that is synchronous zero phase shift to and twice the frequency of the CPU side slave m Its memory side master is half as wide as its CPU side sl
91. Nd ioe Oe Laie Seated SCRI RD y ace qure 1 5 Defining and Generating the System Hardware 0 000 c ccc eee eens 1 5 Creating a Memory Map for Software Development 000 cece cece eee ees 1 6 Creating a Simulation Model and Test Bench 00 1 6 SOPC Builder Design FloW etes e eebetpeC SHE PUR EE da c Ra s CE Dead AVE tap epe aaa 1 6 Visualization of SOPC Builder Systems 6 6 eee eee ene 1 8 Operating System Support et eed ete beg Ep ERE HER A HERE st pa besito tee d esa pipa ded 1 8 Talkback Support serip eent et Ginna RUP UNS READ DPI epa scd rnc dd 1 8 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces High Level Description esie eet ER Fade Sed ae Ier ae ee Ped eee eed ee e es 2 1 Fundamentals of Implementation sssssssesssseleee enn 2 3 Functions of System Interconnect Fabric 2 ee een eee 2 3 Address Decoding i oed de as ek td tede een ein oeste deed eed tsm hae dod ae teen desee lung 2 3 Datapath Multiplexing sssssslsssseellee I Hh nn 2 4 Wait State lrisertoni estet eR EIER RESWERU RE RR dh de o PAREN A UR Meade ea 2 5 Pipelined Read Transfers oer tad netid pe EP en Mi UI ee tee rd rnc ae den eee 2 6 Dynamic Bus Sizing and Native Address Alignment ssseseeseeeeeeee esee 2 6 Dynamic Bus SIZING eo hee RECHERCHER EHE ER IUE ER I HET EN IH dH te dt de pee de oes 2 7 Native Address Alignment 6 6 6 ccc enne 2 8 Arbitration for Multima
92. P File x ebbe t Ree reti a and Me dn ES Rb eDCRDe E be aac 5 1 Quartus II Incremental Compilation 0 enn 5 1 limeOwuest Iuning Analyzer 1 reete ete aude teen dye do diee gl serie dene MIR b eda itg 5 2 Analyzing PLES4 sed acer enr eee Ped He EP bcd accen debout bed a Ea 5 2 Analyzing Slow Asynchronous I O Paths ssseseesssseeesee ee 5 3 Analyzing Single Data Rate SDRAM and SSRAM 0 6 e 5 4 Analyzing Tristate Bridges and Asynchronous Devices eeeeeeeeeeeeeeeeee 5 6 Analyzing DDR and DDR2 Memories ssssssseess hee 5 7 Chapter 6 Component Editor Component Hardware Structure 2 06 66 een 6 1 Starting the Component Editor 2 nnn 6 2 PADE FiOS Tab MCCC rm 6 2 Bottom Up Design 41 heed a Hd Le Ven ha Va needed ice qud desde 6 2 Top Down Design eee e eed ri aped tse qs Rei d a cede cl a ced Re Rae cede Wesley den nta 6 3 Signals Lab C GE 6 3 Naming Signals for Automatic Type and Interface Recognition 000 000000 6 4 Templates for Interfaces to External Logic lsssssssseeeeee eh 6 5 ntertaces Taby ET 6 6 HDL Parameters Tab eiie heat a EE teer obe e Ee MCI EE delen te leen tes 6 6 Library VIO aeneum tet hie a ite seu eat allo won ect Ragen tee lets ined Doge ona irr a tea eine aa ended age dae 6 7 Saving a Component oesr ees eed eR eee Coe a bep Ae ee I e Ca ee aes 6 7 Editing a Component 42 es eene eed vast eig e qat ime oie deed esit erp tech eden ede E 6
93. PC Builder User Guide December 2010 Altera Corporation Chapter 4 SOPC Builder Components 4 7 Installing Additional Components Options m project dir lt directory gt Optional Components can be found in certain locations relative to the project if any By default the current directory js used To exclude any project directory use m name value Optional This argument provides a pattern to filter the names of the components found To show all components use a or By default all components are shown The argument is not case sensitive m verbose true false Optional When true reports the progress of the command m xml lt true false gt Optional When true prints the output in XML format instead of a line and colon delimited format m help Shows help for the ip catalog command ip make ipx This command creates an index file for the directory specified It returns a 0 for successful completion and a non zero value for failure Usage ip make ipx source directory directory output lt files relative vars value thorough descent message before value message after value help Options m source directory lt directory gt Optional The directory to index The default directory is You can also provide a comma separated list of directories m output lt file gt Optional The name of the file to generate The default name is components
94. Path Multiplexing Logic Master 2 M2 M2 Address Write Data amp Control M1 wait Slave 2 Aiia Master Select S2 Read Data amp Control Arbitration Rules SOPC Builder User Guide This section describes the rules by which the arbiter grants access to masters when they contend Setting Arbitration Parameters in SOPC Builder You specify the arbitration shares for each master using the connection panel on the System Contents tab of SOPC Builder as shown in Figure 2 9 Figure 2 9 Arbitration Settings on the System Contents Tab Module Name Description Clock E cpu Nios Il Processor Alte clk instruction master Master port 7 deta master Master port 1 1 jtag debug module Slave port IT E sys elk timer Interval timer clk 1 ME ext_ram_bus Avalon Tri State Bridge clk ext_flash Flash Memory Commo ext_ram IDT71V 416 SRAM 118 epcs controller EPCS Serial Flash Cont clk he lan91c111 LAN91c111 Interface 1 Hijtag uart JTAG UART clk The arbitration settings are hidden by default To see them on the View menu click Show Arbitration December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 13 Arbitration for Multimaster Systems Fairness Based Shares Arbiter logic uses a fairness based arbitration scheme In a fairness based arbitration scheme each master pair has an integer value of transfer shares
95. SOPC Builder click Download Components 2 On the Intellectual Property Solutions web page type SOPC Builder ready in the box labeled Search for IP Development Kits and Reference Designs Functions of SOPC Builder This section describes the functions of SOPC Builder Defining and Generating the System Hardware SOPC Builder allows you to design the structure of a hardware system The GUI allows you to add components to a system configure the components and specify connectivity After you add and parameterize components SOPC Builder generates the system interconnect fabric and outputs HDL files to your project directory During system generation SOPC Builder creates the following items m An HDL file for the top level SOPC Builder system and for each component in the system The top level HDL file is named system name v for Verilog HDL designs and system name vhd for VHDL designs m Synopsis Design Constraints file sdc for timing analysis m A Block Symbol File bsf representation of the top level SOPC Builder system for use in Quartus II Block Diagram Files bdf m An example of an instance of the top level HDL file SOPC project name inst v or SOPC project name inst vhd which demonstrates how to instantiate the top level HDL file in your code m A data sheet called system name html that provides a system overview including the following information m Allexternal connections for the system
96. Sample rate 100 o input src ois s TEL 110 MHz odd utilization output e OUiput 110 MHz On Chip FIFO Data Source d 72 796 Memory Dual Clk sample rate input y ES 8 bits n sink 110 MHz 100 MHz TH 80 channel utilization December 2010 Altera Corporation SOPC Builder User Guide 3 8 Chapter 3 System Interconnect Fabric for Streaming Interfaces Multiplexer Examples SOPC Builder User Guide December 2010 Altera Corporation N DTE RYN l 4 SOPC Builder Components An SOPC Builder component is a hardware design block available within SOPC Builder that can be instantiated in an SOPC Builder system This chapter defines SOPC Builder components with emphasis on the structure of custom components A component includes the following The HDL description of the component s hardware A description of the interface to the component hardware such as the names and types of I O signals A description of the parameters that determine the operation of the component A GUI for parameterizing an instance of the component in SOPC Builder Scripts and other information SOPC Builder requires to generate the HDL files for the component and integrate the component instance into the SOPC Builder system Other component related information such as reference to software drivers necessary for development steps downstream of SOPC Builder This chapter discusses the design flow for new and
97. Sim simulation environment provides an easy to use starting point Sharing Components When you create a component component editor saves the _hw tcl file in the same directory as the top level HDL file Where appropriate files referenced by the hw tcl file are specified relative to the _hw tcl file itself so the files can easily be moved and copied To share a component include it in your IP library For more information about including components in an IP library refer to Finding Components in SOPC Builder in Chapter 4 SOPC Builder Components System Information Files sopcinfo Every time SOPC Builder generates a system a lt mysystem gt sopcinfo is also generated which contains the following information m SOPC Builder project including m Name and tool version m HDL language m Each module instantiated in the system including Nameand version m Where interface information was found on the disk such as signal names and types interface properties and clock domain mapping m Parameter names and values m Each connection including Component and interface connections m Base address Avalon MM interfaces IRO number interfaces m Memory map as seen by each master in the system La The sopcinfo file is a report file only and cannot be edited with SOPC Builder December 2010 Altera Corporation SOPC Builder User Guide 10 8 Chapter 10 SOPC Builder Component Development Walkthrough System Information Files so
98. U and DDR interfaces to run at different frequencies m Places system interconnect fabric for the arbitration logic and multiplexer for the DDR SDRAM controller in the slower clock domain m Reducesthe complexity of the interconnect logic in the faster domain allowing the system to achieve a higher fmax La Inserting the clock crossing bridge does increase read latency and may not be beneficial unless your system includes more devices that access the memory SOPC Builder User Guide December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges Structure of a Bridge 11 5 In the system illustrated in Figure 11 4 the message buffer RAM and message buffer mutex must respond quickly to the CPUs but each response includes only a small amount of data Placing an Avalon MM pipeline bridge between the CPUs and the message buffers results in the following benefits m Eliminates separate arbiter logic for the message buffer RAM and message buffer mutex which reduces logic utilization and propagation delay thus increasing the fmax m Reduces the overall size and complexity of the system interconnect fabric Figure 11 4 Example SOPC System with Bridges SOPC Builder View E cpu1 instruction master data master jtag debug module E cpu2 instruction master data master jtad debug module El cpu3 instruction master data master jtag debug module bridge s1 mi E ddr sdram s1 E
99. Y String Assigns the family name not the specific device part number of the currently selected device to the parameter you specify Set parameter property my parameter SYSTEM INFO DEVICE FAMILY DEVICE FEATURES INTERRUPTS USED String Creates a mask indicating which bits of the interrupt receiver vector are Integer Ol string Creates a list of key value pairs delineated by spaces indicating whether a particular device feature is available in the currently selected device family The format of the list is suitable for passing to the Tcl array set command This list is assigned to the parameter you specify The following features are supported M512 MEMORY M4K MEMORY M9K MEMORY M144K MEMORY MRAM MEMORY MLAB MEMORY ESB DSP and EMUL Set parameter property my parameter SYSTEM INFO DEVICE FEATURES connected to an interrupt sender This mask is assigned to the parameter you specify You can use this interrupt mask to optimize logic that handles interrupts Set parameter property my parameter SYSTEM INFO INTERRUPTS USED my interrupt receiver SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 27 Hardware Tcl Command Reference Table 7 5 SYSTEM_INFO Properties Part 2 of 2 Property Type Description Assigns an integer to the parameter you specify that is the data width of the MAX SLAVE DATA WIDTH widest slave connec
100. a Corporation Chapter 1 Introduction to SOPC Builder SOPC Builder Design Flow 2 Simulate at the unit level possibly incorporating Avalon BFMs to verify the system 3 Complete the SOPC Builder design by adding other components specifying interrupts clocks resets and addresses 9o m oy gr gm Test in hardware Figure 1 2 Complete Qsys Design Flow Perform system level simulation Generate the SOPC Builder system Constrain and compile the design Download the design to an Altera device Package Component Using Component Editor Simulation at Unit Level Possibly Using Avalon BFMs Simulation Give Yes Expected Results Debug Design Complete System Adding Components IRQs Addrs Generate SOPC BuilderFid Yes e Constraint Compile System in Quartus Il Generating sof y Y f Perform System Level Download sof to PCB Simulation with Altera FPGA Simulation Give Expected Results 9 Debug Design HW Testing Give Expected Results Modify Design or Constraints SOPC Builder System Complete December 2010 Altera Corporation SOPC Builder User Guide Chapter 1 Introduction to SOPC Builder Visualization of SOPC Builder Systems La In the alternative top down valid design flow you begin by
101. a Corporation SOPC Builder User Guide iv Contents Example Design with SDR SDRAM 0 eee eee eee eens 9 12 DDE SORA Mis 43 203 kccex d edie ied Ces eed d erg cexad kexad kccdacesau cda deena E eed dede 9 14 DDORZSDRAM 4 sses tects rehearse re ere ee Seg Sd eee SIS Valde ace Ree ee aad 9 14 Off Chip SRAM and Flash Memory lssssssssseeee nee ene eens 9 15 Component Level Design for SRAM and Flash Memory see 9 15 SOPC Builder System Level Design for SRAM and Flash Memory 0 000005 9 17 Simulation for SRAM and Flash Memory 6006 c ce eee eens 9 17 Quartus II Project Level Design for SRAM and Flash Memory 066 e cece eee eens 9 18 Board Level Design for SRAM and Flash Memory 6 000 eee 9 18 Example Design with SRAM and Flash Memory 0600 c cece cence eens 9 20 Chapter 10 SOPC Builder Component Development Walkthrough SOPC Builder Components and the Component Editor 0 0c eee 10 1 PROTEQUISILCS sc oroqaet cine e Ebro ede dues dede tee wi dos a EE shed dodi tee 10 1 Hardware and Software Requirements 6c ccc cent en ne es 10 2 Component Development FIOW 14 5235 dee ee eee EA doe e ee ee ees 10 2 Typical Design Steps 4 eee th bb e EPOR Heu tees e d et educa etd e dao a leq 10 2 Hardware Desig N Se odi i aende ose LEE ILI eot e sta pati eame 10 3 Design Example Checksum Hardware Accelerator sssseeeeeeeeeeeeeeeee 10 4
102. a slave that does not support bursts the burst management logic initiates 16 separate transfers to the slave The burst adapter inserts one idle cycle at the start of each burst System throughput is maximized when burst sizes are as large as possible In the case of a non linewrap burst master connected to a slave with the linewrapBursts property set to TRUE it is not always possible to issue the maximum sized burst to the slave In these cases the burst adapter is not capable of adapting the master and slave pairing An adapter is generated however if the master performs a burst transaction to the slave that crosses the slave burst boundary data corruption can occur To avoid a functional failure you should ensure the master posts bursts of length one until the master burst boundary has been reached The master burst boundary has an alignment of master data width x master maximum burst length Any burst transaction that begins on a master burst boundary is guaranteed to not cross the burst boundary of the slave port regardless of the slave port s maximum burst length Typically the only Avalon MM interfaces that support burst wrapping are burst capable SDRAM controllers For more information about the linewrapBursts property refer to the Avalon Memory Mapped Slave Interfaces chapter in the Avalon Interface Specifications December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 15
103. al hw tcl file contains the following information m Basic component information includes the component s name version and description a link to its documentation and pointers to HDL implementation files for synthesis and simulation m Parameter Declarations Parameters are values that the user of your component can set that affect how the component is implemented such as the size of a memory Properties of each parameter include the parameter s name whether or not it is visible and if visible the text to display when describing it When the SOPC Builder system is generated the parameters can be applied to the component as Verilog HDL parameters or VHDL generics m Interface Properties The interfaces of a component define how to connect it to the rest of the system and determine how other components in the system interact with it When you add interfaces to a component you declare which signals make up each interface You also define interface properties such as wait states for an Avalon Memory Mapped Avalon MM interface December 2010 Altera Corporation SOPC Builder User Guide 7 2 Chapter 7 Component Interface Tcl Reference Component Phases Depending on your component design your _hw tcl file may be one of the following two types B Static A static hw tcl file defines the top level HDL file and associated component files The HDL that describes a static component is created by the component author and is not chang
104. ame group if groupName is an empty string the group is top level m action an action defined by a callback procedure when you click the button labeled by act ionName Provides extra information required for display items The following examples Arguments illustrate how you use the additionalInfo argument for the various types m add display item groupName id icon path to image file m add display item groupName parameterName parameter additionalInfo not required m add display item groupName id text your text additionallnfo The your text argument is a block of text that is displayed in the GUI Some simple HTML formatting is allowed such as b and i if the text starts with html m add display item parentGroupName childGroupName group tab The tab is an optional parameter If present the group appears in separate tab in the GUI for the instance m add display item parentGroupName actionName action buttonClickCallbackProc add display item timing read latency parameter Examples l add_display_item sound speaker icon speaker jpg SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 31 Hardware Tcl Command Reference GET_DISPLAY_ITEMS This command returns a list of all items to be displayed as part of the parameterization GUI get_display_items Sii Main elaboration generation and editor Usage get display
105. ameterName value Returns None parameterName Specifies the parameter that is being set RUINIS value Specifies the value of parameterName Example Set parameter value BAUD RATE 19200 decode address map This is a utility function to convert an XML formatted address map into a list of Tcl lists Each inner list is in the correct format for conversion to an array The XML code describing each slave includes its name start address and end address 1 Figure 7 2 shows a portion of an SOPC Builder system with three Avalon MM slave devices Figure 7 2 SOPC Builder System with Three Avalon MM Slaves v e z E ext ssram Cypress CY7C1380C SSRAM 31 Avalon Memory Mapped Tristate Slave pll c0 El sys clk timer Interval Timer 81 Avalon Memory Mapped Slave pll c0 E sysid System ID Peripheral control slave Avalon Memory Mapped Slave pll c0 0x01000000 jOxOllfffff 0x02120800 0xO212081f 0x021208b8 0xO21208bf SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 29 Hardware Tcl Command Reference Example 7 13 shows the XML that describes the address map for the Avalon MM master that accesses these slaves The format of the XML string provided may differ from that described here it may have different white space between the elements and could include additional attributes or elements Using decode address map command to decode the XML representing an Avalon MM
106. amp Output Channel Signal Width bits Type the width of the channel signal A channel width of 4 allows up to 16 channels The maximum width of the channel signal is 8 bits Type o if you do not need to send channel numbers Max Channel Type the maximum number of channels that the interface supports Valid values are 0 255 Include Packet Support Turn this option on if the interface supports a packet protocol including the startofpacket endofpacket and empty signals Error Signal Width Bits Type the width of the error signal Valid values are 0 31 bits Type o if the error Signal is not used Error Signal Description Type the description for each of the error bits Separate the description fields by semicolons For a connection to be made the description of the error bits in the source and sink must match Refer to Error Adapter on page 12 9 for the adaptations that can be made when the bits do not match Data Bits Per Symbol Type the number of bits per symbol Channel Adapter The channel adapter provides adaptations between interfaces that have different support for the channel signal or for the maximum number of channels supported The adaptations are described in Table 12 7 Table 12 7 Channel Adapter Condition The source uses channels but the sink does not Description of Adapter Logic You are given a warning at generation time The adapter provides a simulat
107. art ee a ee aa ce Iara aa Pee bes sii 12 7 Resource Usage and Performance ssi sbre sips eroras oeiia Eia i py EEEE e E 12 8 Instantiating the Channel Adapter in SOPC Builder eessssseeeeeeeesse 12 8 Error Adapter esses e ph eukien EA Ei EEEE I Nu EN gv EE d 12 9 Instantiating the Error Adapter in SOPC Builder 0 occ ccc 12 9 Installation and Licensing 0 2 eee een nes 12 10 Hardware Simulation Considerations 6 ccc ene teens 12 10 Software Programming Model 6 eee ene 12 10 Additional Information Document Revision History sss ete eh eens REA e ace RH ee dor emer ed Info 1 How to Contact Altera 4s keeerteebRR ERE AES E DUCI ER RUP erg erp ade eren Info 1 Typographic Conventions ssi eeo ee e E I hne Info 1 December 2010 Altera Corporation SOPC Builder User Guide vi Contents SOPC Builder User Guide December 2010 Altera Corporation N DTE YN l 1 Introduction to SOPC Builder SOPC Builder is a powerful system development tool SOPC Builder enables you to define and generate a complete system on a programmable chip SOPC in much less time than using traditional manual integration methods SOPC Builder is included as part of the Quartus II software For a quick introduction on how to use SOPC Builder follow these general steps m Install the Quartus II software which includes SOPC Builder This is available at www altera com m Take advantage of the one hour online c
108. ates the add and remove buttons from tables Refer to Example 7 7 on page 7 8 and Figure 7 1 on page 7 8 for examples illustrating the use of this property DISPLAY NAME String Main program This is the GUI label that appears to the left of the parameter DISPLAY UNITS String Main program This is the GUI label that appears to the right of the parameter ENABLED Boolean tr ue Main program validation and elaboration callbacks When false the parameter is disabled meaning that it is displayed but greyed out indicating that it is not editable on the parameterization GUI HDL PARAMETER SOPC Builder User Guide Boolean false Main program When true the parameter must be passed to the HDL component description The default value is false December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference Table 7 4 Parameter Properties Part 3 of 3 7 25 Property Name NEW_INSTANCE_VALUE Type Default String Can Be Set Main program Description This property allows you to change the default value of a parameter without affecting older components that have assigned a default value to this parameter using the defaultValue argument The practical result is that older components will continue to use defaultValue for the parameter and newer components can use the value assigned by NEW INSTANCE VA
109. ath that uses the data format adapter and Avalon ST channel multiplexer to convert two 8 bit inputs running at 100 MHz to a single 16 bit output at 100 MHz Figure 3 6 Datapath to Double Data Width and Maintain Original Frequency Data Source input Ej 8 bits m Data Format 9100 MHz Adapter Ed 16 bits 0100 MHz Data Source input src 8 bits sink Data Format 100 MHz Adapter Example to Boost the Frequency Figure 3 7 illustrates a datapath that uses the dual clock version of the on chip FIFO memory to boost the frequency of input data from 100 MHz to 110 MHz by sampling two input streams at differential rates In this example the on chip FIFO memory has an input clock frequency of 100 MHz and an output clock frequency of 110 MHz The channel multiplexer runs at 110 MHz and samples one input stream 27 3 percent of the time and the second 72 7 percent of the time SOPC Builder User Guide December 2010 Altera Corporation Chapter 3 System Interconnect Fabric for Streaming Interfaces 3 7 Multiplexer Examples You do not need to know what the typical and maximum input channel utilizations are before attempting this For example if the first channel hits 50 utilization the output stream exceeds 100 utilization Figure 3 7 Datapath to Boost the Clock Frequency On Chip FIFO Data Source 30 27 3 channel utilization Memory Dual Clk
110. ation SOPC Builder User Guide 12 2 Chapter 12 Avalon Streaming Interconnect Components Address Mapping When the interconnect component adapts the data interface it has one Avalon ST sink interface and one Avalon ST source interface as shown in Figure 12 1 You configure the adapter components manually using SOPC Builder In contrast to the Avalon MM interface which allows you to create various topologies with a number of different master and slave components you always use the Avalon ST interconnect components to adapt point to point connections between streaming cores Figure 12 1 Example of an Avalon ST Interconnect Component in an SOPC Builder System streaming streaming i Avalon ST my Avalon ST Avalon ST ES I Bill component Mi adapter component pun T For details about the system interconnect fabric refer to Chapter 12 Avalon Streaming Interconnect Components For details about the Avalon ST interface protocol refer to the Avalon Interface Specifications Figure 12 2 illustrates a datapath that connects a Triple Speed Ethernet MegaCore function to a Scatter Gather DMA controller core using a timing adapter data format adapter and channel adapter so that the cores can interoperate Address Mapping Figure 12 2 Avalon ST Datapath Constructed Using Avalon Streaming Interconnect Components Triple Speed mm Timing Data Format gt Ethernet Lad Adapter Adapter
111. ator on page 10 4 This design example shows you how to develop a component with both Avalon Memory Mapped Avalon MM master and slaves Sharing Components on page 10 7 This section shows you how to use components in other systems or share them with other designers System Information Files sopcinfo on page 10 7 SOPC Builder Components and the Component Editor An SOPC Builder component is usually composed of the following four types of files HDL files define the component s functionality as hardware Hardware Component Description File hw tcl describes the SOPC Builder related characteristics such as interface behaviors This file is created by the component editor C language files define the component register map and driver software to allow programs to control the component Software Component Description File sw tcl file used by the software build tools to use and compile the component driver code The component editor guides you through the creation of your component You can then instantiate the component in an SOPC Builder system and make connections in the same manner as other SOPC Builder components You can also share your component with other designers For information about creating the _sw tcl file see the Developing Device Drivers for the Hardware Abstraction Layer chapter in the Nios II Software Developer s Handbook Prerequisites This chapter assumes that you are familiar with t
112. ave The bridge leverages these two constraints to provide lightweight low latency clock crossing logic between the CPU and the memory These constraints are in contrast with the Avalon MM Clock Crossing Bridge which makes no assumptions about the frequency phase relationship between the master and slave side clocks and provides higher latency logic that fully synchronizes all signals that pass between the two domains The Avalon MM DDR Memory Half Rate Bridge has an Avalon MM slave interface that accepts single word non bursting transactions When the slave interface receives a transaction from a connected CPU it issues a two word burst transaction on its master interface which is half as wide and twice as fast If the transaction is a read request the bridge s master interface waits for the slave s two word response concatenates the two words and presents them as a single readdata word on its slave interface to the CPU Every time the data width is halved the clock rate is doubled As a result the data throughput is matched between the CPU and the off chip memory device December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 23 Avalon MM DDR Memory Half Rate Bridge Figure 11 15 shows the latency in the Avalon MM Half Rate Bridge core The core adds two cycles of latency in the slave clock domain for read transactions The first cycle is introduced during the command phase of the transaction and the second
113. behaves like a synthesis file Example add file my component v SIMULATION SYNTHESIS add documentation link This command allows you to add multiple documentation links for a single component add documentation link Callback ode Main availability a Usage add documentation link filename lt docType gt title lt fileOrUrl gt Returns None One of the following document types USER GUIDE RELEASE NOTES WEBLINK docType ERRATA DATASHEET REFERENCE MANUAL WAVEFORM SCHEMATICS TUTORIAL OTHER Arguments title The title of the document for use on menus and buttons A path to the component documentation using a syntax that provides the entire fileOrUrl URL not a relative path For example http www mydomain com my_ memory_controller htm or file datasheet txt E add documentation link USER GUIDE Avalon Verification IP Suite User Guide xample http www altera com literature ug ug_avalon_verification_ip pdf December 2010 Altera Corporation SOPC Builder User Guide 7 20 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference get_file_properties This command returns the list of all properties that have been defined for a file get_file_properties anil Main validation elaboration generation and editor Usage get_file properties Returns List of strings 000000000000 Arguments None Example get file properties g
114. calparam Parameter parameter WIDTH 32 localparam DEPTH WIDTH 32 8 16 SOPC Builder only supports the VHDL port types std_logic and std logic vector 4 Develop the software driver which can occur in parallel with the hardware implementation Create the component s driver including a C header file that defines the hardware level register map for software For further details see the Nios II Software Developer s Handbook 5 Perform in system testing such as the following a Test register level accesses to the component in hardware or simulation using a microprocessor such as the Nios II processor b Performance benchmarking Hardware Design As with any logic design process the development of SOPC Builder component hardware begins after the specification phase Creating the HDL design is often an iterative process as you write and verify the HDL logic against the specification The architecture of a typical component consists of the following functional blocks m Tasklogic Implements the component s fundamental function The task logic is design dependent m Interface logic Provides a standard way of providing data to or getting data from the components and of controlling the functioning of the components T For further details refer to the Avalon Interface Specifications December 2010 Altera Corporation SOPC Builder User Guide 10 4 Chapter 10 SOPC Builder Component Develo
115. ces page of the Altera website December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 15 Off Chip SRAM and Flash Memory Off Chip SRAM and Flash Memory SOPC Builder systems can directly access many off chip RAM and ROM devices without a controller core to drive the off chip memory Avalon MM signals can describe the interfaces on many standard memories such as SRAM and flash memory I O signals on the SOPC Builder system can connect directly to the memory device While off chip memory usually has slower access time than on chip memory off chip memory provides the following benefits m Off chip memory cost per bit is less expensive than on chip memory resources m The size of off chip memory is bounded only by the 32 bit Avalon MM address space m Off chip ROM such as flash memory can be used for bulk storage of nonvolatile data m Multiple off chip RAM and ROM memories can share address and data pins to conserve FPGA I O resources at the expense of throughput Adding off chip memories to an SOPC Builder system also requires the Avalon MM Tristate Bridge component Component Level Design for SRAM and Flash Memory There are several ways to instantiate an interface to an off chip memory device m For common flash interface CFI flash memory devices add the Flash Memory Common Flash Interface component in SOPC Builder m For Altera development boards Altera provides SOPC B
116. ch type of memory as shown in Figure 9 1 Each section of the chapter builds on previous sections culminating in a complete system December 2010 Altera Corporation SOPC Builder User Guide 9 2 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Example Design By following the example design in this chapter you learn how to create a complete customized memory subsystem for your system or design The memory components in the example design are independent For a custom system you only need to instantiate the memories you need You can also create multiple instantiations of the same type of memory limited only by on chip memory resources or FPGA pins to interface with off chip memory devices Example Design Structure Figure 9 1 shows a block diagram of the example system Figure 9 1 Example Design Block Diagram JTAG Interface Altera FPGA JTAG Controller SOPC Builder System Nios Il Processor Data Instr M M JTAG Debug Module System Interconnect Fabric JTAG UART S S S S Avalon MM SDRAM 1K x 32 bit Stirs Tristate Bridge On chip evice a Serle RAM Controller M Core SDRAM EPCS Interface Interface S S 8M x 8 bit 256K x 32 bit 4M x 32 bit EARS el SRAM SAM Configuration Flash Memor
117. change the types of components that SOPC Builder allows you to connect The Insert Avalon ST Adapters command on the System menu attempts to correct these errors automatically if possible by inserting the appropriate adapter types December 2010 Altera Corporation SOPC Builder User Guide 3 4 Chapter 3 System Interconnect Fabric for Streaming Interfaces Adapters T For complete information about these adapters refer to Chapter 12 Avalon Streaming Interconnect Components The following sections provide an overview of these adapters Data Format Adapter The data format adapter allows you to connect interfaces that have different values for the parameters defining the data signal One of the most common uses of this adapter is to convert data streams of different widths Figure 3 4 shows an adapter that allows a connection between a 128 bit input data stream and three 32 bit output data streams Figure 3 4 Avalon Streaming Interconnect Fabric with Data Format Adapter Data 128 bits 4 Format S2bits y 32 bit TX Adapter Interface Data 128 bit RX 32 bits y 32 bit TX Interface k bu Interf dapter grace Data 128 bits EON 32 bits gt 32 bit TX Adapter Interface Timing Adapter The timing adapter allows you to connect component interfaces that require a different number of cycles before driving or receiving data This adapt
118. classic custom defined SOPC Builder components in the following sections Component Providers Component Hardware Structure on page 4 2 Exported Connection Points Conduit Interfaces on page 4 3 SOPC Builder Component Search Path on page 4 4 Component Structure on page 4 8 Classic Components in SOPC Builder on page 4 10 Component Providers SOPC Builder components can be obtained from many providers including the following The components automatically installed with the Quartus II software Third party IP developers can provide IP blocks as SOPC Builder ready components including software drivers and documentation A list of third party components can be found in SOPC Builder by clicking IP MegaStore on the Tools menu Altera development kits such as the Nios II Development Kit can provide SOPC Builder components as features You can use the SOPC Builder component editor to convert your own HDL files into custom components For more information about the hw tcl file refer to Chapter 6 Component Editor December 2010 Altera Corporation SOPC Builder User Guide 4 2 Chapter 4 SOPC Builder Components Component Hardware Structure Component Hardware Structure There are the following types of components in an SOPC Builder system based on where the associated component logic resides m Components that include their associated logic inside the SOPC Builder system m Components that
119. clock domain 8 The master handshake FSM completes the transaction by releasing the master from the wait condition Transfers proceed as normal on the slave and the master side without a special protocol to handle crossing clock domains From the perspective of a slave there is nothing different about a transfer initiated by a master in a different clock domain From the perspective of a master a transfer across clock domains simply requires extra clock cycles Similar to other transfer delay cases for example arbitration delay or wait states on the slave side the system interconnect fabric simply forces the master to wait until the transfer terminates As a result pipeline master ports do not benefit from pipelining when performing transfers to a different clock domain Location of Clock Domain Adapter You can use the clock crossing bridge described in the following paragraphs for higher throughput clock crossing at the expense of memory resources SOPC Builder automatically determines where to insert the CDC logic based on the system contents and the connections between components SOPC Builder places CDC logic to maintain the highest transfer rate for all components SOPC Builder evaluates the need for CDC logic for each master and slave pair independently and generates CDC logic wherever necessary Duration of Transfers Crossing Clock Domains CDC logic extends the duration of master transfers across clock domain boundaries I
120. compose callback may not be necessary for very simple composed components For more information about defining your own generation or compose callback procedure refer to the Generation Callback and Compose Callback sections in Chapter 7 Component Interface Tcl Reference Components Outside the SOPC Builder System Ls For components that interface to external logic or off chip devices with Avalon compatible signals outside the SOPC Builder system the component files describe only the interface to the external logic During system generation SOPC Builder exports an interface for the component in the top level SOPC Builder system You must manually connect the signals at the top level of SOPC Builder to pins or logic defined outside the system that already has Avalon compatible signals This type of component is deprecated and will not be available in future versions of the Quartus II software Exported Connection Points Conduit Interfaces Conduit interfaces are brought to the top level of the system as additional ports Exported signals are usually either application specific signals or the Avalon interface signals Application specific signals are exported to the top level of the system by the conduit interface s defined in the _hw tcl file These are I O signals in a component s HDL logic that are not part of any Avalon interfaces and connect to an external device for example DDR SDRAM memory or logic defined outside of the SOPC B
121. dapter in SOPC Builder You can use the Avalon ST configuration wizard in SOPC Builder to specify the hardware features Table 12 8 describes the options available on the Parameter Settings page of the configuration wizard Table 12 8 Avalon ST Channel Adapter Parameters Parameter Description Input Interface Parameters Type the width of the channel signal A channel width of 4 allows up to Channel Signal Width bits 16 channels The maximum width of the channel signal is eight bits Set to 0 if channels are not used Max Channel Type the maximum number of channels that the interface supports Valid values are 0 255 Output Interface Parameters Type the width of the channel signal A channel width of 4 allows up to Channel Signal Width hits 16 channels The maximum width of the channel signal is eight bits Set to 0 if channels are not used Max Channel Type the maximum number of channels that the interface supports Valid values are 0 255 Common to Input and Output Interfaces Support Backpressure with the ready signal Turn on this option to add the backpressure functionality to the interface Ready Latency When the ready signal is used the value for ready_latency indicates the number of cycles between when the ready signal is asserted and when valid data is driven Data Bits Per Symbol Type the number of bits per symbol Data Symbols Per Beat Type the number of symbols per active transfer Turn
122. data sink in the FIFO m The data source in the FIFO transfers data to the Tx Interface data sink December 2010 Altera Corporation Chapter 3 System Interconnect Fabric for Streaming Interfaces 3 3 Adapters In Figure 3 3 the Avalon MM interface allows a processor to access the data source FIFO or data sink to provide system control Figure 3 3 Use of the Avalon Memory Mapped and Streaming Interfaces Control Plane Avalon Memory Mapped Inteface Processor Control Control Control Slave Slave Slave Data Source FIFO Data Sink Rx Interface Tx Interface Tm ready Tum ready Data valid Data Data Data Source Sink Source Sink data Data Plane Avalon Streaming Interface Adapters Adapters are configurable SOPC Builder components that are part of the streaming interconnect fabric They are used to connect source and sink interfaces that are not exactly the same without affecting the semantics of the data SOPC Builder includes the following four adapters m Data Format Adapter m Timing Adapter m Channel Adapter m Error Adapter You can add Avalon ST adapters between two components with mismatched interfaces The adapter allows you to connect a data source to a data sink of differing byte sizes If you connect mismatched Avalon ST sources and sinks in SOPC Builder without inserting adapters SOPC Builder generates error messages Inserting adapters into the system does not
123. dd parameter PARITY string ODD Set parameter property PARITY ALLOWED RANGES EVEN ODD The validation callback proc my validation callback Get the current value of parameters we care about set br get parameter value BAUD RATE set p get parameter value PARITY Display an error for invalid combinations if br 38400 amp amp p ODD Send message warning Odd parity at 38400 bps is not supported Set the value of our DERIVED parameter set bp expr br 16 set parameter value BAUDRATE PRESCALE bp Elaboration Callback You can use an elaboration callback to change interface properties or add new interfaces as a function of parameter values You define an elaboration callback by setting the ELABORATION CALLBACK module property to the name of the elaboration callback function as shown in Example 7 9 You can enable and disable interfaces from the elaboration callback if they are only needed for some parameterizations of the component Example 7 9 shows how an Avalon MM slave interface can be included in an instance of the component based on the USE STATUS INTERFACE parameter All of the functionality available in the validation callback can also be used in the elaboration callback separate callbacks for validation and elaboration are not required December 2010 Altera Corporation SOPC Builder User Guide 7 10 Chapter 7 Component Interface Tcl Reference Overriding Default Behaviors a The elaboration ca
124. depth is described by equation given in Example 11 1 Example 11 1 Minimum Slave To Master FIFO Depth master to slave FIFO depth max burst length max slave latency pending reads December 2010 Altera Corporation SOPC Builder User Guide 11 16 Chapter 11 Avalon Memory Mapped Bridges Clock Crossing Bridge Example System with Avalon MM Clock Crossing Bridges Figure 11 11 uses Avalon MM clocking crossing bridges to separate slave components into two groups The low performance slave components are placed behind a single bridge and clocked at a low speed The high performance components are placed behind a second bridge and clocked at a higher speed By inserting clock crossing bridges in the system you optimize the interconnect fabric and allow the Quartus II fitter to expend effort optimizing paths that require minimal propagation delay Figure 11 11 One Avalon MM Master with Two Groups of Avalon MM Slaves CPU Avalon MM Avalon MM Clock Crossing Clock Crossing Bridge Bridge iu T s Ls s H Ls AR JTAG Debug UART System ID Seven Segment LCD PIO Display Bridge Module isplay M s O l Flash Memory 4 S S DDR Avalon SDRAM Tristate Bridge M M Avalon MM Master
125. designing the SOPC Builder system and then define and instantiate custom SOPC Buildder component This approach clarifies the system requirements earlier in the design process Designs targeting HardCopy devices are require specific design constraints Consequently if you are targeting a HardCopy series device you must verify you design for the HardCopy companion device Follow these guidelines to verify your design for both devices 1 In the Quartus II Device dialog box select both the FPGA and the appropriate HardCopy companion device 2 In Step 8 of the design flow shown in Figure 1 2 compile for both the FPGA and HardCopy device 3 After Step 10 of the design flow shown in Figure 1 2 if FPGA passes all functional simulation and hardware verification tests generate the HardCopy handoff archive and send this archive to the HardCopy Design Center for the backend flow and tapeout Visualization of SOPC Builder Systems You can use the Filters dialog box to customize the display of your system in the connections panel You can filter the display of your system by interface type instance name interface type or using custom tags For example you can use filtering to view only instances that include an Avalon MM interface or instances that are connected to a particular Nios II processor For more information refer to Quartus II online Help Operating System Support SOPC Builder supports all of the operating systems that the Q
126. e Set Main program Description Set AFFECTS ELABORATION to false for parameters that do not affect the external interface of the module An example of a parameter that does not affect the external interface is isNonVolatileStorage An example of a parameter that does affect the external interface is width When the value of a parameter changes if that parameter has set AFFECTS ELABORATION false the elaboration phase calling the callback or hardware analysis is not repeated improving performance Because the default value Of AFFECTS ELABORATION is true the provided HDL file is normally re analyzed to determine the new port widths and configuration every time a parameter changes AFFECTS_GENERATION Boolean refer to DESCRIPTION Main program The default value of AFFECTS GENERATION is false if you provide a top level HDL module it is true if you provide a custom generation callback Set AFFECTS GENERATION to false if the value of a parameter does not change the results of system generation December 2010 Altera Corporation SOPC Builder User Guide 7 24 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference Table 7 4 Parameter Properties Part 2 of 3 Property Name Pi al Can Be Set Description Indicates the range or ranges that the parameter value can have For integers The ALLOWED RANGES property is a list of ranges that the parameter can take on where each range i
127. e and stops SOPC Builder does not conduct the search just described December 2010 Altera Corporation SOPC Builder User Guide 4 6 Chapter 4 SOPC Builder Components Installing Additional Components Reference Components in an ipx File A second approach is to specify your IP directory in a user_components ipx file under lt install_dir gt ip path Figure 4 3 illustrates this approach Figure 4 3 Specifying A User ipx directory sae ey dir gt quartus Ga ip altera library ipx lt components gt user_components user components ipx The user components ipx file includes a single line of code redirecting SOPC Builder to the location of the user library Example 4 1 shows the code for this redirection Example 4 1 Redirect to User Library library path path c user install dir user ip gt library a For both of these approaches if you install a new version of the Quartus II software you must also update the installation to include your libraries You can verify that components are available and also decrease the time it takes to launch SOPC Builder by using two utilities ip catalog and ip make ipx The following sections describe these utilities ip catalog Shows the a catalog of components in either plain text or XML format Usage ip catalog project dir directory name value verbose lt true false gt xml lt true false gt help SO
128. e design contains a 4 bit PIO filter pio includes the following I O pins E out port from the pio 0 E out port from the pio 1 E out port from the pio 2 WB out port from the pio 3 Analyzing Single Data Rate SDRAM and SSRAM Single data SDRAM interfaces in SOPC Builder typically use the type of circuit shown in Figure 5 3 You can use a PLL to fine tune the phase shift to the external memory to meet I O timing requirements Figure 5 3 Typical Single Data Rate SDRAM Circuit zn FPGA Je Exernal Clock SDRAM Controller To constrain this interface you must create a clock that is recognized by the external SDRAM then you must set the I O timing relative to that clock Example 5 1 shows how to constrain a PLL output clock and set a Tcl variable for that clock Example 5 1 Constraining PLL Output Clock create clock period 20 000 name ext clk get ports clk derive pll clocks set sdram clkWMny pll inst altpll component auto generated pl11 clk 0 SOPC Builder User Guide You can then use the create generated clock command to define a clock as recognized by the external memory This generated clock automatically adds delays associated with routing to the clock output pin and the delay of the pin itself You must also account for some board delay due to the PCB trace between the FPGA and SDRAM by using the offset option The following command shows
129. e functions in a specific SOPC Builder system depends on the design of the components in the system and the settings made in SOPC Builder The remaining sections of this chapter describe how SOPC Builder implements each function Address Decoding Address decoding logic in the system interconnect fabric forwards appropriate addresses to each slave Address decoding logic simplifies component design in the following ways December 2010 Altera Corporation SOPC Builder User Guide 2 4 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Datapath Multiplexing m The system interconnect fabric selects a slave whenever it is being addressed by a master Slave components do not need to decode the address to determine when they are selected m Slave addresses are properly aligned to the slave interface m Changing the system memory map does not involve manually editing HDL Figure 2 2 shows a block diagram of the address decoding logic for one master and two slaves Separate address decoding logic is generated for every master in a system As Figure 2 2 shows the address decoding logic handles the difference between the master address width M and the individual slave address widths lt S gt and lt T gt It also maps only the necessary master address bits to access words in each slave s address space Figure 2 2 Block Diagram of Address Decoding Logic read write y SI address M 0
130. e multiple transfers so that even though the latency increases the throughput does not decrease Because a clock crossing adapter is generated for every master and slave pair you should use a clock crossing bridge if your design contains multiple master and slave pairs operating in different clock domains Alternatively if your design uses a large amount of on chip memory you may need to use a clock domain adapter because the clock crossing bridge uses on chip memory resources for buffering Functional Description Figure 11 10 shows a block diagram of the Avalon MM clock crossing bridge component The following sections describe the component s hardware functionality Figure 11 10 Avalon MM Clock Crossing Bridge Block Diagram Avalon MM Clock Crossing Bridge Master to Slave A Master to Slave Master to Slave P in out 9 Signals FIFO Signals gt 4 Slave Master VF VF Corners 1 T 4 oiii rupe es in eg asa ter Connects to Avalon MM 9 9 Avalon MM Master o gt lt lt Slave Interface Interface Wait waitrequest e Request waitrequest Logic slave_clk master_clk December 2010 Altera Corporation SOPC Builder User Guide 11 14 SOPC Builder User Guide Chapter 11 Avalon Memory Mapped Bridges Clock Crossing Bridge Interfaces The bridge interface comprises an Avalon MM slave and an Avalon MM master The data width of the
131. e state machine that reconciles the difference between master and slave data widths The behavior is different depending on whether the master data width is wider or narrower than the slave Wider Master In the case of a wider master the dynamic bus sizing logic accepts a single wide transfer on the master side and then performs multiple narrow transfers on the slave side For a data width ratio of lt N gt 1 the dynamic bus sizing logic generates up to N slave transfers for each master transfer The master waits while multiple slave side transfers complete the master transfer ends when all slave side transfers end Dynamic bus sizing logic uses the master side byte enable signals to generate appropriate slave transfers The dynamic bus sizing logic performs as many slave side transfers as necessary to write or read the specified byte lanes Narrower Master In the case of a narrower master one transfer on the master side generates one transfer on the slave side In this case multiple master word addresses map to a single offset in the slave memory space The dynamic bus sizing logic maps each master address to a subset of byte lanes in the appropriate slave offset All bytes of the slave memory are accessible in the master address space December 2010 Altera Corporation SOPC Builder User Guide Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Dynamic Bus Sizing and Native Address Alignment Table 2 2 demonstrat
132. ecember 2010 Altera Corporation SOPC Builder User Guide 11 18 Chapter 11 Avalon Memory Mapped Bridges Clock Domain Crossing Logic The clock domain adapters in the system interconnect fabric provide the following benefits that simplify system design efforts m Allow component interfaces to operate at different clock frequencies m Eliminate the need to design CDC hardware m Allow each Avalon MM port to operate in only one clock domain which reduces design complexity of components m Enable masters to access any slave without communication with the slave clock domain m Allow you to focus performance optimization efforts only on components that require fast clock speed Description of Clock Domain Adapter The clock domain adapter consists of two finite state machines FSM one in each clock domain that use a simple hand shaking protocol to propagate transfer control signals read request write request and the master waitrequest signals across the clock boundary Figure 11 12 shows a block diagram of the clock domain adapter between one master and one slave Figure 11 12 Block Diagram of Clock Crossing Adapter Receiver Port Receiver Clock Domain Sender Clock Domain CDC Logic l l l control control transer Synchro quest nizer waitrequest Bee Soden waitrequest 3 Handshake Handshake a FSM I FSM Synchro acknowledge
133. ed by users of the component HDL parameters are available when instantiating the component m Generated A generated _hw tcl file provides a user defined program to generate the component s HDL The HDL can be different for different parameterizations of the component Component Phases The following section describes the distinct phases in the development of an SOPC Builder component m Main Program SOPC Builder first discovers a component and adds it to the component library The _hw tcl file is executed and the Tcl statements provide non instance specific information to SOPC Builder During this phase some component interfaces may be incompletely described and ports may have a width of 0 or 1 to indicate that they are variable m Validation Validation allows the component to generate error warning or informational messages Validation occurs when an instance of a component is created when its parameters are changed or when some other property of the system is changed m Elaboration Elaboration occurs as SOPC Builder queries a component for its interface information Elaboration typically occurs immediately after validation and before generation Interfaces defined in the main program can be enabled or disabled during elaboration Depending on the validation callback code elaboration and validation may alternate a few times Elaboration and validation always occur before generation Once elaboration is complete the component
134. ency ssssseeeeeeeeeeeee 3 6 Example to Boost the Frequency sss e enn 3 6 December 2010 Altera Corporation SOPC Builder User Guide ii Contents Chapter 4 SOPC Builder Components Component Providers cede eee eee fa ene e aan rite aede antedios aeta tet eee duda 4 1 Component Hardware Structure o sssssisssressisisidensdi eiai e een 4 2 Component Instances Inside the SOPC Builder System 0 6 6 e ee 4 2 Components Outside the SOPC Builder System 6 c cece eee eee 4 3 Exported Connection Points Conduit Interfaces 0 6 eee nes 4 3 SOPC Builder Component Search Path 2 6 nents 4 4 Installing Additional Components 666 6 nnn 4 4 Copy to the IP Root Directoty i v eese bee Poh hee Re RYE EA I LG Mea e pea ede 4 5 Reference Components inan ipx File s siss tiranin ia EE aa E EE eee 4 6 Understanding IPX File Syntax esiscese eere er emet emt ee ge ke E Ae ee 4 7 Upgrading from Earlier Versions 000 cis cece ccc eee eens 4 8 Comporient Structure iue es Ra en ee Ve ae P vat Ve Sa a ace wa soe Va Daci Vian Va ae o 4 8 Component Description File hw tcl 0 0 06 e 4 9 Component File Organization cosi eres ciesesigadiiyecigciateeciigesd bes abe bie is 4 9 Component Versioning ct seis sk eC spate a CERA ERRAT Re BEIC RE eRe Ee ed we Ae Res 4 9 Classic Components in SOPC Builder 0 0 0 eee ene 4 10 Chapter 5 Using SOPC Builder with the Quartus Il Software Quartus I I
135. er Guide 10 6 Chapter 10 SOPC Builder Component Development Walkthrough Design Example Checksum Hardware Accelerator Software Design If you want a microprocessor to control your component you must provide software files that define the software view of the component At a minimum you must define the register map for each Avalon MM slave that is accessible to a processor In the example checksum project you can view an example of a software driver in the directory lt projectdir gt ip checksum_accelerator which is the top level folder of the hardware and software for the custom checksum block Software drivers abstract hardware details of the component so that software can access the component at a high level The driver functions provide the software an API to access the hardware The software requirements vary according to the needs of the component The most common types of routines initialize the hardware read data and write data When developing software drivers you should review the software files provided for other ready made components The IP installer provides many components you can use as reference You can also view the lt Nios II EDS install path gt components directory for examples For details about writing drivers for the Nios II hardware abstraction layer HAL refer to the Developing Device Drivers for the Hardware Abstraction Layer chapter of the Nios II Software Developer s Handbook Verifying the Comp
136. er inserts a FIFO between the source and sink to buffer data or pipeline stages to delay the back pressure signals The timing adapter can also be used to connect interfaces that support the ready signal and those that do not SOPC Builder User Guide December 2010 Altera Corporation Chapter 3 System Interconnect Fabric for Streaming Interfaces 3 5 Multiplexer Examples Channel Adapter The channel adapter provides adaptations between interfaces that have different support for the channel signal or channel related parameters For example if the source channel is narrower than the sink channel you can use this adapter to connect them The high order bits of the sink channel are connected to zero You can also use this adapter to connect a source with a wider channel to a sink with a narrower channel If the source provides data for a channel that the sink cannot receive the data is not transferred Error Adapter The error adapter ensures that per bit error information provided by the source interface is correctly connected to the sink interface s input error signal Matching error conditions handled by the source and sink are connected If the source has an error condition that is not supported by the sink the signal is left unconnected the adapter provides a simulation error message and an error indication if this error is ever asserted If the sink has an error condition that is not supported by the source the sink s input is tied to
137. er is derived from its range description Explains the use of the parameter Example add_parameter seed integer 17 The seed to use for data generation get_parameters This command returns the names of all parameters that have been previously defined by add_parameter as a space separated list get_parameters Sibi Main validation elaboration generation and editor Usage get parameters Returns List of strings Arguments None Example set parameter summary get parameters SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference get_parameter_properties This command returns a list of all the available parameter properties as a list of strings The get_parameter_property and set_parameter_property commands are used to get and set the values of these properties respectively 1 23 get parameter properties eid Main validation elaboration generation and editor Usage get parameter properties Returns List of strings Arguments None Example set property summary get parameter properties Table 7 4 Parameter Properties Part 1 of 3 Table 7 4 describes the properties available to describe the behaviors of each of the parameters you can specify their use and when they can be set Property Name AFFECTS ELABORATION 1 Type Default Boolean refer to description Can B
138. erformance Input Output RETE Gx Cyclone Il Stratix Approximate LEs Ready Ready SEE eene M count Mem Bits M Cells Mi Gels Mem Bits 1 2 500 2 0 420 2 422 1 0 1 3 500 2 0 420 3 422 2 0 1 4 500 4 0 420 4 422 3 0 1 0 500 21 80 420 183 422 20 80 2 1 456 21 80 401 188 317 21 80 3 1 456 21 80 401 188 317 21 80 4 1 456 21 80 401 188 317 21 80 Instantiating the Timing Adapter in SOPC Builder You can use the Avalon ST configuration wizard in SOPC Builder to specify the hardware features Table 12 3 describes the options available on the Parameter Settings page of the configuration wizard Table 12 3 Avalon ST Timing Adapter Parameters Input Interface Parameters Parameter Description Support Backpressure with the ready signal Turn on this option to add the backpressure functionality to the interface Ready Latency When the ready signal is used the value for xeady latency indicates the number of cycles between when the ready signal is asserted and when valid data is driven Include valid signal Turn this option on if the interface includes the valid signal Turning this option off means that data being received is always valid Output Interface Parameters Support Backpressure with the ready signal Turn on this option to add the backpressure functionality to the interface Ready Latency When the ready signal is used the value for ready latency indicates
139. error signal Valid values are 0 31 bits Type o if the error signal is not used Type the description for each of the error bits Separate the description fields by commas For a connection to be made the description of the error bits in the source and sink must match Refer to Error Adapter on page 12 9 for the adaptations that can be made when the bits do not match Data Format Adapter The data format adapter handles interfaces that have different definitions for the data signal One of the more common adaptations that this component performs is data width adaptation such as converting a data interface that drives two 8 bit symbols per beat to an interface that drives four 8 bit symbols per beat The available data format adaptations are listed in Table 12 4 Table 12 4 Data Format Adapter Condition are different The source and sink s bits per symbol Description of Adapter Logic The connection cannot be made The source and sink have a different number of symbols per beat The adapter converts from the source s width to the sink s width If the adaptation is from a wider to a narrower interface a beat of data at the input corresponds to multiple beats of data at the output If the input error signal is asserted for a single beat it is asserted on output for multiple beats If the adaptation is from a narrow to a wider interface multiple input beats are required to fill a single output
140. es For more details about archiving Quartus II projects refer to the Managing Quartus II Projects chapter in volume 2 of the Quartus II Handbook This section describes the files required to archive an SOPC Builder system and its associated Nios II software projects if any This is the minimum set of files needed to completely recompile an archived system both the SRAM Object File sof and the executable software elf Ifyou have Nios II software projects archive them together with the SOPC Builder system on which they are based For more details about archiving Nios II designs refer to the Using the Nios II Software Build Tools chapter of the Nios II Software Developer s Handbook The files listed in Table 8 1 are located in the Quartus II project directory Table 8 1 Files Required for an SOPC Builder System File Description File Name Write Permission Required SOPC Builder design file sopc sopc builder system sopc Yes SOPC Builder classic system description for generation a peripheral template file ptf 1 sopc builder system ptt Yes SOPC Builder report file an SOPC information file sopcinto sopc builder system sopcinfo Yes for example top_level_schematic bdf All non generated HDL source files 2 customlogic v No Quartus II project file qpf lt project_name gt qpf No Quartus II settings file qsf lt project_name gt qsf Yes Notes t
141. es the case of a 32 bit master accessing a 64 bit slave with dynamic bus sizing In the table offset refers to the offset into the slave memory space Table 2 2 32 Bit Master View of 64 Bit Slave with Dynamic Bus Sizing 32 bit Address Data 0x00000000 word 0 OFFSET 0 31 9 0x00000004 word 1 OFFSET 0 3 3 0x00000008 word 2 OFFSET 1 31 0 0x0000000C word 3 OFFSET 1 63 39 In the case of a read transfer the dynamic bus sizing logic multiplexes the appropriate byte lanes of the slave data to the narrow master In the case of a write transfer the dynamic bus sizing logic uses slave side byte enable signals to write only to the appropriate byte lanes Altera recommends that you select dynamic bus sizing whenever possible Dynamic bus sizing offers more flexibility when the master and slave components in your system have different widths Native Address Alignment Table 2 3 demonstrates native address alignment and dynamic bus sizing for a 32 bit master connected to a 16 bit slave a 2 1 ratio In this example the slave is mapped to base address BASE in the master s address space In Table 2 3 OFFSET refers to the offset into the 16 bit slave address space Table 2 3 32 Bit Master View of 16 Bit Slave Data 32 bit Master Address Data with Native Alignment Data with Dynamic Bus Sizing BASE 0x0 word 0 0x0000 0FFSET 0 OFFSET 1 OFFSET 0 BASE 0x4 word 1 0x0000 0FFSET 1
142. et file property This command returns the value of a single file property The file name passed as an argument may be a partial as long as it is unique For example if the full file name is components my file v my file v is sufficient get file property Callback Main validation elaboration generation and editor availability Usage get file property filename propertyName Returns Boolean filename The file name whose properties are being retrieved Arguments UNES 7 propertyName The file name property whose value is being retrieved Example set forSynthesis get file property my file v SYNTHESIS set file property This command sets the value of a single file property The file name passed to the function can be a partial file name as long as it is unique For example if the full file name is components my file v my file v is sufficient The available properties are described in the add files command set file property Sabi Main elaboration and generation Usage set file property filename lt propertyName gt lt propertyValue gt Returns Boolean filename The file name whose properties are being retrieved Arguments propertyName Name of the file property whose value is being retrieved propertyValue Value to set for the file property Example set file property my file v SYNTHESIS true SOPC Builder User Guide December 2010 Altera Corporation Chapter 7
143. eters must be 32 bit decimal integers When passing other numeric parameter types unpredictable results occur Refer to Chapter 7 Component Interface Tcl Reference for detailed information about creating and displaying parameters using Tcl scripts December 2010 Altera Corporation Chapter 6 Component Editor 6 7 Saving a Component Library Info The Library Info tab allows you to specify the following information about your component m Display Name Specifies the user visible name for this component in SOPC Builder m Version Specifies the version number of the component m Group Specifies which group in SOPC Builder displays your component in the list of available components If you enter a previously unused group name SOPC Builder creates a new group by that name m Description Allows you to describe the component m Created By Allows you to specify the author of the component m Icon Allows you to place an image in the title bar of your component in place of the MegaCore logo The icon can be a jpg gif or png file The directory for the icon is relative to the directory that contains the hw tcl file m Documentation Allows you to specify multiple documents that pertain to your component You can use this property to specify a file on the internet or in your company s file system The specified file can be in either html or pdf format To specify an internet file begin your path with http for example
144. eturned by the UI program includes the new paramter values set result exec my component ui exe pl p1 csr csr Use the fictional parse for new value procedure to parse the returned text for the new parameter values set pl parse for new value result pl set csr parse for new value result csr Return the new parameter values to SOPC Builder Set parameter value PARAMETER ONE p1 set parameter value CSR ENABLED csr return OK Hardware Tcl Command Reference This section provides a reference for all hardware Tcl commands as follows m Module Definition on page 7 14 m Parameters on page 7 21 m Display Items on page 7 29 m Interfaces and Ports on page 7 32 m Generation on page 7 38 The description of each command indicates during which phases it is available in the main body of the program main or during the validation elaboration generation and editor callback phases or any combination Table 7 2 summarizes the commands and provides a reference to the full description SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference 7 13 s Starting with Quartus II software version 9 1 all Tcl commands that you can use in the validation callback are also available in the elaboration callback With this change you may be able to omit the custom validation callback by including some validation commands in your elaboration cal
145. f the valid signal types for the type of interface Refer to the Avalon Interface Specifications for the signal types available for each interface type You can append nto indicate an active low signal Table 6 1 lists the valid values for interface type Table 6 1 Valid Values for Interface Type Value Meaning avs Avalon MM slave avm Avalon MM master ats Avalon MM tristate slave aso Avalon ST source asi Avalon ST sink cso Clock output csi Clock input coe Conduit inr Interrupt receiver ins Interrupt sender ncm Nios Il custom instruction master ncs Nios Il custom instruction slave December 2010 Altera Corporation Chapter 6 Component Editor 6 5 Signals Tab Example 6 1 shows a Verilog HDL module declaration with signal names that infer two Avalon MM slaves Example 6 1 Verilog HDL Module With Automatically Recognized Signal Names module my slave irq component Signals for Avalon MM slave port s1 with irq csi clockreset clk clockreset clock interface csi clockreset reset n clockreset clock interface avs sl address s1 slave interface avs s1 read s1 slave interface avs sl write s1 slave interface avs sl writedata s1 slave interface avs sl readdata s1 slave interface ins irq0 irq irq0 interrupt sender interface 3 input csi clockreset clk input csi clockreset reset n input 7 0 avs si address input avs s1 read input avs sl write
146. following sections m Adapters on page 3 3 m Multiplexer Examples on page 3 5 High Level Description Avalon ST interconnect fabric is logic generated by SOPC Builder Using SOPC Builder you specify how Avalon ST source and sink ports connect SOPC Builder then creates a high performance point to point interconnect between the two components The Avalon ST interconnect is flexible and can be used to implement on chip interfaces for industry standard telecommunications and data communications cores such as Ethernet IEEE 802 3 MAC and SPI 4 2 In all cases bus widths packets and error conditions are custom defined Figure 3 1 illustrates the simplest system example that generates an interconnect between the source and sink This source sink pair includes only the data and valid signals Figure 3 1 Interconnect for a Simple Avalon Streaming Source Sink Pair vali Data valid y Data Source data gt Sink Figure 3 2 illustrates a more extensive interface that includes signals indicating the start and end of packets channel numbers error conditions and back pressure Figure 3 2 Avalon Streaming Interface for Packet Data ready Data valid Data Source channel Sink startofpacket endofpacket empty error data gt December 2010 Altera Corporation SOPC Builder User Guide 3 2 Chapter 3 System Interconnect Fabric for Streaming Interfaces Avalon Streami
147. for use with the current version you normally use the current installed components If your SOPC Builder system was developed with an earlier version of the Quartus II Complete Design Suite and you restore it for use with the current version the regenerated system is functionally identical to the original system However there might be differences in details such as timing performance component implementation or HAL implementation Te For details of version changes refer to the Quartus II Reference Documentation To ensure that you can regenerate your exact original design maintain a record of the tool and IP version s originally used to develop the design Retain the original installation files or media in a safe place The archival process addressed by this chapter is different than Quartus II project archiving A Quartus II project archive contains the complete Quartus II project including the SOPC Builder module The Quartus II software adds all HDL files to the archive including HDL files generated by SOPC Builder although these files are not strictly necessary if you regenerate the design files afterwards A Quartus II project archive also archives the Quartus II IP qip file December 2010 Altera Corporation SOPC Builder User Guide 8 2 Chapter 8 Archiving SOPC Builder Projects Required Files This chapter is only concerned with archiving the SOPC Builder system without the generated HDL files Required Fil
148. g file is only needed in some parameterizations of the component you should add it from the main program and turn it on or off by setting its SYNTHESIS and SIMULATION properties appropriately from the elaboration callback Example 7 10 Generation Callback Example Set module property GENERATION CALLBACK my generate My generation method proc my generate Send message info Starting Generation get generation settings set language get generation property HDL LANGUAGE Set outdir get generation property OUTPUT DIRECTORY Set outputname get generation property OUTPUT NAME get parameter values set pl get parameter value PARAMETER ONE set csr get parameter value CSR ENABLED Your callback needs to write outdir outputname v here perhaps by using exec to call an external program add file creates files relative to the _hw tcl directory therefore specify Soutdir for synthesis and simulation files exec perl my generate pl lang Slanguage dir Soutdir name outputname pl p1 csr csr add file outdir outputname v SYNTHESIS add file outdir outputname sim v SIMULATION Editor Callback You can use the editor callback procedure to replace the parameterization GUI An editor callback is defined by setting the EDITOR CALLBACK module property to the name of your editor callback procedure as shown in the Example 7 11 If the editor callback is defined SOPC Builder calls the editor callback instead of display
149. gt directory for the project You should store the HDL and other files in the same directory as the _hw tcl file December 2010 Altera Corporation SOPC Builder User Guide 6 8 Chapter 6 Component Editor Editing a Component Editing a Component After you save a component and exit the component editor you can edit it in SOPC Builder To edit a component right click it in the list of available components on the System Contents tab and click Edit Component You cannot edit components that were created outside of the component editor such as Altera provided components If you edit the HDL for a component and change the interface to the top level module you need to edit the component to reflect the changes you made to the HDL Software Assignments You can use Tcl commands to create software assignments You can register any software assignment that you want as arbitrary key value pairs Example 6 2 shows a typical Tcl API script Example 6 2 Typical Software Assignment with Tcl API Scripting set_module_assignment name value set_interface_assignment name value The assignments are added to the SOPC information file sopcinfo available for use for downstream components Component Parameterization SOPC Builder User Guide To edit component instance parameters select a component in the System Contents tab of the SOPC Builder window and click Edit December 2010 Altera Corporation N OTS RYA 7 Component Inte
150. h of the address signal in the slave interface Slave interface s Byte Enable Width The width of the byte enable signal in the master interface The width of the byte enable signal in the slave interface December 2010 Altera Corporation SOPC Builder User Guide 11 24 Chapter 11 Avalon Memory Mapped Bridges Avalon MM DDR Memory Half Rate Bridge Example System The following example provides high level steps showing how the Avalon MM DDR Memory Half Rate Bridge core is connected in a system This example assumes that you are familiar with the SOPC Builder GUI Fora quick introduction to this tool read of the one hour online course Using SOPC Builder 1 Add a Nios II Processor to the system 2 Adda DDR2 SDRAM High Performance Controller and configure it to full rate mode 3 Add Avalon MM DDR Memory Half Rate Bridge to the system 4 Configure the parameters of the Avalon MM DDR Memory Half Rate Bridge based on the memory controller For example for a 32 MByte DDR memory controller in full rate mode with 8 DQ pins see Figure 11 14 the parameters should be set as the following m Data Width 16 For a memory controller that has 8 DQ pins its local interface width is 16 bits The local interface width and the data width must be the same therefore data width is set to 16 bits m Address Width 25 For a memory capacity of 32 MBytes the byte address is 25 bits Because the master address
151. h of the default behaviors by using callbacks This section explains how to write callback procedures for each phase of component development SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 9 Overriding Default Behaviors Validation Callback You can use the validation callback to provide validation that extends beyond the default range checking A validation callback is defined by setting the VALIDATION CALLBACK module property to be the name of the validation callback procedure as shown in Example 7 8 This validation procedure displays an error if you select a baud rate of 38400 and odd parity You can also use the validation callback to set the value of derived parameters Derived parameters are parameters that are derived from other parameters their values are not editable and are not saved in the SOPC Builder design file sopc You indicate that a parameter is derived by setting the parameter s DERIVED property to true In Example 7 8 BAUDRATE PRESCALE is a derived parameter whose value is 1 16 of the value of the BAUDRATE parameter Example 7 8 Custom Validation Callback Function Declare the validation callback set module property VALIDATION CALLBACK my validation callback Add the BAUDRATE PRESCALE parameter and indicate that it s derived add parameter BAUDRATE PRESCALE int 600 set parameter property BAUDRATE PRESCALE DERIVED true Add the PARITY parameter a
152. handle pipeline latency The system interconnect fabric forces the master to wait through any slave side aa me latency cycles This master slave pair gains no benefits of pipelining because C Pipelined with fixed i uo No pipeline or variable latent the master waits for each transfer to complete before beginning a new transfer y However while the master is waiting the slave can accept transfers from a different master Pipelined No pipeline The system interconnect fabric carries out the transfer as if neither master nor p pip slave were pipelined causing the master to wait until the slave returns data Pipelined with fixed The system interconnect fabric allows the master to capture data at the exact Pipelined din clock cycle when data from the slave is valid This process enables the y master slave pair to achieve maximum throughput performance Pipelined with This is the simplest pipelined case in which the slave asserts a signal when its Pipelined Cane iatane readdata is valid and the master captures the data This case enables this y master slave pair to achieve maximum throughput SOPC Builder generates logic to handle pipeline latency based on the properties of the master and slaves in the system When configuring a system in SOPC Builder there are no settings that directly control the pipeline management logic in the system interconnect fabric Dynamic Bus Sizing and Native Address Alignment SOPC Builder User Guide SOPC Bui
153. he FPGA configuration process and therefore the EPCS controller does not model the configuration features December 2010 Altera Corporation SOPC Builder User Guide 9 10 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough EPCS Serial Configuration Device m The simulation model does not support read and write operations to the flash region of the EPCS device m A Nios II processor can boot from the EPCS device in simulation However the boot loader code is different during simulation The EPCS controller boot loader code assumes that all other memory simulation models are initialized and therefore the boot load process is unnecessary During simulation the boot loader simply forces the Nios II processor to jump to start skipping the boot load process Verification in the hardware is the best way to test features related to the EPCS device Quartus Il Project Level Design for an EPCS Device If you use a device from Cyclone III Stratix III or Stratix IV families you must connect the EPCS pins manually For earlier device families however the Quartus II software automatically connects the EPCS controller core in the SOPC Builder system to the dedicated configuration pins on the FPGA This connection is invisible to you Therefore there are no EPCS related signals to connect in the Quartus II project Board Level Design for an EPCS Device You must connect the EPCS device to the FPGA as described in the Altera Conf
154. he following Building systems with SOPC Builder For details refer to Chapter 1 Introduction to SOPC Builder SOPC Builder components For details refer to Chapter 4 SOPC Builder Components Basic concepts of the Avalon MM interface December 2010 Altera Corporation SOPC Builder User Guide 10 2 Chapter 10 SOPC Builder Component Development Walkthrough Hardware and Software Requirements Hardware and Software Requirements To use the design example in this chapter in addition to the current version of the Quartus II software and Nios II Embedded Design Suite you must have the following m Design files for the example design A hyperlink to the design files appears next to this user guide on the SOPC Builder literature page m Nios development board and an Altera USB Blaster download cable You can use either of the following Nios development boards m Stratix II Edition RoHS compliant version m Cyclone II Edition If you do not have a development board you can follow the hardware development steps You cannot download the complete system without a working board but you can simulate the system Te You can download the Quartus II Web Edition software and the Nios II EDS Evaluation Edition for free from the Altera Download Center at www altera com Component Development Flow This section provides an overview of the development process for SOPC Builder components Typical Design Steps A typical develo
155. hw tcl file defines a single component m IPIndex ipx files Each file indexes a collection of available components In general ipx files facilitate faster startup for SOPC Builder and other tools because fewer files need to be read and analyzed Some directories are searched recursively others only to a specific depth In the following list of search locations a recursive descent is annotated by The signifies any file When a directory is recursively searched the search stops at any directory containing a hw tcl or ipx file subdirectories are not searched E SSPROJECT DIR m SSPROJECT DIR ip B SQUARTUS INSTALLDIR ip In SOPC Builder you can extend the default search path by including additional directories by clicking Options then clicking IP Search Path and Add These additional paths apply to all projects that is the paths are global to the current version of SOPC Builder The search path is ultimately defined by the file lt QUARTUS_INSTALLDIR gt sopc_builder bin root_components ipx Installing Additional Components There are a few different ways to make your components available to SOPC Builder projects The following sections describe some of these methods SOPC Builder User Guide December 2010 Altera Corporation Chapter 4 SOPC Builder Components 4 5 Installing Additional Components Copy to the IP Root Directory The simplest strategy is to copy your components into the standard IP directory
156. ic that the adapter can insert that prevents data loss when the source asserts valid but the sink is not ready The adapter provides simulation time error messages and an error indication if data is ever lost The user is presented with a warning and the connection is allowed The source and sink both support backpressure but the sink s ready latency is greater than the source s The source responds to ready assertion or deassertion faster than the sink requires it A number of pipeline stages equal to the difference in ready latency are inserted in the ready path from the sink back to the source causing the source and the sink to see the same cycles as ready cycles The source and sink both support backpressure but the sink s ready latency is less than the source s The source cannot respond to ready assertion or deassertion in time to satisfy the sink A buffer whose depth is equal to the difference in ready latency is inserted to compensate for the source s inability to respond in time Jeydepy uru sjuauodui 129uuo219ju Bumuieans uojeAy z 19 deug L 12 4 Chapter 12 Avalon Streaming Interconnect Components Timing Adapter Resource Usage and Performance Resource utilization for the timing adapter depends upon the function that it performs Table 12 2 provides estimated resource utilization for seven different configurations of the timing adapter Table 12 2 Timing Adapter Estimated Resource Usage and P
157. ides the base address of each Avalon MM slave component In addition each slave component can provide software drivers and other software functions and libraries for the processor You can create C header files for your system using the sopc create header files utility For details type sopc create header files help ina Nios II Command shell For more details about how to provide Nios II software drivers for components refer to the Developing Device Drivers for the Hardware Abstraction Layer chapter of the Nios II Software Developer s Handbook The Nios II EDS is separate from SOPC Builder but it uses the output of SOPC Builder as the foundation for software development Creating a Simulation Model and Test Bench You can simulate your system after generating it with SOPC Builder During system generation SOPC Builder outputs a simulation test bench and a ModelSim setup script that eases the system simulation effort The test bench does the following m Instantiates the SOPC Builder system m Drives all clocks and resets m Instantiates simulation models for off chip devices when available SOPC Builder Design Flow SOPC Builder User Guide Figure 1 2 illustrates an example bottom up design flow in SOPC Builder which starts with component design As this flow diagram illustrates the typical design flow includes the following high level steps 1 Package your component for SOPC Builder using the Component Editor December 2010 Alter
158. idge address 1 Al No connect tri state bridge address 2 A2 A0 tri state bridge address 3 A3 A1 tri state bridge address 4 A4 A2 tri_state_bridge_address 5 A5 A3 tri_state_bridge_address 6 A6 A4 tri_state_bridge_address 7 A7 A5 tri state bridge address 8 A8 A6 tri state bridge address 9 A9 A7 tri_state_bridge_address 10 A10 A8 tri_state_bridge_address 11 A11 A9 tri_state_bridge_address 12 A12 A10 tri_state_bridge_address 13 A13 A11 tri_state_bridge_address 14 A14 A12 tri_state_bridge_address 15 A15 A13 tri_state_bridge_address 16 A16 A16 tri_state_bridge_address 17 A17 A15 tri_state_bridge_address 18 A18 A16 tri_state_bridge_address 19 A19 A17 tri_state_bridge_address 20 A20 No connect tri_state_bridge_address 21 A21 No connect tri_state_bridge_address 22 A22 No connect December 2010 Altera Corporation SOPC Builder User Guide 9 24 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory SOPC Builder User Guide December 2010 Altera Corporation 10 SOPC Builder Component JN DTE RAN 8 Development Walkthrough This chapter describes the parts of a custom SOPC Builder component and guides you through the process of creating an example custom component integrating it into a system and testing it in hardware This chapter is divided into the following sections Component Development Flow on page 10 2 Design Example Checksum Hardware Acceler
159. ified interface set interface assignment sabi Main validation and elaboration Usage set interface assignment lt interfaceName gt name value Returns None interfaceName The name of the Avalon interface whose assignment is being set Arguments name The assignment whose value is being set value The value to assign Example set interface assignment s1 embeddedsw configuration isFlash 1 Generation This section covers the commands that get generation properties SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 39 Hardware Tcl Command Reference get_generation_properties This command returns the names of all the available generation properties as a space separated list These properties cannot be changed by the module Generation properties are provided to the generation callback to support per instance HDL generation get_generation_properties Men Main validation elaboration generation and editor Usage get generation properties String The following generation properties are supported m hdl language Returns m output directory W output name Refer to Table 7 8 for a description of the generation properties Arguments None Example get generation properties Table 7 8 describes the generation properties Table 7 8 Generation Properties hdl language output directory file Type Description
160. ify an interface There are 7 interfaceTypes The following directions are possible for these interfaceTypes Interface TypeDirection avalonmaster slave 2 interfaceType and avalon tristateslave Arguments direction avalon streamingsource sink interruptsender receiver conduitend clocksource sink nios custom instructionslave nacio EL de This defines the clock associated with the interface It is required for all interfaces except clock interfaces Example add interface mm slave avalon slave clock0 Notes 1 For interfaces that are not associated with clocks such as clock interfaces themselves the associatedClock is omitted Another option is to specify the associatedClock argument as asynchronous 2 The terms master source and start are interchangeable The terms s ave sink and end are interchangeable get interfaces This command returns the names of all interfaces that have been previously defined by add interface as a space separated list get interfaces Mem Main validation elaboration generation and editor Usage get interfaces Returns List of strings Arguments None Example set all interfaces get interfaces December 2010 Altera Corporation SOPC Builder User Guide 7 34 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference get_interface_properties This command returns the names of all the available interface properties for the specified interface as a
161. iguration Handbook No other connections are necessary Example Design with an EPCS Device SOPC Builder User Guide This section demonstrates adding an EPCS device controller core to the example design For demonstration purposes only Figure 9 4 shows the result of generating the SOPC Builder system at this stage Figure 9 4 SOPC Builder System with EPCS Device Because the Quartus II software automatically connects the EPCS controller core to the FPGA pins the SOPC Builder system has no I O signals associated with epcs controller Therefore you do not need to make any connections or assignments between the Quartus II project and the EPCS controller core This chapter does not cover the details of configuration using the EPCS device For further information refer to the Altera Configuration Handbook December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 11 SDR SDRAM SDR SDRAM Altera provides a free SDR SDRAM controller core which allows you to use inexpensive SDRAM as bulk RAM in your FPGA designs The SDR SDRAM controller core is necessary because Avalon MM signals cannot describe the complex interface on an SDRAM device The SDR SDRAM controller acts as a bridge between the system interconnect fabric and the pins on an SDRAM device The SDR SDRAM controller can operate in excess of 100 MHz SDR SDRAM is a single data rate SDR SDRAM Synchronous design allows preci
162. ing that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI CAUTION An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure HN Bullets indicate a list of items when the sequence of the items is not important i The hand points to information that requires special attention A question mark directs you to a software help system with related information Se The feet direct you to another document or website with related information A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING Lj A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents SOPC Builder User Guide December 2010 Altera Corporation
163. ing the parameterization GUI typically when the component is added to a system or updated after it is in the system To display your custom GUI the editor callback must call another program Typically an editor callback provides the current parameter values to your program via the command line and collects the new parameter values via stdout The editor callback then uses the set parameter value command to update SOPC Builder with the new parameter values The editor callback returns one of the following three values m OK indicates that the results of the edit should be applied W CANCEL indicates that the system should revert to the state it was in before the editor callback was called m ERROR indicates that the GUI was unable to launch An appropriate error message should be displayed December 2010 Altera Corporation SOPC Builder User Guide 7 12 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference If no value is returned OK is assumed Example 7 11 Editor Callback Set module property EDITOR CALLBACK my editor Define Module parameters add_parameter PARAMETER ONE integer 32 A parameter add_parameter CSR_ENABLED boolean true Enable CSR interface My editor method proc my editor get parameter values set pl get_parameter_value PARAMETER ONE set csr get parameter value CSR ENABLED Display UI populated with current parameter values The stdout r
164. ink m Avalon MM tristate slave m Interrupt sender and receiver m Clock input and output m Nios II custom instruction master and slave interfaces m Conduit for exporting signals to the top level m Fachinterface is comprised of one or more signals m Thecomponent can represent logic that is instantiated inside the SOPC Builder system or can represent logic outside the system with an interface to it on the generated system Starting the Component Editor HDL Files Tab To start the component editor in SOPC Builder on the File menu click New Component When the component editor starts the Introduction tab displays which describes how to use the component editor The component editor presents several tabs that group related settings A message window at the bottom of the component editor displays warning and error messages Each tab in the component editor provides on screen information that describes how to use the tab Click the triangle labeled About at the top left of each tab to view these instructions You can also refer to Quartus II online Help for additional information about the component editor You navigate through the tabs from left to right as you progress through the component creation process The HDL Files tab allows you to create an SOPC Builder component from existing Verilog HDL or VHDL files or to create an HDL template in either Verilog HDL or VHDL for a SOPC Builder component by first specifying its interfaces
165. interface to logic outside the SOPC Builder system Figure 4 1 shows an example of both types of components Figure 4 1 Component Logic Inside and Outside the SOPC Builder System Conduit Ports or Interface for Exporting Signals Avalon Interface Automatically Connected by SOPC Builder System Module Component Logic HDL Files Exported Signals from Component System Interconnect Fabric Rest of the System 9 S o External Sinal 3938 Logic ignals s a Unrelated E Off Chip to SOPC Device Builder Avalon Interface Manually Connected by System Designer Component Instances Inside the SOPC Builder System SOPC Builder User Guide For components that are instantiated inside the SOPC Builder system the component defines its logic in an associated HDL file During system generation SOPC Builder instantiates the component and connects it to the rest of the system The component can include exported signals in conduit interfaces Conduit interfaces become ports on the system so they can be connected to logic outside the SOPC Builder system in the board level schematic For more information about conduit interfaces refer to the Conduit Interfaces chapter in the Avalon Interface Specifications In general components connect to the system interconnect fabric using the Avalon Memory Mapped Avalon MM interface or the Avalon Streaming Avalon ST i
166. ion error and signals an error for data for any channel from the source other than 0 The sink has channel but the source does not You are given a warning and the channel inputs to the sink are all tied to a logical 0 The source and sink both support channels and the source s maximum number of channels is less than the sink s The source s channel is connected to the sink s channel unchanged If the sink s channel signal has more bits the higher bits are tied to a logical 0 The source and sink both support channels but the source s maximum number of channels is greater than the sink s The source s channel is connected to the sink s channel unchanged If the source s channel signal has more bits the higher bits are left unconnected You are given a warning that channel information may be lost An adapter provides a simulation error message and an error indication if the value of channel from the source is greater than the sink s maximum number of channels In addition the valid signal to the sink is deasserted so that the sink never sees data for channels that are out of range December 2010 Altera Corporation SOPC Builder User Guide 12 8 Chapter 12 Avalon Streaming Interconnect Components Channel Adapter Resource Usage and Performance The channel adapter typically uses fewer than 30 LEs Its frequency is limited by the maximum frequency of the device you choose Instantiating the Channel A
167. iteminstead Deprecated Generation Properties language hdl language SOPC Builder User Guide December 2010 Altera Corporation N DTE RYN l 8 Archiving SOPC Builder Projects This chapter identifies the files you must include when archiving an SOPC Builder project With this information you can archive the SOPC Builder system You may want to archive your SOPC Builder system for one of the following reasons m To place an SOPC Builder design under source control m Tocreate a backup m To bundle a design for transfer to another location To use this information you must decide what source control or archiving tool to use and you must know how to use it This chapter describes how to find and identify the files that you must include in an archived SOPC Builder design Refer to Required Files on page 8 2 Limitations This chapter provides information about archiving SOPC Builder systems including Nios II software applications if any If your SOPC Builder system does not contain a Nios II processor you can disregard information about archiving Nios II software applications This chapter does not cover archiving SOPC Builder components for two reasons m SOPC Builder components can be recovered if necessary from the original Quartus II and Nios II installations m Ifyour SOPC Builder system was developed with an earlier version of the Quartus II software and Nios II Embedded Design Suite EDS when you restore it
168. itions If a port is absent from the module it is removed from the port list You can use the up and down arrows to specify the HDL file analysis order By default all files are added with both Synth and Sim options turned on To add a simulation only file turn off the Synth option for that file Files that turn on the Sim option are passed to ModelSim for simulation To add a synthesis only file turn off the Sim file option Only files that you mark for Synth are added to the Quartus II IP File qip for your project The component editor determines the signals on the component when only the top level module or entity is added to the table but all of the files required for the component must be added for the component to compile in Quartus II software or work in simulation Top Down Design Signals Tab The Create HDL Template button on the HDL Files tab allows you to create an HDL template for a component if you have not provided a HDL description for it Clicking the Create HDL Template button shows you the component HDL and lets you choose between Verilog HDL and VHDL Altera recommends that you define your signals interfaces parameters and basic component information including the component name before creating the HDL template by clicking Save The component editor writes lt component_name gt v or lt component_name gt vhd to your project directory After you have component the component s HDL code you can add other files
169. itor to generate an automatic Tcl description of it This section describes the structure of Tcl components and how they are stored For details about the SOPC Builder component editor refer to Chapter 6 Component Editor For details about the SOPC Builder Tcl commands refer to Chapter 7 Component Interface Tcl Reference December 2010 Altera Corporation Chapter 4 SOPC Builder Components 4 9 Component Structure Component Description File hw tcl A Tcl component consists of m Acomponent description file which is a Tcl file with file name of the form entity name hw tcl m Verilog HDL or VHDL files that define the top level module of the custom component optional The hw tcl file defines everything that SOPC Builder requires about the name and location of component design files The SOPC Builder component editor saves components in the hw tcl format You can use these Tcl files as a template for editing components by hand When you edit a previously saved hw tcl file SOPC Builder automatically saves the earlier version as _hw tcl For more information about the information that you can include in the _hw tcl file refer to the Chapter 7 Component Interface Tcl Reference Component File Organization A typical component uses the following directory structure The precise names of the directories are not significant m lt component_directory gt m lt hdl gt a directory that contains the component HDL
170. l compilation feature which allows you to separately compile isolated portions or partitions of a design From within the Quartus II software you can designate an entire SOPC Builder system as a design partition or you can designate individual SOPC Builder components as design partitions La Changing the parameters of a component and regenerating your system only prompts other partitions within the same system to recompile if the HDL in that partition depends on the changed parameters The HDL you generate for the Nios II processor is optimized as related to components to which the Nios II processor is connected December 2010 Altera Corporation SOPC Builder User Guide 5 2 Chapter 5 Using SOPC Builder with the Quartus Il Software TimeQuest Timing Analyzer For more information about incremental compilation refer to the Quartus II Incremental Compilation for Hierarchical and Team Based Design chapter in volume 1 of the Quartus II Handbook TimeQuest Timing Analyzer Altera recommends the TimeQuest Timing Analyzer in the Quartus II software for analysis of all new designs SOPC Builder automatically generates a TimeQuest sdc constraints file for SOPC Builder systems and components In most cases you use the TimeQuest constraints to declare false paths for signals that cross clock domains within a component so that the TimeQuest Timing Analyzer does not perform normal setup and hold analysis for them You can add sdc files for cus
171. lback Table 7 2 Command Summary Note 1 Part 1 of 2 December 2010 Altera Corporation Command Full Description Module Definition package require exact sopc version page 7 14 get module properties page 7 15 get module property propertyName page 7 16 set module property propertyName lt propertyValue gt page 7 17 get module ports page 7 17 get module assignments page 7 17 get module assignment moduleName page 7 18 set module assignment lt moduleName gt value page 7 18 get files page 7 18 add file filename fileProperties page 7 19 add documentation link docType title fileOrUrl page 7 19 get file properties page 7 20 get file property filename propertyName page 7 20 set file property filename propertyName lt propertyValue gt page 7 20 send message lt messageLevel gt messageText page 7 21 Parameters add parameter parameterName lt parameterType gt defaultValue lt description gt page 7 22 get parameters page 7 22 get_parameter properties page 7 23 get_parameter property lt parameterName gt lt propertyName gt page 7 27 Set parameter property parameterName propertyName value page 7 27 get parameter value parameterName page 7 28 set parameter value parameterName value page 7 28 decode address map address map XML string page 7 28 Di
172. lder generates system interconnect fabric to accommodate master and slaves with unmatched data widths Address alignment affects how slave data is aligned in a master s address space in the case that the master and slave data widths are different Address alignment is a property of each slave and can be different for each slave in a system A slave can declare itself to use one of the following m Dynamic bus sizing December 2010 Altera Corporation Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces 2 7 Dynamic Bus Sizing and Native Address Alignment m Native address alignment The following sections explain the implications of the address alignment property slave devices Dynamic Bus Sizing Dynamic bus sizing hides the details of interfacing a narrow component device to a wider master and vice versa When an lt N gt bit master accesses a slave with dynamic bus sizing the master operates exclusively on full lt N gt bit words of data without awareness of the slave data width La When using dynamic bus sizing the slave data width in units of bytes must be a power of two Dynamic bus sizing provides the following benefits m Eliminates the need to create address alignment hardware manually m Reduces design complexity of the master component m Enables any master to access any memory device regardless of the data width In the case of dynamic bus sizing the system interconnect fabric includes a small finit
173. le in SOPC Builder include the UART Timer and SPI core You are connecting a pipeline bridge to one of these components increase the read latency from 0 to 1 CAUTION The Avalon MM pipeline bridge component integrates easily into any SOPC Builder system December 2010 Altera Corporation SOPC Builder User Guide 11 10 Functional Description Figure 11 8 shows a block diagram of the Avalon MM pipeline bridge component Figure 11 8 Avalon MM Pipeline Bridge Block Diagram Master to Slave Signals Connects to an Avalon MM Slave waitrequest Interface Slave to Master Signals Chapter 11 Avalon Memory Mapped Bridges Avalon MM Pipeline Bridge Avalon MM Pipeline Bridge waitrequest Pipeline Logic Wait Request Master to Slave Pipeline E Master to Slave Signals Master VF Connects to an Avalon MM q waitrequest Master Interface 4 Slave to Master Signals Slave to Master Pipeline SOPC Builder User Guide The following sections describe the component s hardware functionality Interfaces The bridge interface is composed of an Avalon MM slave and an Avalon MM master The data width of the ports is configurable which can affect how SOPC Builder generates dynamic bus sizing logic in the system interconnect fabric Both ports support Avalon MM pipelined transfers with variable latency Both ports optionally support b
174. le of latency for Avalon MM masters accessing memory connected to the tristate bridge in each direction The registers do not affect the timing setup hold and wait of the transfers from the perspective of the memory device For details about the Avalon MM tristate interface refer to the Avalon Interface Specifications Flash Memory In SOPC Builder you instantiate an interface to CFI flash memory by adding a Flash Memory Common Flash Interface component If the flash memory is not CFI compliant you must create a custom interface to the device with the SOPC Builder component editor The choice of flash devices and the configuration of the devices on the board help determine the component level design for the flash memory configuration wizard Typically the component level design task involves parameterizing the flash memory interface to match the devices on the board Using the Flash Memory Common Flash Interface configuration wizard you must specify the structure address width and data width and the timing specifications of the flash memory devices For details about features and usage refer to the Common Flash Interface Controller Core chapter in the Embedded Peripherals IP User Guide December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 17 Off Chip SRAM and Flash Memory For an example of instantiating the Flash Memory Common Flash Interface component in an SOPC Builder sys
175. ll three masters have logical connections to all three slaves although physically each master only connects to the bridge Figure 11 1 Example of an Avalon MM Bridge in an SOPC Builder System Arbiter amp Write Data Control Signal Multiplexing Y S Avalon MM Bridge M A ChipSelect amp Read Data Multiplexing s S S 1 S2 S3 M Avalon MM Master S Avalon MM Slave Transfers initiated to the bridge s slave propagate to the master in the same order in which they are initiated on the slave For details on the Avalon MM interface refer to the Avalon Interface Specifications Reasons for Using a Bridge SOPC Builder User Guide When you have no bridges between master slave pairs SOPC Builder generates a system interconnect fabric with maximum parallelism such that all masters can drive transactions to all slaves concurrently as long as each master accesses a different slave For systems that do not require a large degree of concurrency the default behavior might not provide optimal performance With knowledge of the system and application you can optimize the system interconnect fabric by inserting bridges to control the system topology December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 3 Structure of a Bridge Figure 11 2 and Figure 11 3 show an SOPC system without bridges This sy
176. llback will not be called when parameters with AFFECTS ELABORATION false are changed by the user of the component Example 7 9 Elaboration Callback Declare the callback set module property ELABORATION CALLBACK my elaboration callback 4 Add the USE STATUS INTERFACE parameter add parameter USE STATUS INTERFACE boolean Declare the status slave interface add interface status slave avalon slave clock sink set interface property status slave ENABLED false The elaboration callback Declare signals add interface port status slave st readdata readdata output 16 add interface port status slave st read read input 1 add interface port status slave st write write input 1 add interface port status slave st waitrequest waitrequest output 1 add interface port status slave st address address input 24 add interface port status slave st writedata writedata input 16 The elaboration callback proc my elaboration callback Get the current value of parameters we care about Set use status get parameter value USE STATUS INTERFACE Optionally add the status interface if Suse status Set interface property status slave ENABLED true Generation Callback If you define a generation callback SOPC Builder does not generate an HDL wrapper file to apply parameter values to your component Instead it calls the generation callback you defined during the generation phase allowing the component to programmatically generate its HDL
177. ltimaster systems minimize the impact of arbitration on the system throughput Fundamentals of Implementation System interconnect fabric for memory mapped interfaces implements a partial crossbar interconnect structure that provides concurrent paths between master and slaves System interconnect fabric consists of synchronous logic and routing resources inside the FPGA For each component interface system interconnect fabric manages Avalon MM transfers interacting with signals on the connected component Master and slave interfaces can contain different signals and the system interconnect fabric handle any adaptation necessary between them In the path between master and slaves the system interconnect fabric might introduce registers for timing synchronization finite state machines for event sequencing or nothing at all depending on the services required by the specific interfaces For more information refer to the Avalon Memory Mapped Design Optimizations chapter in the Embedded Design Handbook Functions of System Interconnect Fabric System interconnect fabric logic provides the following functions m Address Decoding on page 2 3 m Datapath Multiplexing on page 2 4 m WaitState Insertion on page 2 5 E Pipelined Read Transfers on page 2 6 Arbitration for Multimaster Systems on page 2 9 m Burst Adapters on page 2 14 m Interrupts on page 2 15 m Reset Distribution on page 2 16 The behavior of thes
178. master s address map is easier and ensures that your code will work with future versions of the XML address map 5E Altera recommends that you use the code provided in the description of Example 7 13 to enumerate over the components within an address map rather than writing your own parser Example 7 13 Address Map for an Avalon MM Master address map Slave name ext ssram start 0x01000000 end 0x01200000 gt slave name sys clk timer start 0x02120800 end 0x02120820 gt slave name sysid start 0x021208B8 end 0x021208C0 gt address map decode address map Callback ss UE Validation compose elaboration and generation availability alidation compose elaboration and generatio Usage decode address map address map XML string Returns List of Tcl lists each one suitable for passing to array set dd Hay Arguments acaress_map_ An XML string describing the address map of an Avalon MM master XML string set address map xml get parameter value my map param set address map dec decode address map address map xml Example foreach i S address map dec array set info i send message info Connected to slave info name Display Items You specify your component GUI using the display commands add_display_item You can use this command to specify the following aspects of component display m You can create logical groups for a component s parameters For example
179. mory device which has slow access time Altera provides software drivers to control the EPCS core for the Nios II processor only T For further details about the features and usage of the EPCS device controller core refer to the EPCS Device Controller Core chapter in the Embedded Peripherals IP User Guide Component Level Design for an EPCS Device In SOPC Builder you instantiate an EPCS controller core by adding an EPCS Serial Flash Controller component There are no settings for this component For details refer to the Nios II Flash Programmer User Guide SOPC Builder System Level Design for an EPCS Device There are two SOPC Builder system level design considerations for EPCS devices m Assign a base address m Set the IRQ connection to NC no connect The EPCS controller hardware is capable of generating an IRQ However the Nios II driver software does not use this IRQ and therefore you can leave the IRQ signal disconnected There can only be one EPCS controller core per FPGA and the instance of the core is always named epcs controller If you want to store Nios II code in the EPCS memory point the Nios II reset address at the EPCS controller Inside the EPCS controller is a bootloader which Nios II runs after it leaves reset that copies the code from the EPCS flash into main memory Simulation for an EPCS Device The EPCS controller core provides a limited simulation model m Functional simulation does not include t
180. mponent by right clicking on the component and selecting Add version version number m Youcancreate an ipx file in the same directory as your SOPC Builder project to control the search path for your project Classic Components in SOPC Builder If you use classic components created with an version 7 2 of SOPC Builder or earlier read through this section to familiarize yourself with the differences This document uses the term classic components to refer to class ptf based components created with a previous version of the Quartus II software If you do not use classic components skip this section Classic components are compatible with newer versions of SOPC Builder but be aware of the following caveats m Classic components configured with the More Options tab in SOPC Builder such as complex IP components provided by third party IP developers are not supported in the Quartus II software in version 7 1 and beyond If your component has a bind program you cannot use the component without recreating it with the component editor or with Tcl scripting m Tomake changes to a classic component with the component editor you must first upgrade the component by editing the classic component and saving it in the _hw tcl component format in the component editor SOPC Builder User Guide December 2010 Altera Corporation 5 Using SOPC Builder with the Quartus II ANU S RYA Software This chapter describes the Quartus II software feat
181. n Memory Mapped Bridges 11 9 Avalon MM Pipeline Bridge Component Overview The Avalon MM pipeline bridge inserts registers in the path between its master and slaves In a given SOPC Builder system if the critical register to register delay occurs in the system interconnect fabric the pipeline bridge can help reduce this delay and improve system fmax The bridge allows you to independently pipeline different groups of signals that can create a critical timing path in the interconnect m Master to slave signals such as address write data and control signals m Slave to master signals such as read data m The waitrequest signal to the master 5 You can also use the Avalon MM pipeline bridge to control topology without adding a pipeline stage To instantiate a bridge that does not add any pipeline stages simply do not select any of the Pipeline Options on the parameter page For the system illustrated in Figure 11 5 a pipeline bridge that does not add a pipeline register stage is optimal because the CPUs benefit from minimal delay from the message buffer mutex and message buffer RAM A pipeline bridge with no latency cannot be used with slaves that support pipelined reads If a slave does not have read latency you cannot connect it to a bridge with no pipeline stages because the pipeline bridge slave port has a readdatavalid signal Pipelined read components cannot have zero read latency Some examples of 0 latency components availab
182. n reset n input 1 Declare the Avalon slave interface name avalon slave 0 type avalon directon slave associated with the clock sink clock interface add interface avalon slave 0 avalon slave clock sink Set a number of properties about the Avalon Slave interface set interface property avalon slave 0 writeWaitTime 0 set interface property avalon slave 0 addressAlignment DYNAMIC set interface property avalon slave 0 readWaitTime 1 set interface property avalon slave 0 readLatency 0 Declare all the signals that belong to my Avalon Slave interface add interface port avalon slave 0 my readdata readdata output 8 add interface port avalon slave 0 my read read input 1 add interface port avalon slave 0 my write write input 1 add interface port avalon slave 0 my waitrequest waitrequest output 1 add interface port avalon slave 0 my address address input 24 add interface port avalon slave 0 my writedata writedata input 8 Adding Files and Guiding Generation Component description files typically provide all of the information required for generation and downstream tools You also identify which of the added files is the top level HDL file and specify which Verilog module or VHDL entity within that file is the top level module for the component Example 7 5 illustrates the files that are typically required for generation and downstream tools Example 7 5 Add Files Add the HDL file to the component to be used for synthesis and sim
183. n the worst case which is for reads each transfer is extended by five master clock cycles and five slave clock cycles Assuming the default value of 2 for the Master domain synchronizer length and the Slave domain synchronizer length the components of this delay are the following m Four additional master clock cycles due to the master side clock synchronizer m Four additional slave clock cycles due to the slave side clock synchronizer December 2010 Altera Corporation SOPC Builder User Guide 11 20 Chapter 11 Avalon Memory Mapped Bridges Avalon MM DDR Memory Half Rate Bridge m One additional clock in each direction due to potential metastable events as the control signals cross clock domains Systems that require a higher performance clock should use the Avalon MM clock crossing bridge instead of the automatically inserted CDC logic The clock crossing bridge includes a buffering mechanism so that multiple reads and writes can be pipelined After paying the initial penalty for the first read or write there is no additional latency penalty for pending reads and writes increasing throughput by up to four times at the expense of added logic resources For more information refer to Chapter 3 System Interconnect Fabric for Streaming Interfaces and Avalon Memory Mapped Design Optimizations in the Embedded Design Handbook Implementing Multiple Clock Domains in SOPC Builder You specify the clock domains used by your system on the
184. ndard SOPC Builder simulation flow to simulate the component design files inside an SOPC Builder system Software Programming Model The Avalon ST interconnect components do not have any control or status registers that you can see Therefore software cannot control or configure any aspect of the interconnect components at run time These components cannot generate interrupts SOPC Builder User Guide December 2010 Altera Corporation N DTE BAAN Additional Information Document Revision History The following table shows the revision history for this document Date Version Changes First release in user guide document format Refer to the Quartus I Development Software December 2010 1 0 Literature Archive website for previous revision history as Quartus II Handbook Volume 4 SOPC Builder How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the
185. ng a 16 Mbyte SDRAM device to the example design using the SDRAM Controller configuration wizard This SDRAM is a single device with 32 bit data December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 13 SDR SDRAM For demonstration purposes Figure 9 5 shows the result of generating the SOPC Builder system at this stage and connecting it in toplevel design bdf Figure 9 5 toplevel design bdf with SDRAM sdram_pll SDRAM PLL This PLL introduces a phase shift which compensates for board level delays in the clock network Other boards pib CLOCKINBUR l incKO inclkO frequency 50 000 MHz co may require different settings Operation Mode Normal 0 purs r BLO CLKGUT Cik Ratio Ph apoE co c0 171 0 00 50 00 e0 1 1 52 00 50 00 inst2 Stratix i sopc_memory_system delay_reset_block ck clock in delayed reset n reset n POSEAN AERIS reset_n zs addr from the sdram 14 0 Yer zs ba from the sdram 0 Reset Delay Allows PLL to stabilize lock after zs_pas_p from jhe_sdrem reset or device configuration 15 5ke froem The piran Z5 Cs n from the sdram zs dq to end from the sdram 31 0 zs dqm from the sdram 3 0 zs ras n from the sdram zs we n from the sdram suai SDRAWWEN After generating the system the top level SOPC Builder system file sopc memory system v contains
186. ng and Avalon Memory Mapped Interfaces All data transfers using Avalon ST interconnect occur synchronously to the rising edge of the associated clock interface All outputs from the source interface including the data channel and error signals must be registered on the rising edge of the clock Registers are not required for inputs at the sink interface Registering signals only at the source provides for high frequency operation while eliminating back to back registration with no intervening logic There is no inherent maximum performance of the interconnect Throughput for a system depends on the components and how they are connected For details about the Avalon ST interface protocol refer to the Avalon Interface Specifications Avalon Streaming and Avalon Memory Mapped Interfaces SOPC Builder User Guide The Avalon ST and Avalon Memory Mapped Avalon MM interfaces are complementary High bandwidth components with streaming data typically use Avalon ST interfaces for the high throughput datapath These components can also use Avalon MM connection interfaces to provide an access point for control In contrast to the Avalon MM interconnect which can be used to create a wide variety of topologies the Avalon ST interconnect fabric always creates a point to point between a single data source and data sink as Figure 3 3 illustrates There are two connection pairs in this figure m The data source in the Rx Interface transfers data to the
187. nits depending on property parameterName Specifies the parameter that is being set Arguments propertyN ie sie d eee Mor E that is being set refer to Table 7 4 on value Provides the values Example set parameter property BAUD RATE ALLOWED RANGES 9600 19200 38400 December 2010 Altera Corporation SOPC Builder User Guide 7 28 Chapter 7 Component Interface Tcl Reference get_parameter_value Hardware Tcl Command Reference This command returns the current value of a parameter defined previously with the add_parameter command get_parameter_value Sli Validation elaboration 1 compose generation and editor Usage get parameter value lt parameterName gt Returns String Arguments parameterName Specifies the parameter that is being retrieved Example set fifo width get parameter value fifo width Note 1 If AFFECTS ELABORATION false for a given parameter get parameter value is not available for that parameter from the elaboration callback If a ects generation false then it is not available from the generation callback set_parameter_value This command sets a parameter value The values of derived parameters can be set from the validation and elaboration callbacks The values of parameters which are not marked as derived or system_info can be set from the editor callback set_parameter_value SIN Validation elaboration and editor Usage set parameter value par
188. nterface A single component can provide more than one Avalon port For example a component might provide an Avalon ST source port for high throughput data in addition to an Avalon MM slave for control December 2010 Altera Corporation Chapter 4 SOPC Builder Components 4 3 Exported Connection Points Conduit Interfaces Static HDL Components You can define SOPC Builder components that accept Verilog HDL parameters or VHDL generics Examples of parameters that can be expressed as Verilog HDL parameters or VHDL generics are address and data widths and FIFO depths These components have HDL files that are not generated as a function of the parameterization and are referred to as static HDL components SOPC Builder automatically generates the top level HDL wrapper file to apply parameter values for static components Generated HDL Components Alternatively you can also define a component whose HDL is generated based on the value of its declared parameters These components use a custom generation callback to generate the HDL for each use of the component instead of having SOPC Builder create an HDL wrapper that specifies these values An example of a parameter that requires generated HDL is a parameter that controls the number of interfaces Composed HDL Components Composed components are constructed from combinations of other components You can use a compose callback to connect and parameterize a composed component however a custom
189. o Avalon Interface Specifications December 2010 Altera Corporation Chapter 1 Introduction to SOPC Builder 1 3 Architecture of SOPC Builder Systems Example System Figure 1 1 shows an FPGA design that includes an SOPC Builder system and custom logic modules You can integrate custom logic inside or outside the SOPC Builder system In this example the custom component inside the SOPC Builder system communicates with other modules through an Avalon MM master interface The custom logic outside of the SOPC Builder system is connected to the SOPC Builder system through a PIO interface The SOPC Builder system includes two SOPC Builder components with Avalon ST source and sink interfaces The system interconnect fabric connects all of the SOPC Builder components using the Avalon MM or Avalon ST system interconnect as appropriate Figure 1 1 Example of an FPGA with a SOPC Builder System Generated by SOPC Builder Printed Circuit Board System Module Custom Logic System Interconnect Fabric DDR2 Streaming Memory Data Controller Source DDR2 DDR2 ji i i Bus Bridge Memory Co Processor EE NANA AE HM Avalon MM Slave Port Avalon ST Source Port Avalon ST Sink Port December 2010 Altera Corporation SOPC Builder User Guide 1 4 Chapter 1 Introduction to SOPC Builder Architecture of SOPC Builder Systems A component
190. o Table 8 1 1 The sopc builder system ptf file is only required if you intend to edit or view the system in a version of SOPC Builder prior to version 7 1 and must also be writable to generate a system 2 Include all HDL source files not generated by SOPC Builder including HDL source files you create or copy from elsewhere To identify a file generated by SOPC Builder open the file and look for the following header Legal Notice C year Altera Corporation All rights reserved Many source control tools mark local files read only by default In this case you must override this behavior You do not have to check the files out of source control unless you are modifying the SOPC Builder design or Nios II software project SOPC Builder User Guide December 2010 Altera Corporation 9 SOPC Builder Memory Subsystem ANU S RYA Development Walkthrough Most systems generated with SOPC Builder require memory For example embedded processor systems require memory for software while digital signal processing DSP systems require memory for data buffers Many systems use multiple types of memories For example a processor based DSP system can use off chip SDRAM to store software and on chip RAM for fast access to data buffers You can use SOPC Builder to integrate almost any type of memory into your system This chapter uses design examples to describe how to build a memory subsystem as part of a larger system created wi
191. o retrieve This property is propertyName either ENABLED Or ASSOCIATED CLOCK or a property name defined by the interface Example get_interface property mm_slave readWaitTime SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference set_interface_property This command sets a single interface property for an interface 7 35 set_interface_property Callback mere Main and elaboration availability dian uana rau Usage set interface property lt interfaceName gt propertyName value Returns String interfaceName The name of an interface that includes this property The name of the property whose value you want to set which is ENABLED Or Argument N eee ERAS came ais ASSOCIATED CLK or a name from the Avalon Interface Specifications value The value to set for the specified property Example set interface property mm slave linewrapBursts false add interface port This command adds a port to an interface on your module As the component author you determine the name of the port The port width and direction must be set by the end of the elaboration phase The port width can be set with one of the following mechanisms m Aconstant width or a width expression can be set in the main program B A constant width can be set in the elaboration callback Ka Without an elaboration callback for static components quart
192. of the data buffer Because the checksum algorithm operates over a data buffer you can implement it more efficiently with a pipelined read master A pipelined read master continuously posts read transactions minimizing the effects of the memory read latency The checksum accelerator can read data and calculate the checksum result every clock cycle which you cannot do with a general purpose processor The checksum hardware accelerator requires information from a host processor such as the buffer base address buffer length and various control signals As a result the hardware accelerator exposes an Avalon MM slave interface so that a host processor can control the read master operation The host processor also accesses the checksum result from the slave interface Each piece of information sent or read by the host processor is accessed separately in the register file implemented with the slave interface For example the status and control signals are implemented as separate registers because they contain information used for different purposes and have different access capabilities December 2010 Altera Corporation Chapter 10 SOPC Builder Component Development Walkthrough 10 5 Design Example Checksum Hardware Accelerator Hardware accelerators can operate in parallel with a host processor consequently adding an interrupt sender interface to the hardware accelerator increases system performance While the accelerator is operating on a buffer
193. omponent editor to create an SOPC Builder component with your HDL files 4 Instantiate your component in the system Once you have created an SOPC Builder component you can use the component in other SOPC Builder systems and share the component with other design teams T For instructions on developing a custom SOPC Builder component the details about the file structure of a component or the component editor refer to Chapter 4 SOPC Builder Components a For details on the Avalon MM interface refer to Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces For details on the Avalon ST interface refer to Chapter 3 System Interconnect Fabric for Streaming Interfaces SOPC Builder User Guide December 2010 Altera Corporation Chapter 1 Introduction to SOPC Builder 1 5 Functions of SOPC Builder Third Party Components You can also use SOPC ready components that were developed by third parties Altera awards the SOPC Builder Ready certification to IP functions that are ready to integrate with the Nios II embedded processor or the system interconnect fabric via SOPC Builder These cores support the Avalon MM interface or the Avalon Streaming Avalon ST interface and may include constraints software drivers simulation models and reference designs when applicable To find SOPC Builder Ready third party components that you can purchase and use in SOPC Builder systems complete the following steps 1 On the Tools menu in
194. onent SOPC Builder User Guide You can verify the component in incremental stages as you complete more of the design You should first verify the hardware logic as a unit which might consist of multiple smaller stages of verification and later verify the component in a system System Console The system console is an interactive Tcl console available from within SOPC Builder that provides you with read and write access to the debugging capabilities that are available in your FPGA logic You can use the system console to control and query the state of the Nios II processor issue Avalon transactions board bring up and access either JTAG UARTS or system level debug SLD nodes For further details refer to the System Console User Guide System Level Verification After you package a hw tcl file with the component editor you can instantiate the component in a system and verify the functionality of the overall SOPC Builder system SOPC Builder provides support for system level verification for HDL simulators such as ModelSim SOPC Builder automatically produces a test bench for system level verification December 2010 Altera Corporation Chapter 10 SOPC Builder Component Development Walkthrough 10 7 Sharing Components La You can include a Nios II processor in your system to enhance simulation capabilities during the verification phase Even if your component has no relationship to the Nios II processor the auto generated Model
195. or integer_list parameter type the parameter you define is displayed in a variable sized table that includes add and remove buttons December 2010 Altera Corporation SOPC Builder User Guide 1 22 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference m Ifyou define multiple parameters of type string list or integer list you can also use the add display itemcommand to specify that parameters should each be displayed as a column in a table each parameter of type string list or integer list becomes a column in the table Example 7 12 illustrates the use of the integer list parameter types to create a multi column table Example 7 12 Creating Tables Using the string list and integer list Parameter Types add parameter add parameter add parameter add parameter bitsWide INTEGER divider INTEGER coefficients INTEGER LIST S positions INTEGER LIST add display item myTable coefficients TABLE add display item myTable positions TABLE add parameter Ilback a Main program Usage add_parameter lt parameterName gt lt parameterType gt lt defaultValue gt lt description gt Returns String parameterName A name that you the component author choose for your parameter The following types are supported Integer Natural Positive parameterType Boolean Std_logic Std_logic vector String String list and Arguments Integer_list 7 defaultValue The default length of the paramet
196. or pending reads and writes increasing throughput at the expense primarily of on chip memory The clock crossing bridge has parameterizeable FIFOs for master to slave and slave to master signals and allows burst transfers across clock domains The Avalon MM clock crossing bridge component is SOPC Builder ready and integrates easily into any SOPC Builder generated system December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 13 Clock Crossing Bridge Choosing Clock Crossing Methodology When determining clock frequencies for your components you should also consider the impact on the latency that transferring data across clock domains can cause Whether you use a clock crossing bridge or rely on the clock domain adapter created automatically by SOPC Builder additional latency occurs You should also consider the resource usage and throughput capabilities of each solution If you rely on the automatically generated clock crossing adapter to connect master and slave ports driven by separate clock inputs there is a fixed latency penalty associated to each transfer Each transfer becomes blocking meaning that while one transfer is underway another cannot begin until the first completes For this reason you should not connect high speed pipelined components such as SDRAM memory to a master on a different clock domain without using a clock crossing bridge between them The clock crossing bridge on the other hand can queu
197. ose ports you want to list Optional Example get interface ports mm slave get port properties This command returns a list of all available port properties get port properties an Main validation elaboration generation and editor Usage get_port_properties lt portName gt Returns String boolean Or units depending on property refer to Table 7 4 on page 7 23 The name of the port whose properties are required The following 7 port properties are supported m direction m termination Arguments portName m termination value m vhdl type m width m width expr Refer to Table 7 7 for a description of these properties Example get port properties mm slave Table 7 7 describes the available port properties Table 7 7 Port Properties Part 1 of 2 Name Type Description direction S DESEAN The direction of the port from the component s perspective When true instead of connecting the port to the SOPC Builder TEN TT bool system it is left unconnected for OUTPUT and BIDIR or set to a fixed aaa Mace value for INPUT Has no effect for components that implement a generation callback instead of using the default wrapper generation termination value integer The constant value to drive an input port SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 37 Hardware Tcl Command Reference Table 7 7 Port Properties Part 2 of 2
198. ourse Using SOPC Builder m Download and run the checksum sample design described in Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough You may have used SOPC Builder to create systems based on the Nios II processor However SOPC Builder is more than a Nios II system builder it is a general purpose tool for creating systems that may or may not contain a processor and may include a soft processor other than the Nios II processor SOPC Builder automates the task of integrating hardware components Using traditional design methods you must manually write HDL modules to wire together the pieces of the system Using SOPC Builder you specify the system components in a GUI and SOPC Builder generates the interconnect logic automatically SOPC Builder generates HDL files that define all components of the system and a top level HDL file that connects all the components together SOPC Builder generates either Verilog HDL or VHDL equally In addition to its role as a system generation tool SOPC Builder provides features to ease writing software and to accelerate system simulation This chapter includes the following sections m Architecture of SOPC Builder Systems on page 1 1 m Functions of SOPC Builder on page 1 5 m Operating System Support on page 1 8 m Talkback Support on page 1 8 Architecture of SOPC Builder Systems An SOPC Builder component is a design module that SOPC Builder recognizes and can automatically in
199. pcinfo SOPC Builder User Guide December 2010 Altera Corporation N DTE RYN 11 Avalon Memory Mapped Bridges You use bridges to control the topology of the generated SOPC Builder system Bridges are not end points for data but rather affect the way data is transported between components By inserting Avalon MM bridges between masters and slaves you control system topology which in turn affects the interconnect that SOPC Builder generates You can also use bridges to separate components in different clock domains and to implement clock domain crossing logic Manual control of the interconnect can result in higher performance or lower logic utilization or both Altera provides the following Avalon MM bridges m Avalon MM Pipeline Bridge on page 11 8 m Clock Crossing Bridge on page 11 12 m Avalon MM DDR Memory Half Rate Bridge on page 11 20 St For additional information on using bridges to optimize and control the topology of SOPC Builder systems refer to Avalon Memory Mapped Design Optimizations in the Embedded Design Handbook December 2010 Altera Corporation SOPC Builder User Guide 11 2 Chapter 11 Avalon Memory Mapped Bridges Structure of a Bridge Structure of a Bridge A bridge has one Avalon MM slave and one Avalon MM master as shown in Figure 11 1 In an SOPC Builder system one or more masters connect to the bridge slave in turn the Avalon MM bridge master connects to one or more slaves In Figure 11 1 a
200. pment Walkthrough Design Example Checksum Hardware Accelerator Figure 10 1 shows the top level blocks of a checksum component which includes both Avalon MM master and slaves The work flow for developing SOPC Builder hardware including how to decide upon and implement the register map is described in the Using the Nios II Software Build Tools chapter in the Nios II Software Developer s Handbook Also guidelines for developing device drivers is described in the Developing Device Drivers for the Hardware Abstraction Layer chapter of the Nios II Software Developer s Handbook Design Example Checksum Hardware Accelerator SOPC Builder User Guide Altera has provided a checksum hardware accelerator design example to demonstrate the steps to create a component and instantiate it in a system This design example is available for download from the Altera literature website Included in the compressed download file is a readme pdf that describes how to create and compile the hardware design and describes how to use the checksum hardware accelerator in your design You can use the checksum algorithm in network applications where data integrity must be inspected by the receiving device The checksum algorithm accumulates data with end round carry summation which means that the carry bit from the accumulator is added to the least significant bit of the next input After the data is accumulated you can use the result to verify the data integrity
201. pment sequence for an SOPC Builder component includes the following items 1 Specification and definition a Define the functionality of the component b Determine component interfaces such as Avalon Memory Mapped Avalon MM Avalon Streaming Avalon ST interrupt or other interfaces c Determine the component clocking requirements what interfaces are synchronous to what clock inputs d If you want a microprocessor to control the component determine the interface to software such as the register map 2 Implement the component in VHDL or Verilog HDL SOPC Builder User Guide December 2010 Altera Corporation Chapter 10 SOPC Builder Component Development Walkthrough 10 3 Component Development Flow 3 Import the component into SOPC Builder a Use the component editor to create a hw tcl file that describes the component b Instantiate the component into an SOPC Builder system When importing an HDL file using the component editor any parameter definitions that are dependent upon other defined parameters cause an error Example 10 1 illustrates the declaration of a DEPTH parameter which is legal Verilog HDL syntax in the Quartus II software but causes an error in the component editor syntax checker Example 10 1 DEPTH Parameter parameter WIDTH parameter DEPTH 32 WIDTH 32 8 16 To avoid this error use a localparam for the dependent parameter instead as shown in Example 10 2 Example 10 2 lo
202. ports is configurable which affects the size of the bridge hardware and how SOPC Builder generates dynamic bus sizing logic in the system interconnect fabric Both ports support Avalon MM pipelined transfers with variable latency Both ports optionally support bursts of user configurable length Ideally the settings for one port match the other such that there are no mixed data widths or bursting capabilities Clock Crossing Bridge and FIFOs Two FIFOs in the bridge transport address data and control signals across the clock domains One FIFO captures data and controls traveling in the master to slave direction and the other FIFO captures data in the slave to master direction Clock crossing logic surrounding the FIFOs coordinates the details of passing data across the clock domain boundaries and ensures that the FIFOs do not overflow or underflow The signals that pass through the master to slave FIFO include E writedata E address E read E write E byteenable WB burstcount when bursting is enabled The signals that pass through the slave to master FIFO include E readdata E readdatavalid You can configure the depth of each FIFO Because there are more signals traveling in the master to slave direction changing the depth of the master to slave FIFO has a greater impact on the memory utilization of the bridge For read transfers across the bridge the FIFOs in both directions incur latency for data to return from the slave To
203. put m Use the create base clocks option of the derive pll clock assignments to designate the base clock feeding the PLL The following example focuses on the use of the derive pll clocks assignment because this method automatically defines clock frequencies and phase shifts derive pll clocks generates clocks for all PLLs in the Quartus II hardware project not just for the PLLs in the SOPC Builder system December 2010 Altera Corporation Chapter 5 Using SOPC Builder with the Quartus Il Software 5 3 TimeQuest Timing Analyzer The SOPC system shown in Figure 5 1 illustrates the use of the derive pll clocks assignment in the case of a single clock input and one PLL using a single output Figure 5 1 Example SOPC System Tem Clock Settings Device Family Cyclone Ill v Name Source MHz Pipeline Add clk External 50 0 O my pli c my pll c 12 5 o Use Module Name Description Clock Base End v E my master master avalon_master_0 Avalon Master clk v E my pil PLL I s1 amp valon Slave clk 0x00000000 Ox0000001f ll v El pio PIO Parallel l O 1 amp valon Slave my pll c 0x00000020 0xoO00002f lt a v Address Map After running the following commands in the TimeQuest Timing Analyzer two clocks are generated create clock name master clk period 20 get ports clk derive pll clocks The TimeQuest Timing Analyzer analyzes and reports performance of the con
204. r in the system Figure 2 4 Block Diagram of Datapath Multiplexing Logic readdata1 address Data Path Multiplexer readdata writedata control readdata2 In SOPC Builder the generation of datapath multiplexing logic is specified using the connections panel on the System Contents tab Wait State Insertion Wait states extend the duration of a transfer by one or more cycles Wait state insertion logic accommodates the timing needs of each slave and causes the master to wait until the slave can proceed System interconnect fabric inserts wait states into a transfer when the target slave cannot respond in a single clock cycle System interconnect fabric also inserts wait states in cases when slave read_enable and write enable signals have setup or hold time requirements Wait state insertion logic is a small finite state machine that translates control signal sequencing between the slave side and the master side Figure 2 5 shows a block diagram of the wait state insertion logic between one master and one slave Figure 2 5 Block Diagram of Wait State Insertion Logic Wait State Insertion Logic read write read write wait request Slave address Port System interconnect fabric can force a master to wait for several reasons in addition to the wait state needs of a slave For example arbitration logic in a multimaster system can force a master to wait until
205. rate and you use the additional arguments to specify things such as which clock input interface you require Example 7 3 illustrates the use of the SYSTEM INFO parameter For more information about the SYSTEM INFO parameter properties refer to Table 7 5 on page 7 26 Example 7 3 Syntax of Tcl Command using the SYSTEM INFO Parameter set parameter property my parameter SYSTEM INFO lt info type gt arg SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 1 5 Writing a Hardware Component Description File Declaring Interfaces To declare an interface use the add interface command Then use the set interface property and add interface port commands to set its properties and indicate which signals belong to it The interface declaration statement includes the name of the interface the interface direction and the clock interface with which it is associated For interfaces that are not associated with clocks such as clock interfaces themselves omit the associated clock interface or use the word asynchronous Example 7 4 illustrates interface declaration Example 7 4 Declare Interfaces Declare the clock sink interface clock sink type clock direction sink add interface clock sink clock sink The clock interface has two signals named clk and reset n of types clk reset n add interface port clock sink clk clk input 1 add interface port clock sink reset
206. rdware Tcl Command Reference Table 7 5 lists the properties that you can use with the system info parameter property Table 7 5 SYSTEM INFO Properties Part 1 of 2 Property ADDRESS MAP Type String Description Assigns an XML formatted string describing the address map to the parameter you specify Set parameter property my parameter SYSTEM INFO ADDRESS MAP my avalon mm master ADDRESS WIDTH Integer Assigns an integer to the parameter that you specify that is the number of bits an Avalon MM master must drive to address all of its slaves using byte addresses Set parameter property my parameter SYSTEM INFO ADDRESS WIDTH my avalon mm master CLOCK DOMAIN Integer Assigns an integer representing the clock domain to the parameter you specify You can use this command to determine whether multiple interfaces in your module are on the same clock domain The absolute value of the integer value is arbitrary but if two interfaces are on the same clock domain the CLOCK_DOMAIN value is guaranteed to be the same and greater than zero set parameter property mmy parameter SYSTEM INFO CLOCK DOMAIN my clk CLOCK RATE Integer Ol String Assigns a positive number which is the clock frequency in Hz to the clock input interface you specify Assigns 0 if the clock rate is not known set parameter property my parameter SYSTEM INFO CLOCK RATE my clk DEVICE FAMIL
207. ready instantiated This example design uses the default settings for the Nios II core and the JTAG UART core these settings do not affect the rest of the memory subsystem Hardware and Software Requirements To build a memory subsystem similar to the example design in this chapter you need the following tools m Quartus II software version 5 0 or higher Both Quartus II Web Edition and the fully licensed version support this design flow m Nios II Embedded Design Suite EDS version 5 0 or higher Both the evaluation edition and the fully licensed version support this design flow The Nios II EDS provides the SOPC Builder memory components described in this chapter It also provides several complete example designs which demonstrate a variety of memory components instantiated in working systems The Quartus II Web Edition software and the Nios II EDS Evaluation Edition are available free for download from the Altera website Visit www altera com download Also for further reference see the Design Examples This chapter does not describe downloading and verifying a working system in hardware Therefore there are no hardware requirements for the completion of this chapter However the example memory subsystem has been tested in hardware December 2010 Altera Corporation SOPC Builder User Guide Design Flow Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Design Flow This section describes the design flow for
208. rface Tcl Reference You define SOPC Builder components by declaring their properties and behaviors ina Hardware Component Description File hw tcl Each hw tcl file represents one component instance which you can add to an SOPC Builder system You can also share the components that you design with other designers For your component to have maximum flexibility you should consider what aspects of its behavior can be parameterized so that other users can change the default parameterization to address different design requirements An SOPC Builder component is usually composed of the following four types of files gm hw tcl file describes the SOPC Builder related characteristics such as interface behaviors This file is required m HDL files define the component s functionality as hardware These files are optional m sw tcl used by the software build tools to compile the component driver code This file is optional m Component driver files defines the component register map and driver software to allow software to control the component These files are optional This chapter discusses the following topics Information in a Hardware Component Description File Component Phases on page 7 2 m Writing a Hardware Component Description File on page 7 2 m Overriding Default Behaviors on page 7 8 Hardware Tcl Command Reference on page 7 12 Information in a Hardware Component Description File A typic
209. rmance but also adds latency cycles when reading the memory The Read latency option allows you to specify either one or two cycles of read latency required to access data If the Dual port access setting is turned on you can specify a different read latency for each slave When you have dual port memory in your system you can specify different clock frequencies for the ports You specify this on the System Contents tab in SOPC Builder Non Default Memory Initialization For ROM memories you can specify your own initialization file by selecting Enable non default initialization file This option allows the file you specify to be used to initialize the ROM in place of the default initialization file created by SOPC Builder Enable In System Memory Content Editor Feature Enables a JTAG interface used to read and write to the RAM while it is operating You can use this interface to update or read the contents of the memory from your host PC For more information refer to In System Updating of Memory and Constants in volume 3 of the Quartus II Handbook December 2010 Altera Corporation SOPC Builder User Guide 9 8 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough On Chip RAM and ROM SOPC Builder System Level Design for On Chip Memory There are few SOPC Builder system level design considerations for on chip memories See SOPC Builder System Level Design on page 9 4 When generating a new system SOPC Builder creates
210. s Figure 2 11 Arhitration of Two Masters with a Gap in Transfer Requests ck 1 1 1 1 1 1 M1 transfer request y l l l l l l l l l l l l l l l M1_waitrequest l J M2_transfer_request J l l P T T l M2_waitrequest i wooo aoa dd i T Current_Master X Master 1 Jose Master 1 Y Master 2 y Master 1 Y Master 2 Round Robin Scheduling When multiple masters contend for access to a slave the arbiter grants shares in round robin order Round robin scheduling drives a request interface according to space available and data available credit interfaces At every slave transfer only requesting masters are included in the arbitration December 2010 Altera Corporation SOPC Builder User Guide 2 14 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Burst Adapters Burst Transfers Avalon MM burst transfers grant a master uninterrupted access to a slave for a specified number of transfers The master specifies the number of transfers when it initiates the burst Once a burst begins between a master slave pair arbiter logic does not allow any other master to access the slave until the burst completes For burst masters the size of the burs
211. s a single value or a range of values defined by a start and end value separated by a colon String such as 11 15 This property can also specify legal ALLOWED RANGES Main program values and display strings for integers such as 0 None 1 Monophonic 2 Stereo 4 Quadrophonic meaning 0 1 2 4 are the legal values You can also assign longer strings to be displayed in the GUI to string variables For example ALLOWED RANGES devi Cyclone IV GX dev2 Stratix V GT Refer to Example 7 7 on page 7 8 and Figure 7 1 on page 7 8 for additional examples illustrating the use of this property DERIVED Boolean false Main program When true indicates that the parameter value does not need to be stored typically because it is set from the validation callback The default value is false DESCRIPTION String Main program A user visible description of the parameter DISPLAY_HINT String Main program Provides a hint about how to display a property The following values are possible m boolean for integer parameters whose value can be 0 or 1 The parameter displays as a checkbox m radio displays a parameter with a list of values as radio buttons instead of a drop down list m hexadecimal for integer parameters display and interpret the value as a hexadecimal number for example 0x00000010 instead of 16 m fixed size f0r string list and integer list parameters the ixed size DISPLAY HINT elimin
212. s for all possible Avalon MM data widths Table 9 1 Connecting the Least Significant Avalon MM Address Line Address Line Connecting to Memory Device Avalon MM Address Line 8 bit Memory 16 bit Memory 32 bit Memory 64 bit Memory 128 bit Memory address 0 A0 No connect No connect No connect No connect address 1 Al A0 No connect No connect No connect address 2 A2 Al A0 No connect No connect address 3 A3 A2 A1 AO No connect address 4 A4 A3 A2 A1 AO address 5 A5 A4 A3 A2 A1 address 6 A6 A5 A4 A3 A2 address 7 A7 A6 A5 A4 A3 address 8 A8 A7 A6 A5 A4 address 9 A9 A8 A7 A6 A5 address 10 A10 A9 A8 A7 A6 CAUTION You must ensure that the address bits are properly assigned when mixed width components are connecting to the tristate bridge Failing to ensure that the components are properly aligned may result in a board respin December 2010 Altera Corporation SOPC Builder User Guide 9 20 Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory Aligning the Most Significant Address Bits The Avalon MM address signal contains enough address lines for the largest memory connected to the tristate bridge Smaller off chip memories might not use all of the most significant address lines as Figure 9 7 illustrates Figure 9 7 Connecting a Tristate Bridge to Components with Different Address Widths and Word Sizes
213. se cycle control With the use of system clock I O transactions are possible on every clock cycle Operating over a range of frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications T For further details about the features and usage of the SDR SDRAM controller core refer to the SDR SDRAM Controller Core with Avalon Interface chapter in the Embedded Peripherals IP User Guide Component Level Design for SDRAM The choice of SDRAM device s and the configuration of the device s on the board heavily influence the component level design for the SDRAM controller Typically the component level design task involves parameterizing the SDRAM controller core to match the SDRAM device s on the board You must specify the structure address width data width number of devices number of banks and so on and the timing specifications of the device s on the board St Forcomplete details about configuration options for the SDRAM controller core refer to the SDRAM Controller Core chapter in the Embedded Peripherals IP User Guide SOPC Builder System Level Design for SDRAM You can select the SDRAM controller in the SOPC Builder System Contents tab Like the on chip memory there are few SOPC Builder system level design considerations for SDRAM Refer to SOPC Builder System Level Design on page 9 4 Simulation for SDRAM At system generation time SOPC
214. signed to receive single word requests it does not support bursting Figure 11 14 shows a system including an 8 bit DDR memory a high performance memory controller the Half Rate DDR Bridge and a CPU Figure 11 14 SOPC Builder Memory System Using a DDR Memory Half Rate Bridge PCB DDR2 3 High Performance Half Rate Controller Bridge full rate DDR Clk Karaman gt Controller Clk lt gt Controller Clk 2 burst count 4 burst count 2 burst count 1 The Avalon MM DDR Memory Half Rate Bridge core has the following features and requirements m SOPC Builder ready with TimeQuest Timing Analyzer constraints Requires master clock and slave clock to be synchronous Handles different bus sizes between CPU and memory Requires the frequency of the master clock to be double of the slave clock Has configurable address and data port widths in the master interface Resource Usage and Performance This section lists the resource usage and performance data for supported devices when operating the Half Rate Bridge with a full rate DDR SDRAM high performance memory controller December 2010 Altera Corporation SOPC Builder User Guide 11 22 Chapter 11 Avalon Memory Mapped Bridges Avalon MM DDR Memory Half Rate Bridge Using the Half Rate Bridge with a full rate DDR SDRAM high performance memory controller results an average of 48 performance improvement over a system using a half rate DDR SDRA
215. space separated list get_interface_properties sore Main program validation elaborations and editor Usage get interface properties lt interfaceName gt Returns List of strings Arguments interfaceName The name of an interface that you defined Example get interface properties mm slave T The properties available for each interface type are different Refer to the Avalon Interface Specifications for more information about interface properties The interface properties that are common to all interface types are listed below in Table 7 6 Table 7 6 Interface Properties Common to All Interface Types Property ENABLED ASSOCIATED CLOCK String Boolean Type Description The name of the clock interface that this interface is synchronous to Specifies whether or not interface is enabled get interface property This command returns the value of a single interface property from the specified interface get interface property Ilback Ca paci l Main program and elaboration availability Usage get_interface_property lt interfaceName gt lt propertyName gt Returns string boolean Of units depending on property Refer to the Avalon Interface Specifications for more information about interface properties interfaceName The name of an interface from which you want to retrieve information Arguments The name of the property whose value you want t
216. splay Items add display item groupName id type additionalInfo page 7 29 GET DISPLAY ITEMS page 7 31 GET DISPLAY ITEM properties page 7 31 GET DISPLAY ITEM PROPERTY itemName propertyName page 7 31 set display item PROPERTY itemName propertyName value page 7 31 Interfaces and Ports add interface lt interfaceName gt interfaceType direction lt associatedCl ock gt PAS SOPC Builder User Guide 7 14 Table 7 2 Command Summary Note 1 Part 2 of 2 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference Command Full Description get interfaces lt interfaceName gt page 7 33 get interface property interfaceName propertyName page 7 34 set interface property lt interfaceName gt propertyName value page 7 35 add interface port interfaceName portName lt portRole gt direction width expr page 7 35 get interface ports lt interfaceName gt page 7 36 get port properties page 7 36 get port property portName propertyName page 7 37 set port property portName propertyName lt value gt page 7 37 get interface assignments page 7 38 get interface assignment interfaceName name page 7 38 set interface assignmet lt interfaceName gt name value page 7 38 Generation get generation property propertyName page 7 39 get generation properties page 7 39 Note
217. stem includes three CPUs a DDR SDRAM controller a message buffer RAM a message buffer mutex and a tristate bridge to an external SRAM Figure 11 2 Example System Without Bridges SOPC Builder View Use Connections Module Name Description Base Iv E cpu1 Nios Il Processor instruction master Avalon Master data_master Avalon Master IRQ 0 jtag_debug_module Avalon Slave 0x02002800 iv E cpu2 Nios Il Processor instruction master Avalon Master data_master Avalon Master IRQ 0 jtag_debug_module Avalon Slave 0x00000800 Iv E cpu3 Nios Il Processor instruction master Avalon Master data_master Avalon Master IRQ 0 jtag_debug_module Avalon Slave 0x00001000 Iv DDR SDRAM controller DDR SDRAM High Performance Control s1 Avalon Slave 0x01000000 Iv E message buffer RAM On Chip Memory RAM or ROM s1 Avalon Slave 0x02001000 Iv E message buffer mutex Mutex st Avalon Slave 0x02003000 Iv E external SSRAM bus Avalon MM Tristate Bridge avalon_slave Avalon Slave 0x00000000 tristate master Avalon Tristate Master Iv E external SSRAM Cypress CY7C1380C SSRAM s1 Avalon Tristate Slave Oxffffffff December 2010 Altera Corporation SOPC Builder User Guide 11 4 Chapter 11 Avalon Memory Mapped Bridges Structure of a Bridge Figure 11 3 illustrates the default system interconnect fabric for the system in Figure 11 2 Figure 11 3 Example System without Bridges System Interconnect View
218. ster Systems 6666 eens 2 9 Traditional Shared Bus Architectures seieren rerneriekienskit issie n tien pr eee 2 9 Slave Side Arbitration Cereri edidi eh See das Le ER oen Pede 2 10 Arbiter Detalls qe E m 2 11 Arbitration Rules dtes ba pue t e dd videte wi edo PU EH deci 2 12 Burst Adapters Sende rede Pete dede da ede inet eei fe ieee S edite ers reed dead icio 2 14 liuscql M D E 2 15 Individual Requests IRQ Scheme lsssssssesssseeeeeeee eee 2 15 Priority Encoded Interrupt Scheme sssssseeseesseeeee nee eee 2 15 Assigning IRQs in SOPC Builder nsss ts iiem miin ede nen eens 2 16 Reset Distrib tioti osse Edd seeker tedden b edie EH Pa Pete oa det ede td 2 16 Chapter 3 System Interconnect Fabric for Streaming Interfaces High Level Description i4 extent etel on ee espe E o P lend pee pend iren eed geste 3 1 Avalon Streaming and Avalon Memory Mapped Interfaces llsslseeeeeeeeeeee 3 2 XLI Rr 3 3 Data Format Adapter 4 veieeenee tia Rr pp ee eee tar den ee ak 3 4 Timing Adapter ceerd eere ee Pere pae eir ld met glane e e bae edant Rebate 3 4 Channel Adapter iiec iere d ente eoe ee PAL Ce d eee de Pee Pepe teorie dence 3 5 Error Adapter 5 ie hse thie 3 5 Multiplexer Examples 54 recep etae iinei a dank ahaa ded dude eee d ee Rd ee es 3 5 Example to Double Clock Frequency ssssse cece cece eee 3 6 Example to Double Data Width and Maintain Frequ
219. strained clocks in the Clocks Summary report This displays a report as shown in Figure 5 2 Figure 5 2 Clocks Summary Report Clocks Summary n 1 master clk Base 20 000 the my pllithe plllaltpll componentlauto generatedipll IcIk 0 Generated 80 000 master clkis defined by the create clock command and the my p11 clock is derived from the derive pll clocks command Analyzing Slow Asynchronous 1 0 Paths If you use slow asynchronous I O in an SOPC Builder system such as PIO and UART peripherals you do not have to analyze these paths because they are asynchronous to the clock that is used to capture or output data In this case you must designate false paths to produce an accurate analysis For outputs set a false path between the launch clock and the output For inputs a false path should be set between the input and the latching clock For bidirectional signals set a false path from the launching clock to the bidirectional pin and also from the bidirectional pin to the latching clock Launch and latch clocks are typically the clocks associated with the SOPC Builder module that includes the I O December 2010 Altera Corporation SOPC Builder User Guide Chapter 5 Using SOPC Builder with the Quartus Il Software TimeQuest Timing Analyzer For the system described in the PLL section the following command sets false paths for the PLL outputs set false path to get ports piol Becaus
220. system with top level I O signals associated with the tristate bridge and the memory interface components In the Quartus II project you must connect the I O signals to FPGA pins which connect to the memory devices on the board After generating the system with SOPC Builder you can find the names and directions of the I O signals in the top level HDL file for the SOPC Builder system The file has the name lt Quartus II project directory gt lt SOPC Builder system name gt v or lt Quartus II project directory gt lt SOPC Builder system name gt vhd You must connect these signals in the top level Quartus II design file You must assign a pin location for each I O signal in the top level Quartus II design to match the target board Depending on the performance requirements for the design you might have to assign FPGA pins carefully to achieve timing SOPC Builder inserts synthesis directives in the top level SOPC Builder system HDL to assist the Quartus II fitter with signals that interface with off chip devices Example 9 2 illustrates a directive Using FAST OUTPUT REGISTER ON places the output register in the IO block reducing the off chip delay For more information about improving IO timing refer to the I O Specifications section in The Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook and the Assignment Editor chapter in volume 2 of the Quartus II Handbook Example 9 2 Synthesis Directive reg
221. t determines the number of cycles that the master has access to the slave and the selected arbitration shares have no effect Burst Adapters SOPC Builder User Guide System interconnect fabric provides burst adaptation logic to accommodate the burst capabilities of each port in the system including ports that do not support burst transfers Burst adaptation logic consists of a finite state machine that translates the sequencing of address and control signals between the slave side and the master side The maximum burst length for each port is determined by the component design and is independent of other ports in the system Therefore a particular master might be capable of initiating a burst longer than a slave s maximum supported burst length In this case the burst management logic translates the master burst into smaller slave bursts or into individual slave transfers if the slave does not support bursts Until the master completes the burst the arbiter logic prevents other masters from accessing the target slave For example if a master initiates a burst of 16 transfers to a slave with maximum burst length of 8 the burst adapter logic initiates two bursts of length 8 to the slave If the master initiates a burst of 14 the burst adapter logic segments the burst transfer into a burst of 8 words followed by a burst of 6 words because the slave can only handle a maximum burst length of 8 If a master initiates a burst of 16 transfers to
222. t use the Avalon Memory Mapped Avalon MM interface The system interconnect fabric consumes less logic provides greater flexibility and higher throughput than a typical shared system bus It is a cross connect fabric and not a tristated or time domain multiplexed bus This chapter describes the functions of system interconnect fabric for memory mapped interfaces and the implementation of those functions High Level Description The system interconnect fabric is the collection of interconnect and logic resources that connects Avalon MM master and slaves on components in a system SOPC Builder generates the system interconnect fabric to match the needs of the components in a system The system interconnect fabric implements the connection details of a system It guarantees that signals are routed correctly between master and slaves as long as the ports adhere to the rules of the Avalon Interface Specifications This chapter provides information on the following topics Address Decoding on page 2 3 Datapath Multiplexing on page 2 4 Wait State Insertion on page 2 5 Pipelined Read Transfers on page 2 6 7 m m m m Dynamic Bus Sizing and Native Address Alignment on page 2 6 m Arbitration for Multimaster Systems on page 2 9 m Burst Adapters on page 2 14 m Interrupts on page 2 15 u Reset Distribution on page 2 16 For details about the Avalon MM interface refer to the Avalon Interface Specifications System
223. ted to the specified Avalon MM master nteger Set parameter property my parameter SYSTEM INFO MAX SLAVE DATA WIDTH my avalon mm master Assigns an integer representing the reset domain to the parameter you specify You can use this command to determine whether multiple interfaces in your module are on the same reset domain The absolute RESET DOMAIN value of the integer value is arbitrary but if two interfaces are on the same Integer reset domain the RESET DOMAIN value is guaranteed to be the same and greater than zero set parameter property my parameter SYSTEM INFO RESET DOMAIN my reset get parameter property This command returns a single parameter property get parameter property Mes Main validation elaboration generation and editor Usage get parameter property parameterName propertyName Returns string boolean Or units depending on property refer to Table 7 4 on page 7 23 Arguments parameterName The name of the parameter whose property value is being retrieved propertyName One of the properties listed in Table 7 4 on page 7 23 Example get parameter property parameterl GROUP set parameter property This command sets a single parameter property set parameter property Mer Main validation and elaboration Usage set parameter property parameterName propertyName value Returns string boolean Or u
224. tegrate into a system You can also define and add custom components or select from a list of provided components SOPC Builder connects multiple modules together to create a top level HDL file called the SOPC Builder system SOPC Builder generates system interconnect fabric that contains logic to manage the connectivity of all modules in the system December 2010 Altera Corporation SOPC Builder User Guide Chapter 1 Introduction to SOPC Builder Architecture of SOPC Builder Systems SOPC Builder Modules Ls SOPC Builder User Guide This document refers to components as the class definition for a module for example a Nios II processor An instance is a parameterization of a component that s been added to a system for example cpu_0 SOPC Builder modules are the building blocks for creating an SOPC Builder system SOPC Builder modules use Avalon interfaces such as memory mapped streaming and IRQ for the physical connection of components You can use SOPC Builder to connect any logical device either on chip or off chip that has an Avalon interface There are different types of Avalon interfaces as described in the Avalon Interface Specifications For details on the Avalon MM interface refer to Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces For details on the Avalon ST interface refer to Chapter 3 System Interconnect Fabric for Streaming Interfaces For details about the Avalon ST interface protocol refer t
225. tem see Example Design with SRAM and Flash Memory on page 9 20 SRAM To instantiate an interface to off chip SRAM 1 Create anew component with the SOPC Builder component editor that defines the interface 2 Instantiate the new interface component in the SOPC Builder system The choice of RAM devices and the configuration of the devices on the board determine how you create the interface component The component level design task involves entering parameters into the component editor to match the devices on the board For details about using the component editor refer to Chapter 6 Component Editor SOPC Builder System Level Design for SRAM and Flash Memory In the SOPC Builder System Contents tab the Avalon MM tristate bridge has two ports m Avalon MM slave This port faces the on chip logic in the SOPC Builder system You connect this slave to on chip masters in the system m Avalon MM tristate master This port faces the off chip memory devices You connect this master to the Avalon MM tristate slaves on the interface components for off chip memories You assign a clock to the Avalon MM tristate bridge that determines the Avalon MM clock cycle time for off chip devices connected to the tristate bridge You must assign base addresses to each off chip memory The Avalon MM tristate bridge does not have an address it passes unmodified addresses from on chip masters to off chip slaves Simulation for SRAM and Flash
226. ters Declare Baud Rate parameter as an integer with a default value of 9600 add parameter BAUD RATE int 9600 Display this parameter as Baud Rate in the Parameter Editor Set parameter property BAUD RATE DISPLAY NAME Baud Rate bps We only support three baud rates set parameter property BAUD RATE ALLOWED RANGES 9600 19200 38400 December 2010 Altera Corporation SOPC Builder User Guide 7 4 Chapter 7 Component Interface Tcl Reference Writing a Hardware Component Description File Parameters can be divided into three types user parameters system information parameters and derived parameters The following sections describe these parameter types User Parameters User parameters are parameters that users have control over and that are exposed in the component GUI Derived Parameters Derived parameters are parameters that are inferred by the component itself from user parameters or other derived parameters For example a clock period parameter can be derived from a data rate parameter SYSTEM_INFO Parameters You can use SYSTEM_INFO parameter to request that certain parameter values are populated with information about the system For example you might want to know the frequency of the clock that ends up being connected to your clock input When you declare SYSTEM_INFO properties you provide an lt info type gt and further arguments The lt info type gt is the type of information you want such as clock_
227. th SOPC Builder This chapter focuses on the following kinds of memory most commonly used in SOPC Builder systems m On Chip RAM and ROM on page 9 6 EPCS Serial Configuration Device on page 9 9 SDR SDRAM on page 9 11 DDR SDRAM on page 9 14 DDR2 SDRAM on page 9 14 m Off Chip SRAM and Flash Memory on page 9 15 This chapter assumes that you are familiar with the following task and concepts m Creating FPGA designs and making pin assignments with the Quartus II software For details refer to the Introduction to the Quartus II Software manual m Building simple systems with SOPC Builder For details refer to Chapter 1 Introduction to SOPC Builder m SOPC Builder components For details refer to Chapter 4 SOPC Builder Components m Basic concepts of the Avalon interfaces You do not need extensive knowledge of the Avalon interfaces such as transfer types or signal timing However to create your own custom memory subsystem with external memories you need to understand the Avalon Memory Mapped Avalon MM interface For details refer to Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces and the Avalon Interface Specifications Ta Refer to the Memory System Design chapter in the Embedded Design Handbook for additional information on the efficient use of memories in SOPC Builder systems Example Design This chapter demonstrates the process for building a system that contains one of ea
228. that are required to define your component including the _hw tcl file and synthesis and simulation files using the Add button on the HDL Files tab You use the Signals tab to specify the purpose of each signal on the top level component module If you specified a file on the HDL Files tab the signals on the top level module appear on the Signals tab The Interface list also allows creation of a new interface so that you can assign a signal to a different interface without first switching to the Interfaces tab Each signal must belong to an interface and be assigned a legal signal type for that interface In addition to Avalon Memory Mapped and Streaming interfaces components typically have clock interfaces interrupt interfaces and perhaps a conduit interface for exported signals December 2010 Altera Corporation SOPC Builder User Guide Chapter 6 Component Editor Naming Signals for Automatic Type and Interface Recognition The component editor recognizes signal types and interfaces based on the names of signals in the source HDL file if they conform to the following naming conventions SOPC Builder User Guide Signals Tab Signal associated with a specific interface lt interface type gt _ lt interface name gt _ lt signal type gt _n For any value of lt interface_name gt the component editor automatically creates an interface by that name if necessary and assigns the signal to it The lt signal_type gt must match one o
229. the creation of the sdram clk pin generated clock derived from the output pin sdram_clk clock A 0 5 ns offset accounts for PCB routing delay December 2010 Altera Corporation Chapter 5 Using SOPC Builder with the Quartus Il Software TimeQuest Timing Analyzer 5 5 create_generated_clock name sdram_clk pin source sdram_clk offset 0 5 get_ports sdram_clk There may be some uncertainty associated with the PCB delay not accounted for in this command The uncertainty can be included in the I O constraints that are specific to input or output and minimum or maximum delays The I O constraints must be defined in relation to the data sheet for the external memory Figure 5 4 shows part of a data sheet for an SDRAM device with the worst case input and output timing highlighted for a CAS latency of 3 Figure 5 4 AC Characteristics from SDRAM Device Data sheet AC Characteristics Parameter Access time from CLK pos edge CL 2 TAC 2 7 5 cL 1 TAC 1 17 Address hold time AH 1 1 Address setup time TAS 1 5 2 CLK high level width CH 2 5 2 75 CLK low level width CL 2 5 2 75 Clock cycle time cL 3 CK 3 6 7 cL 2 CK 2 10 10 cL 1 CK 1 20 20 CKE hold time CKH 1 1 CKE setup time CKS 1 5 2 CS RAS CAS WE DOM hold time CMH 1 1 CS RAS CAS WE DOM setup time CMS 1 5 2 Data in hold time
230. the number of cycles between when the ready signal is asserted and when valid data is driven Include valid signal Turn this option on if the interface includes the valid signal Turning this option off means that data driven is always valid Common to Input and Output Interfaces Type the width of the channel signal A channel width of 4 allows up to Channel Signal Width bits 16 channels The maximum width of the channel signal is eight bits Set to 0 if channels are not used SOPC Builder User Guide December 2010 Altera Corporation Chapter 12 Avalon Streaming Interconnect Components 12 5 Data Format Adapter Table 12 3 Avalon ST Timing Adapter Parameters Input Interface Parameters Parameter Max Channel Type the maximum number of channels that the interface supports Valid Description values are 0 255 Data Bits Per Symbol Type the number of bits per symbol Data Symbols Per Beat Type the number of symbols per active transfer Include Packet Support Turn this option on if the interfaces supports a packet protocol including the startofpacket endofpacket and empty signals Include Empty Signal You can use this signal to specify the number of empty symbols in the cycle that includes the endofpacket signal This signal is not necessary if the number of symbols per beat is 1 Error Signal Width Bits Error Signal Description Type the width of the
231. ther information on how to convert older FPGA centric constraints into system centric constraints refer to Switching to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook SOPC Builder User Guide December 2010 Altera Corporation Chapter 5 Using SOPC Builder with the Quartus Il Software 5 7 TimeQuest Timing Analyzer Analyzing DDR and DDR2 Memories When using DDR DDR2 or DDR3 memory with Cyclone III Stratix III and Stratix IV families you must use the corresponding High Performance Controller MegaCore function You can use the MegaWizard Plug In Manager interface to parameterize these functions and generate timing constraints in the form of sdc files You must ensure that the constraints file associated with the MegaCore function is included in the project for timing analysis You can add an sdc file to the project by clicking Add Remove Files in Project on the Project menu in the Quartus II software As these MegaCore functions make use of the derive pll clocks command conflicts may occur if your sdc file also uses these constraints For more design examples refer to TimeQuest Design Examples on www altera com Also AN 433 Constraining and Analyzing Source Synchronous Interfaces describes source synchronous constraints for the TimeQuest Timing Analyzer December 2010 Altera Corporation SOPC Builder User Guide 5 8 Chapter 5 Using SOPC Builder with the Quartus Il Software TimeQuest
232. to Table 7 2 1 Arguments enclosed in s are optional Module Definition This section provides information about the commands that you use to define and query a module package The package command allows you to specify a particular version of the SOPC Builder software to avoid software compatibility issues You should use the package command at the beginning of your _hw tcl file When used the component files behave as if they are interpreted by the version of the SOPC Builder software that you specify When the package command is not used version 9 0 of the SOPC Builder software is assumed For components designed before 9 0 you can set the required package to 9 0 This document describes the behavior of component which start with package require exact sopc 10 0 For earlier releases refer to the documentation for that release package is a standard Tcl command For more information on this command refer to the following web page http www tcl tk man tcl8 0 TclCmd package htm package Callback availability Main before any other commands in the file Usage package require exact sopc Version Returns None SOPC Builder User Guide December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference 7 15 package Arguments version The version of SOPC Builder that you require specified as decimal number Example package req
233. to analyze the HDL file or set them in an elaboration callback The syntax for width expressions is the same as the HDL language that you use however only the addition subtraction December 2010 Altera Corporation Chapter 7 Component Interface Tcl Reference 7 7 Default Behaviors multiplication and division operators are allowed For more complex port widths the width of the port can be set as an arbitrary function of the component s parameters in an elaboration callback The width expression is the last argument to the add interface port command Example 7 6 illustrates the use of mathematical operators and the width expr property Example 7 6 Defining Port Widths Using Simple Mathematical Operators add interface port din din data data input WIDTH SYMBOLS Set port property din data width expr WIDTH Parameterized Parameter Widths For VHDL users SOPC Builder allows a std 1ogic vector parameter to have a width that is defined by another parameter When adding a parameter of type std logic vector you can also specify its width as a parameter property The width can be a constant or the name of another parameter The commands below add a std logic vector parameter called myParameter whose width is set by another parameter called datawidth add parameter myParameter STD LOGIC VECTOR Set parameter property myParameter WIDTH dataWidth Generation Phase Behavior SOPC Builder s default generation does one of the following
234. tom components using Add Files command on HDL Files tab in the Component Editor Turn on the Synth option and turn off the Synth option The Classic Timing Analyzer was primary in earlier versions of the Quartus II software However Altera now recommends that you constrain designs before compilation because the TimeQuest Timing Analyzer reports any unconstrained paths by default during the compilation process Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook for further description of the TimeQuest Timing Analyzer Refer to the Switching to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook for a description of the benefits of using the TimeQuest Timing Analyzer rather than the Classic Timing Analyzer Refer to TimeQuest Example Basic SDC Example on www altera com for a working example of using the TimeQuest Timing Analyzer Refer to TimeQuest Design Examples on www altera com for further details about how to constrain different types of circuits for the TimeQuest Timing Analyzer Analyzing PLLs SOPC Builder User Guide You must constrain PLL clocks for proper analysis by the TimeQuest Timing Analyzer You can define clocks generated by PLLs using one of the following methods m Usethederive pll clocks command to derive clocks for all PLL outputs in the design This is the best method m Use the create generated clock command to designate each clock out
235. typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bald Type with initial Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets For example file name and lt project name gt poft file Indicate keyboard keys and menu names For example the Delete key and the Options menu Initial Capital Letters December 2010 Altera Corporation SOPC Builder User Guide Info 2 Additional InformationAdditional Information Typographic Conventions Visual Cue Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anyth
236. ual transfers December 2010 Altera Corporation SOPC Builder User Guide 11 12 Chapter 11 Avalon Memory Mapped Bridges Clock Crossing Bridge Example System with Avalon MM Pipeline Bridges Figure 11 9 illustrates a system in which seven Avalon MM masters are accessing a single DDR2 memory controller By inserting two Avalon MM pipeline bridges you can limit the complexity of the multiplexer that would be required Figure 11 9 Seven Avalon MM Masters Accessing One Avalon MM Slave External e 10K DMA Read DMA Write Processor M m m External Processor e y S S Avalon MM Avalon MM Pipeline Pipeline Bridge Bridge M M Avalon MM Master Port Avalon MM Slave Port S DDR2 Memory Controller Clock Crossing Bridge SOPC Builder User Guide The Avalon MM clock crossing bridge allows you to connect Avalon MM master and slaves that operate in different clock domains Without a bridge SOPC Builder automatically includes generic clock domain crossing CDC logic in the system interconnect fabric but it does not provide optimal performance for high throughput applications Because the clock crossing bridge includes a buffering mechanism you can pipeline multiple read and write transfers After an initial penalty for the first read or write there is no additional latency penalty f
237. uartus II software supports For details on installation and licensing refer to the Altera Software Installation and Licensing Manual Talkback Support SOPC Builder User Guide Talkback is a Quartus II software feature that provides feedback to Altera on tool and IP feature usage Altera uses the data to help guide future product planning efforts Talkback sends Altera information on the Altera components you use including interface types interface properties parameter names and values clocking and software assignments For components from Altera Talkback sends the component parameter values to help understand what features of the component are being used For non Altera components Talkback collects information about how interfaces such as Avalon MM are being used Connectivity between components is not sent The Talkback file does not include information about system connectivity interrupts or the memory map seen by each master in the system Talkback collects the same very general information about your proprietary components The Talkback feature is enabled by default You can disable Talkback from within the Quartus II software if you do not wish to share your usage data with Altera December 2010 Altera Corporation 2 System Interconnect Fabric for ANU S RAN Memory Mapped Interfaces The system interconnect fabric for memory mapped interfaces is a high bandwidth interconnect structure for connecting components tha
238. uilder components that interface to the specific devices on each development board For example the Nios II EDS includes the components Cypress CY7C1380C SSRAM and IDT71V416 SRAM which appear on Nios II development boards For further details about the features and usage of the SSRAM controller core refer to the Nios Development Board Cyclone II Edition Reference Manual or Nios Development Board Stratix II Edition For further details about the features and usage of the SDRAM controller core refer to Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough These components make it easy for you to create memory systems targeting Altera development boards However these components target only the specific memory device on the board they do not work for different devices m For general memory devices RAM or ROM you can create a custom interface to the device with the SOPC Builder component editor Using the component editor you define the I O pins on the memory device and the timing requirements of the pins In all cases you must also instantiate the Avalon MM Tristate Bridge component Multiple off chip memories can connect to a single tristate bridge in order to share pins such as the off chip address bus December 2010 Altera Corporation SOPC Builder User Guide 9 16 SOPC Builder User Guide Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough Off Chip SRAM and Flash Memory Avalon MM Tristate Bridge
239. uilder system You use conduit interfaces to connect application specific signals of the external device and the SOPC Builder system December 2010 Altera Corporation SOPC Builder User Guide 4 4 Chapter 4 SOPC Builder Components SOPC Builder Component Search Path You can also export the Avalon interfaces to manually connect them to external devices or logic defined outside a system with Avalon compatible signals This method allows a direct connection to the Avalon interface from any device that has Avalon compatible signals You can also export the Avalon interface in either an HDL file using conduit interfaces or in the hw tcl file without an HDL file You export the Avalon interface signals as an HDL file with simple wire connections in the HDL description The Avalon interface port signals are directly connected to external I O signals in the HDL description The conduit interface in the hw tcl file exports the external I O signals to the top level of the system In the _hw tcl file no HDL files are specified and only the Avalon signals and interface ports are declared in the file SOPC Builder Component Search Path Each time SOPC Builder starts it searches for component files The components that SOPC Builder finds are displayed in the list of available components on the SOPC Builder System Contents tab When you launch SOPC Builder the directories in the IP search path are searched for two kinds of files m _hw tcl files Each
240. uire exact sopc 10 0 get module properties This command returns the names of all the available module properties as a list of strings You can use the get module property and set module property commands to get and set values of individual properties The value returned by this command is always the same for a particular version of SOPC Builder get module properties ST Main validation elaboration generation and editor Usage get module properties Returns List of strings Arguments None Example get module properties Table 7 3 lists the available module properties their use and the phases in which they can be set Table 7 3 Module Properties Part 1 of 2 Property Name ios Can Be Set Description AUTHOR String Main program The module s author The description of the module such as i cael String Main program E ample SOPG Builder Module n The name to display when referencing the DISPLAY NAME String Main program nodule such as My SOPC Component Indicates if the component is editable in the EDITABLE Boolean Main program component editor The name of the editor callback The default EDITOR CALLBACK String Main program parameterization UI is displayed if this property is not set The name of the elaboration callback For static ELABORATION CALLBACK String Main program and generated components the default elaborations used if this property
241. ulation add_file simple uart v SYNTHESIS SIMULATION Indicate which of the added HDL files holds the top level module entity that describes the component name of the top level module entity set module property TOP LEVEL HDL FILE simple uart v set module property TOP LEVEL HDL MODULE simple uart December 2010 Altera Corporation SOPC Builder User Guide Chapter 7 Component Interface Tcl Reference Default Behaviors Default Behaviors The _hw tcl file described in the previous section has default behaviors during the editor validation elaboration and generation phases These default behaviors apply to instances of a component This section describes the default SOPC Builder behaviors for each of these phases To override these default behaviors refer to Overriding Default Behaviors on page 7 8 Validation Phase Behavior SOPC Builder s default validation checks each parameter value against its ALLOWED_RANGES property If the values specified are outside the allowed ranges an error message is displayed The ALLOWED_RANGES property of each parameter is a list of ranges that the parameter can take on where each range is a single value or a range of values defined by a start and end value separated by a colon Table 7 1 shows some examples of values the ALLOWED_RANGES property can take Table 7 1 ALLOWED_RANGES Property ALLOWED_RANGES Meaning a b c aorborc 1 2 4 8 16 1 2 4 8 or 16 1 3 1 through
242. ures that are used with SOPC Builder including the following m Quartus II IP File m Quartus II Incremental Compilation m TimeQuest Timing Analyzer on page 5 2 Quartus Il IP File The Quartus II IP File qip generated by SOPC Builder provides the Quartus II software with all required information about your SOPC Builder system SOPC Builder creates the qip during system generation and adds a reference to it in the Quartus II Settings File qsf The qip file includes references to the following information m HDL files used in the SOPC Builder system m TimeQuest Timing Analyzer Synopsys Design Constraint sdc files m Component definition files for archiving purposes The qip file is based on Tcl scripting syntax and is similar to the qsf file The information required to process most components is included in the system s single qip file Some complex components provide their own qip file in which case the system s qip file references the component qip file La The qip file is normally added to your project automatically by SOPC Builder If it does not get added automatically you can add the file in the same way that you add other source files to your project You can also have a qip file for each component in your design When you generate a design each qip is pulled into the main qip file for your system by reference Quartus Il Incremental Compilation SOPC Builder supports the Quartus II incrementa
243. ursts of lengths that you can configure Pipeline Stages and Effects on Latency The bridge provides three optional register stages to pipeline the following groups of signals m Master to slave signals including m address m writedata m write m read m byteenable m chipselect m burstcount optional December 2010 Altera Corporation Chapter 11 Avalon Memory Mapped Bridges 11 11 Avalon MM Pipeline Bridge m Slave to master signals including m readdata m readdatavalid m The waitrequest signal to the master When you include a register stage it affects the timing and latency of transfers through the bridge as follows m The latency increases by one cycle in each direction m Write transfers on the master side of the bridge are decoupled from write transfers on the slave side of the bridge because Avalon MM write transfers do not require an acknowledge signal from the slave m Including the waitrequest register stage increases the latency of master to slave signals by one additional cycle when the waitrequest signal is asserted Burst Support The bridge can support bursts with configurable maximum burst length When configured to support bursts the bridge propagates bursts between master slave pairs up to the maximum burst length Not having burst support is equivalent to a maximum burst length of one In this case the system interconnect fabric automatically decomposes master to bridge bursts into a sequence of individ
244. us map determines the port width from the HDL add interface port Callback i availability Main program and elaboration Usage add_interface_port lt interfaceName gt lt portName gt lt portRole gt lt direction gt lt width_expr gt Returns String interfaceName The name of the interface to which the port belongs portName The name of the port that you the component author have chosen The role of this port within the interfaces Port roles are referred to as signal Arguments portRole types in the Avalon Interface Specification Refer to the Avalon Interface g Specifications for the signal types available for each interface type direction The direction can be input output Or bidir The port s width expression In simple cases this is just the width of the port in width expr bits Example add interface port mm slave s0 rdata readdata output 32 December 2010 Altera Corporation SOPC Builder User Guide 7 36 Chapter 7 Component Interface Tcl Reference Hardware Tcl Command Reference get_interface_ports This command returns the names of all of the ports that have been added to a given interface If the interface name is omitted all ports for all interfaces are returned get_interface_ports asi Main validation elaboration generation and editor Usage get interface ports interfaceName Returns String Arguments interfaceName The name of the interface wh
245. utes to define a component If you provide all the required details for each component in an ipx file the start up time for SOPC Builder is less than if SOPC Builder must discover the files in a directory Example 4 2 shows two component elements Note that the paths for file names are specified relative to the ipx file Example 4 2 Component Elements library component name An SOPC Component displayName SOPC Component version 2 1 file components sopc_component sc_hw tcl gt lt component name legacy component displayName Legacy Component Classic Edition version 0 9 file components legacy old_component class ptf library Upgrading from Earlier Versions If you specified a custom search path in SOPC Builder prior to v8 1 using the IP Search Path option or by adding it to the SOPC BUILDER PATH SOPC Builder automatically adds those directories to the user components ipx file in your home directory This file is saved in lt home_dir gt altera quartus ip 8 1 ip_search_path user_components ipx Go to the IP Search Path option in the Options dialog box to see the directories listed here Component Structure SOPC Builder User Guide Most components are defined with a hw tcl file a text file written in the Tcl scripting language that describes the components in to SOPC Builder You can add a component to SOPC Builder by either writing a Tcl description or you can use the component ed
246. with respect to each interrupt receiver For each slave you can either specify an IRQ number or specify not to connect the IRQ Reset Distribution SOPC Builder User Guide SOPC Builder generates the logic used in the system interconnect fabric which drives the reset pulse to all the logic The system interconnect fabric distributes the reset signal conditioned for each clock domain The duration of the reset signal is at least one clock period The system interconnect fabric asserts the system wide reset in the following conditions m The global reset input to the SOPC Builder system is asserted m Any component asserts its resetrequest signal The global reset and reset requests are ORed together This signal is then synchronized to each clock domain associated to an Avalon MM port which causes the asynchronous resets to be de asserted synchronously December 2010 Altera Corporation 3 System Interconnect Fabric for ANU S RAN Streaming Interfaces The interconnect fabric for Avalon Streaming connects high bandwidth low latency components that use the Avalon Streaming Avalon ST interface This interconnect fabric creates datapaths for unidirectional traffic including multichannel streams packets and DSP data This chapter describes the Avalon ST interconnect fabric and its use in connecting components with Avalon ST interfaces Descriptions of specific adapters and their use in streaming systems can be found in the
247. y m Simplifies master component design The details of arbitration are encapsulated inside the system interconnect fabric Each Avalon MM master connects to the system interconnect fabric as if it is the only master in the system As a result you can reuse a component in single master and multimaster systems without requiring design changes to the component Traditional Shared Bus Architectures This section discusses the architecture of the system interconnect fabric generated by SOPC Builder for multimaster systems As a frame of reference for the discussion of multiple masters and arbitration this section describes traditional bus architectures December 2010 Altera Corporation SOPC Builder User Guide 2 10 Chapter 2 System Interconnect Fabric for Memory Mapped Interfaces Arbitration for Multimaster Systems In traditional bus architectures one or more bus masters and bus slaves connect to a shared bus consisting of wires on a printed circuit board or on chip routing A single arbiter controls the bus that is the path between bus masters and bus slaves so that multiple bus masters do not simultaneously drive the bus Each bus master requests control of the bus from the arbiter and the arbiter grants access to a single master at a time Once a master has control of the bus the master performs transfers with any bus slave When multiple masters attempt to access the bus at the same time the arbiter allocates the bus resources to a
248. y IV Full Full Full MAX Full No support No support MAX II Full No support No support Hardware Simulation Considerations The bridge components do not provide a simulation testbench for simulating a stand alone instance of the component However you can use the standard SOPC Builder simulation flow to simulate the component design files inside an SOPC Builder system Software Programming Model The bridge components do not have any user visible control or status registers Therefore software cannot control or configure any aspect of the bridges during run time The bridges cannot generate interrupts December 2010 Altera Corporation SOPC Builder User Guide 11 26 Chapter 11 Avalon Memory Mapped Bridges Software Programming Model SOPC Builder User Guide December 2010 Altera Corporation 12 Avalon Streaming Interconnect ANU S RAN Components Avalon Streaming Avalon ST interconnect components facilitate the design of high speed low latency datapaths for the system on a programmable chip SOPC environment Interconnect components in SOPC Builder act as a part of the system interconnect fabric They are not end points but adapters that allow you to connect different but compatible streaming interfaces You use Avalon ST interconnect components to connect cores that send and receive high bandwidth data including multiplexed streams packets cells time division multiplexed TDM frames and digital signal
249. y Memory Chip Devi evice Memory Chip Chip M Avalon MM Master Port S Avalon MM Slave Port SOPC Builder User Guide December 2010 Altera Corporation Chapter 9 SOPC Builder Memory Subsystem Development Walkthrough 9 3 Hardware and Software Requirements In Figure 9 1 all blocks shown below the system interconnect fabric comprise the memory subsystem For demonstration purposes this system uses a Nios II processor core to master the memory devices and a JTAG UART core to communicate with the host PC However the memory subsystem could be connected to any master component located either on chip or off chip Example Design Starting Point The example design consists of the following elements m A Quartus II project named quartus2 project A Block Design File bdf named toplevel_design toplevel_design is the top level design file for quartus2_project toplevel_design instantiates the SOPC Builder system as well as other pins and modules required to complete the design m An SOPC Builder system named sopc memory system sopc_memory_system is a subdesign of toplevel design sopc memory system instantiates the memory components and other SOPC Builder components required for a functioning SOPC Builder system This discussion assumes that the quartus2 project already exists sopc memory system has been started in SOPC Builder and the Nios II core and the JTAG UART core are al
250. y devices on the board If the SOPC Builder system interfaces with off chip memory devices you must make board level design choices Simulation Considerations SOPC Builder can automatically generate a testbench for RTL simulation of the system using ModelSim This testbench instantiates the SOPC Builder system and can also instantiate memory models for external memory components The testbench is plain text HDL located at the bottom of the top level SOPC Builder system HDL design file To explore the contents of the auto generated testbench open the top level HDL file and search on keyword test bench Beginning in ModelSim SE 6 2 design optimization is on by default Optimization may eliminate design nodes which are referenced in your wave display file In this case the you cannot display the waveforms You can ignore this failure if you want to run an optimized simulation However if you want to see the simulation signals you can disable the optimized compile by setting VoptFlow 0 in your modelsim ini file The modelsim ini is stored in the top level directory of the ModelSim installation Generic Memory Models The memory components described in this chapter except for the SRAM provide generic simulation models Therefore it is very easy to simulate an SOPC Builder system with memory components immediately after generating the system December 2010 Altera Corporation SOPC Builder User Guide 9 6 Chapter 9 SOPC Builder

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