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1.
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4. C404 alate cit neat ug EO LE 1 R501 47K a 501 0401 NC us E 6501 TUNER PART us 8 PU LV47004 n i 2 0402 NC 5 503 822 OR 407 R416 220 8 am 272 272 rx e C402 an 7 H po C413 CAN 8 L PS 48 ECAI2 8 nr tv 104 20 auo C403 w 5 an ro0uF isv E Ms SED 0402 5 mide i z cem E ot 1 D 2 tor mmo je oj d js e h e e E C505 m TUNER 33 884425407 AU NS 202 m 5 gss J ROS N EH Rig C408 uos mor 10K 470uF
5. 100901 LCD 68 afle 1 eile gl led g R lt S ze SS SS w i i 3 d 3 E i i 3 i i i 3 3 ala Yul TE 8 48 ER 8 4 14 a S c FECCCCCCECCECE 4 4 4 4 a R951 n of S a901 5 9014C 64 517 E 6 ai 17 518 3 le 3 le 3 ls E 18 521 S id 519 ROST 61 osc 56 520 60 ves 12901 821 u 21 5 3 0 59 sz y y a 58 22 82 E 87 SC75823 23 ES 5 x 8 56 24 8 4 5 VDD 25 52 2 903 904 555 55 7 7 4 7 54 26 52 5 27 amp e 53 528 2 20901 20902 ap 20903 20904 104 oO 28 evs evs evs evs 552 pen USB GND 5
6. 6 20 A B repeat setting and play 6 21 CD TEXT analysis and reading 6 22 CD USB SD mode switch 2 6 23 About audio mute pin TOSHIBA T5CJ3 7G28 F M Specification 61 22 63 2 64 22 65 66 68 m 2 74 2 75 2276 17 2278 2479 22280 2 2 84 6 24 About driver mute 6 25 Flash upgrading 6 26 Host MCU upgrading 6 27 About error code 6 28 About standby and resume play 6 29 Set play position and recovery play HA 6 30 Transfering cofficient data 6 31 About E2PROM function 7 Recommanded flow chart for host side software 71 Reset get firmware version set software feature flow 7 2 Mode switch auto play resume recovery play flow E 7 3 Play track change up down dir up dir down 7 4 repeat play 7 5 Host MCU upgrading 7 6 Flash upgrading flow 7 7 Program play flow 8 About characters coding TOSHIBA T5CJ3 7G28 F M Specification 1 Introduction T5CJ3 7G28 F M realizes CD USB SD audio player system It support audio track in CD and mp3 wma CD ROM USB mass storage device MTP device and SD card It is composed of one TOSHIBA 32 bit high speed MCU with a USB host c
7. xeH p 1 M07 lt 4 99 Ajunoes doo 7 gt 1 99 Aowa ysel pue 9AI9281 y y Aowa pue pjowssed y eyep ayes pneq ay xoeq ouo3 LYYN ejep 9 9291 y LYYN doo xuelg 3onpoud jonpoud jonpoid xuelg jonpoud yue qg uON yuejg yep ysey pue BY 55 au LYVN jonpoud xuejg 3joeuo jonpoud yue Page 261 1 id yonpoid yuejq uoN xuelg Aunoes peigesip Ajunoes Ajunoes Ajunoes
8. 1 6 V Standby current lc SRMSTB 73 L 20 uA Ta 20 C 70 C Terminal 1 8053 BUS2 BUS1 BUSO CDMON 0 3 Pio6 Pio7 2 Pio 0 5 Pio 8 11 3 PDo 4 FMo DMo FMoS 5 Foo TRo Note 8 Power supply current of operation is changed with a speed of operation or application The value of table is reference value when operating CDMP3 standard application of operation speed 85MHz MP3 stream condition fs 48kHz 320kbps 20 2010 01 12 TOSHIBA TC94B14MFG 5 3 AC Characteristic 5 3 1 MCU Pararell Mode BUCK I I XO Characteristics Symbol a Test Condition ocem 78 ew weona Dese Ld 21 2010 01 12 TOSHIBA TC94B14MFG 5 3 3 Audio I F LRCKi o BCKi o AIN OUT Characteristics Symbol Test Condition iud BCKo Clock L Term width CL 8pF fs 44 1kHz BCKo 645 BCKo standup falling term 1 BCKo 35pin C 8pF standup falling term 2 tBCORF2 170 70 BCKo 38pin 8pF LRCKo standup falling term 1 LRCKo 36pin C 8 LRCKo standup falling term 2 LRCKo 39pin 8pF AOUT Outpu
9. Juin 11950 uonnoexe Jejunoo ueJ6044d ysenbe yoojo Ulejs s sseippe 13S ur Bues ejduex3 yeys z Ld331S pue 2 eje1edo 2405465 LAS uonongjsul Jejunoo i e e Cie ysenbe yoojo LI LEFLELIELFLFLIE LE LE LELEF LE LELELEFLELFELELELEI Ulejs s Figure 2 11 IDLE1 2 SLEEP1 2 Modes Start Release Page 24 05 Hn 2 2 4 3 IDLEO SLEEPO modes IDLEO SLEEPO IDLEO and SLEEPO modes are controlled by the system control register 2 SYSCR2 and the time base timer control register TBTCR The following status is maintained during IDLEO and SLEEPO modes 1 Timing generator stops feeding clock to peripherals except TBT 2 The data memory CPU registers program status word and port output latches are all held in the status in effect before IDLEO and SLEEPO modes were entered 3 The program counter holds the address 2 ahead of the instruction which starts IDLEO and SLEEPO modes Note Before starting IDLEO or SLEEPO mode be sure to stop Disable peripherals 7 Stopping peripherals by instruction Starting IDLEO SLEEPO modes by instruction CPU and WDT are halted
10. RENE Mee 1227 ted da 12 8 Transmit Receive Operation 12 81 Data Transmit Operation eee dee ert adea 144 12 8 2 Data Receive Operation 144 12 9 Status ird nee E ETE e RT 12 9 T EmO i enne NP RENE RR Ree Ferr 145 12 9 2 Framing tede Gods tere eb Gne ert e tie e Depends be tb eee POUR 145 12 9 3 SQVEMUN etre eer re e esae ense 145 12 9 4 gt Receive Data Buffer repeti trt eoe repre tero pe ee ee PEE Po 146 19 9 Transmit Data Buffer Emply EE KEL denen ae rode ee dea REM 146 12 9 6 Transmit End E S PR eH e 147 13 Asynchronous Serial interface UART2 18 12 ce new par ea ed eue e er p Pers 19 2 CONTON yearn tae sara uo v Pv Tena e eta edita 19 3 Transfer Data Format 18 4 Transfer Rate 22 2 cade Reni E edm ven Sah YS US ba 13 5 Data Sampling 18 6 STOP Bit Eengthi
11. 11 83 PUnctions Zn oe Cee hkl ee lat an Aten Connie du e E UD RU ROSA 11 3 1 11 3 2 11 3 3 11 3 4 11 3 5 11 3 6 11 3 7 11 3 8 11 3 9 8 Bit Timer Mode 5 6 e n tte I OR Reed uo 8 Bit Event Counter Mode TCS 6 222222022 1 6 000000000000000000000000000000000 8 Bit Programmable Divider Output Mode 5 6 8 Bit Pulse Width Modulation PWM Output Mode TC5 6 16 Bit Timer Mode T C5 and 6 r o tte riore er een lee street 16 Bit Event Counter Mode TC5 and 6 16 Bit Pulse Width Modulation PWM Output Mode TC5 and 6 16 Bit Programmable Pulse Generate PPG Output Mode TC5 and 6 Warm Up Counter MOde 11 3 9 1 Low Frequency Warm up Counter Mode iii NORMAL1 NORMAL2 gt SLOW2 SLOW1 11 3 9 2 High Frequency Warm Up Counter Mode SLOW1 gt SLOW2 gt NORMAL2 gt NORMAL1 12 Asynchronous Serial interface UART1 12 Gontig lLatiOn Sus mre werd m eo DAR EID ok SUD eae 12 2 Control ciam eed evan Rn wet pw EN E SN URDU 12 3 Transfer Data Format 12 47 Transfer Rate BGS ware ion ad be la ea he oY LOE Bea bes 12 5 Data Sampling 12 6 STOP Bit
12. 32 sus D TOK ws 996 jm 220NH Ap m m E euo 5255 270 i o p 2 106 1 AO no 9102 0003 i cur C014 Roos m gt cn 10M 220K 1008 100 18 9002 e 077 FB152 90185 90145 FBI L009 AKT 474 Hi an L007 220UH cox cm Kin 104 ECO01 47UF z nois 5 77 6 223 58458288 58523 85558 5 lt TUNES 10 PCB LAYOUT MAIN BOARD SIDE VIEW 0301 702 I D401 A 7020 L 20421 10703 EC201 e 5 x ec3i2a ex 1062 9062 EC305 J18 J35 EC703 EC307 EC401 dU S J21 EC202 Ju 14 J31 120 172 CY GN 166 CON201
13. 50 5 2 Port P1 P17 10 52 5 3 Port P2 P22 to 20 54 5 4 Port P37 to P30 Large Current Port 55 5 5 Port P4 P47 to 40 56 5 6 Port P5 P54 to P50 Large Current Port 58 5 7 6 67 60 59 BBs cone wie ei amet 62 Watchdog Timer WDT 6 1 Watchdog Timer 65 6 2 Watchdog Timer 66 6 2 1 Malfunction Detection Methods Using the Watchdog Timer sess 66 6 2 2 Watchdog Timer Eriable 5 eti rp aee Eng a eate Cep esu sequia eee oe Ronan 67 623 Watchdog Timer Disable n d eee erret ee ce ME 68 6 2 4 Watchdog Timer Interrupt nennen enhn ennt senno 68 6 2 5 Watchdog 5 nes tr t e et ee niet eg eh PR 69 6 9 Address Trap eve viU RUE du d eo Ra dec PE cq 70 6 8 1 Selection of Address Trap in Internal RAM
14. edo Pe Re pic 1 8 Block Diagrams ss se keren trao 1 4 Pin Names 2 Operational Description 2 1 CPU Core Functions 2AA Memory Address Map oe eee eerte ER IE eu etae oT edt tole 2 1 2 Program Memory Flash 2158 se rer RESPETAR Ia 2 2 System Clock Controller 2 21 Clock Generator E 10 222 TAMING eter ro teni E AARE EOE EET R 12 2 2 2 1 Configuration of timing generator 2 2 2 2 Machine cycle 2 2 8 Operation Mode Control Circuit meer EROR RU 13 2 2 3 1 Single clock mode 2 2 3 2 Dual clock mode 2 2 8 8 STOP mode 2 2 4 Control eere teer E repe ces Eae elie 18 2 2 4 1 STOP mode 2 2 4 2 IDLE1 2 mode and SLEEP1 2 mode 2 2 4 3 IDLEO and SLEEPO modes IDLEO SLEEPO 2 2 4 4 SLOW mode 2 3 Resat nons eo ee c RE oce te 2 1 External x ooo eee rettet ete eere Er e NR Seen e esee REY e ee EON 2 3 2 2 3 3 Watchdog timer reset wie si i 2 3 4 System clock reset eve re
15. 251 20 6 7 Flash Memory security program Setting Mode Operation Command 252 207 SERMON Code eR aite Pad mei eR TER eds 20 8 Checksum SUM se Rew Y RE 20 81 Calculation Method i rd cobs ee Per ee epus 254 20 8 2 Calculation eo rae teo oe be o Duero e Yee vL ERR reed aee E ede 255 20 9 Intel Hex Format Binary 20 10 Passwords 22s nS ee RE eL Des Rh eee 20 10 12 oe o omes ERRAT eer nde ut 257 20 10 2 Handling of Password EtTOr ener terrere oed tu des eater oet adore eee aee Re aee ege 257 20 10 3 Password Management during Program 257 20 11 ProductlD Gode RA ERE BEAR ETD LG 20 12 Flash Memory Status 20 13 Specifying the 20 14 Flowchart 4 eas gu PASE 20 15 Timing iiim bo Rec Pe heuer RE edd 21 Input Output Circuit 251 Control pins inse era RR YR PESE aU bd WEN 21 2 Input Output Ports rw REUS Ge ed 22 Ele
16. 70 6 3 2 Selection of Operation at Address Trap 70 6 3 8 Address Trap Interrupt 212 0 400400000000000000000000000000000000000000 0 70 6 3 4 Address Trap Reset ec eR eh enne nero FA 71 Time Base Timer TBT 7 1 TIME Base Ss SE SU ERES YA ERE DA RP 73 TLA M 73 eM ery 1 or sa nes 73 11 38 74 7 2 Divider Output DVO 2 75 1 21 CONQUPAION Rite UR A I a SA 75 122 Control us ier eere ee 75 8 16 Bit TimerCounter 1 TC1 8 1 Configuration RU eene eoa waning epo d 82 TimerCounter 8 97 EUnGHOD OS pe De EE d E M 8 3 1 8 3 2 8 8 8 8 8 4 8 8 5 8 8 6 REM Er E 80 External Trigger Timer Mode ate ttn eri ambu eq EE 82 Event Counter Mode m Window Pulse Width Measurement 86 Programmable Pulse Generate PPG Output 89 9 16 Bit Timer Counter2 TC2 9 1 Configuration pene de ees Pear Adame pan
17. poU UU um y lt 19 91 uus 2 g Eo vO3HMd 0 a POJAM 1601 i 9 giu C oe Ce Jeu49ju 1 1 lt 4 gt lt 5 21 gt 49 21 Figure 10 7 16 Bit PWM Mode Timing Chart TC3 and 4 Page 114 05 Ls 10 3 8 16 Bit Programmable Pulse Generate PPG Output Mode TC3 and 4 This mode is used to generate pulses with up to 16 bits of resolution The timer counter 3 and 4 are cascad able to enter the 16 bit PPG mode The counter counts up using the internal clock or external clock When a match between the up counter and the timer register PWREG3 PWREG4 value is detected the logic level output from the timer F F4 is switched to the opposite state The counter continues counting The logic level output from the timer F F4 is switched to the opposite state again when a match between the up counter and the timer register TTREG3 TTREGA value is detected and the counter is cleared The INTTC4 interrupt is generated at this time Two machine cycles are required for the high or low level pulse input to the TC3 pin Therefore a maxi mum frequency to be supplied 15 24 Hz in the NORMALI 2 or IDLE1 2 mode and fs 2 to in the SLOWI 2 SLEEPI 2 mode Since the initial value can be set to the timer F F4
18. WOOO GND3 8 39 8 B 1250 150301 4128 x RCA401 LI _______ 12301 EC30 ki 8 sje 157 136 3 4130 173 CND 5 J31 SUB OUT 1132 2133 S iss R307 1139 5 2140 159 1138 gt EC404 Ce CY 501 3174 o EC409 1175 5 EMOR E EC405 o Io 8 15 ITEL MUTE 5 8 7 245 ji 7 6 7 8 19 0 2 S _ 411 2 c2 EC306 3 4 ON g 1 m gt 403 5 5 el J112 PHILIPS m 123 SJ CON602 EI ae 8 8 158 5 759 88 P 183 94 0 T Es mm VER1 2 2011 5 EC603 EK NEN Q z 215 as 070 5 8 Q 1163 3 x201 O cso 410 CEM2100A EB 00 x202 5 LI E 4 J34 85 8 506 4 CY 167 5 4172 CY EC308 138 477 E CC X602 EC310 S201 278 EC309 E E GND2 000 000 PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW
19. 2 eres f dia zb y D7 06 05 D4 03 02 D1 DO New D7 mm e eem em rim m mri i mc ic om i mt mik nd n m mini Acknowledge signal to a transmitter f Figure 16 11 Example of when 000 1 Page 206 05 n To make the transmitter terminate transmit clear the ACK to 0 before reading data which 15 1 word before the last data to be received A serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ACK In the interrupt routine of end of transmission when the BC is set to 001 and read the data PIN is set to 1 and generates a clock pulse for a 1 bit data transfer In this case since the master device is a receiver the SDA line on a bus keeps the high level The transmitter receives the high level signal as an ACK signal The receiver indicates to the trans mitter that data transfer is complete After 1 bit data is received and an interrupt request has occurred generate the stop condition to ter minate data transfer SCL pin 1 2 3 4 5 6 1 8 1 pom ea pm mmm pom mmm Rum mmm lt lt m m SDA pin D7 4 D6 A D5 A D4 03 A D2 A Di DO 4 Acknowledge signal sent to a transmitter INTSBI T T T Clear ACK to 0 interrupt request
20. E 5 EM 2 5 8 225052222 22285805885 use noi imas C702 33 18K R709 C703 DSRAMSTB RST o x 4 4148 a G DIV RR6OS C613 614 EE 652 10 C653 10 Uf EEPROM in Eeprom mode SCL ond SDA pull down 10K R648 100 32 768kHz eiiim TORRES Buso Bust BUS Buss LMT SW CD RCH CD LCH DWUTE UCK BUSS 8052 BUSI 8030 9 E VDD1 VDD CO RCH buck BUSS Bus 8051 REQ
21. input pin input ee ql Hune Tempe Note1 For 16 bit operations 16 bit timer event counter warm up counter 16 bit PWM and 16 bit PPG set its source clock on lower bit TC5CK Note2 Available source clock Page 123 11 8 Bit TimerCounter 5 6 11 1 Configuration igurati T5CL8 Table 11 3 Constraints on Register Values Being Compared 16 bit PWM 2 lt PWREG6 5 65534 1 lt PWREG6 5 lt TTREG6 5 65535 16 bit PPG ded PWREG6 5 1 lt TTREG6 5 Note 5 to 6 Page 124 05 11 3 Function The TimerCounter 5 and 6 have the 8 bit timer 8 bit event counter 8 bit programmable divider output PDO 8 bit pulse width modulation PWM output modes The TimerCounter 5 and 6 5 6 are cascadable to form a 16 bit timer The 16 bit timer has the operating modes such as the 16 bit timer 16 bit event counter warm up counter 16 bit pulse width modulation output and 16 bit programmable pulse generation modes 11 3 1 8 Bit Timer Mode TC5 and 6 In the timer mode the up counter counts up using the internal clock When a match between the up counter an
22. 196 16 5 12C Bus Control Rev ERE E SR ERG ES 197 16 5 1 Acknowledgement mode specification esses eene enne een 199 16 5 1 1 Acknowledgment mode 1 16 5 1 2 Non acknowledgment mode ACK 0 1625 2 Number of transter bits eee eek eer ie een ie o eii ees 200 162573 et eee Eee RE he ete 200 16 5 3 1 Clock source 16 5 3 2 Clock synchronization 16 5 4 Slave address and address recognition mode 201 16 5 5 Master slave 16 5 6 Transmitter receiver selection 16 5 7 Start stop condition generation 16 5 8 Interrupt service request and cancel 16 5 9 Setting of I2C bus mode 16 5 10 Arbitration lost detection monitor 16 5 11 Slave address match detection monitor 16 5 12 GENERAL CALL detection monitor 16 5 13 Last received MONON reete ck dene ere e Ne oua 16 6 Data Transfer of I2C 16 6 1 2 25222 RR 16 6 2 Start condition and slave address generation 16 6 3 1 data 16 6 3 1 When the MST is 1 Master mode 16 6 3 2 When the MST is 0 Slave mode 16 6 4 Stop condition gener
23. R619 100R D gt 3395 Li vss ner 565 IN2 um 24 R620 10k case um xi R229 t ti WEIT g E consoa P t c Sex WS i Jr sense GO NSE id hd 27 lt wcu3v3 dor ok 1 decidi AT us siepe 5 15 EIE vul fook 3 5 sddauddag gt F sll Spe sc de Res9 o R65 0 105 gy puts H 1 t O _______ 52 2578 44 KEY 5 5526866 VREF H ER C sit O 85 Ad xd A 4o lt 2 e 888 rcs H m gt get TT voL c3 SaaS SSA S s 7 7 e T 625 ES n i 2 o Li H nu EN Re26 77K M Leon jeo 1 RIT x pem uco cLk 4 lt Fes m iK LCD DATA unc a T Ep H m H H H 14 R240 R241 R242 R243 R628 470 am T REMOTE gt gt TIR H 5 RATES a 8 aw 4 esos 0209 9018 10306 ACP1206 15 ES R279100K AW HITISD LN2050 5V C258 gt 22 272 aho on n C251 v gt oHe
24. X n Lower byte TTREG4 2 m Upper byte 1 detect detect INTTC4 interrupt request 1 Figure 10 6 16 Bit Timer Mode Timing Chart TC3 4 Page 111 10 8 Bit TimerCounter TC3 4 10 1 Configuration T5CL8 10 3 6 16 Bit Event Counter Mode TC3 and 4 In the event counter mode the up counter counts up at the falling edge to the TC3 pin The TimerCounter 3 and 4 are cascadable to form a 16 bit event counter When a match between the up counter and the timer register TTREG3 TTREGA value is detected after the timer is started by setting TC4CR lt TC4S gt to 1 an INTTC4 interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting at the falling edge of the input pulse to the TC3 pin Two machine cycles are required for the low or high level pulse input to the TC3 pin Therefore a maximum frequency to be supplied is fc 2 Hz the NORMAL1 2 or IDLE1 2 mode and fs 24 in the SLOW1 2 SLEEP1 2 mode Program the lower byte TTREG3 and upper byte TTREG4 in this order in the timer register Programming only the upper or lower byte should not be attempted Note 1 In the event counter mode fix TCjCR lt TFFj gt to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the event counter mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configurati
25. 0036H DVOEN DVOCK DV7CK TBTEN TBTCK Initial Value 0000 0000 Time Base Timer 0 Disable TBTEN enable disable 1 Enable NORMAL1 2 IDLE1 2 Mode IDLE1 2 Mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 Mode wm ww CIRE UE M RN ee wem E Pe e Note 1 fc High frequency clock Hz fs Low frequency clock Hz Don t care Page 73 7 7 1 5 8 Note 2 The interrupt frequency TBTCK must be selected with the time base timer disabled TBTEN 0 The interrupt fre quency must not be changed with the disable from the enable state Both frequency selection and enabling can be per formed simultaneously Example Set the time base timer frequency to fc 216 Hz and enable an INTTBT interrupt LD TBTCR 00000010B lt 010 LD TBTCR 00001010B TBTEN lt 1 DI lt 0 EIRL 7 Table 7 1 Time Base Timer Interrupt Frequency Example fc 16 0 MHz fs 32 768 kHz Time Base Timer Interrupt Frequency Hz NORMAL 1 2 IDLE1 2 Mode NORMAL41 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 Mode DV7CK 0 DV7CK 1 001 7 63 010 244 14 128 7 1 3 Function INTTBT Time Base Timer Interrupt is generated on the first falling edge of source clock The divider output of the timing generator which is selected by TBTCK after time base timer has been enable
26. 5 sseJppe je uononujsul 146 eui ejduiex3 yes 18 pue ejeJedo 7 ELTE BIUpm E E LB PE BP B B BEP B 2718 1212 5 ZHOSAS 135 Jejunoo jsenbejJ jdnuey Figure 2 13 IDLEO and SLEEPO Modes Start Release Page 27 2 Operational Description 2 2 System Clock Controller T5CL8 2 244 SLOW mode SLOW mode is controlled by the system control register 2 SYSCR2 The following 15 the methods to switch the mode with the warm up counter 1 Switching from NORMAL2 mode to SLOW1 mode First set SYSCR2 lt SYSCK gt to switch the main system clock to the low frequency clock for SLOW mode Next clear SYSCR2 XEN to turn off high frequency oscillation Note The high frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly Always turn off oscillation of high frequency clock when switching from SLOW mode to stop mode Example 1 Switching from NORMAL2 mode to SLOWI mode SET SYSCR2 5 SYSCR2 lt SYSCK gt lt 1 Switches the main system clock to the low frequency clock for SLOW2 CLR SYSCR2 7 SYSCR2 lt XEN gt lt 0 Turns off high frequency oscillation Example 2 Switching to the SLOWI mode after low frequency clock has stabilized SET SYSCR2 6 SYSCR2 lt XTEN gt lt 1 LD TC5CR 43
27. RF ripple zero cross signal Input pin 23 RFRP ripple signal output pin ipple sig utput pin serises 5000 24 Tracking error signal output pin Connect to VRo by capacitor 25 AVDD3 Power supply pin for 3 3 V CD analog circuits 26 FOo Focus servo equalizer output pin Bulit in serises R 3 3 27 Tracking servo equalizer output pin Bulit in output R 3 3 Grounding pin for 1 5V Decoder DSP 28 VSS dd CD circuit 29 Feed servo equalizer output pin Bulit in output R 3 3 FMoS Feed servo equalizer output pin 5 Stepper motor application 31 DMo Disc servo equalizer output pin Bulit in output R 3 3 Power supply pin for 1 5V Decoder DSP 32 VDD1 3 d ICD circuit 44 Pio8 VO Port 8 General Input Output Port CMOS Port TxD Dout HS UART Out Dout SPDIF Schmitt input 9 VO Port 9 General Input Output Port CMOS Port RxD Aout HS UART In Aout Schmitt input ds Pio10 Port 10 General Input Output Port CMOS Port RTS BCKo HS UART Out BCKo Schmitt input Pio11 yo Port 11 General Input Output Port CMOS Port CTS LRCKo HS UART In LRCKo Schmitt input id Port 12 General Input Output Port CMOS Port ut Outpu CDMONO 3I F m id Monitor 0 Audio data input 2
28. Figure 2 7 Level sensitive Release Mode Note 1 Even if the STOP pin input is low after warm up start the STOP mode is not restarted Note 2 In this case of changing to the level sensitive mode from the edge sensitive mode the release mode is not switched until a rising edge of the STOP pin input is detected 2 Edge sensitive release mode RELM 0 In this mode STOP mode is released by a rising edge of the STOP pin input This is used in appli cations where a relatively short program is executed repeatedly at periodic intervals This periodic signal for example a clock from a low power consumption oscillator is input to the STOP pin In the edge sensitive release mode STOP mode is started even when the STOP pin input is high level Do not use any STOP3 to STOPO pin input for releasing STOP mode in edge sensitive release mode Example Starting STOP mode from NORMAL mode DI lt 0 LD SYSCR1 10010000B Starts after specified to the edge sensitive release mode Sane NORMAL STOP STOP operation operation Warm up operation STOP mode started by the program NORMAL operation STOP mode is released by the hardware at the rising edge of STOP pin input Figure 2 8 Edge sensitive Release Mode Page 19 2 Operational Description 2 2 System Clock Controller T5CL8 STOP mode is released by the following sequence 1 2 Note 1 Note 2 No
29. 104 Ls 2 004 R402 2 235 5 5 TUNER CLK SD 3V3 85 B o d d 4 d 8 s x 005 Rex C TUNER DA BU TB Y 5 5 5 mx 5 ja 106 258 al Ss 5 5 C423 C424 u EC403 202 8 2 72457 s 88 OL SDA 5 509 Dien 22 7 u 5 z nec 5 HSD AC_OND SYR 22K 4 429 me 8 8435 22K C426 10 i m 4 E wur 25 2 15K i 2 igh m all 8 C439 3 X 5 6444 z H rr S 8 5 me 2 2 rere 0403 IN4148 I 15 prd FUB E H bem 8 2 C445 4414 naan 224 C431 4u7 4 497 R aka 1472 820 5 4 m g H ee E gt 1 1 Ej 5 R429 C443 R433 220 5 EC405 L ano Line output 417 A TuF 90N E 5 cans F RATS 383 TKS all gt 4558 E mee lE 407 Rua uk gt 85 0405144148 4 H 552 C4 46100 R478 22K H E UNE FL 2 R475 g s ou SE Eo ae E C447
30. Blac Pe er3 ST BOOKMARK STATUS 0xde eturn of B A S T command ndicates boo mar set status boo mar set mar set BOOKMARK PLAY STATUS O0xdf eturn of B A PA command ndicates boo mar lay is available or not ommand se uence Case 1 bookmark set hen laying normally boo mar set ill be success But if current stream infomation is un no boo mar set maybe set failed 53 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 BOOKMARK SET 1600 BOOKMARK STATUS de Case 2 bookmark clear There is no command return in this case HOST BP3 BOOKMARK CLEAR 1601 Case 3 bookmark play OK fboo mar setis valid boo mar lay ill be success other ise boo mar lay ill be failed HOST BP3 BOOKMARK PLAY 3c BOOKMARK PLAY STATUS df 6 20 A B repeat setting and play er3su ortsA Bre eat laying function But henA Bre eat laying eration is invalid t can only doing normal laying ause Same as boo mar setting setting is maybe failure if stream information is un no n this occasion host need try again after aiting for some time Any of sto o eration trac do no eration ordiru do no eration illclearAB AT setting elevant commands are listed bello ST Blac Pe er3 REPEAT O0x3f CANCEL 3f A B SETA 3f 54 TOSHIBA T5CJ3 7G28 F M Specification Blac Pe er3 ST REPEAT STATUS 0xbf CANCEL STATUS
31. Example Setting the timer mode with source clock fe 2 Hz and generating an interrupt 300 ms later 16 0 MHz LDW TTREGS 927CH Sets the timer register 300 ms 27 fc 927CH DI SET EIRE 2 Enables INTTC6 interrupt El LD 5 13H Sets the operating clock to fc 2 and 16 bit timer mode lower byte LD TC6CR 04H Sets the 16 bit timer mode upper byte LD TC6CR OCH Starts the timer TC6CR lt TC6S gt Internal 1 Source clock 1 Counter TTREG5 X n Lower byte TTREG6 2 m Upper byte 1 detect detect INTTC6 interrupt request 1 Figure 11 6 16 Bit Timer Mode Timing Chart TC5 6 Page 131 11 8 Bit TimerCounter 5 6 11 1 Configuration T5CL8 11 3 6 16 Bit Event Counter Mode TC5 and 6 In the event counter mode the up counter counts up at the falling edge to the TC5 pin The TimerCounter 5 and 6 are cascadable to form a 16 bit event counter When a match between the up counter and the timer register 5 TTREG6 value is detected after the timer is started by setting TC6CR lt TC6S gt to 1 an INTTC6 interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting at the falling edge of the input pulse to the TC5 pin Two machine cycles are required for the low or high level pulse input to the TC5 pin Therefore a maximum frequency to be supplied
32. jonpoud yue yoayo ureBoig Ajunoes Ajunoes Ajunoes SOA sdq 0096 0 49019 eu jsn py pneq y snfpy eyep Hog HOO ejep 1 Ajunoes use J H04 3ndjno 514 HEO jndjno apoo Wu HOOD 09 3ndjno wns ysel HOE L HVS N gt dmes 1 18 y peseq pneq Ajipow 20 Serial PROM Mode
33. 1 EF7 interrupt individual enable flag 1 and TBTCR lt TBTEN gt 1 interrupt pro cessing is performed When IDLEO mode is entered while TBTCR lt TBTEN gt 1 the INTTBT interrupt latch is set after returning to NORMAL mode 2 2 3 2 Dual clock mode Both the high frequency and low frequency oscillation circuits are used in this mode P21 XTIN and P22 XTOUT pins cannot be used as input output ports The main system clock is obtained from the high frequency clock in NORMAL2 and IDLE2 modes and is obtained from the low frequency clock in SLOW and SLEEP modes The machine cycle time is 4 fc s in the NORMAL2 and IDLE2 modes and 4 fs s 122 us at fs 32 768 kHz in the SLOW and SLEEP modes The TLCS 870 C is placed in the signal clock mode during reset To use the dual clock mode the low frequency oscillator should be turned on at the start of a program 1 2 3 NORMAL2 mode In this mode the CPU core operates with the high frequency clock On chip peripherals operate using the high frequency clock and or low frequency clock SLOW2 mode In this mode the CPU core operates with the low frequency clock while both the high frequency clock and the low frequency clock are operated As the SYSCR2 lt SYSCK gt becomes 1 the hard ware changes into SLOW2 mode As the SYSCR2 lt SYSCK gt becomes 0 the hardware changes into NORMAL2 mode As the SYSCR2 lt XEN gt becomes 0 the h
34. 24 2010 01 12 TOSHIBA TC94B14MFG 5 4 Analog Circuit Characteristics 5 4 1 AD Converter Characteristics Test Test Condition Unit EF Resolution Sampling frequency Conversation input range AVSS TON a 13x ee 3 3 V AVpp3 5 4 2 DA Converter Focus and Tracking Sections Characteristics Test Test Condition Min Typ Max Unit Circuit C pe Ses Y 5 4 3 PLL Section Filter Amp Characteristics Test Test Condition Min Typ Max Unit Circuit Frequency characteristic point Gain 1 17 5 4 4 VCO PLL Characteristics Test Test Condition Min Typ Max Unit Circuit Oscillation center frequency LPFO VREF 25 2010 01 12 TOSHIBA TC94B14MFG 5 4 5 TEZI Signal Comparator Characteristics Test Test Condition Min Typ Max Unit Circuit 5 4 6 RFZI Signal Comparator Characteristics Test Test Condition Min Typ Max Unit Circuit 5 4 7 Data Slicer Circuit 1 Comparator Characteristics Test Test Condition Min Typ Max Unit Circuit 2 R 2R DAC DAC for digital slicer Characteristics Test Test Condition Min Typ Max Unit Circuit Output conversation range m SLCOG 0 va Output conversation range SLCOG 1 Output impedance impedance 95065 0 26 2010 01 12 TOSHIBA T
35. 3 At acceptance of an interrupt Figure 3 3 Save store register using PUSH and POP instructions 3 3 2 2 Using data transfer instructions At execution of PUSH instruction At execution of POP instruction At execution of RETI instruction To save only a specific register without nested interrupts data transfer instructions are available Page 40 05 me Example Save store register using data transfer instructions PINTxx LD GSAVA A Save A register interrupt processing LD A GSAVA Restore A register RETI RETURN Main task Interrupt Interrupt acceptance service task Saving registers Restoring registers Interrupt return Saving Restoring general purpose registers using PUSH POP data transfer instruction Figure 3 4 Saving Restoring General purpose Registers under Interrupt Processing 3 3 3 Interrupt return Interrupt return instructions RETI RETN perform as follows RETI RETN Interrupt Return 1 Program counter PC and program status word PSW includes IMF are restored from the stack 2 Stack pointer SP is incremented by 3 As for address trap interrupt INTATRAP it is required to alter stacked data for program counter PC to restarting address during interrupt service program Note If RETN is executed with the above data unaltered the program returns to the address trap area and INTATRAP occurs again When interrupt accept
36. Example 1 Clears interrupt latches DI 0 LDW ILL 1110100000111111B 112 IL10 to IL6 0 EI lt 1 Example 2 Reads interrupt latchess LD WA ILL W lt ILH A lt ILL Example 3 Tests interrupt latches TEST ILL 7 if IL7 1 then jump JR F SSET 3 2 Interrupt enable register EIR The interrupt enable register EIR enables and disables the acceptance of interrupts except for the non maskable interrupts Software interrupt undefined instruction interrupt address trap interrupt and watchdog interrupt Non maskable interrupt 15 accepted regardless of the contents of the EIR The EIR consists of an interrupt master enable flag IMF and the individual interrupt enable flags EF These registers are located on address 002CH 003AH and 003BH in SFR area and they can be read and written by an instructions Including read modify write instructions such as bit manipulation or operation instructions 3 2 1 Interrupt master enable flag IMF The interrupt enable register IMF enables and disables the acceptance of the whole maskable interrupt While IMF 0 all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag EF By setting IMF to 1 the interrupt becomes acceptable if the individuals are enabled When an interrupt is accepted IMF is cleared to 0 after the latest status on IMF 15 stacked Thus the maskable inter rupts
37. RXD1 NTO Initial value 1111 1111 BOOT POOUTCR Initial value 0000 0000 0008H 0 Sink open drain output POOUTCR Port PO output circuit control Set for each bit individually i Chios aba aie pane 000 Read only Page 51 5 Ports 5 2 Port P1 P17 to P10 15018 5 2 Port P4 P17 to P10 Port P1 1s an 8 bit input output port which can be configured as an input or output in one bit unit Port P1 is also used as a timer counter input output an external interrupt input and a divider output Input output mode is specified by the control register PICR During reset the PICR is initialized to 0 and port P1 becomes an input mode And the is initialized to 0 When used as an input port a timer counter input and an external interrupt input the corresponding bit of PICR should be set to 0 When used as an output port the corresponding bit of PICR should be set to 1 When used as a timer counter output and a divider output PIDR 15 set to 1 beforehand and the corresponding bit of PICR should be set to 1 When 15 1 the content of the corresponding output latch is read by reading P1DR Table 5 2 Register Programming for Multi function Ports Programmed Value Function P1DR P1CR Port input timer counter input or external interrupt input Port 1 output a timer output or a divider output Note Asterisk indicates
38. Set up by PINMN command CDMON FGIN CD G CD TEXT CMD PINMN CMD BRKFG CMD CLCKIEN CMD TEXTO CDMONO CDMONO CLCKi Priority on CDMON1 CDMON1 DATA TXSRCKi CDMON CDMON2 CDMON2 SFSY TEXTD CDMONS3 CDMONS3 SBSY SBSY Set up by PINMN command 9 2010 01 12 TOSHIBA TC94B14MFG 2 Initialization method Figure 2 1 shows the power on and initialization sequences of the TC94B14MFG Power On PLL Power On PLL Boot Power On Rebet Period 50 Period Reset Period Set Up Period Wait Period Progtam Boot Period Normal Function Power Off 4 4 gt lt gt 4 SRAMSTB VDDM1 VDD1 4 tdl i 02 AL SS o O oO o e ou e e 5t DVDD3 RVDD3 4 VDD3 trst1 y _ RST _tlocki 4 2 Internal i System Clock twait Program Start MCU L F Note SRMSTB VDDM1 and VDD1 should be supplied at the same time within 100ms Characteristics Symbol Fus we sme me ne Fuse Tex s Poems wor om Figure 2 1 Power on and initialization sequences 10 2010 01 12 TOSHIBA TC94B14MFG 3 Standby Functions The TC94B14MFG supports SRAM standby modes When portable or in vehicle units are on standby using this
39. lt gt 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading for the first time Table 8 1 Internal Source Clock for TimerCounter 1 Example fc 16 MHz fs 32 768 kHz 1 2 IDLE1 2 mode n DV7CK 0 DV7CK 1 Maximum Time Set ting s Resolution Maximum Time Setting Resolution Maximum Time Setting Resolution us us s s 00 128 8 39 244 14 16 0 244 14 16 0 01 8 0 0 524 8 0 0 524 10 0 5 32 77 m 0 5 32 77 m Example 1 Setting the timer mode with source clock fc 2 Hz and generating an interrupt 1 second later fc 16 MHz TBTCR lt DV7CK gt 0 LDW TC1DRA 1E84H Sets the timer register 1 s 211 fc DI IMF 0 SET EIRL 5 Enables INTTC1 EI IMF 1 LD TC1CR 00000000B Selects the source clock and mode LD TC1CR 00010000B Starts TC1 Example 2 Auto capture LD TC1CR 01010000B ACAP1 lt 1 LD WA TC1DRB Reads the capture value Note Since the up counter value is captured into TC1DRB by the source clock of up counter after setting TC1CR lt ACAP1 gt to 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading TC1DRB for the first time Page 80 05 me Timer start Source clock Counter TC1DRA Source clock Counter TC1DRB ACAP1 b Auto capture
40. SIO2CR lt SIOS gt SIO2SR register SIO2RDB register and SIO2TDB register are initialized Note 2 Transfer mode direction of transfer and serial clock must be select during the transfer is stopping when SIO2SR lt SIOF gt 0 Note 3 fc High frequency clock Hz fs Low frequency clock Hz Don t care Page 178 05 dd Serial Interface Status Register SIO2SR 7 6 5 4 3 2 0032H sioF TXERR RXERR Initial value 0010 00 SIOF Serial transfer operation status 0 Transfer finished monitor 1 Transfer in progress Read only SEF Number of clocks monitor 1 1 to 7 clocks 0 Data exists in transmit buffer TXF T it buffi ty fl ES UNSERE MR 1 No data exists in transmit buffer 0 No dat ists i ive buff RXF Receive buffer full flag opu 1 Data exists in receive buffer Read 0 No error exist 1 Transmit buffer under run occurs in an external clock mode Write 0 Clear the flag 1 A write of 1 to this bit is ignored Transfer operation error flag Read 0 No error exist 1 Receive buffer over run occurs in an external clock mode Write 0 Clear the flag 1 A write of 1 to this bit is ignored Receive operation error flag Note 1 The operation error flag TXERR and RXERR are not automatically cleared by stopping transfer with SIO2CR lt SIOS gt 0 Therefore set these bits to 0 for clearing these error flag Or set SIO2CR
41. a gt 8 3 5 MAIN PWR 2 mm rg Ji 8 8 x g FREE B 1 8 mo R490 47K 8 ERE el gt 57 EM mE mss 560 osos CD PWR Prot C461 jiensv AU X 1 ees VOL LED R309 2K2 1 4W mss EL D 58 AUX R R264 270R 58 C462 ATF Rise 560 1 HS RIN 22K 58 8 4 8 Nu me B E d H m x lt cbav H gt cw 5 amp 102 k E rom x ART 1 40 eS 8772 C464 C408 oo seve 1302 100 16V 104 1577 33 40 NC 23 Lid gt Ce c OWNER D 744 5 R4O4A NC Ss R499 AUX2 104 16V ES 29 t 0216 4148 CIRCUIT DIAGRAM PANEL BOARD
42. SCL pin Master 2 Count reset SCL Bus Figure 16 4 Clock Synchronization As Master pulls down the SCL pin to the low level at point the SCL line of the bus becomes the low level After detecting this situation Master 2 resets counting a clock pulse in the high level and sets the SCL pin to the low level Master 1 finishes counting a clock pulse in the low level at point b and sets the SCL pin to the high level Since Master 2 holds the SCL line of the bus at the low level Master 1 waits for counting a clock pulse in the high level After Master 2 sets a clock pulse to the high level at point and detects the SCL line of the bus at the high level Master 1 starts counting a clock pulse in the high level Then the master which has finished the counting a clock pulse in the high level pulls down the SCL pin to the low level The clock pulse on the bus is determined by the master device with the shortest high level period and the master device with the longest low level period from among those master devices connected to the bus 16 5 4 Slave address and address recognition mode specification When the serial bus interface circuit is used with an addressing format to recognize the slave address clear the ALS in I2CAR to 0 and set the SA Bits7 to 1 in I2CAR to the slave address When the serial bus interface circuit is used with a free data format not to recognize the slave address set the
43. SET SYSCR2 7 SYSCR2 lt XEN gt lt 1 Starts high frequency oscillation LD TC5CR 63H Sets mode for TC6 5 16 bit mode fc for source LD TC6CR 05H Sets warming up counter mode LD TTREG6 OF8H Sets warm up time DI lt 0 SET EIRE 2 Enables INTTC6 El 1 SET TC6CR 3 Starts TC6 5 PINTTC6 CLR TC6CR 3 Stops TC6 5 CLR SYSCR2 5 SYSCR2 lt SYSCK gt lt 0 Switches the main system clock to the high frequency clock RETI VINTTC6 DW 6 INTTC6 vector table Page 29 2 Operational Description 2 2 System Clock Controller T5CL8 Z1VINHON 94 0 q c IVWHON MO IS 2 016 Buunp dn we AA F X S CHOSAS 2 6 8 118 MOSAS M07 xooJo MOIS MO TS 1 CIVINHON uonnoexe uononisu MOSAS M07 Figure 2 14 Switching between the 2 SLOW Modes Page 30 05 Hn 2 3 Reset Circuit The T5CL8 has four types of reset generation procedures An external reset input an address trap reset a watchdog timer reset
44. TXD pin CMtr1 Page 262 05 bd 21 Input Output Circuit 21 1 Control pins The input output circuitries of the TSCL8 control pins are shown below Osc enable VDD connecting pins XIN Input high frequency XOUT Output 1 2 typ Ro 70 5 typ Osc enable Resonator connecting pins XTIN Input VDD Low frequency XTOUT Output 6 typ Ro 220 typ Hysteresis input Pull up resistor RESET Input npu Rin 220 Address trap reset R 100 Q typ Watchdog timer reset System clock reset R TEST Input 100 Q typ Note The TEST pin of the T5CL8 does not have a pull down resistor and a protection diode on the VDD side There fore fix the TEST pin at Low level Page 263 21 Input Output Circuit 21 2 Input Output Ports ERR T5CL8 21 2 Input Output Ports Initial High Z Data output Tri state Hysteresis input Disable 100 Q typ Pin input Initial High Z Sink open drain output High current output Data output 100 typ Output latch input Pin input Initial High Z Sink open drain output Hysteresis input Data output R 100 typ Output latch input Pin input Initial High Z Sink open drain output High current output Data output Hysteresis input Output latch input 100 typ Pin input Initial High Z P ch control Sink open drain output or C MOS
45. Timer start Count start Count stop Count start TC1 pin input Internal clock Counter TC1DRA Match detect INTTC1 interrput request Counter clear b Negative logic TC1S 11 Figure 8 5 Window Mode Timing Chart Page 85 8 16 Bit TimerCounter 1 TC1 8 3 Function 8 3 5 Pulse T5CL8 Width Measurement Mode In the pulse width measurement mode the up counter starts counting by the input pulse triggering of the TCI pin and counts up at the edge of the internal clock Either the rising or falling edge of the internal clock is selected as the trigger edge in 1 lt 1 gt Either the single or double edge capture is selected as the trig ger edge in lt gt When lt 1 gt is set to 1 single edge capture Either high or low level input pulse width can be measured To measure the high level input pulse width set the rising edge to TC1CR lt TC1S gt To measure the low level input pulse width set the falling edge to TCICR TCIS When detecting the edge opposite to the trigger edge used to start counting after the timer starts the up counter captures the up counter value into TCIDRB and generates an INTTCI interrupt request The up counter 18 cleared at this time and then restarts counting when detecting the trigger edge used to start counting When lt 1 gt is set to 0 double edge capture Note 1 Note 2
46. fc 13 Hz fc 26 fc 52 fc 104 BRG Transmit clock select 208 fc 416 TC5 Input INTTC5 fc 96 Note 1 When operations are disabled by setting TXE and RXE bit to 0 the setting becomes valid when data transmit or receive complete When the transmit data is stored in the transmit data buffer the data are not transmitted Even if data transmit is enabled until new data are written to the transmit data buffer the current data are not transmitted Note 2 The transmit clock and the parity are common to transmit and receive Note 3 UART2CR1 lt RXE gt and UART2CR1 lt TXE gt should be set to 0 before UART2CR1 lt BRG gt is changed UART2 Control Register2 UART2CR2 7 6 5 4 3 2 1 0 0F99H RXDNC STOPBR Initial value 000 No noise rejection Hysteresis input Selection of RXD input noise Rejects pulses shorter than 31 fc s as noise rejection time Rejects pulses shorter than 63 fc s as noise Write Rejects pulses shorter than 127 fc s as noise only STOPBR top length a lt 2 Note When UART2CR2 lt RXDNC gt 01 pulses longer than 96 fc s are always regarded as signals when UART2CR2 lt RXDNC gt 10 longer than 192 fc 5 and when UART2CR2 lt RXDNC gt 11 longer than 384 fc s Page 150 05 2 Status Register UART2SR 7 6 5 4 3 2 0F98H PERR FERR OERR RBFL TEND TBEP Initial
47. folder down and play c3 MUTE loxtr 2 0 35 OxNN imis on or mute off by mute pin IRESUME 0 36 none OxNN resume play after select mode IINTRO MODE loxtr 2 0x38 DATA OxNN let intro mode cl REPEAT MODE 2 0 39 DATA OxNN setrepeat mode cl _ 2 0 3 OxNN set random mode cl BOOKMARK PLAY 1 0 3 OxNN play from bookmark point cl REPEAT Oxff 2 Ox3f DATA OxNN setor clear repeat mode c3 IPICK UP SELECT loxtr 2 0 40 OxNN pick up sequence number c4 SEND INIT x 0 41 OxNN initial command of pick up c4 SEND EQ DATA Oxff x 10 42 OxNN EQ data of pick up 4 SEND DATA x 0 43 OxNN send RF data of pick up 4 13 TOSHIBA T5CJ3 7G28 F M Specification SEND OK 1 0 44 OxNN pick up data send finish c4 EXT FLASH UPGRADE 1 0 45 OxNN upgrade external flash program UPGRADE 2 0 46 OxNN upgrade host mcu program SYSTEM ON OFF 2 Ox4f DATA OxNN system on or system off INFO TITLE ID3 loxtr 2 0 801 0 001 OxNN mm 193 title information of mp3 wma file c3 GET INFO ARTIST ID3 Oxff 2 0 80 0 01 OxNN id3 artist information of mp3 wma file c3 GET INFO ALBUM ID3 Oxff 2 0 80 0 02 OxNN Jgeti
48. lt 9441 gt 40901 lt 5901 gt 40901 Figure 11 5 8 Bit PWM Mode Timing Chart TC6 Page 130 05 11 3 5 16 Bit Timer Mode TC5 6 In the timer mode the up counter counts up using the internal clock The TimerCounter 5 and 6 are cascad able to form a 16 bit timer When a match between the up counter and the timer register TTREGS TTREG6 value is detected after the timer is started by setting TC6CR lt TC6S gt to 1 an INTTC6 interrupt is generated and the up counter is cleared After being cleared the up counter continues counting Program the lower byte and upper byte in this order in the timer register Programming only the upper or lower byte should not be attempted Note 1 In the timer mode fix TCjCR lt TFFj gt to 0 If not fixed the PWMj and PPGj pins may output a pulse Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediately after programming of TTREGj Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 j 5 6 Table 11 6 Source Clock for 16 Bit Timer Mode Source Clock Maximum Time Setting 1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode
49. when SYSCK 0 or is cleared to 0 when SYSCK 1 Note 2 Don t care TG Timing generator Don t care Note 3 Bits 3 1 and 0 in SYSCR2 are always read as undefined value Note 4 Do not set IDLE and TGHALT to 1 simultaneously Note 5 Because returning from IDLEO SLEEPO to NORMAL1 SLOW 1 is executed by the asynchronous internal clock the period of IDLEO SLEEPO mode might be shorter than the period setting by lt gt Note 6 When IDLE1 2 or SLEEP 1 2 mode is released IDLE is automatically cleared to 0 Note 7 When IDLEO SLEEPO mode is released TGHALT is automatically cleared to 0 Note 8 Before setting TGHALT to 1 be sure to stop peripherals If peripherals not stopped the interrupt latch of peripherals may be set after IDLEO or SLEEPO mode is released Page 17 2 Operational Description 2 2 System Clock Controller T5CL8 2 2 4 Operating Mode Control 2 241 STOP mode STOP mode is controlled by the system control register 1 the STOP pin input and key on wakeup input STOP3 to STOPO which is controlled by the STOP mode release control register STOPCR The STOP pin is also used both as a port P20 and an INTS external interrupt input 5 pin STOP mode is started by setting SYSCRI STOP to 1 During STOP mode the following status is maintained 1 Oscillations are turned off and all internal operations are halted 2 The data m
50. 1 0 0023H TC2S TC2CK TC2M Initial value 00 00 0 NE LEES 000 TC2 source clock select Unit Hz Reserved External clock TC2 pin input TC2M TC2 operating mode 0 counter mode select 1 Window mode Note 1 fc High frequency clock Hz fs Low frequency clock Hz Don t care Note 2 When writing to the Timer Register 2 TC2DR always write to the lower side TC2DRL and then the upper side TC2DRH in that order Writing to only the lower side TC2DRL or the upper side TC2DRH has no effect Note 3 The timer register 2 TC2DR uses the value previously set in it for coincidence detection until data is written to the upper side TC2DRH after writing data to the lower side TC2DRL Note 4 Set the mode and source clock when the TC2 stops 25 0 Note 5 Values to be loaded to the timer register must satisfy the following condition TC2DR gt 1 TC2DR 45 to TC2DR gt 1 at warm up Note 6 If a read instruction is executed for TC2CR read data of bit 7 6 and 1 are unstable Note 7 The high frequency clock fc canbe selected only when the time mode at SLOW2 mode is selected Note 8 On entering STOP mode the TC2 start control TC2S is cleared to 0 automatically So the timer stops Once the STOP mode has been released to start using the timer counter set TC2S again Page 94 05 Lus 9 3 Function The timer counter 2 has three operating modes timer event c
51. Note 2 In the warm up counter mode only upper 8 bits of the timer register TTREGA and are used for match detection and lower 8 bits are not used Note 3 3 4 10 3 9 1 Low Frequency Warm up Counter Mode NORMAL1 NORMAL2 gt SLOW2 gt 1 In this mode the warm up period time from a stop of the low frequency clock fs to oscillation stability is obtained Before starting the timer set SYSCR2 XTEN to 1 to oscillate the low frequency clock When a match between the up counter and the timer register TTREG4 3 value is detected after the timer is started by setting TC4CR lt TC4S gt to 1 the counter is cleared by generating the INTTC4 interrupt request After stopping the timer in the INTTC4 interrupt service routine set SYSCR2 lt SYSCK gt to 1 to switch the system clock from the high frequency to low frequency and then clear of SYSCR2 lt XEN gt to 0 to stop the high frequency clock Table 10 8 Setting Time of Low Frequency Warm Up Counter Mode fs 32 768 kHz Minimum Time Setting Maximum Time Setting TTREG4 3 0100H TTREGA 3 FF00H Example After checking low frequency clock oscillation stability with TC4 and 3 switching to the SLOW1 mode SET SYSCR2 6 SYSCR2 lt XTEN gt lt 1 LD TC3CR 43H Sets TFF3 0 source clock fs and 16 bit mode LD TC4CR 05H Sets TFF4 0 and warm up counter mode Sets the warm up time warm up depends on the oscillator characteris
52. TBT source clock falling edge TBT interrupt enable Normal release mode Yes Interrupt release mode Interrupt processing Execution of the instruction which follows the IDLEO SLEEPO modes start instruction Figure 2 12 IDLEO and SLEEPO Modes Page 25 2 Operational Description 2 2 System Clock Controller T5CL8 Start the IDLEO and SLEEPO modes Stop Disable peripherals such as a timer counter To start IDLEO and SLEEPO modes set SYSCR2 lt TGHALT gt to 1 Release the IDLEO and SLEEPO modes IDLEO and SLEEPO modes include a normal release mode and an interrupt release mode These modes are selected by interrupt master flag IMF the individual interrupt enable flag of TBT and lt gt After releasing IDLEO SLEEPO modes the SYSCR2 lt TGHALT gt is automatically cleared to 0 and the operation mode 15 returned to the mode preceding IDLEO and SLEEPO modes Before starting the IDLEO or SLEEPO mode when the lt gt is set to 1 INTTBT interrupt latch 1s set to 1 IDLEO and SLEEPO modes can also be released by inputting low level on the RESET pin After releasing reset the operation mode is started from NORMAL mode Note IDLEO and SLEEPO modes start release without reference to lt gt setting 1 Normal release mode IMFeEF7eTBTCR TBTEN 0 IDLEO and SLEEPO modes are released by the sour
53. Unless otherwise specified Reference Ground 25 C Characteristics Symbol W Characteristics Supply voltage VDD1 0 3 2 0 03 VOD3 03 Input voltage VIN1 0 3 3 9 2674 12 2010 01 12 TOSHIBA TC94B14MFG 5 Electrical characteristics 5 1 RF core section Unless otherwise specified VDD3 RVDD3 AVDD3 XVDD3 DVDD3L DVDD3R 3 3 V VDD1 2 VDDM1 1 5V 25 Test Characteristics Symbol Test Condition Power supply voltage Guaranteed operation Viens 3 0 3 3 3 6 V supply voltage Reference voltage Reference voltage APC section MDi LDo f 1 ant normal olarit f 1 kHz normal polarit Voltage gain 2 GvaPc2 is porary Operation reference Vi po Vpp 1 3 V voltage 1 normal polarity LDO APCG L Operation reference Vi po Vpp 1 3 V voltage 1 normal polarity LDO APCG H LD off voltage 1 VLDOP1 VDD reference CMD LD OFF PNP Input bias current Wc 11 2 178 mV RF section FPi1 FPi2 FNi1 FNi2 gt RFo Voltage gain amp variable f 100 kHz range 1 _ CD DA mode GVA12RF CMD GVSW 1 Voltage gain 4 variable GyA21RF range 2 CD RW mode f 100 kHz CMD GVSW 0 GvA22RF Frequency characteristic 1 f 9dB point CMD GVSW 1 CD DA mode RFOGAINi 1000 Note 1 Frequency characteristic 2 3 dB point CMD GVSW 0 CD RW mode RFOGAINi 1000 Note
54. When an AD interrupt is used it may not be processed depending on program composition For example if an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 INTADC is being accepted the INTADC interrupt latch may be cleared without the INTADC interrupt being processed The completion of AD conversion can be detected by the following methods 1 Method not using the AD conversion end interrupt Whether or not AD conversion is completed can be detected by monitoring the AD conversion end flag EOCF by software This can be done by polling EOCF or monitoring EOCF at regular intervals after start of AD conversion 2 Method for detecting AD conversion end while a lower priority interrupt is being processed While an interrupt with priority lower than INTADC is being processed check the AD conversion end flag and interrupt latch IL15 If IL15 0 and EOCF 1 call the AD conversion end interrupt processing routine with consideration given to PUSH POP operations At this time if an interrupt request with priority higher than INTADC has been set the AD conversion end interrupt processing routine will be executed first against the specified priority If necessary we recommend that the AD conversion end interrupt processing rou tine be called after checking whether or not an interrupt request with priority higher than INTADC has been set 17 6 2 Analog input pin voltage range
55. enables the watchdog timer Since WDTCRI WDTENC is initialized to 1 during reset the watchdog timer 1s enabled automatically after the reset release Page 67 6 Watchdog Timer WDT 6 2 Watchdog Ti Control atchdog Timer Contro 15018 6 2 3 Watchdog Timer Disable To disable the watchdog timer set the register in accordance with the following procedures Setting the reg Ister in other procedures causes a malfunction of the microcontroller Set the interrupt master flag IMF to 0 Set WDTCR2 to the clear code 4EH Set WDTCR1 lt WDTEN gt to 0 Set WDTCR2 to disable code Note While the watchdog timer is disabled the binary counters of the watchdog timer are cleared Example Disabling the watchdog timer DI 0 LD WDTCR2 04EH Clears the binary counter LDW WDTCR1 0B101H WDTEN lt 0 WDTCR2 lt Disable code Table 6 1 Watchdog Timer Detection Time Example fc 16 0 MHz fs 32 768 kHz Watchdog Timer Detection Time s WDTT NORMAL1 2 mode SLOW DV7CK 0 DV7CK 1 mode 00 2 097 4 4 01 524 288 m 1 1 10 131 072 m 250m 250m 11 32 768 m 62 5 62 5 6 2 4 Watchdog Timer Interrupt INTWDT When WDTCR1 lt WDTOUT gt is cleared to 0 a watchdog timer interrupt request INTWDT is generated by the binary counter overflow A watchdog timer interrupt is the non maskable interrupt which can be accepted regardless of the interrupt mast
56. iid ma ee 22309 RISATR air 10307 al 9x5 So cnn 1 2930 2 3 29308 Q208 1004F 18V 4 i IUE 1 7 seno a EN our e USB HOLD 10K R278 470 507 16V o VCC3 3V I 7 R228 EHE n av 4 3 R297 0 R298 0 E 100K 10s PEE 7 slo 8 v 8 sov doS 398 L303 dor M H R248 10K 2 bvecs 3v H mate 47K 5 REC L C206 04 poop 150K D 18V 1 1 5 a EC313 5 reo r 2079 8263 150K D212 IN4148 nce j 3 100ut 16V m 1 gt azos 8 D I soo p 5 tar E 22K R318 ia 9015 2 5 lt 2 1 sono 8 E 2 47852 0506 em 3
57. 1 or 0 either of which be selected STOP OUTEN P1CRi input Data input PTDR Data output P1DR Output latch Control output Control input Note i2 7100 Figure 5 3 Port 1 and Note The port set to an input mode reads the terminal input data Therefore when the input and output modes are used together the content of the output latch which is specified as input mode might be changed by executing a bit Manipulation instruction Page 52 TOSHIBA P1DR 0001H R W Initial value 0000 0000 P1CR 0009H Initial value 0000 0000 __ control for port Specified for each bit 25 R W Page 53 5 Ports 5 3 Port P2 P22 to P20 15018 5 3 Port P2 P22 to 20 Port P2 15 a 3 bit input output port Itis also used as an external interrupt a STOP mode release signal input and low frequency crystal oscillator con nection pins When used as an input port or a secondary function pins respective output latch P2DR should be set to 1 During reset the P2DR is initialized to 1 A low frequency crystal oscillator 32 768 kHz is connected to pins P21 XTIN and P22 XTOUT in the dual clock mode In the single clock mode pins P21 and P22 can be used as normal input output ports It is recommended that pin P20 should be used as an external interrupt input a STOP mode release signal input or an input port If it is used as an o
58. 1 the serial clock is generated from 5 2 pin after maximum 1 cycle of serial clock frequency During the receive operation The 51025 lt gt 18 cleared to 0 by reading a data SIO2RDB In the internal clock operation the serial clock stops to H level by an automatic wait function when the all of the 8 bit data has been received Automatic wait function is released by reading a received data from SIO2RDB Then receive operation 15 restarted after maximum 1 of serial clock In external clock operation after SIO2SR lt RXF gt is set to 1 the received data must be read from SIO2RDB before the next data shift in operation is finished Page 186 05 me If received data is not read out from SIO2RDB receive error occurs immediately after shift opera tion is finished Then INTSIO2 interrupt request is generated after 51025 lt gt is set to 1 3 Stopping the receive operation There are two ways for stopping the receive operation The way of clearing 5102 lt 51 5 gt When SIO2CR lt SIOS gt is cleared to 0 receive operation is stopped after all of the data is finished to receive When receive operation is finished SIO2SR lt SIOF gt is cleared to 0 In external clock operation SIO2CR lt SIOS gt must be cleared to 0 before SIO2SR lt SEF gt 15 set to 1 by starting the next shift operation The way of setting SIO2CR lt SIOINH gt Rec
59. 1 1 IDDEW mA 4 PH Figure 22 2 Current When an Erase or Program is Being Performed on the Flash Memory Page 271 22 Electrical Characteristics 22 1 Absolute Maximum Ratings T5CL8 22 4 AD Characteristics Vss 0 0 V 4 5 V lt Vpp lt 5 5 V 40 to 85 C Paramete Condition Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range Note 4 Analog input voltage Power supply current of analog refer Vaggr 5 5 V ence voltage Vss 0 0 V Non linearity error Vpp 5 0 V Vss 0 0V VAREF 5 0V Zero point error Full scale error Total error Parameter Condition Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range Note 4 Analog input voltage Power supply current of analog refer Vpp Aypp Varer 4 5 V ence voltage Vss 0 0 V Non linearity error Aypp 2 7 V Vss 0 0 V 2 7 V Zero point error Full scale error Total error Note 1 The total error includes all errors except a quanitization error and is defined as a maximum deviation from the ideal con version line Note 2 Conversion time is defferent in recommended value by power supply voltage Note 3 The
60. 3 After setting up 1 and 2 above set AD conversion start ADRS of AD converter control register 1 ADCCRI to 1 If software start mode has been selected AD conversion starts immediately 4 After an elapse of the specified AD conversion time the AD converted value is stored in AD con verted value register 1 ADCDR1 and the AD conversion finished flag EOCF of AD converted value register 2 ADCDR2 is set to 1 upon which time AD conversion interrupt INTADC is gener ated 5 EOCF is cleared to 0 by a read of the conversion result However if reconverted before a register read although EOCF is cleared the previous conversion result is retained until the next conversion is completed Page 216 05 Example After selecting conversion time 19 5 us at 16 MHz and analog input channel AING pin perform AD con version once After checking EOCF read the converted value store the lower 2 bits in address 0009 EH nd store the upper 8 bits in address 0009FH in RAM The operation mode is software start mode port register approrriately before setting AD port setti port setting converter registers Refer to section port in details LD ADCCR1 00100011B Select AIN3 LD ADCCR2 11011000B Select conversion time 312 fc and operation mode SET ADCCR1 7 ADRS 1 AD conversion start SLOOP TEST ADCDR2 5 EOCF 1 JRS T SLOOP LD A ADCDR2 Read result data LD 9
61. 4 5 to 5 5 V 15 6 us and more VAREF 2 7 to 5 5 V 31 2 us and more AD Converted value Register 1 ADCDR1 7 6 5 4 3 2 1 0 06 ADO5 004 ADO03 02 Initial value 0000 0000 001FH 009 08 007 AD Converted value Register 2 ADCDR2 7 6 5 4 Initial value 0000 Page 213 17 10 bit AD Converter ADC 17 2 Register configuration gi igurati T5CL8 EOCF AD conversi n end fla 0 Before or during conversion 1 Conversion completed Read only ADBF AD conversion BUSY flag 2220 Note 1 The 2 lt gt is cleared to 0 when reading the ADCDR1 Therfore the AD conversion result should be read to ADCDR2 more first than ADCDR1 Note 2 The ADCDR2 ADBF is set to 1 when AD conversion starts and cleared to 0 when AD conversion finished It also is cleared upon entering STOP mode or SLOW mode Note 3 If a read instruction is executed for ADCDR2 read data of bit3 to are unstable Page 214 TOSHIBA kd 17 3 Function 17 3 1 Software Start Mode After setting ADCCRI lt AMD gt to 01 software start mode set ADCCR1I lt ADRS gt to 1 AD conver sion of the voltage at the analog input pin specified by ADCCR1 lt SAIN gt is thereby started After completion of the AD conversion the conversion result is stored in AD converted value registers ADCDRI ADCDR2 and at the same time ADCDR2 lt EOCF gt is set to 1 the AD convers
62. 5101 14 3 Function T5CL8 14 3 Function 14 3 1 Serial clock 14 3 1 1 Clock source The serial clock can be selected by using 5101 lt 5 gt When the serial clock is changed the writing instruction to SIO1CR lt SCK gt should be executed while the transfer is stopped when SIOISR lt SIOF gt 0 1 Internal clock Setting the SIO1CR lt SCK gt to other than 111B outputs the clock shown in Table 14 1 Serial Clock Rate fc 16 MHz fs 32 768kHz as serial clock outputs from SCK1 pin At the before beginning or finishing of a transfer SCK1 pin is kept in high level When writing in the transmit mode or reading in the receive mode data can not follow the serial clock rate an automatic wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is completed shown in Figure 14 2 Automatic wait Function Example of transmit mode The maximum time from releasing the automatic wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from 5 pin 77707070 Automatieally wait 7 SCK1 pin output 501 pin SIO1TDB Automatic wait is released by writing SIOTTDB Figure 14 2 Automatic wait Function Example of transmit mode Table 14 1 Serial Clock Rate fc 16 MHz fs 32 768 2 NORMAL 1 2 IDLE1 2 Mode SLOW1 2 2 SLEEP1 2 Mode
63. 8 12 9 1 4 repeat none 1 10 5 6 8 5 repeat all 4 1 10 7 9 repeat 6 2 11 7 4 8 7 repeat all random 6 2 11 9 8 repeat 3 12 9 6 4 9 repeat all intro 8 3 12 7 5 10 repeat dir 4 1 5 11 12 11 repeat dirtrandom 6 2 7 10 12 12 repeat dirtintro 8 3 9 11 10 Some operation ore ent ill clear play mode setting to default repeat none random off intro off ey are Command or event Repeat mode setting clear Intro setting clear Random setting clear S command S S S auto stop command in mode R command S de ice becomes unready S card becomes unready S S S S S S S S S S S S S S S Rele ant commands are listed bello S REPEAT MODE 0x39 Set repeat none dir all setting INTRO_MODE 0x38 Set intro on off setting RANDOM_MODE 0x3a Set random on off setting lac 5 REPEAT_MODE 0xb7 Returns repeat mode INTRO_MODE 0xb8 Returns intro mode RANDOM_MODE 0xb9 Returns random mode 48 TOSHIBA T5CJ3 7G28 F M Specification bout t e command sequence returning command is not a ac no ledgement for sending command nly ente related mode setting is anged related command returns So if current command is in alid or it donesnt anget e setting no command ill return ut in some occasions for e a
64. CD DA mode Gain balance 2 CD RW mode 2 characteristic 1 fc1TE CD DA mode characteristic 2 2 CD RW mode Output offset voltage 1 CD DA mode VOF1TE Note 6 Output offset voltage 2 Note 6 Output upper limit voltage VOHTE Output lower limit voltage VOLTE Permissible load LMTE Gya21TE Frequency resistance f 1 kHz TEOGAINi 0000 75 00h CMD GVSW f 1kHz TEOGAINi 0000 00h CMD GVSW 0 TEOGAINi 1111 7Fh GVSW 1 80h GVSW 1 AGVA1 TE AGVA2 TE ERE BEBE kHz 33 ERE 29 9dB point CMD GVSW 1 9dB point CMD GVSW 0 VRO reference TPI TNI open TEBC 00h GVSW 1 VRO reference TPI TNI open TEBC 00h CMD GVSW 0 GND reference GND reference V Note 6 These values are those for which offset correction is completed 16 2010 01 12 TOSHIBA TC94B14MFG Characteristics Symbol Test Condition RFRP section RFRPi RFRP input amp gain point with reference to low frequency side on the assumption Detection fae that RFRPI 1 2 Vpp for Vopirp and output amplitude OdB for a 700 kHz sine wave input RFRPI 1 2 Vpp for Vop4np and Detection constant 1 T4RP slew rate Cin gt 1 F for a 5 kHz rectangular wave inpu
65. Figure 2 1 shows T5CL8 memory address map 00004 64 bytes 003F 0040 2048 RAM bytes 08 OF80 OFFF 1000 Flash FFBO FFBF FFCO FFDF FFEO FFFF SFR DBR Flash Special function register includes ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes Data memory Stack Data buffer register includes Peripheral control registers Peripheral status registers Program memory Vector table for interrupts 16 bytes Vector table for vector call instructions 32 bytes Vector table for interrupts 32 bytes Figure 2 1 Memory Address Map 2 1 2 Program Memory Flash The T5CL8 has 61440 bytes Address 1000H to FFFFH of program memory Flash 2 1 3 Data Memory RAM The 5 8 has 2048 bytes Address 0040H to 083FH of internal RAM The first 192 bytes 0040H to 00 of the internal RAM are located in the direct area instructions with shorten operations are available against such an area Page 9 2 Operational Description 2 2 System Clock Controller T5CL8 The data memory contents become unstable when the power supply is turned on therefore the data memory should be initialized by an initialization routine Example Clears RAM to 00H T5CL8 LD HL 0040H Start address setup LD Initial value 00 setup LD BC
66. File extension mp3 Folder name File name length 64bytes maximum ID3 TAG Version2 4 Version2 3 Version2 2 Version1 1 Version1 0 ID3 title artist album The max number of bytes of title artist aloum is 60 60 60 Sampling rate KHz 48 44 1 32 24 22 05 16 11 025 8 Bit rate kbps 8 16 24 32 40 48 56 64 80 96 112 128 144 160 192 224 256 320 Variable bit rates WMA decoder File Windows Media Audio 9 File extension Folder name File name length 64bytes maximum ID3 title artist album The max number of bytes of title artist aloum is 60 60 60 Sampling rate kHz 48 44 1 32 TOSHIBA T5CJ3 7G28 F M Specification Bit rate kbps 32 to 192 CD TEXT Language code English 0x09 Album Maximum 64 bytes Title Maximum 64 bytes Artist Maximum 64 bytes ESP feature Only B14 has ESP feature TOSHIBA T5CJ3 7G28 F M Specification 3 Function outline System function Internal pick up or mechanism selection Update COEF data from HOST or E2PROM Update PRAM for decoder from 2 Rom correction from 2 Standby in and low power comsumption Can connect a external flash and upgrading flash from USB memory Upgrade host MCU softare from USB memory MP3 WMA play function Play Pause FF FR and Stop Play by selecting file or selecting folder File up down Folder up down Get folder or file info Resume play from standby Resume play from mode switch
67. No received data is echoed back to the external controller After receiving the start mark 3AH for in Intel Hex format the device starts data record reception Therefore the received data except 3AH is ignored until the start mark is received After receiving the start mark the device receives the data record that consists of data length address record type write data and checksum The writing data of the data record is written into RAM specified by address Since the device starts checksum calculation after receiving an end record the external controller should wait for the check sum after sending the end record If a receiving error or Intel Hex format error occurs the device enters the halts condition without returning an error code to the external controller The n th 1 and n th bytes contain the checksum upper and lower bytes For details on how to calcu late the SUM refer to 20 8 Checksum SUM The checksum is calculated only when the end record is detected and no receiving error or Intel Hex format error occurs After sending the end record the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device After transmitting the checksum to the external controller the boot program jumps to the RAM address that 15 specified by the first received data record To rewrite data to Flash memory addresses at which data including FFH is already written make s
68. PROOF WEB CLOTH 31 660 0 60 21 00 SCREW 3 0x16mm 30 660 2608 21 00 SCREW 2 6 10 29 650 10006 05 00 SINK 28 660 TPH30101 21 00 SCREW 3 0x10mm 27 660 2608 21 00 SCREW 2 6x8mm 26 850 CEW310007 00 00 WIRE CLAMP 25 600 FIX10031 00 00 __ Patch Plastic PA 66 24 650 0 310004 00 00 BACK COVER CD 23 650 CEM310003 00 00 DECK 22 432 SCD300LK 00 31 MECHANISM 21 660 EPH2005B 27 00 SCREW 206mm 20 410 CEM21008 EB 00 CD Connect fo fo _ _ foo _ _ _ _ __ __ io _ _ lt 18 650 5 885 07 00 00 BRACKET 17 j660 MPH30060 21 00 SCREW 3 0x6 0mm 16 50 00051855 00 00 7808 BRACKET 15 A10 CEM2100A EB 00_ MAIN PCB 14 10 21000 0 10 50 12 650 CEM310001 00 00 MAIN BRACKET 2 13 701 CEM310001 00 00 FIBRE_SHEET 3 11 1000 310003 00 00 PANEL LOCKER 10 650 CEM200010 00 00 SPRING B 09 661 0 04 00 E RING 08 600 CEM310002 00 00 PANEL LOCKER P P 07 650 CEN200009 00 00 SPRING A 06 650 E200011 00 00 05 03 CEM200002 00 00 DUSTPROOF FELT 04 660 2606 24 00 SCREW 2 6x6 NO MATERIAL sit Gum sium 03 660 F
69. Pulse width measurement mode 11 PPG Programmable pulse generate output mode Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note 2 The timer register consists of two shift registers A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte TC1DRAH and TC1DRBH is written Therefore write the lower byte and the upper byte in this order it is recommended to write the register with a 16 bit access instruction Writing only the lower byte TC1DRAL and TC1DRBL does not enable the setting of the timer register Note 3 To set the mode source clock output control and timer F F control write to TC1CR during 15 00 Set the timer F F1 control until the first timer start after setting the PPG mode Page 78 05 Ls Note 4 Auto capture can be used only in the timer event counter and window modes Note 5 To set the timer registers the following relationship must be satisfied TC1DRA gt TC1DRB gt 1 PPG output mode TC1DRA gt 1 other modes Note 6 Set TFF1 to 0 in the mode except PPG output mode Note 7 Set TC1DRB after setting TC1M to the PPG output mode Note 8 When the STOP mode is entered the start control 15 is cleared to 00 automatically and the timer stops After the STOP mode is exited set the TC1S to use the timer counter again Note 9 Use the auto capture function in the operative con
70. SIOINH to 1 Note 2 Don t care Receive buffer register SIO2RDB 7 6 5 4 3 2 1 0 Read only 002BH Initial value 0000 0000 Transmit buffer register SIO2TDB 7 6 5 4 3 2 1 0 Write only 002BH Initial value Note 1 SIO2TDB is write only register A bit manipulation should not be performed on the transmit buffer register using a read modify write instruction Note 2 The SIO2TDB should be written after checking SIO2SR TXF 1 When 5 025 lt gt is 0 the writing data can t be transferred to SIO2TDB even if write instruction is executed to SIO2TDB Note 3 Don t care Page 179 15 Synchronous Serial Interface 5102 15 3 Function T5CL8 15 3 Function 15 3 1 Serial clock 15 3 1 1 Clock source The serial clock can be selected by using 5102 lt 5 gt When the serial clock is changed the writing instruction to SIO2CR lt SCK gt should be executed while the transfer is stopped when SIO2SR lt SIOF gt 0 1 Internal clock Setting the SIO2CR lt SCK gt to other than 111B outputs the clock shown in Table 15 1 Serial Clock Rate fc 16 MHz 6 32 768kHz as serial clock outputs from SCK2 pin At the before beginning or finishing of a transfer SCK2 pin is kept in high level When writing in the transmit mode or reading in the receive mode data can not follow the serial clock rate an automatic wait function is executed to stop the serial clock
71. TBTCR lt DV7CK gt 0 gt gt 1 Serial Clock Baud Rate Serial Clock Baud Rate Serial Clock Baud Rate 3 906 kbps 2048 bps fs 24 2048 bps 62 5 kbps 62 5 kbps Reserved 125 kbps 125 kbps Reserved 250 kbps 250 kbps Reserved 500 kbps 500 kbps Reserved 1 00 Mbps 1 00 Mbps Reserved 2 00 Mbps 2 00 Mbps Reserved Page 162 05 me 2 External clock When an external clock is selected by setting SIOTCR SCK to 111B the clock via the SCK1 pin from an external source is used as the serial clock To ensure shift operation the serial clock pulse width must be 4 fc or more for both H and L levels SCK1 pin gt tSCKL tSCKL SCKH gt 4 fc Figure 14 3 External Clock 14 3 1 2 Shift edge The leading edge is used to transmit data and the trailing edge is used to receive data 1 Leading edge shift Data is shifted on the leading edge of the serial clock falling edge of the SCK1 pin input output 2 Trailing edge shift Data is shifted on the trailing edge of the serial clock rising edge of the SCK1 pin input output SIO1CR SIOS SCK1 Shift register 01234567 X 0123456 X 012345 X 01234 X 0123 Men Shift out 01 pin Leading edge shift Example of MSB transfer 5 1 b Trailing edge shift Example of MSB transfer Figure 14 4 Shift Edge Pa
72. TOSHIBA T5CJ3 7G28 F M Specification Ic 5 6 Contents REDE System feature Function outline System etf 4 1 System configuration 4 2 System block diagram 4 3 BlackPeppers pin layout 4 4 BlackPepper 3 pin assignment and description Communication and command 5 1 Communication protocol 5 2 Command list 5 3 Command data field detals Function details 6 1 Resetand select your piekc up 6 2 Getfirmware version and set fifinware feature 63 Detect USB device SD card _ 6 4 Select a mode 6 5 Read USB SD CD without CD TEXT 6 6 Play up down dir up dir down track number auto change 6 7 Get play information 6 8 Play Pause FF FR playing status change 6 9 Stop 6 10 Play end 6 11 About BlackPepper3 status 6 12 Get File name 6 13 Get Folder name 6 14 Get ID3 information sets etos 6 15 Get bitrate and sample fieaistiey informaiton 6 16 Set repeat intro random play mode 6 17 MSF play function CD DA only 6 18 Select folder or file 6 18 1 Select a folder and inside file t to net herp NAME M DA 6 18 2 Selecta file to get its located folder 6 18 3 Select a folder to get folder inside information 6 19 Bookmark setting and play
73. The counter continues counting The logic level output from the timer F Fj is switched to the opposite state again by the up counter overflow and the counter is cleared The INTTC interrupt request is generated at this time Since the initial value can be set to the timer by lt gt positive and negative pulses can be gen erated Upon reset the timer F Fj is cleared to 0 The logic level output from the PWMj pin is the opposite to the timer F Fj logic level Since PWREGj in the PWM mode is serially connected to the shift register the value set to PWREGj can be changed while the timer is running The value set to during a run of the timer is shifted by the INTTC interrupt request and loaded into PWREGj While the timer is stopped the value is shifted immedi ately after the programming of If executing the read instruction to PWREG during PWM output the value in the shift register is read but not the value set in Therefore after writing to the reading data of is previous value until is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREGj immediately after the INTTCj interrupt request is generated normally in the INTTCj interrupt service routine If the programming of PWREGj and the inter rupt request occur at the same time
74. The following status is maintained during these modes 1 Operation of the CPU and watchdog timer WDT is halted On chip peripherals continue to operate 2 The data memory CPU registers program status word and port output latches are all held in the status in effect before these modes were entered 3 The program counter holds the address 2 ahead of the instruction which starts these modes Starting IDLE1 2 and SLEEP 1 2 modes by instruction CPU and WDT are halted Yes Reset input No Interrupt request Interrupt release mode Interrupt processing Execution of the instruc tion which follows the IDLE1 2 and SLEEP1 2 modes start instruction Reset Normal release mode Figure 2 10 IDLE1 2 and SLEEP1 2 Modes Page 22 05 Start the IDLE1 2 and SLEEP1 2 modes After IMF is set to 0 set the individual interrupt enable flag EF which releases IDLE1 2 and SLEEPI1 2 modes start IDLE1 2 SLEEP1 2 modes set SYSCR2 lt IDLE gt to 1 Release the IDLE 1 2 and SLEEP1 2 modes IDLE1 2 and SLEEP1 2 modes include a normal release mode and an interrupt release mode These modes are selected by interrupt master enable flag IMF After releasing IDLE1 2 and SLEEP 1 2 modes the SYSCR2 lt IDLE gt is automatically cleared to 0 and the operation mode is returned to the mode preceding IDLE1 2 SLEEP1 2 modes IDLE1 2 and SLEEP1 2 modes can also be released by
75. When data are received via the RXD1 pin the receive data are transferred to RDIBUF Receive data buffer At this time the data transmitted includes a start bit and stop bit s and a parity bit if parity addition is specified When stop bit s are received data only are extracted and transferred to RDIBUF Receive data buffer Then the receive buffer full flag UART1SR lt RBFL gt is set and an INTRXD1 interrupt is generated Select the data transfer baud rate using UARTICRI BRG If an overrun error OERR occurs when data are received the data are not transferred to RDIBUF Receive data buffer but discarded data in the RDIBUF are not affected Note When a receive operation is disabled by setting UART1CR1 lt RXE gt bit to 0 the setting becomes valid when data receive is completed However if a framing error occurs in data receive the receive disabling setting may not become valid If a framing error occurs be sure to perform a re receive operation Page 144 05 Hn 12 9 Status Flag 12 9 1 Parity Error When parity determined using the receive data bits differs from the received parity bit the parity error flag UARTISR lt PERR gt is set to 1 The UARTISR PERR is cleared to 0 when the RDIBUF is read after reading the UARTISR 1 UART1SR lt PERR gt After reading UART1SR then RD1BUF clears PERR INTRXD1 interrupt Figure 12 5 Generation of Parity Error 12 9 2 Framing Error When 0
76. ao SL ak SE DEC ERASTA to OFFFH to 1FFFH to 2FFFH to 3FFFH to 4FFFH to 5FFFH to 6FFFH The end address of the to to 8FFFH to 9FFFH to AFFFH to BFFFH to CFFFH to DFFFH to EFFFH to FFFFH ERAEND Note When the sector erase is executed for the area containing no flash cell T5CL8 stops the UART commu nication and enters the halt condition Page 260 T5CL8 eae aui 10 jonposd xuejq pue 1 5 ay jo SNIS ue jo qi yonpold Jo eunue ue jo enue ue jo 5 svn svn sseJppe 5 y svn 1 5 ejqesiq 20 14Flowchart TOSHIBA HOOOL X 9 HOOOL jeddr ayuyuy 018 4095 eunue uo 9523 diuo Sse90Jd AV 5990 9 peiqesip Ajunoes use 4 Ajnoes
77. before reading SBIDBR Set BC to 001 before reading SBIDBR Figure 16 12 Termination of Data Transfer in Master Receiver Mode 16 6 3 2 When the MST is 0 Slave mode In the slave mode a serial bus interface circuit operates either in normal slave mode or in slave mode after losing arbitration In the slave mode the conditions of generating INTSBI interrupt request are follows At the end of acknowledge signal when the received slave address matches to the value set by the I2CAR At the end of acknowledge signal when a GENERAL CALL is received At the end of transferring or receiving after matching of slave address or receiving of GENERAL CALL A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode And an INTSBI interrupt request occurs when word data transfer terminates after losing arbitration The behavior of INTSBI interrupt request and PIN after losing arbitration are shown in Table 16 3 Table 16 3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration When the Arbitration Lost Occurs during Trans When the Arbitration Lost Occurs during Trans mission of Slave Address as a Master mission of Data as a Master Transmit Mode INTSBI interrupt INTSBI interrupt request is generated at the termination of word data request When the slave address matches the value set by I2CAR the PIN is cleared to 0 by generating of INTSBI interrupt reque
78. h 104 15K RHAIOR 5 4 55 P 4 gt age H ae d i UNE RL 7 40 C435474 4sse 9013 LINE RR 5 A B RAO6A 0 9 AUX2 ROUT Ecko 5 5 100uF 16V RATTIOK f i C436 2 5 5 8 5 zl 3 I 8 9301 22K LL 5 E R455 22K 8 8 8 5 TI 3 i 3 EM i 5 8 C453 R457 22K 5 m M s 455 100 M Ld Zr OUT R453 220 H 8 456 ono i 5 45 A eso Es 5 NC EC302 i CON201 0302 on gt 1OuF 25V 104 2 5 R4612K2 CN22P H UNE FR 5 m he GR t ys 2 ji bist an as MAT 47 T PM ES 5 as o R451 C454 4 5 R462 2 2 wey 20203 NC Bs lt 3 Line output 407 7 il 0254 m La aso E 4558 m 8772 ruen 5 E or d R307 E 8 t x 8 C255 1 0 ou ie 47K R304 2K2 E noe 5 m voosv L AUX 4 R306 22K 0 H BT 8 1 vo R303 R305 2K2 1 40 MES ian H x m JR um fl vs ui
79. is sampled as the stop bit in the receive data framing error flag UART1SR lt FERR gt is set to 1 The UARTISR FERR is cleared to 0 when the RDIBUF is read after reading the UARTISR RXD1 pin Final bit 1 UART1SR lt FERR gt After reading UART1SR then RD1BUF clears FERR INTRXD1 interrupt Figure 12 6 Generation of Framing Error 12 9 3 Overrun Error When all bits in the next data are received while unread data are still in RDIBUF overrun error flag UART1SR lt OERR gt is set to 1 In this case the receive data is discarded data in are not affected UARTISR lt OERR gt is cleared to 0 when the RDIBUF is read after reading UARTISR Page 145 12 Asynchronous Serial interface UART1 12 9 Status Fla METRE T5CL8 UART1SR lt RBFL gt Shift register RD1BUF UART1SR lt OERR gt 1 After reading UART1SR then RD1BUF clears OERR 1 INTRXD1 interrupt Figure 12 7 Generation of Overrun Error Note Receive operations are disabled until the overrun error flag 15 lt gt is cleared 12 9 4 Receive Data Buffer Full Loading the received data in RDIBUF sets receive data buffer full flag UARTISR lt RBFL gt to 1 The UART1SR lt RBFL gt is cleared 0 when the RDIBUF is read after reading the UARTISR RXD1 pin Final bit RD1BUF yyyy XXXX 1 1 UART1SR lt RBFL gt ij After reading UART1SR then 1 RD1BUF clears RBFL 1 IN
80. o E S 7 Tt rer 425 08 n Ras 22 8 R305 C423 Cae _ _ d 2 RATZ 2 3 iUe 454 La JRA C 4 DERE 479 6435 ff E R273 3 mE au R488 22 2 p 8405 ROSA C460 R492 CABS 5 5 C458 E MS case Se pja COLE E OR 84 En R471 M APO R455 0455 Was Ra R254 8 2 t 0 mw e C428 Raso O 8 570 REDE E 299 ee 29 me hr xx SS aL 0303 R38 e e 292 999 Las Re J amp ry R313 Ne 5 R457 C464 gg 022 453 ono 0407 gig 15 20 mE gt gt 5 x S 7 R312 Sm aL 5 E C208 8 g 0405 L 5 5 5 Ls 8 N 204 271 S 5 ISTE 2 8 8528 55 T 5 eT non x El zo tu s zm cx 8 E cese c DED R423 0202 5214 d B R401 272 10902 gt 4 cn 8 8 Q 5 RD 56 9223 8 gi 1 R224 m gor 8274 2 R220 c251 0 ROOT S 2227 88 R610 Rag e 217 Bs EN 8 Z R565 R221 cade 0602 5 zem 605 2 us B Res e603 T pur me Oros i 5665 33 R260 RASH R649 5068 0 g QUEU
81. ust keep aiting evice class t pe checking ust keep aiting evice is rea tart rea process uu Uu river encounters fatal error or over current Har are reset BlackPepper3 B evice etecting is error ispla B error B class t pe is not e supporte ispla unkno B memor is not rea ccurs hen car is remove from car ust keep aiting ispla no rea er tisiPo an cannot esupporte ispla not support others o efinition ove ispla characters in action column is ust ae ample for reference se uence HOST USB SD_DET_STATUS E0 USB SD_DET_STATUS E0 6 4 Select a mode Different with before start reading elevant commands are listed bellow 5 Blac USB device status is changed new status will be returned automatically If SD card status is changed new status will be returned automatically host should select wor mode before reading rocess because need are something SELECT MODE 0x30 Select a wor mode D USB or SD e er S 30 TOSHIBA T5CJ3 7G28 F M Specification MODE SEL 0 80 he ac nowledgement for S D command ommand se uence HOST BP3 Select a mode before start SELECT MODE 30 reading in this mode MODE SEL OK 80 6 5 Read USB SD CD without CD TEXT fter selecting a mode then start a reading rocess b send command hast
82. 00 00 BU Eject 57 600 CEMS10012 00 00 VOL REFI m TOR RACKET B w 55 600 CEM310026 00 00 BU 5 5 5 56 600 CEM310027 00 00 BU 5 2 54 650 CEM20011 00 00 EASE SPRING 53 600 CEM310029 00 00 BUTT ELEASE 52 600 CEM310014 00 00 BU 51 600 0EM310015 00 00 BU 50 600 CEM310028 10 00 SE 49 600 CEM310020 00 00 SE ooo 48 600 CEM310021 00 00 5 5 47 O CENGIO018 00 00 46 600 CEM310019 00 00 BU DIAGRAM 45 600 CEN310024 00 00 BU 43 600 CEM310051 00 00 58 over 42 705 CEM200001 00 00 PC SHEET T 0 15mm gt 41 600 CEM310006 00 00 FRONT PANEL 40 600 CEM310008 00 00 LENS USB 39 600 CEM310016 00 00 KNOB COVER A 38 600 CEMS10013 00 00 REFLECTOR 37 00 CEM310017 00 00 KNOB COVER B 36 600 CEM310010 00 00 KNOB COVER LENS M M 5 44 600 310025 00 00 BU M 7 5 M 35 AH4 CEVST0001 00 10 RUBBER Ring 34 650 CEM200005 00 00 HALF SLEEVE 33 650 CEM310002 00 00 TOP COVER 32 103 210001 00 00 005
83. 07FFH SRAMCLR LD HL A INC HL DEC BC JRS F SRAMCLR 2 2 System Clock Controller The system clock controller consists of a clock generator a timing generator and a standby controller 2 2 1 Timing generator control register Clock pee generator High frequency Timing clock oscillator generator System clocks Standby controller _ System control registers Low frequency clock oscillator Clock generator control Figure 2 2 System Colck Control Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware It contains two oscillation circuits One for the high frequency clock and one for the low frequency clock Power consumption can be reduced by switching of the standby controller to low power operation based on the low frequency clock The high frequency fc clock and low frequency fs clock can easily be obtained by connecting a resonator between the XIN XOUT and XTIN XTOUT pins respectively Clock input from an external oscillator is also possible In this case external clock is applied to XIN XTIN pin with XOUT XTOUT pin not connected Page 10 05 High frequency clock E Low frequency clock XIN XOUT XIN XOUT XTOUT XTIN XTOUT Open Open a Crystal Ceramic b External oscil
84. 0x07 SET_FIRMWARE 0x83 Set firmware feature before starting reading process Host side can check receiving is right or not by comparing with FIRMWARE FEATURE command received 21 TOSHIBA T5CJ3 7G28 F M Specification BlackPepper3 gt HOST FIRMWARE_VERSION 0xF701 Byte0 of data field 0x01 FIRMWARE_FEATURE 0xF700 Byte0 of data field 0x00 About USB SD folder searching order in command SET_FIRMWARE 0x83 there is 1 bit to select the searching order About the explanation of searching order refer to bellow example This is the original structure dir 1 EI e 4 in 3 sb 4 file 4 1 file 2 O 3 7 B dir 5 dir 6 dir 7 Pre rf file 5 file 6 dir 8 dir 9 2 file 9 file 8 9 file 10 After BlackPepper3 reading the folder number assigned refer to bellow table folder name Assign folder number Assign folder number Set bit to 0 Set bit to 1 Root Folder number 1 Folder number 1 Dir 1 Folder number 2 Folder number 2 Dir 2 Folder number 5 Folder number 3 Dir 3 Folder number 8 Folder number 4 Dir 4 Folder number 10 Folder number 5 28 TOSHIBA T5CJ3 7G28 F M Specification Dir 5 Folder number 3 Folder number 6 Dir 6 Folder number 6 Folder number 7 Dir 7 Folder number 9 Folder number 8 Dir 8 Folder number 4 Folder number 9 Dir 9 Folder number 7 Folder number 10 Another point need
85. 0x83 byte 0 set 0 don t output SPDIF set 1 SPDIF 0000 1000b use PRAM from E2ZPROM set 0 use internal PRAM set 1 use PRAM from E2PROM 0001 0000b enable or disable read iPod as MSC device set 0 don t read iPod as MSC device set 1 iPod as MSC device PARTII 0x01 mixed disc 0x02 0x03 CD ROM 0x04 SD card 0x05 USB device MSC 0x06 USB device MTP partial device 0x07 USB device iPod DEVICE TYPE 0x82 byte 0 0x16 USB device MTP not partial device for MTP partial device FF FR bookmark AB repeat resume play set position and play are supported 20 TOSHIBA T5CJ3 7G28 F M Specification 0x00 no disc 0x01 disc toc read error 0x02 disc not support 0x03 disc play error 0x04 no definition 0x05 no SD card insert 0x06 SD card read error 0x07 no USB device insert 0x08 USB read error ERROR CODE 0x83 byte 0 0x09 no mp3 wma file in SD card 0 mp3 wma file in USB device MSC 0 0 no mp3 wma file in USB device MTP Ox0c no mp3 wma file in USB device iPod 0x30 USB is not ready external flash upgrade mcu upgrade 0x31 h16 s24 file open failed external flash upgrade mcu upgrade ERROR_CODE UPGRADE 0x83 byte 0 0x32 h16 s24 file format error external flash upgrade only 0x33 flash write error external flash upgrade only 0x00 play mode 0x01 stop mode 0x02 pause mode 0x03 pause mode is relea
86. 1 SDA Master 1 SDA pin becomes 1 after losing arbitration 2 427 Figure 16 7 Arbitration Lost The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of the SCL line If the levels are unmatched arbitration is lost and the AL in SBISRB is set to 1 Page 203 16 Serial Bus Interface I2C Bus Ver D 581 16 5 I2C Bus Control T5CL8 When the AL is set to 1 the MST and are cleared to 0 and mode is switched to a slave receiver mode Thus the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set to 1 AL is cleared to 0 by writing data to the SBIDBR reading data from the SBIDBR writing data to the SBICRB SCL pin Master A soan VOAN pan Dan ovn onn Toa SCL pin 1 2 z4x 5x 777 97 Vl ul ul 7 Vl d 4 Master B Stop clock output SDA pin XD6B Releasing SDA pin SCL pin to high level as losing arbitration AL MST Accessed to SBIDBR SBICRB INTSBI Figure 16 8 Example of when Serial Bus Interface Circuit is a Master B 16 5 11Slave address match detection monitor In the slave mode the AAS Bit2 in SBISRB is set to 1 when the received data is GENERAL CALL the received data matches the slave address s
87. 1 Output upper limit voltage VOHRF GND reference V Output lower limit Permissible load Note 1 Design guarantee 19 2010 01 12 TOSHIBA TC94B14MFG Characteristics Symbol Test Condition ircuit AGC RFEQ section gt RFEQo Voltage gain 1 Note 2 GV1AGC RFGC 80h Voltage gain 2 Note 2 100 kHz RFGC EIC Voltage gain 3 Note 2 gain 3 Note Voltage gain 3 Note 2 7Fh Peak frequency 1 f CMD D7CO1E Boost Max x1 speed mode C1EQ RFGC 00h Peak frequency 2 CMD D7C11E Boost Max x2 speed mode fc2EQ 00h Group delay difference CMD D7001E RFGC 00h 1101 speed mode GD1EQ 100 700 kHz 100kHz step Note 3 Peak gain difference 21 x2 speed mode fVoEQ Note 4 Output slew rate Output slew rate rate SRAGC SRacc Crreqo 20pF CRFEQO Crreqo 20pF 00000 pF Output upper limit voltage VOHAGC GND reference Output lower limit Permissible load ETI resistance ETI Note 2 These values were measured in the AGC AMP section f 100 kHz reference RFGC 00h CMD D7C11E Boost Max Peak gain difference f 100 kHz reference RFGC 11 x1 mode 4 Note 3 Group delay difference of Peak Bottom 100 to 700KHz at x1 speed mode Note 4 These values were measured in the RFEQ section Design guarantee 14 2010 01 12 TOSHIBA TC94B
88. 5 6219 Weight 0 6 g Typical 28 2010 01 12 TOSHIBA About solderability following conditions were confirmed e Solderability 1 Use of Sn 37Pb solder Bath solder bath temperature 230 C dipping time 5 seconds the number of times once use of R type flux 2 Use of Sn 3 0Ag 0 5Cu solder Bath solder bath temperature 245 dipping time 5 seconds the number of times once use of R type flux 29 TC94B14MFG 2010 01 12 TOSHIBA TC94B14MFG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates collectively TOSHIBA reserve the right to make changes to the information in this document and related hardware software and systems collectively Product without notice This document and any information herein may not be reproduced without prior written permission from TOSHIBA Even with TOSHIBAS written permission reproduction is permissible only if reproduction is without alteration omission Though TOSHIBA works continually to improve Product s quality and reliability Product can malfunction or fail Customers responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware software and Systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life bodily injury or damage to property including data loss or corruption
89. 5 d To check whether there is wearing and scratch of the USB defective shrapnel and pin of the USB e To check the oscillation frequence of the 7 pin of main board 604 should be 32 768KHZ f To check whether there is any contamination and bad contact on the male female connector of the panel and main board If necessary can exchange the panel to test whether the defective is occurred by the unit or panel a To check the SOURCE shoule be in MP3 LINK mode b To check the AUX IN input signal D am c To check whether there is any contamination and bad contact on the male female connector of the panel and main board If necessary can exchange the panel to test whether the defective is occurred by the unit or panel TOSHIBA T5CJ3 7G28 F M Specification CD SD USB MP3 WMA ESP player system 15CJ3 7G28 F M Technical Specification Ver 1 0 2010 4 7 This product is a strategic material or service as defined by the Foreign Exchange and Trade Control Laws Permission must be gained under these laws before the product is exported Toshiba Corp e The contents of this specification are subject to change without notice technical information provided in this document is for describing typical operations and applications of the product and does not guarantee the intellectual or other property rights of Toshiba Corp or third parties nor constitutes an approval of the right of execution
90. ALS 1 With a free data format the slave address and the direction bit are not recognized and they are processed as data from immediately after start condition 16 5 5 Master slave selection To set a master device the MST 7 in SBICRB should be set to 1 To set a slave device the MST should be cleared to 0 When a stop condition on the bus or an arbitration lost is detected the MST 15 cleared to 0 by the hard ware 16 5 6 Transmitter receiver selection To set the device as a transmitter the in SBICRB should be set to 1 To set the device as a receiver the TRX should be cleared to 0 When data with an addressing format is transferred in the slave mode the is set to 1 by a hardware if the direction bit R W sent from the master device is 1 and is cleared to 0 by a hardware if the bit is 0 In the master mode after an acknowledge signal is returned from the slave device the is cleared to 0 by a hardware if a transmitted direction bit 1s 1 and is set to 1 a hardware if it is 0 When an acknowledge signal is not returned the current condition is maintained Page 201 16 Serial Bus Interface I2C Bus Ver D 581 16 5 I2C Bus Control T5CL8 When stop condition the bus or an arbitration lost is detected the TRX is cleared to 0 by the hardware Table 16 2 TRX changing conditions in each mode shows T
91. Before creating and producing designs and using customers must also refer to and comply with a the latest versions of all relevant TOSHIBA information including without limitation this document the specifications the data sheets and application notes for Product and the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook and b the instructions for the application that Product will be used with or for Customers are Solely responsible for all aspects of their own product design or applications including but not limited to a determining the appropriateness of the use of this Product in such design or applications b evaluating and determining the applicability of any information contained in this document or in charts diagrams programs algorithms sample application circuits or any other referenced documents and c validating all operating parameters for such designs and applications TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS PRODUCT DESIGN OR APPLICATIONS Product is intended for use in general electronics applications e g computers personal equipment office equipment measuring equipment industrial robots and home electronics appliances or for specific applications as expressly stated in this document Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and or reliability and or a malfunction or failure of which may ca
92. CD USB SD mode switch Repeat 1 folder all Play Random play folder random play depend on repeat area Intro play Repeat play A B within one song Bookmark play CD audio track play function Play Pause FF FR and Stop Play by selecting track Track up down Resume play from standby Resume play from USB SD mode CD TEXT function MSF play Bookmark play Repeat 1 All Play Random play Intro play Repeat play A B with in one song Data track will be auto skipped TOSHIBA T5CJ3 7G28 F M Specification 4 System composition 4 1 System configuration 32 bit MCU with USB host controller T5CJ3 7G28 F M CD processor MP3 WMA decoder and audio DAC system B13 TC94B13FG 002 B14 TC94B14MFG 202 Pickup and CD mechanism Sanyo DA11 1x speed or 2x speed Sany DA23 1x speed or 2x speed Samsung 55 1 speed or 2x speed Tanashin 2002 2x speed Tanashin 2007 2x speed Shinny IS68 2x speed Shinwa CLCO1 2x speed Shinwa CLCO8 2x speed CP2 2x speed TOSHIBA T5CJ3 7G28 F M Specification 4 2 System block diagram driver TC94B13FG 002 BlackPepper3 TC94B14MFG 202 T5CJ3 7G28 F M Host MCU TOSHIBA T5CJ3 7G28 F M Specification 4 3 BlackPepper3 pin layout lt oi es 2 lt lt lt agog 2 6016 20 sosa sum dowtitooo05bc522z0 o m o 12 gt is 75
93. Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm _ 12 0 0 2 10 0 0 2 5 12 0 0 2 45 0 055 Page 275 23 Package Dimensions T5CL8 Page 276 This is a technical document that describes the operating functions and electrical specifications of the 8 bit microcontroller series TLCS 870 C LSI Toshiba provides a variety of development tools and basic software to enable efficient software development These development tools have specifications that support advances in microcomputer hardware LSI and can be used extensively Both the hardware and software are supported continuously with version updates The recent advances in CMOS LSI production technology have been phenomenal and microcomputer systems for LSI design are constantly being improved The products described in this document may also be revised in the future Be sure to check the latest specifications before using Toshiba is developing highly integrated high performance microcomputers using advanced MOS production technology and especially well proven CMOS technology We are prepared to meet the requests for custom packaging for a variety of application areas We are confident that our products can satisfy your application needs now and in the future TOSHIBA TC94B14MFG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic SiP System in Package LSI of Single Chip Digital Servo Processor incorpo
94. External Clock 15 3 1 2 Shift edge The leading edge is used to transmit data and the trailing edge is used to receive data 1 Leading edge shift Data is shifted on the leading edge of the serial clock falling edge of the SCK2 pin input output 2 Trailing edge shift Data is shifted on the trailing edge of the serial clock rising edge of the SCK2 pin input output SIO2CR lt SIOS gt SCK2 Shift register 01234567 4 0123456 X 012345 X 01234 X 0123 Men Shift out SO2 pin Leading edge shift Example of MSB transfer siozcr lt sios gt SCK2 pin b Trailing edge shift Example of MSB transfer Figure 15 4 Shift Edge Page 181 15 Synchronous Serial Interface 5102 15 3 Functi unction T5CL8 15 3 2 Transfer bit direction Transfer data direction be selected by using SIO2CR lt SIODIR gt The transfer data direction can t be set individually for transmit and receive operations When the data direction is changed the writing instruction to SIO2CR lt SIODIR gt should be executed while the transfer is stopped when SIO2CR lt SIOF gt 0 SIO2CR SIOS SCK2 Shift out a MSB transfer SIO2CR lt SIOS gt SCK2 Shift out b LSB transfer Figure 15 5 Transfer Bit Direction Example of transmit mode 15 3 2 1 Transmit mode 1 MSB transmit mode MSB transmit mode is selected by setting SIO2CR lt SIODIR gt to 0 in wh
95. Generation of Transmit End and Transmit Data Buffer Empty Page 147 12 Asynchronous Serial interface UART1 12 9 Status Fla rasis T5CL8 Page 148 05 13 Asynchronous Serial interface UART2 13 1 Configuration 1 UART control register 1 Transmit data buffer Receive data Buffer UART2CR1 TD2BUF RD2BUF i MPX Multiplexer 5 5 5 lt j eat o INTIXDZ o Noise rejection 9 circuit RXD2 TXD2 INTRXD2 Transmit receive clock Y fc 2 i B 1 2 5 X c foz fc 13 A 5 fc 26 B A A fc 52 C 04 gt Y 2 fc 416 5 UART status register UART control register 2 fc 96 H 1 1 Baud rate generator Figure 13 1 UART2 Asynchronous Serial Interface Page 149 13 Asynchronous Serial interface UART2 13 2 Control T5CL8 13 2 Control UART2 is controlled by the UART2 Control Registers UART2CRI UART2CR2 The operating status can be monitored using the UART status register UART2SR UART2 Control Register1 UART2CR1 7 6 5 4 3 2 1 0 0F98H TXE STBT EVEN BRG Initial value 0000 0000 0 Disable Transfer operation 4 Enable 0 Disable Receive operation 4 Enable 0 1 bit STBT Ti it stop bit length EM DUNT EARS 0 Odd bered parit EVEN Even numbered parity e M 1 Even numbered parity 0 N it Parity addition y 1
96. IMF 1 Page 38 05 me 3 3 Interrupt Sequence An interrupt request which raised interrupt latch is held until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction Interrupt acceptance sequence requires 8 machine cycles 2 us 16 MHz after the completion of the current instruction The interrupt service task terminates upon execution of an interrupt return instruction RETI for maskable interrupts or RETN for non maskable interrupts Figure 3 1 shows the timing chart of interrupt acceptance processing 3 3 1 Interrupt acceptance processing is packaged as follows The interrupt master enable flag IMF is cleared to 0 in order to disable the acceptance of any fol lowing interrupt b The interrupt latch IL for the interrupt source accepted is cleared to 0 c The contents of the program counter PC and the program status word including the interrupt master enable flag IMF are saved Pushed on the stack in sequence of PSW IMF PCH PCL Mean while the stack pointer SP is decremented by 3 d The entry address Interrupt vector of the corresponding interrupt service program loaded on the vec tor table is transferred to the program counter e The instruction stored at the entry address of the interrupt service program is executed Note When the contents of PSW are saved on the stack the contents of IMF are also saved Interrupt service
97. Line output Amp IC Fornt Line output Amp IC Motor Driver IC 5 5888 s ZN 22pin Connector SD MMC BOARD Reset SW 22pin Connector Panel Board POWER 9V SERVO 8V CIRCUIT DIAGRAM MAIN BOARD R658 OR R663 06049015 R662 OR DVCC3A R629 10K sav RC RST 8 2 gt Z ag 122253 21 PWE p wi s H ww mim L57805 8 Aic penus 3 a RT IBS R640 100 2 B uS 8 6648 keeps 2 S EA EIE x E g yl Fg x 5 REEL S 5 EX mum E T D DATAQUT A4 1604 1 22 52 zn asoc nnw 5 5 9 _ ___ _ 50_ cs 82 d1 i 8 s aran ac 2 m pan 5 80 94 30 ne 4 4 E 2 ua LR LE U S B be SORTED E
98. Make sure the analog input pins AINO to AIN15 are used at voltages within VAREF to VSS If any voltage outside this range is applied to one ofthe analog input pins the converted value on that pin becomes uncertain The other analog input pins also are affected by that 17 6 3 Analog input shared pins The analog input pins AINO to AINI5 are shared with input output ports When using any of the analog inputs to execute AD conversion do not execute input output instructions for all other ports This is necessary to prevent the accuracy of AD conversion from degrading Not only these analog input shared pins some other pins may also be affected by noise arising from input output to and from adjacent pins 17 6 4 Noise Countermeasure The internal equivalent circuit of the analog input pins is shown in Figure 17 5 The higher the output impedance of the analog input source more easily they are susceptible to noise Therefore make sure the out put impedance of the signal source in your design is 5 or less Toshiba also recommends attaching a capac itor external to the chip Internal resistance Analog comparator 5 typ issi i Internal capacitance Permissible signal source impedance 12 pF 5 Note i 15100 DA converter Figure 17 5 Analog Input Equivalent Circuit and Example of Input Pin Processing Page 219 17 10 bit AD Converter ADC 17 6 Precautions about AD Converte
99. Match detect Counter clear INTTC2 interrupt Figure 9 4 Window Mode Timing Chart Page 98 05 pem 10 8 Bit TimerCounter TC4 10 1 Configuration PWM mode L2 11 3 interrupt request fc 2 5 2 A cop a P fc 2 C 1072 D fs fc 2 48 Bit made DH a B gt fc G o 16 bit PDO4 PWM4 Timer Event TCAM mode Counter mode 45 Timer F F4 4 4 PWREG4 PWM PPG mode Decodegw PDO PWM mode C 16 bit mode E CR TFF4 gt gt wrres 2 1 or fs 2 gt Clear pda request C PDO mode 2 D gt I EE gt d Toggle c 2 16 bit mode Q gt PDO3 PWM3 Event Couter mode pin TC3M TC3s TER Timer F F3 TFF3 TC3CR TTREG3 PWREG3 O 16 bit mode T d Figure 10 1 8 Bit TimerCounter 3 4 Page 99 10 8 Bit TimerCounter TC3 4 10 1 Configuration igurati T5CL8 10 2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register TC3CR and two 8 bit timer registers TTREG3 PWREG3 TimerCounter 3 Timer Register TTREG3 7 6 5 4 3 2 1 0 0014H R W Initial value 1111 1111 PWREG3 7 6 5 4 3 2 1 0 0018H R W Initial value 1111 1111 Note 1 Do not
100. Nothing transmitted m th 1 byte Intel Hex format Binary Modified baud rate Note 2 n th 2 byte Modified baud rate n th 1 byte Modified baud rate OK SUM Upper byte Note 3 Error Nothing transmitted n th byte Modified baud rate OK SUM Lower byte Note 3 Error Nothing transmitted The program jumps to the start address of RAM in which the first transferred data is written Note 1 xxH x 3 indicates that the device enters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Note 2 Refer to 20 9 Intel Hex Format Binary Note 3 Refer to 20 8 Checksum SUM Note 4 Refer to 20 10 Passwords Note If addresses from FFEOH to FFFFH are filled with the passwords not compared because the device is consid ered as a blank product Transmitting a password string is not required Even in the case of a blank product it is required to specify the password count storage address and the password comparison start address Transmit these data from the external controller If a password error occurs due to incorrect password count storage address or password comparison start address T5CL8 stops UART communication and enters the halt condition Therefore when a password error occurs initialize T5CL8 by the RESET pin and reactivate the serial ROM mode Note 6 After transmitting a password string the external controller must
101. Operational Description 2 2 System Clock Controller 2 3 T5CL8 IDLE1 mode In this mode the internal oscillation circuit remains active The CPU and the watchdog timer are halted however on chip peripherals remain active Operate using the high frequency clock IDLE1 mode is started by SYSCR2 lt IDLE gt 1 and IDLE1 mode is released to NORMALI mode by an interrupt request from the on chip peripherals or external interrupt inputs When the IMF Interrupt master enable flag is 1 Interrupt enable the execution will resume with the acceptance of the interrupt and the operation will return to normal after the interrupt service is completed When the IMF 15 0 Interrupt disable the execution will resume with the instruction which follows the mode start instruction IDLEO mode In this mode all the circuit except oscillator and the timer base timer stops operation This mode is enabled by SYSCR2 lt TGHALT gt 1 When IDLEO mode starts the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT Then upon detecting the falling edge of the source clock selected with lt gt the timing generator starts feeding the clock to all peripheral circuits When returned from IDLEO mode the CPU restarts operating entering NORMALI mode back again IDLEO mode is entered and returned regardless of how lt gt is set When IMF
102. P66 AING STOP2 P54 C11 56 250 P65 AIN5 STOP1 P30 TT 57 24 P64 AINA STOPO P31 C58 2301 P63 AIN3 P3211 59 22 01 P62 AIN2 P3360 21 P61 AIN1 1 20 111 P60 AINO P35 62 19 AVDD P36 18 0 VAREF P37 1T 64 17 2 L IL NZEFOTA 525 58 5568 g rc e x E amp wn D m Figure 1 1 Pin Assignment Page 3 1 3 Block Di ock Diagram T5CLS 1 3 Block Diagram High frequency clock CPU TLOS 870 0 10 bit AD oscillator Converter 16ch Low frequency clock HSIO 2ch oscillator M Standby Controller Key On Wakeup Interrupt Controller 16Bit Timer Counter TC1 Time Base Timer 16Bit Timer Counter TC2 BOOTROM 2048Bytes 8bit Timer Counter 4ch RAM 2048Bytes UART 2ch FLASH 61440Bytes Figure 1 2 Block Diagram Page 4 TOSHIBA 1 4 Pin Names and Functions T5CL8 The T5CL8 has MCU mode parallel PROM mode and serial PROM mode Table 1 1 shows the pin functions in MCU mode The serial PROM mode is explained later in a separate chapter Table 1 1 Pin Names and Functions 1 3 Pin Name Pin Number Input Output Functions PORTO7 External interrupt 2 input 6 Serial clock input output 1 5 Serial data output 1 PORT04 Serial data input 1 E
103. P6CR2 should be set to 0 When is 1 the content of the corresponding output latch is read by reading P6DR Table 5 4 Register Programming for Multi function Ports Programmed Value Function P6DR P6CR1 P6CR2 STOPKEN LC e 22 Lo LLL Note Asterisk indicates 1 or 0 either of which can be selected Table 5 5 Values Read from P6DR and Register Programming Conditions Values Read from P6DR P6CR1 P6CR2 1 Output latch contents Page 59 5 Ports 5 7 Port P6 P67 to P60 P6CR2i P6CR2i input P6CR1i P6CRi1i input Control input Data input P6DRi Data output P6DRi STOP OUTTEN Analog input AINDS SAIN Key on wakeup STOPKEN P6CR2j P6CRQj input PeCR1j P6CR1j input Data input Data output P6DRj STOP OUTTEN Analog input AINDS SAIN T5CL8 a P63 to P60 SM gt JP6j b P67 to P64 Note 1 1 3 0 7 104 3100 Note 2 STOP is bit7 SYSCR1 Note 3 SAIN is AD input select signal Note 4 STOPKEN is input select signal in a key on wakeup Figure 5 8 Port 6 1 and P6CR2 Page 60 05 de 7 6 5 4 3 2 1 0 P6DR 0006H P67 P66 P65 P64 P63 P61 P60 RW AIN7 AING AIN5 AIN4 AIN3 AIN1 AINO Initial value 0000 0000 STOP3 STOP2 5 1 STOPO P6CR1 7 6 5 4 3 2 1 0 OF9BH Initial value 0000 0000 0 Input mod P6CR1 contr
104. PERR gt is cleared to 0 when the RD2BUF is read after reading the UART2SR 1 UART2SR lt PERR gt After reading UART2SR then RD2BUF clears PERR INTRXD2 interrupt Figure 13 5 Generation of Parity Error 13 9 2 Framing Error When 0 is sampled as the stop bit in the receive data framing error flag UART2SR FERRC is set to 1 The 25 lt gt is cleared to 0 when the RD2BUF is read after reading the UART2SR RXD2 pin Final bit 1 UART2SR lt FERR gt After reading UART2SR then RD2BUF clears FERR INTRXD2 interrupt Figure 13 6 Generation of Framing Error 13 9 3 Overrun Error When all bits in the next data are received while unread data are still in RD2BUF overrun error flag UART2SR lt OERR gt is set to 1 In this case the receive data is discarded data in RD2BUF are not affected UART2SR lt OERR gt is cleared to 0 when the RD2BUF is read after reading the UART2SR Page 155 13 Asynchronous Serial interface UART2 13 9 Status Fla NE T5CL8 UART2SR lt RBFL gt Shift register RD2BUF UART2SR lt OERR gt 1 After reading UART2SR then RD2BUF clears OERR 1 INTRXD2 interrupt Figure 13 7 Generation of Overrun Error Note Receive operations are disabled until the overrun error flag UART2SR OERR is cleared 13 9 4 Receive Data Buffer Full Loading the received data in RD2BUF sets receive data buffer full flag UART2SR l
105. PLAY STATUS te ofdata field PLAY STATUS 0x8400 f set ato la ith command PLAY STATUS command ret rns other ise STOP STATUS ret rns ence CD ROM USB SD case HOST BP3 Can set auto play or not in this READ DEVICE 12 DEVICE TYPE 82 command TTL FILE NUMBER 94 If set auto play return PLAY MODE otherwise return STOP mode STOP STATUS 8401 or PLAY STATUS 8400 CD DA case HOST BP3 Can set auto play or not in this READ DEVICE 12 DEVICE TYPE 82 CD TOC INFO 0x90 command If set auto play return PLAY MODE otherwise return STOP mode STOP STATUS 8401 or PLAY STATUS 8400 MIX CD case 32 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 Can set auto play or not in this READ DEVICE 12 command DEVICE TYPE 82 CD TOC INFO 90 TTL FILE DIR NUMBER 94 STOP STATUS 8401 or PLAY If set auto play return PLAY STATUS 8400 MODE otherwise return STOP mode ERROR case HOST BP3 Can set auto play or not in this READ DEVICE 12 command ERROR CODE 83 In error case STOP STATUS return STOP STATUS 8401 6 6 Play up down dir up dir down track number auto change Command li e P A AC UP I cause P into play process and P return playin trac num er hen playin i currenttrac playin inished P illstartne ttrac play hichtrac ne tto play its depend on repeat intro random settin And i this is the las
106. S After EA command 6 S card reading error S After EA command here is no USB device detected USB After EA command 8 USB device reading error USB After EA command omp3or mafiein S S After EA command a o mp3 or ma file in USB device mass storage USB After EA class device command omp3or ma file in USB device M P device USB After EA command eserved this value USB After EA command 3 USB is not read upgrade Prepare MCU flash upgrading 31 h16 524 file found upgrade Prepare MCU flash upgrading 32 h16 or s24 file format reading error upgrade In MCU flash upgrading 33 lash riting error upgrade In lash upgrading 6 28 About standby and resume play BlackPepper3 has stand function In stand state BlackPepper3 enters into po er consumption ork mode About standby in Set O 2 to BlackPepper3 stand in After stand in almost all of ports are cut off po er suppl onl several port have po er suppl So port level cannot e keptin stand mode If stand C mode please ensure C is in stop status If no sent OP command to after stop ok start stand process his point is same as S itching mode from C others About standby out Set 2 to BlackPepper3 stand out After stand irst command of returned is ESE SA Inthis case dont need to send coefficient or set pick up selection and firm feature again 65 TOSHIBA T5CJ3 7G28 F M Specific
107. S bellow Byte n Byte 1 Byte 2 EQ data format Byte n Byte 1 2 Higher 4 bits Lower 4 bits data address data or e ample S bellow Byte n Byte 1 Byte n 2 RF data format Byte n Byte 1 Byte 2 Higher 4 bits Lower 4 bits f ed ata byte or e ample S bellow Byte n Byte 1 Byte 2 lease be sure package ncludes not more than commands n other words alue of length f eld of command s not more than ere s a sample of completed commands of coeff c ent ommand ff f ff ff d ommand ff f a f d d d d d d d ommand ff f d d d db dc e e e e e ommand ffc ee e e e eb ec ed ee ef ommand ff f fff af f f f f f ff f fa f fa fb fc ee 69 TOSHIBA T5CJ3 7G28 F M Specification ommand ff f fff cf f f f f f ommand ff f fa f fa f b fdf c fdffe f f e ommand ff f fff f f f f aaf aaf ff f fa f cf a fb fc fedffe ommand ff f fff f f f f aaf aaf ff f fa f cf a f fc f d fcf e ff aca ommand ff f fef f f f f f ff af ommand ff f ff facfbefc fff d fef e ff e ommand ff f e f cf cd f f cf f fcf d ommand ff f f f b f cf fd fe ff ff f ef fcf f f f f f f ommand ff f f fa fb fc fe ff f ommand ff f f f f f f f
108. SLEEP mode and automatically restarts continues counting when the STOP IDLE SLEEP mode is inactivated Note The watchdog timer consists of an internal divider and a two stage binary counter When the clear code 4 is written only the binary counter is cleared but not the internal divider The minimum binary counter overflow time that depends on the timing at which the clear code is written to the WDTCR2 register may be 3 4 of the time set in WODTCR1 lt WDTT gt Therefore write the clear code using a cycle shorter than 3 4 of the time set to WOTCR1 lt WDTT gt Example Setting the watchdog timer detection time to 2 fc s and resetting the CPU malfunction detection LD WDTCR2 4EH Clears the binary counters LD WDTCR1 00001101B WDTT lt 10 WDTOUT lt 1 LD WDTCR2 4EH Clears the binary counters always clears immediately before and after changing WDTT Within 3 4 of WDT detection time LD WDTCR2 4EH Clears the binary counters Within 3 4 of WDT detection time LD WDTCR2 4EH Clears the binary counters Page 66 05 Watchdog Timer Control Register 1 WDTCR1 7 6 5 4 3 2 1 0 0034H ATAS ATOUT WDTEN WDTT WDTOUT Initial value 11 1001 0 Disable Writing the disable code to WDTCR2 i ired WDTEN Watchdog timer enable disable is required i 1 Enable mode SLOW1 2 REM 0 DV7CK
109. SRAM stand by pin SRAMSTB L VDDM1 Power Supply for 1 5V 1Mbit SRAM circuit PDo EFM and PLCK Phase difference signal output pin 4 state output RVDD3 RVSS3 PVREF TMAX TMAX detection result output pin 3 state output RVDD3 RVSS3 Hiz LPFN PLL circuit LPF amplifier inversion input pin LPFo PLL circuit LPF amplifier Output pin PVREF PLL circuit 1 65 V reference voltage pin Connected to VRO Connect to GND by 0 1uF and 100uF VCOF VCO filter pin 3 V analog circuit input output pin 1 5 1 5 Vdigital input output pin digital input output pin Connect to GND by 0 01uF Note1 The servo output pins FOO TRO FMO DMO become undefined or GND level under the following conditions e RST pin Low Crystal oscillation stopped according to the instructions by the Stop crystal oscillation command Power supply for CD is OFF e SRAMSTB pin Low To prevent the undefined pin states from affecting the servo circuitry or any other mechanical blocks in the system appropriate measures should be taken such as using a driver IC supporting a standby feature to place the system in standby mode while either of the above conditions is satisfied 2010 01 12 TOSHIBA TC94B14MFG Note 2 This IC does not have a power on reset circuit Keep the RST pin low until crystal oscillation becomes sufficiently
110. STOP STATUS SELECT MODE S30 MODE SEL OK 80 READ DEVICE 12 Statt read after selecting a mode Select a mode Case 3 USB or SD to others current is stop status HOST BP3 SELECT MODE S30 MODE SEL OK 80 READ DEVICE 12 Start read after selecting a mode Select a mode Case 4 USB or SD to others current is reading or playing 59 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 SYSTEM OFF 4f00 Sto USB or SD latform first STOP_STATUS SELECT_MODE 30 Select a mode MODE_SEL_OK 80 READ_DEVICE 12 Start read after selecting a mode ote if se SU command instead of DD command it ill start a res me la ing after reading tnota to la orgoing into sto 6 23 About audio mute pin e er one in UD U in to ot t a dio m te signal to control dio o t t or not f e er tin itneed to m teonso nd itot t ifitt in it need to m te off ito t t n occasion li e sto se ortrac c ange ito t tm teoffsignal tito t tm teonin normal la ing tert antis ost side can also control t is in U command as a ac no ledgement Blac e er ret rn a command U S US titis staac noledgement it doesnt resent act al te stat s fc rrent stat s is normal la ing send m te on command ill ca sea dio m te ingoesto soso ndissto ed tifc rrentis sto or a seatt etime noso nd send m te off command ill not ca se a dio m te Different it efore roect alid inan state and sto orrea
111. Schmitt input AiN2 Plots Port 13 General Input Output Port CMOS Port ut Outpu CDMON1 3I F m 98 Monitor1 Bitclock input 2 Schmitt input BCKi2 Port 14 General Input Output Port CMOS Port ut Outpu CDMON2 3I F m 39 Monitor 2 LR Clock input 2 Schmitt input LRCKi2 40 Monitor3 output 58579 CMOS Port 2010 01 12 TOSHIBA Description Default TC94B14MFG Remarks DVSS3R Grounding pin for 3 3V Muiti Bit DAC circuit 42 channel audio output of Audio DAC 43 DVDD3R Power supply pin for 3 3V Audio DAC circuit 44 DVDD3L Power supply pin for 3 3V Audio DAC circuit 45 Lo L channel audio output pin of Audio DAC 46 DVSS3L Grounding pin for 3 3V Muiti Bit DAC Circuit 47 XVSS3 Grounding pin for 3 3V clock oscillator circuit 7 Xtal oscillation circuit 48 Xi System clock Input pin Connect feedback resistor 1 O between and Xi 49 Xo System clock Output pin 50 XVDD3 Power Supply pin for 3 3V clock _ oscillator circuit 51 VDD1 2 Power Supply pin for 1 5V Digital circuit 52 VSS Grounding pin for 1 5V digital circuit y o CMOS Port 53 0 ve Port 0 General Input Output Port Schmitt input CMOS Port 54 Pio1 as Port 1 General Input Output Port Schmitt input CM
112. Specifying the Erasure Area Note 3 Refer to 20 8 Checksum SUM Note 4 Refer to 20 10 Passwords Note 5 Do not transmit the password string for a blank product Note 6 When a password error occurs T5CL8 stops UART communication and enters the halt mode Therefore when a password error occurs initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Note 7 If an error occurs during transfer of a password address or a password string T5CL8 stops UART communica tion and enters the halt condition Therefore when a password error occurs initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Description of the flash memory erasing mode 1 The Ist through 4th bytes of the transmitted and received data contain the same data as in the flash memory writing mode Page 241 20 Serial PROM Mode 20 6 Operation Mode T5CL8 The 5th byte of the received data contains the command data in the flash memory erasing mode When the 5th byte of the received data contains the operation command data shown in Table 20 6 the device echoes back the value which is the same data in the 6th byte position of the received data in this case If the 5th byte of the received data does not contain the operation command data the device enters the halt condition after sending 3 bytes of the operation command error code 63H The 7th thorough m th bytes of the transmitted and received
113. WHATSOEVER INCLUDING WITHOUT LIMITATION INDIRECT CONSEQUENTIAL SPECIAL OR INCIDENTAL DAMAGES OR LOSS INCLUDING WITHOUT LIMITATION LOSS OF PROFITS LOSS OF OPPORTUNITIES BUSINESS INTERRUPTION AND LOSS OF DATA AND 2 DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE USE OF PRODUCT OR INFORMATION INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE ACCURACY OF INFORMATION OR NONINFRINGEMENT Do use or otherwise make available Product or related software or technology for any military purposes including without limitation for the design development use stockpiling or manufacturing of nuclear chemical or biological weapons or missile technology products mass destruction weapons Product and related software and technology may be controlled under the Japanese Foreign Exchange and Foreign Trade Law and the U S Export Administration Regulations Export and re export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive TOSHIBA assumes no liability for damages or losse
114. When read the terminal input data the PSPRD register should be read read instruction is executed for port P5 read data of bit 7 to 5 are unstable STOP OUTEN Data input Output latch read P5DR Data output P5DR Output latch Control output Control input Note i2 4100 Figure 5 7 Port 5 P5DR 7 6 5 4 3 2 1 0 0005H P54 P53 P52 P51 P50 RIW SDA SCL Initial value 1 1111 000 Read only Page 58 05 5 7 Port P6 P67 to P60 Port P6 15 an 8 bit input output port which can be configured as an input or output in one bit unit Port P6 15 also used as an analog input and key on wakeup input Input output mode is specified by the P6 control register P6CR1 and P6 input control register P6CR2 During reset the is initialized to 0 the P6CR2 is initialized to 1 and port P6 becomes an input mode And the P6DR is initialized to 0 When used as an output port the corresponding bit of P6CR1 should be set to 1 When used as an input port the corresponding bit of P6CR1 should be set to 0 and then the corresponding bit of P6CR2 should be set to 1 When used as wakeup input the corresponding bit of P6CR1 should be set to 0 and then the corre sponding bit of STOPKEN should be set to 1 When used as an analog input the corresponding bit of 6 1 should be set to 0 and then the corresponding bit of
115. and a system clock reset Of these reset the address trap reset the watchdog timer and the system clock reset are a malfunction reset When the malfunction reset request is detected reset occurs during the maximum 24 fc s The malfunction reset circuit such as watchdog timer reset address trap reset and system clock reset is not initial ized when power is turned on Therefore reset may occur during maximum 24 fc s 1 5us at 16 0 MHz when power is turned on Table 2 3 shows on chip hardware initialization by reset action Table 2 3 Initializing Internal Status by Reset Action On chip Hardware Initial Value On chip Hardware Initial Value Program counter PC FFFEH Stack pointer Not mitalized Prescaler and divider of timing generator General purpose registers et Not initi d W A B C D E H L IX IY Jump status flag JF Notinitialized Watchdog timer Zero flag ZF Notinitialized Carry flag CF Notinitialized Half carry flag HF Notinitialized Output latches of I O ports Refer to I O port circuitry Sign flag SF Not initialized Overflow flag VF Not initialized Interrupt master enable flag IMF Interrupt individual enable flags Refer to each of control Control registers Interrupt latches IL register 2 3 1 External Reset Input The RESET pin contains a Schmitt trigger Hysteresis with an internal pull up resistor When the RESET pin i
116. area start address hgh bts Addr 7 atch code area start address hgh bts Addr 8 atch code area start address hgh bts Addr 9 atch code area start address hgh bts Addr atch code area address hgh bts Addr Oxb atch code area start address hgh bts ap of patch code to patch code Addr 0 F edto Addr 1 gh bts of compared address Addr 2 ddle bts of compared R address Addr 3 ow bts of compared address Addr 4 gh bts ofth s patch code length Addr 5 ow bts ofth s patch code length From addr 6 ata of patch code Area 6 map ength byte ed to bytes ommand bytes ommand bytes ommand bytes ommand bytes ommand bytes ommand bytes ast command bytes command s bytes twll bee tractedto bytes then send to decoder Area 7 map S IF 15 command bytes hecksum calculate command bytes hecksum read command bytes hecksum alue lo hecksum alue h 73 TOSHIBA T5CJ3 7G28 F M Specification 7 Recommanded flow chart for host side software Th s chapter descr bes some flow chart n host s de controll ng F rst we cons der software has bellow status def n t on Status escr pt on Reset status rogram s n resett flow Ready status fter reset flow goes to ready status nd eect S orS remo e stop read ng all wll cause program goes to ready status Read ng sta
117. bf A BSETAOK bf SETANG bf A B SETBOK bf A BSETBNG bf SET PLAY bff ommand se uence HOST BP3 A B SET A 3f01 A B SET A OK bf10 A B SET B 3f02 A B SET B OK bf20 SET PLAY bf1f A B SET PLAY bf1f A B CANCEL 3f00 CANCEL STATUS bf00 6 21 CD TEXT analysis and reading Chapter already describes about C disc reading operation but it dont ha e C TE T reading re uest Send this command when playing Normally it is ok but it will fail when stream is unknown Send this command when SET AOK Normally it is ok but it will fail when stream is unknown If B SET OK it start AB area playing automatically When playing goes to B point replay again Send this command when A SET OK or A B playing Cancel status return C TE T EA E ICE command must include the C TE T reading re uest or reading The result of TE T found or not will be return by command TE T ES be command when reading 55 TOSHIBA T5CJ3 7G28 F M Specification process is finished TE T found it can get album title artist information ET C TE T command and contents will be return byC TET IN O bd command And please be noted that Black epper read C TE Tin first session ele ant commands are listed bellow OST Black epper READ DEVICE 0x12 Byte of data field read disc with C TE T reading re uest After reading stop read disc with C TE T reading re uest Aft
118. buffi ty fl ES 1 No data exists transmit buffer 0 No dat ists i ive buff RXF Receive buffer full flag O EAA s ebd 1 Data exists in receive buffer Read 0 No error exist 1 Transmit buffer under run occurs in an external clock mode Write 0 Clear the flag 1 A write of 1 to this bit is ignored Transfer operation error flag Read 0 No error exist 1 Receive buffer over run occurs in an external clock mode Write 0 Clear the flag 1 A write of 1 to this bit is ignored Receive operation error flag Note 1 The operation error flag TXERR and RXERR not automatically cleared by stopping transfer with SIO1CR lt SIOS gt 0 Therefore set these bits to 0 for clearing these error flag Or set SIOTCR SIOINH to 1 Note 2 Don t care Receive buffer register SIO1RDB 7 6 5 4 3 2 1 0 Read only 0022H Initial value 0000 0000 Transmit buffer register SIO1TDB 7 6 5 4 3 2 1 0 Write only 0022H Initial value Note 1 SIO1TDB is write only register A bit manipulation should not be performed on the transmit buffer register using a read modify write instruction Note 2 SIO1TDB should be written after checking SIO1SR lt TXF gt 1 When SIO1SR lt TXF gt is 0 the writing data can t be transferred to SIO1TDB even if write instruction is executed to SIO1TDB Note 3 Don t care Page 161 14 Synchronous Serial Interface
119. by hardware However there are no prioritized interrupt factors among non maskable interrupts t Interrupt Vector Int t Fact Enable Condit Priorit INTSWI Software interrupt Non maskable maskable INTUNDEF Executed the undefined instruction N fcmaskable eo FFFC interrupt 17 172 3 omm mm p meu ms wem ee Note 1 To use the address trap interrupt INTATRAP clear WDTCR1 ATOUTS to 0 It is set for the reset request after reset is cancelled For details see Address Trap Note 2 To use the watchdog timer interrupt INTWDT clear WOTCR1 lt WDTOUT gt to 0 It is set for the Reset request after reset is released For details see Watchdog Timer Note 3 If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 INTADC is being accepted the INTADC interrupt latch may be cleared without the INTADC interrupt being processed For details refer to the corresponding notes in the chapter on the AD converter 3 1 Interrupt latches IL23 to IL2 An interrupt latch is provided for each interrupt source except for a software interrupt and an executed the unde fined instruction interrupt When interrupt request is generated the latch is set to 1 and the CPU is requested to accept the interrupt 1f its interrupt 1
120. control ling address and data signals directly For the support of the program writer please ask Toshiba sales rep resentative In the MCU and serial PROM modes the flash memory control register FLSCR is used for flash memory con trol This chapter describes how to access the flash memory using the flash memory control register FLSCR in the MCU and serial PROM modes Note 1 The Read Protect described by data sheet of old edition was changed into Security Program Page 223 19 19 1 Flash Memory Control 5 8 19 1 Flash Memory Control The flash memory is controlled via the flash memory control register FLSCR Flash Memory Control Register FLSCR 7 6 5 4 3 2 1 0 OFFFH FLSMD BANKSEL Initial value 1100 1 Eiash memonieommand seauncs exe 1100 Disable command sequence execution FLSMD 3 0011 Enable command sequence execution R W cution control Others Reserved Flash memory bank select control 0 Select BANKO BANKSEL Eg Serial PROM mode only 1 Select BANK1 Note 1 The command sequence of the flash memory be executed only when FLSMD 0011B In other cases any attempts to execute the command sequence are ineffective Note 2 FLSMD must be set to either 1100B or 0011B Note 3 BANKSEL is effective only in the serial PROM mode In the MCU mode the flash memory is always accessed with actual addresses 1000 FFFFH regardless of BANKS
121. eee doeet E eek eee ead eaa 164 14 3 2 1 Transmit mode 14 3 2 2 Receive mode 14 3 2 383 Transmit receive mode 14 3 3 Transfer modes peret tee e tet eee ei ees taedas pap eae es ese de 165 14 3 3 1 Transmit mode 14 3 3 2 Receive mode 14 3 3 3 Transmit receive mode 15 Synchronous Serial Interface SIO2 15 1 Configuration adero teta 177 15 9 Control QE ES 178 19 84 FUNCION a PL BREE ENRICO 180 15 394 Senabclock sin ere eer uie ve 180 15 3 1 1 Clock source 15 3 1 2 Shift edge 15 3 2 Transfer Dit direction entero tren 182 15 3 2 1 Transmit mode 15 3 2 2 Receive mode 15 3 2 3 Transmit receive mode 15 3 3 Transfer tbe erm e erre yere etr e repe Lee rtr mene 183 15 3 8 1 Transmit mode 15 3 3 2 Receive mode 15 3 3 3 Transmit receive mode 16 Serial Bus Interface I2C Bus Ver D SBI 16 1 coto eg EV EARS RIA 195 16 2 SOMO v Sata ven RUNS e S ERU CONG 195 163 Software Reset eed 6 UE Va Red 195 16 4 Data Format in the I2C Bus
122. flash memory writ ing mode is not activated In this case perform the chip erase command beforehand in the flash memory erasing mode Before activating the flash memory writing mode T5CL8 checks the password except a blank product If the password is not matched flash memory writing mode is not activated RAM loader mode The RAM loader transfers the data in Intel Hex format sent from the external controller to the internal RAM When the transfer is completed normally the RAM loader calculates the checksum After transmit ting the results the RAM loader jumps to the RAM address specified with the first data record in order to execute the user program When the security program is enabled the RAM loader mode is not activated In this case perform the chip erase beforehand in the flash memory erasing mode Before activating the RAM loader mode T5CL8 checks the password except a blank product If the password is not matched flash RAM loader mode is not activated Flash memory SUM output mode The checksum is calculated for the entire flash memory area 1000H to FFFFH and the result is returned to the external controller Since the BOOTROM does not support the operation command to read the flash memory use this checksum to identify programs when managing revisions of application programs Product ID code output The code used to identify the product 1s output The code to be output consists of 13 byte data which includes the information i
123. inputting low level on the RESET pin After releasing reset the operation mode is started from NORMALI mode 1 Normal release mode IMF 0 IDLE1 2 and SLEEP1 2 modes are released by any interrupt source enabled by the individual interrupt enable flag EF After the interrupt is generated the program operation is resumed from the instruction following the IDLE1 2 and SLEEPI 2 modes start instruction Normally the interrupt latches IL of the interrupt source used for releasing must be cleared to 0 by load instructions 2 Interrupt release mode IMF 71 IDLE1 2 SLEEP1 2 modes are released by any interrupt source enabled with the individual interrupt enable flag EF and the interrupt processing 15 started After the interrupt 15 processed the program operation is resumed from the instruction following the instruction which starts IDLE1 2 SLEEP1 2 modes Note When a watchdog timer interrupts is generated immediately before IDLE1 2 and SLEEP1 2 modes are started the watchdog timer interrupt will be processed but IDLE1 2 and SLEEP1 2 modes will not be started Page 23 T5CL8 2 Operational Description 2 2 System Clock Controller se j z Ld33 s pue 2 1011 9 jdnueju 2 ejejedo PUE uonnoexe Jo eouejdeooy uononasu Jejunoo ueJ604d ysenbe yoojo Ulejs s
124. is cut off and long term battery backup Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP3 to STOPO input is low STOP mode does not start but instead the warm up sequence starts immedi ately Thus to start STOP mode in the level sensitive release mode it is necessary for the program to first confirm that the STOP pin input is low or STOP3 to STOPO input is high The following two methods can be used for confirmation 1 Testing a port 2 Using an external interrupt input 5 INTS is a falling edge sensitive input Example 1 Starting STOP mode from NORMAL mode by testing a port P20 LD SYSCR1 01010000B Sets up the level sensitive release mode SSTOPH TEST P2PRD 0 Wait until the STOP pin input goes low level JRS F SSTOPH DI 0 SET SYSCR1 7 Starts STOP mode Page 18 05 Hn Example 2 Starting STOP mode from NORMAL mode with an INTS interrupt PINT5 TEST P2PRD 0 To reject noise STOP mode does not start if JRS SINT5 port P20 is at high LD SYSCR1 01010000B Sets up the level sensitive release mode DI 0 SET SYSCR1 7 Starts STOP mode SINT5 RETI STOP pin V Vin XOUT pin UL NORMAL STOP NORMAL operation x operation gt Warm up gt lt operation Confirm by program that the STOP mode is released by the hardware HR E is low and start Always released if the STOP input is high
125. itrate samp e fre uency ta e Byte vaue Sampe fre uency eserve eserve eserve ot ers eserve e evant comman s iste eo HOST B ackPepper3 GET INFO 5 0 8005 e uestt e itrate samp e fre uency of mp3an songs B ackPepper3 HOST STREAM UNKNOW 0x9b Bitrate or samp e fre uency is unkno PLAY STREAM INFO 0x97 eturn itrate smape fre uency se uence ase stream information is unkno HOST BP3 Start to get stream information GET INFO STREAM 8005 Stream information is unknown STREAM UNKNOW 9b now 46 TOSHIBA T5CJ3 7G28 F M Specification ase HOST stream information is known BP3 GET INFO STREAM 8005 PLAY STREAM INFO 97 Return frequency 6 16 Set repeat intro random play mode epper play mode t ey are repeat intro random set a single mode but also can set compound mode nd please be noted t at epper isrepeat none random off intro off setting as a default lay mode definition table Start to get stream information bitrate and sample ost can sett ese play mode by command not only can 1 repeat1 repeat play the current song dir up down operation 2 repeat1 random repeat play the current song same as mode 1 is forbidden 3 repeatitintro repeat play the first 10 second of the curr
126. lt TEND gt is cleared to 0 when the data transmit is started after writing the TD2BUF Shift register TXD2 pin UART2SR lt TBEP gt UART2SR lt TEND gt MEM A INTTXD2 interrupt Figure 13 10 Generation of Transmit End and Transmit Data Buffer Empty Page 157 13 Asynchronous Serial interface UART2 13 9 Status Fla T5CL8 Page 158 05 me 14 Synchronous Serial Interface 5101 The serial interfaces connect to an external device via 51 501 and SCK1 pins When these pins are used as serial interface the output latches for each port should be set to 1 14 1 Configuration Internal data bus SIO1CR SIO1SR SIO1TDB Shift clock J Shift register on transmitter MSB LSB Serial data output Serial data input Shift register on receiver Serl SIO1RDB To BUS Port Note SCKT pin INTSIO1 Internal clock Serial data output interrupt input Note Set the register of port correctly for the port assigned as serial interface pins For details see the description of the input output port control register Figure 14 1 Synchronous Serial Interface SIO Page 159 14 Synchronous Serial Interface 5101 14 2 Control T5CL8 14 2 Control The SIO is controlled using the serial interface control register SIOICR The operating status of the serial inter face can be inspected by reading the status register SIOICR Serial Interface Contr
127. mode Steps 1 2 are controlled by the program the flash memory and steps 3 through 11 are controlled by the control program in the RAM area Transfer the write control program to the RAM area Jump to the RAM area Disable DI the interrupt master enable flag IMF 0 Disable the watchdog timer if it is used Set FLSCR lt FLSMD gt to 0011B to enable command sequence execution Execute the erase command sequence y A IOS ER Read the same flash memory address twice Repeat step 7 until the same data 15 read by two consecutive read operations oo Execute the write command sequence It is not required to specify the bank to be written Read the same flash memory address twice Repeat step 9 until the same data is read by two consecutive read operations 10 Set FLSCR lt FLSMD gt to 1100B to disable command sequence execution 11 Jump to the flash memory area Note 1 Before writing to the flash memory in the RAM area disable interrupts by setting the interrupt master enable flag IMF to 0 Usually disable interrupts by executing the DI instruction at the head of the write control program in the RAM area Note 2 When writing to the flash memory do not intentionally use non maskable interrupts the watchdog timer must be disabled if it is used If a non maskable interrupt occurs while the flash memory is being written unexpected data is read from the flash memory inte
128. mode can reduce waste in battery power consumption 3 1 Standby mode After shutting down all supply voltages except for VDDM1 pin 74 making the SRAMSTB pin pin 73 low makes it possible to put the built in 1 Mbit SRAM alone on standby The data in the 1 Mbit SRAM is preserved so the SRAM standby mode is useful to implement a resume function to be used after the standby mode is exited Figure 3 1 shows the sequence of the SRAM standby mode Power On PLL Power On PLL Boot Reset Period Set Up Period Reset Period2 Set Up Period2 Wait Period Program Boot Peribd Normal Function Power Off SRAM StandBy Period SRAMSTB VDDM1 LLL 4 AVDD3XVDD3 DVDD3RVDD3 EIS MEM NE VDD3 TIENE EN RST X 4 dock2 Internal gt System Clock Program Start Characteristics Symbol Pus sme pwa pns Puma war ome ewm wat ome en Figure 3 1 Standby mode note All input terminals other than SRMSTB terminal are given as opening or L fixation at the time of SRAM standby mode 11 2010 01 12 TOSHIBA 4 Absolute Maximum rating TC94B14MFG
129. modes and it cannot be used in the parallel PROM mode Page 225 19 19 2 Command Sequence T5CL8 A maximum of 30 ms is required to erase 4 kbytes The next command sequence cannot be executed until the erase operation is completed To check the completion of the erase operation perform read operations repeat edly for data polling until the same data 15 read twice from the same address in the flash memory During the erase operation any consecutive attempts to read from the same address is reversed bit 6 of the data toggling between 0 and 1 19 2 3 Chip Erase All Erase This command erases the entire flash memory in approximately 30 ms The next command sequence cannot be executed until the erase operation is completed To check the completion of the erase operation perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory During the erase operation any consecutive attempts to read from the same address is reversed bit 6 of the data toggling between 0 and 1 After the chip is erased all bytes contain FFH 19 2 4 Product ID Entry This command activates the Product ID mode In the Product ID mode the vendor ID the flash ID and the security program status can be read from the flash memory Table 19 4 Values To Be Read in the Product ID Mode 60 kbytes 48 kbytes 32 kbytes F002H Flash size 24 kbytes 16 kbytes 8 kbyt
130. not transmit only an end record If receiving an end record after a password string the device may not operate correctly Note 7 If the security program is enabled or a password error occurs T5CL8 stops UART communication and enters the halt condition In this case initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Page 246 TOSHIBA T5CL8 Note 8 If an error occurs during the reception of a password address or a password string T5CL8 stops UART com munication and enters the halt condition In this case initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Description of RAM loader mode 1 Note 1 1st through 4th bytes of the transmitted and received data contains the same data as the flash memory writing mode In the 5th byte of the received data contains the RAM loader command data 60H When th 5th byte of the received data contains the operation command data shown in Table 1 6 the device echoes back the value which is the same data in the 6th byte position in this case 60H If the 5th byte does not contain the operation command data the device enters the halt condition after send ing 3 bytes of operation command error code 63H The 7th through m th bytes of the transmitted and received data contain the same data as in the flash memory writing mode The m th 1 through n th 2 bytes of the received data contain the binary data in the Intel Hex for mat
131. o selection one is to if starta to la is to set if read reading is st alid for mode b t host send itin S orS mode e illdisc ss reading later or a oid error and eas ing rogramming in host soft are its better sending command after orS isread stat sifstarttoread S orS bot S orS stat s referto chat er lease be noted that de icehast o ind neis artial de ice one is b tnot artial de ice or bt not artial de ice nctions of boo mar re eatres me la osition la allare na ailable ele ant commands are listed bello S lac e er READ DEVICE 0x12 ere stdisc ss first b te of data field or means sto after read means a to la from first song after read and hae reading re st disc ss it later lac e er S DEVICE TYPE 0x82 fde iceis la a ailable ret rn this command etailed infomation lease refer to command cha ter ERROR CODE 0x83 f error occ in reading rocess or de ice is la ailable ret rn this command to re ort a error bo treading error b te of data field is in mode in 5 mode a b cin S mode etailed infomation lease refer to command cha ter CD TOC INFO 0x90 et rns first trac n mber final trac n mber and disc total time if it is disc 31 TOSHIBA T5CJ3 7G28 F M Specification TTL FILE DIR NUMBER 0x94 et rns total file n mber total folder n mber fo nd in the de ice S S etc or disc the total folder n mber is PLAY STATUS 0x84 STOP STATUS te of data field STOP STATUS 0x8401
132. of less than 1 fs s NM are eliminated as noise Pulses of 3 5 fs s or more are considered to be signals Pulses of less than 7 fc s are eliminated as noise Pulses of 25 fc s or more considered Falling edge to be signals In the SLOW or the SLEEP mode INT2 IMF EF8 1 or ne pulses of less than 1 16 s are eliminated as oe noise Pulses of 3 5 fs s or more are consid ered to be signals Pulses of less than 7 fc s are eliminated as noise Pulses of 25 fc s or more considered Falling edge to be signals In the SLOW or the SLEEP mode INT3 EF12 1 or poa i Rising edge pulses of less than 1 fs s are eliminated as g e29 noise Pulses of 3 5 fs s or more are consid ered to be signals Pulses of less than 2 fc s are eliminated as noise Pulses of 7 fc s or more are considered INT5 EF23 1 Falling to be signals In the SLOW or ihe SLEEF mode pulses of less than 1 fs s are eliminated as noise Pulses of 3 5 fs s or more are consid ered to be signals Note 1 In NORMAL1 2 or IDLE1 2 mode if a signal with no noise is input on an external interrupt pin it takes a maximum of sig nal establishment time 6 fs s from the input signal s edge to set the interrupt latch Note 2 When INTOEN 0 IL4 is not set even if a falling edge is detected on the INTO pin input Note 3 When a pin with more than one function is used as an output and a change oc
133. output Output latch input Hysteresis input Disable 100 typ Pin input Control input Page 264 TOSHIBA T5CL8 Initial High Z Analog input Data output P67 P66 vo Output latch input P65 P64 Disable Pin input Key on Wakeup Initial High Z Analog input Data output Output latch input Disable Pin input Page 265 Tri state 1 R 100 typ Tri state 1 R 100 typ 21 Input Output Circuit 21 2 Input Output Ports dido T5CL8 Page 266 05 22 Electrical Characteristics 22 1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation even for an instant Any one of the ratings must not be exceeded If any absolute maximum rating is exceeded a device may break down or its performance may be degraded causing it to catch fire or explode resulting in injury to the user Thus when designing products which include this device ensure that no absolute maximum rating value will ever be exceeded VSS 0 V Md p Output voltage Vour1 0 3 to Vpp 0 3 P1 P6 P7 ports put current Per 1 pin PO P1 P2 P4 P6 P7 ports X louri P1 P2 P6 P7 ports put current Total UN lour2 P3 P5 ports Power dissipation Topr 85 Soldering temperature time Tsld 260 10 s Storage temperature Tstg 55 to 125 Operating tempe
134. pmx1 HOLD 55 REQ STATUS o pnx2 4 F nAM1 INNER 5 I nBS DVCC3B TEST XT1 LI n CCE XT2 MCU_RESET PWE oc E InMCU TEST DSS Black Pepper 3 a BUCK DVCC1B 65 E mrEsT RVOUT1 22 5 RVIN EGEPTOU E nDVvCC3A ODVSS TOPVIEW RVOUT2 15 L nMODEA4 DVCC1A DVSS TEST TEST 54 TEST TEST TEST TEST TEST TEST lt nEn gt Q u wu u ul m uu u uou 2u uu iu Ou m mu u OPP ERE RE a 14 mo u m 2 oo a e i TOSHIBA T5CJ3 7G28 F M Specification 4 4 BlackPepper 3 pin assignment and description of pins Pin name Input output Function 1 RESET Chip reset 2 HOLD System standby in or standby out control 3 REQ STATUS Request from B13 B14 4 SBSY SBSY input from 13 14 36 B13 B14 RESET RESET to B13 B14 37 B13 B14 STANDBY Standby control 13 14 57 60 050 1 2 3 Command bus with B13 B14 66 BUCK Command clock to 13 14 69 13 14 67 MCU TEST yo Connect to MCU TEST pin for MCU upgrade 68 MCU RESET yo Connect to MCU RESET pin for MCU upgrade 71 BS LRCK BSIF 92 BS BCK BSIF 93 BS DATA BSIF 94 BS GATE BSIF 96 BS RE
135. string specified to the password with the password string transmitted from the external controller The area in which passwords can be specified is located at addresses 1000H to FF9FH The area from to FFFFH can not be specified as the passwords area If addresses from FFEOH through FFFFH are filled with the passwords are not compared because the product is considered as a blank product Even in this case the password count storage addresses and password comparison start address must be specified Table 20 16 shows the password setting in the blank product and non blank product Table 20 16 Password Setting in the Blank Product and Non Blank Product Password Blank Product Note 1 Non Blank Product PNSA 1000H x PNSA x FF9FH 1000H x PNSA x FF9FH Password count storage address PCSA 1000 lt lt 1000 x PCSA lt Password comparison start address N 8 lt Password count Password string setting Not required Note 5 Required Note 2 Note 1 When addresses from FFEOH through FFFFH are filled with FFH the product is recognized as a blank product Note 2 The data including the same consecutive data three or more bytes can not be used as a password This causes a pass word error data T5CL8 transmits no data and enters the halt condition Note 3 Don t care Note 4 When the above condition is not met a password error occurs If
136. this case FLSCR BANKSEL is ineffective 1 e its value has no effect on other operations Table 19 1 Flash Memory Access FLSCR 22 Operating Mode lt gt Specified Address MCU mode 1000H FFFFH 8000H FFFFH BANK1 0 1000H 7FFFH 9000H FFFFH Serial PROM mode BEER Page 224 05 2 19 2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands JEDEC compatible as shown in Table 19 2 Addresses specified in the command sequence are recognized with the lower 12 bits excluding BA SA and FF7FH used for security program The upper 4 bits are used to specify the flash memory area as shown in Table 19 3 Table 19 2 Command Sequence 1st Bus Write 2nd Bus Write 3rd Bus Write 4th Bus Write 5th Bus Write 6th Bus Write Command Cycle Cycle Cycle Cycle Cycle Cycle um Byt 555H AAAH 555H Sector Erase 555H AAH AAAH 555H 555H AAH AAAH 4 kbyte Erase Ma 2 Sequence foe fm ml Product ID Product ID Entry 555 sss KC a raame e er 4 4 Note 1 Set the address and data to be written Note 2 The area to be erased is specified with the upper 4 bits of the address Table 19 3 Address Specification in the Command Sequence FLSCR Operating Mode lt BANK
137. voltage 2 VoP2SB CD RW mode Output upper limit voltage ROHSB GND reference Output lower limit Permissible load Fuse resistance Fuse 18 2010 01 12 TOSHIBA TC94B14MFG 5 2 DSP core section 5 2 1 DC characteristics Unless otherwise specified VDD3 AVDD3 DVDD3L R XVDD3 RVDD3 3 3 V VDD1 VDDM1 1 5 Ta 25 C Test us 5 Characteristics Symbol Circuit Test Condition Min Typ Max Unit VDD3 RVDD3 AVDD3 3 0 3 3 3 6 V Oprating Power Supply DVDD3L R Voltage XVDD3 VDD1 1 4 1 5 1 6 V VDDM1 Oprating frequency range 20 70 C VDD1 VDDM1 1 4V 95 MHz DDS XI 16 9344 MHz fopr 85 2 Note 8 x1 speed IDD1 Operating power supply CDMP3 opration MP3 Stream current IDD3 fs 48kHz 320 kbps x2 speed IDD1 donee Includs current for CD servo VIH3 H level CMOS input pins 3 V circuits excluding analog input pins L level Input Voltage H level SRMSTB pin H level VIH3 VDD3 Input current L level VIL3 VSS H level 2 9 Pins listed at 1 in L level VOL3 0 4V the following table Output current level VOH3 2 9 Ding listed at 2 in 4 level VOL3204v _ the following table 19 2010 01 12 TOSHIBA TC94B14MFG Characteristics Symbol Test Condition ne EN Pins listed at 3 in the following table Output resistance integrated at pin Pins listed at 84 and 5 in the following table
138. which follow are disabled By executing return interrupt instruction RETI RETN the stacked data which was the status before interrupt acceptance is loaded on IMF again The IMF is located on 100 EIRL Address 003AH in SFR and can be read and written by an instruction The IMF is normally set and cleared by ET and DI instruction respectively During reset the IMF is initial ized to 07 Page 36 05 Lus 3 2 2 Individual interrupt enable flags EF23 to EF4 Each of these flags enables and disables the acceptance of its maskable interrupt Setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptance of its interrupt and setting the bit to 0 dis ables acceptance During reset all the individual interrupt enable flags EF23 to EF4 are initialized to 0 and all maskable interrupts are not accepted until they are set to 1 Note In main program before manipulating the interrupt enable flag EF or the interrupt latch IL be sure to clear IMF to O Disable interrupt by DI instruction Then set IMF newly again as required after operating on the EF or IL Enable interrupt by EI instruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute nor mally on interrupt service routine However if using multiple interrupt on interrupt service routine manipulat ing EF or IL should be executed before setting IMF 1 E
139. x 3 62H x 3 Note 1 5th byte 6th byte Operation command data COH Modified baud Modified baud OK Echo back data COH Error A1H x 3 A3H x 3 63H x 3 Note 1 Tth byte Modified baud Start mark 8th byte Modified baud The number of transfer data from 9th to 18th bytes 9th byte Modified baud rat 02H Length of address 2 bytes 10th byte Modified baud Reserved data 11th byte Modified baud Reserved data 12th by Modified baud Reserved data 13th by Modified baud Reserved data 14th by Modified baud ROM block count 1 block 15th by Modified baud First address of ROM Upper byte 16th by Modified baud First address of ROM Lower byte 17th by Modified baud ra End address of ROM Upper byte 18th by Modified baud End address of ROM Lower byte 19th by Modified baud Checksum of transferred data 9th through 18th byte 20th by Wait for the next operation command data Modified baud Note xxH x 3 indicates that the device enters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Description of Product ID code output mode 1 The 1st through 4th bytes of the transmitted and received data contain the same data as in the flash
140. 0 0 91 Initial value 5 R W Note 1 For writing transmitted data start from the MSB Bit7 Note 2 The data which was written into SBIDBR can not be read since a write data buffer and a read buffer are independent in SBIDBR Therefore SBIDBR cannot be used with any of read modify write instructions such as bit manipulation etc Note 3 Don t care Page 197 16 Serial Bus Interface I2C Bus Ver D SBI 16 5 I2C Bus Control T5CL8 12 bus Address Register I2CAR 7 6 5 4 3 2 1 0 0 92 Slave address Initial value 0000 0000 SA3 Slave address selection NI Address recognition mode spec 0 Slave address recognition ification 1 Non slave address recognition Note 1 I2CAR is write only register which cannot be used with any of read modify write instruction such as bit manipulation etc Note 2 Do not set I2CAR to to avoid the incorrect response of acknowledgment in slave mode If is set to I2CAR as the Slave Address and a START Byte 01H in bus standard is recived the device detects slave address match Serial Bus Interface Control Register B SBICRB 7 6 5 4 3 2 1 0 Slave Master slave selection Master Receiver Transmitter receiver selection Transmitter 0 Generate a stop condition when MST TRX and PIN are 1 Start stop generation 1 Generate a start condition when MST TRX and PIN are 1 Can not clear this bit by a softwa
141. 0 2Handling of Password Error If a password error occurs the device enters the halt condition In this case reset the device to reactivate the serial PROM mode 20 10 3Password Management during Program Development If a program is modified many times in the development stage confusion may arise as to the password Therefore it is recommended to use a fixed password in the program development stage Example Specify PNSA to F000H and the password string to 8 bytes from address F001H PCSA becomes F001H Password Section code abs DB 08H PNSA definition DB CODE1234 Password string definition Page 257 20 Serial PROM Mode 20 11 Product ID Code 20 11Product ID Code T5CL8 The product ID code is the 13 byte data containing the start address and the end address of ROM Table 20 17 shows the product ID code format Table 20 17 Product ID Code Format Description Start Mark 3AH In the Case of T5CL8 The number of transfer data 10 bytes from 3rd to 12th byte Address length 2 bytes Reserved data Reserved data Reserved data Reserved data ROM block count The first address of ROM Upper byte The first address of ROM Lower byte The end address of ROM Upper byte The end address of ROM Lower byte Checksum of the transferred data 2 s compliment for the sum of through 12th bytes 20 12Flash Memory Status Code Th
142. 0ms 0 9 Oxbb Oxac command Store title content Id3 none Read bit rate info TI gt getbitrateinfo 4 8005 received 0 90 command command 0x97 command Store bit rate and sample frequency Wait 200ms TOSHIBA T5CJ3 7G28 F M Specification 7 4 repeat play flow Set point A Set point B Send command Send command 3101 3102 Wait 100ms then retry bf11 Wait 100ms then retry bf21 dge received command dge receive command bf10 bf20 Set Ais OK Set B is OK Received command bf1f repeat playing status 78 TOSHIBA T5CJ3 7G28 F M Specification 7 5 Host MCU upgrading flow d START Hardware reset BP3 Reset process Wait until 05 USB not ready ready USB ready Send command to start MCU upgrading 0x46 ait and che received 0x83 command USB is not ready or can not file s24 n16 file Nothing it means OK MCU is being upgraded by BP3 After finish MCU will be reset by BP3 ERROR display 79 TOSHIBA T5CJ3 7G28 F M Specification 7 6 Flash upgrading flow C S
143. 1 when a start condition on a bus is detected Bus Busy State and is cleared to 0 when a stop condition is detected Bus Free State 16 5 8 Interrupt service request and cancel When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC and the ACK is complete a serial bus interface interrupt request INTSBI is generated Page 202 05 n In the slave mode the conditions of generating INTSBI interrupt request are follows At the end of acknowledge signal when the received slave address matches to the value set by the DCAR At the end of acknowledge signal when a GENERAL CALL is received At the end of transferring or receiving after matching of slave address or receiving of GENERAL CALL When a serial bus interface interrupt request occurs the PIN Bit4 in SBISRB is cleared to 0 During the time that the PIN is 0 the SCL pin is pulled down to low level Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN 10 1 The time from the PIN being set to 1 until the SCL pin is released takes tj ow Although the PIN Bit4 in SBICRB can be set to 1 by the softrware the PIN can not be cleared to 0 by the softrware Note When the arbitration lost occurs if the slave address sent from the other master devices is not match the INTSBI interrupt request is generated But the PIN is not cleared 16 5 9 Se
144. 1 mode Write only 25 17 17 xr mm 0 Int t t Writ WDTOUT Watchdog timer output select eae 1 Reset request only Note 1 After clearing WDTOUT to 0 the program cannot set it to 1 Note 2 fc High frequency clock Hz fs Low frequency clock Hz Don t care Note 3 WDTCRI is a write only register and must not be used with any of read modify write instructions If WDTCR 1 is read a don t care is read Note 4 To activate the STOP mode disable the watchdog timer or clear the counter immediately before entering the STOP mode After clearing the counter clear the counter again immediately after the STOP mode is inactivated Note 5 To clear WDTEN set the register in accordance with the procedures shown in 6 2 3 Watchdog Timer Disable Watchdog Timer Control Register 2 WDTCR2 7 6 5 4 3 2 1 0 0035H Initial value Clear the watchdog timer binary counter Clear code Write B1H Disable the watchdog timer Disable code Watchdog timer control code D2H Enable assigning address trap area Others Invalid WDTCR2 Note 1 The disable code is valid only when WDTCR1 WDTEN 0 Note 2 Don t care Note 3 The binary counter of the watchdog timer must not be cleared by the interrupt task Note 4 Write the clear code using a cycle shorter than 3 4 of the time set in WOTCR1 lt WDTT gt 6 2 2 Watchdog Timer Enable Setting WDTCRI WDTEN to 1
145. 1 mode the difference between the peak current and the average current becomes large Note 7 If a write or erase is performed on the flash memory or a security program is enabled in the flash memory an instanta neous peak current flows as shown in Figure 22 2 Page 270 05 ne Note 8 The circuit of a power supply must be designed such as to enable the supply of a peak current This peak current causes the supply voltage in the device to fluctuate Connect a bypass capacitor of about 0 1uF near the power supply of the device to stabilize its operation Note 9 Viy is supply volage to the terminals except for TEST is supply voltage for TEST pin Note 10 To execute the Program Erase and Security Program commands on the flash memory the temperature must be kept within Topr 10 to 40 degree celsius If this temperature range is not observed operation cannot be guaranteed 1 machine cycle 4 fc or 4 fs Le gt 1 Program coutner PC X mi X m2 X m8 1 1 Momentary flash current IDDP P mA Max current Sum of average Typ current momentary flash current and MCU current Figure 22 1 Intermittent Operation of Flash Memory 1 machine cycle 1 lt Internal data bus Internal write signal 1 Last write cycle of each of the Byte Program 1 1 1 Security Program Chip Erase Sector Erase 1
146. 1 system reset is ok standby out reset 0x00 no repeat 0x01 repeat 1 REPEAT MODE 0xb7 byte 0 0x02 repeat dir 0x03 repeat all 0x00 intro on INTRO MODE 0xbS8 byte 0 0x01 intro off 23 TOSHIBA T5CJ3 7G28 F M Specification 0x00 random on mode 0x01 random track iPod don t use RANDOM MODE 0xb9 byte 0 0x02 random album iPod don t use 0x03 random off 0x00 CD TEXT not found CD TEXT RESULT Oxbc byte 0 0x01 CD TEXT found CD TEXT character set code 0x00 ISO 8859 1 8bits 0x01 150646 ASCII 7bits byte 1 0x80 Shif JIS Japanese character 0x81 Korean character 0x82 Chinese character CD TEXT INFO 0xbd byte 0 0x00 title 0x01 artist byte 1 track number byte 2 info data first byte byte 3 info data byte n info data last byte 0x00 A B repeat is cancel 0x10 A B repeat start point set OK 0x11 A B repeat start point set NG A B_REPEAT_STATUS 0xbf 0 Ox1F Replay start 0x20 A B repeat end point set OK 0x21 A B repeat end point set NG character coding type FILE_NAME SELECTED 0xc0 byte 0 0x00 ISO 8859 1 0x01 Unicode USB SD mode is UTF 16 CD mode is UTF 16BE byte 1 select file name first byte byte 2 select file name byte n select file name last byte character coding type DIR NAME SELECTED Oxc1 byte 0 0x00 ISO 8859 1 0x01 Unicode USB SD mode is UTF 16 CD mo
147. 10 to the SBIM and 00 to bits S WRSTI and SWRSTO Note The initialization of a serial bus interface circuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition If not the data can not be received correctly because the other device starts transferring before an end of the initialization of a serial bus interface circuit 16 6 2 Start condition and slave address generation Confirm bus free status BB 0 Set the ACK to 1 and specify a slave address and a direction bit to be transmitted to the SBIDBR By writing 1 to MST TRX BB and PIN the start condition is generated on a bus and then the slave address and the direction bit which are set to the SBIDBR are output The time from generating the START condition until the falling SCL pin takes tj ow An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle and the PIN is cleared to 0 The SCL pin is pulled down to the low level while the PIN 15 0 When an interrupt request occurs the TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device Note 1 Do not write a slave address to be output to the SBIDBR while data is transferred If data is written to the SBIDBR data to been outputting may be destroyed Note 2 The bus free must be confirmed by software within 98 0 us The s
148. 1111 1111 PWREG6 7 6 5 4 3 2 1 0 001BH R W Initial value 1111 1111 Note 1 Do not change the timer register TTREG6 setting while the timer is running Note 2 Do not change the timer register PWREG6 setting in the operating mode except the 8 bit and 16 bit PWM modes while the timer is running TimerCounter 6 Control Register TC6CR 7 6 5 4 3 2 1 0 002 TC6CK TC6S TC6M Initial value 0000 0000 TFF6 Timer F F6 control Ws SIRE 1 Set NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 TC6CK Operating clock selection Hz R W fc fc TC6 input TC6S TC6 start control 0 Operation stop and counter clear 1 Operation start 000 timer event counter mode 001 8 bit programmable divider output PDO mode 010 8 bit pulse width modulation PWM output mode TC6M TC6M operating mode select 01 100 16 bit timer event counter mode 101 Warm up counter mode 110 16 bit pulse width modulation PWM output mode 111 16 bit PPG mode Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note 2 Do not change the TC6M TC6CK and TFF6 settings while the timer is running Note 3 To stop the timer operation TC6S 1 0 do not change the TC6M TC6CK and TFF6 settings To start the timer operation TC6S 0 gt 1 TC6M TC6CK and TFF6 be programmed Note 4 When TC6M 1 upper byte in the 16 bit mode the source clock becomes the TC5 overflow sign
149. 14MFG Characteristics Symbol Test Condition ircuit FE section FPi1 FPi2 gt Note 5 Voltage gain amp variable range 1 CD DA mode Voltage gain amp variable range 2 CD RW mode Gain balance 1 GB CD DA mode TRE Gain balance 2 CD RW mode 2 characteristic 1 CD DA mode Frequency characteristic 2 CD RW mode Output offset voltage 1 CD DA mode Note 5 Output offset voltage 2 CD RW mode Note 5 Output upper limit voltage Output lower limit voltage Permissible load resistance 1FE GvA12FE Eu FE fC1FE 2 tiz omo FEOGAINi 1111 Fem fs AGVA1 FE AGVA2 FE 3dB point CMD FEBW 0 CMD GVSW 1 point CMD FEBW 0 CMD GVSW 0 BE VRO reference 2 2 open 50 FEBC 00h CMD GVSW 1 E VRO reference 2 2 open FEBC 00h CMD GVSW 0 GND reference GND reference These values are those for which offset correction is completed 19 2010 01 12 TOSHIBA TC94B14MFG Characteristics Symbol Post Test Condition TE section TNi gt Voltage gain amp variable range 1 CD DA mode GVA12TE Voltage gain amp variable range 2 CD RW mode GVA22TE Gain balance H DA adjustment Gain balance 1 GB
150. 16 0 MHz Setting ports LDW PWREGS5 07D0H Sets the pulse width LD 5 33H Sets the operating clock to 23 and 16 bit PWM output mode lower byte LD TC6CR 056H Sets TFF6 to the initial value 0 and 16 bit PWM signal generation mode upper byte LD TC6CR 05EH Starts the timer Page 133 11 8 Bit TimerCounter 5 TC6 11 1 Configuration T5CL8 1senbei 92 L LNI E 94 3 1 IG yore yore B yore poU UU uy lt uus 2 g 3 1601 deme TX i SUM SOAYMd 9 giu OVP ug aX C Ce Jeu49ju 1 1 9441232921 1 1 lt 5921 gt 429921 Figure 11 7 16 Bit PWM Mode Timing Chart TC5 TC6 Page 134 05 11 3 8 16 Bit Programmable Pulse Generate PPG Output Mode TC5 and 6 This mode is used to generate pulses with up to 16 bits of resolution The timer counter 5 and 6 are cascad able to enter the 16 bit PPG mode The counter counts up using the internal clock or external clock When a match between the up counter and the timer register PWREGS5 PWREG6 value is detected the logic level output from the timer F F6 is switched to the opposite state The counter co
151. 20 15 UART Timing 20 15UART Timing T5CL8 Table 20 19 UART Timing 1 VDD 4 5 to 5 5 V fc 2 to 16 MHz 10 to 40 Parameter Time from matching data reception to the echo back Minimum Required Time Clock Frequency fc Approx 930 At fc 2 MHz At fc 16 MHz Time from baud rate modification data reception to the echo back Approx 980 Time from operation command reception to the echo back Approx 800 Checksum calculation time Approx 7864500 Erasure time of an entire flash memory Erasure time for a sector of a flash memory in 4 kbyte units Table 20 20 UART Timing 2 VDD 4 5 to 5 5 V fc 2 to 16 MHz Topr 10 to 40 C Parameter Time from the reset release to the acceptance of start bit of RXD pin Clock Frequency fc Minimum Required Time At fc 2 MHz At fc 16 MHz 131 3 ms Matching data transmission interval 1 78 ms Time from the echo back of matching data to the acceptance of baud rate modification data 23 8 us Time from the echo back of baud rate modification data to the acceptance of an operation command 40 6 us Time from the echo back of operation command to the acceptance of password count storage addresses Upper byte 50 us RESET pin TE 28H RXD 28H TXD pin i i CMeb1
152. 22 Electrical Characteristics 22 8 Handling Precaution T5CL8 22 Recommended Oscillating Conditions XIN XOUT XTIN XTOUT j 1 High frequency Oscillation 2 Low frequency Oscillation Note 1 To ensure stable oscillation the resonator position load capacitance etc must be appropriate Because these factors are greatly affected by board patterns please be sure to evaluate operation on the board on which the device will actually be mounted Note 2 The product numbers and specifications of the resonators by Murata Manufacturing Co Ltd are subject to change For up to date information please refer to the following URL http www murata com 22 8 Handling Precaution The solderability test conditions for lead free products indicated by the suffix G in product name are shown below 1 When using the Sn 37Pb solder bath Solder bath temperature 230 C Dipping time 5 seconds Number of times once R type flux used 2 When using the Sn 3 0Ag 0 5Cu solder bath Solder bath temperature 245 C Dipping time 5 seconds Number of times once R type flux used Note The pass criteron of the above test is as follows Solderability rate until forming gt 95 When using the device oscillator in places exposed to high electric fields such as cathode ray tubes we recommend elec trically shielding the package in order to maintain normal operating condition Page 274 TOSHIBA T5CL8 23 Package
153. 22 42 ER ae eee PA Ra dud 8 7 Dn 19 8 Transmit Receive Operation 13 81 Transmit 154 18 8 2 Data Receive Operation 000000 010000000000000000000001000000 000 154 19 9 Status Flag o mS ese etd 18 92 rere aee er I OE 155 13 9 2 Framing Ce PIX convent ee De Dr oe PERPE Ee OE 155 13 93 155 18 94 Receive Data Buffer Full 2 2 cette deer nei ere resp ee Peek dope er oe 156 13 9 5 Buffer Emply ettet tenere eere oie ite 156 18 9 6 hransmit End FElag s E A esee edet eoe eere ER ER teens 157 14 Synchronous Serial Interface SIO1 Gonfig ratiOn E ERES REPRE 74 29 Gontrol eo iet eere pae eed ate Gok RAM Du Y 143 FUNCIONS s dre coa hate M us oe io Xs Nee ah 14 3 1 Senalclock cce etre ree Pee e e OR ve 162 14 311 Clock source 14 3 1 2 Shift edge 14 3 2 Transfer bit omine
154. 2TDB must be finished before the shift operation of the next data begins If the transmit data is not written to SIO2TDB after SIO2SR lt TXF gt is set to 1 transmit error occurs immediately after shift operation is started When the transmit error occurred 51025 lt gt is set to 1 If received data is not read out from SIO2RDB before next shift operation starts after setting 51025 lt gt to 1 receive error occurs immediately after shift operation is finished When the receive error has occurred 510252 lt gt is set to 1 Stopping the transmit receive operation There are two ways for stopping the transmit receive operation The way of clearing 5102 lt 51 5 gt When SIO2CR lt SIOS gt is cleared to 0 transmit receive operation is stopped after all trans fer of the data is finished When transmit receive operation is finished SIO2SR lt SIOF gt is cleared to 0 and 502 pin 1 kept in high level In external clock operation SIO2CR lt SIOS gt must be cleared to 0 before SIO2SR lt SEF gt 15 set to 1 by beginning next transfer The way of setting SIO2CR lt SIOINH gt Transmit receive operation is stopped immediately after SIO2CR SIOINH is set to 1 In this case SIO2CR lt SIOS gt SIO2SR register SIO2RDB register and SIO2TDB register are initialized Page 190 05 n Clearing SIOS SIO2CR SIOS SIO2SR lt SIOF gt Start shi
155. 36 05 11 3 9 Warm Up Counter Mode In this mode the warm up period time is obtained to assure oscillation stability when the system clocking 1s switched between the high frequency and low frequency The timer counter 5 and 6 are cascadable to form a 16 bit TimerCounter The warm up counter mode has two types of mode switching from the high frequency to low frequency and vice versa Note 1 In the warm up counter mode fix TCiCR TFFi to 0 If not fixed the PDOi PWMi and PPGi pins may output pulses Note 2 In the warm up counter mode only upper 8 bits of the timer register TTREG6 and 5 are used for match detection and lower 8 bits are not used Note 3 5 6 11 3 9 1 Low Frequency Warm up Counter Mode NORMAL 1 NORMAL2 SLOW2 SLOW1 In this mode the warm up period time from a stop of the low frequency clock fs to oscillation stability is obtained Before starting the timer set SYSCR2 XTEN to 1 to oscillate the low frequency clock When a match between the up counter and the timer register TTREG6 5 value is detected after the timer is started by setting TC6CR lt TC6S gt to 1 the counter is cleared by generating the INTTC6 interrupt request After stopping the timer in the INTTC6 interrupt service routine set SYSCR2 lt SYSCK gt to 1 to switch the system clock from the high frequency to low frequency and then clear of SYSCR2 lt XEN gt to 0 to stop the high frequency clock Table 11 8 Set
156. 3PRD are located on their respective address When read the output latch data the P3DR should be read When read the terminal input data the P3PRD register should be read STOP OUTEN Data input P3PRD Output latch read P3DR Data output P3DR Note i 7 toO Figure 5 5 Port 3 P3DR 7 6 5 4 3 2 1 0 R W 000DH Read only Page 55 5 Ports 5 5 Port P4 P47 to 40 T5CL8 5 5 Port P4 P47 to P40 Port 15 an 8 bit input output port Port is also used as a serial interface input output and an UART input output When used as an input port a serial interface input output and an UART input output the corresponding output latch PADR should be set to 1 During reset the PADR is initialized to 1 and the PAOUTCR is initialized to 0 It can be selected whether output circuit of P4 port is a C MOS output or a sink open drain individually by setting P4OUTCR When a corresponding bit of PAOUTCR is 0 the output circuit is selected to a sink open drain and when a corresponding bit of PAOUTCR is 1 the output circuit 1s selected to a C MOS output When used as an input port a serial interface input and an UART input the corresponding output control PAOUTCR should be set to 0 after PADR is set to 1 P4 port output latch PADR and P4 port terminal input PAPRD are located on their respective address When read the output latch data the PADR should be read When read the terminal
157. 51 51 530 N 50 CON901 360 z 31 4 549 53 32 GND zl a8 R927 2 USB_DP Hyr 4 31919 8928 ____ 22 5 5 USB DN Ez coo R929 2 USB 5V Hg 1 cow ce d 5 NC BA SLA BL aL AL ALAA GLA GLA 5VH7 BT LED Hg amp lo LAMP g 2 INH R901 R903 R904 R905 R907 R908 R909 R910 R911 DATA Hr 180 330 470 680 TKS E H 8 9 9 Sw908 Sw909 R om 2 g Swoot Swoos swoo4 woos 34906 sw907 lo M2 FOLDER M3 RPT lo l MENU lo DBB AS REMOTE MUSONG TUNEISEEK UP TUNERISEEK ON M4 SHUF MSIINTRO TRACK UP TRACK DN ENCODER fg ET gt GND 5 RES R912 R914 R915 R916 R918 R919 R920 R921 KEY F7 1 1 1 1 180 330 470 680 TKS E AUX AUXL o lo Q Wir hue Dis m R922 R923 l eene o BAND lo UP ZONE DN AUX GND 4T 22 PIN 57 R926 1 ENC EA cis 225 22 NU CIRCUIT DIAGRAM REMOTE BOARD ic ic N qa 2 mulum POWER MUTE SOURCE CIRCUIT DIAGRAM TUNER BOARD
158. 5CJ3 7G28 F M Specification ERROR CODE UPGRADE 0x83 U grading occ rs error ommand se ence case 1 upgrade OK HOST BP3 EXT FLASH UPGRADE 45 BP3 received this command it start to check USB device and 824 file If all checking are OK it start upgrading and command responded After EXT FLASH UPGRADE OK 8e upgrading is finished BP3 return 8E command case 2 USB is detached or no USB attached HOST BP3 Checked USB device is not ready or removed case 3 no s24 file or file open failed HOST BP3 Checked no s24 file in USB root folder case 4 file format check error 62 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 EXT FLASH UPGRADE 45 ERROR CODE 8332 Checked file format error when writing flash case 5 flash writting error HOST BP3 EXT FLASH UPGRADE 45 ERROR CODE 8333 Writing flash error 6 26 Host MCU upgrading BlackPepper3 can rite code to several U please refer to command details Same as flash upgrading it should cop a h or s24file to USB root folder At once U upgrading is started BP3 ill control pin U ES andpin 8 U ESE tocontrol U reset and enter into program mode ritting is OK ill reset U again to normal mode then U restart its program Aout 0 ES and U ESE output timing different Ut pe has different timing A out control flo please refer to flo chart elevant commands are listed ello OS BlackPepper3 MCU U
159. 7 umber of patch ma Address 8 rea start address hgh bts Address 9 rea address low bts Address 0 rea start address hgh bts Address 0xb rea start address low bts Address rea start address hgh bts Address 0 rea start address low bts Address Oxe ed to Address Oxf F edto Area 2 area 3 area 4 map Length 2bytes Command command number 3 bytes bout length area Addr 0 addr 1 Followed area length by byte hgh bts Followed area length by byte low bts bout command area ddress Addr 0 Addr 1 Addr 2 Initial ommand address byte ommand data h gher byte ommand data lower byte command EQ data Q data address hgher bts gh btsae data address Q data lower bts F to F lower bts ow bt sae Q data hgher b ts RF data f ed RF data byte RF reg ster number from to f Area 5 map Patch address table 12bytes f ed bytes Patch code 1 area Patch code 2 area Patch code 3 area Patch code 4 area Patch code 5 area Patch code 6 area ap patch address table 72 TOSHIBA T5CJ3 7G28 F M Specification Addr 0 atch code area start address hgh bts Addr 1 atch code area start address hgh bts Addr 2 atch code area start address hgh bts Addr 3 atch code area start address hgh bts Addr 4 atch code area start address hgh bts Addr 5 atch code area start address hgh bts Addr 6 atch code
160. 8 enabled The interrupt latch 15 cleared to 0 immediately after accepting inter rupt All interrupt latches are initialized to 0 during reset Page 35 3 Interrupt Control Circuit 3 2 Interrupt enable register EIR T5CL8 The interrupt latches are located on address 002EH 003CH and 003DH in SFR area Each latch can be cleared to 0 individually by instruction However IL2 and IL3 should not be cleared to 0 by software For clearing the interrupt latch load instruction should be used and then IL2 and IL3 should be set to 1 If the read modify write instructions such as bit manipulation or operation instructions are used interrupt request would be cleared inade quately if interrupt is requested while such instructions are executed Interrupt latches are not set to 1 by an instruction Since interrupt latches can be read the status for interrupt requests can be monitored by software Note In main program before manipulating the interrupt enable flag EF or the interrupt latch IL be sure to clear IMF to 0 Disable interrupt by DI instruction Then set IMF newly again as required after operating on the EF or IL Enable interrupt by El instruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute normally on interrupt service routine However if using multiple interrupt on interrupt service routine manipulating EF or IL should be executed before setting IMF 1
161. B register are initialized Page 170 TOSHIBA SIO1CR SIOS SIO1SR sSIOF SIO1SR lt SEF gt 5 pin SI1 pin SIO1SR RXF T5CL8 Start shift Start shift Start shift operation operation operation Co SIO1SR RXERR INTSIO1 interrupt request SIO1RDB Write a 0 after reading the received data when a receive error occurs 8 Writing transmit Writing transmit data A data B Figure 14 12 Example of Receive Error Processing Note If receive error is not corrected an interrupt request does not generate after the error occurs 14 3 3 3 Transmit receive mode The transmit receive mode are selected by writing 10 to SIO 1CR lt SIOM gt 1 Starting the transmit receive operation Transmit receive mode is selected by writing 10B to SIO1CR lt SIOM gt Serial clock is selected by using SIO1CR lt SCK gt Transfer direction is selected by using SIO1CR lt SIODIR gt When a transmit data is written to the transmit buffer register SIOTTDB SIO1SR lt TXF gt is cleared to 0 After SIO1CR lt SIOS gt is set to 1 SIOISR lt SIOF gt is set synchronously to the falling edge of pin The data is transferred sequentially starting from 501 pin with the direction of the bit specified by SIO1CR lt SIODIR gt synchronizing with the 5 pin s falling edge And receiving operation
162. BA T5CJ3 7G28 F M Specification 3 program start flow chart C START 2 send RANDOM OFF command to BP3 _1 command to BP3 status PROG PREP ARE Calculate first song number and Send PLAY command to BP3 with file number as parameter status PROG NEXT 82 TOSHIBA T5CJ3 7G28 F M Specification 4 A0 command process flowchart NO eceived command YES urrent i Not program play mode program play NO PROG PLAY YES Ceived 8 NO and 8400 5 release CD Status PROG PLAY Normal play FF FR playing FR release USB SD YES Calculate next song number and send PLAY command with file number as parameter Status PROG NEXT Y Normal AO command process 83 TOSHIBA T5CJ3 7G28 F M Specification 8 About characters coding nfocodng fle nfohas types IS TF TF TF In command there s one byte to nd cate the cod ng type fle TF only F le name foler name cod ng R F le name or folder name s IS or TF There s one byte n command to nd cate the cod ng type S ors F le name or folder name s s IS TF There s one byte n command to nd cate the cod ng type Sugges
163. BH 6058 21 00 SCREW 2 6x5 X crack 1 0700 i e 1 1 1 Z z DENG 01 MME EXPLODED DIAGRAM CEI NW E CEM2100 DETACHABLE PANEL MAIN FRAME EXPLODED DIAGRAM d ma lt Cr DIOR PNE S0 20 see Ro Is Tu Force Electronic Co ltd PART NUBER DESCRIPTION 2100 Trouble shooting 1 of 2 2100 Trouble shooting NO failure cause remark failure phenomena Ze a To check whether it is connect well of the ISO connector power input Whether it is loose of the 15A fuse of the ISO connector or insert non in place b To check whether the reset button Sw201 is long term functional then caused short circuit and no power c To check whether there is any contamination and bad contact on the 22 Pin male female connector on the panel and main board 1 NO Power d To check the power supply of main board B ACC should be 12V The voltage of stabilivolt of ACC power supply wire ZD210 6V8 should be 6V8 e To check the voltage of the 19 pin AVDD of MCU T5CL8 should be 3V3 The output voltage of 307 LM2950 should be 3V3 f To check the oscillation frequence of crystal X201 shuold be 8MHz and f
164. C94B14MFG 5 4 10 Audio DAC Characteristics Characteristics Symbol Piu Test Condition 1 kHz sine wave full scale input Noise distortion factor 10 kHz sine wave BEDS full scale input SIN ratio SIN ratio SN SN 1 internal zero detectionon Internal zero detectonon detection on Dynamic range INI kHz sine wave gt 60 dB input conversion Crosstalk CT 1 1 kHz sine wave 97 full scale input Analog output amplitude DACout 1 sing wave 780 820 860 mvrms full scale input Stop band Attenuation 60dB In band ripple below 0 025dB This characteristic is the characteristic at the time of 1x Playback mode Test circuit 1 The application circuit shown in the following example is used TC94B14MFG Lout 20 kHz Distortion Application circuit Rout ideal LPF meter LPF Filter incorporated in the SHIBASOKU distortion meter 725D Distortion meter SHIBASOKU 725D or equivalent Characteristics Distortion Filter Setting A weight A weight IEC A or equivalent Application circuit example TC94B14MFG XVDD3 DVSS3R 3 3uF Ro 5 33V a c x DVDD3R E 5 16 9344MHz E3 E 1 j m DVDD3L i 3 3uF Lo DVSS3L OHI 5 27 2010 01 12 TOSHIBA LQFP80 P 1212 0 50F 5 a 1 e9TYP 0
165. CL8 8 2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register and two 16 bit timer registers TCIDRA and TCIDRB Timer Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC1DRA TC1DRAH 0011H TC1DRAL 0010H 0011H 0010H Initial value 1111 1111 1111 1111 Read Write 0013H 0012H Initial value 1111 1111 1111 1111 Read Write Write enabled only in the PPG output mode TimerCounter 1 Control Register 7 6 5 4 3 2 1 0 TC1CR 0026H Read Write Initial value 0000 0000 TFF1 Timer F F1 control 0 Clear Auto capture control 0 disable 1 Auto capture enable Pulse width measure mode control 0 Double edge capture 1 Single edge capture External trigger timer 0 start 1 Trigger start and stop PPG output control 0 Continuous pulse generation 1 One shot dow 00 Stop and counter clear 01 Command start 10 Rising edge start TC1 start control Ex trigger Pulse PPG Rising edge count Event Positive logic count Window 11 Falling edge start Ex trigger Pulse PPG Falling edge count Event Negative logic count Window NORMAL1 2 IDLE 2mode IDLE1 2 mode Divider DV7CK 0 DV7CK 1 TC1 source clock select 00 15 23 Hz 0 5 DV1 External clock 1 pin input 00 Timer external trigger timer event counter mode TC1 operating mode 01 Window mode select 10
166. Counter Mode Timing Chart TC6 11 3 3 8 Bit Programmable Divider Output PDO Mode TC5 6 This mode is used to generate a pulse with a 50 duty cycle from the pin In the PDO mode the up counter counts up using the internal clock When a match between the up counter and the value is detected the logic level output from the pin is switched to the opposite state and the up counter is cleared The INTTC interrupt request is generated at the time The logic state opposite to the timer F Fj logic level is output from the PDOj pin An arbitrary value can be set to the timer F Fj by TCjCR lt TFFj gt Upon reset the timer F Fj value is initialized to 0 To use the programmable divider output set the output latch of the I O port to 1 Page 126 05 Example Generating 1024 Hz pulse using TC6 fc 16 0 MHz Setting port LD TTREG6 3DH 1 1024 27 2 LD TC6CR 00010001B Sets the operating clock to fc 2 and 8 bit PDO mode LD TC6CR 00011001 Starts TC6 Note 1 In the programmable divider output mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the programmable divider output mode the new value programmed in TTREGj is in effect immediately after programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 2 When the timer is stoppe
167. Cycle ting Mod CPUC TBT perating Mode ee Peripherals Time Frequency E Oscillation Operate s Single clock Stop Operate Halt Hat rg with frequency s mE Oscillation SLOW2 E with low Operate Oscillati t Dual clock SLEEP2 SLOW1 E with 415 s low frequency SLEEP Stop E Halt 5 Page 16 05 de System Control Register 1 SYSCR1 0038H stop RELM RETM OUTEN Initial value 0000 007 0 CPU core and peripherals remain active STOP STOP mode start R W soe semen 1 CPU core and peripherals are halted Start STOP mode RELM Release method for STOP 0 release RW mode 1 Level sensitive release en mode after STOP 0 Return to NORMAL 1 2 mode OUTEN Port output during STOP mode 1 Return to NORMAL mode Return to SLOW mode Warm up time at releasing 3 x 21612 3x 2795 16 13 STOP mode 2 2 ffs 3 x 214 3 x 285 214 fc 2646 Note 1 Always set RETM to 0 when transiting NORMAL mode to STOP mode Always set RETM to 1 when transiting from SLOW mode to STOP mode Note 2 When STOP mode is released with RESET pin input a return is made to NORMAL1 regardless of the RETM contents Note 3 fc High frequency clock Hz fs L
168. DATA O0xNN command 2 1 OxNN folder name of selected folder NAME SELECTED IDIR INSIDE INFO 5 2 OxNN inside info of selected folder folder info of selected ack to 0 07 5 file2 DIR INFO OF FILE Oxff 7 Oxc3 DATA OxNN command SELECT WRONG Oxff 2 OxNN select file or folder number is wrong PLAY CD TRACK ATIME 3 10 490 OxNN of CDDA track PLAY SONG TOTAL TIME 0 4 0xd2DATA OxNN mp3 wma file total time or total msf time of CDD track TRACK INFO 0 7 Oxd5 DATA OxNN track start msf time total msf time BOOKMARK STATUS 2 Oxde DATA OxNN set ok or ng 2 BOOKMARK PLAY STATUS Oxff 2 Oxdf DATA OxNN j bookmark play ok or ng USB SD DET STATUS 2 0 0 OxNN USB and SD card detecting status PLAY POSITION 7 0xNN play position FIRMWARE VERSION 3 Oxf7 OxNN firmware version information FIRMWARE FEATURE 3 Oxf7 DATA OxNN return firmware feature parameter ack to 0x83 command DISC BRAKE ERR 1 Oxfa none OxNN Note 1 if status changed from play to any other the setting will be cleared And read stop command also can clear the setting 2 read comma
169. DTCR2 0036H TBTCR 0037H EINTCR 0038H SYSCR1 0039H SYSCR2 003AH EIRL 003BH EIRH 003CH ILL 003DH ILH Reserved PSW Note 1 Do not access reserved areas by the program Note 2 Cannot be accessed Note 3 Write only registers and interrupt latches cannot use the read modify write instructions Bit manipulation instructions such as SET CLR etc and logical operation instructions such as AND OR etc Page 46 TOSHIBA 42 T5CL8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SBISRA SBICRA I2CAR SBISRB SBICRB UART1SR UART1CR1 UART1CR2 RD1BUF TD1BUF UART2SR UART2CR1 UART2CR2 RD2BUF TD2BUF STOPCR Reserved Reserved Reserved Reserved Page 47 4 Special Function Register SFR 4 2 DBR T5CL8 Address Read Write OFEOH Reserved OFE1H Reserved OFE2H Reserved OFE3H Reserved OFE4H Reserved Reserved OFE6H Reserved OFE7H Reserved OFE8H Reserved OFE9H Reserved OFEAH Reserved OFEBH Reserved OFECH Reserved OFEDH Reserved OFEEH Reserved OFEFH Reserved OFFOH Reserved OFF1H Reserv
170. E wmm TC1DRA INTTC1 interrupt request Note lt b Trigger start and stop METT1 1 Figure 8 3 External Trigger Timer Mode Timing Chart Page 83 8 16 Bit TimerCounter 1 TC1 8 3 Function 8 3 3 1 pin Input i At the Up counter TC1DRA INTTC1 interrput request T5CL8 Event Counter Mode In the event counter mode the up counter counts up at the edge of the input pulse to the pin Either the rising or falling edge of the input pulse is selected as the count up edge lt 18 gt When a match between the up counter and the TCIDRA value is detected an INTTC1 interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting at each edge of the input pulse to the pin Since a match between the up counter and the value set to TCIDRA 15 detected at the edge opposite to the selected edge an interrupt request is generated after a match of the value at the edge opposite to the selected edge Two or more machine cycles are required for the low or high level pulse input to the pin Setting lt gt to 1 captures the up counter value into TCIDRB with the auto capture function Use the auto capture function in the operative condition of TC1 A captured value may not be fixed if it s read after the execution of the timer stop
171. E CON AUX IN RECEIVER 5 MN REMO CON TRANSMTTER ROS 4 Optical Pick up Front Aux Audio Power IC LV47004 SPEAKER OUTPUT LINE OUTPUT 2C CD AUDIO IC602 DSP TC94BI4MFG IC604 USB SD MMC Driver IC 12 T5CJ3 7G28 F M 603 Motor Driver IC USB Socket SD MMC CARD Socket 5 5888 ISO SPEAKER OUTPUT BATT INPUT ACC INPUT AMP ANT Remote OUT illumination WIRING DIAGRAM USB 45V 1 E ANT INPUT Tuner Module BVLIE BYLLE YL SPEAKER OUTPUT Sub woofer Filter IC H Tuner SD 3 3V MCU IC TSCL8 or TMPBGFS49BUG Fornt Rear AUX Audio Setting IC Cd Connector Car CD Mechanism Board Optical Pick up Motor A 17 Pin FCC 12 Pin FCC Volume IC 7313 4052 1 Main Board 1563 7628 Line Output POWER IC LV47004 TC94BMMFG USB SD MMC Driver IC 8 Rear
172. E T 8230 d 4 H R287 L RSS 5 don g gu oe 10208 e pigs 289 2 8 RREOS RR604 8608 E ES Foy 6626 z SSE g S 8 d C H 4 8 7 8 ip 5 lt TN a 1302 R666 2 8 8 E Jj ES gy 88 HE S ILL 277 R609 286078 e Se 0303 302 12602 CD 552 mox 0652 D209 2 ks BS NS R622 605 D Ru S ES 5 2 R623 2S 8548 B 55 Sf E 30 i 2 55 ROSA An s C305 5 H 55 22 3 eL 202037 8 1 5 m 8 AC E 102 5 2 D210 F 5 9 uu D601 Ie 8 is 0701 PA m C258 au g m iof cos R632 E ccm 810 02048 0 0306 1638 8645 R322 2 R289 20207 Ree R639 8 5 8 8 z 8658 111 6 2 254 4 2 po R657 n R297 CON202 R319 2 0620 moti 619 22 9 4 ba R286 55 D ROBT 22 Es Y 28 88 3 2 9701 Mi 8 ss 8 C703 R295 zgm R71 8710 29 R709 R712 _ 12 PCB LAYOUT PANEL BOARD SIDE VIEW OO hh ga SW9 Ne M S i SEEN CENE PCB LAYOUT PANEL BOARD B
173. EE 1 or more _ Start condition R W Direction bit ACK Acknowledge bit P Stop condition Figure 16 2 Data Format in of IC Bus Page 196 05 16 5 12C Bus Control The following registers used to control the serial bus interface and monitor the operation status of the bus Serial Bus Interface Control Register A SBICRA 7 6 5 4 3 2 1 0 0 90 BC ACK SCK Initial value 0000 000 2 9 2 Number of transferred bits 3 4 5 6 7 8 ACK 1 ACK Slave mode Not generate a clock pulse for Not count a clock pulse for Acknowledgement mode 2 acknowledgement acknowledgement R W specification Generate a clock pulse for Count a clock pulse for an acknowledgement acknowledgement n 16 MHz 8 MHz 4 MHz Reserved Reserved 100 0 kHz Reserved Reserved 55 6 kHz Serial clock fscl selection Reserved 58 8 kHz 29 4 kHz Output on SCL pin 60 6 kHz 30 3 kHz 15 2 kHz 1 2 fc 8 fc 30 8 2 15 4 2 7 7 2 15 5 2 7 8 2 3 9 2 7 8 2 3 9 2 1 9 2 Reserved Note 1 fc High frequency clock Hz Don t care Note 2 SBICRA cannot be used with any of read modify write instructions such as bit manipulation etc Note 3 Do not set SCK as the frequency that is over 100 kHz Serial Bus Interface Data Buffer Register SBIDBR 7 6 5 4 3 2 1
174. EH LD A ADCDR1 Read result data LD 9FH A 17 4 STOP SLOW Modes during AD Conversion When standby mode STOP or SLOW mode is entered forcibly during AD conversion the AD convert operation is suspended and the AD converter is initialized and ADCCR2 are initialized to initial value Also the conversion result is indeterminate Conversion results up to the previous operation are cleared so be sure to read the conversion results before entering standby mode STOP or SLOW mode When restored from standby mode STOP or SLOW mode AD conversion is not automatically restarted so it is necessary to restart AD conversion Note that since the analog reference voltage is automatically disconnected there is no possibility of current flowing into the analog reference voltage Page 217 17 10 bit AD Converter ADC 17 5 Analog Input Volt d ADC ion Result nalog Input Voltage an onversion T5CL8 17 5 Analog Input Voltage and AD Conversion Result The analog input voltage 15 corresponded to the 10 bit digital value converted by the AD as shown in Figure 17 4 conversion result 03 02 01 VAREF VSS 1021 1022 1023 1024 1024 Analog input voltage Figure 17 4 Analog Input Voltage and AD Conversion Result Typ Page 218 05 17 6 Precautions about AD Converter 17 6 1 Restrictions for AD Conversion interrupt INTADC usage
175. EL Note 4 Bits 2 through 0 in FLSCR are always read as don t care 19 1 1 Flash Memory Command Sequence Execution Control FLSCR lt FLSMD gt The flash memory can be protected from inadvertent write due to program error or microcontroller misoper ation This write protection feature is realized by disabling flash memory command sequence execution via the flash memory control register write protect To enable command sequence execution set FLSCR lt FLSMD gt to 0011B To disable command sequence execution set FLSCR lt FLSMD gt to 1100B After reset FLSCR lt FLSMD gt 15 initialized to 1100B to disable command sequence execution Normally FLSCR lt FLSMD gt should be set to 1100B except when the flash memory needs to be written or erased 19 1 2 Flash Memory Bank Select Control FLSCR lt BANKSEL gt In the serial PROM mode a 2 kbyte BOOTROM is mapped to addresses 7800H 7FFFH and the flash mem ory is mapped to 2 banks at 8000H FFFFH Flash memory addresses 1000H 7FFFH are mapped to 9000H FFFFH as BANKO and flash memory addresses 8000H FFFFH are mapped to 8000H FFFFH as BANKI FLSCR BANKSEL is used to switch between these banks For example to access the flash memory address 7000H set FLSCR lt BANKSEL gt to 0 and then access F000H To access the flash memory address 9000H set FLSCR lt BANKSEL gt to 1 and then access 9000H In the MCU mode the flash memory is accessed with actual addresses at 1000H FFFFH In
176. FO ac01 GET INFO ALBUM ID3 8002 ID3 ALBUM INFO ac02 6 15Get bitrate and sample frequency informaiton T is paragrap escri es getting stream information itrate samp e fre uency In ackPepper3 it returns reatime for P3 fie In t ereis yte to te yout e mpeg version yte tote you itrate yteto te you samp efre out o to eco e itratean sampe fre uency referto e o 44 TOSHIBA T5CJ3 7G28 F M Specification ta es Datafie ta e Data fie Byte Byte Byte P3 mpeg version P3 itrate P3 samp e fre uency mpeg version e Byte vaue P version itateta e Byte vaue P 3 k ps k ps k ps k ps 3 k ps k ps k ps 3 k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps k ps 3 k ps k ps 3 kps k ps fori fori en ot ers fori fori samp e fre uency ta Byte vaue P P k k k k k k 3k k k ot ers reserve reserve reserve In B ackPepper3 it returns averate itrate for fie In t ereis ytes tote you average itrate teunitisk ps t ereis ytetote yousampefre o to eco esampe fre uency referto e ta es Datafie ta e 45 TOSHIBA T5CJ3 7G28 F M Specification Data fie Byte Byte Byte itate ig itate o samp e fre uency
177. FOH Modified baud 6th Modified baud OK Echo back data FOH Error A1H x 3 A3H x 3 63H x 3 Note 1 Tth Password count storage address bit Modified baud 8th 15 to 08 Note 4 5 Modified baud ra OK Nothing transmitted Error Nothing transmitted 9th Password count storage address bit Modified baud ra 10th 07 to 00 Note 4 5 Modified baud OK Nothing transmitted Error Nothing transmitted 11th byte Password comparison start address Modified baud 12th byte bit 15 to 08 Note 4 5 Modified baud ra OK Nothing transmitted Error Nothing transmitted 13th Password comparison start address Modified baud ra 14th bit 07 to 00 Note 4 5 Modified baud ra OK Nothing transmitted Error Nothing transmitted 15th Password string Note 4 5 Modified baud m th byte Modified baud ra OK Nothing transmitted Error Nothing transmitted th 2 byte Erase area specification Note 2 Modified baud rate th 1 byte Modified baud rate OK Checksum Upper byte Note 3 Error Nothing transmitted OK Checksum Lower byte Note 3 hi byte Modified baud rate Error Nothing transmitted Wait for the next operation command th 1 byt data Modified baud rate Note 1 xxH x 3 indicates that the device enters the halt condition after transmitting 3 bytes of xxh Note 2 Refer to 20 13
178. Figure 8 2 Timer Mode Timing Chart Page 81 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 8 3 2 External Trigger Timer Mode In the external trigger timer mode the up counter starts counting by the input pulse triggering of the pin and counts up at the edge of the internal clock For the trigger edge used to start counting either the rising or falling edge is defined in TC1CR lt TCIS gt When lt 1 gt is set to 1 trigger start and stop When a match between up counter and the TCIDRA value is detected after the timer starts the up counter is cleared and halted and an interrupt request is generated If the edge opposite to trigger edge 1s detected before detecting a match between the up counter and the TCIDRA the up counter is cleared and halted without generating an interrupt request Therefore this mode can be used to detect exceeding the specified pulse by interrupt After being halted the up counter restarts counting when the trigger edge is detected When lt gt is set to 0 trigger start When a match between the up counter and the TCIDRA value is detected after the timer starts the up counter is cleared and halted and an interrupt request is generated The edge opposite to the trigger edge has no effect in count up The trigger edge for the next count ing is ignored if detecting it before detecting a match between the
179. H Sets mode for TC6 5 16 bit mode fs for source LD TC6CR 05H Sets warming up counter mode LDW 5 8000H Sets warm up time Depend on oscillator accompanied DI lt 0 SET EIRE 2 Enables INTTC6 EI lt 1 SET TC6CR 3 Starts TC6 5 PINTTC6 CLR TC6CR 3 Stops TC6 5 SET SYSCR2 5 SYSCR2 lt SYSCK gt lt 1 Switches the main system clock to the low frequency clock CLR SYSCR2 7 SYSCR2 lt XEN gt lt 0 Turns off high frequency oscillation RETI VINTTC6 DW 6 INTTC6 vector table Page 28 05 Hn 2 Switching from SLOW1 mode to NORMAL2 mode First set SYSCR2 lt XEN gt to turn on the high frequency oscillation When time for stabilization Warm up has been taken by the timer counter TC6 TC5 clear SYSCR2 lt SYSCK gt to switch the main system clock to the high frequency clock SLOW mode can also be released by inputting low level on the pin After releasing reset the operation mode is started from NORMAL mode Note After SYSCK is cleared to 0 executing the instructions is continiued by the low frequency clock for the period synchronized with low frequency and high frequency clocks High frequency cock LLL Low frequency clock 7 21 42 Main System clock LL S SYSCK Example Switching from the SLOW1 mode to NORMAL2 mode fc 16 MHz warm up time is 4 0 ms
180. IO1RDB receive error occurs immediately after shift opera tion is finished Then INTSIO1 interrupt request is generated after 51015 lt gt is set to 1 3 Stopping the receive operation There are two ways for stopping the receive operation The way of clearing 5101 lt 51 5 gt When SIOICR lt SIOS gt is cleared to 0 receive operation is stopped after all of the data is finished to receive When receive operation is finished SIO1SR lt SIOF gt is cleared to 0 In external clock operation SIOICR SIOS must be cleared to 0 before SIO1SR lt SEF gt 15 set to 1 by starting the next shift operation The way of setting SIO1CR lt SIOINH gt Receive operation is stopped immediately after SIOICR SIOINH is set to 1 In this case 5 lt 51 5 gt SIOISR register SIOIRDB register and SIOITDB register are initialized Clearing SIOS SIO1CR SIOS i SIO1SR SIOF Start shift Start shift operation y operation 5 015 lt 5 gt SCK1 pin Automatic wait N pin AAA RERAN EER co SIO1SR lt RXF gt INTSIO1 interrupt Writing transmit Writing transmit Writing transmit data A data B data C Figure 14 10 Example of Internal Clock and MSB Receive Mode Page 169 14 Synchronous Serial Interface 5101 14 3 Function SIO1CR SIOS 5 015 lt 5 gt 5 015 lt 5 gt SCK1 pin SI1 pin SIO1SR RXF INTSIO1 interrupt req
181. IOM gt 15 3 3 1 Transmit mode Transmit mode is selected by writing 00B to SIO2CR lt SIOM gt 1 Starting the transmit operation Transmit mode is selected by setting 00B to 51 02 lt 5 gt Serial clock is selected by using 5102 lt 5 gt Transfer direction is selected by using SIO2CR lt SIODIR gt When a transmit data is written to the transmit buffer register SIOZ2TDB SIO2SR lt TXF gt is cleared to 0 After SIO2CR lt SIOS gt is set to 1 SIO2SR lt SIOF gt is set synchronously to 1 the falling edge of SCK2 pin The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by SIO2CR lt SIODIR gt synchronizing with the SCK2 pin s falling edge SIO2SR lt SEF gt is kept in high level between the first clock falling edge of SCK2 pin and eighth clock falling edge SIO2SR lt TXF gt is set to 1 at the rising edge of pin after the data written to the SIO2TDB is transferred to shift register then the INTSIO2 interrupt request is generated synchronizing with the next falling edge on SCK2 pin Note 1 In internal clock operation when SIO2CR lt SIOS gt is set to 1 transfer mode does not start with out writing a transmit data to the transmit buffer register SIO2TDB Note 2 In internal clock operation when the SIO2CR SIOS is set to 1 SIO2TDB is transferred to shift register after maximum 1 cycle of serial clock frequency the
182. IOS gt SIOISR register SIOIRDB register and SIO1TDB register ini tialized i Clearing SIOS D i Start shift Start shift Start shift operation y operation operation y x t t Writing transmit Writing transmit Writing transmit data A data B data C Figure 14 6 Example of Internal Clock and MSB Transmit Mode Page 166 05 me Writing transmit Clearing SIOS SIO1CR sSIOS i i 1 1 5 015 lt 5 gt Start shift Start shift i Start shift y operation 1 5 015 lt 5 gt SCK1 pin 4 2 INTSIO1 interrupt request Writing transmit Writing transmit Writing transmit data A data B data C 501 pin SIO1SR lt TXF gt Figure 14 7 Exaple of External Clock and MSB Transmit Mode SCK1 pin SIO1SR sSIOF SODH i lt gt lt lt 8 fc Figure 14 8 Hold Time of the End of Transmit Mode 4 Transmit error processing Transmit errors occur on the following situation Shift operation starts before writing next transmit data to SIOITDB in external clock opera tion If transmit errors occur during transmit operation 51015 lt gt is set to 1 immedi ately after starting shi
183. Mini Svstem 2100 00 98 Service Service COMPACT COMPACT DIGITAL AUDIO DIGITAL AUDIO OBDAB COMPACT DIGITAL AUDIO CIRCUIT DIAGRAM REMOTE CD CONNECTOR COMPONENT 20 CIRCUIT DIAGRAM TUNER LLL 10 ISO 21 SET EXPLODER VIEW 22 Version1 1 DHILIDS Oy e 2011 6 29 DIAGRAM 2100 BLOCK DIAGRAM Sub Woofer Out Sub Weofer Out tse Rear Line Out Amp IC 4558 Fornt Lire Qut Amp IC 4558 ANT IN TUNER Module Amp Tuner Audio RDS 514745 Non RDS Function Sl4744 Q401 0402 1C403 Volume 7313 O D O Rear Aux_Audio 2 Rear AUX IN I2C MCU 201 Panel 0 T5CL8 TMP86FS49BUG LCD Audio Setting IC Seta T 4052 LCD Driver SC75823 Function Key Rotary encoder REMOT
184. Note 3 The cycle starting with either the high or low going input pulse can be measured To measure the cycle starting with the high going pulse set the rising edge to TC1CR lt TC1S gt To measure the cycle starting with the low going pulse set the falling edge to TC1CR lt TCIS gt When detecting the edge opposite to the trigger edge used to start counting after the timer starts the up counter captures the up counter value into TCIDRB and generates an INTTCI interrupt request The up counter continues counting up and captures the up counter value into TCIDRB and generates INTTCI interrupt request when detecting the trigger edge used to start counting The up counter 18 cleared at this time and then continues counting The captured value must be read from TC1DRB until the next trigger edge is detected If not read the cap tured value becomes a don t care It is recommended to use a 16 bit access instruction to read the captured value from TC1DRB For the single edge capture the counter after capturing the value stops at 1 until detecting the next edge Therefore the second captured value is 1 larger than the captured value immediately after counting starts The first captured value after the timer starts may be read incorrectively therefore ignore the first captured value Page 86 05 me Example Duty measurement resolution 27 Hz CLR INTTC1SW 0 INTTC1 service switch initial setting Address set t
185. O2SR RXF SIO2SR lt RXERR gt Q6 Reading received Reading received data D data E SIO2CR lt SIOINH gt Figure 15 16 Example of Transmit Receive Receive Error Processing Note If receive error is not corrected an interrupt request does not generate after the error occurs 5 2 pin SIO2SRsSIOF SODH lt lt 8 fc Figure 15 17 Hold Time of the End of Transmit Receive Mode Page 194 05 Hn 16 Serial Bus Interface I C Bus Ver D 581 The 5 8 has a serial bus interface which employs an bus The serial interface is connected to an external devices through SDA and SCL The serial bus interface pins are also used as the port When used as serial bus interface pins set the output latches of these pins to 1 When not used as serial bus interface pins the port is used as a normal I O port Note 1 The serial bus interface can be used only in NORMAL 1 2 and IDLE1 2 mode It can not be used IDLEO SLOW1 2 and SLEEPO 1 2 mode Note 2 The serial bus interface can be used only in the Standard mode of The fast mode and the high speed mode can not be used Note 3 Please refer to the port section about the detail of setting port 16 1 Configuration INTSBI interrupt request SCL SCL ed output control control SDA Noise canceller SBI control register B bus
186. ONE e EE CE OC 3 Interrupt Control Circuit 3 1 Interrupt latches IL23 to 12 2 3 2 Interrupt enable register 3 2 1 Interrupt master enable flag IMF 3 2 2 Individual interrupt enable flags EF23 to EF4 JW ecc 3 3 Interrupt Sequence vus Eu ODE 3 3 1 Interrupt acceptance processing is packaged as follows 3 3 2 Saving restoring general purpose eene 3 3 2 1 Using PUSH and POP instructions 8 8 2 2 Using data transfer instructions 3 3 3 41 3 4 Software Interrupt 5 42 3421 Address error detection ooo tto a eee dor 42 Bea De e 42 3 5 Undefined Instruction Interrupt 42 3 6 Address Trap Interrupt 42 3 1 External Interrupts i uso ade re RD pe ERE e ead v 43 Special Function Register SFR SERA ERS edu 45 4 2 Sere ed aha aed 47 I O Ports 5 1 7 0
187. OS Port 55 Pio2 aur Port 2 General Input Output Port Schmitt input CMOS Port 56 Pio3 BUE Port 3 General Input Output Port Schmitt input VO Port 4 General Input Output Port CMOS Port Pio4 1 m SE andes 3UF _ Audio data Input 1 Schmitt input VO Port 5 General Input Output Port CMOS Port Pio5 BCKi1 m IB 3I F Bit Clock Input 1 Schmitt input VO Port 6 General Input Output Port CMOS Port Pio6 LRCKi1 SET ue LR Clock input 1 Schmitt input y o CMOS Port 60 Pio7 ail Port 7 General Input Output Port Schmitt input 2010 01 12 TOSHIBA VDD3 Description Power Supply pin for 3 3V Digital circuit Default TC94B14MFG Remarks Connect to GND by 0 1uF BUSO Microprocessor data input output 0 CMOS Port Schmitt input BUS1 Microprocessor I F data input output pin 1 CMOS Port Schmitt input BUS2 Microprocessor data input output 2 CMOS Port Schmitt input BUS3 Microprocessor I F data input output pin CMOS Port Schmitt input BUCK Microprocessor I F BUS clock Input pin Schmitt input ICCE Microprocessor I F chip enable input pin Schmitt input Test1 Test pin H input Pull up IRST Reset Input pin Schmitt input Test Test pin 17 input VDD1 1 Power Supply pin for 1 5V Digital circuit VSS Grounding pin for 1 5V Digital circuit SRAMSTB 1Mbit
188. OTTOM SIDE VIEW PHILIPS RM9000 00 PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW PCB LAYOUT TUNER BOARD TOP SIDE VIEW coos C009 1 001 6025 1009 dn EL 2011 n 1003 2102 5001 109 PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 00 530 443 10 0 1 WW 1 1 S N 5 S PCB LAYOUT SD BOARD SIDE VIEW Z0 90 TLTOC u 1 ONG E BN 01 2Q d00TCW32 0TF 21 4 a as 2 05 1134 15 IN9 22 225 05 IN9 1005 05 319 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW 20 LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 SET EXPLODER VIEW DRAWING 76 01 CEM310003 00 00 FIBRE SHEET 71 660 TBH20083 24 00 SCREW 2 0x8 0mm 70 600 CEM310007 00 00 BACK PANEL 69 600 CEM310032 00 00 LED BRACKET 68 410 CEM2100C DC 00_ PANEL_PCB 67 M3 82008220 00 00 RUBBER CONTACT 66 600 CEM310030 00 00 SENSOR BRACKET 65 600 CEM200024 00 00 LCD HOLDER 64 000 200025 00 00 LCD_REFLECTOR 63 104 200001 00 00 LCD DIFFUSION SHEET 62 M0 06352494 00 00 LCI 61 650 CEM200006 00 00 LCD 20 ET 60 600 CEW31001 1 00 00 CD SLOT ILLU 59 600 CEM310023 00 00 SE Soit 58 600 510022
189. P mode is released by a inputting Either level sensitive or edge sensitive can be programmably selected to the STOP pin After the warm up period 15 completed the execution resumes with the instruction which follows the STOP mode start instruction Page 15 2 Operational Description 2 2 System Clock Controller T5CL8 Reset release mode NORMAL1 mode SYSCR2 lt TGHALT gt 1 SYSCR2 lt IDLE gt 1 Interrupt SYSCR1 lt STOP gt 1 STOP pin input SYSCR2 lt XTEN gt 1 IDLE1 mode a Single clock mode SYSCR2 lt XTEN gt 0 IDLE2 mode SYSCR2 lt IDLE gt 1 SYSCR1 lt STOP gt 1 mode STOP pin input SYSCR2 lt SYSCK gt 1 Interrupt SYSCR2 lt SYSCK gt 0 STOP SYSCR2 lt IDLE gt 1 SLEEP2 mode Interrupt SYSCR2 lt XEN gt 1 SYSCR2 XEN 0 SYSCR2 lt IDLE gt 1 SYSCR1 lt STOP gt 1 1 Interrupt STOP pin input b Dual clock mode Note 2 SYSCR2 lt TGHALT gt 1 SLEEPO mode Note 1 NORMAL1 and NORMAL2 modes are generically called NORMAL SLOW1 and SLOW2 are called SLOW IDLEO IDLE1 and IDLE2 are called IDLE SLEEPO SLEEP1 and SLEEP2 are called SLEEP Note 2 The mode is released by falling edge of TBTCR TBTCK setting Figure 2 6 Operating Mode Transition Diagram Table 2 1 Operating Mode and Conditions Other Machine
190. PCR before the STOP mode is started Note2 3 Note 1 When the STOP mode released by the edge release mode SYSCR1 RELM 07 inhibit input from STOPO to STOP3 pins by Key on Wakeup Control Register STOPCR or must be set level into STOPO to STOP3 pins that are available input during STOP mode Note 2 When the STOP pin input is high or STOPO to STOPS pins input which is enabled by STOPCR is low executing instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence Warm up Note 3 The input circuit of Key on Wakeup input and Port input is separated so each input voltage threshold value is dif ferent Therefore a value comes from port input before STOP mode start may be different from a value which is detected by Key on Wakeup input Figure 18 2 Note 4 STOP pin doesn t have the control register such as STOPCR so when STOP mode is released by STOPO to STOPS pins STOP pin also should be used as STOP mode release function Note 5 In STOP mode Key on Wakeup pin which is enabled as input mode for releasing STOP mode by Key on Wakeup Control Register STOPCR may generate the penetration current so the said pin must be disabled AD conversion input analog voltage input Note 6 When the STOP mode is released by STOPO to STOP3 pins the level of STOP pin should hold L level Figure 18 3 Port input External pin Key on wakeup input Figure 18 2 Ke
191. PGRADE 0X46 Should specif U t pe num er BlackPepper3 0 ERROR CODE UPGRADE 0x83 U upgrading onl haserrorcode 3 and 3 ommand se uence case 1 upgrade OK 63 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 MCU_UPGRADE 46 BP3 received this command it start to check USB device and RESET MCU 524 116 file If all checking are OK it starts MCU reset and upgrading After upgrading is finished BP3 reset MCU again case 2 USB is detached or no USB attached HOST BP3 MCU UPGRADE 46 Checked USB device is ERROR CODE 8330 not ready or removed MCU will not be reset in this case case 3 no s24 h16 file or file open failed HOST BP3 MCU UPGRADE 46 Checked no s24 or h16 ERROR 8331 file in root folder MCU will not be reset in this case 6 27 About error code A out BlackPepper3 error code and its e planation and action is listed ello Command ID Error Explanation Mode Occasion code disc Occurs ustin mode After EA command 1 isc toc reading error Occurs ustinC mode C After 64 TOSHIBA T5CJ3 7G28 F M Specification 83 2 isc not support It means there is no pla a le C After media in disc Occurs in C mode 3 Pla error It means error occurs in pla ing process C In pla ing Occurs in C mode 4 eserved this value is no S card
192. Q BSIF 5 INNER Pick up inner switch 39 DRIVER MUTE Output to driver 77 AUDIO MUTE Audio mute output 78 USB PON USB power control 79 USB D USB data bus 80 USB D y o USB data bus 84 SD DATA OUT SD data bus out 85 SD DATA IN SD data bus in 86 SD CLK SD data bus clock 89 SD CS SD CS signal 98 SD DETECT SD detect signal 87 TX TX 88 RX RX 90 E2PROM SDA yo SDA connect to 91 E2PROM SCL SCL connect to 7 8 XT1 XT2 32KHZ OSC connect 73 75 X1 X2 9MHZ OSC connect 9 PWE Power control standby mode 10 17 26 44 627 DVSS Ground 4 83 100 TOSHIBA T5CJ3 7G28 F M Specification 6 DVCC3B Power supply 3 3V 27 45 63 76 95 DVCC3A Power supply 3 3V 11 DVCC1B Power supply 1 5V 16 DVCC1A Power supply 1 5V 12 15 RVOUT1 RVOUT2 1 5V output from Internal Regulator 13 14 RVIN Power supply pin for Internal Regulator 18 25 28 35 TEST Connect to ground or open 38 40 43 46 56 64 65 70 82 TEST2 Connect ground 97 MODE2 Software mode refer to notes 99 MODE3 Software mode refer to notes 61 MODE4 Software mode refer to notes 72 AM1 Hardware mode refer to notes 81 AMO Hardware mode need to be pull up refer to notes NOTES AMO 1 fixed AM1 1 run program in internal rom 0 run program in external flash MODE2 1 enable external flas
193. REG6 and 5 immediately after the INTTC6 interrupt request is generated normally in the INTTC6 interrupt service routine If the programming of PWREGj and the interrupt request occur at the same time an unstable value is shifted that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is generated Note 2 When the timer is stopped during PWM output the PWM6 pin holds the output status when the timer is stopped To change the output status program TC6CR lt TFF6 gt after the timer is stopped Do not program TC6CR lt TFF6 gt upon stopping of the timer Example Fixing the PWM6 pin to the high level when the TimerCounter is stopped Page 132 05 CLR TC6CR 3 Stops the timer CLR TC6CR 7 Sets the PWM6 pin to the high level Note 3 To enter the STOP mode stop the timer and then enter the STOP mode If the STOP mode is entered with out stopping of the timer when fc fc 2 or fs is selected as the source clock a pulse is output from the PWM6 pin during the warm up period time after exiting the STOP mode Table 11 7 16 Bit PWM Output Mode NORMAL 1 2 IDLE1 2 mode SLOW1 2 16 MHz fs 32 768 kHz SLEEP1 2 fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode 15 23 Hz fs 2 Hz 8 39 5 fc 27 524 3 ms fc 25 131 1 ms fc 23 32 8 ms fs 2s 8 2ms 4 1 ms Example Generating a pulse with 1 ms high level width and a period of 32 768 ms fc
194. RT control register 1 Transmit data buffer Receive data Buffer UART1CR1 TD1BUF RD1BUF Shift register 1 i Noise rejection circuit _ RXD1 i Receive control circuit Transmit receive clock Y A fc 2 i B fc 2 1 5 X 1 28 1 S 2 4 2 UART1SR UART1CR2 UART status register UART control register 2 Multiplexer 1 1 B 1 1 G 1 1 H i 1 1 Baud rate generator Figure 12 1 UART1 Asynchronous Serial Interface Page 139 12 Asynchronous Serial interface UART1 12 2 Control T5CL8 12 2 Control UARTI is controlled by the UARTI Control Registers UARTICRI UARTICR2 The operating status can be monitored using the UART status register UARTISR UART1 Control Register1 UART1CR1 7 6 5 4 3 2 1 0 OF 95H TXE STBT EVEN BRG Initial value 0000 0000 0 Disable Transfer operation 4 Enable 0 Disable Receive operation 4 Enable 0 1 bit STBT Ti it stop bit length EM DUNT EARS 0 Odd bered parit EVEN Even numbered parity e M 1 Even numbered parity 0 N it Parity addition y 1 fc 13 Hz fc 26 fc 52 fc 104 BRG Transmit clock select fc 208 fc 416 Input INTTC3 96 Note 1 When operations are disabled by setting and RXE bit to 0 the setting becomes valid when data transmit receive complete
195. RX changing conditions in each mode and TRX value after changing Table 16 2 TRX changing conditions in each mode When a serial bus interface circuit operates in the free data format a slave address and a direction bit are not recognized They are handled as data just after generating a start condition The TRX is not changed by a hard ware signal is returned 16 5 7 Start stop condition generation When the BB Bit5 in SBISRB is 0 a slave address and a direction bit which are set to the SBIDBR are output on a bus after generating a start condition by writing 1 to the MST TRX BB and PIN It is necessary to set to 1 beforehand SCL pin 1 2 3 4 5 6 7 8 9 1 Start condition Slave address and the direction bit Acknowledge signal Figure 16 5 Start Condition Generation and Slave Address Generation When the BB is 1 sequence of generating a stop condition is started by writing 17 to the MST and PIN and 0 to the BB Do not modify the contents of MST BB and PIN until a stop condition is gener ated on a bus When a stop condition is generated and the SCL line on a bus is pulled down to low level by another device a stop condition is generated after releasing the SCL line SCL pin 777 SDA E Stop condition Figure 16 6 Stop Condition Generation The bus condition can be indicated by reading the contents of the BB Bit5 in SBISRB The BB is set to
196. SBI data SBI control register A SBI status register B address register buffer register SBI status register A Figure 16 1 Serial Bus Interface SBI 16 2 Control The following registers are used for control the serial bus interface and monitor the operation status Serial bus interface control register A SBICRA Serial bus interface control register B SBICRB Serial bus interface data buffer register SBIDBR bus address register IZCAR Serial bus interface status register A SBISRA Serial bus interface status register B SBISRB 16 3 Software Reset A serial bus interface circuit has a software reset function when a serial bus interface circuit is locked by an exter nal noise etc To reset the serial bus interface circuit write 10 01 into the SWRST 0 in SBICRB And a status of software reset canbe read from SWRMON Bit0 in SBISRA Page 195 16 Serial Bus Interface I2C Bus Ver D SBI 16 4 The Data Format in the I2C Bus Mode 15018 16 4 The Data Format in the 12 Bus Mode The data format of the bus is shown below a Addressing format lt 8bits 1 1 to 8 bits Au 1 to 8 bits gt S Slave address 1 Data Data lt 1 gt lt 1 or more b Addressing format with restart I 806 1 to 8 bits gt I 8 bits 1 to 8 bits gt 1 1 A e c Free data format lt 8 bits TEE 1 to 8 bits e 1 to 8 bits T
197. SEL gt Specified Address Q H F H BANKO 1 g H F H Serial PROM mode 19 2 1 Byte Program This command writes the flash memory for each byte unit The addresses and data to be written are specified in the 4th bus write cycle Each byte can be programmed in a maximum of 40 us The next command sequence cannot be executed until the write operation is completed To check the completion of the write operation per form read operations repeatedly until the same data 1s read twice from the same address in the flash memory During the write operation any consecutive attempts to read from the same address 1 reversed bit 6 of the data toggling between 0 and 1 Note To rewrite data to Flash memory addresses at which data including FFH is already written make sure to erase the existing data by sector erase or chip erase before rewriting data 19 2 2 Sector Erase 4 kbyte Erase This command erases the flash memory in units of 4 kbytes The flash memory area to be erased 1s specified by the upper 4 bits of the 6th bus write cycle address For example in the MCU mode to erase 4 kbytes from 7000 to specify one of the addresses 7000H 7FFFH as the 6th bus write cycle In the serial PROM mode to erase 4 kbytes from 7000H to 7FFFH set FLSCR lt BANKSEL gt to 0 and then specify one of the addresses in FOOOH FFFFH as the 6th bus write cycle The sector erase command is effective only in the MCU and serial PROM
198. Shift clock J Shift register on transmitter MSB LSB Serial data output Serial data input Shift register on receiver Ser SIO2RDB To BUS Port SCK2 pin INTSIO2 Internal clock Serial data output interrupt input Note Set the register of port correctly for the port assigned as serial interface pins For details see the description of the input output port control register Figure 15 1 Synchronous Serial Interface SIO Page 177 15 Synchronous Serial Interface 5102 15 2 Control T5CL8 15 2 Control The SIO is controlled using the serial interface control register SIO2CR The operating status of the serial inter face can be inspected by reading status register SIO2CR Serial Interface Control Register SIO2CR 7 6 5 4 3 2 1 0 0031H SIOS SIOINH SIOM SIODIR SCK Initial value 0000 0000 0 Stop SIOS Specify start stop of transf ie T MEN SIOINH Forcibly stops transfer Note 1 EX TOM 1 Forcibly stop Automatically cleared to 0 after stopping 00 Transmit mode 01 Receive mode 10 Transmit receive mode 11 Reserved Selects transfer mode NORMAL1 2 or IDLE1 2 modes or IDLE1 2 modes SLOW SLEEP LE UE TBTCR mode lt DV7CK gt 0 DV7CK 1 15 25 Reserved Selects serial clock Reserved Reserved Reserved Reserved Reserved External clock Input from SCK2 pin Note 1 When SIO2CR SIOINH is set to 1
199. T50 I2C bus clock PORT67 Analog STOP3 input PORT66 Analog Input6 STOP2 input PORT65 Analog Input5 STOP 1 input PORT64 Analog Input4 STOPO input Page 6 TOSHIBA Table 1 1 Pin Names and Functions 3 3 Pin Name Pin Number Input Output T5CL8 Functions PORT63 Analog Inpu PORT62 Analog Inpu 61 Analog Inpu PORT60 Analog Inpu PORT77 Analog Inpu PORT76 Analog Inpu PORT75 Analog Inpu PORT74 Analog Inpu PORT73 Analog Input11 PORT72 Analog Input10 PORT71 Analog Input9 PORT70 Analog Input8 Resonator connecting pins for high frequency clock Resonator connecting pins for high frequency clock Reset signal Test pin for out going test Normally be fixed to low Analog Base Voltage Input Pin for A D Conversion Analog Power Supply 5V Page 7 0 GND 1 4 Pin Names and Functions T5CL8 Page 8 TOSHIBA 2 Operational Description 2 1 CPU Core Functions T5CL8 The CPU core consists of a CPU a system clock controller and an interrupt controller This section provides a description of the CPU core the program memory the data memory and the reset circuit 2 1 1 Memory Address T5CL8 memory is composed Flash RAM DBR Data buffer register and SFR Special func tion register They are all mapped in 64 Kbyte address space
200. TART Hardware reset BP3 start inside program 1 1 MODE2 1 process Wait until USB USB not ready USB ready Send command to start external flash upgrading 0x45 0x83 command Hardware reset BP3 start external program 1 0 MODE2 1 OK and exit ERROR and exit 80 TOSHIBA T5CJ3 7G28 F M Specification 7 7 Program play flow 1 Program task mode definition R program play s dle R R R prepare to program play t need to setup someth ng R T after send ng play command tgo to th s status frece ed command tgoto status R status frece ed command go to th s status 2 state transition IDLE Stop program pla Start program play note2 E is Receive A0 command in FR RI PROG_PLAY ARE Received A0 c status it means in NEXT status current song FR It mean is auto released don t need to commai process it knote3 change to NEXT stat amp Cknotel operation notel AO command play or FF status It means current song playing is finished notel calculate next program track number and send play command to BP3 note2 set to random off mode and repeat_1 mode note3 in FR case USB SD and CD is different Please refer to following flowchart 81 TOSHI
201. TRXD1 interrupt Figure 12 8 Generation of Receive Data Buffer Full Note If the overrun error flag lt gt is set during the period between reading the UART1SR and read ing the RD1BUF it cannot be cleared by only reading the RD1BUF Therefore after reading the RD1BUF read the UART1SR again to check whether or not the overrun error flag which should have been cleared still remains set 12 9 5 Transmit Data Buffer Empty When no data is in the transmit buffer TD1 BUF that is when data in TDIBUF are transferred to the transmit shift register and data transmit starts transmit data buffer empty flag lt gt is set to 1 The UART1SR lt TBEP gt is cleared to 0 when the TD1BUF is written after reading UARTISR Page 146 05 Hn Data write Data write TD1BUF 2222 Shift register TXD1 pin UART1SR lt TBEP gt 7 After reading UART1SR writing INTTXD1 interrupt TD1BUF clears Figure 12 9 Generation of Transmit Data Buffer Empty 12 9 6 Transmit End Flag When data are transmitted and data is in TDIBUF UARTISR lt TBEP gt 1 transmit end flag UARTISR lt TEND gt is set to 1 The UARTISR lt TEND gt is cleared to 0 when the data transmit is started after writing the TDIBUF Shift register TXD1 pin UART1SR lt TBEP gt UART1SR lt TEND gt MEM A INTTXD1 interrupt Figure 12 10
202. TXD1 Output Pin Name MCU Mode Function Serial data output BOOT RXD1 Input Input Serial PROM mode control Serial data input Note 1 RESET Input Serial PROM mode control TEST Input Fixed to high Power VDD AVDD supply 4 5 to 5 5 V Power supply VSS Power supply VAREF Leave open or apply input reference voltage ports except P02 These ports are in the high impedance state in the serial PROM mode XIN Input XOUT Output Self oscillate with an oscillator Note 1 During on board programming with other parts mounted on a user board be careful no to affect these communication control pins Note 2 Operating range of high frequency in serial PROM mode is 2 MHz to 16 MHz Page 234 05 me T5CL8 VDD 4 5 V to 5 5 V Serial PROM mode 1 MCU mode BOOT RXD1 P01 TXD1 P02 External control RESET GND Figure 20 2 Serial PROM Mode Pin Setting Note 1 For connection of other pins refer to Table 20 3 Pin Function in the Serial PROM Mode 20 3 3 Example Connection for On Board Writing Figure 20 3 shows an example connection to perform on board wring jus V to 5 5 V VDD lt Serial PROM mode TEST Pull up 7 MCU mode BOOT RXD1 01 TXD1 P02 converter PC control RESET 1 RC power on d circuit XIN XOUT VSS Application board External cont
203. TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the pin to the high level Note 3 To enter the STOP mode during PWM output stop the timer and then enter the STOP mode If the STOP mode is entered without stopping the timer when fc fc 2 or fs is selected as the source clock a pulse is out put from the PWMj pin during the warm up period time after exiting the STOP mode Note 4 3 4 Table 10 5 PWM Output Mode NORMAL1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fo 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 fc 211 Hz 15 23 Hz 15 23 Hz fc 27 fc 27 fc 2 fc 25 fc 23 fc 23 fs fs Page 109 10 8 Bit TimerCounter TC3 4 10 1 Configuration T5CL8 polad euo 1 2 L LNI vals YUS eounos lt 331 gt 701 lt 791 gt 39794 Figure 10 5 8 Bit PWM Mode Timing Chart TC4 Page 110 05 me 10 3 5 16 Bit Timer Mode TC3 and 4 In the timer mode the up counter counts up using the internal clock The TimerCounter 3 and 4 are cascad able to form a 16 bit timer When a match between the up counter and the timer register TTREG3 value is detected after the timer is started by setting TC4CR lt TC4S gt to 1 an INTTC4 interrupt is generated and the up counter is cleared After
204. US or not if necessary TOSHIBA T5CJ3 7G28 F M Specification Case 2 current is pause status HOST BP3 Specify pick up inner moving STOP 0x18 or not if necessary PAUSE RELEASE STOP STATUS Case 3 current is FF or FR status HOST BP3 Specify pick up inner moving STOP 0x18 or not if necessary FF or FR RELEASE STOP STATUS 6 10 Play end f avent set any eat mo e aftera songs p aye start stop process comman is return ust at te einning of stop process e evant s are iste ack epper S PLAY END Ox9E eansa songs p aying is finis e PLAY STATUS 0x84 STOP STATUS se uence 40 TOSHIBA T5CJ3 7G28 F M Specification HOST PLAY TO 9 STOP STATUS BP3 6 11 About BlackPepper3 status eo ta e escri es epper insi estate events ifting State Stop ay ause pause pause vent STOP command Stop Stop Stop Stop Stop Stop PLAY command ay ay ause pause pause PAUSE command ause pause pause PAUSE RELEASE command ay FF command pause pause FR command pause pause FF FR RELEASE command ay ay ause ause Track up command p ay ause pause pause Track down command p ause pause pause Dir up command p ause pause pause Dir down command ause pause pause Play to end or beginning s
205. When the transmit data is stored in the transmit data buffer the data are not transmitted Even if data transmit is enabled until new data are written to the transmit data buffer the current data are not transmitted Note 2 The transmit clock and the parity are common to transmit and receive Note 3 UART1CR1 RXE and UART1CR1 lt TXE gt should be set to 0 before UART1CR1 BRG is changed UART1 Control Register2 UART1CR2 7 6 5 4 3 2 1 0 0F96H RXDNC STOPBR Initial value 000 No noise rejection Hysteresis input Selection of RXD input noise Rejects pulses shorter than 31 fc s as noise rejection time Rejects pulses shorter than 63 fc s as noise Write Rejects pulses shorter than 127 fc s as noise only STOPBR top length T 0 00008 Note When UART1CR2 lt RXDNC gt 01 pulses longer than 96 fc s are always regarded as signals when UART1CR2 lt RXDNC gt 10 longer than 192 fc 5 and when UART1CR2 lt RXDNC gt 11 longer than 384 fc s Page 140 05 Pod 1 Status Register UART1SR 7 6 5 4 3 2 0 95 PERR FERR OERR RBFL TEND TBEP Initial value 0000 11 0 N it PERR Parity error flag 4 Babe Read only 0 No FERR Framing error flag anng d 1 Framing error 0 overrun error Overrun error flag 1 Overrun error 0 Receive data buffer empty RBFL Receive data
206. a guide for the applications of our products No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use No license is granted by impli cation or otherwise under any patents or other rights of TOSHIBA or the third parties 070122 C products described in this document are subject to foreign exchange and foreign trade control laws 060925 E For a discussion of how the reliability of microcontrollers can be predicted please refer to Section 1 3 of the chapter entitled Quality and Reliability Assurance Handling Precautions 030619 S Page 1 1 1 Features T5CL8 8 8 bit timer counter 4 ch Timer Event counter Programmable divider output PDO Pulse width modulation output Programmable pulse generation PPG modes 9 8 bit UART 2 ch 10 High Speed SIO 2ch 11 Serial Bus Interface I C Bus Ich 12 10 bit successive approximation type AD converter Analog input 16 ch 13 Key on wakeup 4 ch 14 Clock operation Single clock mode Dual clock mode 15 Low power consumption operation STOP mode Oscillation stops Battery Capacitor back up SLOW 1 mode Low power consumption operation using low frequency clock High frequency clock stop SLOW2 mode Low power consumption operation using low frequency clock High frequency clock oscillate IDLEO mode CPU stops and only the Time Based Timer TBT on peripher
207. a in the erased area of the flash memory Flash Memon erasing mode the whole or part of the flash memory used to calculate the checksum In the case of the chip erase an entire area of the flash memory is used Page 255 20 Serial PROM Mode 20 9 Intel Hex Format Binary T5CL8 20 9 Intel Hex Format Binary 1 After receiving the checksum of a data record the device waits for the start mark of the next data record After receiving the checksum of a data record the device ignores the data except transmitted by the external controller 2 After transmitting the checksum of end record the external controller must transmit nothing and wait for the 2 byte receive data upper and lower bytes of the checksum 3 Ifareceiving error or Intel Hex format error occurs the device enters the halt condition without returning an error code to the external controller The Intel Hex format error occurs in the following case When the record type is not 00H 01H or 02H When a checksum error occurs When the data length of an extended record record type 02H 15 not 02H When the device receives the data record after receiving an extended record record type 02H with extended address of 1000H or larger When the data length of the end record record type 01H is not 00H 20 10Passwords The consecutive eight or more byte data in the flash memory area can be specified to the password T5CL8 compares the data
208. a password error occurs the device enters the halt con dition without returning the error code Note 5 In the flash memory writing mode or RAM loader mode the blank product receives the Intel Hex format data immediately after receiving PCSA without receiving password strings In this case the subsequent processing is performed correctly because the blank product ignores the data except the start mark as the Intel Hex format data even if the exter nal controller transmits the dummy password string However if the dummy password string contains it is detected as the start mark erroneously The microcontroller enters the halt mode If this causes the problem do not transmit the dummy password strings Note 6 In the flash memory erasing mode the external controller must not transmit the password string for the blank product Page 256 05 s PNSA PCSA Password string Flash memory 08H becomes the umber of gt 107 passwords Compare F108H F109H F10AH 8 bytes F10BH Example F10CH PCSA F107H Password string 01H 02H 03H 04H 05H F10EH 06H 07H 08H Figure 20 5 Password Comparison 20 10 1Password String The password string transmitted from the external controller 15 compared with the specified data in the flash memory When the password string is not matched to the data in the flash memory the device enters the halt condition due to the password error 20 1
209. able with TC6M 1 Reserved Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note 2 Do not change the TC5M TC5CK and TFF5 settings while the timer is running Note 3 To stop the timer operation TC5S 1 0 do not change the TC5M TC5CK and TFF5 settings To start the timer opera tion TC5S 0 gt 1 TC5M TC5CK and TFF5 be programmed Note 4 To use the TimerCounter in the 16 bit mode set the operating mode by programming TC6CR lt TC6M gt where TC5M must be fixed to 011 Note 5 To use the TimerCounter in the 16 bit mode select the source clock by programming TC5CK Set the timer start control and timer F F control by programming TC6CR lt TC6S gt and TC6CR lt TFF6 gt respectively Note 6 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 1 and Table 11 2 Page 120 05 Note 7 The timer register settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 3 Note 8 The operating clock fc in the SLOW or SLEEP mode can be used only as the high frequency warm up mode Page 121 11 8 Bit TimerCounter 5 6 11 1 Configuration 15018 The TimerCounter 6 is controlled by the TimerCounter 6 control register TC6CR and two 8 bit timer registers TTREG6 and PWREG6 TimerCounter 6 Timer Register TTREG6 7 6 5 4 3 2 1 0 0017H R W Initial value
210. age MaskROM MCU Emulation Chip 61440 2048 T5CL8 LQFP64 P 1010 0 50D bytes bytes 1 1 Features 1 8 bit single chip microcomputer TLCS 870 C series nstruction execution time 0 25 us at 16 MHz 122 us at 32 768 kHz 132 types amp 731 basic instructions 2 24interrupt sources External 5 Internal 19 3 Input Output ports 56 pins Large current output 13pins Typ 20mA LED direct drive 4 Watchdog Timer 5 Prescaler Time base timer Divider output function 6 16 bit timer counter 1 ch Timer External trigger Window Pulse width measurement Event counter Programmable pulse generate PPG modes 7 16 bit timer counter 1 ch Timer Event counter Window modes This product uses the Super Flash technology under the licence of Silicon Storage Technology Inc Super Flash is registered trademark of Silicon Storage Technology Inc The information contained herein is subject to change without notice 021023 D TOSHIBA is continually working to improve the quality and reliability of its products Nevertheless semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress It is the responsibility of the buyer when utilizing TOSHIBA products to comply with the standards of safety in making a safe design for the entire system and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of hum
211. ailable source clock Page 103 10 8 Bit TimerCounter TC3 4 10 1 Configuration igurati T5CL8 Table 10 3 Constraints on Register Values Being Compared 16 bit PWM 2 lt PWREGA 3 65534 1 lt PWREGA 3 lt TTREGA 3 65535 16 bit PPG ded PWREGA 3 1 3 Note 3104 104 05 2 10 3 Function The TimerCounter 3 and 4 have the 8 bit timer 8 bit event counter 8 bit programmable divider output PDO 8 bit pulse width modulation PWM output modes The TimerCounter 3 and 4 TC3 4 are cascadable to form a 16 bit timer The 16 bit timer has the operating modes such as the 16 bit timer 16 bit event counter warm up counter 16 bit pulse width modulation output and 16 bit programmable pulse generation modes 10 3 1 8 Bit Timer Mode TC3 and 4 In the timer mode the up counter counts up using the internal clock When a match between the up counter and the timer register j TTREGj value is detected an INTTCj interrupt is generated and up counter is cleared After being cleared the up counter restarts counting Note 1 In the timer mode fix TCjCR TFFj to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediat
212. al filter for lower in band ripple less than 0 025dB and high attenuation less than 60dB on out of the band Built in x8 over sampling digital filter 2 2010 01 12 TOSHIBA TC94B14MFG Pin Layout and Block Diagram Top View Pin Layout Top View s of BB 5 e 172 92222 222 2 0 gt 5 gt gt gt gt gt gt VDD3 61 CDMoN3 BUSO 162 Pio14 CDMoN2 BUS1 63 Pio13 1 BUS2 64 Pio12 CDMoNO FGiN BUS3 165 Pio11 BUCK 66 Pio10 Pio9 pM TC94B14MFG p TEST DMo VDD1 1 Top View FMoS vSS 1 FMo SRAMSTB VSS 3 VDDM1 TRo PDo Foo TMAX AVDD3 LPFN TEi LPFo RFRP PVREF RFZi VCoF 80 FSMoNiT 3 2010 01 12 TOSHIBA TC94B14MFG Pin Descriptions 1 1 Pin Descriptions Description Default Remarks DSP VCO EFM Phase difference 1 VCOI signal output pin 3 state output DSP VCO control voltage inputr pin CD DSP Power supply for 3 3V RF 2 RVDD3 amplifier core PLL circuit Connect capacitor accordin SLCo EFM slice level output pin ng with servo frequency band RFi i i i i 4 i RF signal input pin Selectable Zin 20 10 5 RFRPi RF ripple signal input pin 6 RFEQo RF equalizer c
213. al regardless of the TC6CK setting Note 5 To use the TimerCounter in the 16 bit mode select the operating mode by programming TC6M where lt 5 gt must be set to 011 Page 122 05 Note 6 To the TimerCounter in the 16 bit mode select the source clock by programming TC5CR lt TC5CK gt Set the timer start control and timer F F control by programming TC6S and TFF6 respectively Note 7 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 1 and Table 11 2 Note 8 The timer register settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 3 Table 11 1 Operating Mode and Selectable Source Clock NORMAL 1 2 and IDLE1 2 Modes input pin input Sbt mr bit timer SDi event Counter bit PDO ug Exe ETT ee Tei se EL T LC _ guum ER co pese E o Note 1 For 16 bit operations 16 bit timer event counter warm up counter 16 bit PWM 16 bit PPG set its source clock lower bit TC5CK Note 2 O Available source clock Table 11 2 Operating Mode and Selectable Source Clock SLOW1 2 and SLEEP 1 2 Modes M
214. als operate using high fre quency clock Release by falling edge of the source clock which is set by lt gt IDLE1 mode CPU stops and peripherals operate using high frequency clock Release by interru puts CPU restarts IDLE2 mode CPU stops and peripherals operate using high and low frequency clock Release by inter ruputs CPU restarts SLEEPO mode CPU stops and only the Time Based Timer TBT on peripherals operate using low fre quency clock Release by falling edge of the source clock which is set by lt gt SLEEP1 mode CPU stops and peripherals operate using low frequency clock Release by interru put CPU restarts SLEEP2 mode CPU stops and peripherals operate using high and low frequency clock interruput 16 Wide operation voltage 4 5 V to 5 5 V at 16MHz 32 768 kHz 2 7 V to 5 5 V at 8 MHz 32 768 kHz Page 2 05 1 2 Pin Assignment TC4 PD04 PWM4 PPG4 TC3 PDO3 PWM3 PPG DVO TC1 14 4 1 13 4611 P12 4511 P11 44 1 10 4 31 P47 4211 P46 1 1 45 400171 44 2 1 42 4801 1 INT3 TC2 P15 PDOS PWMB TC5 P16 50 3211 7 12 PDO6 PWM6 PPG6 TC6 P17 51 31 ELA P73 AIN11 30 ELE P72 AIN10 SCL P50 17452 2900 P71 AIN9 SDA P51 rrise 28 CCI P70 AIN8 P52 co 27 KX P67 AIN7 STOP3 P53 1155 26 11 1
215. also starts with the direction of the bit specified by SIO1CR lt SIODIR gt synchronizing with the SCKT pin s rising edge 51015 lt 5 gt is kept in high level between the first clock falling edge of pin and eighth clock falling edge SIOISR TXF is set to 1 at the rising edge of SCKI pin after the data written to the SIOITDB is transferred to shift register When 8 bit data has been received the received data is transferred to SIOIRDB from shift register then the INTSIO1 interrupt request occurs synchronizing with setting SIOISR lt RXF gt to 1 Note 1 In internal clock operation when the SIO1CR lt SIOS gt is set to 1 SIO1TDB is transferred to shift register after maximum 1 cycle of serial clock frequency then a serial clock is output from SCK1 pin Note 2 In external clock operation when the falling edge is input from SCK1 pin after SIO1CR lt SIOS gt is set to 1 SIO1TDB is transferred to shift register immediately When the rising edge is input from SCK1 pin receive operation also starts Page 171 14 Synchronous Serial Interface 5101 14 3 Function 2 3 T5CL8 During the transmit receive operation When data is written to SIOTTDB SIOISR TXF is cleared to 0 and when a data is read from SIOIRDB SIOISR RXF is cleared to 0 In internal clock operation in case of the condition described below the serial clock stops to H level by an automatic wait fu
216. ammable Pulse Generate PPG Output Mode In the programmable pulse generation PPG mode an arbitrary duty pulse is generated by counting per formed in the internal clock To start the timer TC1CR lt TC1S gt specifies either the edge of the input pulse to the TCI pin or the command start lt gt specifies whether a duty pulse is produced continuously or not one shot pulse When TCICR MPPG I is set to 0 Continuous pulse generation When a match between the up counter and value is detected after the timer starts the level of the PPG pin is inverted and an INTTC interrupt request is generated The up counter contin ues counting When a match between the up counter and the TCIDRA value 15 detected the level of the pin is inverted and an interrupt request is generated The up counter is cleared at this time and then continues counting and pulse generation When TCIS is cleared to 00 during PPG output the PPG pin retains the level immediately before the counter stops When TCICR MPPGI is set to 1 One shot pulse generation When match between the up counter and the TCIDRB value is detected after the timer starts the level of the PPG pin is inverted and an INTTC interrupt request is generated The up counter contin ues counting When a match between the up counter and the TCIDRA value is detected the level of the PPG pin is inverted and an
217. an life bodily injury or damage to property In developing your designs please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications Also please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices or TOSHIBA Semiconductor Reliability Handbook etc 021023 A The TOSHIBA products listed in this document are intended for usage in general electronics applications computer personal equip ment office equipment measuring equipment industrial robotics domestic appliances etc These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may cause loss of human life or bodily injury Unintended Usage Unintended Usage include atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments medical instru ments all types of safety devices etc Unintended Usage of TOSHIBA products listed in this document shall be made at the customer s own risk 021023 B The products described in this document shall not be used or embedded to any downstream products of which manufacture use and or sale are prohibited under any applicable laws and regulations 060106 Q The information contained herein is presented only as
218. an unstable value is shifted that may result in generation of the pulse different from the programmed value until the next interrupt request is generated Note 2 When the timer is stopped during PWM output the PWMj pin holds the output status when the timer is stopped To change the output status program TCjCR lt TFFj gt after the timer is stopped Do not change the TCjCR lt TFFj gt upon stopping of the timer Example Fixing the PWMj pin to the high level when the TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the pin to the high level Note 3 To enter the STOP mode during PWM output stop the timer and then enter the STOP mode If the STOP mode is entered without stopping the timer when fc fc 2 or fs is selected as the source clock a pulse is out put from the PWMj pin during the warm up period time after exiting the STOP mode Note 4 j 5 6 Table 11 5 PWM Output Mode NORMAL1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fo 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 fc 211 Hz 15 23 Hz 15 23 Hz fc 27 fc 27 fc 2 fc 25 fc 23 fc 23 fs fs Page 129 11 8 Bit TimerCounter 5 TC6 11 1 Configuration T5CL8 polad euo PHM GO 1 92 LNI 9WMd 94 4 19W L ylus Jojuno 2 eounos
219. ance processing has completed stacked data for PCL and PCH are located on address SP 1 and SP 2 respectively Example 1 Returning from address trap interrupt INTATRAP service program PINTxx POP WA Recover SP by 2 LD WA Return Address PUSH WA Alter stacked data interrupt processing RETN RETURN Page 41 3 Interrupt Control Circuit 3 4 Software Interrupt INTSW 5 8 Example 2 Restarting without returning interrupt In this case PSW Includes IMF before interrupt acceptance is discarded PINTxx INC SP Recover SP by 3 INC SP INC SP interrupt processing LD EIRL data Set IMF to 1 or clear it to 0 JP Restart Address Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed Thus the next inter rupt can be accepted immediately after the interrupt return instruction 1s executed Note 1 It is recommended that stack pointer be return to rate before INTATRAP Increment 3 times if return inter rupt instruction RETN is not utilized during interrupt service program under INTATRAP such as Example 2 Note 2 When the interrupt processing time is longer than the interrupt request generation time the interrupt service task is performed but not the main task 3 4 Software Interrupt INTSW Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing INTSW 18 highest priorit
220. ansmitted and received data contains the same data as the flash memory writing mode The 5th byte of the received data contains the command data in the flash memory SUM output mode 90H When the 5th byte of the received data contains the operation command data shown in Table 1 6 the device echoes back the value which is the same data in the 6th byte position of the received data in this case 90H If the 5th byte of the received data does not contain the operation command data the device enters the halt condition after transmitting 3 bytes of operation command error code 63H The 7th and the 8th bytes contain the upper and lower bits of the checksum respectively For how to calculate the checksum refer to 20 8 Checksum SUM After sending the checksum the device waits for the next operation command data Page 248 TOSHIBA T5CL8 20 6 5 Product ID Code Output Mode Operation Command COH Table 20 11 shows product ID code output mode process Table 20 11 Product ID Code Output Process 1st byte 2nd byte Transfer Bytes Transfer Data from External Controller to T5CL8 Matching data Baud Rate 9600 bps 9600 bps T5CL8 to External Controller Transfer Data from Automatic baud rate adjustment OK Echo back data Error Nothing transmitted 3rd byte 4th byte Baud rate modification data See Table 20 4 9600 bps 9600 bps OK Echo back data Error A1H x 3 A3H
221. ardware changes into SLOWI mode Do not clear SYSCR2 XTEN to 0 during SLOW2 mode SLOW1 mode This mode can be used to reduce power consumption by turning off oscillation of the high fre quency clock The CPU core and on chip peripherals operate using the low frequency clock Page 14 05 i Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 lt XEN gt In SLOW1 and SLEEP modes the input clock to the 1st stage of the divider is stopped output from the 1st to 6th stages is also stopped 4 IDLE2 mode In this mode the internal oscillation circuit remain active The CPU and the watchdog timer are halted however on chip peripherals remain active Operate using the high frequency clock and or the low frequency clock Starting and releasing of IDLE2 mode are the same as for IDLE1 mode except that operation returns to NORMAL2 mode 5 SLEEP1 mode In this mode the internal oscillation circuit of the low frequency clock remains active The CPU the watchdog timer and the internal oscillation circuit of the high frequency clock are halted how ever on chip peripherals remain active Operate using the low frequency clock Starting and releas ing of SLEEP mode the same as for IDLE1 mode except that operation returns to mode In SLOW1 and SLEEPI modes the input clock to the 1st stage of the divider is stopped output from the 1st to 6th stages is also stopped 6 SLEEP2 m
222. are controlled by the BOOTROM and steps 3 through 10 are controlled by the control executed in the RAM area Transfer the write control program to the RAM area in the RAM loader mode Jump to the RAM area Disable DI the interrupt master enable flag IMF 0 Set FLSCR lt FLSMD gt to 0011B to enable command sequence execution Execute the erase command sequence Read the same flash memory address twice Repeat step 6 until the same data is read by two consecutive reads operations Specify the bank to be written in FLSCR lt BANKSEL gt 8 Execute the write command sequence 9 Read the same flash memory address twice 10 Note 1 Note 2 Repeat step 9 until the same data is read by two consecutive reads operations Set FLSCR lt FLSMD gt to 1100B to disable command sequence execution Before writing to the flash memory in the RAM area disable interrupts by setting the interrupt master enable flag IMF to 0 Usually disable interrupts by executing the DI instruction at the head of the write control program in the RAM area Since the watchdog timer is disabled by the BOOTROM in the RAM loader mode it is not required to disable the watchdog timer by the RAM loader program Page 228 TOSHIBA T5CL8 Example After chip erasure the program in the RAM area writes data 3FH to address F000H DI LD LD LD LD FLSCR 00111000B 0 555 IY OFAAAH HL OFOOOH HHH Flash Memory Ch
223. ating EF or IL should be exe cuted before setting IMF 1 Note 3 Do not clear IL with read modify write instructions such as bit operations Interrupt Enable Registers Initial value 00000000 0000 0 EIRH EIRL 1514 13 12 10 9 8 7 6 5 4 3 2 1 0 003BH IMF EIRH 003BH EIRL 003AH Initial value 00000000 EIRE 0 7 6 5 4 3 2 1 002CH EF23 22 21 20 19 18 17 EF16 EIRE 002CH EF23 to EF4 Individual interrupt enable flag 0 Disables the acceptance of each maskable interrupt Specified for each bit 1 Enables the acceptance of each maskable interrupt R W IMF teripi master cnabi fia 0 Disables the acceptance of all maskable interrupts 9 1 Enables acceptance of all maskable interrupts Note 1 Don t care Note 2 Do not set IMF and the interrupt enable flag EF15 to EF4 to 1 at the same time Note 3 In main program before manipulating the interrupt enable flag EF or the interrupt latch IL be sure to clear IMF to 0 Disable interrupt by DI instruction Then set IMF newly again as required after operating on the EF or IL Enable interrupt by El instruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute normally on inter rupt service routine However if using multiple interrupt on interrupt service routine manipulating EF or IL should be exe cuted before setting
224. ation 4 1 1 0 0 0004000000000000000000000000000000000000150 208 HOHEM COCO M 209 17 10 bit AD Converter ADC 7 1 Configuration EP EROS PIS 211 17 2 Register 212 17 8 S d at ute e aw 215 17 3 1 Software Start 215 17 3 2 Repeat Mode 172373 Register Settihig 2o ed tete e eie e e cene eM 216 17 4 STOP SLOW Modes during AD 217 17 5 Analog Input Voltage and AD Conversion 218 17 6 Precautions about AD 219 17 6 1 Restrictions for AD Conversion interrupt INTADC 219 17 6 2 Analog input pin voltage range 17 6 3 Analog input shared pins vis 17 6 4 Noise Countermeasul dae 0 des gea eee eee aon eu eeu eer Eon a 18 Wakeup KWU 181 Config rations Eo c eek de 221 1852 tex te Verte terat e OD 221 18 3 oues er es eeu eic bx e
225. ation Stand out amp resume relevant commands are listed ello OS BlackPepper3 RESUME 0X36 Start resume of one mode BlackPepper3 OS RESET STANDBY 0xb5 B te of data filed 1 in case of It means BP3 finished his stand stand out process RESUME CHECK STATUS 0xb4 It tells host that resume check is ok or ng If ok start pla ing from last position of this mode if ng start pla ing from first song In most of case host side don t need concern this command BlackPepper3 do it automaticall Stand out and resume command se uence HOST BP3 RESET STANDBY b501 SELECT MODELO Select a mode before resume play MODE_SEL_OK 80 RESUME 36 Start read and resume check after read If resume check ok then start resume play RESUME_CHECK_STATUS b4 Resume check ok or ng status In fact R S command flo s almost same as R command flo It return all of commands of R return ng but add one more R S S S command after read ng fnshed nd R S command ssue resume play f resume check ok or auto play from frst song f resume thers command return ng can refer to charper or a od error and easy ng programm ng n host soft are ts better send ng R S command after S orS s ready status f start to resume play of orS bout S orS status referto chatper 6 29 Set play position and recovery play lack epper has reco ery play funct on So host can nfo
226. automatically and hold the next shift operation until reading or writing is completed shown in Figure 15 2 Automatic wait Function Example of transmit mode The maximum time from releasing the automatic wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from SCK2 pin SIO2CR lt SIOS gt SCK2 pin output SO2 pin SIO2TDB Automatic wait is released by writing SIOZ2TDB Figure 15 2 Automatic wait Function Example of transmit mode Table 15 1 Serial Clock Rate fc 16 MHz fs 32 768 2 NORMAL 1 2 IDLE1 2 Mode SLOW1 2 2 SLEEP1 2 Mode TBTCR lt DV7CK gt 0 gt gt 1 Serial Clock Baud Rate Serial Clock Baud Rate Serial Clock Baud Rate 3 906 kbps 2048 bps fs 24 2048 bps 62 5 kbps 62 5 kbps Reserved 125 kbps 125 kbps Reserved 250 kbps 250 kbps Reserved 500 kbps 500 kbps Reserved 1 00 Mbps 1 00 Mbps Reserved 2 00 Mbps 2 00 Mbps Reserved Page 180 05 Hn 2 External clock When an external clock is selected by setting SIO2CR lt SCK gt to 111B the clock the SCK2 pin from an external source is used as the serial clock To ensure shift operation the serial clock pulse width must 4 fc or more for both and levels SCK2 pin gt tSCKL tSCKL SCKH gt 4 fc Figure 15 3
227. b lt sono AC ANA Nd SET J BSF DATA Be NS a soo itd 106 ases cont un gt 0 D H so or 11 C603 cM To UP C250H 25 TF toour idy 0645 gt at MES aRERRRRREK RBBB ES p n 5129024 20K R216 oR 8909220 1 B 8 8016 cen P 20442 4 M Ra20 it 8 RUDI gt SENSE E TE TG IE TB a 1004F E S183 i 16602 mo t C618 104 a H zE 4 7 m En t cd ed 48 co ve 84 2 E N MDC Ss Toner iis gl e 8 E 4880 1 1 2 P 5 ti peel cem g E Eu E ud ge 6 8 ovonst t i C631 66 oR 3 sss mE ms Xo E RET ax 7 125685555855 C830 L Tes exe CD RCH 2 28804324282 25548 88 cen Y 2 sono 0 een i AVCC3 3V 4 4 s 1 4 i lt ACC DET 8 Lope gt 2 ruen nes 88 E toa D 4 gt SGND 104 t 4 E 4 8 77 85 Ei Bt gt 22K 55
228. baud rate of UARTI is set of UARTICRI BRG The example of the baud rate are shown as follows Table 12 1 Transfer Rate Example Source Clock 76800 baud 38400 baud 19200 baud 38400 19200 9600 19200 9600 4800 9600 4800 2400 4800 2400 1200 2400 1200 600 When is used as the UART transfer rate when UARTICRI BRG 110 the transfer clock and transfer rate are determined as follows Transfer clock Hz source clock Hz TTREG3 setting value Transfer Rate baud Transfer clock Hz 16 12 5 Data Sampling Method The UARTI receiver keeps sampling input using the clock selected by UARTICR1I lt BRG gt until a start bit is detected in RXD1 pin input RT clock starts detecting L level of RXDI pin Once a start bit is detected the start bit data bits stop bit s and parity bit are sampled at three times of RT7 RT8 and RT9 during one receiver clock interval RT clock RTO is the position where the bit supposedly starts Bit is determined according to major ity rule The data are the same twice or more out of three samplings RXD1 pin Start bit Bit 0 RTO 12 34 5 6 7 8 9 10111213 14150 12 34 5 6 7 9 10 11 RT clock Internal receive data Start bit Bit 0 Without noise rejection circuit RTO 12 3 4 5 6 7 8 9 1011121314150 12 34 56 7 10 11 RT clock Internal receive data Start bit Bit 0 b With noise r
229. being cleared the up counter continues counting Program the lower byte and upper byte in this order in the timer register Programming only the upper or lower byte should not be attempted Note 1 In the timer mode fix TCjCR lt TFFj gt to 0 If not fixed the PWMj and PPGj pins may output a pulse Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediately after programming of TTREGj Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 3 4 Table 10 6 Source Clock for 16 Bit Timer Mode Source Clock Resolution Maximum Time Maximum Time Setting 1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode Example Setting the timer mode with source clock fe 2 Hz and generating an interrupt 300 ms later 16 0 MHz LDW 927CH Sets the timer register 300 ms 27 fc 927CH DI SET EIRH 1 Enables INTTC4 interrupt El LD TC3CR 13H Sets the operating clock to fc 2 and 16 bit timer mode lower byte LD TC4CR 04H Sets the 16 bit timer mode upper byte LD TC4CR OCH Starts the timer TC4CR lt TC4S gt Internal 1 Source clock 1 Counter
230. bit mode Q gt 5 s Timer PDO5 PWMB Event Couter mode pin TC5M TC5S Timer F F5 TFF5 TC5CR TTREG5 PWREG5 O 16 bit mode T d d Figure 11 1 8 Bit TimerCounter 5 6 Page 119 11 8 Bit TimerCounter 5 6 11 1 Configuration igurati T5CL8 11 2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register TCSCR and two 8 bit timer registers TTREGS PWREGS TimerCounter 5 Timer Register 5 7 6 5 4 3 2 1 0 0016H R W Initial value 1111 1111 PWREGS 7 6 5 4 3 2 1 0 001 R W Initial value 1111 1111 Note 1 Do not change the timer register TTREG5 setting while the timer is running Note 2 Do not change the timer register PWREGS setting in the operating mode except the 8 bit and 16 bit PWM modes while the timer is running TimerCounter 5 Control Register TC5CR 7 6 5 4 3 2 1 0 0029H TC5CK TC5S TC5M Initial value 0000 0000 TFF5 Time F F5 control NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 010 Operating clock selection Hz 011 100 101 110 fc fc fc Note 8 111 TC5 pin input TC5S TCS start control 0 Operation stop and counter clear RIW 1 Operation start 000 8 bit timer event counter mode 001 8 bit programmable divider output PDO mode TC5M TOSM operating mode select 010 8 0 pulse width modulation PWM output mode 011 16 bit mode Each mode is select
231. ble se pertinent command to reali e these operation After these command sent BP3 playing status will be change quickly but sometimes it need a moment For FF F operation there is a high speed or low speed selection They are invalid for D device in fact Even for mp3 wma file D Speed is changed only after current song playing is finished the speed becomes effective at next song playing But for audio track playing D DA or IX D it becomes effective any time Please be careful this issue For FF F operation there is another selection about mute sound or 1 db outputing audio But please be noted that the sound mute is control byA DI pin About A DI TE pin will be described later If hos want this function he need to connect this pin And please be noted that F status can be release automatically in some case like F to the first song header to song header in repeat 1 mode etc About the status change more detailed information is available later elevant commands are listed bellow T BlackPepper3 PAUSE 0x19 tart pause PAUSE RELEASE 0x1a elease pause condition FF 0x1b tart FF playing FR 0x1c tart F playing FF FR RELEASE 0x1d elease FF or F condition BlackPepper3 T 36 TOSHIBA T5CJ3 7G28 F M Specification PLAY STATUS 0x84 0x00 PLAY STATUS 0x01 STOP STATUS Ox0 PAUSE STATUS 0x03 PAUSE RELEASE Ox0 0 0 FFSTATUS 0 0 0 0 FR STATUS OxOd FF release or FR
232. buffer full flag 4 Receive data buffer full 0 Ont itti TEND Transmit end flag bel 1 Transmit end TBEP Transmit data buffer empty flag 0 Transmit data buffer full Transmit data writing is finished 1 Transmit data buffer empty Note When an INTTXD is generated TBEP flag is set to 1 automatically UART1 Receive Data Buffer RD1BUF 7 6 5 4 3 2 1 0 Read only T T T T T T d emm nm UART1 Transmit Data Buffer TD1BUF 7 6 5 4 3 2 1 0 Write only em T TTL d eee soon Page 141 12 Asynchronous Serial interface UART1 12 3 Transfer Data Format T5CL8 12 3 Transfer Data Format In UARTI an one bit start bit Low level stop bit Bit length selectable at high level by UART1CR1 lt STBT gt and parity Select parity in UART1CR1 lt PE gt even or odd numbered parity by lt gt are added to the transfer data The transfer data formats are shown as follows Frame Length se JC Y se De ay Figure 12 2 Transfer Data Format Without parity 1 STOP bit With parity 1 STOP bit Without parity 2 STOP bit With parity 2 STOP bit Figure 12 3 Caution on Changing Transfer Data Format NY Note In order to switch the transfer data format perform transmit operations in the above Figure 12 3 sequence except for the initial setting Page 142 05 Hn 12 4 Transfer Rate The
233. by TC4CR lt TFF4 gt positive and negative pulses can be generated Upon reset the timer 4 15 cleared to 0 The logic level output from the PPG4 pin is the opposite to the timer F F4 Set the lower byte and upper byte in this order to program the timer register TTREG3 TTREG4 PWREG3 Programming only the upper or lower byte should not be attempted For PPG output set the output latch of the I O port to 1 Example Generating a pulse with 1 ms high level width and a period of 16 385 ms fc 16 0 MHz Setting ports LDW PWREGS3 0700 Sets the pulse width LDW 8002H Sets the cycle period 3 LD TC3CR 33H Sets the operating clock to fc 2 and16 bit PPG mode lower byte Sets 4 to the initial value 0 and 16 bit LD TC4CR 057H mode upper byte LD TCACR 05FH Starts the timer Note 1 In the PPG mode do not change the PWREGi and TTREGi settings while the timer is running Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode the new values grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and Therefore if PWREGi and TTREGi are changed while the timer is running an expected operation may not be obtained Note 2 When the timer is stopped during PPG output the PPG4 pin holds the output status when the timer is stopped To change the output status program TC4CR l
234. bytes of operation command error code 63H 4 The 9th through 13th bytes contain the status code For details on the status code refer to 20 12 Flash Memory Status Code 5 After sending the status code the device waits for the next operation command data Page 251 20 Serial PROM Mode 20 6 Operation Mode perati T5CL8 20 6 7 Flash Memory security program Setting Mode Operation Command FAH Table 20 13 shows Flash memory security program setting mode process Table 20 13 Flash Memory security program Setting Mode Process Transfer Bvtes Transfer Data from External Con Baud Rate Transfer Data from T5CL8 y troller to T5CL8 External Controller 1st byte Matching data 9600 bps Automatic baud rate adjustment 2nd byte 9600 bps OK Echo back data Error Nothing transmitted 3rd byte Baud rate modification data 9600 bps See Table 20 4 4th byte 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 Operation command data FAH Modified baud ra Modified baud ra OK Echo back data FAH Error A1H x 3 A3H x 3 63H x 3 Note 1 Password count storage address Modified baud ra 15 to 08 Note 2 Modified baud ra OK Nothing transmitted Error Nothing transmitted 9th byte Password count storage address Modified baud ra 10th byte 07 to 00 Note 2 Modified baud ra OK Nothing transmitted Error Nothing transmitted 11th byte Password comparison start Modified baud ra 12th byte ad
235. ce clock falling edge which 15 setting by the lt gt After the falling edge is detected the program operation is resumed from the instruction following the IDLEO and SLEEPO modes start instruction Before starting the IDLEO or SLEEPO mode when the lt gt is set to 1 INTTBT interrupt latch is set to 1 2 Interrupt release mode IMFeEF7eTBTCR TBTEN 1 IDLEO and SLEEPO modes are released by the source clock falling edge which is setting by the lt gt and INTTBT interrupt processing is started Note 1 Because returning from IDLEO SLEEPO to NORMAL 1 SLOW1 is executed by the asynchro nous internal clock the period of IDLEO SLEEPO mode might be the shorter than the period set ting by lt gt Note 2 When a watchdog timer interrupt is generated immediately before IDLEO SLEEPO mode is started the watchdog timer interrupt will be processed but IDLEO SLEEPO mode will not be started Page 26 T5CL8 TOSHIBA esee a1 odds pue adi 9 eseejeJ jdnueju uonnoexe uononusu jdnuuejur jo eouejdeooy Jejunoo Lal yoojo 5 uonnoexe uononasu SseJppe uoronJjsu Jejunoo LaL yoojo
236. ceive mode are selected by writing 10 to SIO2CR lt SIOM gt 1 Starting the transmit receive operation Transmit receive mode is selected by writing 10B to SIO2ZCR lt SIOM gt Serial clock is selected by using SIO2CR lt SCK gt Transfer direction is selected by using SIO2CR lt SIODIR gt When a transmit data is written to the transmit buffer register SIO2TDB SIO2SR lt TXF gt is cleared to 0 After SIO2CR lt SIOS gt is set to 1 SIO2SR lt SIOF gt is set synchronously to the falling edge of SCK2 pin The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by SIO2CR lt SIODIR gt synchronizing with the SCK2 pin s falling edge And receiving operation also starts with the direction of the bit specified by SIO2CR lt SIODIR gt synchronizing with the SCK2 pin s rising edge SIO2SR lt SEF gt is kept in high level between the first clock falling edge of SCK2 pin and eighth clock falling edge 51025 lt gt is set to 1 at the rising edge of SCK2 pin after the data written to the SIO2TDB is transferred to shift register When 8 bit data has been received the received data is transferred to SIO2RDB from shift register then the INTSIO2 interrupt request occurs synchronizing with setting SIO2SR lt RXF gt to 1 Note 1 In internal clock operation when the SIO2CR lt SIOS gt is set to 1 SIO2TDB is transferred to shift register after maximum 1 cy
237. ceive operation confirm that SIOISR lt SIOF gt is cleared to 0 If the received error occurs set SIO1CR lt SIOINH gt to 1 for stopping the receive operation immediately In this case SIOICR SIOS SIOISR register SIOIRDB reg ister and SIOITDB register are initialized Page 175 14 Synchronous Serial Interface 5101 14 3 Function T5CL8 SIO1CR SIOS Start shift Start shift Start shift operation Y operation SIO1SR SEF SCKT pin output 501 pin ___________ __ sit pin V699939999999900 0 interrupt request GR Unknown Writing transmit al transmit transmit data A data B data C SIO1SR RXF M SIO1SR RXERR soros Reading received Reading received data D data E SIO1CR sSIOINH Figure 14 16 Example of Transmit Receive Receive Error Processing Note If receive error is not corrected an interrupt request does not generate after the error occurs SCK1 pin SIO1SR lt SIOF gt i SODH Alfc lt tSODH lt 8 fc Figure 14 17 Hold Time of the End of Transmit Receive Mode Page 176 05 15 Synchronous Serial Interface 5102 The serial interfaces connect to an external device via SI2 SO2 and SCK2 pins When these pins are used as serial interface the output latches for each port should be set to 1 15 1 Configuration Internal data bus SIO2CR SIO2SR SIO2TDB
238. change the timer register TTREG3 setting while the timer is running Note 2 Do not change the timer register PWREG3 setting in the operating mode except the 8 bit and 16 bit PWM modes while the timer is running TimerCounter 3 Control Register TC3CR 7 6 5 4 3 2 1 0 0027H TC3CK TC3S TC3M Initial value 0000 0000 Time F F3 control NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 010 Operating clock selection Hz 011 100 101 110 fc fc fc Note 8 111 TC3 pin input TC3 start control 0 Operation stop and counter clear RIW 1 Operation start 000 8 bit timer event counter mode 001 8 bit programmable divider output PDO mode TC3M TC3M operating mode select 010 8 0 pulse width modulation PWM output mode 011 16 bit mode Each mode is selectable with TC4M 1 Reserved Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note 2 Do not change the TC3M TC3CK and TFF3 settings while the timer is running Note 3 To stop the timer operation TC3S 1 0 do not change the TC3M TC3CK and TFF3 settings To start the timer opera tion TC3S 0 gt 1 TC3M TC3CK and TFF3 be programmed Note 4 To use the TimerCounter in the 16 bit mode set the operating mode by programming lt gt where TC3M must be fixed to 011 Note 5 To use the TimerCounter in the 16 bit mode select the source clock by programming TC3CK Set the t
239. cho back data C3H Error A1H x 3 A3H x 3 63H x 3 Note 1 Modified baud rate Start mark Modified baud rate 04H Byte count from 9th to 12th byte 7th 8th byte BOOT oth byte Modified baud rate Status code 1 ROM 10th byte Modified baud rate 00H Reserved data 11th byte MEE Modified baud rate 00H Reserved data 12th byte Do Modifedbaudrate _ Modified baud rate 00H Reserved data 13th byte Modified baud rate Checksum 2 s complement for the sum of 9th through 12th bytes 9th byte Checksum OOH 00H 01H FFH js 14th byte Wait for the next operation com Modified baud rate mand data Note 1 xxH x 3 indicates that the device enters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Note 2 For the details on status code 1 refer to 20 12 Flash Memory Status Code Description of Flash memory status output mode 1 The Ist through 4th bytes of the transmitted and received data contain the same data as in the Flash memory writing mode 2 The 5th byte of the received data contains the flash memory status output mode command data C3H 3 When the 5th byte contains the operation command data shown in Table 20 6 the device echoes back the value which is the same data in the 6th byte position of the received data 1n this case C3H If the 5th byte does not contain the operation command data the device enters the halt condition after send ing 3
240. ck total time second 25 TOSHIBA T5CJ3 7G28 F M Specification 0x00 bookmark set ok BOOKMARK STATUS 0xde byte 0 0x01 bookmark set NG 0x00 bookmark play ok BOOKMARK PLAY STATUS 0xdf byte 0 0x01 bookmark play NG 0x02 SD card is removed 0x03 SD card is inserted 0x05 SD card detect ready 0x07 SD card detect error 0x10 USB bus is stoped 0 11 USB bus is initializing 0x12 USB device is removed 0x13 USB device is inserted USB SD DET STATUS 0xe0 byte 0 0x15 USB device detect ready 0x16 USB fatal error need hardware reset 0 17 U U U U 0 14 USB class is under checking U U USB detect error U 0x18 USB class is not support 0x19 USB is not ready 1 Limited USB device if don t read iPod as MSC other reserved PLAY POSITION Oxea byte 0 position parameter 1 1 position parameter 2 byte 2 position parameter 3 3 position parameter 4 byte 4 position parameter 5 5 position parameter 6 FIRMWARE VERSION 0xf7 byte 0 0x01 firmware version case this byte is fixed to 0x01 byte 1 version value FIRMWARE FEATURE 0xf7 byte 0 0x00 firmware feature case this byte is fixed to 0x00 byte 1 feature parameter 26 TOSHIBA T5CJ3 7G28 F M Specification 6 Function details This chapter describes all of function about BlackPepper3 6 1 Reset and select your pick up After syste
241. cle of serial clock frequency then a serial clock is output from 5 2 pin Note 2 In external clock operation when the falling edge is input from SCK2 pin after SIO2CR lt SIOS gt is set to 1 SIO2TDB is transferred to shift register immediately When the rising edge is input from 5 2 pin receive operation also starts Page 189 15 Synchronous Serial Interface 5102 15 3 Function 2 3 T5CL8 During the transmit receive operation When data is written to SIO2TDB 51025 lt gt is cleared to 0 and when a data is read from SIO2RDB SIO2SR lt RXF gt is cleared to 0 In internal clock operation in case of the condition described below the serial clock stops to H level by an automatic wait function when all of the bit set in the data has been transmitted Next transmit data is not written to SIOZ2TDB after reading a received data from SIO2RDB Received data is not read from SIO2RDB after writing a next transmit data to SIOZTDB e Neither SIO2TDB nor SIO2RDB is accessed after transmission The automatic wait function is released by writing the next transmit data to SIO2TDB after reading the received data from SIO2RDB or reading the received data from SIO2RDB after writing the next data to SIO2TDB Then transmit receive operation is restarted after maximum 1 cycle of serial clock In external clock operation reading the received data from SIO2RDB and writing the next data to SIO
242. combustion control instruments medical instruments all types of safety devices etc Unintended Usage of TOSHIBA products listed in this document shall be made at the customer s own risk 021023 B The products described in this document shall not be used or embedded to any downstream products of which manufacture use and or sale are prohibited under any applicable laws and regulations 060106 Q The information contained herein is presented only as a guide for the applications of our products No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties 070122 C The products described in this document are subject to foreign exchange and foreign trade control laws 060925 E For a discussion of how the reliability of microcontrollers can be predicted please refer to Section 1 3 of the chapter entitled Quality and Reliability Assurance Handling Precautions 030619 S O 2007 TOSHIBA CORPORATION Rights Reserved Revision History Date Revision 2008 7 31 1 First Release Table of Contents Differences among Products T5CL8 Tos c c dtes ee a eat ds deett 1 2
243. ctrical Characteristics 22 1 Absolute Maximum 6 22 2 Operating 22 2 1 mode Flash Programming or 268 22 2 2 mode Except Flash Programming or 268 22 9 3 Serial PROM een eee eere ea eae vue ep xe eua oe kv dee e eee era ee ehe x eva er deae ge e aeu 269 22 9 DO CHaraCtEnStiCS 5 24 356 EEUU Ga el A aia EE 224 AD Characteristics aoe biu uu a dec ba ene Gel 20 5 Characteristics dt tra ae tiat e tec 22 6 Flash 22 6 1 Write Retention Characteristics 1 2 1 2 002 0000000110000000000000000000000000 273 227 Recommended Oscillating 22 8 Handling Precaution 23 Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8 bit microcontroller series TLCS 870 C LSD 05 CMOS 8 Bit Microcontroller TSCL8 5 8 is a single chip 8 bit high speed and high functionality microcomputer incorporating 61440 bytes of Flash Memory ROM Product No FLASH RAM Pack
244. curs in data or input output status an inter rupt request signal is generated in a pseudo manner In this case it is necessary to perform appropriate processing such as disabling the interrupt enable flag Page 43 3 Interrupt Control Circuit 3 7 External Interrupts T5CL8 External Interrupt Control Register EINTCR 7 6 5 4 3 2 1 0 0037H INTOEN __ INT3ES iNT2ES INT1ES Initial value 00 0007 0 Pulses of less than 63 fc s are eliminated as noise Noise reject time select 1 Pulses of less than 15 fc s are eliminated as noise 0 input output port INTOEN POO INTO fi ti 1 INTO Port should be set to an input mode 0 Risi d INT2 ES INT2 edge select SUM e 1 Falling edge 0 Risi d INT1 ES INT1 edge select 03 ee 1 Falling edge Note 1 fc High frequency clock Hz Don t care Note 2 When the system clock frequency is switched between high and low or when the external interrupt control register EINTCR is overwritten the noise canceller may not operate normally It is recommended that external interrupts are dis abled using the interrupt enable register EIR 0 Ri d INT3 ES INT3 edge select ising 1 Falling edge Note 3 The maximum time from modifying INT1NC until a noise reject time is changed is 26 Page 44 TOSHIBA 4 Special Function Register SFR T5CL8 The T5CL8 adopts the memo
245. d The divider is not cleared by the program therefore only the first interrupt may be generated ahead of the set interrupt period Figure 7 2 Source clock TBTCR lt TBTEN gt A j 1 Interrupt period Enable TBT Figure 7 2 Time Base Timer Interrupt Page 74 05 7 2 Divider Output DVO Approximately 50 duty pulse can be output using the divider output circuit which is useful for piezoelectric buzzer drive Divider output is from DVO pin 7 2 1 Configuration Output latch Data output fc 23 fs 29 fc 21 fs 24 fc 21 or fs 23 219 or 16 22 Port output latch TBTCR lt DVOEN gt i 4 DVOEN i 1001 1 DVO output a configuration b Timing chart Divider output control register Figure 7 3 Divider Output 7 2 2 Control The Divider Output is controlled by the Time Base Timer Control Register Time Base Timer Control Register 7 0 TBTCR 0036H DVOEN DVOCK DV7CK TBTEN TBTCK Initial value 0000 0000 Divider output 0 Disable DVEEN enable disable 1 Enable NORMAL1 2 IDLE1 2 Mode IDLE1 2 Mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 Mode Note Selection of divider output frequency DVOCK must be made while divider output is disabled DVOEN 0 Also in other words when changing the state of the divider output frequency from enabled DVOEN 1 t
246. d by setting 1 to the MST TRX and PIN and clear 0 to the Do not modify the contents of the MST BB PIN until a stop condition is generated on a bus When a SCL line on a bus is pulled down by other devices a serial bus interface circuit generates a stop con dition after they release a SCL line The time from the releasing SCL line until the generating the STOP condition takes tj ow Page 208 05 Hn 0 gt 1 PIN 1 gt MST 1 gt Stop condition SDA pin PIN BB Read Figure 16 13 Stop Condition Generation 16 6 5 Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data The following explains how to restart a serial bus interface circuit Clear 0 to the MST and BB and set 1 to the PIN The SDA pin retains the high level and the SCL pin is released Since a stop condition is not generated on a bus a bus is assumed to be in a busy state from other devices Test the BB until it becomes 0 to check that the SCL pin of a serial bus interface circuit 1s released Test the LRB until it becomes 1 to check that the SCL line on a bus is not pulled down to the low level by other devices After confirming that a bus stays in a free state generate a start condition with proce dure 16 6 2 Start condition and slave address generation In order to meet setup time w
247. d during PDO output the PDOj pin holds the output status when the timer is Stopped To change the output status program TCjCR lt TFFj gt after the timer is stopped Do not change the TCjCR lt TFFj gt setting upon stopping of the timer Example Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the PDOj pin to the high level Note 3 5 6 127 11 8 Bit TimerCounter 5 TC6 11 1 Configuration T5CL8 peddois 1 BY USYM 1 1 3 4195 4 1 1 YEN NNNM SNNT ANSA ZX OMX AA CANA dA SAC 1 1 aba JO SWIM i 1senbej 901 1 94 4 99381 1 eounos lt 9441 gt 49901 lt 5901 gt 40901 Figure 11 4 8 Bit PDO Mode Timing Chart TC6 Page 128 05 11 3 4 8 Bit Pulse Width Modulation PWM Output Mode TC5 6 This mode is used to generate a pulse width modulated PWM signals with up to 8 bits of resolution The up counter counts up using the internal clock When a match between the up counter and the PWREGj value is detected the logic level output from the timer 1s switched to the opposite state
248. d o ill not clear t is setting ele ant commands are listed ello S e MUTE 0x35 m te on m te off e er S MUTE_STATUS 0x8c to to ence 1 60 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 Mute on 3500 Mute 8 00 Case 2 mute off HOST BP3 Mute off 3501 Mute 8 01 6 24 About driver mute pin e er asone U in toot tdri er m te signal D U ot t in D mode ando t t inan ot er mode 6 25 Flash upgrading e er canconnect ae ternal it flas as ing e er can grade rogram for e ternal B t at first itneed toco a file to USB de ice root folder en grading e ternal flas r n rogram of internal code after grading is finis ed t enB canr n e ternal rogram So lease notes setting AM1 rn rogram in internal rom rogram ine ternal flas ormall if starting grading its o ld s to internal rom nning after grading is finis ed t en s to e ternalflas r nning f connected a e ternal flas itm st set D not onl r nning in e ternal flas t also nning in internal rom o tcontrolflo lease refertoflo c art ele ant commands are listed ello S Blac e er EXT FLASH UPGRADE 0x45 Start grading e ternal flas e S EXT FLASH UPGRADE 0 8 t means e ternal flas grading is finis ed and 61 TOSHIBA T
249. d the timer register j TTREGj value is detected an INTTCj interrupt is generated and up counter is cleared After being cleared the up counter restarts counting Note 1 In the timer mode fix TCjCR TFFj to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 5 6 Table 11 4 Source Clock for TimerCounter 5 6 Internal Clock Source Clock Maximum Time Setting NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode fc 211 Hz 15 23 Hz fs 23 Hz 27 27 fc 25 fc 25 fc 23 fc 23 Example Setting the timer mode with source clock fc 27 Hz and generating an interrupt 80 later TimerCounter6 fc 16 0 MHz LD TTREG6 OAH Sets the timer register 80 us 2 fc OAH DI SET EIRE 2 Enables INTTC6 interrupt El LD TC6CR 00010000B Sets the operating clock to fc 2 and 8 bit timer mode LD TC6CR 00011000B Starts TC6 Page 125 11 8 Bit TimerCounter 5 TC6 11 1 Configuration igurati T5CL8 TC6CR lt TC6S gt Internal 1 Sourc
250. d3 album information of mp3 wma file c3 GET INFO FILE NAME Oxff 2 0 80 0x03 OxNN file name of mp3 wma file c3 INFO DIR NAME 2 0 80 0 04 OxNN get folder name of mp3 wma file c3 INFO STREAM loxtr 2 0x80 0x05 OxNN leet stream information of mp3 wma file c3 CD TEXT 3 0 81 OxNN cd text information cl CD TRACK INFO loxer 2 10 82 OxNN m cd track information cl SET FIRMWARE 2 0 83 OxNN set firmware feature FIRM VERSION 2 0 80 0 07 OxNN firmware version Note c1 valid when read process is finished and device is play available C2 valid when read process is finished device is play available and current state is stop c3 valid in just play state include play pause FF FR c4 valid just after BP2 request pick up selection About DATA details please refer to 5 3 PART 1 TOSHIBA T5CJ3 7G28 F M Specification PARTII Command list send from BlackPepper3 to host MCU command name sync length data checksum function description note MODE SEL 1 0 80 OxNN lack to select mode command DEVICE TYPE 2 10 82 OxNN type information ERROR CODE Oxff 2 10 83 OxNN error play error information ERROR CODE UPGRADE 2 Ox83 DATA OxNN luperade error information STATUS O
251. das e dU etes 9 2 CONTONA a e C Ext D Du 9 9 EUNN eed Aine OS RS OU Nes INDE ER ENDE 9 919 Timer mode Sie ii erties codi nee LA gt eh tao ee oe 95 9 8 2 Event counter mode 9 9 9 n WindoW modB 97 10 8 Bit TimerCounter TC3 4 10 1 Config ratiOmns ehe t oe ere ete erem ORC a 10 2 TimerCounter 10 85 Funciones emos ome UU tote x st ei Mu 10 3 1 10 3 2 10 8 8 10 8 4 10 8 5 10 8 6 10 8 7 10 8 8 10 8 9 8 Bit Timer Mode and 4 8 Bit Event Counter Mode TC3 4 8 Bit Programmable Divider Output PDO Mode TC3 4 8 Bit Pulse Width Modulation PWM Output Mode 4 109 16 Bit Timer Mode TC3 and 4 16 Bit Event Counter Mode and 4 16 Bit Pulse Width Modulation PWM Output Mode and 4 16 Bit Programmable Pulse Generate PPG Output Mode TC3 and 4 Warm Up Counter Mode C n o 10 3 9 1 Low Frequency Warm up Counter Mode NORMAL1 gt NORMAL2 gt SLOW2 gt SLOW1 10 3 9 2 High Frequency Warm Up Counter Mode SLOW1 SLOW2 gt NORMAL2 gt NORMAL1 11 8 Bit TimerCounter TC5 TC6 14 21 Configurations e ier na Rex Meira dtes ue lb Baa 11 2 TimerCounter
252. data contain the same data as in the flash memory writing mode In the case of a blank product do not transmit a password string Do not transmit a dummy password string Then th 2 byte contains the erasure area specification data The upper 4 bits and lower 4 bits specify the start address and end address of the erasure area respectively For the detailed description see 1 13 Specifying the Erasure Area The n th 1 byte and n th byte contain the upper and lower bytes of the checksum respectively For how to calculate the checksum refer to 1 8 Checksum SUM Checksum is calculated unless receiving error or Intel Hex format error occurs After sending the end record the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device After sending the checksum the device waits for the next operation command data Page 242 T5CL8 TOSHIBA 20 6 2 Flash Memory Writing Mode Operation command 30H Table 20 8 shows flash memory writing mode process Table 20 8 Flash Memory Writing Mode Process Transfer Data from T5CL8 to External Controller Transfer Data from External Controller to TSCL8 Baud Rate Transfer Byte 1st byte Matching data 5Ah 2nd byte 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data Error Nothing transmitted 3rd by 4th Baud rate modification data 9600 bps See Tab
253. de after stop 0x01 stop If it is CD mode keep pick up position after stop 0x00 start FF at normal speed FF 0x1b byte 0 0x01 start FF at high speed 0x80 start FF at normal speed mute pin output H 17 TOSHIBA T5CJ3 7G28 F M Specification 0x81 start FF at high speed mute pin output 0x00 start FR at normal speed 0x01 start FR at high speed FR 0x1c byte 0 0x80 start FR at normal speed mute pin control 0x81 start FR at high speed mute pin control POSITION PLAY 0x20 byte 0 position parameter 1 byte 1 position parameter 2 byte 2 position parameter 3 3 position parameter 4 4 position parameter 5 5 position parameter 6 0x01 select CD mode SELECT MODE 0x30 byte 0 0x02 select USB mode 0x03 select SD mode 0x00 mute on mute pin control MUTE 0x35 byte 0 0x01 mute off mute pin control 0x00 intro on INTRO_MODE 0x38 byte 0 0x01 intro off 0x00 repeat off 0x01 repeat 1 REPEAT MODE 0x39 byte 0 0x02 repeat dir 0x03 repeat all 0x00 random on 0x01 random track iPod only RANDOM MODE 0x3a byte 0 0x02 random album iPod only 0x03 cancel random mode TOSHIBA T5CJ3 7G28 F M Specification 0x00 cancel A B repeat REPEAT 0x3f byte 0 0 01 set start point 0x02 set end point 0 Sanyo DA11 1x 1 Sanyo DA23 1x 2 SamsungB55 1x 3 default 4
254. de is UTF 16BE 24 TOSHIBA T5CJ3 7G28 F M Specification byte 1 select folder name first byte byte 2 select folder name byte select folder name last byte DIR INSIDE INFO 0xc2 byte 0 local total file number in selected folder high byte byte 1 local total file number in selected folder low byte byte 2 local start file number in selected folder high byte byte 3 local start file number in selected folder low byte DIR INFO OF FILE 0xc3 byte 0 folder number of selected file high byte 1 folder number of selected file low byte byte 2 local total file number in this folder high byte 3 local total file number in this folder low byte byte 4 local start file number in this folder high byte byte 5 local start file number in this folder low byte 0x00 file number is wrong SELECT WRONG 0xc6 0 0x01 folder number is wrong PLAY CD TRACK ATIME 0xd0 byte 0 A time minute byte 1 A time second mp3 wma minute high byte PLAY SONG TOTAL TIME 0xd2 byte 0 ed track minute mp3 wma minute low byte byte 1 cd track second mp3 wma second byte 2 cd track frame track type CD TRACK INFO 0xd5 byte 0 0x00 audio track 0x01 data track byte 1 track number byte 2 track start MSF minute 3 track start MSF second byte 4 track total time minute 5 tra
255. ded Figure 2 16 Address Trap Reset 2 3 3 Watchdog timer reset Refer to Section Watchdog Timer 2 3 4 System clock reset If the condition as follows is detected the system clock reset occurs automatically to prevent dead lock of the CPU The oscillation is continued without stopping In case of clearing SYSCR2 lt XEN gt and 5 5 2 lt gt simultaneously to 0 In case of clearing SYSCR2 lt XEN gt to 0 when SYSCR2 lt SYSCK gt is 0 In case of clearing SYSCR2 lt XTEN gt to 0 when the SYSCR2 lt SYSCK gt is 1 The reset time is maximum 24 fc 1 5 us at 16 0 MHz Page 32 05 33 2 Operational Description 2 3 Reset Circuit T5CL8 Page 34 TOSHIBA 3 Interrupt Control Circuit The 5 8 has a total of 24 interrupt sources excluding reset Interrupts can be nested with priorities Four of the internal interrupt sources are non maskable while the rest are maskable Interrupt sources are provided with interrupt latches IL which hold interrupt requests and independent vectors The interrupt latch is set to 1 by the generation of its interrupt request which requests the CPU to accept its inter rupts Interrupts are enabled or disabled by software using the interrupt master enable flag IMF and interrupt enable flag EF If more than one interrupts are generated simultaneously interrupts are accepted in order which 15 domi nated
256. default 5 Sanyo 11 2 6 Sanyo DA23 2x 7 SamsungB55 2x PICK UP_SELECT 0x040 byte 0 8 Tanashin 2007 2x 9 Shinny IS68 2x 10 CP2 2x 11 Shinwa CLCO1 2x 12 ShinwaCLC08 2x 13 TN2002 14 default 15 default 16 254 reserved 255 read coefficient data from E2PROM SEND_INIT_CMD 0x41 byte 0 Ist byte of initial command byte 1 2nd byte of initial command byte 2 3rd byte of initial command byte n SEND_EQ_DATA 0x42 byte 0 Ist byte of EQ data byte 1 2nd byte of EQ data 2 3rd byte of EQ data byte n SEND RF DATA 0x43 byte 0 Ist byte of RF data byte 1 2nd byte of RF data byte 2 3rd byte of RF data byte n MCU sequence number 0 Redchili 1 TMP91FW27 MCU_UPGRADE 0x46 byte 0 2 TMP91FY42 3 TMP91FW60 4 TMP91FU62 TOSHIBA T5CJ3 7G28 F M Specification 0x00 system off SYSTEM ON OFF 0x4f byte 0 0x01 system on 0x00 get title content GET CD TEXT 0x81 byte 0 0x01 get artist content byte 1 track number GET CD TRACK INFO 0x82 byte 0 track number feature parameter default is 0000 0000b 0000 0001b USB SD reading method setting set 0 search folder by directory path set 1 search folder by parent child recommend 0000 0010b CD ROM reading method setting set 0 path table sort order CD ROM set 1 parent child sort order CD ROM 0000_0100b SPDIF setting SET_FIRMWARE
257. dification becomes effective If the 3rd byte of the received data does not contain the baud rate modification data the device enters the halts condition after sending 3 bytes of baud rate modification error code 62H The 5th byte of the received data contains the command data 30H to write the flash memory When the 5th byte of the received data contains the operation command data shown in Table 1 6 the device echoes back the value which is the same data in the 6th byte position of the received data in this case 30H If the 5th byte of the received data does not contain the operation command data the device enters the halt condition after sending 3 bytes of the operation command error code 63H The 7th byte contains the data for 15 to 8 bits of the password count storage address When the data received with the 7th byte has no receiving error the device does not send any data If a receiving error or password error occurs the device does not send any data and enters the halt condition The 9th byte contains the data for 7 to 0 bits of the password count storage address When the data received with the 9th byte has no receiving error the device does not send any data If a receiving error or password error occurs the device does not send any data and enters the halt condition The 11th byte contains the data for 15 to 8 bits of the password comparison start address When the data received with the 11th byte has no receiving error the d
258. dition of TC1 A captured value may not be fixed if it s read after the execution of the timer stop or auto capture disable Read the capture value in a capture enabled condition Note 10 Since the up counter value is captured into TC1DRB by the source clock of up counter after setting TC1CR lt ACAP1 gt to 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading TC1DRB for the first time Page 79 8 16 Bit TimerCounter 1 1 8 3 Function T5CL8 8 3 Function TimerCounter 1 has six types of operating modes timer external trigger timer event counter window pulse width measurement programmable pulse generator output modes 8 3 1 Timer mode In the timer mode the up counter counts up using the internal clock When a match between the up counter and the timer register TCIDRA value is detected an INTTCI interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting Setting TCICR ACAPI to 1 captures up counter value into the timer reg ister TCIDRB with the auto capture function Use the auto capture function in the operative condition of TC1 cap tured value may not be fixed if it s read after the execution of the timer stop or auto capture disable Read the capture value in a capture enabled condition Since the up counter value is captured into TCIDRB by the source clock of up counter after setting
259. dress 15 to 08 Note 2 Modified baud ra OK Nothing transmitted Error Nothing transmitted 13th byte Password comparison start Modified baud ra 14th byte address 07 to 00 Note 2 Modified baud ra OK Nothing transmitted Error Nothing transmitted 15th byte Password string Note 2 Modified baud ra m th byte Modified baud ra OK Nothing transmitted Error Nothing transmitted n th byte Modified baud rate OK FBH Note 3 Error Nothing transmitted n 1th byte Wait for the next operation com Modified baud rate mand data Note 1 xxH x 3 indicates that the device enters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Note 2 Refer to 20 10 Passwords Note 3 If the security program is enabled for a blank product or a password error occurs for a non blank product T5CL8 stops UART communication and enters the halt mode In this case initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Note 4 If an error occurs during reception of a password address or a password string T5CL8 stops UART communi cation and enters the halt mode In this case initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Description of the Flash memory security program setting mode 1 The Ist through 4th bytes of the transmitted and received data contain the same data as in the Flash memory writing mode 2 The 5th byte of the received data contains the co
260. e to 1 and write the transmitted data to the SBIDBR After writing the data the PIN becomes 1 a serial clock pulse is generated for transferring a next 1 word of data from the SCL pin and then the 1 word of data 1s transmitted After the data 15 transmitted and an INTSBI interrupt request occurs The PIN become 0 and the SCL pin is set to low level If the data to be transferred is more than one word in length repeat the procedure from the LRB test above 1 2 3 4 5 6 8 9 0 D2 A D X DO M signal from receiver E EE t 1 Figure 16 10 Example of when 000 1 2 When the TRX is 0 Receiver mode SCL pin SDA pin PIN INTSBI interrupt request When the next transmitted data is other than of 8 bits set the BC again Set the to 1 and read the received data from the SBIDBR Reading data is undefined immediately after a slave address is sent After the data is read the PIN becomes 1 A serial bus interface circuit outputs a serial clock pulse to the SCL pin to transfer next 1 word of data and sets the SDA pin to 0 at the acknowledge signal timing An INTSBI interrupt request occurs and the PIN becomes 0 Then a serial bus interface circuit outputs a clock pulse for 1 word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR Read SBIDBR
261. e SET LD LD LD DI SET EI SET PINTTC4 CLR CLR CLR VINTTCA DW SYSCR2 7 TC3CR 63H TC4CR 05H TTREG3 OF800H EIRH 1 TC4CR 3 TC4CR 3 SYSCR2 5 SYSCR2 6 PINTTC4 SYSCR2 lt XEN gt lt 1 Sets TFF3 0 source clock fc and 16 bit mode Sets TFF4 0 and warm up counter mode Sets the warm up time The warm up time depends on the oscillator characteristic lt 0 Enables the INTTC4 lt 1 Starts the 4 and 3 Stops the 4 and 3 SYSCR2 lt SYSCK gt lt 0 Switches the system clock to the high frequency clock SYSCR2 lt XTEN gt lt 0 Stops the low frequency clock INTTC4 vector table Page 118 TOSHIBA Lipi 11 8 Bit TimerCounter 5 TC6 11 1 Configuration PWM mode L2 gt 11 3 interrupt request fc 2 5 2 A cop a P fc 2 C 1072 D fs fc 2 48 Bit made DH E B gt fc G gt E i 16 bit PDO6 PWM6 Timer Event TC6M mode Counter mode PPG6 pin TC6S Timer F F6 TFF6 1 TTREGS PWREGG PWM PPG mode Decodegw PDO PWM mode E TFF6 gt gt 2 1 or fs 2 gt Clear gt mes C PDO mode 2 D gt I EE gt d Toggle c 2 16
262. e Sec Chip 290 Erase tor Erase Security pro gram Setting Mode Note m x The command can be executed Pass The command can be executed with a password The command can not be executed After echoing the command back to the external controller the halt condition Page 259 T5CL8 stops UART communication and enters 20 Serial PROM Mode 20 13 Specifying the Erasure Area POM T5CL8 20 13Specifying the Erasure Area In the flash memory erasing mode the erasure area of the flash memory is specified by n 2 byte data The start address of an erasure area is specified by ERASTA and the end address is specified by ERAEND If ERASTA is equal to or smaller than ERAEND the sector erase erasure in 4 kbyte units is executed Executing the sector erase while the security program is enabled results in an infinite loop If ERASTA is larger than ERAEND the chip erase erasure of an entire flash memory area is executed and the security program is disabled Therefore execute the chip erase not sector erase to disable the security program Erasure Area Specification Data n 2 byte data 7 6 5 4 3 2 1 0 ERASTA ERAEND from 0000 from 1000 from 2000 from 3000 from 4000 from 5000 from 6000 The start address of the from 7000 erasure area from 8000 from 9000H from A000H from 000 from 000 from DOOOH from 000 from FOOOH
263. e Clock 1 Counter TTREG6 X n INTTC6 interrupt request Figure 11 2 8 Bit Timer Mode Timing Chart TC6 11 3 2 8 Bit Event Counter Mode TC5 6 In the 8 bit event counter mode the up counter counts up at the falling edge of the input pulse to the pin When a match between the up counter and the TTREGj value is detected an INTTC interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting at the falling edge of the input pulse to the pin Two machine cycles are required for the low or high level pulse input to the pin Therefore a maximum frequency to be supplied is fc 2 Hz in the NORMALI 2 IDLE1 2 mode and 5 24 Hz in the SLOW1 2 SLEEPI 2 mode Note 1 In the event counter mode fix TCjCR TFFj to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the event counter mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the event counter mode the new value programmed in TTREGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 2 5 6 6 lt 65 gt 1 1 TC6 pin input 1 1 Counter 0 TTREG6 X n Match detect clear Figure 11 3 8 Bit Event
264. e flash memory status code is the 7 byte data including the security program status and the status of the data from FFEOH to FFFFH Table 20 18 shows the flash memory status code Status Code 1 Table 20 18 Flash Memory Status Code Description Start mark In the Case of T5CL8 Transferred data count 3rd through 6th byte 04H Status code 00H to 03H See figure below Reserved data 00H Reserved data 00H Reserved data 00H Checksum of the transferred data 2 s compliment for the sum of 3rd through 6th data 3rd byte checksum 00H 00H 01H FFH 02H FEH 03H FDH 0 BLANK Initial Value 0000 00 Page 258 TOSHIBA RPENA Flash memory security 0 program status 1 Security program is disabled Security program is enabled T5CL8 data 15 in the area from FFEOH to FFFFH The value except FFH is included in the area from FFEOH to FFFFH The status from FFEOH 0 BLANK to FFFFH 1 Some operation commands are limited by the flash memory status code 1 If the security program 15 enabled flash memory writing mode command and RAM loader mode command can not be executed Erase all flash memory before executing these command Flash Memory Writing Mode RAM Loader Mode Flash memory SUM Output Mode Product ID Code Output Mode Flash Memory Status Output Mode Flash Memory Erasing Mod
265. e serially connected to the shift register the values set to PWREG4 and 3 can be changed while the timer is running The values set to PWREG4 and 3 during a run of the timer shifted by the INTTCj interrupt request and loaded into PWREG4 and 3 While the timer is stopped the values are shifted immediately after the programming of PWREG4 and 3 Set the lower byte PWREG3 and upper byte PWREG4 in this order to program PWREG4 and 3 Programming only the lower or upper byte of the register should not be attempted If executing the read instruction to PWREG4 and 3 during PWM output the values set in the shift register is read but not the values set in PWREG4 and 3 Therefore after writing to the PWREG4 and 3 reading data of PWREG4 and 3 is previous value until INTTC4 is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated normally in the INTTC4 interrupt service routine If the programming of PWREGj and the interrupt request occur at the same time an unstable value is shifted that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated Note 2 When the timer is stopped during PWM output the PWM4 pin holds the output status when the timer is stopped To change the output status program TC4CR lt TFF4 gt aft
266. ed OFF2H Reserved OFF3H Reserved OFF4H Reserved OFF5H Reserved OFF6H Reserved OFF7H Reserved OFF8H Reserved OFF9H Reserved OFFAH Reserved OFFBH Reserved OFFCH Reserved OFFDH Reserved OFFEH Reserved OFFFH FLSCR Note 1 Do not access reserved areas by the program Note 2 Cannot be accessed Note 3 Write only registers and interrupt latches cannot use the read modify write instructions Bit manipulation instructions such as SET CLR etc and logical operation instructions such as AND OR etc Page 48 05 Hn 5 Ports The 5 8 has 8 parallel input output ports 56 pins as follows Primary Function Secondary Functions Port PO 8 bit port extemal interrupt Serial PROM mode cotrol input serial interface input output UART input output Port P1 8 bit port External interrupt timer counter input output divider output Port P2 3 bit port Low trequency resonator connections external interrupt input STOP mode release signal input Port P5 5 bit port Serial bus interface input output Port P6 8 bit I O port Analog input and key on wakeup input Port P7 8 bit port Analog input Each output port contains a latch which holds the output data input ports do not have latches so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing Figure 5 1 shows input output timin
267. eive operation is stopped immediately after SIO2CR SIOINH is set to 1 In this case SIO2CR lt SIOS gt SIO2SR register SIO2RDB register and SIO2TDB register are initialized Clearing SIOS SIO2CR SIOS i 11 SIO2SR SIOF Start shift Start shift operation y operation SIO2SR lt SEF gt SCK2 pin Automatic wait N SI2 pin SIO2SR RXF INTSIO2 interrupt Writing transmit Writing transmit Writing transmit data A data B data C Figure 15 10 Example of Internal Clock and MSB Receive Mode Page 187 15 Synchronous Serial Interface 5102 15 3 Function T5CL8 Reading received data Clearing SIOS SIO2CR SIOS SIO2SR lt SIOF gt Start shift Start shift i Start shift operation Kk operation operation SIO2SR lt SEF gt d SCK2 pin SE 5 025 lt gt INTSIO2 interrupt request Writing transmit Writing transmit Writing transmit data A data B data C Figure 15 11 Example of External Clock and MSB Receive Mode 4 Receive error processing Receive errors occur on the following situation To protect SIO2RDB and the shift register con tents the received data is ignored while the SIO2SR lt RXERR gt is 1 Shift operation is finished before reading out received data from SIO2RDB at SIO2SR lt RXF gt is 1 in an external clock operation If receive error occurs set the SIO2CR l
268. ejection circuit Figure 12 4 Data Sampling Method Page 143 12 Asynchronous Serial interface UART1 12 6 STOP Bit Length T5CL8 12 6 STOP Bit Length Select a transmit stop bit length 1 bit or 2 bits by VARTICR1 lt STBT gt 12 7 Parity Set parity parity by UARTICRI lt PE gt and set parity type Odd or Even numbered by UARTICRI lt EVEN gt 12 8 Transmit Receive Operation 12 8 1 Data Transmit Operation Set UARTICR1 lt TXE gt to 1 Read UARTISR to check UARTISR lt TBEP gt 1 then write data in TDIBUF Transmit data buffer Writing data in TD1BUF zero clears 15 lt gt transfers the data to the transmit shift register and the data are sequentially output from the TXD1 pin The data output include one bit start bit stop bits whose number is specified in UART1CR1 lt STBT gt and a parity bit if parity addition is specified Select the data transfer baud rate using UARTICRI BRG When data transmit starts transmit buffer empty flag UART1SR lt TBEP gt is set to 1 and an INTTXDI interrupt is generated While UART1CR1 lt TXE gt 0 and from when 1 is written to VART1CR1 lt TXE gt to when send data are written to TDIBUF the TXD1 pin is fixed at high level When transmitting data first read UARTISR then write data in TDIBUF Otherwise UARTISR TBEP 15 not zero cleared and transmit does not start 12 8 2 Data Receive Operation Set UART1CR1 lt RXE gt to 1
269. elow the non inverting high level input voltage Hysteresis input Table 2 2 Warm up Time Example at fc 16 0 MHz fs 32 768 kHz Warm up Time ms Return to NORMAL Mode Return to SLOW Mode Note 1 750 250 The warm up time is obtained by dividing the basic clock by the divider Therefore the warm up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released Thus the warm up time must be considered as an approximate value Page 20 T5CL8 TOSHIBA esee eJ 4015 dn 1 1 uonnoexe uonongsu uononasu 1 Jejunoo 94e GHE yoojo ulejs s i L yO jndui 3015 e a M i dn e sseuppe 42645 LIS peg ejduiex3 uejs 4015 uonnoexo TY 2 40549 138 uononujsul Jejunoo e e Che 2 4 yo un Figure 2 9 STOP Mode Start Release Page 21 2 Operational Description 2 2 System Clock Controll ystem Clock Controller 15018 2 2 4 2 IDLE1 2 mode SLEEP1 2 mode IDLE1 2 SLEEP1 2 modes are controlled by the system control register 2 SYSCR2 and maskable interrupts
270. ely after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 3 4 Table 10 4 Source Clock for TimerCounter 3 4 Internal Clock Source Clock Maximum Time Setting NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode fc 211 Hz 15 23 Hz fs 23 Hz 27 27 fc 25 fc 25 fc 23 fc 23 Example Setting the timer mode with source clock fc 2 Hz and generating an interrupt 80 later TimerCounter4 fc 16 0 MHz LD TTREG4 OAH Sets the timer register 80 us 2 fc OAH DI SET EIRH 1 Enables INTTC4 interrupt El LD TC4CR 00010000B Sets the operating clock to fc 2 and 8 bit timer mode LD TC4CR 00011000B Starts TC4 Page 105 10 8 Bit TimerCounter TC3 4 10 1 Configuration igurati T5CL8 4 lt 45 gt Internal 1 Source Clock 1 Counter 4 X n INTTCA interrupt request Figure 10 2 8 Bit Timer Mode Timing Chart TC4 10 3 2 8 Bit Event Counter Mode TC3 4 In the 8 bit event counter mode the up counter counts up at the falling edge of the input pulse to the pin When a match between the up counter and the TTREG value is detected an INTTC interrupt is generated and the up counter is cleared After being cleared the up counter restarts counting at the falling edge of the input pul
271. emory registers the program status word and port output latches are all held in the status in effect before STOP mode was entered 3 The prescaler and the divider of the timing generator are cleared to 0 4 The program counter holds the address 2 ahead of the instruction e g SET SYSCR1 7 which started STOP mode STOP mode includes a level sensitive mode and an edge sensitive mode either of which can be selected with the SYSCRI lt RELM gt Do not use any wakeup input STOP3 to STOPO for releas ing STOP mode in edge sensitive mode Note 1 The STOP mode be released by either the STOP or wakeup pin STOPS to STOPO However because the STOP pin is different from the key on wakeup and can not inhibit the release input the STOP pin must be used for releasing STOP mode Note 2 During STOP period from start of STOP mode to end of warm up due to changes in the external interrupt pin signal interrupt latches may be set to 1 and interrupts may be accepted immediately after STOP mode is released Before starting STOP mode therefore disable interrupts Also before enabling interrupts after STOP mode is released clear unnecessary interrupt latches 1 Level sensitive release mode RELM 1 In this mode STOP mode is released by setting the STOP pin high or setting the STOP3 to STOPO pin input which is enabled by STOPCR This mode is used for capacitor backup when the main power supply
272. empt be made to fetch an instruction from the on chip RAM while WDTCR1 lt ATAS gt is 17 DBR or the SFR area address trap reset will be generated When an address trap reset request is generated the internal hardware is reset The reset time is maximum 24 fe s 1 5 us fc 16 0 MHz Note When an address trap reset is generated in the SLOW1 mode the reset time is maximum 24 fc high fre quency clock since the high frequency clock oscillator is restarted However when crystals have inaccura cies upon start of the high frequency clock oscillator the reset time should be considered as an approximate value because it has slight errors Page 71 6 Watchdog Timer WDT 6 3 Address Tra p T5CL8 Page 72 05 bd 7 Time Base Timer TBT The time base timer generates time base for key scanning dynamic displaying etc It also provides a time base timer interrupt INTTBT T 1 Time Base Timer 7 1 1 Configuration MPX fc 223 fs 215 221 165 213 216 fs 28 214 or 15 26 fc 213 15 25 212 15 24 fc 2 or 15 23 16 29 15 2 IDLEO SLEEPO release request INTTBT interrupt request Source clock Falling edge detector Time base timer control register Figure 7 1 Time Base Timer configuration 7 1 2 Control Time Base Timer is controlled by Time Base Timer control register TBTCR Time Base Timer Control Register 7 6 5 4 3 2 1 0
273. enerating the INTTC6 interrupt request After stopping the timer in the INTTC6 interrupt service routine clear SYSCR2 lt SYSCK gt to 0 to switch the system clock from the low frequency to high frequency and then SYSCR2 XTEN to 0 to stop the low frequency clock Table 11 9 Setting Time in High Frequency Warm Up Counter Mode Minimum time Setting Maximum time Setting TTREG6 5 0100H TTREG6 5 FF00H Example After checking high frequency clock oscillation stability with TC6 and 5 switching to the NORMALI mode SET LD LD LD DI SET EI SET PINTTC6 CLR CLR CLR RETI VINTTC6 DW SYSCR2 7 TC5CR 63H TC6CR 05H TTREGS EIRE 2 TC6CR 3 TC6CR 3 SYSCR2 5 SYSCR2 6 PINTTC6 SYSCR2 lt XEN gt lt 1 Sets TFF5 0 source clock fc and 16 bit mode Sets TFF6 0 and warm up counter mode Sets the warm up time The warm up time depends on the oscillator characteristic lt 0 Enables the INTTC6 lt 1 Starts the TC6 and 5 Stops the TC6 and 5 SYSCR2 lt SYSCK gt lt 0 Switches the system clock to the high frequency clock SYSCR2 lt XTEN gt lt 0 Stops the low frequency clock INTTC6 vector table Page 138 TOSHIBA T5CL8 12 Asynchronous Serial interface UART1 12 1 Configuration INTTXD1 INTRXD1 fc 13 fc 26 fc 52 fc 104 fc 208 fc 416 INTTC3 fc 96 UA
274. ent song 4 repeat none play all songs and it will stop after all songs played play all songs and it will restart to play the first song after all songs 5 repeat all played random play all songs stop after all songs are played repeat TRACK UP command is invalid when random playing last song up down operation 6 nonerrandom DOWN command is playing from current song beginning forbidden random play all songs not stop same as mode 6 TRACK UP command is valid all along dir up down operation 7 repeat all random TRACK DOWN command is playing from current song beginning is forbidden play the first 10 seconds of every song in the device After all songs 8 repeat nonetintro played it stop play the first 10 seconds of every song in the device After all songs 9 repeat played it play from the first song again 10 repeat dir repeat play current folder inside songs 11 repeat dir randomrandom play current folder inside songs play the first 10 seconds of every song in the folder After all songs 12 repeat dir intro played it play from the first song of the folder again 41 TOSHIBA T5CJ3 7G28 F M Specification play mode s ift table REP REP 1 DIR REP RANDOM RANDOM INTRO INTRO ID Current setting set set set set SET OFF SET OFF 1 repeat1 4 10 5 3 2 repeat1 random 6 11 7 1 3 3 repeat
275. er flag IMF When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt 15 already accepted the new watchdog timer interrupt is processed immediately and the previous interrupt 1s held pending Therefore 1f watchdog timer interrupts are generated continuously without execution of the RETN instruction too many levels of nesting may cause a malfunction of the microcontroller To generate a watchdog timer interrupt set the stack pointer before setting WDTCRI lt WDTOUT gt Example Setting watchdog timer interrupt LD SP 083FH Sets the stack pointer LD WDTCR1 00001000B WDTOUT lt 0 Page 68 05 6 2 5 Watchdog Timer Reset When a binary counter overflow occurs while WDTCRI lt WDTOUT gt is set to 1 a watchdog timer reset request 15 generated When a watchdog timer reset request is generated the internal hardware is reset The reset time is maximum 24 fc s 1 5 us fc 16 0 MHz Note When a watchdog timer reset is generated the SLOW1 mode the reset time is maximum 24 fc high fre quency clock since the high frequency clock oscillator is restarted However when crystals have inaccura cies upon start of the high frequency clock oscillator the reset time should be considered as an approximate value because it has slight errors 219 fc s 17 211 Binary counter D GNOME GLO GELT Overflow INTWDT inte
276. er reading auto play CD TEXT 0x81 etC TE Ttitle album and title information Byte of data field get title or album information get artist information Black epper OST DEVICE TYPE 0x82 If de ice is play a ailable B return this command etailed infomation please refer to command chapter ERROR CODE 0x 83 If error occur in reading process or de ice is play una ailable B return this command to report a error About reading error byte of data field is in C mode in S mode b cin SB mode etailed infomation please refer to command chapter CD TOC INFO 0x90 eturns first track number final track number and disc total time if it is C Adisc TTL FILE DIR NUMBER 0x94 eturns total file number total folder number found in the de ice SB S C O C A etc Adisc the total folder number is CD TEXT_RESULT 0xbc C TE T found or not and TE T character set code eturn this command only when disc typeisC Aor 1 CD TEXT_INFO 0xbd Itreturn TE T title album and artist contents Byte of data field it is title or album information it is artist information PLAY STATUS 0x84 STOP STATUS Byte of data field STOP STATUS 0x8401 PLAY STATUS Byte of data field PLAY STATUS 0x8400 If set auto play with E ICE EA command PLAY STATUS command returns otherwise STOP STATUS returns 56 TOSHIBA T5CJ3 7G28 F M Specification Command se ue
277. er the timer is stopped Do not program TC4CR lt TFF4 gt upon stopping of the timer Example Fixing the PWM4 pin to the high level when the TimerCounter is stopped Page 112 05 Lus CLR TCACR 3 Stops the timer CLR TCACR 7 Sets the PWMA pin to the high level Note 3 To enter the STOP mode stop the timer and then enter the STOP mode If the STOP mode is entered with out stopping of the timer when fc fc 2 fs is selected as the source clock a pulse is output from the PWM4 pin during the warm up period time after exiting the STOP mode Table 10 7 16 Bit PWM Output Mode NORMAL 1 2 IDLE1 2 mode SLOW1 2 16 MHz fs 32 768 kHz SLEEP1 2 fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 mode 15 23 Hz fs 2 Hz 8 39 5 27 524 3 25 131 1 fc 23 32 8 ms fs 2s 8 2ms 4 1 ms Example Generating a pulse with 1 ms high level width and a period of 32 768 ms fc 16 0 MHz Setting ports LDW PWREGS3 07D0H Sets the pulse width LD TC3CR 33H Sets the operating clock to 23 and 16 bit PWM output mode lower byte LD TCACR 056H Sets 4 to the initial value 0 and 16 bit PWM signal generation mode upper byte LD TCACR 05EH Starts the timer Page 113 10 8 Bit TimerCounter TC3 4 10 1 Configuration T5CL8 1senbei t2 LLNI E 73 9 19W L IG yore yore B yore
278. es 4 kbytes FFH Security program disabled Security program status Other than FFH Security program enabled Note The value at address F002H flash size depends on the size of flash memory incorporated in each product For example if the product has 60 kbyte flash memory OEH is read from address F002H 19 2 5 Product ID Exit This command is used to exit the Product ID mode 19 2 6 Security Program This command enables the read protection or write protection setting in the flash memory When the security program is enabled the flash memory cannot be read in the parallel PROM mode In the serial PROM mode the flash write and RAM loader commands cannot be executed To enable the security program setting in the serial PROM mode set FLSCR lt BANKSEL gt to 1 before executing the security program command sequence To disable the security program setting it is necessary to execute the chip erase command sequence Whether or not the security program is enabled can be checked by reading FF7FH in the Product ID mode For details see Table 19 4 Page 226 05 Ls It takes a maximum of 40 us to set security program in the flash memory The next command sequence can not be executed until this operation is completed To check the completion of the security program operation perform read operations repeatedly for data polling until the same data 15 read twice from the same address in the flash memory During the securit
279. eset SET FTRMWARE 83 Set f rmware feature FIRMWARE FEATURE f7 SELECT MODE 30 Select a work mode MODE SEL OK 80 READ DEVICE 12 device information Read process STOP STATUS 8401 Return stop status at the end of read process POSITION PLAY 20 Start reco ery play 6 30 Transfering cofficient data lack epper support rece ng coeffcent from host sde ost sde can transfer all coeff cent nstead of us ng S command Rele ant commands are sted bellow lack epper SEND INIT CMD 0x41 se th s command to send nt al command mum commands n one command package SEND EQ DATA 0x42 se th s command to send data a mum commands n one command package SEND DATA 0X43 se ths command to send data mum commands n one command package SEND OK 0x44 It nforms all command send ng fn sh 68 TOSHIBA T5CJ3 7G28 F M Specification lack epper S RESET POWER 0xb5 of data fled case of It means fn shed hs reset process hardware reset PICK UP REQUEST 0xb6 hs sthe f rst command after hardware reset th s command to synchrona e your System hs command w not be sent aga n after standby out ery command of nt al command data or data s bytes hey ha e bellow format Initial command format Byte n Byte 1 Byte 2 In t al command address In t al command data hgh byte In tal command data low byte or e ample
280. etting by I2CAR with an address recognition mode ALS 0 When a serial bus interface circuit operates in the free data format ALS 1 the AAS is set to 1 after receiving the first 1 word of data The AAS is cleared to 0 by writing data to the SBIDBR or reading data from the SBIDBR 16 5 12GENERAL CALL detection monitor The ADO Bitl in SBISRB is set to 1 when all 8 bit received data is 0 immediately after a start condi tion in slave mode The ADO is cleared to 0 when a start stop condition is detected on a bus 16 5 13Last received bit monitor The SDA line value stored at the rising edge of the SCL line is set to the LRB in SBISRB In the acknowledge mode immediately after an INTSBI interrupt request is generated an acknowledge signal is read by reading the contents of the LRB Page 204 05 Hn 16 6 Data Transfer of I2C Bus 16 6 1 Device initialization For initialization of device set the in SBICRA to 1 and the BC to 000 Specify the data length to 8 bits to count clocks for an acknowledge signal Set a transfer frequency to the SCK in SBICRA Next set the slave address to the SA in I2CAR and clear the ALS to 0 to set an addressing format After confirming that the serial bus interface pin is high level for specifying the default setting to a slave receiver mode clear 0 to the MST and BB in SBICRB set 1 to the PIN
281. evice receives the data record that consists of data length address record type write data and checksum Since the device starts checksum calculation after receiving an end record the external controller should wait for the checksum after sending the end record If a receiving error or Intel Hex format error occurs the device enters the halts condition without returning an error code to the external con troller The n th 1 and n th bytes contain the checksum upper and lower bytes For details on how to calcu late the SUM refer to 20 8 Checksum SUM The checksum is calculated only when the end record is detected and no receiving error or Intel Hex format error occurs After sending the end Page 244 05 as record the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device 14 After transmitting the checksum the device waits for the next operation command data Note 1 Do not write only the address from FFEOH to FFFFH when all flash memory data is the same If only these area are written the subsequent operation can not be executed due to password error Note 2 To rewrite data to Flash memory addresses at which data including FFH is already written make sure to erase the existing data by sector erase or chip erase before rewriting data Page 245 20 Serial PROM Mode 20 6 Operation Mode perati T5CL8 20 6 3 RAM Loader Mode Operation C
282. evice does not send any data If a receiv ing error or password error occurs the device does not send any data and enters the halt condition The 13th byte contains the data for 7 to 0 bits of the password comparison start address When the data received with the 13th byte has no receiving error the device does not send any data If a receiv ing error or password error occurs the device does not send any data and enters the halt condition The 15th through m th bytes contain the password data The number of passwords becomes the data N stored in the password count storage address The external password data is compared with N byte data from the address specified by the password comparison start address The external control ler should send N byte password data to the device If the passwords do not match the device enters the halt condition without returning an error code to the external controller If the addresses from FFEOH to FFFFH are filled with FFH the passwords are not conpared because the device is consid ered as a blank product The m th 1 through n th 2 bytes of the received data contain the binary data in the Intel Hex for mat No received data 15 echoed back to the external controller After receiving the start mark for in the Intel Hex format the device starts data record reception Therefore the received data except 3AH is ignored until the start mark is received After receiving the start mark the d
283. executed in 8 bits Other than these the BC retains a specified value 16 5 3 Serial clock 16 5 3 1 Clock source The SCK Bits2 to 0 in SBICRA is used to select a maximum transfer frequency output from the SCL pin in the master mode Four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from SCL pin Note Since the serial bus interface can not be used as the fast mode and the high speed mode do not set SCK as the frequency that is over 100 kHz tLow 1 fscl gt SCK Bits2 to 0 in the SBICRA n 2 tHIGH 2 fc 8 fc 1 LOW tHIGH 4 5 6 7 8 9 LPLI LI Lt ME Rh tsckL tsckH tSCKL tSCKH gt 4 Note 1 fc High frequency clock Note 2 tcyc 4 fc in NORMAL mode IDLE mode Figure 16 3 Clock Source 16 5 3 2 Clock synchronization In the bus in order to drive a bus with a wired AND a master device which pulls down a clock pulse to low will in the first place invalidate a clock pulse of another master device which generates a high level clock pulse Page 200 05 Hn The serial bus interface circuit has a clock synchronization function This function ensures normal transfer even if there are two or more masters on the same bus The example explains clock synchronization procedures when two masters simultaneously exist on a bus SCL pin Master 1
284. f eb ommand ff f f fa fb fc fd ffeeff a ommand ff f f f fef f f f f ommand ff f f fa fb f fd fe ff ommand ff ommand se uence 70 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 request host set p ck up PICK UP REQUEST b6 Send ntal commands by SEND INIT CMD 41 packages Initial command SEND EQ DATA 42 Send Q data by packages SEND EQ DATA 42 EQ data SEND RF DATA 43 SEND RF DATA 43 Send RF data by packages RF data SEND OK 44 coeff c ents sends RESET POWER b500 fter rece ed all coeffcent sendaR S T command 6 31 About E2PROM function lack epper can connect to a btor bt R t has some funct on of stor ng custom ed coffcents of pck up new R for decoder and patch data to repar R code R outl ne map s bellow R data area outl ne rea header nformaton _ bytesf ed rea ntal commands of coeff c ent rea Q data of coeff cent rea RF data of coeff c ent rea atch data for R code rea gt decoder rea R nformat on Area 1 map header information Address 0 rea start address hgh bts Address 1 rea address low bts Address 2 rea start address hgh bts Address 3 rea address low bts Address 4 rea start address hgh bts Address 5 rea address low bts 71 TOSHIBA T5CJ3 7G28 F M Specification Address 6 F edto Address
285. figuration T5CL8 peddois 1 BY USYM 1 1 3 4195 4 1 1 YEN NNNM SNNT ANSA ZX OMX AA CANA dA SAC 1 1 aba JO SWIM i 1senbej 211 3 3 eounos y3dl2HOvO l lt 791 gt 39794 Figure 10 4 8 Bit PDO Mode Timing Chart 4 Page 108 05 Lus 10 3 4 8 Pulse Width Modulation PWM Output Mode 4 This mode is used to generate a pulse width modulated PWM signals with up to 8 bits of resolution The up counter counts up using the internal clock When a match between the up counter and the PWREGj value is detected the logic level output from the timer 1s switched to the opposite state The counter continues counting The logic level output from the timer F Fj is switched to the opposite state again by the up counter overflow and the counter is cleared The INTTC interrupt request is generated at this time Since the initial value can be set to the timer by lt gt positive and negative pulses can be gen erated Upon reset the timer F Fj is cleared to 0 The logic level output from the PWMj pin is the opposite to the timer F F
286. flags To avoid overloaded nesting clear the individual interrupt enable flag whose interrupt is currently serviced before setting IMF to 1 As for non maskable interrupt keep interrupt service shorten compared with length between interrupt requests otherwise the status cannot be recovered as non maskable interrupt would simply nested Saving restoring general purpose registers During interrupt acceptance processing the program counter PC and the program status word PSW includes IMF are automatically saved on the stack but the accumulator and others are not These registers are saved by software if necessary When multiple interrupt services are nested it is also necessary to avoid using the same data memory area for saving registers The following methods are used to save restore the general purpose registers Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested general purpose registers can be saved restored using the PUSH POP instructions Example Save store register using PUSH and POP instructions PINTxx PUSH WA Save WA register interrupt processing POP WA Restore WA register RETI RETURN Me tede ens Address S E ZZ m Example kebide tad mm d os D DAMEN ME NAE S PCL PCL b 2 d duet Bon u x ee Bc
287. ft Start shift Start shift operation y operation operation SIO2SR lt SEF gt 2 SO2 pin p 59996982 y Co Fo SIO2SR lt TXF gt SIO2TDB An c Writing transmit Writing transmit Writing data data B data C SIO2SR lt RXF gt Reading received Reading received Reading received data D dataE data F Figure 15 13 Example of Internal Clock and MSB Transmit Receive Mode Page 191 15 Synchronous Serial Interface 5102 15 3 Function SIO2CR lt SIOS gt 5 025 lt 5 gt 5 025 lt 5 gt SCK2 pin output SO2 pin SI2 pin INTSIO2 interrupt request SIO2SR TXF SIO2TDB SIO2SR lt RXF gt SIO2RDB T5CL8 Reading received data Writing transmit data i Clearing SIOS Start shift operation Start shift operation operation Start shift Fo Writing transmit data B Writing transmit data A Writing transmit data C XE Reading received data E Reading received data D Reading received data F Figure 15 14 Example of External Clock and MSB Transmit Receive Mode 4 Transmit receive error processing Transmit receive errors occur on the following situation Corrective action is different which errors occur transmits or receives a Transmit errors Transmit errors occur on the following situation Shift operation starts before
288. ft operation Synchronizing with the next serial clock falling edge INTSIO1 interrupt request is generated If shift operation starts before writing data to SIOITDB after SIOICR SIOS is set to 1 5 5 lt gt is set to 1 immediately after shift operation is started and then INTSIO1 interrupt request is generated pin is kept in high level when 51015 lt gt is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing 5101 CR lt SIOINH gt to 1 In this case 5101 lt 6105 gt SIOISR register SIOIRDB register and SIOITDB register are initialized Page 167 14 Synchronous Serial Interface 5101 14 3 Function SIO1CR SIOS 5 015 lt 5 gt 5 015 lt 5 gt SCK1 pin 501 pin SIO1SR TXF SIO1SR TXERR INTSIO1 interrupt request SIO1TDB SIO1CR lt SIOINH gt MC T5CL8 Start shift Start shift Start shift X operation operation operation MM nanni nnii 2 Writing transmit Writing transmit data A data B Figure 14 9 Example of Transmit Error Processingme 14 3 3 2 Receive mode The receive mode is selected by writing 01B to SIO1CR lt SIOM gt 1 2 Starting the receive operation Receive mode is selected by setting 01 to 5 lt 5 gt Serial clock is selected by using 5 lt 5 gt Transfer direc
289. g examples Port P4 8 bit port Serial interface input output and UART input output External data is read from an port in the S1 state of the read cycle during execution of the read instruction This timing cannot be recognized from outside so that transient input such as chattering must be processed by the pro gram Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I O port Fetch cycle Fetch cycle Read cycle 50 51 52 53 50 51 52 53 50 51 52 S3 Instruction execution cycle Example LD A x Input strobe Data X XR a Input timing Fetch cycle Fetch cycle Write cycle 50 51 52 53 50 51 52 53 50 51 S2 S3 Instruction execution cycle Example LD x A Output strobe Data output Old New b Output timing Note The positions of the read and write cycles may vary depending on the instruction Figure 5 1 Input Output Timing Example Page 49 5 Ports 5 1 Port PO 07 to 00 5 1 T5CL8 Port P07 to P00 Port PO is an 8 bit input output port Port PO is also used as an external interrupt input Serial PROM mode control input a serial interface input output and an UART input output When used as an input port an external interrupt input a serial interface input output and an UART input output the corresponding output latch PODR should be set to 1 During
290. g received data Writing transmit data i Clearing SIOS Start shift operation Start shift operation operation Start shift Fo Writing transmit data B Writing transmit data A Writing transmit data C XE Reading received data F Reading received data D Reading received data E Figure 14 14 Example of External Clock and MSB Transmit Receive Mode 4 Transmit receive error processing Transmit receive errors occur on the following situation Corrective action is different which errors occur transmits or receives a Transmit errors Transmit errors occur on the following situation Shift operation starts before writing next transmit data to SIOITDB in external clock op eration If transmit errors occur during transmit operation 51015 lt gt is set to 1 im mediately after starting shift operation And INTSIO1 interrupt request is generated af ter all of the 8 bit data has been received If shift operation starts before writing data to SIOITDB after SIOICR SIOS is set to 1 SIOISR lt TXERR gt is set immediately after starting shift operation And INTSIOI interrupt request is generated after all of the 8 bit data has been received SOI pin is kept in high level when SIO1SR lt TXERR gt is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIOICR SIOINH to 1 af
291. ge 163 14 Synchronous Serial Interface 5101 14 3 Functi unction T5CL8 14 3 2 Transfer bit direction Transfer data direction be selected by using SIO1ICR lt SIODIR gt The transfer data direction can t be set individually for transmit and receive operations When the data direction is changed the writing instruction to SIO1CR lt SIODIR gt should be executed while the transfer is stopped when SIOICR lt SIOF gt 0 SIOCR lt SIOS gt SCK1 Shift out a MSB transfer SIO1CR SIOS SCK1 Shift out b LSB transfer Figure 14 5 Transfer Bit Direction Example of transmit mode 14 3 2 1 Transmit mode 1 MSB transmit mode MSB transmit mode is selected by setting SIO1CR lt SIODIR gt to 0 in which case the data is transferred sequentially beginning with the most significant bit Bit7 2 LSB transmit mode LSB transmit mode is selected by setting SIO1CR lt SIODIR gt to 1 in which case the data is transferred sequentially beginning with the least significant bit 14 3 2 2 Receive mode 1 MSB receive mode MSB receive mode is selected by setting SIOICR SIODIR to 0 in which case the data 15 received sequentially beginning with the most significant bit Bit7 Page 164 05 2 LSB receive mode LSB receive mode is selected by setting SIO1CR lt SIODIR gt to 1 in which case the data is received sequentially beginning wi
292. h and disable 2 function Need connection with a 4Mbit flash 0 disable external flash and enable E2PROM function MODE3 1 disable the SD function 0 enable the SD function MODE4 1 B14 TC94B14MFG 202 connection 0 B13 TC94B13FG 002 connection TOSHIBA T5CJ3 7G28 F M Specification 5 Communication and command 5 1 Communication protocol BlackPepper3 communicates with HOST MCU by the UART interface pin 87 88 Bellow is UART feature Baudrate 19200 kbps Data width 8 bit Stop bit Yes Parity bit None BlackPepper3 receving and transmitting command by a packet Bellow is packet fomat Byte number Value Comment 0x00 OxFF Sync byte 0x01 XX Command length 0x02 XX Command ID 0x03 XX Command data XX Command data Last byte NN Checksum Command length length from byte of command ID to last byte of command data Checksum Sum of value from byte of command length to last byte of command data If there is no command data command length 1 and Checksum command ID command length TOSHIBA T5CJ3 7G28 F M Specification 5 2 Command list PARTI Command list send from host MCU to BlackPepper3 command name synclength data checksum description note MSF PLAY 4 0 00 OxNN start msf play select folder with folder analyze to get folder inside information SEL FOLDERI Oxff 4 0x05 OxNN Jand f
293. h memory writing mode 1 10 1 12 13 The 1st byte of the received data contains the matching data When the serial PROM mode is acti vated 5 8 hereafter called device waits to receive the matching data SAH Upon reception of the matching data the device automatically adjusts the UART s initial baud rate to 9600 bps When receiving the matching data 5 the device transmits an echo back data 5AH as the second byte data to the external controller If the device can not recognize the matching data it does not transmit the echo back data and waits for the matching data again with automatic baud rate adjust ment Therefore the external controller should transmit the matching data repeatedly till the device transmits an echo back data The transmission repetition count varies depending on the frequency of device For details refer to Table 20 5 The 3rd byte of the received data contains the baud rate modification data The five types of baud rate modification data shown in Table 20 4 are available Even if baud rate is not modified the external controller should transmit the initial baud rate data 28H 9600 bps Only when the 3rd byte of the received data contains the baud rate modification data corresponding to the device s operating frequency the device echoes back data the value which 1s the same data in the 4th byte position of the received data After the echo back data 15 transmitted baud rate mo
294. h the frequency is supported in the serial PROM mode the serial PROM mode may not be activated correctly due to the frequency difference in the external controller such as personal computer and oscillator and load capacitance of communication pins Note 2 It is recommended that the total frequency difference is within 3 so that auto detection is performed correctly by the ref erence frequency Note 3 The external controller must transmit the matching data repeatedly till the auto detection of baud rate is performed This number indicates the number of times the matching data is transmitted for each frequency Page 238 05 Lus 20 5 Operation Command The eight commands shown in Table 20 6 are used in the serial PROM mode After reset release the 5 8 waits for the matching data SAH Table 20 6 Operation Command in the Serial PROM Mode Command Data Operating Mode Description Setup Matching data Execute this command after releasing the reset Flash memory erasing Erases the flash memory area address 1000H to FFFFH Flash memory writing Writes to the flash memory area address 1000H to FFFFH RAM loader Writes to the specified RAM area address 0050H to 083FH Outputs the 2 byte checksum upper byte and lower byte in this order for the output entire area of the flash memory address 1000H to FFFFH Product ID code output Outputs the product ID code 13 byte data Outpu
295. he chapter of Flash Memory Control Register To use the Flash memory writing command 30H specify the flash memory addresses from 1000H to FFFFH that is the same addresses in the MCU mode because the BOOTROM changes the flash memory address 0000H 0000H 003FH 64 bytes 003FH ado 0040H 0040H RAM 2048 bytes RAM 2048 bytes 083FH OF80H DBR 128 bytes DBR 128 bytes OFEFH OFFFH 1000H 7800H BOOTROM 2048 bytes 8000H 47 61440 bytes 8000H 9000H Flash memory Flash memory BANKO BANK1 FFFFH Serial PROM mode MCU mode Figure 20 1 Memory Address Maps Page 233 20 Serial PROM Mode 20 3 Serial PROM Mode Setting T5CL8 20 3 Serial PROM Mode Setting 20 3 1 Serial PROM Mode Control Pins To execute on board programming activate the serial PROM mode Table 20 2 shows pin setting to activate the serial PROM mode Table 20 2 Serial PROM Mode Setting Setting TEST pin BOOT RXD1 pin RESET pin Note The BOOT pin is shared with the UART communication pin RXD1 pin the serial PROM mode This pin is used UART communication pin after activating serial PROM mode 20 3 2 Pin Function In the serial PROM mode TXD1 P02 and RXDI P01 are used as a serial interface pin Table 20 3 Pin Function in the Serial PROM Mode Pin Name Input Serial PROM Mode Output
296. he entire area or in units of 4 kbytes whereas read operations can be performed by an one transfer instruction However the command sequence method is adopted for write and erase operations requiring several byte transfer instruc tions for each operation Note 2 To rewrite data to Flash memory addresses at which data including FFH is already written make sure to erase the existing data by sector erase or chip erase before rewriting data 19 4 1 Flash Memory Control in the Serial PROM Mode The serial PROM mode is used to access to the flash memory by the control program provided the BOOTROM area Since almost of all operations relating to access to the flash memory can be controlled sim ply by the communication data of the serial interface UART these functions are transparent to the user For the details of the serial PROM mode see Serial PROM Mode To access to the flash memory by using peripheral functions in the serial PROM mode run the RAM loader command to execute the control program in the RAM area The procedures to execute the control program in the RAM area is shown in 19 4 1 1 How to write to the flash memory by executing the control program in the RAM area in the RAM loader mode within the serial PROM mode 19 4 1 1 How to write to the flash memory by executing the control program in the RAM area in the RAM loader mode within the serial PROM mode Steps program 2 ui and 2
297. hen restarting take at least 4 7 us of waiting time by software from the time of restarting to confirm that a bus is free until the time to generate a start condition Note When the master is in the receiver mode it is necessary to stop the data transmission from the slave devcie before the STOP condtion is generated To stop the transmission the master device make the slave device receiving a negative acknowledge Therefore the LRB is 1 before generating the Restart and it can not be confirmed that SCL line is not pulled down by other devices Please confirm the SCL line state by reading the port 1 gt MST 9 MST x 3 TRX 0 gt 4 gt PIN Q gt 1 gt PIN 4 7 Start condition SCL Bus SCL pin SDA pin LRB BB PIN Figure 16 14 Timing Diagram when Restarting Page 209 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 Page 210 05 E 17 10 bit AD Converter ADC The T5CLS8 have a 10 bit successive approximation type AD converter 17 1 Configuration The circuit configuration of the 10 bit AD converter is shown in Figure 17 1 It consists of control register ADCCRI and ADCCR2 converted value register ADCDR1 and ADCDR2 a DA converter a sample hold circuit a comparator and a successive comparison circuit DA converter VAREF YSS 1 AVDD Analog input ird mul
298. high byte byte 1 playing file number low byte byte 2 playing folder number high byte byte 3 playing folder number low byte byte 4 local total file number in folder high byte 5 local total file number in folder low byte byte 6 local start file number in folder high byte byte 7 local start file number in folder low byte IPLAY TIME 0xa2 byte 0 time minute high byte byte 1 playing time minute low byte byte 2 playing time second character coding type PLAY FILE NAME 0xaa byte 0 0x00 ISO 8859 1 0x01 Unicode USB SD mode is UTF 16 CD mode is UTF 16BE byte 1 file name first byte byte 2 file name byten file name last byte 22 TOSHIBA T5CJ3 7G28 F M Specification character coding type PLAY DIR NAME 0xab 0 0x00 ISO 8859 1 0x01 Unicode USB SD mode is UTF 16 CD mode is UTF 16BE byte 1 folder name first byte byte 2 folder name byten folder name last byte 0x00 title info PLAY ID3 INFO 0xac byte 0 0 01 artist info 0x02 album info mp3 file 0x00 ISO 8859 1 0x01 UTF 16 1 0x02 UTF 16BE 0x03 UTF 8 wma file 0x00 UTF 16 byte 2 info data first byte 3 info data byte n info data last byte 0x00 resume check ok RESUME STATUS 0xb4 byte 0 0x01 resume check ng 0x00 system reset is ok power on reset RESET 0xb5 byte 0 0x0
299. hortest transmitting time according to the bus standard after setting of the slave address to be output Only when the bus free is confirmed set 1 to the MST TRX BB and PIN to generate the start conditions If the writing of slave address and setting of MST TRX BB and PIN doesn t finish within 98 0 us the other masters may start the transferring and the slave address data written in SBIDBR may be broken al Acknowledge pus condition Slave address Direction bit signal from a slave device PIN INTSBI t interrupt request Figure 16 9 Start Condition Generation and Slave Address Transfer SDA pin 16 6 3 1 word data transfer Check the MST by the INTSBI interrupt process after an 1 word data transfer is completed and determine whether the mode is a master or slave Page 205 16 Serial Bus Interface I2C Bus Ver D 581 16 6 Data Transfer of I2C Bus T5CL8 16 6 3 1 When the MST is 1 Master mode Check the TRX and determine whether the mode is a transmitter or receiver 1 When the TRX is 1 Transmitter mode SCL pin Write to SBIDBR SDA pin PIN INTSBI interrupt request Test the LRB When the LRB is 1 a receiver does not request data Implement the process to generate a stop condition Described later and terminate data transfer When the LRB is 0 the receiver requests next data When the next transmitted data is other than 8 bits set the BC set th
300. ich case the data is transferred sequentially beginning with the most significant bit Bit7 2 LSB transmit mode LSB transmit mode is selected by setting SIO2CR lt SIODIR gt to 1 in which case data is transferred sequentially beginning with the least significant bit 15 3 2 2 Receive mode 1 MSB receive mode MSB receive mode is selected by setting SIO2CR lt SIODIR gt to 0 in which case the data is received sequentially beginning with the most significant bit Bit7 Page 182 05 2 LSB receive mode LSB receive mode is selected by setting SIO2CR lt SIODIR gt to 1 in which case the data is received sequentially beginning with the least significant bit 15 3 2 3 Transmit receive mode 1 MSB transmit receive mode MSB transmit receive mode are selected by setting SIO2CR lt SIODIR gt to 0 in which case data is transferred sequentially beginning with the most significant bit Bit7 and the data is received sequentially beginning with the most significant 2 LSB transmit receive mode LSB transmit receive mode are selected by setting SIO2CR lt SIODIR gt to 1 in which case data is transferred sequentially beginning with the least significant bit 10 and the data is received sequentially beginning with the least significant 15 3 3 Transfer modes Transmit receive and transmit receive mode are selected by using SIO2CR lt S
301. imer start control and timer F F control by programming TC4CR lt TC4S gt TC4CR lt TFF4 gt respectively Note 6 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 1 and Table 10 2 Page 100 05 Lus Note 7 The timer register settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 3 Note 8 The operating clock fc in the SLOW or SLEEP mode can be used only as the high frequency warm up mode Page 101 10 8 Bit TimerCounter TC3 4 10 1 Configuration 15018 The TimerCounter 4 is controlled by the TimerCounter 4 control register TCACR and two 8 bit timer registers TTREG4 and PWREGA TimerCounter 4 Timer Register TTREG4 7 6 5 4 3 2 1 0 0015H R W Initial value 1111 1111 PWREGA 7 6 5 4 3 2 1 0 0019H R W Initial value 1111 1111 Note 1 Do not change the timer register TTREG4 setting while the timer is running Note 2 Do not change the timer register PWREG4 setting in the operating mode except the 8 bit and 16 bit PWM modes while the timer is running TimerCounter 4 Control Register 7 6 5 4 3 2 1 0 0028H Tc4s Initial value 0000 0000 TFF4 Timer F F4 control 1 Set NORMAL41 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 TC4CK Operating clock selection Hz R W fc fc TC4 pin inpu
302. imum instruction execution unit is called an machine cycle There are a total of 10 different types of instructions for the TLCS 870 C Series Ranging from 1 cycle instructions which require one machine cycle for execution to 10 cycle instructions which require 10 machine cycles for execution A machine cycle consists of 4 states 50 to S3 and each state consists of one main system clock 1 fe or 1 45 s Main system clock Machine cycle 39 Figure 2 5 Machine Cycle 2 2 3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high frequency and low frequency clocks and switches the main system clock There are three operating modes Single clock mode dual clock mode and STOP mode These modes are controlled by the system control registers SYSCR1 and SYSCR2 Figure 2 6 shows the operating mode transition diagram 2 2 3 1 Single clock mode Only the oscillation circuit for the high frequency clock is used and P21 XTIN and P22 XTOUT pins are used as input output ports The main system clock is obtained from the high frequency clock In the single clock mode the machine cycle time is 4 fc s 1 NORMAL1 mode In this mode both the CPU core and on chip peripherals operate using the high frequency clock The 5 8 is placed in this mode after reset Page 13 2
303. input data the PAPRD register should be read Table 5 3 Register Programming for Multi function Ports P47 to P40 Programmed Value Function P4DR P4OUTCR Port input UART input or serial interface input o v Port 0 output Programming Port 1 output UART output or serial interface ijr for output tions STOP OUTEN input Data input PAPRD Output latch read PADR Data output PADR Output latch Control output Control input Note i 7 toO Figure 5 6 Port 4 Page 56 TOSHIBA iu P4DR 7 6 5 4 3 2 1 0 0004 47 46 45 44 P43 P42 41 40 Initial value 1111 1111 R W SCK2 SO2 SI2 TXD2 RXD2 f I1 LL T semet 000AH 0 Sink open drain output PAOUTCR Port P4 output circuit control Set for each bit individually i 2 000 Read only Page 57 5 Ports 5 6 Port P5 P54 to P50 Large Current Port T5CL8 5 6 Port P5 P54 to P50 Large Current Port Port P5 is an 5 bit input output port Port P5 is also used as Bus input output When used as an input port and Bus input output the corresponding output latch PSDR should be set to 1 During reset is initialized to 1 PS port output latch PSDR and P5 port terminal input PSPRD are located on their respective address When read the output latch data the PSDR should be read
304. input state Therefore when the input and output modes are used together the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction Note 2 When used as an analog inport be sure to clear the corresponding bit of P7CR2 to disable the port input Note 3 Do not set the output mode P7CR1 1 for the pin used as an analog input pin Note 4 Pins not used for analog input can be used as ports During AD conversion output instructions should not be executed to keep a precision In addition a variable signal should not be input to a port adjacent to the analog input during AD con version Page 63 5 Ports 5 8 Port P7 P77 to P70 Page 64 05 Hn 6 Watchdog Timer WDT The watchdog timer is a fail safe system to detect rapidly the CPU malfunctions such as endless loops due to spu rious noises or the deadlock conditions and return the CPU to a system recovery routine The watchdog timer signal for detecting malfunctions can be programmed only once as reset request or inter request Upon the reset release this signal is initialized to request When the watchdog timer is not used to detect malfunctions it can be used as the timer to provide a periodic inter rupt Note Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise 6 1 Watchd
305. interrupt request is generated TC1CR lt TC1S gt is cleared to 00 automatically at this time and the timer stops The pulse generated by PPG retains the same level as that when the timer stops Since the output level of the PPG pin can be set with TC1CR lt TFF1 gt when the timer starts a positive or neg ative pulse can be generated Since the inverted level of the timer F F1 output level is output to the PPG pin specify TCICR TFF gt to 0 to set the high level to the PPG pin and 1 to set the low level to the PPG pin Upon reset the timer F F1 is initialized to 0 Note 1 To change TC1DRA or TC1DRB during a run of the timer set a value sufficiently larger than the count value of the counter Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified Note 2 Do not change TC1CR TFF 1 during a run of the timer TC1CR lt TFF1 gt can be set correctly only at initial ization after reset When the timer stops during PPG TC1CR TFF 1 can not be set correctly from this point onward if the PPG output has the level which is inverted of the level when the timer starts Setting TC1CR lt TFF1 gt specifies the timer F F1 to the level inverted of the programmed value Therefore the timer F F1 needs to be initialized to ensure an arbitrary level of the PPG output To initialize the timer F F1 change TC1CR lt TC1M gt to the timer mode it is not req
306. ion finished inter rupt INTADC is generated ADRS is automatically cleared after AD conversion has started Do not set ADCCRI lt ADRS gt newly again Restart during AD conversion Before setting ADRS newly again check ADCDR2 lt EOCF gt to see that the conversion is completed or wait until the interrupt signal INTADC is generated e g interrupt handling rou tine AD conversion start AD conversion start ADCCR1 lt ADRS gt ADCDR2 lt ADBF gt ADCDR1 status Indeterminate 1st conversion result 2nd conversion result EOCF cleared by reading conversion result ADCDR2 lt EOCF gt INTADC interrupt request ADCDR1 Conversion result Conversion result read read ADCDR2 Conversion result Conversion result read read Figure 17 2 Software Start Mode 17 3 2 Repeat Mode AD conversion of the voltage at the analog input pin specified by ADCCR1 lt SAIN gt is performed repeatedly In this mode AD conversion is started by setting ADCCRI lt ADRS gt to 1 after setting ADCCRI lt AMD gt to 11 Repeat mode After completion of the AD conversion the conversion result 15 stored in AD converted value registers ADCDRI ADCDR2 and at the same time ADCDR2 lt EOCF gt is set to 1 the AD conversion finished inter rupt INTADC is generated In repeat mode each time one AD conversion is completed the next AD conversion is started To stop AD conversion set ADCCR1 AMD to 00 Disable mode by wri
307. ip erase Process SLOOP1 LD LD LD LD LD LD LD CMP JR SET IX 0AAH IY 55H IX 80H IX 0AAH IY 55H IX 10H W HL W HL NZ sLOOP1 FLSCR 3 HHH Flash Memory Write Process SLOOP2 SLOOP3 LD LD LD LD LD CMP JR LD 1 1 55 IX 0AOH HL 3FH W HL W HL NZ sLOOP2 FLSCR 11001000B sLOOP3 Disable interrupts IMF lt 0 Enable command sequence execution 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Loop until the same value is read Set 1 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle FOOOH 3FH Loop until the same value is read Disable command sequence execution Page 229 19 19 4 Access to the Flash Memory Area T5CL8 19 4 2 Flash Memory Control in the MCU mode In the MCU mode write operations are performed by executing the control program in the RAM area Before execution of the control program copy the control program into the RAM area or obtain it from the external using the communication pin The procedures to execute the control program in the RAM area in the MCU mode are described below 19 4 2 1 How to write to the flash memory by executing a user write control program in the RAM area in the MCU
308. ircuit output pin Connect RFi by 4700pF 7 RFEQo offset compensation LPF output 0 015uF 8 signal amplifier input pin 9 RFo Q RF signal generation amplifier output pin g plifier output pi Grounding pin for 3 3 RF amplifier core and 10 RVSS3 EN PLL circuit i FNI2 Main beam signal input pin 3AI F To be connected to PIN diode C 18 Main beam signal input be connected to PIN diode A i3 Main beam signal input pin 3AI F To be connected to PIN diode D T Main beam signal input be connected to PIN diode B PE TPi Sub beam signal input pin i be connected to PIN diode F 16 TNi Sub beam signal input be connected to PIN diode E Connected to PVREF 17 VRo 1 65 V reference voltage output pin And connect to by 0 1uF 100uF 18 AVSS3 Grounding pin for 3 3V CD analog circuits MDi Monitor photodiode amplifier input pi Rererence 19 i onitor photodiode amplifier input pin Voltage 178mVtyp 20 Laser diode amplifier output 4 2010 01 12 TOSHIBA Description Default Remarks Focus Error signal Sub beam add signal 21 FSMONIT output pin monitor pin GND 22
309. is fc 2 Hz in the NORMAL1 2 or IDLE1 2 mode and fs 24 in the SLOW1 2 SLEEP1 2 mode Program the lower byte TTREGS and upper byte TTREG6 in this order in the timer register Programming only the upper or lower byte should not be attempted Note 1 In the event counter mode fix TCjCR lt TFFj gt to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the event counter mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the event counter mode the new value programmed in TTREGj is in effect imme diately after the programming Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 5 6 11 3 7 16 Bit Pulse Width Modulation PWM Output Mode 5 and 6 This mode is used to generate a pulse width modulated PWM signals with up to 16 bits of resolution The TimerCounter 5 and 6 are cascadable to form the 16 bit PWM signal generator The counter counts up using the internal clock or external clock When a match between the up counter and the timer register PWREGS5 PWREG6 value is detected the logic level output from the timer F F6 is switched to the opposite state The counter continues counting The logic level output from the timer F F6 is switched to the opposite state again by the counter overflow and the counter is cleared The INTTC6 interrupt is generated at this
310. ized interrupt Use the SWI instruction only for detection of the address error or for debugging 3 4 1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non existent memory address during single chip mode Code FFH is the SWI instruction so a software interrupt 1s gener ated and an address error is detected The address error detection range can be further expanded by writing FFH to unused areas of the program memory Address trap reset is generated in case that an instruction 1s fetched from RAM DBR or SFR areas 3 4 2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address 3 5 Undefined Instruction Interrupt INTUNDEF Taking code which is not defined as authorized instruction for instruction causes INTUNDEF INTUNDEF is gen erated when the CPU fetches such a code and tries to execute 1t INTUNDEF 1 accepted even 1f non maskable inter rupt is in process Contemporary process is broken and INTUNDEF interrupt process starts soon after it is requested Note The undefined instruction interrupt INTUNDEF forces CPU to jump into vector address as software interrupt SWI does 3 6 Address Trap Interrupt INTATRAP Fetching instruction from unauthorized area for instructions Address trapped area causes reset output or address trap interrupt INTATRAP INTATRAP is accepted even if non maskable in
311. j logic level Since PWREGj in the PWM mode is serially connected to the shift register the value set to PWREGj can be changed while the timer is running The value set to during a run of the timer is shifted by the INTTC interrupt request and loaded into PWREGj While the timer is stopped the value is shifted immedi ately after the programming of If executing the read instruction to PWREG during PWM output the value in the shift register is read but not the value set in Therefore after writing to the reading data of is previous value until is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREGj immediately after the INTTCj interrupt request is generated normally in the INTTCj interrupt service routine If the programming of PWREGj and the inter rupt request occur at the same time an unstable value is shifted that may result in generation of the pulse different from the programmed value until the next interrupt request is generated Note 2 When the timer is stopped during PWM output the PWMj pin holds the output status when the timer is stopped To change the output status program TCjCR lt TFFj gt after the timer is stopped Do not change the TCjCR lt TFFj gt upon stopping of the timer Example Fixing the PWMj pin to the high level when the
312. lator 0 Crystal d External oscillator i resonator i prP RI e e P Figure 2 3 Examples of Resonator Connection Note The function to monitor the basic clock directly at external is not provided for hardware however with dis abling all interrupts and watchdog timers the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program The system to require the adjustment of the oscillation frequency should create the program for the adjust ment in advance Page 11 2 Operational Description 2 2 System Clock Controll ystem Clock Controller 15018 2 2 2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock fc or fs The timing generator provides the following functions Generation of main system clock Generation of divider output DVO pulses Generation of source clocks for time base timer Generation of source clocks for watchdog timer Generation of internal source clocks for timer counters Qv M is spot scs Generation of warm up clocks for releasing STOP mode 2 2 2 1 Configuration of timing generator The timing generator consists of a 2 stage prescaler a 21 stage divider a main system clock generator and machine cycle counters A
313. lay position track index number track playing Atime ere discuss them elevant commands are listed bellow otes playing total time of song means the total time the song can be played this info is not fixed for ever ometimes this information maybe change so host need to check this info in playing status all along BlackPepper3 T PLAY CD TRACK INDEX Ox9f ortrackin only If track number change returns it PLAY TIME 0xa2 It is playing elapsed time eturns it in every 1 second PLAY CD TRACK 0 0 or track D only It includes Aminute and Asecond eturns it in every 1 second PLAY SONG TOTAL TIME 0xd2 It is total time of this file eturns it if thinks this infomaition is changed oted that track D and file have different format in this command PLAY POSITION 0xea This command returning goes along with P E command Every 1 second returns it once This command includes bytes parameters save it If BP3 is hardware reset use these parameters to resume play from last position again ommand sequence 35 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 PLAY CD TRACK INDEX 9F 9F and DO command is for track D DA IX D PLAY CD TRACK ATIME DO only PLAY TIME A2 PLAY POSITION EA PLAY SONG TOTAL TIME D2 6 8 Play Pause FF FR playing status change After playing is started play pause FF F change is availa
314. lculated result is returned as a word Example If the data to be calculated consists of the four bytes the checksum of the data is as shown below A1H B2H 02EAH SUM HIGH 02H SUM LOW EAH The checksum which is transmitted by executing the flash memory write command RAM loader command or flash memory SUM output command is calculated in the manner as shown above Page 254 05 Ls 20 8 2 Calculation data The data used to calculate the checksum is listed in Table 20 15 Table 20 15 Checksum Calculation Data Flash memory writing mode Even when a part of the flash memory is written the checksum of the entire flash memory area 1000H to is calculated Data in the entire area of the flash memory Flash memory SUM output The data length address record type and checksum in Intel mode Hex format are not included in the checksum RAM loader mode RAM data written in the first received RAM The length of data address record type and checksum in Intel address through the last received RAM address Hex format are not included in the checksum Product ID Cod ek 995 9th through 18th bytes of the transferred data For details refer to 20 11 Product ID Code Output mode Flash Memory Status Output mode 9th through 12th bytes of the transferred data For details refer to 20 12 Flash Memory Status Code When the sector erase is executed only the erased area is dat
315. le 20 4 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 5th Operation command data 30H 6th Modified baud Modified baud OK Echo back data 30H Error A1H x 3 A3H x 3 63H x 3 Note 1 7th 8th Password count storage address bit 15 to 08 Note 4 Modified baud ra OK Nothing transmi ed Error Nothing transmitted 9th Password count storage address bit Modified baud ra 10th 07 to 00 Note 4 OK Nothing transmitted Error Nothing transmitted 11th byte 12th byte Modified baud OK Nothing transmitted Error Nothing transmitted Password comparison start address bit 15 to 08 Note 4 Modified baud OK Nothing transmitted Error Nothing transmitted 13th by 14th by Password comparison start address bit 07 to 00 Note 4 15th Password string Note 5 Modified baud ra m th byte OK Nothing transmitted Error Nothing transmitted Intel Hex format binary Modified baud rate Note 2 n th 2 byte m th 1 byte n th 1 byte Modified baud rate OK SUM Upper byte Note 3 Error Nothing transmitted th byte Modified baud rate OK SUM Lower byte Note 3 Error Nothing transmitted Wait state for the next operation com data Modified baud rate th 1 byte Note 1 xxH x 3 indicates that the device e
316. lock frequency 4 5 to 5 5V 268 TOSHIBA 2 22 2 3 Serial mode Vss 0 V 10 to 40 Except hysteresis input 0270 0 70 Input high voltage Vpp24 5V Vpp Hysteresis input x 0 75 Except hysteresis input Vpp x 0 30 Input low voltage gt 4 5 V Hysteresis input E x 0 25 Clock frequency XIN XOUT Page 269 22 Electrical Characteristics 22 1 Absolute Maximum Ratings T5CL8 22 3 DC Characteristics Vss 0 V 40 to 85 Hysteresis voltage Hysteresis input Vpp 5 5 V VTEST 5 5 Input current Sink open drain tri state port Input resistance RESET pull up Vpp 5 5 V Vin O V Sink open drain port Vpp 5 5 V Vout 5 5 V Output leakage current Tri state port 5 5 V 5 5 VIO V Output high voltage Tri state port 4 5 V lop 0 7 mA Output low voltage Except XOUT P3 P5 4 5 V logi 1 6 mA High t port Output low curren Pepe 4 5V Vg 1 0 V Vpp 5 5V When program Vin 5 3 V 0 2 V operates on flash Vrest 5 3 Vjo 1 v Memory Note5 6 fc 16 MHz fs 32 768 kHz When a program operates on flash memory Note5 6 Vpp 3 0V Vin 228 02 V When program INT operates on RAM VTEST 2 8 V 0 1 V fs 32 768 kHz 5 5 V Vin 5 3 V 0 2 V VTEST 5 3 V 0 1 V Supply current in NORMAL1 2 modes Supply current in IDLE 0 1 2 modes Supply c
317. m is reseted BlackPepper3 will send PICK UP REQUEST command first This command will be sent every 200ms until host side return PICK UP SELECT command If host side doesn t want to use BlackPepper3 inside coefficient can send command 0x41 0x42 0x43 0x44 to start a coefficient transmission process This process will be told you in 6 34 Anyway BlackPepper3 will return a RESET POWER 0xB500 command eventually so reset process is finished Relevant commands are listed bellow HOST gt BlackPepper3 PICK UP_SELECT 0x40 This command is valid only when sent Oxb6 command BlackPepper3 gt HOST RESET POWER 0xb5 ByteO of data filed 0 00 in case of It means BP3 finished his reset process hardware reset PICK UP_REQUEST 0xb6 This is the first command after hardware reset Use this command to synchronaize your system This command will not be sent again after standby out Command sequence HOST PICK UP_REQUEST BP3 BP3 send command to request host select pick up This command is sent in every 200ms until host acknowledge PICK UP_SELECT it RESET POWER BP3 reset OK 6 2 Get firmware version and set firmware feature After reset ok host can get firmware version and set firmware feature This process can only be done before any reading process Relevant commands are listed bellow HOST gt BlackPepper3 GET_FIRM_VERSION 0x8007 byteO of data field
318. mand se uence PLAY TRACK UP TRACK DOWN DIR UP DIR DOWN command case HOST BP3 PLAY TRACK UP TRACK DOW N DIR UP DIR DOWN These command will issue a 0 command from BP3 even track number is the same for example in repeat 1 mode PLAY FILE DIR NUMBER AO Every A0 command will be PLAY FILE TYPE 99 followed this command command return very quickly even playing is not start genuinely But 99 command is returned after the file dir name is got but before ID3 reading process playing track number is auto changed case Please be noted that this case include that playing track number is no change but begin another playing for example in repeat 1 mode 34 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 New playing happen 0 PLAY FILE DIR NUMBER AO command returns 99 command returns after AO PLAY FILE TYPE 99 command if file type is known 6 7 Get play information The play information includes file name folder name ID3 info title artist album bitrate info sample frequency info playing time playing total time of song play position used for resume play and some infomation only be available in auio track playing like track index number track playing Atime The file name folder ID3 info bitrate info sample frequency info need a request command first but others info can be return automatically if BP3 thinks they are changed These info are playing time playing total time of song p
319. me PLAY FILE NAME Oxff length 2 DATA 0xN Z file name of playing file Oxff length 2 0xab DATA 0xN 2 PLAY DIR NAME folder name of playing folder PLAY ID3 INFO 3 DATA OxNN lias information of playing file MSF PLAY NG 0 2 10 63 0 01 OxNN m play is ng IRESUME STATUS 2 10 64 0 resume check result is ok or ng 0 2 0 5 0 00 OxNN system reset out power on reset STANDBY Oxff 2 0 5 0 01 OxNN reset out from standby request host side select pick up or send pick up coefficient PICK UP REQUEST 1 Oxb6 OxNN MODE 2 Oxb7 DATA OxNN repeat mode INTRO MODE Oxff 2 0 8 OxNN intro mode TOSHIBA T5CJ3 7G28 F M Specification 2 random mode MODE 2 10 59 DATA OxN 1 Oxbb OxNN ID3 NONE there is no id3 information ack to id3 request command CD TEXT RESULT 3 Oxbc DATA 0 2 gt cd text information found or not CD TEXT INFO Oxffllength 3 0xbd DATA OxNN_ cd text title or artist information REPEAT STATUS Oxff 2 Oxbf DATA OxNN repeat status file name of selected file ack to Ox06 select FILE NAME SELECTED Oxff length 2 0 0
320. memory writing mode The 5th byte of the received data contains the product ID code output mode command data COH When the 5th byte contains the operation command data shown in Table 20 6 the device echoes back the value which is the same data in the 6th byte position of the received data in this case COH If the 5th byte data does not contain the operation command data the device enters the halt condition after sending 3 bytes of operation command error code 63H The 9th through 19th bytes contain the product ID code For details refer to 20 11 Product ID Code Page 249 20 Serial PROM Mode 20 6 Operation Mode T5CL8 5 After sending the checksum the device waits for the next operation command data Page 250 05 Ls 20 6 6 Flash Memory Status Output Mode Operation Command C3H Table 20 12 shows Flash memory status output mode process Table 20 12 Flash Memory Status Output Mode Process Transfer Bytes Transfer Data from External Con Baud Bale Transfer Data from T5CL8 troller to T5CL8 External Controller 1st byte Matching data 9600 bps Automatic baud rate adjustment 2nd byte 7 9600 bps OK Echo back data Error Nothing transmitted 3rd byte Baud rate modification data 9600 bps See Table 20 4 4th byte 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 5th byte Operation command data C3H Modified baud rate 6th byte Modified baud rate OK E
321. mit receive operation is stopped after all trans fer of the data is finished When transmit receive operation is finished SIO1SR lt SIOF gt 15 cleared to 0 and 501 pin 15 kept in high level In external clock operation SIO1CR lt SIOS gt must be cleared to 0 before SIO1SR lt SEF gt 15 set to 1 by beginning next transfer The way of setting SIO1CR lt SIOINH gt Transmit receive operation is stopped immediately after SIOICR SIOINH is set to 1 In this case SIO1CR lt SIOS gt SIOISR register SIOIRDB register and SIOITDB register initialized Page 172 05 un Clearing SIOS SIO1CR SIOS SIO1SR SIOF Start shift Start shift Start shift operation y operation operation SIO1SR SEF ee Te e SO pee n 59996992 8 20 SI1 pin FO INTSIO1 interrupt request SIO1SR TXF 1 1 SIO1TDB m Writing transmit Writing transmit Writing T data data B data C SIO1SR RXF IS Reading received Reading received Reading received data D data E data F Figure 14 13 Example of Internal Clock and MSB Transmit Receive Mode Page 173 14 Synchronous Serial Interface 5101 14 3 Function SIO1CR SIOS SIO1SRsSIOF 5 015 lt 5 gt SCK1 pin output 501 pin SI1 pin INTSIO1 interrupt request SIO1SR TXF SIO1TDB SIO1SR RXF SIO1RDB T5CL8 Readin
322. mmand data in the flash memory status output mode FAH 3 When the 5th byte of the received data contains the operation command data shown in Table 1 6 the device echoes back the value which is the same data in the 6th byte position of the received data in Page 252 TOSHIBA T5CL8 this case FAH If the 5th byte does not contain the operation command data the device enters the halt condition after transmitting 3 bytes of operation command error code 63H The 7th through m th bytes of the transmitted and received data contain the same data as in the flash memory writing mode The n th byte contains the status to be transmitted to the external controller in the case of the success ful security program Page 253 20 Serial PROM Mode 20 7 Error Code T5CL8 20 7 Error Code When detecting an error the device transmits the error code to the external controller as shown in Table 20 14 Table 20 14 Error Code Transmit Data Meaning of Error Data 62H 62H 62H Baud rate modification error 63H 63H 63H Operation command error ATH A1H A1H Framing error in the received data A3H A3H A3H Overrun error in the received data Note If a password error occurs T5CL8 does not transmit an error code 20 8 Checksum SUM 20 8 1 Calculation Method The checksum SUM is calculated with the sum of all bytes and the obtained result is returned as a word The data is read for each byte unit and the ca
323. mode select LD TC2CR 00111100B Starts 2 Table 9 2 Timer Counter 2 External Input Clock Pulse Width Minimum Input Pulse Width s 1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 mode Timer start TC2 pin input Counter TC2DR INTTC2 interrupt Figure 9 3 Event Counter Mode Timing Chart 9 3 3 Window mode In this mode counting up performed on the rising edge of an internal clock during TC2 external pin input Window pulse is H level The contents of TC2DR are compared with the contents of up counter If a match found an INTTC2 interrupt is generated and the up counter is cleared The maximum applied frequency TC2 input must be considerably slower than the selected internal clock by the TC2CR lt TC2CK gt Note It is not available window mode in the SLOW SLEEP mode Therefore at the window mode in NORMAL mode the timer should be halted by setting TC2CR lt TC2S gt to 0 before the SLOW SLEEP mode is entered Page 97 9 16 Bit Timer Counter2 2 9 3 Function T5CL8 Example Generates an interrupt inputting H level pulse width of 120 ms or more at fe 16 MHz TBTCR lt DV7CK gt sr LDW TC2DR Sets TC2DR 120 ms 21 OOEAH DI IMF 0 SET EIRE 6 Enables INTTC2 interrupt EI IMF 1 LD TC2CR 00000101B TC2sorce clock mode select LD TC2CR 00100101B Starts TC2 Timer start TC2 pin input Internal clock Counter TC2DR
324. mple auto stopping e ent cleared all mode setting so command ill return ommand sequence Set play mode HOST BP3 REPEAT MODE 39 INTRO MODE 38 RANDOM MODE 3a BlackPepper3 return play mode when play mode change HOST BP3 REPEAT MODE b7 INTRO MODE b8 RANDOM_MODE b9 6 17 MSF play function CD DA only or disc or disc it can start play by specified S alue Send command S it specified minute second frame alue e adecimal alue after reading process is finis ed playing ill be start from t S alue f S alue specified is out of playable range lac returns a command Rele ant commands are listed bello S lac MSF PLAY 0x00 lay it specified S alue lac S 49 TOSHIBA T5CJ3 7G28 F M Specification MSF PLAY NG 0xb301 S alue is out of playable range ommand sequence ase S play ere is no command returned HOST BP3 MSF PLAY 00 ase S play lay doesnt start returna command to ost HOST BP3 MSF PLAY 00 MSF PLAY NG B301 6 18Select folder or file epper support type of select folder or file operation ello is command list and later ill describe e type operation boutt is function please conform recommended command flo Rele ant commands are listed bello S lac SEL FOLDER1 05xxxx00 Select a folder to get its information include folder name t ill issue a folder analysis process So t is need a time to process Supp
325. n a serial clock is output from 5 2 pin Note 3 In external clock operation when the falling edge is input from SCK2 pin after SIO2CR lt SIOS gt is set to 1 SIO2TDB is transferred to shift register immediately Page 183 15 Synchronous Serial Interface 5102 15 3 Function SIO2CR lt SIOS gt SIO2SR lt SIOF gt SIO2SR lt SEF gt 5 2 pin outout 502 pin 5 025 lt gt INTSIO2 interrupt request SIO2TDB T5CL8 2 During the transmit operation When data is written to SIO2TDB SIO2SR TXF is cleared to 0 In internal clock operation in case a next transmit data is not written to SIO2TDB the serial clock stops to level by an automatic wait function when all of the bit set in the SIOZ2TDB has been transmitted Automatic wait function is released by writing a transmit data to SIO2TDB Then trans mit operation is restarted after maximum 1 of serial clock When the next data is written to the SIOZ2TDB before termination of previous 8 bit data with SIO2SR lt TXF gt 1 the next data is continuously transferred after transmission of previous data In external clock operation after SIO2SR lt TXF gt is set to 1 the transmit data must be written to SIO2TDB before the shift operation of the next data begins If the transmit data 15 not written to SIOZ2TDB transmit error occurs immediately after shift opera tion is started Then INTSIO2 interrupt request i
326. n input clock to the 7th stage of the divider depends on the operating mode SYSCR2 lt SYSCK gt and TBTCR DV7CK that is shown in Figure 2 4 As reset and STOP mode started canceled the prescaler and the divider are cleared to 07 High frequency clock fc Low frequency Multiplexer clock fs Warm up controller Watchdog timer Timer counter Serial interface Time base timer divider output etc Peripheral functions Figure 2 4 Configuration of Timing Generator Page 12 05 n Timing Generator Control Register TBTCR F 6 5 4 3 2 1 0 0036H DVOEN DVOCK DV7CK TBTEN TBTCK Initial value 0000 0000 B DV7CK of input to the 7th stage 0 fc 2 Hz R W of the divider 1 fs Note 1 In single clock mode do not set DV7CK to 1 Note 2 Do not set 1 on DV7CK while the low frequency clock is not operated stably Note 3 fc High frequency clock Hz fs Low frequency clock Hz Don t care Note 4 In SLOW1 2 and SLEEP 1 2 modes the DV7CK setting is ineffective and fs is input to the 7th stage of the divider Note 5 When STOP mode is entered from NORMAL 1 2 mode the DV7CK setting is ineffective during the warm up period after release of STOP mode and the 6th stage of the divider is input to the 7th stage during this period 2 2 2 2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock The min
327. nce 42 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 GET INFO DIR NAME 8004 PLAY NAME AB 6 14 Get ID3 information is paragrap es getting information ack epper supports featureas eo ta e ie type version engt o ing yes V ytes so 5 information ytes ack epper ing type an content y comman e evant s iste S ack epper GET INFO TITLE ID3 0x8000 e uesttit e informaiton GET INFO ARTIST ID3 0x8001 e uest artist information GET INFO ALBUM ID3 0x8002 e uesta um information ack epper S PLAY 103 INFO 0xac ID3 TITLE INFO 0xac00 ts tite infomation ID3 ARTIST INFO 0xacO01 ts artist information ID3 ALBUM INFO 0xac02 ts a um information ID3_NONE 0xbb isn t foun ID3_BUSY 0x9b rea ingis usy se uence Case 1 ID3 reading busy 43 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 Start to get tit e information GET INFO TITLE ID3 8000 ID3 BUSY 9b BP3 report 103 rea ing E un usy HOST can try it again after un re s ms Case 2 ID3 no found HOST BP3 Start to get tit e information GET INFO TITLE ID3 8000 ID3 NONE bb os asn t foun any 103 in t is song Case 3 ID3 reading ok HOST BP3 GET INFO TITLE ID3 8000 ID3 TITLE 00 GET INFO ARTIST ID3 8001 ARTIST IN
328. nce of disc read with C TE T analysis CD DA case HOST BP3 Can set auto play or not in this READ DEVICE 12 command CD TOC INFO 0x90 RESULT bc This command tell host CD TEXT exist or not and the character set code if exist STOP STATUS 8401 or PLAY STATUS 8400 If set auto play return PLAY MODE otherwise return STOP mode MIX CD case HOST BP3 Can set auto play or not in this READ DEVICE 12 DEVICE TYPE 82 CD TOC INFO 90 command TTL FILE DIR NUMBER 94 This command tell host RESULT bc CD TEXT exist or not and the character set code if exist STOP STATUS 8401 or PLAY If set auto play return PLAY STATUS 8400 MODE otherwise return STOP mode Command se uence of ettin CD TEXT information Case 1 get album or title al um information is same as ettin title if set num ero itis al um information of total disc if set trac 57 TOSHIBA T5CJ3 7G28 F M Specification num er none ero it is title information of e ery trac HOST BP3 GET CD TEXT title album 8100 CD TEXT_INFO title album bd00 Case 2 get artist Same as title information itcan et artist of trac num er ero In fact it is the artist of total disc HOST BP3 CD TEXT artist 8101 CD TEXT_INFO artist bd01 Case 3 title or artist content is empty ecause not e ery trac has title or artist information In this case lac Pepper ustretu
329. nction when all of the bit set in the data has been transmitted Next transmit data is not written to SIOITDB after reading a received data from SIOIRDB Received data is not read from SIOIRDB after writing a next transmit data to SIOITDB e Neither SIOITDB nor SIOIRDB is accessed after transmission The automatic wait function is released by writing the next transmit data to SIOITDB after reading the received data from SIOIRDB or reading the received data from SIOIRDB after writing the next data to SIOITDB Then transmit receive operation 15 restarted after maximum 1 cycle of serial clock In external clock operation reading the received data from SIOIRDB and writing the next data to SIOITDB must be finished before the shift operation of the next data begins If the transmit data is not written to SIOITDB after SIOISR TXF is set to 1 transmit error occurs immediately after shift operation is started When the transmit error occurred SIOISR TXERR is set to 1 If received data is not read out from SIOIRDB before next shift operation starts after setting SIOISR RXF to 1 receive error occurs immediately after shift operation is finished When the receive error has occurred SIO1SR lt RXERR gt is set to 1 Stopping the transmit receive operation There are two ways for stopping the transmit receive operation The way of clearing 5101 lt 51 5 gt When SIO1CR lt SIOS gt is cleared to 0 trans
330. nd can clear bookmark setting About DATA details please refer to 5 3 PART Il TOSHIBA T5CJ3 7G28 F M Specification 5 3 Command data field detals PARTI MSF PLAY 0x00 byte 0 MSF play minute setting 1 MSF play second setting 2 MSF play frame setting SEL FOLDERI 0x05 byte 0 folder number high byte byte 1 folder number low byte byte 2 0x00 need analyze folder and get folder name SEL FOLDER2 0x05 byte 0 folder number high byte byte 1 folder number low byte byte 2 0x01 don t need analyze folder don t get folder name SEL 1 0 06 byte 0 relative number in selected folder high byte 1 relative file number in selected folder low byte SEL FILE2 0x07 byte 0 file number high byte byte 1 file number low byte 0x00 read and stop after read process 0 01 read an play after read process READ DEVICE 0x12 byte 0 0x80 TOC read CD TEXT read and stop after read CD only 0x81 TOC read CD TEXT read and play after read CD only 0x01 play by file number PLAY 0x14 byte 0 0x02 play by folder number byte 1 file number or folder number high byte byte 2 file number or folder number low byte For USB or SD mode this command just issue a stop operation and ignore this byte value For CD mode this byte value define the pick up moving after stop STOP 0x18 byte 0 0x00 stop If it is CD mode move pick up to inner si
331. nd t is folder s inside info local total file and start file of S command SELECT WRONG 0xc6 Return selecting 15 rong for all of S R S R S S command 6 18 1 Select a folder and inside file to get their name ommand sequence 51 TOSHIBA T5CJ3 7G28 F M Specification HOST SEL FOLDER1 05xxxx00 INSIDE INFO c2 DIR NAME SELECTED c1 SEL FILE1 06 FILE NAME SELECTED cO SEL FILE1 06 FILE NAME SELECTED cO ote erateitinsto state ote lease conform above command se uence until get returning of D A S ote3 any selection out of selecting available cause BP3 return a S T command 5 5 D If selection is out range of total folder number in device S T returns for S command if selection is out range of dir local total file number S T returns for S Selection is out range of total file number in device S returns 6 18 2 Select a file to get its located folder number ommand se uence HOST BP3 SEL FILE2 07 DIR INFO OF FILE c3 ote any selection out of selecting available ill cause BP3 return a S T command orS S D If selection is out range of total folder number in device S T returns for S command if selection is out range of dir local total file number S T returns for S Selection is out range of total file number in device S T D command BP3 52 Select a folder it issue BP3 starting a folder analysis Don t send command again until received folder name Afte
332. ndicating the area of the ROM incorporated in the product The external control ler reads this code and recognizes the product to write In the case of T5CL8 the addresses from 1000H to FFFFH become the ROM area Page 239 20 Serial PROM Mode 20 6 tion Mod peration Mode 15018 6 Flash memory status output mode The status ofthe area from FFEOH to FFFFH and the security program condition are output as 7 byte code The external controller reads this code to recognize the flash memory status 7 Flash memory security program setting mode This mode disables reading and writing the flash memory data in parallel PROM mode In the serial PROM mode the flash memory writing and RAM loader modes are disabled To disable the flash memory security program perform the chip erase in the flash memory erasing mode Page 240 05 Ls 20 6 1 Flash Memory Erasing Mode Operating command FOH Table 20 7 shows the flash memory erasing mode Table 20 7 Flash Memory Erasing Mode Transfer Transfer Data from the External BARRES Transfer Data from T5CL8 to y Controller to T5CL8 the External Controller 1st byte Matching data 5AH 9600 bps Automatic baud rate adjustment 2nd byte 9600 bps OK Echo back data Error No data transmitted 3rd by Baud rate change data Table 20 4 9600 bps 4th by 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 5th Operation command data
333. nsfer Data Format NY Note In order to switch the transfer data format perform transmit operations in the above Figure 13 3 sequence except for the initial setting Page 152 05 me 13 4 Transfer Rate The baud rate of UART2 is set of UART2CR1 lt BRG gt The example of the baud rate are shown as follows Table 13 1 Transfer Rate Example Source Clock 76800 baud 38400 baud 19200 baud 38400 19200 9600 19200 9600 4800 9600 4800 2400 4800 2400 1200 2400 1200 600 When TCS is used as the UART2 transfer rate when UART2CRI BRG 110 the transfer clock and transfer rate are determined as follows Transfer clock Hz TCS source clock Hz TTREGS setting value Transfer Rate baud Transfer clock Hz 16 13 5 Data Sampling Method The UART2 receiver keeps sampling input using the clock selected by UART2CRI BRG until a start bit is detected in RXD2 pin input RT clock starts detecting L level of the RXD2 pin Once a start bit is detected the start bit data bits stop bit s and parity bit are sampled at three times of RT7 RT8 and RT9 during one receiver clock interval RT clock RTO is the position where the bit supposedly starts Bit is determined according to major ity rule The data are the same twice or more out of three samplings RXD2 Start bit Bit 0 RTO 12 34 5 6 7 8 9 10111213 14150 12 34 5 6 7 9 10 11 RT clock I
334. nternal receive data Start bit Bit 0 Without noise rejection circuit RTO 12 3 4 5 6 7 8 9 1011121314150 12 34 56 7 10 11 RT clock Internal receive data Start bit Bit 0 b With noise rejection circuit Figure 13 4 Data Sampling Method Page 153 13 Asynchronous Serial interface UART2 13 6 STOP Bit Length T5CL8 13 6 STOP Bit Length Select a transmit stop bit length 1 bit or 2 bits by VART2CR1 lt STBT gt 13 7 Parity Set parity no parity by UART2CRI lt PE gt and set parity type Odd Even numbered by 2 lt gt 13 8 Transmit Receive Operation 13 8 1 Data Transmit Operation Set 2 lt gt to 1 Read UART2SR to check UART2SR lt TBEP gt 1 then write data in TD2BUF Transmit data buffer Writing data in TD2BUF zero clears 25 lt gt transfers the data to the transmit shift register and the data are sequentially output from the TXD2 pin The data output include a one bit start bit stop bits whose number is specified in UART2CR1 lt STBT gt and a parity bit if parity addition is specified Select the data transfer baud rate using UART2CR1 lt BRG gt When data transmit starts transmit buffer empty flag UART2SR lt TBEP gt is set to 1 and an INTTXD2 interrupt is generated While UART2CR1 lt TXE gt 0 and from when 1 is written to UART2CRI TXE to when send data are written to TD2BUF
335. nters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Note 2 Refer to 20 9 Intel Hex Format Binary Note 3 Refer to 20 8 Checksum SUM Note 4 Refer to 20 10 Passwords Note If addresses from FFEOH to FFFFH are filled with the passwords not compared because the device is consid ered as a blank product Transmitting a password string is not required Even in the case of a blank product it is required to specify the password count storage address and the password comparison start address Transmit these data from the external controller If a password error occurs due to incorrect password count storage address or password comparison start address T5CL8 stops UART communication and enters the halt condition Therefore when a password error occurs initialize T5CL8 by the RESET pin and reactivate the serial ROM mode Note 6 If the security program is enabled or a password error occurs T5CL8 stops UART communication and enters the halt confition In this case initialize T5CL8 by the RESET pin and reactivate the serial ROM mode Note 7 If an error occurs during the reception of a password address or a password string T5CL8 stops UART com munication and enters the halt condition In this case initialize T5CL8 by the RESET pin and reactivate the serial PROM mode Page 243 20 Serial PROM Mode 20 6 Operation Mode T5CL8 Description of the flas
336. ntinues counting The logic level output from the timer F F6 is switched to the opposite state again when a match between the up counter and the timer register TTREGS TTREG6 value is detected and the counter is cleared The INTTC6 interrupt is generated at this time Two machine cycles are required for the high or low level pulse input to the TC5 pin Therefore a maxi mum frequency to be supplied 15 fc 2 Hz in NORMALI 2 or IDLE1 2 mode and fs 2 to in the SLOWI 2 or SLEEPI 2 mode Since the initial value can be set to the timer F F6 by TC6CR lt TFF6 gt positive and negative pulses be generated Upon reset the timer F F6 is cleared to 0 The logic level output from the PPG6 pin is the opposite to the timer F F6 Set the lower byte and upper byte in this order to program the timer register 5 TTREG6 PWREGS PWREGO Programming only the upper or lower byte should not be attempted For PPG output set the output latch of the I O port to 1 Example Generating a pulse with 1 ms high level width and a period of 16 385 ms fc 16 0 MHz Setting ports LDW PWREGS5 07D0H Sets the pulse width LDW 5 8002H Sets the cycle period 3 LD TC5CR 33H Sets the operating clock to fc 2 and16 bit PPG mode lower byte Sets TFF6 to the initial value 0 and 16 bit LD TC6CR 057H mode upper byte LD TC6CR 05FH Starts the timer Note 1 In the PPG mode d
337. o convert INTTC1SW at each INTTC1 LD TC1CR 00000110B Sets the TC1 mode and source clock DI IMF 0 SET EIRL 5 Enables INTTC1 EI IMF 1 LD TC1CR 00100110B Starts TC1 with an external trigger at MCAP1 0 PINTTC1 CPL INTTC1SW 0 INTTC1 interrupt inverts and tests INTTC1 service switch JRS F SINTTC1 LD A TC1DRBL Reads TC1DRB High level pulse width LD W TC1DRBH LD HPULSE WA Stores high level pulse width in RAM RETI SINTTC1 LD A TC1DRBL Reads TC1DRB Cycle LD W TC1DRBH LD WIDTH WA Stores cycle in RAM RETI Duty calculation VINTTC1 DW PINTTC1 INTTC1 Interrupt vector WIDTH HPULSE TC1 pin interrupt request INTTC1SW 87 8 16 Bit TimerCounter 1 TC1 8 3 Functi unction 15018 Count start Count start TC1 pin input f Trigger l TC1S 10 Internal clock LEEFLELELELEHELELE UE LUE LL LT Counter TC1DRB INTTC1 interrupt request Application High or low level pulse width measurement a Single edge capture MCAP1 1 Count start Count start TC1 pin input 4 TC1S 40 Internal clock LELELELELE MV LE TELE LT I Counter TC1DRB INTTC1 interrupt request Application 1 Cycle frequency measurement 2 Duty measurement b Double edge capture MCAP1 0 Figure 8 6 Pulse Width Measurement Mode Page 88 05 Ls 8 3 6 Progr
338. o disable DVOEN 0 do not change the setting of the divider output frequency Page 75 7 7 2 Divider Output DVO Example 1 95 kHz pulse output fc 16 0 MHz LD TBTCR 00000000B DVOCK lt 00 LD TBTCR 10000000B DVOEN lt 1 Table 7 2 Divider Output Frequency Example fc 16 0 MHz fs 32 768 kHz Divider Output Frequency Hz 1 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 DV7CK 0 DV7CK 1 Mode 1 953 1 024 3 906 2 048 k 7 813 4 096 15 625 8 192 k Page 76 T5CL8 TOSHIBA TC1 16 Bit TimerCounter 1 8 Configuration 8 1 eu ees 5 eJou 104 uod uo ejejedo jou uonounJ 1 LOL basal T HOLOL G IUM ejqeu3 y 6 9 E MOLIOL VSOLOL 51 19592 Odd g 9190 9dd 5 52 eoujnos V A 1 Jejunoo dn 319 9 3 9 esind 10129 ep D LOLLNI E i Figure 8 1 TimerCounter 1 TC1 Page 77 8 16 Bit TimerCounter 1 TC1 8 2 TimerCounter Control T5
339. o not change the PWREGi and TTREGi settings while the timer is running Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode the new values grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and Therefore if PWREGi and TTREGi are changed while the timer is running an expected operation may not be obtained Note 2 When the timer is stopped during PPG output the PPG6 pin holds the output status when the timer is stopped To change the output status program TC6CR lt TFF6 gt after the timer is stopped Do not change TC6CR lt TFF6 gt upon stopping of the timer Example Fixing the PPG6 pin to the high level when the TimerCounter is stopped CLR TC6CR 3 Stops the timer CLR TC6CR 7 Sets the PPG6 pin to the high level Note 3 i 5 6 Page 135 11 8 Bit TimerCounter 5 TC6 11 1 Configuration T5CL8 3 jsenbai 991 LNI 1 gt lt 4 sdojs UBYM 4 4 1 JO 1 1 peep yey 93 4 99441 1 1901 59341 1 993HMd 1901 SgodHMd eounos lt 9441 gt 40901 lt 5901 gt 40901 Figure 11 8 16 Bit Mode Timing Chart TC5 and TC6 Page 1
340. ode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode The status under the SLEEP2 mode is same as that under the SLEEP1 mode except for the oscillation circuit of the high frequency clock 7 SLEEPO mode In this mode all the circuit except oscillator and the timer base timer stops operation This mode is enabled by setting 1 on bit SYSCR2 lt TGHALT gt When SLEEPO mode starts the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT Then upon detecting the falling edge of the source clock selected with lt gt the timing generator starts feeding the clock to all peripheral circuits When returned from SLEEPO mode the CPU restarts operating entering SLOW1 mode back again SLEEPO mode is entered and returned regardless of how lt gt is set When IMF 1 interrupt individual enable flag 1 and lt gt 1 interrupt pro cessing is performed When SLEEPO mode is entered while TBTCR lt TBTEN gt 1 the INTTBT interrupt latch is set after returning to SLOW1 mode 2 2 8 8 STOP mode In this mode the internal oscillation circuit is turned off causing all system operations to be halted The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode STOP mode is started by the system control register 1 SYSCR1 and STO
341. ode with source clock fc 2 Hz and generates an interrupt every 25 ms at fc 16 MHz LDW TC2DR 061AH Sets TC2DR 25 ms 28 fc 061AH DI IMF 0 SET EIRE 6 Enables INTTC2 interrupt EI IMF 1 LD TC2CR 00001000B Source clock mode select LD TC2CR 00101000B Starts Timer Page 95 9 16 Bit Timer Counter2 2 9 3 Function T5CL8 Timer start Source clock Up counter TC2DR INTTC2 interrupt Figure 9 2 Timer Mode Timing Chart Page 96 05 9 3 2 Event counter mode In this mode events are counted on the rising edge of the TC2 pin input The contents of TC2DR are com pared with the contents of the up counter If a match is found an INTTC2 interrupt is generated and the counter 1s cleared Counting up is resumed every the rising edge of the TC2 pin input after the up counter 18 cleared Match detect 1s executed on the falling edge of the TC2 pin Therefore an INTTC2 interrupt is generated at the falling edge after the match of TC2DR and up counter The minimum input pulse width of TC2 pin is shown in Table 9 2 Two or more machine cycles are required for both the and levels of the pulse width Example Sets the event counter mode and generates an INTTC2 interrupt 640 counts later LDW TC2DR 640 Sets TC2DR DI IMF 0 SET EIRE 6 Enables INTTC2 interrupt EI IMF 1 LD TC2CR 00011100B TC2 source vclock
342. og Timer Configuration Reset release 223 or fs 215 1 221 or 5 213 fc 29 or 5 211 1 217 or fs 29 Binary counters Selector Reset request INTWDT interrupt request Internal reset Writing disable code Writing WDTOUT clear code Controller 0034 8 0035 if WDTCR1 WDTCR2 Watchdog timer control registers Figure 6 1 Watchdog Timer Configuration Page 65 6 Watchdog Timer WDT 6 2 Watchdog Timer Control T5CL8 6 2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers WDTCR1 and WDTCR2 watch dog timer is automatically enabled after the reset release 6 2 1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected as shown below 1 Setthe detection time select the output and clear the binary counter 2 Clear the binary counter repeatedly within the specified detection time If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason the watch dog timer output is activated by the binary counter overflow unless the binary counters are cleared When WDTCRI lt WDTOUT gt is set to 1 at this time the reset request is generated and then internal hardware is initialized When WDTCR1 lt WDTOUT is set to 0 a watchdog timer interrupt INTWDT is generated The watchdog timer temporarily stops counting in the STOP mode including the warm up or IDLE
343. ogramming the communication format of the write controller must also be set in the same manner The default baud rate is 9600 bps regardless of operating frequency of the microcontroller The baud rate can be modified by transmitting the baud rate modification data shown in Table 1 4 to 5 8 The Table 20 5 shows an operating frequency and baud rate The frequencies which are not described in Table 20 5 can not be used Baud rate Default 9600 bps Data length 8 bits Parity addition None Stop bit 1 bit Table 20 4 Baud Rate Modification Data Baud rate modification data 04H 05H 06H 07H 18 28 Baud rate bps 76800 62500 57600 38400 31250 19200 9600 Page 237 20 Serial PROM Mode 20 4 Interface Specifications for UART T5CL8 Table 20 5 Operating Frequency and Baud Rate in the Serial PROM Mode Reference Baud Rate bps Baud Rate Modification Data Ref Fre SEE Rating MHz quency MHz 1 91 to 2 10 3 82 to 4 19 3 82 to 4 19 4 70 to 5 16 4 70 to 5 16 5 87 to 6 45 5 87 to 6 45 7 05 to 7 74 7 64 to 8 39 9 40 to 10 32 10 9 40 to 10 32 12 11 75 to 12 90 12 288 11 75 to 12 90 12 5 11 75 to 12 90 14 7456 14 10 to 15 48 16 15 27 to 16 77 Note 1 Ref Frequency and Rating show frequencies available in the serial PROM mode Thoug
344. ol Register SIO1CR 7 6 5 4 3 2 1 0 0020H SIOS SIOINH SIOM SIODIR SCK Initial value 0000 0000 0 Stop SIOS Specify start stop of transf SIOINH Forcibly stops transfer Note 1 a 1 Forcibly stop Automatically cleared to 0 after stopping 00 Transmit mode 01 Receive mode 10 Transmit receive mode 11 Reserved SIODIR Selects direction of transfer 0 MSB Transfer beginning with Dita 1 LSB Transfer beginning with bitO NORMAL1 2 or IDLE1 2 modes or IDLE1 2 modes Selects transfer mode SLOW SLEEP E TBTCR mode lt DV7CK gt 0 DV7CK 1 15 25 Reserved Selects serial clock Reserved Reserved Reserved Reserved Reserved External clock Input from SCK1 pin Note 1 When SIO1CR SIOINH is set to 1 SIO1CR lt SIOS gt SIO1SR register SIOTRDB register and SIO1TDB register are initialized Note 2 Transfer mode direction of transfer and serial clock must be select during the transfer is stopping when SIO1SR lt SIOF gt 0 Note 3 fc High frequency clock Hz fs Low frequency clock Hz Don t care Page 160 05 d Serial Interface Status Register SIO1SR 7 6 5 4 3 2 1 0021H SIOF SEF TXERR RXERR Initial value 0010 00 SIOF Serial transfer operation status 0 Transfer finished monitor 1 Transfer in progress Read only SEF Number of clocks monitor 1 1 to 7 clocks 0 Data exists in transmit buffer TXF T it
345. ol for port P6 Specified for each bit x R W P6CR2 T 6 5 4 3 2 1 0 OF9CH Initial value 1111 1111 2 P6 port input control Specified for each bit eae R W Note 1 The port placed in input mode reads the pin input state Therefore when the input and output modes are used together the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction Note 2 When used as an analog inport be sure to clear the corresponding bit of POCR2 to disable the port input Note 3 Do not set the output mode 6 1 1 for the pin used as an analog input pin Note 4 Pins not used for analog input can be used as ports During AD conversion output instructions should not be executed to keep a precision In addition a variable signal should not be input to a port adjacent to the analog input during AD con version Page 61 5 Ports 5 8 Port P7 P77 to P70 15018 5 8 Port P7 P77 to 70 Port P7 1s an 8 bit input output port which can be configured as an input or output in one bit unit Port P7 is also used as an analog input Input output mode is specified by the P7 control register P7CR1 and P7 input control register P7CR2 During reset the P7CRI is initialized to 0 the P7CR2 is initialized to 1 and port P7 becomes an input mode And the P7DR is initialized to 0 When used as an output port the corresponding bit of P7CR1 should be se
346. oldre name C2 select folder without folder analyze to get folder inside SEL_FOLDER2 4 0 05 OxNN information cl SEL_FILE1 3 0x06 OxNN select file to get file name 2 SEL FILE2 3 10 07 OxNN select file to get folder inside information cl EJECT Oxff 1 0 10 OxNN disc cd mode only READ DEVICE loxtr 2 0 12 OxNN start read process PLAY 4 10 14 OxNN play cl STOP loxtr 2 0 18 OxNN stop PAUSE 1 0 19 OxNN start pause c3 PAUSE RELEASE Oxff 1 0 1 OxNN release pause c3 2 10 16 OxNN FF play c3 2 0 OxNN start FR play c3 R RELEASE loxtr 1 0Oxld none OxNN c3 BOOKMARK SET 2 0 1 0 00 OxNN bookmark point c3 BOOKMARK CLEAR 0 2 0 1 0 01 OxNN clear bookmark point cl POSITION PLAY 7 0 20 OxNN set position and play cl ISELECT MODE 2 10 30 OxNN mode TRACK UP Oxff 0 31 OxNN up and play c3 TRACK DOWN Oxff 0x32 OxNN track down and play c3 DIR UP Oxff 0 33 OxNN up and play c3 DIR DOWN Oxff 0 34
347. ommand 60H Table 20 9 shows RAM loader mode process Table 20 9 RAM Loader Mode Process Transfer Data from T5CL8 to External Controller Transfer Data from External Control ler to T5CL8 Baud Rate Transfer Bytes 1st byte Matching data 5AH 2nd byte 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error Nothing transmitted 3rd byte Baud rate modification data See Table 20 4 4th byte 9600 bps 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 5th byte Operation command data 60H Modified baud 6th byte Modified baud OK Echo back data 60H Error A1H x 3 A3H x 3 63H x 3 Note 1 7th byte 8th byte Password count storage address bit 15 to 08 Note 4 Modified baud OK Nothing transmitted Error Nothing transmitted 9th byte 10th byte Modified baud OK Nothing transmitted Error Nothing transmitted Password count storage address bit 07 to 00 Note 4 Modified baud OK Nothing transmitted Error Nothing transmitted 11th byte 12th byte Password comparison start address bit 15 to 08 Note 4 13th byte 14th byte Modified baud OK Nothing transmitted Error Nothing transmitted Password comparison start address bit 07 to 00 Note 4 15th byte Password string Note 5 Modified baud m th byte OK Nothing transmitted Error
348. on 0 monitor 1 Detect GENERAL CALL 0 Lastreceive bit is 0 L Last received bit monitor 1 Last receiv bit is 1 16 5 1 Acknowledgement mode specification M 1 T 1 Bus free Bus status monitor 1 Bus busy 1 1 AA 1 Interrupt service requests sta Requesting interrupt service tus monitor Releasing interrupt service request Read ST RX BB AL S RB 16 5 1 1 Acknowledgment mode ACK 1 To set the device as an acknowledgment mode the ACK Bit4 in SBICRA should be set to 1 When a serial bus interface circuit is a master mode an additional clock pulse is generated for an acknowledge signal In a slave mode a clock is counted for the acknowledge signal In the master transmitter mode the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle In the master receiver mode the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle In a slave mode when a received slave address matches to a slave address which is set to the 2 or when a GENERAL CALL is received the SDA pin is set to low level generating an acknowledge sig nal After the matching of slave address or the detection of GENERAL CALL in the transmitter the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle In a receiver the SDA pin is set to lo
349. on in the event counter mode the new value programmed in TTREGj is in effect imme diately after the programming Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 3 4 10 3 7 16 Bit Pulse Width Modulation PWM Output Mode TC3 and 4 This mode is used to generate a pulse width modulated PWM signals with up to 16 bits of resolution The TimerCounter 3 and 4 are cascadable to form the 16 bit PWM signal generator The counter counts up using the internal clock or external clock When a match between the up counter and the timer register PWREG3 PWREGA value is detected the logic level output from the timer F F4 is switched to the opposite state The counter continues counting The logic level output from the timer F F4 is switched to the opposite state again by the counter overflow and the counter is cleared The INTTC4 interrupt is generated at this time Two machine cycles are required for the high or low level pulse input to the TC3 pin Therefore a maxi mum frequency to be supplied is fc 2 Hz in the NORMAL1 2 IDLE1 2 mode and fs 2 to in the SLOW1 2 or SLEEP 1 2 mode Since the initial value can be set to the timer F F4 by TC4CR lt TFF4 gt positive and negative pulses can be generated Upon reset the timer F F4 is cleared to 0 The logic level output from the PWM4 pin is the opposite to the timer F F4 logic level Since PWREG4 and 3 in the PWM mode ar
350. ontroller inside and one TOSHIBA audio DSP which integrated MP3 WMA decoder and CD servo controller Term and Abbreviation T5CJ3 7G28 FM is also called BlackPepper3 in this specification BlackPepper3 is a term in software scope T5CJ3 7G28 FM is the masking product of BlackPepper3 is abbreviation of BlackPepper3 2 System feature Compatiable disc type Audio CD support sigle session CD ROM support single session or multi session MIX CD support single session first track is data track and other tracks are audio track CD EXTRA support first session is audio session second session is data session CD ROM decoder Format Compliant with ISO9660 level 1 and 2 mode 1 and 2 form 1 PVD SVD management Analyze the PVD and SVD and stores folder and file information in SRAM Dir File maximum number 1024 B14 or 512 B13 Dir maximum number 511 B14 or 256 B13 Folder names and file names Level1 2 Remeo Joliet are supported Folder name File name length 64bytes maximum USB and SD file management Support format type FAT12 FAT16 FAT32 Long file name support VFAT Maximum cluster size 64KB Maximum sector size 4 Max folder number support 128 Max file in one folder 512 file in device 65535 Max directory depth 8 Folder name File name length 64bytes maximum ID3 title artist album The max number of bytes of title artist album is 30 30 30 MP3 decoder File 1 2 2 5 Layer3
351. or auto capture disable Read the capture value in a capture enabled condi tion Since the up counter value is captured into TCIDRB by the source clock of up counter after setting lt gt to 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading TCIDRB for the first time Timer start rising edge TC1S 10 Match detect Counter clear Figure 8 4 Event Counter Mode Timing Chart Table 8 2 Input Pulse Width to TC1 Pin Minimum Pulse Width s NORMAL 1 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 Mode Low going Page 84 05 8 3 4 Window Mode In the window mode the up counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the pin window pulse and the internal source clock Either the positive logic count up during high going pulse or negative logic count up during low going pulse can be selected When a match between the up counter and the TC1DRA value is detected an interrupt is generated and the up counter is cleared Define the window pulse to the frequency which is sufficiently lower than the internal source clock pro grammed with lt gt Count start Count stop Count start Timer start Y TC1 pin input Internal clock Counter TC1DRA INTTC1 Match detect Counter clear interrput request a Positive logic TC1S 10
352. or the crystal X202 should be 32 768KHZ 9 To check Panel LED 5 voltage should be normal To check whether the volume knob is turn to the minimum position b To check whether the unit is at MUTE mode press SOURCE button and check whether it is effective of the input sound source c To check whether the connection of 8PIN audio output wire of ISO connector is correct wrong connection or short circuit to the ground will caused the protection of the power amplifier no NO audio output voltage output To check the circuit of power amplifier 10501 LV47004 and VOL 403 PT7313E e To check the normal voltage of 22 PIN MUTE of power amplifier IC501 LV47004 normally should be 4V f To check the voltage of control PIN SDA SCL the 27 28pin of audio processor 403 PT7313E should be 3V3 a To check the antenna of the tuner b To check whether the strength of then input signal of the tuner is too weak c To check the voltage of the 7 pin VDD of the tuner should be 3V3 NES 1 d To check the voltage of the 10 pin RES of the tuner should adio abnorma 3V6 the 11 pin CLK should be 3V1 the 12 pin date should be 2V8 To check the oscillation frequence of crystal 001 of the tuner should be 32 768KHZ f To check the L output voltage of the 5 pin of tuner should be 1V5 the 6 pin R output voltage should be 1V5 1 failure phenomena failure cause remark a To check
353. ore data to address 98H Page 231 19 19 4 Access to the Flash Memory Area T5CL8 Page 232 TOSHIBA 20 Serial PROM Mode 20 1 Outline The T5CL8 has a 2048 byte BOOTROM Mask ROM for programming to flash memory The BOOTROM is available in the serial PROM mode and controlled by TEST BOOT and RESET pins Communica tion is performed via UART The serial PROM mode has seven types of operating mode Flash memory writing RAM loader Flash memory SUM output Product ID code output Flash memory status output Flash memory eras ing and Flash memory security program setting Memory address mapping in the serial PROM mode differs from that in the MCU mode Figure 20 1 shows memory address mapping in the serial PROM mode Table 20 1 Operating Range in the Serial PROM Mode Parameter Power supply High frequency Note Note Though included in above operating range some of high frequencies are not supported in the serial PROM mode For details refer to Table 20 5 20 2 Memory Mapping The Figure 20 1 shows memory mapping in the Serial PROM mode and MCU mode In the serial PROM mode the BOOTROM Mask ROM is mapped in addresses from 7800H to 7FFFH The flash memory is divided into two banks for mapping Therefore when the RAM loader mode 60H is used it is required to specify the flash memory address according to Figure 20 1 For detail of banks and control register refer to t
354. ort t is function ust in stop state doesn t operation it in any play state of data field must be SEL FOLDER2 05xxxx01 Select a folder but ust get its inside local file number local start file number informaiton t doesnt issue a folder analysis process Result returns at once recei ed t e command Support t is function in any mode as long as reading process is finis ed and play a aiable of data field must be 50 TOSHIBA T5CJ3 7G28 F M Specification SEL FILE1 0x06 Select a file in t e folder specified by S R command fter folder analysis process is finis ed getting any files file name is a ailable Support t is function ust in stop state doesn t operation it in any play state ile number as parameters is relati e file number in t e folder of S R command specified SEL FILE2 0x07 Select a file to get t e folder number t at t is file locates and t is folder s inside information includes local total file number and start file number Support t is function in any mode as long as reading process is finis ed and play a aiable ile number as parameters is absoluted file number in t e de ice lac S FILE NAME SELECTED 0xcO Return file name of S command DIR NAME SELECTED 0xc1 Return folder name of S R command DIR INSIDE INFO 0xc2 Return folder inside info local total file and start file of S R S R command DIR INFO OF FILE 0xc3 Return folder number a
355. ounter and window modes And if fc or fs is selected as the source clock in timer mode when switching the timer mode from SLOWI to NORMAL2 the timer counter2 can generate warm up time until the oscillator is stable 9 3 1 Timer mode In this mode the internal clock is used for counting up The contents of TC2DR are compared with the con tents of up counter If a match is found a timer counter 2 interrupt INTTC2 is generated and the counter is cleared Counting up is resumed after the counter 15 cleared When fc is selected for source clock at SLOW2 mode lower 11 bits of TC2DR are ignored and generated a interrupt by matching upper 5 bits only Though in this situation it is necessary to set TC2DRH only Table 9 1 Source Clock Internal clock for Timer Counter2 at fc 16 MHz DV7CK 0 ae NORMAL1 2 IDLE1 2 mode SLOW1 2 mode SLEEP1 2 mode K DV7CK 0 DV7CK 1 Maxi Maxi Maximum Time Set Maximum Time Set Resolu mum Resolu mum Resolution Resolution s A ting ting tion Time tion Time Setting Setting 524 29 ms 9 54 h 1 s 18 2 h 1 s 1 8 512 0 ms 33 55 s 0 98 ms 1 07 min 0 98 ms 0 98 ms 16 0 ms 1 05 s 16 0 ms 1 05 s 0 5 ms 32 77 ms 0 5 ms 32 77 ms 62 5 ns 30 52 ms 2 s 30 52 ms 2 s Note When fc is selected as the source clock timer mode it is used at warm up for switching from SLOW1 mode to NORMAL2 mode Example Sets the timer m
356. ow frequency clock Hz Don t care Note 4 Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed Note 5 As the hardware becomes STOP mode under OUTEN 0 input value is fixed to 0 therefore it may cause external interrupt request on account of falling edge Note 6 When the key on wakeup is used RELM should be set to 1 Note 7 Port P20 is used as STOP pin Therefore when stop mode is started OUTEN does not affect to P20 and P20 becomes High Z mode Note 8 The warmig up time should be set correctly for using oscillator System C pica ontrol Register 2 Note 1 0 Turn off oscillation XTEN Low frequency oscillator control 1 Turn on oscillation Main system clock select Write main system clock moni tor Read 0 High frequency clock NORMAL 1 NORMAL2 IDLE1 IDLE2 1 Low frequency clock SLOW1 SLOW2 SLEEP 1 SLEEP2 0 T ff oscillati XEN High frequency oscillator control d E SA 1 Turn on oscillation R W 0 Feeding clock to all peripherals from TG TGHALT modes 1 Stop feeding clock to peripherals except TBT from TG TG control IDLEO and SLEEPO Start IDLEO and SLEEPO modes IDLE CPU and watchdog timer control 0 CPU and watchdog timer remain active IDLE1 2 and SLEEP1 2 modes 1 CPU and watchdog timer are stopped Start IDLE1 2 and SLEEP1 2 modes R W A reset is applied if both XEN and XTEN are cleared to 0 XEN is cleared to 0
357. posite to the timer F Fj logic level is output from the PDOj pin An arbitrary value can be set to the timer F Fj by TCjCR lt TFFj gt Upon reset the timer F Fj value is initialized to 0 To use the programmable divider output set the output latch of the I O port to 1 Page 106 05 Ls Example Generating 1024 Hz pulse using fc 16 0 MHz Setting port LD TTREG4 1 1024 27 2 LD 00010001B Sets the operating clock to fc 2 and 8 bit PDO mode LD 00011001B Starts 4 Note 1 In the programmable divider output mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the programmable divider output mode the new value programmed in TTREGj is in effect immediately after programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 2 When the timer is stopped during PDO output the PDOj pin holds the output status when the timer is Stopped To change the output status program TCjCR lt TFFj gt after the timer is stopped Do not change the TCjCR lt TFFj gt setting upon stopping of the timer Example Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the PDOj pin to the high level 3 3 4 Page 107 10 8 Bit TimerCounter TC3 4 10 1 Con
358. pports CLV modes for up to x2 speed Supporting automatic loop gain offset and balance adjustments for focus and tracking servo sections Built in RF gain automatic adjustment circuit Built in digital equalizer Built in digital equalizer coefficient RAM supporting various pickup types Built in focus and tracking servo control circuits Supports all search control modes thus realizing high speed stable searches Uses speed controlled lens kick and feed kick Built in AFC and APC circuits for disc motor CLV servo control Built in anti defect and anti shock circuits Support Stepper Motor Audio DSP section e Incorporating firmware for processing signals in various audio compression formats such as MP3 WMA and MPEG4 AAC Incorporating 1 Mbit of SRAM 128 Kwords 8 bits Operation Clock Built in PLL for generating clock pulses for operation of the DSP block any frequency can be specified for clock pulses to be generated Operating speed 87 5MIPS DSP block having the following specifications Operation block 24 bits x 24 bits 51 bit multiplier and 51 bit ALU Data buss 24 bits x 3 Data RAM 12 Kwords Coefficient ROM 44 Kwords Program RAM 1 Kwords Program ROM 36 Kwords Audio Input port 2 Supports 3line PCM and 125 32 48 6416 Audio Output port 1 Support 3 line PCM and 125 32 48 64fs SPDIF Output Audio DAC section Supports externally input Ai signals Built in 24 bit FIR digit
359. r T5CL8 Page 220 05 me 18 Key on Wakeup KWU In the 5 8 the STOP mode is released by not only P20 INTS STOP pin but also four STOPO to STOP3 pins When the STOP mode is released by STOPO to STOP3 pins the STOP pin needs to be used In details refer to the following section 18 2 Control 18 1 Configuration STOP mode STOP release signal 1 Release STOPO STOP1 STOP2 STOP3 STOPCR OF9FH Figure 18 1 Key on Wakeup Circuit 18 2 Control STOPO to STOP3 pins can controlled by Key on Wakeup Control Register STOPCR It can be configured as enable disable in 1 bit unit When those pins are used for STOP mode release configure corresponding I O pins to input mode by I O port register beforehand Key on Wakeup Control Register STOPCR 7 6 5 4 3 2 1 0 STOP3 STOP2 STOP1 STOPO Initial value 0000 STOP3 0 Disable 1 Enable STOP2 0 Disable 1 Enable STOP4 0 Disable 1 Enable 0 Disable 1 Enable 18 3 Function Stop mode can be entered by setting up the System Control Register SYSCR1 and can be exited by detecting the L level on STOPO to STOP3 pins which are enabled by STOPCR for releasing STOP mode Notel Page 221 18 Wakeup KWU 18 3 Function T5CL8 Also each level of the STOPO to STOP3 pins can be confirmed by reading corresponding I O port data register check all STOPO to STOP3 pins H that is enabled by STO
360. r Therfore to use AD converter again set the ADCCR1 newly after returning to NORMAL NORMAL2 mode Page 212 TOSHIBA AD Converter Control Register 2 T5CL8 ADCCR2 7 6 5 4 3 2 1 0 001DH IREFON ACK o Initial value 0 000 0 Connected only during AD conversion 1 Always connected IREFON DA converter Ladder resistor connection control AD conversion time select Refer to the following table about the con version time 39 fc Reserved 78 fc 156 fc 312 fc 101 624 fc 110 1248 fc 111 Reserved Note 1 Always set in ADCCR2 to 0 and set bit4 in ADCCR2 to 1 Note 2 When a read instruction for ADCCR2 bit6 to 7 in ADCCR2 read in as undefined data Note 3 After STOP or SLOW SLEEP mode are started AD converter control register2 ADCCR2 is all initialized and data be written in this register Therfore to use AD converter again set the ADCCR2 newly after returning to NORMAL 1 or NORMAL2 mode Table 17 1 ACK setting and Conversion time Condition 16 MHz 8 MHz 4 MHz 2MHz 10 MHz 5 MHz ACK Conversion 25 MHz 15 6 Reserved CL TL Lose ne reme me 312 us 62 4 us 124 8 us Reserved Note 1 Setting for in the above table inhibited High Frequency oscillation clock Hz Note 2 Set conversion time setting should be kept more than the following time by Analog reference voltage VAREF VAREF
361. r deer ed E ers 221 19 Flash Memory 191 Flash Memory 224 19 1 1 Flash Memory Command Sequence Execution Control FLSCR FLSMD 224 19 1 2 Flash Memory Bank Select Control lt gt 224 19 2 Command Sequences EUN AR PR CEN 225 19521 teens ceteri de M 225 19 2 2 Sector Erase 4 kbyte Erase 1 1 1 1 1 1 42 42 4 0 etin netten teet ast eine se tane se eine seta a 225 19 2 87 Erase EFaS8 ey Eee eee oret ee eger ee eite ER COP oe REA 226 19 2 4 Product ID Entry 19 2 5 Product eren 19 26 5 Program eee eee Ce du e REPE A ep T 226 19 8 109916 i osos epe DR VR UE VES UR a 227 19 4 Access to the Flash Memory 228 19 4 1 Flash Memory Control the Serial PROM 228 19 4 1 1 How to write to the flash memory by executing the control program in the RAM area in the RAM loader mode within the serial PROM mode 19 4 2 Flash Memory Control in the MCU 230 19 4 2 1 How to w
362. r folder analysis folder name returns Don t send any command before folder analysis is finished Select a file and read its file name The file number is relative file number of this folder By this method after a folder analysis is finished you can send command to get all of file name in this folder 5 ecially don t send a ne command after 5 D returns TOSHIBA T5CJ3 7G28 F M Specification 6 18 3 Select a folder to get folder inside information ommand se uence HOST BP3 SEL FOLDER2 05xxxx01 INSIDE INFO c2 ote any selection out of selecting available ill cause BP3 return a S T command orS D S D If selection is out range of total folder number in device S T returns for S command if selection is out range of dir local total file number S T returns for S command if Selection is out range of total file number in device S returns 6 19 Bookmark setting and play Blac Pe er3has boo mar function irst set boo mar and then e ecuate boo mar lay AD command can clear boo mar setting Thant mean if doing mode s itch boo mar setting ill disa ear automatically Please be noted that if current stream information is un no boo mar setting ill fail n this occasion host need try again after aiting for some time elevant commands are listed bello ST Blac Pe er3 BOOKMARK SET 0x1e00 Setaboo mar hen laying BOOKMARK CLEAR 0x1e01 lear the boo mar BOOKMARK PLAY 0x3c Start boo mar laying
363. range of 6 dB e Built in RF equalizer correction circuit e Built in focus error signal and tracking error signal circuits e Built in signal generation circuit for track counting RFRP e Built in circuit for generating a sub beam addition signal or an RFDC signal whichever is selected as a defect detection signal Note that the RFDC signal is supported only when the RFO signal is positive e Supports DC offset correction functions for focus tracking and RF sections e Supports both CD DA and CD R RW modes e Supports a voltage output type pickup 1 2010 01 12 TOSHIBA TC94B14MFG Digital servo processor section Capable of decoding text data CD TEXT mode 4 Capable of performing sync pattern detection sync signal protection and interpolation securely Built in EFM demodulation circuit and sub code demodulation circuit Has a jitter absorbing capacity be switched among 6 frames and 22 frames Capable of making double C1 correction and quadruple C2 correction using CIRC correction logical expressions Built in 64Kbit RAM Built in digital attenuators Enables audio outputs to be switched among 32 fs 48 fs and 64 fs Capable of reading sub code Q data at any time and outputting it in synchronization with audio data Built in data slice circuit analog digital slicing and compensation circuit Built in analog PLL with an adjustment free VCO Uses an active wide range PLL system Supports variable speed playback Su
364. rating CD Head Amplifier Compression AudioDecoder and 16Mbit DRAM for ESP Electrical Shock Proof function The TC94B14MFG is a single chip processor which incorporates the following functions CD Head amplifier EFM synchronous signal separation protection and interpolation EFM demodulation error correction microcontroller interface servo use digital equalizer and servo control circuit multi bit DA converter and Compression audio a Le decoder firmware such as for WMA MPEG4 AAC and 16Mbit LQFP80 P 1212 0 50F DRAM for ESP The TC94B14MFG makes it possible to configure a CD MP3 Weight 0 69 typ player with ESP quite easily with an adjustment free basis Features General Common to all sections Operation Supply Voltage CD I O DAC 3 0 3 6V DSP Logic 1MbitSRAM 1 4 1 6V Stand By function Hold the data stores in 1MbitSRAM supplying the Voltage only to 1MbitSRAM Operation Temperature 20 70 C e Package LQFP 80 Pin pitch 0 5 mm Micro controller interface 4bit parallel interface 6 lines CMOS silicon Monolithic LSI Head amplifier section e CD DA R RW up to x2 speed e Built in reference voltage VRO generation circuit e Built in APC auto laser power control circuit e Built in RF signal generation circuit e Enables the polarity of the offset voltage correction of the RF signal to be switched e Built in AGC auto gain control circuit for the RF signal gain adjustment
365. rature Topr 40 to 85 Page 267 22 Electrical Characteristics 22 1 Absolute Maximum Ratings T5CL8 22 2 Operating Conditions The Operating Conditions shows the conditions under which the device be used in order for it to operate normally while maitaining its quality If the device is used outside the range of Operating Conditions power supply voltage operating temperature range or AC DC rated values it may operate erratically Therefore when designing your application equipment always make sure its intended working conditions will not exceed the range of Operating Conditions 22 2 1 MCU mode Flash Programming or erasing Vss 0 V 10 to 40 Except hysteresis input Vpp x 0 70 Input high level 2 4 5 V Vpp Vin2 Hysteresis input input Von x 0 75 x 0 75 hysteresis input x0 30 x 0 30 Input low level Vpp2 4 5 Hysteresis input E x 0 25 Clock frequency fe xN xor ______ XIN _______ XOUT 22 2 2 MCU mode Except Flash Programming or erasing Vss 0 V 40 to 85 C NORMAL1 2 modes 1e 18 Mig IDLEO 1 2 modes fc 8 MHz NORMAL41 2 modes Supply voltage IDLEO 1 2 modes 55 V SLOW1 2 modes fs 32 768 KH STOP mode mode Except hysteresis input Vpp x 0 70 Vpp 2 4 5 V Input high level Hysteresis input Vpp x 0 75 Vpp Except hysteresis input Vpp x 0 30 p24 5V Input low level Hysteresis input Vpp x 0 25 XIN XOUT 1 0 MHz C
366. re Cancel interrupt service request Cancel interrupt service request Port mode Serial bus interface output disable Serial bus interface operating Reserved mode selection 12 bus mode Reserved SWRST1 SWRSTO Note 1 Switch a mode to port after confirming that the bus is free Note 2 Switch a mode to bus mode after confiming that the port is high level Note 3 SBICRB has write only register and must not be used with any of read modify write instructions such as bit manipulation etc Note 4 When the SWRST Bit1 0 SBICRB is written to 10 01 in bus mode software reset is occurred In this case the SBICRA I2CAR SBISRA and SBISRB registers are initialized and the bits of SBICRB except the Bit3 2 in SBI CRB are also initialized Serial Bus Interface Status Register A SBISRA 7 6 5 4 3 2 1 0 OF90H SWRMON Initial value 1 0 During software reset Read SWRMON Software reset monitor 1 Initial value only Serial Bus Interface Status Register B SBISRB 7 6 5 4 3 2 1 0 PERS Page 198 05 ig Master slave selection status 0 Slave monitor Master Transmitter receiver selection 0 Receiver status monitor Transmitter 0 0 0 only Arbitration lost detection monitor Arbitration lost detected Slave address match detection 0 monitor Detect slave address match or GENERAL CALL ADO GENERAL CALL detecti
367. register settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 3 Table 10 1 Operating Mode and Selectable Source Clock NORMAL 1 2 and IDLE1 2 Modes iid input pin input bit timer S D Oven Connie bit PDO gt Bug LC _ RW guum ER co rese ese Note 1 For 16 bit operations 16 bit timer event counter warm up counter 16 bit PWM 16 bit PPG set its source clock lower bit TC3CK Note 2 O Available source clock Table 10 2 Operating Mode and Selectable Source Clock SLOW1 2 and SLEEP 1 2 Modes input pin input Clo KETTE RE EN E epe Teen Note1 For 16 bit operations 16 bit timer event counter warm up counter 16 bit PWM and 16 bit PPG set its source clock on lower bit TC3CK Note2 Av
368. release ommand sequence play pause play urrent is play status HOST BP3 PAUSE 19 PAUSE STATUS PAUSE RELEASE 1A PAUSE RELEASE PLAY STATUS ase FF play urrent is play status HOST BP3 FF STATUS FF FR RELEASE 1D FF RELEASE PLAY STATUS ase3 play F play 37 TOSHIBA T5CJ3 7G28 F M Specification urrent is play status HOST BP3 FR STATUS FF FR RELEASE 1D FR RELEASE PLAY STATUS ase pause FF pause urrent is pause status HOST BP3 FF STATUS FF FR RELEASE 1D FF RELEASE PAUSE STATUS ase pause pause urrent is pause status 38 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 FR 1C FR STATUS FF FR RELEASE 1D FR RELEASE PAUSE STATUS 6 9 Stop In play pause FF F status send T P command start stop process returns T P finally D mode pick up moving inner or not can be specified elevant commands are listed bellow T BlackPepper3 STOP 0x18 There is one byte in data field indicate need pick up move to inner or not But this indication is invalid for Bor D mode BlackPepper3 T PLAY STATUS 0x84 0x00 PLAY STATUS 0x01 STOP STATUS Ox0 PAUSE STATUS 0x03 PAUSE RELEASE Ox0 0 0 FFSTATUS 0x0 0 0 FR STATUS OxOd FF release or FR release ommand sequence Case 1 current is play status HOST BP3 pecify pick up inner moving STOP 0x18 STOP STAT
369. reliability of its products Nevertheless semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress It is the responsibility of the buyer when utilizing TOSHIBA products to comply with the standards of safety in making a safe design for the entire system and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life bodily injury or damage to property In developing your designs please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications Also please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices or TOSHIBA Semiconductor Reliability Handbook etc 021023 The TOSHIBA products listed in this document are intended for usage in general electronics applications computer personal equipment office equipment measuring equipment industrial robotics domestic appliances etc These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may cause loss of human life or bodily injury Unintended Usage Unintended Usage include atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments
370. requests next data In the slave transmitter mode 1 word data is transmitted A serial bus interface circuit loses arbitra tion when transmitting a slave address AS Read the SBIDBR for setting the PIN to 1 Reading dummy data or write 1 to the PIN And receives a slave address of which the value of the direction bit sent from another master is or receives a GENERAL CALL A serial bus interface circuit loses arbitra A serial bus interface circuit is changed to slave mode To clear AL to 0 read the SBIDBR or write the data to SBIDBR tion when transmitting a slave address or data And terminates transferring word data In the slave receiver mode a serial bus interface circuit receives a slave address Read the SBIDBR for setting the PIN to of which the value of the direction bit sent from the master is 0 or receives GEN ERAL CALL In the slave receiver mode a serial bus 1 Reading dummy data or write 1 to the PIN Set the number of bits in 1 word to the BC interface circuit terminates receiving of 1 and read received data from the SBIDBR word data Note In the slave mode if the slave address set in I2CAR is 00H a START Byte 01H in bus standard is recived the device detects slave address match and the TRX is set to 1 16 6 4 Stop condition generation When the BB is 1 a sequence of generating a stop condition is starte
371. reset the PODR is initialized to 1 and the POOUTCR is initialized to 0 It can be selected whether output circuit of PO port is a C MOS output or a sink open drain individually by setting POOUTCR When a corresponding bit of POOUTCR is 0 the output circuit is selected to a sink open drain and when a corresponding bit of POOUTCR is 1 the output circuit 1s selected to a C MOS output When used as an input port an external interrupt input a serial interface input and an UART input the correspond ing output control POOUTCR should be set to 0 after PODR is set to 1 PO port output latch PODR and PO port terminal input POPRD are located on their respective address When read the output latch data the PODR should be read When read the terminal input data the POPRD register should be read Table 5 1 Register Programming for Multi function Ports 7 to Programmed Value Function PODR POOUTCR Port input external interrupt input serial inter face input or UART input Serial PROM mode cotrol input Programming for each applica tions STOP OUTEN POOUTCRI POOUTCRi input Data input POPRD Output latch read PODR Data output PODR Output latch Control output Control input Note i 7 to 0 Figure 5 2 Port 0 POOUTCR Page 50 TOSHIBA 7 6 5 4 3 2 1 0 PODR POS P04 P03 P02 P01 RAN 2 5 01 INT4
372. rite to the flash memory by executing a user write control program in the RAM area in the MCU mode 20 Serial PROM Mode 2071 UUUlBe Sg SS M a occu Sh ile o esM Roe ds 233 20 2 Memory 233 20 8 Serial PROM 234 20 3 1 Serial PROM Mode Control PINS eee ertet eies eaaa asies 234 20 3 2 Pin Function webs 20 3 8 Example Connection for On Board 235 20 3 4 Activating the Serial PROM 236 20 4 Interface Specifications for 237 20 5 Operation 239 20 6 Operation 239 20 6 1 Flash Memory Erasing Mode Operating command 241 20 6 2 Flash Memory Writing Mode Operation command 30H 20 6 3 RAM Loader Mode Operation Command 60 vi 20 6 4 Flash Memory SUM Output Mode Operation Command 9 248 20 6 5 Product ID Code Output Mode Operation Command 249 20 6 6 Flash Memory Status Output Mode Operation Command
373. rm lack to start a reco ery play from last poston n case of lack epper encounters a un ntended reset rst of all lack epper Il not return R 5 b command agan after lack epper s orkng So 66 TOSHIBA T5CJ3 7G28 F M Specification host s de should detect th s command any t me If host doesn treset lack epper butherece esa command b that tell host lack epper has aun ntended reset If host ant to cont nue play from last nterrupted pos t on host can start reco play process by steps Step reset process Set p ck up select on or transfer ng coff c ent data See chapter Step Selectlast mode Select last ork mode nd atselect ng mode ok See chapter Step Ifselect S orS mode atfor S 5 gongtoR status See chapter Step Start a read process Start read ng de ce ut recommand to use stop not auto play for easy ng programm ng See chapter Step Start reco ery play fter rece ed S S S that mean read ng s fn shed so host can send SI I command to start reco play hen lack go nto play process SII command ncludes bytes parameter hey the same order as SI I ea command bytes data bout ea command see chapter Rele ant commands are sted bello S lack epper POSITION PLAY 0x20 Rough command se uence s bello 67 TOSHIBA T5CJ3 7G28 F M Specification HOST BP3 PICK UP REQUEST b6 Select a p ck up PICK UP SELECT 40 RESET POWER b5 r
374. rn yte data filled with Case 4 track number out of range In this case lac Pepper will not return anythin 6 22CD USB SD mode switch lac Pepper system there are steps need to do when switch mode from one to another Step select the new mode see Step start read process see If switch from CD mode to others additionally please ensure CD is in stop mode In other words if CD is in TOC readin playin state first send STOP command to stop it then start step step outstop see If switch from 5 SD mode to others you also can send STOP command to stop it ut it is not necessary If current stateis S readin or SD readin use STOP command is not ood ecause itta time in this occasion you etter use system off command SYSTEM X f with data x after lac Pepper system off STOP STAT Swill e return ele ant commands are listed ellow OST lac Pepper SYSTEM_ON_OFF 0x4f It di ides into SYSTEM and SYSTEM two commands SYSTEM 0 4 01 System on dont need to use this command SYSTEM OFF 0x4f00 System off use this command ellow se uence 58 TOSHIBA T5CJ3 7G28 F M Specification Case 1 CD to USB or SD CD is stop status HOST BP3 SELECT MODE S30 MODE SEL OK 80 Select a mode READ DEVICE 12 Start read after selecting a mode Case 2 CD to USB or SD CD is reading or playing HOST BP3 STOP 18 Stop disc rotation first
375. rol board Figure 20 3 Example Connection for On Board Writing Note 1 When other parts on the application board effect the UART communication in the serial PROM mode iso late these pins by a jumper or switch Note 2 When the reset control circuit on the application board effects activation of the serial PROM mode isolate the pin by a jumper or switch Note 3 For connection of other pins refer to Table 20 3 Pin Function in the Serial PROM Mode Page 235 20 Serial PROM Mode 20 3 Serial PROM Mode Setting T5CL8 20 3 4 Activating the Serial PROM Mode The following is a procedure to activate the serial PROM mode Figure 20 4 Serial PROM Mode Timing shows a serial PROM mode timing l 2 3 4 5 6 VDD TEST Input RESET Input PROGRAM BOOT RXD1 Input Supply power to the VDD pin Set the RESET pin to low Set the TEST pin and BOOT RXDI pins to high Wait until the power supply and clock oscillation stabilize Set the RESET pin to high Input the matching data 5AH to the BOOT RXDI pin after setup sequence For details of the setup timing refer to 20 15 UART Timing High level setting Setup time for serial PROM mode Rxsup gt gt Matching data input Figure 20 4 Serial PROM Mode Timing Page 236 T5CL8 TOSHIBA 20 4 Interface Specifications for UART The following shows the UART communication format used in the serial PROM mode To perform on board pr
376. rrupt request WDTCR1 lt WDTOUT gt 0 Internal reset 5 86 WDTCR1 lt WDTOUT gt 17 reset occurs Write 4 to WDTCR2 Figure 6 2 Watchdog Timer Interrupt Page 69 6 Watchdog Timer WDT 6 3 Address Tra p T5CL8 6 3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps Watchdog Timer Control Register 1 WDTCR1 7 6 4 3 2 1 0 5 0034H ATAS ATOUT WDTEN WDTT WDTOUT Initial value 11 1001 Select address trap generation in 0 iGenerat n address trap ATAS the internal RAM una 1 Generate address traps After setting ATAS to 1 writing the control code D2H to WDTCR2 is required Write only 0 Int t t ATOUT Select operation at address trap 4 Mn Watchdog Timer Control Register 2 WDTCR2 7 6 5 4 3 2 1 0 0035 Initial value doe Write D2H Enable address trap area selection ATRAP control code Watchdog timer control code 4EH Clear the watchdog timer binary counter WDT clear code and address trap area control B1H Disable the watchdog timer WDT disable code code Others Invalid WDTCR2 6 3 1 Selection of Address Trap in Internal RAM ATAS WDTCRI lt ATAS gt specifies whether or not to generate address traps in the internal RAM area To execute an instruction in the internal RAM area clear lt 5 gt to 0 To enable the WDTCR1 lt ATAS g
377. rrupt vector resulting in malfunc tion of the microcontroller Page 230 TOSHIBA T5CL8 Example After sector erasure EOOOH EFFFH the program in the RAM area writes data to address E000H DI LD LDW LD LD LD LD WDTCR2 4EH WDTCR1 0B101H FLSCR 00111000B 0 555 0 000 HHH Flash Memory Sector Erase Process LD LD LD LD LD LD SLOOP1 LD CMP JR IX 0AAH IY 55H IX 80H IX 0AAH IY 55H HL 30H W HL W HL NZ sLOOP1 HHH Flash Memory Write Process LD LD LD LD SLOOP2 LD CMP JR LD JP 1 IY 55H IX 0AOH HL 3FH W HL W HL NZ sLOOP2 FLSCR 11001000B XXXXH Loop until the same value is read Disable command sequence execution Disable interrupts IMF lt 0 Clear the WDT binary counter Disable the WDT Enable command sequence execution 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5 bus write cycle 6th bus write cycle Loop until the same value is read 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 1000H 3FH Jump to the flash memory area Example This write control program reads data from address F000H and stores it to 98H the RAM area LD LD A 0F000H 98H A Read data from address 000 St
378. ry mapped system and all peripheral control and data transfers are performed through the special function register SFR or the data buffer register DBR The SFR is mapped on address 0000H to 003FH DBR 15 mapped on address OF80H to OFFFH This chapter shows the arrangement of the special function register SFR and data buffer register DBR for TSCL8 4 1 SFR 0000H PODR 0001H P1DR 0002H P2DR 0003H P3DR 0004H P4DR 0005H P5DR 0006H P6DR 0007H P7DR 0008H POOUTCR 0009H P1CR 000 P4OUTCR 000BH POPRD 000CH P2PRD 000DH P3PRD 000EH P4PRD 000 P5PRD 0010H TC1DRAL 0011H TC1DRAH 0012H TC1DRBL 0013H TC1DRBH 0014H TTREG3 0015H TTREG4 0016H TTREGS 0017H TTREG6 0018H PWREG3 0019H PWREG4 001AH 5 001 PWREG6 001CH ADCCR1 001DH ADCCR2 001EH ADCDR2 001FH ADCDR1 0020H SIO1CR 0021H SIO1SR 0022H SIO1RDB SIO1TDB 0023H TC2CR 0024H TC2DRL 0025H TC2DRH Page 45 4 Special Function Register SFR 4 1 SFR T5CL8 Address Read Write 0026H TC1CR 0027H TC3CR 0028H TC4CR 0029H TC5CR 002AH TC6CR 002BH SIO2RDB SIO2TDB 002CH EIRE 002DH Reserved 002EH ILE 002FH Reserved 0030H Reserved 0031H SIO2CR 0032H SIO2SR 0033H Reserved 0034H WDTCR1 0035H W
379. s generated after 51025 lt gt is set to 1 3 Stopping the transmit operation There are two ways for stopping transmits operation The way of clearing 5102 lt 51 5 gt When SIO2CR lt SIOS gt is cleared to 0 transmit operation is stopped after all transfer of the data is finished When transmit operation is finished SIO2SR lt SIOF gt is cleared to 0 and SO2 pin is kept in high level In external clock operation SIO2CR lt SIOS gt must be cleared to 0 before SIO2SR lt SEF gt 15 set to 1 by beginning next transfer The way of setting SIO2CR lt SIOINH gt Transmit operation is stopped immediately after SIO2CR lt SIOINH gt is set to 1 In this case 5102 lt 51 5 gt SIO2SR register SIO2RDB register and SIO2TDB register are ini tialized i Clearing SIOS D i Start shift Start shift Start shift operation y operation operation y x t t Writing transmit Writing transmit Writing transmit data A data B data C Figure 15 6 Example of Internal Clock and MSB Transmit Mode Page 184 05 Hn Writing transmit Clearing SIOS SIO2CR lt SIOS gt i i 1 1 51025 lt 5 gt Start shift Start shift i Start shift y operation 1 SIO2SR lt SEF g
380. s held at L level for at least 3 machine cycles 12 fc s with the power supply volt age within the operating voltage range and oscillation stable a reset is applied and the internal state is initial ized When the RESET pin input goes high the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2 15 Reset Circuit Page31 2 Operational Description 2 3 Reset Circuit T5CL8 2 3 2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on chip RAM when WDTCR1 lt ATAS gt is set to 1 DBR or the SFR area address trap reset will be generated The reset time is maximum 24 fc s 1 5ps at 16 0 MHz Note The operating mode under address trapped is alternative of reset or interrupt The address trap area is alter native Instruction JP a Reset release X Instruction at address r execution Address trap is occurred 1 Internal reset 1 to 12 fc s 16 fc s maximum 24 fc s Note 1 Address is in the SFR DBR or on chip RAM WDTCR1 lt ATAS gt 1 space Note 2 During reset release reset vector is read out and an instruction at address is fetched and deco
381. s occurring as a result of noncompliance with applicable laws and regulations 30 2010 01 12
382. se to the pin Two machine cycles are required for the low or high level pulse input to the pin Therefore a maximum frequency to be supplied is fc 2 Hz in the NORMALI 2 IDLE1 2 mode and 5 24 Hz in the SLOW1 2 SLEEPI 2 mode Note 1 In the event counter mode fix TCjCR TFFj to 0 If not fixed the PWMj and PPGj pins may output pulses Note 2 In the event counter mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the event counter mode the new value programmed in TTREGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 3 4 TC4CR lt TC4S gt 1 1 TC4 pin input 1 1 Counter 0 4 X n Match detect clear Figure 10 3 8 Bit Event Counter Mode Timing Chart TC4 10 3 3 8 Bit Programmable Divider Output PDO Mode TC3 4 This mode is used to generate a pulse with a 50 duty cycle from the pin In the PDO mode the up counter counts up using the internal clock When a match between the up counter and the value is detected the logic level output from the pin is switched to the opposite state and the up counter is cleared The INTTC interrupt request is generated at the time The logic state op
383. sed 0x04 0x07 FF mode 0x04 FF normal speed 0x05 FF high speed PLAY STATUS 0x84 byte 0 0x06 FF normal speed mute on control 0x07 FF high speed mute on control 0x08 0x0b FR mode 0x08 FR normal speed 0x09 FR high speed 0 0 FR normal speed mute on control Ox0b FR high speed mute on control 0 0 FF FR mode is released 0x00 mute on MUTE STATUS 0x8c byte 0 0x01 mute off 0x00 system is off SYS ON OFF STATUS 0x8d byte 0 0 01 system is on CD TOC INFO 0x90 byte 0 first track number of CD byte 1 final track number of CD byte 2 disc all time minute of CD 21 TOSHIBA T5CJ3 7G28 F M Specification byte 3 disc all time second of CD TTL FILE DIR NUMBER 0x94 byte 0 USB SD CD ROM mixed disc total folder number high byte byte 1 USB SD CD ROM mixed disc total folder number low byte byte 2 USB SD CD ROM mixed disc total file number high byte 3 USB SD CD ROM mixed disc total file number low byte mp3 it is mpeg version value PLAY STREAM INFO 0x97 byte 0 wma it is bitrate high byte mp3 it is bitrate value byte 1 wma it is bitrate low byte byte 2 mp3 wma it is sample frequency value PLAY FILE TYPE 0x99 byte 0 0x01 mp3 0x02 wma 0x03 audio track 0x04 data track PLAY CD TRACK INDEX 0x9f byte 0 track index number PLAY FILE DIR NUMBER 0xa0 byte 0 playing file number
384. st When the slave PIN keeps 1 PIN is not cleared to 0 address doesn t match the value set by I2CAR the PIN keeps 1 When an INTSBI interrupt request occurs the PIN bit 4 in the SBICRB is reset and the SCL pin is set to low level Either reading or writing from or to the SBIDBR or setting the PIN to 1 releases the SCL pin after taking tj ow Page 207 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 Check the AL in the SBISRB the Bit6 in the SBISRB the AAS Bit2 in the SBISRB and the ADO Bitl in the SBISRB and implements processes according to conditions listed in Table 16 4 Operation in the Slave Mode Table 16 4 Operation in the Slave Mode A serial bus interface circuit loses arbitra tion when transmitting a slave address And receives a slave address of which the value of the direction bit sent from another master is 1 Set the number of bits in 1 word to the BC and write transmitted data to the SBIDBR In the slave receiver mode a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is 1 Test the LRB If the LRB is set to 1 set the PIN to 1 since the receiver does not request next data Then clear the TRX to 0 to release the bus If the is set to 0 set the number of bits in 1 word to the BC and write transmitted data to the SBIDBR since the receiver
385. stable with the voltage on each power supply pin risen to a level within the rated range Once crystal oscillation is stable keep RST low for another 10 or more crystal oscillation cycles before driving RST high To prevent the undefined pin states from affecting the servo circuitry or any other mechanical blocks in the system appropriate measures should be taken such as using a driver IC supporting a standby feature to place the system in standby mode before RST is driven high Note 3 Attach bypass capacitors of 0 1uF and 10uF between VDD pins and VSS pins to reduce noise from power supply lines Place the bypass capacitors as close to the device pins as possible 8 2010 01 12 TOSHIBA TC94B14MFG 1 2 Pin Assinment Table 1 Audio DSP Audio DSP Pin No Symbol AUDIO 53 0 0 E 54 Pio1 Pio1 ST REQ ES 55 Pio2 Pio2 GATE 56 Pio3 Pio3 DoUT B B 57 Pio4 Pio4 AiN e 58 Pio5 5 BCKi B 5 59 Pio6 Pio6 m LRCKi md 60 Pio7 Pio7 IRQ ZDET FS 33 DoUT Pio8 DoUT 34 AoUT Pio9 AoUT 35 Pio10 BCKo 36 LRCKo Pio11 LRCKo 37 CDMONO Pio12 AoUT AiN2 ZDET See 2 Priority on 38 CDMON1 Pio13 BCKo BCKi2 ZDET CDMON 39 CDMON2 Pio14 LRCKo LRCKi2 ZDET 40 CDMON3 ZDET
386. status Y Read stop status Y Send stop Reset status Pd USB SD command Y Stop stat Busy 0 command ived Ready Send stop Send system off command stop YES status exit Stop status Y Send command 0x30 ready status read method Stop after read Recovery play after read Auto play after read Resume play y y y Send command Send command Send command Send command 0x1200 or 0x1280 0x1200 or 0x1280 0x1201 or 0x1281 0x136 Stop stat NO Y command Y Busy 0 eceived 0 0 YES Send command 0x20 0 Y Y 76 TOSHIBA T5CJ3 7G28 F M Specification 7 3 Play track change up down dir up dir down flow 0 received Clear last play information store file number dir number and dir inside info 0x99 command received CDD type No wait YES exit Send command get dir name 8004 Dir name data received No wait Send command get ID3 artist 8001 NO command wes Store artist content Send command get ID3 album 8002 NO Send command Send command get file name 8003 received No wait Send command get ID3 title 8000 amp udge receive command Wait 20
387. t SCK2 pin 4 INTSIO2 interrupt request Writing transmit Writing transmit Writing transmit data A data B data C SO2 pin SIO2SR TXF Figure 15 7 Exaple of External Clock and MSB Transmit Mode SCK2 pin SIO2SR lt SIOF gt SODH i lt gt lt lt 8 fc Figure 15 8 Hold Time of the End of Transmit Mode 4 Transmit error processing Transmit errors occur on the following situation Shift operation starts before writing next transmit data to SIOZTDB in external clock opera tion If transmit errors occur during transmit operation 51025 lt gt is set to 1 immedi ately after starting shift operation Synchronizing with the next serial clock falling edge INTSIO2 interrupt request is generated If shift operation starts before writing data to SIOZ2TDB after 5102 lt 8105 gt is set to 1 51025 lt gt is set to 17 immediately after shift operation is started and then INTSIO2 interrupt request is generated SIO2 pin is kept in high level when SIO2SR lt TXERR gt is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO2CR lt SIOINH gt to 1 In this case SIO2ZCR lt SIOS gt SIO2SR register SIOZRDB register and SIO2TDB register initialized Page 185 15 Synchronous Serial Interface 5102 15 3 Func
388. t TC4S TCA start control 0 Operation stop and counter clear 1 Operation start 000 timer event counter mode 001 8 bit programmable divider output PDO mode 010 8 bit pulse width modulation PWM output mode TC4M TC4M operating mode select 01 100 16 bit timer event counter mode 101 Warm up counter mode 110 16 bit pulse width modulation PWM output mode 111 16 bit PPG mode Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note 2 Do not change the TC4M TC4CK and TFF4 settings while the timer is running Note 3 To stop the timer operation TC4S 1 0 do not change the TC4M and settings To start the timer operation TC4S 0 gt 1 TC4M TC4CK and TFF4 can be programmed Note 4 When 1 upper byte in the 16 bit mode the source clock becomes the TC3 overflow signal regardless of the TC4CK setting Note 5 To use the TimerCounter in the 16 bit mode select the operating mode by programming TC4M where TC3CR lt TC3M gt must be set to 011 Page 102 05 Ls Note 6 To the TimerCounter in the 16 bit mode select the source clock by programming lt gt Set the timer start control and timer F F control by programming 45 and respectively Note 7 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 1 and Table 10 2 Note 8 The timer
389. t Operating reference voltage 1 RIEN ii V 0 3 1 0 Operating reference voltage 2 VoP2RP VRO reference RFRPI 1 2Vpp 700 kHz GND reference 2 9 Output upper limit voltage RFDC section FPi1 FPi2 FNi1 FNi2 RFDC Detection frequency 1 f Note 7 1DC slew rate Cin gt 1 uF for a 5 kHz Detection constant 1 T4DC rectangular wave input VRO reference oai in reference Vosipe 2 2 open 9 CMD RFOOLDi 00 9dB point with reference to low frequency side on the assumption that RFDCI 1 2 Vpp for Vop4pc and output amplitude OdB for a 700 kHz sine wave input RFDCI 1 2 Vpp for Vop4pc and Operating reference V VRO reference voltage 2 OP2DC RFDCI 1 2Vpp 350 2 CMD RFOOLDi 00 Output upper limit voltage GND reference GND reference Note 7 The detection frequency values are for only reference purposes Output lower limit voltage Permissible load resistance 17 2010 01 12 TOSHIBA TC94B14MFG Characteristics Symbol end Test Condition section gt f 1kHz SBADGAINi 0000 25 22 15 00 CMD GVSW 1 SBADGAINi 1111 ees CMD GVSW 0 SBADGAINi 1111 SBADGAINi 1444 Frequency Voltage gain 2 CD RW mode Operating reference voltage 1 VoP1SB CD DA mode VRO reference No input Operating reference SBADINV 0
390. t set ting set WDTCRI ATAS and then write D2H to WDTCR2 Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the setting in WDTCRI lt ATAS gt 6 3 2 Selection of Operation at Address Trap ATOUT When an address trap is generated either the interrupt request or the reset request can be selected by WDTCRI lt ATOUT gt 6 3 3 Address Trap Interrupt INTATRAP While WDTCRI lt ATOUT gt is 0 if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on chip RAM while WDTCR1 lt ATAS gt is 1 DBR or the SFR area address trap interrupt INTATRAP will be generated An address trap interrupt is a non maskable interrupt which can be accepted regardless of the interrupt mas ter flag IMF When an address trap interrupt is generated while the other interrupt including an address trap interrupt is already accepted the new address trap is processed immediately and the previous interrupt is held pending Therefore if address trap interrupts are generated continuously without execution of the RETN instruction too many levels of nesting may cause a malfunction of the microcontroller To generate address trap interrupts set the stack pointer beforehand Page 70 05 6 3 4 Address Trap Reset While WDTCRI ATOUT is 1 if the CPU should start looping for some cause such as noise and att
391. t RBFL gt to 1 The UART2SR RBFL is cleared 0 when the RD2BUF is read after reading the UART2SR RXD2 pin Final bit RD2BUF yyyy XXXX 1 1 UART2SR lt RBFL gt ij After reading UART2SR then 1 RD2BUF clears RBFL 1 INTRXD2 interrupt Figure 13 8 Generation of Receive Data Buffer Full Note If the overrun error flag UART2SR OERR is set during the period between reading the UART2SR and read ing the RD2BUF it cannot be cleared by only reading the RD2BUF Therefore after reading the RD2BUF read the UART2SR again to check whether or not the overrun error flag which should have been cleared still remains set 13 9 5 Transmit Data Buffer Empty When no data is in the transmit buffer TD2BUF that is when data in TD2BUF are transferred to the transmit shift register and data transmit starts transmit data buffer empty flag UART2SR TBEP is set to 1 The 25 lt gt is cleared to 0 when the TD2BUF is written after reading UART2SR Page 156 05 me Data write Data write TD2BUF 2222 Shift register TXD2 pin UART2SR lt TBEP gt 7 After reading UART2SR writing INTTXD2 interrupt TD2BUF clears Figure 13 9 Generation of Transmit Data Buffer Empty 13 9 6 Transmit End Flag When data are transmitted and no data is in TD2BUF UART2SR lt TBEP gt 1 transmit end flag UART2SR lt TEND gt is set to 1 The UART2SR
392. t SIOS gt to 0 for reading the data that received immediately before error occurence And read the data from SIO2RDB Data in shift register at errors occur can be read by reading the SIO2RDB again When SIO2SR lt RXERR gt is cleared to 0 after reading the received data SIO2SR lt RXF gt 15 cleared to 0 After clearing SIO2CR lt SIOS gt to 0 when 8 bit serial clock is input to SCK2 pin receive operation is stopped To restart the receive operation confirm that SIO2SR lt SIOF gt is cleared to 0 If the receive error occurs set the SIO2CR lt SIOINH gt to 1 for stopping the receive opera tion immediately In this case SIO2CR lt SIOS gt SIO2SR register SIO2RDB register and SIO2TDB register are initialized Page 188 TOSHIBA SIO2CR lt SIOS gt SIO2SR lt SIOF gt SIO2SR lt SEF gt SCK2 pin SI2 pin 5 025 lt gt T5CL8 oe Start shift Start shift Start shift operation a operation operation Co 5 025 lt gt INTSIO2 interrupt request SIO2RDB Write a 0 after reading the received data when a receive error occurs 8 Writing transmit Writing transmit data A data B Figure 15 12 Example of Receive Error Processing Note If receive error is not corrected an interrupt request does not generate after the error occurs 15 3 3 3 Transmit receive mode The transmit re
393. t TFF4 gt after the timer is stopped Do not change TC4CR lt TFF4 gt upon stopping of the timer Example Fixing the PPG4 pin to the high level when the TimerCounter is stopped CLR TCACR 3 Stops the timer CLR TC4CR 7 Sets the PPG4 pin to the high level Note 3 3 4 Page 115 10 8 Bit TimerCounter TC3 4 10 1 Configuration T5CL8 3 jsenbai jdnuejul 1 gt lt 4 sdojs UBYM 4 4 1 JO 1 1 peep yey vals 1901 1eddm 1901 eounos lt 331 gt 0701 lt 5 gt Figure 10 8 16 Bit Mode Timing Chart TC3 and 4 Page 116 05 Lus 10 3 9 Warm Up Counter Mode In this mode the warm up period time is obtained to assure oscillation stability when the system clocking 1s switched between the high frequency and low frequency The timer counter 3 and 4 are cascadable to form a 16 bit TimerCounter The warm up counter mode has two types of mode switching from the high frequency to low frequency and vice versa Note 1 In the warm up counter mode fix TCiCR TFFi to 0 If not fixed the PDOi PWMi and PPGi pins may output pulses
394. t delay time ee LRCKo Output delay time 8 pF fs 44 1 kHz BCKo 64 fs BCKi LRCKi AIN tecorr tircorr tecorr tLRcorr BCKo LRCKo BCKo LRCKo AOUT 22 2010 01 12 TOSHIBA 5 3 3 DATA CLCK Input Output timing TC94B14MFG 1 CLCK input mode Characteristics Symbol Test Test Condition Unit H level level Clock pulse width Input set up time E CLCK Input mode Transfer time 1 tpHL 1 Transfer time 2 tpHL1 tpHL2 tpLH2 SFSY tSU tHW tLW CLCK DATA SUBP SUBQ 2 CLCK output mode only for tHW tLW tpLH3 xn speed x 1 n Characteristics Symbol Test Test Condition Unit Circuit level Hw Clock pulse width wa e Transfer time 3 tpLH3 CLCK Output mode Transfer time 2 tpHL1 tpHL2 tpLH2 SFSY tpLH3 tHW tW CLCK DATA SUBP SUBQ 23 2010 01 12 TOSHIBA TC94B14MFG 5 3 4 SBSY SBOK Input Output timing Characteristics Symbol Test Condition Circuit EO m EXE ransfer time SBOK tpLH1 tpHL1 SFSY tpLH2 tpHL2 SBSY SBOK 5 3 5 Output pin timing Risingtime time 0 5 8 11 Falling time 1 a Rising time 2 Pio6 7 12 15 Falling time 2 tof2 CL Clock time CL 8 fs 44 1kHz MCKo 384fs Xi MCKo Clock time MCKo Clock H time tor tof
395. t on to these ngs IS ormally one byte nd cates one character ut fth s byte s equal to or greater than ths byte and ne t byte these two bytes nd cate one character TF code str ng Two bytes nd cate one character t s end a Somet mes th s str ng wth byte t ust means the the d rect on of hgh and low byte ust skp t and no need d splay TF n code str ng Two bytes nd cate one character t s b g end a Somet mes th s str ng begn wth byte t ust means the the d rect on of hgh and low byte ust skp t and no need d splay TF byte byte or byte cates one character For deta Is please referto TF format T Tcodng In T Trelated command there s one byte ndcates T T character set code lack epper ust reports the or g nal code read from dsc bout the character set code refer to bellow table 1 IS Shft IS code apanese cod ng orean characters h nese characters others Refer to related spec f cat on 84 TOSHIBA T5CJ3 7G28 F M Specification Revision history Version Date Comment In charge 1 0 2010 4 7 BlackPepper3 specification first version TLSZ Yang Jiangfeng 85 TOSHIBA 8 Bit Microcontroller TLCS 870 C Series T5CL8 TOSHIBA CORPORATION The information contained herein is subject to change without notice 021023 D TOSHIBA is continually working to improve the quality and
396. t to 1 When used as an input port the corresponding bit of P7CR1 should be set to 0 and then the corresponding bit of P7CR2 should be set to 1 When used as an analog input the corresponding bit of P7CR1 should be set to 0 and then the corresponding bit of P7CR2 should be set to 0 When P7CRI is 1 the content of the corresponding output latch is read by reading P7DR Table 5 6 Register Programming for Multi function Ports Programmed Value P7DR P7CR1 P7CR2 Note Asterisk indicates 1 or O either of which can be selected Table 5 7 Values Read from P7DR and Register Programming Values Read from P7DR P7CR1 P7CR2 EM x 25 1 62 05 P7CR2i P7CR2i input P7CR i P7CR1i input Control input Data input P7DRi Data output P7DRi STOP OUTTEN Analog input AINDS SAIN Note 1 i2 7 to O Note 2 STOP is bit7 SYSCR1 Note 3 SAIN is AD input select signal Figure 5 9 Port 7 7 1 and P7CR2 P7DR 7 6 5 4 3 2 1 0 0007H P77 P76 P75 P74 P73 P72 P71 P70 Initial value 0000 0000 R W 15 AIN13 AIN12 AIN10 AN9 amg Cna value P7CR1 7 6 5 4 3 2 1 0 0 Input mod P7CR1 control for port P7 Specified for each bit ARR R W P7CR2 7 6 5 4 3 2 1 0 0 Analog input P7CR2 P7 port input control Specified for each bit E R W Note 1 The port placed in input mode reads the pin
397. t trac in repeat none mode it ill stop mode and return P TO command A outP A TO command and play status e disscuss later erytime play process is start to oin the irst returned command must eP U command and thenPA TP command 9 can tell you a ne playin is started In some occasion the trac num erisntchan e utne playin is started itis same ore ample in repeat mode ater this son is played then P starttoplaythis son a ain PA U ill also e returned at playin innin 1 U command is la that orm host side last son playin inished and ne son playin ill e started ele ant commands are listed ello OST lac Pepper 33 TOSHIBA T5CJ3 7G28 F M Specification PLAY 0x14 Play a ile y speciyin a num er ost send this command any status as lon as readin process is inished and de ice is play a aila le The num er is the se uence in this de ice TRACK UP 0x31 Send this command in playin state play pause TRACK DOWN 0x32 Send this command in playin state play pause DIR UP 0x33 Send this command in playin state play pause DIR DOWN 0x34 Send this command in playin state play pause lac Pepper OST PLAY FILE DIR NUMBER 0xaO eturns this command P detects playin trac num eris chan ed PLAY FILE TYPE 0x99 ery command ill e ollo ed a command to tell host the type o current playin P ile A ile audio trac or other thin Com
398. task d ow P Y 1 machine cycle 1 Interrupt request Interrupt latch IL IMF A Execute Execute Execute i instruction instruction Interrupt acceptance instruction 4 Execute RETI instruction gt 92 Co oD SP n Kn 2 n 3 Note 1 a Return address entry address b Entry address c Address which RETI instruction is stored Note 2 On condition that interrupt is enabled it takes 38 fc s or 38 fs s at maximum If the interrupt latch is set at the first machine cycle on 10 cycle instruction to start interrupt acceptance processing since its interrupt latch is set Figure 3 1 Timing Chart of Interrupt Acceptance Return Interrupt Instruction Example Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address D203H Vector D204H Figure 3 2 Vector table address Entry address Interrupt service program Page 39 3 Interrupt Control Circuit 3 3 Interrupt Sequence 3 3 2 3 3 2 1 T5CL8 A maskable interrupt 1s not accepted until the IMF 15 set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is requested In order to utilize nested interrupt service the IMF is set to 1 in the interrupt service program In this case acceptable interrupt sources are selectively enabled by the individual interrupt enable
399. te 3 In the dual clock mode when returning to NORMAL2 both the high frequency and low frequency clock oscillators are turned on when returning to SLOWI mode only the low frequency clock oscillator is turned on In the single clock mode only the high frequency clock oscillator is turned on A warm up period is inserted to allow oscillation time to stabilize During warm up all internal operations remain halted Four different warm up times can be selected with the SYSCR1 lt WUT gt in accordance with the resonator characteristics When the warm up time has elapsed normal operation resumes with the instruction follow ing the STOP mode start instruction When the STOP mode is released the start is made after the prescaler and the divider of the timing generator are cleared to O STOP mode can also be released by inputting low level on the RESET pin which immediately performs the normal reset operation When STOP mode is released with a low hold voltage the following cautions must be observed The power supply voltage must be at the operating voltage level before releasing STOP mode The RESET pin input must also be H level rising together with the power supply voltage In this case if an external time constant circuit has been connected the RESET pin input voltage will increase at a slower pace than the power supply voltage At this time there is a danger that a reset may occur if input voltage level of the RESET pin drops b
400. ter the received data is read from SIOIRDB In this case SIOTCR SIOS SIOISR register SIOIRDB register and SIOITDB register are initialized Page 174 05 me SIO1CR SIOS SIO1SR lt SIOF gt Start shift Start shift Start shift operation K operation K operation e KANTEA BY t 31 iat SIO1TDB A Writing transmit Writing transmit data A data B SIO1SR RXF SIO1RDB Reading received Reading received Reading received data D data E data F SIO1CR SIOINH Figure 14 15 Example of Transmit Receive Transmit Error Processing b Receive errors Receive errors occur on the following situation To protect SIOIRDB and the shift register contents the received data is ignored while the SIOISR lt RXERR gt is 1 Shift operation is finished before reading out received data from SIOIRDB at SIOISR lt RXF gt is 17 in an external clock operation If receive error occurs set the SIO1CR lt SIOS gt to 0 for reading the data that received immediately before error occurence And read the data from SIOIRDB Data in shift register at errors occur can be read by reading SIOIRDB again When SIOISR RXERR is cleared to 0 after reading the received data SIOISR lt RXF gt is cleared to 0 After clearing SIO1CR lt SIOS gt to 0 when 8 bit serial clock is input to 5 pin re ceive operation is stopped To restart the re
401. terrupt is in process Contemporary cess is broken and INTATRAP interrupt process starts soon after it is requested Note The operating mode under address trapped whether to be reset output or interrupt processing is selected on watchdog timer control register WDTCR Page 42 05 Ls 3 External Interrupts The 5 8 has 5 external interrupt inputs These inputs are equipped with digital noise reject circuits Pulse inputs of less than a certain time are eliminated as noise Edge selection is also possible with to INT3 The INTO POO pin can be configured as either an external inter rupt input pin or an input output port and 1s configured as an input port during reset Edge selection noise reject control and INTO P00 pin function selection are performed by the external interrupt control register EINTCR Enable Conditions Release Edge Digital Noise Reject Pulses of less than 2 fc s are eliminated as noise Pulses of 7 fc s or more are considered to be signals In the SLOW or the SLEEP mod INTO IMF EF4 INTOEN 1 Falling edge SII is pulses of less than 1 15 s are eliminated as noise Pulses of 3 5 fs s or more are consid ered to be signals Pulses of less than 15 fc or 63 fc s are elimi 1 nated noise Pulses of 49 fc or 193 fc s or Falling edge INT1 IME EF6 1 f more are considered to be signals In the SLOW Bisina dge or the SLEEP mode pulses
402. th the SCK1 pin s falling edge 51015 lt 5 gt is kept in high level between the first clock falling edge of SCK1 pin and eighth clock falling edge SIOISR lt TXF gt is set to 1 at the rising edge of pin after the data written to the SIOITDB 15 transferred to shift register then the INTSIOI interrupt request is generated synchronizing with the next falling edge on 5 pin Note 1 In internal clock operation when SIO1CR lt SIOS gt is set to 1 transfer mode does not start with out writing a transmit data to the transmit buffer register SIO1TDB Note 2 In internal clock operation when the SIO1CR lt SIOS gt is set to 1 SIO1TDB is transferred to shift register after maximum 1 cycle of serial clock frequency then a serial clock is output from SCK1 pin Note 3 In external clock operation when the falling edge is input from SCK1 pin after SIO1CR lt SIOS gt is set to 1 SIO1TDB is transferred to shift register immediately Page 165 14 Synchronous Serial Interface 5101 14 3 Function SIO1CR SIOS SIO1SR sSIOF 5 015 lt 5 gt 5 pin outout 501 pin 5 015 lt gt INTSIO1 interrupt request SIO1TDB T5CL8 2 During the transmit operation When data is written to SIOTTDB SIOISR TXF is cleared to 0 In internal clock operation in case a next transmit data is not written to SIOITDB the serial clock stops to level by an automatic
403. th the least significant bit 14 3 2 3 Transmit receive mode 1 MSB transmit receive mode MSB transmit receive mode are selected by setting SIO1CR lt SIODIR gt to 0 in which case the data is transferred sequentially beginning with the most significant bit Bit7 and the data is received sequentially beginning with the most significant 2 LSB transmit receive mode LSB transmit receive mode are selected by setting SIOTCR SIODIR to 1 in which case the data is transferred sequentially beginning with the least significant bit 10 and the data is received sequentially beginning with the least significant 14 3 3 Transfer modes Transmit receive and transmit receive mode are selected by using SIO1CR lt SIOM gt 14 3 3 1 Transmit mode Transmit mode is selected by writing 00B to SIO1CR lt SIOM gt 1 Starting the transmit operation Transmit mode is selected by setting 00B to SIOICR SIOM Serial clock is selected by using SIOICR SCK Transfer direction is selected by using SIO1CR lt SIODIR gt When a transmit data is written to the transmit buffer register SIOTTDB SIOISR lt TXF gt is cleared to 0 After SIOICR lt SIOS gt is set to 1 SIOISR lt SIOF gt is set synchronously to 1 the falling edge of 5 pin The data is transferred sequentially starting from 501 pin with the direction of the bit specified by SIOLCR lt SIODIR gt synchronizing wi
404. the TXD2 pin is fixed at high level When transmitting data first read UART2SR then write data in TD2BUF Otherwise VART2SR lt TBEP gt 15 not zero cleared and transmit does not start 13 8 2 Data Receive Operation Set UART2CR1 lt RXE gt to 1 When data are received via the RXD2 pin the receive data are transferred to RD2BUF Receive data buffer At this time the data transmitted includes a start bit and stop bit s and a parity bit if parity addition 1 specified When stop bit s are received data only are extracted and transferred to RD2BUF Receive data buffer Then the receive buffer full flag UART2SR lt RBFL gt is set and an INTRXD2 interrupt is generated Select the data transfer baud rate using UART2CR1 lt BRG gt If an overrun error OERR occurs when data are received the data are not transferred to RD2BUF Receive data buffer but discarded data in the RD2BUF are not affected Note When a receive operation is disabled by setting UART2CR1 lt RXE gt bit to 0 the setting becomes valid when data receive is completed However if a framing error occurs in data receive the receive disabling setting may not become valid If a framing error occurs be sure to perform a re receive operation Page 154 05 13 9 Status Flag 13 9 1 Parity Error When parity determined using the receive data bits differs from the received parity bit the parity error flag UART2SR lt PERR gt is set to 1 The UART2SR lt
405. tic DI IMF lt 0 SET EIRH 1 Enables the INTTC4 El IMF lt 1 SET TC4CR 3 Starts TC4 and 3 PINTTC4 CLR TC4CR 3 Stops TC4 and 3 SET SYSCR2 5 SYSCR2 lt SYSCK gt lt 1 Switches the system clock to the low frequency clock CLR SYSCR2 7 SYSCR2 lt XEN gt lt 0 Stops the high frequency clock RETI VINTTC4 DW PINTTC4 INTTC4 vector table Page 117 10 8 Bit TimerCounter TC3 4 10 1 Configuration T5CL8 10 3 9 2 High Frequency Warm Up Counter Mode SLOW1 SLOW2 gt NORMAL2 NORMAL1 In this mode the warm up period time from a stop of the high frequency clock fc to the oscillation sta bility is obtained Before starting the timer set SYSCR2 XEN to 1 to oscillate the high frequency clock When a match between the up counter and the timer register TTREG4 3 value is detected after the timer is started by setting TC4CR lt TC4S gt to 1 the counter is cleared by generating the INTTC4 interrupt request After stopping the timer in the INTTC4 interrupt service routine clear SYSCR2 lt SYSCK gt to 0 to switch the system clock from the low frequency to high frequency and then SYSCR2 XTEN to 0 to stop the low frequency clock Table 10 9 Setting Time in High Frequency Warm Up Counter Mode Minimum time Setting Maximum time Setting TTREG4 3 0100H TTREG4 3 FF00H Example After checking high frequency clock oscillation stability with and 3 switching to the NORMALI mod
406. time Two machine cycles are required for the high or low level pulse input to the TC5 pin Therefore maxi mum frequency to be supplied is fc 2 Hz in the NORMAL17 IDLE1 2 mode and fs 2 to in the SLOW1 2 or SLEEP1 2 mode Since the initial value can be set to the timer F F6 by TC6CR lt TFF6 gt positive and negative pulses can be generated Upon reset the timer F F6 is cleared to 0 The logic level output from the PWM6 pin is the opposite to the timer F F6 logic level Since PWREG6 and 5 in the PWM mode are serially connected to the shift register the values set to PWREG6 and 5 can be changed while the timer is running The values set to PWREG6 and 5 during a run of the timer are shifted by the INTTC interrupt request and loaded into PWREG6 and 5 While the timer is stopped the values are shifted immediately after the programming of PWREG6 and 5 Set the lower byte PWREGS and upper byte PWREG6 in this order to program PWREG6 and 5 Programming only the lower or upper byte of the register should not be attempted If executing the read instruction to PWREG6 and 5 during PWM output the values set in the shift register is read but not the values set in PWREG6 and 5 Therefore after writing to the PWREG6 and 5 reading data of PWREG6 and 5 is previous value until INTTC6 is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PW
407. ting Os The AD convert operation is stopped immediately The converted value at this time is not stored in the AD converted value register Page 215 17 10 bit AD Converter ADC 17 3 Function T5CL8 ADCCR1 lt AMD gt AD conversion start ADCCR1 lt ADRS gt AD convert operation suspended Conversion result is not stored 1st conversion Conversion operation result 2nd conversion result 3rd conversion result z 1st conversion result 2nd conversion result ADCDR2 lt EOCF gt FT 22 EOCF cleared by reading conversion result Indeterminate 3rd conversion result ADCDR1 ADCDR2 INTADC interrupt request ADCDR1 Conversion Conversion Conversion ADCDR2 result read result read result read Conversion Conversion Conversion result read result read result read Figure 17 3 Repeat Mode 17 3 3 Register Setting 1 Setup the AD converter control register 1 ADCCR1 as follows Choose the channel to AD convert using AD input channel select SAIN Specify analog input enable for analog input control AINDS Specify AMD for the AD converter control operation mode software or repeat mode 2 Setup the AD converter control register 2 ADCCR2 as follows Set the AD conversion time using AD conversion time ACK For details on how to set the con version time refer to Figure 17 1 and AD converter control register 2 Choose IREFON for DA converter control
408. ting Time of Low Frequency Warm Up Counter Mode fs 32 768 kHz Minimum Time Setting Maximum Time Setting TTREG6 5 0100H TTREG6 5 FF00H Example After checking low frequency clock oscillation stability with TC6 and 5 switching to the SLOW1 mode SET SYSCR2 6 SYSCR2 lt XTEN gt lt 1 LD TC5CR 43H Sets TFF5 0 source clock fs and 16 bit mode LD TC6CR 05H Sets TFF6 0 and warm up counter mode Sets the warm up time S0001 warm up ine depends on the oscillator characteristic DI IMF lt 0 SET EIRE 2 Enables the INTTC6 EI IMF lt 1 SET TC6CR 3 Starts TC6 and 5 PINTTC6 CLR TC6CR 3 Stops TC6 and 5 SET SYSCR2 5 SYSCR2 lt SYSCK gt lt 1 Switches the system clock to the low frequency clock CLR SYSCR2 7 SYSCR2 lt XEN gt lt 0 Stops the high frequency clock RETI VINTTC6 DW 6 INTTC6 vector table Page 137 11 8 Bit TimerCounter 5 6 11 1 Configuration T5CL8 11 3 9 2 High Frequency Warm Up Counter Mode SLOW1 SLOW2 gt NORMAL2 NORMAL1 In this mode the warm up period time from a stop of the high frequency clock fc to the oscillation sta bility is obtained Before starting the timer set SYSCR2 XEN to 1 to oscillate the high frequency clock When a match between the up counter and the timer register TTREG6 5 value is detected after the timer is started by setting TC6CR lt TC6S gt to 1 the counter is cleared by g
409. tion SIO2CR lt SIOS gt SIO2SR lt SIOF gt 5 025 lt 5 gt SCK2 pin SO2 pin SIO2SR TXF 5 025 lt gt INTSIO2 interrupt request SIO2TDB SIO2CR lt SIOINH gt MC C T5CL8 Start shift Start shift Start shift X operation operation operation MM RES nanni nnii 7 cc amp Writing transmit Writing transmit data A data B Figure 15 9 Example of Transmit Error Processingme 15 3 3 2 Receive mode The receive mode is selected by writing 01B to SIO2CR lt SIOM gt 1 2 Starting the receive operation Receive mode is selected by setting 01 to 5 02 lt 5 gt Serial clock is selected by using 5102 lt 5 gt Transfer direction is selected by using SIO2CR lt SIODIR gt After SIO2CR lt SIOS gt is set to 1 51025 lt 5 gt is set synchronously to 1 the falling edge of SCK2 pin Synchronizing with the SCK2 pin s rising edge the data 1s received sequentially from SI2 pin with the direction of the bit specified by SBIZDIR lt SIODIR gt 51025 lt 5 gt is kept in high level between the first clock falling edge of SCK2 pin and eighth clock falling edge When 8 bit data is received the data is transferred to SIOZ2RDB from shift register INTSIO2 inter rupt request is generated and 51025 lt gt is set to 1 Note In internal clock operation when the 5102 lt 5105 gt is set to
410. tion is selected by using SIO1CR lt SIODIR gt After SIOICR lt SIOS gt is set to 1 51015 lt 5 gt is set synchronously to 1 the falling edge of pin Synchronizing with the SCK1 pin s rising edge the data is received sequentially from SII pin with the direction of the bit specified by SBI DIR lt SIODIR gt 51015 lt 5 gt is kept in high level between the first clock falling edge of 5 pin and eighth clock falling edge When 8 bit data is received the data is transferred to SIOITRDB from shift register INTSIO1 inter rupt request is generated and SIOISR lt RXF gt is set to 1 Note In internal clock operation when the SIO1CR lt SIOS gt is set to 1 the serial clock is generated from SCK1 pin after maximum 1 cycle of serial clock frequency During the receive operation The SIOISR lt RXF gt is cleared to 0 by reading a data from SIOIRDB In the internal clock operation the serial clock stops to H level by an automatic wait function when the all of the 8 bit data has been received Automatic wait function is released by reading a received data from SIOIRDB Then receive operation is restarted after maximum 1 of serial clock In external clock operation after SIO1SR lt RXF gt 15 set to 1 the received data must be read from SIOIRDB before the next data shift in operation is finished Page 168 05 me If received data is not read out from S
411. tiplexer _ Sample hold _ 0 89 circuit T Ct V comparator AIN15 n Successive approximate circuit Shift clock mE INTADC 4 Control circuit ______ SAN AINDS E ts 8 as ADBF ACK ADCCR1 ADCCR2 ADCDR1 ADCDR2 AD converter control register 1 2 AD conversion result register 1 2 Note Before using AD converter set appropriate value to I O port register conbining a analog input port For details see the sec tion on I O ports Figure 17 1 10 bit AD Converter Page 211 17 10 bit AD Converter ADC 17 2 Register configuration gi igurati T5CL8 17 2 Register configuration The AD converter consists of the following four registers 1 AD converter control register 1 ADCCRI This register selects the analog channels and operation mode Software start or repeat in which to per form AD conversion and controls the AD converter as it starts operating 2 AD converter control register 2 ADCCR2 This register selects the AD conversion time and controls the connection of the DA converter Ladder resistor network 3 AD converted value register 1 ADCDR1 This register used to store the digital value fter being converted by the AD converter 4 AD converted value register 2 ADCDR2 This register monitors the operating status of the AD converter AD Converter Control Register 1 ADCCR41 7 6 5 4 3 2 1 0 001CH ADRS AMD AINDS SAIN Initial val
412. to be clarified is that empty folder is also counted in driver layer if set bit to O but BlackPepper3 doesn t show you these folders If set to 1 empty folder is excluded About CD ROM directory sort please refer to B13 B14 datasheet Command sequence HOST BP3 GET FIRM VERSION 8007 FIRMWARE VERSION F701 SET FIRMWARE 83 BP3 return the same value of FIRMWARE FEATURE F700 host setting Host can compare this value to check it is right or not 6 3 Detect USB device and SD card BP3 etecting an car realtime an return their status automaticall an separatel fter reset B us start orking hen usis orking an eventfrom ill e return to host But us ill estoppe if ou select or o B plug or out event can not e etecte BP3 ust keet status at us stop please enote this point But car status is etecting all along elevant s are liste ello BlackPepper3 H USB SD_DET_STATUS 0xE0 Bor status separatel out B status meaning an its action is liste ello Status Explanation Action code remove ispla no car 29 TOSHIBA T5CJ3 7G28 F M Specification 3 car is inserte ustkeep aiting car is rea tartrea process car etecting is error ispla car error us is stoppe onee oan action us start initiali ing ust keep aiting evice is remove ispla evice is inserte
413. top Stop ay Stop ause f epper etects ove status c anging an it matc est e status or event in S S it returns ostne status or event yt is comman ese status or event in comman S Sarestate in eo ta e omman ata Status represente S S S 5 5 5 5 5 5 reeaseor 41 TOSHIBA T5CJ3 7G28 F M Specification 6 12Get File name is paragrap escri es getting name of current p aying ma imum aracters in fi e name utfor evant s iste S ack isc in fact ma imum is ytes ack epper support up to ytes fie name t at mean GET INFO FILE NAME 0x8003 et fi e name of current p aying ack epper S PLAY FILE irst of fie represent t e c aracter co ing is co ing is nico e co ing ic is in S S moe ut in omman se uence HOST BP3 GET INFO FILE NAME 8003 PLAY FILE NAME AA 6 13Get Folder name is paragrap escri es getting fo er name fo er name t atmean ma imum evant s iste eo S ack current aying fie is aracters ut for isc in fact ma imum is ytes ack epper support up to ytes in GET INFO DIR 0 8004 etfo ername of current p aying ack epper S PLAY DIR NAME 0xab irst of fie represent t e c aracter co ing is co ing is nico e co ing ic is in S S moe ut in omman se ue
414. ts the status code 7 byte data such as the security program condi Flash tat tput ash memory status outpu Flash memory security program setting Enables the security program 20 6 Operation Mode The serial PROM mode has seven types of modes that are 1 Flash memory erasing 2 Flash memory writing 3 RAM loader 4 Flash memory SUM output 5 Product ID code output 6 Flash memory status output and 7 Flash memory security program setting modes Description of each mode is shown below l Flash memory erasing mode The flash memory is erased by the chip erase erasing an entire flash area or sector erase erasing sectors in 4 kbyte units The erased area is filled with FFH When the security program is enabled the sector erase in the flash erasing mode can not be performed To disable the security program perform the chip erase Before erasing the flash memory T5CL8 checks the passwords except a blank product If the password is not matched the flash memory erasing mode is not activated Flash memory writing mode Data is written to the specified flash memory address for each byte unit The external controller must trans mit the write data in the Intel Hex format Binary If no error 1s encountered till the end record 5 8 calculates the checksum for the entire flash memory area 1000H to FFFFH and returns the obtained result to the external controller When the security program is enabled the
415. tting of IC bus mode The SBIM Bit3 and 2 in SBICRB is used to set C bus mode Set the SBIM to 10 in order to set I2C bus mode Before setting of bus mode confirm serial bus inter face pins in a high level and then write 10 to SBIM And switch a port mode after confirming that a bus 1s free 16 5 10Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus a bus arbitration procedure is imple mented in order to guarantee the contents of transferred data Data on the SDA line is used for bus arbitration of the IC bus The following shows an example of a bus arbitration procedure when two master devices exist simulta neously on bus Master and Master 2 output the same data until point After that when Master 1 outputs 1 and Master 2 outputs 0 since the SDA line of a bus is wired AND the SDA line is pulled down to the low level by Master 2 When the SCL line of a bus is pulled up at point b the slave device reads data on the SDA line that is data in Master 2 Data transmitted from Master 1 becomes invalid The state in Master 1 is called arbitration lost A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration When more than one master sends the same data at the first word arbitration occurs continuously after the second word SCL Bus 0
416. tuation To protect SIO2RDB and the shift register contents the received data is ignored while the SIO2SR lt RXERR gt is 1 Shift operation is finished before reading out received data from SIO2RDB at SIO2SR lt RXF gt is 17 in an external clock operation If receive error occurs set the SIO2CR lt SIOS gt to 0 for reading the data that received immediately before error occurence And read the data from SIO2RDB Data in shift register at errors occur can be read by reading the SIO2RDB again When 51025 lt gt is cleared to 0 after reading the received data SIO2SR lt RXF gt is cleared to 0 After clearing SIO2CR lt SIOS gt to 0 when 8 bit serial clock is input to SCK2 ceive operation is stopped To restart the receive operation confirm that SIO2SR lt SIOF gt is cleared to 0 If the received error occurs set SIO2CR lt SIOINH gt to 1 for stopping the receive operation immediately In this case 5102 lt 510 5 gt SIO2SR register SIO2RDB reg ister and SIO2TDB register are initialized Page 193 15 Synchronous Serial Interface 5102 15 3 Function T5CL8 SIO2CR SIOS Start shift Start shift Start shift operation operation Y operation SIO2SR SEF SCK2 pin output 502 pin ________ Si2pin 666 interrupt request siozros GR Unknown Writing transmit al transmit transmit data A data B data C SI
417. tus It sreadng 5 5 or Read Stop hen read ng send command to stop read ng process It goest to read stop status status Stop status fter read ng or stop play ng lay ng status lay ng pause FF or FR 74 Resetflow start TOSHIBA T5CJ3 7G28 F M Specification 7 1 Reset get firmware version set software feature flow C _ Received NO command gt Oxb62 YES inside Send from host lt coefficient gt send by host BP3 inside coefficient Y Send initial Send command command by 0x41 0x40 Send EQ data by 0x42 Send RF data by 0x43 0 44 a E Y NO command Oxb5 YES Get firmware version send command 0x8007 NO command OxF701 YES Set firmware feature send command 0x83 NO Reset flow end 75 TOSHIBA T5CJ3 7G28 F M Specification 7 2 Mode switch auto play resume recovery play flow Start lt System status gt Playing status Reading
418. ue 0001 0000 ADRS AD conversion start AD conversion start AD operation disable Software start mode AD ti d operating mode Reseed Repeat mode Anal t bl AINDS Analog input control nalog input enable Analog input disable 0000 AINO 0001 1 0010 2 0011 0100 4 0101 5 0110 6 0111 1000 8 1001 9 1010 10 1011 11 1100 12 1101 AIN13 1110 14 1111 15 Analog input channel select Note 1 Select analog input channel during AD converter stops ADCDR2 lt ADBF gt 0 Note 2 When the analog input channel is all use disabling the ADCCR1 lt AINDS gt should be set to 1 Note 3 During conversion Do not perform port output instruction to maintain a precision for all of the pins because analog input port use as general input port And for port near to analog input Do not input intense signaling of change Note 4 The ADCCR1 lt ADRS gt is automatically cleared to 0 after starting conversion Note 5 Do not set ADCCR1 lt ADRS gt newly again during AD conversion Before setting ADCCR1 lt ADRS gt newly again check 2 lt gt to see that the conversion is completed or wait until the interrupt signal INTADC is generated e g interrupt handling routine Note 6 After STOP or SLOW SLEEP mode are started AD converter control register ADCCR1 is all initialized and no data can be written in this registe
419. uest SIO1RDB T5CL8 Reading received data Clearing SIOS Start shift Start shift i Start shift operation Kk operation operation Writing transmit Writing transmit Writing transmit data A data B data C Figure 14 11 Example of External Clock and MSB Receive Mode 4 Receive error processing Receive errors occur on the following situation To protect SIOIRDB and the shift register con tents the received data is ignored while the SIOTSR RXERR is 1 Shift operation is finished before reading out received data from SIOIRDB at SIOISR lt RXF gt is 1 in an external clock operation If receive error occurs set the SIOICR SIOS to 0 for reading the data that received immediately before error occurence And read the data from SIOIRDB Data in shift register at errors occur can be read by reading the SIOIRDB again When 51 15 lt gt is cleared to 0 after reading the received data SIO1SR lt RXF gt is cleared to 0 After clearing SIO1CR lt SIOS gt to 0 when 8 bit serial clock is input to SCK1 pin receive operation is stopped To restart the receive operation confirm that SIOTSR SIOF is cleared to 0 If the receive error occurs set the SIO1CR lt SIOINH gt to 1 for stopping the receive opera tion immediately In this case 5101 lt 5105 gt SIOISR register SIOIRDB register and SIOITD
420. uired to start the timer mode and then set the PPG mode Set TC1CR TFF 1 at this time Note 3 In the PPG mode the following relationship must be satisfied TC1DRA TC1DRB Note 4 Set TC1DRB after changing the mode of TC1M to the PPG mode Page 89 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 Example Generating a pulse which is high going for 800 us and low going for 200 us fc 16 MHz Setting port LD TC1CR 10000111B Sets the PPG mode selects the source clock LDW TC1DRA 007DH Sets the cycle 1 ms 2716 ms 007DH LDW TC1DRB 0019H Sets the low level pulse width 200 us 2 fc 0019H LD TC1CR 10010111B Starts the timer Example After stopping PPG setting the PPG pin to a high level to restart PPG fc 16 MHz Setting port LD TC1CR 10000111B Sets the PPG mode selects the source clock LDW TC1DRA 007DH Sets the cycle 1 ms 2710 us 007DH LDW TC1DRB 0019H Sets the low level pulse width 200 us 2 fc 0019H LD TC1CR 10010111B Starts the timer LD TC1CR 10000111B Stops the timer LD TC1CR 10000100B Sets the timer mode LD TC1CR 00000111B Sets the PPG mode TFF1 0 LD TC1CR 00010111B Starts the timer Port output enable EE gt PPG port output latch shared with PPG output Data output Function output TC1CR lt TFF1 gt Write to TC1CR Internal reset Match to TC1DRB Match to TC1DRA Timer F F1 interr
421. up counter and the TCIDRA Since pin input has the noise rejection pulses of 4 s or less are rejected as noise A pulse width of 12 fc s or more is required to ensure edge detection The rejection circuit is turned off in the SLOWI 2 or SLEEP1 2 mode but a pulse width of one machine cycle or more is required Example 1 Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin fc 16 MHz LDW TC1DRA 007DH 1ms 2 fc DI IMF 0 SET EIRL 5 Enables INTTC1 interrupt EI IMF 1 LD TC1CR 00000100B Selects the source clock and mode LD TC1CR 00100100B Starts TC1 external trigger METT1 0 Example 2 Generating an interrupt when the low level pulse with 4 ms or more width is input to the TC1 pin fc 16 MHz LDW TC1DRA 01F4H 4 ms 27 1F4H DI IMF 0 SET EIRL 5 Enables INTTC1 interrupt EI IMF 1 LD TC1CR 00000100B Selects the source clock and mode LD TC1CR 01110100B Starts TC1 external trigger METT1 1 Page 82 05 me At the rising Count start Count start edge TC1S 10 TC1 input Source clock 0 104 _ Wd wee TC1DRA INTTC1 interrupt request a Trigger start METT1 0 At the rising Count start Count clear Count start edge TC1S 10 TC1 pin input uuu N
422. upt request TC1CR MPPG1 TC1CR lt TC1S gt clear Figure 8 7 Output Page 90 05 me Timer start Internal clock Counter TC1DRB TC1DRA PPG pin output INTTC1 interrupt request Continuous pulse generation TC1S 01 Count start TC1 pin input Trigger Internal clock Counter 0 rom TC1DRA output interrupt request Application One shot pulse output b One shot pulse generation TC1S 10 Note m gt n Figure 8 8 PPG Mode Timing Chart Page 91 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 Page 92 05 9 16 Bit Timer Counter2 2 9 1 Configuration TC2 pin 1 223 fs 215 fc 219 16 25 fc 28 fc 23 2 fs interrupt TC2 control register 16 bit timer register 2 Note When control input output is used I O port setting should be set correctly For details refer to the section I O ports Figure 9 1 Timer Counter2 TC2 Page 93 9 16 Bit Timer Counter2 2 9 2 Control T5CL8 9 2 Control The timer counter 2 is controlled by a timer counter 2 control register TC2CR and a 16 bit timer register 2 TC2DR TER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0025 TC2DRH 0025H TC2DRL 0024H 00241 Initial value 1111 1111 1111 1111 R W TC2CR 7 6 5 4 3 2
423. ure to erase the existing data by sector erase or chip erase before rewriting data Page 247 20 Serial PROM Mode 20 6 Operation Mode T5CL8 20 6 4 Flash Memory SUM Output Mode Operation Command 90H Table 20 10 shows flash memory SUM output mode process Table 20 10 Flash Memory SUM Output Process E Transfer Bytes Baud Rate 1st byte 2nd byte Transfer Data from External Control Transfer Data from T5CL8 to ler to T5CL8 External Controller Matching data 5AH 9600 bps Automatic baud rate adjustment 9600 bps OK Echo back data Error Nothing transmitted 3rd byte Ath by Baud rate modification data 9600 bps See Table 20 4 9600 bps OK Echo back data Error A1H x 3 A3H x 3 62H x 3 Note 1 h h Operation command data 90H Modified baud rate Modified baud rate OK Echo back data 90H Error A1H x 3 A3H x 3 63H x 3 Note 1 h Modified baud rate OK SUM Upper byte Note 2 Error Nothing transmitted h Modified baud rate OK SUM Lower byte Note 2 Error Nothing transmitted Wait for the next operation com mand data Modified baud rate Note 1 xxH x 3 indicates that the device enters the halt condition after sending 3 bytes of xxH For details refer to 20 7 Error Code Note 2 Refer to 20 8 Checksum SUM Description of the flash memory SUM output mode The 1st through 4th bytes of the tr
424. urrent in SLOW1 mode Supply current in SLEEP1 mode Supply current in SLEEPO mode Supply current in STOP mode Peak current for SLOW1 mode Ippp p Note5 6 Write Erase Security program current for Ippew Flash memory Note7 8 Note 1 Typical values show those at 25 C and 5 V 5 5 V Vin 5 3 V 0 2 V 5 3 V 0 1 V 10 to 40 3 0V Vin 2 8 V 0 2 V 2 8 V 0 1 V 10 to 40 Vpp 5 5 Vin 5 3 V 0 2 V 5 3 0 1 V 10 to 40 Note 2 Input current The current through pull up resistor is not included Note 3 Ipp does not include Note 4 The supply currents of SLOW2 and SLEEP2 modes are equivalent to those of IDLEO IDLE1 and IDLE2 modes Note 5 When a program is executing in the flash memory or when data is being read from the flash memory the flash memory operates in an intermittent manner causing peak currents in the operation current as shown in Figure 22 1 In this case the supply current Ipp in NORMAL1 2 SLOW1 modes is defined as the sum of the average peak current and MCU current Note 6 When designing the power supply make sure that peak currents can be supplied The internal supply voltage of this device may be changed by this peak current Thus it needs a bypass capacitor about 0 1uF near its power terminal to stabilize its operation In SLOW
425. use loss of human life bodily injury serious property damage or serious public impact Unintended Use Unintended Use includes without limitation equipment used in nuclear facilities equipment used in the aerospace industry medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators devices related to electric power and equipment used in finance related fields Do not use Product for Unintended Use unless specifically permitted in this document Do not disassemble analyze reverse engineer alter modify translate or copy Product whether in whole or in part Product shall not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable laws or regulations e The information contained herein is presented only as guidance for Product use No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product No license to any intellectual property right is granted by this document whether express or implied by estoppel or otherwise ABSENT AWRITTEN SIGNED AGREEMENT EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW TOSHIBA 1 ASSUMES NO LIABILITY
426. utput port the interrupt latch is set on the falling edge of the output pulse P2 port output latch P2DR and P2 port terminal input P2PRD are located on their respective address When read the output latch data the P2DR should be read and when read the terminal input data the P2PRD reg ister should be read If a read instruction is executed for port P2 read data of bits 7 to 3 are unstable Data input P20 lt Data output P20 Output latch Contorl input Q Data input P21PRD C IOS Output latch read P21 Osc enable Data output P21 P21 Data input P22PRD pomme Output latch read P22 Data output P22 P22 XTOUT ur s ES Data input P20PRD di V B P20 INT5 STOP VA OUTEN fs XV Figure 5 4 Port 2 7 6 5 4 3 P2DR 0002H P22 P21 P20 _ RIW XTOUT XTIN 5 Initial value 111 STOP P2PRD P22 P21 P20 000CH Read only Note Port P20 is used as STOP pin Therefore when stop mode is started OUTEN does not affect to P20 and P20 becomes high Z mode Page 54 05 de 5 4 Port P37 to P30 Large Current Port Port P3 is an 8 bit input output port When used as an input port the corresponding output latch P3DR should be set to 1 During reset the P3DR is initialized to 1 P3 port output latch P3DR and P3 port terminal input P
427. value 0000 11 0 N it PERR Parity error flag 4 Babe Read only 0 No FERR Framing error flag anng d 1 Framing error 0 overrun error Overrun error flag 1 Overrun error 0 Receive data buffer empty RBFL Receive data buffer full flag 4 Receive data buffer full 0 Ont itti TEND Transmit end flag bel 1 Transmit end TBEP Transmit data buffer empty flag 0 anemi data buffer full Transmit data writing is finished 1 Transmit data buffer empty Note When an INTTXD is generated TBEP flag is set to 1 automatically UART2 Receive Data Buffer RD2BUF 7 6 5 4 3 2 1 0 Read only ew LT T T LT LT UART2 Transmit Data Buffer TD2BUF 7 6 5 4 3 2 1 0 Write only e TT T TIL T seme eom Page 151 13 Asynchronous Serial interface UART2 13 3 Transfer Data Format T5CL8 13 3 Transfer Data Format In UART2 an one bit start bit Low level stop bit Bit length selectable at high level by UART2CR1 lt STBT gt and parity Select parity in UART2CR1 lt PE gt even or odd numbered parity by UART2CRI EVEN are added to the transfer data The transfer data formats are shown as follows Frame Length se JC Y se De ay Figure 13 2 Transfer Data Format Without parity 1 STOP bit With parity 1 STOP bit Without parity 2 STOP bit With parity 2 STOP bit Figure 13 3 Caution on Changing Tra
428. voltage to be input on the input pin must not exceed the range between Varer and Vas If a voltage outside this range is input conversion values will become unstable and conversion values of other channels will also be affected Note 4 Analog reference voltage range AVAngr Varer Vss Note 5 When AD converter is not used fix the AVDD and VAREF pin on the level Page 272 05 NT 22 5 AC Characteristics Vss 0 V 4 5 V lt Vpp lt 5 5 V 40 to 85 NORMAL1 2 modes 0 25 4 IDLEO 1 2 modes Machine cycle time tcy us SLOW1 2 modes 117 6 133 3 SLEEPO 1 2 modes High level clock pulse width For external clock operation XIN input Low level clock pulse width fc 16 MHz High level clock pulse width For external clock operation XTIN input Low level clock pulse width fs 32 768 kHz Vss 0 V 2 7 V lt 4 5 V 40 to 85 C NORMAL41 2 modes IDLEO 1 2 modes Machine cycle time SLOW1 2 modes SLEEPO 1 2 modes High level clock pulse width For external clock operation XIN input Low level clock pulse width fc 8 MHz High level clock pulse width For external clock operation XTIN input Low level clock pulse width fs 32 768 kHz 22 6 Flash Characteristics 22 6 1 Write Retention Characteristics Vss 0 V Number of guaranteed writes to flash memory Vgg 0 V 10 to 40 10 Times Page 273
429. w level generation an acknowledge signal during addi tional clock pulse cycle after the matching of slave address or the detection of GENERAL CALL The Table 16 1 shows the SCL and SDA pins status in acknowledgment mode Table 16 1 SCL and SDA Pins Status in Acknowledgement Mode An additional clock pulse is generated ____ Master SDA Released in order to receive Set to low level generating an an acknowledge signal acknowledge signal SCL A clock is counted for the acknowledge signal When slave address matches Set to low level generating an Slave or a general call is detected acknowledge signal SDA After matching of slave Released in order to receive Set to low level generating an address or general call an acknowledge signal acknowledge signal 16 5 1 2 Non acknowledgment mode 0 To set the device as a non acknowledgement mode the ACK Bit4 in SBICRA should be cleared to 0 Page 199 16 Serial Bus Interface I2C Bus Ver D 581 16 5 I2C Bus Control T5CL8 In the master mode a clock pulse for an acknowledge signal is not generated In the slave mode a clock for a acknowledge signal is not counted 16 5 2 Number of transfer bits The BC Bits7 to 5 in SBICRA is used to select a number of bits for next transmitting and receiving data Since the 15 cleared to 000 by a start condition a slave address and direction bit transmissions always
430. wait function when all of the bit set in the SIOITDB has been transmitted Automatic wait function is released by writing a transmit data to SIOITDB Then trans mit operation is restarted after maximum 1 of serial clock When the next data is written to the SIOITDB before termination of previous 8 bit data with SIOISR lt TXF gt 1 the next data is continuously transferred after transmission of previous data In external clock operation after SIOTSR TXF is set to 1 the transmit data must be written to SIOITDB before the shift operation of the next data begins If the transmit data is not written to SIOITDB transmit error occurs immediately after shift opera tion is started Then INTSIO1 interrupt request is generated after 51015 lt gt is set to 1 3 Stopping the transmit operation There are two ways for stopping transmits operation The way of clearing 5101 lt 51 5 gt When SIO1CR lt SIOS gt is cleared to 0 transmit operation is stopped after all transfer of the data is finished When transmit operation is finished SIO1SR lt SIOF gt is cleared to 0 and SOI pin is kept in high level In external clock operation SIO1CR lt SIOS gt must be cleared to 0 before SIO1SR lt SEF gt 15 set to 1 by beginning next transfer The way of setting SIO1CR lt SIOINH gt Transmit operation is stopped immediately after SIOICR SIOINH is set to 1 In this case SIOLCR lt S
431. whether the signal format of the disc is correspond to the request of the unit whether there is any contamination or damage or light leakage on the surface of the disc b To check whether there is any abnormal of the rotation of the deck mecahnism or whether the disc is enter in position c To check whether it is normal when reading USB REED d To check whether the 17 P FFC of laser pick up is inserted in place whether the socket of it is loose 4 CD defective e To check whether there is any contamination or foreign body on the surface of the laser pick up f To check the servo connector of CON601 602 9 To check the oscillation frequence of crystal X602 should be 16 9344M h To check the oscillation frequence of crystal X603 should i 9MHZ i To check the voltage of the 50 pin of IC 602 should be 3 3V E j To check the switch S601 on the servo board 33 check the rotation mechanism of CD deck mechanism To check the voltage of the 8 pin of IC 603 shouldbe 8V m To check whether the rotation belt of deck mechanism is dislocation or loose a To check whether the USB signal format is correspond to the request of the unit b To check the voltage of the the uppermost pin of the USB connector should be 5 To check the voltage of the first pin of main board IC604 should be 3V3 when insert USB the voltage of the second pin should be if no insert the USB the voltege should be
432. writing next transmit data to SIO2TDB in external clock op eration If transmit errors occur during transmit operation 51025 lt gt is set to 1 im mediately after starting shift operation And INTSIO2 interrupt request is generated af ter all of the 8 bit data has been received If shift operation starts before writing data to SIO2TDB after SIO2CR lt SIOS gt is set to 1 SIO2SR lt TXERR gt 15 set immediately after starting shift operation And INTSIO2 interrupt request is generated after all of the 8 bit data has been received 502 pin is kept in high level when 51025 lt gt is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO2CR lt SIOINH gt to 1 after the received data is read from SIO2RDB In this case SIO2CR lt SIOS gt SIO2SR register SIO2RDB register and SIO2TDB register are initialized Page 192 05 Hn SIO2CR lt SIOS gt SIO2SR lt SIOF gt Start shift Start shift Start shift operation K operation K operation KANTEA BY t 31 SIO2TDB A Writing transmit Writing transmit data A data B SIO2SR RXF sic2npo Reading received Reading received Reading received data D data E data F SIO2CR lt SIOINH gt Figure 15 15 Example of Transmit Receive Transmit Error Processing b Receive errors Receive errors occur on the following si
433. xample 1 Enables interrupts individually and sets IMF DI 0 LDW EIRL 1110100010100000B EF15 to EF13 EF11 EF7 EF5 lt 1 Note IMF should not be set EI lt 1 Example 2 C compiler description example unsigned int io 3AH EIRL shows address 010 EIRL 101000008 _ 10 37 3 Interrupt Control Circuit 3 2 Interrupt enable register EIR 15018 Interrupt Latches Initial value 00000000 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 003DH 003CH 12 ILH 003DH ILL 003CH Initial value 00000000 ILE 7 6 5 4 3 2 1 0 002 123 1022 1121 1L20 119 IL17 116 ILE 002EH at RD at WR IL23 to IL2 Interrupt latches 0 No interrupt request 0 Clears the interrupt request R W 1 Interrupt request 1 Interrupt latch is not set Note 1 To clear any one of bits IL7 to IL4 be sure to write 1 into IL2 and IL3 Note 2 In main program before manipulating the interrupt enable flag EF or the interrupt latch IL be sure to clear IMF to 0 Disable interrupt by DI instruction Then set IMF newly again as required after operating on the EF or IL Enable interrupt by El instruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute normally on inter rupt service routine However if using multiple interrupt on interrupt service routine manipul
434. xff 2 10 84 DATA OxNN liay status FAIL 1 Ox8b OxNN command can not be accpeted 2 Ox8c DATA OxNN sound mute on or off status ack to mute on off command SYS OFF STATUS Oxff 2 0x8d DATA OxNN on or off status ack to system on off command FLASH UPGRADE OK 1 Ox8e OxNN_ Jexternal flash upgrade is finished and no problem first track final track total time information CD TOC INFO Oxff 5 10 90 DATA OxNN CDDA MIXCD disc total number total folder number TTL FILE DIR NUMBER 0 5 0x94 DATA OxNN MIXCD CDROM USB SD MTP 4 0x97 DATA OxN gt PLAY STREAM INFO bitrate information sample frequency information PLAY FILE 2 0x99 DATA OxNN Hite type mp3 wma cdda track STREAM UNKNOW 0 1 Ox9b OxNN stream info is unknow ack to stream request command BUSY 1 Ox9b OxNN lias analyze is busy ack to id3 request command PLAY END Oxff 1 0 9 OxNN fall songs playing is finished PLAY CD TRACK INDEX 2 Ox9f DATA 0 gt index number of CDDA track play file number play folder number folder inside PLAY FILE DIR NUMBER 0 9 0 0 gt information 4 0 2 gt PLAY TIME playing ti
435. xternal interrupt 1 input PORTO2 UART data output 1 P01 RXD1 BOOT PORTO1 UART data input 1 Serial PROM mode control input 00 INTO PORTOO External interrupt O input P17 TC6 PDO6 PWM6 PPG6 PORT17 TC6 input PDO6 PWM6 PPG6 output P16 5 PDOS PWM5 PORT16 TC5 input PDOS5 PWMS5S output P15 TC2 INT3 15 TC2 input External interrupt 3 input 14 4 PDO4 PWM4 PPG4 PORT14 TC4 input PDO4 PWM4 PPG4 output P13 PDO3 PWM3 PORT13 TC3 input PDO3 PWM3 output P12 PPG PORT12 PPG output P11 DVO PORT11 Divider Output P10 TC1 PORT10 TC1 input P22 XTOUT PORT22 Resonator connecting pins 32 768kHz for inputting external clock Page 5 PORT21 Resonator connecting pins 32 768kHz for inputting external clock 1 4 Pin Names and Functions T5CL8 Table 1 1 Pin Names and Functions 2 3 Pin Name Pin Number Input Output Functions PORT20 External interrupt 5 input STOP mode release signal input PORT37 6 5 4 PORT32 PORT31 PORT30 PORT47 PORT46 Serial clock input output 2 PORT45 Serial data output 2 PORT44 Serial data input 2 PORT43 PORT42 UART data output 2 PORT41 UART data input 2 40 54 PORT53 52 PORT51 I2C bus data POR
436. y on Wakeup Input and Port Input a STOP b In case of to STOP3 STOP pin STOP pin L lt lt gt STOP mode gt SToRmods Release STOP mode STO mod Figure 18 3 Priority of STOP pin and STOPO to STOP3 pins Table 18 1 Release level edge of STOP mode Release level edge SYSCR1 lt RELM gt 1 Note2 Pin name SYSCR1 lt RELM gt 0 Page 222 TOSHIBA us 19 Flash Memory TSCL8 has 61440byte flash memory address 1000H to FFFFH The write and erase operations to the flash memory are controlled in the following three types of mode MCU mode The flash memory is accessed by the CPU control in the MCU mode This mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash memory is available by retaining the application behavior Serial PROM mode The flash memory is accessed by the CPU control in the serial PROM mode Use of the serial interface UART enables the flash memory to be controlled by the small number of pins 5 8 in the serial PROM mode supports on board programming which enables users to program flash memory after the microcontroller is mounted on a user board Parallel PROM mode The parallel PROM mode allows the flash memory to be accessed as a stand alone flash memory by the program writer provided by the third party High speed access to the flash memory is available by
437. y program operation any attempts to read from the same address is reversed bit 6 of the data toggling between 0 and 1 19 3 Toggle Bit D6 After the byte program chip erase and security program command sequence is executed any consecutive attempts to read from the same address 15 reversed bit 6 D6 of the data toggling between 0 and 1 until the opera tion is completed Therefore this toggle bit provides a software mechanism to check the completion of each opera tion Usually perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory After the byte program chip erase or security program command sequence is executed the initial read of the toggle bit always produces a 1 Page 227 19 19 4 Access to the Flash Memory Area T5CL8 19 4 Access to the Flash Memory Area When the write erase and security program are set in the flash memory read and fetch operations cannot be per formed the entire flash memory area Therefore to perform these operations in the entire flash memory area access to the flash memory area by the control program in the BOOTROM or RAM area The flash memory pro gram cannot write to the flash memory The serial PROM or MCU mode is used to run the control program in the BOOTROM or RAM area Note 1 The flash memory can be written or read for each byte unit Erase operations can be performed either in t

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