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AT8030 User's Guide

1. 35 4 3 2 5 5015 255 2 and gatas SR RATER RARE E E 36 iii AT8030 User s Guide Table of Contents 5 5955455 n 42 4 4 1 Supported 1 1 30 42 4 4 2 Sensor Data RECOMS suu due aimo S deese deeds wes 50 4 4 3 xd Sid RE a nd Ui 63 gt Saw see ORCI A UE 89 4 5 KR AERE EF 91 4 5 1 Supported Commands eese ae eere 605 91 4 5 2 Sensor Data Recordsis REX bu s ums 100 4 5 3 FRU Informations ola noa ERA GE bei 107 4 5 4 MMC FRUS FRUZ FRU Data 1 108 A455 PMIOVerDAN uus vga TE ERE XU ENTM ANNAM REESE Le DEL SAT a ODES 109 4 5 6 Serial Over Lan p eoe RO 112 Software Setup vier EXC OCC D OUTRE ROUES C c ECC Ra e e 116 5 1 AMI BIOS Setup 116 5 1 1 Accessing the BIOS Setup 08 116 5 1 2 Menu
2. 147 6 2 Unit Computer 5 147 iv AT8030 User s Guide Table of Contents 7 Thermal Considerations s Ves REA UC E VERE E E RC DV 150 7 1 Thermal 150 7 1 1 HEAD 150 7 1 2 Temperature Sensors cere TA ad wea 150 A13 Airflow Blocker cons AU I Se abd x eg hats 152 7 24 System Aitlow ERI 152 As us uso Vae iR CE ORE 1 1 1 A 2 Kontron I O Mapping E NUR E ER sake E RU 2 PCIIDSELand Device Numbers a pt T A 3 B Kontron Extension lt lt 5 aye e oo p B 1 B 1 FPGA CPLD Registers 5 B 1 2 17400 Addressing 5 B 2 IPMC LPCAddressingSpace B 3 Connector i ess E e m S RC AKE DURO
3. Blak Cee 118 5 1 3 Main CA s e exon die Stade dau dau 120 Advanced RC EE Oe a pe e rue ante ee 120 5 1 5 Security pA EE a LEER E 129 5 1 6 Boot Menu M SERE 130 5 1 7 System Management 134 5 1 8 Dab Mens a AN d aestas 142 5 2 Boot Utiles eee o eye EG a ES ben 143 5 2 1 Pressing SF225 iis ves wh setae i 143 5 2 2 Pressing lt F11 gt or F3 from a Console Redirection terminal 143 5 2 3 BOOT Menu POP UP iscsi Sais nee RA S RR Re ADR RUN RE AUR 143 5 3 Console Redirection VT100 144 5 3 1 Requirements ote fart too s axo sage ooi oa 144 5 3 2 ANSIand VT100 Keystroke 144 5 3 3 VT UTF8 Keystroke 144 5 4 5 145 Unit Computer 147 6 1 Ethernet Switch
4. 96 Bridge ICMB Management Supported Commands for MMC builtin 97 Discovery ICMB Commands for MMC 1 98 Bridging ICMB Commands for MMC 1 98 Event ICMB Commands for MMC builtin 98 ix AT8030 User s Guide List of Tables Table 4 63 Table 4 64 Table 4 65 Table 4 66 Table 4 67 Table 4 68 Table 4 69 Table 4 70 Table 4 71 Table 4 72 Table 4 73 Table 4 74 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 6 1 Table 6 2 Table 7 1 Table 7 2 OEM for Bridge NetFn ICMB Commands for 98 Other Bridge ICMB Commands for MMC 99 PICMG 3 0 Commands for MMC 1 99 0 Commands for MMC 1 100 MMC Built in FRU2 FRU3 FRU4 Sensors 101 MMC Sensor Names ccu e esie EE EE EM RC Ru 106 CPUO Engine Board Information 107 CPUO Engine Product Information 107 CPU1 CPU2 Engine Board Information Area 108 CPU1 CPU2 Engine Product Information Area 109 Front
5. C 1 C 1 Connectors and Headers Summary C 1 C2 SenalPort J5 C 1 Ethernet J6 E CFLC C 1 USBPort 710 115 46 amp 17 ees esee RE ER UR RES C 2 5 Telco Clock 120 cesser kiirte ERE P EE Eb ER nes wees RE RES S ERE RES 2 C 6 AdvancedTCA 1 0 AdvancedTCA 3 1 223 C 3 C 7 AdvancedTCAI O RTM Connector 330 C 4 56 AMOBI B1 oo eiua rs Ra c SEE C 6 207 Power croceo CHE UD Ub REL E PENES C 7 D BIOS Setup Error Codes RR D IA ws D 1 D 1 Bootblock Initialization Code D 1 D 2 Bootblock Recovery Code Checkpoints 2 D 3 POST Code Checkpoints D 2 D 4 5 D 5 D 5 Memory Initialization ERROR D 6 Software Update oaov See WWD ONAN Dee E 1 1 IPMC MMC Firmware Update Procedure E 1 E 2 Updating ATB030 BIDS usos
6. EC FCR US E 2 Updating the switch E 3 v AT8030 User s Guide Table of Contents F I Supported RECS and lt RIA Va wis F 1 Supported RFCS 1 Supported MIBS 4 6 1 G 1 General Operations uie e re here E ai 6 1 6 2 Bootloader CommandS e ord ux a G 1 G 3 Bootloader 5 55 55 5 5 555 5 5 55 555595 4 QNM 0 G 4 G 4 Setting the G 5 Getting Help ioi 1 H 1 Returning Defective H 2 H 2 When Returning a H 3 Gloss ly 1 1 AT8030 User s Guide List of Figures List of Figures Figure Figure Figure Figure Figure Figure Figure Figure 2 1 3 1 3 2 3 3 4 1 5 1 5 2 7 1 Block Diagram sb pe EUR 12 Setting
7. rtt doom 20 Jumper Descnption zi e ta mex 25 CPU engines 0 1 amp 2 memory list and 5 26 PowerQuicc memory list and characteristics 27 Onboard Connectors and lt 5 29 Kontron OEM Power Good Sensor definition 36 Kontron OEM FRU Info Agent Sensor 37 Kontron OEM IPMB L Link Sensor definition 38 Kontron OEM POST Code Value Sensor 38 Kontron OEM Management Controller firmware ugrade Status Sensor definition 39 Kontron OEM Switch Management Status Sensor definition 39 Kontron OEM Diagnostic Status Sensor 39 Kontron OEM External Component Firmware Upgrade Status Sensor definition 39 Kontron OEM FRU Over current Sensor definition 40 Kontron OEM FRU Sensor error Sensor definition 40 Kontron OEM FRU Power denied Sensor 40 Kontron OEM Reset Sensor definition 41 IPM De
8. 74 Point To Point Connectivity Record 2 of 2 Update Channel Switcher 79 Carrier Clock Resource Ids assignment 81 Carrier Clock Point to Point Connectivity 81 0 R2 0 Clock Configuration Record 1 of 2 PCIe Clock 83 0 R2 0 Clock Configuration Record 2 of 2 Clock Multiplexer 85 IPM Device Supported Commands for MMC builtin 91 Watchdog Timer Supported Commands for MMC builtin 91 Device Messaging Supported Commands for builtin 92 Chassis Device Supported Commands for 93 Event Supported Commands for MMC built 94 PEF and Alerting Supported Commands for 94 Sensor Device Supported Commands for 94 FRU Device Supported Commands for MMC builtin 95 SDR Device Supported Commands for MMC builtin 95 SEL Device Supported Commands for MMC 96 LAN Device Supported Commands for MMC builtin 96 Serial Modem Device Supported Commands for MMC builtin
9. 55445 35 wera waded vin es Bae Wes xvii 1 Product Description idees eee ERREICHT DESCR COE CR VOI e 2 LI Prod ctOVerVieW oaa o ER NN ERE OE VPN RR MM US NN OS RN E RES 2 1 2 E ERE RE NOCHE EE A AR Ce T Rant o E io S 2 1 3 Board Specifications Unit Computer Section 3 1 4 Board Specifications CPUO 4 1 5 Board Specifications CPU1 25 6 1 6 Board Specifications all iue ER e E Y PE ARIS 7 1 7 Compliance sese hene rna Rr 8 1 8 8 1 9 Interfacing with the Environment 9 1 9 1 RTM rear transition 9 1 9 2 Mezzanine so RR KR 10 22 Board 12 2 1 BlockDiagram 2 p Iu e 12 2 2 25555355552 eer ee re 13 2 3 CPU Engines Virtual 5 sesso nn ha m Rx XR ERU ERE ERE E RR a ees 14 2 3 1 Engine
10. 65 AT8030 User s Guide Hardware Management Type 14 Atca Point to Point Connectivity Record Link Designator Bits 11 0 141h Fabric Interface Channel 1 Port 0 Link Descriptor 00102F42h Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 1h Fixed 10GBASE BX4 XAUI Link Type Bits 19 12 02h PICMG 3 1 Ethernet Fabric Interface F42h Fabric Interface Channel 2 Port 0 1 2 3 Link Descriptor 00102142h Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 Oh Fixed 1000Base BX Link Type Bits 19 12 02h PICMG 3 1 Ethernet Fabric Interface Link Designator Bits 11 0 142h Fabric Interface Channel 2 Port 0 Link Descriptor OOOFOF81h Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 Oh None Link Type Bits 19 12 FOh OEM GUID Definition F81h Update Channel Interface 1 Port 0 all ten pairs Link Descriptor 0010214Dh Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 Oh Fixed 1000Base BX Link Type Bits 19 12 02h PICMG 3 1 Ethernet Fabric Interface Link Designator Bits 11 0 14Dh Fabric Interface Channel 13 Port 0 Link Descriptor 0010214Eh Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 Oh Fixed 1000Base BX Link Type Bits 19 12 02h PICMG 3 1 Ethernet Fabric Interface Link Designator Bits 11 0 1
11. FRU3 FRU4 FRU Data Information Table 4 71 CPU1 CPU2 Engine Board Information Area CPU1 CPU2 Engine Board Information Area Format Version 0x01 Manufacturing Date Time Based on mfg date Board Manufacturer type length Board Manufacturer KONTRON Board Name type length Calculated Board Name AT8030 CPUX Engine Calculated Board Serial Number CO type length Board Serial Number null Board Part Number type length Board Part Number null FRU FileIDtype length 0 00 FRU File ID null No more fields OxC1 Padding 0x00 Board Area Checksum Calculated CO 108 AT8030 User s Guide Hardware Management Table 4 72 CPU1 CPU2 Engine Product Information Area CPU1 CPU2 Engine Product Information Area Product Manufacturer type length Calculated Product Manufacturer KONTRON Product Name type Calculated length Product Name 8030 Product Part Number type length Product Part Number AT8030 CPUX Engine Product Version type Calculated length Calculated Product Version Product Serial Number type length Product Serial Number CO Product Part Number type length null null 4 5 5 Over LAN As mentioned earlier the LAN interface specifications defines how IPMI messages can be sent to and from the MMCs encapsulated in RMCP Remote Management Control Protocol packets datagrams The LAN interface is a multisession interfa
12. Slc E PE eS 14 2 3 2 Features to CPUO CPU1 amp CPU2 5 15 ii AT8030 User s Guide Table of Contents 244 Ethernet Interfaces SE pa e hes ea a e Rar 18 2 4 1 182571 Ethernet 18 2 4 2 Onboard Ethernet Switch Broadcom BCM56502 19 2 4 3 Base amp Fabric Interface Ethernet 19 2 5 Serial Interfaces isses es a ie TEN RE QE 20 2 06 AMCMezzanine s colle e err oti ra esr err 21 2 4 AEBPBA o X EE ERE NR RENT UP ALONE EM 22 2 8 Clock 22 2 9 Redundant IPMC MMC Firmware amp BootBlock 23 Installing the BOG sais xx eo PERS WE SHR ORE Bd AU o E EA E 25 3 1 22 500 EMEN TUE 25 3 144 Jumper Description ss ressa ie e RI e E E EN ER T ee 25 3 1 2 Setting Jumper amp Locations eR UHR AREE RR 25 3 2 PrOCesSO ole ete eret ee hne e ow 26 3 3 MOMORY oov NU DOS VUE S COP ELA Ne SS EAS MIO SS 26 3 3 1 CPU eng
13. Verify your boot devices Ifthe system does not start properly try booting without any other 1 0 peripherals attached including AMC adapters Make sure your system provides the minimum DC voltages required at the board s slot especially if DC power is carried by cables If you are still not able to get your board running contact our Technical Support for assistance Adapter Cables Because adapter cables come from various manufacturers pinouts can differ The direct crimp design offered by Kontron allows the simplest cable assembly All cables are available from Kontron Sales Department Storing Boards Electronic boards are sensitive devices Do not handle or store device near strong electrostatic electromagnetic magnetic or radioactive fields AT8030 User s Guide Preface Regulatory Compliance Statements FCC Compliance Statement for Class A Devices This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generated uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause
14. Test for total memory installed in the system Also Check for DEL or ESC keys to limit memory test Display total memory in the system Mid POST initialization of chipset registers Detect different devices Parallel ports serial ports and coprocessor CPU etc successfully installed in the system and update the BDA EBDA etc Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed Updates CMOS memory size from memory found in memory test Allocates memory for Extended BIOS Data Area from base memory Initializes NUM LOCK status and programs the KBD typematic rate Initialize Int 13 and prepare for IPL detection Initializes IPL devices controlled by BIOS and option ROMs Initializes remaining option ROMs Generate and write contents of ESCD in NVRam D 3 AT8030 User s Guide Checkpoint Description Log errors encountered during POST Display errors to the user and gets the user response for error Execute BIOS setup if needed requested Late POST initialization of chipset registers Build ACPI tables if ACPI is supported Program the peripheral parameters Enable Disable NMI as selected Late POST initialization of system management interrupt Check boot password if installed Clean up work needed before booting to OS Takes care of runtime image preparation for different BIOS modules Fill the free area in F000h segment with OFFh Initiali
15. 2 L7400 Addressing Space The following ranges will be used on Kontron Canada AdvancedTCA boards e 1 0 0080 0081hfor 16 bit postcodes e 1 0 0200 020Fhto reserve permanently 32 locations in 1 0 space for on board resources e 1 0 0378 037Ahhidden legacy LPT port for Xilinx JTAG programmer Not all those I O locations are used but the LPC bridge will answer the cycle in zero wait state B 2 1 Summary of On board Registers Those registers are physically implemented in the AT8030 FPGA Address Function 80 81h 378 37Ah 600 7FFh in case of hardware conflict possible alternate addresses are e LPT1 378 37Ah e LPT2 278 27Ah e LPT3 3BC 3BFh B 2 AT8030 User s Guide IPMC LPC Addressing Space This function has a dual interface At all time all statuses are readable by the IPMC and by the main processor Only one side can write into the interface Bit IFSEL is used to select which processor can write to the interface Bit IFSEL is part of the interface all processors can read its status but only the IPMC can write into it With the exception of bit IFSEL and the Event amp Alarm register both sides of the interface are identical B 3 AT8030 User s Guide B 3 1 Registers Summary Offset Function 00 TelClock0 Backplane Clock Status amp Interface select 01 TelClock1 DPLL control amp status 02 TelClock2 AMCs Clock Enables amp Frequency select
16. 2 3 2 4 Onboard Storage Each CPU engine includes a USB mass storage controller ST72681 attached to 16 Gb of NAND Flash memory The BIOS supports this as a boot device This device is available for any OS that supports the standard USB mass storage interface Note These Flash memories should be used in read only to preserve their memory life 17 AT8030 User s Guide Board Features 2 3 2 5 Real Time Clock amp NVRAM The AT8030 is a battery less board The real time clock and non volatile RAM integrated in the 3100MCH are powered by the suspend power when available A double layer SuperCap powers CPUOs RTC and NVRAM when the suspend power 15 absent The SuperCap will keep the real time clock running for a typical duration of 2 hours after 10 years The real time clock precision is 27ppm or better Although itis possible to save the CMOS setup in NVRAM or CMOS RAM the default configuration saves the setup in flash So when the AT8030 are unpowered for too long only the time and date will be lost 2 3 2 6 Redundant BIOS Flash Two BIOS flash firmware hub or FWH per CPU engine are present on the AT8030 If a BIOS update corrupts a flash and prevents the CPU from completing the boot sequence the MMC will force a reboot from the other BIOS flash Note Since the CMOS setup is saved in flash this will also restore the previous BIOS setup iat BIOS Settings 0101 Management gt System Information gt FWH In Use E
17. 2 Carefully engage the AMC into the card guide Push the AMC until it fully mate with its connector Secure the AMC handle to the locking position 3 In normal condition the blue LED shall turn ON as soon as the AMC is fully inserted It will turn OFF at the end of the hot swap sequence 3 5 4 Removing an To remove an AMC 1 Pull out the handle to unlock the AMC 2 Waitforthe blue LED to turn on continuously 3 Pull out the AMC using the handle 3 5 5 Installing the RTM8030 To install the RTM 1 Remove the filler panel of the slot 2 Ensurethe board is configured properly 3 Carefully align the PCB edges in the bottom and top card guide 4 Insertthe board in the system until it makes contact with the CPU board 5 Using both ejector handles engage the board in the CPU board connectors until both ejectors are locked 6 Fasten screws at the top and bottom of the faceplate 3 5 6 Removing the RTM8030 To remove the RTM 1 Unscrewthe top and the bottom screw of the faceplate 2 Unlockthe lower handle latch 3 Waituntil the blue LED is fully ON this mean that the hot swap sequence is ready for board removal 4 Use both ejectors to disengage the board from the CPU board 5 Pull the board out of the chassis 32 AT8030 User s Guide 4 Hardware Management 4 1 Hardware Management 34 4 2 Hardware Management Architecture on Front Blade Unit 34 4 3
18. 26 Onboard Interconnectvity 29 Board Hot Swap and Installation 31 24 AT8030 User s Guide Installing the Board 3 Installing the Board 3 1 Setting Jumpers 3 1 1 Jumper Description Table 3 1 Jumper Description Description Watchdogs Disable JP1 1 2 Shelf Manager Override JP1 3 4 IPMIOverride JP1 5 6 AMC Override JP1 7 8 AMC PCIe Override JP1 9 10 Postcodes Display JP1 11 12 Flash Drive Write Protect JP1 13 14 FWHs top block Protect JP2 1 2 FPGA PROM Selection JP2 3 4 Clear CMOS Setup JP2 5 6 BIOS Recovery JP2 7 8 Reserved 1 JP2 9 10 Reserved 2 2 11 12 Reserved 3 2 13 14 3 1 2 Setting Jumper amp Locations Figure 3 1 Setting Jumpers amp Locations JUMPER SETTINGS 9 Default Setting JP1 1 2 Watchdogs Disable JP2 1 2 FWHs top block protect in Unprotected Enabled out Normal protected 9 JP1 3 4 Shelf Manager Override 2 3 4 FPGA PROM Selection Override in Factory Prom m Normal Operation out Normal 2 JP1 JP2 J3 JP1 5 6 Override 2 5 6 Clear CMOS Setup GD EXE Override in Reserved n m Normal Normal Operation out g5 JP1 7 8 AMC Override 2 7 8 BIOS Recovery Override in Recovery Mode E Normal Operation out Normal Operation J6 24 JP1 9 10 Reserved
19. ICMB ICMB ICMB ICMB ICMB ICMB ICMB Bridge Bridge Bridge Bridge Bridge Bridge Bridge Bridge Bridge Bridge Bridge Bridge 02h 03h 04h 05h 06h 09h OCh 97 AT8030 User s Guide Hardware Management Table 4 60 Discovery ICMB Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req 0 Discovery Commands ICMB 2 0 Prepare For Discovery ICMB Bridge 10h 0 M No Get Addresses ICMB Bridge 11h 0 M No Set Discovered ICMB Bridge 12h 0 M Get Chassis Device ID ICMB Bridge 13h 0 M Set Chassis Device ID ICMB Bridge 14h 0 M No No No Table 4 61 Bridging ICMB Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC Bridging Commands 0 0 ICMB 2 Bridge Request ICMB Bridge 20h 0 M 0 No Bridge Message ICMB Bridge 21h 0 M 0 No Table 4 62 Event ICMB Commands for MMC built in NetFn Ir Kontron support on req MMC Event Commands ICMB 0 2 0 0 Get Event Count ICMB Bridge 30h 0 M No Set Event Destination ICMB Bridge 31h 0 M 0 No Set Event Reception State Send ICMB Event Message Get Event Destination ICMB Bridge 34h 0 M No Get Event Reception State ICMB Bridge 32h 0 M 0 No ICMB Bridge 33h 0 M No ICMB Bridge 35h 0 M No
20. AT8030 User s Guide Aivancea Document Revision 1 2 May 2009 S kontron Revision History Rev Index Brief Description of Changes Date of Issue 1 0 first release December 2007 cal second release November 2008 1 2 third release May 2009 Customer Service Contact Information Kontron Canada Inc Kontron Modular Computer GMBH 4555 Ambroise Lafortune Sudetenstrasse 7 Boisbriand Qu bec Canada 87600 Kaufbeuren J7H 0A4 Germany Tel 450 437 5682 49 0 8341 803 333 800 354 4223 Fax 450 437 8053 49 0 8341 803 339 E mail support ca kontron com support kom kontron com Visit our site at www kontron com 2009 Kontron an International Corporation All rights reserved The information in this user s guide is provided for reference only Kontron does not assume any liability arising out of the application or use of the information or products described herein This user s guide may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Kontron nor the rights of others Kontron is a registered trademark of Kontron All trademarks registered trademarks and trade names used in this user s guide are the property of their respective owners All rights reserved Printed in Canada This user s guide contains information proprietary to Kontron Customers may reprint and use this user s guide in other
21. Boot from USB 2 0 Floppy CD ROM Hard Disk Flash Auto configuration and extended setup BIOS Features Diskless Keyboard less and battery less operation extensions System and LAN BIOS shadowing Advanced Configuration and Power Interface ACPI 1 0 amp 2 0 Console redirection to serial port VT100 with CMOS setup access Field updateable BIOS Event SERR PERR correctable uncorrectable ECC POST errors PCI Express log support to the management controller Management Controller compliant to 0 R2 0 IPMI v1 5 rev 1 1 Management Controller is run time field reprogrammable without payload impact Robust fail safe bootblock implementation Remote upgrade capability from all IPMI interfaces Host Interface IPMB 0 LAN compliant to HPM 1 Fast interrupt driven SMS host interface compliant to IPMI KCS v1 5 rev 1 1 Gracefull shutdown support via ACPI IPMIWatchdog supporting FRB2 POST OS Load and 5 5 05 watchdog with interrupt on pretimeout IPMI v2 0 IOL and Serial Over Lan support on base interface FRU Inventory Area support SENSOR device support Supports a system management interface via an IPMI V1 5 compliant controller Watchdog for BIOS execution and OS loading through IPMT Hardware system monitor voltages temperature CPU temperature monitor alarm board temperature sensor power failure through the management controller IPMI Features Supervisory 5 AT8030 User s Guide Product Description 1 5 Board S
22. Features 1 1b Connected through PLL 0 1b Clock Source Descriptor 2 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 1b Clock Source Descriptor 3 Dependent ClockId 3 Direct clock Descriptor none Clock Id 0x08 Receiver input from TCLKB 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Clock Control 0x01 88 AT8030 User s Guide Hardware Management Type 2D Clock Configuration Record 7 2 Oh reserved Features 1 1b Connected through PLL 0 Ob Clock Receiver Descriptor 0 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 Ob Clock Receiver Descriptor 1 Dependent ClockId 5 Direct clock Descriptor none Clock Id 0x09 Receiver input from TCLKD 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Clock Control 0x01 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor 4 e n e e o c 7 2 Oh reserved Features 0x02 1 1b Connected through PLL 0 Ob Clock Receiver Dependent ClockId 7 2 Oh reserved Features 0x02 1 1b Connected through PLL 0 06 Clock Receiver Dependent ClockId Direct clock Descriptor none Clock Descriptor 1 4 4 4 Over LAN Onthe Ethernet Switch the IPMI O
23. Hardware Management Type 2C Carrier Clock Point To Point Connectivity Record Header Remote Clock Id 0x05 0 2 0 FCLKA clock Remote Clock Resource Id 0 45 7 6 01b Clock Resource Id 0x00 7 6 00b On Carrier device Remote Clock Id Ox01 1 Remote Clock Resource Id 0x80 7 6 10b Backplane clock Remote Clock Id 0x04 CLK2A Remote Clock Resource Id 0x80 7 6 10b Backplane clock Remote Clock Id 0x05 CLK2B Remote Clock Resource Id 0x80 7 6 10b Backplane clock 82 AT8030 User s Guide Hardware Management Type 2C Carrier Clock Point To Point Connectivity Record Header Remote Clock Id 0x08 Remote Clock Resource Id 0x80 27 6 10b Backplane clock 5 4 Oh reserved 3 0 0h Point to Point Clock Connection descriptor Local Clock Id 0x06 Remote Clock Id 0x01 Remote Clock Resource Id 0x45 7 6 016 5 4 Oh reserved 3 0 AMC Site Number 5 AMC B1 Point to Point Clock Connection descriptor Local Clock Id 0x07 Remote Clock Id 0x02 Remote Clock Resource Id 0x45 7 6 016 5 4 Oh reserved 3 0 AMC Site Number 5 AMC B1 Point to Point Clock Connection descriptor Local Clock Id 0x08 Remote Clock Id 0x03 Remote Clock Resource Id 0x45 7 6 01b 5 4 Oh reserved 3 0 AMC Site Number 5 AMC B1 Point to Point Clock Connection descriptor Local Clock Id 0x09 Remote Clock Id 0x04 Remote Clock Resource Id 0x45 7 601
24. JP2 9 10 Reserved 1 m Reserved in Reserved in Normal Operation out Normal Operation out JP1 11 12 Postcodes Display JP2 11 12 Reserved 42 Reserved in Reserved in BIOS postcodes out Normal Operation out JP1 13 14 Flash Drive write protect JP2 13 14 Reserved 3 Enabled Reserved in Disabled Normal Operation Note More details about the jumper settings can be found on the Quick Reference Sheet 25 AT8030 User s Guide Installing the Board 3 2 Processor This product ships with the CPUs and a thermal solution installed Because the thermal solution is custom and critical for passive cooling Cooling performance can greatly be affected if manipulation is not handled within Kontron facility 3 3 Memory The CPU engines use 240 pins 25 degree DIMM sockets They are interfaced through a single memory channel that supports registered ECC x4 or x8 memory CPU engines 1 amp 2 provide only one DIMM while CPU engine 0 provides 2 DIMM DDR2 400 1 8 V max 1 2 inches high registered DIMMs must be used The maximum DDR2 SDRAM size is 8 GB for CPU engine 0 and 4GB for CPU engine 1 and 2 The minimum size of SDRAM is 512 MB using a single 512 Mbit technology DIMM 9x8 DRAMs The CPU engines support single sided and dual sided single dual rank memory modules This gives a possibility of 4 ranks for CPU 0 and 2 ranks for CPU1 amp 2 The PowerQuicc III has
25. Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Channel Descriptor OFFFFE3h Update Channel Reserved Bits 23 20 0 Lane 3 Port Number Bits 19 15 1 0 0 Lane 0 Port Number Bits 4 0 01 AMC Channel Descriptor OFFFFE2h Update Channel 0 02 79 AT8030 User s Guide Hardware Management Type 19h AMC Point To Point Connectivity Record 2 of 2 On Carrier Update Channel Switcher 4 4 3 5 IPMC FRU 0 Clock Ekeying Information The clock ekeying is used to find and activate matching clock pairs to from available clock sources and clock receivers The Front Blade Unit hardware implementation specification provides an overview of the clock synchronization structure The carrier has a clock generator to be used as the PCIe FCLKA of AMC B1 Additionally clocks from to the AdvancedTCA backplane can be driven to from the AMC B1 site using an on carrier clock multiplexer 80 AT8030 User s Guide Hardware Management Table 4 43 Carrier Clock Resource Ids assignment table Carrier Clock Resource Ids 0 PCIe Clock Generator 1 Clock Multiplexer As the following tables indicate match making and clock activation responsibility is split between the Carrier IPMC and the Application As an exclusive local resource PCIe clock generator clocks are matched and activated by the Carrier IPMC However shared clocks such as AdvancedTCA backplane clocks require control by t
26. The Unit Computer DDR2 SDRAM memory is assembled on a SO CDIMM The SO CDIMM is an upcoming JEDEC standard that uses the DDR2 SODIMM envelope but modifies the pinout in order to add ECC support This means that the bus width supported is 64 bits plus 8 bits for ECC The DDR2 SDRAM module is clocked at 200Mhz The design supports modules of 512MB This memory module consists of 9 CMOS DDR2 SDRAM chips Standard DDR2 SODIMM are not supported Memory should have the following characteristics DDR2 400 1 8V only Single sided or double sided e 1layer of BGA on side e X8 configuration supported Serial Presence Detect SPD EEPROM 72 bit DIMMs only e 1 2 inch maximum height WARNING Because static electricity can cause damage to electronic devices take the following precautions Keep the board in its anti static package until you are ready to install memory Wear a grounding wrist strap before removing the board from its package this will discharge any static electricity that may have built up in your body Handle the board by the faceplate or its edges 27 AT8030 User s Guide Installing the Board 3 3 3 Installing Memory Figure 3 2 Installing Memory anti static plane place the board so that you are facing the memory sockets Insert the memory module into any available Socket aligning the notches on the module with the socket s key inserts Push down the memory mod
27. Voltage on CPU VCCA Sensor type 02h Voltage Event Reading type code O1h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 1 58v 596 Lower Critical Event 1 42v 596 Hysteresis 0 025v 1 590 Board reset type and sources Sensor type OEM Kontron Reset Sensor Event Reading type code 03h Digital Discrete offset 0 1 are used see table sws 10 1177 for event trigger information 103 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name BX Boot Error BX POST Value BX POST Error BX Critical Int BX Memory BX Cmos Mem Size Description Sensor Type Event trigger CPU Boot Error Sensor type 1Eh Boot Error Event Reading type code 6Fh Sensor specific only offset 0 is used offset 0 event trigger No bootable Media see IPMI v1 5 table 36 3 Sensor type code 1Eh Boot Error for sensor definition Show current postcode value No event generated by this sensor Sensor type C6h OEM Kontron POST value sensor Event Reading type code 6Fh Sensor specific offset 0 to 7 and 14 are used see table sws 10 1140 for event trigger information CPU Power On Self Test Error Sensor type OFh System Firmware Progress Event Reading type code 6Fh Sensor specific only offset 0 is used offset 0 event data 2 00 unspecified event trigger CMOS Setting Wrong CMOS checksum bad CMO
28. see table sws 10 1139 for event trigger information EventRcv ComLost IPMI Watchdog IPMC Link State FRUO IPMBL State FRU1 IPMBL State FRU2 IPMBL State FRU3 IPMBL State FRU4 IPMBL State FRU5 IPMBL State General health status Aggregation of critical sensor This list is flexible and could be adjust based on customer requirements Sensor type 24h Platform Alert Health Error Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger no critical sensors is asserted offset 1 event trigger one or multiple critical sensors are asserted see IPMI v1 5 table 36 3 Sensor type code 24h for sensor definition 56 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name FRU Over Icc FRU Sensor Error FRU Pwr Denied FRUO Agent FRU1 Agent FRU5 Agent IPMC Storage Err IPMC Reboot Ver change Description Sensor Type Event Trigger FRU OEM Over Current Sensor type CBh OEM Kontron FRU Over Current Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger no Over Current offset 1 event trigger Over Current detected see table sws 10 1174 for event trigger information FRU Error during external FRU Sensor discovery Sensor type CCh OEM Kontron FRU sensor error Event Reading type code 03h Digital Discrete offset 0 1 are used see table sws 10 1175 for event trigger information FRU is notallowed to p
29. set bootstopkey must be used This resets the bootstopkey and the boot process can not be interrupted The command gt set bootstopkey reinitiates the key stop as bootstopkey For additional information about the CLI refer to the CLI Reference Manual G 5 AT8030 User s Guide Getting Help If at any time you encounter difficulties with your application or with any of our products or if you simply need guidance on system setups and capabilities contact our Technical Support at North America Tel 450 437 5682 Fax 450 437 8053 EMEA Tel 49 0 8341 803 333 Fax 49 0 8341 803 339 If you have any questions about Kontron our products or services visit our Web site at www kontron com You also can contact us by E mail at North America support ca kontron com EMEA support kom kontron com Or at the following address North America Kontron Canada Inc 4555 Ambroise Lafortune Boisbriand Qu bec J7H 0A4 Canada EMEA Kontron Modular Computers GmbH Sudetenstrasse 7 87600 Kaufbeuren Germany AT8030 User s Guide 1 Returning Defective Merchandise Before returning any merchandise please do one of the following all Fax E mail Call our Technical Support department in North America at 450 437 5682 and in EMEA at 49 0 8341 803 333 Make sure you have the following on hand our Invoice your Purchase Order and the Serial Number of the defective u
30. 1 590 Voltage on 1 2v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 forthreshold base event Upper Critical event 1 26v 5 Lower Critical Event 1 14v 596 Hysteresis 0 018v 1 596 Voltage on 1 25v board power supply Sensor type 02h Voltage Event Reading type code O1h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 Vcc 1 25 for threshold base event Upper Critical event 1 312v 5 Lower Critical event 1 187v 5 Hysteresis 0 0187v 1 5 Voltage on 1 5v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for Vcc 1 5V threshold base event Upper Critical event 1 58v 5 Lower Critical event 1 42v 5 Hysteresis 0 025v 1 5 Voltage on 1 8v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for Vcc 1 8V threshold base event Upper Critical event 1 89v 5 Lower Critical event 1 71v 5 Hysteresis 0 027v 1 5 Voltage on 2 5v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for Vcc 2 5V threshold ba
31. Ctrl alt del keys During BIOS POST enter BIOS Setup Menu by typing Del key In BIOS Setup Menu make sure to select BIOS Optimal Default Settings by typing F9 key E 2 AT8030 User s Guide E 3 Updating the switch The following procedure describes the firmware update of the board 1 2 Prepare network access of the board see previous chapters Log in to the privileged exec mode of the CLI ofthe board Check availability of valid boot image in slot 1 using the command Ethernet Fabric show bootvar Copy new correct image for example initrd2 pkg into slot 2 using the CLI command Ethernet Fabric tftp IP address initrd2 pkg image2 Select the second boot image to be used for next boot with the command Ethernet Fabric boot system image2 Reboot system Ethernet Fabric reload System will start using image 2 Check with Ethernet Fabric show bootvar In case of having updated with a corrupted image the AT8030 should try to boot twice the corrupted image and for the third time boot it should recover to image 1 to boot the system Check with Ethernet Fabric show bootvar E 3 AT8030 User s Guide F Supported RFCs and MIBs F 1 Supported RFCs The Software supports the following standards and RFCs F 1 1 Management RFC 826 ARP RFC 854 Telnet RFC 855 Telnet Option RFC 1155 SMI v1 RFC 1157 SNMP RFC 1212 Concise MIB Definitions RFC 1867 HTML 2
32. Frequency Selection EN gt 02h Read B2TCF B2TAF B2TCEN B2TAEN B1TCEN B1TAEN Write B2TCF B2TAF B2TCEN B2TAEN PowerUp 0 0 0 0 0 0 also forced to 0 when the corresponding is fault or extracted B1TAEN AMC B1 TCLKA Enable 1 drive AMC B1 clock TCLKA 0 don t drive AMC B1 TCLKA B1TCEN AMC B1 TCLKC Enable 1 drive AMC B1 clock TCLKC 0 don t drive AMC B1 TCLKC B1TAF AMC B1 TCLKA Frequency 1 use 8kHz frame pulse from PLL 0 use 19 44MHz from PLL B1TCF AMC B1 TCLKC Frequency 1 use 8kHz frame pulse from PLL 0 use 19 44MHz from PLL B2 Reserved for AMC B2 for boards that have two AMCs B 6 AT8030 User s Guide Note about the 8kHz frequency If the clock source of the is 19 44MHz the phase of this clock is unrelated to any other 8kHz clock in the system Also note that the AMC has to be present and fully powered for the enable bits to be settable On a surprise extraction user doesn t wait for the blue LED the hardware automatically clears bits B1TCEN and B1TAEN in case a user would extract and re insert immediatly the AMC B 3 5 TelcoClock3 PLD Configuration amp Version ee eee Read PLD_CONFIG PLD_VERSION Write PowerUp PLD_CONFIG Circuit configuration that the PLD expect For the interface and circuit described in this document this field is always 0000 PLD_VERSION Code
33. Memory Sockets Size Rank DIMM 1 Memory Size 1024MB Double DIMM 2 Memory Size 1024MB Double DDR2 Speed 400 MHz Single Channel Mode 2048MB OK USB Device s 1 Storage Device The main menu of the AMI BIOS CMOS Setup Utility appears on the screen This example is based on CPUO BIOS Setup Menu Figure 5 1 Example of BIOS Setup Menu BIOS Setup Utility Main Advanced Security Boot System Management Exit System Overview Item Specific Help BIOS Version Boot Block Version CPU Engine DIMM 1 Memory Size 1 GB DIMM 2 Memory Size 1 GB System Memory Speed 400 MHz System Memory 642 KB Extended Memory 2048 MB Select Screen Select Item System Time 15 00 03 Change Field System Date 09 08 2006 Select Field General Help Save and Exit Exit Setup Default values provide optimum performance settings for all devices and system features Note 4 The CMOS setup option described in this section is based on BIOS Version 2 00 The options and default settings may change in a new BIOS release CAUTION These parameters have been provided to give control over the system However the A values for these options should be changed only if the user has a full understanding of the timing relationships involved gt 117 AT8030 User s Guide Software Setup Note 22 AlLoptions in Bold are the default settings 5 1 2 Menu Bar The Menu Bar at the top of the window lists these selections Table 5 1 BIOS Menu Bar Men
34. Select serial port for console redirection Serial Port 11 0 address 3F8 IRO4 N A display only Serial Port 2 1 0 address 2F8 IRQ3 N A display only Configures serial port Baud rate for both serial Select serial port Baud Pauc Rete ports rate Configures the number of data bits in each transmitted or received serial character for Data Bits both serial ports 8 Note Serial Over LAN operation uses fixed parameter Data Bits 8 Select the number of data bits in each transmitted or received serial character Select if parity bit is generated transmit data or checked receive data between the last data word bit and stop bit ofthe serial data Configures if parity bitis generated transmit data or checked receive data between the last data word bit and stop bit ofthe serial data for both serial ports Note Serial Over LAN operation uses fixed parameter Parity None Configures the number of stop bits transmitted and received in each serial character for both Stop Bits serial ports Note Serial Over LAN operation uses fixed parameter Stop Bits 1 Select the number of stop bits transmitted and received in each serial character Hardware Flow Control Software None ANSI Terminal Type VT100 VTUTF8 Terminal Size Displays terminal size N A display only Configures flow control for console redirection Select flow control for for both serial ports console redirection Configures the ty
35. Sensor type F1h PICMG Physical IPMB 0 Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 8 4 2 for event trigger and sensor definition IPMB L branch from FRUO fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information IPMB L branch from FRU1 fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information IPMB L branch from FRU2 fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information IPMB L branch from FRU3 fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information IPMB L branch from FRU4 fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information IPMB L branch from FRUS fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used
36. Set Watchdog Timer 21 6 App Get Watchdog Timer 21 7 App 91 AT8030 User s Guide Hardware Management Table 4 49 Device Messaging Supported Commands for builtin MMC IPMISpec section NetFn BMC Device and Messaging Commands 5 Set BMC Global Enables 18 1 Get BMC Global Enables 18 2 Clear Message Flags 18 3 Get Message Flags 18 4 Enable Message Channel 1 Receive Get Message 18 6 Send Message 18 7 8 5 Read Event Message Buffer Get BT Interface Capabilities Master Write Read 18 10 Get System GUID 18 13 Get Channel Authentication Capabilities 18 8 18 9 Carrier IPMC Kontron support on req MMC CMD IPMI BMC req Get Session Challenge 18 14 App 39h Activate Session 18 15 App 3Ah Set Session Privilege Level 18 16 App Close Session 18 17 App Get Session Info 18 18 App Get AuthCode 18 19 Ap 0 0 No 0 0 No 3Bh 0 0 No 3Ch 3Dh 3Fh e No No N ojo 0 Set Channel Access 18 20 App 40h N Get Channel Access 18 21 App 41h No Get Channel Info 18 22 App 42h No Set User Access 18 23 Get User Access 18 24 Set User Name 18 25 App Get User Name 18 26 App Set User Password 18 27 App Activate Payload 24 1 2 0 Deactivate Payload 24 2 IPMI2 0 App Get Payload Activation Status Get Payload Instance Info 24 4 IPMI 2 0 App 24 5 IPMI 2 0 App App 43h App 44h e No No 45
37. 03 h h h B 3 2 00 TelClockO Backplane Clock Status PLL Reference amp Interface Selection NN 00h Read IFSEL MAN SEL REFA REF CLK2B CLK2A CLK1B CLK1A Write IFSEL MAN in BP REF NU NU NU NU PowerUp 0 0 0 0 NA NA NA NA CLK1A B CLK2A B Coarse monitoring status A 1 indicate that the corresponding backplane clock is present A 0 that itis absent Those statuses are valid only if CLK1A B is 8kHz and CLK2A B is 19 44MHz If other frequencies are used those bits should be ignored BP REF Backplane set of clock to connect to the PLL 0 Use backplane CLK1A and CLK1B 8kHz 1 Use backplane CLK2A and CLK2B 19 44MHz SEL read SEL REFM write On a read return the reference automatically selected by the PLD 0 REFO is the reference used by the PLL i e CLKA 1 REF1 is the reference used by the PLL i e CLKB When bit MAN 1 the application software can select the reference by writting the desired value in this bit This bit is not writtable when MAN 0 Note that on a read this bit return the automatic selection even if MAN 1 MAN 0 The PLD choose automatically the reference use by the DPLL CLKA or B 1 Selection of the DPLL reference is manual Write the selection in bit SEL_REF B 4 AT8030 User s Guide IFSEL Interface selection This bitis always writable from the IPMC side but on the LPC side the C
38. 1 Internal mismatch Bit 0 Match Error Not in single link matches Bit 0 Match Error Not in single link matches 37 AT8030 User s Guide Hardware Management Table 4 3 Kontron OEM IPMB L Link Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset IPMB L Disable Event Data 2 always 0 Event Data 3 bit 7 3 always 0 bit 2 0 Oh no failure 1h Unable to drive clock HI 2h Unable to drive data HI 3h Unable to drive clock LO 4h Unable to drive data LO 5h clock low timeout 6h Under test the IPM Controller is attempting to determine who is causing a bus hang 07h Undiagnosed Communication Failure IPMB L Enable Event Data 2 always 0 Event Data 3 bit 7 3 always 0 bit 2 0 Oh no failure 1h Unable to drive clock HI 2h Unable to drive data HI 3h Unable to drive clock LO 4h Unable to drive data LO 5h clock low timeout 6h Under test the IPM Controller is attempting to determine who is causing a bus hang 07h Undiagnosed Communication Failure 6Fh C3h Standard IPMI OEM Kontron sensor specific IPMB L Link Table 4 4 Kontron OEM POST Code Value Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 00h to 07h POST code LOW byte value no event genarated on these 6Fh C6h offsets Standard IPMI OEM Kontron POST Code Error Event Trigger sensor specific POST Code Value Event Data 2 POST Low
39. 13 3 for threshold base event Upper Non Critical event 65 C After Thermal Analysis Upper Critical event 75 C After Thermal Analysis Upper Non Recoverable 90 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis 52 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Temp PQ3 Temp Dual Phy Se Temp LSI SAS Dis Temp Mez 12v Out Temp 48 A Feed Description Sensor Type Event Trigger PQ3 Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 75 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 100 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Dual PHY SERDES Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 80 C After Thermal Analysis Upper Critical event 90 C After Thermal Analysis Upper Non Recoverable 105 C After Thermal Analysis Hysteresis 2 deg C value can be adjusted after thermal analysis Dual LSI SAS Disc Temperature Sensor type 01h temperature Event Reading type code 01h threshol
40. Adjust policies and cache first 8MB Set stack 5 D Bootblock code is copied from ROM to lower system memory and control is given to it BIOS now executes out of RAM Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced Main BIOS checksum is tested If BIOS recovery is necessary control flows to checkpoint EO See Bootblock Recovery Code Checkpoints section of document for more information D7 Restore CPUID value back into register The Bootblock Runtime interface module is moved to system memory and control is given to it Determine whether to execute serial flash 8 The Runtime module is uncompressed into memory CPUID information is stored in memory 9 D Store the Uncompressed pointer for future use in PMM Copying Main BIOS into memory D Leaves all RAM below 1MB Read Write including E000 and F000 shadow areas but closing SMRAM DA Restore CPUID value back into register Give control to BIOS POST ExecutePOSTKernel See POST Code Checkpoints section of document for more information OEM memory detection configuration error This range is reserved for chipset vendors amp system manufacturers The error associated with this value may be different from one platform to the next Refer to memory initialization ERROR CODE D 5 D 1 AT8030 User s Guide D 2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery
41. After Thermal Analysis Hysteresis 2 deg C value can be adjusted after thermal analysis LSI SAS Controller Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 85 C After Thermal Analysis Upper Critical event 95 C After Thermal Analysis Upper Non Recoverable 110 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Voltage on the memory 1 05 Sensor type 02h Voltage Event Reading type code 01h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 1 11v 10 Lower Critical Event 0 99v 1090 Hysteresis 0 016v 1 590 CPU Core Voltage Sensor type 02h Voltage Event Reading type code 01h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical Event 1 03 Vmax vid Lower Critical Event 0 97Vmin vid Hysteresis 0 015v 1 596 Voltage on 1 5v suspend management board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 1 58v 590 Lower Critical Event 1 42v 596 Hysteresis 0 025v 1 590
42. Appendix D BIOS Setup Error Codes e Appendix Software Update e Appendix Supported and MIB Appendix G Bootloader Appendix Getting Help xiii AT8030 User s Guide Preface Customer Comments If you have any difficulties using this user s guide discover an error or just want to provide some feedback please send a message to Tech Writer g ca kontron com Detail any errors you find We will correct the errors or problems as soon as possible and post the revised user s guide on our Web site Thank you Advisory Conventions Seven types of advisories are used throughout the user guides to provide helpful information or to alert you tothe potential for hardware damage or personal injury They are Note Signal Paths Jumpers Settings BIOS Settings Software Usage Cautions and Warnings The following is an example of each type of advisory Use caution when servicing electrical components Note Indicate information that is important for you to know Signal Path Indicate the places where you can fin the signal on the board Jumper Settings Indicate the jumpers that are related to this sections BIOS Settings Indicate where you can set this option in the BIOS Software Usage Indicates how you can access this feature through software WARNING Indicates potential for bodily harm and tells you how to avoid the problem CAUTION Indicate potential damage to hardware and tells you how to
43. B169 B42 12V B84 12V B127 RxD14 170 GND B85 GND B128 GND C 9 Power P10 Pin Signal 2 N P 4 N P HAO 6 1 2 8 HA4 10 HA5 HA6 12 HA7 P IPMBA_SCL 14 SDA_A SCL_B 16 SDA_B N C 18 N C N C 20 N C N C 22 N C N C 24 N C SHELF_GND 26 LOGIC_GND ENABLE_B 28 VRTN_A VRTN_B 30 EARLY_A EARLY_B 32 ENABLE_A 48V_A 34 48V_B C 7 AT8030 User s Guide D BIOS Setup Error Codes D 1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset memory and other components before system memory is available The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS Checkpoint Description Early chipset initialization is done Early super I O initialization is done including RTC and keyboard controller NMI is disabled D1 Perform keyboard controller BAT test Check if waiking up from power management suspend state Save power on CPUID value in scratch CMOS 0 Go to flat mode with 4GB limit and GA20 enabled Verify the bootblock checksum D D Before D1 Disable CACHE before memory detection Execute full memory sizing module Verify that flat mode is enabled 2 If memory sizing module not executed start memory refresh and do memory sizing in D3 Bootblock code Do additional chipset initialization Re enable CACHE Verify that flat mode is enabled D4 Test base 512KB memory
44. Blade Unit Default User for 5 51 111 LAN Parameters CR Ie 111 BIOS Men iBatzz ETE REESE E MEN SE EE 118 BIOS Legend a e d 118 ANSI VT100 Keystroke Mapping 144 VT UTF8 Keystroke 144 POST routines and error 147 POST BOOUStEPS access CL eme aed eI e ed Seale We TO 148 Temperature Sensors 10 151 Pressure curve T5006 with AMC 152 x AT8030 User s Guide Safety Instructions Safety Instructions Before You Begin Before handling the board read the instructions and safety guidelines on the following pages to prevent damage to the product and to ensure your own personal safety Refer to the Advisories section in the Preface for advisory conventions used in this user s guide including the distinction between Warnings Cautions Important Notes and Notes Always use caution when handling operating the computer Only qualified experienced authorized electronics service personnel should access the interior of the computer The power supplies produce
45. Computer Onboard Ethernet Switch RESET is separated from the Unit Computer RESET in order to provide a hitless restart function in case the Unit Computer software crashes See www broadcom com for additional details on the BCM56502 2 4 3 Base amp Fabric Interface Ethernet Base amp Fabric Interface Ethernet are implemented using a single chip Onboard Ethernet Switch 56502 Fabric Interface FI traffic is separated from Base Interface BI traffic by switch fabric configuration All GbE FI interfaces operate in SERDES mode The Zone 2 FI connection from the switch operate in 10 GbE XAUI or 1 GbE based on e keying The BI interfaces operate in SERDES mode except the two ports connected to Zone 2 of the PIGMG 3 0 backplane Those ports operate in SGMII mode An additional Dual Port 10 100 1000Base T Gigabit Ethernet Transceiver BCM5482 is required to connect the switch to Zone 2 of the PIGMG backplane The Base Interface Ethernet has the following connections to from the Onboard Ethernet Switch Two 10 100 1000Base T connections to the Base Interface in Zone 2 of the PIGMG 3 0 backplane One 1000Base BX connection to the RTM through Zone 3 One 1000Base BX connection to the Unit Computer One 1000Base BX connection to CPU 0 One 1000Base BX connection to CPU 1 One 1000Base BX connection to CPU 2 One 1000Base BX connection to AMC B1 The Fabric Interface Ethernet has the following connections from the
46. Controller of each CPU to receive IPMI Over LAN command and send Serial Over LAN data to the two base interface channels The Fabric Interface is two XAUI 10G Base CX4 links The Zone 3 connector RTM Interface has three GbE linkthat come from the Base interface switch the fabric interface switch and the PowerQuicc Within PICMG wording the RTM is an intelligent FRU of the blade which means it includes an IPMI Controller The interface to that RTM IPMI Controller is IPMB L and is accessible from the IPMC as a regular AMC A serial port connector is also available on the RTM and is connected to the desired CPU using a rotary switch 34 AT8030 User s Guide Hardware Management 4 3 Hardware Management Functionality The Front Blade Unit supports an intelligent hardware management system based on the Intelligent Platform Management Interface Specification The hardware management system of the Front Blade Unit provides the ability to manage the power and interconnect needs of intelligent devices to monitor events and to log events to a central repository 4 3 1 IPMC specific features 4 3 1 1 IPMC ShMC interface The principal management oriented link within a Shelf is a two way redundant implementation of the Intelligent Platform Management Bus IPMB IPMB is based on the inter integrated circuit I2C bus and is part of the IPMIarchitecture AdvancedTCA Shelves the main IPMB is called 0 Each entity att
47. Description 1 4 Board Specifications CPUO Section Table 1 2 Board Specifications CPUO Section Features Description One 1 5 GHz Intel LV 17400 dual core processor Passive heatsink 32KB L1 instruction and 32KB L1 data cache dedicated for each core 4MB L2 cache on each processor chip shared by both cores Processors Cache Memory Chipset Embedded Northbridge MCH and Southbridge ICH Intel 3100 CPUs Front Side bus at 667 MHz 64 bit data 36 bit address Single channel DDR2 Registered ECC at 400 MHz One x8 configurable PCI express port 2x4 mode Four x1 configurable PCI express port 4x1 mode 1 Mid size AdvancedMC bay AMC 1 x4 PCIExpress Expansion Slot 2 Common Options Type E2 Dual GbEthernet Fat pipes options Type 4 Quad GbEthernet AMC 3 Dual port SAS Up to 8 GB on 2x240 pin latching DDR 2 400MHz SDRAM PC2 3200 System Memory ECC support support SEC DED 512Mbit 1Gbit or 2Gbit Technology Two redundant 1MB BIOS Field software upgradeable Roll back functionality controlled by the management controller 2 ports SAS available through AdvancedMC modules or through Rear 1 0 2 GB USB FLASH drive Bus Interfaces BIOS Storage Storage 4 AT8030 User s Guide Product Description Features Description 1 selectable Serial Port RJ 45 Connectors 2 USB 2 0 2 GbE ports RJ 45 AMI BIOS Save CMOS in NVRAM Boot from all Ethernet interfaces Boot from SAS
48. Discrete offset 0 1 are used offset 0 event trigger normal condition no resize offset 1 event trigger CMOS memory size if wrong see IPMI v1 5 table 36 3 Sensor type code OEh for sensor definition 104 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name BX PrebootPasswd BX CPU Status BX FWH 0 Error BX FWH 1 Error BX ACPI State BX IPMI Watchdog BX Health Error BX MMC FwUp Description Sensor Type Event trigger Platform Security Violation Attempt Sensor type 06h Platform Security Violation Attempt Event Reading type code 6Fh Sensor Specific offset 1 and 4 are used offset 1 event trigger Pre Boot Password Violation User password BIOS password check location is critical offset 4 event trigger Other Pre Boot Password Violation BIOS password check location is not critical see IPMI v1 5 table 36 3 Sensor type code 06h for sensor definition CPU Status Sensor type 07h Processor Event Reading type code 6Fh Sensor Specific offset 0 1 5 are used offset 0 event trigger CPU IERR offset 1 event trigger CPU Thermal Trip offset 5 event trigger Configuration Error see IPMI v1 5 table 36 3 Sensor type code 07h for sensor definition Firmware Hub Boot Error Specify if it was unable to boot from the BIOS on the Firmware Hub Sensor type 1Eh Boot Error Event Reading type code 6Fh Sensor specific only offset 3 is used offset 3 event trigger Invalid boo
49. Executes four instructions per clock cycle to improve execution speed and efficiency Each core can complete up to four full instructions simultaneously using an efficient 14 stage pipeline Intel amp Advanced Smart Cache Improves system performance by significantly reducing memory latency to frequently used data through dynamic allocation of shared L2 cache to each of the processor cores Intel Smart Memory Access Optimizes use of available data bandwidth from the memory subsystem to accelerate out of order execution A newly designed prediction mechanism reduces the time in flight instructions have to wait for data New pre fetch algorithms move data from system memory into fast L2 cache in advance of execution These functions keep the pipeline full improving instruction throughput and performance Intel Advanced Digital Media Boost Accelerates execution of SSE 2 3 instructions to significantly improve multimedia performance 128 bit SSE instructions are issued at a throughput rate of one per clock cycle effectively doubling the speed of execution on a per clock basis over previous generation processors Intel Intelligent Power Capability Manages runtime power consumption of execution cores by turning on computing functions only when needed Reduces overall power consumption enabling quieter more power efficient system designs Intel Virtualization Technology Allows one hardware platform to function as multiple v
50. FC AL Fibre Channel Arbitrated Loop C D FPL FPGA to PLD Link FPL is a 20 MHz serial link that exchange 32 bit of data in each direction between the FPGA and a companion PLD Kontron proprietary S FD Floppy Disk Drive F Fault Resilient Booting level 1 3 A term used to describe system features and algorithms that improve the likelihood of the detection of and recovery from processor failures in a multiprocessor system FRB2 Fault Resilient Booting Level 2 FRT Free Running Timer FRU FSB Front Side Bus P File Transfer Protocol E 0 FirmWare Hub Boot flash connected to the LPC bus containing BIOS FW R R S FT W A b Same as GByte GigaByte b GARP Generic Attribute Registration Protocol Gigabit Ethernet G Geographic Address B H GigaHertz GMRP GARP Multicast Registration Protocol GN GrouND GPCM General Purpose Chip select Machine GP General Purpose Input GPIO General Purpose Input Output GP General Purpose Output GRUB GRand Unified Bootloader GVRP GARP VLAN Registration Protocol H G G i GByte Same as GB GigaByte G GHz D HDD Hard Disc Drive M 5 GUID Globally Unique Identifier D HW HardWare Field Replaceable Unit Any entity that can be replaced by a user in the field Not all FRUs are hot swappable I4 AT8030 User s Guide Acronyms Descriptions IA32 Same as IA 32 Intel Architecture 32 bits C 2 Integrated Drive Electronics Internat
51. Hardware Management Functionality 35 SM ae 42 4 5 91 33 AT8030 User s Guide Hardware Management 4 Hardware Management 4 1 Hardware Management Overview The purpose of the hardware management system is to monitor control ensure proper operation and provides hot swap support of AdvancedTCA Boards The hardware management system watches over the basic health of the system reports anomalies and takes corrective action when needed It can retrieve inventory information and sensor readings as well as receive event reports and failure notifications from boards and other Intelligent FRUs The hardware management system can also perform basic recovery operations such as power cycle or reset of managed entities 4 2 Hardware Management Architecture on Front Blade Unit Each CPU blade is logically independent and seen as built in AMC The Zone 1 connector is the card power entry the dual IPMB and the chassis slot address The power entry is a dual 48Vdc The IPMB is the I2C bus that connects the IPMC to the Shelf manager The Hardware address is the 8 bit port that defines the address of the blade in the chassis The Zone 2 contains the base and the fabric interface The Base interface is feed with two 1000 Base T Ethernet link to an onboard Ethernet switch Each CPU has an Ethernet link connected to the switch This allows the IPMI
52. Jumpers amp Locations 25 Installing Memory 2 wie OE mE s ars 28 Board and Carrier Point to Point Interconnect Overview 30 SeriaLOverEan siu durada b RR DURER LER ERU ie 113 Example of BIOS Setup Menu 117 BIOS General Help 4 5 119 Pressure curve T5006 with AMC Filler 153 vii AT8030 User s Guide List of Tables List of Tables Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 2 1 Table 2 2 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 4 20 Table 4 21 Table 4 22 Table 4 23 Table 4 24 Board Specifications Unit ComputerSection 3 Board Specifications CPUO 1 4 Board Specifications CPU1 amp 2 5 6 Board Specifications all 7 USB Connector Pinout 25555 INR 17 Senat Interface PINOUT
53. LSI SAS Dis BAC 09 10 C 80 90 C 105 C Temp Mez 12v Out 0 C 5 C 70 C 85 C 110 C Temp 48V A Feed 0 C 5 C 70 C 85 110 Temp 48V B Feed 0 C 5 C N A 70 C 85 C 110 C CPU2 Temp DIMMO BE 09 10 75 C 85 C 100 C CPU2 Temp MCH 5 C 0 C 10 C 85 C 95 C 110 C CPU2 Temp Vcore Bele 0 C 10 C 95 C 105 C 120 C CPU2 Temp FI BI 5 C 0 C 10 C 95 C 105 C 115 C CPU2 Temp CPU 10 C 90 C 100 C 115 C CPU1 Temp DIMMO 5 C 0 C 10 C 75 C 85 C 100 C CPU1 Temp MCH BAC 0 10 C 85 95 C 110 C CPU1 Temp Vcore 5 C 0 C 10 C 95 C 105 C 120 C CPU1 Temp FI BI 58C 09 10 95 105 120 CPU1 Temp CPU 5 C 0 C 10 C 90 C 100 C 115 C CPUO Temp LSI SAS 10 C 85 C 95 C 110 C CPUO Temp FrontEth 5 C 0 C 10 C 95 C 105 C 115 C BIMM1 52C 0 10 75 85 100 CPUO Temp DIMMO 5 C 0 C 10 C 75 C 85 C 100 C CPUO Temp MCH Bt 0 10 C 85 95 C 110 C CPUO Temp Vcore 5 C 0 C 10 C 95 105 120 CPUO Temp FI BI 10 C 95 105 115 5 C 0 C 10 C 90 C 100 C 115 C Table 7 1 Temperature Sensors Thresholds 151 AT8030 User s Guide Thermal Considerations 7 1 3 Airflow Blockers Itis highly recommended to use airflow blockers in any empty ATCA slot or AMC bay to keep the airflow within the ATCA chassis Failure to do so would go against forced air principles used by ATCA components reducin
54. M 20 11 Transport 1Ah 20 12 Transport 1Bh Table 4 25 Bridge ICMB Management Supported Commands for IPMC req IPMC Bridge Management 0 0 Commands ICMB 2 Get Bridge State ICMB Bridge Set Bridge State ICMB Bridge 018 IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on Get Address ICMB Bridge 02h v Set ICMB Address ICMB Bridge 03h 0 M No No Set Bridge Proxy Address Bridge 04h vs M Get Bridge Statistics ICMB Bridge Get ICMB Capabilities ICMB Bridge Clear Bridge Statistics ICMB Bridge 47 AT8030 User s Guide Hardware Management Get Bridge Proxy Address Get ICMB Connector Info Get ICMB Connection ID Send ICMB Connection ID IPMISpec section ICMB ICMB ICMB ICMB Carrier IPMC req Kontron support on NetFn CMD IPMI BMC req IPMC Bridge 09h 0 M 0 OAh OBh Bridge 0 M Bridge 0 M Bridge OCh 0 M 0 No Table 4 26 Discovery ICMB Commands for IPMC Discovery Commands ICMB 2 Prepare For Discovery Get Addresses Set Discovered Get Chassis Device ID Set Chassis Device ID IPMISpec section ICMB ICMB ICMB ICMB ICMB Carrier IPMC Kontron support on NetFn CMD IPMI BMC req IPMC Bridge 11h 12h 13h 14h Bridge Bridge vs 0 M 0 M Bridge Bridge No Table 4 27 Bridging ICMB Commands fo
55. PC FLASH 0x19 Flash OK PC CPU2 0 1 Init higher level parts of CPU PC RELOCENV 0x1B Relocation of environment Ok PC_BDINFO 0x1C Fill missing fields of bdinfo PC_PCI 0x1D PCI configuration done PC_DEVICES Ox1E Device init done PC JUMPTABLE Ox1F Jumptable init done PC CONSOLE 0x20 Console init done PC_MAIN Ox2F Enter main loop PC START OS Ox3F Pass control to OS leave bootloader 148 AT8030 User s Guide 7 Thermal Considerations 7 1 Thermal Monitoring bentes 150 Thermal Considerations 7 Thermal Considerations The following chapters provide system integrators with the necessary information to satisfy thermal and airflow requirements when using the AT8030 7 1 Thermal Monitoring To ensure optimal operation and long term reliability of the AT8030 all on board components must remain within the maximum temperature specifications The most critical components on the AT8030 are the processors the memory modules and the chipset Operating the AT8030 above the maximum operating limits will result in application performance degradation due to throttling of the processor or may even damage the board To ensure functionality at a maximum operating temperature the blade supports several temperature monitoring and control features 7 1 1 Heat Sinks Multiple key components of the AT8030 are equipped with specifically designed heat sinks to ensure the best possible product for oper
56. Qu bec 87600 Kaufbeuren J7H 0A4 Canada Germany H 3 AT8030 User s Guide G kontron iple Manufacturer Authorization Request Contact Name Company Name Street Address City Province State Country Postal Zip Code Phone Number Extension Fax Number E Mail P 0 8 if not under warranty Serial Number Failure or Problem Description Fax this form to Kontron s Technical Support department in North America at 450 437 0304 in EMEA at 49 0 8341 803 339 H 4 AT8030 User s Guide I Glossary Acronyms Descriptions P Horizontal Pitch 1 HP 2 inches ATCA board is 6HP Refers to width L ACPI Advanced Configuration amp Power Interface D Analog to Digital Converter AdvancedMC Same as AMC Advanced Mezzanine Card C AER Advanced Error Reporting PCI Express device capability for more robust error reporting and is implemented with a specific PCI Express capability structure See the PCI Express Base Specification AMC Same as AdvancedMC Advanced Mezzanine Card 0 Advanced Mezzanine Card Base Specification PCI Express and Advanced Switching on AdvancedMC A subsidiary specification to the Advanced Mezzanine Card Base Specification 0 6H AC Access Control List IP Access Control List A Ethernet Advanced Mezzanine Card Specification A subsidiary specification to the Advanced Mezzanine Card Base Specification 0 Advanced Mezz
57. Remote Access Configuration menu Remote Access Configuration menu is located under System Management 2 Setthe Primary Serial Port Number to the serial port corresponding to the SOL architecture of the blade The serial portis 1 The serial portis the same as the front connector serial port In order to leave the serial port to the SOL interface just unconnected the serial cable from the front RJ45 jack or select another CPU engine 3 Select port Baud Rate from the corresponding menu Data Bits Parity and Stop Bits shall be set to 8 None 1 4 Flow control shall be set to Hardware for proper operation 5 SelectTerminal option if required 6 Save CMOS and exit 113 AT8030 User s Guide Hardware Management 4 5 6 2 Using SOL on remote CPU IPMITool implements a Serial Over LAN console Itis recommended to have IPMITool version 1 8 9 or higher IPMITool can be downloaded from http ipmitool sourceforge net IOL information per board User Password The default user admin and password admin give administrator priviledges IOL SOL is unavailable when payload power is off or in reset 1 Test the IOL connectivity The following command shall return IPMC specific information ipmitool H ip address I lanplus C 1 U user P password bmc info 2 Setup SOL console The following command shall establish IOL session and enable SOL console ipmitool H ip address lanplus C 1 u
58. Table 4 63 0EM for Bridge NetFn ICMB Commands for MMC built in IPMISpec section NetFn CMD Carrier IPMC Kontron support on req MMC OEM Commands for 0 Bridge NetFn 0 0 OEM Commands ICMB Bridge COh FEh 0 M No 98 AT8030 User s Guide Hardware Management Table 4 64 0ther Bridge ICMB Commands for MMC built in IPMISpec section NetFn Ee pus Carrier IPMC Kontron support on req MMC Other Bridge Commands 0 0 Error Report ICMB Bridge FFh 0 M 0 No Table 4 65 PICMG 3 0 Commands for MMC built in acd NetFn press Carrier IPMC Kontron support req MMC AdvancedTCA PICMG 3 0 Table Get Address Info 3 8 PICMG 018 Get Shelf Address Info 3 13 PICMG 02h Set Shelf Address Info 3 14 PICMG 03h FRU Control 3 22 PICMG 04h Get FRU LED Properties 3 24 PICMG 05h Get LED Color Capabilities Set FRU LED State 3 26 PICMG 07h Get FRU LED State 3 27 PICMG 08h Set IPMB State 3 51 PICMG 09h oj N A N A N A Yes z Yes 3 25 PICMG 06h Yes Yes Yes N A Set FRU Activation Policy 3 17 PICMG OAh N A Get FRU Activation Policy 3 18 PICMG OBh N A Ch N A lt Set FRU Activation 3 16 PICMG 0 Get Device Locator Record ID Set Port State PICMG OEh N A Get Port State PICMG OFh N A Compute Power Properties Set Power Level 3 62 PICMG 11h Get Power Level 3 61 PICMG 12h Renegotiate Power 3 66 PICMG 13h Get Fan Spee
59. command is not supported the privilege limits for the channel are used for all users Chosen implementation 5 users including the USER 1 Table 4 73 Front Blade Unit Default User for CPU session User ID Username Password Can be modified Privileges Reserved Reserved Reserved Reserved NULL Empty No User admin admin Yes Administrator Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty 4 5 5 2 IPMI Send Message is an interface like the KCS and the IPMB The implementation supports the send message and the message bridging from one interface to the other See IPMI specification 2 0 section 6 13 named Message Bridging for all the details 4 5 5 3 LAN Parameters The IPMI specifies 2 commands to configure the LAN interface of a specific channel Set and Get LAN Parameters For more details about the bytes and bits defined here refer to IPMI specification 2 0 Markup 2 May 2005 section 23 2 To clarify the document the undefined bits and bytes are not showed in the following table Table 4 74 LAN Parameters Parameter Byte Bit Default Value Default Description Set In Progress Set complete Volatile Notes Rollback is implemented as defined by the specification Auth Type Support read 1 only 1 5 0 010001h None and Straight password key supported 111 AT8030 User s Guide Hardware Management Parameter Byte Bit Default Value Default Description 0
60. decimal Proper value below 8 N A display only AT8030 User s Guide Software Setup 5 1 7 9 Watchdog Timer sub menu Feature Description Help text Configures the BIOS POST IPMI HW watchdog timeout value in seconds Select the BIOS POST BIOS POST Ti HW wat S The BIOS POST watchdog will be disabled ifthe HW watchdog timeout value is set 0 Configures which action to take when the BIOS No Action POST IPMI HW watchdog expires Select which action to Warm Reset Note warm reset is done only if a complete take when the BIOS POST Power Down cold boot POST sequence has been successfully HW watchdog Power Cycle completed If the warm reset flag at address expires 40 72h is not set BIOS will force a cold reset BIOS POST Action Configures the OS Load IPMI HW watchdog timeout value in seconds Select the 05 Load IPMI The 0S Load watchdog willbe disabled ifthe W Watchdog timeout timeout value is set 0 No Action Select which action to Warm Reset Configures which action to take when the 05 take when the OS Load Power Down Load IPMI HW watchdog expires IPMI HW watchdog Power Cycle expires OS Load Action 5 1 7 10 System Information sub menu Feature Option Description Help text Board Product Name AT8030 Displays the CPU blade product name N A display only Board Vendor Kontron Displays CPU blade vendor N A display only Board Serial Number Varies Displays the CPU b
61. for PCIe 100Mhz tdb waiting for AMC 1 Min Clock workgroup on FCLKA usage for PCIe 100Mhz tdb waiting for AMC 1 Max Clock workgroup on FCLKA usage for PCIe Clock Id 0x01 7 1 Oh reserved Clock Control 0x00 0 Ob Activated by Carrier IPMC Indirect Clock Descriptors Count m 0x00 Direct Clock Descriptors Count n 0x01 Indirect clock Descriptor none Direct clock Descriptor 7 2 Oh reserved 1 0b Not connected through PLL 0 1b Clock source 0x02 Reserved for PCI Express Features 0x01 84 AT8030 User s Guide Hardware Management Type 2D Clock Configuration Record Accuracy Level 0x00 N A TBC unspecified 100Mhz tdb waiting for AMC 1 Frequency workgroup on FCLKA usage for PCIe 100Mhz tdb waiting for AMC 1 Min Clock workgroupon FCLKA usage for PCIe 100Mhz tdb waiting for Max Clock AMC 1 workgroup on FCLKA usage for PCIe Table 4 46 0 2 0 Clock Configuration Record 2 of 2 Clock Multiplexer Type 2D Clock Configuration Record 7 6 006 On Carrier device 5 4 Oh reserved 3 0 01h On Carrier Device 1 Clock Multiplexer Clock Configuration Descriptor Count 0 0 Clock Configuration Descriptors Clock Resource Id 0x00 Clock Id 0x00 Receiver input from CLK1A 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor 7 2 Oh reserved Fea
62. for discovering IPMI based systems The Distributed Management Task Force DMTF specifies the RMCP format This LAN communication path make the Front Blade Unit reachable to the System Manager for any management action IPMC firmware upgrade query of all FRU Data CPU reset etc without the needs to goes through the ShMC Onthe Ethernet Switch this communication path is supported from the OS layer Since the Ethernet Switch is parts of the FRU 0 payload power the IPMI over LAN is available only when payload is powered on FRUO M4 active and the OS of Ethernet Switch is running Kontron includes the open source OpenIPMI LAN software modules under the Linux OS of the Ethernet Switch to provide the IPMI over LAN feature For more information see http openipmi sourceforge net The features of IPMI over LAN offers by Open IPMIis provided as is Kontron will not support enhance or provides maintenance for any of the Open IPMI software module 35 AT8030 User s Guide Hardware Management 4 3 1 3 IPMC Payload interface The IPMC payload interface of the Front Blade Unit uses the standard IPMI KCS interface The IPMC KCS interface is visible from Ethernet Switch Linux OS The standard Open IPMI Linux driver build for PowerPC is able to communicate with the IPMC through the standard KCS driver implementation The FPGA bridges the two bus type since the 852166 used for IPMC has LPC host interface and the Ethernet Switch has LBC interf
63. high voltages and energy hazards which can cause bodily harm Useextreme caution when installing or removing components Refer to the installation instructions in this user s guide for precautions and procedures If you have any questions please contact Kontron Technical Support WARNING A High voltages are present inside the chassis when the unit s power cord is plugged A into an electrical outlet Turn off system power turn off the power supply and then disconnect the power cord from its source before removing the chassis cover Turning off the system power switch does not remove power to components xi AT8030 User s Guide Safety Instructions Preventing Electrostatic Discharge Static electricity can harm system boards Perform service at an ESD workstation and follow proper ESD procedure to reduce the risk of damage to components Kontron strongly encourages you to follow proper ESD procedure which can include wrist straps and smocks when servicing equipment Take the following steps to prevent damage from electrostatic discharge ESD When unpacking a static sensitive component from its shipping carton do not remove the component s antistatic packing material until you are ready to install the component in a computer Just before unwrapping the antistatic packaging be sure you are at an ESD workstation or grounded This will discharge any static electricity that may have built up in your body When transporting a sensit
64. in which the product was employed or any loss incurred as a result of the product not functioning at any given time are excluded The extent of Kontron liability to the customer shall not exceed the original purchase price of the item for which the claim exists Kontron issues no warranty or representation either explicit or implicit with respect to its products reliability fitness quality marketability or ability to fulfiLany particular application or purpose As a result the products sold asis and the responsibility to ensure their suitability for any given task remains that of the purchaser In no event will Kontron be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even if Kontron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase Please remember that no Kontron employee dealer or agent is authorized to make any modification or addition to the above specified terms either verbally or in any other form written or electronically transmitted without the company s consent xvii AT8030 User s Guide Chapter 1 Product Description Product OVeEVIBW decor eeu NO edat ipe icu Ev 2 Whats Sek LEE 2 Board Specifications Unit Computer Section 3 Board Specifications CPUO Section 4 Bo
65. publications Customers may alter this user s guide and publish it only after they remove the Kontron name cover and logo Kontron reserves the right to make changes without notice in product or component design as warranted by evolution in user needs or progress in engineering or manufacturing technology Changes that affect the operation of the unit will be documented in the next revision of this user s guide 1 AT8030 User s Guide Table of Contents Table of Contents Safety Instr ctlons sco vv va e xi Before You Begin 55255855066 ares s hne n ms t RS ree xi Preventing Electrostatic Discharge xii Preface cis ovr aO CT ERO V ERE xiii How to Use This Stews wees RE xiii Customer xiv Advisory Conventions ese see err hu n Rhe ma erra xiv Powering Up the Adapter Cables rosno sasse Sa e saw nie Storing Boards EA UNE Regulatory Compliance 5 5 xvi Limited
66. scan for devices from 12 ADDR LIST PCW I2C ES FE Phy access PCW ETH1 ES FE Phy loopback test using special Ethernet test frame PCW ETH2 KCS KCS READY signal test KCSCTL In addition to the Power On Self Tests described above the bootloader logs the board startup sequence in the postcode low byte register A postcode value is written each time a step in the start sequence has been completed successfully The postcode stored is also accessible by the IPMC In the case that an error occurs during execution of a step the boot sequence is stopped because a fatal error has occurred with great likelihood In this case a management instance can read the last postcode written via the IPMC and thus determine where the fatal error has occurred A list of defined postcodes is shown in the table below Table 6 2 POST Boot Steps POST Step Code Value Boot Step PC INIT 0x00 Initial PC EBC has been set up PC BINIT 0x01 Board early init interrupt settings PC CLOCKS 0x02 Get system clocks PC TIMEB 0x03 Init timebase PC ENVINIT 0x04 Init environment PC BAUD 0x05 Init baudrate PC SERIAL 0x06 Init UART PC CPU 0x07 Check CPU PC PHY 0x08 Setup PHY PC 12 0x09 Init I2C PC INITRAM Init SDRAM controller and SDRAM PC TESTRAM 0x0B Test SDRAM PC_INITSEQ OxOF Board init sequence completed PC INITBOARD 0x10 Board init ok stack set up ok board info struct set up PC RELOC 0x11 Relocation completed PC TRAP 0x18 Setup trap handler
67. see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition Built in AMC CPUO B2 Hot Swap sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition Built in CPU1 B3 Hot Swap sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition Built in AMC CPU2 B4 Hot Swap sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition FRUO Hot Swap FRU1 Hot Swap FRU2 Hot Swap FRU3 Hot Swap FRU4 Hot Swap RTM Hot Swap sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition FRU5 Hot Swap 51 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name FRUO Reconfig Temp Switch Temp Dual Phy Co Temp SOC DIMM Temp Air Inlet Description Sensor Type Event Trigger Sensor Population Change on Carrier caused by manage FRU insertion extraction Sensor type 12h System Event Event Reading type code 6Fh Sensor specific only offset 0 is used see AMC 0 R2 0 for event trigger and see IPMI v1 5 table 36 3 Sensor type code 12h for sensor definition Switch T
68. supporton re MMC Serial Modem Device 0 Commands 0 q 0 Set Serial Modem Transpor Configuration 208 t om Hs No Get Serial Modem Configuration 0 2 n 0 M No Set Serial Modem Mux 20 3 ous 12h 0 0 No GetTAP Response Codes 20 4 one 13h 0 0 No 96 AT8030 User s Guide 2 Transpor 11h 0 M Hardware Management Set PPP UDP Proxy Transmit Data Get PPP UDP Proxy Transmit Data Send PPP UDP Proxy Packet Get PPP UDP Proxy Receive Data Serial Modem Connection Active Callback Set User Callback Options Get User Callback Options Table 4 59 Bridge ICMB Management Supported Commands for MMC built in Bridge Management IPMISpec section 20 5 20 6 20 7 20 8 20 9 20 10 20 11 20 12 IPMISpec section NetFn CMD Transpor t Transpor t Transpor t Transpor t Transpor t Transpor t Transpor t Transpor t 14h 15h 16h 17h 18h 19h 1Ah 1Bh NetFn CMD 0 le Carrier IPMC req 0 Carrier IPMC Kontron support on MMC No No No No No No No No Kontron support on MMC Commands ICMB 2 Get Bridge State Set Bridge State Get ICMB Address Set ICMB Address Set Bridge Proxy Address Get Bridge Statistics Get ICMB Capabilities Clear Bridge Statistics Get Bridge Proxy Address Get ICMB Connector Info Get ICMB Connection ID Send ICMB Connection ID ICMB ICMB ICMB ICMB ICMB
69. version of the PLD for the above configuration Currently 0000 Note that if the PLD is absent or not programmed this register will return FFh B 3 6 Base 04h TelcoClock4 Backplane CLK3A B connguranion optional LER Read CLK3AMC CLK3BE CLK3AE Write CLK3AMC CLK3BE CLK3AE PowerUp 0 0 0 0 CLK3AE Backplane CLK3A Enable 0 don t drive this clock 1 drive this clock CLK3BE Same as CLK3AE but for CLK3B CLK3FRQO Backplane CLK3A frequency 0 copy AMCTCLKB to backplane CLK3A B 1 copy AMCTCLKD to backplane CLK3A B B 7 AT8030 User s Guide CLK3AMC Reserved for selection of the AMC that provides the clock for backplane CLK3A B Applicable to boards with two AMCs 0 use AMC B1 1 use AMC B2 This register may be removed as well as the corresponding CLK3 buffer if the customer has no need to drive the backplane CLK3A B Note that the FPGA will automatically clear bits CLK3BE and CLK3AE when the AMC is removed since the clock source is not valid anymore B 8 AT8030 User s Guide C Connector Pinouts C 1 Connectors and Headers Summary Connector Description C 2 Port J5 Pin Pin Signal RTS 1 5 GND DTR RX Driven Active but Not Used Not Used Ethernet J6 amp J7 Pin Signal C 1 AT8030 User s Guide C 4 USB Port J10 J15 316 8217 C 5 Telco Clock 220 Pi
70. 0 disable all devices on the BUS concerned 1 functi static devices initialization on the BUS concerned 2 func 2 output device initialization on the BUS concerned 3 func 3 input device initialization on the BUS concerned 4 func 4 IPL device initialization on the BUS concerned 5 func 5 general device initialization on the BUS concerned 6 func 6 error reporting for the BUS concerned 7 func 7 add on ROM initialization for all BUSes 8 func 8 BBS ROM initialization for all BUSes The lower nibble Y indicates the BUS on which the different routines are being executed Y can be from 0 to 5 D 5 AT8030 User s Guide 0 Generic DIM Device Initialization Manager 1 On board System devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices D 5 Memory Initialization ERROR Code Checkpoint Description Eth Memory Error No memory installed E3h Memory Error Unsupported DIMM type EAh Memory Error Memory timing error D 6 AT8030 User s Guide E Software Update 1 IPMC MMC Firmware Update Procedure It is important to use compatible BIOS FPGA and U BOOT switch versions Since all these software and hardware solution are exchanging information they must be in synch Please always follow Kontron documentation for all your upgrade The current version of the IPMC firmware can be retrieved from the BIOS Setup IPMI Menu or using IPMITOOL th
71. 0 Forms w file upload extensions RFC 1901 Community based SNMP v2 RFC 2068 HTTP 1 1 protocol as updated by draft ietf http v11 spec rev 03 RFC 2246 The TLS Protocol Version 1 0 RFC 2271 SNMP Framework MIB RFC 2295 Transparent Content Negotiation RFC 2296 Remote Variant Selection RSVA 1 0 State Management cookies RFC 2346 AES Ciphersuites for Transport Layer Security RFC 2576 Coexistence between SNMP v1 v2 amp v3 RFC 2578 SMI v2 RFC 2579 Textual Conventions for SMI v2 RFC 2580 Conformance statements for SMI v2 RFC 2818 HTTP over TLS RFC 3410 Informational Introduction and Applicability Statements for Internet Standard Management Framework December 2002 RFC 3411 An Architecture for Describing SNMP Management Frameworks December 2002 F 1 AT8030 User s Guide 3412 Message Processing and Dispatching December 2002 RFC 3413 SNMP Applications December 2002 RFC 3414 User based Security Model December 2002 RFC 3415 View based Access Control Model December 2002 RFC 3416 Version 2 of SNMP Protocol Operations December 2002 RFC 3417 Transport Mappings December 2002 RFC 3418 Management Information Base MIB for the Simple Network Management Protocol SNMP December 2002 RFC 3635 Definition of Managed Objects for Ethernet like Interface Types HTML 4 0 Specification December 1997 Java amp Java Script 1 3 SSL 3 0 amp TLS 1 0 SSH 1 5 amp 2 0 Draft i
72. 00000h Callback No enable 010000h User level Straight password key supported Operator level Straight password key supported Auth Type Enable Admin level None and Straight password key 0100 Uns level Unsupported level IP Address 0 0 0 0 0 0 Fixed to static address No other setting planned to be supported MAC Address 5 E Chip MAC Set to chip MAC in production Subnet Mask 0 0 0 0 0 0 0 0 Time to live IP Address source Oth Flags fixed to don t fragment Precedence fixed to 000b Type of service fixed to minimize delay Ipv4 Header Parameters Primary RMCP port number Secondary RMCP port number Unsupported pot 298h BMC generated ARP n 01 1 Enable BMC generated ARP responses control Enable BMC generated Gratuitous ARPs Gratuitous ARP interval 8 Seconds VLAN ID VLAN ID data VLAN PRIORITY VLAN Priority data 4 5 5 3 1 VLAN Configuration options have been added to support IEEE 802 1q VLAN virtual LAN headers for IPMI over IP sessions on IEEE 802 3 Ethernet VLAN works with VLAN aware routers and switches to allow a physical network to be partitioned into virtual networks This can be used to isolate classes of network membership at the Ethernet Packet level rather than at the IP level as might be done with a router This can be used to set up a management VLAN where only devices that are members of that VLAN receives packets related to management an
73. 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Clock Control 0x01 7 2 Oh reserved Features 1 1b Connected through PLL 0 Ob Clock Receiver Descriptor 0 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 Clock Receiver Descriptor 1 Dependent ClockId 7 Direct clock Descriptor 86 AT8030 User s Guide Hardware Management Type 2D Clock Configuration Record Clock Id 0x04 Clock Control 0x01 Source output to CLK3A 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Features Descriptor 0 Dependent ClockId Features Descriptor 1 Dependent ClockId 7 2 Oh reserved 1 0b Not Connected through PLL 0 1b Clock Source 7 2 Oh reserved 1 0b Not Connected through PLL 0 1b Clock Source Direct clock Descriptor none Clock Id 0x05 Clock Control 0x01 Source output to CLK3B 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor 7 2 Oh reserved 1 0b Not Connected through PLL Features Descriptor 0 Dependent ClockId Features Descriptor 1 Dependent ClockId 0 1b Clock Source 7 2 Oh r
74. 1h 0 M Yes 02h 0 M Yes 03h No 04h N 05 Set Power Restore Policy 22 7 Chassis 06h N 07 0 0 08h No 09h No OFh No 93 AT8030 User s Guide Hardware Management Table 4 51 Event Supported Commands for MMC built in IPMISpec section NetFn CMD Carrier IPMC Kontron support on req MMC Event Commands Set Event Receiver 23 1 S E 01h Yes Get Event Receiver 23 2 S E 02h Yes Platform Event a k a Event Message 23 3 S E 03h vee Table 4 52 PEF and Alerting Supported Commands for MMC built in NetFn E Kontron support on req MMC PEF and Alerting Commands Get PEF Capabilities 24 1 S E Arm PEF PostponeTimer 24 2 S E Set PEF Configuration Parameters Get PEF Configuration Parameters 0 0 24 3 S E 24 4 S E Set Last Processed Event ID Get Last Processed Event 24 5 S E 24 6 S E Alert Immediate S E PET Acknowledge S E Table 4 53 Sensor Device Supported Commands for MMC built in IPMISpec section NetFn Carrier IPMC Kontron support on MMC req Sensor Device Commands 0 M Get Device SDR Info 29 2 0 Get Device SDR 29 3 0 M 0 M 0 S E 20h Yes S E 21h Yes Reserve Device SDR Repository 29 4 S E 22h Yes 29 5 S E 23h No S E 24h Yes Get Sensor Reading M Factors Set Sensor Hysteresis 29 6 Get Sensor Hysteresis 29 7 S E 25h Yes Set Sensor Threshold 29 8 Yes Yes S
75. 31 DHCP Server RFC 2132 DHCP Options and BOOTP Vendor Extensions RFC 2865 RADIUS Client AT8030 User s Guide 2866 RADIUS Accounting 2868 RADIUS Attributes for Tunnel Protocol Support RFC 2869 RADIUS Extensions RFC2869bis RADIUS support for EAP RFC 3176 InMon Corporation s sFlow A Method for Monitoring Traffic in Switched and Routed Networks RFC 3396 Encoding Long Option in the Dynamic Host Configuration Protocol DHCPv4 RFC 3580 802 1X RADIUS Usage Guidelines Draft ietf magma snoop 11 txt Considerations for IGMP and MLD Snooping Switches F 1 3 QoS Bandwidth Policing Min and Max per port per VLAN Committed Information Rate CIR Maximum Burst Rate MBR Per Port Interface Per VLAN Filtering L3 L4 Access Lists IP Classification 6 Tuple Classification RFC 2474 DiffServ Definition RFC 2475 DiffServ Architecture RFC 2597 Assured Forwarding PHB RFC 3246 An Expedited Forwarding PHB RFC 3260 New Terminology and Clarifications for DiffServ F 2 Supported MIBs The Software supports the following MIBs F 2 1 Enterprise MIB Support for all managed objects not contained in standards based MIBs F 4 AT8030 User s Guide F 2 2 Switching Package MIBs RFC 1213 MIB II RFC 1493 Bridge MIB RFC 1643 Ethernet like MIB RFC 2233 The Interfaces Group MIB using SMI v2 RFC 2618 RADIUS Authentication Client MIB RFC 2620 RADIUS Accounting
76. 4 68 MMC Sensor Names Sensor Name 106 AT8030 User s Guide Hardware Management Sensor Name BX CPU Critical Int BX IPMI Watchdog BX FWH 0 Error BX FWH 1 Error 4 5 3 FRU Information Table 4 69 CPUO Engine Board Information Area CPUO Engine Board Information Area Field Description Value hex Format Version 0x01 Board Area Length Calculated Language code 0x19 Manufacturing Date Time Based on mfg date Board Manufacturer type length Board Manufacturer KONTRON Board Name type length Calculated Board Name AT8030 CPUO Engine Board Serial Number type length Board Serial Number null Calculated cm Board Part Number type length Board Part Number null FRU FileIDtype length 0 00 FRU File ID null No more fields OxC1 Padding 0x00 Board Area Checksum Calculated em e Table 4 70 CPUO Engine Product Information Area CPUO Engine Product Information Area Field Description Value hex Format Version 0x01 Board Area Length Calculated Language code 0x19 Board Manufacturer type length Calculated 107 AT8030 User s Guide Hardware Management CPUO Engine Product Information Area Board Manufacturer KONTRON Board Nametype length Calculated Board Name AT8030 CPUO Engine Board Serial Number CO type length Board Serial Number null type length No more fields OxC1 Padding 0x00 Board Area Checksum Calculated 4 5 4
77. 4Eh Fabric Interface Channel 14 Port 0 Link Descriptor 0010214Fh Link Grouping ID Bits 31 24 Oh Single Channel link Link Type Extension Bits 23 20 Oh Fixed 1000Base BX Link Type Bits 19 12 02h PICMG 3 1 Ethernet Fabric Interface Link Designator Bits 11 0 14Fh Fabric Interface Channel 15 Port 0 Link Designator Bits 11 0 Link Designator Bits 11 0 4 4 3 2 IPMC FRU 0 Carrier Activation and Carrier Information Table The following structure describes the maximum internal current the current capacity of the AMC Bays and their power on treatment TBC Module Current and Maximum Internal Current needs to be confirmed after the Hardware qualification 66 AT8030 User s Guide Hardware Management Table 4 38 AMC Carrier Activation and Current Management Record Type 17 Carrier Activation And Current Management Record Maximum Internal Current 0069h 10 5 Amps at 12 V gt 126 Watts Maximum Module Current 22h 3 40 Amps at 12 V gt 40 8 Watts Maximum Module Current 19h 2 50 Amps at 12 V gt 30 Watts Maximum Module Current 19h 2 50 Amps at 12 V gt 30 Watts Maximum Module Current 09h 0 90 Amps at 12 V gt 10 8 Watts Reserved FFh The Carrier Information Table shows the required FRU Information format that describes the specific AMC Bays implemented on a Carrier For each AMC Bay on the Carrier the Carrier Information Table includes a Site Number for that AMC Bay The Carrier Informatio
78. 4h Manufacturing Test On 17 5 App 05h Yes Get ACPI Power State 17 7 App 07h No Get Device GUID 17 8 App 08h No Broadcast Get Device Yes Yes No Yes m 0 0 0 0 ojo 17 9 App oih Table 4 14 Watchdog Timer Supported Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC BMC Watchdog Timer Commands Reset Watchdog Timer 21 5 Set Watchdog Timer 21 6 Get Watchdog Timer 21 7 M Table 4 15 Device Messaging Supported Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC BMC Device and Messaging Commands 5 Set BMC Global Enables 18 1 2 0 M Yes Get BMC Global Enables 18 2 pp 2Fh M 0 M Yes Clear Message Flags 18 3 App 30h M 0 M Yes 42 AT8030 User s Guide Hardware Management on IPMC req Get Message Flags 18 4 App 31h M 0 M Yes Enable Message Channel paces 18 5 App 32h 0 0 Yes App 33h M 0 M Yes 34h M M Yes Get Message 18 6 4 IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support Send Message 18 7 Ap p Read Event Message Buffer 18 8 App 35h 0 0 Yes Get BT Interface Capabilities 18 9 App 36h 0 M Yes Master Write Read 18 10 App 52h M 0 M No Get System GUID 18 13 App 37h 0 0 No A 38h 0 0 N Get Channel Authentication Capabilities LENT App 3Bh 0 0 No Close Se
79. 5_TXC ROW ROW AB ROW CD ROW GH GND GND GND GND 8 N C N C GND GND GND GND 9 SAS1_RX SAS1_RX GND GND GND GND C 7 1 RTM Intelligent Managed FRU Port Mapping B D Ch10 NU NU NU NU 1000 TX2 in 1000BX TX2 in 1000BX RX2 out 1000BX RX2 out Port 1 SAS 0 TX in SAS 0 SAS 0 RX out SAS 0 RX out SAS 1 TX in SAS 1 SAS 1 RX out SAS 1 RX out Port 2 Port 2 chs 100BASE_TX 100BASE TX 100BASE RX4 100BASE RX 100BASE CT NC NC NC Port 5 ces lid re Ch6 RS232 5 TX RS232 5 RX RS232 6 TX RS232 6 RX RS232 7 TX RS232 7 RX UC SCL UC SDA Port 17 RTM SP5 Port 18 RTM SP6 Port 19 RTM SP7 RS232 1 TX RS232 1 RX RS232 2 TX RS232 2 RX RS232 3 TX RS232 3 RX RS232 4 TX RS232 4 RX Port 13 5 1 Port 14 RIM SP2 Port 15 RTM SP3 Port 16 RTM SP4 th Reserved Reserved Into RESET PROG Port 12 5 Port 20 C 4 AT8030 User s Guide In Input driven by Carrier Out Output driven by RTM IO Bidirectional port ID for carrier p2p connectivity information see 0 2 section 3 9 1 connected to separate RJ45 connector RTM connection selected by rotary switch In order to support ekey governed interfaces on the RTM AMC style port mapping is necessary For consistency with AMC 2 and AMC 3 SAS and GbE port numbers have been assi
80. 8c Intel Corporation 3100 Chipset EHCI 0582 Controller USB Conteoller 7 00 1e 8086 244e 0 Intel Corporation 82801 PCI Bridge PCI Bridge 00 1f 8086 2670 0 Intel Corporation 3100 Chipset LPC Interface Controller ISA Bridge 02 00 8086 1060 Intel Corporation 82571EB Gigabit Ethernet Controller Ethernet Controller 02 00 8086 1060 1 Intel Corporation 82571EB Gigabit Ethernet Controller Ethernet Controller LSI Logic Symbios Logic SAS1064E PCI Express Fusion SCSI Storage MPT SAS Controller 00 8086 105e 0 Intel Corporation 82571EB Gigabit Ethernet Controller Ethernet Controller 00 8086 105e 1 Intel Corporation 82571EB Gigabit Ethernet Controller Ethernet Controller 0 1c 0 1c i 0 1d i 0 1d 03 00 1000 0056 0 A 3 AT8030 User s Guide 3 2 CPU Engine 1 amp 2 DEV V ID D ID Funct Description 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 02 00 8086 00 8086 01 8086 02 8086 03 8086 1c 8086 1c 8086 1c 8086 1c 8086 1d 8086 1d 8086 1d 8086 1e 8086 1f 8086 1f 8086 00 8086 00 8086 35b0 35b1 3505 35b6 35b7 2690 2692 2694 2696 2688 2689 268c 244e 2670 269b 1060 1060 0 0 0 0 Intel Corporation 3100 Chipset Memory 1 0 Controller Hub Intel Corporation 3100 DRAM Controller Error Reporting Registers Intel Corporation 3100 Chipset Enhanced DMA Controller Intel Corporation 3100 Chipset PCI Express Port A Intel Corporation 3100 Chipset PCI E
81. Access View Only Limited Full Access Enabled Disabled Description Indicates the status of the Supervisor Password Indicates the status of the User Password The supervisor password can be installed or changed The user password can be installed or changed Immediately clears the User password Controls the user access level to the BIOS Setup utility Supervisor has full access to the BIOS Setup utility No Access Prevents user access to the setup utility View Only Allows read only user access to the setup utility i e none of the fields can be changed Limited Allows limited fields such as date and time to be changed in user access to the setup utility Full Access Allows unlimited user access to the setup utility Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot preventing certain classes of malicious buffer overflow attacks when combined with a supporting operating system 129 Help text Indicates the status of the supervisor password Indicates the status of the user password Install or change the supervisor password Install or change the user password Clears user password Controls access to the setup utility No Access Prevents user access View Only Allows read only user access Limited Allows limited fields to be changed Full Access Allows unlimited user access Enabled Allows pro
82. Clear all Event Logs ECC Event Logging ECC Error Reporting NSI Event Logging FSB Event Logging Memory Buffer Event Logging PCI Express Error Logging PCI Express Error Masking Event Log Configuration sub menu Space Available No Space Enabled Disabled Enabled Disabled Correctable Uncorrectable Both Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled N A Description Displays whether there is room left to log events to the local system event log The local event log needs to be cleared when this field shows No Space Configures if local system event log logging is enabled disabled View all unread events in the Event Log Mark all unread events as read in the Event Log Discard all events in the Event Log ECC Event Logging can be enabled disabled ECC error reporting mode The IMCH and IICH are physically connected by an internal interface called NSI North South Interface NSI event logging can be enabled disabled The Front Side Bus is the connection between the chipset and the memory FSB event logging can be enabled disabled Signals errors occurring in the chipset memory system coherent Posted Memory Write Buffer PMWB Memory buffer event logging can be enabled disabled PCI Express error event logging can be enabled disabled Selects sub menu 124 Help text Shows if space is available in the Event Log for new
83. E 26h Get Sensor Threshold 29 9 S E 27h SetSensorEventEnable 29 10 S E 28h Yes 94 AT8030 User s Guide Hardware Management req MMC Get Sensor Event Enable 29 11 S E 29h Yes Re arm Sensor Events 29 12 S E 2Ah N Get Sensor Event Status 29 13 S E 2Bh N Get Sensor Reading 29 14 S E 2Dh Yes Set Sensor Type 29 15 No No S E 2Eh Get Sensor Type 29 16 S E 2Fh IPMI Spec section NetFn CMD Carrier IPMC Kontron support on 0 Table 4 54 FRU Device Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC FRU Device Commands M M us USED 28 1 Storage 10h M M Yes Read FRU Data 28 2 Storage 11h M M Yes Write FRU Data 28 3 Storage 12h M M Yes Table 4 55 SDR Device Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on q MMC SDR Device Commands re M 0 Get SDR Repository Info 27 9 Storage 20h M M 0 0 No Get SDR Repository Allocation Info 27 10 Storage 21h No Reserve SDR Repository 27 11 Storage 22 M No Get SDR 27 12 Storage 23h M No Add SDR 27 13 Storage 24h 0 M No Partial Add SDR 27 14 Storage 25h 0 M No Delete SDR 27 15 Storage 26 0 Clear SDR Repository 27 16 Storage 27h 0 M GetSDRRepository Time 27 17 Storage X 28h 0 M SetSDRRepository Time 27 18 Storage 29h Enter SDR Repository Update Mode Exit SDR Repositor
84. Each interface has a channel number that is used when configuring the channel and for routing messages between channels Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Display Valid if IPMC support LAN Channel This allows setting of a Subnet Mask for LAN configuration Display the current Subnet Mask configuration stored in IPMI NVRAM for IPMI LAN 137 Help text N A display only Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only N A display only Help text N A display only Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only Enter Subnet Mask in decimal in the form of XXX less than 256 and in decimal only N A display only AT8030 User s Guide Software Setup 5 1 7 6 Gateway Address Configuration sub menu Feature Description The parameter selector assignments are LAN Parameter Selector 12 described in IPMI Specification 1 5 table 19 4 Selector 12 Default Gateway Address Each interface has a channel number that is used when configuring the channel and for routing messages between channels Channel Number Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Help text N A disp
85. H Displays DIMM 2 memory size DIMM electrically furthest to MICH filled 2 Size X KB MB GB first N A display only y Kontron DIMM slot physically closest to the MICH N A display only DIMM Memory Size CPU 1 and 2 System Memory Speed XMHz Displays system memory speed N A display only XKB MB GB Display DIMM memory size N A display only System Memory XKB Displays amount system memory N A display only Extended Memory XKB Displays amount of extended memory N A display only Use or to configure system time Use or to configure system date System Time HH MM SS Setthe system time System Date MM DD YYYY Setthe system date 5 1 4 Advanced Menu Feature Option Description Help text Advanced Processor Configuration ACPI Configuration N A Selects sub menu N A Event Log Configuration N Selects sub menu N A Selects sub menu N A Expansion ROM Configuration PCI Express Configuration N A Selects sub menu N A N A Selects sub menu N A N A USB Configuration Selects sub menu N A N A Advanced Chipset Control N A Selects sub menu Configures the Multiprocessor Specification MPS revision level Some operating systems might require revision 1 1 for compatibility reasons Multiprocessor specification revision level MPS Revision 120 AT8030 User s Guide Software Setup 5 1 4 1 Advanced Processor Configuration sub
86. I Express For demanding 1 0 and networking applications PCI Express interfaces attach a variety of Intel and third party 1 0 solution components and adapters directly to the Intel 3100 chipset one x8 PCI Express interface and one x4 PCI Express interface Each interface may be bifurcated to provide additional configuration flexibility The interfaces provide throughput speeds of up to 4 GB s on the x8 interface and up to 2 GB s on the x4 interface allowing 1 0 to keep pace with the rest of the platform 2 3 2 2 1 3Data Protection The Intel 3100 chipset is designed to bring enterprise level reliability availability serviceability usability and manageability RASUM to the embedded platform The chipset supports two bits of parity on 64 bits of data on internal buses The PCI Express interface supports 32 bit cyclic redundancy check CRC for detection and automatic recovery of transient signaling errors Memory interface supports Single Error Correct Double Error Detect SEC DED ECC auto retry on uncorrectable errors and integrates a hardware memory scrubber to scan the populated memory space proactively seeking out soft errors in the memory subsystem 2 3 2 2 1 4Enhanced Direct Memory Access EDMA A four channel EDMA controller efficiently moves data within local system memory or from the local system memory to the 1 0 subsystem Each EDMA channel provides low latency highthroughput data transfer capability with no CPU intervention fo
87. MIB RFC 2674 VLAN amp Ethernet Priority MIB RFC 2819 RMON Groups 1 2 3 amp 9 RFC 2863 Interfaces Group MIB RFC 3291 Textual Conventions for Internet Network Addresses IANA ifType MIB IEEE 802 1X MIB IEEE8021 PAE MIB IEEE 802 3AD MIB IEEE8021 AD MIB F 2 3 QoS Package MIB RFC 3289 DIFFSERV MIB amp DIFFSERV DCSP TC MIBs F 5 AT8030 User s Guide Bootloader The bootloader initializes the Unit Computer and its associated components board like SDRAM serial lines etc for operation After this kernel and application are started from flash In addition the bootloader provides a user interface with commands to access the board s components Networking functions are available to load and start alternative kernel and application files A powerful redundant environment gives the user the capabilities to tailor the bootloader s startup behaviour to his needs G 1 GeneralOperation Upon power on or system reset the bootloader is started and the Ethernet Switch subsystem is initialized In the case that the serial portis connected to a terminal and a predefined string is entered after the SDRAM test and within the bootdelay time which is 5 seconds by default the startup procedure is interrupted and the bootloader s command prompt is presented to the user If the bootdelay time expires without user interaction the start sequence proceeds with loading and starting the operating system from flash In case of ha
88. Nibble Event Data 3 POST High Nibble 38 AT8030 User s Guide Hardware Management Table 4 5 Kontron OEM Management Controller firmware ugrade Status Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 6Fh C7h First Boot asfet upgrade Standard IPMI feat dp E 2 ontroller firmware 01h First Boot after rollback sensor specific upgrade Status Table 4 6 Kontron OEM Switch Management Status Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset Switch Management Software Not Loaded No event generated Switch Management Software Initializing No event 6Fh C8h generated Standard IPMI OEM Kontron Switch Management Ready No event generated sensor specific Switch Management Switch Management Software Fail Status Event Data 2 03h 00 05 configuration file corrupted O1h OS startup failure 02h Switch Management Application Fail Table 4 7 Kontron OEM Diagnostic Status Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 6Fh Diagnostic Started Standard IPMI OEM Kontron Diagnostic PASS sensor specific Diagnostic Status Diagnostic FAIL Table 4 8 Kontron OEM External Component Firmware Upgrade Status Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 6Fh CAh Firmware upgrade in progress no event Standard IPMI OEM Kontron Ex
89. Onboard Ethernet Switch Two 10G XAUI connections to the Fabric Interface in Zone 2 of the PIGMG 3 0 backplane Two 1000Base BX connection to the Zone 2 e 1000Base BX connection to the RTM in Zone 3 One 1000Base BX connection to the Unit Computer One 1000Base BX connection to CPU 0 19 AT8030 User s Guide Board Features One 1000Base BX connection to CPU 1 One 1000Base BX connection to CPU 2 Five 1000Base BX connection to AMC B1 one to common option port 1 four to fat pipe port 8 to 11 Only one of those connections is enabled at the same time by e keying 2 5 Serial Interfaces The AT8030 uses serial interfaces to manage the CPUs Since no video interface is provided on board the only way to get visual information on the CPU engines is the serial console Serial ports are provided on the board for asynchronous serial communications They are 16C550 high speed UART compatible and support 16 byte FIFO buffers for transfer rates from 9 6Kbps to 115Kbps There is a single serial port connector on the front plate This connector can be routed to any ofthe primary serial ports of the CPU engines and the Unit Computer The user selects the routing with a pushbutton on the front plate The selected console will be displayed using a bank of 4 green LEDs The primary serial port of each CPU engine and UARTO ofthe Unit Computer can also be redirected to the RTM The secondary port of the CPU engines is routed di
90. PU Light Emitting Diode Limited First Customer Shipment Refers to Kontron scheduling for boards Low Frequency Mode The lowest operating speed for the processor Loop Initialization Primitive Related to FC arbitrated loop topology an initial message needed for learning the loop addresses and acquiring one Low Pin Count port Line Print Terminal 1 Least Significant Byte Logical Unit Number Low Voltage LVCMOS Low Voltage Complementary Metal Oxide Semiconductor Low Voltage Differential Signaling Media Access Controller address of a computer networking device MegaByte Multiple Bit Error same as MemBIST Memory Built In Selft Test Chipset feature for out of band memory testing and intialization Master Boot Record Management Controller Memory Controller Hub MemBIST same as M BIST Memory Built In Selft Test Chipset feature for out of band memory testing and intialization Message Digest algorithm n 2 5 Medium Dependent Interface MDI port or uplink port MegaHertz MICH Memory controller Hub and 1 0 Controller Hub Chipset that integrates IMCH and in a single chip solution Microcode Intel supplied data block used to correct specific errata in the processor 1 6 8030 User s Guide Acronyms Descriptions MMIO Memory Mapped IO MOSFET Metal Oxide Semiconductor Field Effect Transistor MultiProcessor MultiProcessor Specification Memory Reference Code Chipset specific code provided by the manufactur
91. PU can only read it 1 IPMC has write control of the interface 0 Main CPU LPC has write control of the interface bit IFSEL is writable only on the IPMC side ofthe interface B 3 3 Base 01h TelClock1 PLL Control amp Status 01 Read Write power up and lpc reset OOR RESET MODE TIE_CLR FAILO FAIL1 FAILO TIE CLR amp MODE RESET OOR TIE_CLR MODE RESET OOR 1 1 0 0 Out Of Range selection Determine what is considered a precision fault by the PLL 1 64 83ppm 0 40 52ppm Hardware reset of the PLL This bitis forced to 1 when the payload power i e PLL power is turned off 1 reset 0 normal operation PLL operating mode 1 freerun mode may be used for tests 0 normal mode Timing Interval Error adjustment 1 normal mode 0 adjust phase to match reference REFO CLK2A failed with current OOR setting 1 failed clock 0 passed clock B 5 AT8030 User s Guide FAIL1 CLK2B failed with current setting Same as FAILO but for LOCK PLL lock status 1 PLL locked 0 PLL not locked PLL in holdover or free running Note that this register needs to be reprogrammed every time the blade is reset Those are direct pin control and status See the 21 30108 datasheet for a detailed explanation of the functionality B 3 4 Base O2h TelClock2 AMCs Clock Enables amp
92. RMS Root Mean Square RoHS Restriction of the Use of Certain Hazardous Substances Read Only Memory Also refers to option ROM or expansion ROM code used during POST to provide ROM 52 S services for specific controllers such as boot capabilities RPP Reliability Prediction Procedure RS 232 Same as RS232 Recommended Standard 232 RS232 Same as RS 232 Recommended Standard 232 RSS Receive Side Scaling RTC Real Time Clock RTM Rear Transition Module RTM Link Rear Transition Module Link Kontron 3 wire protocol RTS Request To Send S M A R T Self Monitoring Analysis and Reporting Technology for IDE SO ACPI OS System State 0 Indicates fully on operating state S5 ACPI OS System State 5 Indicates Soft Off operating state SAS Serial Attached SCSI SATA Serial ATA SBC Single Board Computer SBE Single Bit Error SCI System Control Interrupt SCL Serial CLock SCSI Small Computer System Interface SDH Synchronous Digital Hierarchy SDR Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory SEC Single bit Error Correct SEEPROM Serial EEPROM SEL System Event Log SERDES SERializer DESerializer Pair of functional blocks commonly used in high speed communications These blocks convert data between serial data and parallel interfaces in each direction SERIRQ Serial IRQ SERR System ERRor A signal on the PCI bus that indicates a fatal error on the bus SFP Small Form factor Pluggable Serial Gigabit Med
93. ROM 21 AT8030 User s Guide Board Features Software Usage To access the SAS BIOS press CTRL C when the board boots You can also access the SAS controller by using the LSI Util Linux Tool Software Usage y AMC serial port available on port 15 AMC serial port E Keying OEM link type port GUID 471C5D14 2AE7 42B9 A9B0 0628546B42CC 2 7 The FPGA has many functions One of them is to act as a companion chip to the IPMC The states of all the critical signals controlled by the IPMC are memorized in the FPGA and are preserved while the IPMC firmware is being updated The FPGA is a RAM based chip that is preloaded from a separate flash memory at power up Two such flash memory devices are provided one that can only be programmed in factory and the other one that can be updated in the field The factory flash is selected by inserting jumper JP2 pins 3 4 Field updates require to cycle the power of the board The selected LED will blink if the factory flash is being used The appropriate procedure to upgrade the FPGA will be provided with the update code when needed 2 8 Telecom Clock Option The telecom clock option is not shown on the main block diagram The circuit is made of MLVDS buffers a PLD and a multi service line card PLL The PLD is hooked to the main FPGA with a fast serial link and from there to the IPMC via a proprietary bus The PLD receives 19 44MHz clocks from the backplane CLK2A and CLK2B and use it a
94. RTN A Feed Description Sensor Type Event Trigger Power Mezzanine Feed B Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 70 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 110 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Actual power status Sensor type 08h Power Supply Event Reading type code 77h OEM see table sws 10 1137 for event trigger information Power status event that occur since the last power on or reset Sensor type 08h Power Supply Event Reading type code 77h OEM see table sws 10 1137 for event trigger information Voltage on 48v feed A board input power supply Sensor type 02h voltage Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 37 5v Lower Critical event 75v Hysteresis 1 26v Voltage on 48v feed B board input power supply Sensor type 02h voltage Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 37 5v Lower Critical event 75v Hysteresis 1 26v Fuse presence and fault detection 48 V on supply A Se
95. RUO sensors aggregation for health sensor The following table shows the sensors involved in the health sensor aggregation Table 4 34 FRUO Sensor Name Sensor Name Temp Switch Temp Dual Phy Co Temp SOC DIMM Temp Air Inlet Temp PQ3 Temp Dual Phy Se Temp LSI SAS Dis Temp Mez 12v Out Temp 48 A Feed Temp 48 B Feed Power Good Event IPMI Watchdog Reset PQ3 POST Value PQ3 OS stop PQ3 Critical Int Vcc 48V A Vcc 48V B Vcc 1 1 62 AT8030 User s Guide Hardware Management Sensor Name 4 4 3 FRU Information Table 4 35 ES Board Information Area ES Board Information Area Manufacturing Date Time Based on mfg date Board Manufacturer type length Board Manufacturer KONTRON Calculated Board Nametype length Calculated Board Name 8030 Board Serial Number type length Board Serial Number 10 digits serial number Board Part Number type length Calculated Board Part Number T5006 FRU File ID type length 0x00 Calculated 63 AT8030 User s Guide Hardware Management ES Board Information Area FRU File ID null No more fields OxC1 Padding 0x00 Board Area Checksum Calculated Table 4 36 ES Product Information Area ES Product Information Area Format Version 0x01 Product Manufacturer type length Calculated Product Manufacturer KONTRON Product Name type Calculated length Product Name 8030 Product Part N
96. S Date Time not set offset 0 event data 2 01h event trigger No system memory is physically installed in the system offset 0 event data 2 02h event trigger No usable system memory offset 0 event data 2 03h event trigger Unrecoverable hard disk ATAPI IDE device failure offset 0 event data 2 04h Unrecoverable system board failure offset 0 event data 2 ODh CPU speed matching failure see IPMI v1 5 table 36 3 Sensor type code OFh System Firmware Progress for sensor definition Critical Interrupt Sensor type 13h Critical Interrupt Event Reading type code 6Fh Critical Interrupt offset 0 4 5 are used offset 0 event trigger Front Panel NMI Diagnostic Interrupt offset 4 event trigger PCI PERR offset 5 event trigger PCI SERR see IPMI v1 5 table 36 3 Sensor type code 13h for sensor definition Memory Status Sensor type OCh System Firmware Progress Event Reading type code 6Fh Sensor specific offset 0 1 3 4 5 are used offset 0 event trigger Memory Correctable ECC offset 1 event trigger Memory Uncorrectable ECC offset 3 event trigger Memory Scrub Failed stuck bit offset 4 event trigger Memory Device Disabled offset 5 event trigger Memory Correctable ECC Memory logging limit Reach see IPMI v1 5 table 36 3 Sensor type code OCh for sensor definition POST Memory Resize Indicates if CMOS memory size if wrong Sensor type OEh Critical Interrupt Event Reading type code 03h Digital
97. ST PCI Express Configuration sub menu Enabled Disabled Description AMC slot hot plug support can be enabled disabled 126 Help text Enabled Initializes base interface PXE expansion ROM Disabled Base interface PXE expansion ROM not used If disabled remote LAN boot via 15 not available to boot the system Enabled Initializes fabric interface PXE expansion ROM Disabled Fabric interface PXE expansion ROM not used Tf disabled remote LAN boot via is not available to boot the system Enabled Initializes Management Ports PXE expansion ROM Disabled Management Ports PXE expansion ROM not used If disabled remote LAN boot via Management Ports is not available to bootthe system Enabled Initializes SAS expansion ROM Disabled SAS expansion ROM not used If disabled any SAS devices attached to the system are not available to boot the system Enabled Initializes AMC slot expansion ROM Disabled AMC slot expansion ROM not used Enabled Hot plug for AMC slot available Disabled Hot plug for AMC slot not available AT8030 User s Guide Software Setup 5 1 4 9 USB Configuration sub menu Feature Option Description Help text FullSpeed Configures the USB 2 0 Controller in HiSpeed FullSpeed 12 Mbps HiSpeed 480Mbps or FullSpeed 12Mbps HiSpeed 480 Mbps A workaround for OSes without EHCI hand off Enabled EHCI hand off Enabled support can be
98. T Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre boot process The following table describes the type of checkpoints that may occur during the POST portion of the BIOS Checkpoint Description Disable NMI Parity video for EGA and DMA controllers Initialize BIOS POST Runtime data area Also initialize BIOS modules on POST entry and GPNV area Initialized CMOS as mentioned in the Kernel Variable wCMOSFlags Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verify CMOS checksum manually by reading storage area If the CMOS checksum is bad update CMOS with power on default values and clear passwords Initialize status register A Initializes data variables that are based on CMOS setup questions Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware generally PIC and interrupt vector table Do R W test to CH 2 count reg Initialize CH 0 as system timer Install the POSTINT1Ch handler Enable IRQ 0 in PIC for system timer interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock D 2 AT8030 User s Guide Checkpoint Description Initializes the CPU The BAT test is being done on KBC Program the keyboard controller command byte is being done after Auto detection of KB MS using AMI KB 5 Early CPU Init Start Disable Cache Init Local APIC Set up boot strap processor Information Se
99. User s Guide Product Description 1 9 1 4 2 Removing the RTM8030 from the slot The EJECT signal goes HIGH by opening the RTM lower ejector handle This indicates to the front blade IPMC that a hot swap action is going to take place The IPMC then negotiates the removal with the System manager and if itis granted it proceeds with the removal process The IPMC proceeds to the deactivation by disabling ekey governed links the IPMC then disables the RTM Link and turns OFF the payload 12V power When it is safe to remove the RTM blade from the slot the IPMC turns the Blue Hot Swap LED ON Front Blade IPMC turns OFF the management power only when there is no RTM detected RTM8030 removed from the slot 1 9 2 Mezzanine AT8030 has one bay Using a mezzanine allows to add storage or 1 0 not provided on board 1 9 2 1 Expansion The slot provides AMC 1 type 4 AMC 2 Type E2 and 4 AMC 3 Dual Port SAS This means that the following signaling are supported PCI Express X4 on AMC ports 4 7 PCI Express clock on FCLKA Gigabit Ethernet on AMC port 0 and 1 8 11 Telco clocks on TCLKA B C D SASon AMC port 2 and 3 10 AT8030 User s Guide Chapter 2 5 Blot Dia GIN ssi Pu e etx eue 12 Unit 18 CPU Engines Virtual prAMCS 14 Ethernet Interfates 18 Serial Inter
100. ace 4 3 1 4 IPMC System Event Log The Kontron IPMC implementation includes a Local System Event Log device as specified in the Section 12 of IPMI 1 5 The local System Event Log is a nonvolatile repository for the front board and all managed FRU events AMC RTM MMC built in The local SEL uses 17 4K of non volatile storage and provides space for 1023 entries However even if blade events are log into the local SEL the IPMI platform event messages are still generated by the IPMC s Event Generator and sent to the centralized SEL hosted by the Shelf Manager through the IPMB 0 communication path PICMG 3 0 chapter 3 5 IPMI 1 5 Section 23 Local SEL is useful for maintenance purposes and provides access to the events when the FRU is extracted from the Shelf 4 3 2 OEM Sensors The IPMI v1 5 specification describes most of the sensors on the Front Blade Unit However in some situation the IPMI specification does not have adequate sensor definition for the specific Unit or AdvancedTCA features To fill this gap the IPMI specification provides the ability to create OEM sensor definition that fulfills specific needs Using OEM sensor for the System Management Software requires a priori knowledge of the OEM sensor type and OEM defined Event Reading Type Code enumeration The following table describes Kontron OEM sensor Table 4 1 Kontron OEM Power Good Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cif
101. ached to IPMB 0 does so through an IPM Controller the distributed management controller of the IPMI architecture Shelf Managers attach to IPMB 0 through a variant IPM Controller called the Shelf Management Controller ShMC AdvancedTCA IPM Controllers besides supporting dual redundant IPMBs also have responsibility for detecting and recovering from IPMB faults The reliability of the AdvancedTCA 0 is improved by using two IPMBs with the two IPMBs referenced as IPMB A and IPMB B The aggregation of the two IPMBs is 0 The IPM Controllers aggregate the information received on both IPMBs An IPM Controller that has a message ready for transmit uses the IPMBs in a round robin fashion An IPM Controller tries to alternate the transmission of messages between IPMB A and IPMB B If an IPM Controller is unable to transmit on the desired IPMB then it tries to send the message on the alternate IPMB By using this approach an IPMB can become unavailable and then available without the IPM Controller needing to take specific action 4 3 1 2 IPMC System Manager Interface The Section 25 of IPMI 1 5 describes how IPMI messages can be sent to and from the IPMC encapsulated in RMCP Remote Management Control Protocol packets datagrams This capability is also referred to as IPMI over LAN IOL IPMI also defines the associated LAN specific configuration interfaces for setting things such as IP addresses other options as well as commands
102. and application software are kept in the flash memory and are field updateable The update process is described in Software Update appendix For supported RFCs and SNMP MIBs refer to appendices Supported RFCs and Supported MIBs For a comprehensive listing and description of available CLI commands refer to the CLI Reference Manual 6 2 Unit Computer Diagnostics Upon power on or system reset the bootloader performs a set of Power On Self Tests POST to check the integrity of specific components Components where a POST is available are SDRAM Serial line Ethernetinterfaces e IPMC KCS interface In the case that a POST fails a POST error code is written into the postcode high byte register ofthe onboard FPGA The boot process is not stopped as there are good chances the board can boot even in case of POST errors The postcode high byte register is also accessible by the IPMC which can report error codes to a separate management instance Thus more comprehensive diagnostic tests could be started The following table shows a list of available POST routines including POST error codes Table 6 1 POST routines and error codes Device Test POST Error Code SDRAM Data bus walking 1 test PCW_DLINE SDRAM Address bus walking 1 test PCW_ALINE SDRAM Memory read write test PCW_MEM ES UART Serial loopback teststring PCW_SERIAL 147 AT8030 User s Guide Unit Computer Management Device Test POST Error Code ES I2C Bus
103. anine Card Specification for Storage A subsidiary specification to the Advanced Mezzanine Card Base Specification 0 ARP Address Resolution Protocol American Standard Code for Information Interchange ASCII codes represent text in computers communications equipment and other devices that work with text Alert Standard Format A standard for how alerting and remote control capabilities on network controllers work ASF DA ER EV I ASCII BIOS Basic Input Output System BIST Built in Self Test I 1 AT8030 User s Guide Acronyms Descriptions CDROM Same as CD ROM Compact Disk Read Only Memory CFM Cubic Foot per Minute Comit International Sp cial des Perturbations Radio lectriques publication 22 Special International Committee on Radio Interference publication 22 CLK1A AdvancedTCA bused resource Synch clock group 1 bus A CLK3A AdvancedTCA bused resource Synch clock group 3 bus A CISPR22 CLK3B AdvancedTCA bused resource Synch clock group 3 bus B CMIC CPU Management Interface Controller CMOS Complementary Metal Oxide Semiconductor Also refers to the small amount of battery or capacitor powered CMOS memory to hold the date time and system setup parameters DDR2 Same as DDR IT DDR2 SDRAM or Double Data Rate two 2 Synchronous Dynamic Random Access Memory Same as DDR2 DDR2 SDRAM or Double Data Rate two 2 Synchronous Dynamic Random Access Memory DED Double bit Error Detect
104. ard Specifications CPU1 amp 2 Section 6 Board Specifications all 7 Compliance co coe ie x ERU e MESA 8 Hot Plug 8 Interfacing with the Environment 9 1 AT8030 User s Guide Product Description 1 Product Description 1 1 Product Overview An ideal processor node for IP Multimedia System IMS clustering applications the AT8030 AdvancedTCA processor board is designed with three Intel Core 2 Duo processors each with dedicated memory plus 10 GbEthernet GbE links on the fabric interface and one AdvancedMC slot The AT8030 provides equipment manufacturers the flexibility to customize the design of their network system solutions especially for various 10 GbE based systems that drive IMS based broadband applications that require the seamless delivery of video and data content in IPTV or VoD networks 1 2 What s Included This board is shipped with the following items e One AT8030 board e One RJ45 DB9 serial adaptor 1015 9404 One AMC gap filler e Cables that have been ordered If any item is missing or damaged contact the supplier 2 AT8030 User s Guide Product Description 1 3 Board Specifications Unit Computer Section Table 1 1 Board Specifications Unit Computer Section Features Description One PowerQUICC IIT MPC8547 1GHz Passive heatsink Memory bus at 400 MHz 72 bits wide
105. ase BX z COM2 RS232 Debug IF 2 8 4 pia CPU 1 5 8 5 5 engine ESTEE 21214 LPC 2 g FWH amp MISC 5 8 5 3 8 5 E T 4 Pals E e 82 4 2 8 Base IF 1000Base BX 5 Fabric IF 1000Base BX Sce E a CPU 2 ERES PowerQuicc 5 5 engine comt I amp R FWH amp MISC Ethernet switch E 5 gu subsystem 2 8 E E 8 z 24 62 m m RS232 a LPC AD8159 5 O rwH amp Msc 4 MUX i 54 2 RS232 E 5 MISC 8 2 P 44 els E 8 FPGA logic 9 z 2 amp E da 5 5 telco clock 5232 8 gg gt 2 amp LPC 5 7 4 Piz 2 IPMI gt Aiae 8 S Pro gpl 8 Voltage monitoring El amp 12C 8 connections not POM lt shown Telco clocks AMC e 8 Telco clocks 5 se IPMB I F t On board capacitor bank for Hold Up and pal audio filtering m Piz B Isolated gt 8 Other power Converter Mezzanine E regulators 48V to 12V 10 8 200W 5 12VSB es 12 AT8030 User s Guide Board Features 2 2 Unit Computer The Unit Computer manages the Ethernet switch of the AT8030 It is a Freescale MPC8547 which integrates a PowerPC processor core with system logic required for networking telecommunications and wireless infrastructure applications The MPC85470perates with a core frequency o
106. ational stability and long term reliability The physical size shape and construction of the heat sinks ensures the lowest possible thermal resistance Moreover the heat sinks were specifically designed to use forced airflow as found in ATCA systems Because the thermal solution is custom and critical for passive cooling Kontron does not guarantee thermal performance if the heatsinks are removed and then reinstalled by the end user 7 1 2 Temperature Sensors The AT8030 is equipped with 28 temperature sensors that are accessible via IPMI Sensors are precisely positioned near critical components to accurately measure the on board parts temperature Temperature monitoring must be exercised to ensure highest possible level of system thermal management An external system manager constitutes one of the best solutions for thermal management being able to report sensor status to end user or manage events filters for example All sensors available on the AT8030 its RTM and the AMC it can carry are listed into the Sensor Data Repository with their thresholds as defined by the PICMG 3 0 specification The following extract from the PICMG 3 0 Base Specification details naming convention for thresholds as well as the meaning of each threshold level IPMI non critical PICMG 3 0 minor telco minor A warning that things are somewhat out of normal range but not really a problem yet IPMI critical PICMG 3 0 major telco major Things are still
107. avoid the problem A ESD Sensitive Device This symbol and title inform that electronic boards and their components are sensitive to static electricity Therefore care must be taken during all handling operations and inspections of this product in order to ensure product integrity at all times Please read also the section Special Handling and Unpacking Instructions CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards Please refer also to the section Regulatory Compliance Statements in this manual Disclaimer We have tried to identify all situations that may pose a warning or a caution condition in this user s guide However Kontron does not claim to have covered all situations that might require the use of a Caution or a Warning xiv AT8030 User s Guide Preface Unpacking Follow these recommendations while unpacking e Remove all items from the box If any items listed on the purchase order are missing notify Kontron customer service immediately Inspectthe product for damage If there is damage notify Kontron customer service immediately Save the box and packing material for possible future shipment Powering Up the System Before any installation or setup ensure that the board is unplugged from power sources or subsystems If you encounter a problem verify the following items e Make sure that all connectors are properly connected
108. ay only Enter Gateway IP Address in decimalin the form of XXX XXX XXX XXX XXX less than 256 and in decimal only N A display only N A display only Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only Enter VLAN ID value in hexadecimalin the form of XXX N A display only Select if VLAN Tagged Packets are to be added or not N A display only AT8030 User s Guide Software Setup 5 1 7 8 LAN Parameter Selector Channel Number Channel Status 802 1q VLAN Priority Value Current VLAN Priority Value VLAN Priority Configuration Description 21 Valid or Invalid The parameter selector assignments are described in IPMI Specification 2 0 table 23 4 Selector 21 802 1q VLAN Priority Each interface has a channel number that is used when configuring the channel and for routing messages between channels Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Display Valid if IPMC support LAN Channel This allows setting an 802 1q VLAN priority for LAN configuration Display the current 801 1q VLAN Priority configuration stored in IPMI NVRAM for IPMI LAN 139 Help text N A display only Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only Enter VLAN Priority value in
109. b 5 4 Oh reserved 3 0 AMC Site Number 5 AMC B1 The Clock Configuration record describes the characteristics of each of the clock identified the previous record A separate record is present for each of the on carrier resources Table 4 45 0 R2 0 Clock Configuration Record 1 of 2 PCIe Clock Generator Type 2D Clock Configuration Record e Record Type ID 2h Record format version 0 Record Length Calculated Record Checksum Calculated Header Checksum Calculated Manufacturer ID 00315Ah PICMG Record ID PICMG Record ID 2D Clock Configuration Record 83 AT8030 User s Guide Hardware Management Type 2D Clock Configuration Record Record Format Version 00h Type 2D Clock Configuration Record Data 7 6 006 On Carrier device 5 4 Oh reserved 3 0 00h On Carrier Device 0 PCIe clock generator Clock Configuration Descriptor Count 0x02 Clock Configuration Descriptors Clock Id 0x00 7 1 Oh reserved Clock Control 0x00 0 0b Activated by Carrier IPMC Indirect Clock Descriptors Count m 0x00 Direct Clock Descriptors Count n 0x01 Indirect clock Descriptor Direct clock Descriptor Clock Resource Id 0x00 7 2 Oh reserved 1 0b Not connected through PLL 0 1b Clock source Family 0x02 Reserved for PCI Express Features 0x01 Accuracy Level 0x00 N A TBC unspecified 100Mhz tdb waiting for AMC 1 Frequency workgroup on FCLKA usage
110. ble 4 41 AMC Point To Point Connectivity Record 1 of 2 Ethernet Switch Type 19h AMC Point To Point Connectivity Record 1 of 2 On Carrier Ethernet Switch PICMG Record ID 19h AMC Point To Point Connectivity Record Record Format Version 00h Type 19h AMC Point To Point Connectivity Record data 1 of 2 On Carrier Ethernet Switch h AMC Channel Descriptor OFFFFE5h Ethernet Port Reserved Bits 23 20 OF 74 AT8030 User s Guide Hardware Management Type 19h AMC Point To Point Connectivity Record 1 of 2 On Carrier Ethernet Switch 75 AT8030 User s Guide Hardware Management Type 19h AMC Point To Point Connectivity Record 1 of 2 On Carrier Ethernet Switch 76 AT8030 User s Guide Hardware Management Type 19h AMC Point To Point Connectivity Record 1 of 2 On Carrier Ethernet Switch 77 AT8030 User s Guide Hardware Management Type 19h AMC Point To Point Connectivity Record 1 of 2 On Carrier Ethernet Switch 78 AT8030 User s Guide Hardware Management Table 4 42 AMC Point To Point Connectivity Record 2 of 2 Update Channel Switcher Type 19h AMC Point To Point Connectivity Record 2 of 2 On Carrier Update Channel Switcher Record Format Version 00h Type 19h AMC Point To Point Connectivity Record Data 2 of 2 On Carrier Update Channel Switcher its 4 h i 1Fh i 1Fh its 9 1Fh its 4 h Fh Fh Lane 3 Port Number Bits 19 15
111. bles protect enable or disable FLASH write protection rarpboot boot image via network using RARP TFTP protocol reset Perform RESET of the CPU run run commands in an environment variable Saveenv save environment variables to persistent storage setenv set environment variables tftpboot boot image via network using TFTP protocol version print monitor version More detailed help is displayed when entering help command gt help mm mm b w 1 address memory modify auto increment address Important commads are ordered in functional groups CMD Function Remarks printenv Print current environment variables setenv Set environment variable Normal and redundant environment are saveenv Save environment variables to persistent storage written alternately Environment Control G 2 AT8030 User s Guide Function Remarks Memory display Command without parameters displays the next memory block Memory modify auto incrementing Memory modify constant address Memory write fill This command also works when copying from and to flash cmp Memory compare crc32 Checksum calculation loop Infinite loop on address range Memory Operations cp Memory cp CMD Function Remarks flinfo Print FLASH memory information erase Erase FLASH memory protect Enable or disable FLASH write protection Flash operations CMD Function Remarks Short or long list of PCI devices on specifi
112. cation PICMG 3 1 Ethernet Fiber Channel over Advanced TCA PICMG AMC 0 Advanced mezzaninne card base specification PICMG AMC 1 Advance mezzaninne card PCI Express PICMG AMC 2 Advance mezzaninne card Ethernet PICMG AMC 3 Advance mezzaninne card Storage Red Hat Enterprise Linux 5 Wind River PNE Linux 1 5 38Vdc to 72 Vdc for Canada and USA input voltage must not exceed 60Vdc for safety compliance 200W maximum including 25W budget for an AMC module Additional 25W maximum for RTM Operating 0 55 C 32 131 F with 30 CFM airflow Storage and Transit 40 to 70 C 40 to 158 F Operating 5 to 93 40 C 104 F non condensing Storage and Transit 5 to 95 40 C 104 F non condensing Operating 4 000 m 13 123 ft Storage and Transit 15 000 m 49 212 ft Operating 3G each axis Storage and Transit 18G each axis Operating 5 200Hz 0 2G each axis Storage and Transit 5 Hz to 20 Hz 1 m2 s3 0 01 g2 Hz flat 20 Hz to 200 Hz 2 3 dB oct slop down MTBF gt 105 000 hours 40 C 104 F Telcordia SR 332 Issue 1 AMC supply protected by active breaker USB voltage protected by active breakers Safety CB report to IEC60950 1 CE Mark to EN 60950 1 2001 Meets or exceeds UL 60950 1 CSA C22 2 No 60950 1 07 Designed to meet GR 1089 CORE EMI EMC FCC 47 CFR Part 15 Class A CE Mark to EN55022 EN55024 EN300386 Designed to meet or exceed 7 AT8030 User s Guide Product Description 1 7 Compliance T
113. ce compared to the KCS IPMB interfaces that are session less interface Also the LAN interface is considered as a not secure interface compared to the KCS IPMB Authentication and privileges level has been added for the commands that are critical to the system With IOL 2 0 the concept of data integrity and confidentiality has been also added to offer full security 109 AT8030 User s Guide Hardware Management 4 5 5 1 IPMI Sessions Authentications and Users With the addition of LAN interface the concept of sessions has been introduced in IPMI Authenticated IPMI communication to the MCis accomplished by establishing a session Once established a session ID identifies a session The Session ID may be thought as a handle that identifies a connection between a given remote user and the IPMC Session less connections IPMB KCS etc Multisession connections LAN etc Four different sessions is available at the same time for multisession connections For more information about session activation see IPMI specification 2 0 Markup 2 May 2005 section 6 12 7 Inactive sessions are closed after 1 minute as per IPMI specification Markup 2 2005 section 6 12 15 The session must be re authenticated to be restored 4 5 5 1 1 Authentication Integrity and Confidentiality For each session type RMCP RMCP some algorithms types are available RMCP supported algorithms are Authentication None Straight Password There is no co
114. ces and PnP ISA cards It also assigns PCI bus numbers Function 1 initializes all static devices that include manual configured onboard peripherals memory and 1 0 decode windows in PCI PCI bridges and noncompliant PCI devices Static resources are also reserved Function 2 searches for and initializes any PnP PCI or AGP video devices Initialize different buses and perform the following functions Boot Input Device Initialization function 3 IPL Device Initialization function 4 General Device Initialization function 5 Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller Function 4 searches for and configures all PnP and PCI boot devices Function 5 CONFIGURES all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices OEM PCT init debug POST code during DIMM init DEh during BUS number assignment and DDh during ressource allocation Hight byte is the BUS number While control is in the different functions additional checkpoints are output to port 80h as a word value to identify the routines under execution The low byte value indicates the main POST Code Checkpoint The high byte is divided into two nibbles and contains two fields The details of the high byte of these checkpoints are as follows HIGH BYTE XY The upper nibble X indicates the function number that is being executed X can be from 0 to 7 0 func
115. cessor to prevent application code access to certain memory areas Needs supporting 0S Disabled No restrictions to application code memory area access by processor AT8030 User s Guide Software Setup 5 1 6 Feature Boot Settings Configuration Boot Device Priority Hard Disk Drives Removable Drives CD DVD Drives USB Drives Network Drives Other Drives 5 1 6 1 Feature Quick Boot Mode Extended Memory Test Boot Menu Option N A N A N A Description Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Boot Settings Configuration sub menu Enabled Disabled Enabled Disabled Description Allows denies skipping the memory tests during a cold boot Quick Boot enabled has no impact on a warm reset boot since then memory is not initialized during a warm reset If enabled extended memory test is applicable when Quick Boot is disabled and a cold reset occurs If disabled extended memory test is not performed except if memory configuration has changed or in the very first boot of the blade Warm reset should always be as fast as possible and extended memory testis never executed in warm reset Help text Selects boot settings configuration Selects boot device priority Lists available hard disk drives in priority order Lists available removable disk dri
116. code cific offset Event Trigger 00h 018 03h CFh State Standard IPMI OEM Kontron Reset Asserted Discrete State Deasserted 41 Event Data 2 Reset Type 00h Warm reset O1h Cold reset 02h Forced Cold Warm reset reverted to Cold 03h Soft reset Software jump Event Data 3 Reset Source 00h IPMI Watchdog cold warm or forced cold IPMI Watchdog2 sensors gives additionnal details O1h IPMI commands cold warm or forced cold chassis control fru control 02h Processor internal checkstop 03h Processor internal reset request 04h Reset button warm or forced cold 05h Power up cold 06h Legacy Initial Watchdog Warm Reset Loop Detection cold reset 07h Legacy Programmable Watchdog cold warm or forced cold 08h Software Initiated soft cold warm of forced cold 09h Setup Reset Software Initiated Cold FFh Unknown AT8030 User s Guide Hardware Management 4 4 4 4 1 Supported commands The table below lists the IPMI commands supported by the IPMC FRUO This table is identical as the one provided by and PICMG 3 0 The last column states the Kontron support for the specific command Table 4 13 IPM Device Supported Commands for IPMC addc NetFn Carrier IPMC req Kontron support on IPMC IPM Device Global Commands Get Device ID 17 1 App 018 Cold Reset App 02h Warm Reset 17 3 App 03h Get Self Test Results 17 4 App 0
117. d Exits the Setup utility without saving any changes and then performs a swap of the on board BIOS FWH chips If the currently executing BIOS was the primary BIOS the system would change to the backup BIOS and vice versa 142 Exit system setup saving changes to non volatile memory Exit system setup without saving changes Load default settings Discard changes without exiting setup Force BIOS recovery mode on next system reset Swap BIOS FWH without saving any changes AT8030 User s Guide Software Setup 5 2 Boot Utilities AMI Boot Utilities are Boot Menu POP UP Boot Menu POP UP is a boot screen that displays a selection of boot devices from which you can boot your operating system 5 2 1 Pressing F2 Pressing lt F2 gt during POST enters Setup 5 2 2 Pressing lt F11 gt or F3 from a Console Redirection terminal Pressing lt F11 gt or F3 from a Console Redirection terminal displays the Boot Menu POP UP with these options 1 Loadthe operating system from a boot device of your choice 2 Exit the Boot Menu POP UP with lt ESC gt and load the operating system from the boot devices in the order specified in Setup 5 2 3 BOOT Menu POP UP The BOOT Menu POP UP expands your boot options by letting you choose your boot device which could be a hard disk floppy disk CDROM Flash Disk SCSI or LAN You can select your boot device in Setup or you can choose a different dev
118. d Default CPU speed is used Minimum speed 1000 MHz Maximum speed 1500 MHz N A display only Enabled CMP is in use i e both CPU cores are available Disabled CMP is not used Only Core 0 is available Enabled TM1 in use Disabled TM1 notin use Use only for testing purposes Enabled TM2 in use Disabled TM2 not in use Use only for testing purposes Enabled DTS for each core is in use AT8030 User s Guide Software Setup 5 1 4 4 Feature ACPI 2 0 Support ACPI APIC Support Headless Mode ACPI Configuration sub menu Enabled Disabled Enabled Disabled Enabled Disabled Description Support for 64 bit addressing for ACPI System Description Tables can be enabled disabled Support for ACPI APIC table pointer to Root System Description Table RSDT pointer list can be enabled disabled Headless operation mode through ACPI can be enabled disabled 123 Help text Enabled 64 bit addressing supported for ACPI system description tables Disabled Only 32 bit addressing supported for ACPI system description tables Enabled ACPI APIC table support Disabled ACPI APIC table not supported Enabled Headless operation mode through ACPI supported Disabled Headless operation mode through ACPI not supported AT8030 User s Guide Software Setup 5 1 4 5 Feature Event Log capacity Event Logging View Event Log Mark Events as read
119. d base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 80 C After Thermal Analysis Upper Critical event 90 After Thermal Analysis Upper Non Recoverable 105 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Power Mezzanine 12v Output Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 70 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 110 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Power Mezzanine Feed A Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 70 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 110 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis 53 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Temp 48 B Feed Power Good Power Good Event Vcc 48 V A Feed Vcc 48 V B Feed Fuse Pres A Feed Fuse Pres B Feed Fuse
120. d conversely is isolated from the need to process network traffic for other VLANs IPMIIOL end node supports Ethernet II VLAN tagged frame format This supports is provided by the 82571EB 4 5 6 Serial Over Lan This section provides the information required to establish an IPMI Over LAN sessions and activate the SOL payload in order to get an active SOL console sessions In addition to the board payload supporting the IOL 112 AT8030 User s Guide Hardware Management CPUx engine a second CPU is required in order to remotely establish the IOL sessions This second CPU is referred as the remote CPU and can be any computers no IPMI support required Figure 4 1 Serial Over Lan Remote Network Board with CPU Switch IOL SOL 4 5 6 1 Configuring the IOL and SOL on the board payload 4 5 6 1 1 Configuring the IPMI Over LAN IOL 1 Enterthe BIOS setup 2 Go to LAN configuration menu LAN Configuration menu is located under System Management There is only 1 channel connected to the base interface 3 Set LAN channel IP Address Subnet Mask and if required the Gateway Address the corresponding menu The IOLIP address is static and does not support DHCP Normally the IOLIP address matches the corresponding base address LAN interface 4 Setthechannelto Active Only 1 channel is available so choose Disabled or Activate Channel 1 5 Stayin CMOS setup to configure SOL 4 5 6 1 2 Configuring the Serial Over LAN SOL 1 Gotothe
121. d Enabled offset 0 and 1 are used offset 0 event trigger chassis telecom clock support Disable offset 1 event trigger chassis telecom clock support Enable see IPMI v1 5 table 36 3 Sensor type code 24h Platform Alert for sensor definition U BOOT Boot error sensor Sensor type 1Eh Boot Error Event Reading type code 6Fh Sensor specific offset 0 and 3 are used offset 0 event trigger OS load failed offset 3 event trigger Boot monitor load failed see IPMI v1 5 table 36 3 Sensor type code 1Eh Boot Error for sensor definition 60 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event Trigger U BOOT System Firmware Progress Sensor type OFh System Firmware Progress Event Reading type code 6Fh Sensor specific only offset 0 is used offset 0 event data 2 00h unspecified event trigger A Boot monitor POST failure offset 0 event data 2 OBh Firm corruption event trigger Boot monitor backup image loaded Primary boot monitor corrupted see IPMI v1 5 table 36 3 Sensor type code OFh System Firmware Progress for sensor definition PQ3 POST Error Show current U BOOT postcode value No event generated by this sensor Sensor type C6h OEM Kontron POST value sensor PQ3 POST Value Event Reading type code 6Fh Sensor specific offset 0 to 7 and 14 are used see table sws 10 1140 for event trigger information PQ3 OS critical Stop Sensor
122. d Properties 3 63 PICMG 14h N A Set Fan Level 3 65 PICMG 15h N A Get Fan Level 3 64 PICMG 16h N A Bused Resource 3 44 PICMG 17h N A Get IPMB Link Info 3 49 PICMG 18h N A FRU Control Capabilities 3 24 PICMG 1Eh Yes PICMG ODh N A PICMG 10h N A N A 99 AT8030 User s Guide Hardware Management Table 4 66 AMC 0 Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC AMC AMC 0 Table Set AMC Port State Table 3 27 PICMG 19h 0 M Yes Get AMC Port State Table 3 28 PICMG 1Ah Yes Set Clock State Table 3 44 PICMG 2Ch Yes Get Clock State Table 3 45 PICMG 2Dh Yes 4 5 2 Sensor Data Records 4 5 2 1 MMC Built in FRU2 FRU3 FRU4 sensors Built in MMCs have the capability of supporting any of the IPMI or OEM sensor types similar to an IPM Controller on an AdvancedTCA Board The MMC s sensors on IPMB L are visible to the Shelf Manager through the Front Blade Unit Carrier IPMC over Since the IPMC must present unique sensor numbers and sensor LUN over 0 it is necessary for the Front Blade Unit pseudo Carrier IPMC to translate the MMC s sensor number and sensor LUN to Carrier IPMC wide unique numbers The Unit Carrier IPMC device SDR repository holds a combination of its own SDRs and SDRs from the built in Module s MMC The Unit Carrier IPMC adds the MMC s SDRs into its SDR Repository after Management Pow
123. dustrial Computer Manufacturers Group PIR Product Issue Report PIU Plug In Unit PLCC Plastic Leaded Chip Carrier PLD Programmable Logic Device PLL Phase Lock Loop PCI Mezzanine Card POST Memory Manager Platform for Network Equipment A Carrier Grade Linux 4 0 platform System Operating Power On Hours Power On Reset Power On Self Test Point to Point Protocol Processor AMC Programmable Read Only Memory Prepare To Sleep An ACPI method called before the OS makes a change to system power state level Same as PCB Printed Wiring Board Pulse Width Modulation Preboot eXecution Environment QuickPath Interconnect Point to point interconnect between Intel processors and IOH Redundant Array of Independent Disks Redundant Array of Inexpensive Disks RMCP Authenticated Key Exchange Protocol Random Access Memory Row Address Strobe used in DRAM May also refers to Reliability Availability Serviceability features of the chipset Reliability Availability Serviceability Usability and Manageability features of the chipset AER and ECC are RASUM features Root Complex Register Block registers Chipset memory mapped space for configuration registers Reduced Gigabit Media Independent Interface Red Hat Enterprise Linux Rambus Inline Memory Module Remote Management Control Protocol 1 8 AT8030 User s Guide Acronyms Descriptions RMII Reduced Media Independent Interface RMON Remote network MONitoring
124. e P I32bits 66MHz Expansion Slot None Up to 512 MB on 1x200 pin latching DDR 2 400MHz SDRAM SO CDIMM System Memory ECC support support SEC DED 1 DDR 2 channel Flash Memory 256 NOR Flash Connectors 1 selectable Serial Port RJ 45 Management Controller compliant to PICMG 3 0 R2 2 0 R2 0 and IPMI v1 5 rev 1 1 Management Controller is run time field reprogrammable without payload impact Robust fail safe bootblock implementation Remote upgrade capability from all IPMI interfaces Host Interface IPMB 0 LAN compliant to HPM 1 Fast interrupt driven SMS host interface compliant to IPMI KCS v1 5 rev 1 1 Standard Management Controller message bridging to AMC via IPMB L Management Controller support standard PCI Hot Plug for PCI Express AMC IPMIWatchdog supporting FRB2 POST OS Load and SMS OS watchdog with interrupt on pretimeout SEL System Event Log support with storage for up to 1023 events FRU Inventory Area support SENSOR device support 0 R2 0 Clock Ekeying support PICMG 3 0 Bused Resource Control support Processors Bus Interfaces IPMI Features Supports a system management interface via an IPMI V1 5 compliant controller Watchdog for Boot Loader execution and OS loading through IPMI and FPGA Supervisory watchdogs Hardware system monitor voltages temperature CPU temperature monitor alarm board temperature sensor power failure through IPMC 3 AT8030 User s Guide Product
125. e 4 59 Table 4 60 Table 4 61 Table 4 62 Bridge ICMB Management Supported Commands 47 Discovery ICMB Commands for 48 Bridging Commands for 48 Event ICMB Commands Tor 48 OEM for Bridge NetFn Commands 49 Other Bridge ICMB Commands for 49 PICMG 3 0 Commands for IPMC 49 AMC O Carrier Commands for 50 e EK EEE ES 51 ERUO Sensor res S cn nee mn em es wie 62 ES Board Information 63 ES Product Information 64 Board Point to Point Connectivity 65 AMC Carrier Activation and Current Management 67 Carrier Information Table 68 Carrier Point To Point Connectivity 68 Point To Point Connectivity Record 1 of 2 Ethernet Switch
126. e 46h Clear SEL 25 9 Storage 47h Get SEL Time 25 10 Storage 48h Set SEL Time 25 11 Storage 49h Get Auxiliary Log Status 25 12 Storage 5Ah Set Auxiliary Log Status 25 13 Storage 5Bh z o a CO ojo d m Em e CO 2 a e 2 Table 4 23 LAN Device Supported Commands for IPMC NetFn Carrier IPMC Kontron support on req IPMC LAN Device Commands 0 0 Set LAN Configuration Parameters Get LAN Configuration Parameters Suspend BMC ARPs 19 3 Transport 03h 0 M 0 M Get IP UDP RMCP Statistics 19 1 Transport 01h 0 M 0 M 19 2 Transport 02h 0 M 0 M 19 4 Transport 04h 0 0 46 AT8030 User s Guide Hardware Management Table 4 24 Serial Modem Device Supported Commands for IPMC IPMISpec section NetFn CMD i IPMI BMC req IPMC Kontron support on IPMC Serial Modem Device Commands Set Serial Modem Configuration Get Serial Modem Configuration Set Serial Modem Mux 20 3 Transport 12h Get TAP Response Codes 20 4 Transport 13h Set PPP UDP Proxy Transmit Data Get PPP UDP Proxy Transmit Data Send PPP UDP Proxy Packet Get PPP UDP Proxy Receive Data Serial Modem Connection Active Callback 20 10 Transport Set User Callback Options Get User Callback Options Transport 20 2 Transport 11h 0 M 20 5 Transport 14h 20 6 Transport 15h 20 7 Transport 16h 20 8 Transport 17h 20 9 Transport 18h 0
127. e Data two computers TCLKD Telecom CLocK D AMC Clock Interface 1 10 8030 User s Guide Acronyms Descriptions T Total Cost of Ownership Refers to a logic block in the Intel ICH products family The watchdog timer WDT is one of the functions of that logic block Transmission Control Protocol Thermal Design Power UDP User Datagram Protocol An Internet Protocol 0 1 Thermal monitor 1 CPU Thermal based on clock throttling 2 itor 2 TuS M D TC TD TM Same as TM1 Thermal monitor CPU Thermal based on clock throttling TM TM Thermal monitor 2 CPU Thermal based on Enhanced Intel SpeedStep Technology transitions P UA UC Universal Host Controller Interface Specification for Universal Serial Bus specification revision 1 0 voltages WWPN World Wide Port Name X meaning ten Attachement Unit Interface A standard for connecting 10 Gigabit Ethernet 10GbE ports XDP eXtended Debug Port XMC Switched Mezzanine Card L PM B C z D VGA Video Graphics Array T D DT i fM WN XAUI 1 11 AT8030 User s Guide
128. e Port 0 and 1 8 11 connected to onboard Ethernet Switch Provision for telecom clocks on TCLKA B C D SAS link to the CPU Engine 0 SAS controller and an other SAS link to the RTM connector Compliant to 0 1 AMC 2 and AMC 3 As per AMC 1 R2 0 the carrier board is required to provide PCI E 100MHz reference clock to the AMC on FCLKA However modules are not required to use it Kontron recommends using AMC Express modules that use the reference clock on FCLKA If the module makes its own reference clock then the spread spectrum of CPU Engine 0 5 PCI Express clock synthetizer will be disabled by e keying otherwise the behavior of the PCI Express link will be erratic Note All electromagnetic compatibility testing has been done with spread spectrum Disabling the spread spectrum can complicate EMC The SAS interface on port 2 allow to use SAS AMC storage mezzanine with AT8030 however it can also accommodates SATA drives It is correct electrically to hot swap a SATA SAS AMC but it may cause driver problem in different operating system The telco clock signals allow the AT8030 to provide clocks to the AMC on TCLKA and TCLKC Tt also allows an AMC to retrieve a clock and to provide it to the system through TCLKB and TCLKD For possible clock frequency and connection with the backplane refer to section Telecom Clock Option 14 BIOS Settings 000 24 Advanced gt PCI Express Configuration SAS SATA gt Expansion
129. e either e the faceplate through SFF 8470 connector for cabling signal integrity garanted over 6 meters Through an onboard SFF 8482 hard drive receptacle 1 9 1 3 Serial Port Feature Two serial ports available on the RTM face plate through two RJ 45 connectors e RS 232 signal levels at RTM face plate connector Serial port speed capability is 9 6kbits s to 115 2kbits s 1 9 1 4 Hot Swap The RTM8030 supports hot swapping by using the switch connected to the face plate lower ejector This switch indicates the coming hot swap action The insertion of the RTM to a slot is always done over a non powered connector During the extraction procedure the management power is disabled only when the RTM8030 is removed This procedure meets the AdvancedTCA AMC behavior 1 9 1 4 1 Inserting the RTM8030 into the slot The presence of the RTM is indicated by one signal The front blade IPMC recognizes the RTM insertion when the signal is low After recognizing the RTM the IPMC turns the blue LED ON and enables the management power to the RTM Once the IPMB L link is working the IPMC accesses the MMC to retrieve FRU data After knowing the type of RTM inserted the IPMC negotiates with the shelf manager in order to activate the 12 payload power After RTM local voltages have been ramped up the RTM s MMC enables the RTM Link After this the front board IPMC informs the shelf manager there is a functional RTM blade present 9 AT8030
130. e errors found in successive SMI interrupts are not masked Note Duplicate errors in single SMI interrupt are always masked Yes Unsupported request errors can be masked No Default mask is used AT8030 User s Guide Software Setup 5 1 4 7 Ethernet BI Expansion ROM Ethernet FI Expansion ROM Management Ports Expansion ROM CPU 0 only SAS Expansion ROM CPU 0 only AMC Slot Expansion ROM CPU 0 only 5 1 4 8 Feature AMC Slot Hot Plug Support CPU 0 only Expansion ROM Configuration sub menu Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Description The base interface PXE Expansion ROM can be enabled disabled If disabled remote LAN boot via base interface is not available to boot the system The fabric interface PXE Expansion ROM can be enabled disabled If disabled remote LAN boot via fabric interface is not available to boot the system The Management Ports PXE Expansion ROM on the face plate can be enabled disabled If disabled remote LAN boot via the management ports on the face plate is not available to boot the system The SAS Expansion ROM can be enabled disabled If disabled any SAS devices attached to the system are not available to boot the system Enables or disables AMC Slot Expansion ROM s if any detected If disabled AMC Expansion ROM s code will not be executed during PO
131. e on SOC DIMM sensor 9 if absent on board diode is used Sensor type 25h Entity Presence Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger no event generated Entity Present offset 1 event trigger no event generated Entity Absent see IPMI v1 5 table 36 3 Sensor type code 25h Entity Presence for sensor definition Temp Pres SPDO 61 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event Trigger Fault status on SAS 0 link hook on CPUO Sensor type 24h Platform Alert Event Reading type code 03h Digital Discrete offset 0 1 are used Fault SASO offset 0 event trigger no critical sensors is asserted offset 1 event trigger one or multiple critical sensors are asserted see IPMI v1 5 table 36 3 Sensor type code 25h Entity Presence for sensor definition Fault on SAS 1 link hook on CPUO Sensor type 24h Platform Alert Event Reading type code 03h Digital Discrete offset 0 1 are used Fault SAS1 offset 0 event trigger no critical sensors is asserted offset 1 event trigger one or multiple critical sensors are asserted see IPMI v1 5 table 36 3 Sensor type code 25h Entity Presence for sensor definition Internal IPMC firmware diagnostic IPMI Info 1 event trigger internal error condition Internal IPMC firmware diagnostic IPMIInfo 2 event trigger internal error condition 4 4 2 2 IPMC F
132. e priority of the available boot sources Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device AT8030 User s Guide Software Setup 5 1 6 4 Feature 1st Drive Nth Drive 5 1 6 5 1st Drive Nth Drive Removable Drives sub menu Description Specifies the boot priority of the available Varies x Removable devices Specifies the boot priority of the available Removable devices CD DVD Drives sub menu Option Description Varies DVDDisk devices Varies 132 Specifies the boot priority of the available CD Specifies the boot priority ofthe available CD DVD Disk devices Help text Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Selectthe boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the select
133. ed bus i header Show header of PCI bus device function PCI CMD Function Remarks bootp Boot image via network using BootP TFTP protocol tftpboot Boot image via network using TFTP protocol Boot image via network using RARP TFTP protocol MII utility commands U boot does not respond to ICMP echo ping Send ICMP ECHO REQUEST to network host requests Networking functions G 3 AT8030 User s Guide CMD Function Remarks This command is used to start the operating system go Start application at specified address Kernel and ramdisk images for u boot are preceded by a 64 byte header bootm Boot application image from memory iminfo Print header information for application image Application Control CMD Function Remarks A pointer to the board info structure is passed when starting the linux kernel echo Echo args to console bdinfo Print board info structure reset Perform RESET of the CPU run run commands in an environment variable version Print monitor version Miscellaneous Commands G 3 Bootloader Environment The u boot environment is a set of variables that can be used to customize the bootloader s startup behaviour The environment is stored in a sector of the flash memory and copied into RAM upon bootloader startup It is possible to change environment variables using the setenv command Changes take place in the copy of the environment located in the RAM they are stored perma
134. em The System Manager uses the Sensor Device Commands to gather this information Thus commands such as Get Device SDR Info and Get Device SDR which are optional in the IPMI specification are mandatory in AdvancedTCA systems Most of the current Shelf Manager implementation gathers the individual Device Sensor Data Records of each FRU into a centralized SDR Repository This SDR Repository may exist in either the Shelf Manager or System Manager If the Shelf Manager implements the SDR Repository on board it shall also respond to SDR Repository commands This duplication of SDR repository commands creates sometime some confusion among AdvancedTCA users This is mandatory for IPMC to support the Sensor Device Commands for IPMC built in SDR as described in the IPMI 1 5 specification Section 29 Sensor Device Commands For the ShMC the same set of commands forthe centralized SDR Repository must be supported but they are described in the IPMI 1 5 specification Section 27 SDR Repository Commands 4 4 2 1 IPMC FRUO sensors Table 4 33 FRUO sensors IPMI sensor ID Sensor Name Description Sensor Type Event Trigger ATCA Board FRU Hot Swap Sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific see PICMG 3 0R2 0 section 3 2 4 3 for event trigger and sensor definition External AMC Bay B1 Hot Swap sensor Sensor type FOh PICMG Hot Swap Event Reading type code 6Fh Sensor specific
135. emperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 90 C After Thermal Analysis Upper Critical event 100 C After Thermal Analysis Upper Non Recoverable 115 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Dual PHY Copper Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 80 C After Thermal Analysis Upper Critical event 90 C After Thermal Analysis Upper Non Recoverable 105 C After Thermal Analysis Hysteresis 2 deg C value can be adjusted after thermal analysis SOC DIMM Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 75 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 100 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis Air inlet Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29
136. enabled disabled The EHCI support enabled Disabled ownership change should be claimed by an Disabled EHCI hand off EHCI driver support disabled USB 2 0 Controller Mode BIOS EHCI Hand Off External USB storage Devices booting can be Enabled On board or disabled External USB storage This is used to prevent booting from external devices can boot the USB hard drive CD ROM floppy or memory system stick Disabled Only on board This option only affect USB booting not 05 USB storage device can support for USB storage devices bootthe system External USB Storage Enabled Booting Disabled USB Mass Storage Device Configuration Configure the USB Mass only present if USB Mass Storage Class Devices Storage detected 514 10 USB Mass Storage Device Configuration sub menu Feature Option Description Help text Device 41 6 Mass Storage Device identification If Auto USB devices less than 530MB will be emulated as Floppy and remaining as hard drive drive Forced FDD option can be used to force a Forced FDD option can Hard Disk HDD formatted drive to boot as FDD Ex ZIP Re d HDD CDROM drive formatted drive to boot as FDD Auto If Auto USB devices less than 530MB will be Floppy emulated as Floppy and remaining as hard Emulation Type for each Forced FDD devices 127 AT8030 User s Guide Software Setup 5 1 4 11 Feature Memory Remapping Feature DMA C
137. er MP has been enabled to the built in MMC Conversely the MMC s SDRs are removed from the Unit Carrier IPMC s SDR repository after Management Power MP has been removed from a MMC As mentioned previously when the Carrier IPMC adds the MMC s SDRs into its SDR repository it needs to ensure that the sensor number and sensor LUN assigned are unique to the Unit Carrier IPMC This is the list of FRU2 FRU3 FRU4 sensors 100 AT8030 User s Guide Hardware Management Table 4 67 MMC Built in FRU2 FRU3 FRUA sensors IPMI sensor ID Sensor Name Description Sensor Type Event trigger 0 Module Hot Swap Sensor Sensor type F2h PICMG Hot Swap Event Reading type code 6Fh Sensor specific see 0 R2 0 section 3 6 6 for event trigger and sensor definition Module Data agent that verify FRU Data validity checksum E key etc Sensor type C5h OEM Kontron FRU Info Agent Event Reading type code OAFh Generic Discrete offset 6 8 are used see table sws 10 1138 for event trigger information IPMB L fault detection sensor Sensor type C3h OEM Kontron IPMB L link state Event Reading type code 6Fh Sensor specific offset 2 and 3 are used see table sws 10 1139 for event trigger information BX ModuleHotSwap BX FRU Agent BX IPMBL State Management sub system health non volatile memory error Sensor type 28h Management Subsystem Health BX MMC Stor Err Event Reading type code 6Fh Sensor specific only off
138. er and integrated into the BIOS to test and intialize the system memory Most Significant Byte Message Signaled Interrupts Model Specific Register inside IA32 processors Mean Time Between Failures Memory Type Range Register CPU cache control registers MUltipleXer Type of Flash Memory used for mass storage Not Connected S 5 E gt zi al A Non Disclosure Agreement NEBS Network Equipment Building System PAE Physical Address Extension Feature of x86 processors that allows for up to 64 gigabytes of physical memory to be used in 32 bit systems given appropriate operating system support PAM Programmable Attribute Map Chipset registers that controls the steering of read and write cycles that address the BIOS area 1 7 AT8030 User s Guide Acronyms Descriptions PECI Platform Environment Control Interface PECL Positive Emitter Coupled Logic PEF Platform Event Filtering An IPMI subfunction PET Platform Event Trap An IPMI message type PEM Power Entry Module PERR Parity ERRor A signal on the PCI bus that indicates a parity error on the bus PHYsical layer Generic electronics term referring to a special electronic integrated circuit or functional block of a circuit that takes care of encoding and decoding between a pure digital domain on off and a modulation in the analog domain PIC Programmable Interrupt Controller PICMG PCI Industrial Computer Manufacturers Group PICMG PCI In
139. erature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 95 C After Thermal Analysis Upper Critical event 105 C After Thermal Analysis Upper Non Recoverable 120 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis BX Temp FI BI CPU Vcore Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 95 After Thermal Analysis Upper Critical event 105 C After Thermal Analysis Upper Non Recoverable 120 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis BX Temp Vcore MCH Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 85 C After Thermal Analysis Upper Critical event 95 C After Thermal Analysis Upper Non Recoverable 110 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis BX Temp MCH Memory DIMM Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following t
140. ershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 12 60v 5 Lower Critical event 11 40v 5 Hysteresis 0 180v 1 5 Voltage on 2 5v REF board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 2 63v 5 Lower Critical event 2 37v 5 Hysteresis 0 038 1 5 Voltage on 12v AMC power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 12 60v 5 Lower Critical event 11 40v 5 Hysteresis 0 180v 1 5 Voltage on 12v RTM power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 12 60v 5 Lower Critical event 11 40v 5 Hysteresis 0 180v 1 5 Sensor type 24h Platform Alert Event Reading type code 03h digital Discrete deasserted asserted offset 0 and 1 are used offset 0 event trigger deasserted telecom clock synchronisation alarm deasserted offset 1 event trigger asserted telecon clock synchronisation alarm asserted Sensor type 24h Platform Alert Event Reading type code 03h digital Discrete Disable
141. eserved 1 0b Not Connected through PLL 0 1b Clock Source Direct clock Descriptor none Clock Id 0x06 Clock Control 0x01 Source output to TCLKA 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x04 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Features Descriptor 0 Dependent ClockId 7 2 Oh reserved 1 1b Connected through PLL 0 1b Clock Source AT8030 User s Guide 87 Hardware Management Type 2D Clock Configuration Record 7 2 Oh reserved Features 1 1b Connected through PLL 0 1b Clock Source Descriptor 1 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 1b Clock Source Descriptor 2 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 1b Clock Source Descriptor 3 Dependent ClockId 3 Direct clock Descriptor none Clock Id 0x07 Source output to TCLKC 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x04 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Cloc k 7 2 Oh reserved Desc Features 0x02 1 1b Connected through PLL Clock Control 0x01 ript 0 1b Clock Source o n fes Dependent ClockId 0 7 2 Oh reserved Features 1 1b Connected through PLL 0 1b Clock Source Dependent ClockId 7 2 Oh reserved
142. esistance while inserting the board 3 Screwthe frontplate to the enclosure to firmly attach the board to its enclosure 4 Useextractor handles to disconnect and extract the board from its enclosure WARNING Always use grounding wrist wrap before installing or removing the board from A chassis 3 5 1 Installing the Card in the Chassis To install card in a chassis 1 Remove the filler panel of the slot or see Removing the Board below 2 Ensure the board is configured properly 3 Carefully align the PCB edges in the bottom and top card guide 4 Insert the board in the system until it makes contact with the backplane connectors 5 Using both ejector handles engage the board in the backplane connectors until both ejectors are locked 6 Fasten screws at the top and bottom of the faceplate 3 5 2 Removing the Board If you would like to remove a card from your chassis please follow carefully these steps 1 Unscrew the top and the bottom screw of the front panel 2 Unlock the lower handle latch depending on the software step this may initiate a clean shutdown of the operating system 3 Wait until the blue LED is fully ON this mean that the hot swap sequence is ready for board removal 4 Use both ejectors to disengage the board from the backplane 5 Pull the board out of the chassis 31 AT8030 User s Guide Installing the Board 3 5 3 Installing To install an AMC 1 Remove the AMC filler panel
143. etf secsh transport 16 SSH Transport Layer Protocol Draft ietf secsh userauth 17 SSH Authentication Protocol Draft ietf secsh connect 17 SSH Connection Protocol Draft ietf secsh architecture 14 SSH Protocol Architecture Draft ietf secsh publickeyfile 03 SECSH Public Key File Format Draft ietf secsh dh group exchange 04 Diffie Hellman Group exchange for the SSH Transport Layer Protocol Configurable Management VLAN ID Industry Standard CLI F 1 2 Switching IEEE 802 3ac VLAN Tagging IEEE 802 3ad Link Aggregation with Static LAG and LACP support IEEE 802 15 Multiple Spanning Tree IEEE 802 1W Rapid Spanning Tree IEEE 802 1D Spanning Tree GARP F 2 AT8030 User s Guide GVRP Dynamic VLAN Registration GMRP Dynamic L2 Multicast Registration IEEE 802 10 Virtual LANs with Port Based VLANs IEEE 802 1v Protocol based VLANs IEEE 802 1p Ethernet Priority with User Provisioning amp Mapping IEEE 802 1X Port Authentication IEEE 802 3x Flow Control IGMP Snooping Port Mirroring Broadcast Storm Recovery Static MAC Filtering Double VLAN vMAN Tagging Jumbo Frames IPv6 Classification APIs XMODEM RFC 768 UDP RFC 783 TFTP RFC 791 IP RFC 792 ICMP RFC 793 TCP RFC 951 BOOTP RFC 1321 Message Digest Algorithm MD5 RFC 1534 Interoperation between BOOTP and DHCP RFC 2030 Simple Network Time Protocol SNTP Version 4 for IPv4 IPv6 and OSI RFC 2131 DHCP Client RFC 21
144. f 1000MHz and 400MHz Core Complex Bus CCB frequency respective DDR2 SDRAM data rate 512MB external onboard DDR2 400MHz SDRAM with ECC support are available to the Unit Computer Memory used is standard SO CDIMM module using a DDR II SODIMM socket The boot code is fetched from two external NOR FLASH memory chips Two 1024Mb NOR FLASH memory chips are assembled resulting in a total of 256 Mbytes of Flash Memory The FLASH memory is connected to the LBC bus of the MPC8547 in 32bit port size The Unit Computer manages the Ethernet Switch via the 32bit 66MHz PCI local bus and acts as the PCI host processor with internal PCI arbiter The PCI interface operates synchronously to the system clock The Unit Computer is connected to the FPGA via the LBC bus in 8bit port size The LBC controller operates at a frequency of 50 MHz or 66 MHz depending on the MPC8547 speed The Unit computer has 3 Ethernet connections One 1000Base BX to the Base Interface One 1000Base BX to the Fabric Interface One 10 100Base TX to the RTM 13 AT8030 User s Guide Board Features 2 3 Engines Virtual prAMCs 2 3 1 CPUO Engine 2 3 1 1 Serial Attached SCSI SAS The CPU engine 0 includes a SAS controller LSISAS1064E This controller embeds four 3 Gb s SAS link but only two are used One port goes to the AMC storage port 2 and the other port is routed to the Zone 3 RTM connector The AMC storage port 3 is a direct connection to the Zone 3 RTM co
145. faces 20 ad 21 226 22 Telecom Clock Option eee herren enne 22 Redundant IPMC MMC Firmware amp BootBlock 23 11 AT8030 User s Guide Board Features 2 Board Features 2 1 Block Diagram Figure 2 1 Block Diagram 8 Gb SAS Gb SAS gt E Base IF 1000Base BX CPU 0 Fabric IF 5x 1000Base BX 8 B1 RS232 Debug IF 2 a Clocking Update channel a USB k 4 p 3 Gb SAS i 3 Gb SAS Le i Base IF Lae Fabric IF 1000Base BX ps 8 CPU 0 2 5232 Debug IF 3 519 engine COM1 RS232 LPC FWH amp MISC gt E 2 8 N 4 52 8 Base IF 1000Base BX Ej E Fabric IF 1000B
146. fic only offset 0 1 are used offset 0 event trigger Presence detected always present and do not generate event offset 1 event trigger Power supply Failure detected fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition Fuse presence and fault detection RTN Return on supply B Sensor type 08h Power Supply Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger Presence detected always present and do not generate event offset 1 event trigger Power supply Failure detected fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition Fuse presence and fault detection RTN Return on supply B Sensor type 08h Power Supply Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger Presence detected always present and do not generate event offset 1 event trigger Power supply Failure detected fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition FRU 0 Power consumption in watts FRU 0 also includes FRU2 3 4 Sensor type OBh Other Unit Based Sensor Watt Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 180 Watts TBC Upper Critical event 200 Watts TBC Hysteresis 20 Watts FRU 1 AMC B2 Power consumption in watts Sensor type OBh Other Uni
147. g the system s cooling efficiency Moreover airflow blockers offer an equivalent impedance to forced air to a typical board which balances airflow across the chassis 7 1 4 System Airflow The airflow impedance pressure curve gives information for the thermal operational range of the system carrying the AT8030 Once the volumetric airflow capability of your chassis is known the pressure curve can help determine the ambient room temperature setpoint that should be used for optimal operation If you are using various models of ATCA blades in the same chassis it is possible to find the best thermal fit Having the volumetric airflow value for each chassis slot it is then possible to decide the layout using the pressure curves Airflow CFM Pressure drop Airflow CFM Pressure Drop inch of water inch of water 18 9 1 2 4 0 0433 0 1316 0 0505 0 1501 20 26 0 0799 Table 7 2 Pressure curve T5006 with Filler 27 28 r 29 30 r 31 32 33 35 36 r 37 38 r 39 j 40 152 AT8030 User s Guide Thermal Considerations 0 2500 0 2000 0 1500 0 1000 Pressure inch 2 0 0500 0 0000 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Airflow CFM Figure 7 1 Pressure curve T5006 with AMC Filler 153 AT8030 User s Guide A Memory 1 0 Maps A 1 Memory Mapping FFFFFh System BIOS E0000h 1MB to to
148. ged ethaddr afterwards Contains hardware identification information such as type string and or serial number This variable serial cannot be changed This variable gives the amount of RAM memory which is not used by u boot This is necessary because the linux kernel has to be started with reduced memory to leave some memory for DMA If the bootloader would use the full memory the ramdisk would be located at an address that linux could not access later stdin This and and the following 2 variables are set to serial automatically by the bootloader bootcount This variable holds the number of CPU resets without power loss This variable controls the amount of the POST SDRAM testing 0 No SDRAM testing is performed upon power up 1 Data and address bus testing is performed upon power up In addition a memory read write test is performed for 64 kB blocks at each 1MB boundary fast testing 2 Data and address bus testing is performed upon power up In addition a complete memory read write test is performed for the total amount of RAM complete testing memtest Inthe case this variable has been set independent of its value a Power On Self Test testing several onboard devices is performed upon reset SDRAM POST is not affected by this variable Important environment variables G 4 Setting the bootstopkey The default setting for the bootstopkey is stop To change the bootstopkey the command
149. gned to standard port numbers OEM links that require physical interconnects on the carrier RS232 and SOC have been assigned port numbers in the extended option region C 5 AT8030 User s Guide C8 1 1 Pin Pin EN TE B Pin ali Pin Signal B129 TxD15 RxD4 B87 TxD8 B130 TxD15 RxD4 B88 TxD8 B131 GND B132 RxD15 TxD4 RxD8 B133 RxD15 TxD4 RxD8 B134 B135 TxD16 B50 RxD5 TxD9 B136 TxD16 B51 RxD5 TxD9 B137 GND B138 RxD16 B53 TxD5 RxD9 B139 RxD16 B54 TxD5 7 RxD9 B140 GND B141 TxD17 IPMB L SCL B99 TxD10 B142 TxD17 B100 TxD10 B143 B101 B144 RxD17 B59 RxD6 B102 RxD10 B145 RxD17 B18 12V B60 RxD6 B103 RxD10 B146 GND B19 GND B61 GND B104 GND B147 TxD18 B20 RxD1 B62 TxD6 B105 TxD11 B148 TxD18 B21 RxD1 B63 TxD6 B106 TxD11 B149 GND B22 GND B64 GND B107 GND B150 RxD18 B23 TxD1 B65 RxD7 B108 RxD11 B151 RxD18 TxD1 RxD7 B109 RxD11 B152 B110 B153 TxD19 B68 TxD7 B111 TxD12 B154 TxD19 B69 TxD7 B112 TxD12 B155 GND B70 GND B113 GND B156 RxD19 B71 IPMB_SDA B114 RxD12 B157 RxD19 B72 12V B115 RxD12 B158 GND B73 GND B116 GND B159 TxD20 B117 TxD13 B160 TxD20 B118 TxD13 B161 B119 B162 RxD20 B120 RxD13 B163 RxD20 B121 RxD13 B164 B122 GND B165 TCLK B123 TxD14 B166 TMS B124 TxD14 B167 TRST C 6 AT8030 User s Guide Pin Signal Pin Signal Pin Signal Pin Signal B40 GND B82 GND B125 GND B168 TDO B TDI B41 ENABLE 83 PSOR GND B126 RxD14
150. h 46h 47h 48h 49h oj O amp 0 0 Yes Set User Payload Access 24 6 IPMI 2 0 Get User Payload Access 24 7 IPMI 2 0 A App 4Ch 0 0 Yes pp 4Dh 0 0 Yes 92 AT8030 User s Guide Hardware Management Get Channel Payload Support Get Channel Payload Version Get Channel OEM Payload Info Master Write Read Get Channel Cipher Suites Suspend Resume Payload Encryption Set Channel Security Keys Get System Interface Capabilities IPMISpec section 24 8 IPMI 2 0 App 24 9 IPMI 2 0 App 24 10 IPMI 2 0 App 18 10 22 15 IPMI2 0 App 24 3 IPMI2 0 App 22 25 IPMI2 0 App 22 9 IPMI2 0 App NetFn CMD App 52h Carrier IPMC Kontron support on IPMI BMC req req MMC 4Eh 0 0 Yes 4Fh Yes 50h 0 0 No M 0 M Yes 0 0 54h Yes 55h Yes 56h 57h Table 4 50 Chassis Device Supported Commands for MMC built in IPMISpec section NetFn Carrier IPMC Kontron support on CMD IPMI BMC req req MMC 0 Chassis Device Commands Get Chassis Capabilities Get Chassis Status Chassis Control Chassis Reset Chassis Identify Set Chassis Capabilities Get System Restart Cause Get System Restart Cause Get System Restart Cause Get POH Counter 22 1 Chassis 22 2 Chassis 22 3 Chassis 22 4 Chassis 22 5 Chassis 22 6 Chassis 22 9 Chassis 22 10 Chassis 22 11 Chassis 22 12 Chassis 0 00h M Yes 0
151. harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more ofthe following measures Reorientor relocate the receiving antenna Increase the separation between the equipment and receiver Connectthe equipment into an outlet on a circuit different from that to which the receiver is connected Consultthe dealer or an experience radio TV technician for help WARNING This is Class product If not installed in a properly shielded enclosure and used in A accordance with this User s Guide this product may cause radio interference in which case users may need to take additional measures at their own expense Safety Certification All Kontron equipment meets or exceeds safety requirements based on the IEC EN UL CSA 60950 1 family of standards entitled Safety of information technology equipment All components are chosen to reduce fire hazards and provide insulation and protection where necessary Testing and reports when required are performed under the international IECEE CB Scheme Please consult the Kontron Safety Conformity Policy Guide for more information For Canada and USA input voltage must not exceed 60Vdc for safety compliance CE Certification The product s described in this user s guide complies with all applicable European Union CE directives if it has a CE marking For compu
152. he Application as such the Clock Control flag is setto Activated by the Application for these resources and this means that the Application that needs these clocks shall issue a SetClockState enable command to the Carrier IPMC as well as to mating resources This is the clock ekeying information as it appears in the FRU multirecord area For more details about these records and the AMC O clock ekeying mechanism refer to AMC 0 R2 0 section 3 9 1 It should be noted that for the AMC 1R1 0 FCLKA usage is not yet fully defined by subsidiary specification and is subject to change The current implementation on this unit is base on the information provided by AMC OR2 0 The Carrier Clock Point to Point connectivity record describes as its name implies the point to point clock links available between different resources Table 4 44 Carrier Clock Point to Point Connectivity Record Type 2C Carrier Clock Point To Point Connectivity Record Header 2C Carrier Clock Point To Point Connectivity Record Record Format Version 00h Type 2C Carrier Clock Point To Point Connectivity Record Data Clock Point To Point Resource Descriptor Count m 0x02 Clock Point To Point Resource Descriptor Clock Resource Id 0x00 7 6 00b On Carrier device 5 4 Oh reserved 3 0 On Carrier Device 0 PCIe clock generator Clock Point to Point Connection Count 0x01 Point to Point Clock Connection descriptor 81 AT8030 User s Guide
153. hershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 75 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 100 C After Thermal Analysis Hysteresis 2 deg C All value can be adjusted after thermal analysis BX Temp DIMMO Memory Second DIMM Temperature only available on CPUO Sensor Type O1h temperature Event Reading type code O1h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for B2 Temp DIMM1 threshold base event Engine Upper Non Critical event 75 C After Thermal Analysis Upper Critical event 85 C After Thermal Analysis Upper Non Recoverable 100 C After Thermal Analysis Hysteresis 2 deg C value can be adjusted after thermal analysis 102 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name B2 Temp FrontEth FRU2 CPUO Engine Only B2 Temp LSI SAS FRU2 CPUO Engine Only BX Vcc VIT DDR BX VCORE BX Vcc 1 5V SUS BX CPU VCCA BX CPU Reset Description Sensor Type Event trigger Front Panel Ethernet Temperature Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 95 After Thermal Analysis Upper Critical event 105 C After Thermal Analysis Upper Non Recoverable 115 C
154. his product conforms to the following specifications e PICMG3 0R2 0 001 8 002 Advanced TCA core specification e PICMG3 1R1 0 Ethernet Fiber Channel over Advanced TCA 0 R2 0 Advanced mezzaninne card base specification 1 R1 0 Advance mezzaninne card PCI Express e AMC 2 R1 0 Advance mezzaninne card Ethernet AMC 3 R1 0 Advance mezzaninne cardStorage ACPIrev 2 0 1 8 Hot Plug Capability The AT8030 supports Full Hot Plug capability as per PICMG3 0R2 0 1 amp 002 It be removed from or installed in the system while it is on without powering down the system Please refer to the PICMG3 0R2 0 specification for additional details The AT8030 supports PCI Express Hotplug on AMC B1 The IPMC uses the standard PCI Express Hotplug Controller on the CPUO Engine allowing hot insertion and removal of an AMC 1 module 8 AT8030 User s Guide Product Description 1 9 Interfacing with the Environment 1 9 1 RTM rear transition module The RTM8030 is a single slot 6HP AdvancedTCA Rear Transition Module This module provides additional connectivity for AT8030 CPU front blade 1 9 1 1 Standard Compliance e PICMG3 0 R2 0 1 8 ECNOO2 Advanced Telecommunication Computing Architecture SAS1R10 Serial Attached SCSI 1 1 Revision 10 SAS 1 1 SFF 8470 T10 Technical Committee and SCSI Trade Association 1 9 1 2 SAS Feature One 3Gbit s SAS port availabl
155. ia Independent Interface Standard interface used to connect a Gigabit Ethernet MAC block to a PHY ShMC Shelf Management Controller SIMD Single Instruction Multiple Data SIMM Single In line Memory Module SIRO Serial Interrupt ReQuest Single Level Cell SGMII 29 1 9 AT8030 User s Guide Acronyms Descriptions Self Monitoring Analysis and Reporting Technology or S M A R T A monitoring system for computer hard disks to detect and report on various indicators of reliability in the hope of anticipating failures Symmetric MultiProcessing SMP systems allow any processor to work on any task no matter where the data for that task are located in memory with proper operating system support SMP systems can easily move tasks between processors to balance the workload efficiently SNMP Simple Network Management Protocol SNTP Simple Network Time Protocol SO CDIMM Small Outline Clocked 72 bit Dual In line Memory Module SO DIMM Small Outline Dual In line Memory Module 50 Serial Over LAN SONET Synchronous Optical NETworking L SPD Serial Presence Detect A standardized way to automatically access information about a computer memory module P SPI Serial Peripheral Interface SpeedStep Same as EIST Enhanced Intel SpeedStep Technology SRAM Static Random Access Memory SSE2 Streaming SIMD Extension 2 SIMD is Single Instruction Multiple Data SSE3 Streaming SIMD Extension 3 SIMD is Single Instruction Multipl
156. ic offset 00h VccGood 12V 018 VccGood 5V 02h VccGood 3 3V 03h VccGood 2 5V 04h VccGood 1 8V 05h VccGood 1 5V 06h VccGood 1 2V 07h VccGood Core 08h VccGood 5V 09h VccGood 1 1V 10h VccGood 1 05V 11h VccGood 1 25V 77h 08h OEM Kontron Standard IPMI ATCA Power Good Power Supply 36 AT8030 User s Guide Hardware Management Table 4 2 Kontron OEM FRU Info Agent Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset Transition to degraded Event Data 2 is used a bit flag error Bit 7 unspecifiedError Bit 6 notPresentError Bit 5 multirecHeaderError Bit 4 multirecDataError Bit 3 timeout error Bit 2 ipmcError Bit 1 fruDataError Bit 0 commonHeaderError Event Data 3 is used a bit flag error Bit 7 reserved Bit 6 reserved Bit 5 SetPortState Not Supported Bit 4 SetPortState Error Bit 3 reserved Bit 2 reserved Bit 1 reserved C5h Standard IPMI OEM Kontron Discrete FRU Info Agent Install Error Event Data 2 is used a bit flag error Bit 7 unspecifiedError Bit 6 notPresentError Bit 5 multirecHeaderError Bit 4 multirecDataError Bit 3 timeout error Bit 2 ipmcError Bit 1 fruDataError Bit 0 commonHeaderError Event Data 3 is used a bit flag error Bit 7 SetClockState Not Supported Bit 6 SetClockState Error Bit 5 SetPortState Not Supported Bit 4 SetPortState Error Bit 3 Clock Internal Mismatch Bit 2 Clock Match Error Not a single clock matches Bit
157. ical event 12 60v 5 Lower Critical event 11 40v 5 Hysteresis 0 180v 1 5 Voltage on 1 2v suspend management board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 1 26v 10 Lower Critical event 1 14v 10 Hysteresis 0 018v 1 5 Voltage on 3 3v suspend management board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 3 47v 5 Lower Critical event 3 13v 5 Hysteresis 0 050v 1 5 Voltage on 5v suspend management board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 5 25v 5 Lower Critical event 4 75v 5 Hysteresis 0 075v 1 5 59 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Vcc 12 SUS Vcc 2 5 REF Vcc 12V AMC Vcc 12V RTM TelcoClock Alarm Telecom Sync PQ3 Boot Error Description Sensor Type Event Trigger Voltage on 12v suspend management board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following th
158. ice each time you boot during POST by selecting your boot device in the Boot device lt F11 gt or F3 from a Console Redirection terminal 143 AT8030 User s Guide Software Setup 5 3 Console Redirection VT100 Mode The VT100 operating mode allows remote setup of the board This configuration requires a remote terminal that must be connected to the board through a serial communication link 5 3 1 Requirements The terminal should emulate a VT100 or an ANSI terminal Terminal emulation programs such as Telix HyperTherminal Windows minicom Linux ProcommO Windows can also be used 5 3 2 ANSI and VT100 Keystroke Mapping Table 5 3 ANSI and VT100 Keystroke Mapping 5 3 3 VTI UTF8 Keystroke Mapping The following escape sequences are defined in the Conventions for Keys Notin VT100 Terminal Definition and ASCII Character Set section of Standardizing Out of Band Management Console Output and Terminal Emulation VT UTF8 and VT100 available for download at microsoft com Table 5 4 VT UTF8 Keystroke Mapping F1 Key lt ESC gt 1 F2 Key lt ESC gt 2 F3 Key lt ESC gt 3 144 AT8030 User s Guide Software Setup Control Modifier lt ESC gt C These escape sequences are supported by VT UTF8 compliant terminal connections such as Windows Server 2003 Emergency Management Services EMS AMIBIOSS Serial Redirection supports these key sequences under two configurations Terminal Type setup quest
159. in valid operating range but are getting close to the edge unit still operating within vendor specified tolerances 150 AT8030 User s Guide Thermal Considerations non recoverable PICMG 3 0 critical telco critical Unit no longer operating within vendor specified tolerances Most ATCA chassis react to temperature events in the following manner when a minor threshold is reached the shelf manager will incrementally increase airflow fan speed to bring the temperature below the crossed threshold When a major threshold is reached the shelf manager will increase the fans to maximum speed When a critical threshold is reached the shelf manager will shutdown the blade to prevent damage The shelf alarm panel when available can inform the operator with LEDs when an alarm minor major critical is raised Refer to your chassis documentation to adapt and optimize your temperature monitoring application to chassis capabilities See also System Airflow section for more information Below is the list of temperature sensors with their respective thresholds Sensor ID Lower Thresholds Upper Thresholds Minor Major Critical Minor Major Critical Temp Switch BC 0 10 C 90 C 100 C 115 C Temp Dual Phy Co 5 C 10 C 80 C 90 C 105 C Temp SOC DIMM 58C 09 10 C 75 C 85 C 100 C Temp Air Inlet 5 C 0 C 10 C 65 C 75 C 90 C Temp PQ3 GOC 0 C 10 C 75 C 85 C 100 C Temp Dual Phy Se 5 C 0 C 10 C 80 C 90 C 105 C Temp
160. ines 0 1 amp 2 memory list and lt lt 26 3 3 2 PowerQuicc III memory list and 5 27 3 3 3 Installing Memory iere ERE Hee nde SEN EIE ERE 28 3 4 Onboard Interconnectivity 29 3 4 1 Onboard Connectors and lt 29 3 4 2 Board and Carrier Point to Point Interconnect Overview 29 3 5 Board Hot Swap and Installation 31 3 5 1 Installing the Cardin the 515 31 3 5 2 Removing the Board Re DER Rd UNES 31 3 5 3 JInstal ngan AMG pee a ese ree es 32 3 5 4 Removing AMC oc le RR LL UU RR cade S E E RR 32 3 5 5 Installing the RIMB030 RR EK Mae RR Repo 32 3 5 6 Removing the RIM8O03 0 osas cre wate alg mare REIS wierd 32 Hardware Management NIST 34 4 4 Hardware Management 34 4 2 Hardware Management Architecture on Front Blade 34 4 3 Hardware Management 35 4 3 1 specific features 00
161. ion as the intended boot device AT8030 User s Guide Software Setup 5 1 6 8 All Other Disk Drives sub menu Feature Description Help text Specifies the boot priority ofthe available devices Specifies the boot priority of any other Select the boot device 1st Drive Varies available devices other than Hard Disk with UpArrow or Removable CD DVD USB disk or Network DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Specifies the boot priority of any other Select the boot device Nth Drive available devices other than Hard Disk with UpArrow or Removable CD DVD USB disk or Network DownArrow key Press Enter to set the selection as the intended boot device 5 1 7 System Management Menu Feature Option Description Help text Remote Access N A Configuration Selects sub menu N A IPMI over LAN and Serial Over LAN Watchdog Timers N A Selects sub menu N A System Information N A Selects sub menu N A Set LAN Configuration N A Selects sub menu 134 AT8030 User s Guide Software Setup 5 1 7 1 Remote Access Configuration sub menu Feature Description Help text Configures serial port for console redirection Serial Port Number Also used for Headless operation mode through ACPI Displays the hardware address of the COM 1 port Displays the hardware address of the COM 2 porti e RTM serial port
162. ion as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device AT8030 User s Guide Software Setup 5 1 6 6 1st Drive Nth Drive 5 1 6 7 1st Drive Nth Drive USB Disk Drives sub menu Description Specifies the boot priority ofthe available USB Varies d Disk devices Specifies the boot priority ofthe available USB Disk devices Network Disk Drives sub menu Option Description Specifies the boot priority of the available Varies Network Disk devices Specifies the boot priority of the available Network Disk devices Varies 133 Help text Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority ofthe available devices Select the boot device with UpArrow or DownArrow key Press Enter to set the select
163. ion is set to VT UTF8 Terminal Type setup question is set to VT100 or ANSI and VTUTF8 Combo Key Support setup question is set to Enabled 5 4 Installing Drivers WindRiver PNE Linux 1 5 BSP and RedHat Enterprise Linux 5 include all required drivers to fully support all on board sevices 145 AT8030 User s Guide Chapter 6 Unit Computer Management 6 1 Ethernet Switch 147 6 2 Unit Computer Diagh stics cos csee eene aeo redde 147 146 AT8030 User s Guide Unit Computer Management 6 Unit Computer Management 6 1 Ethernet Switch Management The BCM56502 Ethernet Switch is managed by the Unit Computer The basic management interfaces are SNMP and a command line interface CLI The CLI is accessible by the Unit Computer s serial or Ethernet interface The Unit Computer can not be operated with an arbitrary operating system but executes a custom 05 and switch specific application software Before loading the OS and application software the bootloader code universal bootloader u boot initializes the main components of the board like CPU SDRAM serial lines etc for operation After this kernel and application are started from flash The bootloader may also be used for adjusting some basic settings like the parameters of the serial interface Bootloader commands are listed in appendix Bootloader All three Unit Computer SW components bootloader 05
164. ional Electrotechnical Commission TICH Integrated 1 0 Controller Hub Sub part of the MICH chipset i I I I I IEEE Institute of Electrical and Electronics Engineers IERR Internal ERRor A signal from the Intel Architecture processors indicating an internal error condition INT INTerrupt IMCH Integrated Memory Controller Hub Sub part of the MICH chipset Xilinx iMPACT a tool featuring batch and GUI operations allows you to perform two basic functions Device Configuration and File Generation Intel Mobile Voltage Positioning The Intel Mobile Voltage Positioning specification for the Intel amp Core Duo Processor It is a DC DC converter module that supplies the required voltage and current to a single processor IPMI Intelligent Platform Management Interface IPMIFWU Intelligent Platform Management Interface FirmWare Update U IT International Telecommunication Union I 5 AT8030 User s Guide Acronyms Descriptions ITU T ITU Telecommunication standardization sector ITU is International Telecommunication Union JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group KiloByte Keyboard Controller Style An IPMI system interface KCS SMM Keyboard Controller Style BIOS private IPMI system interface KCS SMS Keyboard Controller Style Application IPMI system interface KiloHertz Local Area Network Logical Block Addressing Local Bus Controller 0n PowerQuicc III C
165. irtual platforms improving manageability limiting downtime and maintaining worker productivity by isolating computing activities into separate partitions It also provides greater isolation and security between different applications and operating systems for added protection against corruption Intel 64 Architecture Supports 64 bit instructions providing flexibility for 64 bit and 32 bit applications and operating systems Access to larger physical memory space reduces load on the system and allows faster access to data from RAM instead of drive Digital Thermal Sensor DTS Measures maximum temperature the die at any given time 15 AT8030 User s Guide Board Features 2 3 2 2 Intel 3100 Chipset The Intel 3100 chipset combines server class memory and 1 0 controller functions into a single component creating the first integrated Intel chipset specifically optimized for embedded communications and storage applications This single chip system controller replaces a separate memory controller hub and 1 0 controller hub significantly conserving board real estate and power consumption 2 3 2 2 1 Product Highlights 2 3 2 2 1 1Memory Intel 3100 chipset based platforms are ECC enabled and support single channel DDR2 400 memory up to 8 4 GB which is ideal for storage and memory intensive applications The memory subsystem interface supports up to four ranks for a total system bandwidth of 3 2 GB s 2 3 2 2 1 2PC
166. ity Record Data OEh Calculated Point to Point AMC Resource Descriptor Resource ID 85h gt AMC Bay AMC 1 Point to Point Count Point to Point Resource Descriptor 001000h Reserved Bits 23 18 0 68 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record 69 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record 70 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record 71 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record 72 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record 73 AT8030 User s Guide Hardware Management Type 18 Carrier Point To Point Connectivity Record Reserved Bits 23 18 0 Local Port Bits 13 17 15 it 12 30 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 00 gt Carrier Device 0 Serial Port 4 4 3 4 IPMC FRU 0 AMC Point To Point Connectity Information Each AMC point to point connectivity record contains AMC Link Descriptors each of which identifies a Link and an associated protocol Multiple AMC Link Descriptors can exist for a given point to point AMC Channel This is used when a Channel can support multiple protocols such as SAS and SATA For more details about this record refer to 0 R2 0 Section 3 9 2 Ta
167. ive component first place itin an antistatic container or packaging Handle all sensitive components at an ESD workstation If possible use antistatic floor pads and workbench pads Handle components and boards with care Don t touch the components or contacts on a board Hold a board by its edges or by its metal mounting bracket Do not handle or store system boards near strong electrostatic electromagnetic magnetic or radioactive fields When you wantto remove the protective foil if present make sure you are properly grounded and that you touch a metalic part of the board CAUTION N Removing the protective foil from the top and bottom cover might create static N When you remove those protections make sure you follow the proper ESD procedure xii AT8030 User s Guide Preface Preface How to Use This Guide This user s guide is designed to be used as step by step instructions for installation and as a reference for operation troubleshooting and upgrades For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned The following is a summary of chapter contents Chapter 1 Product Description Chapter 2 Board Features Chapter 3 Installing the board Chapter 4 Hardware Management Chapter 5 Software Setup Appendix A Memory amp 1 0 Maps Appendix B Extension Registers Appendix C Connector Pinout
168. l Monitor 1 Thermal Monitor 2 Digital Thermal Sensor SpeedStep Configuration sub menu Maximum Speed Minimum Speed Variable Speed Fixed Speed Disabled 1000 MHz here all supported speeds between LFM and HFM as supported by Intel 1500 MHz Enabled cannot be disabled Enabled Disabled Description Maximum CPU speed is set to maximum Minimum CPU speed is setto minimum Variable CPU speed is controlled by operating system Fixed CPU speed is set to fixed value Disabled Default CPU speed is used All processor speed values are supported from LFM to HFM and in between as defined by Intel Note Help field will be shown only if option Mode is set to Fixed Speed All other modes make this option display only Core 0 is the bootstrap core and it can t be disabled can be disabled with this option i e only one execution core would be used Thermal Management sub menu Option Enabled Disabled Enabled Disabled Enabled Description CPU thermal monitor mechanism CPU thermal monitor mechanism Each execution core has a unique on die digital sensor called Digital Thermal Sensor DTS whose temperature is accessible by BIOS via MSR model specific register 122 Help text Maximum CPU speed is set to maximum Minimum CPU speed is set to minimum Variable CPU speed is controlled by operating system Fixed CPU speed is set to fixed value Disable
169. lade serial number N A display only Board Part Number Varies Displays the CPU blade part number N A display only Displays the current chassis slot number for Chassis Slot 1 16 the CPU blade N A display only The current Firmware device in use primary or secondary IPMI Device and FW Info N A Selects sub menu N A display only FWH In Use Primary Displays the current Firmware device in use Secondary primary or secondary 140 AT8030 User s Guide Software Setup 5 1 7 11 Feature IPMI Version IPMI Device ID IPMI Device Revision IPMI Firmware Version SDR Revision Aux Revision Info byte 1 Aux Revision Info byte 2 Aux Revision Info byte 3 IPMI Device and FW Info sub menu Description Varies Varies Varies Varies Varies Varies Displays IPMI Specification version Displays IPMI device ID OEM defined IPMI Device ID has been assigned like this Renesas 852148 1 Kontron PMM 2 Renesas 852145 3 Renesas 852166 4 Renesas 852138 5 Renesas 852168 6 Displays IPMI device revision OEM defined specify the version of the IPMI Device controller Displays IPMI firmware version Displays SDR Sensor Data Record revision This field correpond to the implementation specific auxiliary information from IPMI Get Device ID Command byte 13 The SDR revision is displayed in decimal notation Displays implementation specific auxiliary info
170. lay only Enter Channel Number for SET LAN Config Command Proper value below 16 Channel Status Valid or Invalid Display Valid if IPMC support LAN Channel This allows setting an Gateway IP Address for Gateway Address XXX XXX XXX XXX LAN configuration Display the current Gateway configuration Current Gateway Address stored in IPMI NVRAM for IPMI LAN 5 1 7 7 VLAN ID Configuration Feature Option Description The parameter selector assignments are described in IPMI Specification 2 0 table 23 4 Selector 20 802 1q VLAN ID 12 bit Each interface has a channel number that is used when configuring the channel and for routing messages between channels Channel Number Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Channel Status Valid or Invalid Display Valid if IPMC support LAN Channel LAN Parameter Selector 20 This allows setting an 802 1q VLAN ID for LAN 802 1q VLAN ID Value configuration Display the current 801 1q VLAN ID configuration stored in IPMI NVRAM for IPMI LAN Current 802 1q VLAN ID Value Support VLAN Tagged Enabled Select if 802 1q VLAN tagged packets are Packets Disabled added Display the current status of the 801 1q VLAN E or tagged packets configuration stored in IPMI NVRAM for IPMI LAN VLAN Tagged Packets Status Disabled 138 N A displ
171. log events Enabled Event Log is used Disabled Event Log is not used Ifthis option is disabled no SEL events are available from this blade View all unread events in the Event Log Mark all unread events as read in the Event Log Discard all events in the Event Log Enabled ECC event logging enabled Disabled ECC event logging disabled Correctable ECC for testing purposes Uncorrectable ECC errors reported Both ECC errors for testing purposes Disabled ECC errors not reported Enabled NSI event logging enabled Disabled NSI event logging disabled Enabled FSB event logging enabled Disabled FSB event logging disabled Enabled Memory buffer event logging enabled Disabled Memory buffer event logging disabled Enabled PCI E error event logging enabled Disabled PCI E error event logging disabled AT8030 User s Guide Software Setup 5 1 4 6 Mask duplicate Errors Mask Unsupported Requests PCI Express Error Masking sub menu Description Duplicate errors can be masked if they are found in successive SMI interrupts when set to Yes Note Duplicate errors detected within a single SMI interrupt are always masked Unsupported request errors can be masked when set to Yes If set to No the default Mask is used based on Chipset recommendations 125 Help text Yes Mask duplicate errors found in successive SMI interrupts No Duplicat
172. ments are described in IPMI Specification 1 5 table 6 1 Display Valid if IPMC support LAN Channel Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Selects sub menu Each interface has a channel number that is used when configuring the channel and for routing messages between channels The channel number assignments are described in IPMI Specification 1 5 table 6 1 IP Configuration sub menu Option 03 Valid or Invalid XXX XXX XXX XXX XXX XXX XXX XXX Description The parameter selector assignments are described in IPMI Specification 1 5 table 19 4 Selector 03 IP Address Each interface has a channel number that is used when configuring the channel and for routing messages between channels Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Display Valid if IPMC support LAN Channel This allows setting an IP Address for LAN configuration Display the current LAN configuration stored in IPMI NVRAM for IPMI LAN 136 Help text Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only Enter for IP Address Configuration Enter for MAC Address Configuration Enter for Subnet Mask Configuration Enter for Gateway IP Address Configuration Enter for VLAN ID Configuration Enter for VLAN Priority Configuratio
173. menu Option Description Physical Processors 1 Displays the number of physical processors Logical Processors 10r2 Displays the number of logical processors Processor Type Merom Displays the type of the processor Processor 0 Speed Varies Displays the core speed of processor 0 Displays the Front Side Bus speed of processors processor system bus speed FSB Speed CPUID XXX Update Revision XXX Processor 0 Microcode Displays the microcode version Help text N A display only N A display only N A display only N A display only N A display only N A display only Processor 0 12 Cache Size 2 Displays processor 0 L2 Cache Size N A display only Allows a platform to run multiple operating systems and applications in independent partitions With virtualization one computer system can function as multiple virtual systems BIOS locks this setting atthe end of POST Once locked only a power cycle can unlock it for change Enabled Vi rocessor Virtualization Disabled SpeedStep N A Selects sub menu Thermal Management N A Selects sub menu 121 Enabled Processor virtualization in use Disabled Processor virtualization not in use Configures SpeedStep technology Configures thermal monitors AT8030 User s Guide Software Setup 5 1 4 2 Feature Processor 0 Speed Processor 0 Core 0 Processor 0 Core 1 5 1 4 3 Feature Therma
174. n Enter Active LAN Channel Number for Set LAN Configuration Command Help text N A display only Enter Channel Number for SET LAN Config Command Proper value below 16 N A display only Enter IP Address in decimal in the form of XXX less than 256 and in decimal only N A display only AT8030 User s Guide Software Setup 5 1 7 4 Feature LAN Parameter Selector Channel Number Channel Status Current MAC Address 5 1 7 5 LAN Parameter Selector Channel Number Channel Status Subnet Mask Current Subnet Mask MAC Address Configuration sub menu 05 Valid or Invalid XX XX XX XX XX XX Description The parameter selector assignments are described in IPMI Specification 1 5 table 19 4 Selector 05 MAC Address Each interface has a channel number that is used when configuring the channel and for routing messages between channels Only one channel on Base interface is available The channel number assignments are described in IPMI Specification 1 5 table 6 1 Display Valid if IPMC support LAN Channel Display the current MAC Address stored in IPMI NVRAM for IPMI LAN Subnet Mask Configuration sub menu 06 Valid or Invalid XXX XXX XXX XXX XXX XXX XXX XXX Description The parameter selector assignments are described in IPMI Specification 1 5 table 19 4 Selector 06 Subnet Mask
175. n ROW A ROW ROW ROW D ROW E ROW Tx4 UP Tx4 UP Rx4 UP Rx4 UP CLK3A CLK3A 5 Tx2 15 N C Tx2 15 N C Rx2 15 N C Rx2 15 N C Tx3 15 N C Tx3 15 N C 6 Tx0 15 Tx0 15 Rx0 15 Rx0 15 Tx1 15 N C Tx1 15 N C 7 Tx2 14 N C Tx2 14 N C Rx2 14 N C Rx2 14 N C Tx3 14 N C Tx3 14 N C 9 Tx2 13 N C Tx2 13 N C Rx2 13 N C Rx2 13 N C Tx3 13 N C Tx3 13 N C Tx0 13 Tx0 13 Rx0 13 Rx0 13 Tx1 13 N C Tx1 13 N C Pin ROW G ROW ROW AB ROW CD ROW EF ROW GH 1 CLK2B CLK2B GND GND GND GND GND GND GND 9 Rx3 13 N C 3 13 GND 10 Rx1 13 N C 1 13 GND GND GND C 2 AT8030 User s Guide C 6 AdvancedTCA 1 0 AdvancedTCA 3 1 J23 Pin ROW A ROW ROW C ROW E ROW F 5 BI_DA1 BI_DA1 BI_DB1 BI_DB1 BI_DC1 BI DC1 6 BI 2 DI DA2 BI_DB2 BI_DB2 DI_DC2 BI DC2 Pin ROW G ROW ROW AB fhe ROW CD ROW EF ROW GH 5 C 3 AT8030 User s Guide C 7 AdvancedTCA 1 0 RTM Connector J30 Pin ROWA ROW ROW C ROW D ROW E ROWF SP1 RX SP2 TX SP2 RX SP3 TX SP3 RX SP5 RX SP6 TX SP6 RX SP7 TX SP7 RX Reserved Reserved Reserved N C RESET CPUO RESET CPU14 PQ3 FE TX PQ3 FE RX PQ3 FE RX PQ3 FE CTR N C 9 5450 5450 TX 5450 RX SASO SAS1 TX SAS TX 10 GE18_TXC GE18_TXC GE18_RXC GE18_RXC GE15_TXC GE1
176. n Table also includes a byte that contains the AMC O specification revision supported by the Carrier IPMC Only the real physical site numbers are included as AMC B1 is the only physical site available to the operator 67 AT8030 User s Guide Hardware Management Table 4 39 Carrier Information Table Record Type 1Ah Carrier Information Table Record Carrier Site Number 01 Count Carrier Site Number 05h 4 4 3 3 IPMC FRU 0 Carrier Point To Point Connectivity Information The Carrier Point to Point Connectivity record is included in the Carrier FRU Information and describes the point to point connections implemented on the Carrier The carrier FRU Information may include several Carrier Point to Point Connectivity records if a single record is not sufficient for describing all point to point connections implemented on the Carrier The Carrier IPMC treats these multiple records as a single logical point to point AMC Bay Descriptors list For more details about this record refer to 0 R2 0 Section 3 9 1 Table 4 40 Carrier Point To Point Connectivity Record Type 18 Carrier Point To Point Connectivity Record Record Type ID Coh Record format 02h version Record Length Calculated Record Checksum Calculated Header Checksum Manufacturer ID 00315Ah PICMG Record ID PICMG Record ID 18h Carrier Point To Point Connectivity Record Record Format Version 00h Type 18 Carrier Point To Point Connectiv
177. ncept of integrity and confidentiality in RMCP IOL 1 5 RMCP supported algorithms are all the mandatory one Authentication RAKP none RAKP HMAC SHA1 Integrity None HMAC SHA1 96 Confidentiality None AES CBC 128 4 5 5 1 2 Users USER 1 The IPMI specification 2 0 Markup 2 May 2005 mention that a NULL user must be present This is in fact when no user or NULL is provided The specification provide a way to access the User 1 but don t define is initial privileges The selected privileges are the USER one forbidding to upgrade the IPMC For example in order to upgrade the IPMC over LAN an external user needs to Connectto the IPMC using the IPMB interface or the System Interface Creates an account and gives the Administrator privileges Then using the LAN it is possible to upgrade the IPMC IPMI specification 2 0 Markup 2 May 2005 do not specify the number of users but writes the following section 6 9 110 AT8030 User s Guide Hardware Management e Allauthenticated channels are required to support at least one user User ID 1 Usernames may be fixed or configurable or a combination of both atthe choice of the implementation e Ifan implementation supports only one user with a fixed user name then the fixed user name must be null all zeros Support for configuring user passwords for all User IDs is required Support for setting per user privilege limits is optional If the Set User Access
178. needs to occur because the user has forced the update or the BIOS checksum is corrupt The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS Checkpoint Description Initialize the floppy controller in the super 1 0 if present Some interrupt vectors are initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled Set up floppy controller and data Attempt to read from media Enable ATAPI hardware Attempt to read from ARMD and ATAPI CDROM Disable ATAPI hardware Jump back to checkpoint E9 Read error occurred on media Jump back to checkpoint EB Search for pre defined recovery file name in root directory Recovery file not found Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file Start reading the recovery file cluster by cluster Check the validity of the recovery file configuration to the current configuration of the flash part Make flash write enabled through chipset and OEM specific method Detect proper flash part Verify that the found flash part size equals the recovery file size The recovery file size does not equal the found flash part size Erase the flash part Program the flash part The flash has been updated successfully Make flash write disabled Disable ATAPI hardware Restore CPUID value back into register Give control to F000 ROM at F000 FFFOh D 3 POS
179. nently after using the saveenv command To keep the integrity and availability of the bootloader s environment two mechanisms are used The set of environment variables in flash is protected by a CRC32 checksum This prevents the bootloader from reading a corrupted environment in case power failure occurs during the saveenv command A redundant environment sector is used When storing the environment using the saveenv command the environment is written into the redundant sector After this has been successfully completed the redundant environment becomes the active one and will be used upon next system reset In case of a power failure during the environment storage only the new environment would be corrupted It won t be set to be active and the old environment would be used Only the latest environment changes would be Lost Function baudrate Serial console baudrate bootdelay Delay before automatically booting the default image bootargs This can be used to pass arguments to the bootm command and thus to the kernel started This defines a command string that is automatically executed when the boot stop string is not entered on the console interface within the bootdelay time after reset bootcmd G 4 AT8030 User s Guide Variable Function i2cfast This configures the LINUX 12 driver for fast mode 400 kHz Ethernet MAC address This variable is set once during manufacturing and cannot be chan
180. nit Provide the serial number found on the back of the unit and explain the nature of your problem to a service technician The technician will instruct you on the return procedure if the problem cannot be solved over the telephone Make sure you receive an RMA from our Technical Support before returning any merchandise Make a copy of the request form on the following page Fill it out Fax it to us at North America 450 437 0304 EMEA 49 0 8341 803 339 Send us an e mail at RMA ca kontron com in North America and at orderprocessing kontron modular com in EMEA In the e mail you must include your name your company name your address your city your postal zip code your phone number and your e mail You must also include the serial number of the defective product and a description of the problem H 2 AT8030 User s Guide H 2 WhenReturning a Unit e Inthe box you must include the name and telephone number of a contact person in case further explanations are required Where applicable always include all duty papers and invoice s associated with the item s in question e Ensure that the unit 15 properly packed Pack it in a rigid cardboard box e Clearly write or mark the RMA number on the outside of the package you are returning Ship prepaid We take care of insuring incoming units North America EMEA Kontron Canada Inc Kontron Modular Computers GmbH 4555 Ambroise Lafortune Sudetenstrasse 7 Boisbriand
181. nnector The controller is connected to a x1 PCI Express port on the Intel 3100 IMCH Here s a list of the main features of the controller SAS and SSP Features Each PHY supports 3 0 Gbit s and 1 5 Gbit s SAS data transfers Support SSP to enable communication with other SAS device Support SMP to communicate topology management information Provide a serial point to point enterprise level storage interface Transfer data using SCSI information units SATA and STP features Supports SATA data transfers of 3 0 Gb s and 1 5 Gb s Support STP data transfers of 3 0Gb s and 1 5 Gb s Provide a serial point to point storage interface 14 AT8030 User s Guide Board Features 2 3 2 Features to CPU1 amp CPU2 Engines 2 3 2 1 Processors Intel Core 2 Duo 17400 processors are members of Intel s growing product line of multi core processors based on Intel Core microarchitecture delivering breakthrough energy efficient performance for embedded platforms This processor provides an excellent performance per watt choice It integrates two complete execution cores in one physical package providing advancements in simultaneous computing for multi threaded applications and multi tasking environments While incorporating advanced processor technology this processor remains softwarecompatible with previous IA 32 processors 2 3 2 1 1 Processors Highlights Intel amp Wide Dynamic Execution
182. not all the IOL Session Channel User commands are supported this IMPLEMENTATION IS NOT IOL 1 5 NOR 2 0 COMPLIANT but offer a nice path for other commands supported by the IPMC The features of IPMI over LAN offers by Open IPMIis provided as is Kontron doesn t support enhance or provide maintenance for any of the Open IPMI software module 90 AT8030 User s Guide Hardware Management 4 5 Built In MMCs 4 5 1 Supported Commands Thetable below lists the IPMI commands supported by the built in MMC FRU2 3 4 This table is identical as the one provided by 0 and PICMG 3 0 The last column states the Kontron support for the specific command Table 4 47 IPM Device Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC IPM Device Global Commands Get Device ID 17 1 Cold Reset 17 2 App Warm Reset 17 3 pp Get Self Test Results 17 4 pp Manufacturing Test On 17 5 Set ACPI Power State 17 6 Get ACPI Power State 17 7 Get Device GUID 17 8 Broadcast Get Device ID 1 o oj o z x gt w gt A lt gt o gt 79 e oj 17 9 Table 4 48 Watchdog Timer Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC BMC Watchdog Timer Commands Reset Watchdog Timer 21 5 App
183. nsor type 08h Power Supply Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger Presence detected always present and do not generate event offset 1 event trigger Power supply Failure detected fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition Fuse presence and fault detection 48 V on supply B Sensor type 08h Power Supply Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger Presence detected always present and do not generate event offset 1 event trigger Power supply Failure detected fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition Fuse presence and fault detection RTN Return on supply A Sensor type 08h Power Supply Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 Presence detected always present and do not generate event offset 1 Power supply Failure detected event trigger fuse blown see IPMI v1 5 table x xx Sensor type code 08h for sensor definition 54 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Fuse RTN B Feed Fuse Earl A Feed Fuse Earl B Feed FRU input Power FRU1 Power FRU5 Power Board Reset Description Sensor Type Event Trigger Fuse presence and fault detection RTN Return on supply B Sensor type 08h Power Supply Event Reading type code 6Fh Sensor speci
184. o Set Shelf Address Info FRU Control PICMG 3 0 Table 3 9 3 8 3 13 3 14 3 22 3 24 Get FRU LED Properties Get LED Color Capabilities Set FRU LED State 3 25 3 26 3 27 3 51 3 17 3 18 Get FRU LED State Set IPMB State Set FRU Activation Policy Get FRU Activation Policy NetFn CMD IPMI BMC req PICMG 00h PICMG 01 PICMG 02h PICMG 03h PICMG 04h PICMG 05h PICMG 06h PICMG 07h PICMG 08h PICMG 09h PICMG OAh PICMG OBh 49 Carrier IPMC req Kontron support on IPMC z Yes Yes N A N A Yes 5 Yes 5 Yes Yes Yes AT8030 User s Guide Hardware Management IPMISpec section NetFn CMD Carrier IPMC Kontron support on req IPMC Set FRU Activation 3 16 PICMG OCh M Yes Get Device Locator Record ID Set Port State 3 41 PICMG OEh Yes Get Port State PICMG OFh Yes 3 29 PICMG ODh M Yes Compute Power Properties PICMG 10h Yes Set Power Level PICMG 11h Get Power Level 3 61 PICMG 12h Renegotiate Power 3 66 PICMG 13h Yes Yes N A e M Get Fan Speed Properties 3 63 PICMG 14h if controls Shelf N A fans Set Fan Level 3 65 PICMG 15h 0 M N A Get Fan Level 3 64 PICMG 16h 0 M N A Bused Resource 3 44 PICMG 17h 0 M N A Get IPMB Link Info 3 49 PICMG 18h 0 M Yes FRU Control Capabilities 3 24 PICMG 1Eh M Yes Table 4 32 0 Car
185. one SO CDIMM 512MB DDR2 400 SDRAM All memory busses operate at 200 MHz clock speed with dual data rate This means that data is transferred at 400 MHz The content of the SDRAM is not affected by a warm reset Only use validated memory with this product Thermal issues or other problems may arise if you don t use recommended modules Atthe time of publication ofthis user guide the following memories were confirmed functional with the product As the memory market is volatile this list is subject to change please consult your local technical support for an up to date list 3 3 1 engines 0 1 amp 2 memory list and characteristics Table 3 2 CPU engines 0 1 amp 2 memory list and characteristics Manufacturer Part Number Description M393T2863AZA CE6 DIMM DDR2 533 1GB Samsung M393T5660AZA CE6 DIMM DDR2 533 2GB Samsung M393T5166AZA CE6 DIMM DDR2 533 4GB Samsung Memory should have the following characteristics e DDR2 400 1 8V only Single sided or double sided e 1 layer of BGA on PCB side 26 AT8030 User s Guide Installing the Board X4 or X8 configuration supported Serial Presence Detect SPD EEPROM 72 bit DIMMs only 1 2inch maximum height 3 3 2 PowerQuicc memory list and characteristics Table 3 3 PowerQuicc ITI memory list and characteristics Manufacturer Part Number Description Company VL491T6553T D5 DIMM DDR2 400 512MB ECC Virtium Technology Inc
186. ontroller DDR2 Refresh Spread Spectrum Clocking Mode Enabled Disabled Enabled Disabled Enabled Disabled Advanced Chipset Control sub menu Description Remapping of overlapped PCI memory above the total physical memory can be allowed denied If remapping of memory is done it will be accessible above 4GB and thus will require PAE support in OS DMA Controller can be enabled disabled Allows override selection of the DDR2 refresh rate for normal operation Higher Refresh Rate may be required when operating in high temperature environments Allows BIOS to set Clock Spread Spectrum for EMI electromagnetic interference control 128 Help text Enabled Allows remapping of overlapped PCI memory above the total physical memory Requires PAE support in 05 Disabled Memory remapping not allowed Enabled DMA controller enabled Disabled DMA controller disabled Allows override selection of the DDR2 refresh rate for normal operation Enabled Allows setting of Clock Spread Spectrum for EMI control Disabled Denies setting of Clock Spread Spectrum for EMI control AT8030 User s Guide Software Setup 5 1 5 Feature Supervisor Password User Password Set Supervisor Password Set User Password Clear User Password User Access Level Execute Disable Bit Security Menu Option Installed Not Installed Installed Not Installed Enter Enter Enter No
187. or Double symbol Error Detect DFTG Design For Testability Guidelines C Central Processing Unit This sometimes refers to a whole blade not just a processor component CPUID CPU IDentification Code that uniquely identify a processor type M CRC Cyclic Redundancy Check S1 S2 TS DDR II 1 2 AT8030 User s Guide Acronyms Descriptions SP am R DTS igi Enhanced Host Controller Interface Specification for Universal Serial Bus specification revision 2 0 EIA Electronic Industries Alliance EISA Extended Industry Standard Architecture Superset of ISA 32 bit bus architecture EIST Same as SpeedStep Enhanced Intel SpeedStep Technology l C D Digital Signal Processing D Data Terminal Ready Extended Memory 64 Technology Intel 64 is Intel s implementation of x86 64 used by 64 bit operating systems SI i TH EM64T E E E E E ElectroStatic Discharge Enterprise South bridge Interface Interface to the 1 0 legacy bridge component of the Intel ICHx ETSI European Telecommunications Standards Institute FADT Fixed ACPI Description Table FAT File Allocation Table Usually followed by a number ex FAT32 which defines the number of bits used to address clusters on a disk FC Fibre Channel FCC Federal Communications Commission 1 3 AT8030 User s Guide Acronyms Descriptions FCPGA Flip Chip Pin Grid Array F First Customer Shipment Refers to Kontron scheduling for boards
188. orage 2 GB USB FLASH drive Management Controller compliant to 0 R2 0 and IPMI v1 5 rev 1 1 Management Controller is run time field reprogrammable without payload impact Robust fail safe bootblock implementation Remote upgrade capability from all IPMI interfaces Host Interface IPMB 0 LAN compliant to HPM 1 Fast interrupt driven SMS host interface compliant to IPMI KCS v1 5 rev 1 1 Gracefull shutdown support via ACPI IPMIWatchdog supporting FRB2 POST OS Load and 5 5 05 watchdog with interrupt on pretimeout IPMI v2 0 IOL and Serial Over Lan support on base interface FRU Inventory Area support SENSOR device support Supports a system management interface via an IPMI V1 5 compliant controller Watchdog for BIOS execution and OS loading through Hardware system monitor voltages temperature CPU temperature monitor alarm board temperature sensor power failure through the management controller BIOS Storage Connectors BIOS Features IPMI Features Supervisory 6 AT8030 User s Guide Product Description 1 6 Board Specifications all Table 1 4 Board Specifications all Features Board Specifications 05 Compatibility CPU Engine 0 1 amp 2 Power Requirements Environmental Temperature Environmental Humidity Environmental Altitude Environmental Shock Environmental Vibration Reliability Safety EMC Description PICMG 3 0 Advanced TCA core specifi
189. ower up because it power request is deny Sensor type CDh OEM Kontron FRU Power denied Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger Normal Condition Power Deny deasserted offset 1 event trigger Shelf Manager deny Power to this FRU see table sws 10 1176 for event trigger information Module Data agent that verify FRUO Data validity checksum E key etc Sensor type C5h OEM Kontron FRU Info Agent Event Reading type code OAFh Generic Discrete offset 6 8 are used see table sws 10 1138 for event trigger information Module Data agent that verify FRU1 Data validity checksum E key etc Sensor type C5h OEM Kontron FRU Info Agent Event Reading type code OAFh Generic Discrete offset 6 8 are used see table sws 10 1138 for event trigger information Module Data agent that verify FRU5 Data validity checksum E key etc Sensor type C5h OEM Kontron FRU Info Agent Event Reading type code OAFh Generic Discrete offset 6 8 are used see table sws 10 1138 for event trigger information Management sub system health non volatile memory error Sensor type 28h Management Subsystem Health Event Reading type code 6Fh Sensor specific only offset 1 is used offset 1 event trigger IPMC Non volatile memory error see IPMI v1 5 table 36 3 Sensor type code 28h for sensor definition IPMC reboot detection Sensor type 24h Platform Alert Event Reading type code 03h Digital Disc
190. p of DRAM Optional ROM free LAN BIOS if activated 30KB See Note 2 SAS BIOS if activated 18KB at runtime See Note 1 Optional ROM Free C0000h See detailed map to the right XBDA USB Legacy BIOS Stac Video DRAM 0 622KB DRAM A0000h Note 1 LAN BIOS address may vary Note2 SAS BIOS address may vary Size is only 2KB if no device Address Function 00000 9B7FF 0 622 KB DRAM 9B800 9FFFF 622KB 640 KB XBDA USB Legacy BIOS Stack A0000 BFFFF Video DRAM Optional ROM Free C0000 DBFFF LAN BIOS around 30KB if activated address may vary External Fiber Channel BIOS 18KB 64KB address may vary E0000 FFFFF System BIOS 100000 PCI Memory DRAM available A 1 AT8030 User s Guide A 2 Kontron 1 0 Mapping Address Optional Address Function A 2 AT8030 User s Guide PCIIDSEL and Device Numbers A 3 1 Engine 0 BUS DEV V ID D ID Funct Description PCI Description 0 00 8086 35b0 0 Intel Corporation 3100 Chipset Memory 1 0 Controller Hub Host Bridge 0 00 00 8086 35b1 1 3100 DRAM Controller Error Reporting Class 00 00 02 8086 35b6 0 Intel Corporation 3100 Chipset PCI Express Port A PCI Bridge 00 03 8086 35b7 0 Intel Corporation 3100 Chipset PCI Express Port A1 PCI Bridge 00 1c 8086 2692 1 Intel Corporation 3100 Chipset PCI Express Root Port 2 PCI Bridge 0 1 0 8086 2689 Intel Corporation 3100 Chipset UHCI USB Controller 2 USB Conteoller 0 8086 26
191. pe of console emulation used Select the typeof for both serial ports console emulation used Configures terminal display mode If Normal Mode console redirection done by the BIOS after POST will send ANSI codes Normal Mode If Recorder Mode console redirection done by Select terminal display the BIOS after POST will not send ANSI codes mode This will result in faster text outputs similar to a Linux console but any program that rely on ANSI code to position the text will be practically unreadable Terminal Display M erminal Display Mode R corder mails Select if BIOS POST Enabled Configures if BIOS POST messages are messages are duplicated BIOS Printouts 3 duplicated in a separate reserved memory in separate reserved Disabled region for 05 examination memory region for OS examination 135 AT8030 User s Guide Software Setup 5 1 7 2 Channel Number Channel Status IP Address MAC Address Subnet Mask Gateway Address VLAN ID VLAN Priority Active LAN Channel Number 5 1 7 3 LAN Parameter Selector Channel Number Channel Status IP Address Current IP Address Set LAN Configuration Sub menu Description Valid or Invalid N A N A N A N A N A N A Each interface has a channel number that is used when configuring the channel and for routing messages between channels Only one channel on Base interface is available The channel number assign
192. pecifications CPU1 amp 2 Section Table 1 3 Board Specifications CPU1 amp 2 Section Features Description One 1 5 GHz Intel LV 17400 dual core processor Passive heatsink s 32KB L1 instruction 32KB L1 data cache dedicated for each core 4MB L2 cache on each processor chip shared by both cores Processors Cache Memory Chipset Embedded Northbridge MCH and Southbridge ICH Intel 3100 CPUs Front Side bus at 667 MHz 64 bit data 36 bit address Bus Interface Single channel DDR2 Registered ECC at 400 MHz One configurable PCI express port 1x4 mode Expansion Slot Up to 4 on 1x240 pin latching DDR 2 400MHz SDRAM PC2 3200 System Memory ECC support support SEC DED 512Mbit 1Gbit or 2Gbit Technology only Two redundant 1MB BIOS Field software upgradeable Roll back functionality controlled by the management controller 1 selectable Serial Port RJ 45 1 USB 2 0 10 Save CMOS in Boot from all Ethernet interfaces Boot from USB 2 0 Floppy CD ROM Hard Disk Flash Auto configuration and extended setup Diskless Keyboard less and battery less operation extensions System and LAN BIOS shadowing Advanced Configuration and Power Interface ACPI 1 0 amp 2 0 Console redirection to serial port VT100 with CMOS setup access Field updateable BIOS Event SERR PERR correctable uncorrectable ECC POST errors PCI Express log support to the management controller St
193. r IPMC Bridging Commands ICMB 2 Bridge Request Bridge Message IPMI Spec section ICMB ICMB Carrier IPMC Kontron support on NetFn CMD IPMI BMC req IPMC Bridge Bridge Table 4 28 Event ICMB Commands for IPMC Event Commands ICMB 2 Get Event Count Set Event Destination IPMISpec section ICMB ICMB IPMC Kontron support on NetFn CMD IPMI BMC req IPMC Bridge Bridge 31h 48 AT8030 User s Guide Hardware Management IPMISpec section Set Event Reception State Send ICMB Event Message ICMB ICMB Get Event Destination ICMB Get Event Reception State CMB NetFn CMD IPMI BMC req Bridge 32h 0 M Bridge 33h 0 M Bridge 34h 0 M Bridge 35h 0 M Table 4 29 0EM for Bridge NetFn ICMB Commands for IPMC IPMI Spec section NetFn CMD IPMI BMC req Carrier IPMC req Kontron support on IPMC 0 No No No No Carrier IPMC Kontron support on IPMC req OEM Commands for 0 Bridge NetFn 0 0 OEM Commands ICMB Bridge COh FEh 0 M No Table 4 30 0ther Bridge ICMB Commands for IPMC IPMISpec section Other Bridge Commands NetFn CMD IPMI BMC req Carrier IPMC Kontron support on req IPMC 0 0 0 Error Report ICMB Bridge FFh 0 M No Table 4 31 PICMG 3 0 Commands for IPMC IPMISpec section AdvancedTCA Get PICMG Properties Get Address Info Get Shelf Address Inf
194. r higher overall system performance These transfers may be individually designated to be coherent snooped on the FSB or non coherent not snooped on the FSB providing improvements in system performance and utilization when cache coherence is managed by software rather than hardware EDMA also enables quality of service by prioritization of data 16 AT8030 User s Guide Board Features 2 3 2 3 USB 2 0 Interfaces Each CPU engine embeds a USB storage controller This controller is compliant to USB 2 0 CPU engine provides two USB ports on the face plate and one on the RTM CPU engine 1 amp 2 provide one USB port on the front plate Those ports can be used for external storage and for booting USB features include Capability to daisy chain as many as 127 devices per interface Fastbi directional Isochronous asynchronous interface 480 Mbs transfer rate Standardization of peripheral interfaces into a single format Retro compatible with USB 1 1 devices USB supports Plug and Play and hot swapping operations OS level These features allow USB devices to be automatically attached configured and detached without reboot or running setup Table 2 1 USB Connector Pinout Signal Path 2 USB 2 0 on front panel for CPU engine 0 310 amp 216 1 USB 2 0 on front panel for CPU engine 1 J17 1 USB 2 0 on front panel for CPU engine 2 215 m BIOS Settings 000 002080 gt USB Configuration
195. r specific offset 0 1 are used 105 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event trigger Internal Temperature sensor presence on DIMM sensor 10 if absent on board diode is used Sensor type 25h Entity Presence Event Reading type code 6Fh Sensor specific only offset 0 1 are used offset 0 event trigger no event generated Entity Present offset 1 event trigger no event generated Entity Absent see IPMI v1 5 table 36 3 Sensor type code 25h Entity Presence for sensor definition BX Temp Pre SPDO Internal Temperature sensor presence on DIMM1 sensor 11 if absent on board diode is used Sensor type 25h Entity Presence Event Reading type code 6Fh Sensor specific only offset 0 1 are used Only 9 offset 0 event trigger event generated Entity Present offset 1 event trigger no event generated Entity Absent see IPMI v1 5 table 36 3 Sensor type code 25h Entity Presence for sensor definition Internal IPMC firmware diagnostic BX IPMI Info 1 event trigger internal error condition Internal IPMC firmware diagnostic BX IPMIInfo 2 event trigger internal error condition 4 5 2 2 MMC Built in sensors aggregation for health sensor The following table shows the sensors involved in the health sensor aggregation This sensor is part of table MMC built in Sensor SWS 10 1051 sensor name BX Health Error Table
196. rectly to the RTM and there is a direct connection between the AMC connector and the RTM The front plate serial port selection user interface is composed of four green LEDs and one pushbutton On a blade insertion the default selected port is the Ethernet Switch ES and the corresponding LED is turned on the other LEDs remain off Each time the user presses the button the selected port changes to the next one in the following sequence ES then CPUO then CPU1 then CPU2 then ES and so on Table 2 2 Serial Interface Pinout Driven Active but Not Used Not Used Note Standard product uses a RJ 45 8 pins connector RI ring indicator and DCD data carrier detect signals are not available The pinout is a custom one notthe same as RS 232D TIA EIA 561 20 AT8030 User s Guide Board Features Signal Path 1 of each X86 CPU can be routed to the RTM or to their companion MMC IPMC for SOL They can also be routed to a RJ45 on the front plate or to the RTM COM2 of the X86 CPUs are routed to the RTM UARTO of the ES can be routed to a RJ45 on the front plate or to the RTM BIOS Settings 101 900 29198 System Management gt Remote Access Configuration 2 6 Mezzanine One site is available Characteristics of the AMC are as follow Type B Support mid size single width mechanical format PCI Express X4 with reference clock AMC FCLKA Fully compliant PCI Express hot swap support
197. rete offset 0 1 are used offset 0 event trigger Normal Condition IPMC is running offset 1 event trigger IPMC has reboot see IPMI v1 5 table 36 3 Sensor type code 24h for sensor definition IPMC firmware upgrade detection Sensor type 2Bh Version Change Event Reading type code 6Fh Sensor specific only offset 1 is used offset 1 event data 2 00h unspecified event trigger A sensor configuration has changed offset 1 event data 2 02h Firm Rev event trigger A Firmware Upgrade has been done see IPMI v1 5 table 36 3 Sensor type code 2Bh Version Change for sensor definition 57 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event Trigger Specify if the status of the SEL Cleared Almost Full Full Sensor type 10h Event Logging Disable Event Reading type code 6Fh Sensor specific only offset 2 4 5 are used offset 2 event trigger The SEL has been cleared offset 4 event trigger The SEL is Full offset 5 event trigger The SEL has reached 75 of its capacity see IPMI v1 5 table 36 3 Sensor type code 10h Event Log Disable for sensor definition SEL State Voltage on 1 2v board power supply Sensor type 02h Voltage Event Reading type code O1h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 1 16v 10 Lower Critical Event 1 04v 1090 Hysteresis 0 017v
198. rier Commands for IPMC IPMISpec section NetFn pues Carrier IPMC Kontron support on req IPMC AMC Table Set AMC Port State Table 3 27 PICMG 19h 0 M Yes Get AMC Port State Table 3 28 PICMG 1Ah 0 M Yes Set Clock State Table 3 44 PICMG 2Ch 0 M Yes Get Clock State Table 3 45 PICMG 2Dh 0 M Yes 4 4 2 Sensor Data Records Information that describes the IPMC capabilities is provided through two mechanisms capabilities commands and Sensor Data Records SDRs Capabilities commands are commands within the IPMI command set that return fields providing information on other commands and functions the controller can handle Sensor Data Records are data records containing information about the type and number of sensors in the platform sensor threshold support event generation capabilities and information on what types of readings the sensor provides The primary purpose of Sensor Data Records is to describe the sensor configuration of the hardware management subsystem to system software The IPMC are required to maintain Device Sensor Data Records for the sensors and objects they manage Access methods for the Device SDR entries are described in the IPMI 1 5 specification Section 29 Sensor Device Commands 50 AT8030 User s Guide Hardware Management After a FRU is inserted the System Manager using the Shelf Manager may gather the various SDRs from the FRU sIPM Controllerto learn the various objects and how to use th
199. rmation from IPMI Get Device ID Command byte 14 The byte is displayed as a 2 digit hexadecimal number Displays implementation specific auxiliary information from IPMI Get Device ID Command byte 15 The byte is displayed as a 2 digit hexadecimal number Displays implementation specific auxiliary information from IPMI Get Device ID Command byte 16 The byte is displayed as a 2 digit hexadecimal number 141 Help text N A display only N A display only N A display only N A display only N A display only N A display only N A display only N A display only AT8030 User s Guide Software Setup 5 1 8 Exit Menu Feature Exit Saving Changes Exit Discarding Changes N A Load Setup Defaults Discard Changes Exit amp Update BIOS Exit amp Execute BIOS Swap N A Description Saves modified settings into non volatile memory and reboots the system Discards modifications to settings and reverts tothe state when Setup was entered then complete remaining POST Loads the factory default settings Discards modifications to settings and reverts to the state when Setup was entered Discard changes and forces a BIOS recovery mode on the next system reset and performs the system reset A recovery USB CD ROM Flash disk or floppy must be present or the system needs to be configured for serial recovery mode This mode can be used when on board recovery jumper is not installe
200. rough HPM 1 functionalities The upgrade of the firmware is also done using HPM 1 functionalities of IPMITOOL The upgrade can be done through any IPMI interface and is designed to be without payload impact Kontron recommends to use it s update CD to upgrade the firmware To obtain the update CD contact Kontron technical support department E 1 AT8030 User s Guide E 2 Updating AT8030 BIOS The AMI Linux upgrade utility is used to upgrade the BIOS Please note that you ll have to reboot in order to take advantage of the new BIOS Itis important to use compatible BIOS IPMC and FPGA versions Since all these software and hardware solution are exchanging information they must be in synch Please always follow Kontron documentation forall your upgrade Kontron recommand to use it s update CD to upgrade the BIOS To obtain the update CD contact Kontron technical support department The recommended upgrade sequence must be FPGA IPMC BIOS To read the actual version of FPGA and IPMC use the IPMITOOL tool The BIOS version is written at every boot during BIOS POST you can also get it by entering BIOS Setup Menu The BIOS Setup does also provide the IPMC firmware version via the IPMI Menu Type the following afulnx2 1 lt 105 BIN File pbnc enter no space between i and the filename pbncis for b Program Boot Block n Program NVRAM c Destroy System CMOS After the upgrade process is completed reboot by typing
201. rview The Front Blade Unit is divided in multiple sections In this way each CPU engine represents a virtual The following figure represents all virtual devices present on the Front Blade Unit and the virtual links This figure helps to clarify some sections for the E Keying It gives an overview of the logical physical interconnections available between and carrier components including pseudo AMCs virtual carrier resources and intelligent RTM 29 AT8030 User s Guide Installing the Board Figure 3 3 Board and Carrier Point to Point Interconnect Overview FRU1 AMC B1 Res Id 85h FRU2 CPU 0 engine Res Id 86h DL IU nr FRU3 CPU 1 engine Res Id 87h FRUA4 CPU2 engine Res Id 88h Link Type unn USB Link FRUO PowerQuicc amp Ethernet switch subsystem Res Id 0 11 PCle Link OEM Serial Console Interconnect OEM Update Channel Interconnect 100 BaseT Link SAS Link 1000 Base BX XAUI 10G Base BX4 XAUI or GbE Exclusive FRU 5 RTM Res Id 90h Zone 2 30 AT8030 User s Guide Installing the Board 3 5 Board Hot Swap and Installation Because of the high density pinout of the hard metric connector some precautions must be taken when connecting or disconnecting a board to from a backplane 1 Rail guides must be installed the enclosure to slide the board to the backplane 2 Donotforce the board if there is mechanical r
202. s M IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support Get FRU Inventory Area Info Read FRU Data Storage 11h Write FRU Data Storage 12h Storage 10h Table 4 21 SDR Device Supported Commands for IPMC IPMI Spec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC SDR Device Commands M 0 Get SDR Repository Info 27 9 Storage 20h M M No Get SDR Repository Allocation Info Reserve SDR Repository 27 11 Storage 22h M No Get SDR 27 12 Storage 23h M No 27 10 Storage 21h 0 No 45 AT8030 User s Guide Hardware Management IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC Add SDR 27 13 Storage 24h Partial Add SDR 27 14 Storage 25h Delete SDR 27 15 Storage 26h Clear SDR Repository 27 16 Storage 27h GetSDRRepository Time 27 17 Storage 28h 0 M SetSDRRepository Time 27 18 Storage 29h 0 M Enter SDR Repository Update Mode Exit SDR Repository Update Mode Run Initialization Agent 27 21 Storage 2Ch 0 27 19 Storage 2Ah 0 27 20 Storage 2Bh M Table 4 22 SEL Device Supported Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC SEL Device Commands Get SEL Info 25 2 Storage 40h Get SEL Allocation Info 25 3 Storage 41h Reserve SEL 25 4 Storage 42h Get SEL Entry 25 5 Storage 43h Add SEL Entry 25 6 Storage 44h Partial Add SEL Entry 25 7 Storage 45h Delete SEL Entry 25 8 Storag
203. s a reference to the DPLL Anyone of the PLL clock outputs can be used to feed the AMC s TCLKA using the FPGA interface Please refer to section B 5 If a backplane clock is lost the circuit will automatically switch to the redundant clock If all backplane clocks are lost the PLL will switch to holdover mode until a clock reappears If both copies of the 19 44MHz from CLK2A and CLK2B are lost the clock control circuitry activates an alarm to the IPMC as long as the telecom sync option is enabled in the shelf The PLD is field upgradeable If upgrade is necessary for this device an appropriate procedure will be provided with the code update Refer to the register description in appendix B 5 and to the 2130108 datasheet available on Zarlink s web site www zarlink com for further details on possible clock speed and configuration 22 AT8030 User s Guide Board Features 2 9 Redundant IPMC MMC Firmware amp BootBlock The IPMC MMC run firmware from their internal 512KB flash The BootBlock manager keeps the two copies of the IPMC MMC firmware in dedicated flash memories Tt acts as a watchdog to the IPMC MMC and can rollback a firmware update in the IPMC MMC in case of problems Note The IPMC MMC has an internal hardware watchdog 23 AT8030 User s Guide 3 Installing the Board Setting JuimpelsS ona serva 2b PROCESSON uale te de EM EN 26
204. se event Upper Critical event 2 63v 5 Lower Critical event 2 37v 5 Hysteresis 0 038v 1 5 58 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Vcc 3 3V Vcc Mez Hold UP Vcc 12V Vcc 1 2 SUS Vcc 3 3V SUS Vcc 5V SUS Description Sensor Type Event Trigger Voltage on 3 3v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 3 47v 5 Lower Critical event 3 13v 5 Hysteresis 0 050v 1 5 Voltage on 5v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 5 25v 5 Lower Critical event 4 75v 5 Hysteresis 0 075v 1 5 Voltage on power mezsanine Vcc HUV Hold UP Audio filter Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Critical event 59 2v 5 Lower Critical event 16v 5 Hysteresis 1 6v 1 5 Voltage on 12v board power supply Sensor type 02h Voltage Event Reading type code 01h threshold base Event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Crit
205. ser P password sol activate Ifthis command returns Command not supported in present state disconnect the serial cable in the front serial RJ45 connector 3 To access the CMOS BIOS menu reset the board Board BIOS splash screen will appear Follow information to enter BIOS CMOS menu 4 Ifyouhave a Linux console started on ttySO getty or other upon boot you should get a login prompt if you have the proper security configured infile etc securetty In order to have a console on ttySx here is an example of the command to be added in the inittab file adds1 2345 respawn sbin agetty hL ttySO 115200 vt100ininittab file etc inittab the line should be add before 1 2345 respawn sbin mingetty tty1 See Linux documentation for complete details on how to get a Linux console started serial ttySO 114 AT8030 User s Guide 5 Software Setup AMI BIOS Setup Program state eid Fo 116 EET 143 Console Redirection VT100 Mode 144 145 115 AT8030 User s Guide Software Setup 5 Software Setup 5 1 AMIBIOS Setup Program All relevant information for operating the board and connected peripherals is stored in the CMOS memory backed up by a supercap CPU Engine 0 only or in the main BIOS flash and EEPROM The latest is the default configuration 5 1 1 Accessing the BIOS Setup Utility The sy
206. set 1 is used offset 1 event trigger IPMC Non volatile memory error see IPMI v1 5 table 36 3 Sensor type code 28h for sensor definition Management Controller reboot detection Sensor type 24h Platform Alert Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger Normal Condition IPMC is running offset 1 event trigger Management Controller has reboot see IPMI v1 5 table 36 3 Sensor type code 24h for sensor definition Management Controller firmware upgrade detection Sensor type 2Bh Version Change Event Reading type code 6Fh Sensor specific only offset 1 is used offset 1 event data 2 00h unspecified event trigger A sensor BX Ver change configuration has changed offset 1 event data 2 02h Firm Rev event trigger A Firmware Upgrade has been done see IPMI v1 5 table 36 3 Sensor type code 2Bh Version Change for sensor definition BX MMC Reboot Temperature of CPU Sensor type 01h temperature Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 65 deg C Upper Critical event 75 deg C Upper Non Recoverable 125 deg C Hysteresis 2 deg C All value can be adjusted after thermal analysis BX Temp CPU 101 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event trigger Fabric Base interfaces Temp
207. ssion 18 17 App 3Ch Get Session Info 18 18 App 3Dh Get AuthCode 18 19 App 3Fh Set Channel Access 18 20 App 40h Get Channel Access 18 21 App 41h No Set User Access 18 23 App 43h No No App 45h Get User Name 18 26 App 46h Set User Password 18 27 App 47h oj Table 4 16 Chassis Device Supported Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC 0 Chassis Device 0 Commands Get Chassis Capabilities 22 1 Chassis 00h M Yes Get Chassis Status 22 2 Chassis 01h 0 Yes Chassis Control 22 3 Chassis 02h 0 M Chassis Reset 22 4 Chassis 03h Chassis Identify 22 5 Chassis 04h Set Chassis Capabilities 22 6 Chassis 05h Set Power Restore Policy 22 7 Chassis 06h 43 AT8030 User s Guide Hardware Management IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC Get System Restart Cause 22 9 Chassis 07h 0 0 No Get System Restart Cause Chassis 08h No Get System Restart Cause Get POH Counter Chassis OFh No Chassis 09h No Table 4 17 Event Supported Commands for IPMC IPMI Spec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC Event Commands M Set Event Receiver S E 01h M Yes Get Event Receiver S E 02h Yes Platform Event a k a Event Message 23 3 S E 03h Yes Table 4 18 PEF and Alerting Suppor
208. stem BIOS Basic Input Output System provides an interface between the operating system and the hardware of the AT8030 SBC Tt uses the AMI Setup program a setup utility in flash memory that is accessed by pressing the F2 key at the appropriate time during system boot This utility is used to set configuration data in CMOS RAM To run the AMI Setup program incorporated in the ROM BIOS Turn on or reboot the system When you get the following messages hit F2 key to enter SETUP AMIBIOS C 2006 American Megatrends Inc KONTRON AT8030 BIOS Version 2 00 EVALUATION COPY NOT FOR SALE C American Megatrends Inc 64 0100 000001 00101111 102907 WHITLAKE 5006 040 Y2KC CPU Engine 0 Physical Processors 1 Logical Processors 2 Core Multi Processing Enabled FSB Speed 666 MHz Processor 0 Core 0 Type Intel R Core TM 2 CPU 17400 1 50GHz Processor 0 Core 0 Speed 1 50 GHz Processor 0 Core 0 CPUID 06 6 Processor 0 Core 0 Update Revision 00 8 Processor 0 Core 1 Type Intel R Core TM 2 CPU 17400 1 50GHz Processor 0 Core 1 Speed 1 50 GHz Processor 0 Core 1 CPUID 06F6 Processor 0 Core 1 Update Revision 00 8 Reset Type Cold Reset Currently Running on Primary FWH BIOS Press DEL to run Setup FA on Remote Keyboard Press F12 if you want to boot from the network Press F11 for BBS POPUP F3 on Remote Keyboard nitializing USB Controllers Done 116 AT8030 User s Guide Software Setup
209. t Based Sensor Watt Event Reading type code 01h threshold base event base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 27 Watts TBC Upper Critical event 30 Watts TBC Hysteresis 3 75 Watts FRU 5 RTM Power consumption in watts Sensor type OBh Other Unit Based Sensor Watt Event Reading type code 01h threshold base event trigger base on following thershold see IPMI v1 5 section 29 13 3 for threshold base event Upper Non Critical event 21 25 Watts TBC Upper Critical event 25Watts TBC Hysteresis 1 75 Watts Board reset type and sources Sensor type CFh OEM Kontron Reset Sensor Event Reading type code 03h Digital Discrete offset 0 1 are used see table sws 10 1177 for event trigger information 55 AT8030 User s Guide Hardware Management IPMI sensor ID Sensor Name Description Sensor Type Event Trigger Specify if the communication with the event receiver ShMc has been lost Sensor type 1Bh Cable Interconnect Event Reading type code 03h Digital Discrete offset 0 event trigger communication with ShMC lost offset 1 event trigger communication with ShMC regain see IPMI v1 5 table 36 2 and table 36 3 for sensor definition IPMI Watchdog Sensor type 23h Watchdog 2 Event Reading type code 6Fh Sensor specific see IPMI v1 5 table 36 2 and table 36 3 for sensor definition 0 fault detection sensor
210. t sector see IPMI v1 5 table 36 3 Sensor type code 1Eh Boot Error for sensor definition Firmware Hub Boot Error Specify if it was unable to boot from the BIOS on the Firmware Hub Sensor type Boot Error Event Reading type code 6Fh Sensor specific only offset 3 is used offset 3 eventtrigger Invalid boot sector see IPMI v1 5 table 36 3 Sensor type code 1Eh Boot Error for sensor definition Advance Configuration and Power Interface State Sensor type Boot Error Event Reading type code 6Fh Sensor specific offset 0 to15 are used see IPMI v1 5 table 36 3 Sensor type code 22h Boot Error for sensor definition and event trigger IPMI watchdog Sensor type 23h Watchdog 2 Event Reading type code 6Fh Sensor specific offset 0 1 2 3 8 are used see IPMI v1 5 table 36 3 Sensor type code 23h Watchdog 2 for sensor definition and event trigger General health status Aggregation of critical sensor This list is flexible and could be adjust based on customer requirements Sensor type 24h Platform Alert Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger no critical sensors is asserted offset 1 event trigger one or multiple critical sensors are asserted see IPMI v1 5 table 36 3 Sensor type code 24h for sensor definition Kontron OEM MMC firmware upgrade Status Sensor type C7h OEM Management Controller firmware upgrade Status Event Reading type code 6Fh Senso
211. t up boot strap processor for POST Enumerate and set up application processors Re enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller Detects the presence of PS 2 mouse Detects the presence of Keyboard in KBC port Testing and initialization of different Input Devices Also update the Kernel Variables Traps the INTO9h vector so that the POST INTO9h handler gets control for IRQ1 Uncompress all available language BIOS logo and Silent logo modules Early POST initialization of chipset registers Uncompress and initialize any platform specific BIOS modules Initialize System Management Interrupt Initializes different devices through DIM See DIM Code Checkpoints section of document for more information Initializes different devices Detects and initializes the video adapter installed in the system that have optional ROMs Initializes all the output devices Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Activate ADM module Initializes the silent boot module Set the window for displaying text information Displaying sign on message CPU information setup key message and any OEM specific information Initializes different devices through DIM See DIM Code Checkpoints section of document for more information Initializes DMAC 1 amp DMAC 2 Initialize RTC date time
212. tage or temperature or which has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty Ifthe customer s eligibility for warranty has not been voided in the event of any claim he may return the product at the earliest possible convenience to the original place of purchase together with a copy of the original document of purchase a full description of the application the product is used on and a description of the defect Pack the product in such a way as to ensure safe transportation see our safety instructions Kontron provides for repair or replacement of any part assembly or sub assembly attheir own discretion or to refund the original cost of purchase if appropriate In the event of repair refunding or replacement of any part the ownership of the removed or replaced parts reverts to Kontron and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report issued by Kontron with the repaired or replaced item Kontron will not accept liability for any further claims resulting directly or indirectly from any warranty claim other than the above specified repair replacement or refunding In particular all claims for damage to any system or process
213. ted Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC 0 PEF and Alerting 0 Commands Get PEF Capabilities 24 1 S E 10h No Arm PEF Postpone Timer 24 2 S E 11h No Set PEF Configuration 24 3 S E 12h No Get PEF Configuration Parameters 5 13h Set Last Processed Event ID Get Last Processed Event S E 14h S E 15h Alert Immediate S E 16h PET Acknowledge S E 17h 44 AT8030 User s Guide Hardware Management Table 4 19 Sensor Device Supported Commands for IPMC IPMISpec section NetFn CMD IPMI BMC req Carrier IPMC Kontron support req on IPMC Sensor Device 0 Commands Get Device SDR Info 29 2 S E Get Device SDR 29 3 S E Reserve Device SDR Repository lt 29 4 S E Get Sensor Reading Factors 29 5 S E e Set Sensor Hysteresis 29 6 S E e Get Sensor Hysteresis 29 7 S E Set Sensor Threshold 29 8 S E Get Sensor Threshold 29 9 S E Set Sensor Event Enable 29 10 S E Get Sensor Event Enable 29 11 S E Re arm Sensor Events 29 12 S E Get Sensor Event Status 29 13 S E Get Sensor Reading 29 14 S E Set Sensor Type 29 15 S E Get Sensor Type 29 16 S E e SS 7 oj O lt lt 17 o z o of of z Table 4 20 FRU Device Supported Commands for IPMC req on IPMC FRU Device Command
214. ter systems to remain CE compliant only CE compliant parts may be used Maintaining CE compliance also requires proper cable and cabling techniques Although Kontron offers accessories the customer must ensure that these products are installed with proper shielding to maintain CE compliance Kontron does not offer engineering services for designing cabling systems In addition Kontron will not retest or recertify systems or components that have been reconfigured by customers xvi AT8030 User s Guide Preface Limited Warranty Kontron grants the original purchaser of Kontron s products a TWO YEAR LIMITED HARDWARE WARRANTY as described in the following However no other warranties that may be granted or implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron Kontron warrants their own products excluding software to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other users or long term storage of the product does not cover products which have been modified altered or repaired by any other party than Kontron or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence improper use incorrect handling servicing or maintenance or which has been damaged as a result of excessive current vol
215. ternal Firmware upgrade succeeded Component Firmware sensor specific Upgrade Status Firmware upgrade failed 39 AT8030 User s Guide Hardware Management Table 4 9 Kontron OEM FRU Over current Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 00h E Data 2 03h CBh 01h vent Data State 00h Over Current on Management power Standard IPMI OEM Kontron FRU Over Asserted O1h Over Current on Payload power Discrete Current State Event Data 3 FRU ID Deasserted Table 4 10 Kontron OEM FRU Sensor error Sensor definition Event Reading Sensor type SensorSpe Event Trigger type code cific offset 00h 03h CCh Oth Event Data 2 Standard IPMI OEM Kontron FRU Sensor State undefined Discrete Error sserted Event Data 3 FRU ID State Deasserted Table 4 11 Kontron OEM FRU Power denied Sensor definition Event Reading Sensor type Sensor Spe Event Trigger type code cific offset 00h Event Data 2 Power denial cause 03h CDh Oth Explicit by shelf manager or application Standard IPMI OEM Kontron FRU Power Discrete denied State O1h Decided by carrier based on fru information Asserted 03h Timeout shelf manager didn t grant power in time State FFh Undefined Deasserted Event Data 3 FRUID 40 AT8030 User s Guide Hardware Management Table 4 12 Kontron OEM Reset Sensor definition Event Reading Sensor type Sensor Spe type
216. tures 1 1b Connected through PLL 0 Ob Clock Receiver Clock Control 0x01 Descriptor 0 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 Ob Clock Receiver Descriptor 1 Dependent ClockId Direct clock Descriptor none Clock Id 0x01 Receiver input from CLK2A 85 AT8030 User s Guide Hardware Management Type 2D Clock Configuration Record 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Clock Control 0x01 7 2 Oh reserved Features 1 1b Connected through PLL 0 Clock Receiver Descriptor 0 Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 06 Clock Receiver Descriptor 1 Dependent ClockId 7 Direct clock Descriptor none Clock Id 0x02 Receiver input from CLK1B 7 1 Oh reserved 0 1b Activated by Application Indirect Clock Descriptors Count m 0x02 Direct Clock Descriptors Count n 0x00 Indirect clock Descriptor Clock Control 0x01 7 2 Oh reserved Features 1 1b Connected through PLL 0 Clock Receiver e o 4 e a Dependent ClockId 7 2 Oh reserved Features 1 1b Connected through PLL 0 Ob Clock Receiver Descriptor 1 Dependent ClockId 7 Direct clock Descriptor none Clock Id 0x03 Receiver input from CLK2B 7 1 Oh reserved 0
217. type 20h OS Critical Stop Event Reading type code 6Fhh Sensor specific only offset 1 is used offset 1 event trigger Linux Kernel panic encontered see IPMI v1 5 table 36 3 Sensor type code 20h 0S Critical Stop for sensor definition PQ3 OS stop PQ3 Processor checkstop condition encontered Sensor type 13h Critical Interrupt Event Reading type code 03h Digital Discrete offset 0 1 are used offset 0 event trigger normal condition no checkstop offset 1 event trigger processor is in checkstop condition see IPMI v1 5 table 36 3 Sensor type code 03h for sensor definition PQ3 Diagnostic Status Sensor type C9h OEM Kontron OEM Diagnostic Status Event Reading type code 6Fh Sensor specific offset 0 1 2 are used see table sws 10 1152 for event trigger information PQ3 Critical Int PQ3 Diag Status Kontron OEM External Component firmware upgrade Status Sensor type CAh OEM OEM Kontron External Component Firmware FwUp status Upgrade Status Event Reading type code 6Fh Sensor specific offset 0 1 2 are used U BOOT OEM Switch Management Status Switch Status Sensor type C8h OEM Kontron Switch Management Status Event Reading type code 6Fh Sensor specific offset 0 1 2 3 are used Kontron OEM IPMC firmware upgrade Status IPMC FwUp Sensor type C7h OEM Management Controller firmware upgrade Status Event Reading type code 6Fh Sensor specific offset 0 lare used Internal Temperature sensor presenc
218. u Selection Description Main Use this menu for basic system configuration Advanced Use this menu to set the Advanced Features available on your system Boot Use this menu to determine the booting device order Security Use this menu to configure Security features System Management Use this menu to set and view the System Managment on your system Exit Use this menu to choose Exits option Use the left and right arrows keys to make a selection 5 1 2 1 Legend Bar Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu The chart on the following page describes the legend keys and their alternates Table 5 2 BIOS Legend Bar Key Function F1 General Help windows see 4 1 2 2 Home or End Move cursor to top or bottom of window Esc Exit this menu lt PgUp gt or lt PgDn gt Move cursor to top or bottom of window gt arrow keys Select a different menu lt gt Select the Previous Value for the field lt gt Select the Next Value for the field lt F7 gt Disacard the changes for all menus lt Enter gt Execute Command display possible value for this field or Select the sub menu To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field To save value commands in the Exit Menu save the values displayed in all menus 118 AT8030 User s Guide Soft
219. ule until the retaining clips clip on each side Repeat these steps to populate the other socket To remove a memory module from a socket push sideway the retaining clips on each side of the socket to release the module Pull out the memory from the socket 28 AT8030 User s Guide Installing the Board 3 4 Onboard Interconnectivity 3 4 1 Onboard Connectors and Headers Table 3 4 0nboard Connectors and Headers Description Connector Comments CPU 0 XDP ITP J2 CPU 1 ITP 1 CPU 2 ITP 2 Serial Port J5 Shared RJ 45 Serial port connector Ethernet J6 Ethernet CPU Engine Ethernet J7 Ethernet CPU Engine USB CPUO A J10 USB 2 0 Connector on faceplate CPU Engine CPU 0 Memory 11 12 CPU 0 Memory sockets CPU 1 Memory J13 CPU 1 Memory socket CPU 2 Memory J14 CPU 2 Memory socket USB J15 USB 2 0 Connector on faceplate CPU Engine 2 USB CPUO B J16 USB 2 0 Connector on faceplate CPU Engine 0 USB CPU1 J17 USB 2 0 Connector on faceplate CPU Engine 1 ES Memory J18 ES Memory soket Update Ch Telco Clock J20 Update Channel and Telco Clock connector Zone 2 BaseInterfac amp FabricInterface 23 Base 8 Frabric Interfcae Connector Zone 2 RTM Connector J30 RTM connector to connect to the ARTM3 Zone 3 AMC B1 B1 Mid Size AMC connector Power Connector P10 Power Connector Zone 1 3 4 2 Board and Carrier Point to Point Interconnect Ove
220. umber type length Product Part Number T5006 Product Version type Calculated Calculated length Product Version XX Product Serial Number type length Product Serial Number XXXXXXXXX Product Part Number type length No more fields OxC1 Padding 0x00 Board Area Checksum Calculated Variable X may change on revisions Calculated Calculated 4 4 3 1 IPMC FRU 0 Board E Keying Information One or more Board Point to Point Connectivity Records are included in the Board FRU Information and describe the connections to the Base Fabric and Update Channel Interfaces that are implemented on the 64 AT8030 User s Guide Hardware Management Board These connections each consisting of some subset of the Ports in one or more Channels are generically referred to as a link For more details about this record refer to PICMG 3 0 R2 0 section 3 7 2 3 In addition to mandatory base interface links and to the XAUI capability on the fabric this record describes alternative 1000Base BX links on the fabric channel 1 and 2 and OEM connectivity on the update channel Table 4 37 Board Point to Point Connectivity Record Type 14 Atca Point to Point Connectivity Record Link Type Extension Bits 23 20 Oh None 01h PICMG 3 0 Base Interface 10 100 1000 BASE T Link Type Bits 19 12 n 3 0 Base Interface 10 100 Link Designator Bits 11 0 A Fabric Interface Channel 1 Port 0 1 Link Type Bits 19 12
221. ver LAN functionality is provided via an OpenIPMI utility named IPMILAN The IPMILAN daemon allows an IPMI system interface using the OpenIPMI device driver to be accessed using the IPMI 1 5 or 2 0 LAN protocol The IPMILAN utility establishes the session and provides a bridge with the IPMC to execute the requested commands The OpenIPMI IPMI utility has the following known features Limitations Allthe commands supported by the IPMC are working since they are forwarded from the IPMILAN utility to the IPMC via the host interface KCS Allthe minimum commands to establish a session are supported Session commands with invalid parameters may be unsupported depending on the error Allthe commands related to Channels are not supported 89 AT8030 User s Guide Hardware Management All the commands related to Users are not supported IOL and Users can be configured via a configuration file only Some commands related to Session are not supported SOL is not implemented IOL 1 5 and 2 0 session establishment supported RMCP supported algorithms are Authentication Straight Password There is no concept of integrity and confidentiality in RMCP IOL 1 5 RMCP supported algorithms are all the mandatory Authentication RAKP none RAKP HMAC SHA1 Integrity None HMAC SHA1 96 Confidentiality None AES CBC 128 Upgrading a firmware using IOL 2 0 or 1 5 is working 64 simultaneous sessions supported Since
222. ves in priority order Lists available CD DVD drives in priority order Lists available USB drives in priority order Lists available network drives in priority order Lists available other drives in priority order Enabled Allows skipping the memory tests during a cold boot Disabled Allows the extended memory test to be executed during a cold boot Enabled Extended memory test is applicable when Quick Boot 15 disabled and a cold reset occurs Disabled Extended memory test is not performed in a reset AT8030 User s Guide 130 Software Setup 5 1 6 2 1st Boot Device Nth Boot Device 5 1 6 3 Feature 1st Drive Nth Drive Boot Device Priority sub menu Description Specifies the priority of the available boot sources The list includes USB CD ROM USB Hard Drive SAS Hard Drive and PXE Other supported devices might be dynamically added to the list Type Boot device Specifies the boot priority of the available boot sources The list includes USB CD ROM USB Hard Drive SAS Hard Drive and PXE Other supported devices might be dynamically added to the list Type Boot device Hard Disk Drives sub menu Option Description Specifies the boot priority of the available Varies Hard Disk devices Specifies the boot priority of the available Hard Disk devices 131 Help text Specifies the priority of the available boot sources Specifies th
223. vice Supported Commands for 42 Watchdog Timer Supported Commands for 42 Device Messaging Supported Commands for 42 Chassis Device Supported Commands for 43 Event Supported Commands for 44 PEF and Alerting Supported Commands for 44 Sensor Device Supported Commands 45 FRU Device Supported Commands for 45 SDR Device Supported Commands for 45 SEL Device Supported Commands forIPMC 46 LAN Device Supported Commands for 46 Serial Modem Device Supported Commands 47 viii AT8030 User s Guide List of Tables Table 4 25 Table 4 26 Table 4 27 Table 4 28 Table 4 29 Table 4 30 Table 4 31 Table 4 32 Table 4 33 Table 4 34 Table 4 35 Table 4 36 Table 4 37 Table 4 38 Table 4 39 Table 4 40 Table 4 41 Table 4 42 Table 4 43 Table 4 44 Table 4 45 Table 4 46 Table 4 47 Table 4 48 Table 4 49 Table 4 50 Table 4 51 Table 4 52 Table 4 53 Table 4 54 Table 4 55 Table 4 56 Table 4 57 Table 4 58 Tabl
224. ving reset the bootstopkey the boot process can not be interrupted see section Setting the bootstopkey In the bootloader command prompt enter boot to continue the boot process G 2 Bootloader Commands The user interface of the u boot bootloader provides a set of powerful commands to the user The following functional groups can be distinguished Environment control Memory operations Flash operations PCI control Networking functions Application control Miscellaneous commands All commands available are listed with a short description when entering the help command help alias for help Base print or set address offset Bdinfo print Board Info structure bootm boot application image from memory bootp boot image via network using BootP TFTP protocol cmp memory compare G 1 AT8030 User s Guide memory crc32 checksum calculation echo echo args to console erase erase FLASH memory flinfo print FLASH memory information go start application at address addr help print online help iminfo print header information for application image loop infinite loop on address range md memory display mii MII utility commands mm memory modify auto incrementing mw memory write fill nm memory modify constant address pci list and access PCI Configuraton Space ping send ICMP ECHO REQUEST to network host printenv print environment varia
225. ware Setup To display a submenu use the arrow keys to move the cursor to the submenu you want Then press lt Enter gt 5 1 2 2 Field Help Window The help window on the right side of each menu displays the help text for the selected field It updates as you move the cursor to each field 5 1 2 3 General Help Windows Pressing lt F1 gt on any menu brings up the General Help window that describes the legend keys and their alternates Figure 5 2 BIOS General Help Windows General Help lt Select Screen Select Item Change Option Field Enter Go to Sub Screen PGDN Next Page PGUP Previous Page HOME Go to Top of Screen END Go to Bottom of Screen F2 F3 Change Colors F7 Discard Changes F9 Load Defaults ESC Exit F10 Save and Exit 119 AT8030 User s Guide Software Setup 5 1 3 Main Menu Feature Option Description Help text BIOS Version X YY KK Displays the AMI BIOS version N A display only Build Date MM DD YY Display the BIOS build Date N A display only BIOS ID 5006_XYY Displays the boot block version N A display only Boot Block Version XYY Diplay the FPGA Version N A display only Displays the X86 CPU Engine currently CPU Engine 0 1 2 executing this BIOS N A display only Displays DIMM 1 memory size DIMM 1 Memory Size DIMM electrically closest to MICH filled last XKB MB GB CPU 0 only Kontron DIMM slot physically furthest to the MIC
226. xit gt Exit and Execute BIOS Swap 2 4 Ethernet Interfaces 2 4 1 182571EB Ethernet Controller The four Ethernet controllers on the AT8030 are Intel s 82571EB The front panel connections of CPU engine 0 are two copper 10 100 1000Base T interfaces The backplane Base and Fabric Interface connections for all three CPU engines are 1000Base BX interface through the onboard Ethernet switch The 182571EB features high performance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K See www intel com for additional details on the 182571 The AT8030 has boot from LAN capability PXE on these ports Enable the option from the BIOS Setup Program Please refer to Section 5 1 AMI BIOS Set up Program Signal Path The Ethernet Management RJ45 connector is on the faceplate 110 BIOS Settings 900 15303 Advanced gt Expansion ROM Configuration 4 Software Usage You might need to configure the VLANs the onboard switch For proper commands please refer to the manual 18 AT8030 User s Guide Board Features 2 4 2 Onboard Ethernet Switch Broadcom BCM56502 The Onboard Ethernet Switch is a Broadcom 56502 24 Port GbE Multilayer Switch with two 10 GbE Uplink ports The board use 20 GbE and two 10GbE ports The four 4 unused ports are disabled by SW for power saving The BCM56502 provides a 32bit 66MHz PCI Management Interface which is connected to the Unit
227. xpress Port A1 Intel Corporation 3100 Chipset PCI Express Root Port 1 Intel Corporation 3100 Chipset PCI Express Root Port 2 Intel Corporation 3100 Chipset PCI Express Root Port 3 Intel Corporation 3100 Chipset PCI Express Root Port 4 Intel Corporation 3100 Chipset UHCI USB Controller 1 Intel Corporation 3100 Chipset UHCI USB Controller 2 Intel Corporation 3100 Chipset EHCI 0582 Controller Intel Corporation 82801 PCI Bridge Intel Corporation 3100 Chipset LPC Interface Controller Intel Corporation 3100 Chipset SMBUS Controller Intel Corporation 82571EB Gigabit Ethernet Controller Intel Corporation 82571EB Gigabit Ethernet Controller A 4 PCI Description Host Bridge Class ff00 System Peripheral PCI Bridge PCI Bridge PCI Bridge PCI Bridge PCI Bridge PCI Bridge USB Conteoller USB Conteoller USB Conteoller PCI Bridge ISA Bridge SMBus Ethernet Controller Ethernet Controller AT8030 User s Guide Kontron Extension Registers B 1 FPGA CPLD Registers Definition Unused bits are reserved To insure compatibility with other product and upgrades to this product do not modify unused bits Bits marked NU are not used on this board Writing to such bit does nothing and reading is undefined either 0 or 1 may be returned Legend Symbol Signification Unchanged stay unchanged after reset U X Not Defined bit not used on this board NU Not Used NA Not Applicable B 1 AT8030 User s Guide
228. y Update Mode Run Initialization Agent 27 21 Storage 2 27 19 Storage 2 27 20 Storage 2 95 AT8030 User s Guide Hardware Management Table 4 56 SEL Device Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req MMC SEL Device Commands Get SEL Info 25 2 Storage 40h No Get SEL Allocation Info 25 3 Storage 41h No No Reserve SEL 25 4 Storage 42h oj O 3 z Get SEL Entry 25 5 Storage 43h Add SEL Entry 25 6 Storage 44h z No No No Partial Add SEL Entry 25 7 Storage 45h Delete SEL Entry 25 8 Storage 46h Clear SEL 25 9 Storage 47h Get SEL Time 25 10 Storage 48h No Get Auxiliary Log Status 25 12 Storage 5Ah No Set Auxiliary Log Status 25 13 Storage 5Bh oj x No No S CO S Table 4 57 LAN Device Supported Commands for MMC built in IPMISpec section NetFn CMD IPMIBMCreq Carrier IPMC Kontron support on req LAN Device Commands 0 0 Set LAN Configuration Transpor Parameters na t 01 0 M 0 M Yes Get LAN Configuration Parameters 2 i M 0 M Yes Suspend BMC ARPs 19 3 0 M 0 M Yes Get IP UDP RMCP Transpor Statistics 19 4 t 04h 0 0 Yes Transpor 19 02h 0 Table 4 58 Serial Modem Device Supported Commands for MMC built in IPMISpec section NetFn CMD Carrier IPMC Kontron
229. zes the Microsoft IRQ Routing Table Prepares the runtime language module Disables the system configuration display if needed Initialize runtime language module Displays the system configuration screen if enabled Initialize the CPU s before boot which includes the programming of the MTRR s Prepare CPU for OS boot including final MTRR values Wait for user input at config display if needed Uninstall POST INT1Ch vector and INTO9h vector Deinitializes the ADM module Prepare BBS for Int 19 boot End of POST initialization of chipset registers Save system context for ACPI Passes control to OS Loader typically INT19h OEM POST Error This range is reserved for chipset vendors amp system manufacturers The error associated with this value may be different from one platform to the next OEM PCI init debug POST code during DIMM init See DIM Code Checkpoints section of document for more information D 4 AT8030 User s Guide D 4 DIM Code Checkpoints The Device Initialization Manager DIM gets control at various times during BIOS POST to initialize different system busses The following table describes the main checkpoints where the DIM module is accessed Checkpoint Description Initialize different buses and perform the following functions Reset Detect and Disable function 0 Static Device Initialization function 1 Boot Output Device Initialization function 2 Function 0 disables all device nodes PCI devi

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