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Xilinx UG029 ChipScope Pro Software and Cores User Guide v7.1

1. jets et LA Show DCODE r Aan p Show USERCODE Listing Show Configuration Status Bus Plot P E La Show JTAG Instruction Register Figure 4 23 Device Menu Options After selecting the configuration mode the JTAG Configuration dialog box opens Figure 4 24 This dialog box reflects the configuration choice and defaults to a blank entry for the configuration file ChipScope Pro Analyzer new project x JTAG Configuration File Directory cXilimaChipScope Pro 7 1i Select New File Cancel Figure 4 24 Selecting a Bitstream ChipScope Pro Software and Cores User Guide www xilinx com 4 21 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer To select the BIT file to download click on Select New File The Open Configuration File dialog box Figure 4 25 opens Using the browser select the device file you want to use to configure the target device It is important to select a BIT file generated with the proper BitGen settings Specifically the g StartupCIk JtagCIk option must be used in BitGen in order for configuration to be successful Once you locate and select the proper device file click Open to return to theJTAG Configuration dialog box Figure 4 24 Open Configuration File Look in ChipScope Pro 7 1i 4 data icons My Recent Gijret 5 0 Document e templates 3 Desktop My Documents 448 My Computer
2. 0 0 2 cece eee eee 1 29 Installing ChipScope Pro Software for Windows 2000 XP isses 1 29 Installing ChipScope Pro Software for Solaris 2 8and2 9 oooooommooomo 1 30 Installing ChipScope Pro Software for Linux 0 6 6 eee eee 1 31 Installing the Java Run time Environment 0 66 66 c cece eee 1 31 Chapter 2 Using the ChipScope Pro Core Generator Core Generator Overview 0 00 n ene e tenn nen ees 2 1 Generating an ICON Cote c s cccssiceai scans ese ER a tan 2 1 General ICON Core Options ssssresssygi esed orten sentit eee nnn eens 2 2 Choosing the File Destination eee 2 3 Selecting the Target Device Family 1 0 cc cee eee 2 3 Entering the Number of Control Ports 6 0 eee cece eee 2 3 Disabling the Boundary Scan Component Instance 6 eee eee 2 3 Selecting the Boundary Scan Chain 6 0 cece eee eee 2 3 Disabling JTAG Clock BUFG Insertion 2 4 Including Boundary Scan Ports 0 cc cette eens 2 4 Creating Example Templates 2 0 cnn 2 5 HDL Example Files oett e ore Hatin a d cem ees od epa is aa 2 5 Batch Mode Generation Argument Example Files 0 cee eee eee mo 2 5 Generating the Core iilis e kae be a acd ick i deed eee E Le dels 2 6 Using the ICON Core scissa marre merken ERR ERE sages Rr E e DER RE d 2 6 Generating an ILA CORE poet epe ERE adem Ein pda daa pui pad dade d 2 7 General ILA Core Options seers Thiini in EEE EE en 2 8
3. Core Utilization LUT Count 158 FF Count Previous xt Remove Unit U Netlist fiesta Rd rebuilding esigi copy c projectsumy design ise xstimy design cs ngc gt cA projectsimy_designise_xst_ngoimy_design_cs_signalbrowser ngo SetDesign my design 4 Figure 3 12 ATC2 Core STATE Mode Data Capture Settings ChipScope Pro Core Inserter my_design cdc File Edit Help BH o ATC2 Select ATC2 Options Pin Selection Parameters Net Connections Global Parameters Capture Mode Pin Edit Mode Endpoint Type TIMING Same as ATCK SINGLE ENDED _Detauts ATD Pin Count Signal Bank Count 8 Yx 4 Max Frequency Range 301 500MHz v v Enable Auto Setup Enable Always On Mode Individual Pin Settings Pin Name Pin Loc lO Standard ATCK AB21 LVCMOS25 JATDIO w21 LVOMOS25 Es n TIM E ATO 22 vcwo825 ATDGI n LVCMOS25 25 fa 7 reser y prom m LVCMOS25 ms Bo FAST gt ATD S v20 ATDIAL AA pron v22 pows e j xi 2 5 r Core Utilization LUT Count 114 FF Count 100 Netlist nta pet rebuilding lesi n copy cprojectsumy designtise xstimy design cs ngc gt ciprojectsimy_designlise_xsti_ngolmy_design_cs_signalbrowser ngo SetDesign my design Figure
4. Using RPMs The Use RPMs checkbox is used to select whether the individual cores should be relationally placed macros RPMs This option places restraints on the place and route tool to optimize placement of all the logic for the ChipScope Pro core in one area If your design uses most of the resources in the device these placement constraints may not be met The Use RPMs checkbox is checked by default in order to generate cores that are optimized for placement When this step is completed click Next Choosing ICON Options The first options that need to be specified are for the ICON core The ICON core is the controller core that connects all ILA ILA ATC and ATC2 cores to the JTAG boundary scan chain The ICON core has the parameters shown in Figure 3 6 Disabling JTAG Clock BUFG Insertion Disabling the JTAG clock BUFG insertion causes the implementation tools to route the JTAG clock using normal routing resources instead of global clock routing resources By default this clock is placed on a global clock resource BUFG To disable this BUFG insertion check the Disable JTAG Clock BUFG Insertion checkbox Note This should only be done if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew Make sure the design is adequately constrained to minimize this skew After selecting the desired ICON parameters Figure 3 6 click Next or New ILA Unit to automat
5. General IBA PLB Core Options The second screen in the Core Generator is used to set up the of the general IBA PLB core options Figure 2 27 e ChipScope Pro Core Generator IBA for Processor Local Bus General Options Design Files Output Netlist Aiba lb edn Browse Device Settings Device Family Virtex2P y v Use SRL16s v Use RPMs Clock Settings Sample On Rising ly Edge Of Clock PLB Bus Settings Number of PLB Masters 2 Number of PLB Slaves 4 lt Previous Figure 2 27 IBA PLB Core General Options Choosing the File Destination The destination for the IBA PLB EDIF netlist iba_p1b edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the IBA PLB core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan Il Spartan IIE and Spartan 3 device families including the QPro variants of these families Virtex II Pro is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spa
6. Trigger Width 8 Match Type Extended wiedges v Match Units 1 KA Bit Values 0 1 X R F B Counter Width 16 Y Functions lt gt gt gt lt lt TRIGO Trigger Width 16 Match Type Basic y Match Units 1 Bit Values 0 1 X E ed Counter Width Disabled Functions lt gt Trigger Condition Settings v Enable Trigger Sequencer Max Number of Sequencer Levels 16 Storage Qualification Condition Settings v Enable Storage Qualification lt Previous Next gt lessages Successfully read project ciprojectsimy_designliselmy_design cdc Netlist timestamp changed rebuilding design copy ciprojectsimy_designtiselmy_design_cs ngc gt ciprojectsimy designlisel ngoimy design cs signalbrowser ngo SetDesign my design Figure 3 7 ILA Core Trigger Parameters Selecting the Number of Trigger Ports Each ILA or ILA ATC core can have up to 16 separate trigger ports that can be set up independently After you select the number of trigger ports from the Number of Trigger Ports pull down list a group of options appears for each of these ports The group of options associated with each trigger port is labeled with TRIGn where n is the trigger port number 0 to 15 The trigger port options include trigger width number of match units connected to the trigger port and the type of these match units En
7. 1 27 Table 1 15 Solaris Requirements for ChipScope Pro 7 1i Tools 1 28 Chapter 2 Using the ChipScope Pro Core Generator Table 2 1 ILA Trigger Match Unit Types 0 2 11 Table 2 2 Maximum Data Widths for Virtex II II Pro 4 Spartan 3 3E 2 14 Table 2 3 Maximum Data Widths for Virtex E Spartan II IIE 2 14 Table 2 4 ILA ATC Trigger Match Unit Types 0 occ ee 2 23 Table 2 5 ILA ATC Clock Resource Utilization 2 26 Table 2 6 ILA ATC Output Buffer Types by Device Family 2 26 Table 2 7 ILA ATC Core Capabilities 00 eens 2 27 Table 2 8 CoreConnect OPB Protocol Violation Error Description 2 32 Table 2 9 OPB Signal Groups 0 eee 2 35 Table 2 10 IBA OPB Trigger Match Unit Types oooooccocococccccccccccos 2 37 Table 2 11 PLB Signal Groups 0 ee 2 47 Table 2 12 IBA PLB Trigger Match Unit Types 0 cece cece eee 2 50 Chapter 3 Using the ChipScope Pro Core Inserter Table 3 1 ILA Trigger Match Unit Types 0 cee 3 11 Table 3 2 Maximum Data Widths for Virtex II II Pro 4 Spartan 3 3E 3 14 Table 3 3 Maximum Data Widths for Virtex E Spartan II ITE 3 14 Table 3 4 ILA ATC Clock Resource Utilization 0 0 00 3 17 Table 3 5 ILA ATC Output Buffer Types by Device Family 3 17 Table 3 6 ILA
8. Table 2 8 CoreConnect OPB Protocol Violation Error Description Continued Priority Bit Encoding Error Description 9 000111 1 4 3 OPB retry OPB retry active for more than a single cycle 10 000000 1 2 1 OPB MxGrant More than 1 OPB_MxGrant signals active in same cycle 11 000001 1 2 2 OPB_MxGrant An OPB_MxGrant signal is active for a non owning master 12 000010 1 3 1 OPB_BusLock OPB_BusLock asserted without a grant in the previous cycle and without OPB_select 13 000011 1 3 2 OPB_BusLock Bus is locked and a master other than bus owner has been granted the bus 14 001000 1 4 4 OPB_retry OPB_select remained active after a retry cycle 15 001001 1 4 5 OPB retry OPB retry active with no Mx select 16 001110 1 8 1 OPB Select Mx Select signal active without having control of the bus via OPB MxGrant orOPB busLock 17 001111 1 8 2 OPB Select More than one Mx Select signals active in the same cycle 18 010000 1 9 1 OPB RNW OPB RNW high with no Mx select 19 011011 1 19 3 OPB RNW changed state during an operation before receipt of OPB xferAck 20 011100 1 19 4 OPB select changed state during an operation before receipt of OPB xferAck 21 011101 1 19 5 OPB BEBus changed state during a write or read operation before receipt of OPB_xferAck 22 011110 1 20 3 Byte enable transfer not aligned with address offset 23 011111 1 20 4 Byte enable transfer initiate
9. XILINX Chapter 3 Using the ChipScope Pro Core Inserter 3 30 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 7 XILINX Chapter 4 Using the ChipScope Pro Analyzer Analyzer Overview The ChipScope Pro Analyzer tool interfaces directly to the ICON ILA ILA ATC IBA OPB IBA PLB VIO and ATC2 cores collectively called the ChipScope Pro cores You can configure your device choose triggers setup the console and view the results of the capture on the fly The data views and triggers can be manipulated in many ways providing an easy and intuitive interface to determine the functionality of the design Note Even though the ChipScope Pro Analyzer tool will detect the presence of an ATC2 core an Agilent Logic Analyzer attached to a Xilinx JTAG cable is required to control and communicate with the ATC2 core The ChipScope Pro Analyzer tool is made up of two distinct applications the server and the client The ChipScope Pro Analyzer server is a command line application that connects to the JTAG chain of the target system using any of the supported JTAG download cables shown in Table 4 1 The ChipScope Pro Analyzer client is a graphical user interface GUI application that allows you to interact with the devices in the JTAG chain and the ChipScope Pro cores that are found in those devices Table 4 1 Operating System Support for the ChipScope Pro Analyzer Solaris 2 8
10. endstate state device devicenumber discard Required Arguments All arguments are passed directly to the cable driver handle Handle to the cable connection constant 0 1 Shift in a constant 0 or constant 1 Only required if buffer is not specified bitcount count Number of bits to shift Only required if buffer is not specified If buffer is specified the bitcount is automatically computed buffer buffer buffer is a binary string of bits Buffer to shift in to TDI Format is a string consisting of 0 s and 1 s like 1100101 Only required if constant is not specified Note Bits are shifted LSB gt MSB in the order of the Tcl string index This means that 100 will first shift 1 into TDI followed by 0 followed by O If you don t like this order make a simple function to reverse your strings before passing to the buffer Optional Arguments All arguments are passed directly to the cable driver endstate state State to navigate into after the shift operation One of TLR RTI SIR Default is SIR device devicenumber Shift bits into and out of devicenumber by padding extra bits IR lengths must be set up correctly to use this argument If no device is specified no padding is done and shifts apply to the entire jtag chain discard Do not return output buffer from the shift This is an optimization to allow ignoring the TDO pin when writing data to the chain Returns Bits shifted out of the JTAG
11. gt microPortaddr 06 microPortDataly 01 microPortData0y 01 nicroReadStrob Hals cud LULLE MALLEO EA ALLOULA EOLIE mn AA AT TT Ruler o To O Cursor PlaceXCursor GoToTrigger gt Place O Cursor microWritestrol microInterrupt npIrqInt tat sectorRead3tro sectorllrite tr sacfReadRegStr oO o o o o o oF sacfReconfigSti gt MPA reg BUS BUS MPCE reg MPOE reg Ll MPWE req MPIRQ reg ON o Bon o o EN olus o Ea MPBRDY req gt sine E r 4 did did bia gt X 60 s 0 1343 aJe AtX 0 1403 Figure 4 43 Centering the Waveform on a Marker Cursors Two cursors are available in the Waveform window X and O To place a cursor right click anywhere in the waveform section and select Place X Cursor or Place O Cursor A colored vertical line will appear indicating the cursor s position Additionally the status of all the signals and buses at that point will be displayed in the X or O column The position of both cursors and the difference in position of the cursors appears at the bottom of the Waveform window Both cursors are initially placed at sample 0 To move a cursor either right click in a new location in the waveform or drag the cursor using the handles X or O labels in the waveform header or drag the cursor line itself in
12. seen 2 38 Enabling the Storage Qualification Condition 0 cece eee eee 2 38 Enabling the Trigger Output Port cesses 2 38 IBA OPB Core Data Port Options isssssse en 2 39 Selecting the Data Depth sio e ed actus ede 2 39 Selecting the Data Type 2e Ea tede eee hacen de eb dead e 2 40 Entering the Data Width cese e ton wag kk nk ede ete 2 41 Selecting the Data Same As Trigger Ports 0 6 cece eens 2 41 Number of Block RAMS 444 xx rex oret s keda eere ies Snead CREE ER eR 2 41 ChipScope Pro Software and Cores User Guide www xilinx com vii UGO29 v7 1 February 16 2005 XILINX Creating Example Templates 2 0606 6 2 41 HDL Example Files s 7 SS cies deo AAA ela ara edu tet bg 2 42 Bus Signal Name Example Files cdc esee 2 42 Batch Mode Generation Argument Example Files oooo ooocooomomm o o 2 42 Generating the Core ica sisse dete raw rig ema RP a EE E 2 43 Using the IBA OPB Core 10 6 6 een 2 43 Generating the IBA PLB Core 4 4 beh vende Poe E weeded ed ees 2 44 General IBA PLB Core Options 6 0 0 cece nn 2 45 Choosing the File Destination cese e 2 45 Selecting the Target Device Family o oooccocooococconconcr ne 2 45 Using SRL168 vue iria ur ld eee he bate e A aa 2 45 Using RPMS eeen i a beeta hU PE bea tx A ate stets re 2 46 Selecting the Clock Edge oe sese ccr i 2 46 Selecting the PLB Bus Settings 6 6 6c cc c
13. 0000 cece eee eee 2 17 Generating the Cores esse eee ee pe ab ina eei een ree Rak ege RU Rn 2 17 Using the ILA Cote suis Sosa oi UTR UR DR SUE Red BE US dp ios 2 18 vi www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 7 XILINX Generating an ILAJATG Core ies ebur redu dba eds ad aad 2 19 General ILA ATC Core Options isssseee n 2 20 Choosing the File Destination cesse 2 20 Selecting the Target Device Family o ooocoocooccocconconcar ne 2 20 Using SREl68 eii ve weve ade ies oe RR Er a es ek ied eer Ee us 2 20 Using RPMS 4 5 robbed dues Be Cep ded kd tpa ab A 2 21 Selecting the Clock Edge 5 isses bee p E ES IRE REDE LEER nd 2 21 ILA ATC Core Trigger Port Options 2 21 Selecting the Number of Trigger Ports 6 cc cece eee eee eee 2 22 Entering the Width of the Trigger Ports 0 2 0 cece cece eens 2 22 Selecting the Number of Trigger Match Units sees 2 22 Selecting the Match Unit Type 2 6 6 ccc enn 2 23 Selecting Match Unit Counter Width 0 0 0 ce e 2 24 Enabling the Trigger Condition Sequencer 2 0 cece eens 2 24 Enabling the Trigger Output Port cesses ee 2 24 ILA ATC Core Data Port Options isse 2 25 Transmit Rate caved ok ot bev RI Reed nensis ey dee E E DE eda 2 25 Maximum CLK Port Frequency 0 00 cece cee hh n 2 25 Clock Resource Utilization 6 0 cece eee nee e has 2 26 Number of Data Pins 0
14. Separates items in a list of choices lowpwr on of Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 Name Name QOUT CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block name loci loc2 locn ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com xxiii XILINX Preface About This User Guide Online Document The following conventions are used in this document Convention Meaning or Use Example Cross reference link to a See the section Additional location in the current file or Resources for details Blue text ie in another file in the current Refer to Title Formats in document Chapter 1 for details Bos ias Cross reference link to a See Figure 2 5 in the Virtex II location in another document Handbook Go to http www xilinx com Blue underlined text Hyperlink to a website URL for the latest speed files xxiv www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction ChipScope Pro Tools Overview As the density of FPGA devices increases so does the impracticality of attaching test equipment probes to these devices under test The ChipScope Pro tools integrate key logic analyzer hardware components with the targe
15. o00 0000 0111 000_0001_0000 Cycle 10 J000 0000 1000 000 0010 0001 Cycle D000 0000 1001 000 0100 0010 Cycle12 Dooo oo00 1010 3000 1000 0011 Cycle 13 9000 0000 0000 001 0000 0100 Cycle14 D000 0000 0000 010 0000 O101 Cycle 15 Doo0 0000 0000 Jo cane Figure 4 49 The Pulse Train Dialog Single Pulse Synchronous outputs only The Signal Pulse control is a special kind of push button When the button is pressed instead of the core driving a constant active value for the duration of the button being pressed a pulse train with a single high cycle will be executed exactly once 4 42 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Help Global Console Controls Located at the bottom of the Console window are controls that affect all the inputs or outputs as applicable see Figure 4 50 Read Inputs Outputs Activity Display Key Read Period 250 ms y Update Static Inputs Blue ClearAllActivity y _ Outputs Green Reset All Figure 4 50 Global Controls and Key Read Inputs The Read Period at which the VIO core inputs are read is selectable via a combo box The default sample period is 250 ms You can also set the sample period to 500 ms 1s 2s or Manual Scan When Manual Scan is chosen the Read Once button becomes enabled At that point the VIO core inputs are only read when
16. D My Network File name bil Places Files of type All Files Figure 4 25 Opening a Configuration File Once the BIT file has been chosen click OK to configure the device Observing Configuration Progress While the device is being configured the status of the configuration is displayed at the bottom of the Analyzer window If the DONE status is not displayed a dialog box opens explaining the problem encountered during configuration If the download is successful the target device is automatically queried for ChipScope Pro cores and the project tree is updated with the number of cores present A folder is created for each core unit found and Trigger Setup Waveform and Listing leaf nodes appear under each ChipScope Pro unit A Bus Plot leaf node will appear only if the core unit is determined to be an ILA core Displaying JTAG User and ID Codes One method of verifying that the target device was configured correctly is to upload the device and user defined ID codes from the target device The user defined ID code is the 8 digit hexadecimal code that can be set using the BitGen option g UserID To upload and display the user defined ID code for a particular device select the Show USERCODE option from the Device menu for a particular device Figure 4 23 page 4 21 Select the Show IDCODE option from the Device menu to display the fixed device ID code for a particular device The results of these queries are displa
17. MPOE reg MPWE reg MPIRQ reg on o Hal o Hal Sl o Bon o al MPBRDY reg gt sine J In 4 Il la pia vl a gt X 1024 0 1024 GI a x 0 0 Figure 4 41 Zoom Area Using the Automatic Popup Menu To zoom in to the space marked by the X and O cursors select Waveform Zoom gt Zoom X O or right click in the waveform and select Zoom gt Zoom X O Other zoom features include zooming to the previous zoom factor by selecting Zoom Zoom Previous zooming to the next zoom factor by selecting Zoom Zoom Forward and zoom to a specific range of samples by selecting Zoom Zoom Sample Figure 4 42 Zoom to Sample End bon Window 0 Sample 1815 Figure 4 42 Zoom to Sample Range 4 34 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Analyzer Menu Features XILINX Centering the Waveform Center the waveform display around a specific point in the waveform by selecting Waveform gt Go To then centering the waveform display around the X and O markers as well as the previous or next trigger position or right click in the waveform and select Go To Figure 4 43 E waveform DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA nm bd E 1024 704 384 64 256 576 896 1216 1536 1856 2176 2496 2816 Bus Signal X0 9 microProgaddr AND rb_
18. System ACE le 02001093 1 MyDevice1 xC18V00 JB 105026093 2 MyDevice2 XC2VP4 ho 11238093 LULL JTAG Chain Transactions e Start transactions in Run Testidle End in Run Testidle Default Start transactions in Test Logic Reset End in Run Testidle Setting may matter when multiple applications take turn accessing the JTAG chain oK cancer Read USERCODES Figure 4 22 Advanced JTAG Chain Parameters Setup Window Device Configuration The ChipScope Pro Analyzer can configure target FPGA devices using the following download cables in JTAG mode only Xilinx Platform Cable USB Xilinx Parallel Cable III Xilinx Parallel Cable IV Xilinx MultiPRO Xilinx MultiLINX or Agilent E5904B TPA If the target device is to be programmed using a download cable by way of the JTAG port select the Device menu select the device you wish to configure and select the Configure menu option Only valid target devices can be configured and are therefore the only devices that have the Configure option available Figure 4 23 Alternatively you can right click on the device in the project tree to get the same menu as Device El ChipScope Pro Analyzer sacfdemo2 File View JTAG Chain Device Window Help DEV 0 MyDeviceO System ACE gt xi Project sacfdemo2 DEV 1 MyDevice1 XC18W00 B r sere mevn ve DEV MyDevice2 XC2VP4 M Rename UNIT 0 MyVIOO VIG Console Configure
19. Xilinx MultiLINX USB Cable If MultiLINX USB Cable is chosen no other setup is necessary The ChipScope Analyzer will automatically query the USB ports and connect to the cable If MultiLINX Serial Cable is chosen a configuration dialog box will open Figure 4 19 Select the correct port and baud rate The default values will work in most cases Note The ChipScope Pro Analyzer supports only the JTAG configuration mode for the MultiLINX cable regardless of port connection El ChipScope Pro Analyzer sacfdemo2 File View JTAG Chain Device Server Host Setting ChipScope Pro Analyzer sacfdemo2 x Project sac UNA Xilinx Parallel Cable 2 Serial Port Selection C O Xilinx MultiLINX Serial Cable q Port comi UNI O Xilinx MultiLINX USB Cable a H Xilinx Platform USB Cable Baud Rate Auto E Cx k Signals DE t Data Po B o arem Auto Core Status Pou wiere Figure 4 19 Opening a MultiLINX Serial Port Connection Opening a Platform Cable USB Connection To open a connection to the Parallel Cable including the MultiPRO cable make sure the cable is connected to one of the computer s parallel ports Selecting the JTAG Chain Xilinx Platform USB Cable menu option pops up a dialog window as shown in Figure 4 20 You can choose the speed of the cable from any of the settings 24 MHz 12 MHz 6 MHz 3 MHz default 1 5 MHz or 750 KHz Choose the speed tha
20. 32 bit Red Hat Linux Application M dtd pipe or Enterprise WS3 0 Solaris 2 9 32 bit 32 bit ChipScope Pro Yes No Yes Analyzer Server supported JTAG supported JTAG cables Platform cables Platform Cable USB Parallel Cable USB Parallel Cable IV Parallel Cable IV Parallel Cable III MultiPRO Cable III and MultiLINX and MultiPRO Agilent E5904B TPA ChipScope Pro Yes Yes Yes Analyzer Client Local and Remote Remote Only Local and Remote ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 4 1 XILINX Chapter 4 Using the ChipScope Pro Analyzer The ChipScope Pro Analyzer server and client can be running on the same machine local host mode or on different machines remote mode Remote mode is useful in the following situations e You need to debug a system that is in a different location e You need to share a single system resource with other team members e You need to demonstrate a problem or feature to someone who is not at your location Remote mode is available on all operating systems as shown in Table 4 1 page 4 1 Analyzer Server Interface The ChipScope Pro Analyzer server command line application is available on Windows and Linux operating systems as shown in Table 4 1 page 4 1 If you desire to debug a target system that is connected directly to your local machine via a JTAG download cable then you do not need to start the server ma
21. 8 1x 7 2 097 120 1 048 560 200 MHz 8 2x 13 1 048 560 524 280 100 MHz 8 4x 27 524 280 262 136 50 MHz 12 1x 11 2 097 120 1 048 560 200 MHz 12 2x 21 1 048 560 524 280 100 MHz 12 4x 43 524 280 262 136 50 MHz 16 1x 15 2 097 120 1 048 560 200 MHz 16 2x 29 1 048 560 524 280 100 MHz 16 4x 59 524 280 262 136 50 MHz 20 1x 19 2 097 120 1 048 560 200 MHz 20 2x 37 1 048 560 524 280 100 MHz 20 4x 75 524 280 262 136 50 MHz a The maximum clock pin frequency is always 200 MHz but may differ from the CLK port frequency depending on the transmit rate The external data and clock pins of the ILA ATC core are connected to the Agilent TPA using a special 38 pin MICTOR connector Both the Agilent TPA and the special connector are described in the companion Agilent document called Deep Storage with Xilinx ChipScope Pro and Agilent Technologies FPGA Trace Port Analyzer which is available for download at http www xilinx com ise verification cspro_agilent_brochure pdf ILA ATC Control and Status Logic The ILA contains a modest amount of control and status logic that is used to maintain the normal operation of the core All logic necessary to properly identify and communicate with the ILA core is implemented by this control and status logic ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 1 13 lt XILINX Chapter 1 Introduction IBA OPB Core Th
22. Choosing the File Destination isses 2 8 Selecting the Target Device Family eseeeeeeeeeeee eee 2 8 WISIN SRET OS M re 2 9 Using RPMS 31 dae thea ii bee e e et a 2 9 Selecting the Clock Edge sese ee etm Sow nus MEE hd mee eh we ee 2 9 ILA Core Trigger Port Options ssssssssse ccc eee eee ees 2 9 Selecting the Number of Trigger Ports 2 0 0 ce ne 2 10 Entering the Width of the Trigger Ports 0 0 eee cece ee 2 10 Selecting the Number of Trigger Match Units 0 0 c cee cee eee 2 10 Selecting the Match Unit Type c l nnn 2 11 Selecting Match Unit Counter Width ocooccoococcoocconcco eens 2 12 Enabling the Trigger Condition Sequencer 2 6 cee eee 2 12 Enabling the Storage Qualification Condition oo ooocoocooconcoorooooo 2 12 Enabling the Trigger Output Port cesses nnn 2 12 ILA Core Data Port Options isses eee e ee hh ed ers 2 13 Selecting the Data Depth s isi etsitu da LE da di 2 14 Selecting the Data Type eter e heme e haee ace a ee eee dh eoa 2 15 Entering the Data Width sita e oca cui Cte Rd Pe eR Cd aee ee 2 15 Selecting the Data Same As Trigger Ports 0 6 eee cee ene 2 15 Number of Block RAMS 0 cc erras 2 16 Creating Example Templates 2 2 oc eens 2 16 HDL Example Files aeo Gah doe eae Re eee baee gaa id eg 2 16 Bus Signal Name Example Files cdc 0 0 occ eens 2 17 Batch Mode Generation Argument Example Files
23. If the Analyzer returns the error message Failed to Open Communication Port verify that the cable is connected to the correct LPT port If you have not installed the Parallel Cable driver follow the instructions in the ChipScope Pro Software installation program to install the required device driver software ChipScope Pro Analyzer sacfdemo2 Parallel Cable Selection El ChipScope Pro Analyzer sacfdemo2 File View JTAG Chain Device D Xilinx Parallel Ill Server Host Setting D Xilinx Parallel IV Project sac 9 UNN Xilinx Parallel Cable O Xilinx MultiLINX Serial Cable UNIT Xilinx MultiLINX USB Cable A Xilinx Platform USB Cable 8 Auto Detect Cable Type Parallel Cable Parameters Speed Port 5 MHz y eri Figure 4 17 Opening a Parallel Cable Connection ChipScope Pro Software and Cores User Guide www xilinx com 4 17 UGO029 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Opening an Agilent E5904B Cable Connection To connect to the Agilent E5904B cable make sure it has been properly configured beforehand with a valid IP address sub net mask gateway etc To open a connection select JTAG Chain Agilent E5904B Cable This will bring up the Agilent E5904B Cable Options dialog box Figure 4 18 The Host IP is the IP address of the cable To properly configure the IP address of the Agilent cable
24. The match counter will not be included on each match unit if the Counter Width combo box is set to Disabled The default Counter Width setting is Disabled Enabling the Trigger Condition Sequencer The trigger condition sequencer can be either a Boolean equation or an optional trigger sequencer that is enabled by checking the Enable Trigger Sequencer checkbox A block diagram of the trigger sequencer is shown in Figure 2 8 page 2 12 The trigger sequencer is implemented as a simple cyclical state machine and can transition through up to 16 states or levels before the trigger condition is satisfied The transition from one level to the next is caused by an event on one of the match units that is connected to the trigger sequencer Any match unit can be selected at run time on a per level basis to transition from one level to the next The trigger sequencer can also be configured at run time to transition from one level to the next on either contiguous or non contiguous sequences of match function events Enabling the Storage Qualification Condition In addition to the trigger condition the IBA OPB core can also implement a storage qualification condition The storage qualification condition is a Boolean combination of match function events These match function events are detected by the match unit comparators that are subsequently attached to the trigger ports of the core The storage qualification condition differs from the trigger condition i
25. Trigger Marks The data sample in the sample window that coincides with a trigger event is tagged with a trigger mark This trigger mark tells the ChipScope Pro Analyzer the position of the trigger within the window This trigger mark consumes one extra bit per sample in the sample buffer Data Port The ILA core provides the capability to capture data on a port that is separate from the trigger ports that are used to perform trigger functions This feature is useful for limiting the amount of data to be captured to a relatively small amount since itis not always useful to capture and view the same information that is used to trigger the core However in many cases it is useful to capture and view the same data that is used to trigger the core In this case you can choose for the data to consist of one or more of the trigger ports This feature allows you to conserve resources while providing the flexibility to choose what trigger information is interesting enough to capture ILA Control and Status Logic The ILA contains a modest amount of control and status logic that is used to maintain the normal operation of the core All logic necessary to properly identify and communicate with the ILA core is implemented by this control and status logic ILA ATC Core The ILA ATC core is a customizable logic analyzer core that is very similar to the ILA core with the exception that it does not use on chip block RAM resources to store captured trace
26. ccc ce ehh ras 2 26 Output Buffer Type spirit eee ie C94 rv ET Vee eV NGS SA Peek EE 2 26 Output Clock and Data Pin Locations s s eee eee ene 2 27 Data Width and Depth s eese poet cs LE da ated ee eee 2 27 Creating Example Templates 2 0 6 6 eee eee 2 28 HDL Example Files uu asas ERE eek FX REA RY ee He pae 2 28 Bus Signal Name Example Files cdc 0 6 ce eee ene 2 28 Batch Mode Generation Argument Example Files lees 2 29 Generating the Core iiiis cias e bk ag ep ba b cere dake Ee aS 2 29 Using the ILA ATC Core re RR err eR Re e aa ke c Peay 2 29 Generating the IBA OPB Core suse ee 2 30 General IBA OPB Core Options s na su nsnn nnr r nr rr e nn 2 31 Choosing the File Destination cies en 2 31 Selecting the Target Device Family o oooccoccoococconcorcr eens 2 31 Using RETOS 5 pde RE Rt op at 2 31 Usina RPMS eren tae o redde iacere bae e dee ba ess 2 32 Selecting the Clock Edge eode eive e pet rece Er eee pct dece 2 32 Selecting the OPB Bus Settings 6 rd ai nen 2 32 IBA OPB Core Trigger Port Options 66 2 34 Selecting the OPB Signal Groups as Trigger Ports 0 0 6 cee eee eee 2 35 Entering the Width of the Trigger Ports 2 36 Selecting the Number of Trigger Match Units sees 2 36 Selecting the Match Unit Type 6 0 ce nn 2 37 Selecting Match Unit Counter Width cesses ee 2 38 Enabling the Trigger Condition Sequencer
27. diagram of the trigger sequencer is shown in Figure 2 8 page 2 12 The trigger sequencer is implemented as a simple cyclical state machine and can transition through up to 16 states or levels before the trigger condition is satisfied The transition from one level to the next is caused by an event on one of the match units that are connected to the trigger sequencer Any match unit can be selected at run time on a per level basis to transition from one level to the next The trigger sequencer can be configured atrun time to transition from one level to the next on either contiguous or non contiguous sequences of match function events Enabling the Trigger Output Port The output of the ILA ATC trigger condition module can be brought out to a port signal by checking the Enable Trigger Output Port checkbox The trigger output port is used to trigger external test equipment by attaching the port signal to a device pin in the HDL design The trigger output port can also be attached to other logic or ChipScope Pro cores in the design to be used as a trigger an interrupt or another control signal The shape level or pulse and sense active high or low of the trigger output can also be controlled at run time The clock latency of the ILA ATC trigger output port is 10 clock CLK cycles with respect to the trigger input ports 2 24 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC
28. e PLB Mn Busy e PLB Mn Err e PLB_MnRdDAck e PLB MnRdWdAddr 0 e PLB_MnRdWdAddr 1 e PLB MnRdWdAddr 2 e PLB MnRdWdAddr 3 e PLB_MnRearbitrate e PLB_MnSSize 0 e PLB_MnSSize 1 e PLB Mn WrDAck e Mn_abort e Mn BE 0 e Mn BE 1 e Mn BE 2 e Mn BE 3 e Mn BE 4 e Mn BE 5 e Mn BE 6 e Mn BE 7 e Mn busLock e Mn MSize 0 e Mn MSize 1 e Mn priority 0 e Mn priority 1 Mn request e Mn RNW e Mn size 0 e Mn size 1 e Mn size 2 e Mn size 3 where n is the master number 0 to 15 1 20 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX Table 1 8 PLB Signal Groups Continued Trigger Group Name PLB_SEm_CTRL 12 PLB control signals slave rri including e Slm_addrAck e Slm_rdDAck e Slm_rdWdAddr 0 e SIm rdWdAddr 1 e SIm rdWdAddr 2 e Slm_rdWdAddr 3 e Slm_rearbitrate e Slm_SSize 0 e Slm_SSize 1 e SIm wait Width Description uN e Slm_wrComp e SIm wrDAck where m is the slave number 0 to 15 TRIG IN User defined Generic trigger input IBA PLB Trigger Output Logic The IBA OPB core implements a trigger output port called TRIG OUT The TRIG OUT portis the output of the trigger condition that is set up at run time using the ChipScope Pro Analyzer The latency of the TRIG OUT port relative to the input trigger ports is 10 clock cycles The T
29. purposes the unused USER port signals are available for use by other design elements respectively If the Boundary Scan component is instantiated inside the ICON core then selecting the Include Boundary Scan Ports checkbox provides access to the unused USER scan chain interfaces of the Boundary Scan component Note The Boundary Scan ports should be included only if the design needs them If they are included and not used some synthesis tools do not connect the ICON core properly causing errors during the synthesis and implementation stages of development 2 4 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ICON Core 7 XILINX Creating Example Templates After selecting the parameters for the ICON core click Next to view the Example and Template Options Figure 2 3 e ChipScope Pro Core Generator ICON Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL x Synthesis Tool Xilinx XST Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg lt Previous I Generate Core Figure 2 3 Icon Core Example and Template Options HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported
30. template for the various synthesis tools To generate the ILA ATC core without any HDL example files deselect the Generate HDL Example File checkbox Bus Signal Name Example Files cdc The bus signal name example file for the ILA ATC core for example ila atc cdc contains generic information about the trigger and data ports of the ILA ATC core The ila atc cdc file will be created if you select the Generate Bus Signal Name Example File cdc checkbox You can use the ila atc cdc file as a template to change trigger and or data port signal names create buses and so on The modified ila_atc cdc file can then be imported into the ChipScope Pro Analyzer tool and applied to the appropriate ILA ATC core by using the File Import option 2 28 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC Core 7 XILINX Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example ila_atc arg by selecting the Generate Batch Mode Argument Example File arg checkbox The ila_atc arg file is used with the command line program called generate The ila atc arg file contains all of the arguments necessary for generating the ILA ATC core without having to use the ChipScope Pro Core Generator GUI tool Note An ILA ATC core can be generated by running generate exe ila pro atc f ila atc arg atthe command prompt on Windows syst
31. the capture buffer will not be downloaded from the device and displayed in any of the data viewer s until the Auto Core Status Poll option is turned on again Configuring the Target Device s You can use the ChipScope Pro Analyzer software with one or more valid target devices The first step is to set up all of the devices in the Boundary Scan chain Setting Up the Boundary Scan JTAG Chain After the Analyzer has successfully communicated with a download cable it automatically queries the Boundary Scan JTAG chain to find its composition All Xilinx Virtex E II II Pro 4 Spartan II IIE 3 3E XL 9500 XL XV 4000XL XLA 18V00 Platform FLASH PROMs CoolRunner CoolRunner II and System ACE devices are automatically detected The entire IDCODE can be verified for valid target devices To view the chain composition select JTAG Chain JTAG Chain Setup A dialog box appears with all detected devices in order For devices that are not automatically detected you must specify the IR Instruction Register length to insure proper communication to the ChipScope Pro cores This information can be found in the device s BSDL file The following example has one System ACE CompactFlash controller device System ACE one serial PROMs XC18V00 and one Virtex II Pro device XC2VP4 in a chain Figure 4 21 USERCODEs can be read out of the ChipScope Pro target devices only the XC2VP4 device in this example by selecting Rea
32. the waveform Special drag icons will appear when the mouse pointer is over the cursor Sample Display Numbering The horizontal axis of the waveform can be displayed as the sample number relative to the sample window default or by the overall sample number in the buffer To display the sample number starting over at 0 for each window select Ruler gt Sample in Window in the right click menu To display the sample number as an overall sample count in the buffer select Ruler gt Sample in Buffer in the right click menu You can also select toggle the way that the samples that occur before the trigger marker are shown in the ruler either negative or positive by selecting Ruler Negative Time Samples in the right click menu ChipScope Pro Software and Cores User Guide www xilinx com 4 35 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Displaying Markers A static red vertical bar is displayed at each trigger position A static black bar is displayed between two windows to indicate a period of time where no samples were captured To not display either of these markers un check them on the right click menu under Markers Window Markers or Markers Trigger Markers Listing Window To view the Listing window for a particular ChipScope Pro ILA or IBA core select Window New Unit Windows and the ChipScope Pro core desired A dialog box will be displayed for that ChipScope Pro Unit
33. 00 0000 e eee 3 2 Figure 3 2 The cdc Source File oooooooocococconcoccncrrrrre no 3 2 Figure 3 3 Blank Core Inserter Project oooooocoocccccccccccccccccccc o 3 5 Figure 3 4 Core Inserter Project with Files Specified ooo o m omoo o 3 7 Figure 3 5 Core Inserter as Launched from Project Navigator 3 8 Figure 3 6 ICON Options 0 n 3 9 Figure 3 7 ILA Core Trigger Parameters 3 10 Figure 3 8 Trigger Sequencer Block Diagram with 16 Levels and 16 Match Units 3 12 Figure 3 9 ILA Core Capture Parameters 00 eee eee 3 13 Figure 3 10 ILA Core Data Same As Trigger Parameters 04 3 15 Figure 3 11 ILA ATC Core Data Settings 3 16 Figure 3 12 ATC2 Core STATE Mode Data Capture Settings 3 19 Figure 3 13 ATC2 Core TIMING Mode Data Capture SettingS 3 19 Figure 3 14 ILA and ILA ATC Net Connecti0nS o oooccccccccccccccccccc 3 23 Figure 3 15 ATC2 Net Connections slss ee 3 24 Figure 3 16 Select Net Dialog Box 00 6 ccc ene ees 3 25 Figure 3 17 Specifying Data Connections 000000 eee eee 3 27 Figure 3 18 Core Inserter Tools Preference Settings 0058 3 28 Figure 3 19 Core Inserter ISE Integration Preference SettingS 3 29 Figure 3 20 Core Inserter Miscellaneous Preference Settings 3 29 xviii www xilinx
34. 1 13 1 OPB xferAck OPB xferAck active with no Mx select 6 010110 1 13 2 OPB xferAck OPB xferAck did not activate within 16 cycles of OPB select 7 010111 1 15 1 OPB errAck OPB errAck active with no Mx select 8 000100 1 4 0 OPB retry OPB_retry and OPB_xferAck active in the same cycle 9 000111 1 4 3 OPB_retry OPB_retry active for more than a single cycle 10 000000 1 2 1 OPB MxCGrant More than 1 OPB_MxGrant signals active in same cycle 1 14 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX Table 1 6 CoreConnect OPB Protocol Violation Error Description Continued Priority Bit Encoding Error Description 11 000001 122 OPB_MxGrant An OPB MxGrant signal is active for a non owning master 12 000010 1 3 1 OPB_BusLock OPB_BusLock asserted without a grant in the previous cycle and without OPB select 13 000011 1 3 2 OPB_BusLock Bus is locked and a master other than bus owner has been granted the bus 14 001000 1 4 4 OPB_retry OPB_select remained active after a retry cycle 15 001001 1 4 5 OPB retry OPB_retry active with no Mx select 16 001110 1 8 1 OPB Select Mx Select signal active without having control of the bus via OPB MxGrant or OPB busLock 17 001111 1 8 2 OPB Select More than 1 Mx Select signals active in the same cycle 18 010000 1
35. 12 4x 43 524 280 262 136 16 1x 15 2 097 120 1 048 560 16 2x 29 1 048 560 524 280 16 4x 59 524 280 262 136 20 1x 19 2 097 120 1 048 560 20 2x 37 1 048 560 524 280 20 4x 75 524 280 262 136 ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 2 27 XILINX Chapter 2 Using the ChipScope Pro Core Generator Creating Example Templates After selecting the parameters for the ILA ATC core click Next to view the Example and Template Options Figure 2 17 e ChipScope Pro Core Generator ILA ATC Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL y Synthesis Tool X nxXST Bus Signal Name Example File Settings v Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg Figure 2 17 ILA ATC Core Example and Template Options HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation
36. 2 34 e ChipScope Pro Core Generator VIO General Options Design Files Output Netlist Wwio edn Browse Device Settings Device Family Virtex2 v Use SRL 16s Input Output Port Settings v Enable Asynchronous Input Port v Enable Asynchronous Output Port v Enable Synchronous Input Port v Enable Synchronous Output Port Clock Settings Sample On Rising w Edge Of Clock Previous Next gt Figure 2 84 VIO Core General Options Choosing the File Destination The destination for the VIO EDIF netlist vio edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the VIO core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan II Spartan IIE and Spartan 3 device families including the QPro variants of these families Virtex II is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Using SRL 16s
37. 2 of 3 Bus Signal mkcroPraglddr mkroProgfddr micraPragfiddr t mkroPraghddep mkroPraglddrp mkraPragfdirk mkcroPraghddds mkcroProagfddrg mkcroPragldd mkraPraghddep mkroPraglddrb eS microPariiddr a Ica amp 000 Cs _ONOCOO ISOS 20080008 0000806000008 0006 X AO OOOO a 0000000 20000008 X 00000000000000000000000000000 Iu f r m Mona miroParDaaln mikraPan Data mkraPatDatzO4 p n mkraPorDatOu l miraPonDatzO dp mkraPas Dau miroPotDatzO dk mkraPonDatzO4 5 mkeraPanDatzOu p mbraPanD3204 7 ji f IL nnn n nn m p nnn m miraReadStrabe 1 o o o 1 1 1 o o o 0 w o o o o o o o o 1 o taka Aa vane n dE TEE UPA reg Bust susu X CDOGOOCOODO0000000CO0000COO0000000COO0COO0000000000000 Back Send to PDE Send to Printer Figure 4 9 Expanding Buses in Print Wizard 2 of 3 Print Wizard 3 of 3 Window In the Print Wizard 2 of 3 window clicki
38. 3 and Spartan 3E device families including the OPro variants of these families you can set the data depth to one of six values Table 2 2 Table 2 2 Maximum Data Widths for Virtex ll Il Pro 4 Spartan 3 3E Depth Depth Depth Depth Depth Depth 512 1024 2048 4096 8192 16384 1 block RAM 31 15 7 3 1 2 block RAMs 63 31 15 7 3 1 4 block RAMs 127 63 31 15 7 3 8 block RAMs 255 127 63 31 15 7 16 block RAMs 255 127 63 31 15 32 block RAMs 255 127 63 31 64 block RAMs 255 127 63 128 block RAMs 255 127 256 block RAMs 255 Note One extra bit per sample is required for the trigger mark that is a trigger data width of 7 bits requires a full sample width of 8 bits etc For the Virtex Virtex E Spartan II and Spartan IIE device families including the QPro variants of these families you can set the data depth to one of five values Table 2 3 Table 2 3 Maximum Data Widths for Virtex E Spartan I1 I1E Depth Depth Depth Depth Depth 256 512 1024 2048 4096 1 block RAM 15 7 3 1 2 block RAMs 31 15 7 3 1 4 block RAMs 63 31 15 7 3 8 block RAMs 127 63 31 15 7 16 block RAMs 255 127 63 31 15 32 block RAMs 255 127 63 31 64 block RAMs 255 127 63 128 block RAMs 255 127 256 block RAMs 255 Note One extra bit per sample is required for the trig
39. 3 13 ATC2 Core TIMING Mode Data Capture Settings ChipScope Pro Software and Cores User Guide www xilinx com 3 19 UG029 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Capture Mode The Capture Mode setting of the ATC2 core can be set to either STATE mode Figure 3 12 page 3 19 for synchronous data capture to the CLK input signal or to TIMING mode Figure 3 13 page 3 19 for asynchronous data capture In STATE mode the data path through the ATC2 core uses pipeline flip flops that are clocked on the CLK input port signal In TIMING mode the data path through the ATC2 core is composed purely of combinational logic all the way to the output pins Also in TIMING mode the ATCK pin is used as an extra data pin Clock Edge The ATC2 unit can use either the rising or falling edges of the CLK signal to capture data and run the internal calibration logic The Clock Edge pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the ATC2 core Max Frequency Range The Max Frequency Range parameter is used to specify the maximum frequency range in which you expect to operate the ATC2 core The implementation of the ATC2 core will be optimized for the maximum frequency range selection The valid maximum frequency ranges are 0 100 MHz 101 250 MHz 251 300 MHz and 301 500 MHz The maximum frequency range selection only has an affect on core implementation
40. 38 Cursor Tracking ect ERR ERA RES TES PREX REESE ERN ones 4 38 ChipScope Pro Software and Cores User Guide www xilinx com xi UGO29 v7 1 February 16 2005 XILINX VIO Console Window 0 ccc ee enn hrs 4 39 Bus Signal Colm 1 9 20 33 40 E naw Paises A blew tae 4 40 Value Coltmitvs ium 0 era ier bue Ra ee eb questi e babe sau 4 41 Global Console Controls 0 0 cc eee has 4 43 Helpa ys sodes eats vex quo a een he ee belts eed pad ub Paquetes 4 43 Viewing the Help Pages i ecce need oh eed esas diene eae a 4 43 ChipScope Pro Main Toolbar Features 00 0 e cece eee eee 4 44 ChipScope Pro Analyzer Command Line Options 4 45 Optional Arguments tre bae Pee E ede ba eue e aerea ees 4 45 Windows Command Line Example esee e 4 45 Chapter 5 Tcl JTAG Interface DV CLV A ON 5 1 RRequirements 24 0 ber Uere e Ege ire eee Nu e der es bd eet ei s 5 1 lico CAM 5 1 Tcl JTAG Command Summaty 0000s 5 2 Command Details iussus e 5 3 RAS autodetect a cotes O DI M I UE DE A EE een sia 5 3 SyNtaXs CT OQ 5 3 Required ATSUImbenta s iit aaa es ductu qu be deed quee ed eed 5 3 Rets esu respe eaa Eee WE EIUS epi A ed e mre ss 5 3 EXAMPlE d rn 5 3 jtag close o setas dienen adorna sedere Ia beg ar 54 o cartes A 5 4 Required Arguments sere eres ved rp Na wee da Iur vp Er RE
41. A Xilinx Tcl shell xtclsh exe is provided in the Xilinx ISE 7 1i tool installation other non Xilinx Tcl shells are currently not supported and will not work with the Tcl JTAG interface e Make sure the dynamically linked library files 411 provided in this Tcl JTAG package are in your PATH environment variable or in the current working directory Limitations The Tcl JTAG interface package favors simplicity over performance Some commands suchas jtag shiftirand jtag shiftdr transfer bits as strings for example 0001000 instead of as packed binary data structures The extra overhead in converting particularly large data strings does result in some loss of performance however the simple design of the application programming interface API and the use of the Tcl scripting language makes Tcl JTAG an easy to use means to interact with devices in the JTAG chain Note Tcl JTAG is only compatible with software that uses the JTAGComm interface to the JTAG cable communication device such as the ChipScope Pro tool and the XMD tool that is part of the Xilinx Embedded Development Kit Tools such as Xilinx iMPACT do not use the JTAGComm interface and therefore are not compatible for use with Tcl JTAG scripts or programs ChipScope Pro Software and Cores User Guide www xilinx com 5 1 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface Tcl JTAG Command Summary A brief summary of the Tcl JTAG commands is shown in T
42. ATC Core Capabilities 0 eee eens 3 18 ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 XV XILINX Chapter 4 Using the ChipScope Pro Analyzer Table 4 1 Operating System Support for the ChipScope Pro Analyzer 4 1 Table 4 2 ChipScope Pro Analyzer Server Command Line Options 4 2 Chapter 5 Tcl JTAG Interface Table 5 1 Tcl JTAG Command Summaty 0 00 5 2 xvi www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Schedule of Figures Chapter 1 Introduction Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 ChipScope Pro System Block Diagram 000000 12 ChipScope Pro Tools Design FloW oooooooococcococooooo oo 1 4 LA Core Connection Example sse 1 8 ATC2 Core and System Block DiagraM oooooococcoccccoo ooo 1 23 Chapter 2 Using the ChipScope Pro Core Generator Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 2 17 Figure 2 18 Figure 2 19 Figure 2 20 Figure 2 21 Figure 2 22 Figure 2 23 Figure 2 24 Figure 2 25 Figure 2 26 Figure 2 27 Figure 2 28 Figure 2 29 Figure 2 30 Figure 2 31 Selecting the ICON Core 0 22 ICON Core Ge
43. All Waveform or Clear All gt Listing In the case of a VIO core to remove all the signals from the VIO console right click on any signal or bus and select Clear All Console Similarly all signals and buses can be added to the views through the Add All to View menu options Selected signals and buses can be added through the Add to View menu options To select a contiguous group of signals and buses click on the first signal hold down the Shift key and click on the last signal in the group To select a non contiguous group of signals and buses click on each of the signals buses in turn while holding down the Ctrl key When you use this method the order of the signals in the bus are in the order in which you select them Combining and Adding Signals Into Buses For ILA and IBA cores only data signals can be combined into buses For VIO cores signals of a particular type can be grouped together to form buses To combine signals into buses select the signals using the Shift or Ctrl keys as described above When the Shift key is used the uppermost signal in the tree will be the LSB once the bus is created If the Ctrl key is used the signals will be in ordered in the bus the same order that they are clicked the first signal being the LSB After you have selected the signals right click on any selected signal and select Add to Bus New Bus A new bus will be created at the top of the Data Signals and Buses sub tree in the
44. Analyzer for Processor Local Bus D MIO Virtual Input Output Core ATC2 Agilent Trace Core 2 Figure 2 5 Selecting the ILA Core ChipScope Pro Software and Cores User Guide www xilinx com 2 7 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator General ILA Core Options The second screen in the Core Generator is used to set up the of the general ILA core options Figure 2 6 e ChipScope Pro Core Generator ILA General Options Design Files Output Netlist ila edn Browse Device Settings Device Family Virtex2 y v Use SRL16s v Use RPMs Clock Settings Sample On Rising ly Edge Of Clock lt Previous s Next gt Figure 2 6 ILA Core General Options Choosing the File Destination The destination for the ILA EDIF netlist ila edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ILA core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan II Spartan IIE and Spartan 3 device
45. Argument Example File arg checkbox The iba_plb arg file is used with the command line program called generate The iba_plb arg file contains all of the arguments necessary for generating the IBA PLB core without having to use the ChipScope Pro Core Generator GUI tool Note An IBA PLB core can be generated by running generate exe iba plb f iba plb arg atthe command prompt on Windows systems or by running generate sh iba plb f iba plb arg atthe UNIX shell prompt on Linux and Solaris systems ChipScope Pro Software and Cores User Guide www xilinx com 2 55 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Generating the Core After entering the IBA PLB core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 32 You can select to either go back and specify different options or click Start Over to generate new cores e ChipScope Pro Core Generator Generate Generating Core Messages Extra Trigger input port disabled Extra Trigger input width 1 Number of CCPLB Masters 2 Number of CCPLB Slaves 4 Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinx ip iba plb iba plb Writing iba plb edn Post Processing EDIF netlist liba_plb edn Generating constrai
46. Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC Core 7 XILINX Using RPMs The ILA ATC core normally uses relationally placed macros RPMs to increase the performance of the core If the device family is Virtex II Virtex II Pro Virtex 4 or Spartan 3 including the QPro variants of these families the usage of RPMs by the ILA ATC core can be disabled by deselecting the Use RPMs checkbox It is recommended that the Use RPMs checkbox remain enabled for these device families Note RPMs cannot be used with the Virtex Virtex E Spartan ll or Spartan IIE device families including the QPro variants of these families Selecting the Clock Edge The ILA ATC unit can use either the rising or falling edges of the CLK signal to trigger and capture data The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the ILA ATC core ILA ATC Core Trigger Port Options After you have set up the general ILA ATC core options click Next This takes you to the third screen in the Core Generator that is used to set up the of the ILA ATC core trigger port options Figure 2 15 er ChipScope Pro Core Generator ILA with Agilent Trace Core Trigger Port Options Trigger Input and Match Unit Settings Number of Input Trigger Po 16 y Number of Match Units Used 16 Trigger Width 32 Match Type Basic wedges v Match Units 1 y Bi
47. Destination 6 6 ne 2 58 Selecting the Target Device Family eseeeeeeeeeee ee 2 58 Using SREI6S opt REA DEREN uaa peser punte aeu sae toties di eats 2 58 Selecting Input Output Port Settings 2 6 ee 2 59 Selecting the Clock Edge tii web gun led salts amete ede e Rute doe 2 59 Creating Example Templates 00 06 2 60 HDL Example Files aia eR RR Ee xor er a ERR 2 60 Batch Mode Generation Argument Example Files 2 61 Generating the Cote s eee eges ee etie Sutra he eleg PRSE ees qst ine 2 61 Using the VIO Core sie HE dene HH E e p HERR Ee C Hie es 2 61 Generating the ATC2 COTE onsirra ria ii 2 62 General ATC2 Core Options gedio nera DEE EA rr 2 63 Choosing the File Destination cies e 2 63 Selecting the Target Device Family llle ne 2 63 Selecting the Clock Edge co bed rede aa BETA ERES EA 2 63 viii www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 7 XILINX ATC2 Core Data Options oooocccocococconcncccnnnccnnnnnnnn a E A 2 64 Capture Modes eto a tado dee Pubs d ce Paises tee lace sae da 2 65 Signal Bank Count sesser eass ke a ERA AEN EE Pei gere e 2 65 Driver Endpoint Type iid xb Epp t bx dei es obe cele eee eaa 2 65 TDM Rale sa eva oe Eee VPE ID DRE adt eee eed pde de es 2 65 ATD Pin Counts eec ieee cece pede gees ae dos a ee ead 2 65 Data Port Width deed eed tt hated eras d bee eerte adr aed 2 65 Max Frequency Range rita
48. F Resource Utilization BlockRAMs used 3 lessages Successfully read project c projectsimy_designiiseimy_design cdc Netlist timestamp changed rebuilding design copy ciprojectsimy_designtiselmy_design_cs nge gt ciprojectsimy designlsel ngoimy design cs signalbrowser ngo SetDesign my design 4 Figure 3 9 ILA Core Capture Parameters ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 3 13 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Selecting the Data Depth The maximum number of data sample words that the ILA core can store in the sample buffer is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit For the Virtex II Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E device families including the OPro variants of these families you can set the data depth to one of six values Table 3 2 Table 3 2 Maximum Data Widths for Virtex ll Il Pro 4 Spartan 3 3E Depth Depth Depth Depth Depth Depth 512 1024 2048 4096 8192 16384 1 block RAM 31 15 7 3 1 2 block RAMs 63 31 15 7 3 1 4 block RAMs 127 63 31 15 7 3 8 block RAMs 255 127 63 31 15 7 16 block RAMs 255 127 63 31 15 32 block RAMs 255 127 63 31 64 block RAMs 255 127 63 128 block RAMs 255 127 256 block RAM
49. Figure 4 13 Blank Signal Import Dialog Box To select the signal import file select Select New File A file dialog box will appear for you to navigate and specify the signal import file After you choose the file the Unit Device combo box will be populated according to the core types specified in the signal import file If the signal import file contains signal names for more than one core the combo box will contain device numbers for all devices that contain only ChipScope Pro capture cores If the signal import file contains signal names for only one core the combo box will be populated with names of the individual cores that match the type specified in the signal import file If the import file is a file from Synplicity Certify you will also have the option of choosing a device name from the Certify file as well as the device in the JTAG chain To import the signal names click OK If the parameters in the file do not match the parameters of the target core or cores a warning message will be displayed If you choose to proceed the signal names will be applied to the cores as applicable 4 14 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Exporting Data Captured data from an ILA or IBA core can be exported to a file for future viewing or processing To export data select File Export The Export Signals dialog box appears Figure 4 14 Expo
50. IDCODE for each device that supports it Typical users do not need to call this function Instead call the jtag_autodetect function Side effects This navigates to test logic reset to obtain IDCODEs from devices that support the idcode command The device count is set to the number of devices found in the chain Required Arguments All arguments are passed directly to the cable driver handle Handle to the cable connection Returns List of device IDCODEs 0 when not supported for each device in the chain Examples 1 Capture list of IDCODEs into variable idcode list set idcode list jtag scanchain handle 5 16 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX jtag_unlock This command is used to release an exclusive lock on a cable resource Required Arguments handle Handle to the cable connection Returns 1 success O failure Example 1 Attempt to release lock on handle jtag_unlock handle ChipScope Pro Software and Cores User Guide www xilinx com 5 17 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag version This command is used to get the current Tcl JTAG API version Returns Current version of the package Example 1 Get current Tcl JTAG version set current version jtag version 5 18 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16
51. Lee EV ute 5 4 R t trn cocseeexe ERE ae Save A er det ee ra E Rus 5 4 ID curd O new a 5 4 jtag devicecOUriE ca eoi erect a Cie seen opta teda orte qme deese eet ee 5 5 Synta cvs ree Cie eS ade T Bde Men Eus 5 5 Required Areuments zone erro A ted a tib d tr ua 5 5 Optional Arguments exedcteeee coa bec qp ee oe IAN ETT ERE FEE 5 5 RUTIS Li ue bae g back uie PE dos CRURA CORR COUR ERU c Re 5 5 Examples cir e er Meee eae eee dde o kd bou e e e and 5 5 a E 5 6 dc KT E 5 6 Required Arsuments iui aca tad Sante a ee dotes a bed UTE doe doe Pads 5 6 Optional Arguments sui opa Soak ee li Edd Ei ba 5 6 RUINS os eet ux RR EE Ee aT AE SUPR T E Ge RP TUE RA E E 5 6 Examples c PC 5 6 jtag LOCK cocos sed eet E eh ae dpt cce 5 7 Synt X cue vis hove ay eek are en PEDE ud seid gu dct ee btc Vans 5 7 Required Arsuments 42 05 tera d erp bs d pO Icd t deu E ri 5 7 Optional Arguments esie ses ce nea rtorras eu er Ew eae rete tends 5 7 REUS ri A A GE RE RR EU e ERES GR ec e UR 5 7 Example vc avs bia x E ERREUR A oe ess 5 7 Jtag navigate uia Reed ROCHE ER need ones PONE M REI S e a PR a 5 8 Sainte errada ev pq oret dip round 5 8 Required ATSUmbentsi id Parte deo Vea ege rated b ete ea docete ata 5 8 Optional Arguments 0 234 cy cv vee la pepe eR bue a ans 5 8 REUS 5 eese ERE RE E A Eden Y eed C CEP Ea 5 8 Exaniples u dede re Rer ea i ease ES red eritque ires ea
52. Monitor Number of OPB Slaves 4 v lt Previous Figure 2 20 IBA OPB Core General Options Choosing the File Destination The destination for the IBA OPB EDIF netlist iba opb edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the IBA OPB core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex IL Virtex II Pro Virtex 4 Spartan II Spartan IIE and Spartan 3 device families including the QPro variants of these families Virtex II Pro is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Using SRL 16s The IBA OPB core normally uses the SRL16 feature of the FPGA device to increase performance and decrease the area used by the core If the device family is Virtex IL Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the QPro variants of these families the usage of SRL16s by the IBA OPB core can be disabled by deselecting the Use SRL16s checkbo
53. PLB read data bus from slaves PLB WRDBUS 64 PLB write data bus to slaves ChipScope Pro Software and Cores User Guide www xilinx com 2 47 UGO29 v7 1 February 16 2005 lt XILINX 2 48 Chapter 2 Using the ChipScope Pro Core Generator Table 2 11 PLB Signal Groups Continued Trigger Group Name PLB Mn CTRL Width 32 Description PLB control signals for master n including e PLB_MnAddrAck e PLB_Mn_Busy e PLB_Mn_Err e PLB MnRdDAck e PLB MnRdWdAddr 0 e PLB_MnRdWdAddr 1 e PLB_MnRdWdAddr 2 e PLB_MnRdWdAddr 3 e PLB_MnRearbitrate e PLB MnSSize 0 e PLB MnSSize 1 e PLB Mn WrDAck e Mn abort e Mn BE 0 e Mn BE 1 e Mn BE 2 e Mn BE 3 e Mn BE 4 e Mn BE 5 e Mn BE 6 e Mn BE 7 e Mn busLock e Mn MSize 0 e Mn MSize 1 e Mn priority 0 e Mn priority 1 e Mn request e Mn RNW e Mn_size 0 e Mn size 1 e Mn size 2 e Mn size 3 no where n is the master number 0 to 15 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA PLB Core XILINX Table 2 11 PLB Signal Groups Continued Trigger Group Name Width Description PLB SLm CTRL 12 PLB control signals slave m including e Slm_addrAck e Slm_rdDAck e Slm_rdWdAddr 0 e Slm_rdWdAddr 1 e Slm_rdWdAddr 2 e Slm_rdWdAddr 3 e Slm_rearbitrate e Slm_SSize 0 e Slm_SSize 1 e Sim wait uN e Slm_wrComp e Slm_wrDAck w
54. Selections pane respectively Nets that are selected at a given level of hierarchy can be connected to inputs of the ILA ILA ATC or ATC2 capture cores by following these steps 1 In the lower left table of the Select Net dialog box select the net s that you want to connect to the capture core Note You can select multiple nets to connect to an equivalent number of capture core input connections Hold down the Shift key and use the left mouse button to select contiguous nets Use a combination of the Ctrl key and left mouse button to select non contiguous nets You can also connect a single net to multiple capture core input signals by selecting a single net and multiple capture core port signals 2 Inthe upper right tabbed panel of the Select Net dialog box select the desired capture core input category Clock Signals Trigger Signals trigger port tab if applicable Data Signals or Trigger Data Signals if trigger is same as data 3 In the right hand table of capture core inputs select the channel s that you want to connect to the selected net s Note You can select multiple capture core inputs to connect to an equivalent number of nets Hold down the Shift key and use the left mouse button to select contiguous ILA core inputs Use a combination of the Ctrl key and left mouse button to select non contiguous ILA core inputs You can also connect a single net to multiple capture core input signals by selecting a single net and mu
55. Yes LVTIL 3 3V 12mA Fast Yes Yes Yes LVCMOS 3 3V 24mA Fast Yes No No LVCMOS 3 3V 12mA Fast Yes No No LVCMOS 2 5V 24mA Fast Yes No No LVCMOS 2 5V 12mA Fast Yes Yes Yes LVCMOS 1 8V 16mA Fast Yes No No LVCMOS 1 8V 12mA Fast Yes Yes No LVDCI 3 3V Yes No No LVDCI 2 5V Yes No No LVDCI 1 8V Yes No No ChipScope Pro Software and Cores User Guide www xilinx com 3 17 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Number of Data Pins The ILA ATC core can use 4 8 12 16 or 20 output data pins for external capture Output Clock and Data Pin Locations The clock and data pins are instantiated inside the ILA ATC core for your convenience This means that although you do not have to manually bring the clock and data pins through every level of hierarchy to the top level of your design you do need to specify the location of these pins in the Core Generator The pin locations are then added to the ncf file of the ILA ATC core Data Width and Depth The data width and depth of the ILA ATC core depend on the transmit rate and the number of data pins Table 3 6 Table 3 6 ILA ATC Core Capabilities Number of Transmit Max Width of Max DATA Depth Data Pins Rate DATA Port with timestamps 4 1x 3 2 097 120 1 048 560 4 2x 5 1 048 560 1048560 4 4x 11 524 280 262 136 8 1x 7 2 097 120 1 048 560 8 2x 13 1 048 560 524 280
56. a in range not range of values and transition in range detection are important a Bit values 0 means logical 0 1 means logical 1 X means don t care R means 0 to 1 transition F means 1 to 0 transition and B means any transition b The Bits Per Slice value is only an approximation that is used to illustrate the relative resource utilization of the different match unit types It should not be used as a hard estimate of resource utilization Use the TRIGn Match Type pull down list to select the type of match unit that will apply to all match units connected to the trigger port However as the functionality of the match unit increases so does the amount of resources necessary to implement that functionality This flexibility allows you to customize the functionality of the trigger module while keeping resource usage in check 2 50 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA PLB Core XILINX Selecting Match Unit Counter Width The match unit counter is a configurable counter on the output of the each match unit in a trigger port This counter can be configured at run time to count a specific number of match unit events To include a match counter on each match unit in the trigger port select a counter width from 1 to 32 The match counter will not be included
57. after entering the stable state default is 0 Returns 1 success 0 failure when the state parameter is provided Current state when the state parameter is not provided Examples 1 Tonavigate to run test idle and clock 15 times jtag navigate handle RTI 15 2 If no state is provided return the current tap state puts Current state is jtag navigate handle 5 8 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX jtag_open This command is used to open a cable connection and returns a handle to the opened cable This handle is used by all other Tcl JTAG commands to access the JTAG cable functions The jtag_open command may be called with optional parameters to set up specific JTAG cable options Syntax jtag open type port frequency Optional Arguments Set of parameters for the JTAG cable These are passed directly to the cable driver Xilinx Plattorm Cable USB Arguments type Cable type for Xilinx Platform Cable USB is xilinx platformusb port USB port identifier such as usb1 usb2 and so on frequency TCK clock frequency in Hz 750000 1500000 3000000 6000000 12000000 24000000 default is 5000000 Xilinx Parallel Cable IV and MultiPRO Arguments type Cable type for Xilinx Parallel Cable IV and MultiPRO is x ilinx parallel4 port Parallel port identifier such as 1pt1 1pt2 and so on frequency TCK clock freque
58. and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data is captured In the ILA core example shown in Figure 1 3 suppose you want to do the following e Trigger on the first memory write cycle CE rising edge WE 1 OE 0 to Address OxFF0000 e Capture only memory read cycles CE rising edge WE 0 OE 1 from Address Ox23A ACC where the Data values are between 0x00000000 and 0x1000FFFF To implement these conditions successfully you would need to make sure that both the TRIGO and TRIGI trigger ports each have two match units attached to them one for the trigger condition and one for the storage qualification condition Here is how you would set up the trigger and storage qualification equations and each individual match unit to satisfy the conditions above e Trigger Condition MO amp amp M2 where MO 2 0 CE WE OE R10 where R means rising edge M2 23 0 Address FF0000 e Storage Qualification Condition M1 amp amp M3 amp amp M4 where M1 2 0 CE WE OE R10 where R means rising edge M3 23 0 Address 23AACC M4 31 0 Data in the range of 0x00000000 through 0x1000FFFF The triggering and storage qualification capabilities of the ILA IBA OPB and IBA PLB cores allow you to locate and capture exactly the information that you want without w
59. and trigger ports are identical This mode is very common in most logic analyzers since you can capture and collect any data that is used to trigger the core Individual trigger ports can be selected to be included in the data port If this selection is made then the DATA input port will not be included in the port map of the ILA core This mode conserves CLB and routing resources in the ILA core but is limited to a maximum aggregate data sample word width of 256 bits ChipScope Pro Core Inserter my design cdc File Edit Help E a o ILA Select Integrated Logic Analyzer Options Trigger Parameters Capture Parameters Net Connections Capture Settings Data Depth 1024 E Samples Sample On Rising w Clock Edge v Data Same As Trigger Trigger Ports Used As Data v Include TRIGO Port width 8 v Include TRIG1 Port width 16 v Include TRIG2 Port width 16 v Include TRIG3 Port width 1 Resource Utilization BlockRAMs used 3 Say Remove Unit Successfully read project ciprojectsimy design seWwny design cdc Netlist timestamp changed rebuilding design copy ciprojectsimy_desigmliselmy_design_cs ngc gt ciprojectsimy designise ngowny design cs signalbrowser ngo SetDesign my design 1 Figure 3 10 ILA Core Data Same As Trigger Parameters Selecting the Data Same As Trigger Ports If the Data Same As Trigger checkbox is selected
60. case of ILA and IBA cores or at the top of that particular sub tree in the case of VIO To add a signal or signals into an existing bus select the signals and select Add to Bus and then the bus name in the following submenu Added signals always go on the MSB end of the bus Reverse Bus Ordering To reverse the order of the bits in a bus i e make the LSB the MSB right click on the bus and select Reverse Bus Order The signal browser and all data views that contain that bus will be immediately updated and the bus values recalculated 4 4 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Client Interface 7 XILINX Bus Radices Each bus can be displayed in the data views in any one of the following radices e ASCI e Binary e Hexadecimal e Octal e Signed decimal e Token e Unsigned decimal ASCII is only available if the number of bits in the bus is evenly divisible by 8 Changing the radix will change the bus radix in every data view it is resident Signed and Unsigned When either signed or unsigned is chosen as a bus radix a small dialog box appears for you to enter three additional parameters scale factor offset and precision e Scale factor is a multiplier value to use when calculating bus values For instance if the LSB of a 4 bit bus is 0010 and the scale factor is set to 2 0 the actual displayed bus value will be 4 given a precision of 0 If t
61. chain If discard option is specified nothing is returned 5 12 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Command Details XILINX Examples 1 Shift the BYPASS instruction into device 2 jtag shiftir handle constant 1 bitcount 6 device 2 discard 2 Shift USERCODE instruction into chain end in TLR and capture last instruction set oldir jtag shiftir handle buffer 000100 endstate TLR ChipScope Pro Software and Cores User Guide www xilinx com 5 13 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag shiftdr This command is used to shift bits into the specified device s data register Syntax jtag shiftdr handle I constant 0 1 bitcount count buffer buffer endstate state device devicenumber discard Required Arguments All arguments are passed directly to the cable driver handle Handle to the cable connection constant 0 1 Shift in a constant 0 or constant 1 Only required if buffer is not specified bitcount count Number of bits to shift Only required if buffer is not specified If buffer is specified the bitcount is automatically computed buffer buffer buffer is a binary string of bits Buffer to shift in to TDI Format is a string consisting of 0 s and 1 s like 1100101 Only required if constant is not specified Note Bits are shifted LSB gt MSB in the order of th
62. characters Valid characters for the different radices are e Hex X 0 9 and A F X indicates that all four bits of that nibble are don t cares A indicates that the nibble consists of a mixture of 1 s 0 s X s R s F s and B s where appropriate e Octal X 0 7 e Binary X don t care 0 1 R rising F falling and B either transition R F and B are only available if the match unit can detect transitions Basic w edges Extended w edges Range w edges e Unsigned 0 9 0 to 2 1 for an n bit bus e Signed 0 9 27 1 to 271 1 for an n bit bus Also when Bin is chosen as the radix positioning the mouse pointer over a specific character will display a tool tip indicating the name and position of that bit 4 28 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Radix The Radix combo box selects which radix to display in the Value field Values are Hex Octal Bin Signed not allowed for In Range and Out of Range comparisons and Unsigned Counter The Counter field selects how many match function events must occur for the function to be satisfied If the match counter is present for a particular match unit the text in the Counter column will be in black text If the counter is not present in the core the text in that column will be grayed out To change the value of the match counter click on the counter cell w
63. ciere qe ebbe beverage 2 65 Enable Auto Setup xi edere rM RR EPA eeu rg reU x ee EE e be 2 66 Enable Always On Mode rA erkb eee epe PX tiri AAA AAA 2 66 Pin Edit Mode use REIR RAM ed en hee eee eo ed 2 66 Pin Parameters 4 eek eek REG EEG EE E ni EE E d 2 66 Core Utilization a seio A A A E xus ere 2 67 Creating ATC2 Example Templates oooooooccococorococonnnrroac 2 67 HDL Example Files eie ek IE ere as FEAR bed e n 2 67 Bus Signal Name Example Files cdc 0 0 cc eee ees 2 69 Batch Mode Generation Argument Example Files lese 2 69 Generating the Core sssr isso dee da e dace a das a ace haie e per er RR 2 69 Using the ATC2 Cot eese me rk E RE RE dee p HRS stage ste RE 2 70 Chapter 3 Using the ChipScope Pro Core Inserter Gore Inserter Overview i ss0 0s il RR eI edd eee edt dare d EE Ei RbXY s 3 1 Using the Core Inserter with ISE Project Navigator ssuuuuuuse 3 1 ChipScope Definition and Connection Source File 3 1 Useful Project Navigator Settings isses en 3 3 Using the Core Inserter with Command Line Implementation 3 4 ChipScope Pro Core Inserter Features 0 00 cece eee eee eee 3 5 Working with Projects ct wis Y eres EE ELE ra n E eie ope Va E E ea Pda 3 5 Opening an Existing Project seo Linie bh hee re e eade bia gees 3 5 Saving Projects ederet oe A Dd darti dee e Ee eene 3 5 Refreshing the Netlist esee 9 tos poete he gue org eee Re
64. clock resources for example BUFG or DCM components Creating ATC2 Example Templates After selecting the data capture parameters for the ATC2 core click Next to view the Example and Template Generation Options Figure 2 41 ChipScope Pro Core Generator BEE ATC2 Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL y Synthesis Tool Xilinx XST Bus Signal Name Example File Settings v Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg Figure 2 41 ATC2 Core Example and Template Options HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are ChipScope Pro Software and Cores User Guide www xilinx com 2 67 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the ATC2 core without any HDL example files deselect the Generate HDL Example File checkbox 2 68 www
65. com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Figure 4 21 Figure 4 22 Figure 4 23 Figure 4 24 Figure 4 25 Figure 4 26 Figure 4 27 Figure 4 28 Figure 4 29 Figure 4 30 Figure 4 31 Figure 4 32 Figure 4 33 Figure 4 34 Figure 4 35 Figure 4 36 Figure 4 37 Figure 4 38 Figure 4 39 Figure 4 40 Figure 4 41 Figure 4 42 Example Token File e crcr eneren i ei en a e ee 4 5 Example Waveform with Tokens 0 0 000000 e eee eee 4 6 Saving d Project isses eye e ok cee eer Cete ee aah oe ae e ets 4 7 Example Waveform sisse et Res Ree hd e eene s 4 8 Selecting the File Print Option 4 8 Print Wizard Lof 3 cios et ReREIE Y case E ES 4 9 Waveform Printout Footer Example ssssssseeseeeeeee 4 10 Print Wizard 20 3 sisse ne 4 11 Expanding Buses in Print Wizard 20 3 o o o o o o o oooooo oo 4 12 Print Wizard 3 of 3 for Sending to a PDF File 4 12 Print Wizard 3 of 3 for Sending to a Printer oooooo o 4 13 Page Setup Window ssssssseessseeeeeee eee 4 13 Bl
66. data Instead the ILA ATC core stores captured trace data in the two million sample deep trace buffer in the Agilent E5904B TPA The ILA ATC core consists of three major components e Trigger input and output logic Trigger input logic detects elaborate trigger events Trigger output logic triggers external test equipment and other logic e Data capture logic Captures and stores trace data information in the Agilent E5904B Trace Port Analyzer via a 38 pin MICTOR connector e Control and status logic Manages the operation of the ILA ATC core ILA ATC Trigger Input Logic The trigger input capabilities of the ILA ATC core are very similar to those of the ILA core These features are described in ILA Trigger Input Logic page 1 5 Note The ILA ATC core does not have the storage qualification condition capability that the ILA IBA OPB and IBA PLB cores have ILA ATC Trigger Output Logic The trigger output capabilities of the ILA ATC core are identical to those of the ILA core These features are described in ILA Trigger Output Logic page 1 10 ChipScope Pro Software and Cores User Guide www xilinx com 1 11 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction ILA ATC Data Capture Logic Each ILA ATC core can capture data independently from all other cores in the design as long as each ILA ATC core uses its own special data connector and the Agilent E5904B TPA Currently the ILA ATC core on
67. either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select ILA ATC Integrated Logic Analyzer with Agilent Trace Core and click Next Figure 2 13 e ChipScope Pro Core Generator ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate 2 ICON Integrated Controller 2 ILA Integrated Logic Analyzer 8 IL A ATC Integrated Logic Analyzer with Agilent Trace Core IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus 2 IBA PLB Integrated Bus Analyzer for Processor Local Bus D VIO Virtual Input Output Core 2 ATC2 Agilent Trace Core 2 Figure 2 13 Selecting the ILA ATC Core ChipScope Pro Software and Cores User Guide www xilinx com 2 19 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator General ILA ATC Core Options The second screen in the Core Generator is used to set up the of the general ILA ATC core options Figure 2 14 e ChipScope Pro Core Generator ILA with Agilent Trace Core General Options Design Files Output Netlist ila edn Browse Device Settings Device Family Virtex2 lxi Y Use SRL 16s v Use RPMs Clock Settings Sample On Rising y Edge Of Clock IS lt Previous Next gt el Figure 2 14 ILA ATC Core General Options Choosing the File Destination The destination for the ILA ATC EDIF netlist ila_atc edn is displayed in the Output Netlist field The default direc
68. factors the maximum allowable data width is 256 bits Selecting the Data Same As Trigger Ports If the Data Same As Trigger checkbox is selected then a checkbox for each TRIGn port appears in the data port options screen These checkboxes should be used to select the individual trigger ports that will be included in the aggregate data port Note that selecting the individual trigger ports automatically updates the Aggregate Data Width field accordingly A maximum data width of 256 bits applies to the aggregate selection of trigger ports Number of Block RAMs As the data depth and data width selections are changed the Number of Block RAMs field notifies you of how many block RAMs will be used by the IBA OPB core The trigger mark is automatically taken into account when calculating this value Creating Example Templates After selecting the parameters for the IBA OPB core click Next to view the Example and Template Options Figure 2 24 e ChipScope Pro Core Generator IBA OPB Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL v Synthesis Tool Xilinx XST Bus Signal Name Example File Settings v Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg lt Previous Generate Core Figure 2 24 IBA OPB Core Example and Template Options ChipScope Pro Software
69. families including the QPro variants of these families Virtex II is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices 2 8 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA Core 7 XILINX Using SRL 16s The ILA core normally uses the SRL16 feature of the FPGA device to increase performance and decrease the area used by the core If the device family is Virtex II Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the OPro variants of these families the usage of SRL16s by the ILA core can be disabled by deselecting the Use SRL16s checkbox It is recommended that the Use SRL16s checkbox remain enabled Note SRL16s must be used with the Virtex Virtex E Spartan ll or Spartan IIE device families including the QPro variants of these families Using RPMs The ILA core normally uses relationally placed macros RPMs to increase the performance of the core If the device family is Virtex II Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the QPro variants of these families the usage of RPMs by the ILA core can be disabled by deselecting the Use RPMs checkbox It is recommended that the Use RPMs checkbox remain enabled for these device families Note RPMs cannot be used with the Virtex Virtex E Sp
70. in range comparisons Detects high to low and low to high bit wise transitions Compares 1 bit per slice All match units connected to a given trigger port are the same type Choice of Match Function Event Counter All the match units of a trigger port can be configured with an event counter with a selectable size of 1 to 32 bits This counter can be configured at run time to count events in the following ways e Exactly n occurrences Matches only when exactly n consecutive or non consecutive events occur e Atleast n occurrences Matches and stays asserted once n consecutive or non consecutive events occur e Atleast n consecutive occurrences Matches once n consecutive events occur and stays asserted until the match function is not satisfied 1 6 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description 7 XILINX Table 1 3 Trigger Features of the ILA and ILA ATC Cores Continued Feature Trigger Output Port Description The internal trigger condition of the ILA core can be accessed using the optional trigger output port This signal can be used as a trigger for external test equipment by attaching the signal to an output pin However it can also be used by internal logic as an interrupt a trigger or to cascade multiple ILA cores together The trigger output port will have a determined a
71. individual signals or bits The number of bits used to compose a trigger port is called the trigger width The width of each trigger port can be set independently using the TRIGn Trigger Width field The range of values that can be used for trigger port widths is 1 to 256 Selecting the Number of Trigger Match Units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form what is called the overall trigger condition event that is used to control the capturing of data Each trigger port TRIGn can be connected to 1 to 16 match units by using the Match Units pull down list Selecting one match unit conserves resources while still allowing some flexibility in detecting trigger events Selecting two or more trigger match units allows a more flexible trigger condition equation to be a combination of multiple match units However increasing the number of match units per trigger portincreases the usage of logic resources accordingly Note The aggregate number of match units used in a single ILA ATC core cannot exceed 16 regardless of the number of trigger ports used 2 22 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC Core 7 XILINX Selecting the Match Unit Type The different comparisons or match functions that can be performed by the trig
72. message signals the end of the process You can select to either go back and specify different options or click Start Over to generate new cores ChipScope Pro Core Generator Generate Messages Device Family Virtexz Control port count 1 Enable BSCAN instance true BSCAN chain USER1 Enable JTAG global clock buffer true Enable unused BSCAN ports false Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinx ip icon icon Writing licon edn Post Processing EDIF netlist icon edn Generating constraints file icon ncf Generating batch mode argument file icon arg ChipScope Pro Core Generator Version 7 11 Build 4 212 895 Example Usage File icon_xst_example vhd Generating batch mode argument file ticon_xst_vhdl_example arg CORE GENERATION COMPLETE Previous Figure 2 4 ICON Core Generation Complete Using the ICON Core To instantiate the example ICON core HDL files into your design use the following guidelines to connect the ICON core port signals to various signals in your design e Connect one of the ICON core s unused CONTROL port signals to a control port of only one ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core instance in the design e Donotleave any unused CONTROL ports of the ICON core unconnected as this will cause the implementation tools to report an error Instead use an ICON core with the same number of CONTRO
73. of TriggerSetup Run cause the trigger to re arm 4 32 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Analyzer Menu Features XILINX Waveform Window To view the waveform for a particular ChipScope Pro ILA or IBA core select Window New Unit Windows and the ChipScope Pro core desired A dialog box will be displayed for that ChipScope Pro Unit and the user can select the Trigger Setup Waveform Listing and or Bus Plot window or any combination Windows cannot be closed from this dialog box The same operation can be achieved by double clicking on the Waveform leaf node in the project tree or right clicking on the Waveform leaf node and selecting Open Waveform The Waveform window displays the sample buffer as a waveform display similar to many modern simulators and logic analyzers All signal browser operations can also be performed in the waveform window such as bus creation radix selection renaming etc To perform a signal operation right click on a signal or bus in the Bus Signal column Bus and Signal Reordering Buses and signals can be reordered in the Waveform window Select one or more signals and buses and drag it to its new location A ghost image of the signal or signals appears with the cursor and a red line shows the potential drop location En Waveform DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA ng E z 1024 704 384 64 256 576 896 121
74. of handling up to 16 OPB masters and 64 OPB slaves Note It is very important to specify the same number of OPB masters and slaves that you have on the OPB bus of your embedded processor design otherwise the IBA OPB core may not function properly Another key feature of the IBA OPB core is its ability to monitor the OPB bus for up to 32 different bus protocol violations Table 2 8 which spans multiple pages To include this functionality in the IBA OPB core select the Enable Protocol Violation Monitor checkbox Table 2 8 CoreConnect OPB Protocol Violation Error Description Priority Bit Encoding Error Description 1 011010 1 19 2 OPB DBus changed state during a write operation before receipt of OPB xferAck 2 011001 1 19 1 OPB ABus changed state during an operation before receipt of OPB xferAck 3 001100 1 6 1 OPB ABus NoMx Select signal active and non zero OPB ABus 4 001101 1 7 1 OPB DBus NoMx Select signal active and non zero OPB DBus 5 010101 1 13 1 OPB_xferAck OPB_xferAck active with no Mx select 6 010110 1 13 2 OPB_xferAck OPB_xferAck did not activate within 16 cycles of OPB_select 7 010111 1 15 1 OPB errAck OPB errAck active with no Mx select 8 000100 1 4 0 OPB retry OPB retryandOPB xferAck active in the same cycle 2 32 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core XILINX
75. or bus and select the operation desired Alternatively the standard Windows key combinations are available Ctrl X for cut Ctrl C for copy Ctrl V for paste Del for delete 4 40 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Value Column The Value column displays the current value of each of the signals in the console see Figure 4 47 page 4 39 In the case of VIO core inputs those cells are non editable Buses are displayed according to their selected radix The VIO core inputs are updated periodically by default according to a drop down combo box at the bottom of the console Each of the VIO core inputs captures along with the current value of the signal activity information about the signal since the last time the input was queried At high design speeds it is possible for a signal to be sampled as a 0 then have the signal transition from a 0 to a 1 then back to a 0 again before the signal is sampled again In the case of synchronous inputs the activity is also detected with respect to the design clock This can be useful in detecting glitches If a 0 to 1 transition is detected an up arrow will appear alongside the value If a 1 to 0 transition is detected a down arrow appears If both are detected a two headed arrow is displayed The length of time the activity is displayed in the table is called the persistence The persistence is also ind
76. please consult the Agilent E5904B option FPGA 500 trace port analyzer documentation The Connection Attempt Timeout text field indicates how long the ChipScope Analyzer should attempt to communicate to the cable unsuccessfully before timing out The JTAG TCK Frequency combo box indicates the speed of the JTAG interface from the Agilent cable to the JTAG chain Choose a frequency that is appropriate for your system given signal integrity and other concerns The JTAG Voltage Reference combo box indicates which voltage supply to use for the communication to the JTAG chain 3 3V internal 2 5V internal or an external supply The Trace Voltage Reference combo box indicates which voltage supply to use for the trace port data pins 3 3V internal 2 5V internal or an external supply ChipScope Pro Analyzer new project 2 y Agilent ES904B Cable Options HostiP KXXX Connection Attempt Timeout 10 Seconds JTAG TCK Frequency 1 MHz JTAG Voltage Reference 3 3V Internal Trace Voltage Reference 33VIntemal 7 F Cancel Figure 4 18 Agilent E5904B Cable Options Dialog Box 4 18 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Opening a MultiLINX connection To connect to a MultiLINX cable make sure the cable is properly connected to either the serial or USB port and select Cable Xilinx MultiLINX Serial Cable or Cable
77. synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus and click Next Figure 2 19 e ChipScope Pro Core Generator ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate ICON Integrated Controller ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus 2 IBA PLB Integrated Bus Analyzer for Processor Local Bus D MIO Virtual Input Output Core ATC2 Agilent Trace Core 2 Figure 2 19 Selecting the IBA OPB Core 2 30 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core 7 XILINX General IBA OPB Core Options The second screen in the Core Generator is used to set up the of the general IBA OPB core options Figure 2 20 e ChipScope Pro Core Generator IBA for On Chip Peripheral Bus General Options Design Files Output Netlist iba_opb edn Browse Device Settings Device Family Virtex2P Use SRL16s v Use RPMs Clock Settings Sample On Rising Ly Edge Of Clock OPB Bus Settings Number of OPB Masters 2 xj v Enable Protocol Violation
78. the ChipScope Pro cores you can use the instantiation templates that are provided to quickly and easily insert the cores into their VHDL or Verilog design After completing the instantiation and running synthesis you can implement the design using the Xilinx ISE 7 1i implementation tools Generating an ICON Core The Core Generator tool provides the ability to define and generate a customized ICON core to use with one or more ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 capture cores in HDL designs You can customize control ports that is the number of ChipScope Pro cores to be connected to the ICON core and customize the use of the Boundary Scan primitive component for example BSCAN_VIRTEX2 that is used for JTAG communication After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file nc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows ChipScope Pro Software and Cores User Guide www xilinx com 2 1 UGO029 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select ICON Integrated Controller core Figure 2 1 page 2 2 and click Next e ChipScope Pro Core Generator ChipScope
79. the number of pins and their characteristics to be used for external capture as well as how many input data ports you need You can also customize the type of capture mode state or timing to be used as well as the TDM compression mode 1x or 2x After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file ncf a signal import file cdc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select ATC2 Agilent Trace Core 2 and click Next Figure 2 37 5 ChipScope Pro Core Generator BEE ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate 2 ICON Integrated Controller D ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core 2 IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus IBAPPLB Integrated Bus Analyzer for Processor Local Bus D VIO Virtual Input Output Core ATC2 Agilent Trace Core 2 Figure 2 37 Selecting the ATC2 Core 2 62 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the ATC2 Core 7 XILINX General ATC2 Core Options The second screen in the Core Gene
80. using the ChipScope Pro tools e The ChipScope Pro Core Generator e The ChipScope Pro Core Inserter e The ChipScope Pro Analyzer These tools integrate key logic analyzer hardware components with the target design inside Xilinx Virtex Virtex E Virtex Il Virtex II Pro Virtex 4 Spartan I Spartan IIE Spartan 3 and Spartan 3E devices including the QPro variants of these families The ChipScope Pro tools communicate with these components and provide the designer with a complete logic analyzer User Guide Contents This user guide contains the following chapters e Chapter 1 Introduction describes the ChipScope Pro tools These tools integrate key logic analyzer hardware components with the target design inside Xilinx Virtex Virtex E Virtex IL Virtex II Pro Virtex 4 Spartan IL Spartan IIE Spartan 3 and Spartan 3E devices including the QPro variants of these families The ChipScope Pro tools communicate with these components and provide the designer with a complete logic analyzer e Chapter 2 Using the ChipScope Pro Core Generator explains how to use this graphical interface to generate the ChipScope Pro cores Integrated Controller core ICON Integrated Logic Analyzer core ILA Integrated Logic Analyzer with Agilent Trace Core ILA ATC Integrated Bus Analyzer for CoreConnect On Chip Peripheral Bus core IBA OPB Integrated Bus Analyzer for CoreConnect Processor Local Bus core
81. value is only an approximation that is used to illustrate the relative resource utilization of the different match unit types It should not be used as a hard estimate of resource utilization Use the TRIGn Match Type pull down list to select the type of match unit that will apply to all match units connected to the trigger port However as the functionality of the match unit increases so does the amount of resources necessary to implement that functionality This flexibility allows you to customize the functionality of the trigger module while keeping resource usage in check ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 2 23 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting Match Unit Counter Width The match unit counter is a configurable counter on the output of the each match unit in a trigger port This counter can be configured at run time to count a specific number of match unit events To include a match counter on each match unit in the trigger port select a counter width from 1 to 32 The match counter will not be included on each match unit if the Counter Width combo box is set to Disabled The default Counter Width setting is Disabled Enabling the Trigger Condition Sequencer The trigger condition sequencer can be either a Boolean equation or an optional trigger sequencer that is enabled by checking the Enable Trigger Sequencer checkbox A block
82. version registration ID More information on how to obtain a full version of ChipScope Pro is available at http www xilinx com chipscope pro ChipScope Pro Software and Cores User Guide www xilinx com 4 43 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer ChipScope Pro Main Toolbar Features In addition to the menu options other ChipScope Pro Analyzer commands are available on a toolbar residing directly below the ChipScope Pro Analyzer menu Figure 4 51 The second set of toolbar buttons is available only when the Trigger Setup window is open The third and fourth sets of toolbar buttons are only available when the Waveform window is active Qunti F 2A Figure 4 51 Main ChipScope Pro Analyzer Toolbar Display The toolbar buttons from left to right correspond to the following equivalent menu options e Open Cable Search JTAG Chain Automatically detects the cable and queries the JTAG chain to find its composition e Turn On Off Auto Core Status Polling Green icon means polling is on red icon means polling is off Same as JTAG Chain gt Auto Core Status Poll e Run Same as Trigger Setup gt Run F5 e Stop Same as Trigger Setup gt Stop Acquisition F9 e Trigger Immediate Same as Trigger Setup gt Trigger Immediate Ctrl F5 e Go To X Marker Same as Waveform gt Go To gt Go To X Marker e GoTo O Marker Same as Waveform gt Go To gt Go To O Marker e Go To Previou
83. when the Capture Mode is set to STATE mode Enable Auto Setup The Enable Auto Setup option is used to enable a feature that allows the Agilent Logic Analyzer to automatically set up the appropriate ATC2 pin to Logic Analyzer pod connections This feature also allows the Agilent Logic Analyzer to automatically determine the optimal phase and voltage sampling offsets for each ATC2 pin This feature is enabled by default Enable Always On Mode The Enable Always On Mode option is used to force an ATC2 core to always enable its internal logic and output buffers The Always On mode will also force the selection of signal bank 0 upon FPGA device configuration This mode makes it possible to capture events that immediately follow device configuration without having to first set up the ATC2 core manually This feature is disabled by default and is only available when the capture mode is set to TIMING mode Pin Edit Mode The Pin Edit Mode parameter is a time saving feature that allows you to change the IO Standard Drive and Slew Rate pin parameters on individual pins or together as a group of pins Setting the Pin Edit Mode to Individual allows you to edit the parameters of each pin independently from one another Setting the mode to Same as ATCK will allow you to change the ATCK pin parameters and will force all ATD pins to the same settings You need to set unique pin locations for each individual pin regardless of the Pin Edit Mode ATD P
84. xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Generating the ATC2 Core 7 XILINX Bus Signal Name Example Files cdc The bus signal name example file for the ATC2 core for example atc2 cdc contains generic information about the data ports of the ATC2 core The atc2 cda file will be created if you select the Generate Bus Signal Name Example File cdc checkbox You can use the atc2 cdc file as a template to change data port signal names create buses and so on The modified atc2 cdc file can then be imported into the Agilent logic analyzer Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example atc2 arg by selecting the Generate Batch Mode Argument Example File arg checkbox The atc2 arg file is used with the command line program called generate The atc2 arg file contains all of the arguments necessary for generating the ATC2 core without having to use the ChipScope Pro Core Generator GUI tool Note An ATC2 core can be generated by running generate exe atc2 f atc2 arg atthe command prompt on Windows systems or by running generate sh atc2 f atc2 arg atthe UNIX shell prompt on Linux and Solaris systems Generating the Core After entering the ATC2 core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information app
85. you can force the Core Inserter to refresh the netlist by selecting File Refresh Netlist Inserting and Removing Units You can insert new units into the project by selecting Edit gt New ILA Unit Edit gt New ILA ATC Unit or Edit New ATC2 Unit You can remove a unit by selecting Edit gt Remove Unit after choosing which unit to delete Setting Preferences You can set the ChipScope Core Inserter project preferences by selecting Edit Preferences They are organized into three categories Tools ISE Integration and Miscellaneous Refer to Managing Project Preferences page 3 28 for more information about setting these preferences Inserting the Cores ICON ILA ILA ATC and ATC2 cores are inserted when the flow is completed or by selecting Insert gt Insert Core If all channels of all the capture cores are not connected to valid signals an error message results Exiting the Core Inserter To exit the ChipScope Core Inserter select File Exit 3 6 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX Specifying Input and Output Files The ChipScope Core Inserter works in a step by step process 1 Specify the Input Design Netlist Figure 3 3 page 3 5 2 Click Browse to navigate to the directory where the netlist resides 3 Modify the Output Design Netlist and Output Directory fields as needed These fields are auto
86. 0090000000000000000000000000000000000000000000000000000 lt Back Send to PDF Send to Printer Figure 4 8 Print Wizard 2 of 3 Page Preview Buttons The buttons at the top of the page control which page of the waveform printout is being previewed as follow e The and gt gt buttons go to the first and last preview pages respectively e The lt and gt buttons go to the previous and next preview pages respectively e The text box in the middle can be used to go to a specific preview page Navigation Buttons The buttons at the bottom of the Print Wizard 2 of 3 window Figure 4 8 are defined as follows Back Returns to the Print Wizard 1 of 3 window Send to PDF Opens the Print Wizard 3 of 3 window for writing directly to a PDF File Send to Printer Opens the Print Wizard 3 of 3 window for sending to a printer Close Closes the Print Wizard window without printing ChipScope Pro Software and Cores User Guide www xilinx com 4 11 UGO29 v7 1 February 16 2005 7 XILINX Chapter 4 Using the ChipScope Pro Analyzer Bus Expansion and Contraction You can manipulate the waveform by expanding and contracting the buses in the print preview window For example if you expand a bus in Figure 4 8 page 4 11 such that it pushes other signals buses to another page the total print preview page count at the top will change accordingly as shown in Figure 4 9 Print Wizard
87. 2005 Tcl JTAG Example XILINX Tcl JTAG Example The following example shows how you can have complete access to a JTAG chain over a Xilinx parallel cable by using just a few Tcl commands 1 From the DOS prompt navigate to the ChipScope Pro install directory and invoke your tcl shell The executable is tclsh exe for the standard one or xtclsh exe if you have the Xilinx tools installed You receive a prompt like this Load the tc1j tag library and support functions Assuming you are in the ChipScope installation directory type the following at the tc1 shell prompt source tcljtag tcl You should see a message similar to Attaching XYZ where XYZ is an address Open a cable Assuming you have a Xilinx Parallel Cable III Parallel Cable IV or MultiPRO cable attached on a standard 1pt1 port type set handle jtag open If the cable open operation was successful handle will see something like cable0x10 0068 the numbers will vary Get an exclusive lock on the cable resource jtag lock handle Autodetect the devices in the jtag chain jtag autodetect handle If the autodetect was successful you see a list of devices found for example 80a30093 xcv600e 5 21028093 xc2v1000 6 05026093 xc18v00 8 Navigate to Test gt Logic Reset According to the JTAG specification this will load the IDCODE or BYPASS instruction into all the instruction registers jtag navigate handle TLR Shift some 1 bits in
88. 33 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Zooming In and Out Select Waveform Zoom Zoom In to zoom in to the center of the waveform display or right click in the waveform section and select Zoom Zoom In To zoom out from a waveform use Waveform Zoom Zoom Out or right click in the waveform and select Zoom Zoom Out To view the entire waveform display select Waveform Zoom Zoom Fit or right click in the waveform and select Zoom Zoom Fit To zoom into a specific area just use the left mouse button to drag a rectangle in the waveform display Once the drag is complete a popup appears Select Zoom Area to perform the zoom Figure 4 41 E Waveform DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA num A 1024 704 384 64 256 576 896 1216 1536 1856 2176 2496 2816 Bus Signal xio microProgAddr uml sun E microPortAddr 06 06 microPortDataIj 01 01 microPortData0y 01 01 nicroReadStrob UN 1 HA LI LLLI TELLE EHE EHE EHE EHE ELLE ELLE ELLE LUE LULLL ULL LLL LI T T RO I A WON microWritestrol microInterrupt npIrqInt tat sectorRead3trol Zoom Area sectorUritestr sacfReadRegStr ol oui o Bol o Ben o 5l o Zon o lod o Bea o sacfReconfig3t Uu gt ren ves Po NN LL MINI MPCE reg
89. 4 45 any number of buses may be displayed at one When data vs data is chosen Figure 4 46 two buses need to be selected and each point in the plot s x coordinate will be the value of one of the buses at a particular time and the y coordinate will the value of the other bus at the same time Each bus will have its own color and will be displayed according to its radix hexadecimal binary octal token and ASCII radices are displayed as unsigned decimal values with scale factor 1 0 precision 0 a Bus Plot DEV 2 MyDevice2 XC2VP7 UNIT 0 MyILAO ILA Plot O data vs time data vs data Display line E Bus Selection X COSINE NA SINE y Min Max Min Max 32767 32167 X 11140 Y 11796 Figure 4 46 The Bus Plot Window Data vs Data Display Type The bus plot can be displayed using lines points or lines and points The display type affects all bus values being displayed Bus Selection The bus selection control allows you to select the individual buses to plot in data vs time mode or the buses to plot against one another in data vs data mode The color of each bus can be changed by clicking on the colored button next to the bus name Figure 4 45 page 4 37 Min Max The Min Max display is used to show the maximum and minimum values of the axis in the current view of the bus plot Cursor Tracking The X and Y displays at the b
90. 52 lt Previous Figure 2 39 ATC2 Core State Mode Data Capture Options e ChipScope Pro Core Generator Agilent Trace Core 2 Data Options Data Capture Settings Capture Mode Timing TDM Rate Signal Bank Count 4 ATD Pin Count g Driver Endpoint Type Single Ended Data Port Width 9 Pin Edit Mode Same as ATCK v Enable Auto Setup Max Frequency Range 301 500 MHz C Enable Always On Mode Pin Parameters Pin Name PinLoc O Standard veco Drive _ Slew Rate krek m Tepo y ATDIOI wm 1 83 m wfrast kron ee ees m2 wfrast ATDI vre rbs m2 v rer TD 3 vr debs 2 least 1 ever 83 m2 wfrast f 3 4 15 vr fps m wfrast TDIB vr fps m2 w rer 7 L L 12 v ATD VTTI Core Utilization LUT Count 114 FFCount 100 mm Previous Figure 2 40 ATC2 Core Timing Mode Data Capture Options 2 64 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the ATC2 Core 7 XILINX Capture Mode The Capture Mode of the ATC2 core can be set to either State mode Figure 2 39 page 2 64 for synchronous data capture to the CLK input signal or to Timing mode Figure 2 40 page 2 64 for asynchronous data capture In State mode the data path through the ATC2 core uses pipeline flip flops that are clocked on the CLK input por
91. 6 1536 1856 2176 2496 2816 Bus Signal x 0 J o microProghdar sun sun z microPortaddr 06 06 EN microPortDataly 01 01 222 bd microPortDataOy 01 01 ae ew nicroReadStrob LAMM EEHEEHLEHEL EHE EHE LEE EHE EHE EHE EHE ENDE ELEE LUE E UELLE LULLL ULL ULL LI nicrolritesStrol microlnterrupt npIrqInt tat sectorReadStro sectorWriteStr sacfReadReg3tr OU o Hol o Hal o fea o Sl o Bol o fall o M o sacfReconfig ti ies Lobo T MPCE reg 0 O TULLE l l ll ll ll ll l l l LLALLA IIN MPOE reg o o Ll ALLEE LLL LEE EL LEE ELE EE ELLE ELLE EE ELLE ELLE LEE LL LL LEE LEE L LLLI NPUE reg 0 o LL iii MPIRQ reg 0 o MPBRDY reg 0 a sine 18 18 EM 4 plana vl al X 1024 4 gt 0 1024 gt aix 0 0 LILBL A OnA nA Figure 4 40 Reordering Buses or Signals in the Waveform Cut Copy Paste Delete Signals and Buses Signals and buses can be cut copied pasted or deleted using right click menus Select one or more signals and or buses right click on a selected signal or bus and select the operation desired Alternatively the standard Windows key combinations are available Ctrl X for cut Ctrl C for copy Ctrl V for paste Del for delete ChipScope Pro Software and Cores User Guide www xilinx com 4
92. 8 4x 27 524 280 262 136 12 1x 11 2 097 120 1 048 560 12 2x 21 1 048 560 524 280 12 4x 43 524 280 262 136 16 1x 15 2 097 120 1 048 560 16 2x 29 1 048 560 524 280 16 4x 59 524 280 262 136 20 1x 19 2 097 120 1 048 560 20 2x 37 1 048 560 524 280 20 4x 75 524 280 262 136 3 18 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX Choosing ATC2 Data Capture Settings If you are inserting an ATC2 core the Pin Selection Parameters look like those in Figure 3 12 and Figure 3 13 for STATE mode and TIMING mode respectively ChipScope Pro Core Inserter my_design cdc File Edit Help d occ El DEVICE ATC2 Gi ICON UD ILA Pin Selection Parameters Net Connections U1 ATC2 Global Parameters 5 E Capture Mode Pin Edit Mode Endpoint Type TDM Rate STATE v Same as ATCK v SINGLE ENDED px y _Defauts Clock Edge ATD Pin Count Signal Bank Count Data Width RISING vj 8 x 4 Max Frequency Range 301 500MHz v Y Enable Auto Setup Select ATC2 Options Individual Pin Settings Pin Name Pin Loc JO Standard ATCK AB21 24 F ATDIOI wat vemoss des Ja v esr lvW ATOM v22 vcwosos dees fa wfrasr lv L 24 F ATDI v22 i F hron ya vcwosas eps m rast ATDIAI m CTO O CS CS 7 AR lATD 5 IATDIEI
93. 9 1 OPB RNW OPB_RNW high with no Mx select 19 011011 1 19 3 OPB RNW changed state during an operation before receipt of OPB xferAck 20 011100 1 19 4 OPB select changed state during an operation before receipt of OPB xferAck 21 011101 1 19 5 OPB BEBus changed state during a write or read operation before receipt of OPB xferAck 22 011110 1 20 3 Byte enable transfer not aligned with address offset 23 011111 1 20 4 Byte enable transfer initiated with non contiguous byte enables 24 000110 1 4 2 OPB_retry Mx_Request from retried master remained active after a retry cycle 25 000101 1 4 1 OPB_retry OPB_BusLock remained active after a retry cycle 26 010001 1 11 1 OPB seqAddr OPB seqAddr active with no OPB BusLock 27 010010 1 11 2 OPB seqAddr OPB seqAddr active with no Mx select 28 010011 1 11 3 OPB_seqAddr OPB_ABUS did not increment properly during OPB_seqAddr 29 010100 1 11 4 OPB_seqAddr OPB_seqAddr was asserted without a transaction boundary ChipScope Pro Software and Cores User Guide www xilinx com 1 15 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction Table 1 6 CoreConnect OPB Protocol Violation Error Description Continued Priority Bit Encoding Error Description 30 011000 1 16 1 OPB ToutSup OPB ToutSup active with no Mx select 31 001010 1 5 1 OPB Timeout Arbiter failed to signal OPB Timeout after 16 non responding cycles 32 001011 1 5 2 OPB Ti
94. Arguments count New JTAG chain device count Returns 1 success 0 failure for set operation if count parameter is provided Current device count for get operation if count parameter is not provided Examples 1 To set the JTAG chain to three devices jtag devicecount handle 3 2 To print the number of devices puts Number of devices in the chain jtag devicecount handle ChipScope Pro Software and Cores User Guide www xilinx com 5 5 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag_irlength This command is used to get or set the instruction register length for a device in the JTAG chain Syntax jtag irlength handle device length Required Arguments handle Handle to the cable connection device Device number 0 chainlength 1 Optional Arguments length Length to set Returns 1 success 0 failure if length is provided Current length of the IR if length parameter is not provided Examples 1 Ifthe length parameter is provided set the instruction register length of the given device jtag irlength handle 0 5 2 Ifthe length parameter is not provided return the IR length of the given device puts IR Length of device 0 is jtag irlength handle 0 5 6 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX jtag_lock This command is used to try to obtain an exclusive lock on the c
95. ChipScope Pro Software and Cores User Guide ChipScope Pro Software v7 11 UG029 v7 1 February 16 2005 XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection w
96. ChipScope Pro Core Generator Version 7 11 Build 4 212 895 Example Usage File wio_xst_example vhd Generating batch mode argument file Wwio_xst_vhdl_example arg CORE GENERATION COMPLETE En 4 lt Previous Start Over Figure 2 36 VIO Core Generation Complete Using the VIO Core To instantiate the example VIO core HDL files into your design use the following guidelines to connect the VIO core port signals to various signals in your design e Connect the VIO core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the VIO core s asynchronous and synchronous input signals to a 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process e For best results make sure the synchronous input source signals are synchronous to the VIO clock signal CLK also make sure the synchronous output sink signals are synchronous to the VIO clock signal CLK ChipScope Pro Software and Cores User Guide www xilinx com 2 61 UGO29 v7 1 February 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator Generating the ATC2 Core The ChipScope Pro Core Generator tool provides the ability to define and generate a customized ATC2 core for adding external Agilent logic analyzer capture capabilities to your HDL designs You can customize
97. Core 7 XILINX ILA ATC Core Data Port Options After you have set up the ILA ATC core trigger port options click Next This takes you to the fourth screen in the Core Generator that is used to set up the of the ILA ATC core data port options Figure 2 16 e ChipScope Pro Core Generator ILA with Agilent Trace Core Data Port Options External Capture Settings Transmit Rate lax v Max CLK port frequency 50 MHz Number of Data Pins 8 v Number of DCMs Used 1 Output Buffer Type LVTTL 3 3V 24mA Fast vj Number of BUFGs Used 2 Clock Pin Location P13 Data Pin Locations Pin 0 ra Pint pg Pin 2 Ra Pin 3 Ns Pin 4 les Pin 5 P12 Pin 6 IE Pin 7 rra Data Port Settings Data Width 1 to 27 27 Data Depth Up to 524280 samples lt Previous Next gt Figure 2 16 ILA ATC Core Data Port Options Transmit Rate The ILA ATC core does not use on chip memory resources to store the captured trace data Instead it transmits the data to be captured to an Agilent TPA that is attached to a special connector via FPGA device pins The data can be transmitted out the device pins at the same rate as the incoming DATA port transmit rate 1x twice the rate as the DATA port transmit rate 2x or four times the DATA port rate transmit rate 4x Maximum CLK Port Frequency The maximum output clock frequency is 200 MHz The incoming CLK port rate is limited by the max
98. E 2 e Mn BE 1 e Mn BE 0 e Mn select e Mn_RNW e Mn_seqAddr where n is the master number 0 to 15 ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 1 17 XILINX Chapter 1 Introduction Table 1 7 OPB Signal Groups Continued Trigger Group Width Description Name OPB_SLm_CTRL 4 OPB control signals slave m including e Slm xferAck e Slm errAck e Slm_toutSup e Slm retry where m is the slave number 0 to 63 OPB PV 6 OPB protocol violation signals TRIG IN User defined Generic trigger input The IBA OPB core can monitor not only CoreConnect OPB bus signals but can also monitor generic design signals using the TRIG IN trigger group This capability allows the user to correlate events that are occurring on the CoreConnect OPB bus with events elsewhere in the design The IBA OPB core can also be connected to other ChipScope Pro capture cores using the TRIG IN and TRIG OUT port signals to perform cross triggering operations while monitoring different parts of the design IBA OPB Data Capture Logic The data capture logic capabilities of the IBA OPB core are identical to those of the ILA core These features are described in ILA Data Capture Logic page 1 10 IBA OPB Control and Status Logic The IBA OPB contains a modest amount of control and status logic that is used to maintain the normal operation of the core All logic necess
99. F B Trigger Condition Settings v Enable Trigger Sequencer Max Number of Sequencer Levels 16 Dd Storage Qualification Condition Settings v Enable Storage Qualification Trigger Output Settings v Enable Trigger Output Port lt Previous Figure 2 28 IBA PLB Core Trigger Port Options 2 46 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Generating the IBA PLB Core 7 XILINX Selecting the PLB Signal Groups as Trigger Ports The PLB bus is divided into logical signal groups as described in Table 2 11 which spans multiple pages You can select any of these PLB signal groups as trigger ports by selecting the checkbox to the left of each group Note that the IBA PLB core is limited to either 16 trigger ports or 16 total match units used whichever limit is reached first Table 2 11 PLB Signal Groups Trigger Group Name Width Description PLB CTRL 26 PLB combined control signals including e SYS plbReset e PLB_abort e PLB BE 0 e PLB BE 1 e PLB BE 2 e PLB BE 3 e PLB BE 4 e PLB BE 5 e PLB BE 6 e PLB BE 7 e PLB_busLock e PLB masterID 0 e PLB masterID 1 e PLB masterID 2 e PLB masterID 3 e PLB Msize 0 e PLB Msize 1 e PLB PAValid e PLB SAValid e PLB_rdPrim e PLB RNW e PLB_size 0 e PLB size 1 e PLB_size 2 e PLB_size 3 e PLB wrPrim o o a PLB ABUS 32 PLB address bus PLB RDDBUS 64
100. FDR FDR PB IBUF IBUF IBUF IMshreg count dly 3 COSINE 4 gt IMshreg count dly 3 pbCount 1 gt Mshreg_count_dly_3 lt pbCount 10 gt TRIG_OUT mpo imp mp2 imp3 count 31 pbSync Mshreg_count_dly_3 lt U SINCOS Mshreg count dly 3 pbCount 1 Mshreg count dly 3 pbCount 10 FD FD FD FD FD FD FORE FDE sine_cosine FOE FoR FOE FOR FD FD FD FD FD FD FDRE FDE sine cosine FDE FDR FDE FDR CH CPO Mshreg pbSynca D Mshreg pbSynca 0 FDE FDE 1 OK Cancel Make Connections 4 Move Nets Up Remove Connections l Y Move Nets Down Figure 3 16 Select Net Dialog Box This dialog box provides an easy interface to choose nets to connect to the ILA ILA ATC or ATC2 cores The hierarchical structure of the design can be traversed using the Structure Nets pane on the upper left of the Select Net dialog box All the design s nets of the selected structure hierarchy level appear in the table on the lower left pane of the Select Net dialog box The following net information is displayed in this table e Net Name The name of the net as it appears in the EDIF netlist The net name may be different than the corresponding signal name in the HDL source due to renaming and other optimizations during synthesis e Source Instance The instance name of th
101. IBA PLB Virtual Input Output core VIO Agilent Trace Core 2 ATC2 As a group these cores are called the ChipScope Pro cores After generating the ChipScope Pro cores you can use the instantiation templates that are provided to quickly and easily insert the cores into VHDL or Verilog designs After completing the instantiation and running synthesis you can implement the design using the Xilinx ISE 7 1i implementation tools ChipScope Pro Software and Cores User Guide www xilinx com xxi UGO29 v7 1 February 16 2005 7 XILINX Preface About This User Guide e Chapter 3 Using the ChipScope Pro Core Inserter explains how to use this post synthesis tool to generate a netlist that includes the user design as well as ICON ILA ILA ATC and ATC2 cores as needed parameterized accordingly The Core Inserter gives you the flexibility to quickly and easily use the ChipScope Pro debug functionality to analyze an already synthesized design and without any HDL instantiation e Chapter 4 Using the ChipScope Pro Analyzer explains how to use this tool which interfaces directly to the ICON ILA ILA ATC IBA OPB IBA PLB VIO and ATC2 cores collectively called the ChipScope Pro cores You can configure your device choose triggers setup the console and view the results of the capture on the fly The data views and triggers can be manipulated in many ways providing an easy and intuitive interface to determine the func
102. IBA PLB core cannot exceed 16 regardless of the number of trigger ports used ChipScope Pro Software and Cores User Guide www xilinx com 2 49 UGO29 v7 1 February 16 2005 2 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting the Match Unit Type The different comparisons or match functions that can be performed by the trigger port match units depend on the type of the match unit Six different types of match units are supported by the IBA PLB cores Table 2 12 Table 2 12 IBA PLB Trigger Match Unit Types Type Bit Values Match Function ts Description Basic 0 1 X n od 8 Can be used for comparing data signals where transition detection is not important This is the most bit wise economical type of match unit Basic 0 1 X R F B ZO 4 Can be used for comparing w edges control signals where transition detection e g low to high high to low etc is important Extended 0 1 X ft o du S 2 Can be used for comparing gt lt lt address or data signals where magnitude is important Extended 0 1 X R E B uo do n 2 Can be used for comparing w edges SL lt address or data signals where a magnitude and transition detection are important Range 0 1 X ES P 1 Can be used for comparing SY address or data signals where a in range not range of values is important in range Range 0 1 X R F B tel Do 1 Can be used for comparing w edges gt lt lt address or data signals where
103. INPUT s0 VIOSTATUSREG ADDR 06 mainLoop INPUT s0 VIOSTATUSREG_ADDR 06 JUMP mainLoop 001 JUMP mainLoop 001 AND s0 ERROR STATUS 02 0 2367 aJe a x 0 1403 Figure 4 44 The Listing View Bus and Signal Reordering Buses and signals can be reordered in the Listing window Simply click on a signal or bus heading in the table and drag it to a new location Removing Signals Buses Individual signals and buses can be removed from the Listing window by right clicking anywhere in the signal s column and selecting Remove If Remove All is selected all signals and buses will be removed 4 36 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Cursors Cursors are available in the Listing window the same way as in the Waveform window To place a cursor right click in the data section of the Listing window and select either Place X Cursor or Place O Cursor That line in the table will be colored the same as the cursor color To move the cursor to a different position in the table either right click in the new location and do the same operation as before or right click on the cursor handle in the first column and drag it to the new location Goto Cursors To automatically scroll the listing view to a cursor right click and select Go To gt Go To X Cursor or Go To gt Go To O Cursor Bus Plot Window To view the Bus Pl
104. L ports as you have ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 cores 2 6 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA Core 7 XILINX Generating an ILA Core The ChipScope Pro Core Generator tool provides the ability to define and generate a customized ILA capture core to use with HDL designs You can customize the number width and capabilities of the trigger ports You can also customize the maximum number of data samples stored by the ILA core and the width of the data samples if different from the trigger ports After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file nc a signal import file cdc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select ILA Integrated Logic Analyzer and click Next Figure 2 5 e ChipScope Pro Core Generator ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate 2 ICON Integrated Controller ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core D IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus 2 IBA PLB Integrated Bus
105. M microProgAddr 3FF exactly one clock cycle fal M1 microProgAddr x exactly one clock cycle 9 M2 micraPortAddr D 0000 t laci M3 microPortDataln 100K 0009 exactly one cl M4 microPoriDataOut 000 0000 actly gt M5 microStrobes x exactly one clock cycle 9 MG MPA reg 100 000X exactly one cl M7 MP control regs X XXXF exactly one clock cycle 9 M amp MP control regs X 5000 exactly one clock cycle bn M8 microlnterrupts XX 5600 exactly one clock cycle M10 microInterrupts Xx 3000 exactly one clock cycle M11 sine 3000 2000 2000 3000 3000 tly one clock cycle Add Active Trigger Condition Name Trigger Condition Equation Output Enable j OJ TriggerCondition M Pulse High Type Window Windows o 4 Depth 4096 v Position 1024 Storage Qualification All Data Figure 4 31 Trigger Setup Window with All Sections Expanded Capture Settings The capture settings section of the Trigger Setup window Figure 4 32 defines the number of windows and where the trigger event occur in each of those windows A window is a contiguous sequence of samples containing one and only one trigger event If an invalid number is entered for any parameter the text field turns red and an error is displayed in the Message pane E r Q Type Win
106. Make sure that the gzip and tar programs are in your executable path Copy the ChipScope Pro 7 1i sol tar gz file to the desired installation directory Change directory to the desired installation directory Uncompress and extract the ChipScope Pro 7 1i sol tar ggz file using the following command gzip cd ChipScope Pro 7 li sol tar gz tar xvf This will create a directory called chipscope under the current working directory Set up the CHIPSCOPE environment variable to point to the chipscope installation For csh setenv CHIPSCOPE path to chipscope parent chipscope For sh set CHIPSCOPE path to chipscope parent chipscope export CHIPSCOPE Run the CHIPSCOPE bin sol register sh program to register your copy of the ChipScope Pro 7 1i tools Use your 16 digit registration ID when prompted You must register your ChipScope Pro 7 1i product at http www xilinx com chipscope in order to obtain your valid registration ID Run the ChipScope Pro tools For the ChipScope Pro Core Generator SCHIPSCOPE bin sol gengui sh For the ChipScope Pro Core Inserter CHIPSCOPE bin sol inserter sh For the ChipScope Pro Analyzer SCHIPSCOPE bin sol analyzer sh 1 30 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Software Installation XILINX Installing ChipScope Pro Software for Linux After downloading the ChipScope Pro Tools in the form of a compressed t
107. Pro Core Generator Selecting the Data Same As Trigger Ports If the Data Same As Trigger checkbox is selected then a checkbox for each TRIGn port appears in the data port options screen These checkboxes should be used to select the individual trigger ports that will be included in the aggregate data port Note that selecting the individual trigger ports automatically updates the Aggregate Data Width field accordingly A maximum data width of 256 bits applies to the aggregate selection of trigger ports Number of Block RAMs As the data depth and data width selections are changed the Number of Block RAMs field notifies you of how many block RAMs will be used by the IBA PLB core The trigger mark is automatically taken into account when calculating this value Creating Example Templates After selecting the parameters for the IBA PLB core click Next to view the Example and Template Options Figure 2 31 ChipScope Pro Core Generator BEE IBA PLB Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL y Synthesis Tool Xilinx XST Bus Signal Name Example File Settings v Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg lt Previous GenerateCore Figure 2 31 IBA PLB Core Example and Template Options 2 54 www xilinx com ChipScope Pro Software an
108. Pro Core Generator Core Type Selection Select Core Type To Generate ICON Integrated Controller 2 ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core 9 IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus 2 IBAPLB Integrated Bus Analyzer for Processor Local Bus D VIO Virtual Input Output Core ATC2 Agilent Trace Core 2 Figure 2 1 Selecting the ICON Core General ICON Core Options The second screen in the Core Generator is used to set up the of the general ICON core options Figure 2 2 e ChipScope Pro Core Generator ICON General Options Design Files Output Netlist icon edn Device Settings Device Family irtex2 ICON Parameters Number of Control Ports 1 z _ Disable Boundary Scan Component Instance Boundary Scan Chain USER1 y C Disable JTAG Clock BUFG Insertion _ Enable Unused Boundary Scan Ports only if necessary me Previous Figure 2 2 ICON Core General Options 2 2 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ICON Core 7 XILINX Choosing the File Destination The destination for the ICON EDIF file icon edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selectin
109. Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features XILINX Maximum CLK Port Frequency The maximum output clock frequency is 200 MHz The incoming CLK port rate is limited by the maximum output clock frequency as well as the transmit rate If the transmit rate is 1x then the maximum CLK port frequency is 200 MHz If the transmit rate is 2x then the maximum CLK port frequency is 100 MHz Finally if the transmit rate is 4x then the maximum CLK port frequency is 50 MHz Clock Resource Usage The ILA ATC core will use dedicated clock resources if the transmit rate is 2x or 4x The number of clock resources required by the ILA ATC core are shown in Table 3 4 Table 3 4 ILA ATC Clock Resource Utilization Virtex Virtex E Virtex ll Virtex Il Pro Virtex 4 Spartan ll and Spartan llE Spartan 3 and Spartan 3E Transmit Rate Number of Number of BUFGs CLKDLLs Number of BUFGs Number of DCMs 1x 0 0 0 0 2x 1 1 1 1 4x 1 2 2 1 Output Buffer Type You can select the type of output buffer used for the output clock and data pins The types of output data buffers that are supported by the ILA ATC cores depend on the device family Table 3 5 Table 3 5 ILA ATC Output Buffer Types by Device Family Virtex ll Butter Type me pr d Spartan 3 Spartan 3E LVTTL 3 3V 24mA Fast Yes Yes
110. RIG OUT port is very flexible and has many uses You can connect the TRIG OUT port to a device pin in order to trigger external test equipment such as oscilloscopes and logic analyzers Connecting the TRIG_OUT to an interrupt line of an embedded PowerPC 405 or MicroBlaze processor can be used to cause a software event to occur You can also connect the TRIG_OUT port of one core to a trigger input port of another core in order to expand the trigger and data capture capabilities of your on chip debug solution IBA PLB Data Capture Logic The data capture capabilities of the IBA PLB core are identical to those of the ILA core These features are described in ILA Data Capture Logic page 1 10 IBA PLB Control and Status Logic The IBA PLB core contains a modest amount of control and status logic that is used to maintain the normal operation of the core All logic necessary to properly identify and communicate with the IBA PLB core is implemented by this control and status logic ChipScope Pro Software and Cores User Guide www xilinx com 1 21 UGO29 v7 1 February 16 2005 7 XILINX Chapter 1 Introduction VIO Core The Virtual Input Output VIO core is a customizable core that can both monitor and drive internal FPGA signals in real time Unlike the ILA and IBA cores no on or off chip RAM is required Four kinds of signals are available in a the VIO core e Asynchronous inputs These are sampled using the JTAG clock signal that
111. RR Fe ER aede 4 7 Creating and Saving A New Project 6 ccc cence ees 4 7 Saving Projects xdi dd br etek ae bate ductae qe eda dece ceste koe ara 4 7 Printing Waveforms viscosidad ad ee oe REPE EH RE 4 8 Print Wizard 1 of 3 Window 0 cece e en 4 9 Print Wizard 2 of 3 Window lees 4 11 Print Wizard 3 of 3 Window 0 cece eee hn 4 12 Page Setup users eo eA a cx ex e ee 4 13 Importing Signal Names sida UC REC EE xp ee ree eid 4 14 Exporting Data 22s neecabe renes eUam exe ees cen doses di aan fep i 4 15 Closing and Exiting the Analyzer 006 6 cence eee 4 15 Viewing Opuons 2 2 8 vee evs esate ee eg be pa SEP ae Dole 4 15 Setting up a Server Host Connection 0 cece eee eee 4 16 Opening a Parallel Cable Connection n nanasan nsanra nnr ne cence eee 4 17 Opening an Agilent E5904B Cable Connection 000 000 eee eee eee 4 18 Opening a MultiLINX connection 0 6666s 4 19 Opening a Platform Cable USB Connection 00 0 c cee eee 4 19 Polling the Auto Core Status 66 ne 4 20 Configuring the Target Device s 2 cies 4 20 Setting Up the Boundary Scan JTAG Chain 2 6 6 4 20 Device Configurations cer iori a hapa E E Ed C pP aes eae 4 21 Observing Configuration Progress 1 6 cc nen 4 22 Displaying JTAG User and ID Codes 0 6 cence eens 4 22 Displaying Configuration Status Information 006 c eee ee eee ee 4 23 Trigger 5etup
112. The VIO core normally uses the SRL16 feature of the FPGA device to increase performance and decrease the area used by the core If the device family is Virtex II Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the QPro variants of these families the usage of SRL16s by the VIO core can be disabled by deselecting the Use SRL16s checkbox It is recommended that the Use SRL16s checkbox remain enabled Note SRL16s must be used with the Virtex Virtex E Spartan ll or Spartan lIE device families including the QPro variants of these families 2 58 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the VIO Core XILINX Selecting Input Output Port Settings Asynchronous Input Signals The VIO core will include asynchronous inputs when the Enable Asynchronous Input Signals checkbox is enabled When enabled you can specify that up to 256 asynchronous input signals should be used by entering a value in the Width text field Asynchronous input signals are inputs to the VIO core and can be used as outputs from your design regardless of the clock domain Asynchronous Output Signals The VIO core will include asynchronous outputs when the Enable Asynchronous Output Signals checkbox is enabled When enabled you can specify that up to 256 asynchronous output signals should be used by entering a value in the Width text field Asynchronous output signals are outputs from the VIO co
113. UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting the Number of Trigger Ports Each ILA core can have up to 16 separate trigger ports that can be set up independently After you choose a number from the Number of Trigger Ports pull down list a group of options appears for each trigger port The group of options associated with each trigger port is labeled with TRIGn where n is the trigger port number 0 to 15 The trigger port options include trigger width number of match units connected to the trigger port and the type of these match units Entering the Width of the Trigger Ports The individual trigger ports are buses that are made up of individual signals or bits The number of bits used to compose a trigger port is called the trigger width The width of each trigger port can be set independently using the TRIGn Trigger Width field The range of values that can be used for trigger port widths is 1 to 256 Selecting the Number of Trigger Match Units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form what is called the overall trigger condition event that is used to control the capturing of data Each trigger port TRIGn can be connected to 1 to 16 match units by using the Match Units pull down list Selecting one match unit conserves resources whi
114. UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Text Field When the Text Field type is selected a text field is available for input using only the following valid characters e Qand 1 for individual signals and binary buses e 0 9 A F for hex buses e 0 7 for octal buses e Valid signed and unsigned integers Push Button The Push Button type simulates an actual push button on a PCB The inactive value is set when the button is not pressed in 0 for active high 1 for active low As long as the button is pressed in the active value will be output from the VIO core Toggle Button The Toggle Button type switches between a 1 and a 0 with a single click Pulse Train Synchronous outputs only The Pulse Train output type provides a control for synchronous outputs A pulse train is a 16 cycle train of 1 s and 0 s defined by the user To edit the pulse train click Edit This brings up the Pulse Train dialog box see Figure 4 49 One text field is available for each cycle in the pulse train The text fields are populated by default according to the last value of the bus or signal For buses the fields are always displayed in binary to allow explicit control over each of the individual signals When Run is clicked the pulse train is executed one time This allows fine control over the output with respect to the design clock 000 0000 0000 cycles 100 0000 0110 000 0000 0000 Cycle9
115. Unit Type The different comparisons or match functions that can be performed by the trigger port match units depend on the type of the match unit Six types of match units are supported by the ILA and ILA ATC cores Table 3 1 Table 3 1 ILA Trigger Match Unit Types Bits Per P Type Bit Values Match Function Sliceb Description Basic 0 1 X lt gt 8 Can be used for comparing data signals where transition detection is not important This is the most bit wise economical type of match unit Basic OLX REB t lt gt 4 Can be used for comparing control w edges signals where transition detection e g low to high high to low etc is important Extended 0 1 X tS du AS 2 Can be used for comparing address lt lt lt or data signals where magnitude is important Extended 0 1 X R F B lt gt gt gt 2 Can be used for comparing address w edges E cd or data signals where a magnitude and transition detection are important Range 0 1 X Co do o Ld 1 Can be used for comparing address lt lt lt in or data signals where a range of range not in values is important range Range 0 1 X R F B lt gt gt gt 1 Can be used for comparing address w edges lt lt in or data signals where a range of range not in values and transition detection are range important a Bit values 0 means logical 0 1 means logi
116. WIDndOW 3 0 sen bec eec ida 4 24 CaptureSettngs eehed terea rk prre e ex dae a eae eee rte ipa 4 25 Match FunctionS o oooooor ehh raras 4 28 Trigger Conditions i44 cayos li ia EX YT 4 29 Saving and Recalling Trigger Setups oooooccooococconconcan ee 4 32 Running Arming the Trigger c ceeeeeeeeeeeeee teen ens 4 32 Stopping Disarming the Trigger cies e 4 32 Waveform Window 4 22 tv EXER Ry RA e wA T REX reu br E ok b E RN Y 4 33 Bus and Signal Reordering cod A bp UE De EE C E C ERE A 4 33 Cut Copy Paste Delete Signals and Buses oooocoocoocooconccnccco 4 33 Zooming and Out Eb ie ebd een erc iia 4 34 Centering the Waveform spuie trinek borai ehh hh n 4 35 CUT aet o det aie Se E E Ce ed Rk d A RSE ARERR a eee 4 35 Sample Display Numbering a cessos tinae tu eraann aae en 4 35 Displaying Markers Sidi A O E ai 4 36 Listing WandoW iers c vsseserte ni A AA bae ee lg 4 36 Bus and Signal Reordering Leer Uere CC e Ptr E EPI ES 4 36 Removing Signals BUSES esses m eu ERR eR eEVLE LEES aos 4 36 CUISO S it ger ek E dE ded Se d RR e SE Ee 4 37 Goto Cursors Li vex ERREUR INS Erit av ee vad oe ES 4 37 Bus Plot Window o ooooooooor hr 4 37 PlOt LY PC esc ected ure er ere bebe eed casui sace doeet d den tee 4 38 Display Typezsus duin dtiasa s desees Sekt aues iacere Mit eL dete tied 4 38 Bus Selections vv uo cet exar REESE eius cos d rd e ee als 4 38 MIO Max iau aie ae REG Peu RI EEE DIR E RA A Parr acr drag 4
117. Waveform and Listing windows Storage Qualification Condition The storage qualification condition is a Boolean combination of events that are detected by the match unit comparators that are subsequently attached to the trigger ports of the core The storage qualification condition evaluates trigger port match unit events to decide whether or not to capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start or finish the capture process and what data is captured respectively The Storage Condition dialog box has a table of all the match units Each match unit occupies a row in the table The Enable column indicates if that match unit is part of the trigger condition The Negate column indicates if that match unit should be individually negated Boolean NOT in the trigger condition The storage qualification condition can be configured to capture all data as shown in Figure 4 33 page 4 27 or it can be set up to capture data that satisfies a Boolean AND or OR combination of all the enabled match units as shown in Figure 4 34 page 4 27 The overall Boolean equation can also be negated selectable using the Negate Whole Equation checkbox above the table The resulting equation appears in the Storage Condition Equation pane at the bottom of the window 4 26 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer M
118. able 5 1 See the Command Details page 5 3 section for additional information about these commands Table 5 1 Tcl JTAG Command Summary Tcl JTAG Command Description jtag autodetect Automatically detects devices in the JTAG chain jtag close Closes a JTAG cable connection jtag devicecount Gets or sets the number of devices in the JTAG chain jtag irlength Gets or sets length of the instruction register IR jtag lock Lock a JTAG cable resource jtag navigate Get or set the JTAG test access port TAP state jtag open Opens a JTAG cable connection jtag scanchain Get a list of device IDCODEs by scanning the JTAG chain jtag shiftir Shift bits into the JTAG instruction register IR jtag shiftdr Shift bits into the JTAG data register DR jtag unlock Unlock a JTAG cable resource jtag version Get the current version of the Tcl JTAG interface 5 2 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX Command Details jtag_autodetect This command is used to autodetect the devices in the current JTAG chain This function calls jtag scanchain first to obtain IDCODEs for devices in the chain The devices with known IDCODEs have IR lengths automatically assigned Unrecognized devices must have their IR lengths assigned manually with jtag irlength Syntax jtag autodetect handle Required Arguments handle Handle to the
119. able resource If mswait is provided block a maximum of mswait milliseconds while waiting for the resource If mswait is not provided this command will not block Note A lock should always be obtained before performing any JTAG transactions Failure to do so may result in unexpected behavior Syntax jtag lock handle mswait Required Arguments handle Handle to the cable connection Optional Arguments mswait Time to wait in milliseconds Returns 1 success 0 failure to get lock Example 1 Try to obtain a JTAG connection lock and wait at least 1000 milliseconds If the lock fails after 1000 ms then a failure will be asserted by returning a value of 0 jtag_ lock handle 1000 ChipScope Pro Software and Cores User Guide www xilinx com 5 7 UGO029 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag navigate This command is used to set or get the current JTAG TAP state If state is provided navigate the JTAG TAP state machine to the given stable state e Test Logic Reset TLR e Run Test Idle RTT The state parameter must be one of TLR RTI The cycles parameter represents the number of extra times to toggle the JTAG TAP clock signal TCK after arriving at the stable state Syntax jtag navigate handle state cycles Required Arguments handle Handle to the cable connection Optional Arguments state JTAG state TLR RTI cycles Number of extra times to toggle TCK
120. an be saved in any location with a ctj extension To load a trigger settings file into the current project select Trigger Setup Read Trigger Setup A Read Trigger Setup file dialog box will open and you can navigate to the folder where the trigger settings file with a ctj extension exists Once the trigger setting file is chosen select Open and those settings will be loaded into the Trigger Settings window Running Arming the Trigger After setting up the trigger select Trigger Setup Run to arm it The trigger stays armed until the trigger condition is satisfied or you disarm the trigger Once the trigger condition is satisfied the core captures data according to the capture settings When the sample buffer is full the core stops capturing data The data is then uploaded from the core and is displayed in the Waveform and or Listing windows To force the trigger select Trigger Setup Trigger Immediate This causes the ChipScope Pro unit to ignore the trigger condition and trigger immediately After the sample buffer fills with data the trigger disarms and the captured data appears in the Waveform and or Listing window s Stopping Disarming the Trigger To disarm the trigger select TriggerSetup Stop Acquisition If the trigger condition has been satisfied at least once before the acquisition is stopped the ChipScope Pro Analyzer program disarms the trigger and downloads displays the captured data Subsequent selections
121. and Cores User Guide www xilinx com 2 41 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the IBA OPB core without any HDL example files deselect the Generate HDL Example File checkbox Bus Signal Name Example Files cdc The bus signal name example file for the IBA OPB core for example iba opb cdc contains generic information about the trigger and data ports of the IBA OPB core The iba opb cdc file will be created if you select the Generate Bus Signal Name Example File cdc checkbox You can use the iba opb cdc file as a template to change trigger and or data port signal names create buses and so on The modified iba_opb cda file can then be imported into the ChipScope Pro Analyzer tool and applied to the appropriate IBA OPB core by using the File Import option Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example iba o
122. and the user can select the Trigger Setup Waveform Listing and or Bus Plot window or any combination Windows cannot be closed from this dialog box The same operation can be achieved by double clicking on the Listing leaf node in the project tree or right clicking on the Listing leaf node and selecting Open Listing The Listing window displays the sample buffer as a list of values in a table Individual signals and buses are columns in the table Figure 4 44 All signal browser operations can also be performed in the listing window such as bus creation radix selection and renaming To perform a signal operation right click on a signal or bus in the column heading Eco BEIDE IRAN E B lt gt 3 microPortAddr JUMP mainLoop 001 mainLoop INPUT s0 VIOSTATUSREG ADDR 06 mainLoop INPUT s0 VIOSTATUSREG ADDR 06 JUMP mainLoop 001 JUMP mainLoop 001 AND s0 ERROR STATUS 02 AND s0 ERROR STATUS 02 start ENABLE INTERRUPT start ENABLE INTERRUPT mainLoop INPUT s0 VIOSTATUSREG ADDR 06 mainLoop INPUT s0 VIOSTATUSREG_ADDR 06 JUMP nainLoop 001 JUMP mainLoop 001 mainLoop INPUT s0 VIOSTATUSREG ADDR 06 mainLoop INPUT s0 VIOSTATUSREG ADDR 06 JUMP mainLoop 001 JUMP mainLoop 001 AND s0 ERROR STATUS 02 AND s0 ERROR STATUS 02 start ENABLE INTERRUPT start ENABLE INTERRUPT nainLoop INPUT s0 VIOSTATUSREG ADDR 06 mainLoop INPUT s0 VIOSTATUSREG ADDR 06 JUMP mainLoop 001 JUMP mainLoop 001 mainLoop
123. ank Signal Import Dialog BO0x 0oooooococococoorcccoornccoo 4 14 Export Signals Dialog Box 0 eens 4 15 Server Settings for Local Mode 0 00 0c cece 4 16 Server Settings for Remote Mode 0 002s eee 4 16 Opening a Parallel Cable Connection 004 4 17 Agilent E5904B Cable Options Dialog BO0xX oooooooomommoo o 4 18 Opening a MultiLINX Serial Port Connection 4 19 Opening a Platform Cable USB Connection 4 19 Boundary Scan JTAG Setup Window 00 0 cee eee 4 20 Advanced JTAG Chain Parameters Setup Window 4 21 Device Menu Options sssssssss e 4 21 Selecting a Bitstream 6 eee 4 21 Opening a Configuration File 4 22 Device USERCODE and IDCODE s sees 4 23 Displaying Device Configuration Status 0004 4 23 Displaying Device Instruction Register Status 4 23 Opening New Unit Windows ssseessseeeeee eee 4 24 Trigger Setup Window with Only Match Functions Expanded 4 24 Trigger Setup Window with All Sections Expanded 4 25 Capture Settings iii a rd EY eb aad Hoe dee Ed e decens 4 25 Storage Qualification Condition Set to Capture All Data 4 27 Storage Qualification Condition Using Boolean Equation 4 27 Setting the Match Functions 0 c
124. ape archive file ie ChipScope Pro 7 1i lin tar gz 1 10 Make sure that your Linux operating system has all required patches for more details refer to the README LINUX file found in the installation archive Make sure that the Xilinx ISE 7 1i tools are installed on your system and that the XILINX environment variable is set up correctly Make sure that the gzip and tar programs are in your executable path Copy the ChipScope Pro 7 1i lin tar gz file to the desired installation directory Change directory to the desired installation directory Uncompress and extract the ChipScope Pro 7 1i lin tar gz file using the following command gzip cd ChipScope Pro 7 1i lin tar gz tar xvf This will create a directory called chipscope under the current working directory Set up the CHIPSCOPE environment variable to point to the chipscope installation For csh setenv CHIPSCOPE path to chipscope parent chipscope For sh Set CHIPSCOPE path to chipscope parent chipscope export CHIPSCOPE If you plan to use the ChipScope Pro Analyzer to connect to download cables that are attached to your Linux system please follow the download cable driver installation instructions in the README LINUX file found in the installation archive Run the CHIPSCOPE bin lin register sh program to register your copy of the ChipScope Pro 7 1i tools Use your 16 digit registration ID when prompted You must register your ChipScope Pro 7 1i produc
125. are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the ICON core without any HDL example files deselect the Generate HDL Example File checkbox Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example icon arg by selecting the Generate Batch Mode Argument Example File arg checkbox The icon arg file is used with the command line program called generate The icon arg file contains all of the arguments necessary for generating the ICON core without having to use the ChipScope Pro Core Generator GUI tool Note An ICON core can be generated by running generate exe icon pro f icon arg at the command prompt on Windows systems or by running generate sh icon pro f icon arg at the UNIX shell prompt on Linux and Solaris systems ChipScope Pro Software and Cores User Guide www xilinx com 2 5 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Generating the Core After entering the ICON core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens Figure 2 4 the progress information appears and the CORE GENERATION COMPLETE
126. aring w edges pa Cd address or data signals where a magnitude and transition detection are important Range 0 1 X a lt gt gt 1 Can be used for comparing gt lt lt address or data signals where a in range not range of values is important in range Range OLX REB fest ees ost 1 Can be used for comparing w edges em e RE address or data signals where a in range not range of values and transition in range detection are important a Bit values 0 means logical 0 1 means logical 1 X means don t care R means 0 to 1 transition F means 1 to 0 transition and B means any transition b The Bits Per Slice value is only an approximation that is used to illustrate the relative resource utilization of the different match unit types It should not be used as a hard estimate of resource utilization Use the TRIGn Match Type pull down list to select the type of match unit that applies to all match units connected to the trigger port However as the functionality of the match unit increases so does the amount of resources necessary to implement that functionality This flexibility allows you to customize the functionality of the trigger module while keeping resource usage in check ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 2 11 XILINX Chapter 2 Using the ChipScope Pr
127. artan ll or Spartan IIE device families including the QPro variants of these families Selecting the Clock Edge The ILA unit can use either the rising or falling edges of the CLK signal to trigger and capture data The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the ILA core ILA Core Trigger Port Options After you have set up the general ILA core options click Next This takes you to the third screen in the Core Generator that is used to set up the of the ILA core trigger port options Figure 2 7 e ChipScope Pro Core Generator ILA Trigger Port Options Trigger Input and Match Unit Settings Number of Input Trigger Po 6 Pa Number of Match Units Used 16 Trigger Width 32 Match Type Basic w edges Match Units Bit Values 0 1 X R F B Counter Width 8 Functions lt gt TRIGO Trigger Width Match Type Extended Match Units Bit Values 0 1 X Counter Width Functions lt gt gt gt lt lt TRIG1 Trigger Condition Settings v Enable Trigger Sequencer Max Number of Sequencer Levels 16 Storage Qualification Condition Settings v Enable Storage Qualification Trigger Output Settings v Enable Trigger Output Port lt Previous Figure 2 7 LA Core Trigger Port Options ChipScope Pro Software and Cores User Guide www xilinx com 2 9
128. articular clock in your design or to be completely asynchronous with respect to any clock domain in your design You can also customize the number of input and output signals used by the VIO core After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file nc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select VIO Virtual Input Output Core and click Next Figure 2 33 e ChipScope Pro Core Generator ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate 2 ICON Integrated Controller D ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core 2 IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus IBAPPLB Integrated Bus Analyzer for Processor Local Bus VIO Virtual Input Output Core ATC2 Agilent Trace Core 2 Figure 2 33 Selecting the VIO Core ChipScope Pro Software and Cores User Guide www xilinx com 2 57 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator General VIO Core Options The second screen in the Core Generator is used to set up the of the general VIO core options Figure
129. ary 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator Creating Example Templates After selecting the parameters for the VIO core click Next to view the Example and Template Generation Options Figure 2 35 e ChipScope Pro Core Generator VIO Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language VHDL Synthesis Tool Xilinx XST Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg lt Previous I Generate Core Figure 2 35 VIO Core Example and Template Options HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the VIO core without any HDL example files deselect the Generate HDL Example File checkbox 2 60 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the VIO Core 7 XILINX Batch Mode Generation Argument Example Files You can also create a batch mode argument examp
130. ary Scan port of the target FPGA and up to 15 ILA ILA ATC IBA OPB IBA PLB VIO and or ATC2 cores as shown in Figure 1 1 page 1 2 For non Virtex 4 devices the ICON core uses either the USER1 or USER2 JTAG Boundary Scan instructions for communication via the BSCAN_VIRTEX primitive The unused USER1 or USER2 scan chain of the BSCAN_VIRTEX primitive can also be exported for use in your application if needed 1 4 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX For Virtex 4 devices the ICON core uses any one of the USER1 USER2 USER3 or USER4 scan chains available via the BSCAN_VIRTEX4 primitive In Virtex 4 devices it is not necessary to export unused USER scan chains since each BSCAN_VIRTEX4 primitive implements a single scan chain ILA Core The ILA core is a customizable logic analyzer core that can be used to monitor any internal signal of your design Since the ILA core is synchronous to the design being monitored all design clock constraints that are applied to your design are also applied to the components ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 inside the ILA core The ILA core consists of three major components e Trigger input and output logic Trigger input logic detects elaborate trigger events Trigger output logic triggers external test equipment and other logic e Data captu
131. ary to properly identify and communicate with the IBA OPB core is implemented by this control and status logic IBA PLB Core The IBA PLB core is a specialized logic analyzer core specifically designed to debug embedded systems that contain the IBM CoreConnect Processor Local Bus PLB The IBA PLB core consists of three major parts components e Trigger input and output logic Trigger input logic detects PLB bus and other user defined events Trigger output logic triggers external test equipment and other logic e Data capture logic Captures and stores trace data information using on chip block RAM resources e Control and status logic Manages the operation of the IBA PLB core IBA PLB Trigger Input Logic The IBA core for the IBM CoreConnect Processor Local Bus IBA PLB is used to monitor the PLB bus of embedded Virtex II Pro and Virtex 4 FX PowerPC 405 processor systems Up to 16 different trigger groups can be monitored by the IBA PLB core at any given time 1 18 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 ChipScope Pro Cores Description 7 XILINX The types of PLB signal groups that can be monitored are described in Table 1 8 page 1 19 which spans multiple pages The IBA PLB core can also monitor other generic design signals using the TRIG IN trigger group in addition to the PLB bus signals This capability allows the user to correlate events that are oc
132. asting valuable on chip memory resources ChipScope Pro Software and Cores User Guide www xilinx com 1 9 UGO29 v7 1 February 16 2005 7 XILINX Chapter 1 Introduction ILA Trigger Output Logic The ILA core implements a trigger output port called TRIG_OUT The TRIG_OUT port is the output of the trigger condition that is set up at run time using the ChipScope Pro Analyzer The shape level or pulse and sense active high or low of the trigger output can also be controlled at run time The latency of the TRIG_OUT port relative to the input trigger ports is 10 clock cycles The TRIG_OUT port is very flexible and has many uses You can connect the TRIG_OUT port to a device pin in order to trigger external test equipment such as oscilloscopes and logic analyzers Connecting the TRIG_OUT port to an interrupt line of an embedded PowerPC 405 or MicroBlaze processor can be used to cause a software event to occur You can also connect the TRIG OUT port of one core to a trigger input port of another core in order to expand the trigger and data capture capabilities of your on chip debug solution ILA Data Capture Logic Each ILA core can capture data using on chip block RAM resources independently from all other cores in the design Each ILA core can also capture data using one of two capture modes Window and N samples Window Capture Mode In Window capture mode the sample buffer can be divided into one or more equal sized sample
133. c Successfully read project c projectsimy designlisewny design cdc 4 Figure 3 5 Core Inserter as Launched from Project Navigator Project Level Parameters Three project level parameters device family SRL16 usage and RPM usage must be specified for every project Due to the increased depth of Virtex II device block RAM different cores can be generated to take advantage of these deeper RAMs Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ICON and capture cores are optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The default target device family is Virtex II Using SRL 16s The Use SRL16s checkbox is used to select whether or not the cores will be generated using SRL16 and SRL16E components This option is only available for the Virtex II Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E device families including the OPro variants of these families If the checkbox is not selected the SRL16 components are replaced with flip flops and multiplexers which affects the size and performance of the generated cores The Use SRL16s checkbox is checked by default to generate cores that use the optimized SRL16 technology 3 8 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX
134. cable connection that is returned by jtag open Returns A list of devices in the chain List elements are in the format IDCODE DEVICETYPE IRLENGTH An exception is thrown if the detect chain fails to return a valid JTAG chain Example 1 Autodetect the devices in the JTAG chain and assign the list of devices to the variable called mychain set mychain jtag autodetect handle ChipScope Pro Software and Cores User Guide www xilinx com 5 3 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag close This command is used to close a JTAG cable connection The handle is no longer valid after closing the connection Syntax jtag close handle Required Arguments handle Handle to the cable connection that is returned by jtag open Returns 1 success O failure Example 1 Close the JTAG cable connection jtag_close handle 5 4 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX jtag_devicecount This command is used to get or set the device count If the count is specified set the device count If no count is specified return the current number of devices in the JTAG chain This function is called by jtag_autodetect to set the number of devices automatically Syntax jtag devicecount handle count Required Arguments handle Handle to the cable connection that is returned by jtag_open Optional
135. cal 1 X means don t care R means 0 to 1 transition F means 1 to 0 transition and B means any transition b The Bits Per Slice value is only an approximation that is used to illustrate the relative resource utilization of the different match unit types It should not be used as a hard estimate of resource utilization Use the TRIGn Match Type pull down list to select the type of match unit that will apply to all match units connected to the trigger port However as the functionality of the match unit increases so does the amount of resources necessary to implement that functionality This flexibility allows you to customize the functionality of the trigger module while keeping resource usage in check ChipScope Pro Software and Cores User Guide www xilinx com 3 11 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Selecting Match Unit Counter Width The match unit counter is a configurable counter on the output of the each match unit in a trigger port This counter can be configured at run time to count a specific number of match unit events To include a match counter on each match unit in the trigger port select a counter width from 1 to 32 The match counter will not be included on each match unit if the Counter Width combo box is set to Disabled The default Counter Width setting is Disabled Enabling the Trigger Condition Sequencer The trigg
136. capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data to capture The storage qualification condition can be enabled by checking the Enable Storage Qualification checkbox Enabling the Trigger Output Port The output of the IBA PLB trigger condition module can be brought out to a port signal by checking the Enable Trigger Output Port checkbox The trigger output port is used to trigger external test equipment by attaching the port signal to a device pin in the HDL design The trigger output port can also be attached to other logic or ChipScope Pro cores in the design to be used as a trigger an interrupt or another control signal The shape level or pulse and sense active high or low of the trigger output can also be controlled at run time The clock latency of the IBA PLB trigger output port is 15 clock PLB_CLK cycles with respect to the trigger input ports ChipScope Pro Software and Cores User Guide www xilinx com 2 51 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator IBA PLB Core Data Port Options After you have set up the IBA PLB core trigger port options click Next This takes you to the fourth screen in the Core Generator that is used to set up the of the IBA PLB core data port options Figure 2 29 e ChipScope Pro Core Generator IBA for Processor Local Bus Da
137. cc ec ro 4 28 Setting up the Match Counter 0 0 000 e eee eee 4 29 Viewing the Trigger Condition 0 000 esses 4 30 Setting the Trigger Condition Boolean Equation 4 30 Setting the Trigger Condition Sequencer 00 4 31 Reordering Buses or Signals in the Waveform 4 33 Zoom Area Using the Automatic Popup Menu 4 34 Zoom to Sample Range 0 eee eee 4 34 ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 xix XILINX Figure 4 43 Centering the Waveform on a Marker 0005 4 35 Figure 4 44 The Listing View ssssse cece eee eee eee 4 36 Figure 4 45 The Bus Plot Window Data vs Time ss sssssssss 4 37 Figure 4 46 The Bus Plot Window Data vs Data 4 38 Figure 4 47 The VIO Console Window sss 4 39 Figure 4 48 The Type Selection Menu sssss e 4 41 Figure 4 49 The Pulse Train Dialog 1 2 0 ooo cnn ee 4 42 Figure 4 50 Global Controls and Key sess eee 4 43 Figure 4 51 Main ChipScope Pro Analyzer Toolbar Display 4 44 Chapter 5 Tcl JTAG Interface XX www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 XILINX Preface About This User Guide This document provides users with information for
138. chain of the board under test Downloads at speeds up to 24 Mb s throughput e Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 5V down to 1 5V e Windows and Linux OS support Parallel Cable IV Uses the parallel port i e printer port to communicate with the Boundary Scan chain of the board under test Downloads at speeds up to 5 Mb s throughput e Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 5V down to 1 5V e Windows and Linux OS support Parallel Cable III Uses the parallel port i e printer port to communicate with the Boundary Scan chain of the board under test Downloads at speeds up to 500 kb s throughput e Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 5V down to 2 5V e Windows and Linux OS support MultiPRO Cable Uses the parallel port i e printer port to communicate with the Boundary Scan chain of the board under test Downloads at speeds up to 5 Mb s throughput e Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 5V down to 1 5V e Windows OS support only MultiLINX Cable Uses either the RS 232 i e serial port or USB 1 0 ports to communicate with the Boundary Scan chain of the board under test Downloads at speed
139. connection has been made so the connection appears in red S ChipScope Pro Core Inserter my_design cdc File Edit Help El E DEVICE E ICON U0 ILA U1 ATC2 ATC2 Pin Selection Parameters Net Connections Select ATC2 Options Net Connections UNIT CLOCK PORT CLK CLK_N DATA PORTS DATAO CHO CH1 CH2 CH3 CH4 CH5 CHE CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 nHA15 Modify Connections lt Previous Return to Project Navigator L Remove Unit Successfully read project c projectsimy_designiiselmy_design cdc Netlist timestamp changed rebuilding design copy c projectsimy_designiiseimy_design_cs ngc gt c projectsimy_design ise _ngo my_design_cs_signalbrowser ngo SetDesign my_design show SignalBrowserDialog Figure 3 15 ATC2 Net Connections 3 24 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX To change any core connection select Modify Connections The Select Net dialog box now appears Figure 3 16 Select Net Structure Nets my_design Net Selections Clock Signals Trigger Data Signals Channel Pattern z Source Instance Source Component Base Type CLK_BUFGP BUFGP BUFGP pbCount_0
140. created The ChipScope Pro Analyzer communicates with the ChipScope Pro cores by using one of the two internal scan chains USER1 or USER2 provided by the Boundary Scan component Since ChipScope Pro cores do not use both internal scan chains of the Boundary Scan component it is possible to share the Boundary Scan component with other elements in the user s design The Boundary Scan component can be shared with other parts of the design by using one of two methods e Instantiate the Boundary Scan component inside the ICON core and include the unused Boundary Scan scan chain signals as port signals on the ICON core interface e Instantiate the Boundary Scan component somewhere else in the design and attach either the USER1 or USER2 scan chain signals to corresponding port signals the ICON core interface The Boundary Scan component is instantiated inside the ICON core by default Use the Disable Boundary Scan Component Instance checkbox to disable the instantiation of the Boundary Scan component Selecting the Boundary Scan Chain The ChipScope Pro Analyzer can communicate with the ChipScope Pro cores using either the USER1 or USER2 boundary scan chains If the Boundary Scan component is instantiated inside the ICON core then you can select the desired scan chain from the Boundary Scan Chain pull down list ChipScope Pro Software and Cores User Guide www xilinx com 2 3 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using
141. curring on the PLB bus with events elsewhere in the design The IBA PLB core can also be connected to other ChipScope Pro capture cores using the TRIG IN and TRIG OUT port signals to perform cross triggering operations while monitoring different parts of the design The IBA PLB core is also able to implement the same trigger and storage qualification condition equations as the ILA core These features are described in the section called ILA Trigger Input Logic page 1 5 Table 1 8 PLB Signal Groups Trigger Group Name PLB CTRL Width 26 Description PLB bus control signals including e SYS plbReset e PLB_abort e PLB BE 0 e PLB BE 1 e PLB BE 2 e PLB BE 3 e PLB BE 4 e PLB BE 5 e PLB BE 6 e PLB BE 7 e PLB_busLock e PLB masterID 0 e PLB masterID 1 e PLB masterID 2 e PLB masterID 3 e PLB Msize 0 e PLB Msize 1 e PLB PAValid e PLB SAValid e PLB_rdPrim e PLB RNW e PLB_size 0 e PLB size 1 e PLB_size 2 e PLB_size 3 e PLB_wrPrim no PLB_ABUS PLB address bus PLB_RDDBUS PLB read data bus from slaves PLB_WRDBUS PLB write data bus to slaves ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 1 19 XILINX Chapter 1 Introduction Table 1 8 PLB Signal Groups Continued Trigger Group Name Width Description PLB_Mn_CTRL 32 PLB control signals for master ri including e PLB_MnAddrAck
142. d Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA PLB Core XILINX HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the IBA PLB core without any HDL example files deselect the Generate HDL Example File checkbox Bus Signal Name Example Files cdc The bus signal name example file for the IBA PLB core for example iba plb cdc contains generic information about the trigger and data ports of the IBA PLB core The iba plb cdc file will be created if you select the Generate Bus Signal Name Example File cdc checkbox You can use the iba plb cdc file as a template to change trigger and or data port signal names create buses and so on The modified iba_plb cda file can then be imported into the ChipScope Pro Analyzer tool and applied to the appropriate IBA PLB core by using the File gt Import option Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example iba plb arg by selecting the Generate Batch Mode
143. d USERCODEs ChipScope Pro Analyzer JTAG Chain Device Order Index Name Device Name IR Length Device IDCODE USERCODE D MyDevice System ACE 8 04001093 1 MyDevice1 xC18W00 18 05026093 2 MyDevice2 JXC2VP4 10 11238093 Advanced ox Cancel Read USERCODEs Figure 4 21 Boundary Scan JTAG Setup Window The ChipScope Pro Analyzer tool automatically keeps track of the test access port TAP state of the devices in the JTAG chain by default If the ChipScope Pro Analyzer is used in conjunction with other JTAG controllers such as the System ACE CompactFlash CF controller or processor debug tools then the actual TAP state of the target devices can differ from the tracking copy of the ChipScope Pro Analyzer In this case the ChipScope Pro Analyzer should always put the TAP controllers into a known state for example the Run Test Idle state before starting any JTAG transaction sequences Clicking on the 4 20 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Advanced button on theJTAG Chain Device Order dialog box reveals the parameters that control the start and end states of JTAG transactions Figure 4 22 Use the second parameter if the JTAG chain is shared with other JTAG controllers ChipScope Pro Analyzer JTAG Chain Device Order Index Name Device Name IR Length Device IDCODE USERCODE MyDevice
144. d bits of the ATC2 core s asynchronous and synchronous input signals to a 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process For best results make sure the State mode input data port signals are synchronous to the ATC2 clock signal CLK this is not important for Timing mode input data port signals 2 70 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Core Inserter Overview The ChipScope Pro Core Inserter is a post synthesis tool used to generate a netlist that includes the user design as well as parameterized ICON ILA ILA ATC and ATC2 cores as needed The Core Inserter gives you the flexibility to quickly and easily use the ChipScope Pro debug functionality to analyze an already synthesized design and without any HDL instantiation Note The IBA OPB IBA PLB and VIO cores are currently not supported in the Core Inserter Using the Core Inserter with ISE Project Navigator This section is provided for users of the Windows Linux or Solaris versions of ChipScope Pro 7 1i and Xilinx ISE 7 1i The Core Inserter cdc file can be added as a new source file to the Project Navigator source file list In addition to this the Project Navigator tool will also recognize and invoke the Core Inserter tool during the appropriate steps
145. d nec eens esed ahaa halen aes a a eet A 5 18 EXAM PIG ict rm 5 18 TRUST AG Example cir dd dor 5 19 ChipScope Pro Software and Cores User Guide www xilinx com xiii UGO029 v7 1 February 16 2005 EZ XILINX xiv www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Schedule of Tables Chapter 1 Introduction Table 1 1 ChipScope Pro Tools Description 1 1 Table 1 2 ChipScope Pro Features and Benefits 0 cece cece eee eee 1 3 Table 1 3 Trigger Features of the ILA and ILA ATC Cores ooooooocoooomomoo 1 5 Table 1 4 ILA ATC Clock Resource Utilizati0N ooooooooommmm 1 12 Table 1 5 ILA ATC Core Capabilities oooooooccorcoccocorcccooncccooo 1 13 Table 1 6 CoreConnect OPB Protocol Violation Error Description 1 14 Table 1 7 OPB Signal Groups ssssssssssesssesee e 1 17 Table 1 8 PLB Signal Groups sssssssssssssesee eens 1 19 Table 1 9 ICON and ILA Core CLB Usage in Virtex II Pro Devices 1 24 Table 1 10 ICON and ILA Core Block RAM Usage in Virtex II Pro Devices 1 24 Table 1 11 Design Parameter Changes Requiring Resynthesis 1 25 Table 1 12 ChipScope Pro Download Cable Support oooooococcccoccccco 1 26 Table 1 13 PC System Requirements for ChipScope Pro 7 1i Tools 1 27 Table 1 14 Linux Requirements for ChipScope Pro 7 1i ToolsS
146. d or Console window s in any combination Figure 4 29 Windows cannot be closed from this dialog box El ChipScope Pro Analyzer new project File View JTAG Chain Device Window Help ChipScope Pro Analyzer e NEW RIRWIGHBWSTM DEV2 MyDevice2 t C2VP 4 UNIT 0 MIO VIO Be New window selection DEV 2 MyDevice2 KC2VP4 UNIT MYILAT ILA I New Project PDA DEV 2 MyDevice2 XC2VP4 UNIT 2 MyATC22 ATC A Ls DEV 1 MyDevice1 XC18V00 DEV 2 MyDevice2 XC2VP 4 vj Trigger Setup UNIT O MyVIOO VIO ay Console l Waveform UNIT 1 MylLA1 ILA Trigger Setup v Listing Waveform x E arn v Bus Plot Figure 4 29 Opening New Unit Windows The same operation can by achieved by double clicking on the Trigger Setup leaf node in the project tree or by right clicking on the Trigger Setup leaf node and selecting Open Trigger Setup Each ChipScope Pro ILA ILA ATC and IBA core has its own Trigger Setup window which provides a graphical interface for the user to set up triggers The trigger mechanism inside each ChipScope Pro core can be modified at run time without having to re compile the design The following sections describe how to modify the trigger mechanism s three components e Match Functions Defines the match or comparison value for each match unit e Trigger Conditions Defines the overall trigger condition based on a binary equation or sequence of one or mor
147. d with non contiguous byte enables 24 000110 1 4 2 OPB_retry Mx_Request from retried master remained active after a retry cycle 25 000101 1 4 1 OPB_retry OPB_BusLock remained active after a retry cycle 26 010001 1 11 1 OPB segAddr OPB segAddr active with no OPB_BusLock ChipScope Pro Software and Cores User Guide www xilinx com 2 33 UGO29 v7 1 February 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator Table 2 8 CoreConnect OPB Protocol Violation Error Description Continued Priority Bit Encoding Error Description 27 010010 1 11 2 OPB segAddr OPB segAddr active with no Mx select 28 010011 1 11 3 OPB segAddr OPB ABUS did not increment properly during OPB segAddr 29 010100 1 11 4 OPB segAddr OPB segAddr was asserted without a transaction boundary 30 011000 1 16 1 OPB ToutSup OPB ToutSup active with no Mx select 31 001010 1 5 1 OPB_Timeout Arbiter failed to signal OPB_Timeout after 16 non responding cycles 32 001011 1 5 2 OPB Timeout OPB Timeout active with no Mx select 33 111111 N A No errors a Refer to Chapter 8 of the OPB Bus Functional Model Toolkit User s Manual from IBM for more information on these CoreConnect OPB errors This manual is included in the IBM CoreConnect installation IBA OPB Core Trigger Port Options After you have set up the general IBA OPB core options click Next This takes you to the t
148. de then the DATA input port will not be included in the port map of the IBA PLB core This mode conserves CLB and routing resources in the IBA PLB core but is limited to a maximum aggregate data sample word width of 256 bits e DataSeparate from Trigger Figure 2 29 page 2 52 The data port is completely independent of the trigger ports This mode is useful when you want to limit the amount of data being captured ChipScope Pro Core Generator BEE IBA for Processor Local Bus Data Port Options Data Port Settings Data Depth 1024 y Samples Aggregate Data Width 186 v Data Same As Trigger Number of Block RAMs 12 Include PLB Control Signals combined port TRIGO width 26 Include PLB Address Bus port TRIG1 width 32 v Include PLB Read Data Bus from slaves port TRIG2 width 64 Include PLB Write Data Bus to slaves port TRIG3 width 64 lt Previous Figure 2 30 IBA PLB Core Data Same As Trigger Options Entering the Data Width The width of each data sample word stored by the IBA PLB core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However regardless of these factors the maximum allowable data width is 256 bits ChipScope Pro Software and Cores User Guide www xilinx com 2 53 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope
149. design netlist as part of the Translate phase of the flow There is no need to set any properties to enable this to happen The cdc is in the project and associated with the design module being implemented and causes the cores to be inserted automatically 3 2 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Using the Core Inserter with ISE Project Navigator XILINX Useful Project Navigator Settings The following are useful Project Navigator settings to help you implement a design with ChipScope Pro cores 1 If you use the XST synthesis tool set the Keep Hierarchy option to Yes or Soft to preserve the design hierarchy and prevent the XST tool from optimizing across all levels of hierarchy in your design Using the Keep Hierarchy option preserves the names of nets and other recognizable components during the ChipScope Pro core insertion stage of the flow If you do not use the Keep Hierarchy option some of your nets and or components may be combined with other logic into new components or otherwise optimized away To keep the design hierarchy a b c d e Select Edit Preferences to bring up the Preferences dialog box Select the Processes tab Set the Property Display Level combobox dropdown to Advanced and click OK Right click on the Synthesize process and select the Properties option Make sure the Keep Hierarchy option is set to Yes or Soft and click OK 2 Prio
150. dow v Windows 1 Depth 4096 z Position 1024 o E Storage Qualification All Data Samples Per Trigger 1 Storage Qualification All Data Type andes Figure 4 32 Capture Settings Type The Type combo box in the capture settings defines the type of windows to use If Window is selected the number of samples in each window must be a power of two However the trigger can be in any position in the window If N Samples is selected the buffer will have as many windows as possible with the defined samples per trigger The trigger will always be the first sample in the window if N Samples is selected Windows The Windows text field is only available when Window is selected in the Type combo box The number of windows is specified in this field and can be any positive integer from 1 to the depth of the capture buffer ChipScope Pro Software and Cores User Guide www xilinx com 4 25 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Depth The Depth combo box is only available when Window is selected in the Type combo box The Depth combo box defines the depth of each capture window It is automatically populated with valid selections when values are typed into the Windows text field Only powers of two are available Note When the overall trigger condition consists of at least one match unit function that has a counter that is set t
151. e subsequently attached to the trigger ports of the core The storage qualification condition differs from the trigger condition in that it evaluates trigger port match unit events to decide whether or not to capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data to capture The storage qualification condition can be enabled by checking the Enable Storage Qualification checkbox Note The storage qualification condition is not available in the ILA ATC core 3 12 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features Choosing ILA Core Capture Parameters S ChipScope Pro Core Inserter my design cdc File Edit Help BH oo ILA Trigger Parameters Capture Settings Capture Parameters Net Connections 7 XILINX The second tab in the Core Inserter that is used to set up the of the capture parameters of the ILA core Figure 3 9 The capture parameters for ILA are different from ILA ATC see Figure 3 11 page 3 16 Select Integrated Logic Analyzer Options Data Depth 1024 Samples Data Width 32 _ Data Same As Trigger Trigger Ports Used As Data Include TRIGO Port width 8 Sample On Rising Clock Edge O Include TRIG1 Port s O Include 32 Port O Include TRIG3
152. e the connection is not actually established until you open a connection to a JTAG download cable as described in the subsequent sections of this document Note n remote mode the server needs to be started manually as described in the section Analyzer Server Interface page 4 2 4 16 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Opening a Parallel Cable Connection To open a connection to the Parallel Cable including the MultiPRO cable make sure the cable is connected to one of the computer s parallel ports Select JTAG Chain Xilinx Parallel Cable Figure 4 17 This pops up the Parallel Cable Selection configuration dialog box You can choose the Parallel Cable III Parallel Cable IV or have the Analyzer autodetect the cable type Note In order to open a connection to the MultiPRO cable select either Parallel Cable IV or Auto Detect Cable Type If the Parallel Cable IV or Auto Detect Cable Type option is selected you can choose the speed of the cable the choices are 10 MHz 5 MHz 2 5 MHz default 1 22 MHz or 625 kHz Choose the speed that makes the most sense for the board under test Type the printer port name in the Port selection box usually the default LPT1 is correct and click OK If successful the Analyzer queries the Boundary Scan chain to determine its composition see Setting Up the Boundary Scan JTAG Chain page 4 20
153. e IBA OPB core is a specialized logic analyzer core specifically designed to debug embedded systems that contain the IBM CoreConnect On Chip Peripheral Bus OPB The IBA OPB core consists of four major components A protocol violation monitor Detects and reports up to 32 violations of the IBM CoreConnect OPB bus protocol Trigger input and output logic Trigger input logic detects OPB bus and other user defined events Trigger output logic triggers external test equipment and other logic Data capture logic Captures and stores trace data information using on chip block RAM resources Control and status logic Manages the operation of the IBA OPB core IBA OPB Protocol Violation Monitor Logic The IBA OPB core includes a protocol violation monitor that can detect up to 32 different IBM CoreConnect OPB protocol violation errors The protocol violations that can be detected by the IBA OPB core are shown in Table 1 6 which spans multiple pages Table 1 6 CoreConnect OPB Protocol Violation Error Description Priority Bit Encoding Error Description 1 011010 1 19 2 OPB DBus changed state during a write operation before receipt of OPB xferAck 2 011001 1 19 1 OPB ABus changed state during an operation before receipt of OPB xferAck 3 001100 1 6 1 OPB ABus No Mx Select signal active and non zero OPB ABus 4 001101 1 7 1 OPB_DBus No Mx_Select signal active and non zero OPB_DBus 5 010101
154. e Miscellaneous preferences section Figure 3 20 contains other settings that affect how the Core Inserter operates For example the Core Inserter can be set up by the user to display the ports in the Select Net dialog box This may be desired if the cores are being inserted into a lower level EDIF netlist instead of the top level These port nets are shown in gray in the Select Net dialog box The Core Inserter can also be set up to display nets that are illegal for connection in the Select Net dialog box When this preference option is enabled any illegal nets are shown in red in the Select Net dialog box Edit Preferences Tools Miscellaneous Options ISE Integration Net Browser Miscellaneous E v Show Nets attached to Ports C Show Nets with Unroutable Components v Show Source Component Instance Names Show Source Component Types ivi v Show Base Net Driver Types Preference Options Reset all values to installation defaults Reset OK Cancel Figure 3 20 Core Inserter Miscellaneous Preference Settings Also the Core Inserter can be set up by the user to disable the display of source component instance names source component types and base net driver types in the Select Net dialog box You can reset the Core Inserter project preferences to the installation defaults by clicking on the Reset button ChipScope Pro Software and Cores User Guide www xilinx com 3 29 UGO29 v7 1 February 16 2005
155. e TRIG6 port width 8 v Include TRIG port width 8 v Include TRIG8 port width 8 v Include TRIG9 port width 8 v Include TRIG10 port width 8 v Include TRIG11 port width 8 v Include TRIG12 port width 8 Y Include TRIG13 port width 8 lt Previous Next Figure 2 10 ILA Core Data Same As Trigger Options Entering the Data Width The width of each data sample word stored by the ILA core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However regardless of these factors the maximum allowable data width is 256 bits Selecting the Data Same As Trigger Ports If the Data Same As Trigger checkbox is selected then a checkbox for each TRIGn port appears in the data port options screen These checkboxes should be used to select the individual trigger ports that will be included in the aggregate data port Note that selecting the individual trigger ports automatically updates the Aggregate Data Width field accordingly A maximum data width of 256 bits applies to the aggregate selection of trigger ports ChipScope Pro Software and Cores User Guide www xilinx com 2 15 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Number of Block RAMs As the data depth and data width selections are changed the Number of Block RAMs field n
156. e Tcl string index This means that 100 will first shift 1 into TDI followed by 0 followed by O If you don t like this order make a simple function to reverse your strings before passing to the buffer Optional Arguments All arguments are passed directly to the cable driver endstate state State to navigate into after the shift operation One of TLR RTI SDR Default is SDR device devicenumber Shift bits into and out of devicenumber by padding extra bits IR lengths must be set up correctly to use this argument If no device is specified no padding is done and shifts apply to the entire jtag chain discard Do not return output buffer from the shift This is an optimization to allow ignoring the TDO pin when writing data to the chain Returns Bits shifted out of the JTAG chain If discard option is specified nothing is returned 5 14 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX Examples 1 Shift 32 bits out of device 2 set mydata jtag shiftdr handle constant 0 bitcount 32 device 2 2 Shift bits into chain and end in TLR jtag shiftdr handle buffer 11110000 endstate TLR discard ChipScope Pro Software and Cores User Guide www xilinx com 5 15 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag_scanchain This command is used to scan the JTAG chain for the current device count and an
157. e aa 5 8 xii www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 7 XILINX Jag Opens Laco cose edi ru ee tees a Dao sta ipta ion s apa 5 9 udo c 5 9 Optional Arguments eee ke cia ERAN LEN EPA Pei qeEUA ERES E EOS 5 9 RetutiS i49 ibd a DRE a bale GERE SHE SUN VeRO Roe eed 5 11 Examples PME 5 11 erac M P EE 5 12 o con s gisele Weeder bed aae be auge d bles teet di e ved 5 12 Required Arsuments 2a sch tuations A cbe e s bee eerte eet 5 12 Optional Arpumenhts 2 2 opio ad qur cp e Y RE DERE WE ua 5 12 REUS ccce e A DENEN DONE X Rp EE Rr P See Rr ad 5 12 Examples e cosmos erre er prae bera ra edd eae nes a 5 13 jtae shido c qu ida epiac ques cita 5 14 Synta ke vie Vee E o be RYE tee Theda Vr PU RE EE RR LEE EU 5 14 Required Arsuments ir a sec PII ed eR ted A pe aa 5 14 Optional Arguments eseis e Peces 4m o bec pepe pads bee d hide rn 5 14 REUS Li A PIGNORE 6 Meds EE KG eR E 5 14 Examples P a id lo he he ke ee Yo 5 15 jtag scanchaii o te Le dotem pdt LUE 5 16 Required Arguments eee E rere p3HO RES ie eee 5 16 Ret tnSz2ice ubexedbeee ehe bb RPG ge SEG eb SIS A A 5 16 Examples PME 5 16 jtag Unlock seen c eL UU CU 5 17 Required Arguments verd ree Ree pua EP IR UPS P bane a sa ien 5 17 REUS ri cde ek e e EE ERE VR Ee S Ee e ea 5 17 Examples pda riada nre sry v reu Ra vue lea aane ved dre pa 5 17 JAS VEO p EET 5 18 O bes
158. e for more information ar COMMAND show_config_status 2 INFO Bits 15 0 0001 1111 1110 1100 Bit 15 D RESERVED Bit 14 0 RESERVED Bit 13 0 ID ERROR Bit 12 1 DONE Bit11 1 INIT B Bit 10 1 MODEM2 Bit 9 1 MODEM1 Bit 8 1 MODE MO Bit 7 1 GHIGH B Bit 6 1 GWE Bit 5 1 GTS CFG Bit 4 0 IN ERROR Bit 3 1 DCI MATCH Bit 2 1 DCM LOCK Bit 1 D RESERVED Bit 0 0 CRC ERROR Figure 4 27 Displaying Device Configuration Status For some devices the JTAG instruction register contains status information as well Use Device Show Instruction Register to display this information in the messages window for any device in the JTAG chain Figure 4 28 COMMAND show instruction register 2 INFO Bits 8 0 11 1111 0101 Bit 9 1 Cpubit3 Bit 8 1 Cpubit2 Bit 7 1 Cpubit1 Bit 6 1 Cpubit Bit 5 1 DONE Bit 4 1 Init Complete Bit 3 0 ISC Enabled Bit 2 1 ISC Done Bit 1 0 Always Zero Bit 0 1 Always One Figure 4 28 Displaying Device Instruction Register Status ChipScope Pro Software and Cores User Guide www xilinx com 4 23 UGO29 v7 1 February 16 2005 7 XILINX Chapter 4 Using the ChipScope Pro Analyzer Trigger Setup Window To set up the trigger for a ChipScope Pro ILA or IBA core select Window gt New Unit Windows and the ChipScope Pro core desired Figure 4 29 A dialog box will be displayed for that ChipScope Pro core and you can select the Trigger Setup Waveform Listing Bus Plot an
159. e from the trigger input ports The ILA ATC core uses 4 8 12 16 or 20 external pins to transmit the data A transmit clock pin is also used to synchronize the Agilent TPA with the ILA ATC core The 2x and 4x transmit rates also use internal global clock buffer and clock management resources in the FPGA device Table 1 4 shows how the transmit rate affects the usage of these internal device resources Table 1 4 ILA ATC Clock Resource Utilization Virtex Virtex E Virtex ll Virtex ll Pro Virtex 4 Spartan ll and Spartan llE Spartan 3 and Spartan 3E Transmit Rate Number of Number of Number of Number of BUFGs CLKDLLs BUFGs DCMs 1x 0 0 0 0 2x 1 1 1 1 4x 1 2 2 1 1 12 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX The data is transmitted at 1 2 or 4 times the rate of the CLK port of the ILA ATC core where the maximum CLK port rate is 200 100 and 50 MHz respectively Table 1 5 shows the possible data rate and pin combinations and how they affect the width and depth of the DATA port Table 1 5 ILA ATC Core Capabilities Number of Transmit Max Width of Max Number of Samples Max CLK Port Data Pins Rate DATA Port with timestamps Frequency 4 1x 3 2 097 120 1 048 560 200 MHz 4 2x 5 1 048 560 1048560 100 MHz 4 4x 11 524 280 262 136 50 MHz
160. e lower level hierarchical component from which the net at the current level of hierarchy is driven The source instance does not necessarily describe the originating driver of the net e Source Component The type of the component described by the Source Instance e Base Type The type of the lowest level driving component of the net The base type is either a primitive or black box component All of the net identifiers described above can be filtered for key phrases using the Pattern text box and Filter button Also nets can be sorted in ascending and descending order based on the various net identifiers by selecting the appropriate net identifier button in the column headers of the net selection table Note The net names are sorted in alpha numeric or bus element order whenever possible Common delimiters such as etc are used to identify possible bus element nets ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 3 25 XILINX Chapter 3 Using the ChipScope Pro Core Inserter The tabs for clock data and trigger inputs of the ILA or ILA ATC core appear in the pane at the upper right of the Select Net dialog box If you are selecting nets for an ATC2 core then only the Clock and Data input port categories will appear at the upper right of the Select Net dialog box If multiple trigger or data ports exist there will be multiple sub tabs on the bottom of the Net
161. e match functions e Capture Settings Defines how many samples to capture how many capture windows and the position of the trigger in those windows Each component is expandable and collapsible in the Trigger Setup window To expand click on the desired button at the bottom of the window Figure 4 30 Match Unit I Function Counter gt M microProgAddr nn 3FF exactly one clock cycle S e M1 microProgAddr 360 exactly one clock cycle amp M2 microPortAddr 0_0000 exactly cycle amp M3 microPortDataln OK 2000 9 M4 microPortDataOut 3660 2000 M5 microStrobes xi 9 ME MPA reg 100 000X exactly one clock cycle 9 M7 MP control regs exactly one clock cycle M amp MP control regs exactly one clock cycle M8 microlnterrupts M10 microlnterrupts xoox exactly one clock cycle exactly one clock cycle o M11 sine 3000 3000 2000 3000 2000 Trigger Conditions Capture Settings Figure 4 30 Trigger Setup Window with Only Match Functions Expanded 4 24 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX To collapse click on the button to the left of the expanded section you wish to collapse Figure 4 31 gl Trigger Setup DEV 2 MyDevice2 XC2VP4 UNIT 1 MyiLA1 ILA ee 2 2 2 2 2 2 2 a 4 B Match Unit Function Counter
162. e mode and the TDM rate In STATE mode the width of each data port is equal to ATD pin count TDM rate In TIMING mode the width of each data port is equal to ATD pin count 1 TDM rate since the ATCK pin is used as an extra data pin Pin Parameters The settings in the Individual Pin Settings table control the location I O standard output drive and slew rate of each individual ATCK and ATD pin The output clock ATCK and data ATD pins are instantiated inside the ATC2 core for your convenience This means that although you do not have to manually bring the ATCK and ATD pins through every level of hierarchy to the top level of your design you do need to specify the location and other characteristics of these pins in the Core Generator These pin attributes are then added to the ncf file of the ATC2 core Pin Name The ATC2 core has two types of output pins ATCK and ATD The ATCK pin is used as a clock pin when the capture mode is set to STATE and is used as a data pin when the capture mode is set to TIMING The ATD pins are always used as data pins The names of the pins cannot be changed Pin Loc The Pin Loc column is used to set the location of the ATCK or ATD pin ChipScope Pro Software and Cores User Guide www xilinx com 3 21 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter IO Standard The IO Standard column is used to set the I O standard of each individual ATCK
163. e ro 2 46 IBA PLB Core Trigger Port OptiONS oooococcccoooorrocccnnrrrrna eee 2 46 Selecting the PLB Signal Groups as Trigger Ports nuns 000 c eee eee eee 2 47 Entering the Width of the Trigger Ports 2 49 Selecting the Number of Trigger Match Units lees 2 49 Selecting the Match Unit Type clie n 2 50 Selecting Match Unit Counter Width esses 2 51 Enabling the Trigger Condition Sequencer lees 2 51 Enabling the Storage Qualification Condition oo ooocoocoocorcooroo o o 2 51 Enabling the Trigger Output Port cesses ee 2 51 IBA PLB Core Data Port Options sseeeeeee e 2 52 Selecting the Data Depth siad bd ete de de 2 52 Selecting the Data Type iii esis pe Rete t quee ers Sete d eek e da Rete 2 53 Entering the Data Width oce erbe ee eura ed use pone s 2 53 Selecting the Data Same As Trigger Ports 26 sisse ee 2 54 Number of Block RAMS llle hrs 2 54 Creating Example Templates 2 0 0c eens 2 54 HDL Example Files rcr de e ede d ead ee aid ee don 2 55 Bus Signal Name Example Files cdc cesses 2 55 Batch Mode Generation Argument Example Files eese 2 55 Generating the Core oeste ne Ee en ori een e epe ead nora quen ta 2 56 Using the IBA PLB Core nre ERR ener PESE e PR Rees 2 56 Generating the VIO Cotes 4 eir ERR pen Fe RCRR ADR on qat Rak RC e Ro Re RR 2 57 General VIO Core Options sssssss nen 2 58 Choosing the File
164. e section Setting up a Server Host Connection page 4 16 for more information on how to connect to the server application from the ChipScope Pro Analyzer client application 4 2 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Analyzer Client Interface XILINX Analyzer Client Interface The ChipScope Pro Analyzer client interface consists of four parts e Project tree in the upper part of the split pane on the left side of the window e Signal browser in the lower part of the split pane on the left side of the window e Message pane at the bottom of the window e Main window area Both the project tree signal browser split pane and the Message pane can be hidden by deselecting those options in the View menu Additionally the size of each pane can be adjusted by dragging the bar located between the panes to a new location Each pane can be maximized or minimized by clicking on the arrow buttons on the pane separator bars Project Tree The project tree is a graphical representation of the JTAG chain and the ChipScope Pro cores in the devices in the chain Although all devices in the chain are displayed in the tree only valid target devices Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan ll Spartan IIE Spartan 3 Spartan 3E and their QPro variants can contain ChipScope Pro cores and be operated upon Leaf nodes in the tree appear when further operations are available Fo
165. e waveform printing options in more detail Print Wizard 1 of 3 Horizontal Scaling Time Sample Range Print Signal Names 9 FitTo D Current View First Page Only Page s Wide D Full Range 2 On Each Page E Between vO Cursors Fixed Custom View XO Cursor Values v Show X O Cursor Values Signal Bus Selection E Footer 2 Current View D All v Show Footer Selected Page Setup sess Cancel Figure 4 6 Print Wizard 1 of 3 Horizontal Scaling You can control the amount of waveform data that prints to each column of pages using one of two methods e Fit To Fit the waveform to one or more columns of pages e Fixed Fit a specific number of waveform samples on each column of pages The default fits the entire waveform printout to a single column of pages wide Signal Bus Selection You can control which signals and buses will be present in the waveform printout using one of three methods e Current View Print waveform data for all of the signals and buses in the current view of the waveform window e All Print waveform data for all of the signals and buses available in the entire core unit e Selected Print waveform data for only those signals and buses that are currently selected in the waveform window The default prints waveform data using the Current View method ChipScope Pro Software and Cores User Guide www xilinx com 4 9 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Usi
166. ears and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 42 You can select to either go back and specify different options or click Start Over to generate new cores e ChipScope Pro Core Generator Generate Messages Clock Pin Location AB21 Clock Pin VO Standard LVCMOS25 Clock Pin Drive 24 Clock Pin Slew Rate fast Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilincip atc e200 vhd atc e200 vhd Writing Xatc2 edn Post Processing EDIF netlist Xatc2 edn Generating constraints file Xatc2 ncf Generating CDC file Xatc2 cdc Generating batch mode argument file tatc2 arg ChipScope Pro Core Generator Version 7 1i Build 4 212 895 Example Usage File atc2_xst_example vhd Generating batch mode argument file Xatc2 xst vhdl example arg CORE GENERATION COMPLETE 5 lt Previous Start Over Figure 2 42 ATC2 Core Generation Complete ChipScope Pro Software and Cores User Guide www xilinx com 2 69 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Using the ATC2 Core To instantiate the example ATC2 core HDI files into your design use the following guidelines to connect the ATC2 core port signals to various signals in your design Connect the ATC2 core s CONTROL port signal to an unused control port of the ICON core instance in the design Connect all unuse
167. ed aede 3 21 Core Utilization 10 ii e E AUR A RE EAE ER Rn 3 22 Choosing Net Connections for ILA or ILA ATC Signals ooooooooommm 3 23 Adding Unis ta cc e dS Cx Le CU UL 3 28 Inserting Cores into Netlist 0 6 0 occ eee e 3 28 Managing Project Preferences 1 2 cece een es 3 28 Chapter 4 Using the ChipScope Pro Analyzer Analyzer OVEIVIEW iced eat elas iger Ede rd EREE EEE A Ce PE Rai ds 4 1 Analyzer Server Interface ja es ves tur A ees 4 2 Analyzer Client Interface sce edad dies 4 3 Project tee 5 ce p A AA aod sce e tee ep tt ed 4 3 Signal BfOWSet 5 4e dae ear diede qu pese ted eee da Eee 4 3 Renaming Signals Buses and Triggers Ports ooooocoocooococconcancoo ro 4 3 Adding Removing Signals from Views eeeeeeeeeee eee 4 4 Combining and Adding Signals Into Buses 00 ce cece eee eee 4 4 Reverse Bus Orderilg cesce nis robo a dae a editae up edi gos 4 4 Bus Radices oa Lane Ea ace ee aee a e e ER CER ae eae 4 5 Deleting Bises penei ree ERU pes erster puit De qued dendum dei ad oe bae 4 6 Type and Persistence VIO only oooocooccooccooncocco ee 4 6 Message Panes c csv sedis dines cee pr oe FR ee E Ee ER FERRENT RI ENTER ER IRAE 4 6 Main Window Arta 4 6 x www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 7 XILINX Analyzer Menu Features is crie be pia ERR e e ro eed ear d 4 7 Working with Projects aret eU E etate CIE E
168. elected to be included in the data port If this selection is made then the DATA input port will not be included in the port map of the IBA OPB core This mode conserves CLB and routing resources in the IBA OPB core but is limited to a maximum aggregate data sample word width of 256 bits e DataSeparate from Trigger Figure 2 22 page 2 39 The data port is completely independent of the trigger ports This mode is useful when you want to limit the amount of data being captured ChipScope Pro Core Generator BEE IBA for On Chip Peripheral Bus Data Port Options Data Port Settings Data Depth 1024 y Samples Aggregate Data Width 87 v Data Same As Trigger Number of Block RAMs 6 v Include OPB Control Signals combined port TRIGO width 17 v Include OPB Address Bus port TRIG1 width 32 v Include OPB Data Bus combined port TRIG2 width 32 v Include OPB Protocol Violation Monitor Signals port TRIG3 width 6 Figure 2 23 IBA OPB Core Data Same As Trigger Options 2 40 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core 7 XILINX Entering the Data Width The width of each data sample word stored by the IBA OPB core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However regardless of these
169. ems or by running generate sh ila pro atc f ila atc arg atthe UNIX shell prompt on Linux and Solaris systems Generating the Core After entering the ILA ATC core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 18 You can select to either go back and specify different options or click Start Over to generate new cores ChipScope Pro Core Generator BEE Generate Generating Core Messages External capture data pin 5 location P12 External capture data pin 6 location N12 External capture data pin 7 location R13 External capture clock pin location P13 Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinx ip ila ila Writing Xila edn Post Processing EDIF netlist ila edn Generating constraints file ila ncf Generating CDC file Aila cdc Generating batch mode argument file ila arg ChipScope Pro Core Generator Version 7 1i Build 4 212 895 Example Usage File ila_xst_example vhd Generating batch mode argument file ila xst vhdl example arg CORE GENERATION COMPLETE 4 lt Previous Start Over J Figure 2 18 ILA ATC Core Generation Complete Using the ILA ATC Core To instantiate the example ILA ATC core HDL files into your design use the following
170. enu Features 7 XILINX Storage Condition amp All Data AND Equation OR Equation Match Unit Enable Negate Storage Condition Equation OK Cancel Figure 4 83 Storage Qualification Condition Set to Capture AII Data Storage Condition O All Data 8 AND Equation OR Equation Match Unit Enable MO M1 M2 M3 M4 M5 M6 M7 M8 M8 Storage Condition Equation MO amp amp M4 amp amp M6 amp amp M7 OK Cancel Figure 4 34 Storage Qualification Condition Using Boolean Equation ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 4 27 XILINX Chapter 4 Using the ChipScope Pro Analyzer Match Functions A match function is a definition of a trigger value for a single match unit All the match functions are defined in the Match Functions section of the Trigger Setup window Figure 4 35 One or more match functions will be defined in an equation or sequence in the Trigger Conditions section to specify the overall trigger condition of the ChipScope Pro core E Trigger Setup DEV 2 MyDevice2 XC2VP4 UNIT 1 MyiLA1 ILA o bd E Match Unit Function Value Radix Counter 8 amp MO microProgAddr In Range gt 000 lt 3FF Hex atleast 20 clock cycles mg Mi mic
171. er Data Width LUTs Flip Flops 8 177 171 16 186 187 32 216 221 64 252 287 128 336 425 256 501 675 This example uses a single ILA core with a single trigger port a single basic match unit data same as trigger and 512 data samples Table 1 10 ICON and ILA Core Block RAM Usage in Virtex Il Pro Devices Trigger Data Samples Data Width 54 1024 2048 4096 8192 16384 8 1 1 2 3 5 9 16 1 2 3 5 9 17 32 2 3 5 9 17 33 64 3 5 9 17 33 65 128 5 9 17 33 65 129 256 9 17 33 65 129 257 This example uses a single ILA core with a single trigger port a single basic match unit data same as trigger and 512 data samples Also note that one extra bit per sample is required for the trigger mark e g a trigger data width of 8 bits requires a sample width of 9 bits etc 1 24 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 System Requirements XILINX Synthesis Requirements Users can modify many options in the ILA ILA ATC IBA OPB IBA PLB VIO and ATC2 cores without resynthesizing However after changing selectable parameters such as width of the data port or the depth of the sample buffer the design must be resynthesized with new cores Table 1 11 shows which design changes require resynthesizing Table 1 11 Design Parameter Changes Requiring Resynthesis Design Parameter Change Res
172. er Condition Editor Dialog Box If a trigger sequencer is present in the core the Trigger Condition dialog will have two tabs Boolean and Sequencer When the Boolean tab is active the trigger condition of a Boolean equation of the available match units When the sequencer tab is active the trigger condition is a state machine where each state transition is triggered by a match function being satisfied The Boolean tab of the Trigger Condition dialog box has a table of all the match units Each match unit occupies a row in the table The Enable column indicates if that match unit is part of the trigger condition The Negate column indicates if that match unit should be individually negated Boolean NOT in the trigger condition All the enabled match units can be combined in a Boolean AND or OR operation selectable using the radio buttons below the match unit table The overall equation can also be negated selectable using the Negate checkbox below the table The resulting equation appears in the Trigger Condition Equation pane at the bottom of the window Figure 4 38 Trigger Condition TriggerConditionO Boolean Sequencer 8 AND Equation OR Equation v Negate Whole Equation Match Unit Enable Negate MO vj mI M1 inl M2 L lv Trigger Condition Equation MO a
173. er condition sequencer is a standard Boolean equation trigger condition that can be augmented with an optional trigger sequencer by checking the Enable Trigger Sequencer checkbox A block diagram of the trigger sequencer is shown in Figure 3 8 Match Unit O Match Unit 1 T rigger Match Unit 2 Level 7997 16 Match Unit 15 gt Match Unit O Match Unit 1 Match Unit 2 Match Unit O Match Unit 1 Match Unit 2 Match Unit 15 Match Unit 15 UGO29 trig seq blk diag 081903 Figure 3 8 Trigger Sequencer Block Diagram with 16 Levels and 16 Match Units The trigger sequencer is implemented as a simple cyclical state machine and can transition through up to 16 states or levels before the trigger condition is satisfied The transition from one level to the next is caused by an event on one of the match units that is connected to the trigger sequencer Any match unit can be selected at run time on a per level basis to transition from one level to the next The trigger sequencer can be configured at run time to transition from one level to the next on either contiguous or non contiguous sequences of match function events Enabling the Storage Qualification Condition In addition to the trigger condition the ILA core can also implement a storage qualification condition The storage qualification condition is a Boolean combination of match function events These match function events are detected by the match unit comparators that ar
174. ete 2 43 Selecting the IBA PLB Core 2 44 IBA PLB Core General Options uueeseeeeeeeeeee 2 45 IBA PLB Core Trigger Port Options issues 2 46 IBA PLB Core Data Port Options ooooooooocccocnorccconccoo 2 52 IBA PLB Core Data Same As Trigger Opti0NS ooooooooomo o 2 53 IBA PLB Core Example and Template Options 2 54 ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 xvii XILINX Figure 2 32 IBA PLB Core Generation Complete o oooooocccccccccccc 2 56 Figure 2 33 Selecting the VIO Core 0 0 0 6 occ nee ee 2 57 Figure 2 34 VIO Core General Options sse 2 58 Figure 2 35 VIO Core Example and Template Options 2 60 Figure 2 36 VIO Core Generation Complete o oooooocococcccccccccccccccc 2 61 Figure 2 37 Selecting the ATC2 Core 0 0 0 cece eens 2 62 Figure 2 38 ATC2 Core General Options 0 00 0000 2 63 Figure 2 39 ATC2 Core State Mode Data Capture Options 2 64 Figure 2 40 ATC2 Core Timing Mode Data Capture Options 2 64 Figure 2 41 ATC2 Core Example and Template Options 2 67 Figure 2 42 ATC2 Core Generation Complete ooooc ocococccccccccccccc 2 69 Chapter 3 Using the ChipScope Pro Core Inserter Figure 3 1 Creating a New cdc Source File
175. fied When trigger equals data only the clock and trigger data ports must be specified Double click on the CLOCK PORT label or click on the plus sign next to it to expand as shown in Figure 3 14 No connection has been made so the connection appears in red ChipScope Pro Core Inserter my_design cdc File Edit Help e gt ILA Select Integrated Logic Analyzer Options Trigger Parameters Capture Parameters I Net Connections Net Connections 9 UNIT 9 CLOCK PORT CHO TRIGGER PORTS TRIGO CHO CH1 CH2 CH3 CH4 CH5 CHB CH TRIG1 TRIG2 TRIG3 Modify Connections lt Previous Return to Project Navigator Successfully read project c projectsimy_designiiseimy_design cdc Netlist timestamp changed rebuilding design copy cprojectsimy designtise my design cs ngc gt cprojectsimy designlise ngowny design cs signalbrowser ngo SetDesign my design Figure 3 14 ILA and ILA ATC Net Connections ChipScope Pro Software and Cores User Guide www xilinx com 3 23 UGO029 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter The ATC2 Net Connections tab Figure 3 15 allows you to choose the signals to connect to the ATC2 core The clock and data ports must be specified Double click on the Clock Net label or click on the plus sign next to it to expand as shown in Figure 3 15 No
176. g the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ILA core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex IL Virtex II Pro Virtex 4 Spartan Il Spartan IIE Spartan 3 and Spartan 3E device families including the QPro variants of these families Virtex II is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Entering the Number of Control Ports The ICON core can communicate with up to 15 ILA ILA ATC IBA OPB IBA PLB VIO and ATC2 capture core units at any given time However individual capture core units cannot share their control ports with any other unit Therefore the ICON core needs up to 15 distinct control ports to handle this requirement You can select the number of control ports from the Number of Control Ports pull down list Disabling the Boundary Scan Component Instance The Boundary Scan primitive component for example BSCAN_VIRTEX2 is used to communicate with the JTAG Boundary Scan logic of the target FPGA device The Boundary Scan component extends the JTAG test access port TAP interface of the FPGA device so that up to two internal scan chains can be
177. ger mark e g a trigger data width of 7 bits requires a full sample width of 8 bits etc 2 14 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA Core 7 XILINX Selecting the Data Type The data captured by the ILA trigger port can come from two different source types e Data Same as Trigger Figure 2 10 The data and trigger ports are identical This mode is very common in most logic analyzers since you can capture and collect any data used to trigger the core Individual trigger ports can be selected to be included in the data port If this selection is made then the DATA input port will not be included in the port map of the ILA core This mode conserves CLB and routing resources in the ILA core but is limited to a maximum aggregate data sample word width of 256 bits e DataSeparate from Trigger Figure 2 9 page 2 13 The data port is completely independent of the trigger ports This mode is useful when you want to limit the amount of data being captured e ChipScope Pro Core Generator ILA Data Port Options Data Port Settings Data Depth 1024 xi Samples Aggregate Data Width 156 lv Data Same As Trigger Number of Block RAMs 10 v Include TRIGO port width 32 v Include TRIG1 port width 12 v Include TRIG2 port width 8 v Include TRIG3 port width 8 Y Include TRIG4 port width 8 v Include TRIG5 port width 8 v Includ
178. ger port match units depend on the type of the match unit Six types of match units are supported by the ILA ATC cores Table 2 4 Table 2 4 ILA ATC Trigger Match Unit Types Type Bit Values Match Function pons Description Basic 0 1 X CN o d 8 Can be used for comparing data signals where transition detection is not important This is the most bit wise economical type of match unit Basic OLX REB n ed 4 Can be used for comparing w edges control signals where transition detection e g low to high high to low etc is important Extended 0 1 X E o O LN 2 Can be used for comparing gt lt lt lt address or data signals where magnitude is important Extended 0 1 X R F B 1S O 2 Can be used for comparing w edges gt E C address or data signals where a magnitude and transition detection are important Range 0 1 X O du d 1 Can be used for comparing gt lt lt address or data signals where a in range not range of values is important in range Range 0 1 X R F B E d Sh 1 Can be used for comparing w edges SEE address or data signals where a in range not range of values and transition in range detection are important a Bit values 0 means logical 0 1 means logical 1 X means don t care R means 0 to 1 transition F means 1 to 0 transition and B means any transition b The Bits Per Slice
179. gt cprojectsimy designse ngony design cs signalbrowser ngo SetDesign my design show SignalBrowserDialog Figure 3 17 Specifying Data Connections After specifying the clock trigger and data nets click Next If you are using the Core Inserter in stand along mode a dialog box appears asking if you want to proceed with Core Insertion If Yes the cores are generated inserted into the netlist and an NGO file is created with the EDIF2NGD tool Details of this process can be viewed in the Messages pane at the bottom of the window A Core Generation Complete message in the Messages pane indicates successful insertion of ChipScope cores If you are using the Core Inserter as part of the Project Navigator mode a dialog box appears asking if you want to return to Project Navigator If Yes the Core Inserter settings are saved and you are returned to the Project Navigator tool The actual core generation and insertion processes take place in the proper sequence as deemed necessary by the Project Navigator tool ChipScope Pro Software and Cores User Guide www xilinx com 3 27 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Adding Units Each device can support up to 15 ILA ILA ATC or ATC2 units depending on block RAM availability and unit parameters e Toadd another ILA unit to the project select Edit gt New ILA Unit or go to the ICON Options window by c
180. guidelines to connect the ILA ATC core port signals to various signals in your design e Connect the ILA ATC core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the ILA ATC core s data and trigger port signals to 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process e Make sure the data and trigger source signals are synchronous to the ILA ATC clock signal CLK ChipScope Pro Software and Cores User Guide www xilinx com 2 29 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Generating the IBA OPB Core The ChipScope Pro Core Generator tool provides the ability to define and generate a customized IBA core for monitoring and debugging CoreConnect OPB buses in your HDL designs You can customize the number of OPB masters and slaves as well as the types of OPB signals that you want to use as triggers to your IBA OPB core You can also customize the maximum number of data samples stored by the IBA OPB core and the width of the data samples if different from the trigger ports After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file ncf a signal import file cdc a protocol violation bus token file tok and example HDL code specific to the
181. h or active low e VIO input buses have only one valid type Text e VIO outputs have the following types control types Text ASCII text field Push Button either active high or low Toggle Button Pulse Train synchronous outputs only Single Pulse synchronous outputs only e VIO output buses have two valid types 9 9 9 9 Text Pulse Train synchronous output buses only VIO Bus Signal Activity Persistence The persistence of a signal indicates how long the activity is displayed in the Value Column see Value Column page 4 41 for a description of signal activity If the persistence is Infinite the activity will be displayed in the column forever If the persistence is Long the activity will be displayed in the column for 80 times the sample period If the persistence is Short the activity will be displayed in the column for 8 times the sample period When the time limit on the persistence expires a new activity will be displayed If no activity occurred in the last sample cycle no activity will be displayed in the Value column Bus and Signal Reordering Buses and signals can be reordered in the Waveform window Simply click on a signal or bus and drag it to its new location A red line then appears in the Bus Signal column indicating the potential drop location Cut Copy Paste Delete Signals and Buses Individual signals and buses can be cut copied pasted or deleted using right click menus Right click on a signal
182. he ChipScope Core Inserter is first opened all the relevant fields are completely blank Using the command File New also results in this condition Figure 3 3 ChipScope Pro Core Inserter File Edit Insert Help De gt k DEVICE Select Device Options Design Files SS Input Design Netlist Browse Output Design Netlist Browse Output Directoy Browse Device Settings Device Family Virtex2 lv Use SRL 16s v Use RPMs Figure 3 3 Blank Core Inserter Project Opening an Existing Project To open an existing project select it from the list of recently opened projects or select File Open Project and Browse to the project location After you locate the project you can either double click on it or click Open Saving Projects If a project has changed during the course of a session you will be prompted to save the project upon exiting the Core Inserter You can also save a project by selecting File gt Save To rename the current project or save it to another filename select File Save As type in the new name and click Save ChipScope Pro Software and Cores User Guide www xilinx com 3 5 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Refreshing the Netlist The Core Inserter automatically reloads the design netlist if it detects that the netlist has changed since the last time it was loaded However
183. he ChipScope Pro Core Inserter tool The design is then placed and routed using the Xilinx ISE 7 1i implementation tools Next the user downloads the bitstream into the device under test and analyzes the design with the ChipScope Pro Analyzer software www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Tools Description XILINX The ChipScope Pro Analyzer and ChipScope Pro cores contain many features that Xilinx FPGA designers need for thoroughly verifying their logic Table 1 2 User selectable data channels range from 1 to 256 and the sample buffer sizes range from 256 to 2 million samples Users can change the triggers in real time without affecting their logic The ChipScope Pro Analyzer leads designers through the process of modifying triggers and analyzing the captured data Table 1 2 ChipScope Pro Features and Benefits Feature 1 to 256 user selectable data channels Benefit Accurately captures wide data bus functionality User selectable sample buffers ranging in size from 256 to 2 million samples Large sample size increases accuracy and probability of capturing infrequent events Up to 16 separate trigger ports each with a user selectable width of 1 to 256 channels for a total of up to 4096 trigger channels Multiple separate trigger ports increase the flexib
184. he scale factor is set to 0 1 then the actual displayed bus value will be 0 2 given a precision of 1 The default scale factor is 1 0 e Offset is a constant value that will be added to the scaled bus value The default offset is 0 e Precision is the number of decimal places to display after the decimal point The default precision is 0 Token Tokens are string labels that are defined in a separate ASCII file and can be assigned to a particular bus value These labels can be useful in applications such as address decoding and state machines The token file tok extension has a very simple format and can be created or edited in any text editor An example token file is provided in the token directory in the ChipScope Pro install path Figure 4 1 B token sample tok Notepad Eile Edit Format View Help nS chipscope Example Token File Tokens are in the form NAME VALUE where NAME is the token name and VALUE is the token value Chex binary or decimal Ld values are hex by default To specify a radix for the value append Mb binary Nu Cunsigned decimal h Chex to the value so valid token definitions would be MEM_WRITE c5 h MEM_READ 1101 b EEE EEE EEE EEE EEE EE EEE EE FILE_VERSION 1 0 0 If you want the default token when no matches are found to be something other than HEX uncomment the following line and set the amp DEFAULT TOKEN to something useful G DEFAULT_TOKEN Begi
185. here m is the slave number 0 to 15 TRIG_IN User defined Generic trigger input Entering the Width of the Trigger Ports The individual trigger ports are buses that are made up of individual signals or bits The number of bits used to compose a trigger port is called the trigger width Most of the trigger port signal groups for the IBA PLB have predefined widths and are not user editable However the width of generic trigger port can be set independently using the Trigger Width field for that group The range of values that can be used for the generic trigger port width is 1 to 256 Selecting the Number of Trigger Match Units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form what is called the overall trigger condition event that is used to control the capturing of data Each trigger port can be connected to 1 to 16 match units by using the Match Units pull down list Selecting one match unit conserves resources while still allowing some flexibility in detecting trigger events Selecting two or more trigger match units allows a more flexible trigger condition equation to be a combination of multiple match units However increasing the number of match units per trigger port also increases the usage of logic resources accordingly Note The aggregate number of match units used in a single
186. here m is the slave number 0 to 63 OPB_PV 6 OPB protocol violation monitor signals TRIG_IN User defined Generic trigger input Entering the Width of the Trigger Ports The individual trigger ports are buses that are made up of individual signals or bits The number of bits used to compose a trigger port is called the trigger width Most of the trigger port signal groups for the IBA OPB have predefined widths and are not user editable However the width of generic trigger port can be set independently using the Trigger Width field for that group The range of values that can be used for the generic trigger port width is 1 to 256 Selecting the Number of Trigger Match Units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form the overall trigger condition event that is used to control the capturing of data Each trigger port can be connected to 1 to 16 match units by using the Match Units pull down list Selecting one match unit conserves resources while still allowing some flexibility in detecting trigger events Selecting two or more trigger match units allows a more flexible trigger condition equation to be a combination of multiple match units However increasing the number of match units per trigger port also increases the usage of logic resources accordingly Note The aggregate number of match units u
187. hich will bring up the match unit counter dialog box Figure 4 36 Match Function M7 Match Events occurring in exactly v 1 1 65536 clock cycles OK Cancel Reset Figure 4 36 Setting up the Match Counter The Counter field selects how many match function events must occur for the function to be satisfied e If occurring in exactly n clock cycles is selected then n contiguous or n noncontiguous events will satisfy the match function counter condition e If occurring in at least n clock cycles is selected then n contiguous or n noncontiguous events will satisfy the match function counter condition and will remain satisfied until the overall trigger condition is met e If occurring for at least n consecutive cycles is selected then n contiguous events will satisfy the match function counter condition and will remain satisfied until the overall trigger condition is met or the match function value is no longer satisfied Note When the overall trigger condition consists of at least one match unit function that has a counter set to either Occurring in at least n cycles or Lasting for at least n consecutive cycles the Window Depth or Samples Per Trigger setting cannot be less than eight samples This is due to the pipelined nature of the trigger logic inside the ILA ILA ATC IBA OPB or IBA PLB cores Trigger Conditions A trigger condition is a Boolean equation or sequence of one or more match func
188. hird screen in the Core Generator that is used to set up the of the IBA OPB core trigger port options Figure 2 21 e ChipScope Pro Core Generator IBA for On Chip Peripheral Bus Trigger Port Options Trigger Input and Match Unit Settings Number of Trigger Ports Used 4 Number of Match Units Used 7 OPB Control Signals combined Trigger Width 17 Match Type Basic w edges ivi Match Units 4 v Bit Values 0 1 X R F B Counter Width Disabled Functions lt gt OPB Address Bus 4 Pe gy Trigger Width 32 Match Type Extended w edges v PE vj Match Units 1 v Bit Values 0 1 X R F B Trigger Condition Settings v Enable Trigger Sequencer Max Number of Sequencer Levels 16 Storage Qualification Condition Settings v Enable Storage Qualification Trigger Output Settings v Enable Trigger Output Port lt Previous Next Figure 2 21 IBA OPB Core Trigger Port Options 2 34 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core XILINX Selecting the OPB Signal Groups as Trigger Ports The OPB bus is divided into logical signal groups as described in Table 2 9 which spans multiple pages You can select any of these OPB signal groups as trigger ports by selecting the checkbox to the left of each group Note that the IBA OPB core is limited to either 16 trigger ports o
189. ically create an ILA core and display the Select Logic Analyzer Options window To add a new ATC2 core instead of an ILA core click either New ATC2 Unit To add a new ILA ATC core select the Edit New ILA ATC Unit menu option ChipScope Pro Core Inserter my design cdc File Edit Help Select Integrated Controller Options Parameters C Disable JTAG Clock BUFG Insertion lt Previous xt New ILA Unit New ATC2 Unit lessages ChipScope Loading CDC project cprojectsimy_designliselmy_design cde Successfully read project caprojectsimy_designtiselmy_design cdc 1 Figure 3 6 ICON Options ChipScope Pro Software and Cores User Guide www xilinx com 3 9 UG029 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Choosing ILA or ILA ATC Trigger Options and Parameters Notice in Figure 3 7 that a new ILA unit has been created in the device hierarchy on the left The next step is to set up the ILA unit Figure 3 7 shows a sample of the first tab in the ILA options and parameters sequence The first tab sets up the trigger options for the ILA or ILA ATC core ChipScope Pro Core Inserter my design cdc File Edit Help B gt ILA Select Integrated Logic Analyzer Options Trigger Parameters Capture Parameters Net Connections Trigger Input and Match Unit Settings Number of Input Trigger Ports 4 ly Number of Match Units Used 4
190. ility of event detection and reduce the need for sample storage Up to 16 separate match units per trigger port up to 16 total match units for a total of 16 different comparisons per trigger condition Multiple match units per trigger ports increase the flexibility of event detection while conserving valuable resources All data and trigger operations are synchronous to the user clock at rates over 300 MHz Capable of high speed trigger event detection and data capture Trigger conditions implement either a boolean equation or a trigger sequence of up to 16 match functions Can combine up to 16 trigger port match functions using a boolean equation or a 16 level trigger sequencer Data storage qualification condition implements a boolean equation of up to 16 match functions Can combine up to 16 trigger port match functions using a boolean equation to determine which data samples will be captured and stored in on chip memory Trigger and storage qualification conditions are in system changeable without affecting the user logic No need to single step or stop a design for logic analysis Easy to use graphical interface Guides users through selecting the correct options Up to 15 independent ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 cores per device Can segment logic and test smaller sections of a large design for greater accuracy Multiple trigger settings Records duration and numbe
191. imum output clock frequency as well as the transmit rate If the transmit rate is 1x then the maximum CLK port frequency is 200 MHz If the transmit rate is 2x then the maximum CLK port frequency is 100 MHz Finally if the transmit rate is 4x then the maximum CLK port frequency is 50 MHz ChipScope Pro Software and Cores User Guide www xilinx com 2 25 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Clock Resource Utilization The ILA ATC core will use dedicated clock resources if the transmit rate is 2x or 4x The number of clock resources required by the ILA ATC core is shown in Table 2 5 Table 2 5 ILA ATC Clock Resource Utilization Virtex Virtex E Virtex ll Virtex ll Pro Spartan ll and Spartan IIE Virtex 4 Spartan 3 and Spartan 3E b Number of Number of Number of Rate umber o umber o umber o BUFGs CLKDLLs BUFGs Number of DCMs 1x 0 0 0 0 2x 1 1 1 1 4x 1 2 2 1 Number of Data Pins The ILA ATC core can use 4 8 12 16 or 20 output data pins for external capture Output Buffer Type You can select the type of output buffer used for the output clock and data pins The types of output data buffers supported by the ILA ATC cores depend on the device family Table 2 6 Table 2 6 ILA ATC Output Buffer Types by Device Family Virtex ll Virtex ll Pro Buffer Type Nin i
192. in Count The ATC2 core can implement any number of ATD output pins in the range of 4 through 128 3 20 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features XILINX Endpoint Type The Endpoint Type setting is used to control whether single ended or differential output drivers are used on the ATCK and ATD output pins All ATCK and ATD pins must use the same driver endpoint type Signal Bank Count The ATC2 core contains an internal run time selectable data signal bank multiplexer The Signal Bank Count setting is used to denote the number of data input ports or signal banks the multiplexer will implement The valid Signal Bank Count values are 1 2 4 8 16 32 or 64 TDM Rate The time division multiplexing TDM rate is used to increase the amount of data transmitted over each data pin by as much as 200 percent The ATC2 core does not use on chip memory resources to store the captured trace data Instead it transmits the data to be captured by an Agilent logic analyzer that is attached to the FPGA pins using a special probe connector The data can be transmitted out the device pins at the same rate as the incoming DATA port TDM rate 1x or twice the rate as the DATA port TDM rate 2x The TDM rate can be set to 2x only when the capture mode is set to State Data Width The width of each input data port of the ATC2 core depends on the captur
193. in the implementation flow For more information on how the Project Navigator and the Core Inserter are integrated refer to the Project Navigator section of the Xilinx ISE Software Manuals http support xilinx com support software manuals htm ChipScope Definition and Connection Source File To use the ChipScope Pro Core Inserter tool to insert ChipScope cores into a design processed by the Xilinx ISE 7 1i Project Navigator tool follow these steps 1 Add the definition and connection file cdc to the project and associate it with the appropriate design module a Tocreatea new cdc file select Project New Source then select ChipScope Definition and Connection File and give the file a name Figure 3 1 page 3 2 Click through the remaining dialog boxes using the default settings as needed Note The ChipScope Definition and Connection File source type is only listed if Project Navigator 7 1i detects a ChipScope Pro 7 1i installation the respective versions must match ChipScope Pro Software and Cores User Guide www xilinx com 3 1 UG029 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter New Source BMM File Su ChipScope Definition and Connection U Implementation Constraints File X IP CoreGen amp Architecture Wizard m MEM File my_design cde Eile Name Schematic E State Diagram Location Test Bench Waveform User Document y Verilog Module Veri
194. individual data port from 128 to 256 bits Supports both asynchronous timing and synchronous state capture modes Supports any valid I O standard drive strength and output slew rate on each output data pin on an individual pin by pin basis Supports any Agilent probe connection technology for more information please refer to http www agilent com find softtouch The maximum number of data probe points available at run time is calculated as 32 data ports 128 bits per data port 2x TDM 8192 probe points ATC2 Core Data Capture and Run Time Control The external Agilent logic analyzer is used to trigger on and capture the data that passes through the ATC2 core This allows you to take full advantage of the complex triggering deep trace memory and system level data correlation features of the Agilent logic analyzer as well as the increased visibility of internal design nodes provided by the ATC2 core The Agilent logic analyzer is also used to control the run time selection of the active data port by communicating with the ATC2 core via a JTAG port connection as shown in Figure 1 4 ChipScope Pro Software and Cores User Guide www xilinx com 1 23 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction ICON and ILA Core Resource Usage Table 1 9 and Table 1 10 show the ICON core and ILA core resource utilization Table 1 9 ICON and ILA Core CLB Usage in Virtex Il Pro Devices Trigg
195. ing the target device s then jumpers on these signals are required to disable these sources preventing contention with the download cable e If using the Parallel Cable III download cable then Vcc 2 5V 5 0V and GND headers must be available for powering the Parallel Cable III cable e If using the Parallel Cable IV MultiPRO or Platform Cable USB download cable then VREF 1 5 5 0V and GND headers must be available for connecting to the Parallel Cable IV cable e If using the Agilent TPA download cable a specially defined connector is required as described in the companion Agilent document called Deep Storage with Xilinx ChipScope Pro and Agilent Technologies FPGA Trace Port Analyzer which is available for download at http www xilinx com ise verification cspro agilent brochure pdf Host System Requirements for Windows 2000 XP The ChipScope Pro Core Generator ChipScope Pro Core Inserter and ChipScope Pro Analyzer client and server modes tools run on PC systems running the Microsoft Windows operating system and meet the requirements outlined in Table 1 13 Table 1 13 PC System Requirements for ChipScope Pro 7 1i Tools OS Version Memory Java Environment Windows 2000 512 MB Java Run time Environment version 1 5 0 b64 SP2 or later automatically included in ChipScope Pro 7 1i lati Windows XP 512 MB software installation Professional Host System Requirements for Linux The ChipScope Pro Core Generat
196. ings Connection Settings UA ILA ATC External Capture Settings Transmit Rate 1x v Max CLK port frequency 200 MHz Number of Data Pins vj Number of DCMs Used 0 Output Buffer Type LVCMOS 2 5 24mA Fast w Number of BUFGs Used 0 Clock Pin Location lag21 Data Pin Locations Pin hayas Pin 1 v22 Pin 2 v22 Pin3 54 Pina ya Pins jg Pine azz Pin fra Data Port Settings Data Width 1 to 7 7 Data Depth Up to 2097120 samples Sample On Rising w Clock Edge lt Previous Next gt Remove Unit Lo lessages Successfully read project c projectsimy_designiiseimy_design cdc Netlist timestamp changed rebuilding design copy c projectsimy_designliseimy_design_cs ngc gt cprojectsimy designlise ngowny design cs signalbrowser ngo SetDesign my design show SignalBrowserDialog i Figure 3 11 ILA ATC Core Data Settings Transmit Rate The ILA ATC core does not use on chip memory resources to store the captured trace data Instead it transmits the data to be captured to an Agilent E5904B TPA that is attached to a special connector via FPGA device pins The data can be transmitted out the device pins at the same rate as the incoming DATA port transmit rate 1x twice the rate as the DATA port transmit rate 2x or four times the DATA port rate transmit rate 4x 3 16 www xilinx com ChipScope
197. ipScope Pro Core Generator IBA for On Chip Peripheral Bus Data Port Options Data Port Settings Data Depth 1024 M Samples Data Width 32 _ Data Same As Trigger Number of Block RAMs 3 mm Previous Figure 2 22 IBA OPB Core Data Port Options Selecting the Data Depth The maximum number of data sample words that the IBA OPB core can store in the sample buffer is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the IBA OPB unit For the Virtex II Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E device families including the OPro variants of these families you can set the data depth to one of six values Table 2 2 page 2 14 For the Virtex Virtex E Spartan Il and Spartan IIE device families including the QPro variants of these families you can set the data depth to one of five values Table 2 3 page 2 14 ChipScope Pro Software and Cores User Guide www xilinx com 2 39 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting the Data Type The data captured by the IBA OPB trigger port can come from two different source types e Data Same as Trigger Figure 2 23 The data and trigger ports are identical This mode is very common in most logic analyzers since you can capture and collect any data that is used to trigger the core Individual trigger ports can be s
198. is driven from the JTAG cable The input values are read back periodically and displayed in the ChipScope Pro Analyzer e Synchronous inputs These are sampled using the design clock The input values are read back periodically and displayed in the ChipScope Pro Analyzer e Asynchronous outputs These are defined by the user in the ChipScope Pro Analyzer and driven out of the core to the surrounding design A logical 1 or 0 value may be defined for individual asynchronous outputs e Synchronous outputs These are defined by the user in the ChipScope Pro Analyzer synchronized to the design clock and driven out of the core to the surrounding design A logical 1 or 0 may be defined for individual synchronous outputs Pulse trains of 16 clock cycles worth of 1 s and or 0 s may also be defined for synchronous outputs Activity Detectors Every VIO core input has additional cells to capture the presence of transitions on the input Since the design clock will most likely be much faster than the sample period of the Analyzer it s possible for the signal being monitored to transition many times between successive samples The activity detectors capture this behavior and the results are displayed along with the value in the ChipScope Pro Analyzer In the case of a synchronous input activity cells capable of monitoring for asynchronous and synchronous events are used This feature can be used to detect glitches as wel
199. ith the Design THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life supp
200. ition The storage qualification condition can consist of a Boolean AND or OR equation of up to 16 match unit functions Note The storage qualification condition is not available on the ILA ATC core www xilinx com 1 5 2 XILINX Chapter 1 Introduction Table 1 3 Trigger Features of the ILA and ILA ATC Cores Continued Feature Choice of Match Unit Types Description The match unit connected to each trigger port can be one of the following types e Basic comparator Performs and lt gt comparisons Compares up to 8 bits per slice e Basic comparator w edges Performs and lt gt comparisons Detects high to low and low to high bit wise transitions Compares up to 4 bits per slice e Extended comparator Performs lt gt gt gt lt and lt comparisons Compares up to 2 bits per slice e Extended comparator w edges e Performs lt gt gt gt lt and lt comparisons Detects high to low and low to high bit wise transitions Compares up to 2 bits per slice e Range comparator Performs lt gt gt gt lt lt in range and not in range comparisons Compares 1 bit per slice e Range comparator w edges e Performs lt gt gt gt lt lt in range and not
201. ively The Tools section Figure 3 18 contains settings for the command line arguments used by the Core Inserter to launch the EDIF2NGD tool Edit Preferences External Tool Configuration ISE Integration Edif2Ngd Miscellaneous Command edif2ngd Browse Arguments ox Cancel Figure 3 18 Core Inserter Tools Preference Settings 3 28 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX The ISE Integration section Figure 3 19 contains settings that affect how the Core Inserter integrates with the Xilinx ISE Project Navigator tool When ISE integration is enabled the default the Core Inserter automatically searches the current working directory for ISE temporary netlist directory called _ngo If a valid ISE ngo directory is found the Core Inserter project will be set up automatically to overwrite the intermediate NGD files of the ISE project with those produced by the Core Inserter The ISE Integration preferences can be set by the user to prompt the user before overwriting any intermediate NGD files Edit Preferences Tools Xilinx Foundation ISE Integration Options Miscellaneous v Enable Foundation ISE Project Navigator Integration When Replacing ISE NGD File 2 Prompt then Backup Backup but Do Not Prompt OK Cancel Figure 3 19 Core Inserter ISE Integration Preference Settings Th
202. ividually selectable via the right click menu Note The activity arrow will be displayed in black if the activity is synchronous and red if it is asynchronous You can choose the VIO signal bus value type by right clicking on the signal or bus and selecting the Type menu choice as shown in Figure 4 48 El Console DEV 2 MyDevice2 XC2VP4 UNIT 0 MyVIOO VIO mm pj Bus Signal Value System Reset System Statu_ Rename Type gt Text Field tivity Push Button ERE Add to Bus gt i Toggle Button Get Lock Rev B Pulse Train Li Single Pulse Ready Cmd Ready Copy Cut Buffer Re SACF Sector SACF Sector Remove From Viewer Sector Buffej Clear All Sector Buffer Read Strobe Sector Buffer Read Data 7 0 Directory Entry Offset 9 Directory Entry Read Strobe Edit Run 9 Directory Entry Hame po0000000000 9 SACF MPU Address 7 0 SACF MPU Read Strobe SACF MPU Data 7 0 Sine Wave Select 1 0 SACF CFGADDR 2 0 Reconfigure Strobe ILA Trigger Output 4 pr Read Inputs p output r Activity Display Key Read Period 250 ms Update Static pa aue Clear All Activity Reset All Outputs Green Inputs Blue Figure 4 48 The Type Selection Menu ChipScope Pro Software and Cores User Guide www xilinx com 4 41
203. ize the number of PLB masters and slaves as well as the types of PLB signals that you want to use as triggers to your IBA PLB core You can also customize the maximum number of data samples stored by the IBA PLB core and the width of the data samples if different from the trigger ports After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file ncf a signal import file cdc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate either an ICON ILA ILA ATC IBA OPB IBA PLB VIO or ATC2 core Select IBA PLB Integrated Bus Analyzer for Processor Local Bus and click Next Figure 2 26 e ChipScope Pro Core Generator ChipScope Pro Core Generator Core Type Selection Select Core Type To Generate ICON Integrated Controller 2 ILA Integrated Logic Analyzer D ILA ATC Integrated Logic Analyzer with Agilent Trace Core D IBA OPB Integrated Bus Analyzer for On Chip Peripheral Bus 8 IBA PLB Integrated Bus Analyzer for Processor Local Bus D VIO Virtual Input Output Core O ATC2 Agilent Trace Core 2 Figure 2 26 Selecting the IBA PLB Core 2 44 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA PLB Core 7 XILINX
204. ken file iba opb pv errors tok Generating CDC file iba opb cdc Generating batch mode argument file iba opb arg ChipScope Pro Core Generator Version 7 11 Build 4 212 895 Example Usage File iba_opb_xst_example vhd Generating batch mode argument file iba opb xst vhdl example arg CORE GENERATION COMPLETE Previous Figure 2 25 IBA OPB Core Generation Complete Using the IBA OPB Core To instantiate the example IBA OPB core HDL files into your design use the following guidelines to connect the IBA OPB core port signals to various signals in your design e Connect the IBA OPB core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the IBA OPB core s data trigger and OPB port signals to 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process e Make sure the data and trigger source signals are synchronous to the IBA OPB clock signal OPB_CLK ChipScope Pro Software and Cores User Guide www xilinx com 2 43 UGO29 v7 1 February 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator Generating the IBA PLB Core The ChipScope Pro Core Generator tool provides the ability to define and generate a customized IBA core for monitoring and debugging CoreConnect PLB buses in your HDL designs You can custom
205. l as synchronous transitions on the synchronous input signal Pulse Trains Every VIO synchronous output has the ability to output a static 1 a static 0 or a pulse train of successive values A pulse train is a 16 clock cycle sequence of 1 s and 0 s that drive out of the core on successive design clock cycles The pulse train sequence is defined in the ChipScope Pro Analyzer and is executed only one time after it is loaded into the core 1 22 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX ATC2 Core The Agilent Trace Core 2 ATC2 is a customizable debug capture core that is specially designed to work with the latest generation Agilent logic analyzers The ATC2 core provides external Agilent logic analyzers access to internal FPGA design nets as shown in Figure 1 4 ATC2 Agilent Logic Analyzer Probes s syueg Ze O i JoyeuU0D eqold LPT or USB JTAG Cable ICON Core UG029_atc2_block_diagram_020904 Figure 1 4 ATC2 Core and System Block Diagram Data Path Description The data path of the ATC2 core consists of Up to 32 run time selectable input data ports that connect to the user s FPGA design Up to 128 output data pins that connect to an Agilent logic analyzer s probe connectors Optional 2x time division multiplexing TDM available on each output data pin that can be used to double the width of each
206. l is a shell program that is used to run Tcl scripts Tcl JTAG requires the Tcl shell that is included in the Xilinx ISE 7 1i tool installation XILINX bin nt xtclsh exe ChipScope Pro Software and Cores User Guide www xilinx com 1 1 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction The ChipScope Pro Analyzer tool supports the following download cables for communication between the PC and the devices in the JTAG Boundary Scan chain Platform Cable USB Parallel Cable IV Parallel Cable III MultiPRO JTAG mode only MultiLINX JTAG mode only Agilent E5904B Option 500 FPGA Trace Port Analyzer Agilent E5904B TPA Host Computer with ChipScope Pro Software ChipScope Pro Target Device Under Test User User Function Function User M Function ICON Pro Bansa JTAG Parallel Cable Connections f Nts Board Under Test cs_pro_sys_blk_diag Figure 1 1 ChipScope Pro System Block Diagram Figure 1 1 shows a block diagram of a ChipScope Pro system Users can place the ICON ILA ILA ATC IBA OPB IBA PLB VIO and ATC2 cores collectively called the ChipScope Pro cores into their design by generating the cores with the ChipScope Pro Core Generator and instantiating them into the HDL source code You can also insert the ICON ILA ILA ATC and ATC2 cores directly into the synthesized design netlist using t
207. le file for example vio arg by selecting the Generate Batch Mode Argument Example File arg checkbox The vio arg file is used with the command line program called generate The vio arg file contains all of the arguments necessary for generating the VIO core without having to use the ChipScope Pro Core Generator GUI tool Note A VIO core can be generated by running generate exe vio f vio argatthe command prompt on Windows systems or by running generate sh vio f vio arg atthe UNIX shell prompt on Linux and Solaris systems Generating the Core After entering the VIO core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 36 You can select to either go back and specify different options or click Start Over to generate new cores eu ChipScope Pro Core Generator DER Generate Generating Core Messages SRLT6 Type SRLCTBIE Synchronous Input Port Width 10 Synchronous Output Port Width 32 Asynchronous Input Port Width 2 Asynchronous Output Port Width 5 Clock Edge Used for Sampling rising edge Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinx ip vio vio Writing Wwio edn Post Processing EDIF netlist Wwio edn Generating constraints file wio ncf Generating batch mode argument file vio arg
208. le still allowing some flexibility in detecting trigger events Selecting two or more trigger match units allows a more flexible trigger condition equation to be a combination of multiple match units However increasing the number of match units per trigger port also increases the usage of logic resources accordingly Note The aggregate number of match units used in a single ILA core cannot exceed 16 regardless of the number of trigger ports used 2 10 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA Core XILINX Selecting the Match Unit Type The different comparisons or match functions that can be performed by the trigger port match units depend on the type of the match unit Six types of match units are supported by the ILA cores Table 2 1 which spans multiple pages Table 2 1 ILA Trigger Match Unit Types Type Bit Values Match Function pour Description Basic 0 1 X C NL o d 8 Can be used for comparing data signals where transition detection is not important This is the most bit wise economical type of match unit Basic OLX REB n ed 4 Can be used for comparing w edges control signals where transition detection e g low to high high to low etc is important Extended 0 1 X ro 2 Can be used for comparing gt lt lt lt address or data signals where magnitude is important Extended 0 1 X R F B E ST 2 Can be used for comp
209. licking on ICON in the tree on the left pane Figure 3 6 page 3 9 and clicking the New ILA Unit button e To add another ILA ATC unit to the project select Edit New ILA ATC Unit or go to the ICON Options window by clicking on ICON in the tree on the left pane Figure 3 6 page 3 9 and clicking the New ILA ATC Unit button e To add another ATC2 unit to the project select Edit New ATC2 Unit or go to the ICON Options window by clicking on ICON in the tree on the left pane Figure 3 6 page 3 9 and clicking the New ATC2 Unit button You can set up the parameters for the additional units by using the same procedure as described above Inserting Cores into Netlist The core insertion step can be invoked by selecting the Insert Insert Core menu option or by clicking Insert Core on the toolbar Note f you are using the ChipScope Pro Core Inserter flow in the Xilinx ISE 7 1i Project Navigator tool click Return to Project Navigator instead of selecting the Insert Insert Core option The insertion of the cores will happen automatically as part of the Translate process in the Project Navigator tool Refer to Using the Core Inserter with ISE Project Navigator page 3 1 for more details Managing Project Preferences The preference settings are organized into three categories Tools ISE Integration and Miscellaneous These preference settings are shown in Figure 3 18 Figure 3 19 page 3 29 and Figure 3 20 page 3 29 respect
210. log Test Fixture VHDL Library VHDL Module E VHDL Package IAEA C projects my_design ise sv amp IV Add to project Cancel Help Figure 3 1 Creating a New cdc Source File b To add an existing cdc file select Project Add Source or Project Add Copy of Source then browse for the existing cdc file When prompted associate the cdc file with the appropriate top level design module The cdc file should now be displayed in the Sources in Project window underneath the associated design module Figure 3 2 tix Sources in Project El my design ise Ed xc2vp 7 g456 Mm my_design virtex src my_design vhd U Astc my_design uct ny_design cde S EEES 7 sine_cosine sl B Module View t1 Snapshot D Library View Figure 3 2 The cdc Source File 2 To create the ChipScope Pro Cores and complete the signal connections double click the cdc file in the Sources in Project window This runs the Synthesis if applicable and Translate processes as necessary and then opens the cdc file in the ChipScope Pro Core Inserter tool 3 Modify the cores and connections in the Core Inserter tool as necessary as shown in the section called ChipScope Pro Core Inserter Features page 3 5 then close the Core Inserter tool 4 When the associated top level design is implemented in Project Navigator the ChipScope Pro cores are automatically inserted into the
211. ltiple capture core port signals 4 Inthelower right part of the Select Net dialog box click the Make Connections button to make a connection between the selected nets and capture core inputs Use the Remove Connections button to remove any existing connections Use the Move Nets Up and Move Nets Down buttons to reorder the position of any selected connection Once the desired net connections have been made click OK to return to the main Core Inserter window 3 26 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX All the trigger and data nets must be chosen in this fashion After you have chosen all the nets for a given bus the ILA ILA ATC or ATC2 bus name changes from red to black see Figure 3 17 ChipScope Pro Core Inserter my design cdc File Edit Help E e gt ILA Select Integrated Logic Analyzer Options Trigger Parameters Capture Parameters Net Connections Net Connections UNIT CLOCK PORT CHO CLK BUFGP TRIGGER PORTS TRIGO CHO fcount 0 gt CH1 fcount 1 gt CH2 count 27 CH3 icount 3 CH4 fcount lt 4 gt CHS fcount lt 5 gt CHE fcount 6 gt CH7 counts TRIG1 TRIG2 TRIG3 Modify Connections lt Previous Return to Project Navigator Netlist timestamp changed rebuilding design copy ciprojectsimy_designliselmy_design_cs ngc
212. ly supports the single window capture mode Single Window Capture Mode In Single Window capture mode the entire sample buffer is viewed as a single sample window A single trigger condition event i e a Boolean combination of the individual trigger match unit events is used to collect enough data to fill the entire sample buffer The depth of the sample windows can be up to two million samples The trigger position can be set to the beginning of the sample window trigger first then collect or at the end of the sample window collect until the trigger event or anywhere in between Trigger Marks The data sample in the sample window that coincides with a trigger event is tagged with a trigger mark This trigger mark tells the ChipScope Pro Analyzer the position of the trigger within the window This trigger mark consumes one extra bit per sample in the sample buffer Timestamps The Agilent TPA JTAG cable can record timestamps along with each of the samples captured by the ILA ATC core These timestamp values are measured from the first sample of the buffer and are displayed in nanoseconds in the various data views within the ChipScope Pro Analyzer When timestamps are enabled the maximum number of data samples is limited to the values shown in Table 1 5 page 1 13 Data Port The data port of the ILA ATC core is used to capture data and transmit it to the Agilent TPA using external pins The ILA ATC data port are always separat
213. matically filled in initially Figure 3 4 shows a project with input and output files specified ChipScope Pro Core Inserter File Edit Insert Help DOS lt gt DEVICE Select Device Options Design Files Input Design Netlist fc projectsimy_designimy_design edn Browse f Output Design Netlist lc Aprojectsmy designimy design ila edn Browse Output Directory lc Aprojectsimy design Browse Device Settings Device Family Virtex2 v Use SRL 16s v Use RPMs Figure 3 4 Core Inserter Project with Files Specified Note When the Core Inserter is invoked from the Project Navigator tool the Input Design Netlist Output Design Netlist Output Directory and Device Family fields are automatically filled in Figure 3 5 page 3 8 In this case these fields can only be changed by the Project Navigator tool and cannot be modified directly in the Core Inserter ChipScope Pro Software and Cores User Guide www xilinx com 3 7 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter ChipScope Pro Core Inserter my design cdc File Edit Help YH lt DEVICE Select Device Options Design Files Input Design Netlist Output Design Netlist Output Directory Device Settings Device Family v Use SRL 16s lv Use RPMs Messages ChipScope Loading CDC project cprojectsimy designtisewny design cd
214. meout OPB Timeout active with no Mx select 33 111111 N A No errors a Refer to Chapter 8 of the OPB Bus Functional Model Toolkit User s Manual document from IBM for more information on these CoreConnect OPB errors The protocol violation monitor detects and reports any errors that occur on the OPB bus The error is reported as a 6 bit priority encoded value that can be used as both trigger and data to the IBA OPB core Priority 1 is the highest priority error and masks any other lower priority errors etc IBA OPB Trigger Input Logic The IBA core for the IBM CoreConnect On Chip Peripheral Bus IBA OPB is used to monitor the CoreConnect OPB bus of embedded MicroBlaze soft processor or Virtex II Pro and Virtex 4 FX PowerPC 405 hard processor systems Up to 16 different trigger groups can be monitored by the IBA OPB core at any given time The OPB signal groups that can be monitored are described in Table 1 7 page 1 17 which spans multiple pages The IBA OPB core can also implement the same trigger and storage qualification condition equations as the ILA core These features are described in the section called ILA Trigger Input Logic page 1 5 IBA OPB Trigger Output Logic The IBA OPB core implements a trigger output port called TRIG OUT The TRIG OUT portis the output of the trigger condition that is set up at run time using the ChipScope Pro Analyzer The latency of the TRIG OUT port relative to the input trigger
215. mount of latency depending on the core type e ILA core 10 clock cycles e ILA ATC core 10 clock cycles e IBA OPB core 15 clock cycles e IBA PLB core 10 clock cycles The shape level or pulse and sense active high or low of the trigger output can be controlled at run time Using Multiple Trigger Ports The ability to monitor different kinds of signals and buses in the design requires the use of multiple trigger ports For example if you are instrumenting an internal system bus in your design that is made up of control address and data signals then you could assign a separate trigger port to monitor each signal group as shown in Figure 1 3 If you connected all of these different signals and buses to a single trigger port you would not be able to monitor for individual bit transitions on the CE WE and OE signals while looking for the Address bus to be in a specified range The flexibility of being able to choose from different types of match units allows you to customize the ILA cores to your triggering needs while keeping resource usage to a minimum ChipScope Pro Software and Cores User Guide UGO029 v7 1 February 16 2005 www xilinx com 1 7 XILINX Chapter 1 Introduction Clock CE WE OE Address Data Ext Trigger Match Unit MO Basic w edges Match Unit M1 Basic w edges Match Unit M2 Basic Match Unit M3 Basic Match Unit M4 Range Ma
216. mp amp M3 amp amp M7 oK Cancel Figure 4 38 Setting the Trigger Condition Boolean Equation 4 30 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX The Sequencer tab of the Trigger Condition dialog box has a combo box from which you can select the number of levels in the trigger sequence and a table listing all the levels The sequencer begins at Level 1 and proceeds to Level 2 when the match unit specified in Level 1 has been satisfied The number of levels available is a parameter of the core up to a maximum of 16 levels Each level can look for a match unit being satisfied or not satisfied To negate a level for instance to look for the absence of a particular match function check the Negate cell for that level A representation of the sequence appears in the Trigger Condition Equation pane at the bottom of the window Figure 4 39 Trigger Condition TriggerConditionO Boolean Sequencer 1 Number of Levels 3 ly C Use Contiguous Match Events Only LE Level Match Unit Negate Li a M1 Li M3 I Trigger Condition Equation M0 gt M1 gt M3 oK Cancel Figure 4 39 Setting the Trigger Condition Sequencer The trigger sequence in Figure 4 39 can be satisfied by the eventual occurrence of match unit events MO followed by M1 followed by M3 with any occurrence or non occurrence of events i
217. n a per level basis to transition from one level to the next The trigger sequencer can be configured at run time to transition from one level to the next on either contiguous or non contiguous sequences of match function events Enabling the Storage Qualification Condition In addition to the trigger condition the ILA core can also implement a storage qualification condition The storage qualification condition is a Boolean combination of match function events These match function events are detected by the match unit comparators that are subsequently attached to the trigger ports of the core The storage qualification condition differs from the trigger condition in that it evaluates trigger port match unit events to decide whether or not to capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data to capture The storage qualification condition can be enabled by checking the Enable Storage Qualification checkbox Enabling the Trigger Output Port The output of the ILA trigger condition module can be brought out to a port signal by checking the Enable Trigger Output Port checkbox The trigger output port is used to trigger external test equipment by attaching the port signal to a device pin in the HDL design The trigger output port can also be attached to other logic or ChipScope Pro cores in the design to be used as a trigger an i
218. n ae 1 18 IBA OPB Control and Status Logic o oooccoccoococconconcr e 1 18 IBA PLB CoOre siii ii A Sac y AA A AN ade SS 1 18 IBA PLB Trigger Input Logic oce re b ex a Rr RE HELP ERE oboe 1 18 IBA PLB Trigger Output Logic cuido putet ia e E eU A EAR be ET E eaa 1 21 IBA PLB Data CaptureLogic c l 1 21 IBA PLB Control and Status Logic sse 1 21 MIO Cort iu tierce Pe Sa ERR eS eR kts Baa ste 1 22 Activity Detector Scsi n i eux e Pu Ede c ia a ioc ded a eene i 1 22 Pulse Trams 0 9 uy Edu A edt t dct v 1 22 ATIC2 COL sss 1 A AAA EE GOD AAD DEN DARA EYE 1 23 ATC2 Data Path Description sissies sesso eter rh Ru a REY en 1 23 ATC2 Core Data Capture and Run Time Control 0 2 6 cece eee 1 23 ICON and ILA Core Resource Usage 0 66 1 24 Synthesis Requirements s es morri rann cece eee nee eee 1 25 System Requirements cicer gow Garis REC ed Mew ba e eee as 1 25 Software Tools Requirements 6 66 ee 1 25 Communications Requirements ssssseeeeee ee 1 25 Board Requirements ssssseslssseeeee ne 1 27 Host System Requirements for Windows 2000 XP ooocccccccccccccccn 1 27 Host System Requirements for LinUX oooooccooccconnrorrrccnnnnrrnr eee 1 27 Host System Requirements for Solaris 2 8 and 2 9 ooooo ocococccccccccc coo 1 28 ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 7 XILINX ChipScope Pro Software Installation
219. n between Enable the Use Contiguous Match Events Only checkbox if you desire the trigger sequence to be satisfied only upon contiguous transitions from MO to M1 to M3 and not for instance the transitions of MO followed by M1 followed by M1 followed by M3 Output Enable If the trigger output is present in the core a column named Output Enable becomes available This cell is a combo box that allows the user to select which type of signal will be driven by the trig out port of the ILA ILA ATC or IBA core e Disabled The output is a constant 0 e Pulse High The output is a single clock cycle pulse of logic 1 10 cycles after the actual trigger event e Pulse Low The output is a single clock cycle pulse of logic 0 10 cycles after the actual trigger event e Level High The output transitions from a 0 to a 1 10 cycles after the actual trigger event e Level Low The output transitions from a 1 to 0 10 cycles after the actual trigger event ChipScope Pro Software and Cores User Guide www xilinx com 4 31 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Saving and Recalling Trigger Setups All the information in the Trigger Setup window can be saved to a file for recall later with the current project or other projects To save the current trigger settings select Trigger Setup Save Trigger Setup A Save Trigger Setup As File dialog box will open and the trigger settings c
220. n that it evaluates trigger port match unit events to decide whether or not to capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data to capture The storage qualification condition can be enabled by checking the Enable Storage Qualification checkbox Enabling the Trigger Output Port The output of the IBA OPB trigger condition module can be brought out to a port signal by checking the Enable Trigger Output Port checkbox The trigger output port is used to trigger external test equipment by attaching the port signal to a device pin in the HDL design The trigger output port can also be attached to other logic or ChipScope Pro cores in the design to be used as a trigger an interrupt or another control signal The shape level or pulse and sense active high or low of the trigger output can also be controlled at run time The clock latency of the IBA OPB trigger output port is 15 clock OPB CLK cycles with respect to the trigger input ports 2 38 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core 7 XILINX IBA OPB Core Data Port Options After you have set up the IBA OPB core trigger port options click Next This takes you to the fourth screen in the Core Generator that is used to set up the of the IBA OPB core data port options Figure 2 22 e Ch
221. n the input data port signals The CLK port is also used as a clock source for internal logic that performs data pin calibration The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the ATC2 core ChipScope Pro Software and Cores User Guide www xilinx com 2 63 UGO29 v7 1 February 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator ATC2 Core Data Options After you have set up the general ATC2 core options click Next This takes you to the third screen in the Core Generator that is used to set up the of the ATC2 core data capture options Figure 2 39 and Figure 2 40 for State mode and Timing mode respectively e ChipScope Pro Core Generator Agilent Trace Core 2 Data Capture Settings Capture Mode TDM Rate 2y Signal Bank Count 4 ATD Pin Count g Driver Endpoint Type Single Ended Data Port Width 16 Pin Edit Mode Same as ATCK v Enable Auto Setup Max Frequency Range 301 500 MHz Pin Parameters Pin Name Pin Loc O Standard Drive Slew Rate ATCK AB21 LYTTL 12 w FAST W21 LVTTL 12 FAST v22 LVTTL 12 FAST IY22 LYTTL 12 FAST LVTTL 12 FAST Y21 LVTTL 12 FAST v20 LYTTL 12 FAST AA22 LVTTL 12 FAST LVTTL 12 FAST 4 41 1414 4 41 4 41 4 1 4 4 4 Core Utilization LUT Count 159 FFCount 4
222. n token definitions ZERO 00 Figure 4 1 Example Token File ChipScope Pro Software and Cores User Guide www xilinx com 4 5 UG029 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Tokens are chosen by selecting a bus then choosing Bus Radix Token from the right click menu A dialog box opens and you can choose the token file If the bus is wider than the tokens specify such as choosing 4 bit tokens for an 8 bit bus the upper bits are assumed 0 for the tokens to apply Figure 4 2 shows such a waveform with the example token file in Figure 4 1 applied to an 8 bit bus El Waveform DEV 2 MyDevice2 XC2VP7 UNIT 0 MyILAO ILA i Bus Signal x o 23 204 205 206 207 208 SS o BUS 0 o 3s zERO X ONE X TWO X THREE X FOUR X Five X DataPort 8 DataPort 9 DataPort 10 DataPort 12 DataPort 13 DataPort 14 1 o DataPort 11 E 1 1 1 1 DataPort 15 Figure 4 2 Example Waveform with Tokens Deleting Buses To delete a bus right click on it and select Delete Bus The bus is immediately deleted in every data view it is resident Type and Persistence VIO only VIO signals have two additional properties Type and Persistence See VIO Bus Signal Activity Persistence page 4 40 for explanations of these properties Message Pane The Message pane displays a scroll list of sta
223. n use either the rising or falling edges of the CLK signal to trigger and capture data The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the IBA PLB core Selecting the PLB Bus Settings The IBA PLB core is designed to passively attach to the PLB bus arbiter component in your embedded PowerPC or MicroBlaze processor design Like the PLB bus and arbiter components the IBA PLB core is capable of handling up to 16 PLB masters and 16 PLB slaves Note It is very important to specify the same number of PLB masters and slaves that you have on the PLB bus of your embedded processor design otherwise the IBA PLB core may not function properly IBA PLB Core Trigger Port Options After you have set up the general IBA PLB core options click Next This takes you to the third screen in the Core Generator that is used to set up the of the IBA PLB core trigger port options Figure 2 28 5 ChipScope Pro Core Generator DER IBA for Processor Local Bus Trigger Port Options Trigger Input and Match Unit Settings Number of Trigger Ports Used 4 Number of Match Units Used 7 PLB Control Signals combined Trigger Width 26 Match Type Basic wedges v ivi Match Units 4 v Bit Values 0 1 X R F B Counter Width 16 v Functions lt gt PLB Address Bus Trigger Width Match Type Extended w edges w vi Match Units 1 v Bit Values 0 1 X R
224. n when the capture mode is set to State and is used as a data pin when the capture mode is set to Timing The ATD pins are always used as data pins The names of the pins cannot be changed Pin Loc The Pin Loc column is used to set the location of the ATCK or ATD pin IO Standard The IO Standard column is used to set the I O standard of each individual ATCK or ATD pin The I O standards that are available for selection depend on the device family and driver endpoint type The names of the I O standards are the same as those in the IOSTANDARD section of the Constraints Guide http toolbox xilinx com docsan xilinx6 books docs cgd cgd pdf in the Xilinx Software Manual 2 66 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the ATC2 Core 7 XILINX VCCO The VCCO column setting denotes the output voltage of the pin driver and depends on the IO Standard selection Drive The Drive column setting denotes the maximum output drive current of the pin driver and ranges from 2 to 24 mA depending on the IO Standard selection Slew Rate The Slew Rate column can be set to either FAST or SLOW for each individual ATCK or ATD pin Core Utilization The ATC2 core generator has a core resource utilization monitor that estimates the number of look up tables LUTs and flip flops FF used by the ATC2 core depending on the parameters used The ATC2 core never uses block RAM or additional
225. ncy in Hz 200000 2500000 5000000 default is 5000000 Xilinx Parallel Cable Ill Arguments type Cable type for Xilinx Parallel Cable Ill is xilinx parallel3 port Parallel port identifier ChipScope Pro Software and Cores User Guide www xilinx com 5 9 UGO29 v7 1 February 16 2005 Chapter 5 Tcl JTAG Interface Xilinx MultiLINX Arguments type Cable type for Xilinx MultiLINX is multilinx port USB or RS 232 serial port identifier USB COM1 coM2 cow3 com4 baud RS 232 serial baud rate aUTO 9600 19200 38400 57600 Note The baud argument should not be used when the port argument is set to USB Agilent E5904B Option 500 FPGA Trace Port Analyzer Arguments type Cable type for the Agilent E5904B Option 500 FPGA Trace Port Analyzer Agilent E5904B TPA is agilent gateway host Host name or IP address of the Agilent E5904B TPA port Port number default is 6470 frequency TCK clock frequency in kHz 500 1000 2000 4000 5000 10000 20000 30000 default is 10000 timeout Connection timeout in seconds default is 10 seconds mode Connection mode Exclusive Session defaultis Exclusive vref JTAG pin reference voltage type Internal External default is Internal tvref Trace pin reference voltage type Internal External defaultis Internal voltage Internal JTAG pin reference voltage in mV 2500 3300 default is 3300 Note Note this argument will be ignored if vref is set to Ex
226. neral Options sssssssss e 2 2 Icon Core Example and Template Options 00 2 5 ICON Core Generation Complete sss 2 6 Sel cting the ILA Core esee rm thee th hee eds 2 7 ILA Core General Options sssessss e 2 8 ILA Core Trigger Port Options 0 cece eee 2 9 Trigger Sequencer Block Diagram with 16 levels and 16 match units 2 12 ILA Core Data Port Opti0NS ooooccccoconooorrcrccr eee 2 13 ILA Core Data Same As Trigger Options 0 0000 eee 2 15 ILA Core Example and Template Options 045 2 16 ILA Core Generation Complete 0 nannan nenun 2 17 Selecting the ILA ATC Core n 0 c cee eee 2 19 ILA ATC Core General Options 0 0 ccc ccc 2 20 ILA ATC Core Trigger Port Options 0 00 c cece eee 2 21 ILA ATC Core Data Port Options 2 25 ILA ATC Core Example and Template Options 2 28 ILA ATC Core Generation Complete 0 00 c cece ee eens 2 29 Selecting the IBA OPB Core 0 ccc cece eee 2 30 IBA OPB Core General Options 0 ee ccc eee eee 2 31 IBA OPB Core Trigger Port Options 0 e cece eee 2 34 IBA OPB Core Data Port Options 0 2 39 IBA OPB Core Data Same As Trigger Options 2 40 IBA OPB Core Example and Template Options 2 41 IBA OPB Core Generation Compl
227. nerating an ILA Core 7 XILINX Bus Signal Name Example Files cdc The bus signal name example file for the ILA core for example ila cdc contains generic information about the trigger and data ports of the ILA core The ila cdc file will be created if you select the Generate Bus Signal Name Example File cdc checkbox You can use the ila cda file as a template to change trigger and or data port signal names create buses and so on The modified ila cdc file can then be imported into the ChipScope Pro Analyzer tool and applied to the appropriate ILA core by using the File gt Import option Batch Mode Generation Argument Example Files You can also create a batch mode argument example file for example ila arg by selecting the Generate Batch Mode Argument Example File arg checkbox The ila arg file is used with the command line program called generate The ila arg file contains all of the arguments necessary for generating the ILA core without having to use the ChipScope Pro Core Generator GUI tool Note An ILA core can be generated by running generate exe ila pro f ila argatthe command prompt on Windows systems or by running generate sh ila pro f ila argatthe UNIX shell prompt on Linux and Solaris systems Generating the Core After entering the ILA core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appea
228. ng on the Send to PDF button goes to the Print Wizard 3 of 3 PDF confirmation window see Figure 4 10 Clicking on the Yes button causes the waveform printout to be written to the specified PDF file while clicking on the No button returns you to the Print Wizard 2 of 3 window Clicking on Change File opens a file browser window that allows you to select or create a new PDF file Print Wizard 3 of 3 PDF Y Are you sure you want to printthe waveform for DEV 2 MyDevice2 XC2WP4 UNIT 1 MyILA1 ILA to c DilimaChipScope_Pro_7_1idefault_waveform pdf Yes No Change File Figure 4 10 Print Wizard 3 of 3 for Sending to a PDF File 4 12 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX In the Print Wizard 2 of 3 window clicking on the Send to Printer button goes to the Print Wizard 3 of 3 Printer confirmation window see Figure 4 11 Clicking on the Yes button causes the waveform printout to be sent to the printer while clicking on the No button returns you to the Print Wizard 2 of 3 window Print Wizard 3 of 3 Printer Are you sure you want to print the waveform for DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA Yes No iss Figure 4 11 Print Wizard 3 of 3 for Sending to a Printer Page Setup The Page Setup window shown in Figure 4 12 can be invoked either from the Print Wizard 1 of 3 windo
229. ng the ChipScope Pro Analyzer Time Sample Range You can control the range of time units or number of samples printed using one of four methods e Current View Print waveform data using the same range of samples that is present in the current waveform view e Full Range Print waveform data using a range of samples consisting of all samples in the entire sample buffer e Between X O Cursors Print waveform data using a range of samples starting with the X cursor and ending with the O cursor or vice versa e Custom View Print waveform data using a range of samples defined by a starting window and sample number and an ending window and sample number The default prints waveform data using the Current View method Print Signal Names You can choose to print the signal names and X O cursor values on each page or only on the first page Printing the X O cursor values on the first page only is useful when you assemble multiple printed pages together to form a larger multi dimensional plot X O Cursor Values You can also choose whether or not to include the X O cursor values in the waveform printout If you choose to display the X O cursor values in the waveform printout then they will either appear on each page or only on the first page depending on the Print Signal Names setting see previous section Print Signal Names Footer You can enable or disable the inclusion of a footer at the bottom of each page by selecting the Sh
230. nterrupt or another control signal The shape level or pulse and sense active high or low of the trigger output can also be controlled at run time The clock latency of the ILA trigger output port is 10 clock CLK cycles with respect to the trigger input ports 2 12 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA Core 7 XILINX ILA Core Data Port Options After you have set up the ILA core trigger port options click Next This takes you to the fourth screen in the Core Generator that is used to set up the of the ILA core data port options Figure 2 9 e ChipScope Pro Core Generator ILA Data Port Options Data Port Settings Data Depth 512 Samples Data Width 32 C Data Same As Trigger Number of Block RAMs 2 JJ SSS J 9 S sS s FI FS FSI FSI lt Previous Figure 2 9 ILA Core Data Port Options ChipScope Pro Software and Cores User Guide www xilinx com 2 13 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting the Data Depth The maximum number of data sample words that the ILA core can store in the sample buffer is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit For the Virtex II Virtex II Pro Virtex 4 Spartan
231. nts file liba plb ncf Generating CDC file liba plb cdc Generating batch mode argument file iba plb arg ChipScope Pro Core Generator Version 7 11 Build 4 212 895 Example Usage File iba_plb_xst_example vhd Generating batch mode argument file iba plb xst vhdl example arg CORE GENERATION COMPLETE Previous Figure 2 82 IBA PLB Core Generation Complete Using the IBA PLB Core To instantiate the example IBA PLB core HDL files into your design use the following guidelines to connect the IBA PLB core port signals to various signals in your design e Connect the IBA PLB core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the IBA PLB core s data trigger and PLB port signals to 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process e Make sure the data and trigger source signals are synchronous to the IBA PLB clock signal PLB CLK 2 56 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the VIO Core 7 XILINX Generating the VIO Core The ChipScope Pro Core Generator tool provides the ability to define and generate a customized VIO core for adding virtual inputs and outputs to your HDL designs You can customize the virtual inputs and outputs to be synchronous to a p
232. nually You only need to start the server application manually when you desire to interact with the server from a remote client Note The ChipScope Pro Analyzer server application can handle only one client connection at a time The server can be started as follows e The ChipScope Pro Analyzer server is started on Windows machines by executing SCHIPSCOPE cs server bat command line options e The ChipScope Pro Analyzer server is started on Linux machines by executing SCHIPSCOPE bin lin cs server sh command line options where the CHIPSCOPE environment variable points to the ChipScope Pro 7 1i installation directory The ChipScope Pro Analyzer server application has several command line options that are described in Table 4 2 You can customize the server scripts as needed Table 4 2 ChipScope Pro Analyzer Server Command Line Options Command Line Option Description port lt portnumber gt Used to specify the TCP IP port number that is used by the client and server to establish a connection The default port number is 50001 password password Used to protect the server from unauthorized access No password is set by default l lt logfile gt Used to specify the location of the log file The default log file location is HOME chipscope cs analyzer portnumber log where HOME is the users home directory and lt portnumber gt is the TCP IP port number used by the server Refer to th
233. o Core Generator Selecting Match Unit Counter Width The match unit counter is a configurable counter on the output of the each match unit in a trigger port This counter can be configured at run time to count a specific number of match unit events To include a match counter on each match unit in the trigger port select a counter width from 1 to 32 The match counter will not be included on each match unit if the Counter Width combo box is set to Disabled The default Counter Width setting is Disabled Enabling the Trigger Condition Sequencer The trigger condition sequencer can be either a Boolean equation or an optional trigger sequencer that is enabled by checking the Enable Trigger Sequencer checkbox A block diagram of the trigger sequencer is shown in Figure 2 8 Match Unit O Match Unit 1 Match Unit 2 Match Unit O Match Unit 1 Match Unit 2 Match Unit O Match Unit 1 rigger Match Unit 2 Level 99 16 Match Unit 15 gt Match Unit 15 Match Unit 15 UGO29 trig seq blk diag 081903 Figure 2 8 Trigger Sequencer Block Diagram with 16 levels and 16 match units The trigger sequencer is implemented as a simple cyclical state machine and can transition through up to 16 states or levels before the trigger condition is satisfied The transition from one level to the next is caused by an event on one of the match units that is connected to the trigger sequencer Any match unit can be selected at run time o
234. o capture events that immediately follow device configuration without having to first set up the ATC2 core manually This feature is disabled by default and is only available when the capture mode is set to Timing mode Pin Edit Mode The Pin Edit Mode parameter is a time saving feature that allows you to change the IO Standard Drive and Slew Rate pin parameters on individual pins or together as a group of pins Setting the Pin Edit Mode to Individual allows you to edit the parameters of each pin independently from one another Setting the mode to Same as ATCK allows you to change the ATCK pin parameters and forces all ATD pins to the same settings You need to set unique pin locations for each individual pin regardless of the Pin Edit Mode parameter setting Pin Parameters The output clock ATCK and data ATD pins are instantiated inside the ATC2 core for your convenience This means that although you do not have to manually bring the ATCK and ATD pins through every level of hierarchy to the top level of your design you do need to specify the location and other characteristics of these pins in the Core Generator These pin attributes are then added to the ncf file of the ATC2 core Using the settings in the Pin Parameters table you can control the location I O standard output drive and slew rate of each individual ATCK and ATD pin Pin Name The ATC2 core has two types of output pins ATCK and ATD The ATCK pin is used as a clock pi
235. o either Occurring in at least n cycles or Lasting for at least n consecutive cycles the Window Depth or Samples Per Trigger setting cannot be less than eight samples This is due to the pipelined nature of the trigger logic inside the ILA ILA ATC IBA OPB and IBA PLB cores Position The Position text field is only available when Window is selected in the Type combo box The Position field defines the position of the trigger in each window Valid values are integers from 0 to the depth of the capture buffer minus 1 Samples Per Trigger The Sample Per Trigger text field is only available when N Samples is selected in the Type combo box Samples per trigger defines how many samples to capture once the trigger condition occurs Valid values are any positive integer from 1 to the depth of the capture buffer The trigger mark will always appear as sample 0 in the window There will be as many sample windows as possible captured given the overall sample depth Note When occurring in at least n cycles or occurring for at least n consecutive cycles is selected for a match unit and that match unit is a part of the overall trigger condition the Window Depth or Samples Per Trigger cannot be less than 8 This is due to pipeline effects inside the ILA ILA ATC or IBA core Timestamp The Timestamp checkbox enables timestamps for capturing This option is only enabled for ILA ATC cores The timestamp value will appear in the horizontal ruler of the
236. olvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil tt home jsp xxii www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Conventions 7 XILINX This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Courier font Meaning or Use Messages prompts and program files that the system displays Example Speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design name Helvetica bold Commands that you select from a menu File gt Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on of Vertical bar
237. on each match unit if the Counter Width combo box is set to Disabled The default Counter Width setting is Disabled Enabling the Trigger Condition Sequencer The trigger condition sequencer can be either a Boolean equation or an optional trigger sequencer that is enabled by checking the Enable Trigger Sequencer checkbox A block diagram of the trigger sequencer is shown in Figure 2 8 page 2 12 The trigger sequencer is implemented as a simple cyclical state machine and can transition through up to 16 states or levels before the trigger condition is satisfied The transition from one level to the next is caused by an event on one of the match units that is connected to the trigger sequencer Any match unit can be selected at run time on a per level basis to transition from one level to the next The trigger sequencer can also be configured at run time to transition from one level to the next on either contiguous or non contiguous sequences of match function events Enabling the Storage Qualification Condition In addition to the trigger condition the IBA PLB core can also implement a storage qualification condition The storage qualification condition is a Boolean combination of events that are detected by the match unit comparators that are subsequently attached to the trigger ports of the core The storage qualification condition differs from the trigger condition in that it evaluates trigger port match unit events to decide whether or not to
238. or ATD pin The I O standards that are available for selection depend on the device family and driver endpoint type The names of the I O standards are the same as those in the IOSTANDARD section of the Constraints Guide http toolbox xilinx com docsan xilinx6 books docs cgd cgd pdf in the Xilinx ISE 6 Software Manuals and Help PDF Collection VCCO The VCCO column setting denotes the output voltage of the pin driver and depends on the IO Standard selection Drive The Drive column setting denotes the maximum output current drive of the pin driver and ranges from 2 to 24 mA depending on the IO Standard selection Slew Rate The Slew Rate column can be set to either FAST or SLOW for each individual ATCK or ATD pin Core Utilization The ATC2 core generator has a core resource utilization monitor that estimates the number of look up tables LUTs and flip flops FF used by the ATC2 core depending on the parameters used The ATC2 core never uses block RAM or additional clock resources for example BUFG or DCM components 3 22 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX Choosing Net Connections for ILA or ILA ATC Signals The Net Connections tab Figure 3 14 allows you to choose the signals to connect to the ILA or ILA ATC core If trigger is separate from data then the clock trigger and data ports must be speci
239. or and ChipScope Pro Core Inserter tools run on workstation systems running the Linux operating system and meet the requirements outlined in Table 1 14 Note The Linux version of the ChipScope Pro 7 1i Core Generator and Core Inserter tools require that the Xilinx ISE 7 1i tools are installed on the target system and that the XILINX environment variable is set up correctly Table 1 14 Linux Requirements for ChipScope Pro 7 1i Tools OS Version Memory Java Environment Red Hat Enterprise 512 MB Java Run time Environment version 1 5 0 b64 Linux WS 3 32 bit automatically included in ChipScope Pro 7 1i software installation ChipScope Pro Software and Cores User Guide www xilinx com 1 27 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction Host System Requirements for Solaris 2 8 and 2 9 The ChipScope Pro Core Generator ChipScope Pro Core Inserter and ChipScope Pro Analyzer client mode only tools run on workstation systems running Sun Microsystems Solaris operating system and meet the requirements outlined in Table 1 15 Table 1 15 Solaris Requirements for ChipScope Pro 7 1i Tools OS Version Memory Java Environment Solaris 2 8 512 MB Java Run time Environment version 1 5 0 b64 32 bit automatically included in ChipScope Pro 7 1i Solaris 2 9 512 MB software installation 32 bit Note The ChipScope Pro Analyzer tool only runs on Solaris systems in client mode A Chi
240. ort or weapons systems High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk O 2005 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PowerPC is a trademark of IBM Inc All other trademarks are the property of their respective owners ChipScope Pro Software and Cores User Guide www xilinx com UGO29 v7 1 February 16 2005 Revision History The following table shows the revision history for this document Date 04 09 02 Version 1 0 Revision Initial Xilinx release 10 29 02 5 1 Added new Chapter 3 Using the ChipScope Pro Core Inserter Old Chapter 3 is new Chapter 4 Using the ChipScope Pro Analyzer Updated all chapters to be compatible with 5 1i tools Revised version number to be in sync with version of tools 03 06 03 52 Updated all chapters to be compatible with 5 2i tools Updated version number to reflect version number of tools 05 15 03 Chapter 1 Added the Choice of Match Unit Counter section to Table 1 3 Chapter 2 Added the Selecting Match Unit Counter Width section updated several trigger screen shots Chapter 3 Added Selecting Match Unit Counter Width section Chapter 4 Updated screen shots in
241. ot window for a particular set of ILA or IBA buses select Window gt New Unit Windows and the core desired A dialog box will be displayed for that ChipScope Pro Unit and the user can select the Trigger Setup Waveform Listing and or Bus Plot window or any combination Windows cannot be closed from this dialog box The same operation can be achieved by double clicking on the Bus Plot in the project tree or right clicking on Bus Plot and selecting Open Bus Plot Any buses for a particular core can be displayed in the Bus Plot window Figure 4 45 The Bus Plot window displays buses as a graph of a bus s values over time or one bus s values vs another s e Bus Plot DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA Plot 8 data vs time data vs data Display 200000 line E Bus Selection JM microPort ddr CEM microPortDataln Wil microPortDataO lll microProgAddr o Wil MPA_reg m sine SOD 200000 X 512 Y 343870 Figure 4 45 The Bus Plot Window Data vs Time 1 Bus Plot is not available for ILA ATC cores ChipScope Pro Software and Cores User Guide www xilinx com 4 37 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Plot Type Plot types are chosen in the upper left group of radio buttons There are two plot types data vs time and data vs data When data vs time is chosen Figure
242. otifies you of how many block RAMs will be used by the ILA core The trigger mark is automatically taken into account when calculating this value Creating Example Templates After selecting the parameters for the ILA core click Next to view the Example and Template Options Figure 2 11 e ChipScope Pro Core Generator ILA Example and Template Options HDL Example File Settings v Generate HDL Example File HDL Language voL y Synthesis Tool Xilinx XST Bus Signal Name Example File Settings v Generate Bus Signal Name Example File cdc Batch Mode Argument Example File Settings v Generate Batch Mode Argument Example File arg P lt Previous J ls Generate Core Figure 2 11 ILA Core Example and Template Options HDL Example Files You can choose to construct an example HDL instantiation template by selecting Generate HDL Example File and then selecting which synthesis tool and language to use The synthesis tools supported are e Mentor Graphics HDL e Synopsys Design Compiler FPGA e Synopsys FPGA Compiler II e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the ILA core without any HDL example files deselect the Generate HDL Example File checkbox 2 16 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Ge
243. ottom of the bus plot indicate the current X and Y coordinates of the mouse cursor when it is present in the bus plot view 4 38 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX VIO Console Window To open the Console window for a VIO core select Window New Unit Windows and the core desired A dialog box will be displayed for that ChipScope Pro Unit and the user can select the Console window Windows cannot be closed from this dialog box The Console window is for VIO cores only The Console allows users to see the status and activity of the VIO core input signals and modify the status of the VIO core output signals To open the console for a particular VIO core double click on the Console leaf node in the project tree All signal browser operations can also be performed in the Console window such as bus creation radix selection renaming etc To perform a signal operation right click on a signal or bus in the column heading The Console window has a table with two columns Bus Signal and Value Figure 4 47 a Console DEV 2 MyDevice2 XC2VP4 UNIT 0 MyVIOO VIO Bus Signal Value System Reset System Status Ready Error Get Lock Timeout Cmd Ready Timeout Buffer Ready Timeout gt SACF Sector Offset 27 0 0000000 SACF Sector Read Strobe aj Sector Buffer Address 4 0 00 Sector Buffer Read Strobe Tli 9 Sec
244. ow Footer checkbox An example of the information that appears in the footer is shown in Figure 4 7 2004 02 10 19 27 00 ChipScope Pro Project sacfdemo Device 1 Unit 1 ILA Page Index row 0 col 0 window 0 sample 0 window 0 sample 220 Figure 4 7 Waveform Printout Footer Example Navigation Buttons The buttons at the bottom of the Print Wizard 1 of 3 window Figure 4 6 page 4 9 are defined as follows e Page Setup Opens the page setup window refer to Figure 4 12 page 4 13 e Next Opens the Print Wizard 2 of 3 window e Cancel Closes the Print Wizard window without printing Clicking on the Next button takes you to the Print Wizard 2 of 3 window described in Print Wizard 2 of 3 Window page 4 11 4 10 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Print Wizard 2 of 3 Window The second Print Wizard window shown in Figure 4 8 shows a preview of the waveform printout Print Wizard 2 of 3 Bus Signal micraPragiddr mirePorddie mkcroPasDatain p JXo00 O 20009 OOOO mivoPaDatzOa X9OOOOGOGOOOOOOOOOOGOOOOOOOOOOOOO ERA y f mk habe n 7 SULLA i uL T n nnn m mirala MPA reg MPCE reg MPOE reg MPAVE reg MPIRO reg MPBRDY reg sine 20092 1914 XOQOODOQOSD ODDO 0000000000000000000000000000000
245. pScope Pro Analyzer client running on Solaris will need to connect to a ChipScope Pro Analyzer server running on either a Windows or Linux system 1 28 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Software Installation XILINX ChipScope Pro Software Installation Installing ChipScope Pro Software for Windows 2000 XP After downloading the ChipScope Pro Tools in the form of a self extracting executable file ie ChipScope Pro 7 1i pc exe T oUumROININm Make sure that you have administrator privileges on the target installation system in order to install the cable drivers correctly Choose Start Run Browse for ChipScope Pro 7 1i pc exe Choose Run Follow the install wizard instructions Use your 16 digit registration ID when prompted You must register your ChipScope Pro 7 1i product at http www xilinx com chipscope in order to obtain your valid registration ID ChipScope Pro Software and Cores User Guide www xilinx com 1 29 UG029 v7 1 February 16 2005 XILINX Chapter 1 Introduction Installing ChipScope Pro Software for Solaris 2 8 and 2 9 After downloading the ChipScope Pro Tools in the form of a compressed tape archive file ie ChipScope Pro 7 1i sol tar gz 1 Make sure that your Solaris operating system has all required patches for more details refer to the install solaris html file found in the installation archive
246. pb arg by selecting the Generate Batch Mode Argument Example File arg checkbox The iba opb arg file is used with the command line program called generate The iba_opb arg file contains all of the arguments necessary for generating the IBA OPB core without having to use the ChipScope Pro Core Generator GUI tool Note An IBA OPB core can be generated by running generate exe iba opb f iba opb arg atthe command prompt on Windows systems or by running generate sh iba opb f iba opb arg atthe UNIX shell prompt on Linux and Solaris systems 2 42 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core 7 XILINX Generating the Core After entering the IBA OPB core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 25 You can select to either go back and specify different options or click Start Over to generate new cores e ChipScope Pro Core Generator Generate Generating Core Messages Number of CCOPB Masters 2 Number of CCOPB Slaves 4 Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinxip iba opb iba opb Writing iba opb edn Post Processing EDIF netlist iba opb edn Generating constraints file iba opb ncf Generating PV error to
247. port is equal to ATD pin count TDM rate In Timing mode the width of each data port is equal to ATD pin count 1 TDM rate since the ATCK pin is used as an extra data pin Max Frequency Range The Max Frequency Range parameter is used to specify the maximum frequency range in which you expect to operate the ATC2 core The implementation of the ATC2 core will be optimized for the maximum frequency range selection The valid maximum frequency ranges are 0 100 MHz 101 250 MHz 251 300 MHz and 301 500 MHz The maximum frequency range selection only has an affect on core implementation when the Capture Mode is set to State mode ChipScope Pro Software and Cores User Guide www xilinx com 2 65 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Enable Auto Setup The Enable Auto Setup option is used to enable a feature that allows the Agilent Logic Analyzer to automatically set up the appropriate ATC2 pin to Logic Analyzer pod connections This feature also allows the Agilent Logic Analyzer to automatically determine the optimal phase and voltage sampling offsets for each ATC2 pin This feature is enabled by default Enable Always On Mode The Enable Always On Mode option is used to force an ATC2 core to always enable its internal logic and output buffers The Always On mode will also force the selection of signal bank 0 upon FPGA device configuration This mode makes it possible t
248. ports is 15 clock cycles The TRIG OUT port is very flexible and has many uses For example you can e Connect the TRIG OUT port to a device pin in order to trigger external test equipment such as oscilloscopes and logic analyzers e Connect the TRIG OUT port to an interrupt line of an embedded PowerPC 405 or MicroBlaze processor to cause a software event to occur e Connect the TRIG OUT port of one core to a trigger input port of another core in order to expand the trigger and data capture capabilities of your on chip debug solution 1 16 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description 7 XILINX Table 1 7 OPB Signal Groups Trigger Group Name OPB CTRL Width Description OPB combined control signals including e SYS Rst Debug SYS Rst e WDT Rst e OPB Rst e OPB BE 3 e OPB BE 2 e OPB BE 1 e OPB_BE O e OPB select e OPB xferAck e OPB RNW e OPB errAck e OPB timeout e OPB toutSup e ODPB retry e OPB seqAddr e OPB busLock OPB_ABUS 32 OPB address bus OPB_DBUS 32 OPB combined data bus logical OR of read and write data buses OPB_RDDBUS 32 OPB read data bus from slaves OPB_WRDBUS 32 OPB write data bus to slaves OPB_Mn_CTRL 11 OPB control signals for master n including e Mn_request e OPB MnGrant e OPB_pendReqn e Mn_busLock e Mn_BE 3 e Mn B
249. r 16 total match units used whichever limit is reached first The protocol violation monitor is automatically checked and used as a trigger port if it is enabled on the IBA OPB General Options screen Figure 2 20 page 2 31 Table 2 9 OPB Signal Groups Trigger Group Name Width Description OPB CTRL 17 OPB combined control signals including e SYS Rst e Debug SYS Rst e WDT Rst e OPB Rst e OPB BE 3 e OPB BED e OPB_BE 1 e OPB_BE 0 e OPB select e ODPB xferAck e OPB RNW e OPB errAck e OPB timeout e OPB toutSup e OPB retry e OPB seqAddr e OPB busLock OPB ABUS 32 OPB address bus OPB DBUS 32 OPB combined data bus logical OR of read and write data buses OPB_RDDBUS 32 OPB read data bus from slaves OPB_WRDBUS 32 OPB write data bus to slaves ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 2 35 2 XILINX Chapter 2 Using the ChipScope Pro Core Generator Table 2 9 OPB Signal Groups Continued Trigger Group Name Width Description OPB Mr CTRL 11 OPB control signals for master n including e Mn request e OPB_MnGrant e OPB_pendReqn e Mn busLock e Mn BE 3 e Mn BE 2 e Mn BE I e Mn BE 0 e Mn select e Mn RNW e Mn seqAddr where n is the master number 0 to 15 OPB SL CTRL 4 OPB control signals slave m including e Slm xferAck e Slm errAck e Slm toutSup e Slm_retry w
250. r continuity UG029 v7 1 February 16 2005 www xilinx com ChipScope Pro Software and Cores User Guide ChipScope Pro Software and Cores User Guide www xilinx com UG029 v7 1 February 16 2005 Table of Contents Preface About This User Guide Chapter 1 Introduction ChipScope Pro Tools Overview usse esee 1 1 ChipScope Pro Tools Description 0 00 c cece eee 1 1 Design FlOW eel ele ema c educa de e a pea d He ares 1 4 ChipScope Pro Cores Description 0 ccc nee eee 1 4 ICON Core o5 s h xd a a a a vated belt o ves deste e ratas 1 4 ILA Cote ia AR dee Dr Re E a edt CEU aa 1 5 ILA Trigger Input Logic esexe e ree ke ex Rr eee le needs 1 5 ILA Trigger Output Lopid siisii Budd dete ob doen ere ed eee 1 10 ILA Data Capture Logic eise iba uev bI di dE PETS 1 10 ILA Control and Status Lopine sisri hei een a aE E hn 1 11 ILA ATQ Coria be dU p UG baaa eb is a ERE RES 1 11 ILA ATC Trigger Input Logia cere era tee LE PIE aes paleo liane 1 11 ILA ATC Trigger Output Logic sees nn 1 11 ILA ATC Data Capture Logia A rac ERI dr 1 12 ILA ATC Control and Status Logic seses c ec ne 1 13 IBA OPB Cote soe ed vb bre PU GR RP Y ETRPETIVOPLECUHPPI Y xaT 1 14 IBA OPB Protocol Violation Monitor Logic seen 1 14 IBA OPB Trigger Input LOGIC ss cess das sadist es Gy bet ead EE Red 1 16 IBA OPB Trigger OutputLogic esee 1 16 IBA OPB Data Capt re Logic 4 42 eoliano ede
251. r instance a leaf node for each ChipScope Pro unit appears when that device is configured with a ChipScope Pro core enabled bitstream Context sensitive menus are available for each level of hierarchy in the tree To access the context sensitive menu right click on the node in the tree Device and unit renaming child window opening device configuration and project operations can all be done through these menus To rename a device or core unit node in the project tree right click on the node and select Rename To end the editing press Enter or the up or down arrow key or click on another node in the tree Signal Browser The signal browser displays all the signals for the core selected in the project tree Signals can be renamed grouped into buses and added to the various data views using context sensitive menus in the signal browser Renaming Signals Buses and Triggers Ports To rename a signal bus or trigger port name in the signal browser double click on it or right click and select Rename To end the editing press Enter or the up or down arrow key or click on another node in the tree ChipScope Pro Software and Cores User Guide www xilinx com 4 3 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Adding Removing Signals from Views To remove all the signals from either the waveform or listing view right click on any data signal or bus in the signal browser and select Clear
252. r of events along with matches and ranges for greater accuracy and flexibility Downloadable from the Xilinx Web site Tools are easily accessible from the ChipScope Suite 1 Available when using the ILA with Agilent Trace Core ILA ATC in conjunction with the Agilent E5904B Option 500 trace port analyzer www xilinx com 1 3 XILINX Chapter 1 Introduction Design Flow The ChipScope Pro Tools design flow Figure 1 2 merges easily with any standard FPGA design flow that uses a standard HDL synthesis tool and the Xilinx ISE 7 11 implementation tools ChipScope Pro Core Generator Generate Instantiate Synthesize ICON ILA ILA ATC cores into HDL design without IBA OPB Source instantiating IBA PLB ChipScope cores VIO or ATC2 cores or ChipScope Pro Core Inserter Synthesize Connect Insert design with buses and cores in it internal signals to cores ICON ILA ILA ATC and or ATC2 cores into synthesized design ngc or EDIF netlist Implement design Select bitstream Set trigger View waveform cspro tools design flow 021204 Figure 1 2 ChipScope Pro Tools Design Flow ChipScope Pro Cores Description ICON Core All of the ChipScope Pro cores use the JTAG Boundary Scan port to communicate to the host computer via a JTAG download cable The ICON core provides a communications path between the JTAG Bound
253. r to using the ChipScope Pro Analyzer to download your bitstream into your device make sure the bitstream generation options are set properly a Inthe Project Navigator right click on the Generate Programming File process and select the Properties option b Select the Startup options tab c Setthe FPGA Start Up Clock dropdown to JTAG Clock ChipScope Pro Software and Cores User Guide www xilinx com 3 3 UGO029 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Using the Core Inserter with Command Line Implementation If you use the command line version of the Xilinx ISE tools for instance from a make file or script and you want to use the Core Inserter with those designs follow these steps 1 Synthesize the design This step will create a design netlist file called my design ngc edf edn where the file extension depends on the synthesis tool used to create the file 2 Merge any separate netlists into a single netlist so that you can use the Core Inserter to instrument the entire design ngcbuild sd lt netlist search path p part type gt my_design ngc edf edn my design merged ngc 3 Run the ChipScope Pro Core Inserter The Windows ChipScope Core Inserter is run by selecting the ChipScope Pro Core Inserter option from the appropriate Start All Programs gt ChipScope Pro 7 1i menu folder The Solaris ChipScope Core Inserter is run by executing SCHIPSCOPE bin sol in
254. rator is used to set up the of the general ATC2 core options Figure 2 38 e ChipScope Pro Core Generator Agilent Trace Core 2 General Options Design Files Output Netlist atc2 edn Device Settings Device Family Virtex2P Clock Settings Sample On Rising Edge Of Clock a i lt Previous Figure 2 38 ATC2 Core General Options Choosing the File Destination The destination for the ATC2 EDIF netlist atc2 edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ATC2 core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture For the ATC2 core the ChipScope Pro Core Generator only supports the Virtex II Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E device families including the QPro variants of these families Virtex II is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Selecting the Clock Edge The ATC2 core can use either the rising or falling edges of the CLK signal to capture data o
255. re and can be used as inputs to your design regardless of the clock domain Synchronous Inputs The VIO core will include synchronous inputs when the Enable Synchronous Input Signals checkbox is enabled When enabled you can specify that up to 256 synchronous input signals should be used by entering a value in the Width text field Synchronous input signals are inputs to the VIO core and can be used as outputs from your design as long as those design signals are synchronous to the CLK signal of the VIO core Synchronous Outputs The VIO core will include synchronous outputs when the Enable Synchronous Output Signals checkbox is enabled When enabled you can specify that up to 256 synchronous output signals should be used by entering a value in the Width text field Synchronous output signals are outputs from the VIO core and can be used as inputs to your design as long as those design signals are synchronous to the CLK signal of the VIO core Selecting the Clock Edge The VIO core can use either the rising or falling edges of the CLK signal to capture and generate data on the synchronous input and output signals respectively The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the VIO core Note The clock edge can only be selected if synchronous inputs and or outputs are used ChipScope Pro Software and Cores User Guide www xilinx com 2 59 UGO29 v7 1 Febru
256. re logic ILA cores capture and store trace data information using on chip block RAM resources ILA ATC cores capture on chip data and store trace data information in the Agilent E5904B Trace Port Analyzer e Control and status logic Manages the operation of the ILA core ILA Trigger Input Logic The triggering capabilities of the ILA core and the ILA ATC core include many features that are necessary for detecting elaborate trigger events These features are described in Table 1 3 which spans multiple pages Table 1 3 Trigger Features of the ILA and ILA ATC Cores Feature Description Wide Trigger Ports Each trigger port can be 1 to 256 bits wide Multiple Trigger Ports Each ILA core and ILA ATC core can have up to 16 trigger ports The ability to support multiple trigger ports is necessary in complex systems where different types of signals or buses need to be monitored using separate match units Multiple Match Units per Trigger Port Each trigger port can be connected to up to 16 match units This feature enables multiple comparisons to be performed on the trigger port signals Boolean equation trigger condition The trigger condition can consist of a Boolean AND or OR equation of up to 16 match unit functions Multi level trigger sequencer The trigger condition can consist of a multi level trigger sequencer of up to 16 match unit functions Boolean equation storage qualification cond
257. re s data and trigger port signals to 0 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation process e Make sure the data and trigger source signals are synchronous to the ILA clock signal CLK 2 18 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC Core 7 XILINX Generating an ILA ATC Core The ILA ATC core is similar to an ILA core except that the data is captured off chip by the Agilent E5904B Option 500 Trace Port Analyzer Agilent TPA The ILA ATC core is connected to the Agilent TPA cable using a special 4 to 20 data pin trace port connection The ChipScope Pro Core Generator tool provides the ability to define and generate a customized ILA ATC capture core to use with HDL designs You can customize the number width and capabilities of the trigger ports You can also customize the maximum number of data pins to be used as samples stored by the ILA ATC core the location of these pins and the width of the data samples After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file nc and example HDL code specific to the synthesis tool used You can easily generate the netlist and code examples for use in normal FPGA design flows The first screen in the Core Generator offers the choice to generate
258. roProgAddr gt 734 Unsigned for at least 2 consecutive clock cycles M2 microPortAddr lt gt 0_0000 Bin amp M3 microPoriDataln E 0110 1001 Bin M4microPortDataOut AA Hex M5 microStrobes RX Bin exactly 130 clock cycles MEMPA reg 100 000X Bin M7 MP_control_regs o XOF Bin exactly one clock cycle M8 MP_control_regs 1 00XX Bin exactly 230 clock cycles 9 M9 microlnterrupts X1 0000 Bin exactly one clock cycle M10 microlnterrupts 1X 0000 Bin exactly one clock cycle o M11 sine 13487 Signed 3 Figure 4 35 Setting the Match Functions Match Unit The Match Unit field indicates which match unit the function applies to Clicking on the symbol next to the match unit number or double clicking on the field will expand that match unit so it is displayed as individual trigger port bits in at tree structure Individual values for each bit can then be viewed and set Function The Function combo box selects which type of comparison is done Only those comparators that are allowed for that match unit are listed Value The Value field selects exactly which trigger value to apply to that match unit It is displayed according to the Radix field Double clicking on the field will make it editable Place the cursor before the value you want to change and typing a valid trigger character will overwrite that character Or select the field by single clicking then proceed by typing the trigger
259. rs and the CORE GENERATION COMPLETE message signals the end of the process Figure 2 12 You can select to either go back and specify different options or click Start Over to generate new cores e ChipScope Pro Core Generator Generate Messages Match Counter disabled Trigger Sequencer Type Basic Number oftrigger sequencer levels 16 External capture disabled Force RPM Grid Usage no Warning EDIF Netlist being generated Processing com xilinx ip ila ila Writing Mila edn Post Processing EDIF netlist ila edn Generating constraints file ila nct Generating CDC file Aila cdc Generating batch mode argument file ila arg ChipScope Pro Core Generator Version 7 11 Build 4 212 895 Example Usage File 1ila_xst_example vhd Generating batch mode argument file ila xst vhdl example arg CORE GENERATION COMPLETE 4l lt Previous ll Start Over Figure 2 12 ILA Core Generation Complete ChipScope Pro Software and Cores User Guide www xilinx com 2 17 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Using the ILA Core To instantiate the example ILA core HDL files into your design use the following guidelines to connect the ILA core port signals to various signals in your design e Connect the ILA core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the ILA co
260. rt Signals Core DEv 2 MyDevice2 XC2VP w r Signals to Export All Signals Buses A Export Cancel Figure 4 14 Export Signals Dialog Box Three formats are available value change dump VCD format tab delimited ASCII format or the Agilent Technologies Fast Binary Data Format FBDF To select a format click its radio button To select the target core to export select it from the Core combo box Different sets of signals and buses are available for export Use the Signals to Export combo box to select e All the signals and buses for that particular core or e All the signals and buses present in the core s waveform viewer or e All the signals and buses in the core s listing viewer or e All the signals and buses in the core s bus plot viewer To export the signals click Export A file dialog box will appear from which you can specify the target directory and filename Closing and Exiting the Analyzer To exit the ChipScope Pro Analyzer select File Exit The current active project is automatically saved upon exit Viewing Options The split pane on the left of the Analyzer window and the Message pane at the bottom of the window can both be hidden or displayed per the user s choice Both are displayed the first time the Analyzer is launched To hide the project tree signal browser split pane uncheck it under View Project Tree To hide the Message pane uncheck it under View Message
261. rtan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Using SRL 16s The IBA PLB core normally uses the SRL16 feature of the FPGA device to increase performance and decrease the area used by the core If the device family is Virtex IL Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the OPro variants of these families the usage of SRL16s by the IBA PLB core can be disabled by deselecting the Use SRL16s checkbox It is recommended that the Use SRL 16s checkbox remain enabled Note SRL16s must be used with the Virtex Virtex E Spartan ll or Spartan lIE device families including the QPro variants of these families ChipScope Pro Software and Cores User Guide www xilinx com 2 45 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Using RPMs The IBA PLB core normally uses relationally placed macros RPMs to increase the performance of the core If the device family is Virtex II Virtex II Pro Virtex 4 or Spartan 3 including the QPro variants of these families the usage of RPMs by the IBA PLB core can be disabled by deselecting the Use RPMs checkbox It is recommended that the Use RPMs checkbox remain enabled for these device families Note RPMs cannot be used with the Virtex Virtex E Spartan ll or Spartan lIE device families including the QPro variants of these families Selecting the Clock Edge The IBA PLB unit ca
262. s 255 Note One extra bit per sample is required for the trigger mark e g a trigger data width of 7 bits requires a full sample width of 8 bits etc For the Virtex Virtex E Spartan II and Spartan IIE device families including the QPro variants of these families you can set the data depth to one of five values Table 3 3 Table 3 3 Maximum Data Widths for Virtex E Spartan ll IIE Depth Depth Depth Depth Depth 256 512 1024 2048 4096 1 block RAM 15 7 3 1 2 block RAMs 31 15 7 3 1 4 block RAMs 63 31 15 7 3 8 block RAMs 127 63 31 15 7 16 block RAMs 255 127 63 31 15 32 block RAMs 255 127 63 31 64 block RAMs 255 127 63 128 block RAMs 255 127 256 block RAMs 255 Note One extra bit per sample is required for the trigger mark e g a trigger data width of 7 bits requires a full sample width of 8 bits etc 3 14 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX Selecting the Data Type The data captured by the ILA trigger port can come from two source types e Data Separate from Trigger Figure 3 9 page 3 13 The data port is completely independent of the trigger ports This mode is useful when you want to limit the amount of data being captured e Data Same as Trigger Figure 3 10 The data
263. s ChipScope Pro Software and Cores User Guide www xilinx com 4 15 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Setting up a Server Host Connection The ChipScope Pro Analyzer client GUI application requires a connection to the ChipScope Pro Analyzer server application that is running on either the local or a remote system Select the JTAG Chain JTAG Chain Server Host Setting This pops up the server settings dialog shown in Figure 4 15 ChipScope Pro Analyzer Server Settings Host localhost Port 50001 Password Restore Default Cancel Figure 4 15 Server Settings for Local Mode For local mode operation the server Host setting should always be set to localhost as shown in Figure 4 15 The Port setting can be set to any unused TCP IP port number The default Port number is 50001 In local mode the Password setting is not necessary in local mode Note In local mode the server is started automatically ChipScope Pro Analyzer Server Settings Host lab machine Port 50001 Password Perm Restore Default OK Cancel ox cansas Figure 4 16 Server Settings for Remote Mode For remote mode operation the server Host setting should be set to an IP address or appropriate system name as shown in Figure 4 16 The Port and Password settings should be set to the same port that was used when the server was started on the remote system In remote mod
264. s Trigger Same as Waveform gt Go To gt Trigger gt Previous e Go To Next Trigger Same as Waveform gt Go To gt Trigger Next e Zoom In Same as Waveform gt Zoom gt Zoom In e Zoom Out Same as Waveform gt Zoom gt Zoom Out e Fit Window Same as Waveform gt Zoom gt Zoom Fit 4 44 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Analyzer Command Line Options XILINX ChipScope Pro Analyzer Command Line Options On Windows systems the ChipScope Pro Analyzer can be started either from the command line or from the Start menu e On Windows systems you can invoke the analyzer from the command line by running SCHIPSCOPE analzyer exe e On Linux systems you can invoke the analyzer from the command line by running SCHIPSCOPE bin lin analzyer sh e On Solaris systems you can invoke the analyzer from the command line by running SCHIPSCOPE bin sol analzyer sh where CHIPSCOPE is the installation location Optional Arguments The following command line options are available if run from the command line geometry lt width gt x lt height gt lt left edge x coord gt lt top edge y coord Set location width and height of the Analyzer program window project path and filename gt Reads in specified project file at start Default is not to read a project file at start up init path and filename Read specified init file at start up and write to
265. s or data signals where a in range not range of values and transition in range detection are important a Bit values 0 means logical 0 1 means logical 1 X means don t care R means 0 to 1 transition F means 1 to 0 transition and B means any transition b The Bits Per Slice value is only an approximation that is used to illustrate the relative resource utilization of the different match unit types It should not be used as a hard estimate of resource utilization Use the TRIGn Match Type pull down list to select the type of match unit that will apply to all match units connected to the trigger port However as the functionality of the match unit increases so does the amount of resources necessary to implement that functionality This flexibility allows you to customize the functionality of the trigger module while keeping resource usage in check ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 www xilinx com 2 37 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting Match Unit Counter Width The match unit counter is a configurable counter on the output of the each match unit in a trigger port This counter can be configured at run time to count a specific number of match unit events To include a match counter on each match unit in the trigger port select a counter width from 1 to 32
266. s up to 57 6 kb s throughput when using RS 232 connection e Downloads at speeds up to 8 Mb s throughput when using USB connection e Contains an adjustable voltage interface that enables it to communicate with systems and I O s operating at 5V 3 3V or 2 5V e Windows OS support only Agilent E5904B TPA e Connects to host using 10 100 base T ethernet e Supports remote configuration and debug Downloads at speeds up to 30 Mb s Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 3 3V down to 1 5V e Windows OS support only Note The Parallel Cable IV cable is available for purchase from the Xilinx Online Store from www xilinx com choose Online Store gt Programming Solutions gt Programming Cables 1 26 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 System Requirements 7 XILINX Board Requirements For the ChipScope Pro Analyzer and download cable to work properly with the board under test the following board level requirements must be met e One or more Xilinx Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan ll Spartan IIE Spartan 3 and Spartan 3E devices including the QPro variants of these families must be connected to a JTAG header that contains the TDI TMS TCK and TDO pins e If another device would normally drive the TDI TMS or TDI pins of the JTAG chain contain
267. sed in a single IBA OPB core cannot exceed 16 regardless of the number of trigger ports used 2 36 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA OPB Core 7 XILINX Selecting the Match Unit Type The different comparisons or match functions that can be performed by the trigger port match units depend on the type of the match unit Six different types of match units are supported by the IBA OPB cores Table 2 10 Table 2 10 IBA OPB Trigger Match Unit Types Type Bit Values Match Function pes Description Basic 0 1 X ES 8 Can be used for comparing data signals where transition detection is notimportant This is the most bit wise economical type of match unit Basic 0 1 X R F B A o d 4 Can be used for comparing w edges control signals where transition detection e g low to high high to low etc is important Extended 0 1 X a lt gt gt 2 Can be used for comparing gt lt lt address or data signals where magnitude is important Extended 0 1 X R F B A 2 Can be used for comparing w edges gt lt t lt address or data signals where a magnitude and transition detection are important Range 0 1 X z e V 1 Can be used for comparing gt lt lt address or data signals where a in range not range of values is important in range Range 0 1 X R F B CS NS 1 Can be used for comparing w edges Sa M addres
268. serter sh The Linux ChipScope Core Inserter is run by executing SCHIPSCOPE bin lin inserter sh 4 Browse for the top level design to fill in the Input Design Netlist Verify the following parameters are set under the Device tab Input Design Netlist ProjectDirlmy design merged ngc Output Design Netlist ProjectDir my design merged cs ngo Output Directory ProjectDir 5 Addand modify the cores and connections in the Core Inserter tool as necessary as shown in the section called ChipScope Pro Core Inserter Features page 3 5 Save the project before exiting the Core Inserter 6 Implement the design using the command line version of the Xilinx ISE tools For JTAG configuration ngdbuild p lt parttype gt my design merged cs ngo my design ngd map my design par ol 5 w my design my design bitgen w g UserID userlD g StartupClk JTAGClk my design my design 3 4 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features 7 XILINX ChipScope Pro Core Inserter Features Working with Projects Projects saved in the Core Inserter hold all relevant information about source files destination files core parameters and core settings This allows you to store and retrieve information about core insertion between sessions The project file cdc extension can also be used as an input to the ChipScope Pro Analyzer to import signal names When t
269. t mpIrqInt tat sectorReadstrobeIntstat sectorWritestrobeIntstat sacfReadRegStrobeInt Stat sacfReconfigStrobeIntStat DAAE ANEA PANEI A AARAARASAARATRATARATAATAYT ARARAARATRATARAARAATAEARAARATATARAARA MA VATARRARH gt MPA reg moynna MPCE reg In gt 0 235 A X 0 239 ChipScope Pro Analyzer new project New Project Open Project Save Project Trigger Setup DEV 2 MyDevice2 XC2VP4 I Save Project As Match Unit Function MO TriggerPortO dit TriggerCon Exit Type Window m Windows mn grams DEV amp Data Port Trigger Ports Figure 4 5 Selecting the File Print Option The Print Wizard consists of three consecutive windows 1 10f3 is the Print options and settings window Figure 4 6 page 4 9 2 2 of 3 is the Print waveform printout preview navigator window Figure 4 8 page 4 11 3 3 of 3 is the Print confirmation window Figure 4 11 page 4 13 4 8 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Print Wizard 1 of 3 Window The first Print Wizard window shown in Figure 4 6 is used to set up various waveform printing options The following sections describe thes
270. t Values 0 1 X R F B Counter Width 8 v Functions lt gt TRIGO Trigger Width 12 Match Type Extended Match Units v Bit Values 0 1 Counter Width 32 v Functions lt gt gt gt lt lt Trigger Width le Match Type Range w edges Match Units Bit Values 0 1 X R F B Counter Width Disabled v Functions lt gt gt gt lt lt Trigger Condition Settings lv Enable Trigger Sequencer Max Number of Sequencer Levels 16 Trigger Output Settings v Enable Trigger Output Port em Previous Next gt Figure 2 15 ILA ATC Core Trigger Port Options ChipScope Pro Software and Cores User Guide www xilinx com 2 21 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Selecting the Number of Trigger Ports Each ILA ATC core can have up to 16 separate trigger ports that can be set up independently After you choose a number from the Number of Trigger Ports pull down list a group of options appears for each trigger port The group of options associated with each trigger port is labeled with TRIGn where n is the trigger port number 0 to 15 The trigger port options include trigger width number of match units connected to the trigger port and the type of these match units Entering the Width of the Trigger Ports The individual trigger ports are buses that are made up of
271. t at http www xilinx com chipscope in order to obtain your valid registration ID Run the ChipScope Pro Core Inserter and ChipScope Pro Core Generator tools For the ChipScope Pro Core Generator SCHIPSCOPE bin lin gengui sh For the ChipScope Pro Core Inserter SCHIPSCOPE bin lin inserter sh For the ChipScope Pro Analyzer SCHIPSCOPE bin lin analyzer sh Installing the Java Run time Environment The Java Run time Environment JRE version 1 5 0 b64 used by the ChipScope Pro 7 1i tools is automatically included under the ChipScope Pro 7 1i installation directory ChipScope Pro Software and Cores User Guide www xilinx com 1 31 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction 1 32 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 7 XILINX Chapter 2 Using the ChipScope Pro Core Generator Core Generator Overview The ChipScope Pro Core Generator tool is a graphical user interface used to generate the following cores e Integrated Controller core ICON e Integrated Logic Analyzer core ILA e Integrated Logic Analyzer with Agilent Trace Core ILA ATC e Integrated Bus Analyzer for CoreConnect On Chip Peripheral Bus core IBA OPB e Integrated Bus Analyzer for CoreConnect Processor Local Bus core IBA PLB e Virtual Input Output core VIO e Agilent Trace Core 2 ATC2 As a group these cores are called the ChipScope Pro cores After generating
272. t design inside Xilinx Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan IL Spartan IIE Spartan 3 and Spartan 3E devices including the QPro variants of these families The ChipScope Pro tools communicate with these components and provide the designer with a complete logic analyzer ChipScope Pro Tools Description Table 1 1 ChipScope Pro Tools Description Tool Description ChipScope Pro Core Generator Provides netlists and instantiation templates for the e Integrated Controller Pro ICON core e Integrated Logic Analyzer Pro ILA cores e Agilent Trace Core ILA ATC Integrated Bus Analyzer for the IBM CoreConnect On Chip Peripheral Bus IBA OPB core Integrated Bus Analyzer for CoreConnect Processor Local Bus IBA PLB core e Virtual Input Output VIO core e Agilent Trace Core 2 ATC2 ChipScope Pro Core Inserter Automatically inserts the ICON ILA ILA ATC and ATC2 cores into the user s synthesized design ChipScope Pro Analyzer Provides device configuration trigger setup and trace display for the ILA ILA ATC IBA OPB IBA PLB and VIO cores The various cores provide the trigger control and trace capture capability The ICON core communicates to the dedicated Boundary Scan pins Tel JTAG Scripting The Tcl JTAG scriptable command interface makes it possible to interact with devices in a JTAG chain from a Tcl shell a Tcl stands for Tool Command E and a Tcl shel
273. t makes the most sense for the board under test El ChipScope Pro Analyzer sacfdemo2 File View JTAG Chain Device ae Server Host Setting ChipScope Pro Analyzer sacfdemo2 x Project sac uN Xilinx Parallel Cable L O Xilinx MultiLINX Serial Cable y 9 UNI Platform USB Cable Parameters Speed O Xilinx MultiLINX USB Cable a 24 MHz a o e 9 Data Por li amp micr aa TI MEL e rS Figure 4 20 Opening a Platform Cable USB Connection ChipScope Pro Software and Cores User Guide www xilinx com 4 19 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Polling the Auto Core Status When ChipScope Pro cores are armed the interface cable will query the cores on a regular basis to determine the status of the capture If other programs are using the cable at the same time as the ChipScope Pro Analyzer it may be beneficial to turn this polling off This can be done in the JTAG Chain menu by un checking JTAG Chain Auto Core Status Poll If this option is unchecked when the Run or Trigger Immediate operation is performed the Analyzer will not query the cores automatically to determine the status Note that this does not completely disable communication with the cable it will only disable the periodic polling when cores are armed If one or more cores trigger after the polling has been turned off
274. t signal In Timing mode the data path through the ATC2 core is composed purely of combinational logic all the way to the output pins Also in Timing mode the ATCK pin is used as an extra data pin Signal Bank Count The ATC2 core contains an internal run time selectable data signal bank multiplexer The Signal Bank Count setting is used to denote the number of data input ports or signal banks the multiplexer will implement The valid Signal Bank Count values are 1 2 4 8 16 32 and 64 Driver Endpoint Type The Driver Endpoint Type setting is used to control whether single ended or differential output drivers are used on the ATCK and ATD output pins All ATCK and ATD pins must use the same driver endpoint type TDM Rate The ATC2 core does not use on chip memory resources to store the captured trace data Instead it transmits the data to be captured by an Agilent logic analyzer that is attached to the FPGA pins using a special probe connector The data can be transmitted out the device pins at the same rate as the incoming DATA port TDM rate 1x or twice the rate as the DATA port TDM rate 2x The TDM rate can be set to 2x only when the capture mode is set to State ATD Pin Count The ATC2 core can implement any number of ATD output pins in the range of 4 through 128 Data Port Width The width of each input data port of the ATC2 core depends on the capture mode and the TDM rate In State mode the width of each data
275. ta Port Options Data Port Settings Data Depth 1024 Y y Samples Data Width 32 _ Data Same As Trigger Number of Block RAMs 3 laf Previous Figure 2 29 IBA PLB Core Data Port Options Selecting the Data Depth The maximum number of data sample words that the IBA PLB core can store in the sample buffer is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the IBA PLB unit For the Virtex II Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E device families including the OPro variants of these families you can set the data depth to one of six values Table 2 2 page 2 14 For the Virtex Virtex E Spartan II and Spartan IIE device families including the QPro variants of these families you can set the data depth to one of five values Table 2 3 page 2 14 2 52 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating the IBA PLB Core 7 XILINX Selecting the Data Type The data captured by the IBA PLB trigger port can come from two different source types e Data Same as Trigger Figure 2 30 The data and trigger ports are identical This mode is very common in most logic analyzers since you can capture and collect any data that is used to trigger the core Individual trigger ports can be selected to be included in the data port If this selection is ma
276. tch Unit M5 Basic w edges ILA Core TRIG OUT Interrupt Trigger Condition Data Capture Storage Qualification Condition Data Capture Memory l l l l l l l l l l l l l l l l Control I l l l l l l l l l l I l l l l ila_pro_connection_example_070704 Figure 1 3 LA Core Connection Example 1 8 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description 7 XILINX Using Trigger and Storage Qualification Conditions The ILA IBA OPB and IBA PLB cores implement both trigger and storage qualification condition logic The ILA ATC core only implements the trigger condition logic The trigger condition is a Boolean or sequential combination of events that is detected by match unit comparators that are attached to the trigger ports of the core The trigger condition is used to mark a distinct point of origin in the data capture window and can be located at the beginning the end or anywhere within the data capture window Similarly the storage qualification condition is also a Boolean combination of events that is detected by match unit comparators that are subsequently attached to the trigger ports of the core However the storage qualification condition differs from the trigger condition in that it evaluates trigger port match unit events to decide whether or not to capture
277. tering the Width of the Trigger Ports The individual trigger ports are buses that are made up of individual signals or bits The number of bits used to compose a trigger port is called the trigger width The width of each trigger port can be set independently using the TRIGn Trigger Width field The range of values that can be used for trigger port widths is 1 to 256 Selecting the Number of Trigger Match Units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form the overall trigger condition event that is used to control the capturing of data Each trigger port TRIGn can be connected to 1 to 16 match units by using the Match Units pull down list 3 10 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Core Inserter Features XILINX Selecting one match unit conserves resources while still allowing some flexibility in detecting trigger events Selecting two or more trigger match units allows a more flexible trigger condition equation to be a combination of multiple match units However increasing the number of match units per trigger port also increases the usage of logic resources accordingly Note The aggregate number of match units used in a single ILA core cannot exceed 16 regardless of the number of trigger ports used Selecting the Match
278. ternal tvoltage Internal trace pin output voltage in mV 2500 3300 default is 3300 Note This argument will be ignored if tvref is set to External www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Command Details XILINX Returns Handle to the opened cable if successful nothing if open function failed Examples 1 Manually force a Platform Cable USB open set handle jtag open port usbl type xilinx platformusb frequency 6000000 2 Autodetect the parallel cable type Sset handle jtag open 3 Manually force a Parallel Cable III open Sset handle jtag open port 1pt1 type xilinx parallel3 4 Manually force a Parallel Cable IV or MultiPRO open set handle jtag open port 1pt1 type xilinx parallel4 frequency 5000000 5 Manually force a MultiLINX open 5set handle jtag open port COM1 type multilinx baud 57600 6 Manually force an Agilent E5904B TPA open set handle jtag open type agilent gateway host 192 168 1 3 port 6470 frequency 2000 timeout 10 mode Exclusive vref Internal voltage 3300 tvref Internal tvoltage 2500 ChipScope Pro Software and Cores User Guide www xilinx com 5 11 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface jtag shiftir This command is used to shift bits into the specified device s instruction register Syntax jtag shiftir handle I constant 0 1 bitcount count buffer buffer
279. the Configuring the Target Device s section Added Displaying Configuration Status Information section Updated Counter section Added notes to the Depth and Samples per Trigger sections Updated The VIO Console Window section and most of its screen shots 8 29 03 6 1 Updated all chapters to be compatible with 6 1i tools Updated version number to reflect version number of tools Added Chapter 5 Tcl JTAG Interface 02 13 04 62 Updated all chapters to be compatible with 6 2i tools Updated version number to reflect version number of tools Chapter 2 Added the Generating the ATC2 Core section Updated all chapters to reflect ATC2 compatibility Miscellaneous edits for clarity or continuity 06 30 04 6 3 Updated all chapters to be compatible with 6 3i tools Updated version number to reflect version number of tools Miscellaneous edits for clarity or continuity Added MultiPRO cable information 10 04 04 Minor text corrections 02 16 05 7 1 Updated all chapters to be compatible with 7 1i tools Updated version number to reflect version number of tools Updated ATC2 core description to include the new auto setup and always on features Added information regarding Analyzer support on Linux and Solaris Added information on the client server remote debug feature Added Platform Cable USB cable information Miscellaneous edits for clarity o
280. the ChipScope Pro Core Generator Disabling JTAG Clock BUFG Insertion If the Boundary Scan component is instantiated inside the ICON core then it is possible to disable the insertion of a BUFG component on the JTAG clock signal Disabling the JTAG clock BUFG insertion causes the implementation tools to route the JTAG clock using normal routing resources instead of global clock routing resources By default this clock is placed on a global clock resource BUFG To disable this BUFG insertion check select the Disable JTAG Clock BUFG Insertion checkbox This should only be done if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew Make sure the design is adequately constrained to minimize this skew Including Boundary Scan Ports The Boundary Scan primitive for Xilinx Virtex Virtex E Virtex IL Virtex II Pro Spartan Il Spartan IIE Spartan 3 and Spartan 3E devices including the QPro variants of these families has two sets of ports USER1 and USER2 The Boundary Scan primitive for Xilinx Virtex 4 devices have four sets of ports USER1 USER2 USER3 and USER4 These ports provide an interface to the Boundary Scan TAP controller of the FPGA device Note This feature is not available for Virtex 4 devices since the BSCAN_VIRTEX4 primitive only has a single USER scan port per instance Since the ICON core uses only one of the USER scan chain ports for communication
281. the Read Once button is pressed Update Static By default when one VIO core output is changed information is immediately sent to the VIO core to set up that particular output To update all non pulse train outputs at once click Update Static Reset All To reset all outputs to their default state 0 for text fields and toggle buttons all 0 pulse train for pulse trains click Reset All Activity Display Atsome point it may be desirable to reset the activity display for all VIO core inputs To do so press the Clear All Activity button All input activity will be reset regardless of the selected persistence Key The key defines the colors in the console Viewing the Help Pages The ChipScope Pro Analyzer help pages contain information for only the currently opened versions of the ChipScope Pro software and each of the ChipScope Pro core units Selecting Help gt About ChipScope Software displays the version of the ChipScope Pro Software Selecting Help gt About Cores displays detailed core parameters for every detected core Individual core parameters can be displayed by right clicking on the unit in the project tree and selecting Show Core Info Also you do not need to reinstall the ChipScope Pro tools to convert your evaluation version to a full version You can also register an evaluation version of the ChipScope Pro Analyzer by selecting the Help Register ChipScope Pro menu option and typing in the appropriate full
282. the same file when the Analyzer exits The default is suserprofile chipscope cs analyzer ini log lt path and filename gt log stdout Write log messages to the specified file Specifying stdout will write to standard output The default is SHOME chipscope cs analyzer log Windows Command Line Example C Xilinx ChipScope Pro 7 lilanalyzer exe log c MprojNtNt log init C proj t t ini project c proj t t cpj geometry 1000x300 30 600 ChipScope Pro Software and Cores User Guide www xilinx com 4 45 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer 4 46 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface Overview This simple interface provides Tcl scripting access to Xilinx JTAG download cables via the ChipScope JTAG communication library The purpose of Tcl JTAG is to provide a simple scripting system to access basic JTAG functions In a few lines of Tcl script you can scan and manipulate the JTAG chain through standard Xilinx cables For further information on JTAG see XAPP139 Configuration and Readback of Virtex FPGAs Using JTAG Boundary Scan For information about Tcl see Tcl Developer Xchange at http www tcl tk Requirements e Microsoft Windows 2000 Professional SP2 or Windows XP Professional e Supported Xilinx JTAG cable such as Parallel Cable III IV MultiPRO or MultiLINX e
283. then a checkbox for each TRIGn port appears in the data options screen These checkboxes should be used to select the individual trigger ports that will be included in the aggregate data port Note that selecting the individual trigger ports automatically updates the Aggregate Data Width field accordingly A maximum data width of 256 bits applies to the aggregate selection of trigger ports ChipScope Pro Software and Cores User Guide www xilinx com 3 15 UGO29 v7 1 February 16 2005 XILINX Chapter 3 Using the ChipScope Pro Core Inserter Entering the Data Width The width of each data sample word stored by the ILA core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However regardless of these factors the maximum allowable data width is 256 bits Number of Block RAMs As the data depth and data width selections are changed the Number of Block RAMs field notifies you of how many block RAMs will be used by the ILA core The trigger mark is automatically taken into account when calculating this value Choosing ILA ATC Capture Settings If you are inserting an ILA ATC core the Capture Settings look like those in Figure 3 11 S ChipScope Pro Core Inserter my design cdc File Edit Help B e E DEVICE ILA ATC Select Agilent Trace Core Options El ICON 3 y U0 ILA Trigger Settings Capture Sett
284. tionality of the design Chapter 5 Tcl JTAG Interface explains how to use this JTAG scripting interface which provides Tcl scripting access to the ChipScope Parallel cable JTAG communication library The purpose of Tcl JTAG is to provide a simple scripting system to access basic JTAG functions In a few lines of Tcl script you should be able to scan and manipulate the JTAG chain through standard Xilinx cables Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Tutorials Description URL Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xlnx xil ans browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com apps appsweb htm Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot ps
285. tions The ChipScope Pro core will capture data based on the trigger condition More than one trigger condition can be defined To add a new trigger condition click the Add button To delete a trigger condition highlight any cell in the row and click Del Although many trigger conditions can be defined for a single core only one trigger condition can be chosen active at any one time Active The Active field is a radio button that indicates which trigger condition is the currently active one ChipScope Pro Software and Cores User Guide www xilinx com 4 29 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Trigger Condition Name Field The Trigger Condition Name field provides a mnemonic for a particular trigger condition Trigger Condition n is used by default Figure 4 37 Add Active Trigger Condition Name I Trigger Condition Equation EH Output Enable T TriggerCondition M7 Pulse High Figure 4 37 Viewing the Trigger Condition Trigger Condition Equation The Condition Equation field displays the current Boolean equation or state sequence of match functions that make up the overall trigger condition By default a logical AND of all the match functions present one match function for each match unit is the trigger condition To change the trigger condition click on the Condition Equation field which brings up the Trigger Condition dialog box Trigg
286. to the data registers Returned values represent IDCODEs of the devices in the JTAG chain jtag shiftdr handle constant 1 bitcount 255 endstate TLR Release the cable lock jtag_unlock handle Close the cable jtag close handle 10 Exit the Tcl shell exit ChipScope Pro Software and Cores User Guide www xilinx com 5 19 UGO29 v7 1 February 16 2005 XILINX Chapter 5 Tcl JTAG Interface 5 20 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005
287. tor Buffer Read Data 7 0 00 9 Directory Entry Offset 5 Directory Entry Read Strobe Edit Run 9 Directory Entry Name ooooooo00000 gt SACF MPU Address 7 0 10 SACF MPU Read Strobe SACF MPU Data 7 0 Sine Wave Select 1 0 SACF CFGADDR 2 0 Reconfigure Strobe ILA Trigger Output T Read Inputs Outputs Activity Display 1 Key Clear All Activity Uni Elle Outputs Green Read Period 250 ms Update Static Read Once Reset All Figure 4 47 The VIO Console Window ChipScope Pro Software and Cores User Guide www xilinx com 4 39 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Bus Signal Column The Bus Signal column contains the name of the bus or signal in the VIO core If it is a bus it can be expanded or contracted to view or hide the constituent signals in the bus In addition to all the operations available in the signal manager two additional parameters can be set through the right click menus type and activity persistence VIO Bus Signal Type The signal s type determines how that signal is displayed in the Value column of the VIO Console Different types are available depending on the type of VIO signal e VIO input signals have the following types display types Text ASCII characters LEDs Choose between Red Blue and Green LEDs Either active hig
288. tory is the Core Generator install path To change it you can either type a new path in the field or click Browse to navigate to a new destination Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ILA ATC core is optimized for the selected device family Use the pull down list to change the device family to the desired architecture The ChipScope Pro Core Generator supports the Virtex Virtex E Virtex II Virtex II Pro Virtex 4 Spartan II Spartan IIE and Spartan 3 device families including the QPro variants of these families Virtex II is the default target device family Note Cores generated for Virtex Il Virtex Il Pro Virtex 4 Spartan 3 or Spartan 3E devices do not work for Virtex Virtex E Spartan ll or Spartan IIE devices Using SRL 16s The ILA ATC core normally uses the SRL16 feature of the FPGA device to increase performance and decrease the area used by the core If the device family is Virtex IL Virtex II Pro Virtex 4 Spartan 3 or Spartan 3E including the QPro variants of these families the usage of SRL16s by the ILA ATC core can be disabled by deselecting the Use SRL16s checkbox It is recommended that the Use SRL 16s checkbox remain enabled Note SRL16s must be used with the Virtex Virtex E Spartan ll or Spartan lIE device families including the QPro variants of these families 2 20 www xilinx com ChipScope Pro Software and
289. tus messages Error messages appear in red The Message pane can be resized by dragging the split bar above it to a new location This also changes the height of the project tree signal browser split pane Main Window Area The main window area can display multiple child windows such as Trigger Waveform Listing Plot windows at the same time Each window can be resized minimized maximized and moved as needed 4 6 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Analyzer Menu Features 7 XILINX Analyzer Menu Features Working with Projects Projects hold important information about the ChipScope Pro Analyzer program state such as signal naming signal ordering bus configurations and trigger conditions They allow you to conveniently store and retrieve this information between Analyzer sessions When you first run the ChipScope Pro Analyzer tool a new project is automatically created and is titled new project To open an existing project select File Open Project or select one of the recently used projects in the File menu The title bar of the Analyzer and the project tree displays the project name If the new project is not saved during the course of the session a dialog box appears when the Analyzer is about to exit asking you if you wish to save the project Creating and Saving A New Project To create a new project select File New Project A new project called ne
290. w Figure 4 6 page 4 9 or by using the File Page Setup menu option Note In the ChipScope Pro 7 1i Analyzer program you can print only to the default system printer Changing the target printer in the print setup window does not have any effect To change printers you must close the Analyzer program change your default system printer and restart the Analyzer program Page Setup Size Letter Source Automatically Select Orientation Margins inches C Portrait Lett 0 18 Right 0 181 Landscape Top 0 18 Bottom 0 18 Cancel Printer Figure 4 12 Page Setup Window ChipScope Pro Software and Cores User Guide www xilinx com 4 13 UGO29 v7 1 February 16 2005 XILINX Chapter 4 Using the ChipScope Pro Analyzer Importing Signal Names At the start of a project all of the signals in every ChipScope Pro core have generic names You can rename the signals individually as described in Renaming Signals Buses and Triggers Ports page 4 3 or import a file that contains all the names of all the signals in one or more cores The ChipScope Pro Core Generator ChipScope Pro Core Inserter Synplicity Certify and the Xilinx FPGA Editor tools can create such files To import signal names from a file select File Import A Signal Import dialog box will appear Figure 4 13 El Signal Import Import File File Directory cXXilimaChipScope Pro 7 1i T Select New File Unit Device OK Cancel
291. w project is created and made active in the Analyzer To save the new project under a different name select File Save Project The project file will have a cpj extension Saving Projects To rename the current project or to save a copy to another filename select File Save Project As Figure 4 3 type the new name in the File name dialog box and click Save ChipScope Pro Analyzer Save Project As Save in CJ ise xst A My Recent Documents Desktop My Documents 48 My Computer a My Network File name um Places Save as type All Files 5 Figure 4 3 Saving a Project ChipScope Pro Software and Cores User Guide www xilinx com 4 7 UGO29 v7 1 February 16 2005 7 XILINX Chapter 4 Using the ChipScope Pro Analyzer Printing Waveforms One of the features of ChipScope Pro 7 1i is the ability to print a captured data waveform as shown in Figure 4 4 by using the File Print menu option as shown in Figure 4 5 Selecting the File Print menu option starts the Print Wizard E Waveform DEV 2 MyDevice2 XC2VP4 UNIT 1 MyILA1 ILA RR NN in mg bd 1 21 41 61 81 101 121 141 161 181 201 221 2 Bus Signal x A E o microProgAddr AAA microPortaddr ORGANO ARROBA microPortDataIn XC 00 ROO OOO ROO a S 31 microPortDataDut 0 OR RRA nicroReadStrobe l l l l i microlriteStrobe ll Jm JU ll JM Jl Ml ll Ji ll JM JIN ll microInterrup
292. windows The window capture mode uses a single trigger condition event i e a Boolean combination of the individual trigger match unit events to collect enough data to fill a sample window In the case where the depth of the sample windows is a power of 2 up to 16384 samples the trigger position can be set to the beginning of the sample window trigger first then collect the end of the sample window collect until the trigger event or anywhere in between In the other case where the window depth is not a power of 2 the trigger position can only be set to the beginning of the sample window Once a sample window has been filled the trigger condition of the ILA core is automatically re armed and continues to monitor for trigger condition events This process is repeated until all sample windows of the sample buffer are filled or the user halts the ILA core N Samples Capture Mode The N Samples capture mode is similar to the Window capture mode except for two major differences e The number of samples per window can be any integer N from 1 to the sample buffer size minus 1 e The trigger position must always be at position 0 in the window The N sample capture mode is useful for capturing the exact number of samples needed per trigger without wasting valuable capture storage resources 1 10 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 ChipScope Pro Cores Description XILINX
293. x It is recommended that the Use SRL 16s checkbox remain enabled Note SRL16s must be used with the Virtex Virtex E Spartan ll or Spartan lIE device families including the QPro variants of these families ChipScope Pro Software and Cores User Guide www xilinx com 2 31 UGO29 v7 1 February 16 2005 XILINX Chapter 2 Using the ChipScope Pro Core Generator Using RPMs The IBA OPB core normally uses relationally placed macros RPMs to increase the performance of the core If the device family is Virtex II Virtex II Pro Virtex 4 or Spartan 3 including the QPro variants of these families the usage of RPMs by the IBA OPB core can be disabled by deselecting the Use RPMs checkbox It is recommended that the Use RPMs checkbox remain enabled for these device families Note RPMs cannot be used with the Virtex Virtex E Spartan ll or Spartan IIE device families including the QPro variants of these families Selecting the Clock Edge TheIBA OPB unit can use either the rising or falling edges of the CLK signal to trigger and capture data The Clock Settings pull down list is used to select either the rising or falling edge of the CLK signal as the clock source for the IBA OPB core Selecting the OPB Bus Settings The IBA OPB core is designed to passively attach to the OPB bus arbiter component in your embedded PowerPC or MicroBlaze processor design Like the OPB bus and arbiter components the IBA OPB core is capable
294. x IE Saudi Spartan 3E LVTIL 3 3V 24mA Fast Yes Yes Yes LVTIL 3 3V 12mA Fast Yes Yes Yes LVCMOS 3 3V 24mA Fast Yes No No LVCMOS 3 3V 12mA Fast Yes No No LVCMOS 2 5V 24mA Fast Yes No No LVCMOS 2 5V 12mA Fast Yes Yes Yes LVCMOS 1 8V 16mA Fast Yes No No LVCMOS 1 8V 12mA Fast Yes Yes No LVDCI 3 3V Yes No No LVDCI 2 5V Yes No No LVDCI 1 8V Yes No No 2 26 www xilinx com ChipScope Pro Software and Cores User Guide UGO29 v7 1 February 16 2005 Generating an ILA ATC Core Output Clock and Data Pin Locations 7 XILINX The output clock and data pins are located inside the ILA ATC core for your convenience Although you do not have to manually bring the clock and data pins through every level of hierarchy to the top level of your design you do need to specify the location of these pins in the Core Generator tool The pin locations are then automatically added to the ncf file of the ILA ATC core Data Width and Depth The data width and depth of the ILA ATC core depend on the transmit rate and the number of data pins Table 2 7 Table 2 7 ILA ATC Core Capabilities Number of Transmit Max Width of Max Data Depth Data Pins Rate Data Port with timestamps 4 1x 3 2 097 120 1 048 560 4 2x 5 1 048 560 1048560 4 4x 11 524 280 262 136 8 1x 7 2 097 120 1 048 560 8 2x 13 1 048 560 524 280 8 4x 27 524 280 262 136 12 1x 11 2 097 120 1 048 560 12 2x 21 1 048 560 524 280
295. x ede keen Re eed 3 6 Inserting and Removing Units o ooocoococccooconccoccro n 3 6 Setting Preferences s ee vr ele Dd 3 6 Inserting the Cores as erae tt e a eet er e Pd ete Ine Cn eed Pee erg 3 6 Exiting the Core Inserter s eetedl e ede tor ha Ro b ce doen de Un 3 6 Specifying Input and Output Files ooococccccccncocconnnorrrno ee 3 7 Project Level Parameters oreet espe tere rteree e ee Ea hee a nae echo 3 8 Selecting the Target Device Family l l 3 8 Using SRETES nidad 3 8 Using RPMS i560 6e Paste id att 3 9 Choosing ICON Options 0 666 e nee 3 9 Disabling JTAG Clock BUFG Insertion sese en 3 9 Choosing ILA or ILA ATC Trigger Options and Parameters 3 10 Selecting the Number of Trigger Ports 0 0 3 10 Entering the Width of the Trigger Ports 3 10 Selecting the Number of Trigger Match Units lees 3 10 Selecting the Match Unit Type ooooocoococconnarr ee n nn 3 11 Selecting Match Unit Counter Width esses een 3 12 Enabling the Trigger Condition Sequencer 2 6 cece eee 3 12 Enabling the Storage Qualification Condition oo ooocoocooconconmmm o mo 3 12 ChipScope Pro Software and Cores User Guide www xilinx com ix UGO29 v7 1 February 16 2005 XILINX Choosing ILA Core Capture Parameters 00 0000 cece cece cece eee 3 13 Selecting the Data Depth cera Lease bees e pU P SEE C e ER Ea 3 14 Selecung the Data T
296. yed in the Message window 4 22 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v7 1 February 16 2005 Analyzer Menu Features XILINX Figure 4 26 The IDCODE and USERCODE can also be displayed in the JTAG Chain Setup dialog box STAG Chain JTAG Chain Setup Figure 4 21 page 4 20 ar INFO Cable Parallel IV Port LPT1 Speed 5 MHz INFO Found 3 Core Units in the JTAG device Chain COMMAND show usercode 2 INFO USERCODE for device 2 fr COMMAND show idcode 2 INFO IDCODE for device 2 11238093 Figure 4 26 Device USERCODE and IDCODE Displaying Configuration Status Information The 32 bit configuration status register contains information such as status of the configuration pins and other internal signals If configuration problems occur select Show Configuration Status from the Device menu for a particular target device to display this information in the messages window Figure 4 27 Note All target devices contain two internal registers that contain status information These two registers are the Configuration Status Register 32 bits and the JTAG Instruction Register variable length depending on the device Only valid target devices have a Configuration Status Register Although all devices have a JTAG Instruction Register that can be read whether any status information is present depends on the implementation of that particular device Refer to the data sheet for a particular devic
297. ynthesis Required Change trigger pattern No Running and stopping the trigger No Enabling the external triggers No Changing the trigger signal source No Changing the data signal source No Changing the ILA clock signal Yes Changing the sample buffer depth Yes a The ability to change existing trigger and or data signal source is supported by the Xilinx ISE 7 1i FPGA Editor System Requirements Software Tools Requirements The ChipScope Pro Core Inserter Core Generator and Tcl JTAG tools require that Xilinx ISE 7 1i implementation tools be installed on your system Tcl stands for Tool Command Language and a Tcl shell is a shell program that is used to run Tcl scripts Tel JTAG requires the Tcl shell that is included in the Xilinx ISE 7 1i tool installation SXILINX bin nt xtclsh exe Communications Requirements The ChipScope Pro Analyzer supports the following download cables see Table 1 12 page 1 26 for communication between the PC and the devices in the JTAG Boundary Scan chain e Platform Cable USB e Parallel Cable IV e Parallel Cable III e MultiPRO e MultiLINXTM e Agilent E5904B TPA ChipScope Pro Software and Cores User Guide www xilinx com 1 25 UGO29 v7 1 February 16 2005 XILINX Chapter 1 Introduction Table 1 12 ChipScope Pro Download Cable Support Download Cable Platform Cable USB Features Uses the USB port USB 2 0 or USB 1 1 to communicate with the Boundary Scan
298. ype coria rra Jehan REPE ERES ones 3 15 Selecting the Data Same As Trigger Ports 0 6 ccc ce eee nee 3 15 Entering the Data Width sser v5 posa rc lv ee REIR Vee ee os 3 16 Number of Block RAMS 0 ccc ce een eee teen nee enee 3 16 Choosing ILA ATC Capture Settings 0 0 0 0 0 666 c ccc cence eee 3 16 Transmit Rate ss 00 10 3 408 A dX RUE a eta EO REOR EROR Rd 3 16 Maximum CLK Port Frequency l i n 3 17 ClockiResource USage curia A CU REC de dae eee tc a eee tes d 3 17 Output Buffer Type viccngeic ten esterase MESA Wo ES LENS erede Ree ne eas 3 17 Number of Data Pins leer ras 3 18 Output Clock and Data Pin Locations 0 0 ec ne 3 18 Data Widthand Depth ces id A tae beer eee AA E 3 18 Choosing ATC2 Data Capture Settings ooooocoocccroooncnnnrranc eee 3 19 Capture Mode x actin tid ence elect a cvi eise degrees 3 20 Clock Edge yenen tere ee nrbi al adas pe EX E brace e xa 3 20 Max Frequency Range ti p drca dde A AAA aeta 3 20 Enable Auto Setup ics sereo scree ERE T naes a HE EE e e 3 20 Enable Always On Mode dais da deta e EAR CE ET E Rd 3 20 Pin Edit Modera rara eG ae spite eee ER LIC ES 3 20 ATD Pin Counts ete A ES t de dr a a a ER ARA 3 20 Endpoint Type 2 241200 vee diarreas rro pra I rbd eire e bees 3 21 Signal Bank Count 32i A cse el hice tet gees e 3 21 TDM Rallen uri a pdt t dc 3 21 Data Width iii is ERREUR A DER AAA ARA AA See Rr RR 3 21 Pin Parameters se caseo pra aa a ege ek

Xilinx UG029 ChipScope Pro Software and Cores User Guide v7.1

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