SIS3803 VME Scaler/Counter User Manual
Contents
1. Map etat ERR RD ee eet e eget ee eerte ee etd 8 Register Description de Bs n a 8 1 Status Register 0X0 due tote er ERR UU GIORNI UR e Er He REX ERO EEEE 14 8 2 Control Register OX raster REPREHEN TENENTUR EA ree gebe RR RE e e PRA EREEEI 15 8 3 Module Identification and IRQ control register 0x4 is a 16 8 4 Count disable register OxC i ux is ue 17 8 5 Overflow registers 0x380 0x3A0 s eis ses s 17 8 6 Broadcast Addressing i ede ne eie EO Ir Ee dus oe ER TO trien eet te V 17 EM 19 10 Data Format zn E uA be x TOT D16 tet eee Re Rn e RR e iet Ruta ee m texte Re RR AIDE 11 Readout Schemes 11 1 Read Shadow Register 11 2 Read and Clear all Counters m wis ae T TT 3 Read Countess eee rettet tee Ee ERE Waa WERE ERE SII Ne Arte eset ever A eet 20 12 Input Configuration 12 ECL eet 12 2 NM 123 TTL 12 3 1 TTL LEMO sats m BIN i 12 3 2 EIIJElat Cable tette nt eie e re i eR ne De e He genes esee p eg 13 Connector SpecifICAllon s oue o EUR MOOR MORIR 14 Control Input Modes 15 Signal Specification 15 1 Control Signals as tts ee is 152 Inputs xx ccena testi Dee ee Rte tee ATA eee o e des 16 Operating Conditions ission teet e dere D e ie e tete ERN tentent ee ee E redo 16 1 Power Consumption Voltage requirement seks es is 162 Cooling vnacum pite tet oe de RU e TA D eee e Odes 16 3 Insertion Remoyal erect e2. N OxIBC D16 D32 read shadow register does not initiate clock shadow BLT32 0x280 D16 D32 read counter initiates clock shadow also EET mm mm 8 0x300 D16 D32 read and clear all counters 0x33C BLT32 0x380 R D16 D32 Overflow register channel 1 8 0x3A0 R D16 D32 Overflow register channel 9 16 Note D08 is not supported by the SIS38xx boards Page 13 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 8 Register Description 8 1 Status Register 0x0 The status register reflects the current settings of most of the SIS3803 parameters in read access in write access it functions as the control register 31 0 Status VME IRQ source 2 test IRQ 2 Status VME IRQ source 1 ext clock shadow 2 Status VME IRQ source 0 Overflow 29 Status VME IRQ source 1 ext clock shadow o O 28 Staus VME IRQ source 0 Overflow Cid a CN NN S o ZZZ AE O B Oe 0 reserved read back as 0 at power up Global Count Enable General Overflow Bit Status enable reference pulser channel 1 2 0 10 oo ii TO OT 8 do U O 7 Status broadcast mode handshake controller 6 Status broadcast mode o 2 Status input mode bit 0 Status IRQ source 2 for software IRQ testing o Status user LED The reading of the status register after power up or key reset is 0xO see default settings of control register Page 14 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME
3. counter channels and a maximum counting frequency of 200 MHz ECL and NIM 100 MHz TTL respective As all boards of the family it is of single slot double Eurocard form factor and available with flat cable connectors for ECL and TLL levels and LEMO connectors for NIM and TTL levels The SIS360x 38xx card is a flexible concept to implement a variety of latch and counter firmware designs The flexibility is based on two to six Xilinx FPGAs in conjunction with a FLASHPROM from which the firmware files are loaded into the FPGAs Depending on the stuffing options of the printed circuit board the user has the possibility to cover several purposes with the same card hence the manual is a combination of firmware and hardware description All cards of the family are equipped with the 5 row VME64x VME connectors a side cover and EMC front panel as well as the VIPA LED set For users with VME64xP subracks VIPA extractor handles can be installed The base board is prepared for VIPA style addressing the current first version of the SIS3803 firmware does not feature VIPA modes yet however As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals htm A list of available firmware designs can be retrieved from http
4. in two Xilinx chips also The actual firmware is loaded into the FPGAs upon power up from a FLASHPROM under jumper control The user can select among up to eight different boot files by the means of a 3 bit jumper array The counter and control inputs can be factory configured for ECL NIM and TTL levels on the control outputs the same levels are the available as options The standard SIS3803 design has no outputs implemented The front panel is available as flat cable ECL and TTL or LEMO NIM and TTL version The board layout is illustrated with the block diagram below Page 6 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME Driver Receiver _ Control Level Adaption XILINX Driver Receiver 7 VME Interface XILINX Level Adaption Driver Receiver Level Adaption Driver Receiver Level Adaption Driver Receiver File Level Adaption XILINX Selection Driver Receiver SIS3803 Block Diagram 3 2 Counter Design and Modus Operandi The counters are implemented in XILINX FPGAs One of the counter FPGAs holds 8 32 bit deep counter channels The actual scaler contents are passed to the VME bus via a shadow register The scaler data have to be copied into the shadow register before readout via a software command or a front panel hardware pulse This can take place in parallel to the acquisition of counts what is called read on the fly On a read on the fly the status of the lowest 6 bits may b
5. respective bit in the VME control register disabling is done with the sources J K bit Interrupt generation has to be enabled by setting bit 11 in the IRQ and version register The internal VME interrupt flag can be used to check on an IRQ condition without actually making use of interrupts on the bus The VME interrupt level 1 7 are defined by bits 8 through 10 and the VME interrupt vector 0 255 by bits O through 7 of the VME IRQ and version register In general an interrupt condition is cleared by disabling the corresponding interrupt clearing the interrupt condition i e clear overflow and enabling the IRQ again Note In most cases your experiment may not require interrupt driven scaler readout but the interrupt capability of the SIS3803 provides a way to overcome the problem of missing front panel inputs on most commercial VME CPUs VME IRQ ENABLE Overflow Souceg Enable 0 Clear gt Dos VME IRQ ext Shadow CtrlReg Bit1 Enable 2 Source 1 INTERNAL_VME_IRQ Source 2 Page 19 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 10 Data Format The data format of the actual counter values read via the shadow register for D16 and D32 reads is shown in the two tables below 10 1 D16 high Byte Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 10 2 D32 Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 11 Readout Schemes Scaler dat
6. www struck de sis3638firm htm Page 5 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 3 Technical Properties Features The SIS3803 is rather a firmware design in combination with given board stuffing options than a name for the board this is the reason why the modules are named SIS360x 38xx on the front panel and the distinction of the units is made by the module identifier register The firmware makes use of part of the possibilites of the SIS360x 38xx PCB if the SIS3803 or other firmware designs of the family come close to what you need but something is missing a custom firmware design may be an option to consider Find below a list of key features of the SIS3803 e 16 channels e 200 MHz counting rate ECL and NIM 100 MHz for TTL 32 bit channel depth NIM TTL ECL versions flat cable TTL ECL and LEMO TTL NIM versions Shadow register e Read on the fly e A16 A24 A32 D16 D32 BLT32 CBLT32 prepared e Base address settable via 5 rotary switches A32 A12 and one jumper A11 e VME interrupt capability e VIPA geographical addressing prepared VIPA LED set Reference Pulser Capability Up to eight firmware files single supply 5 V 3 1 Board Layout Xilinx FPGAs are the working horses of the SIS360x 38xx board series The counter prescaler latch logic is implemented in one to four chips each chip handles eight front end channels The VME interface and the input and output control logic reside
7. zabcd VME P1 P2 Harting 02 01 160 2101 20 pin header Control flat cable versions DIN41651 20 Pin AMP e g 34 pin header Inputs flat cable versions DIN41651 34 Pin AMP e g LEMO Control and Input LEMO versions LEMO ERN 00 250 CTL Page 23 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 14 Control Input Modes The assignment of the control inputs can be controlled via the input mode bits in the control register The only mode using the control inputs at present is mode 1 Control Input Modes Mode 0 bit1 0 bit0 0 all control inputs are disabled Mode 1 bit1 0 bit0z 1 input 1 gt disable count all channels input 2 clear all channels input 3 gt external clock shadow register input 4 gt external test pulse max 50 MHz Mode 2 bitl 1 bit0 0 all control inputs are disabled Mode 3 bitl 1 bit0z1 all control inputs are disabled Note The SIS3803 Inline LEMO version has enough front panel space for three letter input labels In return there is no possibility to add output functionality in a later firmware revisions due to four omitted control LEMOs Control Input Modes Mode 1 bit1 0 bit0z1 INH disable count all channels CLR gt clear all channels CLK gt external clock shadow register TST external test pulse max 50 MHz Page 24 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 15 Signal Specification 15 1 Control Signals The width of t
8. 0 SIS3803 Version SIS3803 151298 0 SIS3803 Version 1 Inline Page 34 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 19 7 Row d and z Pin Assignments The SIS3803 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Rowz Inr D GND GND Eg Oooo E N Rowz x GND Ooo GND p E EDEN Ooo Boa a Ooo GND p GND an p E p i CREME poo a5 GND Oo pd eel GND E GND ed Oooo E Oooo ae GND Oooo el GND GND Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 35 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 19 8 Geographical Address Pin Assignments The SIS38xx board series is prepared for geographical addressing via the geographical address pins GAO GA1 GA2 GA3 GA4 and GAP The address pins are left open or tied to ground by the backplane as listed in the following table Slo GAP GA3 GAI Number Pin Pin Pin Pin i en en Open GAO0 JE eg ie 1 o Q O O Oo o Z u s RE 5 9 s Iolo olelelel ely 8 Iols lols o ooo S S 2o d Q Z J Q 2zz J Q Z J Oo Oo JE 8 o
9. 32 30 addressing mode 28 Addressing mode 30 addressing modes 12 Adressing 9 Base address 9 Base Address 12 30 block diagram 6 BLT 28 Board Layout 32 Boot File Selection 30 Bootfile Selection 31 Broadcast Addressing 17 broadcast handshake controller 17 broadcast mode 15 broadcast mode handshake controller 15 broadcast time jitter 17 CBLT 28 CERN 36 Clear Logic 8 Connector Specification 23 control input 30 Input Modes 24 output 24 Register 15 Control and Status register 13 Cooling 25 Count disable register 17 Count Enable 8 custom firmware 6 CVI 27 call back routines 27 project file 27 D08 O 16 D16 20 D32 20 Data Format 20 DC DC converter 30 drivers 27 ECL 5 21 En A16 9 EN A16 12 30 En A24 9 EN A24 12 30 En A32 9 EN A32 12 30 External Latch Shadow Input 19 SIS3803 SIS GmbH 4 Scaler Counter VME Factory Default Settings 9 firmware 5 firmware design 9 16 Firmware Design 9 Firmware Selection 10 Bootfile 10 Examples 10 FLASHPROM 5 6 9 10 FLASHPROM Versions 34 flat cable 5 Floppy 27 FNAL 36 Front Panel LED 11 Front Panel Layout 29 GAO 36 GA1 36 GA2 36 GA3 36 GA4 36 GAP 36 geographical address pins 36 Geographical Address 36 geographical addressing 35 Getting Started 9 hot swap 25 35 http Iwww vita com 36 inline 24 29 33 Input Configuration 21 input mode 15 Input Priority 26 input test mode 15 26 Insertion Removal 25 interrupt acknowledge cycle 16 interrupt condition 19 inte
10. 8 2 Control Register 0x0 The control register is in charge of the control of most of the basic properties of the SIS3803 board in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which has a different location within the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register ee ne tO o reserved VEL COoOOSR 7v Msia 25 reserved S pts ih asooeee aisah Uidadeast mode handshale controller 9 clearIRQtestsource2 o 8 swithoffuserLED 0 6 emablebradcastmode S O enable input test mode 5 enableinputtestmode ee O 3 set input mode bit 1 0 switch on user LED denotes the default power up or key reset state Page 15 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME amp 3 Module Identification and IRQ control register 0x4 This register has two basic functions The first is to give information on the active firmware design This function is implemented via the read only upper 20 bits of the register Bits 16 3 hold the four digits of the SIS module number like 3803 or 3600 e g bits 12 15 hold the version number The version number allows a di
11. ACK cycle 3 ___fread wvrite 00 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle HL essei IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle The second function of the register is interrupt control The interrupter type of the SIS3803 is D08 O Via bits 0 7 of the module identifier and interrupt control register you can define the interrupt vector which is placed on the VME bus during the interrupt acknowledge cycle Bits 8 through 10 define the VME interrupt level bit 11 is used to enable bit set to 1 or disable bit set to 0 interrupting Module identification and version example The register for a SIS3801 in straight 32 bit mode version 1 reads 0x3801Innn for a SIS3801 in 24 bit mode version 2 it reads 0x38012nnn the status of the lower 3 nibbles is denoted with n in the example Page 16of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 8 4 Count disable register OxC The count disable register can be used to disable single channels or arbitrary groups of channels Note that both the external if used and the internal conditions have to be in status enable for the given channel The register is write only If bit N of the register is set channel N 1 is disabled Example If 0x5 is written to the count disable register counting of channel 1 and 3 is dis
12. Power Access and Ready plus 5 additional LEDs VME user LED Clear Overflow Scaler enable and VIPA user LED I iimwe ed pean poe 3 Rc a o lied Signals configured lope Signals soft or hardware clear The LED locations are shown in the portion of the front panel drawing below The VME Access the Clear and the Scaler enable LED are monostable i e the duration of the on phase is stretched for better visibility the other LEDs reflect the current status An LED test cycle is performed upon power up refer to the chapter 17 1 Page 11 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 7 VME addressing 7 1 Address Space As bit 11 is the lowest settable bit on the 360x 38xx board an address space of 2 Kbytes Offset plus 0x000 to Ox7ff is occupied by the module 72 Base Address 7 2 1 VME The VME addressing mode A16 A24 A32 is selected via the jumpers EN Al6 EN_A24 and EN_A32 The mode is selected by closing the corresponding jumper it is possible to enable two or all three addressing modes simultaneously The base address is set via the five rotary switches SW_A32U SW_A32L SW_A24U SW A2AL and SW_A16 and the jumper J All The table below lists the switches and jumpers and their corresponding address bits SW ADAL 19 16 SW AI6 15 12 JAM In the table below you can see which jumpers and switches are used for address decoding in the three different addressing modes fie
13. SIS Documentation SIS3803 SIS GmbH Scaler Counter VME SIS3803 VME Scaler Counter User Manual SIS GmbH Moorhof 2d 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version 1 2 as of 20 12 99 Page of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME Revision Table Modification 0 ps 07 98 18 09 98 FIFO flag changes V2 V3 PAL 5 20 12 99 Introduction of revision table Inline front panel design Page 2 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 1 Table of contents 1 Table of Contents oett PR EE A EA E E EAA E A A 3 2 Introduction eee T ish oi dec ve e Eder o ei e 5 3 Technical Properties Features ze sins EET 6 3 1 Board Layout sees eA ees Ree eee EN eer Tere 6 3 2 Counter Design and Modus Operandi T T Beet eere J 3 3 Count Enable Logic 2b ga e Qus N d An 8 3 4 Clear Logic ne e is E to DR RR OE 8 4 Getting Startedu iini eR RR PORRO te rg RU et eet 9 4 1 F ctory Detault Settings deett eee epe et eite dedu 9 4 1 1 Adressing 4 1 2 System Reset Behaviour 5 Firmware Selection 5 1 Examples 6 Front Panel LEDs A 7 VME addressing 7 1 Address Space 7 2 Base Addre 8 55 sra E OERE e RUPEE RR RUEORE EUR S per PROPRE 7 2 1 4 222 VIPA VME64x 7 3 Address
14. a can be read from different locations The read location has an impact on the counter behaviour 11 1 Read Shadow Register In a single cycle or block transfer read from the shadow register 0x200 0x23C the data from the last transfer to the shadow register are obtained No automatic clock shadow is initiated i e if the user wants to read the actual scaler values he has to ensure a soft or hardware clock shadow before the read 11 2 Read and Clear all Counters In a single cycle or block read from the read and clear all counter registers 0x300 0x33C the data are transferred into the shadow register all counters are cleared after the transfer and the shadow data are read Note If your CPU does not support block transfer you can ensure synchronicity to 5 ns by reading the first scaler value from 0x300 and the rest from the shadow registers 0x204 0x23C 11 3 Head Counter The read counter behaves like the read and clear all counters except that the counter values are not cleared after the copy to the shadow register Page 20 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 12 Input Configuration SIS36 38xx boards are available for NIM TTL and ECL input levels and in LEMO and flat cable versions The boards are factory configured for the specified input level and connector type input termination is installed 12 1 ECL The 100 Q input termination can be removed in groups of four channels by removing the correspondin
15. abled 8 5 Overflow registers 0x380 0x3A0 Each overflow register holds the overflow bit of eight counter channels i e of one counter XILINX in its highest eight bits Example register 0x380 holds the overflow bits of channels 1 8 as shown in the table below Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 undefined 8 6 Broadcast Addressing Broadcast addressing is an efficient way to issue the same command to a number of modules It can be used in A24 and A32 mode on SIS360x 38xx boards The higher address bits are used to define the broadcast class the distinction of the modules is done via the A16 rotary switch and the A 11 jumper If broadcast addressing is used the A32 U the A 32 L the A24 U and the A24 L rotary switches must have the same setting in A32 mode in A24 mode the A24 U and A24 L setting must be the same on all participating units One of the participating units must be configured as broadcast handshake controller by setting bit 7 in the units control register All of the participating units must have set bit 6 enable broadcast in the control register The broadcast time jitter was measured to be less than 40 ns within a VME crate i e you have the possibility issue commands under software control with a maximum uncertainty of 40 ns like clear all counters what sure is worse than a hard wired front panel clear but is much better than a VME single cycle loop over a number of units The four broadcast commands a
16. ard can contain several boot files A list of available FLASHPROM versions can be found on our web site http www struck de in the manuals page If your FLASHPROM has more than one firmware design you can select the Page 9 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME desired firmware via the firmware selection jumper array J500 You have to make sure that the input output configuration and FIFO configuration of your board are in compliance with the requirements of the selected firmware design a base board without FIFO can not be operated as multi channel scaler e g A total of 8 boot files from the FLASHPROM can be selected via the three bits of the jumper array The array is located towards the rear of the card between the VME P1 and P2 connectors The lowest bit sits towards the bottom of the card a closed jumper represents a zero an open jumper a one 5 1 Examples The figures below show jumper array 500 with the soldering side of the board facing the user and the VME connectors pointing to the right hand side Bootfile O selected With all jumpers closed boot file 0 is selected Bootfile 3 selected With the lowest two jumpers open bit 0 and bit 1 are set to 1 and hence boot file 3 is selected Page 10 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 6 Front Panel LEDs The SIS3803 has 8 front panel LEDs to visualise part of the units status Three LEDs according to the VME64xP standard
17. cation 25 VME64x 12 35 Control 25 connector 5 Inputs 25 VME64xP 5 12 35 Single Pulse 26 Voltage requirement 25 SIS360x 38xx 5 VxWorks 27 Software Support 27 Windows 95 27 Status Register 14 XILINX 7 Page 38 of 38
18. e in counts with 40 ns you can measure the single word access time 17 3 Reference pulser channel 1 The reference pulser for channel 1 can be seen rather as a monitoring feature than a test feature It sets the counting rate of channel 1 to 25 MHz note that a simultaneous front panel signal on channel 1 is ignored 17 4 Signal Input Priority If the user happens to enable more than one input option enable test mode enable reference pulser scaler enable at the same time the priority is as show in the table below Reference Pulser channel 1 only Front Panel Inputs Example If test mode and reference pulser are enabled at the same time channel one will count test pulses i e will count synchronous with the test pulser Page 26 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 18 Software Support VME scaler boards are tested at SIS with an OR VP6 VME CPU Pentium II based under Windows 95 and a National Instruments CVI user interface The actual VME C code makes use of the OR Windows 95 DLL which has straightforward to read and understand routines like VMEA24StdWriteWord a32address KEY RESET 0x0 Key Reset rdata VMEA24StdReadWord a32address STAT REG In most cases the user setup will be using different hardware a full fleshed real time operating system like VxWorks and a different user interface We still believe that it is helpful to have a look at the code
19. e not accurate i e the counter readout value is accurate modulo 64 read on the fly readout accuracy down to one count can be achieved with the SIS3801 multiscaler No pulses are missed during a read on the fly i e the frontend continues counting A diagram of the setup is shown in the figure below The different readout schemes are addressed in the key register section Latch Scaler Channel External gl Control Clock Register mS VME Clock Shadow VME Interface Page 7 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 3 8 Count Enable Logic A channel acquires input or test counts if the selective count enable and the global count enable conditions are true Via the test enable toggle bits in the control register the input of the counter is switched to test pulses or front panel signals AND Count Enable Selective Disable Enable Scaler Control Input Disable Scaler Channel N 25 MHz reference channel 1 only Input N 25 MHz test pulses Single Test Pulse External Test Pulse 3 4 Clear Logic The contents of the counters can be cleared via VME access or a front panel pulse The four possible clear sources are ored as shown in the diagram below Scaler Channel N External Clear VME Selective Clear Channel N VME Clear All Clear after VME read Page 8 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 4 Getting Started The minimum setup to operate the SIS3803 requir
20. ecognised by the 5 row VME connectors while the standard VME backplane has three row connectors only Page 25 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 17 Test The SIS380x scaler series provides the user with a number of test features which allow for debugging of the unit as well as for overall system setups 17 1 LED selftest During power up self test and LCA configuration all LEDs except the Ready R LED are on After the initialisation phase is completed all LEDs except the Ready R LED and the Power P have to go off Differing behaviour indicates either a problem with the download of the firmware boot file or one or more LCA and or the download logic 17 2 Internal pulser tests 17 2 1 Single Pulse A single pulse into all channels can be generated with a write to the key address 0x68 if test mode is enabled via the control register In conjunction with the count enable register more complex count patterns like increment patterns e g can be generated before readout 17 2 2 25 MHz Pulser Simultaneous pulsing at 25 MHz into all channels can be used to test the complete readout chain and internal counter logic of the SIS3803 The feature is activated by enabling input test mode and 25 MHz test pulses via the corresponding bits in the control register The 25 MHz test pulser gives easy access to your VME CPUs readout timing By making subsequent reads to the same counter and multiplying the differenc
21. ene rece t RHET etes tee HT perse ERE TAa 17 Testo act eet 17 1 LED selftest 17 2 Internal pulser tests m EE ise 172 1 Simple Pulse zc eso ARR Ae A hl het tS 17 22 25 MHZ Pulser eee ree RO ie eR ten e entr cede Eo E EEEN UR DER 26 17 3 Reference pulser channel 1 A c T s I7 4 Signal Input PriOttty zer Hp E E e t E ee des Page 3 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 18 SOftWare SUDDOEL 3 med teet ette edi tede er e ere e RE be eon 18 1 Contents of the included Floppy 19 Append soie ETET d e EID bb ree RP RD 19 1 Address Modifier Overview 19 2 Front Panel Layout 19 3 List of Jumpers sse 19 4 Jumper and rotary switch locations 19 4 1 Addressing mode and base address selection seen entente 19 4 2 J500 Bootfile Selection and J520 SYSRESET Behaviour 19 5 Board Eayout eot o bL e EDEN eR se e e E Rebeca du ieu 195 ECE andtworow LEMO version etel ete ee du recie eie e o ettet te e PRISE 19 5 2 Inline LEMO version eee 19 6 FLASHPROM Versions 19 7 Row d and z Pin Assignments 19 8 Geographical Address Pin Assignments 19 9 Additional Information on VME Page 4 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 2 Introduction The SIS3803 is one of the classic VME counter scaler implementations on the base of the SIS360x 38xx printed circuit board The unit has 16
22. es the following steps e Check the proper firmware design is selected should be design zero i e all jumpers of jumper array J500 set Select the VME base address for the desired addressing mode Select the VME SYSRESET behaviour via J520 turn the VME crate power off install the scaler in the VME crate connect your signals to the counter turn crate power back on e set global count enable via key address 0x28 e read all counters with clock shadow register via block transfer from start address 0x280 read or 0x300 read and clear or subsequent single word reads A good way of checking first time communication with the SIS3803 consists of switching on the user LED by a write to the control register at offset address OxO with data word Ox1 the LED can be switched back off by writing 0x1000 to the control register 4 1 Factory Default Settings 4 1 1 Adressing SIS3803 boards are shipped with the En A32 the En A24 and the En A16 jumpers installed and the rotary switches set to 3 p 3 po 41 5 3 9 g 9 B ee Setting 3 8 Jumper A_11 is open bit 11 set Hence the unit will respond to the following base addresses 0x38383800 0x383800 0x3800 Firmware Design Design 1 of the FLASHPROM is selected lowest jumper of jumper array J500 open the others set 4 1 2 System Reset Behaviour J520 is set i e the SIS3803 is reset upon VME reset 5 Firmware Selection The FLASH PROM of a SIS360x 38xx bo
23. g resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel 1 K Networks RN10 RN11 12 RN20 RN21 22 The schematics of the ECL input circuitry is shown below GND SIL RN 1 X1 SIL RN 1 X0 SIL RN 1 X2 Page 21 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 12 2 NIM The 50 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel The schematics of the NIM input circuitry is shown below i T Ref 0 35 V Page 22 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 12 3 TTL The TTL input level option is possible with LEMO and flat cable connectors 12 3 1 TTL LEMO The low active TTL LEMO input circuitry is sketched below A high active version can be implemented by replacing the 74F245 with a 74F640 5V m P 1K 245 12 3 2 TTL Flat Cable In the flat cable TTL version the positive right hand side of the connector is tied to ground NE 3 1K EE 245 13 Connector Specification The four different types of front panel and VME connectors used on the SIS360x and SIS38xx boards are Connector Purpose Part Number 160 pin
24. he clear and external latch shadow pulse has to be greater or equal 10 ns an external inhibit has to be present for the period you desire to disable counting An internal delay of some 15 ns has to be taken into account for all external signals 15 2 Inputs The SIS3803 is specified for counting rates of 200 MHz for ECL and NIM signals and 100 MHz for the TTL case Thus the minimum high and low level duration is 2 5 ns 5 ns respective Signal deterioration over long cables has to be taken into account 16 Operating Conditions 16 1 Power Consumption Voltage requirement Although the SIS3803 is prepared for a number of VIPA features it was decided to use an ob board DC DC converter to generate the 5 V which are needed for driver and receiver chips to allow for the use of the module in all 6U VME environments The power consumption is counting rate dependent it varies from the idle value of 5 V 3 3 A to 5 V 4 5 A with all channels counting at 200 MHz i e the power consumption is lt 23 W 16 2 Cooling Forced air flow is required for the operation of the SIS3803 board 16 3 Insertion Removal Please note that the VME standard does not support live insertion hot swap Hence crate power has to be turned off for installation and removal of SIS3803 scalers The leading pins on the SIS3803 VME64x VME connectors and connected on board circuitry are designed for hot swap in conjunction with a VME64x backplane a VME64x backplane can be r
25. jos S ololol lol o s 2 8 ols Open Open Open GND Open Open Open GND Open GND GND QIQIO a ziz 5 o O O e e S5 are o Z Z Q Qo O Q Q Q golog oo I Q u Open GND GND GND Open Open D Q2 z 5 O 3 5 Q u aa e 5 P s B 5 5 5 open GND GND N N N 22 ala Z olo olok s Iolo o 5B m Z d 1 B oos 8 iols lols o a OQ O O Q O Q O a Q O 5 GND Open Open i pen GND GND en o 5 Q Q O o Z Z S 919 12 s iojo G Q oo aeo OS IZ UIS Q S Q O Q 19 9 Additional Information on VME The VME bus has become a popular platform for many realtime applications over the last decade Information on VME can be obtained in printed form via the web or from newsgroups Among the sources are the VMEbus handbook http www vita com the home page of the VME international trade association VITA and comp bus arch vmebus In addition you will find useful links on many high energy physics labs like CERN or FNAL Page 36 of 38 SIS Documentation 20 Index 24 bit mode 17 25 MHz Pulser 26 25 MHz test pulses 15 32 bit mode 17 A 11 9 30 A16 9 A24 9 A24 Broadcast Example 18 A32 9 A32 Broadcast Example 17 Address Map 13 Address Modifier Overview 28 address modifiers 28 Address Space 12 addressing A16 A24 A
26. lds marked with an x are used _ SW_A32U SW_A32L SW_A24U SW_A24L SW_A16 JAN x x Hooccee doo ume 0 oe 1 pU a pA nlsi pup eee ees aes a ee oe Note J_A11 closed represents a 0 J_A11 open a one 7 2 2 VIPA VME64x As the VME64x and the VME64xP VIPA standard are not yet standards to refer to and to declare conformity with addressing modes like geographical addressing e g according to these standards are prepared but not yet implemented in the current firmware revisions Page 12 of 38 SIS Documentation SIS3803 SIS GmbH Scaler Counter VME 7 3 Address Map The SIS360x 38xx boards are operated via VME registers VME key addresses and the FIFO where installed The following table gives an overview on all SIS3803 addresses and their offset from the base address a closer description of the registers and their function is given in the following subsections 0x000 R W D16 D32 Control and Status register 0x004 R W DIGD32 Module Identification and IRQ control register Ox00C W__ D16 D32_ Selective count disable register 0x020 KA W D16 D32_ clear all counters and overflow bits _ 0x024 D16 D32 clock shadow register D KA w Depa sib count enable 0x060 KA W D16 D32 reset register global reset 0x068 KAL WwW D16 D32 Test pulse generate a single pulse D16 D32 clear counter N and its overflow bit Ox180 KA D16 D32 clear overflow bit of counter
27. outputs are grouped to one 8 channel block and the counter inputs are grouped into one block of 16 channels The units are 4 TE one VME slot wide the front panel is of EMC shielding type VIPA extractor handles are available on request or can be retrofitted by the user if he wants to change to a VIPA crate at a later point in time In the drawing below you can find the flat cable left hand side LEMO middle and Inline LEMO right hand side front panel layouts Note Only the aluminium portion without the extractor handle mounting fixtures is shown GIA f AD Dje SIS3803 Scaler DATA Page 29 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 19 3 List of Jumpers Find below a list of the jumpers and jumper arrays Jumper Name Array Singl Function e Single le Input Termination Input Termination Control Input Input 1 19 4 Jumper and rotary switch locations 19 4 1 Addressing mode and base address selection The EN A32 EN_A24 EN_A16 A 11 and the 5 rotary switches are located int the middle of the upper section of the board close to the DC DC converter the corresponding section of the PCB is shown below cx o scibiiiiii Bitte FE ojan o o o o o o oj 7 oja N coon A320 Si 32L A24U SLLA24L SUMS a le 8 3 BE U Page 30 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 19 4 2 J500 Bootfile Selection and J520 SYSRESET Behaviour The jumpe
28. r array J500 is located between the P1 and the P2 connector An open position in J500 defines a one see also chapter 4 the lowest bit is next to the P2 connector J520 is located to the left of J500 and closer to the DC DC converter With jumper J520 closed the SIS3803 executes a key reset upon the VME SYSRESET signal The section of the board with the jumper array and the SYSRESET jumper is shown below 0851232 oN U180 LCA 3190 PQ160 Page 31 of 38 SIS GmbH VME SIS3803 Scaler Counter SIS Documentation Ei gveeseevev e 99929 n ececcce wom ele 6 Ble 6 6 9m a Be 6 2 s mle 9 2 ole 2 ole p um TIT UUU ue au DE 423 19 5 Board Layout 19 5 1 ECL and two row LEMO version Page 32 of 38 oO Ss 25 eo Uu zE O un SIS Documentation 19 5 2 Inline LEMO version Page 33 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 19 6 FLASHPROM Versions A list of available FLASHPROMSs can be obtained from http www struck de sis3638firm htm Please note that a special hardware configuration may be necessary for the firmware design of interest the SIS3801 design requires the installation of a FIFO e g The table on the web is of the format shown below SIS36 38xx FLASHPROM table Boot File s SIS3800 201098 a SIS3800 Version 1 SIS3801 201098 SIS3800 Version 1 ae SIS3800 Version 2 SIS3803 131198
29. re executed via the VME key addresses at offset 0x030 through Ox3C A32 Broadcast Example Let four SIS3803 participate by setting the A_32 jumper and setting the base address of the units to Unit 1 0x32001000 Unit 2 0x32001800 Unit 3 0x32002000 Unit 4 0x32002800 Switch on enable broadcast by setting bit 6 in the control register of the four units Enable broadcast handshake controller on unit 4 by setting bit 7 of its control register An A232 write to address 0x32000034 will clock the shadow register on units 1 through 4 A24 Broadcast Example Page 17 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME Let three SIS3803 participate by setting the A 24 jumper and setting the base address of the units to Unit 1 0x541000 Unit 2 0x542000 Unit 3 0x543000 Switch on enable broadcast by setting bit 6 in the control register of the three units Enable broadcast handshake controller on unit 1 by setting bit 7 of its control register An A24 write to address 0x540030 will clear the counters on units 1 through 3 Page 18 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 9 VME Interrupts Three VME interrupt sources are implemented in the SIS3803 firmware design e Overflow e External Latch Shadow Input e Test Interrupt The interrupter is of type D8 O The interrupt logic is shown below For VME interrupt generation the corresponding interrupt source has to be enabled by setting the
30. rrupt control 16 interrupt level 16 19 interrupt logic 19 interrupt vector 16 19 interrupter type 16 IRQ source 15 J A11 12 30 J101 J108 30 J115 30 J500 9 30 31 J520 9 30 31 jumper firmware selection 10 VME addressing mode 12 Jumper overview 30 Jumper and rotary switch locations 30 key address 13 LED 11 Access 1l Color 11 Power 11 Ready 11 user 9 LEMO 5 live insertion 25 35 Page 37 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME Module Identification and IRQ control register 16 SW A16 9 12 Module Identification and IRQ Control register 13 SW_A24L 9 12 module number 16 SW_A24U 9 12 monostable 11 SW A32L 9 12 NIM 5 22 SW A32U 9 12 Operating Conditions 25 SYSRESET Behaviour 31 OR VP6 27 System Reset 10 output Technical Properties Features 6 control 24 Test Interrupt 19 Overflow 19 TTL 5 23 Overflow registers 17 version number 16 PCB 6 VIPA 25 Pentium II 27 addressing 5 Power Consumption 25 base address 12 Read and Clear Counter 20 extractor handles 5 Read Counter 20 LED set 5 read on the fly 7 VITA 36 Read Shadow Register 20 VME 25 36 Readout Schemes 20 addressing mode 12 Reference pulser channel 1 26 Base Address 12 register CPU 27 Control and Status 13 SYSRESET 31 count disable 13 17 SYSRESET Behaviour 30 Module Identification and IRQ Control 13 VME addressing 12 shadow 7 VME control register 19 rotary switch 30 VME Interrupts 19 shadow register 7 VME IRQ and version register 19 Signal Specifi
31. stinction between different implementations of the same module number the SIS3801 for example has the 24 bit mode with user bits and the straight 32 bit mode as versions Module Identification Bit Module Identification Bit15 30 read only Module Identification Bit 14 Module Id Digit 3 29 readonly Module Identification Bit 13 28 readonly Module Identification Bit12 27 l Readonly Module Identification Bit I1 Identification Bit 11 26 readonly Module Identification Bit 10 Module Id Digit 2 25 readonly Module Identification Bit9 ei pooni P A BiS O Module Identification Bit 7 5 read only Module Identification Bite Module Id Digit 1 21 readonly Module Identification BitS 20 readonly Module Identification Bit4 Module Identification BES Identification Bit 3 rig readonly Module Identification Bit2 Module Id Digit 0 17 readonly Module Identification Bit 5 readony VersionBit3 ooo 14 Do sss i E read write is D o readisrie VMEIRO Level Bi I 8 read write VMEIRQLevelBitO U O IRQ Vector Bit t placed on D7 during VME IRQ ACK cycle 6 read write IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 read write IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 4 read wrte IRQ Vector Bit 4 placed on D4 during VME IRQ
32. which is used to test the units and to take it as an example for the implementation of the actual scaler readout application A floppy with our test software is enclosed with SIS3803 shipments Depending on the user feedback and co operation we expect that we will have drivers or at least example routines for the commonly used VME CPU operating systems at hand in the mid term 18 1 Contents of the included Floppy The Floppy contains a readme txt file with the most up to date information the CVI project file and all home made files from the project The important part of the code for the implementation of your own program is sitting in the CVI call back routines Page 27 of 38 SIS Documentation SIS3803 SIS GmbH 4 Scaler Counter VME 19 Appendix 19 1 Address Modifier Overview Find below the table of address modifiers which can be used with the SIS360x 38xx with the corresponding addressing mode enabled AM code Mode AMcode Mode 0 0 0 0x09 A32 non privileged data access Future option CBLT Page 28 of 38 SIS Documentation SIS3803 SIS GmbH I Scaler Counter VME 19 2 Front Panel Layout The front panel of the SIS3803 is equipped with 8 LEDs 8 control in and outputs and 16 counter inputs On flat cable units ECL and TTL the control connector is a 20 pin header flat cable connector and the channel inputs are fed via a 34 pin headers On LEMO NIM and TTL units the control in and
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