ATD_10B8C Block User Guide V02.12
Contents
1. During a conversion if additional active edges are detected the overrun error flag ETORF is set In either level or edge triggered modes the first conversion begins when the trigger is received In both cases the maximum latency time is one Bus Clock cycle plus any skew or delay introduced by the trigger circuitry NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled 32 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Once ETRIGE is enabled conversions cannot be started by a write to ATDCTLS but rather must be triggered externally If the level mode is active and the external trigger both de asserts and re asserts itself during a conversion sequence this does not constitute an overrun therefore the flag is not set If the trigger is left asserted in level mode while a sequence is completing another sequence will be triggered immediately 4 3 2 General Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data As analog inputs they are multiplexed and sampled to supply signals to the A D converter As digital inputs they supply external input data that can be accessed through the digital port register PORTAD input only The analog digital multiplex operation is performed in the input pads The input pad is always connected to the analog i2. 2 2 Detailed Signal Descriptions 2 2 1 AN7 ETRIG PAD7 This pin serves as the analog input Channel 7 It can be configured to provide an external trigger for the ATD conversion It can be configured as digital port pin 2 2 2 ANG PAD6 This pin serves as the analog input Channel 6 It can be configured as digital port pin 2 2 3 AN5 PAD5 This pin serves as the analog input Channel 5 It can be configured as digital port pin 2 2 4 AN4 PAD4 This pin serves as the analog input Channel 4 It can be configured as digital port pin 2 2 5 AN3 PAD3 This pin serves as the analog input Channel 3 It can be configured as digital port pin 2 2 6 AN2 PAD2 This pin serves as the analog input Channel 2 It can be configured as digital port pin 2 2 7 AN1 PAD1 This pin serves as the analog input Channel 1 It can be configured as digital port pin 2 2 8 ANO PADO This pin serves as the analog input Channel 0 It can be configured as digital port pin AR MOTOROLA Information www freescale com 11 ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 2 2 9 VRH VRL VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion 2 2 10 VDDA VSSA These pins are the power supplies for the analog circuitry of the ATD 10B8C block 12 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Sec
3. serasa eras SEG te 25 ATD Status Register 1 ATDSTAT1 EE eee eee eee 26 ATD Input Enable Register ATDDIEN se SE se de es cee eee 26 Port Data Register PORTAD ii EE EE RE ee se ed ek ee ee 27 Left Justified ATD Conversion Result Register High Byte ATDDRxH 28 Left Justified ATD Conversion Result Register Low Byte ATDDRxL 28 Right Justified ATD Conversion Result Register High Byte ATDDRxH 28 Right Justified ATD Conversion Result Register Low Byte ATDDRxL 29 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 6 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc List of Tables Table 0 1 Revision History or Re a aod er EE RS a RV CT 2 Table 3 1 Module Memory Map sc sap OER eds gt see 5586 pis A 13 Table 3 2 External Trigger Configurations snaa aasa 0 eee ee 16 Table 3 3 Conversion Sequence Length Coding EE EE EE eee eee eee ee 17 Table 3 4 ATD Behavior in Freeze Mode breakpoint EE EE EE ER eee eee 18 Table 3 5 Sample Time Select n n MEE PAN ER E NN Pe RE NE a 19 Table 3 6 Clock Prescaler Values usas ess EER EE EE ia hee eee a a a aa a a RR 20 Table 3 7 Available Result Data Formats EER EE EE Es ee eee 21 Table 3 8 Left Justified Signed and Unsigned ATD Output Codes 22 Table 3 9 Analog I
4. Base Address Address Offset where the Base Address is defined at the MCU level and the Address Offset is defined at the module level AR MOTOROLA Information www freescale com 13 ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 3 3 Register Descriptions This section describes in address order all the ATD_10B8C registers and their individual bits 3 3 1 Reserved Register ATDCTLO 00 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 EE Unimplemented or Reserved Figure 3 1 Reserved Register ATDCTLO Read always read 00 in normal modes Write unimplemented in normal modes 3 3 2 Reserved Register ATDCTL1 01 7 6 5 4 3 2 1 0 53 HARE E E NE NN PA MM HER NEG Mia 0 0 0 0 0 0 0 0 fe Unimplemented or Reserved Figure 3 2 Reserved Register ATDCTL1 Read always read 00 in normal modes Write unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality 3 3 3 ATD Control Register 2 ATDCTL2 This register controls power down interrupt and external trigger Writes to this register will abort current conversion sequence but will not start a new sequence 14 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 02 7 6 5 4 3 2 1 0 i ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE EE RESET 0 0 0 0 0 0 0 0 ET
5. a DE So E AE RE RE 14 3 3 1 Reserved Register ATDCTLO ii EE Es Ee ee se eee 14 3 3 2 Reserved Register ATDCTL1 22 4244 EER at REEDE BREER EE OE et ASE EES 14 3 3 3 ATD Control Register 2 ATDGTL2 su vas es ES EE PAG EE ER a sa a EE ee 14 3 3 4 ATD Control Register 3 ATDCTL3 ss ss si EERS HEESE WAS AA 16 3 3 5 ATD Control Register 4 ATDCTLA4 ss EE EE Re ee ee 18 3 3 6 ATD Control Register 5 AT DC PUG a ase ane DE EE ed a 20 3 3 7 ATD Status Register O ATDSTATO is EE SE Ee ee ee se ee de 23 AR MOTOROLA 3 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 3 3 8 Reserved Register ATDTEST0 Se es ee eee 24 3 3 9 ATD Test Register TIA DO TEST IE ETE PERE ME SE NEED Ee DE Ee RE RER 24 3 3 10 ATD Status Register 1 ATDSTAT1 a 25 3 3 11 ATD Input Enable Register ATDDIEN oooocccccooocccc ee eee 26 3 3 12 Port Data Register PORTAD usas ss as Na Ka ARAW ER OES RE BEE a ed eee 27 3 3 13 ATD Conversion Result Registers ATDDRHx ATDDRLx ie EE Es ed ee 27 Section 4 Functional Description BAM Generalean EDE RE RE Ni a 31 42 Analog SUB DIOCK tit a fed ER eke a EE DE aed a EE ER 31 4 2 1 Sample and Hold Machine risos ad Era EE SAPAT EE REEN Ee EE Te en 31 4 2 2 Analog Input Multiplexer EE SES ess KERE BERE BAKAL O NA EE EE Ep DE 31 4 2 3 Sample Buffer Amplifier se EER AR SEER ER De ES WEG bag Mah EED Ee od 31 4 2 4 Analog to D
6. high accuracy Table 3 5 lists the lengths available for the second sample phase 18 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table 3 5 Sample Time Select Length of 2nd phase of sample time 2 A D conversion clock periods 4 A D conversion clock periods 8 A D conversion clock periods 16 A D conversion clock periods PRS4 PRS3 PRS2 PRS1 PRSO ATD Clock Prescaler These 5 bits are the binary value prescaler value PRS The ATD conversion clock frequency is calculated as follows BusClock ATDclock I x 0 5 PRS 1 i Note that the maximum ATD conversion clock frequency is half the Bus Clock The default after reset prescaler value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12 Table 3 6 illustrates the divide by operation and the appropriate range of the Bus Clock 19 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Freescale Semiconductor Inc Table 3 6 Clock Prescaler Values Total Divisor Prescale Value Value Max Bus Clock Min divide by 2 divide by 4 divide by 6 divide by 8 divide by 10 divide by 12 divi
7. sampled in the sequence are determined by incrementing the channel selection code 1 Sample across several channels 0 Sample only one channel CC CB CA Analog Input Channel Select Code These bits select the analog input channel s whose signals are sampled and converted to digital codes Table 3 9 lists the coding used to select the various analog input channels In the case of single channel scans MULT 0 this selection code specified the channel examined In the case of multi channel scans MULT 1 this selection code represents the first channel to be examined in the conversion sequence Subsequent channels are determined by incrementing channel selection code selection codes that reach the maximum value wrap around to the minimum value Table 3 9 Analog Input Channel Select Coding Analog Input CA Channel 0 0 0 A J ee A EN 0 0 NO 1 AN1 1 0 AN2 22 AR MOTOROLA Information www freescale com ATD_10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table 3 9 Analog Input Channel Select Coding Analog Input CC CB CA Channel 3 3 7 ATD Status Register 0 ATDSTATO This read only register contains the Sequence Complete Flag overrun flags for external trigger and FIFO mode and the conversion counter 06 MEAT Goal er EE E WEN FEER EER EE A A BEET EE Unimplemented or Reserved Figure 3 7 ATD Status Register O ATDSTATO Read anytime Write anyti
8. 0 0 EDS Unimplemented or Reserved Figure 3 4 ATD Control Register 3 ATDCTL3 Read anytime Write anytime 16 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc S8C S4C S2C SIC Conversion Sequence Length These bits control the number of conversions per sequence Table 3 3 shows all combinations At reset S4C is set to 1 sequence length is 4 This is to maintain software continuity to HC12 family Table 3 3 Conversion Sequence Length Coding Number of Conversions S2C S1C per Sequence O O O O O j OLD O O oO O O CO NI HI Al O N E x x x Es Em FIFO Result Register FIFO Mode If this bit is zero non FIFO mode the A D conversion results map into the result registers based on the conversion sequence the result of the first conversion appears in the first result register the second result in the second result register and so on If this bit is one FIFO mode the conversion counter is not reset at the beginning or ending of a conversion sequence sequential conversion results are placed in consecutive result registers In a continuously scanning conversion sequence the result register counter will wrap around when it reaches the end of the result register file The conversion counter value CC2 0 in ATDSTATO can be used to determine where in the result register file the
9. CFx Conversion Complete Flag x x 7 6 5 4 3 2 1 0 A conversion complete flag is set at the end of each conversion in a conversion sequence The flags are associated with the conversion position in a sequence and also the result register number Therefore CCFO is set when the first conversion in a sequence is complete and the result is available in result register ATDDRO CCF 1 is set when the second conversion in a sequence is complete and the result is available in ATDDRI and so forth A flag CCFx x 7 6 5 4 3 2 1 0 is cleared when one of the following occurs A Write to ATDCTLS a new conversion sequence is started B If AFFC 0 and read of ATDSTATI followed by read of result register ATDDRx C If AFFC 1 and read of result register ATDDRx 1 Conversion number x has completed result ready in ATDDRx O Conversion number x not completed 3 3 11 ATD Input Enable Register ATDDIEN OD 7 6 5 4 3 2 1 0 i IEN7 IEN6 IENS IEN4 IENS IEN2 IEN1 IENO RESET 0 0 0 0 0 0 0 0 SSS Unimplemented or Reserved Figure 3 11 ATD Input Enable Register ATDDIEN Read anytime Write anytime IENx ATD Digital Input Enable on channel x x 7 6 5 4 3 2 1 0 This bit controls the digital input buffer from the analog input pin ANx to PTADx data register 1 Enable digital input buffer to PTADx 26 Information www freescale com AR MOTOROLA ATD 10B8C Block User Guide V02 12 Freescale Semicond
10. DOCUMENT NUMBER a S12ATD10B8CV2 D Freescale Semiconductor Inc ATD 10B8C Block User Guide V02 12 Original Release Date 27 OCT 2000 Revised 28 June 2005 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12
11. Freescale Semiconductor Inc Revision History Version Revision Effective anti Number Date Date Author Description of Changes 00 00 27 10 2000 5 Initial SRS2 release 01 00 06 06 2001 Updated the description of ATDDIEN and PORTAD1 register Made SRS2 Compliant 01 10 16 06 2001 V02 00 20 June 2001 20 June 2001 Reworked whole document to make it more user friendly Added document names MOED EE i al Variable definitions and names have been hidden 5 Sept 2001 5 Sept 2001 Corrected sampling phase description other minor corrections 8 Nov 2001 8 Nov 2001 Corrected AWAI bit description 16 Jan 2002 8 Mar 2002 16 Jan 2002 8 Mar 2002 Syntax corrections Removed document number from all pages except cover sheet 11 Apr 2002 11 Apr 2002 Documented special channel conversion in ATDTEST 1 register 22 Apr 2002 16 Aug 2002 22 Apr 2002 16 Aug 2002 Corrected Table Available Result Data Formats 23 Aug 2002 21 Feb 2003 23 Aug 2002 21 Feb 2003 Formal corrections on ATDTESTO 1 and ATDDRHx ATDDRLx register descriptions 24 Mar 2005 24 Mar 2005 Corrected PAD7 0 port description 28 June 2005 28 June 2005 FIFOR flag corrected clearing mechanism B Detailed AWAI Bit description Functional Description Detailed and corrected Low power modes Table Available Result Data Formats Re corrected Enhanced FIFO bit description Tab
12. This register contains the SC bit used to enable special channel conversions 24 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 09 7 6 5 4 3 2 1 0 R U U 0 0 0 0 0 N E es RESET 0 0 0 0 0 0 0 0 EET Unimplemented or Reserved Figure 3 9 ATD Test Register 1 ATDTEST1 Read anytime returns unpredictable values for Bit7 and Bit6 Write anytime SC Special Channel Conversion Bit If this bit is set then special channel conversion can be selected using CC CB and CA of ATDCTLS Table 3 10 lists the coding 1 Special channel conversions enabled O Special channel conversions disabled NOTE Always write remaining bits of ATDTESTI Bit7 to Bit1 zero when writing SC bit Not doing so might result in unpredictable ATD behavior Table 3 10 Special Channel Select Coding Analog Input SC CC CB CA Channel Reserved VRH VRL VRH VRL 2 Reserved 3 3 10 ATD Status Register 1 ATDSTAT1 This read only register contains the Conversion Complete Flags MY MOTOROLA 25 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc OB 7 6 5 4 3 2 1 0 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCFO W RESET 0 0 0 0 0 0 0 0 7 Unimplemented or Reserved Figure 3 10 ATD Status Register 1 ATDSTAT1 Read anytime Write anytime no effect C
13. Unimplemented or Reserved Figure 3 3 ATD Control Register 2 ATDCTL2 Read anytime Write anytime ADPU ATD Power Up This bit provides on off control over the ATD 10B8C block allowing reduced MCU power consumption Because analog electronic is turned off when powered down the ATD reguires a recovery time period after ADPU bit is enabled 1 Normal ATD functionality 0 Power down ATD AFFC ATD Fast Flag Clear All 1 Changes all ATD conversion complete flags to a fast clear sequence Any access to a result register will cause the associate CCF flag to clear automatically 0 ATD flag clearing operates normally read the status register ATDSTATI before reading the result register to clear the associate CCF flag AWAI ATD Power Down in Wait Mode When entering Wait Mode this bit provides on off control over the ATD 10B8C block allowing reduced MCU power Because analog electronic is turned off when powered down the ATD requires a recovery time period after exit from Wait mode 1 Halt conversion and power down ATD during Wait mode After exiting Wait mode with an interrupt conversion will resume But due to the recovery time the result of this conversion should be ignored 0 ATD continues to run in Wait mode ETRIGLE External Trigger Level Edge Control This bit controls the sensitivity of the external trigger signal See Table 3 2 for details ETRIGP External Trigger Polarity This bit controls the polarity of t
14. current conversion result will be placed Aborting a conversion or starting a new conversion by write to an ATDCTL register ATDCTLS 0 clears the conversion counter even if FIFO 1 So the first result of a new conversion sequence started by writing to ATDCTLS will always be place in the first result register ATDDDRO Intended usage of FIFO mode is continuos conversion SCAN 1 or triggered conversion ETRIG 1 Which result registers hold valid data can be tracked using the conversion complete flags Fast flag clear mode may or may not be useful in a particular application to track valid data 1 Conversion results are placed in consecutive result registers wrap around at end O Conversion results are placed in the corresponding result register up to the selected sequence length FRZ1 FRZO Background Debug Freeze Enable When debugging an application it is useful in many cases to have the ATD pause when a breakpoint Freeze Mode is encountered These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 3 4 Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period 17 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table 3 4 ATD Behavior in Freeze Mode breakpoint Behavior in Freeze mode Continue conversion Reser
15. de by 14 divide by 16 divide by 18 divide by 20 divide by 22 divide by 24 divide by 26 divide by 28 divide by 30 divide by 32 divide by 34 divide by 36 divide by 38 divide by 40 divide by 42 divide by 44 divide by 46 divide by 48 divide by 50 divide by 52 divide by 54 divide by 56 divide by 58 divide by 60 divide by 62 divide by 64 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz Bus Clock 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz NOTE 1 Maximum ATD conversion clock frequency is 2MHz The maximum allowed Bus Clock frequency is shown in this column 2 Minimum ATD conversion clock frequency is 500KHz The minimum allowed Bus Clock frequency is shown in this column 3 3 6 ATD Control Register 5 ATDCTL5 This register selects the type of conversion sequence and the analog input channels sampled Writes to this register will abort current conversion sequence and start a new conversion sequence 20 Information www freescale com AR MOTOROLA ATD 10B8C Block User Guide V02 12 Freescale Semiconducto
16. e power down ADPU bit must be set to disable both the digital clocks and the analog power consumption Only analog input signals within the potential range of Vg to Vpyy A D reference potentials will result in a non railed digital output codes 4 3 Digital Sub block This subsection explains some of the digital features in more detail See register descriptions for all details 4 3 1 External Trigger Input ETRIG The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the A TD module when ATD conversions are to take place The input signal ATD channel 7 is programmable to be edge or level sensitive with polarity control Table 4 1 gives a brief description of the different combinations of control bits and their affect on the external trigger function Table 4 1 External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description Ignores external trigger Performs one X X 0 0 y conversion sequence and stops x X 0 1 Ignores external trigger Performs continuous conversion sequences 0 0 1 X Falling edge triggered Performs one conversion sequence per trigger 0 4 1 X Rising edge triggered Performs one conversion sequence per trigger Trigger active low Performs 1 0 1 X continuous conversions while trigger is active Trigger active high Performs 1 1 1 X continuous conversions while trigger is active
17. ent format and only exists in left justified format Signed data selected for right justified format is ignored Read anytime Write anytime no effect in normal modes AR MOTOROLA 27 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 3 3 13 1 Left Justified Result Data 10 ATDDROH 12 ATDDR1H 14 ATDDR2H 16 ATDDR3H 18 ATDDR4H 5 1A ATDDR5H 5 1C ATDDR6H 1E ATDDR7H 7 6 5 4 3 2 1 0 R BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 10 bit data W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT O 8 bit data RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 13 Left Justified ATD Conversion Result Register High Byte ATDDRxH 11 ATDDROL 5 13 ATDDRIL 15 ATDDR2L 17 ATDDR3L 19 ATDDRAL 5 1B ATDDRSL 5 1D ATDDR6L 1F ATDDR7L 7 6 5 4 3 2 1 0 R BIT 1 BIT 0 0 0 0 0 0 0 10 bit data W U U 0 0 0 0 0 0 8 bit data RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 14 Left Justified ATD Conversion Result Register Low Byte ATDDRxL 3 3 13 2 Right Justified Result Data 10 ATDDROH 12 ATDDR1H 14 ATDDR2H 16 ATDDR3H 18 ATDDR4H 1A ATDDRSH 1C ATDDR6H 1E ATDDR7H 7 6 5 4 3 2 1 0 R BIT 9 MSB BIT 8 10 bit data m o lololol o o f o om RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 15 Right Justified ATD Conversion Result Register High By
18. he external trigger signal See Table 3 2 for details AR MOTOROLA 15 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table 3 2 External Trigger Configurations ETRIGLE ETAPA Trigger 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level ETRIGE External Trigger Mode Enable This bit enables the external trigger on ATD channel 7 The external trigger allows to synchronize sample and ATD conversions processes with external events 1 Enable external trigger O Disable external trigger NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled ASCIE ATD Sequence Complete Interrupt Enable 1 ATD Interrupt will be requested whenever ASCIF 1 is set 0 ATD Sequence Complete interrupt requests are disabled ASCIF ATD Sequence Complete Interrupt Flag If ASCIE 1 the ASCIF flag equals the SCF flag see 3 3 7 else ASCIF reads zero Writes have no effect 1 ATD sequence complete interrupt pending 0 No ATD interrupt occurred 3 3 4 ATD Control Register 3 ATDCTL3 This register controls the conversion sequence length FIFO for results registers and behavior in Freeze Mode Writes to this register will abort current conversion sequence but will not start a new sequence _03 7 6 5 4 3 2 1 0 Na S8C S4C S2C S1C FIFO FRZ1 FRZO RESET 0 0 1 0 0 0
19. igital A D Machines as se OE AA 31 4 3 Digital Sub block ss LEES DEE EE REDE ER pet deine AD ER a E E HABANG 32 4 3 1 External Trigger Input ETRIG sore BEE coer BE We GO ke kk EN SEE DE BE RO es 32 4 3 2 General Purpose Digital Input Port Operation asnan EE EE Ek eee eee 33 4 3 3 LOW Power MODES iau OE RE EE EE RED ER AG hoola DE DA ER 33 Section 5 Resets 5 1 General vs EER ER EE DE RE De EE AD SS Baan Ee eo AE EE a 35 Section 6 Interrupts 6 1 General ss EER EERDER ED UR ODE e led lala ad do dede Le MEd ML 37 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc List of Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 AR MOTOROLA ALD 10B8C Block Diagram os EE DA oar eee eye a ER ee Er en 10 Reserved Register ATDCTLO 670 seres es ES KO re ke 14 Reserved Register ATDCTL1 Es EE de ss ee ee 14 ATD Control Register 2 ATDCTL2 nad ha DE EE ES pees EE DE Ee Si ie en 15 ATD Control Register 3 ATDCTL3 EE EE ee eee 16 ATD Control Register 4 ATDCTL4 EE cee ee 18 ATD Control Register 5 ATDCTL5 anaana EE EE enken enken en 21 ATD Status Register O ATDSTATO EE EE cece eee 23 Reserved Register ATDTESTO is es Sa EE EE EER A De ee ee eons 24 ATD Test Register 1 ATDTEST1
20. igned bits 0 7 10 bit left justified unsigned bits 6 15 10 bit left justified signed bits 6 15 10 bit right justified unsigned bits 0 9 20000 X0X 0 AR MOTOROLA 21 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table 3 8 Left Justified Signed and Unsigned ATD Output Codes Input Signal Signed Unsigned Signed Unsigned Vrl 0 Volts 8 Bit 8 Bit 10 Bit 10 Bit Vrh 5 12 Volts Codes Codes Codes Codes 5 120 Volts 7F FF 7FCO FFCO 5 100 7F FF 7F00 FFOO 5 080 7E FE 7E00 FEOO 2 580 01 81 0100 8100 2 560 00 80 0000 8000 2 540 FF TF FFOO 7F00 0 020 81 01 8100 0100 0 000 80 00 8000 0000 SCAN Continuous Conversion Sequence Mode This bit selects whether conversion sequences are performed continuously or only once 1 Continuous conversion sequences scan mode 0 Single conversion sequence MULT Multi Channel Sample Mode When MULT is 0 the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence The analog channel is selected by channel selection code control bits CC CB CA located in ATDCTLS When MULT is 1 the ATD sequence controller samples across channels The number of channels sampled is determined by the sequence length value S8C S4C S2C S1C The first analog channel examined is determined by channel selection code CC CB CA control bits subsequent channels
21. le 0 1 Revision History AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Table of Contents Section 1 Introduction hal ROWER OWN oor a EN BEE O ana ED Rd ala AG 9 AE RE EE OO ERA ses TE N EE re NGA 9 t3 Mod s of Operation 2 ADA ES a e GR a SS RD GE e An E 9 1 3 1 Conversion modes LEES ut peste Dagta ad id 9 1 3 2 MCU Operating Modes Eise sata pad Da bd LA ek Eb a MEE DEE 9 la Block Diagrami ER EE SEE EE EE BP RE is Mabe PAA AO Re eS ee ee 10 Section 2 Signal Description 21 COVE rs OD GREG BE SE BEE BEERS NE ee eee EE do DR 11 2 2 Detailed Signal Descriptions mila 11 2 2 1 ANZAETRIG APAD faces as ors see ee DE ES E ie GE DA ES a Ge se 11 2 2 2 ANG BADO o suas Cee eth Gu SERE SEE EDMS nG DAE dl ae he 11 2 2 3 ANS PRADO rea to eens AE he DE ESA ee a ESE RA EE 11 2 2 4 ANA PADDA EE br see ES ED DE De EE DE EE EE ae DERE ioe 11 2 2 5 PANS PADI 62 0 2 09222 ET EE N RE OD ET EE OR OE ERG 11 2 2 6 AN2 PAD2 SE AS NS GEGEE KG Ee PAA EE GO SE E AA ALA 11 2 2 7 ANTA PADI EE EA DAE HARE EE OT RE ORE 11 2 2 8 AND RADO DES WEMEL EE EES OL rd EE ESRA ME DS DR ee es 11 2 2 9 VE Alp a A AA E EDE AR EG SE 12 22 10 VDDA VS 255 mee a PA BA MEE AE BA NA DE Be EE O Pe Ee aa 12 Section 3 Memory Map and Register Definition B R OVENI os tetera ged fos EE RE o o EE OE SE AAP 13 3 2 Module Memory Map si Es Es Re ee tees 13 3 3 Register Descriptions EED a
22. me No effect on CC2 CCI CCO SCF Sequence Complete Flag This flag is set upon completion of a conversion sequence If conversion sequences are continuously performed SCAN 1 the flag is set after each one is completed This flag is cleared when one of the following occurs A Write 1 to SCF B Write to ATDCTLS a new conversion sequence is started C If AFFC 1 and read of a result register 1 Conversion sequence has completed O Conversion sequence not completed ETORF External Trigger Overrun Flag While in edge trigger mode ETRIGLE 0 if additional active edges are detected while a conversion sequence is in process the overrun flag is set This flag is cleared when one of the following occurs A Write 1 to ETORF B Write to ATDCTL2 ATDCTL3 or ATDCTIA a conversion sequence is aborted C Write to ATDCTLS a new conversion sequence is started 1 External trigger over run error has occurred AR MOTOROLA 23 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 0 No External trigger over run error has occurred FIFOR FIFO Over Run Flag This bit indicates that a result register has been written to before its associated conversion complete flag CCF has been cleared This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels However it is also practical for n
23. nput Channel Select Coding EE EE EE SEE Es se ee ee 22 Table 3 10 Special Channel Select Coding EE EE ennen eee 25 Table 4 1 External Trigger Control BIS pass DEER ME SEER GED DE OR E RES 32 Table 6 1 ATD 10B8C Interrupt VectorS nassaan aaaea 37 AR MOTOROLA 7 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 8 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Section 1 Introduction 1 1 Overview The ATD 10B8C is an 8 channel 10 bit multiplexed input successive approximation analog to digital converter Refer to device electrical specifications for ATD accuracy The block is designed to be upwards compatible with the 68HC11 standard 8 bit A D converter In addition there are new operating modes that are unique to the HC12 design 1 2 Features e 8 10 Bit Resolution e 7 usec 10 Bit Single Conversion Time e Sample Buffer Amplifier e Programmable Sample Time e Left Right Justified Signed Unsigned Result Data External Trigger Control e Conversion Completion Interrupt Generation e Analog Input Multiplexer for 8 Analog Input Channels e Analog Digital Input Pin Multiplexing e 1 to 8 Conversion Sequence Lengths e Continuous Conversion Mode e Multiple Channel Scans 1 3 Modes of Operation 1 3 1 Conversion modes There is software programmable selection between perf
24. nputs of the ATD 10B8C The input pad signal is buffered to the digital port registers This buffer can be turned on or off with the ATDDIEN register This is important so that the buffer does not draw excess current when analog potentials are presented at its input 4 3 3 Low Power Modes The ATD 10B8C can be configured for lower MCU power consumption in 3 different ways e Stop Mode This halts A D conversion Exit from Stop mode will resume A D conversion But due to the recovery time the result of this conversion should be ignored e Wait Mode with AWAI 1 This halts A D conversion Exit from Wait mode will resume A D conversion but due to the recovery time the result of this conversion should be ignored e Writing ADPU 0 Note that all ATD registers remain accessible This aborts any A D conversion in progress Note that the reset value for the ADPU bit is zero Therefore when this module is reset it is reset into the power down state AR MOTOROLA 33 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 34 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Section 5 Resets 5 1 General At reset the ATD 10B8C is in a power down state The reset state of each individual bit is listed within the Register Description section see Section 3 Memory Map and Register Definition which details the registers and thei
25. ode The second stage connects the input directly to the storage node to complete the sample for high accuracy When not sampling the sample and hold machine disables its own clocks The analog electronics still draw their quiescent current The power down ADPU bit must be set to disable both the digital clocks and the analog power consumption The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA 4 2 2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine 4 2 3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential 4 2 4 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The resolution is program selectable at either 8 or 10 bits The A D machine uses a successive approximation architecture It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials By following a binary search algorithm the A D machine locates the approximating potential that is nearest to the sampled potential AR MOTOROLA 31 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc When not converting the A D machine disables its own clocks The analog electronics still draws quiescent current Th
26. on FIFO modes and indicates that a result register has been over written before it has been read i e the old data has been lost This flag is cleared when one of the following occurs A Write 1 to FIFOR B Start a new conversion sequence write to ATDCTLS or external trigger An over run condition exists O No over run has occurred CC2 CC1 CCO Conversion Counter These 3 read only bits are the binary value of the conversion counter The conversion counter points to the result register that will receive the result of the current conversion E g CC2 1 CC1 1 CCO 0 indicates that the result of the current conversion will be in ATD Result Register 6 If in non FIFO mode FIFO 0 the conversion counter is initialized to zero at the begin and end of the conversion sequence If in FIFO mode FIFO 1 the register counter is not initialized The conversion counters wraps around when its maximum value is reached Aborting a conversion or starting a new conversion by write to an ATDCTL register ATDCTL5 0 clears the conversion counter even if FIFO 1 3 3 8 Reserved Register ATDTESTO 08 7 6 5 4 3 2 1 0 A R hd 1 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 8 Reserved Register ATDTESTO Read anytime returns unpredictable values Write anytime in special modes unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality 3 3 9 ATD Test Register 1 ATDTEST1
27. orming single or continuous conversion on a single channel or multiple channels 1 3 2 MCU Operating Modes Stop Mode Entering Stop Mode causes all clocks to halt and thus the system is placed in a minimum power standby mode This aborts any conversion sequence in progress During recovery from Stop Mode there must be a minimum delay for the Stop Recovery Time tgp before initiating a new ATD conversion sequence AR MOTOROLA 9 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc e Wait Mode Entering Wait Mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWATT bit e Freeze Mode In Freeze Mode the ATD_10B8C will behave according to the logical values of the FRZ1 and FRZO bits This is useful for debugging and emulation 1 4 Block Diagram ATD 10B8C Bus Clock Clock ATD clock Prescaler Conversion a Complete Interr Mode and Timing Control Comparator AN1 PAD1 X ANO PADO X VRHK AD VRL X ESA E and DAC AN7 PAD7 ANG PAD6 X AN5 PAD5 mi AN4 PAD4 X ma AN3 PAD3 BSL Bae eG Analog ATD Input Enable Register MUX bs Port AD Data Register Figure 1 1 ATD 10B8C Block Diagram 10 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Section 2 Signal Description 2 1 Overview The ATD 10B8C has a total of 12 external pins
28. r Inc 05 7 6 5 4 3 2 1 0 i DJM DSGN SCAN MULT CC CB CA RESET 0 0 0 0 0 0 0 0 ET Unimplemented or Reserved Figure 3 6 ATD Control Register 5 ATDCTL5 Read anytime Write anytime DJM Result Register Data Justification This bit controls justification of conversion data in the result registers See 3 3 13 ATD Conversion Result Registers ATDDRHx ATDDRLx for details 1 Right justified data in the result registers O Left justified data in the result registers DSGN Result Register Data Signed or Unsigned Representation This bit selects between signed and unsigned conversion data representation in the result registers Signed data is represented as 2 s complement Signed data is not available in right justification See 3 3 13 ATD Conversion Result Registers ATDDRHx ATDDRLx for details 1 Signed data representation in the result registers O Unsigned data representation in the result registers Table 3 7 summarizes the result data formats available and how they are set up using the control bits Table 3 8 illustrates the difference between the signed and unsigned left justified output codes for an input signal range between O and 5 12 Volts Table 3 7 Available Result Data Formats Result Data Formats Description and Bus Bit Mapping SRES8 DJM DSGN 8 bit left justified unsigned bits 8 15 8 bit left justified signed bits 8 15 8 bit right justified uns
29. r bit field 35 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 36 AR MOTOROLA Information www freescale com 6 1 General ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Section 6 Interrupts The interrupt requested by the ATD 10B8C is listed in Table 6 1 Refer to MCU specification for related vector address and priority Table 6 1 ATD 10B8C Interrupt Vectors CCR Interrupt Source Mask Local Enable Seguence Complete I bit ASCIE in ATDCTL2 Interrupt See register descriptions for further details AR MOTOROLA Information www freescale com 37 ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 38 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc User Guide End Sheet AR MOTOROLA 39 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc FINAL PAGE OF 40 PAGES 40 AR MOTOROLA Information www freescale com
30. te ATDDRxH 28 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 11 ATDDROL 5 13 ATDDRIL 15 ATDDR2L 17 ATDDR3L 19 ATDDRAL 5 1B ATDDRSL 5 1D ATDDR6L 1F ATDDR7L 7 6 5 4 3 2 1 0 R BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10 bit data W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT O 8 bit data RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 16 Right Justified ATD Conversion Result Register Low Byte ATDDRxL AR MOTOROLA 29 Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc 30 AR MOTOROLA Information www freescale com ATD 10B8C Block User Guide V02 12 Freescale Semiconductor Inc Section 4 Functional Description 4 1 General The ATD 10B8C is structured in an analog and a digital sub block 4 2 Analog Sub block The analog sub block contains all analog electronics required to perform a single conversion Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub block 4 2 1 Sample and Hold Machine The Sample and Hold S H Machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node The sample process uses a two stage approach During the first stage the sample amplifier is used to quickly charge the storage n
31. tion 3 Memory Map and Register Definition 3 1 Overview This section provides a detailed description of all registers accessible in the ATD 10B8C 3 2 Module Memory Map Table 3 1 gives an overview on all ATD 10B8C registers Table 3 1 Module Memory Map Gie Use Access 00 ATD Control Register 0 ATDCTLO R 01 ATD Control Register 1 ATDCTL1 R 02 ATD Control Register 2 ATDCTL2 R W 03 ATD Control Register 3 ATDCTL3 R W 04 ATD Control Register 4 ATDCTL4 R W _05 ATD Control Register 5 ATDCTL5 R W 06 ATD Status Register 0 ATDSTATO R W 07 Unimplemented 08 ATD Test Register 0 ATDTESTO R 09 ATD Test Register 1 ATDTEST1 R W OA Unimplemented OB ATD Status Register 1 ATDSTAT1 R 0C Unimplemented OD ATD Input Enable Register ATDDIEN R W OE Unimplemented OF Port Data Register PORTAD R 10 11 ATD Result Register 0 ATDDROH ATDDROL RW 12 13 ATD Result Register 1 ATDDR1H ATDDR1L R W E 16 5 17 ATD Result Register 3 ATDDR3H ATDDR3L RW 18 19 ATD Result Register 4 ATDDR4H ATDDR4L RAW _1A _1B ATD Result Register 5 ATDDR5H ATDDR5L RW 1C 1D ATD Result Register 6 ATDDR6H ATDDR6L RW 1E IF ATD Result Register 7 ATDDR7H ATDDR7L R W NOTES 1 ATDCTLO is intended for factory test purposes only 2 ATDCTL1 is intended for factory test purposes only 3 ATDTESTO is intended for factory test purposes only NOTE Register Address
32. uctor Inc O Disable digital input buffer to PTADx NOTE Setting this bit will enable the corresponding digital input buffer continuously If this bit is set while simultaneously using it as an analog port there is potentially increased power consumption because the digital input buffer maybe in the linear region 3 3 12 Port Data Register PORTAD The digital port pins are shared with the analog A D inputs AN7 0 OF 7 6 5 4 3 2 1 0 R BA Pin Func AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO tion EE Unimplemented or Reserved Figure 3 12 Port Data Register PORTAD Read anytime Write anytime no effect PTADx A D Channel x ANx Digital Input x 7 6 5 4 3 2 1 0 If the digital input buffer on the ANx pin is enabled IENx 1 read returns the logic level on ANx pin signal potentials not meeting VIL or VIH specifications will have an indeterminate value If the digital input buffers are disabled IENx 0 read returns a 1 Reset sets all PORTAD bits to 1 3 3 13 ATD Conversion Result Registers ATDDRHx ATDDRLx The A D conversion results are stored in 8 read only result registers ATDDRHx ATDDRLx The result data is formatted in the result registers based on two criteria First there is left and right justification this selection is made using the DJM control bit in ATDCTLS Second there is signed and unsigned data this selection is made using the DSGN control bit in ATDCTLS Signed data is stored in 2 s complem
33. ved Finish current conversion then freeze Freeze Immediately 3 3 5 ATD Control Register 4 ATDCTL4 This register selects the conversion clock frequency the length of the second phase of the sample time and the resolution of the A D conversion 1 e 8 bits or 10 bits Writes to this register will abort current conversion sequence but will not start a new sequence 04 7 6 5 4 3 2 1 0 w SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO RESET 0 0 0 0 0 1 0 1 is Unimplemented or Reserved Figure 3 5 ATD Control Register 4 ATDCTL4 Read anytime Write anytime SRESS A D Resolution Select This bit selects the resolution of A D conversion results as either 8 or 10 bits The A D converter has an accuracy of 10 bits however if low resolution is reguired the conversion can be speeded up by selecting 8 bit resolution 1 8 bit resolution O 10 bit resolution SMP1 SMPO Sample Time Select These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles Note that the ATD conversion clock period is itself a function of the prescaler value bits PRS4 0 The sample time consists of two phases The first phase is two ATD conversion clock cycles long and transfers the sample quickly via the buffer amplifier onto the A D machine s storage node The second phase attaches the external analog signal directly to the storage node for final charging and
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