Dot-Matrix LCD Units - Electrical and Information Technology
Contents
1. 1 1 T 2 E xoxt000 1 A z iig Pd cS LE xt 9 S3 iiv E iu o S do EE AP m ui un si unde Rx PRE LES S IT FE A E iR dL PUTA LS xxi m Im EL VETERI S ZEE s ug E O NOTES 1 The CG RAM generates character patterns in accordance with the user s program 2 Shaded areas indicate 5 x 10 dot character patterns Display Unit User s Manual 8 Dot Matrix LCD Units SHARP 4 Bit Interface Wait 15 ms or more after Vpp reaches 4 5 V RS R W DB DBg DBs Busy flag can t be checked before execution of this 00 00 1 1 instruction Function Set 8 Bit Interface Wait 4 1 ms or more RS R W DB DBg DBs Busy flag can t be checked before execution of this 4 instruction 0 0 0 0 1 Function Set 8 Bit Interface Wait 100 us or more RS R W DB DBs Busy flag can t be checked before execution of this instruction 9g 1 Function Set 8 Bit Interface a Busy flag can be checked after the following instructions are completed If the busy flag is not going to be checked then a wait time longer than the total execution time of these instructions is required See Table 7 RS R W DB DBg DBs DB Function Set 4 Bit Interface This instruction signals the LCD unit to begin accepting and T sending data in dual 4 bit transfers for all subsequent2. transfers for all subsequent transactions This is the only 4 bit instruction recognized by the LCD unit Single Dual Line the display format lll Display Il Function Set 4 Bit Interface Caution At this point Display Display Font can t be changed IV Display Clear V Entry Mode Set 0 0 0 0 0 0 0 0 0 O10 olo O O o End of Initialization LCD21 11 Figure 4 4 Bit Interface Display Unit User s Manual 14 Dot Matrix LCD Units SHARP Table 7 Instruction Set CODE INSTRUCTION FUNCTION bres n RS RW DB DBs DBs DBs DB DB fcp or fosc 250 khz Display Clear 0 0 0 0 0 0 0 0 0 1 Clear enter display area restore display from 1 64 ms shift and load address counter with DD RAM address 00 Display Cursor 0 0 0 0 0 0 0 0 1 Restore display from shift and load address 1 64 ms Home counter with DD RAM address 004 Entry Mode 0 0 0 0 0 0 0 1 VD S Specify cursor advance direction and display 40 us Set shift mode This operation takes place after each data transfer Display ON OFF 0 0 0 0 0 0 1 D C B Specify activation of display D cursor C 40 us and blinking of character at cursor position B Display Cursor 0 0 0 0 0 1 S C R L ii Shift display or move cursor 40 us Shift Function Set 0 0 0 0 1 DL N 0 5 Set interface data length DL and number
3. are as follows Timing Characteristics Dot Matrix LCD Units Table 8 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Output H Von 0205 24 V Voltage vo l s12m 04 V LCD27 24 Display Unit User s Manual Figure 5 Write Operation Timing Diagram For data sent from the external microprocessor to the LCD unit Table 9 Write Operation Timing Characteristics Vpp 5 0 5 Vss Ta 0 50 C VALUE PARAMETER SYMBOL UNIT MIN MAX Enable Cycle Time 1000 ns Enable Pulse Width High Level PWEH 450 ns Enable Rise Fall Time ter ter 25 ns Setup Time RS R W E tas 140 ns Address Hold Time 10 ns Data Setup Time tpsw 195 ns Data Hold Time tH 10 5 19 Dot Matrix LCD Units SHARP RW LCD27 25 Figure 6 Read Operation Timing Diagram For data sent from the LCD unit to the external microprocessor Table 10 Read Operation Timing Characteristics 5 0 5 Vss 0 V Ta 0 50 C Table 11 Power Conditions for Internal Reset VALUE PARAMETER SYMBOL UNIT MIN TYP MAX Voltage Build Up Time troc 0 1 10 ms Power Off Period torr 1 ms PARAMETER SYM
4. BOL sE UNIT MIN MAX Enable Cycle Time 1000 ns Enable Pulse Width High Level 450 ns Enable Rise Fall Time ter tEf 25 ns Setup Time RS R W E tas 140 ns Address Hold Time 10 E ns Data Delay Time 320 ns Data Hold Time 20 ns If the above conditionsare not satisfied the inter nal reset circuit will not operate normally In such a case the LCD unit must be initialized by executing a series of instr uctions see the Ex ecution by In structions section 0 1 ms tiec lt 10 ms NOTE torr indicates Power off Period torr 21ms LCD27 26 Display Unit User s Manual Figure 7 20 SHARP Dot Matrix LCD Units 2 4 Bit Data Transfer with a SingleLine 16 Char Since the data lines DB o DB3 are not con acter Display Using Internal Reset Table 14 nected this data is not accepted and must be shows asample operating procedure foran LCD written again i e the func tion s et instruction unit in this mode After power has been turned must be written twice Subsequent data trans on the 8 bit data transfer mode is in effect and fers are completed in two 4 bit transfer opera the first write operation is assumed tobe an 8 bit tions see Table 14 data transfer S INTERNAL OPERATION READY FOR DATA o XXX Re X susy N ANN 9 XX Write Instruction Check Busy Flag Check Busy Flag Write Instructio
5. Bilaga pot matrix LcD units HARDWARE Interface Signals SHARP Table 2 Interface Signals EXTERNAL SIGNALNAME INPUT OUTPUT CONNECTION FUNCTION RS Input MPU Register select signal 0 Instruction register when writing Busy flag and address counter when reading 1 Data register when writing and reading R W Input MPU Read write select signal 0 Writing 1 Reading E Input MPU Operation data read write enable signal DB4 DB7 Input Output MPU High order lines of data bus with three state bidirctional function for use in data transactions with the MPU DB may also be used to check the busy flag DBo DB3 Input Output MPU Low order lines of data bus with three state bidirectional function for use in data transactions with the MPU These lines are not used when interfacing with a 4 bit microprocessor Vpop Vss Power Supply Vpp 5 V Vss GND Vo Power Supply Contrast adjustment voltage Functional Blocks Registers The LCD unit has two 8 bit registers an instruc tion register IR and a datar egister The instruction register stores instruction codes such as clear display or shift cur sor and als o stor es address information for the display data RAM and character generator RAM The IR can be accessed by the microprocessor only for writing The data register is used for temporarily storing data during data transactions with the microproces sor When writing
6. Dot Matrix LCD Units EL EL T back amp Inverter 5V light See note 2 m Display LED signals Segment back LCD 9 Electrode Scanning Signals 1 light Drive Viep Viss Common Electrode Drive Circuit Timing Generator Character Generator Display Data ROM RAM CG ROM Address DD RAM 7 200 bits Counter 80 x 8 bits AC Character Generator ROM Decoder 8 Instruction Data Register Register R DR Flag BF 8 Buffer 4 4 RS RW DB DB DB NOTES 1 LM16152 incorporates a temperature compensation circuit within the bias voltage generator See table 12 2 For the inverters of EL backlights please contact your representative Parallel to Serial Converter Bias Voltage Generator See Note 1 Vpp Vo Vss LCD27 6 Figure 1 Functional Block Diagram Display Unit User s Manual Dot Matrix LCD Units SHARP Table 4 Character Codes HIGH ORDER 4 BIT LOW 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 ORDER 4 BIT CG oo xxxx0000 Ung e EI 1 2 T 0 OSEE jt Tz xoxot00 RE P bd dec O EP BA TE LEL 01 1 1 8 A 111
7. data to the LCD unit the data is initially stored in the data register and is then auto matically written into either the display data RAM or character gener ator RAM as deter mined by the current operation The data register is also used as a temporary storage area when reading data from the display data RAM or character generator RAM When address information is written into the instruc tion register thecorresponding data fom the display data RAM or character generator RAM is moved to the data register Data transfer is completed when the microprocessor reads the contents of the data register by the next instruction After the transfer is completed data from the next address position of the appropriate RAM is moved to the data register in preparation for subsequent reading operations by the microprocessor One ofthe twor egisters is selected by the register select RS signal Table 3 Register Selection RS RW OPERATION 0 0 Write to instruction register and execute internal operation clear display etc 0 1 Read busy flag DB7 and address counter DBo DBe 1 0 Write to data register and execute internal operation DR DD RAM or DR gt CG RAM 1 1 Read data register and execute internal operation DD RAM DR or CG gt DR Display Unit User s Manual SHARP Busy Flag BF When the busy flag is set at a logial 1 the LCD unit is executing an inter nal operation and no
8. in struction will be accepted The state ofthe busy flag is output ondata line DB in response to the register selection signals RS 0 R W 1 shown Table 3 The next ins truction may be enter ed after the busy flag is reset to logical O Address Counter AC The address counter generates the address for the di splay d ata R AM an d c haracter ge nerator RAM When the address set instruction is written into the instruction register the address information is sent tothe address counter The same instruciton also determines which of the two is to be selected After data has been wr itten to or read from the display data RAM or character generator RAM the address counter is autom atically incr emented or decremented by one The contents of the address counter ar e outputon data lines DB o DBein response to the register selection signals RS 0 R W 1 as shown in Table 3 Display Data RAM DD RAM This 80 x8 bitRAM stores up to 80 8 bit character codes as display data Theunused area of the RAM may be us ed by the m icroprocessor as a general purpose RAM area The display data RAMaddress set in the addess counter is expressed in hexadecimal HEX num bers as follows High order Lower order Bits its ac HEX HEX Digit Digit Example DD RAM address 4E jojo t ils fol 2 bd 4 Y E The address of the dis play data RAM orre sponds to the dis
9. n NOTE IR IR Instruction bits 7 and 3 Address counter bit LCD27 32 Figure 9 4 Bit Interface Timing Example LCD UNIT DB DB LCD27 33 Figure 10 Connection to SM200 Display Unit User s Manual 23
10. of 40 us display lines N CG RAM 0 0 0 1 Acc Load the address counter with aCG RAM 40 us Address Set address Subsequent data is CG RAM data DD RAM 0 0 1 App Load the address counter with a DD RAM 40 us Address Set address Subsequent data is DD RAM data Busy 0 1 BF AC Read busy flag BF and contents of address 0 us Flag Address counter AC Counter Read CG RAM DD 1 0 Write data Write data to CG RAM or DD RAM 40 us RAM Data Write CG RAM DD 1 1 Read data Read data from CG RAM or DD RAM 40 us RAM Data Read I D 1 Increment I D 0 Decrement DD RAM Display Data RAM 5 1 Display Shift On CG RAM Character Generator RAM S C 1 Shift Display S C 0 Move Cursor Acc Character Generator RAM Address RIL 1 Shift Right R L 0 Shift Left App Display Data RAM Address DL 1 8 Bit DL 0 4 Bit AC Address Counter N 1 Dual Line N 0 Single Line BF 1 Internal Operation BF 0 Ready for Instruction NOTES 1 Symbol signifies a don t care bit 2 Correct input value for is predetermined for each model see Table 12 Display Unit User s Manual 18 SHARP ELECTRICAL CHARACTERISTICS Absolue Maximum Ratings See the device specifications for each LCD unit model Electrical Characteristics See the device specificiations for each LCD unit model Some of the cur rently available specifica tions do not describe the test conditions for the high level and low level output v oltages These conditions
11. play position on the LCD panel as follows Display Unit User s Manual Dot Matrix LCD Units a Address type a For dual line display Display Position Digit 1 8 9 39 40 DD RAM Address HEX When a display shift takes place the addresses shift is as follows Left 014 024 034 044 05 4 06 07 08 09 274 00 Shift 44 142 143 1444 45 146 474 484 494 67440 Right 27 00 01 02 03 04 05 06 07 gt gt 254264 Shift 67 40 41 42 43 44 45 46 47 5 664 The addresses for the second line are not con tinuous tothe addresses forthe first line 40 acter RAM area is assigned to each of the two line as follows line 1 OOH 27H line 2 40H 67H For an LCD unit with a dis play capacity of less than 40 char acters per line haracters equal in number to the display capacity as counted from display position 1 are displayed b Address type b For single line display with logically dual line addressing x Display Position 23 4 5 6 7 8 9 10 11 12 13 14 15 16 ppp po pepe DD RAM Address HEX When a display shift takes place the addresses shift as follows Left n Papa pu pupupe pe NN psp E o NENNEN The right hand eight characters for the purposes of addressing and shifting m ay be cons idered to constitute a second display line For the address type of each model see Table 12 SHARP
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