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MC9S12DJ64 Device User Guide V01.20 Covers also MC9S12D64

Contents

1. 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 007C 2 Write Read Bit7 6 5 4 3 2 1 Bit 0 50070 TO2H l Write Read Bit15 14 13 12 11 10 9 Bit 8 007E TO3H h Read Bit7 6 5 4 3 2 1 Bit 0 007F Write 0080 009F ATDO Analog to Digital Converter 10 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0080 ATDOCTLO Read 0 0 0 0 0 0 Write 0081 ATDOCTLI Head 0 E 0 Write 0082 ATDOCTL2 ADPU ETRIGLE ETRIGP ETRIG LASOE Read 0 0083 rito S8C SAC S2C S1C FIFO FRZ FRZO 0084 ATDOCTL4 MA SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0085 ATDOCTLS We DJM DSGN SCAN MULT CC CB CA 0086 ATDOSTATO SCF D lt 460 CRD Read 0 0 0 0 0 0 0 0 0087 Reserved Write 0088 ATDOTESTO 1984 0 0 0 D Write 0089 1984 0 N Q 0 9 0 D SC Write Read 0 0 0 0 0 0 0 0 008A Reserved Write 80088 ArDosrart Read CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 Write Read 0 0 0 0 0 0 0 0 008C Reserved Write 008D ATDODIEN 19804 6 5 4 3 2 1 Bit 0 Write Read 0 0
2. 56 2 3 3 TEST Test Pin ao MO ON et 56 2 3 4 VREGEN Voltage Regulator Enable 56 2 3 5 XFC PLL Loop Filter Pin 3 a8 ah SO 56 2 3 6 BKGD TAGHI MODC Background Debug Tag High and Mode Pin 56 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 57 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins ATD1 57 2 3 9 PADO7 AN07 ETRIGO Port AD Input Pin of 57 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of 57 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port Pins 57 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port Pins 57 2 3 13 _ PE7 XCLKS Port E 7 57 2 3 14 PE6 MODB IPIPEXT Port E VO Pin 6 N OX et 22 2 59 2 3 15 PERAMODANWIPIPEQys 5 59 2 3 16 Port E I O Pin 44 AN oM a 59 2 3 17 LSIRB TAGLO Port E Pin 3 487 Lc Aa dd 59 2 3 18 PE2Z RW Port E I O Pin 25 at NM cemere NN uou 59 2 3 19 PE1 IRQ Rer E Input Pin ANS 59 2 3 20 PE0 XIRQ Port E Input Pin AN 59 M MOTOROL
3. 61 MOSIO Port M I O Pin 4 61 PM3 TXCANO SS0 Port M WO Pin3 62 PM2 RXCANO MISO0 Port M I O Pin2 62 1 TXB Port M I O Pin 1 62 PMO RXCANO RXB Port M I O Pin 0 62 KWP7 PWM7 Port P I O Pin 7 62 PP6 KWP6 PWM6 Port P IO Pin 6 62 PP5 KWP5 PWM5 Port P WO Pin5 62 PP4 KWP4 PWM4 Port P I O Pin4 62 PP3 KWP3 PWM3 Port P I O Pin 3 63 PP2 KWP2 PWM2 Port P I O Pin 2 63 KWP1 PWM1 Port P I O Pin 1 63 PPO KWPO PWM0 Port P Pin 0 63 50 Por SMO Pin Y aN ee 63 PS6 SOKO Port 5 Pin 6 Ne ce ae tee 63 PS5 Port SIOPin5 63 54 500 Port amp TO Pin 4 ak 63 PS3 ARXD1 a Port S ATI 63 PS2 RXD1 Port SIOPin2 64 PS1 TXD0 Port SIOPin1
4. cx Crystal or MCU ceramic resonator Cy VSSPLL Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value Figure 2 4 Colpitts Oscillator Connections 7 1 CI Crystal or ceramic resonator Rs can be zero shorted when used with higher frequency crystals Refer to manufacturer s data Figure 2 5 Pierce Oscillator Connections PE7z0 EXTAL EXTERNAL OSCILLATOR V Level MCU VppPLL XTAL not connected Figure 2 6 External Clock Connections PE7 0 M MOTOROLA 58 MC9S12DJ64 Device User Guide 01 20 2 3 14 IPIPE1 Port E I O Pin 6 is a general purpose input or output pin It is used as MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low 2 3 15 5 MODA IPIPEO Port E I O Pin 5 PES is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the
5. 70 4 3 3 Unsecuring the Microcontroller 71 44 Low Power Modes 5 a ibn eee 71 4 4 1 SOP k Dane N rear 71 4 4 2 Pseudo 4 Y K 71 4 4 3 Wal Qt a M xe RN Lue 71 4 4 4 R N a sa voca ON ee pae oc made s ee De 72 Section 5 Resets and Interrupts 5 1 Overview T NN eee ea NE ONT lt N 73 5 2 ON oe ae 13 5 2 1 VectamNfable q gt AN NE O K 73 5 3 Effects of Reset NS ge NN oS als ae 74 5 3 1 VO pins Nr a NN 74 5 3 2 Mem ty gl NN QG AN 75 Section 6 HCS12 Core Block Description te 7 4 886 3 5753170 Ji JJ EH 86 21 54151736 WE 45 86 755 83298787 M MOTOROLA Http www 100y com tw MC9S12DJ64 Device User Guide V01 20 6 1 6 1 1 6 2 6 2 1 6 3 6 3 1 6 4 6 5 6 5 1 6 6 CPU12 Block Description 77 Device specific information 77 HCS12 Module Mapping Control MMC Block Description 77 Device specific information 77 HCS12 Multiplexed External Bus Interface MEBI Block Description 77 Device specific information 77 HCS
6. 15 MC9S12DJ64 Block Diagram 23 MC9S12DJ64 Memory Map out of Reset 27 9512032 Memory Map out of Reset 29 Pin Assignments in 112 pin LQFP for MC9S12DJ64 52 Pin Assignments 80 pin for MC9S12DJ64 and 9512032 53 PLL Loop Filter Congestiongq 2 2 Nr 2 nae NM Seu 56 Colpitts Oscillator Connections 7 1 58 Pierce Oscillator Connections 7 0 58 External Clock Connections PE720 58 Clock GSonneetions gk e a a eee NT NN EN 67 Recommended PCB Layout 112LQFP Colpitts 82 Recommended PCB Layout for 80QFP Colpitts Oscillator 83 Recommended PCB Layout for 112LQFP Pierce Oscillator 84 Recommended PCB Layout for 80QFP Pierce Oscillator 85 AD Accuracy Definitions af 0 100 Basic PLL functional diagram 109 D finitions gt oN Leere 111 Maximum bus clock jitter approximation 111 SPI Master Timing 0 115 SPI Master Timing 1 116 SPI Slave Timing 0 1
7. 43 0140 017F CANO Freescale Scalable CAN FSCAN 44 Table 1 3 Detailed FSCAN Foreground Receive and Transmit Buffer Layout 45 0180 023F MO tco ge 46 13 MC9S12DJ64 Device User Guide V01 20 0240 0280 Table 1 4 Table 1 5 Table 2 1 Table 2 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 22 1 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 Table A 7 Table A 8 Table A 9 Table A 10 Table A 11 Table A 12 Table A 13 Table A 14 Table A 15 Table A 16 Table A 17 Table A 18 Table A 19 Table A 20 14 027F Port Integration Module 22 2 446 42 0 46 3FF Reserved NI ua inna tna 48 Assigned Part ID Numbers 49 Memory size 5 49 Signal Properties N N A OT AN 54 MC9S12DJ64 Power and Ground Connection Summary 64 Mode Selection N A eh 69 Clock Selection Based on PE7 ust ee Nr LR 69 Voltage Regulator Ne m Haan nn 70 Interrupt Vector hocatioRs SN LN exer 73 Suggested External Component Values 81 Absolute Maximum Ratings 4 Cr SRL 89
8. Write 00E4 229 D6 D5 D4 D3 D2 D1 Write Read 0 0 0 0 0 0 0 00E5 Reserved Write Read 0 0 0 0 0 0 0 0 00E6 Reserved Write Read 0 0 0 0 0 0 0 0 00E7 Reserved Write 40 Ws 4 ZH 886 3 5753170 4 JJ TE 86 21 54151736 HEFJI HGR JI 86 755 83298787 Http www 100y com tw 00E8 00EF Address 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF Name DLCBCR1 DLCBSVR DLCBCR2 DLCBDR DLCBARD DLCBRSR DLCSCR DLCBSTAT 00F0 00FF Address 00 0 00FF Name Reserved 0100 010F Address 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 M MOTOROLA Name FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD Reserved FADDRHI FADDRLO Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write BDLC Bytelevel Data Link Controller J1850 MC9S12DJ64 Device User Guide 01 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMSG CLKS 0 D IE WCM 0 0 I3 12
9. lo Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide 01 20 ECT Enhanced Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 MCZI MODMC RDMCL m un MCEN MCPRO MCZF 0 0 0 POLF3 POLF2 POLF1 POLFO PASEN PA2EN PAOEN 0 gt DLY1 DLYO NOVW7 NOVW6 NOVW5 NOVWA NOVW3 NOVW2 NOVW1 NOVWO SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 PBOVF 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 35 MC9S12DJ64 Device User Guide 01 20
10. Num C Rating Data Retention at an average junction temperature of 1 C ont TJavg 85 C 2 Flash number of Program Erase cycles NFLPE 3 EEPROM number of Program Erase cycles 40 C T 0 C AS EEPROM number of Program Erase cycles ka 100 000 0 C lt Ty lt 140 C FERE gt NOTES 1 Total time at the maximum guaranteed device operating temperature lt 1 year M MOTOROLA 103 MC9S12DJ64 Device User Guide V01 20 104 44 MOTOROLA A 4 Voltage Regulator MC9S12DJ64 Device User Guide 01 20 The on chip voltage regulator is intended to supply the internal logic and oscillator circuits No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 Civpp 220 nF Load Capacitance on VDDPLL Ci vpDfcPLL 220 nF M MOTOROLA 105 MC9S12DJ64 Device User Guide V01 20 106 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 A5 Reset Oscillator PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL A 5 1 Startup Table A 14 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block User Guide Table A 14 Startup Characteristics Conditions are show
11. Output High Voltage pins in output mode 5 Drive 2mA Full Drive 10mA Output Low Voltage pins in output mode 6 P Partial Drive 2mA Full Drive loj 10mA Internal Pull Up Device Current tested at VL Max Internal Pull Up Device Current 8 tested at Internal Pull Down Device Current 9 P tested at Internal Pull Down Device Current 10 C tested at 11 D Input Capacitance Injection current 12 T Single Pin limit Total Device Limit Sum of all injected currents 13 P Port H J P Interrupt Input Pulse filtered 14 P Port H J P Interrupt Input Pulse passed NOTES 1 Refer to Section A 1 4 Current Injection for more details 2 Parameter only applies in STOP or Pseudo STOP mode A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements 94 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 1 10 1 Measurement Conditions measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flow
12. 015F 0160 016F 0170 017F 017F Name CANOTXERR CANOIDARO CANOIDAR3 CANOIDMRO CANOIDMR3 CANOIDAR7 CANOIDMR7 CANORXFG CANOTXFG Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide 01 20 CANO Freescale Scalable CAN FSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXERR7 TXERR6 TXERRS TXERR4 TXERRS TXERR2 TXERR1 TXERRO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 1 AMO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 1 AMO FOREGROUND RECEIVE BUFFER see Table 1 3 FOREGROUND TRANSMIT BUFFER see Table 1 3 Table 1 3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address 0160 0161 0162 0163 0164 016B 016C 016D 016E 016F 0170 0171 Name Extended ID Standard ID CANORIDRO Extended ID Standard ID CANORIDR1 Extended ID Standard ID CANORIDR2 Extended ID Standard ID CANORIDR3 CANORDSRO CANORDSR7 CANORDLR Reserved CANORTSRH CANORTSRL Extended ID CANOTIDRO Standard ID Extended ID CANOTIDR1 Standard ID M MOTOROLA Read Read Write Read Read Write Read Read Write Read Read Write Read Write Read Write Read Write Read Write Read Write Read Write
13. Head 9 2 9 2 Write 0114 EPROT bd EPOPEN 4 Eppis EP2 EP1 EPO 0115 ESTAT BER LE pyioL 0 BLANK 0 0 0116 ECMD ies 0 CMDB6 CMDB5 gt 0 CMDB2 0 CMDBO 0117 Reserved for Read 0 0 0 0 0 0 0 0 Factory Test Write 0118 EADDRHI 1684 0 9 0 0 0 Bit 8 Write 0119 EADDRLO 1980 pi 6 5 4 3 2 1 Bit 0 Write 011A 980 15 14 13 12 11 10 9 Bit 8 Write 80118 EDATALO 192 6 5 4 3 2 1 Bit 0 Write 011C 011F Reserved for RAM Control Register Address Name 011C 011F Reserved 42 M MOTOROLA 0120 013F Address 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133 0134 0135 0136 0137 0138 M MOTOROLA Name ATD1CTLO ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STATO Reserved ATD1TESTO ATD1TEST1 Reserved ATD1STAT1 Reserved ATD1DIEN Reserved PORTAD1 ATD1DROH ATD1DROL ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write
14. Ne 105 Reset Qseillatonand PLIN NN ee Me rng 107 Es ae 107 EE g oan Meee NN S 108 Phage Pocked hoop een 109 MSCAN al So ag at ENS Mesas cae ees 113 SP Mio La AN raf erts u tna Rate a OR aM cct ot s v Nescis 115 ce eee ee NE AME LL ENT CAN 115 Slave AN EAN ONS eee ea A ENT NS 117 External Bus lt Fiming HO Na OY 119 General Mux d Bus Timing Qu Xx 2 222222 5 O I e ues 119 MC9S12DJ64 Device User Guide 01 20 Appendix B Package Information B 1 B 2 B 3 10 dual MX c MTM 123 112 package N da k g ti 4m 124 80 pin QFP package a CR et 125 d 886 3 5753170 WERE TI 86 21 54151736 WE d 3I 86 755 83298787 Http www 100y com tw M MOTOROLA MC9S12DJ64 Device User Guide 01 20 List of Figures Figure 0 1 Figure 1 1 Figure 1 2 Figure 1 3 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 3 1 Figure 22 1 Figure 22 2 Figure 22 3 Figure 22 4 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure B 1 Figure B 2 M MOTOROLA Order Partnumber
15. PORT J I O Pin 7 PJ7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the serial clock pin SCL of the IIC module It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 CANO M 886 3 5753170 Ji JJ EH 86 21 54151736 WERE 86 755 83298787 Http www 100y com tw 60 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 2 3 30 PJ6 KWJ6 SDA RXCANO PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the serial data pin SDA of the IIC module It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 CANO 2 3 31 PJ 1 0 KWJ 1 0 Port J Pins 1 0 and PJO are general purpose input or output pins They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 32 PK7 ECS ROMCTL Port K I O Pin 7 PK7 is a general purpose input or output pin During MCU expanded modes of operation this pin is used as the emulation chip select output ECS During MCU expanded modes of operation this pin is used to enable the Flash EEPROM memory in the memory map ROMCTL At the rising edge of RESET the state of this pin is latched to t
16. 0000 000F MEBI map 1 of 3 HCS12 Multiplexed External Bus Interface Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000 PORTA 16934 pi 6 5 4 3 2 1 Bit 0 Write 0001 PORTE Read pie 7 6 5 4 3 2 1 Bit 0 Write 0002 DDRA Read SR 6 5 4 2 1 Bit 0 Write 0003 DbnB 607 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 0004 Reserved C P n Read 0 0 0 0 0 0 0 0 0005 Reserved rito m M nEm Read 0 0 0 0 0 0 0 0 0006 Reserved us rHnas a Read 0 0 0 0 0 0 0 0 0007 Reserved rto 0008 PORTE 192 gi 6 5 4 3 2 I LEO Write 0009 DDRE 894 Bitz 6 5 4 3 Bit 2 Write 000A PEAR ae NOACCE 0 LSTRE Rowe 2 0 000B MODE E MODB MODA 2 wig 0 EMK EME 000 PUCR ds PUPKE SSS PUDAE 000D RDRIV N RDPK 0 aes 000E MT Write Read 0 0 0 0 0 0 0 0 000F Reserved Write NW CREER CET 0010 0014 MMC map 1 of 4 HCS12 Module Mapping Control Address 0010 Read Ramis Ramia RAMIS RAMI2 Rami e 0 _ Write EN d 0011 INITRG wo MEN L0 REG14 REG13 30 M MOTOROLA 0010 0014 Address Name 0012 INITEE 0013 MISC
17. 0014 Reserved 0015 0016 Address Name 0015 ITCR 0016 ITEST 0017 0019 Address Name 0017 0019 Reserved 001A 001B Address Name 001A PARTIDH 001B PARTIDL 001C 001D Address Name 001C MEMSIZO 001D MEMSIZ1 001E 001E Address Name 001E INTCR M MOTOROLA Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide 01 20 MMC map 1 of 4 HCS12 Module Mapping Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE15 EE14 EE13 EE12 EE11 EEON 0 Q EXSTR1 EXSTRO ROMHM ROMON 0 0 0 0 0 0 0 0 INT map 1 of 2 HCS12 Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 WRINT ADR3 ADR2 ADR1 ADRO INTE INTC INTA INT8 6 INT4 INT2 INTO Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Device ID Register Table 1 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID15 1014 1013 1012 1011 1010 109 108 107 106 105 104 103 102 101 100 map 3 of 4 HCS12 Module Mapping Control Table 1 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O reg swO 0 swi1 sw0 0 ram Sw2
18. 5 are Write once in Normal and Emulation modes and write anytime in Special modes PPAGE Reset state 00 Register is Write anytime in all modes MEMSIZO Reset state 11 MEMSIZI Reset state 80 6 3 HCS12 Multiplexed External Bus Interface MEBI Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module 6 3 1 Device specific information PUCR Reset state 90 77 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 6 4 HCS12 Interrupt INT Block Description Consult the INT Block Guide for information on the 512 Interrupt module 6 5 HCS12 Background Debug BDM Block Description Consult the BDM Block Guide for information on the HCS12 Background Debug module 6 5 1 Device specific information When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock 6 6 HCS12 Breakpoint BKP Block Description Consult the BKP Block Guide for information on the HCS12 Breakpoint module Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 7 1 Device specific information The Low Voltage Reset feature of the CRG is not available on this device Section 8 Oscillator OSC Block Description Consult the OSC Block User Guide for information about the Oscillator module 8 1 Device specific information
19. A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature is not exceeded The average chip junction temperature in can be obtained from Tat Pp Oya Tj Junction Temperature C M MOTOROLA 91 MC9S12DJ64 Device User Guide V01 20 Ambient Temperature C Ta Pp Total Chip Power Dissipation W ja Package Thermal Resistance C W The total power dissipation can be calculated from Pp PINT Chip Internal Power Dissipation W Two cases with internal voltage regulator enabled and disabled must be considered 1 Internal Voltage Regulator disabled Pint Ypo ppPLL VppP LL t ppA VpDA 2 AG Roson lo is the sum of all output currents on I O ports associated with VDDX For Rpson is valid V RDSON outputs driven low respectively V V DA for outputs driven high OH 2 Internal voltage regulator enabled Pint ppR ppa Ippg is the current shown in Table A 7 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high 2 Roson lo is the sum of all output currents on I O ports associated with VDDX and VDDR 92 M MOTOROLA MC9S12DJ64 Devi
20. 002F HCS12 Breakpoint 32 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control 32 0032 50033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface 32 0034 003F CRG Clock and Reset Generator 33 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels 33 0080 009F Analog to Digital Converter 10 Bit 8 Channel 36 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel 37 00C8 00CF SCIO Asynchronous Serial Interface 39 0000 0007 SCI Asynchronous Serial Interface 39 0008 00DF SPIO Serial Peripheral 40 00E0 80E7 IIC Inter IC Bus 40 00E8 00EF BDLC Bytelevel Data Link Controller J1850 41 0056 00FRWReser Qed eNN Maren eee 41 0100 010F Flash Control Register fts64k 41 0110 011 EEPROM Control Register eets1k 42 011 011F Reserved for RAM Control Register 42 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel
21. 2 With each transition of the clock femp the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 3 110 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure A 3 Jitter Definitions The relative deviation of thom 15 at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as max ND N t nom N t nom J N mad x tai N For N lt 100 the following equation is a good fit for the maximum jitter 14 09 Jas j NN 1 5 10 20 N Figure A 4 Maximum bus clock jitter approximation M MOTOROLA 111 MC9S12DJ64 Device User Guide V01 20 This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table A 16 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted Wwe wm Te Tr Fraser 2 VCO locking range fvco 8 50 MHz 3 Lock Detector transition from Acquisition to Tracking lud 3 4 x mode 4 Lock Detect
22. For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table A 4 Operating Conditions Rating Symbol Min Typ Max Unit Regulator and Analog Supply Voltage 505 4 5 5 5 25 V Digital Logic Supply Voltage Vpp 2 35 2 5 2 75 V PLL Supply Voltage VDDPLL 2 35 25 2 75 V Voltage Difference VDDX to VDDR and VDDA ANDDX 0 1 0 0 1 V Voltage Difference VSSX to VSSR and VSSA Avssx 0 1 0 0 1 V Oscillator fosc 0 5 16 MHz Bus Frequency fbus 0 252 25 MHz MC9S12DJ64C Operating Junction Temperature Range 40 100 C Operating Ambient Temperature Range Ta 40 27 85 C MC9S12DJ64V Operating Junction Temperature Range 40 120 C Operating Ambient Temperature Range Ta 40 27 105 C MC9S12DJ64M Operating Junction Temperature Range T 40 140 C Operating Ambient Temperature Range Ta 40 27 125 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The given operating range applies when this regulator is disabled and the device is powered from an external source 2 Some blocks e g ATD conversion and NVMs program erase require higher bus frequencies for proper oper ation 3 Please refer to Section A 1 8 Power Dissipation and Thermal Characteristics for more details about the rela tion between ambient temperature and device junction temperature
23. PRE RTR2 CR2 Bit 1 SYN1 REFDV1 0 SCMIF SCMIE RTIWAI PCE RTR1 0 Enhanced Capture 16 8 Channels 7 57 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN TOV7 OM7 OM3 Bit 6 1056 0 FOC6 OC7M6 OC7D6 14 TSWA TOV6 OL7 OL3 Bit 5 1055 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 Bit 4 1054 0 FOC4 OC7M4 OC7D4 12 TFFCA TOV4 OL6 OL2 Bit 3 1053 0 FOC3 OC7M3 OC7D3 11 TOV3 5 OM1 Bit 2 1052 0 2 OC7M2 OC7D2 10 2 TOV2 15 OL1 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 TOV1 OM4 OM0 SCM Bit 0 SYN0 REFDV0 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0 Bit 0 IOS0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 TOV0 OL4 OL0 33 MC9S12DJ64 Device User Guide V01 20 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Name Bt7 Bite Bits Bit2 Biti Bit 0 004A TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 004B TCTL4 e EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB EDGOA 004C TIE N 5 ca Cal C2l Col 004D TSCR2 ee TOI 9 2 TCRE PR2 PR1 PRO 004E TFLG1 NOn C7F C6F C5F C3F C2
24. 01 20 Section 3 System Clock Description 3 1 Overview The Clock and Reset Generator provides the internal clock signals for the HCS12 Core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide and OSC Block User Guide for details on clock generation Core Clock RB ECT WM HCS12 CORE EXTAL e Nw B e AUT ST EE PES MCI SE ail OSC CRG NN CANO XTAL BDLC Figure 3 1 Clock Connections 67 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 68 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 4 Modes of Operation 4 1 Overview Eight possible modes determine the operating configuration of the MC9S12DJ64 and MC9S12D32 Each mode has an associated default memory map and external bus configuration Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 1 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are latched into these bits on the rising edge of the reset signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible
25. 64 4 FH 886 3 5753170 Ji 7 EN 86 21 54151736 WE 45 86 755 83298787 M MOTOROLA Http www 100y com tw MC9S12DJ64 Device User Guide 01 20 2 3 57 RXD amp Port S VO N OM EN 64 2 3 58 PT 7 0 IOC 7 0 Port T I O Pins 7 0 64 A4 Power Supply Ping N a CUT een 64 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers 65 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator 65 2 4 3 VDD1 VDD2 551 VSS2 Internal Logic Power Supply Pins 65 2 4 4 VDDA VSSA Power Supply Pins for ATDO ATD1 and VREG 65 2 4 5 VRH VRL Reference Voltage Input Pins 66 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL 66 2 4 7 VREGEN On Chip Voltage Regulator Enable 66 Section 3 System Clock Description 8 1 Overview 7 NNM grosse aD 67 Section 4 Modes of Operation _ Overview C D GA 69 42 Chip Configuration Summary LAN AU 69 4 3 SecugfyA NN CO NA 70 4 3 1 Securing the Microcontroller 70 4 3 2 Operation of the Secured Microcontroller
26. Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 PWM Pulse Width Modulator 8 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME7 PWME6 PWME5 PWME4 PWMES PWME2 PWME1 PWMEO PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOLO PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO PCKB2 PCKB1 PCKBO PCKA2 PCKA1 PCKAO CAE7 CAE6 5 CAE4 2 CAE CAEO CON67 CON45 CON23 CONO PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 37 MC9S12DJ64 Device User Guide V01 20 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 009 PWMSCLB 1984 pi 6 5 4 3 2 1 Bit 0 Write PWMSCNTA Read 0 0 0 0 0 0 0 0 00AA Test Only Write PWMSCNTB Read 0 0 0 0 0 0 0 0 00 Test Only Write Read Bit7 6 5 4 3 2 1 Bit 0 MENT Wite 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 800488 ND 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00AE PWMONT2 Write 0 0 0 0 0 0 0 Read Bi
27. MOTOROLA MC9S12DJ64 Device User Guide 01 20 Appendix A Electrical Characteristics A 1 General This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the parameter tables where appropriate Those parameters are guaranteed during production testing on each individual device Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted values shown in the typical column are within this category Those parameters are derived mainly from simulations A 1 2 Power Supply The MC9S12DJ64 and MC9S12D32 utilize several pins to supply power to the ports A D converter oscillator PLL and internal logic The VDDA VSSA pair supplies the A D converter and the resistor ladder of the internal voltage regulator The VDDX VSSX VDDR and VSSR pairs supply the I O pins VDDR supplies also the internal voltage r
28. Read Write Read Write Read Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 ID2 ID1 IDO RTR IDE 0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO DLC3 DLC2 DLC1 DLCO TSR15 TSR14 TSR13 TSR12 11 TSR10 TSR9 TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 ID2 ID1 IDO RTR IDE 0 45 MC9S12DJ64 Device User Guide 01 20 Table 1 3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read nio CANOTIDR2 Write ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Standard ID Read Write Extended ID Read ni CANOTIDRO Write ID6 ID5 ID4 ID3 ID2 101 IDO RTR Standard ID Read Write 0174 CANOTDSRO Read sos CANOTDSRZ DB DB6 DB5 DB4 DB3 DB2 DB1 DBO 017C CANOTDLR Kaw DLC3 DLC2 017D CANOTTBPR N PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIOO Se CAN TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 017 CANOTTSRL Read TSR7 TSR6 T
29. amp 020 C AB p SECTION B B 5 DATUM VIEW ROTATED 90 ELO SED SEATING PLANE NOTES MILLIMETERS DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 DIM MIN MAX 2 CONTROLLING DIMENSION MILLIMETER A 1390 14 10 3 DATUM PLANE H IS LOCATED AT BOTTOM OF B 1390 14 10 LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC C 215 245 BODY AT THE BOTTOM OF THE PARTING LINE D 022 038 4 DATUMS A B D TO BE 200 240 DETERMINED AT DATUM PLANE H 02 5 DIMENSIONS S AND V TO BE DETERMINED DATUM 6 DIMENSIONS A AND 8 DO NOT INCLUDE H 0 25 PLANE CHT MOLD PROTRUSION ALLOWABLE J 013 023 PROTRUSION IS 0 25 PER SIDE DIMENSIONS A AND DO INCLUDE MOLD MISMATCH K 065 0 95 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR M 109 PROTRUSION ALLOWABLE DAMBAR N 17 PROTRUSION SHALL BE 0 08 TOTAL IN 0 13 0 EXCESS OF THE D DIMENSION AT MAXIMUM P 0 325 BSC Q MATERIAL CONDITION DAMBAR CANNOT a oo 79 BE LOCATED ON THE LOWER RADIUS OR R 013 030 THE FOOT S 1695 1745 T 043 DETAIL C ul o V 1695 1745 W 035 045 X 1 6 REF Figure B 2 80 pin QFP Mechanical Dimensions case no 841B M MOTOROLA 125 MC9S12DJ64 Device User Guide V01 20 126 44 M
30. 0 0 0 0 0 0 008E Reserved Write sone Rad 6 5 4 3 2 1 BIT 0 Write 80090 ATDopRou Peagi Bts 14 13 12 11 10 9 Bit8 Write 0091 ATD0DR0L Read Bit7 Bit6 0 0 0 0 0 0 Write 36 M MOTOROLA 0080 009F Address 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F Name ATDODR1H ATDODR1L ATDODR2H ATDODR2L ATDODRSH ATDODRSL ATDODR4H ATDODRAL ATDODRSH ATDODRSL ATDODR6H ATDODR6L ATDODR7H ATDODR7L 00A0 00C7 Address 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 M MOTOROLA Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC Test Only PWMSCLA Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATDO Analog to Digital Converter 10 Bit 8 Channel MC9S12DJ64 Device User Guide 01 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Biti5 14 13 12 11 10 9 Bits
31. 01 20 Internal Pull Pin Name Pin Pin Pin Name Powered Resistor Description Function1 Function2 Function3 Function4 by Reset State PJ7 KWJ7 SCL TXCANO Interrupt SCL of IIC TX of PERJ PJ6 KWJ6 SDA RXCANO VDDX PPSJ 4 I O Interrupt SDA of IIC RX of PJ 1 0 KWJ 1 0 Port J I O Interrupts Port I O Emulation Chip Select PK7 ECS ROMCTL lt Up ROM On Enable p PK 5 0 XADDR 19 14 Port I O Extended Addresses PM7 mE Port M I O PM6 S jw Port M PM5 TXCANO SCK Port M I O TX of CANO of SPIO 4 MOSI Port I O RX of CANO MOSI of SPIO PM3 TXCANO so Port M I O TX of CAN0 SS of SPI0 PM2 RXCANO MISOO Port M I O RX CANO MISO of SPIO PM1 TXCANO TXB Port M I O TX of RX of BDLC PMO RXCANO RXB Port M I O RX of CAN0 RX of BDLC PP7 KWP7 PWM7 Disabled EN Interrupt Channel 7 of PP6 KWP6 PWM6 Port P I O Interrupt PWM Channel 6 PP5 KWP5 PWM5 Port P I O Interrupt PWM Channel 5 PP4 KWP4 PWM4 VDDX 631 Port Interrupt PWM Channel 4 PP3 KWP3 PWM3 Port P I O Interrupt PWM Channel 3 PP2 KWP2 PWM2 SS Port P I O Interrupt PWM Channel 2 PP1 KWP1 PWM1 Port P I O Interrupt PWM Channel 1 PPO KWPO PWMO Port P I O Interrupt PWM Channel 0 PS7 550 Port S 1 0 SS of SPI
32. BDM operation The BDM operation will be blocked 70 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH and EEPROM will be disabled BDM operations will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH and EEPROM must be erased This can be done through an external program in expanded mode or via a sequence of BDM commands Unsecuring is also possible via the Backdoor Key Access Refer to Flash Block Guide for details Once the user has erased the FLASH and EEPROM the part can be reset into special single chip mode This invokes a program that verifies the erasure of the internal FLASH and EEPROM Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult the respective Block User Guide for information on the module
33. Block Description Section 22 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics A 1 A 1 1 A 1 2 A 1 3 A 1 4 1 5 1 6 1 7 1 8 1 9 1 10 2 A 2 1 A 2 2 A 2 3 A 3 A 3 1 A 3 2 A 4 A 5 A 5 1 A 5 2 A 5 3 A 6 A 7 A 7 1 7 2 8 A 8 1 M MOTOROLA A NN een 87 Parameter Classification 1MN ee 87 Rewer Supply ck oe cows ee NT CM N 2 87 AE eR Sera red 88 Current injection ty CI ENT aa S 88 Absolute Maximum Ratings aN 2 222 220 AN BM 89 ESD Protection and Latch up 90 Operating Conditions a er RIN cat 90 Power Dissipation and Thermal Characteristics 91 VOCharacteristics 08 7 Ne bt wal 93 Supply Net a cake age ee ee ee NN Ne 94 Characteristics 2 97 Operating Characteristics 97 FactarSinfluencing 97 ATD NN A ANP LENS rN ee NA 99 NVM Flash and EEPROM 101 NVM ing NS Oh NN 101 NVM Reliability NN AN RM erm Ne 103 Voltage Regulator AN NN QN
34. Divider Figure A 2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for and i from Table A 16 The grey boxes show the calculation for fyco 50MHz and f ef E g these frequencies are used for fosc 4MHz and a 25 bus clock The VCO Gain at the desired VCO frequency is approximated by f fuco 60 50 K 1V 772100 Ke 100 e 99 90 48MHz V M MOTOROLA 109 MC9S12DJ64 Device User Guide 01 20 The phase detector relationship is given by 316 7 2 0 ich 15 the current in tracking mode The loop bandwidth f should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response PAGAN GE 1 ANY SE o 10 tern 0 9 2 eet 0 fc 25kHz And finally the frequency relationship is defined as fvco f 2 8 1 50 ref With the above values the resistance can be calculated The example is shown for a loop bandwidth fc 10kHz 42 mo n fo R K 2 01 50 10kHz 316 7Hz 0 29 9kOz 10k The capacitance C now be calculated as 2 _ 2 0 0 516 _ 5 19nF 4 7nF ET A ae ae The capacitance C should be chosen in the range of 0 20 lt C lt C 10 470 A 5 3 2 Jitter Information The basic functionality of the PLL is shown in Figure
35. PIX4 PIX3 PIX2 PIX PIXO MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface Read 1 i Write a S s i Read i Write idi FRIES N M MOTOROLA 0034 003F Address 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP 0040 007F Address 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 M MOTOROLA Name TIOS CFORC OC7M OC7D TCNT hi TCNT lo TSCR1 TTOV TCTL1 TCTL2 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide 01 20 CRG Clock and Reset Generator Bit 7 0 0 0 RTIF RTIE PLLSEL CME 0 WCOP 0 0 0 Bit 7 Bit 6 0 0 0 PORF PSTP PLLON RTR6 RSBCK Bit 5 SYN5 0 0 0 0 SYSWAI AUTO RTR5 0 0 Bit 4 SYN4 0 0 LOCKIF LOCKIE ROAWAI ACQ RTR4 0 0 Bit 3 SYN3 REFDV3 0 LOCK PLLWAI 0 RTR3 Bit 2 SYN2 REFDV2 0 TRACK CWAI
36. TC RDRF IDLE OR NF FE PF 39 MC9S12DJ64 Device User Guide V01 20 00DO 00D7 SCH Asynchronous Serial Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0005 Head 0 Q 0 D BRK13 Write 0006 Head 8 T8 D 0 0 0 0 0 Write Read R7 R6 R5 R4 R3 R2 Ri RO 50007 Qi CT T6 T6 T4 T3 T2 Ti TO 00D8 00DF SPIO Serial Peripheral Interface Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50008 SPIOCR1 asw SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 50009 SPIOCR2 0 MODFEN BIDIROE 0 spiswai spco 00DA SPIOBR el SPPR2 SPPR1 SPPRO 0 SPR2 SPR1 SPRO spiosn Read SPF 0 SPTEF MODF 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 00DC Reserved Write 50000 sPiopr 198 gig 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00DE Reserved Write Read 0 0 0 0 0 0 0 0 00DF Reserved Write 00E0 00E7 Inter IC Bus Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 IBAD v ADR7 ADR6 ADR5 ADR4 ADR3 ADR ADRI 0 Read 00E1 IBFD wie BC7 1BC6 IBCS IBC4 IBCs IBC2 IBC1 IBCO Read ES 0 0 00E2 IBCR Write IBEN MSE TXRX TXAK I IBSWAI Read IAAS IBB ay 0 SRW
37. The XCLKS input signal is active low see 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 Section 9 Enhanced Capture Timer ECT Block Description Consult the ECT 16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT 16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode 78 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 10 Analog to Digital Converter ATD Block Description There are two Analog to Digital Converters ATD1 and ATDO implemented on the MC9S12DJ64 Consult the 10 8 Block User Guide for information about each Analog to Digital Converter module When the 10B8C Block User Guide refers to freeze mode this is equivalent to active mode Section 11 Inter IC Bus IIC Block Description Consult the IIC Block User Guide for information about the Inter IC Bus module Section 12 Serial Communications Interface SCI Block Description There are two Serial Communications Interfaces 5 and SCIO implemented on the MC9S12DJ64 device Consult the SCI Block User Guide for information about each Serial Communications Interface module Section 13 Serial Peripheral Interface SPI Block Description Consult the SPI Block User Guide for information about each Serial Peripheral Interface module Section 14 J1850 BDLC Block Description Consult the BDLC Block User Guide for information about the J1850 module Section 15
38. VSSPLL PLL P ion Periodic Interrupt EXTAL Module COP Watchdog Clock Monitor RESET Breakpoints PEO XIRQ PE1 IRQ PE2 System PE3 ISTRE Integration PE4 ECLK PE5 MODA PE6 MODB PE7 5 Multiplexed Address Data Bus st QN cn co raaraa QD 10 st CO CELL Ci CAD D O cO O O DONA OQARA lt lt lt lt lt lt lt lt lt lt 4 lt lt lt lt lt lt qi AME ba Multiplexed lt lt lt lt lt lt lt 222524532 Wide Bus 1 i Le 7 5 4 5 lt Multiplexed 22232922 i Narrow Bust 545433533 Internal Logic 2 5V Driver 5 VDD1 2 VDDX VSS1 2 VSSX JE 1 A D Converter 5V amp PLL 2 5V Voltage Regulator Reference VDDPLL VSSPLL VSSA Voltage Regulator 5V amp I O VDDR VSSR M MOTOROLA ATDO VRH VRL VDDA VSSA VRH VRL VDDA VSSA ATD1 XADDR14 XADDR15 2 XADDR16 XADDR17 XADDR18 XADDR19 Enhanced Capture Timer BDLC 41850 gt PMO CANO RXCAN PM1 TXCAN PM2 Signals shown in Bold are not available on the 80 Pin Package 23 MC9S12DJ64 D
39. behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and the Real Time Interrupt RTI or Watchdog COP sub module can stay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU signals address and data bus will be fully static All peripherals stay active For further power consumption the peripherals can individually turn off their local clocks M MOTOROLA 71 MC9S12DJ64 Device User Guide 01 20 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power 72 M MOTOROLA Section 5 Resets and Interrupts 5 1 Overview MC9S12DJ64 Device User Guide 01 20 Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts 5 2 Vectors 5 2 1 Vector Ta
40. can be configured as the transmit pin TXD of Serial Communication Interface 0 SCIO 2 3 57 PSO RXDO0 Port S I O Pin 0 50 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 0 SCIO 2 3 58 PT 7 0 IOC 7 0 Port T I O Pins 7 0 PT7 PTO are general purpose input or output pins They can be configured as input capture or output compare pins IOC7 IOCO of the Enhanced Capture Timer ECT 2 4 Power Supply Pins MC9S12DJ64 power and ground pins are described below NOTE All VSS pins must be connected together in the application Table 2 2 MC9S12DJ64 Power and Ground Connection Summary Mnemonic Description 112 pin Voltage P VDD1 2 13 65 2 5V Internal power and ground generated by internal regulator VSS1 2 14 66 OV VDDR 41 5 0V External power and ground supply to pin drivers and internal VSSR 40 OV voltage regulator VDDX 107 5 0V Ext 4 vice an xternal power and ground su pin drivers VSSX 106 ov Nr VDDA 83 5 0V Operating voltage and ground for the analog to digital converters and the reference for the internal voltage regulator VSSA 86 OV allows the supply voltage to the A D to be bypassed independently VRL 85 OV MU Reference voltages for the analog to digital converter VRH 84 5 0V 64 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Mnemonic Description 11
41. information about the EEPROM module Section 18 RAM Block Description This module supports single cycle misaligned word accesses Section 19 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Freescale Scalable CAN Module Section 20 Port Integration Module PIM Block Description Consult the PIM 9DJ64 Block User Guide for information about the Port Integration Module Section 21 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator Section 22 Printed Circuit Board Layout Proposals 80 4 886 3 5753170 M MOTOROLA EH 86 21 54151736 WERE E FREYI 86 755 83298787 Http www 100y com tw MC9S12DJ64 Device User Guide 01 20 Table 22 1 Suggested External Component Values Component Purpose Type Value VDD1 filter cap ceramic X7R 100 220nF C2 VDD2 filter cap ceramic X7R 100 220nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R tantalum gt 100nF C5 VDDPLL filter cap ceramic X7R 100nF C8 VDDX filter cap X7R tantalum gt 100nF OSC load cap OSC load cap 9 PLL loop filter cap See PLL specification chapter 10 PLL loop filter Colpitts mode only if recommended by 11 C11 Coc DC cutoff cap quartz manufacturer R1 PLL loop filter res See PLL specification chapter PLL loop filter res
42. purpose input or output pin It can be configured to generate an interrupt causing the to exit STOP or WAIT mode M MOTOROLA 59 MC9S12DJ64 Device User Guide 01 20 2 3 22 PH6 KWH6 Port H I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 23 PH5 KWH5 Port H I O Pin 5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 24 PHA KWHA Port H I O Pin 2 PH4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 25 PH3 KWH3 Port H I O Pin PH3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 26 PH2 KWH2 Port H I O Pin 2 PH2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 27 1 KWH1 Port H I O Pin 1 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 28 PHO KWHO Port H I O Pin 0 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 29 PJ7 KWJ7 TXCANO
43. ram_sw1 ram swO rom_sw1 rom_swO 0 0 0 0 sw1 pag_sw0 MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQE IRQEN 0 0 0 0 0 0 31 001F 001F Address 001F Name HPRIO 0020 0027 Address Name 0020 0027 Reserved 0028 002F Address Name 0028 BKPCTO 0029 1 002 002 002 BKPOL 002D BKP1X 002E BKP1H 002F BKP1L 0030 0031 Address Name 0030 PPAGE 0031 Reserved 0032 0033 Address Name 0032 PORTK 0033 DDRK MC9S12DJ64 Device User Guide V01 20 INT map 2 of 2 HCS12 Interrupt Read Write PSEL7 PSEL6 PSEL5 PSELA PSEL3 PSEL2 PSEL1 SG 1 96 sbs 0 0 BKP HCS12 Breakpoint Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read ken BKFULL BKBDM BKTAG Write Pr BKOMBH BKOMBL BK1MBH BK1MBL BKORWE BKORW BK1RWE BK1RW a u BKOV5 BKOV4 BKOV3 BKOV2 BKOVO Read Ss 14 13 12 11 10 9 Bit 8 Write Read i wa NBI 6 5 4 3 2 1 Bit 0 K xs BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1VO Read gt 14 13 12 11 10 9 Bit 8 Write Read i wie BEY 6 5 4 3 2 1 Bit 0 MMC map 4 of 4 HCS12 Module Mapping Control rom PIX5
44. 1 5 Memory size registers Register name MEMSIZO MEMSIZ1 80 49 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 50 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 2 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties and detailed discussion of signals It is built from the signal description sections of the Block Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S12DJ64 is available in a 112 pin low profile quad flat pack LQFP and in a 80 pin quad flat pack QFP The MC9S12D32 is only available in a 80 pin quad flat pack QFP Most pins perform two or more functions as described in the Signal Descriptions Figure 2 1 and Figure 2 2 show the pin assignments M MOTOROLA 51 MC9S12DJ64 Device User Guide V01 20 12 3 PPA KWP4 PWMA 11 3 PP5 KWP5 PWM5 10 3 PP6 KWP6 PWM6 09 2 PP7 KWP7 PWM7 08 O PK7 ECS ROMCTL PWM3 KWP3 PP3 PWM2 KWP2 PP2 PWM1 KWP1 PP1 PWM0 KWP0 PP0 XADDR17 PK3 XADDR16 PK2 XADDR15 PK1 XADDR14 PKO 10C1 PT1 IOC2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 9 ADDRBS DATAS PB5 2 ADDR6 DATA6 PB6 130 ADDR7 DATA7 PB7 0 31 KWH7 PH7 132 KWH6 PH6 KW
45. 12 Interrupt INT Block 78 512 Background Debug Block Description 78 Device specific information 78 HCS12 Breakpoint Block Description 78 Section 7 Clock and Reset Generator CRG Block Description 7 1 Device specific 78 Section 8 Oscillator OSC Block Description 8 1 Device specific 78 Section 9 Enhanced Capture Timer ECT Block Description Section 10 Analog to Digital Converter ATD Block Description Section 11 Inter IC Bus Block Description Section 12 Serial Communications Interface SCI Block Description Section 13 Serial Peripheral Interface SPI Block Description Section 14 J1850 BDLC Block Description Section 15 Pulse Width Modulator PWM Block Description Section 16 Flash EEPROM 64K Block Description Section 17 EEPROM 1K Block Description 7 886 3 5753170 WERE JJ EH 86 21 54151736 WE 4 HL HEI 86 755 83298787 Section 18 RAM Block Description Http www 100y com tw Section 19 MSCAN Block Description M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 20 Port Integration Module PIM Block Description Section 21 Voltage Regulator VREG
46. 13D ATD1DR6L Read Bit7 Bit6 0 0 0 0 0 0 Write sos ar Read Bits 14 13 12 11 10 9 Bit8 Write 013F ATD1DR7L Read Bit7 Bit6 0 0 0 0 0 0 Write 0140 017F CANO0 Freescale Scalable CAN FSCAN Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50140 Ne EXACT LSYNCH time wure SLPRQ INITRO 50141 CANOCTL1 ae CLKSRC LOOPB LISTEN wupm SEPAK 0142 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 50143 1 e SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0144 CANORFLG e WUPIF csc r RSC OVRIF 0145 CANORIER WUPIE CSCIE 1 TSTATE1 TSTATEO OVRIE RXFIE 0146 CANOTFLG 2 9 9 9 D 0 TXE2 1 TXEO 50147 CANOTIER 0 0 Q TXEIE2 TXEIE1 TXEIEO 0148 e 9 0 9 D 0 2 ABTRQ1 ABTRQO cane EE e 0 0 0 ABTAK2 ABTAKO Write 014A CANOTBSEL de 9 9 9 9 9 TX2 TX1 TXO 90148 in 0 0 IDAM1 IDAMO 0 IDHIT2 IDHITO Read 0 0 0 0 0 0 0 0 014C Reserved Write Read 0 0 0 0 0 0 0 0 014D Reserved Write ara OR MES RXERR7 RXERR6 RXERRS RXERR4 RXERR3 RXERR RXERR1 RXERRO 44 M MOTOROLA 0140 Address 014F 0150 0153 0154 0157 0158 015B 015C
47. 17 Slave Timing 1 A EM LAN XN 117 General External Bus Timing 185 49 LU EN 120 112 pin mechanical dimensions case 987 124 80 pin QFP Mechanical Dimensions case no 841B 125 11 MC9S12DJ64 Device User Guide V01 20 12 44 MOTOROLA M MOTOROLA MC9S12DJ64 Device User Guide 01 20 List of Tables Table 0 1 Derivative Differences 15 Table 0 2 Document References 17 Table 1 1 Device Memory Map for MC9S12DJ64 25 Table 1 2 Device Memory Map for 9512032 28 0000 000F MEBI map 1 of 3 HCS12 Multiplexed External Bus Interface 30 0010 0014 MMC map 1 of 4 HCS12 Module Mapping Control 30 0015 0016 map 1 of 2 HCS12 31 0017 8019 BleServegd mese aee IN 31 001A 001B Device ID Register Table 1 4 31 001C 001D MMC map 3 of 4 HCS12 Module Mapping Control Table 1 5 31 001E 001 MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface 31 001F 001F INT map 2 of 2 HCS12 Interrupt M 32 0020 0027 Resefved AM Li En AD Esse 32 0028
48. 2 pin Voltage VDDPLL 43 2 5V Provides operating voltage and ground for the Phased Locked Loop This allows the supply voltage to the PLL to be VSSPLL 45 OV bypassed independenily Internal power and ground generated by internal regulator VREGEN 97 5 0V Internal Voltage Regulator enable disable 2 4 1 VDDX VSSX Power amp Ground Pins for Drivers External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded VDDX and VSSX are the supplies for Ports J K M P T and S 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator External power and ground for I O drivers and input to the internal voltage regulator Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded VDDR and VSSR are the supplies for Ports A B E and H 2 4 3 VDD1 VDD2 VSS1 VSS2 Internal Logic Power Supply Pins Power is supplied to the MCU through VDD and VSS Because fast signal transitions place high short duration current demands on the power supp
49. 6 output 2 3 44 PP5 KWP5 PWM5 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output 2 3 45 KWP4 PWM4 Port P I O Pin 4 PP4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 4 output 62 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 2 3 46 PP3 KWP3 PWM3 Port P I O Pin 3 PP3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 3 output 2 3 47 2 KWP2 PWM2 Port P I O Pin 2 PP2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 2 output 2 3 48 PP1 KWP1 PWM1 Port P I O Pin 1 is a general purpose input or output pin It can be configured to generate an interrupt causing MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 1 output 2 3 49 KWPO PWMO Port P I O Pin 0 PPO is a general purpose input or output pin It can be configured to gener
50. 7 PPSJ6 q D PPSJ1 PPSJO 026E PIEJ Wi PIEJ7 PIEJ6 0 9 0 0 PIEJO 026F PIFJ Read PIFJ6 0 2 0 PIFJ1 PIFJO Write 0270 Mead 0 0 0 0 0 0 0 027 Write 0280 03FF Reserved Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0280 Read 0 0 0 0 0 0 0 0 03FF Write 48 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 1 6 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read only value is a unique part ID for each revision of the chip Table 1 4 shows the assigned part ID number Table 1 4 Assigned Part ID Numbers Device Mask Set Number Part ID MC9S12DJ64 01860 50200 MC9S12DJ64 1L86D 0201 MC9S12DJ64 2L86D 0201 MC9S12DJ64 3L86D 0203 MC9S12DJ64 AL86D 0204 MC9S12DJ64 0M89C 0204 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision 2 1L86D is identical to 2L86D except improved ESD performance on 2L86D The device memory sizes are located in two 8 bit registers MEMSIZO and MEMSIZI addresses 001C and 001D after reset Table 1 5 shows the read only values of these registers Refer to HCS12 Module Mapping Control MMC Block Guide for further details Table
51. A 5 MC9S12DJ64 Device User Guide 01 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 3 32 2 3 33 2 3 34 2 3 35 2 3 36 2 3 37 2 3 38 2 3 39 2 3 40 2 3 41 2 3 42 2 3 43 2 3 44 2 3 45 2 3 46 2 3 47 2 3 48 2 3 49 2 3 50 2 3 51 2 3 52 2 3 53 2 3 54 2 3 55 2 3 56 PR KWAY Port H VORIN 7 2 AN Ku 2 59 PH6 KWH6 Port H I O Pin 6 _ 60 PH5 KWH5 Port H I O Pin _ 60 7 KWH4 Port H I O Pin 2 60 PH3 KWH3 Port H I O _ 60 PH2 KWH2 Poit HO Pin 2 atl nne 60 PH1 KWH1 PortHI OPin1 _ 60 PHO KWHO PortHI OPin0_ 60 KWJ7 SCL TXQANO PORT J VO Pin 7 60 PJ6 KWJ6 SDA RKCANO PORT J 61 PJ 1 0 KWJ 1 0 Port J I O Pins 1 0 61 ECS ROMCTL Port KI OPin7 61 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 61 7 Par M VO RIZ CNE EN 22222 NAN OY LAN 61 PM6 Port Pin et a 26 61 PM5 SCK0 Port M 5
52. Burst Programming Time for 32 Words eem 67842 109553 ws 8 P Mass Erase Time tmass 100 5 133 3 ms 9 D Blank Check Time Flash per block tcheck 116 32778 7 10 D Blank Check Time EEPROM per block 116 2058 NOTES 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency fyymop and maximum bus frequency fous Maximum Erase and Programming times are achieved under particular combinations of fyymop and bus frequency fps Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance Burst Programming operations are not applicable to EEPROM Minimum Erase times are achieved under maximum NVM operating frequency fyymop Minimum time if first word in the array is not blank Maximum time to complete check on an erased block O 102 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 3 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program erase cycling are specified at the operating conditions noted The program erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table 12 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted
53. DOCUMENT NUMBER 9512DJ64DGV1 D MC9S12DJ64 Device User Guide V01 20 Covers also 9512064 9512 64 9512032 9512 32 Original Release Date 19 Nov 2001 Revised 6 April 2005 We J 886 3 5753170 JE EE JJ HT EH 86 21 54151736 MERE E RHI 86 755 83298787 Http www 100 com tw Freescale Semiconductor Inc Freescale reserves the right to make changes without further notice to any products herein to improve reliability function or design Freescale does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Freescale products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use e
54. ESD and Latch up Test Conditions ANT CM AN 90 ESD and Latch Up Protection Characteristics 90 Operating G hditioqSW 2 Lu NN Q QM LL 91 Thermal Package Characteristics 93 SV Characteristics LN 94 Supply Current Characteristics Wr liem AE 95 Operating Characteristics 97 Electrical Characteristics 98 Conversion Performance 99 NVM Timing Characteristics S ake eee ANS AS 102 NVM Reliability Charact niStics amp 103 Voltage Regulator Recommended Load Capacitances 105 Startup Characteristics CRT aN 107 Sscillated Characteristics NS a RO NS 108 Chara teristiesN aN QL CA SN LA 112 MSCAN Wake up Pulse Characteristics 113 SPI Master Mode Timing Characteristics 116 SPI Slave Mode Timing Characteristics 118 Expanded Bus Timing 121 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Derivative Differences and Document References Derivative Differences Table 0 1 shows the availabi
55. F COF 004F TFLG2 Ko TOF 0050 TCO hi Bit 15 14 13 12 11 10 9 Bit 8 0051 TCO lo AN Bit 7 6 5 4 3 2 1 Bit 0 0052 TC1 hi bic Bit 15 14 13 12 11 10 9 Bit 8 0053 TC1 lo Bit 7 6 5 4 3 2 1 Bit 0 0054 TC2 hi a Bit 15 14 13 12 11 10 9 Bit 8 0055 TC2 lo Wi Bit 7 6 5 4 3 2 1 Bit 0 0056 TC3 hi Bit 15 14 13 12 11 10 9 Bit 8 0057 TC3 lo ne Bit 7 6 5 4 3 2 1 Bit 0 0058 TCA hi iis Bit 15 14 13 12 11 10 9 Bit 8 0059 lo Aan Bit 7 6 5 4 3 2 1 Bit 0 005A TC5 hi SG Bit 15 14 13 12 11 10 9 Bit 8 005B TC5 lo we Bit 7 6 5 4 3 2 1 Bit 0 005C TC6 hi ere Bit 15 14 13 12 11 10 9 Bit 8 005D TC6 lo un Bit 7 6 5 4 3 2 1 Bit 0 005E TC7 hi inis Bit 15 14 13 12 11 10 9 Bit 8 005F TC7 lo d Bit 7 6 5 4 3 2 1 Bit 0 0060 PACTL a PAMOD PEDGE CLKO PAOVI 0061 PAFLG ite 9 0 PAOVF 0062 hi e Bit 7 6 5 4 3 2 1 Bit 0 34 M MOTOROLA 0040 007F Address 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 007A 007B M MOTOROLA Name PACNE lo PACN1 hi PACNO lo MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG PA2H PA1H PAOH hi TCOH hi TCOH lo hi
56. H 10 0 0 SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFRO D7 D6 D5 D4 D3 D2 D1 DO 2 RXPOL BO3 BO2 BO1 BOO 0 R5 R4 R3 R2 R1 RO 0 0 0 DIE 0 0 0 0 0 0 0 0 0 0 0 IDLE Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Flash Control Register fts64k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIVO KEYEN 6 NV5 NV4 NV3 NV2 SEC1 SECO 0 0 0 0 0 0 0 0 CBEIE CCIE KEYACC 0 FPOPEN NV6 FPHDIS FPHS1 FPHSO FPLDIS FPLS1 FPLSO cBEIF CCF pvioL accerrL BLANK 0 0 CMDB6 CMDB5 CMDB2 0 CMDBO 0 0 0 0 0 0 0 0 Biti4 Bit14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 41 MC9S12DJ64 Device User Guide V01 20 0100 010F Flash Control Register fts64k Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 010A 9801 15 14 13 12 11 10 9 Bit 8 Write 50108 FDATALO 889 gi 6 5 4 3 2 1 Bit 0 Write 010C Read 0 0 0 0 0 0 0 0 010F Write 0110 011B EEPROM Control Register eets1k Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0110 ECLKDIV c EDIVLD PRpiv8 EDIV5 EDIV4 EDIV3 EDIV2 EDIVi EDIVO Read 0 0 0 0 0 0 0 0 0111 Reserved Write Read 0 0 0 0 0 0 0 0 0112 Reserved Write 0113
57. H5 PH5 134 KWH4 PH4 135 XCLKS NOACC PE7 136 0 137 Figure 2 1 52 MODN IPIPEO PES 138 WA M s ee o TRU Y T ECLK PE4 39 96 3 PS7 SS0 99 PJ6 KWJ6 SDA RXCANO 95 86 5 98 3 PJ7 KWJ7 SCL TXCANO 97 94 PS5 MOSIO 93 PS4 MISOO 92 3 PS3 TXD1 91 1 PS2 RXD1 90 I PS1 TXDO 89 2 PSO RXDO VRH VDDA PAD15 AN15 ETRIG1 PADO7 ANO7 ETRIGO PAD14 AN14 PADO6 AN06 PAD13 AN13 PAD05 AN05 PAD12 AN12 PAD04 AN04 PAD11 AN11 PAD03 AN03 PAD10 AN10 PAD02 AN02 PAD09 AN09 PADO1 ANO1 8 8 PADOO ANOO VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PAS ADDR13 DATA13 PA4 ADDR12 DATA12 PAS ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDR8 DATA8 MC9S12DJ64 112LQFP CM CO LO OO WO cO ME E E LO LO LO LO LO LO LO UU UU UU UU UU UU CC CC 2 8 gt 7 co rri ee zzzzpt sx x ox ox 5 Signals shown Bold are available on the 80 Pin Package Pin Assignments 112 pin LOFP for MC9S12DJ64 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 PJ7 KWJ7 SCL TXCANO VREGEN PS3 TXD1 PS2 RXD1 PS1 TXDO PSO RXDO VSSA PJ6 KWJ6 SDA RXCANO VRL PMO RXCANO RXB PM1 TXCANO TXB PM2 R
58. Interface SPIO 8 00E0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00F0 00FF Reserved 16 0100 010F Flash Control Register 16 0110 011B EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 50140 017F Freescale Scalable Can CANO 64 0180 023F Reserved 192 0240 027F Port Integration Module PIM 64 50280 03FF Reserved 384 0000 07FF Se 1k Array mapped twice in the 2048 0000 0FFF RAM array 4096 neoa Sector at start 16384 58000 BFFF Flash EEPROM Page Window 16384 25 MC9S12DJ64 Device User Guide V01 20 Table 1 1 Device Memory Map for MC9S12DJ64 Size Address Module Bytes Fixed Flash EEPROM array C000 FFFF incl 0 5K 1K 2K or 4K Protected Sector at end 16384 and 256 bytes of Vector Space at FF80 FFFF 26 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure 1 2 MC9S12DJ64 Memory Map out of Reset 0000 0400 0800 1000 Unimplemented 4000 8000 C000 FFOO 777 VECTORS FFFF EXPANDED NORMAL SINGLE CHIP M MOTOROLA SPECIAL SINGLE CHIP XX 4 2222 a gt REGISTERS Mappable to any 2K Boundary within the first 32K 1K Bytes EEPROM Mappable to any 2K Boundary 1K mapped two times in the 2K address space 4K Bytes RAM Mappable to any 4K Boundar
59. L min value from 0 7 VDDPLL to 0 75 VDDPLL item 14 VIL EXTAL max value from 0 3 VDDPLL to 0 25 VDDPLL Table Assigned Part ID Numbers added mask set number 0M89C Table NVM Reliability Characteristics added footnote concerning data retention 886 3 5753170 86 21 54151736 86 755 83298787 Http www 100y com tw M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Table of Contents ME 7 HH 886 3 5753170 Egg 86 21 54151736 86 755 83298787 Http www 100 com tw Section 1 Introduction 14 Overview Sie Rl N sus uses 19 1 2 Features ap k aa NN 4 2 19 13 Modes of Operation nannaa NL AN CNT COX 21 14 BlefKDiagrant CW lt AN AMY GO EN 22 15 Device Memory Map gt AO NN 25 1 5 1 Detailed Register 30 16 Part ID Assignments AN MM ON 49 Section 2 Signal Description 2 1 Device Pinotti Mr aM QD eere AN AY SR 51 2 2 Signal Properties 5 53 2 3 Detailed Signal Descriptions 56 2 3 1 EXTAL XTAL Oscillator Pins 56 2 32 RESET External Reset
60. LA 107 MC9S12DJ64 Device User Guide 01 20 A 5 1 5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After the CPU starts fetching the interrupt vector A 5 2 Oscillator The device features an internal Colpitts and Pierce oscillator The selection of Colpitts oscillator or Pierce oscillator external clock depends on the XCLKS signal which is sampled during reset Pierce oscillator external clock mode allows the input of a square wave Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power on STOP or oscillator fail tco our specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected The quality check also determines the minimum oscillator start up time tuposc The device also features a clock monitor A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fcMFA Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 Crystal oscillator range Colpitts 0 5 16 MHz 1b C Crystal oscillator range Pierce 0 5 40 MHz 2 Startup Current 100 4 Clock Quality check time out tcooUT 0 45 2 5
61. NG PER LS A ASME Y14 5M 1994 s 2 DIMENSIONS IN MILLIMETERS 3 ATUMS L M AND N TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH MENSION D DOES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 4 5 SEATING PLANE MN MAX 20 000 BSC 10 000 BSC 20 000 BSC 5 e e a gt gt Fed Fand Fad io o ex Jon S o gt oje SS e S oo S S alk a E 1 0 250 ole ho no eie ele 0 25 GAGE PLANE lt e o e olo o de o NICE gt d 9 dS B1 D K 0 500 P 5B R1 R2 LS LS LY 2 et 92 93 11 13 VIEW AB Figure B 1 112 pin LQFP mechanical dimensions case no 987 124 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 B 3 80 pin QFP package DETAIL A 020 OIDO DETAIL A D DETAIL C
62. O PS6 SCKO Port S I O of SPIO PS5 MOSIO Port S I O MOSI of SPIO PS4 500 PERS U Port S 1 0 MISO of SPIO PS3 TXD1 PPSS P Port S VO TXD of SCH PS2 RXD1 Port S I O RXD of SCI1 PS1 TXD0 Port S I O TXD of SCI0 PS0 RXD0 Port S I O RXD of SCI0 PT 7 0 IOC 7 0 Disabled Port T I O Timer channels NOTES 1 Refer to PEAR register description in HCS12 Multiplexed External Bus Interface MEBI Block Guide M MOTOROLA 55 MC9S12DJ64 Device User Guide V01 20 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins On reset all the device clocks are derived from the EXTAL input frequency XTAL is the crystal output 2 3 2 RESET External Reset Pin An active low bidirectional control signal it acts as an input to initialize the MCU to a known start up state and an output when an internal MCU function causes a reset 2 3 3 TEST Test Pin This input only pin is reserved for test NOTE The TEST pin must be tied to VSS in all applications 2 3 4 VREGEN Voltage Regulator Enable Pin This input only pin enables or disables the on chip voltage regulator 2 3 5 XFC PLL Loop Filter Pin PLL loop filter Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC R if MCU
63. OTOROLA User Guide End Sheet M MOTOROLA MC9S12DJ64 Device User Guide 01 20 127 MC9S12DJ64 Device User Guide 01 20 886 3 5753170 ESET 86 21 54151736 WEED 86 755 83298787 Http www 100y com tw FINAL PAGE OF 128 PAGES 128 M MOTOROLA
64. OUTPUT MSB OUT BIT6 1 X LSB OUT X 1 If configured as output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 5 SPI Master Timing CPHA 0 115 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 1 SS OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO MESE ww y 10 MASTER MSB OUT MASTER LSB OUT PORT DATA 1 If configured as output OUTPUT PORT DATA 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 6 SPI Master Timing CPHA 1 Table A 18 SPI Master Mode Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted 200pF on all outputs Num Rating MS Min Typ Max Unit P Operating Frequency fpus ERUIT Enable Lead Time tlead lsck Enable Lag Time Data Setup Time Inputs Data Hold Time Inputs Data Valid after SCK Edge Data Hold Time Outputs Rise Time Inputs and Outputs Fall Time Inputs and Outputs NOTES 1 The numbers 7 8 in the column labeled Num are missing This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A 19 116 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 7 2 Slave Mode Figure A 7 and Figure A 8 illustrate the slave mode timing Timing values are shown in Tabl
65. P4 PPSP3 PPSP2 PPSP1 PPsso Read 025E PIEP6 PIEP4 PIEP2 REPI PIEPO Read 025F PIFP Wrte PIFPS PIFP4 PIFP3 PIFP2 PIFP1 PIFPO Read 0260 PTH Wrte PTH6 PTHS PTH4 PTH2 PTHO ses SN Read PTIH7 PTIHG PTIHS PTIH2 PTIHT PTIHO Write 0262 DDRH wee DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRHO 47 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 0240 027F PIM Port Integration Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0263 RDRH D RDRH7 RDRH6 RDRH5 RDRH3 RDRH2 0264 PERH PERH7 PERH6 PERH5 PERH2 0265 PPSH N PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 1 PPSHO 0266 PIEH N PIEH7 PIEH6 5 PIEH2 0267 PIFH NOn PIFH7 PIFH6 PIFH5 PIFH4 PIFH2 PIFH1 PIFHO 0268 PTJ PTJ7 PTJ6 0 9 9 Q PTJ1 PTJO eu Read PT 0 0 0 0 PTIJ PTIJO Write 026A DDRJ AN DDRJ7 DDRJ7 9 0 9 DDRJ1 DDRJO 026B RDRJ dics RDRJ7 RDRJ6 0 0 Q RDRJ1 RDRJ0 026C PERJ PERJ7 PERJ6 O 0 p Q PERJO 026D PPSJ a PPSJ
66. Pierce mode only PLL loop filter res Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 Central point of the ground star should be the VSSR pin Use low ohmic low inductance connections between VSS1 VSS2 and VSSR VSSPLL must be directly connected to VSSR Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and QI as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins M MOTOROLA 81 MC9S12DJ64 Device User Guide V01 20 Figure 22 1 Recommended PCB Layout 112LQFP Colpitts Oscillator 82 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure 22 2 Recommended Layout for 80QFP Colpitts Oscillator M MOTOROLA 83 MC9S12DJ64 Device User Guide 01 20 Figure 22 3 Recommended Layout for 112LQFP Pierce Oscillator 84 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure 22 4 Recommended PCB Layout for 80QFP Pierce Oscillator M MOTOROLA 85 MC9S12DJ64 Device User Guide V01 20 86 44
67. Pulse Width Modulator PWM Block Description Consult the PWM 8B8C Block User Guide for information about the Pulse Width Modulator module When the 8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode Section 16 Flash EEPROM 64K Block Description M MOTOROLA 79 MC9S12DJ64 Device User Guide V01 20 Consult the FTS64K Block User Guide for information about the flash module The S12 LRAE is a generic Load RAM and Execute LRAE program which will be programmed into the flash memory of this device during manufacture This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB Use of the LRAE program is at the discretion of the end user and if not required it must simply be erased prior to flash programming For more details of the 512 LRAE and its implementation please see the 512 LREA Application Note AN2546 D It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash Exact details of the changeover ie blank to programmed for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device Please contact Freescale SPS Sales if you have any additional questions Section 17 EEPROM 1K Block Description Consult the EETS1K Block User Guide for
68. RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS PERS7 PERS6 55 PERS4 PERS3 PERS2 PERS PERSO 024D PPSS S d PPSS7 PPSS6 PPSS5 554 PPSS3 552 ppss 550 024E WOMS NOn WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMSO Read 0 0 0 0 0 0 0 0 024F Reserved Write 0250 PTM 7 6 PTM5 4 PTM3 PTM2 1 de prim Read PTIM7 6 5 PTIM2 PTIMO Write 0252 DDRM ics DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRMO 0253 RDRM RDRM7 RDRM6 RDRM5 RDRM4 RDRM2 RDRM1 RDRMO 0254 PERM ne PERM7 PERM6 PERM5 PERM2 PERMO 0255 PPSM iin PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSMO 0256 WOMM ve WOMM7 WOMM6 WOMMS WOMM4 WOMM3 WOMM2 WOMM1 WOMMO 0257 MODRR Me 9 0 0 _lyonrr4 2 O 1 MODRRO Read 0258 PTP PIRE Press PTPS PTP2S L ont Read PTIP7 6 PTIPT PTIPO Write 025A DDRP ans DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP we RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRPO 025C PERP era PERP7 PERP6 5 PERP4 PERP3 PERP2 PERPO 025D PPSP un ppsp7 PPSP6 PPSP5 PPS
69. Read Write Read Write Read Write MC9S12DJ64 Device User Guide V01 20 ATD1 Analog to Digital Converter 10 Bit 8 Channel Bit 7 0 0 ADPU SRES8 DJM SCF CCF7 Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit 6 0 AFFC S8C SMP1 DSGN 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 AWAI S4C SMPO SCAN ETORF 13 13 13 13 13 Bit 4 0 0 ETRIGLE S2C PRS4 MULT FIFOR 0 12 12 12 12 12 Bit 3 0 0 ETRIGP S1C PRS3 0 0 11 11 11 11 11 Bit 2 0 ETRIG FIFO PRS2 CC CC2 10 10 10 10 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 ASCIF Bit 0 FRZO PRSO CA CCO SC Bit 0 0 Bit8 Bit8 Bit8 Bit8 Bit8 43 MC9S12DJ64 Device User Guide 01 20 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 8880 Bit Bit6 0 0 0 0 0 0 Write sot ne Bitis 14 13 12 11 10 9 Bits Write 013B ATD1DR5L Read Bit7 Bit6 0 0 0 0 0 0 Write gorse Bitia 14 13 12 11 10 9 Bit8 Write 0
70. S 5 Clock Monitor Failure Assert Frequency CMFA 50 100 200 KHz 6 External square wave input frequency fExT 0 50 MHz 5 RANG External square wave pulse width low tExTL 9 5 ns 8 External square wave pulse width high 9 5 ns 9 External square wave rise time 1 ns 10 External square wave fall time 1 ns 11 0 Input Capacitance EXTAL XTAL pins CiN 12 NDS Bias in Colpitts Configuration on 1 1 V 13 EXTAL Pin Input High Voltage Vin extar 0 75 V T EXTAL Pin Input High Voltage VIHEXTAL 0 3 V ia P ere mn mat vote e _ Von en mouttonotaget Ven Vooru 03 15 EXTAL Pin Input Hysteresis VHYS EXTAL 250 mV 108 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 NOTES 1 Depending on the crystal a damping series resistor might be necessary 2 fos 4MHz C 22pF 3 Maximum value is for extreme cases using high Q low frequency crystals 4 Only valid if Pierce oscillator external clock mode is selected A 5 3 Phase Locked Loop The oscillator provides the reference clock for the PLL PLL s Voltage Controlled Oscillator VCO is also the system clock source in self clock mode A 5 3 1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics VDDPLL R Phase VCO fosc 1 fret refdv 1 Detector Loop
71. SR5 TSR4 TSRS TSR2 TSRI TSRO Write 0180 023F Reserved Address u 806 Reserved 0 0 LAS C 023F 0240 027F PIM Port Integration Module Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0240 PTT Ne PTT7 PTT6 PTT5 4 PTT PTTO MS Read PTIT7 6 5 PTIT4 PTIT3 PTIT2 Pritt PTITO Write 0242 DDRT VA DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRTO 0243 RDRT i RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRTO 0244 PERT MN PERT7 PERT6 PERTS PERT4 PERT3 PERT2 PERTO 0245 PPST be PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 1 PPSTO Read 0 0 0 0 0 0 0 0 0246 Read 0 0 0 0 0 0 0 0 0247 Reserved 0248 PTS7 PTS6 PTS5 PTS4 PTS3 52 1 PTso 0248 AM PTIS7 PTIS6 5 PTIS4 PTIS3 PTIS2 51 PTISO 46 M MOTOROLA 0240 027F MC9S12DJ64 Device User Guide 01 20 PIM Port Integration Module Address Name Bt7 Bit6 Bt5 Bit4 Bits Bit2 Biti Bit 0 024A DDRS D DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS RDRS7
72. TAL RESET VDDR External Reset TEST Test Input VREGEN Voltage Regulator Enable Input XFC PLL Loop Filter BKGD TAGHI MODC Debug Tag High Mode Port AD Input Analog Input AN7 of PAD15 AN15 ETRIG1 ATD1 External Trigger Input of ATD1 Port AD Inputs Analog Inputs PAD 14 08 14 08 gt AN 6 0 DATI 9 Port AD Input Analog Input AN7 of ANSE PISO ATDO Exil Sk of ATDO Port AD Inputs Analog Inputs AN 6 0 PAD 06 00 AN 06 00 A ROM Do p 9 6 0 PA 7 0 DAAN 2a a FE Port A I O Multiplexed Address Data ADDRI 7 0 is PB 7 0 DATA 7 0 Port Multiplexed Address Data Mode PE7 NOACC XCLKS depen Port E I O Access Clock Select dant PE6 IPIPE1 MODB While RESET pin is Port E O Pipe Status Mode Input IPIPEO MODA nn Port E I O Pipe Status Mode Input 4 ECLK Port E I O Bus Clock Output PE3 LSTRB TAGLO Port E I O Byte Strobe Tag Low PE2 R W Port E R W expanded modes PE1 IRQ Port E Input Maskable Interrupt PEO XIRQ Port E Input Non Maskable Interrupt PH7 KWH7 Port H I O Interrupt PH6 KWH6 Port H I O Interrupt PH5 KWH5 Port H I O Interrupt PHA KWH4 PERH Port H Interrupt Disabled PH3 KWH3 PPSH Port H Interrupt PH2 KWH2 Port H I O Interrupt PH1 KWH1 Port H I O Interrupt PH0 KWH0 Port H Interrupt 54 M MOTOROLA MC9S12DJ64 Device User Guide
73. XCANO MISOO PM3 TXCANO SSO PM4 RXCANO MOSIO PM5 TXCANO SCKO WO a a Q Q aa zz lt lt w lO aa PP7 KWP7 PWM7 VDDX VSSX PWM3 KWP3 PP3 1 11 VRH PWM2 KWP2 PP2 2 2 VDDA PWM1 KWP1 PP1 23 PADO7 ANO7 ETRIGO PWMO KWPO PPO C 4 PADO6 ANO6 IOCO PTO 5 PADO5 AN05 IOC1 PTI 16 PADO4 ANO4 IOC2 PT2 E17 PADO3 ANO3 18 PADO2 ANO2 VDD1 PADO ANO1 VSS1 MC9S12DJ64 PADOO ANOO IOC4 PT4 80 QFP VSS2 5 VDD2 IOC6 PT6 PA7 ADDR15 DATA15 IOC7 PT7 PAG ADDR14 DATA14 MODC TAGHI BKGD PAS ADDR13 DATA13 ADDRO DATAO PBO PA4 ADDR12 DATA12 ADDR1 DATA1 PB1 PA3 ADDR11 DATA11 ADDR2 DATA2 PB2 PA2 ADDR10 DATA10 ADDR3IDATAS PB3 PA1 ADDR9 DATA9 ADDR4 DATA4 PB4 PAO ADDR8 DATAB a BERERTEBENSRSRERERER g T gt Z D 555253 299592 2 Figure 2 2 Pin Assignments 80 QFP for MC9S12DJ64 and 9512032 2 2 Signal Properties Summary Table 2 1 summarizes the pin functionality Signals shown in bold are not available in the 80 pin package M MOTOROLA 53 MC9S12DJ64 Device User Guide V01 20 Table 2 1 Signal Properties Internal Pull Pin Name Pin Name Pin Name Pin Name Powered Resistor Description Function1 Function2 Function3 Function4 by Reset State EXTAL VDDPLL Oscillator Pins X
74. alues include the quantization error which is inherently 1 2 count for any A D converter Lower Unit 1 2 0 For the following definitions see also Figure 1 Differential Non Linearity DNL is defined as the difference between two adjacent switching steps DNL i 1 1LSB The Integral Non Linearity INL is defined as the sum of all DNLs n V V _ n on INL n L DNL s N 99 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 f 886 3 5753170 HER 86 21 54151736 ERED 86 755 83298787 DNL Http www 100y com tw 10 Bit Absolute Error Boundary SAS SEES 8 Bit Absolute Error Boundary 7 S3FE N 7 3FD 7 7 SEC an Nw gt SY 7 3FB 7 3FA jF b y 3F9 7 FE 3F8 3F7 3F6 7 5385 4 3F4 7 FD 1on 3F3 7 9r 7 deal Transfer Curve 2 mi 2 8 ET if 7 INIO Bit Transfer Curve 8 Bit Resolut N 10 Bit Resolution 1 N N N N N 8 Bit Transfer Curve N T N 2775777 7 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin 4 un D Bk 27 w Un mV Figure A 1 ATD Accuracy Definitions NOTE Figure A 1 shows only definitions for specification values r
75. an be programmed consecutively by keeping the command pipeline filled The time to program a consecutive word can be calculated as 1 1 4 3 8 09 Je t fbus The time to program a whole row is L swpgm 31 Ipwpgm Row programming is more than 2 times faster than single word programming A 3 1 3 Sector Erase Erasing a 512 byte Flash sector or a4 byte EEPROM sector takes M MOTOROLA 101 MC9S12DJ64 Device User Guide 01 20 1 tara 4000 g The setup time can be ignored for this operation A 3 1 4 Mass Erase Erasing a NVM block takes 1 t 20000 CS INVMOP The setup time can be ignored for this operation A 3 1 5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per word to verify plus a setup of the command teheck location 10 Table 11 Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 D External Oscillator Clock 05 50 MHz 2 D Bus frequency for Programming or Erase Operations Wu 1 MHz 3 D Operating Frequency fNvMoP 150 200 kHz 4 P Single Word Programming Time tswpgm 46 74 53 HS 5 D Flash Burst Programming consecutive word towpgm 20 4 313 us 6 D Flash
76. ate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 0 output 2 3 50 PS7 550 Port S I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 51 PS6 SCKO Port S I O Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 52 PS5 MOSIO Port I O Pin 5 PS5 is a general purpose input or output pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 53 PS4 500 Port S I O Pin 4 PS4 is a general purpose input or output pin It can be configured as master input during master mode or slave output pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 54 PS3 TXD1 Port S I O Pin PS3 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 1 SCIL M MOTOROLA 63 MC9S12DJ64 Device User Guide 01 20 2 3 55 PS2 RXD1 Port S I O Pin 2 PS2 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 1 SCI1 2 3 56 PS1 TXD0 Port S I O Pin 1 PS1 is a general purpose input or output pin It
77. ble Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations FFFC FFFD FFFA FFFB Clock Monitor fail reset COP failure reset Vector Address Interrupt Source ar Local Enable uns FFFE FFFF Reset None None PLLCTL CME SCME FFF9 Unimplemented instruction trap None COP rate select FFF0 FFF1 FFEE FFEF Real Time Interrupt Enhanced Capture Timer channel 0 SFFF SW FFF4 FFF5 XIRQ X Bit None _ FFF2 FFF3 IRQ I Bit IRQCR IRQEN F2 CRGINT RTIE FO TIE COl EE FFEC FFED Enhanced Capture Timer channel 1 I Bit I Bit TIE C11 EC FFDE FFDF FFDC FFDD Enhanced Capture Timer overflow Pulse accumulator A overflow FFEA FFEB Enhanced Capture Timer channel 2 FFE8 FFE9 Enhanced Capture Timer channel 3 I Bit TIE E8 FFE6 FFE7 Enhanced Capture Timer channel 4 I Bit TIE CAI E6 FFE4 FFE5 Enhanced Capture Timer channel 5 TIE C51 E4 FFE2 FFE3 Enhanced Capture Timer channel 6 I Bit TIE C61 E2 FFE1 Enhanced Capture Timer channel 7 I Bit TIE C71 EO TSRC2 TOI DE DC PACTL PAOVI FFDA FFDB Pulse accumulator input edge I Bit I Bit PACTL PAI DA SPICR1 SPIE SPTIE D8 FFD8 FFD9 SPIO SCICR2 SFFD6 SERBU 010 TIE TCIE RIE ILIE SCICR2 SFFD4 SEEQD
78. c tap tpsg KD TT mama Non multiplexed address delay time Non muxed address valid to E rise PWg NAD Non multiplexed address hold time Chip select delay time Chip select access time teye tesp tosr Chip select hold time Read write hold time Low strobe delay time Low strobe valid time to E rise PW_ t sp Low strobe hold time D valid time to E rise PWg tNov ns M MOTOROLA 121 MC9S12DJ64 Device User Guide 01 20 Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted 50pF Rating Symbol Min Typ Max Unit IPIPO 1 0 valid time to E rise IPIPO 1 0 delay time PWey tp1v IPIPO 1 0 valid time to E fall NOTES 1 Affected by clock stretch add N x t where N 0 1 2 or 3 depending on the number of clock stretches 122 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Appendix B Package Information B 1 General This section provides the physical dimensions of MC9S12DJ64 and MC9S12D32 packages M MOTOROLA 123 MC9S12DJ64 Device User Guide V01 20 B 2 112 pin LQFP package spon mes TR X L MORN im F D 10 13 IT SECTION J1 J1 A1 ROTATED 90 COUNTERCLOCKWISE x s1 NOTES 1 DIMENSIONING AND TOLERANCI
79. ce User Guide 01 20 Table A 5 Thermal Package Characteristics Num Rating ND Min Typ Max Unit Thermal Resistance LQFP112 single sided C W Thermal Resistance LQFP112 double sided PCB C W with 2 internal planes 3 T Junction to Board LQFP112 4 Junction to Case LQFP112 11 5 Junction to Package Top LOFP112 2 6 Thermal Resistance QFP 80 single sided DR SOM GER NET 2 internal planes T Junction to Board QFP80 9CAN 9 T Junction to Case QFP80 _ gt 14 C W 10 Junction to Package QFP80 Wor _ z 3 C W NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board according to EIA JEDEC Standard 51 3 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 VO Characteristics This section describes the characteristics of all 5V I O pins All parameters are not always applicable e g not all pins feature pull up down resistances M MOTOROLA 93 MC9S12DJ64 Device User Guide V01 20 Table A 6 5V Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 P Input High Voltage 0 65 Vpps Vpps 0 3 V 2 Input Low Voltage VL Voss 0 3 0 35 Vpps V 3 Input Hysteresis Input Leakage Current pins in high impedance input 4 mode Vin Vops or V i SS5
80. cteristics Updated parameters K and f Figure Basic PLL functional diagram Inserted XFC pin in diagram Enhanced section XFC Component Selection Added to Sections ATD ECT and PWM freeze mode active BDM mode Added 1L86D to Table Assigned Part ID numbers Corrected MEMSIZ1 value in Table Memory size registers Subsection Device Memory Map Removed Flash mapping from 0000 to 3FFF Table Signal Properties Added column Internal Pull Resistor Preface Table Document References Changed to full naming for each block Table Interrupt Vector Locations Column Local Enable Corrected several register and bit names Figure Recommended PCB Layout for 80QFP Corrected VREGEN pin position Thermal values for junction to board and package BGND pin pull up Part Order Information Global Register Table Chip Configuration Summary Modified mode of Operations chapter Section Printed Circuit Board Layout Proposals added Pierce Oscillator examples for 112LQFP and 80QFP 7 4 886 3 5753170 Wi JJ H i 86 21 54151736 MC9S12DJ64 Device User Guide 01 20 Wi 0910 86 755 83298787 Http www 100y com tw Version Number Revision Date Effective Date Author Description of Changes NVM electricals updated Subsection Detailed Register Map Address corrections Preface Table Document references added OSC User Guide New section Oscillator OSC Block Description 25 S
81. d to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1 pins Refer to the HCS12 Multiplexed External Bus Interface MEBI Block Guide for mode dependent pin configuration of port A B E and K out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports 74 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 NOTE For devices assembled in 80 pin QFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset M MOTOROLA 75 MC9S12DJ64 Device User Guide V01 20 76 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 6 HCS12 Core Block Description 6 1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU 6 1 1 Device specific information When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods So 1 cycle is equivalent to Bus Clock period 6 2 HCS12 Module Mapping Control MMC Block Description Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module 6 2 1 Device specific information NITEE Reset state 01 Bits 1
82. e A 19 SS INPUT SCK 0 INPUT SCK CPOL 1 INPUT N gt 7 S es MSB OUT DEN SLAVE LSB OUT INPUT MSB IN TEN LSB IN I Figure A 7 SPI Slave Timing CPHA 0 SS INPUT N 0 gt 3 2 2 gt a 1 SCK CPOL 0 INPUT SCK 4 1 gt lt 12 CPOL 1 INPUT O 00 gt 8 oul B ES fwd ENIM 2 7 KG MOSI Figure A 8 SPI Slave Timing CPHA 1 M MOTOROLA 117 MC9S12DJ64 Device User Guide V01 20 Table A 19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted CLOAD 200pF on all outputs e im Sim Mm BEI fees Se 1 Period tsck 1 fop 4 2048 tbus 2 Enable Lead Time 1 teyc 3 Enable Lag Time eo Data Setup Time Inputs Data Hold Time Inputs EAD III Li a e Slave MISO Disable Time ldis lcyc Data Valid after SCK Edge ty 25 ns 10 Data Hold Time Outputs tho ns D Rise Time Inputs and Outputs t 25 ns 12 D Time Inputs and Outputs t 25 ns 118 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 8 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure A 9 with the ac
83. ect pin SS of the Serial Peripheral Interface 0 SPIO 2 3 39 2 RXCANO 500 Port I O Pin 2 PM2 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the master input during master mode or slave output pin during slave mode MISO for the Serial Peripheral Interface 0 SPIO 2 3 40 PM1 TXCANO TXB Port I O Pin 1 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the transmit pin TXB of the BDLC 2 3 41 RXCANO RXB Port M I O Pin 0 PMO is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the receive pin RXB of the BDLC 2 3 42 PP7 KWP7 PWM7 Port P I O Pin 7 PP7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 7 output 2 3 43 PP6 KWP6 PWM6 Port P I O Pin 6 PP6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel
84. ee VDDPLL VDDPLL Figure 2 3 PLL Loop Filter Connections 2 3 6 BKGD TAGHI MODC Background Debug Tag High and Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the 56 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 instruction queue It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET This pin has a permanently enabled pull up device 2 3 7 PAD15 15 ETRIG1 Port AD Input Pin of ATD1 15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1 It can act as an external trigger input for the ATDI 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins ATD1 PAD14 PADOS are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDI 2 3 9 07 ETRIGO Port AD Input Pin of PADO is a general purpose input pin and analog input ANO of the analog to digital converter ATDO It can act as an external trigger input for the ATDO 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO PADO6 PADOO are general purpose input pins and analog inputs AN 6 0 of the analog to digi
85. efer to Table A 10 100 M MOTOROLA MC9S12DJ64 Device User Guide V01 20 A 3 NVM Flash and EEPROM NOTE Unless otherwise noted the abbreviation NVM Non Volatile Memory is used for both Flash and EEPROM A 3 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase operations The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as The minimum program and erase times shown in Table A 11 are calculated for maximum fyyMmop and maximum fp The maximum times are calculated for minimum fyymop and a fy of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fyvmop and can be calculated according to the following formula t toy 25 SWpam A 3 1 2 Row Programming This applies only to the Flash where up to 32 words in a row c
86. egulator VDDI 551 VDD2 and VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL 551 and VSS2 are internally connected by metal M MOTOROLA 87 MC9S12DJ64 Device User Guide V01 20 VDDA VDDX VDDR as well as VSSA VSSX VSSR are connected by anti parallel diodes for ESD protection NOTE Inthe following context VDDS is used for either VDDA VDDR and VDDX VSS5 is used for either VSSA VSSR and VSSX unless otherwise noted 205 denotes the sum of the currents flowing into VDDX and pins VDD is used for VDDI VDD2 and VDDPLL VSS is used for VSS1 VSS2 VSSPLL IDD is used for the sum of the currents flowing into VDDI and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V VO pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the functionality may be disabled E g for the analog inputs the output drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This group is made up by the VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production testing only A 1 3 5 VREGEN This pin is used to enable
87. ept 2002 Electrical Characteristics gt Section General removed preliminary disclaimer gt Table Supply Current Characteristics changed max Run IDD from 65mA to 50mA changes max Wait IDD from 40mA to 30mA changed max Stop IDD from 50uA to 100uA Section HCS12 Core Block Description mentioned alternate clock of BDM to be equivalent to oscillator clock Table 5V 1 0 Characteristics Corrected Input Leakage Current to 1 uA Section Part ID assignment Located on start of next page for better readability 10 Oct 2002 Added MC9S12A64 derivative to cover sheet and Derivative Differences Table Corrected in footnote of Table PLL Characteristics fosc 4MHz Renamed Preface section to Derivative Differences and Document references Added details for derivatives missing CANO and or BDLC Table ESD and Latch up Test Conditions changed pulse numbers from 3 to 1 Table ESD and Latch Up Protection Characteristics changed parameter classification from C to T Table 5V Characteristics removed foot note from Input Leakage Current Table Supply Current Characteristics updated Stop and Pseudo Stop currents Subsection Detailed Register Map Corrected several entries Subsection Unsecuring the Microcontroller Added more details Table Operating Conditions improved footnote 1 wording applied footnote 1 to PLL Supply Voltage Tables SPI Master Slave Mode Timing Characteristics Correc
88. evice User Guide V01 20 24 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 1 5 Device Memory Map Table 1 1 and Figure 1 2 show the device memory map of the MC9S12DJ64 after reset The IK EEPROM is mapped twice in a 2K address space Note that after reset the bottom 1k of the EEPROM 0000 03FF are hidden by the register space and the 0400 07FF is hidden by the RAM M MOTOROLA Table 1 1 Device Memory Map for MC9S12DJ64 Address Module Bytes 0000 000F HCS12 Multiplexed External Bus Interface 16 0010 0014 HCS12 Module Mapping Control 5 0015 0016 HCS12 Interrupt 2 0017 0019 Reserved 3 001A 001B Device ID register PARTID 2 001C 001D HCS12 Module Mapping Control 2 001E HCS12 Multiplexed External Bus Interface 1 001F HCS12 Interrupt 1 0020 50027 Reserved 8 0028 002F HCS12 Breakpoint Module 8 0030 0031 HCS12 Module Mapping Control 2 0032 0033 HCS12 Multiplexed External Bus Interface 2 0034 003F Clock and Reset Generator PLL RTI COP 12 50040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels ATDO 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface O SCIO 8 0000 0007 Serial Communications Interface 0 SCI1 8 00D8 00DF Serial Peripheral
89. he ROMON bit For a complete list of modes refer to 4 2 Chip Configuration Summary 2 3 33 PK 5 0 XADDR 19 14 Port I O Pins 5 0 5 are general purpose input or output pins In MCU expanded modes of operation these pins provide the expanded address XADDR 19 14 for the external bus 2 3 34 PM7 Port M I O Pin 7 PM7 is a general purpose input or output pin 2 3 35 PM6 Port M I O Pin 6 PM6 is a general purpose input or output pin 2 3 36 PM5 TXCANO 5 Port M I O Pin 5 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 37 PM4 RXCANO MOSIO Port M I O Pin 4 is a general purpose input or output pin It can be configured as the receive pin of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral Interface 0 SPIO M MOTOROLA 61 MC9S12DJ64 Device User Guide 01 20 2 3 38 TXCANO SSO Port M I O Pin PM3 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 CANO It can be configured as the slave sel
90. igured as outputs or their pull resistors must be enabled to avoid floating inputs Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input Port S 7 4 PS7 4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs PAD 15 8 ATD1 channels Out of reset the is disabled preventing current flows in the pins Do not modify the ATDI registers Document References The Device User Guide provides information about the MC9S 12DJ64 device made up of standard HCS 12 blocks and the HCS12 processor core This document is part of the customer documentation A complete set of device manuals also includes all the individual Block Guides of the implemented modules In a effort to reduce redundancy all module specific information is located only in the respective Block Guide If applicable special implementation details of the module are given in the block description sections of this document See Table 0 2 for names and versions of the referenced documents throughout the Device User Guide 16 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Table 0 2 Document References Port Integration Module 9DJ64 Block User Guide User Guide Mola Document Order Number HCS12 CPU Reference Manual 02 S12CPUV2 D HCS12 Module Mapping Control MMC Block Guide V04 S12MMCVA4 D HCS12 Multiplexed External Bus I
91. iltering Programmable rising or falling edge trigger Memory 64K Flash EEPROM 1K byte EEPROM M MOTOROLA 19 MC9S12DJ64 Device User Guide 01 20 4Kbyte RAM Two 8 channel Analog to Digital Converters 10 bit resolution External conversion trigger capability e bit per second CAN 2 0 A B software compatible module Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function Loop back for self test operation 4 886 3 5753170 EM 86 21 54151736 Enhanced Capture Timer E FREYI 86 755 83298787 16 bit main counter with 7 bit prescaler Http www 100y com tw 8 programmable input capture or output compare channels Four 8 bit or two 16 bit pulse accumulators 8PWM channels Programmable period and duty cycle 8 61 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Serial interfaces Two asynchronous Serial Communications Interfaces SCI Synchronous Serial Peripheral Interface SPI e Byte Data Link Controller BDLC SAEJI1850 Class B Data Communicati
92. ilure if after exposure to ESD pulses the device no longer meets the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Human Body Number of Pulse per pin positive 1 negative 1 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Machina Number of Pulse per pin positive 3 negative 3 Minimum input voltage limit 2 5 Latch up Maximum input voltage limit 7 5 Table A 3 ESD and Latch Up Protection Characteristics nie Rating Symbol Min Max Unit SE Human Body Model HBM VHBM 2000 V T Machine Model MM VMM 200 V T Charge Device Model CDM 500 V Latch up Current at Ta 125 C 4 T positive 100 mA negative 100 Latch up Current at TA 27 C 5 positive ILAT 200 mA negative 200 A 1 Operating Conditions This chapter describes the operating conditions of the device Unless otherwise noted those conditions apply to all the following data 90 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 NOTE Please refer to the temperature rating of the device C V M with regards to the ambient temperature T4 and the junction temperature
93. in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD PE6 PE5 PK7 ROMON MODB MODA ROMCTL Bit Mode Rescription Special Single Chip BDM allowed and ACTIVE BDM is 0 0 0 x 1 allowed in all other modes but a serial command is required to make BDM active 0 1 0 0 1 1 0 Emulation Expanded Narrow allowed 0 1 0 X 0 Special Test Expanded Wide BDM allowed 0 1 0 1 1 1 0 Emulation Expanded Wide BDM allowed 1 0 0 X 1 Normal Single Chip BDM allowed 0 0 1 0 1 1 1 Normal Expanded Narrow BDM allowed Peripheral BDM allowed but bus operations would cause 1 1 0 x 1 bus conflicts must not be used 0 0 1 1 1 1 1 Normal Expanded Wide BDM allowed For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description 1 Colpitts Oscillator selected M MOTOROLA 69 MC9S12DJ64 Device User Guide 01 20 Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description 0 Pierce Oscillator external clock selected Table 4 3 Voltage Regulator VREGEN VREGEN Description 1 Internal Voltage Regulator enabled Internal Voltage Regulator disabled VDD1 2 and VDDPLL must be supplied externally wi
94. ing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be given A very good estimate is to take the single chip currents and add the currents due to the external loads Table A 7 Supply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit Run supply currents Single Chip Internal regulator enabled Wait Supply current All modules enabled PLL on only RTI enabled 0 0 Pseudo Stop Current RTI and COP disabled 2 40 C 27 C 70 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C TOTOTOOTO Pseudo Stop Current RTI and COP enabled 2 Glo Stop Current 70 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C TOTOTOOTO M MOTOROLA 95 MC9S12DJ64 Device User Guide V01 20 NOTES 1 PLL off 2 At those low power dissipation levels be assumed 96 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 2 ATD Characteristics This section describes the characteristics of the analog to digital converter A 2 1 ATD Operating Characteristics The Table A 8 shows conditions under which the ATD operates The following constraints exist to obtai
95. instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low 2 3 16 4 Port I O Pin 4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3 17 LSTRB TAGLO Port E I O Pin PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus access and when instruction tagging is on TAGLO is used to tag the low half of the instruction word being read into the instruction queue 2 3 18 R W Port E I O Pin 2 PE2 is a general purpose input or output pin In MCU expanded modes of operations this pin drives the read write output signal for the external bus It indicates the direction of data on the external bus 2 3 19 PE1 IRQ Port E Input Pin 1 PE is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 20 PEO XIRQ Port E Input Pin 0 PEO is a general purpose input pin and the non maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 21 PH7 KWH7 Port H I O Pin 7 PH7 is a general
96. ion lALockl 0 1 5 1 HOT p Lock Detector transition from Tracking to Acquisition unt of mode 7 C PLLON Total Stabilization delay Auto Mode 2 tstab 0 5 ms 8 D Acquisition mode stabilization delay 2 tacq 0 3 ms 9 D PLLON Tracking mode stabilization delay 2 tal 0 2 ms m eer 11 Fitting parameter VCO loop frequency Charge pump current acquisition mode lich 38 5 Charge pump current tracking mode ien 3 5 Eee NN SUR SET LE 15 Jitter fit parameter 22 j2 NOTES 1 deviation from target frequency 2 fosc 4MHZ fgus 25MHz equivalent fvco 50MHz REFDV 03 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KQ 112 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 6 MSCAN Table A 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 P MSCAN Wake up dominant pulse filtered twup 2 us 2 MSCAN Wake up dominant pulse pass twup 5 us M MOTOROLA 113 MC9S12DJ64 Device User Guide V01 20 114 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 7 SPI A 7 1 Master Mode Figure A 5 and Figure A 6 illustrate the master mode timing Timing values are shown in Table A 18 551 OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI N
97. lator and Analog Supply Voltage 505 0 3 6 0 V 2 Digital Logic Supply Voltage 2 Voo 0 3 3 0 V 3 Supply Voltage 2 VDDPLL 0 3 3 0 V 4 Voltage difference VDDX to VDDR and VDDA 403 3 5 Voltage difference VSSX to VSSR and VSSA Avssx 0 3 V 6 Digital I O Input Voltage IE 7 Analog Reference 8 XFC EXTAL XTAL inputs 3 0 V 9 TEST input VTEST 10 0 V nacio ai otal p gt MENT a gt m 2 Ne 9 ma 13 Storage Temperature Range Re 65 155 C NOTES 1 Beyond absolute maximum ratings device might be damaged 2 The device contains an internal voltage regulator to generate the logic PLL supply out of the supply The absolute maximum ratings apply when the device is powered from an external source All digital pins are internally clamped to Vssx and Vppx and Vppg or Vssa and Vppa 4 Those pins are internally clamped to Vssp and Vpppi 5 This pin is clamped low to Vssp but not clamped high This pin must be tied low in applications M MOTOROLA 89 MC9S12DJ64 Device User Guide V01 20 A 1 6 ESD Protection and Latch up Immunity ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a fa
98. lity of peripheral modules on the various derivatives For details about the compatibility within the MC9S12D Family refer also to engineering bulletin EB386 Table 0 1 Derivative Differences Generic device se anue MC9S12D64 MC9S12A64 MC9S12D32 MC9S12A32 CANO J1850 BDLC 0 0 0 0 Packages 80QFP 112LQFP 80QFP 112LQFP 80QFP 80QFP 80QFP Mask Set L86D L86D L86D L86D L86D Temp Options M V G V C Package Codes Note PV FU An errata exists contact Sales PV FU An errata exists contact Sales FU An errata exists contact Sales An errata exists contact Sales An errata exists contact Sales office office office office office MC9S12 DJ64 C FU Temperature Options gt Package Option 40 C to 85 C 40 to 105 C sa Option 40 C to 125 C evice Title Pagkage Options Controller Family 80QFP By 112LOFP Figure 0 1 Order Partnumber Example The following items should be considered when using a derivative Registers Do not write or read CANO registers after reset address range 0140 017F if using a derivative without CANO see Table 0 1 Do not write or read BDLC registers after reset address range 00 8 00 if using a derivative without BDLC see Table 0 1 Interrupts the four CANO interrupt vectors SFFBO FFB7 according to your coding policies for unused interrupts if using a derivative witho
99. ly use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VREGEN 15 tied to ground NOTE No load allowed except for bypass capacitors 2 4 4 VDDA VSSA Power Supply Pins for ATDO ATD1 and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator and the two analog to digital converters It also provides the reference for the internal voltage regulator This allows the supply voltage to ATDO ATD1 and the reference voltage to be bypassed independently M MOTOROLA 65 MC9S12DJ64 Device User Guide V01 20 2 4 5 VRH VRL ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE No load allowed except for bypass capacitors 2 4 7 VREGEN On Chip Voltage Regulator Enable Enables the internal 5V to 2 5V voltage regulator If this pin is tied low VDD1 2 and VDDPLL must be supplied externally 66 M MOTOROLA MC9S12DJ64 Device User Guide
100. n full scale full range results VssA lt lt Vin lt Vppa This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit Reference Potential 1 D Low Vssa Vppa 2 V High Ven VppA 2 2 Differential Reference Voltage Vni Vn 4 50 5 00 5 25 V 3 ATD Clock Frequency ATDCLK 0 5 2 0 MHz ATD 10 Bit Conversion Period 4 D Clock Cycles 10 14 28 Cycles Conv Time at 2 0MHz ATD Clock fATDCLK TcoNv1 0 7 14 us ATD 8 Bit Conversion Period 5 D Clock Cycles Conv Time at 2 0MHz Clock farpcik 6 D Recovery Time VppA 5 0 Volts 7 Reference Supply current 2 blocks on 8 P Reference Supply current 1 ATD block on NOTES 1 Full accuracy is not guaranteed when differential voltage is less than 4 50V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks A 2 2 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influence on the accuracy of the ATD 2 2 1 Source Resistance Due to the i
101. n in Table A 4 unless otherwise noted Rating T POR release level T POR assert level 0 97 END ipu pir iium Startup from Reset 5 Interrupt pulse width IRQ edge sensitive mode 20 ns 6 Wait recovery startup time 14 5 1 1 The release level and the assert level are derived from Vpp Supply They are also valid if the device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after a time no valid oscillation is detected MCU will start using the internal self clock The fastest startup time possible is given by Nypose A 5 1 2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset A 5 1 4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system M MOTORO
102. nit HCS12 CPU 64K bytes of Flash EEPROM 4K bytes of RAM IK bytes of EEPROM two asynchronous serial communications interfaces SCT one serial peripheral interfaces SPD an 8 channel IC OC enhanced capture timer two 8 channel 10 bit analog to digital converters ADC an 8 channel pulse width modulator PWM a digital Byte Data Link Controller BDLC 29 discrete digital I O channels Port A Port B Port K and Port E 20 discrete digital I O lines with interrupt and wakeup capability a CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The MC9S12DJ64 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Features e HCS12 Core 16 bit HCS12 CPU i Upward compatible with M68HC11 instruction set ii Interrupt stacking and programmer s model identical to M68HC11 iii Instruction queue iv Enhanced indexed addressing Multiplexed External Bus Interface MMC Module Mapping Control INT Interrupt control Breakpoints BDM Background Debug Mode e CRG low current Colpitts or Pierce oscillator PLL reset clocks COP watchdog real time interrupt clock monitor e 8 bit and 4 bit ports with interrupt functionality Digital f
103. nput pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to the input The maximum source resistance Rg M MOTOROLA 97 MC9S12DJ64 Device User Guide 01 20 specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If device or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowed A 2 2 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage ILSB then the external filter capacitor gt 1024 Cins A 2 2 3 Current Injection There are two cases to consider 1 A current is injected into the channel being converted The channel being stressed has conversion values of 3FF FF 8 bit mode for analog inputs greater than and 000 for values less than unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the con
104. nterface MEBI Block Guide S12MEBIV3 D HCS12 Interrupt INT Block Guide S12INTV1 D HCS12 Background Debug Block Guide V04 S12BDMV4 D HCS12 Breakpoint Block Guide V01 S12BKPV1 D Clock and Reset Generator CRG Block User Guide V04 S12CRGV4 D Oscillator OSC Block User Guide V02 S120SCV2 D Enhanced Capture Timer 16 Bit 8 Channel ECT_16B8C Block User Guide S12ECT16B8CV1 D Analog to Digital Converter 10 Bit 8 Channel ATD_10B8C Block User Guide 02 S12ATD10B8CV2 D Inter IC Bus Block User Guide 02 S121ICV2 D Asynchronous Serial Interface SCI Block User Guide V02 S12SCIV2 D Serial Peripheral Interface SPI Block User Guide V02 S12SPIV2 D Pulse Width Modulator 8 Bit 8 Channel PWM_8B8C Block User Guide 01 S12PWM8B8CV1 D 64K Byte Flash FTS64K Block User Guide S12FTS64KV1 D 1K Byte EEPROM EETS1K Block User Guide S12EETS1KV1 D Byte Level Data Link Controller J1850 BDLC Block User Guide S12BDLCV1 D Freescale Scalable CAN MSCAN Block User Guida VO2 S12MSCANV2 D Voltage Regulator VREG Block User Guide 01 S12VREGV1 D S12PIM9DJ64V1 D M MOTOROLA N MC9S12DJ64 Device User Guide V01 20 18 44 MOTOROLA MC9S12DJ64 Device User Guide 01 20 Section 1 Introduction 1 1 Overview The MC9S12DJ64 microcontroller unit is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing u
105. ons Network Interface Compatible and ISO Compatible for Low Speed 125 Kbps Serial Data Communications in Automotive Applications Inter IC Bus Compatible with I2C Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies 12 Pin LQFP or 80 QFP package 20 M MOTOROLA 1 3 MC9S12DJ64 Device User Guide 01 20 I O lines with 5V input and drive capability 5V A D converter inputs Operation at 50MHZ equivalent to 25MHz Bus Speed Development support Single wire background debug mode On chip hardware breakpoints Modes of Operation User modes Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Freescale use only Special Peripheral Mode Freescale use only Low power modes Stop Mode Pseudo Stop Mode Wait Mode M MOTOROLA 21 MC9S12DJ64 Device User Guide 01 20 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DJ64 device 22 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure 1 1 MC9S12DJ64 Block Diagram 64K Byte Flash EEPROM 4K Byte RAM 1K Byte EEPROM Voltage Regulator Single wire Background Debug Module XFC VDDPLL Clock and
106. ress 00DO 00D1 00D2 00D3 00D4 M MOTOROLA Name SCI1BDH SCHBDL SCHCR2 SCI1SR1 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write PWM Pulse Width Modulator 8 Bit 8 Channel MC9S12DJ64 Device User Guide 01 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 PWMIE PWMLVL pwM7INL PWMTENA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCI0 Asynchronous Serial Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBRO LOOPS SCISWAI RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 9 2 TxDIR R8 bl 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 RO 7 6 5 4 T3 12 1 TO SCI1 Asynchronous Serial Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 5883 5882 SBR1 SBRO LOOPS SCISWAI RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK TDRE
107. sen TIE TCIE RIE ILIE FFD2 FFD3 ATDO ATDCTL2 ASCIE FFDO FFD1 ATD1 ATDCTL2 ASCIE DO PIEJ FFGF ons Bit PIEU7 PIEJ6 PIEJ1 PIEJO 26E FFCC FFCD Port H I Bit PIEH 7 0 CC M MOTOROLA 73 MC9S12DJ64 Device User Guide V01 20 FFCA FFCB FFC8 FFC9 Modulus Down Counter underflow Pulse Accumulator B Overflow I Bit MCCTL MCZI PBCTL PBOVI CA FFB6 FFB7 CANO wake up FFC6 FFC7 CRG PLL lock CRGINT LOCKIE FFC4 FFC5 CRG Self Clock Mode CRGINT SCMIE FFC2 FFC3 BDLC DLCBCR IE FFCO FFC1 Bus IBCR IBIE FFBE FFBF m Reserved Reserved FFBC FFBD FFBA FFBB EEPROM ECNFG CCIE CBEIE FFB8 FFB9 FLASH FCNFG CCIE CBEIE CANRIER WUPIE FFB4 FFB5 CANO errors CANRIER CSCIE OVRIE FFB2 FFB3 FFBO FFB1 CANO receive CANO transmit CANRIER RXFIE CANTIER TXEIE2 TXEIEO FFAE FFAF FFAC FFAD FFAA FFAB FFA8 FFA9 FFA6 FFA7 SFFA4 SFFAS FFA2 FFAO FFA1 SFFOE SFFOF FF9C FF9D FF9A FF9B 8 98 5 99 FF96 FF97 FF94 FF95 SFF92 FF93 FF90 FF91 FF8E FF8F Port P FF8C FF8D PWM Emergency Shutdown I Bit FF80 to FF8B Reserved Reserved PIEP PIEP7 0 PWMSDN PWMIE 8C Reserved 5 3 Effects of Reset When a reset occurs MCU registers and control bits are change
108. t7 6 5 4 3 2 1 Bit 0 00AF PWNS 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 0080 PWMCNM 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00B1 PWMONIS wrie O 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00B2 PWMCNT6 Write 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00B3 PWMCNT7 nd 0 0 0 0 0 0 0 Read 0084 PWMPERO Bit7 6 5 4 3 2 1 Bit 0 Write 0085 PwMPERi 198 gi 6 5 4 3 2 1 Bit 0 Write 0086 PWMPER2 1984 gi 6 5 4 3 2 1 Bit 0 Write 0087 PWMPER3 1984 gi 6 5 4 3 2 1 Bit 0 Write 50088 PWMPER4 1984 gi 6 5 4 3 2 1 Bit 0 Write 0089 PWMPERs 1984 gi 6 5 4 3 2 1 Bit 0 Write 00BA PWMPERe 1984 gi 6 5 4 3 2 1 Bit 0 Write 50088 PWMPER7 19324 pi 6 5 4 3 2 1 Bit 0 Write 5008 Pwuprvo 198 6 5 4 3 2 1 Bit 0 Write 80080 PWMDTvi 1984 6 5 4 3 2 1 Bit 0 Write 008E PWMDTY2 1984 pi 6 5 4 3 2 1 Bit 0 Write 00 198 6 5 4 3 2 1 Bit 0 Write 00c0 PWMDTY4 198 gi 6 5 4 3 2 1 Bit 0 Write 0001 PWMDTY5 1984 6 5 4 3 2 1 Bit 0 Write 38 M MOTOROLA 00A0 00C7 Address 00C2 00C3 00C4 00C5 00C6 00C7 Name PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved 00C8 00CF Address 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF Name SCIOBDH SCIOBDL SCIOCR1 SCIOCR2 SCIOSR1 SCIOSR2 SCIODRH SCIODRL 00D0 00D7 Add
109. tal converter ATDO 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 7 are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port I O Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 13 XCLKS Port E I O Pin 7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator If input is a logic high a Colpitts oscillator circuit 15 configured on EXTAL and XTAL Since this pin is an input with a pull up device during reset if the pin is left floating the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL M MOTOROLA 57 MC9S12DJ64 Device User Guide 01 20
110. ted Operating Frequency Appendix NVM Flash EEPROM Replaced burst programming by row programming Table Operating Conditions corrected minimum bus frequency to 0 25 2 Section Feature List ECT features changed to Four pulse accumulators M MOTOROLA Replaced references to HCS12 Core Guide by the individual HCS12 Block guides Table Signal Properties corrected pull resistor reset state for PE7 and PE4 PE2 Table Absolute Maximum Ratings corrected footnote on clamp of TEST pin Added cycle definition to CPU 12 Block Description Added register reset values to MMC and MEBI block descriptions Diagram Clock Connections Connect Bus Clock to HCS12 Core MC9S12DJ64 Device User Guide 01 20 Version Number V01 16 V01 18 Revision Date 24 Feb 2004 13 July 2004 Effective Date 24 Feb 2004 13 July 2004 Author Description of Changes Mentioned S12 bootloader in Flash section Section Document References corrected 512 CPU document reference Added 3L86D maskset with corresponding Part ID Table Oscillator Characteristics Added more details for EXTAL pin Added 4L86D maskset with corresponding Part ID Table MC9S12DJ64 Memory Map out of Reset corrected 1000 3fff memory in single chip modes to unimplemented Added MC9S12D32 MC9S12A32 Appendix Table Oscillator Characteristics changed item 13 VIH EXTA
111. th 2 5V 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows Protection of the contents of FLASH Protection of the contents of EEPROM Operation in single chip mode Operation from external memory with internal FLASH and EEPROM disabled The user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage of the secured part Everything will appear the same as if the part was not secured with the exception of
112. the on chip voltage regulator A 1 4 Current Injection Power supply must maintain regulation within operating Vpps or Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt Vpps is greater than Ipps the injection current may flow out of VDDS and could result in external power supply going out of regulation Ensure external VDD5 load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption 88 M MOTOROLA A 1 5 Absolute Maximum Ratings MC9S12DJ64 Device User Guide 01 20 Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either or Table A 1 Absolute Maximum Ratings Num Rating Symbol Min Max Unit 1 Regu
113. trol Register 16 50110 011B EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 0140 017F Freescale Scalable Can CANO 0180 023F Reserved 192 0240 027F Port Integration Module PIM 64 0280 03FF Reserved 384 0000 07FF ue 1k Array mapped twice in the 2048 0000 0FFF RAM array lower half 0000 07FF not usable 4096 Fass CEPA aay a ray 1504 8000 FFFF 32K Fixed Flash EEPROM array 32768 64 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Figure 1 3 MC9S12D32 Memory Map out of Reset 0000 0400 0800 1000 Unimplemented 4000 8000 C000 FFOO 777 VECTORS FFFF EXPANDED NORMAL SINGLE CHIP M MOTOROLA SPECIAL SINGLE CHIP XX 4 2222 a gt REGISTERS Mappable to any 2K Boundary within the first 32K 1K Bytes EEPROM Mappable to any 2K Boundary 1K mapped two times in the 2K address space 4K Bytes RAM lower half 0000 07FF not usable Mappable to any 4K Boundary 16K Fixed Flash Block 1 This is dependant on the state of the ROMHM bit 16K Fixed Flash Block 1 paging not usable 16K Fixed Flash Block 2 OO MIL X d if active 222 29 MC9S12DJ64 Device User Guide V01 20 1 5 1 Detailed Register Map
114. tual timing values shown on table Table 20 All major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs M MOTOROLA 119 MC9S12DJ64 Device User Guide V01 20 ECLK PE4 Addr Data read PA PB Addr Data write PA PB Non Multiplexed Addresses PK5 0 ECS PK7 RW PE2 Figure A 9 General External Bus Timing L886 3 5753170 86 21 54151736 E PREI 86 755 83298787 Http www 100 com tw 120 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Cj 50pF Num Rating Symbol Min Typ Max Unit P Frequency of operation E clock fo 0 25 0 MHz GT rue Pulse width E low 4 Pulse width E high 5 Address delay time 6 0 Address valid time to E rise PWEL tap 7 Muxed address hold time Hs Address hold to data valid efi 10 Read data setup time 11 Read data hold time 12 Write data delay time m sees ES 14 Write data setup time PWeH tppw ipsw 15 Address access time tcy
115. ut CANO see Table 0 1 Hill the interrupt vector SFFC2 FFC3 according to your coding policies for unused interrupts if using a derivative without BDLC see Table 0 1 M MOTOROLA 15 MC9S12DJ64 Device User Guide 01 20 Ports The CANO pin functionality TXCANO RXCANO is not available on port PJ7 PJ6 5 PM3 PM2 PMI and if using a derivative without CANO see Table 0 1 BDLC pin functionality TXB RXB is not available on port and PMO if using a derivative without BDLC see Table 0 1 Do not write MODRRI and MODRRO Bit of Module Routing Register 9DJ64 Block User Guide if using a derivative without CANO see Table 0 1 Pins not available in 80 pin QFP package PortH In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register at Base 0262 to FF or enabling the pull resistors by writing a FF to the pull enable register PERH at Base 0264 Port J 1 0 Port J pull up resistors are enabled out of reset on all four pins 7 6 and 1 0 Therefore care must be taken not to disable the pull enables on PJ 1 0 by clearing the bits PERJI and PERJO at Base 026C Port Port K pull up resistors are enabled out of reset i e Bit 7 PUKE 1 in the register PUCR at Base 000C Therefor care must be taken not to clear this bit Port M 7 6 PM7 6 must be conf
116. ven if such claim alleges that Freescale was negligent regarding the design or manufacture of the part M MOTOROLA 1 Revision History 4 886 3 5753170 86 21 54151736 HEF HL VEN 86 755 83298787 Http www 100y com tw Version Revision Effective una Number Date Date Author Description of Changes 16 NOV 19 NOV V01 00 2001 2001 Initial version based on MC9SDP256 2 09 Version In table 7 I O Characteristics of the electrical characteristics V01 01 18 FEB 18 FEB replaced tPULSE with tpign and tpval in lines Port Interrupt Input 2002 2002 Pulse filtered and Port Interrupt Input Pulse passed respectively Table Oscillator Characteristics removed Oscillator start up time from POR or STOP row Table 5V I O Characteristics Updated Partial Drive 2mA and Full Drive 10mA Table Operating Characteristics Distinguish 1 and 2 vo1 o2 SMAR 6MAR ATD blocks on 2002 2002 V01 05 30 July 2002 30 July 2002 Table Electrical Characteristics Update to 22 pF Table Operating Conditions Changed Vpp and to 2 35 V min Removed Document number except from Cover Sheet Updated Table Document References Table 5V 1 0 Characteristics Corrected Input Capacitance to 6pF Section Device Pinout 112 pin and 80 pin added in diagrams RXCANO to PJ6 and TXCANO to PJ7 Table PLL Chara
117. verted channel be calculated as Vggg K Rg Iy With being the sum of the currents injected into the two pins adjacent to the converted channel Table A 9 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 C input Source Resistance Rs 1 Total Input Capacitance 2 Non Sampling Sampling 3 Disruptive Analog Input Current 4 Coupling Ratio positive current injection 5 Coupling Ratio negative current injection 98 M MOTOROLA MC9S12DJ64 Device User Guide 01 20 A 2 3 ATD accuracy Table A 10 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table 10 Conversion Performance Conditions are shown in Table A 4 unless otherwise noted Vner 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV fATDCLK 2 0MHz um L D L D Ws P E A 2 10 Bit Differential Nonlinearity 3 P 10 Bit Integral Nonlinearity 4 10 Bit Absolute Error 5 8 Resolution ER SB NL INL AE SB NL INL AE Counts Counts Counts mV 5 3 emma menm AE 5 r esmesswnmey Tome 8 1 5 8 Bit Absolute Error 1 5 1 0 Counts NOTES 1 These v
118. y 16K Fixed Flash Page 3E 62 This is dependant on the state of the ROMHM bit 16K Page Window 4 x 16K Flash EEPROM pages 16K Fixed Flash Page 3F 63 OO X d if active 222 27 MC9S12DJ64 Device User Guide V01 20 28 Table 1 2 Device Memory Map for MC9S12D32 Address Module Bytes 0000 000F HCS12 Multiplexed External Bus Interface 16 0010 50014 HCS12 Module Mapping Control 5 0015 0016 HCS12 Interrupt 2 0017 50019 Reserved 3 001A 001B Device ID register PARTID 2 001C 001D HCS12 Module Mapping Control 2 001E HCS12 Multiplexed External Bus Interface 1 001F HCS12 Interrupt 1 0020 0027 Reserved 8 0028 002F HCS12 Breakpoint Module 8 0030 0031 HCS12 Module Mapping Control 2 0032 0033 512 Multiplexed External Bus Interface 2 0034 003F Clock and Reset Generator PLL RTI COP 12 0040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels ATDO 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface 0 SCIO 8 0000 0007 Serial Communications Interface 0 SCI1 8 00D8 00DF Serial Peripheral Interface SPIO 8 00E0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00F0 00FF Reserved 16 0100 010F Flash Con

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