Basic Synopsys User Guide
Contents
1. CCU EE VLSI Group Basic Synopsys User Guide 1 ver 1 0 ce s setup a New Synopsys User e Add the contents of usr synopsys cicSynop synopsys cshirc to your cshrc hsieh cat usr synopsys cicS ynop synopsys cshrc gt gt cshrc hsieh source cshrc ES EIMD ES RLS pad hsieh design analyzer amp o HX Synopsys Design Analyzer e Use online documentation hsieh gt cd hsieh cp usr synopsys cicSynop lview hsieh 1view amp oH ver 1 0 xg CB OE XR Design Analyzer HAUS Synopsys Design Analyzer 4A H 3 ver 1 0 ce 2555 Design Analyzer Read File File gt Read HEJH Read File window Read File window FHS verilog file 41617 Ok RRE EE Verilog window 5i PAE 4H ver 1 0 CCU EE VLSI Group E o Bre Verilog XL compile verilog file fi RIAKI Verilog window e Syntax error verilog pE PERR e Unsupported statement Unsupported definitions and declarations Unsupported operator Only for gate level construct oH ver 1 0 AM ce adag i ABA SE RR 1 Unsupported Statement delay initial repeat wait fork event deassign force release 2 Uns2. INCRBen gt Edit View Pttributes Analysis Tools Encr HH fncrvBH DHB1 add 15 H E Current Design incrv Symbol View Left Button Select Middle Button dd Hodify Select Fight Button Henu EE ef View window H MJE HIN Bu J UH zi r je Design View e lesigns Vieu An ERG hes Left Button Select Middle Button Rdd Hodifu Select Fight Button Menu 5 178 ver 1 0 CCU EE YLSI Group verilog file module s Optimize R EE aun Icon EA HT BERE DAN PAREA 1 module module N T 2 module WIERY HEC EE Tas module module XE TUE EAE icon gusuunuum HERTE PM SUEPBPITEETT ERAR e A 188 ver 1 0 CCU EE VLSI Group E Current Design incrv Schematic View Left Button Select Middle Button ddrHodify Select Right Button Henu zi is ERG EINERBisAE DUSWNXERJ Constraint RAJAR 198 ver 1 0 CCU EE VLSI Group Simulation the Synthesis Circuit 1 Save the synthesis circuit as verilog format v Setup File Edit View Attribu
3. ver 1 0 ce co o setting Operating Environment Setting Input Drive Impedance aug dun a Setup File Edit View Attributes Analysis Tools perating Environment Input Delay liptimization Constraints F UH CoL o F Dr t E arme EE e Rise Strength Fall Strength ENG e Strength d Dptimization Directives F Iri Loa lperating Londitions gt Mire Load 5ame Rise and Fall i zi Timing Range INCRAen INCRBen X X port 5855 t Attributes Part IMCRBen Fort INCRAen Port IMCR2IB2en Bus Fort IB22IMCRB Operating Environment gt Drive Strength unit ns pf select input port mouse Ag 138 ver 1 0 Qm setting Operating Environment ent i Setting Capacitive Output Loading a Bus Mame INCEZ2IB2Li15 0 Lapacitive load 0 5 e Select output port e Attributes gt Operating Environment gt Load unit pf 148 ver 1 0 CCU EE VLSI Group File Edit View RHttributes Mnalysis lesign ptimization li K 1 T Finite State Machines e FPGA Lompiler Hap Design Test Synthesis Map Effort 4 Low Medium High More Map ptions iL Verifu Design Ug EPPorLI o wow F llou Bo
4. 1 0 CCU EE VLSI Group simopt f TRAA P Hsm v vIsi a Librarys LIBOO V2 Verilog cb60hp23 Id ismvmd v vIsi a Librarys LIBOO V2 Verilog cb60hd23 Id ismvmd v vIsi a Librarys LIBOO V2 Verilog cb6010420d 1smvmd v vIsi a Librarys LIBOO V2 Verilog cb60hp23 I d cells support udps vmd v vIsi a Librarys LIBOO V2 Verilog cb60hd23 I d cells support udps vmd oe2H ver 1 0
5. View window HJBSUEH down Ag CCU EE VLSI Group ce ze Different view of a circuit Symbol View Current Design incrv Symbol View Left Button Select Middle Button RBdd HMadifu Select Right Button Henu E zl Symbol View window rE7rxH41 module FAPTE input output pin H Symbol View pin Ag 10H ver 1 0 4 57 Different view of a circuit Schematic View CCU EE VLSI Group un Setup File Edit View Pttributes Pnalysis Tools Help Setup File Edit View Rttributes Analysis Tools d P Current Design incrwv Symbol View Current Design incrv U Schematic view Left Button Select Middle Putton Add Modify Select Right Button Menu Left Button Select Middle Putton Add Modify Select Right Button Menu Schematic View p Schematic View button PIHE uA button Ag 5 118 ver 1 0 ce taceo What is Synthesis e 5ynthesis Translation Optimization FI HBJ Synopsys CUR ES R 1H JD LASHSAJDC FREE Translation KFS BUT DU A cR E H Timing Loading PLAN REKI THAN J Spec Constraints SEBERE dA H Design Optimization 12H
6. tes fnalusis Tools Read Analyze M Elaborate M Import Save Pis Save Info E Current Design incrv Left Eutton Select L 1 3 31 11 I 1T TIG Tg i i i i i i i i i a T i i E EE m es Middle Button Rdd Haodifu Select ochematic Wiew Right Button Menu File Namet Directory tmp mntz vlai c msBb changcr s Nove up one directory B b1 Fm uagtebasket code debussyLog dracula epic ERC fourPhaseELhD57 Cancel 208 ver 1 0 e Ag Canan Simulation the Synthesis Circuit cont 2 Simulation Verilog XL command line simulation method ex 73 HAMWE pattern B J test v hsieh verilog incr v test v f simopt f incr v Synopsys EHI verilog file simopt library User ZH P EX Verilog In Verilog In Cadence netlist p schematic HPA Verilog In netlist Synopsys verilog file behavior level EH Verilog In schematic EH S Synopsys S amp H verilog file tof LAJ Verilog In HIRE ex v TP a HAS tri wire Pa ae EUH Bi assign mask 218 ver
7. undaru Optimization Execute int w Foreground Background Cancel Current Design incrv Symbol View Left Button Select Middle Button hddrhModifu Select Right Button Henu RA E Tools gt Design Optimization HHIH Design Optimization window Design Optimization window HE tA Ok Compile Log window Fd P Ede Ag X ver 1 0 CCU EE YLSI Group Happing incrvQ Information Changed wire load model for incrve O from For A to 10007 iO0PT 1 0 OFTIHIZATION DESIGN RULE TRIALS AREA DELTA DELAY COST LOST Transferring Design incre Dll add 15 0 to database incrv o db Transferring Design incrv O to database incrv db Current design is incrw iu dezign analuzer Current design is incrv rtmp mnt v1zi cz mssbzchanacr verilog incr incrv dbz incrvO design analuzer 1 dezign analuzer benerating schematic for design incrv n The schematic for design incrv has 1 pageta 1 Compile Log window optimization Compile k 16H ver 1 0 CCU EE VLSI Group Edit View Pttributes Analysis Tools IB221NCRAI15sH IB22INCRBI15 81 gt INCRZIBZen E erve INCRZIBZI158H INCRAen 5
8. upported Definitions and Declarations primitive time event trand trior triO trireg 3 Unsupported Operators e and s Division 4 Only for Gate Level Construct nmos pmos cmos rnmos rpmos rcmos e pullup pulldown e rtran tranifO tranif1 rtranifO rtran f1 Mi T ver 1 0 aa CCU EE VLSI Group ng A cTUTIUIUTI X 8 3 BEEN EN Cancel view name indicator EDESA HR QUAE HEA Designs View window SHa 1E icon icon J F DARREN verilog file module name FEIER Synopsys CRER AHE T TE ver 1 0 CCU EE VLSI Group e synopsys_dc setup File for Using ompass 0 6um Cell Librar D EASRA RE HH EARE Library AJAR Read File 5 Verilog window FRAJERA nJ e Synopsys dc setup EME KERN ES EKE ta 17155 84 fr synopsys dc setup FEH Library 3f BSAHER ds AE search path vlsi a Librarys LIBOO V2 Synopsys usr synopsys libraries syn FEES ERBUT AUC E EARE VLSI CAD EL Sg EH JBSEXE FS WENEH target library cb6 0hp23Id dbj link library cb60hp23Id dbj symbol library cb60hp231d sdbj 9H ver 1 0 ce sx Different view of a circuit Design View ORBE ASEE ERS icon Pm E 2 fzDesign
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