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TREX C1 User Guide 20050802

1. 25 6 3 THE FLASH PROGRAMMER NN NN NN NN NAN NN 27 6 4 THE SDRAM CONTROLLER AND PROGRAMMER 0 02 200 00 80000000000000000000 29 6 5 PS2 COMMUNICATION TO THE BOARD ceeeceessecescceeccecesccessecceucceeseeceuscesceecascesseecascesseecuscesseecnasceesevenssensners 30 6 6 TOOLS MULTI PORT SDRAM FLASH CONTROLLER USE A MUSIC PLAYER AS AN 31 6 7 VIRTUAL SWITCHES 000 cee ceecececcceescecsscceescecscceeseecsusceseeecaaeceseecasceseecascesssecascesseecsasenessecnaesessevensseneners 35 TREX C1 DEVELOPMENT KIT CHAPTER 7 LAB 4 CD QUALITY MUSIC BOX oocoooooooooooooocooooooooocoooooooooooooooooocooooooooooooooooooooooooooooooooco 37 7 1 LOAD ANOTHER MUSIC FILE TO PLAY FROM FLASH ooooooooooooo oo nana 37 7 2 PLAY MUSIC FROM 8MBYTE 37 7 3 DETAILS OF THE AUDIO DAC CONTROLLER ooooooooooooooo namamu 39 7 4 A REFERENCE DESIGN 1KHZ SOUND GENERATOR oooooooooooooWoooo oo 40 7 5 How TO CREATE YOUR OWN MUSIC RAW DATA uuu eeceeccecescceeccecescceeceeceuscecceecuscesseecascesseecaeceeseecnascesseeensseneners 40 CHAPTER 8 LAB 5 NTSC PAL TV CONTROLLER ooooooooooocoooooooocooooooooooooooooocoooooooooooooooocooooooooooooooio 42 8 1 YCRCB
2. cases in the field The Board TREX C1 DEVELOPMENT KIT Your T REX Board T REX C1 Development Kit Components amp Interfaces 9V DC Power Supply Connector 0 ohm resistor jumpers R6 R10 Power ON OFF Switch 16 bit Audio DAC 4 bit VGA DAC resistor network 8 user LEDs 27 Mhz OSC USB Controller CPLD for JTAG 50Mhz OSC Switch between JTAG Normal Mode RUN and AS Mode PROG Serial Configuration Device EP1CS1 8 Push button Switches 8MByte 1Mx4x16 SDRAM USB Line VGA TV PS2 RS232 Port Out Out Out Port Port Cis Pu IY ubi PABIERZNW Cyclone industrial Grade 0 ohm resistor jumpers R33 R34 RS 2321C amp TX RX LEDs 4 Digit 7 Seg Display Expansion Header 2 JP2 with Protection Resistors Expansion Header 1 JP1 with Protection Resistors DIP Switch TV Encoder Altera Cyclone 1C6 240 pin TQFP F Card Connector 1MByte Flash Memory under the CF card Figure 2 1 TREX C1 Development Board Components amp Interfaces Same as the full size component reference card attached in the package Features Y Altera Cyclone 106 FPGA with 6000 LEs Y Altera Serial Configuration deivices EPCS1 for Cyclone 1C6 USB Blaster built in on board for programming and user API controlling 3 TREX C1 DEVELOPMENT KIT Your T REX Board KAKA AK RA AKA JTAG Mode and AS Mode
3. memory and load 5thElement 1mbyte into the Flash In Lab3 Control Panel click on TOOLS and select Asynchronous 1 as the Flash Memory R W port Click Configure Button and you will hear the music Play Music From 8Mbyte SDRAM 1 Check C Terasic Binary_Raw_Data directory There is 8Mbyte CD music data called 5thElement 8mbyte which is 8Mbyte long raw CD data N You can convert your MP3 file into a CD Raw Data file by using a free tool MP3 to WMA Converter from AudioUtilities Co Ltd 37 TREX C1 DEVELOPMENT KIT Lab 4 CD Quality Music Box Power up the board and make sure the SOF POF file in Lab4 Control Panel SDRAM MusicPlayer is programmed into the FPGA Start TREX C1 Control Panel tool Change the SDRAM control page and download the 5thElement 8mbyte file into the SDRAM The Control Panel will promote users the downloading status in a progress bar shown in Figure 7 1 Control Panel Open Menu Help About LED amp PS2 FLASH Figure 7 1 Downloading 8Mbyte Music Data into SDRAM Once the downloading is finished click on TOOLS button and select Asynchronous 1 as the SDRAM Memory R W port Note Click on SW7 checkbox and click the Configure button as shown in Figure 7 2 You will hear the 40 sec long music from your headset or speaker 38 TREX C1 DEVELOPMENT KIT Lab 4 CD Quality Music Box gt T REX Control Panel TER Open Menu Help
4. webpage Please visit tr ex terasic COm for more information 64
5. 000001 0 000 F100 F200 F300 F400 F500 F600 F700 F800 F900 00 00 FCOO 000 FEO0 FFOO E00 2F00 F00 000 00 3 Un f SSSSS ooooo e eo e e tu 3 e e J o e a N e e e e J un 4 3 a e e Ll e J e J e OOD gt 00 Er ti C3 00 00 3 OY Un e GJ S2 T T tr 54 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code Figure 9 4 The content of the CF card after testing procedure Expansion Connectors JP1 JP2 FPGA Pin Number Header 180 1 2 179 178 3 4 177 175 5 6 174 173 7 8 169 168 9 10 167 VCC5V 1 12 GND 166 13 14 165 164 15 16 163 162 17 18 161 160 19 20 159 158 21 22 141 140 23 24 139 138 25 26 137 136 27 28 135 VCC3 3V 29 30 GND 134 31 32 133 132 33 34 128 126 35 36 125 124 37 38 123 122 39 40 121 FPGA Pin Number Header JP2 199 1 2 7SEGO 7SEG1 3 4 7SEG2 7SEG3 5 6 7SEG4 7SEG5 7 8 7SEG6 7SEG7 9 10 184 VCC5V 11 12 GND 55 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code 183 13 14 182 181 15 16 120 119 17 18 118 117 19 20 116 115 21 22 114 113 23 24 106 105 25 26 104 1
6. 205 on FPGA TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code Video Encoder NTSC PAL TV Out Lab 5 The SPCA711 Bt852 is designed specifically for Video CD video games and any digital video systems which require the conversion of digital YCrCb MPEG data to analog NTSC PAL video The device supports both NTSC N America Japan and PAL B D M Nc The device operates with a single 2x clock and can be powered with a single 3 3V supply YC4 216 YC5 215 YC6 214 YC7 213 YCO 220 YC1 219 YC2 218 YC3 217 P N drive low for NTSC drive high for 222 PAL TVRES drive low to enable the chip 221 turning this chip off can save you 100mA HSYNCn 206 VSYNCn 207 Lab 6 Verilog Code and Quartus II Project for using TV encoder Repeat the following steps to test the TV out feature 1 Launch Quartus II Software 2 Click on File gt Open Project select the project under directory Lab5 TV 3 Download the bitstream LED1 sof into the FPGA 4 Use a RCA Video cable to connect your TREX C1 board to your TV video in jack You should see color pattern shown on your 6 gt Users can use the code in the project library to expand their own ideas 49 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code on showing pictures patterns on TV DIP Switch s
7. Developrr v m ext ram bus Avalon Tri State Bridge clk EP20K200E Hios Develc v E ext_flash Flash Memory Common Flash Interface 0 00000 EP2C35 Hios Developn v m epcs controller PCS Serial Flash Controller 0x02100000 EP2S60 DSP Board Stra v sys cik timer Interval timer 0 02120800 EP2S60 Hios Developr v B jtag_uart UART 0 02120880 Ethernet button_pio PIO Parallel 1 0 0x02120860 n fain aiis Bled pio PIO Parallel 0x02120870 e E v B high res timer Interval timer 0x02120820 _ All Available Components Bseven seg pio PIO Parallel 0 02120880 v RS 232 serial port 0 02120840 v System ID Peripheral 0 02120888 amp Move Up Move Down Figure 11 1 The Screen Capture of the SOPC Builder used to create NIOSII core on TREX C1 Running NIOS Il on TREX C1 1 Make sure C Terasic Lab8_ NIOSII TREXIstandardistandard sof is loaded into the FPGA Start NIOS II IDE program Refer to Figure 11 2 select C Terasic Lab8_NIOSII_TREX standard as om your workspace 4 Click on File hello led c in the left hand side of the window as shown in Figure 11 3 5 Once the NIOSII is running on TREX C1 board you can press the push buttons KEYO KEY3 The corresponding LEDO LEDS will be turned on according to the push button status NIOS II IDE debuggin
8. LED 0 14 LED 1 13 LED 2 12 LED 3 8 7 LED 5 6 LED 6 4 LED 7 2 7 SEG Display oCOM 3 oCOM 2 oCOM 1 oCOM 0 Figure 9 2 The block diagram of the 7 SEG display module 46 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code Sgn Cyclone Pin Numer LED 0 198 LED 1 197 LED 2 196 LED 3 195 LED 4 188 LED 5 187 LED 6 186 LED 7 185 COM 0 203 COM 1 202 COM 201 COMIS 200 VGA DAC ColanR G Figure 9 3 The 4 bit resistor network DAC for Color R G B nat clone Pin Number VGA B 0 216 VGA 215 VGA B 2 214 VGA B 3 213 VGA 220 VGA 219 VGA 218 VGA 217 VGA R 0 225 47 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code VGA 224 VGA 223 VGA RISI 222 TR TVRES 221 Must drive this pin high to disable the TV Encoder chip because the data bus HSYNC and VSYNC pins are all shared HSYNCn 206 VSYNCn 207 Audio DAC LRCK Sampling Clock 233 BCK 226 DATA 234 PS2 amp RS 232 Interface Cyclone Pin Number 0 PS2_CLK 180 PS2_DAT 179 PS2_LAT reserved for joystick 178 PS2 DIN reserved for joystick 177 TR TXD RS 232 transmitter output 204 pin on FPGA TR RXD RS 232 receiver input pin
9. RS232 Version of TREX Panel 57 TREX C1 DEVELOPMENT KIT RS 232 Version of the TREX Control Panel 1 sure that you have programmed the board with the C Terasic Lab7_TREX_Panel_RS232 QIl_Project New_Flash sof 2 Start the TREX C1 Control Panel RS232 program located in your C Terasic The user interface shown in Figure 15 should appear Click Open Open COM Port Select the COM port used to connect to the board TREX Control Panel Application will list all the available COM ports in your system for you to choose Figure 10 1 shows the dialog box for COM port setup Click OK to connect to the board 5 Therest of operations are same as the USB version Settings z Baud rate 115200 z Data bits 8 Stop bits 1 z Parity None z Flow control None z Cancel Figure 10 1 COM Port Setup in TREX Control Panel The C Source Code You should take a rest TREX C1 DEVELOPMENT KIT Lab 8 NIOS II 5 0 Core Lab 8 NIOS 5 0 Core The Nios embedded processor is optimized for Altera FPGA SOPC System on Programmable Chip solutions A user can easily combine the Nios processor with user logic and program it into an FPGA using SOPC Builder and the user can use NIOSII IDE environment to develop software applications running on NIOS processor Nios processor has many features that allow users to accelerate and optimize their designs by using simple yet non traditional methods In
10. are supported 8Mbyte 1M x 4 x 16 SDRAM 1Mbyte Flash Memory CF Card Socket 8 Push button switches 4 bit DIP Switch 8 User LEDs 50MHz Oscillator and 27MHz Crystal for external clock source 16 bit CD Quality Audio DAC with line out jack VGA DAC 4 bit resistor network with VGA out connector TV Encoder NTSC PAL and TV Out connector RS 232 Transceiver and 9 pin connector Two 40 pin Expansion Headers with resistor protection Terasic Lab CD ROM which contains many examples with source code to exercise the boards including SDRAM and Flash Controller CD Quality Music Player VGA and TV Labs CF Card reader RS 232 PS 2 Communication Labs and User Control API Power Up the Board to See the Demo RON Connect the USB cable from PC to your TREX1 board Connect your headphone or PC speaker to the line out jack of TREX1 Connect your LCD Monitor to your TREX1 Press the Power ON OFF Switch on TREX1 Make sure the RUN lt gt PROG switch is set to RUN position Note that PROG position is only used for AS Mode programming Please refer to Figure 2 2 TREX C1 DEVELOPMENT KIT Your T REX Board Figure 2 2 JTAG Operation RUN mode and AS Mode PROG switch settting 6 You should be able to see the board is running And you should hear the 1K 2khz sounds from your headset s left and right channels respectively Figure 2 3 USB Headset and VGA Connection What you should see and hear
11. test their own IPs to speedup the development phase Important Note about the Multiport SDRAM Flash Controller Make sure HOST port is selected and the Configure button is clicked to activate the selection so that you can Read Write access the Flash SDRAM from the TREX Control Panel Once you finish the data downloading from host you can switch to Asynchronous port 1 remember to click Configure button to activate your selection to listen to the music stored in Flash memory to speedup the development phase 34 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel Virtual DPDT Switches Please refer to Figure 6 14 Select the number 3210 in the 7 SEG Digit Boxes and click on the REFRESH button to display the number 3210 on the 7 SEG display module 2 Click on the TOOLS button in the TREX Control Panel to switch to the TOOLS page where you can find the Virtual DPDT Switches 3 Click on the SW3 and SW1 boxes Then Click on the Configure button You will notice that the Digit 3 and Digit 1 are turned off as shown in Figure 6 14 Readers who are interested in using the Virtual DPDT Switches should look at the following Verilog Code examples 7 SEG DIG 3 DIG 2 0161 DIG B ida Virtual DPDT Switches 5 3 2 SW 1 Figure 6 14 TREX Control Panel Virtual DPDT Switches Verilog Code for illustrating how to use the Virtual DPDT Switches to tu
12. the USB version of the TREX Control Panel Package Important Note on the USB Link 1 The TREX Control Panel USB Version is using the same link as Altera USB Blaster You need to release close the USB port in TREX Control Panel before you can use the USB Blaster link from Quartus II 2 If concurrent debugging using TREX Control Panel and Altera Signal is desired users should use the TREX Control Panel s RS232 Version Connect PC to the Board Using USB Cable Y Make sure that you have C Terasi Lab3_TREX_Panel installed in your directory Y Start Quartus II Software Y Click File gt Open Project Y Select C Terasic Lab3_TREX_Panel New_Flash Multiplexer New_Flash project Y Click on Programming button Setup the programming hardware to USB Blaster according to the instructions stated in Chapter 4 Y Select the New Flash sof stored in the Lab3 TREX Panel directory and download it to FPGA 24 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel Control the Board Using TREX Panel Figure 6 1 shows the concept of the TREX Control Panel Users use Window GUI to issue commands via the USB link to the FPGA We provide an IP to handle all the requests and perform data transferring between PC and the TREX board T REX Control Panel TEN EH DIG3 0162 0161 F Random Access Address 0 WOATA 123 DATA Chip Erase 16 Sec Write Read Sequen
13. 0 oCOM 3 oCOM 2 oCOM 1 oCOM 0 output 0 when cnt 11 output 0 when cnt 10 output when cnt 01 output 0 when 00 DeMUX Figure 5 3 The FSM 2 bit counter for the scanning control When Counter 00 TREX C1 DEVELOPMENT KIT Lab 2 How to work with scanned 7 SEG Display oCON 3 oCOM 2 oCOM 1 oCOM 0 DeMUX Figure 5 4 The circuit FSM state when counter CNT 00 The Verilog Code for Scanned Mode Verilog Code for Scanned mode Operation FSM 2 bit counter for 7 SEG digit selection always cnt begin if cnt 2000 begin SEG7_reg lt 8117 Number 4 7 lt 4 b1110 else if cnt 2 b01 begin SEG7_reg lt 8119 Number 3 COM7 reg lt 4 b1101 end else if cnt 2 b10 begin SEG7_reg lt 8158 Number 2 22 TREX C1 DEVELOPMENT KIT Lab 2 How to work with scanned 7 SEG Display 23 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel Chapter Lab 3 TREX Control Panel This chapter will illustrate the TREX Control Panel package that allows users to control the board using Window GUI menu The TREX Control Panel Package is free to the users who purchased TREX C1 Development Kit This package provides users a simple yet powerful method to control the board The connection from your PC to the board can be done by a RS232 or USB cable In this lab we will teach users how to use
14. 0 117 FL DQ 1 118 FL 119 FL DQ S3 120 FL DQ 4 121 FL DQ 5 122 FL DQ 6 123 FL DQ 7 124 FL OE N 116 FL RST N 98 FL WE N 99 nv cs0 n 81 Note that Flash is sharing data bus with CompactFlash connector Need to drive high to this pin to disable CompactFlash nv cs1 n 82 Same as above must drive high to this pin to disable CompactFlash Compact Flash Card 52 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code NN da 0 114 da 1 106 da 2 105 nv 50 n 81 nv cs1 n 82 dd 0 115 dd 1 116 dd 2 118 dd 3 84 dd 4 86 dd 5 88 dd 6 95 dd 7 97 dd 8 117 dd 9 119 dd 1 0 121 dd 11 85 dd 1 2 87 dd 13 94 4 96 dd 15 98 dior_n 99 diow_n 100 nv intrq 102 101516 120 53 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code Note that CF is sharing data bus with Flash you need to drive this pin high to disable Flash Memory IORDY 104 CF REG 113 reset 103 FL CE N 83 1 Cu we GS Lab 5 Testing Your Compact Flash CF Card Repeat the following steps to test the CF card Make sure the power is off Insert your CF card into the CF socket on the TREX C1 board Power on the board Launch Quartus II Software Download the bitstream LED1 sof located in the Lab6 CF directory into the FPGA You will see the pa
15. 03 27 28 102 VCC3 3V 29 30 GND 100 31 32 99 98 33 34 97 96 35 36 95 94 37 38 88 87 39 40 86 56 TREX C1 DEVELOPMENT KIT RS 232 Version of the TREX Control Panel Chapter RS 232 Version of the TREX Control Panel The reason why we provide users the USB Version of TREX Control Panel software package is to dramatically reduce the Flash SDRAM programming time However users cannot use the USB version Control Panel together with Altera Signal Tap tools because both tools share the same USB blaster link To enable users to build their own API or C control tools on top of our current TREX Control Panel Package we provide users all the code C and RTL free of charge Note that users are allowed to use and modify the code provided in the TREX CD ROM only if the FPGA hardware platform used is designed and manufactured by Terasic Technologies Connect PC to the Board using RS232 1 sure the Lab7 TREX Panel RS232 is installed to your project directory Start Quartus II Software Click File gt Open Project Select C Terasic Lab7_TREX_Panel_RS232 New_Flash gi Click on Programming button Setup the programming hardware to USB Blaster according to the instructions stated in Chapter 4 6 Select the New Flash sof stored in the Lab2 TREX Panel RS232 directory and download it to FPGA 7 gt Now you can use the RS232 cable to connect PC to your TREX1 board Control the Board Using
16. AND COMPONENT DIGITAL 42 8 2 TV LAB NTSC PAL TV COLOR PATTERN 43 CHAPTER 9 INTERFACES AND ASSOCIATED TESTING CODE ooocoooocoooooooooooooooooooooooooooooooooooooooooooo 45 9 1 50 MHZ AND 27 MHZ 85 200020200 0 000000000000000000000 45 9 2 Lc 45 9 3 8 PUSH BUTTON SWITCHES KEY 7 TO KEY O ooooooooooo nana 45 9 4 7 SEQ DISPLAY bea an ri 46 9 5 NMAC 47 9 6 AUDIO 48 9 7 62 amp 5 232 2 Er eet pee ee Ce tee een ed aos eal Bia 48 9 8 VIDEO ENCODER NTSC PAL TV OUT LAB 5 49 ODP SWIC 50 9 10 SDRAM INTERFACE 50 92111 FLASH MEMORY Sees es a Ree ee 51 9 12 COMPACT FLASH CARD aa as Rin NAN RN 52 9 13 EXPANSION CONNECTORS JP1 JP2 oooooW oco o Wooo Woman 55 CHAPTER 10 RS 232 VERSION OF THE TREX CONTROL PANEL ooooooooooooooooooooooooooooooooooooooooooooo 57 10 1 CONNECT TO THE BOARD USING 232 2 tese trs aan 57 10 2 CONTROL THE BOARD USING RS232 VERSION OF TREX PANEL ooooooooooooooWoWoo oo Wo mo mma 57 10 3 THE G 4 SOURCE CODE 465 i etn notes 58
17. About LED amp PS2 FLASH SDRAM TOOLS SDRAM Multiplexer Asynchronous 1 FLASH Multiplexer Host USB Port E Virtual DPDT Switches Configure Board Test Figure 7 2 Need to activate SW7 with SDRAM R W port set to Port 1 to listen to the music played Verilog code for using SW7 to control the music source Note that SW 7 is represented by wire mExt_lO 7 internally m AUD XXX 0 wires are connected to the AUDIO DAC IP for Flash memory m AUD XXX 1 wires are connected to AUDIO DAC IP for SDRAM assign AUD mExt IO 7 100 m AUD BCK 0 m AUD BCK 1 assign AUD DATA mExt IO 7 1 b0 m AUD DATA 0 m AUD DATA 1 assign AUD LRCK mExt IO 7 100 m AUD LRCK 0 m AUD LRCK 1 Details of the Audio DAC Controller TREX C1 DEVELOPMENT KIT Lab 4 CD Quality Music Box The master clock for MS6311 supports audio sampling rates from 128fs to 512fs where fs is the audio sampling frequency LRCK typically 2 44 1kHz 96kHz or 192kHz The master clock is used to operate the digital filters and the noise shaping circuits In this lab we use 96kHz sampling rate LRCK with 192fs 18 432Mhz The 18 432Mhz is generated using the PLL block inside Cyclone device Figure 7 3 illustrates the timing diagram we generated for the audio DAC LEFT Channel Right Channel interface LRCK Figure 7 3 The timing diagram of the audio DAC A Referenc
18. CHAPTER 11 LAB 8 NIOS II 5 0 CORE 59 11 1 LOAD NIOSIII 570 ON T REX e eere tte iS Ehe eter ee ere te eese t o oe 59 11 2 RUNNING NIOS Il ON TREX 1 20 60000000000 00000000000 60 CHAPTER 12 APPENDI oo 63 12 1 REVISION HISTORY 0 ecc ce ceeceeccecesscesccecesccceceecusceeceeceasceseecaascesseecaascesssecauecessecasceseecauecesevessecesseesaeenssetenseeesss 63 12 2 TREX CD ROM DIRECTORY STRUCTURE AND REFERENCE DESIGNS ooooooooooooo oo 63 12 9 64 12 4 ALWAYS VISIT TREX C1 WEBPAGE FOR NEW 5 022 0202000000 000 00 64 TREX C1 DEVELOPMENT KIT About this Kit About this Kit The TREX C1 Development Kit provides everything you need to develop many digital designs using Altera Cyclone device The Getting Started User Guide is written in a way to enable users to walk through many reference designs in 30 minutes This chapter provides users key information about the kit Features TREX C1 Development Board USB Cable for power supply and FPGA programming TREX C1 CD ROM containing T
19. CRATCH ccccccecceecceescesscesscesscesccaccseccecaesenevecsvecsvscsusceusceacessecsaecaeessecsaeenseenseess 11 4 3 COMPILING THE DESIGN 13 4 4 DOWNLOAD BITSTREAM Name 15 4 5 THE TOP LEVEL RTL AND PIN 18 CHAPTER 5 LAB 2 HOW TO WORK WITH SCANNED 7 SEG 19 5 1 THE 7 SEG DISPLAY MODULE ON TREX 19 5 2 PURE COMBINATIONAL LOGIC LAB USING NON SCANNED MODE 19 5 3 THE VERILOG CODE FOR COMBINATIONAL 0 00020 022 20 0 010001000000 20 5 4 SEQUENTIAL LOGIC LAB USE THE SCANNED 21 5 5 WHEN COUNTER 00 0000 cece 21 5 6 THE VERILOG CODE FOR SCANNED MODE nana 22 CHAPTER 6 LAB 3 TREX CONTROL PANEL ooooooooooooooooooocooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 24 6 1 CONNECT PC TO THE BOARD USING USB 24 6 2 CONTROL THE BOARD USING TREX
20. I Software v Click File gt Open Project v Select C Terasic Lab5_ TV LED1 project Color Pattern Generator www chromaate com Glick on Programming button Setup the programming hardware to USB Blaster according to the instructions stated in Chapter 4 Y Select the LED1 sof stored in the Lab3 TREX Panel directory and download it to FPGA Y Connect the TV output jack of the TREX C1 board to your TV Video In Jack You should be able to see the color pattern shown in Figure 8 1 Press KEY 2 to switch between NTSC and PAL system lt lt Figure 8 2 shows another setup in our lab where we use TREX C1 board to generate the TV color patterns to feed into the latest Altera DE2 multimedia board The Altera DE2 board then convert the YCbCr 4 2 2 format to RGB using Cyclone II FPGA and display the result on VGA Monitor This lab setup is excellent for video multimedia labs because 1 TREX C1 board serves as a cheap NTSC PAL dual system TV Color Signal Pattern Generator instead of buying expensive NTSC PAL TV Pattern generator 2 Altera DE2 board serves as a video processing compression box 3 Altera DE2 board can also serves as a simple TV Box as in this example which converts TV input to VGA output to enable users to observe the results on a easy to get VGA monitor in the lab 43 TREX C1 DEVELOPMENT KIT Lab 5 NTSC PAL TV Controller Figure 8 1 The output of TREX C1 as a NTSC PA
21. IGO and click on Refresh The 7 SEG display on the board will change accordingly igo maus CAM 7 5 063 081 a Figure 6 4 LED and 7 SEG Display Control Panel The Flash Programmer The Flash memory used on TREX1 board is a 1 Mbyte Flash memory organized as 1M x 8 bit Detailed spec can be found at C Terasic 3rd_party_specs sst39vf800a pdf You need to ERASE entire Flash memory before you can write to it Remember that the number of time a Flash memory can be erased is limited The time required to erase entire Flash memory is 15 secs 21 secs Please do not close the TREX Control Panel in the middle of operation Follow the steps to exercise the operations to the Flash memory 1 Click on Button Flash to change to Flash Memory Control Page Refer to Figure 6 5 Click on Chip Erase The button and window frame title will prompt you to N wait until the operation is finished It will take around 16 secs to finish the operation e Please refer to Figure 6 5 Key in a random address 1688 in the example and value in wDATA field 125 in the example Click on Write will write 125 to address 1688 Key in the address and click on Read The rData will display the data read B back from the address specified 27 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel fics was Figur
22. L Color Pattern Generator USB Blaster Port Power TV NTSC PAL Video VGA Output In i 2 AN errr 3228 er Pee TREX C1 Altera DE2 Multimedia Board serves as a NTSC PAL TV Pattern Generator TV Box which does image processing and convert YCbCr to RGB for VGA Monitor Figure 8 2 Another setup of the lab which uses TREX C1 with Altera DE2 board TREX C1 serves as a TV pattern generator and DE2 board serves as a TV Box 44 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code Chapter Interfaces and Associated testing code This chapter illustrates all major blocks and interfaces of the TREX1 board For some interfaces like Compact Flash Card we will be using a simple example to illustrate how to exercise the interface 50 Mhz and 27 Mhz Oscillators OSC_50 50Mhz Oscillator 28 OSC_27 27Mhz Oscillator 153 LED1 LED8 S Oyaonepintumber 0 LED 0 50 LED 1 11 LED 2 228 193 LED 4 170 LED 5 131 LED 6 108 LED 7 78 8 Push Button Switches KEY 7 to KEY 0 45 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code push button pressed Before Debounce 1 a Schmitt Trigger Debounced gt Figure 9 1 The waveform after RC de bounced and Schmitt trigger circuits
23. LUS II Project 11 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Figure 4 1 Menu for Opening Quartus II Project Select The NewFlash Quartus II project under Lab1 PowerUp directory Refer to Figure 4 2 Open Project New Flash Fa RART Quartos II Project File qpf quartus qar v RRA Figure 4 2 Select the only project PowerUp directory Y Please refer to Figure 4 3 Click on File Icon in the bottom of left hand side window and select New_Flash Examine the file content and the IO port declaration You will find that the 8 bit 7 SEG data bus oSEG7 are shared by all four digits You can enable each digit by drive 0 to its corresponding enable pins oCOMJ3 0 In this case we constantly drive 0 to all four enable pins Therefore the four 7 SEG display digits display the same HEX number 12 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Owartus C T Rex CD Lebl Powert p New Flash New Flash Edit Yow Project Asugument Processing Jools Widow Help Bg R New Flash gt sld Fiks Design Fiks anyar peceiver v g asya transmutter Fisch Controller rCounter S mbrz lt rCounter SOmhz 1 b1 end assign oLED assign oCOM O rCounter SOmhz 28 21 output to 1750 enable 7 SEG Digit 0 27 Bee Plath R5232 Contes 5837 Drivery E Software Files Other Fil
24. REX API reference designs and specs Altera Quartus II 5 0 Web Edition CD ROM and Nios II 5 0 CD ROM RS 232 Cable for board control using UART protocol This Getting Started Guide Full size component reference card lt 5 lt lt lt lt lt 9V DC Wall mount power supply backup power Getting Help Email to support terasic com SkyPE Terasic Taiwan amp China 886 3 553 9672 Korea amp Japan 82 2 512 7661 LEES North America support terasic com TREX C1 DEVELOPMENT KIT Your T REX Board Your T REX Board This chapter will walk you through each part of your TREX C1 TREX1 board to illustrate the features equipped The TREX C1 TR1 Layout traces and components are carefully arranged so that they are properly aligned This nice alignment will increase the yield for manufacturing and ease board debugging procedure Jumper free design for robustness Jumpers are a great point of failure and might cause frustration for users who don t keep the manuals with them all the time TR1 board uses four 0 ohm SMT resistors to replace 4 jumbers used for power measurement in different areas Components selection was made according to the volume shipped We selected the most common component configuration used in PC and DVD players to ensure the continuous supply of the component resource in the future Protection on Power and IOs are considered to cover most of the accidental
25. TREX C1 Development Kit Getting Started User Guide Copyright 2005 by Terasic Technologies Inc http www terasic com TREX C1 DEVELOPMENT KIT CHAPTER 1 ABOUT THIS 1 WAT FEATURES Haa BBB 1 O 1 CHAPTER 2 YOUR T REX BOARD o ooooooooocooooo o ooo oooo oooo ooooo oo moooo wo o o mooooo o oo 2 221 THE TREX 1 TRI T P OK OK 2 2 2 VE BOARD ma NM IN E p LS M MI tU 2 PA ES DIPL DPI LIC MD LIMITI IL Id ch ta FA n ONE UT Coe DT 3 2 4 POWER UP THE BOARD TO SEE THE DEMO 4 CHAPTER 3 INSTALLATION ie 7 3 1 INSTALE QUARTUS Il iti petere tet Eee ERE epe Rete el re EE DR E lessened odes 7 3 2 CONNECTING THE USB CABLE TO THE BOARD USB BLASTER 5 7 3 3 POTENTIAL PROBLEMS AND WORKAROUND FOR USING USB BLASTER eene entren nennen 8 3 4 INSTALL TERASICILAB CD ROM etit rc ete e toe i ter neto erts 8 CHAPTER 4 FIRST LAB 7 SEG DISPLAY ooooooocooocooooooooooooooo oooooooooooooooooooooooooooooooooooooooo oooooo o oo 11 4 1 POWER UP THE BOARD EE Ee Ue AR UR EU a 11 4 2 REPEATING THE LAB FROM S
26. Y should hear 1KHz and 2KHz sound from the left and right channels of headset speaker respectively Y You should see a 4096 color pattern on your LCD monitor Set the DIP switch 4 to ON for 800x600 set DIP switch 4 to OFF for 640x480 Please refer to Figure 2 4 You should see the LEDs and 7 SEG display are running Y Set DIP switch 1 2 3 to ON will turn its corresponding 7 SEG display 5 TREX C1 DEVELOPMENT KIT Your T REX Board digit 3 2 1 OFF respectively Figure 2 4 4096 color VGA Pattern TREX C1 DEVELOPMENT KIT Installation Installation This chapter will walk you through each step to install the kit on your PC and bring up the board correctly Install Quartus Il v Install Quartus II Web Edition using the Quartusll CD ROM in the kit lt Log on to the Altera web site at www altera com licensing Y Quartus II Web Edition Software and follow the instructions to request your license A license file is e mailed to you Follow the instructions in the Specifying the License File in the Quartus II Installation amp Licensing Manual for PCs included on the TREX Development Kit CD ROM Connecting the USB Cable to the Board USB Blaster Installation Y Connect your USB Blaster download cable to the TREX1 board v Found New Hardware wizard may open and prompt you to install a new hardware driver Close the w
27. assignment again 18 TREX C1 DEVELOPMENT KIT Lab 2 How to work with scanned 7 SEG Display Lab 2 How to work with scanned 7 SEG Display Most of the multi bit 7 SEG display modules in the market are using scanning mode because of the consideration on both cost pin and power saving in industry products Also the scanned mode of 7 SEG display gives us an good example to teach students engineers on both combinational and sequential logic using one single device Mostly important the students engineers can learn how to use the most common 7 SEG display device available in the market The 7 SEG Display Module on TREX C1 v 8 data bus pins oSEG7 7 0 are connected to all the LED segments of each digit according to the numbers put in Figure 5 1 For example oSEG7 2 connects to all the LED segments labeled 2 in each digit v Each digit has its own enable oCOMJ3 01 For example oCOM 0 is the enable pin of digit 0 oCON 3 oCOM 2 oCOM 1 oCOM 0 Figure 5 1 7 SEG module block diagram Pure Combinational Logic Lab using non scanned mode 19 TREX C1 DEVELOPMENT KIT Lab 2 How to work with scanned 7 SEG Display Y that both LED segment enable pins oSEG7 7 0 and digit enable pins oCOMJ3 0 are low active Y display 2 on digit 0 drive oCOM 0 low and oSEG bit 1 5 7 0 2 low as shown in the case A of Figure 5 2 Y display 2 on digit 0 and dig
28. box 6 In the programming window select the desired mode JTAG or Active Serial Programming mode 7 Click Add File button and select the desired SOF for JTAG or POF for AS mode accordingly Click Start button to download the selected bitstream In JTAG mode you should see the behavior of the design right away In AS mode you have to reboot the board power on off so that the FPGA can load the bitstream from the Serial Configuration Device The first time when you open up a Quartus II design project copied from somewhere else and open the Programming Window you should delete the existing SOF POF file by selecting the file and clicking on Delete button because the existing SOF POF file path might be different from your current path Once you save the Quartus II configuration before you exit the quartus II it will remember the SOF POF file path next time when open the programming window Remember to check the Configuration Program box after you add a new file In JTAG mode you can use Auto Detect to confirm that the link and device are correct 17 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display The Top Level RTL and Pin Assignment For each lab in the TREX1 Development CD you will find a top level RTL code ex New Flash v and pin assignment table ex New Flash qsf To create your own Quartus II project you can simply copy the top level and pin assignment file to save time in doing the pin
29. d provides users many reference designs and API tool Default Bitstream The Bitstream loaded into the serial configuration device Lab1_PowerUp PowerUp test for LED and 7 SEG Lab2_work_with_scanned The examples on how to control the scanned display 7 SEG display module Lab3 Control Panel TREX C1 Control Panel and associated IPs TREX C1 DEVELOPMENT KIT Appendix SDRAM controller Flash Memory Controller Virtual DPDT switches PS2 VGA controller LED 7 SEG control Applications includes Flash Music box Lab4_Audio 1kHz sound generator Lab4 Control Panel SDRAM Playing CD Quality music from SDRAM MusicPlayer implementation of a CD Music Box Lab5 TV Generating NTSC PAL TV signal and color patterns Lab6 CF Read Write and Compare testing on CF card Lab7 Control Panel RS232 TREX C1 Control Panel via RS232 link and associated IPs By using the RS232 path users can use signal tap to simultaneously with the Control Panel Signal Tap must be shown in this window Lab8 NIOSII TREX A NIOSII example on TREX C1 Raw binary data Some 1Mbyte and 8Mbyte CD music raw data 3 party specs all 39 party ASIC specs Schematic Please send email to support terasic com for requesting schematic information Always Visit TREX C1 Webpage for New Labs We will be continuing providing interesting examples and labs on our TREX C1
30. dress 0 Length 0 File Length Write File To Sdram Sequential Read Address 0 Length 0 Entrie Sdram Load Sdram Content To File Figure 6 8 The SDRAM Controller Panel PS2 Communication to the Board Figure 6 9 shows the setup of the connection Note that the RS 232 link can be the USB as well Figure 6 10 shows the characters typed in from the PS2 keyboard are shown in the message box of the TREX Control Panel PS2 KEYBOARD Figure 6 9 PS2 and USB RS232 connection Setup 30 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel T REX Control Panel Ce Open Menu Help About LED amp PS2 FLASH SDRAM TOOLS LED TN 7 SEG DIG 3 0162 0161 DIG 0 PS2 Keyboard TERASIC TECHNOLOGIES AND ARCHES Figure 6 10 TREX Control Panel PS2 Keyboard message box TOOLS Multi Port SDRAM Flash Controller Use a Music Player as an Example Figure 6 11 shows the concept of the multiport SDRAM Flash controller lt Note that for every board shipped we have downloaded a music file into the Flash memory via the USB link Host USB Port v Inthe TREX Control Panel click on the TOOLS button to reach the window 31 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel in Figure 6 12 As illustrated in Figure 6 13 select the Asynchronous 1 for Flash Multiplexer and then click on the Configure button to activate
31. e 6 5 Random Access to Flash Memor 5 You also load a file into Flash by using Sequential Write function Please refer to Figure 6 6 You have to specify the starting address and the length in bytes to be written into the Flash 6 Youcan click on File Length checkbox to indicate that you want to load entire file into the flash memory Then Click on Write File to Flash to choose the file to be loaded into the flash memory 7 Note Please load c terasic Binary_Raw_Data cdda1m into your Flash Memory now so that we can proceed with the Flash Music Player Lab in the next section Figure 6 6 Write an entire file into the Flash Memor 8 Sequential Read function allows you to read the content in Flash and save into a file Figure 6 7 shows the screen capture of the Sequential Read You can also specify the starting address and the length in bytes to read from the Flash By clicking on the Entire Flash checkbox you are indicating that you would like to load entire flash content 1Mbyte into a file specified by you Load Flash Contentto File AM Figure 6 7 Load the content of the Flash Memory to a file 28 TREX C1 DEVELOPMENT KIT The SDRAM Controller and Programmer The SDRAM memory used on TREX1 board is a 8 Mbyte single data rate SDRAM organized as 1M x 4 x 16 bit Detailed spec can be found at C Terasic 3rd_party_specs Samsung_k4s641632h_tc75 pdf Follow th
32. e Design 1KHz Sound Generator The first audio design is stored under C Terasic Lab4_Audio Open the Quartus II project in Lab4 Audio and download the SOF file in the project directory Plug your headset and you should be able to hear the 1kHz sound How to Create Your Own Music Raw Data 40 TREX C1 DEVELOPMENT KIT Lab 4 CD Quality Music Box 1 Dowload a software tool called to All Converter from internet 2 Convert your desired MP3 music sound file into a WAV file with sampling rate at 44 1Khz Please refer to Figure 7 4 to see how to setup the MP3 conversion tool 3 Once you have the raw WAV file you can use Hex Workshop software to select the desired music portion and copy into a new file Then you can use the new WAV file for TREX C1 board s audio applications MP3 To All Converter v1 37 Unregistered Options Output Music Type Sample Rate Bit Rate Channel Type WAV 44100 O Stereo v Overwrite existing files Delete the source C Save to source directory me NN Figure 7 4 Convert a MP3 file into raw WAV format 41 TREX C1 DEVELOPMENT KIT Lab 5 NTSC PAL TV Controller Chapter Lab 5 NTSC PAL TV Controller The two most important applications of multimedia products are audio and video processing We have demonstrated the audio capability of TREX C1 board with the labs of SDRAM Flash Music Play
33. e is any TREX C1 DEVELOPMENT KIT Installation M Labl_ PowerUp i Lab2_work_with_scanneddisplay LJ Lab3 Control Panel LJ Lab4 Audio LJ Lab4 Control Panel SDRAM MusicPlayer 2 1465 TV Lab6 CF 1 41 Lab Control Panel RS232 i Lab8_NIOSII_TREX T REX Control Panel T REX C1 Control Panel RS232 TREX Cl UserCuide Figure 3 3 After installation you can access all the labs and API from Window Start Menu 10 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Chapter First Lab 7 SEG Display This chapter will walk you through all the steps required to exercise a simple Quartus II design example from the beginning to the end After this chapter users should be able to repeat the other reference designs provided by the kit Power Up the Board your USB download cable to the TREX1 board Y Pushthe Power ON OFF button on the board The Power LED will light up Y will see the board is running with the demo code shown in Chapter 2 Plug your headset and press KEY1 to hear the music If everything works fine go to next section Repeating the Lab From Scratch Y Launch Quartus II Software Y Glick on File gt Open Project See Figure 4 1 IM Edit View Project Assignments Processing Tools Window Help New 8 Open Cho pe pei salad i New Project Wizard Open Project Convert MAX P
34. e steps to exercise the operations to the SDRAM 1 N e gt e Please refer to Figure 6 8 Click on Button SDRAM to switch to SDRAM Control Page Key in a random address 1688 in the example and value in wDATA field abcd in the example Click on Write will write Oxabcd to address 1688 Key in an address and click on Read The rData will display the data read back from the address specified You can also load a file into SDRAM by using Sequential Write function Please refer to Figure 6 8 You have to specify the starting address and the length in bytes to be written into the SDRAM You can click on File Length checkbox to indicate that you want to load entire file into the SDRAM Then Click on Write File to SDRAM to choose the file to be loaded into the SDRAM Sequential Read function allows you to read the content in SDRAM and save into a file Figure 6 8 shows the screen capture of the Sequential Read You can also specify the starting address and the length in bytes to read from the SDRAM By clicking on the Entire SDRAM checkbox you are indicating that you would like to load entire SDRAM 8Mbyte into a file specified by you Lab 3 TREX Control Panel TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel T REX Control Panel Open Menu Help About LED amp PS2 FLASH SDRAM TOOLS SDRAM Random Access Address 1688 wDATA labcd IDATA lABCD Write Read Sequential Write Ad
35. er In this chapter we will demonstrate the video capabilities of the board which is the fundamental building block in digital video processing for TV LCD TV and HDTV YCrCb and Component Digital Video CCIR 601 defines some basic properties common to digital component video such as pixel sampling rate and color space conversion More specific documents such as ITU R BT 656 define how the data format defined by CCIR 601 is to be transmitted over various kinds of links with various numbers of lines 525 or 625 Digital Video uses YCrCb Components format where Y represents luma and CrCb arescaled chroma values This YCrCb refers to a signal format that is transmitted over a wire CCIR 601 illustrates how to perform subsampling on chroma values The most common subsampling method is 4 2 2 where there is one pair of Cr Cb samples for every other Y sample The SPCA711 Bt852 is designed specifically for Video CD video games and any digital video systems which require the conversion of digital YCrCb MPEG data to analog NTSC PAL video The device supports both NTSC N America Japan and PAL B D M Nc The device operates with a single 2x clock and can be powered with a single 3 3V supply 42 TREX C1 DEVELOPMENT KIT Lab 5 NTSC PAL TV Controller TV Lab NTSC PAL TV Color Pattern Generator v sure that you have C Terasic Lab5_TV installed in your directory Y Start Quartus I
36. es assign oCOM 2 assign oCON 3 1 bO enable 7 SEO Digit 2 l bO enable 7 SEG Digit 3 7 assign 1 1 bO enabie 7 SEG Digit 1 t to 7 SEG LEDs always rCounter SOmhze decode the value into 7 SEG begin case rCounter SOmhz 26 23 4 11 3 lt 8 b11010111 4 h2 rSEG 7 lt 8 b01001100 4 h3 lt 8 501000101 4 h4 rSEG lt 8 b10000111 4 h5 cSEG lt 8 00100 01 4 h6 rSEG7 lt gt 8 b00100100 4 h7 5 lt 8 b01010111 4 h8 r5EG lt 8 b00000100 4 h9 lt 8 600000111 4 cSEG7 lt 8 b00000110 4 hb rSEG7 lt 8 b10100100 4 he r5EG lt 8 b00111100 4 hd rSEG7 lt 8 b11000100 4 he r5EG7 lt 8 b00101100 4 hf rSEG7 lt 8 b00101110 4 hO rSEG 7 lt 8 b00010100 end oCOM 3 oCOM 2 oCOM 1 oCOMIO Figure 4 4 The 7 SEG Display Module Diagram Compiling the Design You can dick the compile button to start compilation 1 It will create a SOF file New Flash sof for user to program FPGA program the active serial device you need to convert programming file to POF format Figure 4 5 shows the Convert Programming File menu 13 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display 4 Quartus II File Edit View Project Assignments Processing New Open New Project Wi
37. figure Board Test Figure 6 12 TREX Control Panel The TOOLS page T REX CI Control Panel EIE Open Menu Help About LED amp PS2 FLASH SDRAM TOOLS SDRAM Multiplexer Host USB Port FLASH Multiplexer LSIEN Virtual DPDT Switches configure t B Board Test Figure 6 13 TREX Control Panel multi port SDRAM Flash Usage Verilog Code for Connecting the AUDIO DAC IP Core to Asynchronous Port 1 of the Flash Controller ln the top level RTL code New Flash v you will find the following multi port 33 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel Flash Controller instantiated Multi_Flash u2 Host Side mFL2RS_DATA mRS2FL_DATA mFL_ADDR mFL_CMD mFL_Ready mFL_Start Async Side 1 mFL AS DATA 1 mFL AS ADDR 1 Async Side 2 Note that the Async Side 1 is the Asynchronous Port 1 of the Flash Controller Signal mFL AS DATA 1 is the data bus and mFL AS ADDR 1 is the address bus The Audio DAC IP is connected to these two buses by using the following code which readers can find in the New Flash v file AUDIO DAC u6 Audio DAC IP Controller AUD AUD BCK AUD DATA AUD DATA AUD LRCK AUD LRCK CLK 18 4mhz wOSC 18 4 ENABLE 1 b1 RESET KEY 1 The reset KEY to remove noise FL ADDR mFL AS ADDR 1 FL DATA mFL AS DATA 1 Users are encouraged to leverage the multi port SDRAM and Flash memory controllers to develop and
38. g window will also show the information on which button is pressed as shown in Figure 11 4 60 TREX C1 DEVELOPMENT KIT Lab 8 NIOS II 5 0 Core 5 Workspace Launcher Select a workspace Nios II IDE stores your projects in a directory called a workspace Select the workspace directory to use for this session Workspace C Terasic Lab8_NIOSII_TREX standard X Browse Use this as the default and do not ask again Cmn Figure 11 2 Start NIOSII IDE and open C Terasic Lab8 NIOSII TREX standard as workspace eS hello led 0 Q Binaries Includes Ge Debug C hello led c antena readme txt EES hello_led_O_syslib std_1c20 5 Nios II Device Drivers Figure 11 3 Select hello led c and click on the Green Arrow to build run the project 61 TREX C1 DEVELOPMENT KIT Lab 8 NIOS II 5 0 Core Niss IL IDE Run Project slib Istd 120 Drivers Took Problems E Console 53 Properties Help if last tested edge capture continue else T 1 last tested edge capture IOWR ALTER ALON DATA LED PIO edge capture switch edge capture 0 1 printf inButton 1 500 Pressed LEDO is buttons tested buttons tested 0 1 break case 0 2 printf inButton 2 891 Pressed LED1 is ON n i lt hello_led_0 Nios II HW configura
39. ignal SW1 184 SW2 183 SW3 182 SW4 181 SDRAM Interface Signal Cyclone Pin Number 0 SD ADDR O 77 SD ADDRI1I 78 SD ADDR 10 76 SD ADDR 11 62 SD ADDR 2 79 SD ADDR 3 80 SD ADDR 4 68 SD ADDRISI 67 SD ADDR 6 66 SD ADDRITI 65 SD ADDR 8 64 SD ADDR S 63 SD BA 0 47 SD BA 1 75 SD CAS N 44 SD CKE 61 SD CLK 50 SD CS 46 50 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code SD DATA O 15 SD DATA 1 16 SD DATA 10 57 SD DATA 11 56 SD DATA 12 54 SD DATA 13 53 SD DATA 14 49 SD DATA 15 48 SD DATAJ2 17 SD 3 18 SD DATA 4 19 SD DATA 5 20 SD 21 SD DATA 7 41 SD 8 59 SD 58 SD LDOM 42 SD RAS N 45 SD UDAM 60 SD WE N 43 Flash Memory mat clone Pin Number FL ADDR O 125 FL ADDR 1 115 FL ADDR 2 84 FL ADDR 3 85 FL ADDR 4 86 FL ADDR 5 87 FL ADDR 6 88 TREX C1 DEVELOPMENT KIT Interfaces and Associated testing code FL ADDR 7 94 FL_ADDR 8 95 FL_ADDR 9 101 FL ADDR 10 102 FL ADDR 11 103 FL ADDR 12 104 FL ADDR 13 105 FL ADDR 14 106 FL ADDR 15 113 FL ADDR 16 114 FL ADDR 17 126 FL ADDR 18 96 FL ADDR 19 97 FL ADDR 20 100 FL CE N 83 FL DQ
40. it 2 drive oCOM 0 and oCOM 2 low and drive 0x58 on the bus Please refer to the Case B in Figure 5 2 05 67 01 drive low drive high oSEG oCOM 3 oCOM 2 oCOM 1 oCOM 0 Case A show number 2 on digit 0 by enabling bit 0 and driving 0x58 on databus oSEG7 0 oSEG7 1 oSEG7 oSEG 3 drive low gt drive high oSEG7 7 oCOM 3 oCOM 2 oCOM 1 oCOM 0 CaseB show number 2 on digit 0 and digit 2 by enabling bit 0 bit 2 and driving 0x58 on databus Figure 5 2 Two cases show how to display a number on a specific digit The Verilog Code for Combinational Lab Verilog Code for Case B in the Combinational Lab assign oCOM 0 1 b0 assign oCOM 1 1 b1 assign oCOM 2 1 b0 assign oCOM 3 1 b1 assign oSEG7 0101 1000 0x58 TREX C1 DEVELOPMENT KIT Lab 2 How to work with scanned 7 SEG Display Sequential Logic Lab use the scanned mode Please see Figure 5 3 lt lt The 2 bit counter is running at 400Mhz cannot be too fast or too slow to cheat our vision The counter s output CNT controls a MUX and a DEMUX The MUX has four inputs we supply the FOUR numbers that we would like to display on the four 7 SEG digits as the inputs The output of the MUX drives the common 7 SEG LED databus DeMUX has 1 input GND the FOUR outputs connect to the enable pins of the FOUR 7 SEG digits respectively osEG7 7
41. izard v Verify the USB Blaster driver is located in the Quartus II directory A Quartus directory gt drivers usb blaster If the driver is not in your directory 7 TREX C1 DEVELOPMENT KIT Installation lt lt lt download the USB Blaster driver from the Altera web site http www altera com support software drivers For Window 2000 choose Settings gt Control Panel Windows Start menu for Window XP choose Control Panel Window Start Menu Click Switch to Classic View if you are not in the classic view Double click the Add Hardware icon to start the Add hardware wizard and click Next to continue Select Yes have already connected the hardware and then click Next Select Add a new hardware device from the Installed hardware list Then click Next to continue Select Install from a list or specified location Advanced Click Next to continue Select Sound Video and game controllers Click Next to continue Select Have Disk and point to the location of the USB Blaster driver lt Quartus II directory gt drivers usb blaster Click OK Select Altera USB Blaster Click Next to install the driver Click Continue Anyway if there is any warning message Click Finish and reboot your PC to complete the process Potential Problems and Workaround for Using USB Blaster lt Redo the Hardware Selection step by clicking Hardware Setup button in the programmer menu Remove the USB Cable a
42. m file is downloaded directly to the FPGA chip AS Mode where POF bitstream is downloaded directly to the Flash based Serial Configuration device should be used only when the design is finalized or the design has to be tested without a PC Set the switch to PROG for AS mode Note that the switch position should be kept at RUN position for normal operation Perform the following steps TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Figure 4 7 Switch Position should be kept at RUN for JTAG Normal Operation 2 the programmer button is clicked the following programming window is popped up See Figure 4 8 Figure 4 8 Bitstream Programming Window 3 Click the Hardware Setup The Hardware Settings tab of the Hardware Setup dialog box is displayed USB Blaster is visible in the Available Hardware items list of the Hardware Setup dialog box as shown in Figure 4 9 4 Click USB Blaster to highlight it and then click the Select hardware button 16 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Hardware Setup Hardware Settings JTAG Settings Select o programmung hardware setup to we when programming devices This programamang hardware setup applies only to the current programmer window Currently selected hardware USB Bisster USB 0 Select Hardware I L ua Add Hardware Figure 4 9 Hardware Setup Menu for USB Blaster Click Close to close the Hardware Setup dialog
43. nd then plug in again Then you need to redo the Hardware Selection part for programming Exit Quartus II and restart it again If above workarounds do not solve your problem try to use the 9V DC power adapter because some of the USB ports on PC do not supply enough voltage current Install Terasic Lab CD ROM TREX C1 DEVELOPMENT KIT Installation Y Insert Terasic CD ROM into your CD ROM drive The menu shown in Figure 3 1 will pop up Y Click on Read Me First and then click on Install Software buttons which will install all the labs and API software into your C Terasic directory You might encounter a warning message regarding fonts as shown in Figure 3 2 Simply click on Ignore to continue v After the installation is complete you can access Terasic s lab examples and API using Window s program menu as shown in Figure 3 3 Y Read the User Guide and follow the instructions to exercise all the interesting labs we designed for you Thank you for choosing Terasic T REX C1 Development Kit Please follow the ins ions below to start using the board read T REX C1 Figure 3 1 Installation Menu of Terasic Lab CD ROM T REX CDROM V2 0 Installer Information x Error 1907 Could not register font Verify that you have sufficient permissions to install fonts and that the system supports this font Abort Retry Figure 3 2 Simply ignore the warning message for font if ther
44. rn TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel ON and OFF 7 SEG digits ln the top level RTL code New Flash v you will find the following code use 4 wires mExt IO 3 0 to turn OFF the 4 digit enable pins assign oCOM 3 0 m_oCOM 3 0 mExt 10 3 0 The 7 SEG display controller outputs 4 enable pins m oCOM SEG7 Driver u0 oSEG7 m oCOM mSEG7 DIG OSC 50 KEY 0 The CMD Decoder outputs mExt IO 7 0 according to the setup of the SW7 SWO in the TREX Control Panel CMD Decode u5 skip Ext Control Signals oExt lO mExt IO 36 TREX C1 DEVELOPMENT KIT Lab 4 CD Quality Music Box Chapter Lab 4 CD Quality Music Box This chapter introduces you how to repeat the lab of using the 16 bit CD quality audio DAC on the TREX board We will download a 1Mbyte long CD music stream to the FLASH memory and play the music repeatedly Load Another Music File to Play From Flash Check C Terasic Binary_Raw_Data directory There is 1Mbyte CD music data called 5thElement 1mbyte which is 1Mbyte long raw CD data N You can convert your MP3 file into a CD Raw Data file by using a free tool MP3 to WMA Converter from AudioUtilities Co Ltd Power up the board and make sure the SOF POF file in e Lab3 Control Panel is programmed into the FPGA Start TREX C1 Control Panel tool Following the Flash Programmer section in Chapter 6 to erase Flash
45. the port Note that you need to click the Configure button to enable the connection from the Flash Memory to the Asynchronous Port 1 of the Flash Controller indicated in Figure 6 11 Note Plug in your headset of speaker and you should hear the music played from the Audio DAC circuit Press KEY 1 to reset the Audio DAC circuit to remove the background noise sometime you need to press more than once until the background noise is removed Please refer to Figure 6 11 You should see the Asynchronous Port 1 is connected to the Audio DAC part Once you selected Asynchronous Port 1 and click the Configure button the AUDIO_DAC will talk to the Flash Memory directly In this example the AUDIO_DAC Verilog Module will read the content of the Flash memory and send it to the external audio chip Host Port SDRAM User Port 1 Controller Host Port User Port 3 Controller User Port 2 Audio DAC Controller User Port 1 Music Playing is done via the connection from User Port 1 to Audio DAC Controller 5 2 o 70 E E o u 23 2 o v e Virtual Switches Figure 6 11 Block Diagram of The Multi Port SDRAM Flash integration 32 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel me T REX Ci Control Panel Open Menu Help About LED amp PS2 FLASH SDRAM SDRAM Multiplexer Host USB Port FLASH Multiplexer Host USB Port Virtual DPDT Switches Con
46. this lab we are going to demonstrate a example where we run NIOS II 5 0 CPU on TREX C1 board and use a C software application to control the board Load NIOS II 5 0 on TREX C1 1 sure Lab8 NIOSII TREX in TREX CD ROM is installed to your project directory 2 Start Quartus II Software 3 Click File gt Open Project 4 Select C TerasiALab8 NIOSII TREXistandardistandard 5 Click on Programming button Setup the programming hardware to USB Blaster according to the instructions stated in Chapter 4 6 Select the standard sof stored in the Lab8 NIOSII TREX directory and download it to FPGA 7 Now you can use NIOSII IDE to control the board 8 Figure 11 1 shows the screen capture of SOPC Builder targeting NIOS II core in TREX C1 board TREX C1 DEVELOPMENT KIT Lab 8 NIOS II 5 0 Core 17 Altera SOPC Builder std 1520 File Module System View Tools Help m System Contents Nios More cpu Settings System Generation Altera SOPC Builder Target Create New Component Clock MHz Avalon Components Board Unspecified Board v 150 0 Nios Il Processor Alt Bridges Device Family Cyclone v Hard Communication Display EP1C20 Nios Developn Use Module Name Description Clock Base EP1S10 Hios Developrr v cpu Nios Il Processor Altera Corporation ji 0x02120000 EP1S40 Hios
47. tial Write Address fg Length o File Length Write File To Flash Sequential Read Address n Length n Entrie Flash Load Flash Content to File Figure 6 1 TREX Control Panel Concept Diagram 2 Make sure that you have programmed the board with the C Terasic Lab3_TREX_Panel New_Flash multiplexer New Flash sof 3 Start the TREX C1 Control Panel program located in your C Terasic The user interface shown in Figure 6 2 should appear 25 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel me T REX CI Control Panel Open Menu Help About Figure 6 2 TREX Control Panel 4 Click Open gt Open USB 0 TREX Control Panel Application will list all the USB ports that connect to TREX boards TREX Control Panel can control up to 4 TREX boards using the USB links Figure 6 3 shows the concept of how to connect multiple TREX boards Note that The Control Panel will occupy the USB port until you close the port you cannot use Guartus II to download unless you close the USB port Control Panel can control up to 4 TR1 boards Great scalability for large projects Figure 6 3 TREX Control Panel can control up to 4 TREX C1 boards 5 Refer to Figure 6 4 Click on the check boxes of D3 D4 D7 and DO Then click on Refresh You will find that that the LED3 LED4 LED7 and LEDO 26 TREX C1 DEVELOPMENT KIT Lab 3 TREX Control Panel are lighted up Also you can change the numbers in DIG3 D
48. tion Nios II Hardware Nios II Terminal Window 8 1 05 12 25 AM Button 4 503 Pressed LED3 is ON All Buttons 500 503 were pressed at least once loop will be run until all buttons switches have been pressed NOTE Once a button press has been detected the corresponding LED Button 1 SWO Pressed LEDO is ON Button 3 502 Pressed LED2 is ON are under C Documents and Settings User Accounti sopc builder Therefore the NIOSII IDE will NOT work if your Window home directory is NOT under C Documents and Setting User Accounti sopc builder Figure 11 4 The results of running the example NOTE Is the example NOT working in your environment The NIOSII IDE environment assumes users home directories for SOPC Builder 62 TREX C1 DEVELOPMENT KIT Appendix Appendix Revision History Date Author Change Log April 18 2005 Initial Version Preliminary Sean Peng June 20 2005 V1 2 Sean Peng 1 Provide USB version of the API 2 Added SDRAM features 3 Added multi port Flash SDRAM controllers and associated applications 4 gt Added source code of the TREX Control Panel RS232 version 5 Restructured the CD ROM directory layout and added more code examples July 20 2005 V1 3 Sean Peng 1 Add TV lab and NIOSII IDE Lab examples 2 Use Autorun for CD ROM installation TREX CD ROM Directory Structure and Reference Designs TREX1 boar
49. ttern displayed on the 7 SEG module is changing 5 secs after bitstream downloading you will see all the segments of the 7 SEG module are ON Also the LEDs will be turned off if there is NO error You can redo the test by pressing KEY1 The same testing pattern will be repeated Use tool like Hex WorkShop to examine the content of the CF card Figure 9 4 shows the content of the CF card viewed by Hex Workshop Note that the bytes the test program filled in is incremented from 0000 to OOFF in a 256 byte sector the 5 sector a F n lt lt alr 00000000 0800 00000020 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 1400 1800 1600 00000040 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 2400 2800 2200 00000060 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 3400 3B00 3 00 BOO 4 00 BOO 5 00 BOO 6 00 BOO 7 00 BOO 8 00 0000012019000 9100 9200 9300 9400 9500 9600 9700 9800 9900 9400 9800 9800 9000 00000140 000 A100 A200 A300 4400 4500 4600 A700 800 900 00 4000 00000160 8000 B100 B200 B300 B400 B500 B600 B700 B800 B900 00 000 00000180 C000 C100 C200 C300 C400 C500 C600 C700 C800 C900 00 CBOO 00 00000140 D000 D100 D200 D300 D400 D500 D600 D700 0800 D900 0000 000001 0 000 E100 E200 E300 E400 E500 E600 E700 E800 E900 00 00 ECOO EDOO 00
50. zard Project Convert MAX PLUS II Project ws Create Update Convert Programming Files Figure 4 5 Open the menu for Converting Programming Files Refer to Figure 4 6 In the Convert Programming Files Menu Select 5188 as our configuration devices change the output File name to your desired name with POF extension click on SOF Data label and click on Add File button Select New Flash sof Click on New Flash sof to highlight it and Click on Properties Check the Compression box in the pop up window click OK in the pop up window and OK again in the Convert Programming Files window 14 TREX C1 DEVELOPMENT KIT First Lab 7 SEG Display Y can abo anger ie mdommako om Si file to gene ae MANN m other files soir zip hank dor Conversion setup files Open Conversion Setup Dats Save Conversion Setup Output programming file Programming file type Programmer Object Fle po Configwation device EPCSISIS Mode Actve Senal Configuaton v CiprojectVLabl_PowerUpMew Fashpof Remote Local update difference fJ v Memory Map File Figure 4 6 Convert Programming Files Download Bitstream qu 1 TREX board uses USB Blaster to download bitstream We supports both JTAG mode and Active Serial Programming mode AS mode By default the switch is set to the position of RUN for JTAG mode so that the SOF bistrea

TREX C1 User Guide 20050802

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