bdiGDB User Manual
Contents
1. BDI gt unlock 0x00000000 0x20000 256 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 440 7450 864 1 User Manual 33 3 2 5 Part REGS In order to make it easier to access target registers via the Telnet interface the BDI can read in a register definition file In this file the user defines a name for the register and how the BDI should access it e g as memory mapped memory mapped with offset The name of the register defi nition file and information for different registers type has to be defined in the configuration file The register name type address offset number and size are defined in a separate register definition file An entry in the register definition file has the following syntax name type addr name type addr size SWAP size SWAP The name of the register max 15 characters The register type GPR General purpose register SPR Special purpose register CCSR Relative to CCSRBAR memory mapped register The BDI knows the current position of the CCSR space MM Absolute direct memory mapped register DMM1 DMM4 Relative direct memory mapped register IMM1 IMM4 Indirect memory mapped register The address offset or number of the register The size 8 16 32 of the register default is 32 If present the bytes of a 16bit or 32bit register are swapped This is useful to access little endian ordered registers e g PCI bridge configuration reg2. Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 27 3 2 3 Part HOST The part HOST defines some host specific values IP ipaddress The IP address of the host ipaddress the IP address in the form xxx xxx xxXX XXX Example IP 151 120 25 100 FILE filename The default name of the file that is loaded into RAM using the Telnet load command This name is used to access the file via TFTP If the filename starts with a this is replace with the path of the configuration file name filename the filename including the full path or for relative path Example FILE F gnu demo ppc test elf FILE test elf FORMAT format offset The format of the image file and an optional load address offset If the im age is already stored in ROM on the target select ROM as the format The optional parameter offset is added to any load address read from the im age file format SREC BIN AOUT ELF IMAGE or ROM Example FORMAT ELF FORMAT ELF 0x10000 LOAD mode In Agent mode this parameters defines if the code is loaded automatically after every reset mode AUTO MANUAL Example LOAD MANUAL START address The address where to start the program file If this value is not defined and the core is not in ROM the address is taken from the image file If this val ue is not defined and the core is already in ROM the PC will not be set before starting the program file This means the
3. bdisetup v p dev ttyS0O b57 BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware unknown Logic unknown MAC 00 Oc 01 92 15 21 IP Addr 255 255 255 255 Subnet 255s255 255 255 Gateway 255 255 255 255 Host IP 255 255 255 255 Config 22222222222222722 3 Load Update the BDI firmware logic With bdisetup u the firmware is loaded and the CPLD within the BDI2000 is programmed This con figures the BDI for the target you are using Based on the parameters a and t the tool selects the correct firmware logic files If the firmware logic files are in the same directory as the setup tool there is no need to enter a d parameter root LINUX_1 bdisetup bdisetup u p dev ttyS0O b57 aGDB tMPC7450 Connecting to BDI loader Erasing CPLD Programming firmware with b20pwsgd 100 Programming CPLD with copjed21 102 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 14 4 Transmit the initial configuration parameters With bdisetup c the configuration parameters are written to the flash memory within the BDI The following parameters are used to configure the BDI BDI IP Address The IP address for the BDI2000 Ask your network administrator for as signing an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Subnet Mask The subnet mask of the network where the BDI i
4. select MCCR1 WM32 OXFEEOOOOO 0x0000e075 do not set MEMGO WM32 OxFECO0000 Oxf4000080 select MCCR2 WM32 OxFEE00000 Oxcc044004 WM32 OxFECO0000 Ox 8000080 select MCCR3 WM32 OxFEE00000 0x00004078 A WM32 OxFECO0000 Oxfc000080 select MCCR4 WM32 OxFEE00000 0x39323235 WM32 OxFEC00000 0xf0000080 select MCCR1 WM32 OXFEEOOOOO 0x0000e875 now set MEMGO WM32 OxFECO0000 0x78000080 select EUMBBAR WM32 OXFEEOOOOO 0x000000fc Embedded utility memory block at OxFC000000 WM32 OxFECO0000 0xa8000080 select PICR1 WM32 OxFEE00000 0x901014ff enable flash write Flash on processor bus TARGET CPUTYPE 7450 the CPU type 7450 JTAGCLOCK 1 use 8 MHz JTAG clock WORKSPACE 0x00000000 workspace in target RAM for data cache flush and L3PM access BDIMODE AGENT the BDI working mode LOADONLY AGENT GATEWAY BREAKMOD SOF SOFT or HARD HARD uses PPC hardware breakpoint DCACHE NOFLUSH data cache flushing FLUSH NOFLUSH HOST IP 151 120 25 115 FILE E cygnus root usr demo mpc7450 vmlinux FORMAT IMAGE LOAD ANUAL load code MANUAL or AUTO after reset Based on the information in the configuration file the target is automatically initialized after every re set Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 5 2 Installation 2 1 Connecting the BDI2000 to Target The cable to the target system is a 16 pin flat ribbon cable In case where the target system
5. 120 25 101 Ask your network administrator for assigning an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Enter the subnet mask of the network where the BDI is connected to Use the following format xxx xxx xxX XxxX 9 255 255 255 0 A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Enter the full path and name of the configuration file e g D gnu config bdi ads8260bdi cnf For information about the syntax of the configuration file see the bdiGDB User manual This name is transmitted to the TFTP server when reading the configuration file Click on this button to store the configuration in the BDI2000 flash memory 2 5 3 Recover procedure In rare instances you may not be able to load the firmware in spite of a correctly connected BDI error of the previous firmware in the flash memory Before carrying out the following procedure check the possibilities in Appendix Troubleshooting In case you do not have any success with the tips there do the following e Switch OFF the po
6. Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 37 3 3 5 Target serial VO via BDI A RS232 port of the target can be connected to the RS232 port of the BDI2000 This way it is possible to access the target s serial VO via a TCP IP channel For example you can connect a Telnet session to the appropriate BDI2000 port Connecting GDB to a GDB server stub running on the target should also be possible Target System RS232 Connector 1 CD 2 RXD 3 TXD 4 DTR 5 GROUND 6 DSR 7 RTS 8 CTS 9 RI XXX BDI Output m The configuration parameter SIO is used to enable this serial VO routing The used framing parameters are 8 data 1 stop and not parity The BDI asserts RTS and DTR when a TCP connection is established Ethernet 10 BASE T E TARGET SIO 7 9600 Enable SIO via TCP port 7 at 9600 baud Warning Once SIO is enabled connecting with the setup tool to update the firmware will fail In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 38 3 3 6 Embedded Linux MMU Support The bdiGDB system supports Linux kernel debugging when MMU is on The MMU configuration pa rameter enables this mode of operation In this mod
7. RUN is entered as a second pa rameter the loaded application will be started immedi ately otherwise only the PC is set and BDI waits for GDB requests Example BDIMODE AGENT RUN STARTUP mode runtime mode This parameter selects the target startup mode The second mode defines how to handle the second e600 core in the MPC8641 D Not all mode com binations are supported See chapter about Dual Core support The following modes are supported HALT This default mode forces the target to debug mode im mediately out of reset No code is executed after reset STOP In this mode the BDI lets the target execute code for runtime milliseconds after reset This mode is useful when monitor code should initialize the target system RUN After reset the target executes code until stopped by the Telnet halt command Example STARTUP STOP 3000 let the CPU run for 3 seconds BOOTADDR address The boot address for PowerPC is OxFFFOO100 By default the BDI sets a hardware breakpoint at this address to freeze the processor immediately out of reset You may change this initial breakpoint address address the address where to set the startup breakpoint Example BOOTADDR OxFFF00120 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 24 WORKSPACE address BREAKMODE mode V STEPMODE mode VECTOR CATCH DCACHE mode The BDI needs a workspace of 256 bytes in target RAM
8. This default is compatible with older GDB versions The following names are use to select a register group STD The standard old register block The FPR registers are not read from the target but transferred You can t disable this register group FPR The floating point registers are read and transferred SR The segment registers BAT The IBAT and DBAT registers SPR The additional special purpose registers AUX currently not used ALL Include all register groups Example REGLIST STD only standard registers REGLIST STD FPR SPR all except SR and BAT SIO port baudrate When this line is present a TCP IP channel is routed to the BDI s RS232 connector The port parameter defines the TCP port used for this BDI to host communication You may choose any port except 0 and the default Telnet port 23 On the host open a Telnet session using this port Now you should see the UART output in this Telnet session You can use the normal Telnet connection to the BDI in parallel they work completely inde pendent Also input to the UART is implemented port The TCP IP port used for the host communication baudrate The BDI supports 2400 115200 baud Example SIO 7 9600 TCP port for virtual lO QACK LOW When this line is present the BDI forces the QACK pin pin 2 on the COP connector low By default this pin is not driven by the BDI Maybe useful for PPC750 and PPC7400 targets Example QACK LOW force QACK low via COP connector
9. allows to define a delay time in ms the BDI inserts between releasing the COP HRESET line and starting communicating with the target This init list entry may be necessary if COP HRESET is de layed on its way to the PowerPC reset pin time the delay time in milliseconds Example WAKEUP 3000 insert 83sec wake up time For slow memory it may be necessary to increase the number of clocks used to execute a memory access cycle If for example you cannot access boot ROM content with the default configuration of your memory control ler define additional memory access clocks clocks additional number of CPU clocks for a memory access Example MEMDELAY 2000 additional memory access clocks Defines the base address and size of the L3 cache private memory Be cause L3 cache private memory cannot be accessed directly via JTAG the BDI loads some support code into the workspace and uses it to access this memory range Therefore a workspace is necessary to access this memory range Example L3PM 0x01000000 0x100000 1MB L3 private memory In order to support Linux kernel debugging when MMU is on the BDI translates effective virtual to physical addresses This translation is done based on the current MMU configuration BAT s and page tables If this configuration line is present and address relocation active MSR bits IR DR the BDI translates the addresses received from GDB before it ac cesses physical memory The optional parameter define
10. has an appropriate connector the cable can be directly connected The pin assignment is in accordance with the PowerPC COP connector specification In order to ensure reliable operation of the BDI EMC runtimes etc the target cable length must not exceed 20 cm 8 Target System 1 15 Du mice G a COP JTAG Connector gt BEBE lt 7 i 1 TDO 2 16 3 TDI 4 TRST 6 Vcc Target 7 TCK A TARGET B 15 1 9 TMS ae ee E D E E E E ee eer 11 SRESET 16 2 12 GROUND 13 HRESET The green LED TRGT marked light up when target is powered up 16 GROUND For BDI TARGET B connector signals see table on next page Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450 864 1 User Manual 6 BDI TARGET B Connector Signals Describtion JTAG Test Data Out This input to the BDI2000 connects to the target TDO pin QACK This output of the BDI2000 connects to the target QACK pin By default this pin is not driven by the BDI2000 With an entry in the configuration file it can be forced low JTAG Test Data In This output of the BDI2000 connects to the target TDI pin JTAG Test Reset This output of the BDI2000 resets the JTAG TAP controller on the target General purpose Input This input to the BDI2000 connects to the target HALTED pin Currently not used Vcc Target 1 8 5 0
11. if you enter ERASE at the Telnet prompt without any parameter This list is also used if you enter UNLOCK at the Telnet without any parameters With the in crement and count option you can erase multiple equal sized sectors with one entry in the erase list address Address of the flash sector block or chip to erase increment If present the address offset to the next flash sector count If present the number of equal sized sectors to erase mode BLOCK CHIP UNLOCK Without this optional parameter the BDI executes a sec tor erase If supported by the chip you can also specify a block or chip erase If UNLOCK is defined this entry is also part of the unlock list This unlock list is processed if the Telnet UNLOCK command is entered without any parameters wait The wait time in ms is only used for the unlock mode Af ter starting the flash unlock the BDI waits until it pro cesses the next entry Example ERASE Oxff040000 erase sector 4 of flash ERASE Oxff060000 erase sector 6 of flash ERASE Oxff000000 CHIP erase whole chip s ERASE Oxff010000 UNLOCK 100 unlock wait 100ms ERASE Oxff000000 0x10000 7 erase 7 sectors Example for the ADS8260 flash memory FLASH CHIPTYPE I28BX8 CHIPSIZE 0x200000 BUSWIDTH 32 WORKSPACE 0x04700000 Flash type The size of one flash chip in bytes e g AM29F010 0x20000 The width of the flash memory bus in bits 8 16 32 64 workspace in dual port RA
12. isters The following entries are supported in the REGS part of the configuration file FILE filename DMMn base IMMn addr data Remark The name of the register definition file This name is used to access the file via TFTP The file is loaded once during BDI startup filename the filename including the full path Example FILE C bdi regs mpc8260 def This defines the base address of direct memory mapped registers This base address is added to the individual offset of the register base the base address Example DMM1 0x01000 This defines the addresses of the memory mapped address and data reg isters of indirect memory mapped registers The address of a IMMn regis ter is first written to addr and then the register value is access using data as address addr the address of the Address register data the address of the Data register Example DMM1 0x04700000 The registers msr cr iar and acc and are predefined Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 34 Example for a register definition MPC107 Entry in the configuration file REGS DMM1 OXFCOOOOOO Embedded utility memory base address IMM1 OXFECOOOOO OXFEEOO0OO0O configuration registers at byte offset 0 IMM2 OXFECOOOOO OXFEEOOOO1 configuration registers at byte offset 1 IMM3 OXFECOOOOO OXFEEOO0O002 configuration registers at byte offset
13. space via JTAG can lead to a deadlock this entry can be used to define up to 32 valid memory rang es If at least one memory range is defined the BDI checks against this range s and avoids accessing of not mapped memory ranges start the start address of a valid memory range end the end address of this memory range Example MMAP OXFFEOOOOO 0xFFFFFFFF Boot ROM Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 23 3 2 2 Part TARGET The part TARGET defines some target specific values For MPC8641 do not use parameters marked with a CPUTYPE type NOBURSTREAD This value gives the BDI information about the connected CPU If neces sary burst memory read accesses via JTAG can be disabled but this will slow down memory read performance dramatically type 7450 7451 7441 7455 7445 7457 7447 7448 8641 Example CPUTYPE 7450 JTAGCLOCK value With this value you can select the JTAG clock rate the BDI2000 uses when communication with the target CPU value 0 16 6 MHz 1 8 3 MHz 2 5 5 MHz 3 4 1 MHz Example CLOCK 1 JTAG clock is 8 3 MHz BDIMODE mode param This parameter selects the BDI debugging mode The following modes are supported LOADONLY Loads and starts the application core No debugging via JTAG port AGENT The debug agent runs within the BDI There is no need for any debug software on the target This mode accepts a second parameter If
14. special purpose register display segment register display vector register modify general purpose or user defined register modify special purpose register modify segment register modify vector register four 32bit values display L1 data cache content display L2 cache content display L1 DTAG values display L1 ITAG values reset the target system change startup mode display or set current breakpoint mode set PC and start target system trace on instuction single step trace on change of flow force target to enter debug mode set instruction hardware breakpoint clear instruction hardware breakpoint s set data watchpoint via DABR DABR BT 0 set data watchpoint via DABR DABR BT 1 clear data watchpoint s display information about the current state lt offset gt lt file gt lt format gt load program file to target memory lt offset gt lt file gt lt format gt verify a program file to target memory lt offset gt lt file gt lt format gt program flash memory lt format gt SREC BIN AOUT or ELF erase a flash memory sector chip or block CHIP BLOCK or SECTOR default is sector erase multiple flash sectors unlock a flash sector unlock multiple flash sectors change flash configuration delay for a number of milliseconds change the current core change IP address of the host defines a new prompt
15. string display or update BDI configuration lt file gt lt hostIP gt lt bdiIP gt lt gateway gt lt mask gt display command list enable disable JTAG memory access via SAP reboot the BDI and reload the configuration terminate the Telnet session Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 42 3 5 Dual Core Support for MPC8641D The bdiGDB system supports concurrent debugging of the two e600 cores present in the MPC8641D For every core you can start its own GDB session The port numbers used to attach the remote targets are 2001 and 2002 In the Telnet you switch between the cores with the command select 0 1 In the configuration file simply begin the init list line with the appropriate core number If there is no n in front of a line the BDI assumes core 0 INIT init core register 0 WREG MSR 0x00001002 MSR ME RI Q WSPR 1008 0x84000000 HIDO disable cache set TBEN bit Q WSPR 1017 0x00000000 L2CR disable L2 cache 1 WREG MSR 0x00001002 MSR ME RI 1 WSPR 1008 0x84000000 HIDO disable cache set TBEN bit The BDI supports different startup modes The startup mode is defined via an entry in the TARGET section of the BDI configuration file The second e600 core core 1 is handled by the BDI only if there is a second mode parameter present in the STARTUP line Because after reset
16. supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not support the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets 0x10 for chip erase 0x30 for sector erase 0x50 for block erase To speed up programming of Intel Strata Flash and AMD MirrorBit Flash an additional algorithm is implemented that makes use of the write buffer This algorithm needs a workspace otherwise the standard Intel AMD algorithm is used The following table shows some examples Chipsize Am29F010 AM29F 5 0x020000 Am29F800B AM29BX8 AM29BX16 5 0x100000 Am29DL323C AM29BX8 AM29BX16 0x400000 Am29PDL128G AM29DX16 AM29DX32 0x01000000 Intel 28F032B3 I28BX8 s E 0x400000 Intel 28F640J3A STRATAX8 STRATAX16 E 0x800000 Intel 28F320C3 128BX16 E 0x400000 AT49BV040 AT49 0x080000 AT49BV1614 AT49X8 AT49X16 0x200000 M58BW016BT M58X32 0x200000 SST39VF160 AT49X16 0x200000 Am29LV320M MIRRORX8 MIRRORX16 x 0x400000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 32 Note Some Intel flash chips e g 28F800C3 28F160C3 28F320C3 power up with all blocks in locked state In order to erase program
17. the Telnet prog command This name is used to access the file via TFTP If the file name starts with a this is replace with the path of the configuration file name This name may be overridden interactively at the Telnet interface filename the filename including the full path or for relative path Example FILE F gnu ppc bootrom hex FILE bootrom hex The format of the file and an optional address offset The optional param eter offset is added to any load address read from the program file You get the best programming performance when using a binary format BIN AOUT ELF or IMAGE format SREC BIN AOUT ELF or IMAGE Example FORMAT BIN 0x10000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 30 WORKSPACE address If a workspace is defined the BDI uses a faster programming algorithm that runs out of RAM on the target system Otherwise the algorithm is pro cessed within the BDI The workspace is used for a 1kByte data buffer and to store the algorithm code There must be at least 2kBytes of RAM avail able for this purpose address the address of the RAM area Example WORKSPACE 0x00000000 ERASE addr increment count mode wait The flash memory may be individually erased or unlocked via the Telnet interface In order to make erasing of multiple flash sectors easier you can enter an erase list All entries in the erase list will be processed
18. the second core is disabled the BDI writes to the MCMPCR and enables it in cases where HALT is selected as startup mode for the second core Following some examples STARTUP HALT HALT The second core will be enabled via MCMPCR and both core are halted at the reset vector via an IABR breakpoint STARTUP RUN RUN Both core are let running after reset You can halt them individually via the Telnet halt command The BDI does not write to MCMPCR Halting the second core will only succeed if it has been enabled form the code running on the first core The init list is not processed in this case STARTUP STOP 4000 HALT The second core will be enabled via MCMPCR and halted at the reset vector via an IABR breakpoint The first core is let running for 4 seconds and the halted STARTUP STOP 4000 STOP Both core are let running after reset for 4 seconds and the halted The BDI does not write to MC MPCR Halting the second core will only succeed if it has been enabled form the code running on the first core during this 4 second runtime After halting the init list is processed STARTUP HALT RUN Useful if you want to debug boot code on core 0 but want to be able to access core 1 later The BDI does not write to MCMPCR in this case STARTUP RUN HALT The first core is let running while the second core will be enabled via MCMPCR and halted at the reset vector via an ABR breakpoint Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi fo
19. w1 0_0010b000 VD 0010b000 0010b004 0010b008 0010b00c 0010b010 0010b014 0010b018 0010b01c W2 0_00111000 V 00111000 00111004 00111008 0011100c 00111010 00111014 00111018 0011101c W3 0_0010d000 VD 0010d000 0010d004 0010d008 0010d00c 0010d010 0010d014 0010d018 0010d01c Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 440 7450 864 1 User Manual 44 4 Specifications Operating Voltage Limiting Power Supply Current RS232 Interface Baud Rates Data Bits Parity Bits Stop Bits Network Interface Serial Transfer Rate between BDI and Target Supported target voltage Operating Temperature Storage Temperature Relative Humidity noncondensing Size Weight without cables Host Cable length RS232 5 VDC 0 25 V typ 500 mA max 1000 mA 9 600 19 200 38 400 57 600 115 200 8 none 1 10 BASE T up to 16 Mbit s 1 8 5 0 V 3 0 5 0 V with Rev B 5 60 C 20 CO 65 C lt 90 rF 190 x 110 x 35 mm 420g 2 5m Specifications subject to change without notice Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450 864 1 User Manual 45 5 Environmental notice N es Disposal of the equipment must be carried out at a designated disposal site 6 Declaration of Conformity CE CE DECLARATION OF CONFORMITY This declaration is valid for follow
20. 110 60000000 60000000 60000000 60000000 i g g Notes The DUMP command uses TFTP to write a binary image to a host file Writing via TFTP on a Linux Unix system is only possible if the file already exists and has public write access Use man tftpd to get more information about the TFTP server on your host The BI command sets a hardware breakpoint via the IABR register IABR TE must be equal MSR IR in order for a match to be signalled IABR TE is set when the parameter V is present in the BREAK MODE configuration Otherwise it is cleared You can override this default setting with the optional parameter v virtual sets TE or p physical clears TE Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 AR for BDIZ000 PowerPC 440 7450 864 1 User Manual 47 The Telnet commands PHYS lt address gt MD D MDH B RDUMP DVR lt address gt lt count gt lt address gt lt count gt lt address gt lt count gt lt address gt lt count gt DUMP lt addr gt lt size gt lt file gt MM lt addr gt lt value gt lt cnt gt MMD lt addr gt lt value gt lt cnt gt MMH lt addr gt lt value gt lt cnt gt MMB lt addr gt lt value gt lt cnt gt lt address gt lt count gt lt name gt lt file gt DSPR lt number gt DSR lt number gt lt number gt lt nbr gt lt name gt lt value gt SPR lt number gt
21. 2 TMMA OXFECOOOOO OXFEEOO0003 configuration registers at byte offset 3 FILE E cygnus root usr demo sp7450 mpc107 def The register definition file name type addr size i gpro GPR 0 sp GPR I i xer SPR 1 lr SPR 8 Ctr SPR 9 sprg0 SPR 272 sprgl SPR 273 sprg2 SPR 274 sprg3 SPR 275 i i IMMx must be set to the configuration registers r vendor IMM1 0x00000080 16 SWAP device IMM3 0x00000080 16 SWAP 1mbar IMM1 0x10000080 32 SWAP pmeri IMM1 0x70000080 16 SWAP pmcr2 IMM3 0x70000080 8 oder TMMA 0x70000080 8 cder IMM1 0x74000080 16 SWAP eumbbar IMM1 0x78000080 32 SWAP msarl IMM1 0x80000080 32 SWAP Now the defined registers can be accessed by name via the Telnet interface BDI gt rd Imbar BDI gt rm sprg0 OxFF801801 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 35 3 3 Debugging with GDB Because the target agent runs within BDI no debug support has to be linked to your application There is also no need for any BDI specific changes in the application sources Your application must be fully linked because no dynamic loading is supported 3 3 1 Target setup Target initialization may be done at two places First with the BDI configuration file second within the application The setup in the configuration file must at least enable access to the target memory where the application will be loaded Disable the w
22. 34 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 13 2 5 1 Configuration with a Linux Unix host The firmware logic update and the initial configuration of the BDI2000 is done with a command line utility In the ZIP Archive bdisetup zip are all sources to build this utility More information about this utility can be found at the top in the bdisetup c source file There is also a make file included Starting the tool without any parameter displays information about the syntax and parameters A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 Following the steps to bring up a new BDI2000 1 Build the setup tool The setup tool is delivered only as source files This allows to build the tool on any Linux Unix host To build the tool simply start the make utility root LINUX_1 bdisetup make CC 02 c o bdisetup o bdisetup c cc 02 c o bdicnf o bdicnf c cc 02 c o bdidll o bdidll c cc s bdisetup o bdicnf o bdidll o o bdisetup 2 Check the serial connection to the BDI With bdisetup v you may check the serial connection to the BDI The BDI will respond with infor mation about the current loaded firmware and network configuration Note Login as root otherwise you probably have no access to the serial port root LINUX_1 bdisetup
23. AG connector of the target system see chapter 2 e Target system initialization is not correctly gt enter an appropriate target initialization list e An incorrect IP address was entered BDI2000 configuration BDM JTAG signals from the target system are not correctly short circuit break e The target system is damaged Problem Network processes do not function loading the firmware was successful Possible reasons e The BDI2000 is not connected or not correctly connected to the network LAN cable or media converter e An incorrect IP address was entered BDI2000 configuration Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 440 7450 864 1 User Manual 48 B Maintenance The BDI needs no special maintenance Clean the housing with a mild detergent only Solvents such as gasoline may damage it If the BDI is connected correctly and it is still not responding then the built in fuse might be damaged in cases where the device was used with wrong supply voltage or wrong polarity To exchange the fuse or to perform special initialization please proceed according to the following steps A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF 1 1 Unplug the cables Swiss Made BDl2000 AG F 2 1 Remove the two plastic ca
24. Aa JTAG debug interface for GNU Debugger PowerPC 7440 7480 3644 User Manual Manual Version 1 10 for BDI2000 AAR N 1997 2006 by Abatron AG ldi for BDIZ000 PowerPC 7440 7450 864 1 User Manual 2 1 ntrod cti n EE EE EE EE EE N OE arnasa A ua raaa nana Aasa naani Re niaaa a Rani 3 id BDI2000 oe se Me ES EE N et ee ee eee EE 3 1 2 BDI Configuration ee ED eS Ge aa Ie EE EE GE Ge Ee AE EE oe EE 4 2 Eie EE N EE anes eine dts Ee ee cae NP OE Ne 5 2 1 Connecting the BDI2000 to Vea arcsec access EE GE AE eats EE EE ee EE Ee eee 5 2 1 1 Changing Target Processor Type esse ee see AE RA AA Re ed AR Ge ee ee Ge ee ee AA ee ee 7 2 2 Connecting the BDIZ000 to Power SUBPIY issie GEE Re EENS Es eed Kak es ES EER EE EES EERS RR GOGGA KE eens 8 2 3 Status LED MODE ate aas sesse ee ete eg be ore Reese Re ee SERE Ee eee 9 24 Connecting the BDI200D to Hos ses isi SES EENDE KERKE Ge Ne N GES GREG END Ges GR Re ede 10 2 4 1 Serial line COMMUNICATION ee ee ee ee ee RA AA AR AR ee ee ee ee 10 242 Ethernet communication EE RS EER Ee nee AR Rd DER Rd OG Ee Re GER RAS EE ED 11 2 5 Initial configuration of the DAIGDB system esse ee ek ee RR ee ee ee ee ee ee ee ee ek ee ee ee 12 2 5 1 Configuration with a Linux UNIX hOSt ese ee ee RA Re ee ee ee ee ee de ee ee ee ee ee ee 13 2 5 2 Configuration with a Windows HoSt issSEEe EE ie ss acted EG RA EE oR ee e 15 2 5 3 Recover Doos is EE Ee EE EE ER ROER ee Ee ie DE RR NE
25. ED MODE The built in LED indicates the following BDI states MODE LED BDI STATES The BDI is ready for use the firmware is already loaded The power supply for the BDI2000 is lt 4 75VDC The BDI loader mode is active an invalid firmware is loaded or loading firmware is active Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 10 2 4 Connecting the BDI2000 to Host 2 4 1 Serial line communication Serial line communication is only used for the initial configuration of the bdiGDB system The host is connected to the BDI through the serial interface COM1 COM4 The communication cable included between BDI and Host is a serial cable There is the same connector pinout for the BDI and for the Host side Refer to Figure below RS232 Connector Target System for PC host PPC OO 2 RXD data from host 3 TXD data to host RS232 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 77 2 4 2 Ethernet communication The BDI2000 has a built in 10 BASE T Ethernet interface see figure below Connect an UTP Un shilded Twisted Pair cable to the BD2000 For thin Ethernet coaxial networks you can connect a commercially available media converter BNC gt 10 BASE T between your network and the BDI2000 Cont
26. M FILE E gnu demo ads8260 bootrom hex The file to program ERASE OxFF900000 erase sector 4 of flash SIMM LH28F016SCT ERASE OxFF940000 erase sector 5 of flash SIM ERASE OxFF980000 erase sector 6 of flash SIMM ERASE OxFF9c0O000 erase sector 7 of flash SIMM the above erase list maybe replaces with ERASE OxFF 900000 Ox40000 4 erase sector 4 to 7 of flash SIMM Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 31 Supported Flash Memories There are currently 3 standard flash algorithm supported The AMD Intel and Atmel AT49 algorithm Almost all currently available flash memories can be programmed with one of this algorithm The flash type selects the appropriate algorithm and gives additional information about the used flash For 8bit only flash AM29F MIRROR 128BX8 AT49 For 8 16 bit flash in 8bit mode AM29BX8 MIRRORX8 I28BX8 STRATAX8 AT49X8 For 8 16 bit flash in 16bit mode AM29BX16 MIRRORX16 I28BX16 STRATAX16 AT49X16 For 16bit only flash AM29BX16 28BX16 AT49X16 For 16 32 bit flash in 16bit mode AM29DX16 For 16 32 bit flash in 32bit mode AM29DX32 For 32bit only flash M58X32 The AMD and AT49 algorithm are almost the same The only difference is that the AT49 algorithm does not check for the AMD status bit 5 Exceeded Timing Limits Only the AMD and AT49 algorithm support chip erase Block erase is only
27. V This is the target reference voltage It indicates that the target has power and it is also used to create the logic level reference for the input comparators It also controls the output logic levels to the target It is normally fed from Vdd I O on the target board 3 0 5 0V with Rev B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less TCK JTAG Test Clock This output of the BDI2000 connects to the target TCK pin lt reseved gt TMS JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line lt reseved gt SRESET Soft Reset This open collector output of the BDI2000 connects to the target SRESET pin GROUND System Ground HRESET Hard Reset This open collector output of the BDI2000 connects to the target HRESET pin lt reseved gt IN1 General purpose Input This input to the BDI2000 connects to the target CKSTP_OUT pin Currently not used GROUND System Ground Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 7 2 1 1 Changing Target Processor Type Before you can use the BDI2000 with an other target processor type e g CPU32 lt gt PPC a new setup has to be done see chapter 2 5 During this process the target cable must be disconne
28. act your network administrator if you have questions about the network Target System 10 BASE T Connector 1 TD 2 TD 3 RD LI TX RX 10 BASE T 6 RD BDI2000 PC Unix Host i The following explains the meanings of the built in LED lights Ethernet 10 BASE T LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450 864 1 User Manual 12 2 5 Initial configuration of the bdiGDB system On the enclosed diskette you will find the BDI configuration software and the firmware logic required for the BDI2000 For Windows users there is also a TFTP server included The following files are on the diskette b20pwsgd exe Configuration program 16bit Windows application b20pwsgd hlp Windows help file for the configuration program b20pwsgd xxx Firmware for the BDI2000 copjed20 xxx JEDEC file for the BDI2000 Rev B logic device when working with a COP target copjed21 xxx JEDEC file for the BDI2000 Rev C logic device when working with a COP target tftpsrv exe TFTP server fo
29. ader mode the bdisetup v s can be used You may also power off the BDI wait some time 1min and power on it again to exit loader mode root LINUX_1 bdisetup bdisetup v p dev ttyS0O b57 s BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware V1 00 bdiGDB for MPC7450 Logic V1 02 PPC6xx PPC7xx MAC 00 Oc 01 92 15 21 IP Addr 151 120 25 101 Subnet i 259 29522595 255 Gateway 255 255 255 255 Host 1p lt 151 120 25 118 Config sp7450 cnf The Mode LED should go off and you can try to connect to the BDI via Telnet root LINUX_1 bdisetup telnet 151 120 25 101 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 15 2 5 2 Configuration with a Windows host First make sure that the BDI is properly connected see Chapter 2 1 to 2 4 A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 BDI2000 Update Setup r Connect BDI2000 Loader Channel SN 95111242 C Port l COM2 z MAC 000001951112 Speed 115200 7 r BDI2000 Firmware Logic Current Newest Current Loader 1 05 Erase Firmware 1 10 1 10 acra Logic 1 05 1 05 Jpdate r Configuration BDI IP Address fist 120 25101 Subnet Mask 255 255 255 255 Default Gateway 255 255 255 255 Config Host IP Address 151 120 25 119 Configuratio
30. art end TSZ2 start end TSZ4 start end TSZ8 start end MMAP start end Write a double word 64bit to the selected memory place This entry is mainly used to unlock flash blocks The pattern written is generated by du plicating the value 0x12345678 gt 0x1234567812345678 address the memory address value the value used to generate the pattern Example WM64 0xFFFO0000 0x00600060 unlock block 0 Read a byte 8bit from the selected memory place address the memory address Example RM8 0x00000000 Read a half word 16bit from the selected memory place address the memory address Example RM16 0x00000000 Read a word 32bit from the selected memory place address the memory address Example RM32 0x00000000 Read a double word 64bit from the selected memory place address the memory address Example RM64 0x00000000 Defines a memory range with 1 byte maximal transfer size Normally when the BDI reads or writes a memory block it tries to access the memory with a burst access The TSZx entry allows to define a maxi mal transfer size for up to 8 address ranges start the start address of the memory range end the end address of the memory range Example TSZ1 0xFF000000 OxFFFFFFFF PCI ROM space Defines a memory range with 2 byte maximal transfer size Defines a memory range with 4 byte maximal transfer size Defines a memory range with 8 byte maximal transfer size no burst Because a memory access to an invalid memory
31. atchdog and setting the CPU clock rate should also be done with the BDI configuration file Application specific initializations like setting the timer rate are best located in the application startup sequence 3 3 2 Connecting to the target As soon as the target comes out of reset BDI initializes it and loads your application code If RUN is selected the application is immediately started otherwise only the target PC is set BDI now waits for GDB request from the debugger running on the host After starting the debugger it must be connected to the remote target This can be done with the fol lowing command at the GDB prompt gdb target remote bdi2000 2001 bdi2000 This stands for an IP address The HOST file must have an appropriate entry You may also use an IP address in the form XXX XXX XXX XXX 2001 This is the TCP port used to communicate with the BDI If not already suspended this stops the execution of application code and the target CPU changes to background debug mode Remember every time the application is suspended the target CPU is freezed During this time no hardware interrupts will be processed Note For convenience the GDB detach command triggers a target reset sequence in the BDI gdb gdb detach Wait until BDI has resetet the target and reloaded the image gdb target remote bdi2000 2001 Note After loading a program to the target you cannot use the GDB 47 command to start execution You h
32. ave to use the GDB continue command Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 36 3 3 3 Breakpoint Handling GDB versions before V5 0 GDB inserts breakpoints by replacing code via simple memory read write commands There is no command like Set Breakpoint defined in the GDB remote protocol When breakpoint mode HARD is selected the BDI checks the memory write commands for such hidden Set Breakpoint actions If such a write is detected the write is not performed and the BDI sets an appropriate hardware breakpoint The BDI assumes that this is a Set Breakpoint action when memory write length is 4 bytes and the pattern to write is 0x7D821008 tw 12 r2 r2 GDB version V5 x GDB version gt 5 0 uses the Z packet to set breakpoints watchpoints For software breakpoints the BDI replaces code with 0x7D821008 tw 12 r2 r2 When breakpoint mode HARD is selected the BDI sets an appropriate hardware breakpoint 3 3 4 GDB monitor command The BDI supports the GDB V5 x monitor command Telnet commands are executed and the Telnet output is returned to GDB This way you can for example switch the BDI breakpoint mode from within your GDB session gdb target remote bdi2000 2001 Remote debugging using bdi2000 2001 0x10b2 in start gdb monitor break Breakpoint mode is SOFT gdb mon break hard gdb mon break Breakpoint mode is HARD gdb
33. cted from the target system The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec tor Version A or via the POWER connector Version B For more information see chapter 2 2 1 External Power Supply To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 8 2 2 Connecting the BDI2000 to Power Supply The BDI2000 needs to be supplied with 5 Volts max 1A via the POWER connector The available power supply from Abatron option or the enclosed power cable can be directly connected In order to ensure reliable operation of the BDI2000 keep the power supply cable as short as possible A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics POWER Connector 1 Vcc 1 Vec 5V 3 GROUND The green LED BDI marked light up when 5V power is connected to the BDI2000 Please switch on the system in the following sequence e 1 gt external power supply 2 gt target system Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 9 2 3 Status L
34. cutes L1 L2 cache co herent memory accesses If the L1 L2 cache is enabled and the appropri ate data is valid in the cache data is read from the cache For a write access the cache is updated and the data also written to external memo ry If there is an enabled L3 cache flushing the data cache is recommend ed Otherwise the debugger may display wrong data and working with software breakpoints may also fail The following modes are supported NOFLUSH The caches are not flushed L1 L2 cache coherent memory accesses are used Recommended if there is no enabled L3 cache in the system FLUSH Before the BDI accesses any memory the caches are flushed and only external memory is accessed This mode needs a valid workspace for the flush code Example DCACHE NOFLUSH do not flush caches Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450 864 1 User Manual 25 POWERUP delay WAKEUP time MEMDELAY clocks L3PM base size MMU XLAT kb When the BDI detects target power up HRESET is forced immediately This way no code from a boot ROM is executed after power up The value entered in this configuration line is the delay time in milliseconds the BDI waits before it begins JTAG communication This time should be longer than the on board reset circuit asserts HRESET delay the power up start delay in milliseconds Example POWERUP 5000 start delay after power up This entry in the init list
35. dated by the user with a simple Windows based con figuration program The BDI2000 supports 1 8 5 0 Volts target systems 3 0 5 0 Volts target sys tems with Rev B Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 AR for BDIZ000 PowerPC 7440 7450 864 1 User Manual 4 1 2 BDI Configuration As an initial setup the IP address of the BDI2000 the IP address of the host with the configuration file and the name of the configuration file is stored within the flash of the BDI2000 Every time the BDI2000 is powered on it reads the configuration file via TFTP Following an example of a typical configuration file bdiGDB configuration file for Sandpoint 7450 evaluation system i i INIT init core register WREG MSR 0x00000000 clear MSR init memory controller based on DINK32 WM32 OXFECOOOOO 0x80000080 select MSAR1 WM32 OxFEE00000 0x00204060 WM32 OXFECOOOOO 0x84000080 select MSAR2 WM32 OXFEEOOOOO 0x80a0c0e0 WM32 OxFECO0000 0x90000080 select MEARI1 WM32 OxFEE00000 Ox1f3f5f7f s WM32 OxFEC00000 0x94000080 select MEAR2 WM32 OxFEE00000 Ox9fbfdffFf A WM32 OxFECO0000 0xa0000080 select MBEN WM8 OxFEE00000 0x03 H WM32 OXFECOOOOO 0xa0000080 select MP WM8 OxFEE00003 0x32 F WM32 OxFECO0000 O0xf0000080
36. e all addresses received from GDB are assumed to be virtual Before the BDI accesses memory it translates this address into a physical one based on information found in the kernel user page table In order to search the page tables the BDI needs to know the start addresses of the first level page table The configuration parameter PTBASE defines the physical address where the BDI looks for the virtual address of an array with two virtual addresses of first level page tables The first one points normally to the kernel page table the second one can point to the current user page table As long as the base pointer or the first entry is zero the BDI does only BAT and default translation Default translation maps a 256 Mbyte range starting at KERNELBASE to 0x00000000 The second page ta ble is only searched if its address is not zero and there was no match in the first one The pointer stucture is as follows PTBASE physical address gt PTE pointer pointer virtual or physical address gt PTE kernel pointer virtual or physical address PTE user pointer virtual or physical address Newer versions of arch ppc kernel head S support the automatic update of the BDI page table in formation structure Search head S for abatron and you will find the BDI specific extensions Extract from the configuration file INIT WM32 0x000000f 0 0x00000000 invalidate page table bas TARGET MMU XLAT tra
37. e SERE ERK SAG EE ee ek RR GR GR GR RE RR ee ER Ru EKEN GN GEE 45 Th NNR DANY EE EE EE dle eaetedieenannencie 46 Appendices Wee gele ie PRE EE EE EE EE 47 Mi ie EE EE ieeennsescntanenssecsi aes cameunses entensnteceneanaes ianenssecsnsenecceenacens 48 IT Ui GE N EE EN EE 50 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 3 1 Introduction bdiGDB enhances the GNU debugger GDB with JTAG COP debugging for PowerPC 7440 7450 8641 based targets With the built in Ethernet interface you get a very fast code download speed No target communication channel e g serial line is wasted for debugging purposes Even better you can use fast Ethernet debugging with target systems without network capability The host to BDI com munication uses the standard GDB remote protocol An additional Telnet interface is available for special debug tasks e g force a hardware reset program flash memory The following figure shows how the BDI2000 interface is connected between the host and the target Target System PPC 7450 COP Interface BDl2000 GNU Debugger GDB Ethernet 10 BASE T 1 1 BDI2000 The BDI2000 is the main part of the bdiGDB system This small box implements the interface be tween the JTAG pins of the target CPU and a 10Base T Ethernet connector The firmware and the programmable logic of the BDI2000 can be up
38. for code sequenc es to flush the data cache and to access L3 private memory See also DCACHE and L3PM configuration parameter If no workspace is defined DCACHE is not flused and you cannot access L3 private memory address the address of the RAM area Example WORKSPACE 0x00000000 This parameter defines how GDB requested breakpoints are implement ed The current mode can also be changed via the Telnet interface The V option forces the setting of the IABR TE DABT BT bit SOFT This is the normal mode Breakpoints are implemented by replacing code with a TRAP instruction HARD In this mode the PPC breakpoint hardware is used Only 1 breakpoint at a time is supported IABR Example BREAKMODE HARD This parameter defines how single step instruction step is implemented The alternate step mode HWBP may be useful when stepping instruc tions that causes a TLB miss exception TRACE This is the default mode Single step is implemented by setting the SE bit in MSR HWBP In this mode a hardware breakpoint on the next instruc tion is used to implement single stepping Example STEPMODE HWBP When this line is present the BDI catches all unhandled exceptions Catching exceptions is only possible if the memory at address 0x00000000 to OxO0001FFF is writable Example VECTOR CATCH catch unhandled exception This parameter defines if the BDI flushes the caches before it accesses memory If the BDI does not flush the caches it exe
39. g software on the target system After loading the code via TFTP debugging can begin at the very first assembler statement Whenever the BDI system is powered up the following sequence starts initial configuration valid no activate BDI2000 loader Get configuration file via TFTP Power OFF Process target init list Load program code via TFTP and set the PC RUN selected Start loaded program code Process GDB reguest Power OFF Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 19 Breakpoints There are two breakpoint modes supported One of them SOFT is implemented by replacing appli cation code with a TRAP instruction The other HARD uses the built in breakpoint logic If HARD is used only 1 breakpoint can be active at the same time The following example selects SOFT as the breakpoint mode BREAKMODE SOFT SOFT or HARD HARD uses PPC hardware breakpoints All the time the application is suspended i e caused by a breakpoint the target processor remains freezed Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 20 3 2 Configuration File The configuration file is automatically read by the BDI after every power on The syntax of this file is as follows Co
40. ing product Type of device BDM JTAG Interface Product name BDI2000 The signing authorities state that the above mentioned equipment meets the requirements for emission and immunity according to EMC Directive 89 336 EEC The evaluation procedure of conformity was assured according to the following standards EN 50081 2 EN 50082 2 This declaration of conformity is based on the test report no QNL E853 05 8 a of QUINEL Zug accredited according to EN 45001 Manufacturer ABATRON AG St ckenstrasse 4 CH 6221 Rickenbach Authority VOL LY yew foe ne MMMM CE Max Vock Ruedi Dummermuth Marketing Director Technical Director Rickenbach May 30 1998 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 46 7 Warranty ABATRON Switzerland warrants the physical diskette cable BDI2000 and physical documentation to be free of defects in materials and workmanship for a period of 24 months following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship ABATRON will replace defective diskette cable BDI2000 or documentation The remedy for breach of this warranty shall be limited to replacement and shall not encompass any other damages includ ing but not limited loss of profit special incidental consequential or other similar claims ABATRON Switzerland
41. line mode Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 29 3 2 4 Part FLASH The Telnet interface supports programming and erasing of flash memories The bdiGDB system has to know which type of flash is used how the chip s are connected to the CPU and which sectors to erase in case the ERASE command is entered without any parameter CHIPTYPE type CHIPSIZE size BUSWIDTH width FILE filename FORMAT format offset This parameter defines the type of flash used It is used to select the cor rect programming algorithm format AM29F AM29BX8 AM29BX 16 I28BX8 I28BX16 AT49 AT49X8 AT49X16 STRATAX8 STRATAX16 MIRROR MIRRORX8 MIRRORX16 M58X32 AM29DX16 AM29DX32 Example CHIPTYPE AM29F The size of one flash chip in bytes e g AM29F010 0x20000 This value is used to calculate the starting address of the current flash memory bank size the size of one flash chip in bytes Example CHIPSIZE 0x80000 Enter the width of the memory bus that leads to the flash chips Do not enter the width of the flash chip itself The parameter CHIPTYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you are using two AM29F010 to build a 16bit flash memory bank with the width of the flash memory bus in bits 8 16 32 64 Example BUSWIDTH 16 The default name of the file that is programmed into flash using
42. lt value gt SR lt number gt lt value gt RMVR lt nbr gt lt val val val val gt L2CACH lt addr set gt E lt addr set gt DTAG lt from gt lt to gt ITAG lt from gt lt to gt RESET HALT RUN time BREAK SOFT HARD GO lt pc gt TI lt pc gt TC lt pc gt HALT BI lt addr gt vp CI lt id gt BD R W lt addr gt BDT R W lt addr gt CD lt id gt INFO LOAD VERIFY PROG UI ERASE lt address gt lt mode gt x lt mode gt ERASE lt addr gt lt step gt lt count gt lt addr gt lt delay gt lt addr gt lt step gt lt count gt lt type gt lt size gt lt bus gt lt ms gt lt core gt lt ip gt lt string gt converts an effective to a physical address display target memory as word 32bit display target memory as double word 64bit display target memory as half word 16bit display target memory as byte 8bit dump target memory to a file modify word s 32bit in target memory modify double word s 64bit in target memory modify half word s 16bit in target memory modify byte s 8bit in target memory calculates a checksum over a memory range verifies the last calculated checksum display general purpose or user defined register dump all user defined register to a file display
43. lug the cables A ds Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 50 C Trademarks All trademarks are property of their respective holders Copyright 1997 2006 by ABATRON AG Switzerland V 1 10
44. mment part name identifier parameterl parameter2 parameterN comment identifier parameterl parameter2 parameterN part name identifier parameterl parameter2 parameterN identifier parameterl parameter2 parameterN etc Numeric parameters can be entered as decimal e g 700 or as hexadecimal 0x80000 Note about how to enter 64bit values The syntax for 64 bit parameters is lt high word gt _ lt low word gt The high word optional and low word can be entered as decimal or hexadecimal They are han dled as two separate values concatenated with an underscore Examples 0x01234567_0x89abcdef gt gt 0x0123456789abcdef 10 gt gt 0x0000000100000000 256 gt gt 0x0000000000000100 3_0x1234 gt gt 0x0000000300001234 0x80000000_0 gt gt 0x8000000000000000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 27 3 2 1 Part INIT The part INIT defines a list of commands which should be executed every time the target comes out of reset The commands are used to get the target ready for loading the program file WGPR register value Write value to the selected general purpose register register the register number 0 31 value the value to write into the register Example WGPR 0 5 WSPR register value Write value to the selected special purpose register register the register number value the value to write into the regi
45. n 16 2 6 Testing the BDI2000 to host connection si EER DERE ER aie ED EN EE 17 2 7 TFTP server for WiNdOWS aa EE ED ER EG OE Ge Ee ee GE EE EG GEE eo EE ace 17 3 Using bdiGDB iss Ge aha ve eN ee Ee ee ee ee De 18 d i Prineiple af operate EG EE EERS Ge ERGE Ee Ee Ed NR N Ge teed GR oe De Ge Ee be SN ER eek ie 18 3 2 Gonfig ration FIle AE N EE N EE OE EA EE EE 20 321 sal ER RE AE OE EE RE R 21 3 22 Part TARGET ER EE N EA EE EE EE EEN 23 3 2 9 dle AI OR a N AE N N 27 KENS dl EE dIE ET HE EL LE OE EE EEN en 29 3 25 Part REGS ORE EO DE OE AE OE OF 33 3 3 Debugging with EDE EL EE N AE ED ee Ge DE ED ee 35 Re ME ge o 0 EE EE EE EE EE N ER 35 3 3 2 Connecting to the IDEE EE EE DE GE ER IE ee eee 35 3 3 3 Breakpoint Hieie MIGE SE EE GR GER DE ae EE ARE GE EE ER EE ee De 36 3 3 4 GDB monitor command sissies SERS REED ESE DE RE EAE ee ES Re oe RS RE A 36 3 3 5 Target serial VO via BDI sesse ss enig GE NE Re EER SERE Ee N NA GE KA EE Ke Eg Re Re GEE ENE ee 37 3 3 6 Embedded Linux MMU Supporl sis ee bee Se NSR Eie ie Ge RENEE GREG R RR so GEE 38 3 4 Telnet Interface EE EE N OE OR EE OE OE EE EEEO ernn ntt nEnser trne rEn eneen 40 3 5 Dual Core Support for MPC8641D yicssetisncaisnciccanegesermesasntieasaeeaciatan dus tarmuiagebeesiatieriecieaien 42 A Specifications OR EE EE EE 44 5 Environmental note eek eks R AR SR REKE US AR KEER ERK GERGEN GREG ER e VERRE aaan arannana eN Bee Ee ee bed 45 6 Declaration of Conformity GE EER E
46. n file E cygwin home bdidemo sp7450 mpc8641 cfg Cancel Ok Transmit Writing setup data passed dialog box BDIZ000 Update Setup Before you can use the BDI2000 together with the GNU debugger you must store the initial config uration parameters in the BDI2000 flash memory The following options allow you to do this Channel Select the communication port where the BDI2000 is connected during this setup session Baudrate Select the baudrate used to communicate with the BDI2000 loader during this setup session Connect Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Current Press this button to read back the current loaded BDI2000 software and logic versions The current loader firmware and logic version will be displayed Update This button is only active if there is a newer firmware or logic version present in the execution directory of the bdiGDB setup software Press this button to write the new firmware and or logic into the BDI2000 flash mem ory programmable logic Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 16 BDI IP Address Subnet Mask Default Gateway Config Host IP Address Configuration file Transmit Enter the IP address for the BDI2000 Use the following format XXX XXX XXX XXX 9 151
47. nslate effective to physical address PTBASE Ox000000f0 here is the pointer to the page table pointers Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 440 7450 864 1 User Manual 39 To debug the Linux kernel when MMU is enabled you may use the following load and startup se quence e Load the compressed linux image e Set a hardware breakpoint with the Telnet at a point where MMU is enabled For example at start_kernel BDI gt BI 0xC0061550 v e Start the code with GO at the Telnet e The Linux kernel is decompressed and started e The system should stop at the hardware breakpoint e g at start kernel e Disable the hardware breakpoint with the Telnet command Cl e If not automatically done by the kernel setup the page table pointers for the BDI e Start GDB with vmlinux as parameter e Attach to the target e Now you should be able to debug the Linux kernel To setup the BDI page table information structure manually set a hardware breakpoint at start_kernel and use the Telnet to write the address of swapper_pg_dir to the appropriate place BDI gt bi 0xc0061550 BDI gt go BDI gt ci BDI gt mm Oxf0 OxcOQO0000 8 BDI gt mm OXf8 0xc0057000 BDI gt mm Oxfc 0x00000000 set breakpoint at start_kernel target stops at start_kernel Let PTBASE point to an array of two pointers write address of swapper_pg_dir to first pointer clear second u
48. program starts at the nor mal reset address OxFFFOO100 address the address where to start the program file Example START 0x1000 DEBUGPORT port The TCP port GDB uses to access the target port the TCP port number default 2001 Example DEBUGPORT 2001 Special IMAGE load format The IMAGE format is a special version of the ELF format used to load a Linux boot image into target memory When this format is selected the BDI loads not only the loadable segment as defined in the Program Header it also loads the rest of the file up to the Section Header Table The relationship between load address and file offset will be maintained throughout this process This way the com pressed Linux image and a optional RAM disk image will also be loaded Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 28 PROMPT string This entry defines a new Telnet prompt The current prompt can also be changed via the Telnet interface Example PROMPT PPC_2 DUMP filename The default file name used for the Telnet DUMP command filename the filename including the full path Example DUMP dump bin TELNET mode By default the BDI sends echoes for the received characters and supports command history and line editing If it should not send echoes and let the Telnet client in line mode add this entry to the configuration file mode ECHO default NOECHO or LINE Example TELNET NOECHO use old
49. ps that cover the screws on target front side e g with a small knife 2 2 Remove the two screws that hold the front panel BDI OPTION BDI MAIN BDI TRGT MODE 3 1 While holding the casing remove the front panel and the red elastig sealing casing NS elastic sealing front panel Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 440 7450 864 1 User Manual 49 4 1 While holding the casing slide carefully the print in position as shown in figure below m Jumper settings o E o om DEFAULT INIT MODE Fuse Position Fuse Position Version B Version A N Pull out carefully the fuse and replace it 7 Type Microfuse MSF 1 6AF Manufacturer Schurter Reinstallation 5 1 Slide back carefully the print Check that the LEDs align with the holes in the back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the position of the sealing is as shown in the figure below casing NS elastic sealing back panel Mar front panel 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 P
50. r BDIZ000 PowerPC 7440 7450864 1 User Manual 43 Note about memory accesses via JTAG On MPC8641 targets memory accesses are done via the so called System Access Port SAP The SAP is like an additional bus master You can access memory while the core s are running and memory coherency is maintained because SAP accesses are snooped This has the side effect that for example cache lines are flushed when memory is accessed via the BDI Debugging code where data stack is only present in the cache without real memory behind it becomes almost impossible The following Telnet sequence shows the effect on reading cached data via the BDI 8641 gt dcache 0 WO 0_0010 000 VD 0010f000 0010f004 0010f008 0010f00c 0010 010 0010f014 0010f018 0010f01c w1 0 OO10BOOO VD 0010b000 0010b004 0010b008 0010b00c 0010b010 0010b014 0010b018 0010b01c W2 0_00111000 VD 00111000 00111004 00111008 0011100c 00111010 00111014 00111018 0011101c W3 0_0010d000 VD 0010d000 0010d004 0010d008 0010d00c 0010d010 0010d014 0010d018 0010d01c 8641 gt md 0x00111000 0_00111000 00111000 00111004 00111008 0011100c 00111010 00111010 OOLTLOI4 00111918 OODIUTOVS sasie elek sis ie ed 0_001110e0 001110e0 001110e4 001110e8 001110ec eee eee 0_001110f0 001110f0 001110f4 001110f8 001110fc 8641 gt dcache 0 WO 0_0010f000 VD OO10 000 0010f004 0010f008 0010f00c 0010 010 0010f014 0010f018 0010f01c
51. r Windows WIN32 console application cfg Configuration files def Register definition files bdisetup zip ZIP Archive with the Setup Tool sources for Linux UNIX hosts Overview of an installation configuration process e Create a new directory on your hard disk e Copy the entire contents of the enclosed diskette into this directory e Linux only extract the setup tool sources and build the setup tool e Use the setup tool to load update the BDI firmware logic Note A new BDI has no firmware logic loaded e Use the setup tool to transmit the initial configuration parameters IP address of the BDI IP address of the host with the configuration file Name of the configuration file This file is accessed via TFTP Optional network parameters subnet mask default gateway Activating BOOTP The BDI can get the network configuration and the name of the configuration file also via BOOTP For this simple enter 0 0 0 0 as the BDI s IP address see following chapters If present the subnet mask and the default gateway router is taken from the BOOTP vendor specific field as defined in RFC 1533 With the Linux setup tool simply use the default parameters for the c option root LINUX_1 bdisetup bdisetup c p dev ttySO0 b57 The MAC address is derived from the serial number as follows MAC 00 0C 01 xx xx xx repace the xx xx xx with the 6 left digits of the serial number Example SN 93123457 gt gt 00 0C 01 93 12
52. s connected to A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask If the BDI and the host are in the same subnet it is not necessary to enter a subnet mask Default Gateway Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Config Host IP Address Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Configuration file Enter the full path and name of the configuration file This file is read via TFTP Keep in mind that TFTP has it s own root directory usual tftpboot You can simply copy the configuration file to this directory and the use the file name without any path For more information about TFTP use man tftpd root LINUX_1 bdisetup bdisetup c p dev ttySO b57 N gt 1151 120 25 101 N gt h151 120 25 118 N gt fppe750 cnf Connecting to BDI loader Writing network configuration Writing init list and mode Configuration passed 5 Check configuration and exit loader mode The BDI is in loader mode when there is no valid firmware loaded or you connect to it with the setup tool While in loader mode the Mode LED is flashing The BDI will not respond to network requests while in loader mode To exit lo
53. s the kernel virtual base address default is OxCO000000 and is used for default address translation For more information see also chapter Embedded Linux MMU Support Addresses entered at the Telnet are never translated Transla tion can be probed with the Telnet command PHYS kb The kernel virtual base address KERNELBASE Example MMU XLAT enable address translation Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 26 PTBASE addr 64BIT This parameter defines the physical memory address where the BDI looks for the virtual address of the array with the two page table pointers For more information see also chapter Embedded Linux MMU Support If the additional 64BIT option is present the BDi assume a 64 bit PTE addr Physical address of the memory used to store the virtual address of the array with the two page table pointers Example PTBASE Oxf0 REGLIST list With GDB version 5 0 the number of registers read from the target has been increased Additional registers like SR s BAT s and SPR s are re quested when you select a specific PowerPC variant with the set proces sor command see GDB source file rs6000 tdep c In order to be compatible with older GDB versions and to optimize the time spent to read registers this parameter can be used You can define which register group is really read from the target By default STD and FPR are read and trans ferred
54. se there is no TFTP server bundled with Windows Abatron provides a TFTP server application tftpsrv exe This WIN32 console application runs as normal user application not as a system ser vice Command line syntax __ tftpsrv p w dRootDirectory Without any parameter the server starts in read only mode This means only read access request from the client are granted This is the normal working mode The bdiGDB system needs only read access to the configuration and program files The parameter p enables protocol output to the console window Try it The parameter w enables write accesses to the host file system The parameter d allows to define a root directory tftpsrv p Starts the TFTP server and enables protocol output tftpsrv p w Starts the TFTP server enables protocol output and write accesses are allowed tftpsrv dC tftp Starts the TFTP server and allows only access to files in C tftp and its subdirectories As file name use relative names For example bdi mpc750 cfg accesses C tftp bdi mpc750 cfg You may enter the TFTP server into the Startup group so the server is started every time you login Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 18 3 Using bdiGDB 3 1 Principle of operation The firmware within the BDI handles the GDB request and accesses the target memory or registers via the JTAG interface There is no need for any debu
55. ser pointer Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 40 3 4 Telnet Interface A Telnet server is integrated within the BDI The Telnet channel is used by the BDI to output error messages and other information Also some basic debug commands can be executed Telnet Debug features e Display and modify memory locations e Display and modify general and special purpose registers e Single step a code sequence e Set hardware breakpoints e Load a code file from any host e Start Stop program execution e Programming and Erasing Flash memory During debugging with GDB the Telnet is mainly used to reboot the target generate a hardware reset and reload the application code It may be also useful during the first installation of the bdiGDB sys tem or in case of special debug needs Example of a Telnet session BDI gt res TARGET processing user reset request TARGET Target PVR is 0x80000200 TARGET reseting target passed TARGET processing target init list TARGET processing target init list passed BDI gt info Target CPU MPC7450 Rev 2 Target state debug mode Debug entry cause COP freeze startup Current PC Oxff 00100 Current CR 0x00000000 Current MSR 0x00000000 Current LR 0x00000000 BDI gt md Oxfff00100 fff00100 48003270 60000000 60000000 60000000 H f 00
56. specifically disclaims all other warranties expressed or implied including but not limited to implied warranties of merchantability and fitness for particular purposes with respect to defects in the diskette cable BDI2000 and documentation and the program license granted here in including without limitation the operation of the program with respect to any particular application use or purposes In no event shall ABATRON be liable for any loss of profit or any other commercial damage including but not limited to special incidental consequential or other damages Failure in handling which leads to defects are not covered under this warranty The warranty is void under any self made repair operation except exchanging the fuse Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 7440 7450 864 1 User Manual 47 Appendices A Troubleshooting Problem The firmware can not be loaded Possible reasons The BDI is not correctly connected with the target system see chapter 2 e The power supply of the target system is switched off or not in operating range 4 75 VDC 5 25 VDC gt MODE LED is OFF or RED e The built in fuse is damaged gt MODE LED is OFF e The BDI is not correctly connected with the Host see chapter 2 e A wrong communication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons e Wrong pin assignment BDM JT
57. ster Example WSPR 27 0x00001002 SRR1 ME RI WSR register value Write value to the selected segment register register the register number value the value to write into the register Example WSR 0 0x00001002 SRO WREG name value Write value to the selected CPU register by name name the register name MSR CR XER LR CTR DSISR value the value to write into the register Example WREG MSR 0x00001002 DELAY value Delay for the selected time A delay may be necessary to let the clock PLL lock again after a new clock rate is selected value the delay time in milliseconds 1 30000 Example DELAY 500 delay for 0 5 seconds WM8 address value Write a byte 8bit to the selected memory place address the memory address value the value to write to the target memory Example WM8 OxFFFFFA21 0x04 SYPCR watchdog disable WM16 address value Write a half word 16bit to the selected memory place address the memory address value the value to write to the target memory Example WM16 0x02200200 0x0002 TBSCR WM32 address value Write a word 32bit to the selected memory place address the memory address value the value to write to the target memory Example WM32 0x02200000 0x01632440 SIUMCR Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 ldi for BDIZ000 PowerPC 7440 7450864 1 User Manual 22 WM64 address value RM8 address value RM16 address value RM32 address value RM64 address value TSZ1 st
58. those flash chips use the init list to unlock the appropriate blocks WM16 OXFFFOOOOO 0x0060 unlock block 0 WM16 OxFFF00000 0x00D0 WM16 OxFFF 10000 0x0060 unlock block 1 WM16 OxFFF10000 0x00D0 WM16 OXFFFOOOOO OxFFFF select read mod or use the Telnet Unlock command UNLOCK lt addr gt lt delay gt addr This is the address of the sector block to unlock delay A delay time in milliseconds the BDI waits after sending the unlock com mand to the flash For example clearing all lock bits of an Intel J3 Strata flash takes up to 0 7 seconds If unlock is used without any parameter all sectors in the erase list with the UNLOCK option are processed To clear all lock bits of an Intel J3 Strata flash use for example BDI gt unlock OxFF000000 1000 To erase or unlock multiple continuos flash sectors blocks of the same size the following Telnet commands can be used ERASE lt addr gt lt step gt lt count gt UNLOCK lt addr gt lt step gt lt count gt addr This is the address of the first sector to erase or unlock step This value is added to the last used address in order to get to the next sec tor In other words this is the size of one sector in bytes count The number of sectors to erase or unlock The following example unlocks all 256 sectors of an Intel Strata flash 28F256K3 that is mapped to 0x00000000 In case there are two flash chips to get a 32bit system double the step parameter
59. wer supply for the BDI and open the unit as described in Appendix Maintenance e Place the jumper in the INIT MODE position e Connect the power cable or target cable if the BDI is powered from target system ees areas i iem e Switch ON the power supply for the BDI again and wait untilthe q INIT MODE LED MODE blinks fast P Me e Turn the power supply OFF again N DEFAULT e Return the jumper to the DEFAULT position e Reassemble the unit as described in Appendix Maintenance Copyright 1997 2006 by ABATRON AG Switzerland V 1 10 MA for BDIZ000 PowerPC 440 7450 864 1 User Manual 17 2 6 Testing the BDI2000 to host connection After the initial setup is done you can test the communication between the host and the BDI2000 There is no need for a target configuration file and no TFTP server is needed on the host e If not already done connect the BDI2000 system to the network e Power up the BDI2000 e Start a Telnet client on the host and connect to the BDI2000 the IP address you entered dur ing initial configuration e If everything is okay a sign on message like BDI Debugger for Embedded PowerPC and a list of the available commands should be displayed in the Telnet window 2 7 TFTP server for Windows The bdiGDB system uses TFTP to access the configuration file and to load the application program Becau
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