Home

XST User Guide

1. XCF Cmd Constraint Constraint Constraint VHDL Verilog Cmd Technology Line Name Value Syntax Target Target Value Tar get XST Constraints box type primitive model VHDL component no na Spartan I TIE 3 black box inst in model component entity VirtexTM TI II Pro user black box entity II Pro X E 4 lo XC9500 PROG CoolRunner label XPLA3 module buffer_type bufgdll ibufg net in model signal signal yes bufgdll Spartan TI TIE 3 bufgp ibuf ibufg VirtexTM TI II Pro none bufgp ibuf II Pro X E 4 bufr none bufgce yes no net in model primary primary no na Virtex II II Pro true false clock signal clock signal II Pro X 4 bram_map yes no model VHDL entity yes na Spartan M T ITE 3 true false entity Virtex TI II Pro Verilog Il Pro X E 4 module clock_buffer bufgdll ibufg net in model signal signal no na Spartan II TIE 3 bufgp ibuf Virtex TI II Pro none II Pro X E 4 clock signal yes no clock signal clocksignal clocksignal no na Spartan T TIE 3 true false net in model VirtexTM TI II Pro Il Pro X E 4 decoder_extract yes no model entity entity yes yes no Spartan TT TIE 3 true false net in model signal signal VirtexTM TI II Pro Il Pro X E 4 enable_auto_floorplanning na na na na yes no Spartan TI TIE 3 incremental Virtex II TI Pro design II Pro X E 4 enum encoding string
2. 1 800 255 7778 Name Vendor XST Equivalent Automatic Recognition Available For syn_black_box Synplicity box type na VHDL Verilog syn_direct_enable Synplicity na na na syn_edif_bit_format Synplicity na na na syn_edif_scalar_format Synplicity na na na syn_encoding Synplicity fsm_encoding yes VHDL Note The value safeis not Verilog supported for automatic recognition Please use safe_implementation constraint in XST to activate this mode syn_enum_encoding Synplicity enum_encoding na VHDL syn_hier Synplicity keep_hierarchy yes VHDL Note Only the values hard Verilog and remove are supported for automatic recognition syn_isclock Synplicity na na na syn_keep Synplicity keep yes VHDL Verilog syn_maxfan Synplicity max fanout yes VHDL Verilog syn_netlist_hierarchy Synplicity keep_hierarchy na VHDL Verilog syn_noarrayports Synplicity na na na syn_noclockbuf Synplicity buffer_type yes VHDL Verilog syn_noprune Synplicity optimize primitives yes VHDL Verilog syn_pipeline Synplicity Register Balancing na VHDL Verilog syn probe Synplicity equivalent register yes VHDL removal Verilog syn ramstyle Synplicity na na NA syn reference clock Synplicity na na NA syn romstyle Synplicity na na NA syn sharing Synplicity register duplication yes VHDL Verilog 280 www xilinx com XST User Guide Third Party Constraints Table 5 4 Third Party Constraints
3. architecture ARCHI of EXAMPLE is begin process A B variable X Y BIT begin X and B Y B and A if X Y then S lt 1 end if D end process end ARCHI Note In combinatorial processes if a signal is not explicitly assigned in all branches of if or case statements XST generates a latch to hold the last value To avoid latch creation ensure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the Process statements Different statements can be used in a process e Variable and signal assignment e If statement e Case statement e For Loop statement e Function and procedure call The following sections provide examples of each of these statements If Else Statement If else statements use true false conditions to execute statements If the expression evaluates to true the first statement is executed Ifthe expression evaluates to false or x or z the Else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested Example 6 12 shows the use of an If else statement XST User Guide www xilinx com 301 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Example 6 12 MUX Description Using If Else Statement library IEEE use IEEE std_logic_1164 all entity mux4 is port a b c d in st
4. A multi dimensional array signal or variable can be completely used TAB A TAB B TAB C TAB D TAB C lt CNST A Just an index of one array can be specified TAB A 5 WORD A TAB C 1 lt TAB A www xilinx com 287 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Just indexes of the maximum number of dimensions can be specified TAB A 5 0 lt 1 TAB C 2 5 0 lt T Just a slice of the first array can be specified TAB_A 4 downto 1 lt TAB_B 3 downto 0 Just an index of a higher level array and a slice of a lower level array can be specified TAB_C 2 5 3 downto 0 lt TAB_B 3 4 downto 1 TAB_D 0 4 2 downto 0 lt CNST_A 5 downto 3 Now add the following declaration subtype MATRIX15 is array 4 downto 0 2 downto 0 of STD_LOGIC_VECTOR 7 downto 0 A multi dimensional array signal or variable can be completely used ATRIX15 lt CNST_A Just an index of one row of the array can be specified ATRIX15 5 lt TAB_A Just indexes of the maximum number of dimensions can be specified ATRIX15 5 0 0 lt 1 Just a slice of one row can be specified ATRIX15 4 4 downto 1 lt TAB_B 3 downto 0 Note Indices may be variable Record Types XST supports record types An example of a record is shown below type REC1 is record fieldl std_logic field2 std_logic_vector 3 downto 0 end re
5. Low Level Synthesis i Optimizing unit stopwatch Optimizing unit lt cnt60 gt Optimizing unit lt smallcntr gt Optimizing unit lt statmach gt Optimizing unit decode Optimizing unit lt hex2led gt Loading device for application Rf Device from file 2v40 nph in environment C Xilinx Mapping all equations Building and optimizing final netlist Found area constraint ratio of 100 5 on block stopwatch actual ratio is 11 370 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File XILINX Final Report Final Results RTL Top Level Output File Name Top Level Output File Name stopwatch ngr scs Output Format N S ES topwatch Optimization Goal Keep Hierarchy Ho Q uoa Oo Q Design Statistics IOs 024 Macro Statistics ROMs 16x10 bit ROM 16x7 bit ROM Registers NNN LP W 4 bit register Cell Usage BELS al 99 GND eL LUT1 mn N o UT4_L FlipFlops Latches od DP Clock Buffers BUF GP IO Buffers IBUF OBUF Others tenths Oo od usa iw Q Er PPNNNFRPPRPOOHEUNDN BW Device utilization summary Selected Device 2v40cs144 6 Number of Slices 30 out of 256 11 Number of Slice Flip Flops 14 out of 512 2 Number of 4 input LUTs 52 out of 512 10 Number of bonded IOBs 26 out of 88 29 Number of GCLKs 1 out of 16 6 XST User Guide www xilinx com 37
6. S3 lt ADD A 3 B 3 S2 1 S lt S3 0 amp S2 0 S1 0 amp SO 0 COUT S3 1 end ARCHI www xilinx com XST User Guide 1 800 255 7778 Functions and Procedures XILINX Example 6 24 Procedure Declaration and Procedure Call package PKG is procedure ADD A B CIN in BIT C out BIT VECTOR 1 downto 0 end PKG package body PKG is procedure ADD A B CIN in BIT C out BIT VECTOR 1 downto 0 ye is variable S COUT BIT begin S A xor B xor CIN COUT A and B or A and CIN or B and CIN C COUT amp S end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT_VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B CIN variable S0 S1 S2 S3 BIT_VECTOR 1 downto 0 begin ADD A 0 B 0 CIN SO ADD A 1 B 1 SO 1 S1 ADD A 2 B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S lt S3 0 amp S2 0 amp S1 0 amp SO 0 COUT S3 1 end process end ARCHI XST supports recursive functions as well Example 6 25 represents n function Example 6 25 Recursive Function function my func x integer return integer is begin if x 1 then return x else return x my func x 1 end if end function my func XST User Guide www xilinx
7. Advanced HDL Synthesis MAC inference INFO Xst 1951 Multiplier Mmult mult in block m macl and accumulator accum in block m macl are combined into a MAC Related Constraints Related constraints are USE DSP48 and KEEP which are available for Virtex 4 devices Considerations for Virtex 4 Devices The Multiply Accumulate macro is a complex macro which consists of several basic macros as multipliers accumulators and registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources available in Virtex 4 devices XST supports the registered version of this macro and can push up to 2 levels of input registers into the DSP48 block If Adder Subtractor operation selectors are registered XST pushes these registers into the DSP48 In addition the multiplication operation could be registered as well XST can implement a multiply accumulate in a DSP48 block if its implementation requires only a single DSP48 resource If the macro exceeds the limits of a single DSP48 XST processes it as a 2 separate Multiplier and Accumulate macros making independent decisions on each macro Please refer to the Multipliers and Accumulators sections for more information Macro implementation on DSP48 blocks is controlled by the USE DSP48 constraint command line option with default value of auto Please note that when implementing multiply accumulate macros on DSP
8. This example generates the following error message ERROR Xst 909 Module name conflict UPPERLOWER10 and upperlowerl0 XST User Guide www xilinx com 345 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Blocking and Nonblocking Assignments XST rejects Verilog designs if a given signal is assigned through both blocking and nonblocking assignments as in the following example always Q inl begin if in2 outl inl else outl lt in2 end If a variable is assigned in both a blocking and nonblocking assignment the following error message is generated ERROR Xst 880 design v line n Cannot mix blocking and non blocking assignments on signal lt outl gt There are also restrictions when mixing blocking and nonblocking assignments on bits and slices The following example is rejected even if there is no real mixing of blocking and non blocking assignments if in2 begin out1 0 1 b0 out1 1 lt inl end else begin out1 0 in2 out1 1 lt 1 b1 end Errors are checked at the signal level not at the bit level If there is more than a single blocking non blocking error only the first one is reported In some cases the line number for the error might be incorrect as there might be multiple lines where the signal has been assigned Integer Handling There are several cases where XST handles integers differently from other synthesis tools and so they
9. ooooooococcooorororoconn 171 VEHDL Code cocina ai es EG eRe bad TANE PEDE ee eae Ped eed 171 Verilog Codec A e lead cn EE E eae ed Stace 172 Initializing Block RAM 6 0 Ie 174 sel ii A E RE E OAE ia 174 Verilog Code iii bee doro ii Pate redet 177 Limitations eh e Ege A a Goa giles A A e Wied wie 177 ROMs Using Block RAM Resources n nanunua nanna nnna e 178 ss T 178 Verilog Code iii boe oda bee i ee eb ier Sebo bad ed dde 181 State Machine 182 FSM with 1 Process isis EE IEEE Rede ox bach kad da dd 184 VODLCoOd e ii A A A osa a ii 184 Verlo Code ii A A it eee a eee 185 FSM with 2 Processes a A po e ER ated 186 VHDL Code re ee RE ee Pr er ERN Ego Dx Pede 186 Verilog Code c deeem edt peter e s Riad ieee Bleue iR Edited Prieto PET eoe 187 FSM with 3Processes 00 0 ccc cc ce ee nent hn 188 VADE COGS ii id ta id 188 Verilog Code iii A be 189 State Registers Lei cte independent acie Un E dob S RO Gom Re ARR Ue sd 190 Next State Equations ccce esee et ee hes es ma ER edo a 190 Unreachable States 0 0 0 0 ccc eee eh men 190 FSM Outp lS eee id ee AR UH eet dec el e dede o dni aes 190 FSM Inputs c ener m eee pee te a ge de QS ee pate P De tee iaa 190 State Encoding Techniques ssssseeseeeeese e 191 PAILS isset wished ette SES sete erg dre ed uec tod ee tg od ud a o Rod oe edite ee ed ie Re Du 191 One HOt desde eC ROREM Rede e d e REA E CER REG RR CROP 191 tco ME 191 Compact mii e e
10. 180 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Verilog Code Following is Verilog code for a ROM with registered output module rominfr clk en addr data input clk input en input 4 0 addr output reg 3 0 data always posedge clk begin if en case addr 4 50000 data lt 4 b0010 4 b0001 data lt 4 b0010 4 b0010 data lt 4 b1110 4 p0011 data lt 4 b0010 4 50100 data lt 4 b0100 4 b0101 data lt 4 b1010 4 b0110 data lt 4 b1100 4 b0111 data lt 4 b0000 4 b1000 data lt 4 b1010 4 b1001 data lt 4 b0010 4 b1010 data lt 4 b1110 4 p1011 data lt 4 b0010 4 b1100 data lt 4 b0100 4 b1101 data lt 4 b1010 4 b1110 data lt 4 b1100 4 b1111 data lt 4 b0000 default data lt 4 bXXXX endcase end endmodule XST User Guide www xilinx com 181 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Following is Verilog code for a ROM with registered address module rominfr clk input clk input en input 4 0 addr output reg 3 0 reg 4 0 raddr always posedge clk if en da raddr lt addr end always raddr if en case raddr 4 b0000 4 b0001 4 50010 4 b0011 4 50100 4 50101 4 50110 4 b0111 4 b1000 4 b1001 4 51010 4 51011 4 51100 4 b1101 4 b1110 4 p1111 default endcase end endmodule State Ma
11. Entity lt single_srl gt ERROR Xst assert top Architecture lt beh gt zed Unit top generated Entity single srl Architecture lt beh gt gt analyzed Unit single srl generated Architecture lt beh gt 1 vhd line 15 FAILURE f a single SRL The size of Shift Register XST User Guide www xilinx com 311 1 800 255 7778 XILINX Packages Chapter 6 VHDL Language Support VHDL models may be defined using packages Packages contain type and subtype declarations constant definitions function and procedure definitions and component declarations This mechanism provides the ability to change parameters and constants of the design for example constant values function definitions Packages may contain two declarative parts package declaration and body declaration The body declaration includes the description of function bodies declared in the package declaration XST provides full support for packages To use a given package the following lines must be included at the beginning of the VHDL design library lib pack lib pack is the name of the library specified where the package has been compiled work by default use lib pack pack name all pack name is the name of the defined package XST also supports predefined packages these packages are pre compiled and can be included in VHDL designs These packages are intended for use during
12. while loop end loop Supported loop end loop Only supported in the particular case of multiple Wait statements Next Statement Supported Loop Statement Exit Statement Supported Return Statement Supported Null Statement Supported Process Statement Supported Concurrent Procedure Supported Call Concurrent Assertion Ignored Concurrent Statement Statement Concurrent Signal Assignment Statement Supported no after clause no transport or guarded options no waveforms Component Instantiation Statement Supported For Generate Statement supported for constant bounds only If Generate Statement supported for static condition only www xilinx com 1 800 255 7778 319 7 XILINX Chapter 6 VHDL Language Support VHDL Reserved Words The following table shows the VHDL reserved words abs configuration impure null rem type access constant in of report unaffected after disconnect inertial on return units alias downto inout open rol until all else is or ror use and elsif label others select variable architecture end library out severity wait array entity linkage package signal when assert exit literal port shared while attribute file loop postponed sla with begin for map procedure sll xnor block function mod process sra xor body genera
13. XILINX The following template shows the recommended configuration coded in Verilog module raminfr input clk input we input en clk we en addr di do input 4 0 addr input 3 0 di output 3 0 do reg 3 0 RAM 31 0 reg 3 0 do always posedge clk begin if en begin if we RAM addr lt di else do lt RAM addr end end endmodule Single Port RAM with Asynchronous Read The following descriptions are directly mappable onto distributed RAM only Distributed X8976 The following table shows pin descriptions for a single port RAM with asynchronous read 10 Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output XST User Guide www xilinx com 1 800 255 7778 141 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for a single port RAM with asynchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic a in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and
14. inferred 1 Finite State Machine s Unit lt statmach gt synthesized Synthesizing Unit lt stopwatch gt Related source file is C temp timer stopwatch vhd WARNING Xst 646 Signal lt strtstopinv gt is assigned but never used Unit stopwatch synthesized Advanced HDL Synthesis 2 Advanced RAM inference Advanced multiplier inference Analyzing FSM FSM 0 for best encoding Dynamic shift register inferenc XST User Guide www xilinx com 377 1 800 255 7778 XILINX Chapter 9 Log File Analysis ROMs Counters Registers 1 bit register Macro Statistics 16x10 bit ROM 16x7 bit ROM HDL Synthesis Report 4 bit up counter WWNHNN EF w Low Level Synthesis FSM lt FSM_0 gt on signal lt current_state 1 3 gt with sequential encoding Optimizing State Encoding clear 000 Zero 001 start 010 counting 011 stop 100 stopped 101 Optimizing unit lt stopwatch gt Optimizing unit lt cnt60 gt Optimizing unit lt smallcntr gt Optimizing unit lt hex2led gt Optimizing unit lt statmach gt Optimizing unit lt decode gt Final Report Final Resul RTL Top Level Output File Name ts Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Target Technology Macro Prese rve XOR Preserve Clock Enabl wysiwyg e Design Statistics IOs topwatch ngr topw
15. 00015 70010 0011 5 01 00 OTO0IT 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 0010 0011 01007 0TOLTLT t0ILTOT 0111T 1000 7 10017 1010 LOTTE MTEGO T 1T01 1110 T111 signal rdata std logic vector 3 downto 0 begin rdata lt ROM conv integer addr process clk begin if clk event and clk 1 then if en 1 then data lt rdata end if end if end process end syn XST User Guide www xilinx com 179 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Following is VHDL code for a ROM with registered address library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity rominfr is port clk in std logic en in std_logic addr in std logic vector 4 downto 0 data out std_logic_vector 3 downto 0 end rominfr architecture syn of rominfr is type rom_type is array 31 downto 0 of std_logic_vector 3 downto 0 constant ROM rom_type C0001 0010 TOOL 0100 0701 80210 O11 1000 LOQ1 TOTO LO0l1I 1100 I101 1110 1111 00021 00T0 QOOLI 0100 OLOL APOLLO SOIL ATO00 rO TLOLO 1011T 11007 1T01 LILON MALETA signal raddr std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then raddr lt addr end if end if end process data lt ROM conv_integer raddr end syn
16. Chapter Examples 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out Language Templates 4 bit Loadable Serial In Serial Out Shift Register 4 bit Serial In Parallel out Shift Register 4 bit Serial In Serial Out Shift Register www xilinx com 1 800 255 7778 XST User Guide Introduction XST User Guide XILINX Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Shift Registers continued Chapter Examples 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Out 8
17. For all non native UCF constraints use the MODEL or BEGIN MODEL END constructs This is true for pure XST constraints such as FSM_EXTRACT or RAM STYLE as well as for implementation non timing constraints such as RLOC or KEEP For native UCF constraints such as PERIOD OFFSET TNM_NET TIMEGRP TIG FROM TO etc use native UCF syntax which includes the use of wildcards and hierarchical names Do not use these constraints inside the BEGIN MODEL END construct otherwise XST issues an error IMPORTANT If you specify timing constraints in the XCF file Xilinx strongly suggests that you use character as a hierarchy separator instead of Please refer to Hierarchy Separator for details on its usage XST User Guide www xilinx com 245 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Limitations XCF syntax has the following limitations e Nested model statements are not supported in the current release e Instance or signal names listed between the BEGIN MODEL statement and the END statement are only the ones visible inside the entity Hierarchical instance or signal names are not supported e Wildcards in instance and signal names are not supported except in timing constraints e Notall native UCF constraints are supported in the current release Refer to the Constraints Guide for more information General Constraints This section lists various constraints that you can use with XST These constr
18. Related source file is m multaddsubl vhd Found 8x8 bit multiplier for signal n0000 created at line 20 Found 8 bit register for signal A regl Found 8 bit register for signal A reg2 Found 8 bit register for signal B regl Found 8 bit register for signal B reg2 Found 16 bit adder for signal lt multaddsub gt Summary inferred 32 D type flip flop s inferred 1 Adder Subtractor s inferred 1 Multiplier s Unit lt m_multaddsubl gt synthesized Advanced HDL Synthesis INFO Xst 1952 Multiplier Mmult n0000 in block m multl and adder subtractor Madd mult in block m multi are combined into a MAC INFO Xst 1953 The following registers are also absorbed by the MAC A reg2 in block m multi A regl in block m multl B reg2 in block m multi B regi in block m multi R multl in block m multi Related Constraints Related constraints are USE DSP48 and KEEP which are available for Virtex 4 devices Considerations for Virtex 4 Devices XST supports the registered version of this macro and can push up to 2 levels of input registers on multiplier inputs 1 register level on the Adder Subtractor input and 1 level of output register into the DSP48 block If the Carry In or Add Sub operation selectors are registered XST pushes these registers into the DSP48 In addition the multiplication operation could be registered as well
19. XST User Guide www xilinx com 1 800 255 7778 XILINX 349 XILINX Chapter 7 Verilog Language Support Table 7 6 Procedural Assignments initial Statement Supported always Statement Supported task Supported Recursion Unsupported functions Supported Constant Functions Unsupported Recursion Unsupported disable Statement Supported Table 7 7 System Tasks and Functions System Tasks Ignored System Functions Unsupported Table 7 8 Design Hierarchy Module definition Supported Macromodule definition Unsupported Hierarchical names Unsupported defparam Supported Array of instances Supported Table 7 9 Compiler Directives celldefine endcelldefine Ignored default nettype Supported define Supported ifdef else endif Supported undef ifndef elsif Supported include Supported resetall Ignored timescale Ignored 350 www xilinx com XST User Guide 1 800 255 7778 Primitives Primitives XST User Guide Table 7 9 Compiler Directives unconnected_drive Ignored nounconnected_drive uselib Unsupported file line Supported XILINX XST supports certain gate level primitives The supported syntax is as follows gate_type instance_name output inputs The following example shows Gate Level Prim
20. XST can implement an accumulator in a DSP48 block if its implementation requires only a single DSP48 resource If an accumulator macro does not fit in a single DSP48 XST will implement the entire macro using slice logic Macro implementation on DSP48 resources is controlled by the USE_DSP48 constraint command line option with a default value of auto In this mode XST implements accumulators taking into account the number of available DSP48 resources on the device To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers as possible in the DSP48 If you want to shape a macro ina specific way you must use the KEEP constraint For example if you want to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers As with other families for Virtex 4 XST reports the details of inferred accumulators at the HDL Synthesis step But in the Final Synthesis Report accumulators are no longer visible because they are implemented within the MAC implementation mechanism Shift Registers In general a shift register is characterized by the following control and data signals which are fully recognized by XST e clock e serial input e asynchronous set reset e synchronous set reset e synchronous asynchronous parallel load e clock enable e serial or parallel output The shift register output mode may be
21. yes check box is checked the synthesizer implements the use of the Clock Enable signal of the device no check box is not checked the Clock enable function will be implemented through equivalent logic Keeping or not keeping the clock enable signal depends on the design logic Sometimes when the clock enable is the result of a Boolean expression saying no with this option may improve the fitting result because the input data of the flip flop is simplified when it is merged with the clock enable expression Define this constraint globally with the pld ce command line option of the run command Following is the basic syntax pld ce yes no The default is yes In Project Navigator specify this option globally with the Clock Enable option in the Xilinx Specific Options tab of the Process Properties dialog box Data Gate The CoolRunner IT DataGate DATA GATE feature provides direct means of reducing power consumption in your design Each I O pin input signal passes through a latch that can block the propagation of incident transitions during periods when such transitions are not of interest to your CPLD design Input transitions that do not affect the CPLD design function still consume power if not latched as they are routed among the CPLD s Function Blocks By asserting the DataGate control I O pin on the device selected I O pin inputs become latched thereby eliminating the power dissipation associated with external
22. I sysclk name based referencing endmodule The unisim comp v library file supplied with XST includes the definitions for FDC and BUFG module FDC C CLR D Q input C input CLR input D output 0 endmodule synthesis attribute BOX TYPE of FDC is BLACK BOX module BUFG O I output O input I endmodule synthesis attribute BOX TYPE of BUFG is BLACK BOX Parameters Verilog modules support defining constants known as parameters which can be passed to module instances to define circuits of arbitrary widths Parameters form the basis of creating and using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques The following is an example of the use of parameters Null string parameters are not supported Example 7 13 Using Parameters module lpm reg out in en reset clk parameter SIZE 1 input in en reset clk output out wire SIZE 1 0 in reg SIZE 1 0 out always posedge clk or negedge reset begin if reset out lt 1 b0 else if en out lt in else out lt out redundant assignment end endmodule XST User Guide www xilinx com 343 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support module top portlist left blank intentionally wire 7 0 sys_in sys_out wire sys_en sys_reset sysclk lpm_reg 8 buf_373 sys_out sys_in sys_en sys_reset sysclk endmodule Instantiation of the module lpm_reg with a instantiation w
23. If there is no path in the domain concerned No path found is then printed instead of the value Timing Detail The Timing Detail section describes the most critical path in detail for each region The start point and end point of the path the maximum delay of this path and the slack The start and end points can be Clock with the phase rising falling or Port Path from Clock sysclk rising to Clock sysclk rising 7 523ns Slack 7 523ns The detailed path shows the cell type the input and output of this gate the fanout at the output the gate delay the net delay estimated and the name of the instance When entering a hierarchical block begin scope is printed and similarly end scope is printed when exiting a block The preceding report corresponds to the following schematic gt Ll C Q O O 1 372ns 2 970ns 0 738ns 1 265ns 0 738ns 0 000ns 0 440ns state_FFD1 LUT_54 next state 2 X9554 In addition the Timing Report section shows the number of analyzed paths and ports If XST is run with timing constraints it displays the number of failed paths and ports as well The number of analyzed and failed paths shows you how many timing problems there are in the design The number of analyzed and failed ports may show you how they are spread in the design The number of ports in a timing report represent the number of destination elements for a timing constraint XST User Guide www xilinx com 217 1 800 255
24. Related source file is multiplexers_1 vhd Found 1 bit 4 to 1 multiplexer for signal o Summary inferred 1 Multiplexer s Unit lt mux gt synthesized HDL Synthesis Report Macro Statistics Multiplexers a Ob 1 bit 4 to 1 multiplexer al Related Constraints Related constraints are MUX_EXTRACT and MUX_STYLE 4 to 1 1 bit MUX using IF Statement The following table shows pin definitions for a 4 to 1 1 bit MUX using an If statement 10 Pins Description a b c d Data Inputs s 1 0 MUX selector O Data Output VHDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using an If statement library ieee use ieee std_logic_1164 all entity mux is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end mux 88 www xilinx com XST User Guide 1 800 255 7778 Multiplexers architecture archi of mux is begin process a b c d s begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt Cc else o lt d end if end process end archi Verilog Code Following is the Verilog code for a 4 to 1 1 bit MUX using an If statement module mux a b c d S O input a b c d input 1 0 s output o reg o always a or b or c or d or s begin if s 2 b00 o a else if s 2 b01 o b else if s 2 b10 Oo C else o d end endmodule 4 to 1 MU
25. XPLA3 II wysiw na na na na es es no XC9500 ySIWy8 y y CoolRunner XPLA3 II xsthdpdir directory_path na na na yes yes no Spartan I TIE 3 Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II xsthdpini file_name na na na yes file_name Spartan TI TIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II The following table shows the timing constraints supported by XST that you can invoke only from the command line or the Process Properties dialog box in Project Navigator Table 5 2 XST Timing Constraints Supported Only by Command Line Process Properties Dialog Box Process Property Option ProjNav Values Technology glob opt Global allclocknets Spartan I ITE 3 Virtex TI II Pro Optimization Goal inpad to outpad II Pro X E 4 XC9500 CoolRunner offset in before XPLA3 II offset out after max delay cross clock analysis Cross Clock yes no Spartan IT IIE 3 Virtex TI II Pro Analysis II Pro X E 4 XC9500 CoolRunner XPLA3 II write timing constraints Write Timing yes no Spartan I ITE 3 Virtex II II Pro Constraints II Pro X E 4 XC9500 CoolRunner XPLA3 II XST User Guide www xilinx com 275 1 800 255 7778 7 XILINX Chapter 5 Design Constraints The following table shows the timing constraints supported by XST that you can invoke only through the Xilinx Co
26. block b2 begin STATE lt DATA_IN end endmodule 334 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX The assign deassign statement must be performed in the same always block through an if else statement For example XST rejects the following design module dflop input RST RST SET CLOCK DATA_IN STATE input SE input Cl input DA LOCK rA IN output S ATE Dn reg STATE always case RS 2 b00 2 b01 2 010 2 p11 endcase always begin STATI end endmodule SET RST or SE P block bl assign S 1 b0 assign S 1 b0 assign S deassign A A A S 1 b1 ATE posedge CLOCK E lt DATA IN block b2 You cannot assign a bit part select of a signal through an assign deassign statement For example XST rejects the following design module assig RST SEL input RST input SE LE C input Cl input 0 output reg 0 7 always if RST LOCK 0 7 7 DAT S A IN AT STATE RST begin assign STAT end else begin end always begin posedge CLOCK if E ECT 0 3 lt DAT m end ECT ELOT STATE CLOCK DATA_IN
27. in the Constraints Guide for details Slice Utilization Ratio The Slice Utilization Ratio SLICE_UTILIZATION_RATIO constraint defines the area size that XST must not exceed during timing optimization If the constraint cannot be met XST makes timing optimization regardless This constraint can be specified by selecting the Slice Utilization Ratio option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator or with the slice_utilization_ratio command line option See SLICE_UTILIZATION_RATIO in the Constraints Guide for details Slice Utilization Ratio Delta The Slice Utilization Ratio Delta SLICE_UTILIZATION_RATIO_MAXMARGIN constraint is closely related to the SLICE_UTILIZATION_RATIO constraint It defines the tolerance margin for the SLICE_UTILIZATION_RATIO constraint If the ratio is within the margin set the constraint is met and timing optimization can continue For details see Speed Optimization Under Area Constraint in Chapter 3 and also see SLICE_UTILIZATION_RATIO_MAXMARGIN in the Constraints Guide Map Entity on a Single LUT The Map Entity on a Single LUT LUT_MAP constraint forces XST to map a single block into a single LUT If a described function on an RTL level description does not fit in a single LUT XST issues an error message See LUT_MAP in the Constraints Guide for details Read Cores The Read Cores read_cores command line option enables o
28. 3 b100 code 3 b101 code 3 b110 code 3 b111 code 3 bxxx Xilinx defines a logical shifter as a combinatorial circuit with 2 inputs and 1 output The first input is a data input that is shifted The second input is a selector whose binary value defines the shift distance The output is the result of the shift operation Note All of these l Os are mandatory otherwise XST does not infer a logical shifter Moreover you must adhere to the following conditions when writing your HDL code Use only logical arithmetic and rotate shift operations Shift operations that fill vacated positions with values from another signal are not recognized For VHDL you can only use predefined shift SLL SRL ROL etc or concatenation operations Please refer to the IEEE VHDL language reference manual for more information on predefined shift operations Use only one type of shift operation The n value in the shift operation must be incremented or decremented only by 1 for each consequent binary value of the selector www xilinx com 99 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques e Then value can be only positive e All values of the selector must be presented Log File The XST log file reports the type and size of a recognized logical shifter during the Macro Recognition step Synthesizing Unit lt lshift gt Related source file is Logical_Shifters_1 vhd Found 8 bit shifter logical left for sig
29. 4 b1011 You can also assign a set reset initial value to a register via your behavioral Verilog code Do this by assigning a value to a register when the register s reset line goes to the appropriate value as in the following example www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Example always posedge clk begin if rst arb_onebit lt 1 b0 end end When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip flop whose output can be controlled by a local reset as such itis carried in the NGC file as an FDP or FDC flip flop Local Reset Global Reset Note that local reset is independent of global reset Registers controlled by a local reset may be set to a different value than ones whose value is only reset at global reset power up In the following example the register arb onebit is set to 0 at global reset but a pulse on the local reset rst can change its value to 1 Example module mult clk rst A IN B OUT input clk rst A IN output B OUT reg arb onebit 1 b0 always posedge clk or posedge rst begin LE ESE arb_onebit lt 1 b1 else arb_onebit lt A_ IN end end B_OUT lt arb_onebit endmodule This sets the set reset value on the register s output at initial power up but since this is dependent upon a local reset the value changes whenever the local set reset is acti
30. Abstract Literals Only integer literals are supported Physical Literals Ignored Enumeration Literals Supported String Literals Supported Bit String Literals Supported Record Aggregates Supported Array Aggregates Supported Function Call Supported Qualified Expressions Supported for accepted predefined attributes Types Conversions Supported Allocators Unsupported Static Expressions Supported Table 6 10 Supported VHDL Statements Wait Statement Wait on sensitivity_list until Boolean_expression See Sequential Circuits for details Supported with one signal in the sensitivity list and in the Boolean expression In case of multiple Wait statements the sensitivity list and the Boolean expression must be the same for each Wait statement Note XST does not support Wait statements for latch descriptions Wait for time expression See Sequential Circuits for details Unsupported Assertion Statement Supported only for static conditions Signal Assignment Supported delay is ignored Statement Variable Assignment Supported Statement Procedure Call Statement Supported If Statement Supported Case Statement Supported www xilinx com 1 800 255 7778 XST User Guide VHDL Language Support XST User Guide Table 6 10 Supported VHDL Statements XILINX for loop end loop Supported for constant bounds only
31. Note XST does not support connection to bi directional pass switches in Verilog XST does not support unnamed Verilog ports for mixed language boundaries Use an equivalent component declaration for connecting to a case sensitive port in a Verilog module By default XST assumes Verilog ports are in all lower case XST supports the following VHDL data types for mixed language designs bit bit vector std logic std ulogic std logic vector 9 9 9 9 o std ulogic vector XST supports the following Verilog data types for mixed language designs e wire reg Generics Support in Mixed Language Projects XST supports the following VHDL generic types and their Verilog equivalents for mixed language designs 358 integer real string boolean www xilinx com XST User Guide 1 800 255 7778 Library Search Order File XILINX Library Search Order File The Library Search Order LSO file specifies the search order that XST uses to link the libraries used in VHDL Verilog mixed language designs By default XST searches the files specified in the project file in the order in which they appear in that file XST uses the default search order when either the DEFAULT_SEARCH_ORDER keyword is used in the LSO file or the LSO file is not specified Project Navigator In Project Navigator the default name for the LSO file is project_name 1so Ifa project name 1so file does not already exist Project Navigator automatically
32. RAM addr1 end always posedge clk2 begin do2 lt RAM addr2 end always posedge clk1 begin if enl 1 b1 resl lt dol end always posedge clk2 begin if en2 1 b1 res2 do2 end endmodule then enl en2 addrl addr2 di Following is the Verilog code for a Block Ram with optional output registers resl res2 172 www xilinx com 1 800 255 7778 XST User Guide RAMs ROMs XILINX During the HDL Synthesis process XST recognizes BRAM and 2 optional output registers as separate objects from BRAM Itis atthe Advanced HDL Synthesis step that XST pushes the optional registers to BRAM HDL Synthesis Found 128x8 bit dual port block RAM for signal lt mem gt mode read first dual mode read first aspect ratio 128 word x 8 bit clock connected to signal lt c1k1 gt rise dual clock connected to signal lt clk2 gt rise write enable connected to signal lt we gt high address connected to signal lt addr1 gt dual address connected to signal lt addr2 gt data in connected to signal lt di gt data out connected to signal lt dol gt dual data out connected to signal lt do2 gt ram_style Auto Found 8 bit register for signal lt resl gt Found 8 bit register for signal lt res2 gt Advanced HDL Synthesis E INFO Xst 1954 Data output of block RAM lt Mram_mem gt in block lt m_bram_1 gt
33. Setting Global Constraints and Options in Chapter 5 Changed behavior for Maximum Fanout MAX_FANOUT constraint when it applies to a specific signal See Max Fanout and Constraints Summary in Chapter 5 Convert Tristates To Logic constraint TRISTATE2LOGIC is now active by default for new projects in Xilinx Specific Process Properties See Convert Tristates to Logic and Constraints Summary in Chapter 5 Buffer Type constraint BUFFER TYPE can now be applied on internal clocks See Virtex Primitive Support in Chapter 3 Buffer Type and Constraints Summary in Chapter 5 Introduced new value bufr for Buffer Type constraint BUFFER TYPE See Buffer Type in Chapter 5 Introduced new command line switch bufr to control the number of available regional clock buffers for Virtex 4 devices See Number of Regional Clock Buffers in Chapter 5 Clock Signal constraint CLOCK SIGNAL can now be applied to internal clocks See Clock Signal and Constraints Summary in Chapter 5 Improved Box Type constraint BOX TYPE support See Box Type and Constraints Summary in Chapter 5 New value user black box implemented BOX TYPE is now supported via XCF file Introduced new Duplication Suffix command line switch DUPLICATION SUFFIX to control name generation of replicated flip flops See Duplication Suffix and Constraints Summary in Chapter 5 Run Command in Chapter 10 and Name G
34. XST User Guide Getting Help Z XILINX e To geta list of supported families type help at the command line prompt with no argument XST displays the following message gt help ERROR Xst 1356 Help Missing arch lt family gt Please specify what family you want to target available families spartan3 spartan2 spartan2e virtex virtex2 virtex2p virtex4 virtexe xbr xc9500 xc9500x1 xpla3 e To get a list of available commands for a specific family type the following at the command line prompt with no argument help arch family name For example help arch virtex Example Use the following command to get a list of available options and values for the run command for Virtex II help arch virtex2 command run XST User Guide www xilinx com 389 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode This command gives the following output mult_style Multiplier Style block lut auto pipe_lut bufg Maximum Global Buffers bufgce BUFGCE Extraction YES NO decoder extract Decoder Extraction YES NO ifn 4 ifmt Mixed VHDL Verilog Ofn ofmt NGC NCD p ent top z opt mode AREA SPEED opt level 1 2 keep hierarchy YES NO vlgincdir verilog2001 YES NO vlgcase Full Parallel Full Parallel Set Command In addition to the run command XST also reco
35. dia end if read_addra lt addra end if end if end process process clk begin if clk event and clk 1 then if enb 1 then read addrb lt addrb end if end if end process doa lt RAM conv integer read addra dob lt RAM conv integer read addrb end syn 160 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Verilog Code Following is the Verilog code for a dual port RAM with enable on each port module raminfr clk ena enb wea addra addrb dia doa dob input clk ena enb wea input 4 0 addra addrb input 3 0 dia output 3 0 doa dob reg 3 0 ram 31 0 reg 4 0 read_addra read_addrb always posedge clk begin if ena begin if wea begin ram addra lt dia end end end always posedge clk begin if enb begin read_addrb lt addrb end end assign doa ram read addra assign dob ram read addrb endmodule Dual Port Block RAM with Different Clocks XST User Guide The following example shows where the two clocks are used DIA BLOCK RAM WEA ADDRA DOA ADDRB DOB CLKA CLKB X9799 The following table shows pin descriptions for a dual port RAM with different clocks IO Pins Description clka Positive Edge Clock clkb Positive Edge Clock www xilinx com 161 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 10 Pins Description w
36. in2 Constants Macros Include Files and Comments This section discusses constants macros include files and comments Constants By default constants in Verilog are assumed to be decimal integers They can be specified explicitly in binary octal decimal or hexadecimal by prefacing them with the appropriate syntax For example 4 51010 4 012 4 d10 and 4 ha all represent the same value Macros Verilog provides a way to define macros as shown in the following example define TESTEO1 4 b1101 Later in the design code a reference to the defined macro is made as follows if request TESTEQ1 This is shown in the following example define myzero 0 assign mysig myzero Verilog provides the ifdef and endif constructs to determine whether a macro is defined or not These constructs are used to define conditional compilation If the macro called out by the ifdef command has been defined that code is compiled If not the code following the else command is compiled The else is not required but the endif must complete the conditional statement The ifdef and endif constructs are shown in the following example ifdef MYVAR module if MYVAR is declared endmodule else module if_MYVAR_is_not_declared endmodule endif Include Files Verilog allows separating source code into more than one file To use the code contained in another file the cu
37. input 4 0 addr input 3 0 di output 3 0 do reg 3 0 RAM 31 0 reg 3 0 do always posedge clk begin if en begin if we RAM addr lt di do lt RAM addr end end endmodule Write First Mode The following templates show a single port RAM in write first mode VHDL Code The following template shows the recommended configuration coded in VHDL library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std_logic en in std_logic addr in std_logic_vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr XST User Guide www xilinx com 137 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di do lt di else do lt RAM conv_integer addr end if end if end if end process end syn The following templates show an alternate configuration of a single port RAM in write first mode with a registered read address coded in VHDL library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std_logic en in std_logic
38. reg outp reg 1 0 state reg 1 0 next_state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always posedge clk or posedge reset begin if reset state lt sl else state lt next_state end always G state or x1 begin case state sl if xl 1 b1 next state s2 else S2 next state s4 s3 next state s4 s4 next state sl endcase end XST User Guide www xilinx com 189 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques always state begin case state sl outp 1 b1 s2 outp 1 b1 s3 outp 1 b0 s4 outp 1 b0 endcase end endmodule State Registers State registers must be initialized with an asynchronous or synchronous signal XST does not support FSM without initialization signals Please refer to Registers in this chapter for templates on how to write Asynchronous and Synchronous initialization signals In VHDL the type of a state register can be a different type integer bit_vector std_logic_vector for example But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type In Verilog the type of state register can be an integer or a set of defined parameters In the following Verilog examples the state assignments could have been made like this parameter 3 0 sl 4 b0001 s2 4 p0010 s3 4 b0100 s4 4 p1000 r
39. 0 15 Data Types The Verilog representation of the bit data type contains the following four values e 0 logic zero e 1 logic one e x unknown logic value e z high impedance XST includes support for the following Verilog data types e Net wire tri triand wand trior wor e Registers reg integer e Supply nets supply0 supply1 e Constants parameter e Multi Dimensional Arrays Memories Net and registers can be either single bit scalar or multiple bit vectors The following example gives some examples of Verilog data types as found in the declaration section of a Verilog module Example 7 1 Basic Data Types wire netl single bit net reg rl single bit register tri 7 0 busl 8 bit tristate bus reg 15 0 busl 15 bit register reg 7 0 mem 0 127 8x128 memory register parameter statel 3 b001 3 bit constant parameter component TMS380C16 string 324 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Legal Statements The following are statements that are legal in behavioral Verilog Variable and signal assignment e Variable expression e if condition statement e if condition statement else statement e case expression expression statement default statement endcase e for variable expression condition variable variable expression statement e while condition statement e forever statement e functions and tasks N
40. ADD A 0 B 0 CIN S0 ADD A 1 B 1 SO 1 S1 ADD A 2 B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S S3 0 S2 0 S1 0 SO 0 COUT S3 1 end endmodule Blocking Versus Non Blocking Procedural Assignments The and time control statements delay execution of the statement following them until the specified event is evaluated as true Use of blocking and non blocking procedural assignments have time control built into their respective assignment statement The delay is ignored for synthesis The syntax for a blocking procedural assignment is shown in the following example reg a a 10 b c or if inl out 1 b0 else out in2 As the name implies these types of assignments block the current process from continuing to execute additional statements at the same time These should mainly be used in simulation Non blocking assignments on the other hand evaluate the expression when the statement executes but allow other statements in the same process to execute as well at the same time The variable change only occurs after the specified delay XST User Guide www xilinx com 337 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support The syntax for a non blocking procedural assignment is as follows variable lt posedge_or_negedge_bit expression The following shows an example of how to use a non blocking procedural assignment if inl out lt 1 b1 else out lt
41. CLK begin if CLK EVENT and CLK 1 then DO lt DI end if end process end ARCHI Example 6 19 8 bit Register Description Using a Process without a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE XST User Guide www xilinx com 305 1 800 255 7778 XILINX Chapter 6 VHDL Language Support architecture ARCHI of EXAMPLE is begin process begin wait until CLK EVENT and CLK 1 DO lt DI end process end ARCHI Example 6 20 describes an 8 bit register with a clock signal and an asynchronous reset signal Example 6 20 8 bit Register Description Using a Process with a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT RST in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK RST begin if RST 1 then DO lt 00000000 elsif CLK EVENT and CLK 1 then DO lt DI end if end process end ARCHI Example 6 21 8 bit Counter Description Using a Process with a Sensitivity List library ASYL use ASYL PKG_ARITH all entity EXAMPLE is port CLK in BIT RST in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is beg
42. Related source file is C temp timer smallcntr vhd Found 4 bit up counter for signal lt qoutsig gt Summary inferred 1 Counter s Unit lt smallcntr gt synthesized Synthesizing Unit lt hex2led gt Related source file is C temp timer hex2led vhd Found 16x7 bit ROM for signal lt LED gt Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt cnt60 gt Related source file is C temp timer cnt60 vhd Unit lt cnt60 gt synthesized Synthesizing Unit lt decode gt Related source file is C temp timer decode vhd Found 16x10 bit ROM for signal lt one_hot gt Summary inferred 1 ROM s Unit lt decode gt synthesized XST User Guide www xilinx com 369 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Synthesizing Unit lt statmach gt Related source file is C temp timer statmach vhd Found finite state machine lt FSM_0 gt for signal lt current_state gt States 6 Transitions 11 Inputs 1 Outputs 2 Clock CLK rising_edge Reset RESET positive Reset type asynchronous Reset State clear Power Up State clear Encoding one hot Implementation LUT Summary inferred 1 Finite State Machine s Unit lt statmach gt synthesized Synthesizing Unit lt stopwatch gt Related source file is C temp timer stopwatch vhd WARNING Xst 646 Signal lt strtstopinv gt is assigned but never used Unit lt stopwatch gt synthesized
43. SI CE in std logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 0 then if CE 1 then for i in 0 to 6 loop tmp i 1 lt tmp i end loop tmp 0 lt SI end if end if end process SO lt tmp 7 end archi 74 www xilinx com XST User Guide 1 800 255 7778 Shift Registers XILINX Verilog Code Following is the Verilog code for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out module shift C CE SI SO input C SI CE output SO reg 7 0 tmp always negedge C begin if CE begin tmp lt tmp lt lt 1 tmp 0 lt SI end end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Out Note Because this example includes an asynchronous clear XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock an asynchronous clear a serial in and a serial out 10 Pins Description C Positive Edge Clock SI Serial In CLR Asynchronous Clear active High SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock an asynchronous clear a serial in and a serial out library ieee use ieee std logic
44. Table 7 2 Results of Evaluating Expressions ab a b a b al b al b a amp b a amp amp b a b a b a b 00 1 1 0 0 0 0 0 0 0 01 0 0 1 1 0 0 1 1 1 0x x 0 x 1 0 0 x x x 0z x 0 x 1 0 0 x x x 10 0 0 1 1 0 0 1 1 1 11 1 1 0 0 1 1 1 1 0 1x x 0 x 1 x x 1 1 x 1z x 0 x 1 x x 1 1 x x 0 x 0 x 1 0 0 x x x x1 x 0 x 1 x x 1 1 x Xx x 1 x 0 x x x x x XZ x 0 x 1 x x x x x z0 x 0 x 1 0 0 x x x z1 x 0 x 1 x x 1 1 x ZX x 0 x 1 x x x x x ZZ x 1 x 0 x x x x x www xilinx com 1 800 255 7778 327 XILINX 328 Blocks Modules Chapter 7 Verilog Language Support Block statements are used to group statements together XST only supports sequential blocks Within these blocks the statements are executed in the order listed Parallel blocks are not supported by XST Block statements are designated by begin and end keywords and are discussed within examples later in this chapter In Verilog a design component is represented by a module The connections between components are specified within module instantiation statements Such a statement specifies an instance of a module Each module instantiation statement must be given a name instance name In addition to the name a module instantiation statement contains an association list that specifies which actual nets or ports are associated with which local ports formals of the module declaration All procedu
45. The constraints attributes specified in the HDL design or in the constraint files are written by XST into the NGC file as signal properties Improving Results XST produces optimized netlists for the CPLD fitter which fits them in specified devices and creates the download programmable files The CPLD low level optimization of XST consists of logic minimization subfunction collapsing logic factorization and logic decomposition The result of the optimization process is an NGC netlist corresponding to Boolean equations which are reassembled by the CPLD fitter to fit the best of the macrocell capacities A special XST optimization process known as equation shaping is applied for XC9500 XL XV devices when the following options are selected e Keep Hierarchy No e Optimization Effort 2 or High e Macro Preserve No The equation shaping processing also includes a critical path optimization algorithm which tries to reduce the number of levels of critical paths The CPLD fitter multi level optimization is still recommended because of the special optimizations done by the fitter D to T flip flop conversion De Morgan Boolean expression selection How to Obtain Better Frequency The frequency depends on the number of logic levels logic depth In order to reduce the number of levels the following options are recommended e Optimization Effort 2 or High this value implies the calling of the collapsing algorithm which tries t
46. X 08201 X 00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X 0241E X 00301 X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X 00303 x 02433 X 00301 X 04004 X 00301 X 00102 X 02137 X 02036 X 00301 X 00102 X 02237 X 04004 X 00304 x 04040 X 02500 X 02500 X 02500 X 0030D X 02341 X 08201 X 0400D process clk begin if rising edge clk then if we 1 then RAM conv integer a lt di end if ra lt a end if end process do lt RAM conv_integer ra The block RAM initial contents can be specified in hexadecimal as in the previous example or in binary as shown in the following example type ram_type is array 0 to SIZE 1 of std_logic_vector 15 downto 0 signal RAM ram_type o111100100000101 0000010110111101 1100001101010000 0000100101110011 174 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX e Specify a dual port block RAM initial contents using the following VHDL code library ieee use ieee std logic 1164 a1l use ieee std logic unsigned all entity raminfr is port clkl in std_logic clk2 in std_logic we in std logle addrl in std_logic_vector 7 downto 0 addr2 in std_logic_vector 7 downto 0 di i
47. addr in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 do out std_logic_vector 3 downto 0 end raminfr architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_addr std_logic_vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then mem conv_integer addr lt di end if read_addr lt addr end if end if end process do lt ram conv_integer read_addr end syn 138 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Verilog Code The following template shows the recommended configuration coded in Verilog module raminfr clk we en addr di do input clk input we input en input 4 0 addr input 3 0 di output 3 0 do reg 3 0 RAM 31 0 reg 4 0 read_addr always posedge clk begin if en begin if we RAM addr lt di read_addr lt addr end end assign do RAM read addr endmodule No Change Mode The following templates show a single port RAM in no change mode VHDL Code The following template shows the recommended configuration coded in VHDL library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std_logic en in std_logic addr in std_logic_vector 4 downto 0 di in std_logic_vector 3
48. and the begin statement must be named with a unique qualifier 340 www xilinx com XST User Guide 1 800 255 7778 Variable Part Selects XILINX The following is an example of a generate case statement The generate controls what type of adder is instantiated generate case WIDTH Lis begin casel_name adder WIDTH 8 xl a b ci sum case cO case end 25 begin case2 name adder WIDTH 4 x2 a b ci sum case cO case end default begin d case name adder x3 a b ci sum case cO case end endcase endgenerate Variable Part Selects Verilog 2001 adds the capability to use variables to select a group of bits from a vector A variable part select is defined by the starting point of its range and the width of the vector instead of being bounded by two explicit values The starting point of the part select can vary but the width of the part select remains constant e Indicates that the part select increases from the starting point e Indicates that the part select decreases from the starting point Example reg 3 0 data reg 3 0 select a value from 0 to 7 wire 7 0 byte data select 8 Structural Verilog Features XST User Guide Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design The basic concepts of hardware structure are the module the port and the signal The component is the building or basic block
49. assigned to the signal on the left part Simple Signal Assignment The following example shows a simple assignment T lt A and B XST User Guide www xilinx com 297 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Selected Signal Assignment The following example shows a selected signal assignment Example 6 5 MUX Description Using Selected Signal Assignment library IEEE use IEEE std_logic_1164 all entity select_bhv is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end select bhv architecture bhv of select bhv is begin with selector select T lt a when 00 b when O1 c when 10 d when others end bhv Conditional Signal Assignment The following example shows a conditional signal assignment Example 6 6 MUX Description Using Conditional Signal Assignment entity when ent is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end when ent architecture bhv of when ent is begin T lt a when selector 00 els b when selector 01 els c when selector 10 els d end bhv Generate Statement Repetitive structures are declared with the generate VHDL statement F
50. dia doa dob input clka input clkb input wea input 4 0 addra input 4 0 addrb input 3 0 dia output 3 0 doa output 3 0 dob reg 3 0 RAM 31 0 reg 4 0 read_addra reg 4 0 read_addrb always posedge clka begin if wea 1 b1 RAM addra lt dia read_addra lt addra end always posedge clkb begin read_addrb lt addrb end assign doa RAM read_addra assign dob RAM read_addrb endmodule Dual Port Block RAM with Two Write Ports Starting with release 7 1i XST supports dual port block RAMs with two write ports Please note that this feature supports for VHDL only The notion of dual write ports implies not only distinct data ports but also possibly distinct write clocks and write enables Note that distinct write clocks also means distinct read clocks since the dual port block RAM offers two clocks one shared by the primary read and write port the other shared by the secondary read and write port The description of this type of block RAM is based on the usage of shared variables Until 7 1i release shared variables were not supported and XST would error out with a specific message during VHDL parsing In release 7 1i the XST VHDL analyser accepts all shared XST User Guide www xilinx com 163 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques variables but errors out in the HDL Synthesis step if a shared variable does not describe a valid RAM macro The fo
51. exp x cos x cosh x floor x realmin x y log x tan x tanh x round x sqrt x log2 x arcsin x arcsinh x trunc x cbrt x log10 x arctan x arccosh x sign x e n y log x y arctan y x arctanh x mod xy Gcy sin x sinh x The procedure uniform which generates successive values between 0 0 and 1 0 Note Functions and procedures in the math real package as well as the real type are for calculations only They are not supported for synthesis in XST Example library ieee use IEEE std logic signed all signal a b c std logic vector 5 downto 0 c lt a b this operator is defined in package std logic signed Operands are converted to signed vectors and function defined in package std logic arith is called with signed operands Synopsys Packages The following Synopsys packages are supported in the IEEE library XST User Guide std logic arith supports types unsigned signed vectors and all overloaded arithmetic operators on these types It also defines conversion and extended functions for these types std logic unsigned defines arithmetic operators on std ulogic vector and considers them as unsigned operators std logic signed defines arithmetic operators on std logic vector and considers them as signed operators std logic misc defines supplemental types subtypes constants and functions for the std logic
52. if LEVA must be resynthesized then apply the RESYNTHESIZE constraint to this block All blocks included in the leva logic group are re optimized and new NGC files are generated as shown in the following log file segment Low Level Synthesis Incremental synthesis Unit my and is up to date Incremental synthesis Unit my or is up to date Incremental synthesis Unit levb is up to date Incremental synthesis Unit top is up to date Optimizing unit my sub Optimizing unit my add Optimizing unit leva 1 Optimizing unit leva 2 Optimizing unit leva XST User Guide www xilinx com 211 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization If you have previously run XST in non incremental mode and then switched to incremental mode or the decomposition of the design has changed you must delete all previously generated NGC files before continuing Otherwise XST issues an error In the previous example adding incremental_synthesis true to the block LEVA_1 XST gives the following error ERROR Xst 624 Could not find instance inst leva 1 of cell lt leva_1 gt in leva The problem most likely occurred because the design was previously run in non incremental synthesis mode To fix the problem remove the existing NGC files from the project directory Please note that if you modified the HDL in the top level block of the design and at the same time changed
53. input output output SUM CO CI 7 0 A 720 B 7 0 SUM GO wire 8 0 tmp assign assign assign endmodule 108 tmp A B CI SUM tmp 7 0 CO tmp 8 www xilinx com 1 800 255 7778 XST User Guide Arithmetic Operations XILINX Simple Signed 8 bit Adder The following table shows pin descriptions for a simple signed 8 bit adder 10 pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result VHDL Code Following is the VHDL code for a simple signed 8 bit adder library ieee use ieee std logic 1164 all use ieee std logic signed all entity adder is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 end adder architecture archi of adder is begin SUM lt A B end archi Verilog Code Following is the Verilog code for a simple signed 8 bit adder module adder A B SUM input signed 7 0 A input signed 7 0 B output signed 7 0 SUM wire signed 7 0 SUM assign SUM A B endmodule Unsigned 8 bit Subtractor The following table shows pin descriptions for an unsigned 8 bit subtractor IO pins Description A 7 0 B 7 0 Sub Operands RES 7 0 Sub Result XST User Guide www xilinx com 109 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for an unsigned 8 bit subtractor library ieee use ieee std_logic_1164 all use ieee
54. is tied to register lt resl gt in block lt m_bram_1 gt The register is absorbed by the block RAM and provides isolation from the interconnect routing delay for maximal operating frequency INFO Xst 1955 Dual data output of block RAM Mram mem in block m bram 1 is tied to register lt res2 gt in block m bram 1 The register is absorbed by the block RAM and provides isolation from the interconnect routing delay for maximal operating frequency XST User Guide www xilinx com 173 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Initializing Block RAM Block RAM initial contents can be specified by initialization of the signal describing the memory array in your HDL code You can do this directly in your HDL code or you can specify a file containing the initialization data Starting from release 7 11 XST supports initialization for dual port block RAMs Please note that this mechanism is supported only for Virtex II Virtex II Pro Spartan 3 and Virtex 4 device families Note XST does not support block RAM initialization in Verilog VHDL Code e Specify block RAM initial contents by initializing the signal describing the memory array in your VHDL code as in the following example type ram_type is array 0 to 63 of std_logic_vector 19 downto 0 Signal RAM ram_type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002
55. language forms www xilinx com 283 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Allows the design of a system to be simulated prior to being implemented and manufactured This feature allows you to test for correctness without the delay and expense of hardware prototyping Provides a mechanism for easily producing a detailed device dependent version of a design to be synthesized from a more abstract specification This feature allows you to concentrate on more strategic design decisions and reduce the overall time to market for the design File Type Support XST supports a limited File Read capability for VHDL You can use this file read capability for example to initialize RAMs from an external file Please refer to Initializing Block RAM in Chapter 2 for more information You can use any of the following read functions which are supported by the standard std textio and ieee std_logic_textio packages respectively Table 6 1 Supported File Types Function Package file type text only standard access type line only standard file_open file name open_kind standard file_close file standard endfile file standard text std textio line std textio width std textio readline text line std textio read line bit std textio read line bit_vector std textio read line boolean std textio read line std_ulogic ieee std_logic_te
56. multiplexer glue logic finite state machine where the connections are N bit wires Use of an HDL language like Verilog allows expressing notations such as ASM charts and circuit diagrams in a computer language Verilog provides both behavioral and structural language structures which allow expressing design objects at high and low levels of abstraction Designing hardware with a language like Verilog allows usage of software concepts such as parallel processing and object oriented programming Verilog has a syntax similar to C and Pascal and is supported by XST as IEEE 1364 The Verilog support in XST provides an efficient way to describe both the global circuit and each block according to the most efficient style Synthesis is then performed with the best synthesis flow for each block Synthesis in this context is the compilation of high level www xilinx com 321 1 800 255 7778 XILINX Chapter 7 Verilog Language Support behavioral and structural Verilog HDL statements into a flattened gate level netlist which can then be used to custom program a programmable logic device such as the Virtex FPGA family Different synthesis methods are used for arithmetic blocks glue logic and finite state machines This manual assumes that you are familiar with the basic notions of Verilog Please refer to the IEEE Verilog HDL Reference Manual for a complete specification Behavioral Verilog Features This section contains descriptions
57. no XC9500 CoolRunner XPLA3 II read_cores na na na na yes yes no optimize Spartan II IIE 3 Virtex TI TI Pro IL Pro X E 4 sd na na na na yes directory_path Spartan II IIE 3 Virtex TI II Pro E tristate2logic yes no true false internal tristates only model net in model entity signal module signal yes yes no Spartan II TIE Virtex TI TI Pro IL Pro X E slice packing na na na na yes yes no XC9500 CoolRunner XPLA3 II uc na na na na yes file name xcf Spartan TI TIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II verilog2001 na na na na yes yes no Spartan II IIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II vlgcase na na na na full parallel full parallel Spartan TI TIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II 274 www xilinx com 1 800 255 7778 XST User Guide Constraints Summary XILINX Table 5 1 XST Specific Non timing Options XCF Constraint Consiraint Constraint VHDL Verilog ins Cmd Technology Name Value Syntax Target Target Value Target vlgincdir na na na na yes dir path Spartan TI TIE 3 Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner
58. process CLKA begin if CLKA event and CLKA 1 then DOA lt RAM conv_integer ADDRA The read statement must come BEFORE the write statement if WEA 1 then RAM conv integer ADDRA DIA end if end if end process No Change The following is a description for a no change synchronization process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA else DOA lt RAM conv integer ADDRA end if end if end process Multiple Port RAM Descriptions XST can identify RAM descriptions with two or more read ports that access the RAM contents at addresses different from the write address However there can only be one write port XST implements the following descriptions by replicating the RAM contents for each output port as shown DO1 DO2 X8983 The following table shows pin descriptions for a multiple port RAM IO pins Description clk Positive Edge Clock we Synchronous Write Enable Active High wa Write Address 166 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX 10 pins Description ral Read Address of the First RAM ra2 Read Address of the Second RAM di Data Input dol First RAM Output Port do2 Second RAM Output Port VHDL Code Following is the VHDL code for a multiple port RAM library ieee use ieee std_logic_1164 all use ieee
59. sel input 1 0 i1 i2 i3 i4 output 1 0 o1 reg 1 0 ol always G sel or il or i2 or i3 or i4 begin case sel 2 b00 ol il 2 b01 ol i2 2 b10 ol i3 2 b11 ol i4 endcase end endmodule Not Full but Parallel module notfull sel il 12 13 ol input 1 0 sel input 1 0 i1 12 13 output 1 0 o1 reg 1 0 ol always sel or il or i2 or 13 begin case sel 2 b00 ol il 2 b01 ol i2 2 b10 ol i3 endcase end endmodule 86 www xilinx com XST User Guide 1 800 255 7778 Multiplexers XST User Guide XILINX Neither Full nor Parallel module notfull notparallel sell sel2 il i2 o1 input 1 0 sell sel2 input 1 0 il i2 output 1 0 o1 reg 1 0 o1 always G sell or sel2 begin case 2 b00 sell ol il sel2 ol i2 endcase end endmodule XST automatically determines the characteristics of the Case statements and generates logic using multiplexers priority encoders and latches that best implement the exact behavior of the Case statement This characterization of the Case statements can be guided or modified by using the Case Implementation Style parameter Please refer to the Chapter 5 Design Constraints for more details Accepted values for this parameter are none full parallel and full parallel e Ifnone is used the default XST implements the exact behavior of the Case statements I
60. state machine 182 auto 191 compact 191 gray 191 johnson 191 next state equation 190 one hot 191 RAM based FSM synthesis 194 safe FSM implementation 194 sequential 191 speed1 191 state encoding technique 191 state register 190 unreachable state 190 user 192 state_vector 279 string constants 348 structural Verilog description 341 subprogram 314 subtraction 325 subtractor 104 unsigned 8 bit subtractor 109 switch level primitives 351 syn_allow_retiming 279 syn_black_box 280 syn_direct_enable 280 syn_edif_bit_format 280 syn_edif_scalar_format 280 syn_encoding 280 syn enum encoding 280 syn hier 280 syn isclock 280 syn keep 280 syn maxfan 280 syn netlist hierarchy 280 syn noarrayports 280 syn noclockbuf 280 syn noprune 280 syn pipeline 280 syn probe 280 syn ramstyle 280 syn reference clock 280 syn romstyle 280 syn sharing 280 syn state machine 281 syn tco 281 syn tpd 281 syn tristate 281 syn tristatetomux 281 syn tsu 281 syn useenables 281 syn useioff 281 Synopsys 279 281 synopsys package 313 Synplicity 279 281 synthesis constraint file 237 250 synthesis constraints file 384 synthesis options 234 synthesis options summary 363 synthesis translate off 281 synthesis translate on 281 system function 350 system task 350 T target technology 384 task 350 temp directory 381 temporary files 381 third party constraints 279 tig 267 timegrp 267 timescale 350 timing constraints 263 timing
61. 0 signal read_dpra std_logic_vector 4 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if read_a lt a read_dpra lt dpra end if end process spo lt RAM conv_integer read_a dpo lt RAM conv_integer read_dpra end syn Verilog Code Following is the Verilog code for a dual port RAM with synchronous read read through module raminfr clk we a dpra di spo dpo input clk input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 reg 4 0 read_a reg 4 0 read_dpra always posedge clk begin if we ram a lt di read_a lt a read_dpra lt dpra end assign spo ram read a assign dpo ram read_dpra endmodule Using More than One Clock The two RAM ports may be synchronized on distinct clocks as shown in the following description In this case only a block RAM implementation is applicable The following table shows pin descriptions for a dual port RAM with synchronous read read through and two clocks IO pins Description clk1 Positive Edge Write Primary Read Clock clk2 Positive Edge Dual Read Clock 154 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX IO pins Description we Synchronous Write Enable Active High add1 Write Primary Read Address add2 D
62. 1164 a11 entity shift is port C SI CLR in std logic SO out std logic end shift XST User Guide www xilinx com 75 1 800 255 7778 76 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of shift is signal tmp std_logic_vector 7 downto 0 begin process C CLR begin if CLR 1 then tmp lt others gt 0 elsif C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock asynchronous clear serial in and serial out module shift C CLR SI SO input C SI CLR output SO reg 7 0 tmp always posedge C or posedge CLR begin if CLR tmp lt 8 b00000000 else begin tmp lt tmp 6 0 SI end end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out Note For this example XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a synchronous set a serial in and a serial out IO Pins Description C Positive Edge Clock SI Serial In S Synchronous Set active High SO Serial Output www xilinx com XST User Guide 1 800 255 7778 Shift Registers XILINX VHDL Code Following is the VHDL code for an 8 bit shift left registe
63. 152 Verlo Code eds oe eA Sa a eee eee a aa 152 Dual Port RAM with Synchronous Read Read Through 00 153 VEIDL Code 5 hla Re e ib RI I ae ae E Rs 153 Verilog Coder mST 154 Using More than One Clock 0 0 cece teen eens 154 Dual Port RAM with One Enable Controlling Both PortS 156 VHDL Code 123 debe ee Ie e ee bet ee ede de wed 157 Verilog Code do eese sedute dad pesce late Sox radeon ees ert 158 Dual Port RAM with Enable on Each Port 2 0 00 00 c ccc cee 159 VADE Code M gem ae a E E ae 160 Verilog Code soii aia 161 XST User Guide www xilinx com 11 1 800 255 7778 XILINX Dual Port Block RAM with Different ClockS o ooooooooooooooomomo o 161 XEHDL Code rin a ee er A ARA A AR ai EE E na 162 Verilog Codettearrrda ato pa brida da aa ree retos 163 Dual Port Block RAM with Two Write Ports 0 sese 163 Write Hitsts tates ss A A pee es Bod ee ei Se 165 R ad Fitst iii hed bead e Re Sees deka RE KR eee Hae EIA d 166 No Ch ange eeok eue brsieree ia aieiaa aa phase cba bbs boe 166 Multiple Port RAM Descriptions s seism us ppa mesine Ie 166 MEIDL Code zu eae ee tea a ed edu eda WES EE eel 167 Verilog Codes cer estt ts ia oodd eaa e dace cane ea cede dos 168 Block RAM with Reset 0 00 0 c ccc ccc teen ene t 168 VEHDL Code ini 4 43 vareh a ERR DER RAT RES ie E Da EE 169 Venlog Codev iid aid ico oie e os wate ice 170 Block RAM with Optional Output Registers
64. 281 xc_isgsr 281 xc_loc 281 xc_map 281 xc_ncf_auto_relax 281 xc_nodelay 281 xc_padtype 281 xc_props 281 xc_pullup 282 xc_rloc 282 xc_slow 282 XC9500 19 XC9500XL 19 XC9500XV 19 XCF 244 266 XCF file 277 XCF syntax 244 277 XCF timing constraint 265 Xilinx specific options 240 XOR 262 XOR collapsing 239 259 386 XOR macros 262 XOR preserve 241 262 386 xor_collapse 259 386 XST constraint file 244 XST constraints file 266 XST flow 19 XST in Project Navigator 22 XST log file 30 XST script 383 XST shell 382 xsthdpdir 252 390 xsthdpini 251 390 XST specific non timing options 268 406 www xilinx com 1 800 255 7778 XST User Guide
65. 326 logical inequality 326 logical negation 326 logical or 326 logical shift extraction 386 logical shifter extraction 239 256 logical shifters 99 loop statement 319 low level optimization 29 low level synthesis 364 Iso 249 359 384 391 LSO file 359 lut_map 259 270 macro generation 197 228 macro preserve 241 261 262 386 macro preserve option 228 macromodule definition 350 map entity on a single LUT 259 map logic on BRAM 256 map to module 279 max fanout 240 256 max delay 264 265 max fanout 256 258 270 387 maximum fanout 387 maximum number of bufg 387 mealy 183 meta comments 347 mixed language generics support 358 mixed language instantiation 356 mixed language port mapping 358 mixed language project file 356 mixed language support 355 mode 316 model 244 245 module definition 350 modulus 325 moore machine 183 move first flip flop stage 388 move first stage 240 256 move last flip flop stage 388 move last stage 240 256 move first stage 256 270 388 move last stage 256 270 388 mult style 113 114 256 270 386 multi dimensional array 348 multiple wait statements 306 multiplexer 83 85 4 to 1 1 bit MUX using if statement 88 4 to 1 MUX using case statement 89 4 to 1 MUX using tristate buffers 91 full 86 full and parallel case 86 neither full nor parallel 87 no 4 to 1 MUX 91 not full but parallel 86 parallel 86 multiplication 325 multiplication with constant 114
66. 341 Structural Verilog Features criar pr e RR ar dads RR ai des 341 Parameters sis isc dco EU EE DR Haugh EYE its E E dE es 343 Parameter Attribute Conflicts ssssssssesssee cece eens 344 Verilog Limitations in XST cu ess cao ia dd do eid 345 Case Sensitivity isses ie e RR dA kr ae En ia e RR c Re o a 345 Blocking and Nonblocking Assignments 06 666 c cece eee eee ees 346 Integer Handle iio setae eee I aes a Pi eat 346 Verilog Meta Comments cti a ae diee dal te C tla ac oa oo aie 347 Verilog Language Support Tables 0 0 0 cece eee eee 348 PrimiliveS oras rra ti yebe cine adds cds bae 351 Verilog Reserved Key Words cocinada cate hoi to peti oy diodos eh ie 352 Verilog 2001 Support in XST so0 0 cooccinecrines ue hh REA ee 353 16 www xilinx com XST User Guide 1 800 255 7778 XILINX Chapter 8 Mixed Language Support Introduction 0 00 ccc cc RR e a 355 Mixed Language Project File 0 eese 356 VHDL Verilog Boundary Rules 0 0 0 356 Instantiating a Verilog Module ina VHDL Design 0000 e eee ee 356 Instantiating a VHDL Design Unit in a Verilog DesigN ooooooooommmo 357 II teat eee a ue dd 358 Generics Support in Mixed Language Projects usuuuuuuuuuuuee 358 Library Search Order Fleitas oce Hand E den 359 Project Navigator cu eios ice deor ce COE ed oai Queso ed IA 359 Command Line iwi seb eb eeRR I RERIG cane HUE Du sede ieu
67. 363 synthesis options 385 HDL library mapping file 237 251 390 HDL synthesis report 363 hdl compilation order 385 help 388 hierarchical names 350 hierarchy separator 237 248 384 hierarchy separator 248 265 384 400 IEEE package 312 if statement 349 ifdef 350 ifmt 384 391 ifn 384 391 if then else 85 ignore user constraints 384 implementation constraints 277 include 350 include files 338 incremental synthesis 256 incremental synthesis 255 256 269 indef 350 indexed names 317 402 www xilinx com 1 800 255 7778 XST User Guide XILINX initial statement 350 initial values 289 initialization data 174 inpad_to_outpad 264 265 input filename 384 input project format 384 input project filename 384 instance naming convention 399 integer constants 348 integer handling 346 integer type 286 integer types 315 IOB 257 iob 269 387 iobuf 386 387 iostandard 249 269 ispad 279 iuc 250 384 K KCM 114 keep 249 269 keep hierarchy 237 256 261 386 387 keep_hierarchy 256 261 269 386 387 L latch 48 4 bit latch with inverted gate and asynchronous preset 52 latch with positive gate 49 latch with positive gate and asyn chronous clear 50 launching XST 382 left shift 327 left shift signed 327 library search order 237 249 384 391 library search order file 359 line 351 loc 249 269 local reset 289 log file analysis 363 logical and 326 logical equality
68. BELS This group contains all the logical cells that are basic elements of the Virtex technology for example LUTs MUXCY MUXF5 MUXF6 MUXF7 MUXF8 Flip flops and Latches This group contains all the flip flops and latches that are primitives of the Virtex technology for example FDR FDRE LD RAMS This group contains all the RAMs SHIFTERS This group contains all the shift registers that use the Virtex primitives They are SRL16 SRL16_1 SRL16E SRL16E_1 and SRLC Tristates This group contains all the tristate primitives namely the BUFT www xilinx com XST User Guide 1 800 255 7778 Log File Analysis XILINX e Clock Buffers This group contains all the clock buffers namely BUFG BUFGP BUFGDLL e JO Buffers This group contains all the standard I O buffers except the clock buffer namely IBUF OBUF IOBUF OBUFT IBUF GIL e LOGICAL This group contains all the logical cells primitives that are not basic elements namely AND2 OR2 e OTHER This group contains all the cells that have not been classified in the previous groups The following section is an example of an XST report for cell usage Cell Usage BELS i0 LUT2 34 LUT3 23 LUT4 34 FlipFlops Latches 5 39 FDC 8 FDP PCI Clock Buffers 21 BUFGP 1 IO Buffers 24 IBUF 16 OBUF 38 Device Utilization summary Where XST estimates the number of slices gives the number of flip flops
69. Chapter 2 HDL Coding Techniques Description Using Combinatorial Process and Always Block The following figure shows a tristate element using a combinatorial process and always block BUFT X9543 The following table shows pin definitions for a tristate element using a combinatorial process and always block 10 Pins Description I Data Input T Output Enable active Low Data Output VHDL Code Following is VHDL code for a tristate element using a combinatorial process and always block library ieee use ieee std_logic_1164 all entity three_st is port T an std logic I in std logic O out std logic end three st architecture archi of three st is begin process I T begin if T2 0 then O lt I else O lt Z end if end process end archi 54 www xilinx com XST User Guide 1 800 255 7778 Tristates XILINX Verilog Code Following is Verilog code for a tristate element using a combinatorial process and always block module three st T I 0 input T I output 0 reg O always T or I begin If T O 1 else O 1 bZ end endmodule Description Using Concurrent Assignment In the following two examples note that comparing to 0 instead of 1 infers a BUFT primitive instead of a BUFE macro The BUFE macro has an inverter on the E pin VHDL Code Following is VHDL code for a tristate element using a concurrent assignment library iee
70. Chapter 3 FPGA Optimization Mapping Logic onto Block RAM 204 If there are unused block RAM resources and your design does not fit into your target device you can place some of your design logic into block RAM To do this you must decide what part of the HDL design is to be placed in block RAM and put this part of the RTL description in a separate hierarchical block Attach a BRAM_MAP constraint to this separate block either directly in HDL code or via the XCF file Please note that in the current release XST cannot automatically decide what logic could be placed in block RAM When placing logic into a separate block it must satisfy the following criteria e All outputs must be registered e The block may contain only one level of registers which are output registers e All output registers must have the same control signals e The output registers must have a Synchronous Reset signal e The block cannot contain multisources or tristate busses e The KEEP attribute is not allowed on intermediate signals XST attempts to map the logic onto block RAM during the Advanced Synthesis step If any of the listed requirements are not satisfied XST does not map the logic onto block RAM and generates a warning message with the reason for the warning If the logic cannot be placed in a single block RAM primitive XST spreads it over several block RAMs The following example places 8 bit adders with constant in a single block RAM primitive
71. Found 1 bit latch for signal lt q gt Summary inferred 1 Latch s Unit latch synthesized HDL Synthesis Report Macro Statistics Latches 1 bit latch Related Constraints A related constraint is IOB Latch with Positive Gate The following figure shows a latch with a positive gate D LD X3740 The following table shows pin definitions for a latch with a positive gate 10 Pins Description D Data Input G Positive Gate Q Data Output XST User Guide www xilinx com 49 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the equivalent VHDL code for a latch with a positive gate library ieee use ieee std_logic_1164 all entity latch is port G D in std_logic Q out std logic end latch architecture archi of latch is begin process G D begin if G 2 1 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a latch with a positive gate module latch G D Q input G D output 0 reg Q always G or D begin if G Q lt end endmodule Latch with Positive Gate and Asynchronous Clear The following figure shows a latch with a positive gate and an asynchronous clear 50 www xilinx com XST User Guide 1 800 255 7778 Latches XILINX The following table shows pin definitions for a latch with a positive gate and an asynchr
72. HIERARCHY in the Constraints Guide for details Logical Shifter Extraction The Logical Shifter Extraction SHIFT EXTRACT constraint enables or disables logical shifter macro inference See SHIFT EXTRACT in the Constraints Guide for details Map Logic on BRAM The Map Logic on BRAM BRAM MAP constraint is used to map an entire hierarchical block on the block RAM resources available in Virtex and later technologies See Mapping Logic onto Block RAM in Chapter 3 and also BRAM MAP in the Constraints Guide for details Max Fanout The Max Fanout MAX FANOUT constraint limits the fanout of nets or signals See MAX FANOUT in the Constraints Guide for details Move Last Stage The Move Last Stage MOVE LAST STAGE constraint controls the retiming of registers with paths going to primary outputs See MOVE LAST STAGE in the Constraints Guide for details Move First Stage The Move First Stage MOVE FIRST STAGE constraint controls the retiming of registers with paths coming from primary inputs See MOVE FIRST STAGE in the Constraints Guide for details Multiplier Style The Multiplier Style MULT STYLE constraint controls the way the macro generator implements the multiplier macros Allowed values are auto block lut pipe lut kcm pipe block and csd The default is auto meaning that XST looks for the best implementation for each considered macro The pipe lut option is for pipeline multipliers The implemen
73. ITE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II opt mode speed area model entity module yes speed area Spartan TI TIE 3 Virtex II II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II 270 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX 1 800 255 7778 Table 5 1 XST Specific Non timing Options XCF Cmd Constraint Constraint Constraint VHDL Verilog Cmd Technology Line Name Value Syntax Target Target Value Target parallel case na na case case no na Spartan II IIE 3 statement statement Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II priority extract yes no force model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal force Virtex II II Pro II Pro X E 4 ram_extract yes no model entity module yes yes no Spartan II IE 3 true false net in model signal signal Virtex II II Pro II Pro X E 4 ram_style auto block model entity module yes auto block Spartan II IIE 3 distributed net in model signal signal distributed Virtex II II Pro II Pro X E 4 register_balancing yes no model entity module yes yes no Spartan TI TIE 3 forward net in model signal signal forward Virtex II II Pro backward inst in model FF instance FF instance backward II Pro X E 4 true false name name primary
74. Less vtec treed creed E RR EI ES UR A vie EN ede A ROS Ga aere rA 206 VERILOG iecit eerte ROS eU AR a E EPI E OE 207 LOG ieceered a e pee bk erepe ker eher rk ed oi e epa pie NR REPE RENE 207 Flip Flop Reming unsure dd toda Momia 207 Incremental Synthesis Flow suse eee 208 INCREMENTAL SYNTHESIS cuina nr RERT IRR mein erm ed dte 208 Example i siusiu i anderer dE Rr dite Era ie ee dde da acea cede ec od 209 RESYN THESIZE ota eee edet itio Mba ata de ove tap leida 209 Speed Optimization Under Area Constraint usuuuuuusuuueuuueue 212 Log File AdalysiS iowekeea aed rd eb Et eR PEDE EE REPE Red a a e da 214 Design Optimization ep cioci is niea n 214 Resource Usage essre ciris tae Eie eT nE Inn 214 Device Utilization summary 2 ccc eens 215 Clock Information sium e eee er a sound Paso Y pase aa 215 Timing Report is iii se t i E EERE EE E ERE TEBE 215 Timing Summaly xa asc ennn Oi iia 217 Timing Detail scab cat ae fa bees eee E esee EEE EEE 217 Implementation Constraints snau usanne saanu r cc 218 Virtex Primitive SUDDOPL cene rk r EE IS n EETEREDRRE ES 218 VADE Code sic bere ere ie race e ae E ea ed ea Eels 219 Verilog Code REE RR 220 Log File OON 221 Related Constraints st E E G EE E OE EES 221 Cores PIOCEBSIDE i iis ccc ri dete A A r AAA AS 221 Specifying INITs and RLOCs in HDL Code 0 0005 227 PCT FLOW sita dicta id ido dues de
75. Note Security attributes on the module definition always have higher precedence than any other attribute or parameter 344 www xilinx com 1 800 255 7778 XST User Guide Verilog Limitations in XST XILINX Verilog Limitations in XST This section describes Verilog limitations in XST support for case sensitivity and blocking and nonblocking assignments Case Sensitivity XST supports case sensitivity as follows e Designs can use case equivalent names for I O ports nets regs and memories e Equivalent names are renamed using a postfix rnm lt Index gt e A rename construct is generated in the NGC file e Designs can use Verilog identifiers that differ only in case XST renames them using a postfix as with equivalent names Following is an example module upperlower4 inputl INPUT1 outputl output2 input inputl input INPUT1 For the above example INPUT1 is renamed to INPUT1_rnm0 The following restrictions apply for Verilog within XST e Designs using equivalent names named blocks tasks and functions are rejected Example always clk begin fir_main5 reg 4 0 fir_main5_wl reg 4 0 fir_main5_Wl This code generates the following error message ERROR Xst 863 design v line 6 Name conflict fir main5 fir main5 wl and fir main5 fir main5 W1 e Designs using case equivalent module names are also rejected Example module UPPERLOWER10 module upperlowerl0
76. Number of integer BUFRS created by XST Default value depends on the target device of Virtex 4 family cross clock analysis Enable cross clock domain yes no optimization equivalent register removal Equivalent Register yes no Removal glob opt Global Optimization Goal allclocknets inpad to outpad offset in before Offset out after max delay iob Pack I O Registers into true false auto IOBs iobuf Add I O Buffers yes no keep hierarchy Keep Hierarchy yes soft no max_fanout Maximum Fanout integer Default 500 for Virtex IT II Pro II Pro X 4 Spartan 3 Default 100 for Virtex Virtex E Spartan II and Spartan ITE optimize primitives Optimize Instantiated yes no Primitives read cores Read Cores yes no register balancing Register Balancing yes no forward backward XST User Guide www xilinx com 1 800 255 7778 387 XILINX Chapter 10 Command Line Mode Table 10 6 Target Options Virtex Virtex E Virtex II Virtex Il Pro Virtex Il Pro X Virtex 4 Spartan II Spartan IIE Spartan 3 Run Command Options Description Values move_first_stage Move First Flip Flop Stage yes no move last stage Move Last Flip Flop Stage yes no register duplication Register Duplication yes no sd Cores Search Directories Any valid path to directories separated
77. Positive Edge Clock en Synchronous Enable active High addr Read Address data Data Output VHDL Code Following is the recommended VHDL code for a ROM with registered output library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity rominfr is port clk in std logic en in std_logic addr in std logic vector 4 downto 0 data out std_logic_vector 3 downto 0 end rominfr architecture syn of rominfr is type rom_type is array 31 downto 0 of std_logic_vector 3 downto 0 constant ROM rom_type 0001 0010 0011 0100 0101 0110 0111 1000 1001 WTOLO 10ITLI 1100 1101 1110 IT11T1 0001 0010 TOIL 0t090 0T01 0110 0T11 1000 1001 1010 1011 lT100 TILOIT STILLT U1 317 begin process clk begin if clk event and clk 1 then if en 1 then data lt ROM conv integer addr end if end if end process end syn 178 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Following is alternate VHDL code for a ROM with registered output library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity rominfr is port clk in std logic en in std_logic addr in std logic vector 4 downto 0 data out std_logic_vector 3 downto 0 end rominfr architecture syn of rominfr is type rom_type is array 31 downto 0 of std_logic_vector 3 downto 0 constant ROM rom_type
78. Project Navigator To run synthesis from the command line you must use the XST executable file If you work on a workstation the name of the executable is xst On a PC the name of the executable is xst exe File Types XST generates the following types of files XST User Guide Design output file NGC ngc This file is generated in the current output directory see the ofn option If run in incremental synthesis mode XST generates multiple NGC files RTL netlist for RTL and Technology Viewers ngr Synthesis LOG file srp Temporary files Temporary files are generated in the XST temp directory By default the XST temp directory is tmp on workstations and the directory specified by either the TEMP or TMP environment variables under Windows The XST temp directory can be changed by using the set tmpdir lt directory gt directive www xilinx com 381 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode e VHDL Verilog compilation files VHDL Verilog compilation files are generated in the dump directory The default dump directory is the xst subdirectory of the current directory Note Xilinx strongly suggests that you clean the XST temp directory regularly This directory contains the files resulting from the compilation of al VHDL and Verilog files during all XST sessions Eventually the number of files stored in the dump directory may severely impact CPU performances This directory is not automatically cle
79. Read Write Address di Data Input do Data Output VHDL Code Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic rst t Xm std logic a in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if if rst 1 then do lt others gt 0 else do lt RAM conv integer a end if end if end process end syn XST User Guide www xilinx com 145 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Following is the Verilog code module raminfr clk we rst a di do input clk input we input rst input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if we ram a lt di if rst do lt 4 b0 else do lt ram a end endmodule Single Port RAM with Synchronous Read Read Through The following description implements a true synchronous read A true synchronous read is the synchronization mechanism available in Virtex block RAMs where the read address is registered on the RAM cl
80. Safe Implementation mode Safe Implementation means that XST generates additional logic that forces an FSM to a valid state recovery state if an FSM gets into an invalid state By default XST automatically selects reset as the recovery state If the FSM does not have an initialization signal XST selects power up as the recovery state The recovery state can be manually defined via the RECOVERY STATE constraint To activate Safe FSM implementation from Project Navigator select the Safe Implementation option from the HDL Options tab of the Synthesis Process Properties dialog box in Project Navigator To activate Safe FSM implementation from your HDL code apply the SAFE_IMPLEMENTATION constraint to the hierarchical block or signal that represents the state register in the FSM See SAFE IMPLEMENTATION and SAFE RECOVERY STATE in the Constraints Guide for details e Signal Encoding The Signal Encoding SIGNAL ENCODINGQ constraint can be used to apply a specific encoding to signals See SIGNAL ENCODINC in the Constraints Guide for details FPGA Constraints non timing This section describes FPGA HDL options These options apply only to FPGAs not CPLDs Note Please note that in many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances See Table 5 1 for valid constraint targets e Buffer Type Buffer Typ
81. Shifters e Arithmetic Operations e RAMs ROMs e State Machine e Safe FSM Implementation e Black Box Support Designs are usually made up of combinatorial logic and macros for example flip flops adders subtractors counters FSMs RAMs The macros greatly improve performance of the synthesized designs Therefore it is important to use some coding techniques to model the macros so that they are optimally processed by XST During its run XST first tries to recognize infer as many macros as possible Then all of these macros are passed to the Low Level Optimization step either preserved as separate blocks or merged with surrounded logic in order to get better optimization results This filtering depends on the type and size of a macro for example by default 2 to 1 multiplexers are not preserved by the optimization engine You have full control of the processing of inferred macros through synthesis constraints Note Please refer to Chapter 5 Design Constraints for more details on constraints and their utilization www xilinx com 29 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques There is detailed information about the macro processing in the XST LOG file It contains the following e The set of macros and associated signals inferred by XST from the VHDL Verilog source on a block by block basis The macro inference is done in two steps HDL Synthesis and Advanced HDL
82. Signed Up Counter with Asynchronous Reset and Modulo Maximum 66 VHDL Code veRe 9e eer YY eds Pole gt tale Uae ye vale VEE FRE Eds 66 Verilog Code coi A A eT and citta ew ao hes T pee oom 67 Related Constraints cesare RE eer Gee ERA URBE Wc EAE ep es 67 P eapdro fM 67 LOS E tiles Pope gs 68 Related Coristraints i i rae b ee Er Ee RRECOERES E RE 68 4 bit Unsigned Up Accumulator with Asynchronous Clear ooooooooo 68 VHDL Code ss sii a eet RS RESO ERE oe RES ERE HOES Bae aes RE 69 Verilog Codes is conte bbe bek deb ERES Sohne Heenan e oda obese iig 69 Considerations for Virtex 4 Devices ilie nn 70 8 www xilinx com XST User Guide 1 800 255 7778 XILINX li A A II 70 Los Ple a eee DELE 72 Related Constraints isis ei ek e rk broek bites rn 72 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out 72 VHDE Code ie uri t RU ERE eee vied eed vie tes 73 Verilog Codes a ccs d ies tee baa tesa ee Lcd EE paved 73 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out isc e bE px REO HH x ARE need Ea kien a i bad 74 VHDE Code 4 cene ter iet rhe e ove ege we pe 74 Verilog Code cse iS AER Cag eater ue ccs ceti 75 8 bit Shift Left Register with Positive Edge Clock Asynchronous Clear Serial In and Serial Qut iscisiie ec i a a a e E Re E RE PCR 75 VEHDE Code tna ee Sie ott eee Lie IRR dager ie br pets 75
83. Ss Red be de eret Oe led Ms 244 XST Constraint File XCP Tuus 244 XCF Syntax and Utilization seereis retried i ee a e e n ne nts 244 Native vs Non Native UCF Constraints Syntax s s s ssas eee 245 Eimas ii A 246 General Constraints ccc cece cece eee ence een eens eneens 246 HDL Constraints 000 0 sese e 253 FPGA Constraints non timing 0 0 0 254 CPLD Constraints non timing 00 260 Timing Constraints coi do ni eH dile ees 263 Global Timing Constraints Support 0 0 0 66 cece eee ees 264 Domain Definitions ete krse a 265 XCF Timing Constraint Support 6000 6 eect ee 265 Constraints Summary c seb HER AA AA Er EERE AR EES A 267 Implementation Constraints 0 500 054 edad ER RR ERRAT EE ra 277 Handling by XST iiis feces Sees Sea Nea ete oie Heres Lea dees 277 Examples prados drk pareki ra al aa PRESA DES E GS 278 Example T eco are EE 278 Example 2s tora t er tuer Pb toe breue US ree ev 278 Example ccs E A E ed Gi aa steil cette 278 Third Party Constraints vu ccoiirecin s eek rod hy Rr REN E ER eee 279 14 www xilinx com XST User Guide 1 800 255 7778 XILINX Constraints Precedence 0 cece cece cece eee re 282 Chapter 6 VHDL Language Support XST User Guide Introduction AAA 283 File Type Suppott e PT 284 Limitations sie A nce e a en cu de ea aed ee 284 Data Types dn VEDA e D Re EO ER ed 285 Overloaded Data Types i
84. Synthesis In the HDL Synthesis step XST recognizes as many simple macro blocks as possible such as adders subtractors registers etc In the Advanced HDL Synthesis step XST does additional macro processing by improving the macros for example pipelining of multipliers recognized at the HDL synthesis step or by creating the new more complex ones such as dynamic shift registers e The overall statistics of recognized macros e The number and type of macros preserved by low level optimization The following log sample displays the set of recognized macros on a block by block basis Synthesizing Unit lt timecore gt Related source file is timecore vhd Found finite state machine lt FSM_0 gt for signal lt state gt Found 7 bit subtractor for signal lt fsm_sigl gt Found 7 bit subtractor for signal lt fsm_sig2 gt Found 7 bit register for signal lt min gt Found 4 bit register for signal lt points_tmp gt Summary inferred 1 Finite State Machine s inferred 18 D type flip flop s inferred 10 Adder Subtracter s Unit lt timecore gt synthesized Synthesizing Unit lt divider gt Related source file is divider vhd Found 18 bit up counter for signal lt counter gt Found 1 1 bit 2 to 1 multiplexers Summary inferred 1 Counter s inferred 1 Multiplexer s Unit lt divider gt synthesized 30 www xilinx com XST User Guide 1 800 255 7778 Introduction XILINX The following log
85. This detection is done at the file level This means that if an HDL file contains two blocks both blocks are considered modified If these two blocks belong to the same logic group then there is no impact on the overall synthesis time If the HDL file contains two blocks that belong to different logic groups both logic groups are considered changed and so are resynthesized Xilinx recommends that you only keep different blocks in the a single HDL file if they belong to the same logic group Use the RESYNTHESIZE constraint to force resynthesis of the blocks that were not changed Note In the current release XST runs HDL synthesis on the entire design However during low level optimization XST re optimizes modified blocks only XST User Guide www xilinx com 209 1 800 255 7778 XILINX Chapter 3 FPGA Optimization In this example XST generates three NGC files as shown in the following log file segment Final Report Final Results Top Level Output File Name Output File Name Output File Name c users incr_synt new ngc c users incr_synt leva ngc c users incr_synt levb ngc If you made changes to block LEVA_1 XST automatically resynthesizes the entire logic group including LEVA LEVA_1 LEVA_2 and my_add my_sub as shown in the following log file segment Low Level Synthesis Optimizing Optimizing Optimizing Optimizing Optimizing Final Results Incremental Inc
86. Verilog Codi AA E 76 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Sertal QUES is oda iia 76 VHDL Code iii A dee edes 77 Verilog Cod ss ti dea 77 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out 78 spe e m 78 Verilog Code sa e eh nie e plu Vp og eie RESIS EEN deese 78 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out iussis ley bere bene seb da 79 VHDL Code ypg EP 79 Verlo Codere E eG tee ae EEE 80 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial Tn and Serial Out invita di aba ep E a dsd 80 VHDL COJE idet ii ti 80 Verilog Code iii e e PA a Ge dea as 81 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out sce sic ceeded ect ds 81 use cT mm 82 Veril g Code seo iere teret Eae eate Sie gd ee educi ques cease 82 Dynamic Shift Register cmd rdg Fat p terc eR deste CE p n ides i 82 16 bit Dynamic Shift Register with Positive Edge Clock Serial In and Serial Out 83 LOG File UE 84 Related Constraints ser iii bi ii td ias 84 VADE Code ies Sete esa e Ar fated tend aie E EE rot 84 Verilog Code mein nS 85 Multiplexers viaria Ped toda Vs is rs eds 85 Los Ple a Say ie ne Sa nee ee aay ers wee ee Es 88 Related Constraints sies ik issie cipie eiside eee PRESA ii 88 4 to 1 1 bit MUX using IF Statement 666 88 VEDE Codec o W
87. XILINX Name Vendor XST Equivalent Automatic Recognition Available For syn_state_machine Synplicity fsm_extract na VHDL Verilog syn_tco lt n gt Synplicity na na na syn_tpd lt n gt Synplicity na na na syn_tristate Synplicity na na na syn_tristatetomux Synplicity na na na syn_tsu lt n gt Synplicity na na na syn_useenables Synplicity na na na syn_useioff Synplicity iob na VHDL Verilog synthesis translate_off Synplicity synthesis yes VHDL synthesis translate_on Synopsys translate_off Verilog synthesis translate_on xc_alias Synplicity na na na xc_clockbuftype Synplicity buffer_type na VHDL Verilog xc_fast Synplicity fast na VHDL Verilog xc_fast_auto Synplicity fast na VHDL Verilog xc_global_buffers Synplicity bufg na VHDL Verilog xc_ioff Synplicity iob na VHDL Verilog xc_isgsr Synplicity na na na xc_loc Synplicity loc yes VHDL Verilog xc_map Synplicity lut_map yes VHDL Note Only the value lutis Verilog supported for automatic recognition xc ncf auto relax Synplicity na na na xc nodelay Synplicity nodelay na VHDL Verilog xc padtype Synplicity iostandard na VHDL Verilog xc props Synplicity na na na XST User Guide www xilinx com 281 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 4 Third Party Constraints Name Vendor XST Equivalent Au
88. XST User Guide 1 800 255 7778 Implementation Constraints XILINX Implementation Constraints This section explains how XST handles implementation constraints See the Constraints Guide for details on the implementation constraints supported by XST Handling by XST Implementation constraints control placement and routing They are not directly useful to XST and are simply propagated and made available to the implementation tools When the write timing constraints switch is set to yes the constraints are written in the output NGC file Note TIG is propagated regardless of the setting In addition the object that an implementation constraint is attached to is preserved A binary equivalent of the implementation constraints is written to the NGC file but since it is a binary file you cannot edit the implementation constraints there Alternatively you can code implementation constraints in the XCF file according to one of the following syntaxes To apply a constraint to an entire entity use one of the following two XCF syntaxes MODEL EntityName PropertyName MODEL EntityName PropertyName PropertyValue To apply a constraint to specific instances nets or pins within an entity use one of the two following syntaxes BEGIN MODEL EntityName NET INST PIN NetNamelInstNamelSigName PropertyName END BEGIN MODEL EntityName NET INST PIN NetName InstName SigName PropertyName Propertyvalue END When
89. XST User Guide 1 800 255 7778 Dynamic Shift Register XILINX 16 bit Dynamic Shift Register with Positive Edge Clock Serial In and Serial Out XST User Guide The following table shows pin definitions for a dynamic register The register can be either serial or parallel be left or right have a synchronous or asynchronous clear and have a depth up to 16 bits 10 Pins Description Clk Positive Edge Clock SI Serial In AClr Asynchronous Clear optional SClr Synchronous Clear optional SLoad Synchronous Parallel Load optional Data Parallel Data Input Port optional CIkEn Clock Enable optional LeftRight Direction selection optional SeriallnRight Serial Input Right for Bidirectional Shift Register optional PSO x 0 Serial or Parallel Output www xilinx com 1 800 255 7778 83 XILINX Chapter 2 HDL Coding Techniques LOG File The recognition of dynamic shift registers happens in the Advanced HDL Synthesis step The XST log file reports the size of recognized dynamic shift registers during the Macro Recognition step HDL Synthesis Synthesizing Unit dynamic srl Related source file is vlg v Found 1 bit 16 to 1 multiplexer for signal lt Q gt Found 16 bit register for signal data Summary inferred 16 D type flip flop s inferred 1 Multiplexer s Unit dynamic srl synthesized Advanced HDL Synthe
90. XST offers an automatic RAM recognition capability XST can infer distributed as well as block RAM It covers the following characteristics offered by these RAM types e Synchronous write e Write enable e RAM enable e Asynchronous or synchronous read e Reset of the data output latches e Data output reset e Single dual or multiple port read e Single port Dual port write e Parity bits Virtex 4 devices only Note XST does not support RAMs ROMs with negative addresses The type of inferred RAM depends on its description e RAM descriptions with an asynchronous read generate a distributed RAM macro e RAM descriptions with a synchronous read generate a block RAM macro In some cases a block RAM macro can actually be implemented with distributed RAM The decision on the actual RAM implementation is done by the macro generator Following is the list of VHDL Verilog templates that are described below e Virtex II RAM Read Write modes Read First Mode Write First Mode No Change Mode e Single Port RAM with Asynchronous Read e Single Port RAM with False Synchronous Read e Single Port RAM with Synchronous Read Read Through e Single Port RAM with Enable e Dual Port RAM with Asynchronous Read e Dual Port RAM with False Synchronous Read e Dual Port RAM with Synchronous Read Read Through e Dual Port RAM with One Enable Controlling Both Ports e Dual Port RAM with Enable Controlling Each Port e Dual Port RAM with Diff
91. Xs lt tenths gt Entity lt stopwatch gt analyzed Unit lt stopwatch gt generated Analyzing Entity lt statmach gt Architecture lt inside gt ntity lt statmach gt analyzed Unit lt statmach gt generated E Analyzing Entity lt decode gt Architecture lt behavioral gt ntity lt decode gt analyzed Unit lt decode gt generated E Analyzing Entity lt cnt60 gt Architecture lt inside gt ntity lt cnt60 gt analyzed Unit lt cnt60 gt generated E Analyzing Entity lt smallcntr gt Architecture lt inside gt ntity lt smallcntr gt analyzed Unit lt smallcntr gt generated E Analyzing Entity lt hex2led gt Architecture lt hex2led_arch gt ntity lt hex2led gt analyzed Unit lt hex2led gt generated E Advanced HDL Synthesis Advanced RAM inference Advanced multiplier inference Optimizing FSM FSM 0 on signal current state 1 6 with one hot encoding State Encoding clear 000001 zero 000010 start 000100 counting 001000 stop 010000 stopped 100000 Dynamic shift register inferenc 368 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File XILINX HDL Synthesis Report Macro Statistics ROMs 16x10 bit ROM 16x7 bit ROM Counters 4 bit up counter Registers 1 bit register OY O0 lo P2 2 HP W HDL Synthesis Synthesizing Unit lt smallcntr gt
92. a Case statement www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Example 7 3 MUX Description Using Case Statement module mux4 sel a b C d outmux input 1 0 sel input L70 a Dye d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d begin case sel 2 b00 outmux a 2 b01 outmux b 2 b10 outmux c default outmux d endcase end endmodule The preceding Case statement evaluates the values of the input sel in priority order To avoid priority processing it is recommended that you use a parallel case Verilog meta comment which ensures parallel evaluation of the sel inputs as in the following Example case sel synthesis parallel_case For and Repeat Loops When using always blocks repetitive or bit slice structures can also be described using the for statement or the repeat statement The for statement is supported for e Constant bounds e Stop test condition using operators lt lt gt or gt e Next step computation falling in one of the following specifications e var var step e var var step where var is the loop variable and step is a constant value The repeat statement is only supported for constant values The following example shows the use of a For Loop Example 7 4 For Loop Description module countzeros a Count input 7 0 a output 2 0 Count reg 2 0 Count reg 2 0 Count_Aux int
93. al x a not b and a2 y b not a or out c x y endmodule Each instance of the built in modules has a unique instantiation name such as a inv b inv out The wiring up of the gates describes an XOR gate in structural Verilog Example 7 11 gives the structural description of a half adder composed of four 2 input nand modules Example 7 11 Structural Description of a Half Adder module halfadd X Y C S input X Y output C S wire S1 S2 S3 nand NANDA S3 X Y nand NANDB S1 X S3 nand NANDC S2 S3 Y nand NANDD S S1 S2 assign C S3 endmodule X a A O 1 NANDB Y B A A NANDA Y S3 NANDD Y Os B B A NANDC Y y A B Oc X8952 Figure 7 1 Synthesized Top Level Netlist The structural features of Verilog HDL also allow you to design circuits by instantiating pre defined primitives such as gates registers and Xilinx specific primitives like CLKDLL and BUFGs These primitives are other than those included in the Verilog language These pre defined primitives are supplied with the XST Verilog libraries unisim_comp v 342 www xilinx com XST User Guide 1 800 255 7778 Parameters XILINX Example 7 12 Structural Instantiation of Register and BUFG module foo sysclk in reset out input sysclk in reset output out reg out wire sysclk_out FDC register sysclk reset in out position based referencing BUFG clk O sysclk out
94. bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out Language Templates Multiplexers 4 to 1 1 bit MUX using IF Statement 4 to 1 MUX Using Case Statement 4 to 1 MUX Using Tristate Buffers No 4 to 1 MUX 4 to 1 MUX Design with CASE Statement 4 to 1 MUX Design with Tristate Construct www xilinx com 1 800 255 7778 37 7 XILINX Chapter 2 HDL Coding Techniques Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Chapter Examples Language Templates Decoders VHDL One Hot 1 of 8 Decoder Synchronous with Reset Verilog One Hot VHDL One Cold Verilog One Cold Priority Encoders 3 Bit 1 of 9 Priority Encoder 8 to 3 encoder Synchronous with Reset Logical Shifters Example 1 None Example 2 Example 3 Dynamic Shifters 16 bit Dynamic Shift None Register with Positive Edge Clock Serial In and Serial Out 38 www xilinx com XST User Guide 1 800 255 7778 Introduction XST User Guide XILINX Table 2 1 VHD
95. block bl 8 b0 deassign STATE 0 7 block b2 TA_IN 0 3 4 7 lt DAT m rA IN 4 7 XST User Guide www xilinx com 335 1 800 255 7778 XILINX Chapter 7 Verilog Language Support Assignment Extension Past 32 Bits If the expression on the left hand side of an assignment is wider than the expression on the right hand side the left hand side is padded to the left according to the following rules e If the right hand expression is signed the left hand expression is padded with the sign bit 0 for positive 1 for negative z for high impedance or x for unknown e Ifthe right hand expression is unsigned the left hand expression is padded with 0 s e For unsized x or z constants only the following rule applies If the value of the right hand expression s left most bit is z high impedance or x unknown regardless of whether the right hand expression is signed or unsigned the left hand expression is padded with that value z or x respectively Note The above rules follow the Verilog 2001 standard and are not backward compatible with Verilog 1995 Tasks and Functions The declaration of a function or task is intended for handling blocks used multiple times in a design They must be declared and used in a module The heading part contains the parameters input parameters only for functions and input output inout parameters for tasks The return value of a function can be declared ei
96. blocks so that one component may be a new macro requiring fewer resources than the initial one and another smaller macro www xilinx com XST User Guide 1 800 255 7778 Log File Analysis XILINX may be accepted by XST For instance a flip flop macro with clock enable CE cannot be accepted when mapping onto the XC9500 In this case the HDL synthesizer submits two new macros e a flip flop macro without clock enable signal e a MUX macro implementing the clock enable function A generated macro is optimized separately and then merged with surrounded logic because the optimization process gives better results for larger components Log File Analysis XST messages related to CPLD synthesis are located after the following message Low Level Synthesis The log file produced by XST contains e Tracing of progressive unit optimizations Optimizing unit unit_name e Information warnings or fatal messages related to unit optimization When equation shaping is applied XC9500 devices only Collapsing Removing equivalent flip flops Register ffl equivalent to ff2 has been removed User constraints fulfilled by XST implementation constraint constraint_name value signal_name e Final results statistics Final Results Top Level Output file name file_name Output format ngc Optimization goal area speed Target Technology 9500 9500x1 9500xv xpla3 xbr cr2s Keep Hi
97. clk 1 and clk Event then case state is when sl gt if x1 1 then state lt s2 else state lt s3 end if when s2 gt state lt s4 when s3 gt state lt s4 when s4 gt state lt sl end case end if end process processl 186 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX process2 process state begin case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end case end process process2 end behl Verilog Code Following is the Verilog code for an FSM with two processes module fsm clk reset xl outp input clk reset xl output outp reg outp reg 1 0 state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always posedge clk or posedge reset begin if reset state lt sl else begin case state sl if x1 1 b1 state lt s2 else state lt s3 s2 state lt s4 s3 state lt s4 s4 state lt sl endcase end end always state begin Case state sl outp 1 b1 S2 outp 1 b1 s3 outp 1 b0 s4 outp 1 b0 endcase end endmodule XST User Guide www xilinx com 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques FSM with 3 Processes You can also separate the NEXT State function from the state register State Output 4 Outputs Register
98. com 309 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Assert Statement 310 XST supports the use of the Assert statement By using the Assert statement designers can detect undesirable conditions in their VHDL designs such as bad values for generics constants and generate conditions or bad values for parameters in called functions For any failed condition in an Assert statement XST according to the severity level generates a warning message with the reason for the warning or rejects the design and generates an error message and the reason for the rejection Note XST supports the Assert statement only with static condition The following example contains a block SINGLE_SRL that describes a shift register The size of the shift register depends on the SRL_WIDTH generic value The Assert statement ensures that the implementation of a single shift register does not exceed the size of a single SRL Since the size of the SRL is 16 bit and XST implements the last stage of the shift register using a flip flop in a slice then the maximum size of the shift register cannot exceed 17 bits The SINGLE_SRL block is instantiated twice in the entity named TOP the first time with SRL_WIDTH equal to 13 and the second time with SRL_WIDTH equal to 18 library ieee use leee std_logic_1164 all entity SINGLE_SRL is generic SRL_WIDTH integer 16 port clk in std_logic inp in std_logic outp out std
99. control on procedural assignment 349 timing report 364 366 tmpdir 381 390 tnm 266 tnm net 266 top 384 385 top level block name 384 top module name 385 translate off 250 translate on 250 tristate 53 combinatorial process and always block 54 concurrent assignment 55 tristate replaced by logic 240 260 U uc 244 250 384 unconnected drive 351 undef 350 uperand 318 use carry chain 259 use clock enable 240 260 388 use DSP48 239 260 use synchronous reset 240 260 388 use synchronous set 240 260 388 use synthesis constraint file 244 use synthesis constraints file 237 250 use carry chain 259 use clock enable 260 388 use dsp48 260 use sync reset 260 388 use sync set 260 388 uselib 351 uselowskewlines 258 XST User Guide www xilinx com 1 800 255 7778 405 XILINX user defined primitives 351 user defined compile list 242 V variable declaration 316 322 arrays 323 initial values 322 multi dimensional arrays 323 variable part selects 341 vector 348 Verilog assign statements in 334 assignments in 329 case statement in 330 case statements 247 combinatorial aways blocks in 329 comments in 339 constants in 338 continuous assignments in 329 deassign statements in 334 expressions in 325 for loops in 331 if else statement in 330 include directories 385 language support 321 348 legal statements in 325 limitations 345 macros in 338 meta comment syntax 243 meta co
100. create a mixed language project file at the command line use the ifmt command line switch set to mixed or with its value is omitted Please note that you can still use the VHDL and Verilog formats for existing designs To use the VHDL format set ifmt to vhdl and to use the Verilog format set ifmt to verilog The syntax for invoking a library or any external file in a mixed language project is as follows language library file_name ext The following is an example of how to invoke libraries in a mixed language project vhdl work my vhdll vhd verilog work my vlgl v vhdl my vhdl lib my vhdl2 vhd verilog my vlg lib my vlg2 v Each line specifies a single HDL design file e The first column specifies whether the HDL file is VHDL or Verilog e The second column specifies the logic library where the HDL is compiled By default the logic library is work e The third column specifies the name of the HDL file VHDL Verilog Boundary Rules The boundary between VHDL and Verilog is enforced at the design unit level A VHDL design can instantiate a Verilog module A Verilog design can instantiate a VHDL entity Instantiating a Verilog Module in a VHDL Design 356 To instantiate a Verilog module in your VHDL design do the following 1 Declarea VHDL component with the same name respecting case sensitivity as the Verilog module you want to instantiate If the Verilog module name is not all lower case use the Case property
101. creates one If Project Navigator detects an existing project name 1so file this file is preserved and used as it is Please remember that in Project Navigator the name of the project is the name of the top level block In creating a default LSO file Project Navigator places the DEFAULT_SEARCH_ORDER keyword in the first line of the file Command Line When using XST from the command line specify the Library Search Order file by using the lso command line switch If the lso switch is omitted XST automatically uses the default library search order without using an LSO file Search Order Rules XST User Guide XST follows the following search order rules when processing a mixed language project e When the LSO file contains only the DEFAULT_SEARCH_ORDER keyword XST searches the specified library files in the order in which they appear in the project file updates the LSO file by removing the DEFAULT_SEARCH_ORDER keyword adding the list of libraries to the LSO file in the order in which they appear in the project file See Example 1 e When the LSO file contains the DEFAULT_SEARCH_ORDER keyword and a list of the libraries XST searches the specified library files in the order in which they appear in the project file ignores the list of library files in the LSO file leaves the LSO file unchanged See Example 2 e When the LSO file contains a list of the libraries without the DEFAULT
102. downto 0 do out std logic vector 3 downto 0 end raminfr XST User Guide www xilinx com 139 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di else do lt RAM conv_integer addr end if end if end if end process end syn The following templates show an alternate configuration of a single port RAM in no change mode with a registered read address coded in VHDL library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std logic we in std_logic en in std_logic addr in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addr std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di else read_addr lt addr end if end if end if end process do lt RAM read_addr end syn 140 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs Verilog Code
103. enable port e synchronous and asynchronous reset and load ports Considerations for Virtex ATM Devices The Virtex 4 family allows multipliers to be implemented on DSP48 resources XST supports the registered version of these macros and can push up to 2 levels of input registers and 2 levels of output registers into DSP48 blocks If a multiplier implementation requires multiple DSP48 resources XST automatically decomposes it onto multiple DSP48 blocks Depending on the operand size and to get the best performance XST may implement most of a multiplier using DSP48 blocks and use slice logic for the rest of the macro For example it is not sufficient to use a single DSP48 to implement an 18x18 unsigned multiplier In this case XST implements most of the logic in one DSP48 and the rest in LUTs XST User Guide www xilinx com 113 1 800 255 7778 XILINX 114 Chapter 2 HDL Coding Techniques For Virtex 4 devices XST can infer pipelined multipliers not only for the LUT implementation but for the DSP48 implementation as well Please see Pipelined Multipliers for details Macro implementation on DSP48 blocks is controlled by the USE_DSP48 constraint command line option with a default value of auto In this mode XST implements multipliers taking into account the number of available DSP48 resources in the device Please note that XST can automatically recognize the MULT_STYLE constraint with values lut and block an
104. event and clk 1 then if en 1 then if we 1 then RAM conv_integer a lt di end if read_a lt a end if end if end process do lt RAM conv_integer read_a end syn Verilog Code Following is the Verilog code for a single port block RAM with enable module raminfr clk en we a di do input clk input en input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 4 0 read_a always posedge clk begin if en begin if we ram a lt di read_a lt a end end assign do ram read a endmodule Dual Port RAM with Asynchronous Read The following example shows where the two output ports are used It is directly mappable onto Distributed RAM only Distributed SPO DPO X8980 XST User Guide www xilinx com 149 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin descriptions for a dual port RAM with asynchronous read 10 pins Description clk Positive Edge Clock we Synchronous Write Enable active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port VHDL Code Following is the VHDL code for a dual port RAM with asynchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std logic we in std_logic a in std_l
105. for a 4 bit unsigned up counter with a synchronous load with a constant IO Pins Description C Positive Edge Clock SLOAD Synchronous Load active High Q 3 0 Data Output www xilinx com XST User Guide 1 800 255 7778 Counters XILINX VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with a synchronous load with a constant library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C SLOAD in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if SLOAD 1 then tmp 1010 else tmp lt tmp 1 end if end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with a synchronous load with a constant module counter C SLOAD Q input C SLOAD output 3 0 Q reg 3 0 tmp always 8 posedge C begin if SLOAD tmp lt 4 b1010 else tmp lt tmp 1 b1 end assign Q tmp endmodule XST User Guide www xilinx com 61 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous clear and a clock enable 1
106. for functions and input output and inout parameters for procedures These parameters can be unconstrained This means that they are not constrained to a given bound The content is similar to the combinatorial process content Resolution functions are not supported except the one defined in the IEEE std_logic_1164 package Example 6 23 shows a function declared within a package The ADD function declared here is a single bit adder This function is called 4 times with the proper parameters in the architecture to create a 4 bit adder The same example described using a procedure is shown in Example 6 24 Example 6 23 Function Declaration and Function Call package PKG is function ADD A B CIN BIT return BIT_VECTOR end PKG package body PKG is function ADD A B CIN BIT return BIT_VECTOR is variable S COUT BIT variable RESULT BIT_VECTOR 1 downto 0 begin S A xor B xor CIN COUT A and B or A and CIN or B and CIN RESULT COUT amp S return RESULT end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT_VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT z out BIT 5 end EXAMPLE architecture ARCHI of EXAMPLE is signal SO S1 S2 S3 BIT VECTOR 1 downto 0 begin SO lt ADD A 0 B 0 CIN S1 lt ADD A 1 B 1 SO 1 S2 lt ADD A 2 B 2 S1 1 amp
107. from all primary input ports to either all sequential elements or the sequential elements driven by the given clock signal name OFFSET_OUT_AFTER register to outpad is similar to the previous constraint but sets the constraint from the sequential elements to all primary output ports INPAD_TO_OUTPAD inpad to outpad sets a maximum combinational path constraint MAX_DELAY identifies all paths defined by the following timing constraints ALLCLOCKNETS OFFSET_IN_BEFORE OFFSET_OUT_AFTER INPAD_TO_OUTPAD Offset in Before gt AllClockNets Period gt Offset out After Inpad to Outpad OPAD X8991 XCF Timing Constraint Support IMPORTANT If you specify timing constraints in the XCF file Xilinx strongly suggests that you use character as a hierarchy separator instead of Please refer to Hierarchy Separator page 248 for details on its usage IMPORTANT If all or part of a specified timing constraint is not supported by XST then XST generates a warning about this and ignores the unsupported timing constraint or unsupported part of it in the Timing Optimization step If the Write Timing Constraints option is set to yes XST propagates the entire constraint to the final netlist even if it was ignored at the Timing Optimization step XST User Guide www xilinx com 265 1 800 255 7778 7 XILINX Chapter 5 Design Constraints The following timing constraints are supported
108. incremental_synthesis yes no model entity module no na Spartan IT IIE 3 true false Virtex JI TI Pro II Pro X E 4 iob true false net in model signal signal no true false Spartan II IIE 3 auto inst in model instance instance auto Virtex TI II Pro II Pro X E 4Pro X E 4 iostandard string See net in model signal signal no na Spartan I TIE 3 Constraints inst in model instance instance VirtexTM TI II Pro Guide for II Pro X XC9500 details CoolRunner XPLA3 II keep yes no net in model signal signal no na Spartan M TI TIE 3 true false VirtexTM TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II keep_hierarchy yes no model entity module yes yes no soft Spartan II IIE 3 true false VirtexTM TI II Pro soft II Pro X XC9500 CoolRunner XPLA3 II loc string net in model signal signal no na Spartan TI TIE 3 inst in model primary IO primary IO Virtex TI TI Pro nstancel instance II Pro X E 4 XC9500 CoolRunner XPLA3 II XST User Guide www xilinx com 269 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options XCF n Cmd Constraint Constraint Constraint VHDL Verilog Cmd Technology Line Name Value Syntax Target Target Value Target lut map yes no model entity module no na Spartan II IIE 3 true false a
109. information sd directory_path directory_path There is no default In Project Navigator specify this option with the Cores Search Directories option of the Synthesis Options tab in the Process Properties dialog box Allowed values are names of directories There is no default Decoder Extraction The Decoder Extraction DECODER_EXTRACT constraint enables or disables decoder macro inference See DECODER_EXTRACT in the Constraints Guide for details Enable Auto Floorplanning The Enable Floorplanning enable_auto_floorplanning command line option instructs XST to propagate incremental synthesis constraints placed in the design HDL to the NGC file in the form of rangeless Area Groups where they can be used by the Floorplanner Define this option globally with the enable_auto_floorplanning command line option of the run command Following is the basic syntax enable auto floorplanning no incremental_design The default is no In Project Navigator set this option globally with the Enable Auto Floorplanning option in the Synthesis Options tab of the Process Properties dialog box Refer to Incremental Synthesis Flow in Chapter 3 for more information FSM Style The FSM Style constraint F5M STYLE can be used to make large FSMs more compact and faster by implementing them in the block RAM resources provided in Virtex and later technologies You can direct XST to use block RAM resources rather than LUTS the defa
110. name work library where the top level block was compiled verilog2001 Verilog 2001 yes no vlgincdir Verilog Include Directories Any valid path to directories separated by spaces and enclosed in braces Example 1 How to Synthesize VHDL Designs Using Command Line Mode The goal of this example is to synthesize a hierarchical VHDL design for a Virtex FPGA using Command Line Mode The example uses a VHDL design called watchvhd The files for watchvhd can be found in the ISEexamples watchvhd directory of the ISE installation directory This design contains 7 entities e stopwatch e statmach e tenths a CORE Generator core e decode e smallcntr e cnt60 e hex2led XST User Guide www xilinx com 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode Example 1 1 Create a new directory named vhd1_nm 2 Copy the following files from the ISEexamples watchvhd directory of the ISE installation directory to the newly created vhd1_m directory stopwatch vhd statmach vhd decode vhd cnt60 vhd e smallcntr vhd tenths vhd hex2led vhd To synthesize the design which is now represented by seven VHDL files create a project Please note that starting from the 6 1i release XST supports Mixed VHDL Verilog projects and therefore Xilinx strongly suggests that you use the new project format whether it is a real mixed language project or not In this exampl
111. no na Spartan TI TIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II shift extract yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 shreg extract yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 signal encoding auto one hot model entity module no na Spartan I TIE 3 user net in model signal signal Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II slice_utilization_ratio integer model entity module yes integer range Spartan II IIE 3 range 0 100 0 100 Virtex N N Pro II Pro X E 4 slice utilization ratio max integer model entity module yes integer range Spartan II IIE 3 margin range 0 100 0 100 Virtex M TI II Pro II Pro X E 4 translate off na na local local no na Spartan TI TIE 3 no target no target Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II translate_on na na local local no na Spartan II IIE 3 no target no target Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II use carry chain yes no model entity module no na Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 use clock enable auto yes no model entity module yes auto yes no Spartan II IIE 3 true false
112. not moved forward if the flip flop or the output signal has the KEEP property e Flip flops are not moved backward if the input signal has the KEEP property e Instantiated flip flops are not moved e Flip flops with both a set and a reset are not moved Flip flop retiming can be controlled by applying the REGISTER_BALANCING MOVE_FIRST_STAGE and MOVE_LAST_STAGE constraints Incremental Synthesis Flow The main goal of Incremental Synthesis flow is to reduce the overall time that the designer spends in completing a project This can be achieved by allowing you to re synthesize only the modified portions of the design instead of the entire design We may consider two main categories of incremental synthesis e Block Level The synthesis tool re synthesizes the entire block if at least one modification was made inside this block e Gate or LUT Level The synthesis tool tries to identify the exact changes made in the design and generates the final netlist with minimal changes XST supports block level incremental synthesis with some limitations Incremental Synthesis is implemented using two constraints INCREMENTAL_SYNTHESIS and RESYNTHESIZE INCREMENTAL_SYNTHESIS 208 Use the INCREMENTAL_SYNTHESIS constraint to control the decomposition of the design on several logic groups e If this constraint is applied to a specific block this block with all its descendents is considered as one logic group until the next INCREMENTAL_SYNTH
113. optimizes the period of the entire design OFFSET IN BEFORE optimizes the maximum delay from input pad to clock either for a specific clock or for an entire design OFFSET OUT AFTER optimizes the maximum delay from clock to output pad either for a specific clock or for an entire design INPAD TO OUTPAD optimizes the maximum delay from input pad to output pad throughout an entire design MAX_DELAY incorporates all previously mentioned constraints These constraints affect the entire design and only apply if no timing constraints are specified via the constraint file Define this option globally with the g1ob opt command line option of the run command Following is the basic syntax glob opt allclocknets offset in before offset out after inpad to outpad max delay www xilinx com XST User Guide 1 800 255 7778 Timing Constraints XILINX You can specify glob_opt globally with the Global Optimization Goal option in the Synthesis Options tab of the Process Properties dialog box within the Project Navigator Domain Definitions The possible domains are illustrated in the following schematic ALLCLOCKNETS register to register identifies by default all paths from register to register on the same clock for all clocks in a design To take into account inter clock domain delays the command line switch cross_clock_analysis must be set to yes OFFSET_IN_BEFORE inpad to register identifies all paths
114. or the Verilog style for comments C style comments can be multiple line Verilog style comments end at the end of the line XST supports the following e Both C style and Verilog style meta comments e translate on translate off directives synthesis translate on synthesis translate off e parallel case full case directives synthesis parallel case full case synthesis parallel case synthesis full case e Constraints on individual objects The general syntax is synthesis attribute AttributeName of ObjectName is AttributeValue Examples synthesis attribute RLOC of ul23 is R11C1 S0 synthesis attribute HUSET ul MY_SET synthesis attribute fsm_extract of State2 is yes synthesis attribute fsm_encoding of State2 is gray For a full list of constraints refer to Chapter 5 Design Constraints XST User Guide www xilinx com 347 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Verilog Language Support Tables The following tables indicate which Verilog constructs are supported in XST Previous sections in this chapter describe these constructs and their use within XST Note XST does not allow underscores as the first character of signal names for example DATA 1 Table 7 3 Constants 348 Integer Constants Supported Real Constants Supported Strings Constants U
115. parallel out library ieee use ieee std logic 1164 a11 entity shift is port C SI n std logic PO out std logic vector 7 downto 0 end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process PO tmp end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock a serial in and a parallel out module shift C SI PO input C SI output 7 0 PO reg 7 0 tmp always posedge C begin tmp lt tmp 6 0 SI end assign PO tmp endmodule 78 www xilinx com XST User Guide 1 800 255 7778 Shift Registers XILINX 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a serial in and a serial out 10 Pins Description C Positive Edge Clock SI Serial In ALOAD Asynchronous Parallel Load active High D 7 0 Data Input SO Serial Output VHDL Code Following is VHDL code for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a serial in and a serial out library ieee use ieee std logic 1164 a1 entity
116. raminfr architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_addra std_logic_vector 4 downto 0 signal read_addrb std_logic_vector 4 downto 0 XST User Guide www xilinx com 157 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addra lt di end if read_addra lt addra read_addrb lt addrb end if end if end process doa lt RAM conv_integer read_addra dob lt RAM conv_integer read_addrb end syn Verilog Code Following is the Verilog code for a dual port RAM with one global enable controlling both ports module raminfr clk en we addra addrb di doa dob input clk input en input we input 4 0 addra input 4 0 addrb input 3 0 di output 3 0 doa output 3 0 dob reg 3 0 ram 31 0 reg 4 0 read_addra reg 4 0 read_addrb always posedge clk begin if ena begin if wea ram addra lt di read_aaddra lt addra read_aaddrb lt addrb end end assign doa ram read_addra assign dob ram read_addrb endmodule 158 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Dual Port RAM with Enable on Each Port The following descriptions are directly mappable onto block RAM as shown in the following f
117. sample displays the additional macro processing done during the Advanced HDL Synthesis step Advanced HDL Synthesis m Implementing FSM FSM 0 on signal current state on BRAM INFO Xst Data output of ROM Mrom tmp one hot in block decode is tied to register one hot in block decode INFO Xst The register is removed and the ROM is implemented as read only block RAM The following log sample displays the overall statistics of recognized macros HDL Synthesis Report Macro Statistics FSMs ROMs 16x7 bit ROM Registers 7 bit register 4 bit register Counters 18 bit up counter Multiplexers 2 to 1 multiplexer Adders Subtractors 7 bit adder 7 bit subtractor O4 p p pnpnopsnmp tU xu amp sp XST User Guide www xilinx com 31 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques The following log sample displays the number and type of macros preserved by low level optimization Final Results Macro Statistics FSMs ROMs 16x7 bit ROM Registers 7 bit register 1 bit register 18 bit register Adders Subtractors 7 bit adder 7 bit subtractor 18 bit adder I2 O a4 p p AN YA BE 32 www xilinx com 1 800 255 7778 XST User Guide Introduction XST User Guide XILINX This chapter discusses the following Macro Blocks Registers Tristates Counters Accumu
118. script log file 3 Ifyou want to save XST messages in a different log file for example wat chver 1log execute the following command xst ifn design xst ofn watchver log You can improve the readability of the design xst file especially if you use many options to run synthesis You can place each option with its value on a separate line respecting the following rules e The first line must contain only the run command without any options e There must be no blank lines in the middle of the command e Each line except the first one must start with a dash www xilinx com 395 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode For the previous command example the stopwatch xst file should look like the following run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode The goal of this example is to synthesize a hierarchical mixed VHDL Verilog design for a Virtex FPGA using Command Line Mode 1 Create a new directory named vhdl_verilog 2 Copy the following files from the ISEexamples watchvhd directory of the ISE installation directory to the newly created vhdl verilog directory stopwatch vhd statmach vhd decode vhd cnt60 vhd smallcntr vhd tenths vhd 3 Copy the following file from the ISEexamples watchver directory of the ISE installatio
119. serial only the contents of the last flip flop are accessed by the rest of the circuit parallel the contents of one or several flip flops other than the last one are accessed e shift modes left right etc There are different ways to describe shift registers For example in VHDL you can use e concatenation operator shreg lt shreg 6 downto 0 amp SI e for loop construct for iin 0 to 6 loop shreg i 1 lt shreg i end loop shreg 0 lt SI 70 www xilinx com XST User Guide 1 800 255 7778 Shift Registers XST User Guide XILINX e predefined shift operators for example SLL or SRL Consult the VHDL Verilog language reference manuals for more information FPGAs Virtex E II II Pro II Pro X 4 and Spartan II ITE 3 have specific hardware resources to implement shift registers SRL16 for Virtex E II II Pro II Pro X and Spartan II ITE 3 and SRLC16 for Virtex II II Pro II Pro X 4 and Spartan 3 Both are available with or without a clock enable The following figure shows the pin layout of SRL16E SRL16E lo X8423 The following figure shows the pin layout of SRLC16 CLK NY AO SRLC16 Q15 Al A2 A3 X9497 Note Synchronous and asynchronous control signals are not available in the SLRC16x primitives SRL16 and SRLC16 support only LEFT shift operation for a limited number of IO signals e clock e clock enable e serial data in e serial dat
120. shift is port C SI ALOAD in std logic D in std logic vector 7 downto 0 SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process SO lt tmp 7 end archi XST User Guide www xilinx com 79 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock an asynchronous parallel load a serial in and a serial out module shift C ALOAD SI D SO input C SI ALOAD input 7 0 D output SO reg 7 0 tmp always posedge C or posedge ALOAD begin if ALOAD tmp lt D else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a synchronous parallel load a serial in and a serial out 10 Pins Description C Positive Edge Clock SI Serial In SLOAD Synchronous Parallel Load active High D 7 0 Data Input SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a
121. statmach v verilog work stopwatch v verilog work cnt60 v verilog work smallcntr v verilog work hex2led v 3 To synthesize the design execute the following command from the XST shell or via a script file run ifn watchver v ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 If you want to synthesize just HEX2LED and check its performance independently of the other blocks you can specify the top level module to synthesize in the command line using the top option please refer to Table 10 3 page 385 for more information run ifn watchver v ifmt Verilog ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 top HEX2LED Script Mode XST User Guide It can be very tedious work entering XST commands directly into the XST shell especially when you have to specify several options and execute the same command several times You can run XST in script mode as follows 1 Openanew file called design xst in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to start synthesis xst ifn design xst During this run XST creates the following files watchvhd ngc an NGC file ready for the implementation tools design srp the xst
122. the XC MAP constraint supported by Synplicity to this block indicates to XST that this block must be mapped on a single LUT XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization In the following VHDL example the top block contains the instantiation of two AND gates described in and one and and two blocks XST generates two LUT2s and does not merge them Please refer to the LUT MAP constraint description in the Constraints Guide for details www xilinx com XST User Guide 1 800 255 7778 Specifying INITs and RLOCs in HDL Code XILINX library ieee use ieee std_logic_1164 all entity and_one is port A B in std logic REZ out std logic attribute LUT MAP string attribute LUT MAP of and one entity is yes end and one architecture beh of and one is begin REZ lt A and B end beh library ieee use ieee std logic 1164 all entity and two is port A B in std logic REZ out std logic attribute LUT MAP string attribute LUT MAP of and two entity is yes end and two architecture beh of and two is begin REZ lt A or B end beh library ieee use leee std_logic_1164 all entity top is port A B C in std_logic REZ out std logic end top architecture beh of top is component and one port A B z in std logic REZ out std logic end component component and two port A
123. the equivalent VHDL code for a 4 bit register with a positive edge clock asynchronous set and clock enable library ieee use ieee std_logic_1164 all entity flop is port C CE PRE in std_logic D in std_logic_vector 3 downto 0 Q out std_logic_vector 3 downto 0 end flop architecture archi of flop is begin process C PRE begin if PRE 1 then Q lt 1111 elsif C event and C 1 then if CE 1 then Q lt D end if end if end process end archi Verilog Code Following is the equivalent Verilog code for a 4 bit register with a positive edge clock asynchronous set and clock enable module flop C D CE PRE OQ input C CE PRE input 3 0 D output 3 0 O reg 3 0 Q always posedge C or posedge PRE begin if PRE Q lt 4 b1111 else if CE Q lt D end endmodule Latches XST can recognize latches with the asynchronous set clear control signals Latches can be described using e Process VHDL and always block Verilog e Concurrent state assignment Note XST does not support Wait statements VHDL for latch descriptions 48 www xilinx com XST User Guide 1 800 255 7778 Latches XILINX Log File The XST log file reports the type and size of recognized latches during the Macro Recognition step Synthesizing Unit lt latch gt Related source file is latch l vhd WARNING Xst 737
124. the first Verilog module matching the name and binds it Note Please remember that since libraries are unified a Verilog cell by the same name as that of a VHDL design unit cannot co exist in the same logical library A newly compiled cell unit overrides a previously compiled one Instantiating a VHDL Design Unit in a Verilog Design XST User Guide To instantiate a VHDL entity declare a module name with the same as name as the VHDL entity optionally followed by an architecture name that you want to instantiate and perform a normal Verilog instantiation The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity No other VHDL constructs are visible to Verilog code When you do this XST uses the entity architecture pair as the Verilog VHDL boundary XST performs the binding during elaboration In the binding process XST searches for a Verilog module name it ignores any architecture name specified in the module instantiation using the name of the instantiated module in the user specified list of unified logical libraries in the user specified order See Library Search Order File for search order details If found XST binds the name If XST cannot find a Verilog module it treats the name of the instantiated module as a VHDL entity and searches for it using a case sensitive search fora VHDL entity XST searches for the VHDL entity in the user specified list of unified logical libraries in the user speci
125. then in addition you can use the ENUM_ENCODING constraint to assign a specific binary value to each state Please refer to Chapter 5 Design Constraints for more details Log File The XST log file reports the full information of recognized FSM during the Macro Recognition step Moreover if you allow XST to choose the best encoding algorithm for your FSMs it reports the one it chose for each FSM As soon as encoding is selected XST reports the original and final FSM encoding Please note that if the target family is an FPGA then XST reports this encoding at the HDL 192 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX Synthesis step If the target family is a CPLD then XST reports this encoding at the Low Level Optimization step Synthesizing Unit lt fsm gt Related source file is state machines l vhd Found finite state machine FSM 0 for signal state States 4 Transitions 5 Inputs 1 Outputs 1 Clock clk rising_edge Reset reset positive Reset type asynchronous Reset State sl Power Up State sl Encoding automatic Implementation LUT Summary inferred 1 Finite State Machine s Unit lt fsm gt synthesized Advanced HDL Synthesis Analyzing FSM FSM 0 for best encoding Optimizing FSM FSM 0 on signal lt state 1 4 gt with Speedl encoding State Encoding sl 1010 s2 0011 s3 0001 s4 0100 HDL Synth
126. to define the location of any element within the set relative to other elements in the set regardless of eventual placement in the overall design See RLOC in the Constraints Guide for details www xilinx com 249 1 800 255 7778 XILINX 250 Chapter 5 Design Constraints Synthesis Constraint File The Synthesis Constraint File uc command line option specifies a synthesis constraint file for XST to use The XCF must have an extension of xcf If the extension is not xcf XST will error out and stop processing Please refer to XST Constraint File XCF for details on using the constraint file Specify a file name with the uc command line option of the run command Following is the basic syntax uc filename In Project Navigator specify a synthesis file with the Use Synthesis Constraints File option in the Synthesis Options tab of the Process Properties dialog box Translate Off Translate On Verilog VHDL The Translate Off TRANSLATE_OFF and Translate On TRANSLATE_ON directives can be used to instruct XST to ignore portions of your VHDL or Verilog code that are not relevant for synthesis for example simulation code The TRANSLATE_OFF directive marks the beginning of the section to be ignored and the TRANSLATE_ON directive instructs XST to resume synthesis from that point See TRANSLATE OFF and TRANSLATE ON in the Constraints Guide for details Use Synthesis Constraints File The Use Synthesis Constraint
127. to implement pipelined multipliers in VHDL The following VHDL template shows the multiplication operation placed outside the process block and the pipeline stages represented as single registers library ieee use ieee std logic 1164 all use ieee numeric std all entity mult is generic A port siz integer 18 B port size integer 18 port clk lt in std logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 end mult XST User Guide www xilinx com 117 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 1 pipe 2 pipe 3 unsigned A port size B port size 1 downto 0 begin mult res a in b in process clk begin if clk event and clk 1 then a in lt A b in lt B pipe 1 lt mult res pipe 2 pipe 1 pipe 3 pipe 2 MULT lt pipe 3 end if end process end beh The following VHDL template shows the multiplication operation placed inside the process block and the pipeline stages represented as single registers library ieee use ieee std logic 1164 a1 use ieee numeric std all entity mult is generic A port size integer 18 B port size integer 18 port clk in s
128. unsigned up accumulator with an asynchronous clear IO Pins Description C Positive Edge Clock CLR Asynchronous Clear active High D 3 0 Data Input Q 3 0 Data Output 68 www xilinx com XST User Guide 1 800 255 7778 Accumulators XILINX VHDL Code Following is the VHDL code for a 4 bit unsigned up accumulator with an asynchronous clear library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity accum is port C CLR in std_logic D in std_logic_vector 3 downto 0 Q out std logic vector 3 downto 0 end accum architecture archi of accum is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp D end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up accumulator with an asynchronous clear module accum C CLR D Q input C CLR input 3 0 D output 3 0 Q reg 3 0 tmp always posedge C or posedge CLR begin if CLR tmp 4 b0000 else tmp tmp D end assign Q tmp endmodule XST User Guide www xilinx com 69 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Considerations for Virtex 4 Devices The Virtex 4 family enables accumulators to be implemented on DSP48 resources XST can push up to 2 levels of input registers into DSP48 blocks
129. using the TNM identifier you can also define groups in terms of other groups You can create a group that is a combination of existing groups by defining a TIMEGRP constraint You can place TIMEGRP constraints in a constraints file XCF or NCF You can use TIMEGRP attributes to create groups using the following methods Combining multiple groups into one Defining flip flop subgroups by clock sense See TIMEGRP in the Constraints Guide for details XCF Syntax TIMEGRP newgroup existing grpl existing grp2 existing grp3 TIG The TIG constraint causes all paths going through a specific net to be ignored for timing analyses and optimization purposes This constraint can be applied to the name of the signal affected See TIG in the Constraints Guide for details XCF Syntax NET net name TIG Constraints Summary XST User Guide Table 5 1 summarizes all available XST specific non timing related options This table shows the allowed values for each constraint the type of objects they can be applied to and any usage restrictions Default values are indicated in bold Note Please note that in many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances www xilinx com 267 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options
130. www xilinx com XST User Guide 1 800 255 7778 Mapping Logic onto Block RAM XILINX VHDL Code library ieee use leee std_logic_1164 all use ieee numeric_std all entity logic bram 1 is port clk rst in std logic A B in unsigned 3 downto 0 RES out unsigned 3 downto 0 attribute bram map string attribute bram map of logic bram 1 end logic bram 1 entity is architecture beh of logic bram 1 is begin process clk begin if clk event and clk 1 if rst 1 then RES 0000 else RES lt end if end if end process end beh then A B 0001 VERILOG module vlogic bram 1 input clk input 3 0 A output 3 0 R reg 3 0 R clk rst A B RES rst B ES ES synthesis attribute bram map of vlogic bram 1 is always posedge clk begin if rst RES 4 b0000 else RES A B 8 b0001 end endmodule ves yes XST User Guide www xilinx com 1 800 255 7778 205 XILINX Chapter 3 FPGA Optimization LOG VHDL HDL Synthesis Synthesizing Unit logic bram 1 Related source file is bram map l vhd Found 4 bit register for signal RES Found 4 bit adder for signal n0001 created at line 21 Summary inferred 4 D type flip flop s inferred 1 Adder Subtracter s Unit lt logic_bram_1 gt synthesized Advanced HDL Synthesis K Entity lt
131. z Global Reset Note that local reset is independent of global reset Registers controlled by a local reset may be set to a different value from registers whose value is only reset at global reset power up In the following example the register arb onebit is set to 1 at global reset but a pulse on the local reset rst can change its value to 0 Example entity top is Port Clk rst in std logic a in in std logic dout out std logic end top XST User Guide www xilinx com 289 1 800 255 7778 XILINX architecture Behavioral of top is signal arb onebit std logic 1 begin process clk rst begin if rst 1 then arb onebit lt 0 elsif clk event and clk 1 then arb onebit a in Chapter 6 VHDL Language Support end if end process dout arb onebit end Behavioral This sets the initial value on the register s output to 1 at initial power up but since this is dependent upon a local reset the value changes to 0 whenever the local set reset is activated Default Initial Values on Memory Elements Because every memory element in a Xilinx FPGA must come up in a known state in certain cases XST does not use IEEE standards for initial values In the previous example if signal arb onebit were not initialized to 1 XST would assign it a default of 0 as its initial state In this case XST does not follow the IEEE standard where U is the default for std l
132. 0 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High CE Clock Enable Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with an asynchronous clear and a clock enable library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C CLR CE in std_logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then if CE 2 1 then tmp lt tmp 1 end if end if end process Q lt tmp end archi 62 www xilinx com XST User Guide 1 800 255 7778 Counters XILINX Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with an asynchronous clear and a clock enable module counter C CLR CE Q input C CLR CE output 3 0 Q reg 3 0 tmp always posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else if CE tmp lt tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Down counter with Asynchronous Clear The following table shows pin definitions for a 4 bit unsigned up down counter with an asynchronous clear 10 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High UP DOW up down count mode selector N Q 3 0 Data
133. 0 bg256 6 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to start synthesis xst ifn stopwatch xst During this run XST creates the following files watchvhd ngc an NGC file ready for the implementation tools xst srp the xstlog file 3 Ifyou want to save XST messages in a different log file for example wat chvhd log execute the following command xst ifn stopwatch xst ofn watchvhd log You can improve the readability of the xst t xt file especially if you use many options to run synthesis by placing each option with its value on a separate line respecting the following rules e The first line must contain only the run command without any options e There must be no blank lines in the middle of the command e Each line except the first one must start with a dash www xilinx com 393 1 800 255 7778 XILINX Chapter 10 Command Line Mode For the previous command example xst scr should look like the following run ifn watchvhd vhd ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Example 2 How to Synthesize Verilog Designs Using Command Line Mode 394 The goal of this example is to synthesize a hierarchical Verilog design for a Virtex FPGA using Command Line Mode Example 2 uses a Verilog design called watchver These files can be found in the IS e Fexamples watchver direct
134. 1 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis TIMING REPOR T NOTE THESE IMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE and ROUTE Clock Information Clock Signal Clock buffer FF name Load CLK BUF GP 14 Timing Summary Speed Grade 6 Minimum period 3 321ns Maximum Frequency 301 159MHz Minimum input arrival time before clock 2 779ns Maximum output required time after clock 5 835ns Maximum combinational path delay 6 306ns Timing Detail All values displayed in nanoseconds ns Timing constraint Default period analysis for Clock CLK Clock period 3 321ns frequency 301 159MHz Total number of paths destination ports 59 21 Delay 3 321ns Levels of Logic 4 Source MACHINE current state FFd3 FF Destination sixty msbcount qoutsig 2 FF Source Clock CLK rising Destination Clock CLK rising Data Path MACHINE current state FFd3 to sixty msbcount qoutsig 2 Gate Net Cell in out fanout Delay Delay Logical Name Net Name FDC C gt 0 3 0 449 0 701 current_state_FFd3 CLKEN end scope MACHINE LUT2 I1 gt 0 5 0 347 0 735 cnt60enablel cnt60enable begin scope sixty LUT2 11 gt 0 4 0 347 0 553 sbce2 m
135. 10000111100001111 1001010001000001100000010000100 0000000001111100000000001000001 1111101010000011100010000100100 0 1 0 0 0 1 Example In the following example the loop that generates the initial value is controlled by testing that we are in the RAM address range library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all use std textio all entity raminitfilel is port clk in std_logic we in std_logic addr in std_logic_vector 2 downto 0 din in std logic vector 31 downto 0 dout out std logic vector 31 downto 0 end raminitfilel 176 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX architecture archi of raminitfilel is type RamType is array 0 to 7 of bit_vector 31 downto 0 type RamType is array 0 to 63 of bit_vector 15 downto 0 function InitRamFromFile RamFileName in string return RamType is FILE RamFile text is in RamFileName variable RamFileLine line variable RAM RamType begin for I in RamType range loop readline RamFile RamFileLine read RamFileLine RAM I end loop return RAM end function signal RAM RamType InitRamFromFile raminitfilel data begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer addr lt to bitvector din end if dout lt to stdlogicvector RAM conv integer addr end if end proce
136. 1164 package and reduce or reduce www xilinx com 313 1 800 255 7778 XILINX VHDL Language Support 314 Chapter 6 VHDL Language Support Table 6 3 Design Entities and Configurations The following tables indicate which VHDL constructs are supported in XST For more information about these constructs refer to the sections following the tables Generics Supported integer type only Entity Header Ports Supported no unconstrained ports Entity Declarative Part Supported Entity Statement Part Unsupported Architecture Declarative Part Supported Architecture Bodies Architecture Statement Part Supported Block Configuration Supported Configuration Declarations Component Configuration Supported Functions Supported Subprograms Procedures Supported www xilinx com 1 800 255 7778 XST User Guide VHDL Language Support XST User Guide Table 6 3 Design Entities and Configurations XILINX STANDARD Type TIME is not supported TEXTIO Supported STD_LOGIC_1164 Supported STD_LOGIC_ARITH Supported STD_LOGIC_SIGNED Supported STD_LOGIC_UNSIGNED Supported STD_LOGIC_MISC Supported Packages NUMERIC_BIT Supported NUMERIC_EXTRA Supported NUMERIC_SIGNED Supported NUMERIC_UNSIGNED Supported NUMERIC_STD Supported MATH_REAL Supported ASYL ARITH Supported ASYL SL_ARITH Supported
137. 247 385 case inequality 326 case statement 85 87 349 casex 330 casez 330 cell_list 279 celldefine 350 clock buffer type 255 clock enable 241 260 386 clock information 364 clock signal 264 clock_buffer 254 255 268 clock_list 279 clock_signal 264 268 combinatorial process 299 command line 381 comparator 112 unsigned 8 bit greater or equal com parator 112 compilation files 382 component configuration 295 component declaration 316 component instantiation 293 composite 316 concatenation 325 concurrent signal assignments 297 concurrent statement 319 conditional 327 configuration 317 configuration declaration 314 constant declaration 316 constraint file 234 constraints precedence 282 continuous procedural assignment 349 convert tristates to logic 260 CoolRunner 19 CoolRunner XPLA3 19 CoolRunner II 19 cores search directories 237 255 388 counter 56 4 bit signed up counter with asyn chronous reset 64 4 bit signed up counter with asyn chronous reset and modulo maxi mum 66 4 bit unsigned down counter with synchronous set 58 4 bit unsigned up counter with asyn chronous clear 57 4 bit unsigned up counter with asyn chronous clear and clock enable 62 4 bit unsigned up counter with asyn chronous load from primary input 59 4 bit unsigned up counter with syn chronous load with a constant 60 4 bit unsigned up down counter with asynchronous clear 63 CPLD constraints 260 fit
138. 3 0 tmp always posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else tmp lt tmp 1 b1 end assign Q tmp endmodule XST User Guide www xilinx com 57 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Unsigned Down Counter with Synchronous Set The following table shows pin definitions for a 4 bit unsigned down counter with a synchronous set 10 Pins Description C Positive Edge Clock S Synchronous Set active High Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned down counter with a synchronous set library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C S in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if S 1 then tmp 1111 else tmp tmp 1 end if end if end process Q lt tmp end archi 58 www xilinx com XST User Guide 1 800 255 7778 Counters XILINX Verilog Code Following is the Verilog code for a 4 bit unsigned down counter with synchronous set module counter C S 0 input C S output 3 0 O reg 3 0 tmp always posedge C begin if S tmp lt 4 b1111 else tmp lt tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Counter with Asynchronous Load fr
139. 48 blocks XST does not perform any automatic DSP48 resource control and as consequence the number of generated DSP48 blocks in the NGC netlist may exceed the number of available DSP48 blocks in the target device www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX XST User Guide To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible If you want to shape a macro in a specific way you must use the KEEP constraint For example if you want to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers In the Log file XST reports the details of inferred multipliers accumulators and registers at the HDL Synthesis step The composition of multiply accumulate macros happens at Advanced HDL Synthesis step Multiplier Up Accumulate with Register After Multiplication VHDL Code Use the following templates to implement Multiplier Up Accumulate with Register After Multiplication in VHDL library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD_LOGIC_UNSIGNED ALL entity m macl is generic p width integer 8 port Clk reset in std logic A B in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end m_macl architecture beh of m macl is signal mult accu
140. 55 7778 General Constraints XST User Guide XILINX The default is yes In Project Navigator set verilog2001 globally with the Verilog 2001 option in the Synthesis Options tab of the Process Properties dialog box HDL Library Mapping File INI File Use the HDL Library Mapping File command xsthdpini to define the library mapping There is a library mapping file and two associated parameters XSTHDPINI and XSTHDPDIR The library mapping file contains the library name and the directory in which this library is compiled XST maintains two library mapping files The pre installed file which is installed during the Xilinx software installation The user file which users may define for their own projects The pre installed default INI file is named xhdp ini and is located in XILINX vhdl xst These files contain information about the locations of the standard VHDL and UNISIM libraries These should not be modified but the syntax can be used for user library mapping This file appears as follows Default lib mapping for XST std XILINX vhdl xst std ieee SXILINX vhdl xst unisim unisim XILINX vhdl xst unisim aim SXILINX vhdl xst aim pls SXILINX vhdl xst pls You may use this file format to define where each of your own libraries must be placed By default all compiled VHDL flies will be stored in the xst sub directory of the ISE project directory You may place your custom INI file anywh
141. 7778 7 XILINX Chapter 3 FPGA Optimization For example if you use the following timing constraints TIMESPEC TSidentifier FROM source group TO dest group value units then the number of ports corresponds to the number of elements in the destination group For a given timing constraint XST may report that the number of failed paths is 100 But the number of failed destination ports is only two flip flops This means that it is sufficient to only analyze the design description for these two flip flops to detect what should be changed in order to meet timing Implementation Constraints XST writes all implementation constraints generated from HDL or constraint file attributes LOC into the output NGC file KEEP properties are generated by the buffer insertion process for maximum fanout control or for optimization purposes Virtex Primitive Support XST enables you to instantiate Virtex primitives directly in your VHDL Verilog code Virtex primitives such as MUXCY L LUT4_L CLKDLL RAMB4_ 1_S16 IBUFG_PCI33_5 and NAND3b2 can be manually inserted in your HDL design through instantiation These primitives are not by default optimized by XST and are available in the final NGC file Use the Optimize Instantiated Primitives synthesis option to optimize instantiated primitives and obtain better results Timing information is available for most of the primitives allowing XST to perform efficient timing dr
142. 78 Macro Generation XILINX Shift Register RAMs XST User Guide Two types of shift register are built by XST e Serial shift register with single output e Parallel shift register with multiple outputs The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula Width 8 A3 4 A2 2 A1 A0 1 If A3 A2 Al and AO are all zeros 0000 the shift register is one bit long If they are all ones 1111 it is 16 bits long For serial shift register SRL16 flip flops are chained to the appropriate width For a parallel shift register each output provides a width of a given shift register For each width a serial shift register is built it drives one output and the input of the next shift register You can enable disable shift register inference using the SHREG_EXTRACT constraint Two types of RAM are available in the inference and generation stages distributed and block RAMs e Ifthe RAM is asynchronous READ Distributed RAM is inferred and generated e If the RAM is synchronous READ block RAM is inferred In this case XST can implement block RAM or distributed RAM The default is block RAM For Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Virtex 4 Spartan II Spartan ITE and Spartan 3 devices XST uses the following primitives e RAMI6XIS and RAM32XIS for Single Port Synchronous Distributed RAM e RAMI6XID primitives f
143. A port is a component I O connector A signal corresponds to a wire between components In Verilog a component is represented by a design module The module declaration provides the external view of the component it describes what can be seen from the outside including the component ports The module body provides an internal view it describes the behavior or the structure of the component The connections between components are specified within component instantiation statements These statements specify an instance of a component occurring within another component or the circuit Each component instantiation statement is labeled with an identifier Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list that specifies which actual signals or ports are associated with which local ports of the component declaration www xilinx com 341 1 800 255 7778 XILINX Chapter 7 Verilog Language Support The Verilog language provides a large set of built in logic gates which can be instantiated to build larger logic circuits The set of logical functions described by the built in gates includes AND OR XOR NAND NOR and NOT Here is an example of building a basic XOR function of two single bit inputs a and b module build_xor a b c input a b output c wire c a not b not not a inv a not a not b inv b not b and
144. ASYL PKG_RTL Supported ASYL ASYL1164 Supported BOOLEAN BIT Supported STD_ULOGIC Supported Enumeration Types STD LOGIC XO1 UX01 XO1Z UX01Z Supported Character Supported INTEGER Supported Integer Types POSITIVE Supported NATURAL Supported TIME Ignored REAL Supported only in Physical Types functions for constant calculations www xilinx com 1 800 255 7778 315 XILINX Chapter 6 VHDL Language Support Table 6 3 Design Entities and Configurations BIT_VECTOR Supported STD_ULOGIC_VECTOR Supported STD_LOGIC_VECTOR Supported Composite UNSIGNED Supported SIGNED Supported Record Supported Access Supported File Supported Table 6 4 Mode In Out Inout Supported Buffer Supported Linkage Unsupported Table 6 5 Declarations Type Supported for enumerated types types with positive range having constant bounds bit vector types and multi dimensional arrays Subtype Supported Table 6 6 Objects Constant Declaration Supported deferred constants are not supported Signal Declaration Supported register or bus type signals are not supported Variable Declaration Supported File Declaration Supported Alias Declaration Supported Attribute Declaration Supported for some attributes otherwise skipped see Chapter 5 Design Constraints Component Declaration Supported 316 www xi
145. Architecture Descriptions 7 XILINX architecture ARCHI of EXAMPLE is signal T std_logic begin end ARCHI Component Instantiation Structural descriptions assemble several blocks and allow the introduction of hierarchy in a design The basic concepts of hardware structure are the component the port and the signal The component is the building or basic block A port is a component I O connector A signal corresponds to a wire between components In VHDL a component is represented by a design entity This is actually a composite consisting of an entity declaration and an architecture body The entity declaration provides the external view of the component it describes what can be seen from the outside including the component ports The architecture body provides an internal view it describes the behavior or the structure of the component The connections between components are specified within component instantiation statements These statements specify an instance of a component occurring inside an architecture of another component Each component instantiation statement is labeled with an identifier Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list following the reserved word port map that specifies which actual signals or ports are associated with which local ports of the component declaration Note XST supports unc
146. B in std logic REA out std logic end component signal tmp std logic begin inst and one and one port map A gt A B gt B REZ gt tmp inst and two and two port map A gt tmp B gt C REZ gt REZ end beh XST User Guide www xilinx com 223 1 800 255 7778 XILINX 224 Chapter 3 FPGA Optimization If a function cannot be mapped on a single LUT XST issues an Error and interrupts the synthesis process If you would like to define an INIT value for a flip flop described at RTL level you can assign its initial value in the signal declaration stage This value is not ignored during synthesis and is propagated to the final netlist as an INIT constraint attached to the flip flop This feature is supported for registers only It is not supported for RAM descriptions In the following VHDL example a 4 bit register is inferred for signal tmp An INIT value equal 1011 is attached to the inferred register and propagated to the final netlist library ieee use ieee std_logic_1164 all entity test is port CLK in std_logic DO out std_logic_vector 3 downto 0 end test architecture beh of test is signal tmp std_logic_vector 3 downto 0 1011 begin process CLK begin if clk event and clk 1 then tmp lt DI end if end process DO tmp end beh To infer a register in the previous example and place it in a specific location of a chip attach an RLO
147. C constraint to the tmp signal as in the following VHDL example XST propagates it to the final netlist Please note that this feature is supported for registers and is supported for inferred block RAM as well if it can be implemented on a single block RAM primitive library ieee use ieee std logic 1164 al l entity test is port CLK in std logic DI in std logic vector 3 downto 0 DO out std logic vector 3 downto 0 end test www xilinx com XST User Guide 1 800 255 7778 PCI Flow PCI Flow XST User Guide XILINX architecture beh of test is signal tmp std_logic_vector 3 downto 0 1011 attribute RLOC string attribute RLOC of tmp signal is X3YO X2YO X1Y0 XOYO begin process CLK begin if clk event and clk 1 then tmp lt DI end if end process DO tmp end beh To successfully use PCI flow with XST i e to satisfy all placement constraints and meet timing requirements set the following options For VHDL designs ensure that the names in the generated netlist are all in uppercase Note that by default the case for VHDL synthesis flow is lower Specify the case by selecting the Case option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator For Verilog designs ensure that Case is set to maintain which is a default value Specify Case as described above Preserve the hierarchy of the design Specify the Keep Hierarchy sett
148. D2 components use the entity NAND2 and Architecture ARCHI Note When the configuration clause is missing for a component instantiation XST links the component to the entity with the same name and same interface and the selected architecture to the most recently compiled architecture If no entity architecture is found a black box is generated during synthesis Generic Parameter Declaration Generic parameters may be declared in the entity declaration part XST supports all types for generics including integer boolean string real std_logic_vector etc An example of using generic parameters would be setting the width of the design In VHDL describing circuits with generic ports has the advantage that the same component can be repeatedly instantiated with different values of generic ports as shown in Example 6 4 XST User Guide www xilinx com 295 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Example 6 4 Generic Instantiation of Components Library IEEE use IEEE std_logic_1164 all use IEEE td_logic_unsigned all o o entity addern is generic width integer 8 port A B in std logic vector width 1 downto 0 N out std logic vector width 1 downto 0 end addern architecture bhv of addern is begin Y lt A B end bhv Library IEEE use IEEE std_logic_1164 all entity top is port X Y Z in std logic ve
149. DO input CLK RST output 7 0 DO reg 7 0 DO always posedge CLK or posedge RST if RST 1 b1 DO lt 8 b00000000 else DO lt DO 8 b00000001 endmodule XST User Guide www xilinx com 333 1 800 255 7778 XILINX Chapter 7 Verilog Language Support Assign and Deassign Statements Assign and deassign statements are supported within simple templates The following is an example of the general template for assign deassign statements module assig RST SELECT STATE CLOCK DATA_IN input RST input SELECT input CLOCK input 0 3 DATA_IN output 0 3 STATE reg 0 3 STATE always RST if RST begin assign STATE 4 b0 end else begin deassign STATE end always posedge CLOCK begin STATE lt DATA_IN end endmodule The main limitations on support of the assign deassign statement in XST are as follows e Fora given signal there must be only one assign deassign statement For example XST rejects the following design module dflop RST SET STATE CLOCK DATA_ IN input RST input SET input CLOCK input DATA_IN output STATE reg STATE always RST block bl if RST assign STATE 1 b0 else deassign STATE always SET block bl if SET assign STATE 1 b1 else deassign STATE always posedge CLOCK
150. ESIS constraint is found During synthesis XST generates a single NGC file for the logic group e Beginning in release 7 1i you can apply the INCREMENTAL_SYNTHESIS constraint to a block that is instantiated a multiple number of times e Ifa single block is changed then the entire logic group is resynthesized and a new NGC file s is generated e Beginning in release 7 11 XST can propagate INCREMENTAL_SYNTHESIS constraints to the NGC netlist in the form of rangeless area groups This enables www xilinx com XST User Guide 1 800 255 7778 Incremental Synthesis Flow XILINX automatic floorplanning in the implementation flow You can do this by setting the Enable Auto Floorplaming option to incremental design under the Synthesis Options tab of the Process Properties dialog box Please note that by default XST does not propagate INCREMENTAL_SYNTHESIS constraints to the final netlist Example Figure 3 1 shows how blocks are grouped by use of the INCREMENTAL_SYNTHESIS constraint Consider the following e LEVA LEVA 1 LEVA 2 my add my sub as one logic group e LEVB my and my or and my sub as another logic group e TOP is considered separately as a single logic group LEVA incremental synthesis true LEVB incremental synthesis true X9858 Figure 3 1 Grouping through Incremental Synthesis RESYNTHESIZE XST is able to automatically recognize what blocks were changed and to resynthesize only changed ones
151. Function Inputs 9 Function Only for Mealy Machine PROCESS 1 PROCESS 2 PROCESS 3 X8987 Separating the NEXT State function from the state register provides the following description VHDL Code Following is the VHDL code for an FSM with three processes library IEEE use IEEE std logic 1164 a11 entity fsm is port clk reset xl IN std logic outp OUT std logic end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state next state state type begin processi process clk reset begin if reset 1 then state lt sl elsif clk 1 and clk Event then state lt next_state end if end process processl 188 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX process2 process state x1 begin case state is when sl gt if x1 1 then next_state lt s2 else next_state lt s3 end if when s2 gt next_state lt s4 when s3 gt next_state lt s4 when s4 gt next_state lt sl end Case end process process2 process3 process state begin Case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end Case end process process3 end behl Verilog Code Following is the Verilog code for an FSM with three processes module fsm clk reset x1 outp input clk reset x1 output outp
152. HDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using tristate buffers library ieee use leee std_logic_1164 all entity mux is port ay D O d ds S O end mux td logic in std logic vector 3 downto 0 out std logic architecture archi of mux is begin o o lt o o ow og aao oo when s 0 when s 1 when s 2 when s 3 end archi Verilog Code else Z else Z else Z else Z Following is the Verilog Code for a 4 to 1 1 bit MUX using tristate buffers module mux a b c input a b c d input 3 0 s output o assign o s 3 a assign o s 2 b assign o s 1 c assign o s 0 d endmodule No 4 to 1 MUX XST User Guide d s o EL DZ 1 bz LIDA 1 bz The following example does not generate a 4 to 1 1 bit MUX but a 3 to 1 MUX with 1 bit latch The reason is that not all selector values were described in the If statement It is supposed that for the s 11 case O keeps its old value and therefore a memory element is needed www xilinx com 91 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques The following table shows pin definitions for a 3 to 1 1 bit MUX with a 1 bit latch 10 Pins Description a b c d Data Inputs s 1 0 Selector O Data Output VHDL Code Following is the VHDL code for a 3 to 1 1 bit MUX with a 1 bit latch library ieee use leee std_logic_1164 all ent
153. HESIS constraint can now be applied to blocks that are instantiated more than once See Incremental Synthesis Flow in Chapter 3 Improved detection and reporting of multi source problems Reporting the number of analyzed or failed paths and ports in Detailed Timing Report See Timing Detail in Chapter 3 Detection and reporting of combinatorial loops Improved quality of results under high optimization effort for speed oriented optimization New Message filtering mechanism XST in Project Navigator Before synthesizing your design you can set a variety of options for XST Following are the instructions to set the options and run XST from Project Navigator All of these options can also be set from the command line See Chapter 5 Design Constraints and Chapter 10 Command Line Mode for details 22 www xilinx com XST User Guide 1 800 255 7778 XST in Project Navigator 7 XILINX 1 Select your top level design in the Source window E Xilinx Project Navigator C Temp v2_fifo_vhd_258 v File Edit View Project Source Process Simulation Window as eie 2 8 0 05 5 zd xl cc v2difoctlr cc v2 hdl ffifoctlr cc v2 vi M tb _cc_arch fifoctlr_cc_tb vhd D Ence io IE ncir ic v2 hdl ffaetle ie v2 xn uote enm Generate Pnst Sunthesie Simulation XST User Guide www xilinx com 23 1 800 255 7778 7 XILINX Chapter 1 Introduction 2 To set the options right click Synthesize X
154. IOBs BRAMS etc This report is very close to the one produced by MAP Clock Information A shorttable gives information about the number of clocks in the design how each clock is buffered and how many loads it has Timing Report At the end of the synthesis XST reports the timing information for the design The report shows the information for all four possible domains of a netlist register to register input to register register to outpad and inpad to outpad XST User Guide www xilinx com 215 1 800 255 7778 XILINX Chapter 3 FPGA Optimization The following is an example of a timing report section in the XST log NOTE HESE IMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE and ROUTE Clock Information Clock Signal Clock buffer FF name Load clk BUFGP 9 Timing Summary Speed Grade 6 Minimum period 7 523ns Maximum Frequency 132 926MHz Minimum input arrival time before clock 8 945ns Maximum output required time after clock 14 220ns Maximum combinational path delay 10 889ns Timing Detail All values displayed in nanoseconds ns Timing constraint Clock period frequency 132 9 Default period analysis for Clock clk 7 523ns Total number of paths destinat
155. L and Verilog Examples and Templates Macro Blocks Arithmetic Operators Chapter Examples Unsigned 8 bit Adder Unsigned 8 bit Adder with Carry In Unsigned 8 bit Adder with Carry Out Unsigned 8 bit Adder with Carry In and Carry Out Simple Signed 8 bit Adder Unsigned 8 bit Subtractor Unsigned 8 bit Adder Subtractor Unsigned 8 bit Greater or Equal Comparator Unsigned 8x4 bit Multiplier Division By Constant 2 Resource Sharing Language Templates N Bit Comparator Synchronous with Reset www xilinx com 1 800 255 7778 39 7 XILINX Chapter 2 HDL Coding Techniques Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Chapter Examples Language Templates RAMs Single Port RAM with Single Port Block RAM Asynchronous Read Single Port RAM with Single Port Distributed RAM False Synchronous Read Single Port RAM with Synchronous Read Read Through Dual Port RAM with Dual Port Block RAM Asynchronous Read Dual Port RAM with False Dual Port Distributed RAM Synchronous Read Dual Port RAM with Synchronous Read Read Through Dual Port Block RAM with Different Clocks Block RAM with Reset Multiple Port RAM Descriptions State Machines FSM with 1 Process Binary State Machine FSM with 2 Processes FSM with 3 Processes One Hot State Machine Black Boxes VHDL Code None Verilog Code Signed Unsigned Support When using Verilog or VHDL in
156. LE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 HDL Analysis 4 Advanced HDL Synthesis 4 1 HDL Synthesis Report 5 HDL Synthesis 6 Low Level Synthesis 7 Final Report 7 1 Device utilization summary 7 2 TIMING REPORT Synthesis Options Summary Source Parameters Input File Name Input Format Ignore Synthesis Constraint File Verilog Include Directory Target Parameters Output File Name Output Format Target Device stopwatch prj mixed NO stopwatch NGC xc2v40 6 cs144 366 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File Source Options Top Module Name stopwatch Automatic FSM Extraction YES FSM Encoding Algorithm one hot FSM Style lut RAM Extraction Yes RAM Style Auto ROM Extraction Yes ROM Style Auto Mux Extraction YE Mux Style Auto Decoder Extraction YES Priority Encoder Extraction YES Shift Register Extraction YES Logical Shifter Extraction YES XOR Collapsing YES Resource Sharing YES Multiplier Style auto Automatic Register Balancing No Target Options Add IO Buffers YES Global Maximum Fanout 500 Add Generic Clock Buffer BUFG 16 Register Duplication YES Equivalent register Removal YES Slice Packing YES Pack IO Registers into IOBs auto General Options Optimization Goal Speed Optimization Effort 1 Keep Hierarchy YES Global Optimization AllClockNets RTL Out
157. LT_SEARCH_ORDER 360 www xilinx com XST User Guide 1 800 255 7778 Library Search Order File XILINX XST uses the following search order vhlibl rtfllib vhlib2 After processing the contents of my proj 1so will be rtfllib vhlib2 vhlib1 DEFAULT SEARCH ORDER Example 3 For a project file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my proj 1so created with the following contents rtfllib vhlib2 vhlib1 XST uses the following search order rtfllib vhlib2 vhlibl After processing the contents of my_proj 1so will be rtfllib vhlib2 vhlibl Example 4 For a project file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my_proj 1so created with the following contents personal_lib rtfllib vhlib2 vhlibl XST User Guide www xilinx com 361 1 800 255 7778 7 XILINX Chapter 8 Mixed Language Support XST uses the following search order rtfllib vhlib2 vhlibl After processing the contents of my proj 1so will be rtfllib vhlib2 vhlibl 362 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis Introduction XST User Guide This chapter contains the following sections Introduction Reducing the Size of the LOG File Timing Report FPGA Log File CPLD Lo
158. M is identified it can be inferred either as a distributed ROM plus a register or it can be inferred using block RAM resources The ROM STYLE attribute specifies what kind of synchronous ROM XST infers as follows e Ifsetto block and the ROM fits entirely on a single block of RAM XST infers the ROM using block RAM resources e Ifsetto distributed XST infers a distributed ROM plus register www xilinx com XST User Guide 1 800 255 7778 Using DSP48 Block Resources 7 XILINX e If set to auto XST determines the most efficient method to use and infers the ROM accordingly Auto is the default You can apply ROM_STYLE as a VHDL attribute or a Verilog meta comment to an individual signal or to the entity module of the ROM This attribute can also be applied globally from the Process Properties dialog box in Project Navigator or from the command line Using DSP48 Block Resources XST can automatically implement several macros on a DSP48 block Supported macros are the following e adders subtractors e accumulators e multipliers e multiply adder subtractors e multiply accumulate MAC XST supports the registered versions of these macros as well Macro implementation on DSP48 blocks is controlled by the USE_DSP48 constraint command line option with a default value of auto In auto mode XST attempts to implement accumulators multipliers multiply adder subtractors and MACs on DSP48 resources XST does not implement ad
159. Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs in Verilog module mvl_multaddsub2 clk add_sub A B C RES input clk add_sub input 7 0 A input 7 0 B input 7 0 C output 15 0 RES reg 7 0 A_regl A_reg2 B_regl B_reg2 wire 15 0 mult multaddsub always posedge clk begin A_regl lt A A_reg2 lt A regl B_regl lt B B_reg2 lt B_regl end assign mult A_reg2 B_reg2 assign multaddsub add sub mult C mult C assign RES multaddsub endmodule Multiply Accumulate MAC The Multiply Accumulate macro is a complex macro which consists of several basic macros such as multipliers accumulators and registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources available on Virtex 4 devices XST User Guide www xilinx com 125 1 800 255 7778 XILINX 126 Chapter 2 HDL Coding Techniques Log File In the Log file XST reports the details of inferred multipliers accumulators and registers at the HDL Synthesis step The composition of multiply accumulate macros happens at the Advanced HDL Synthesis step HDL Synthesis Synthesizing Unit m macl Related source file is m macl vhd Found 16 bit up accumulator for signal accum Found 8x8 bit multiplier for signal mult Summary inferred 1 Accumulator s inferred 1 Multiplier s Unit lt m_macl gt synthesized
160. O ke ex ede ded d X HU e s 46 Merniloe Codeces merci deeds acea eue sauce le ren ee iia 47 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable 47 VHDL Cod iiss bes Bae CE eR E RR E GR RR Fe ER AUG RE ETE EES Dae 48 Verilog Codes crece re ere I hen RtRPd D PE LE Re bue pide rubato tede 48 Latcli s a ote os ete cue etes M Itu et 48 Log File vali sd as the Uer Ee eL Ge bbb Udo ayas teda beads 49 Related Constraints o 49 XST User Guide www xilinx com 1 800 255 7778 XILINX Latch with Positiv Gate esed e ee e Ree ae ve ved ered a He s 49 VHDL Code susi RE ER REC Eee nee EHS Dane Tees haw es 50 Verilog Code iccictud mega ira obra rar needa Gaede paisas 50 Latch with Positive Gate and Asynchronous Clear 0 0 e cece eee ee 50 VHDL Code RR bees heeds paws A asi 51 Verilog Code tics c dee eet ee e E AAA EA 51 4 bit Latch with Inverted Gate and Asynchronous Preset ooooooooooommmoo 52 VHDL Code sisi A E X ERHREPRR ERR Sale was wale EA ES 52 Verilog Code vss edet i rk oe Stes YU Yew vga Ru d ev 53 lori e ilhed 53 Log File efire Ra ee eter ER ee pe caa ace hace dns 53 Related Constraints eere a oi pa e Pd PE peni n Eder dis 53 Description Using Combinatorial Process and Always Block 54 VODL Code c c m 54 Verilog Code s ie e o e adit gp ee E eiae ead 55 Description Using Concurrent AssignMenNt oooo
161. OUT 0 end scope lsbcount end scope sixty begin scope lsbled LUT4 10 gt 0 1 0 347 0 383 Mrom_LED_inst_lut4_101 LED 0 end scope lsbled OBUF I O 3 743 ONESOUT 0 OBUF ONESOUT 0 Total 5 835ns 4 539ns logic 1 296ns route 77 8 logic 22 2 route XST User Guide www xilinx com 373 1 800 255 7778 XILINX Chapter 9 Log File Analysis Timing constraint Default path analysis Total number of paths destination ports 41 11 Delay 6 306ns Levels of Logic 4 Source XCOUNTER 0 lt 1 gt PAD Destination TENTHSOUT lt 9 gt PAD Data Path XCOUNTER Q lt 1 gt to TENTHSOUT lt 9 gt Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name tenths Q lt 1 gt 10 0 000 0 000 XCOUNTER 0 lt 1 gt begin scope decoder LUT4 10 gt 0 1 0 347 0 608 Mrom one hot inst lut4 91 one hot 9 end scope decoder LUT1 10 gt 0 L 0 347 0 383 ENTHSOUT lt 9 gt 1 TENTHSOUT_9_OBUF OBUF 1 gt 0 3 743 ENTHSOUT_9_OBUF TENTHSOUT lt 9 gt Total 6 306ns 5 316ns logic 0 990ns route 84 3 logic 15 7 route CPU 5 04 6 55 s Elapsed 5 00 6 00 s Total memory usage is 102576 kilobytes Number of errors O O filtered Number of warnings 3 O filtered Number of infos O O filtered 374 www xilinx com 1 800 255 7778 XST User Guide CPLD Log File XILINX CPLD Log File The following
162. Output VHDL Code Following is the VHDL code for a 4 bit unsigned up down counter with an asynchronous clear library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C CLR UP_DOWN in std_logic Q out std logic vector 3 downto 0 end counter XST User Guide www xilinx com 63 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of counter is signal tmp std_logic_vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp lt 0000 elsif C event and C 1 then if UP_DOWN 1 then tmp lt tmp 1 else tmp lt tmp 1 end if end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up down counter with an asynchronous clear module counter C CLR UP DOWN Q input C CLR UP DOWN output 3 0 Q reg 3 0 tmp always G posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else if UP_DOWN tmp lt tmp 1 b1 else tmp lt tmp 1 b1 end assign Q tmp endmodule 4 bit Signed Up Counter with Asynchronous Reset The following table shows pin definitions for a 4 bit signed up counter with an asynchronous reset 10 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 3 0 Data Output 64 www xilinx com XST User Guide 1 800 255 7778 Counters XILINX VHDL C
163. PPOE ti ii AR E EA 19 XST FloW cuiecoiciina diri a qi ERE PEL 19 What s NeW ocoosiurioss tantos anise RERO REA eA pA AN eIT Y PEST eI4u didus 19 HDL Language Support sssssssseeeeeeeeee eh 19 VHDLD ce ht te ed bee od eal bee Lae Pie te Veen A REN ee 19 MEL o A PT A EA ATA A A cie dta 20 Macro Inference sb eb REESE ER e CERAM REA betes bree RUNG 20 Design Constraints cerro a ria 21 FPGA PlOW iu y bres PE la op ba diia 22 Log Filete t so vs ePi Rei utu M UE 22 XST in Project Navigator cie rye e IR PER PDAs 22 Chapter 2 HDL Coding Techniques Introduction Hei HR P E det io dn 29 Signed Unsipned Sap potty cic cence HERR Ie OE bci RADICIS dor tp Ro ERR coke 40 REIS M 41 Los A eiteasdode 41 Related Constraints o 42 Flip flop with Positive Edge Clock nananana nannan cen eens 42 VADL Code cuisine eT de EY exe radere 42 Verlog Codez sss cene ibd pr cbr treed erede eed tp Paeaope tipos 43 Flip flop with Negative Edge Clock and Asynchronous Clear 43 VADC Code eui da A bee reb A ERN RA Oe t 44 Venlog Code ccce ii iere rid ee ia cud adeat a e e 44 Flip flop with Positive Edge Clock and Synchronous Set Lsssue 44 VEIDL Code iia bee tr E ERE RE A ae eae les ee avd 45 Verilog Codec 12 40 resibes 4t be P bU P sex EE Ca peu ep We Vues 45 Flip flop with Positive Edge Clock and Clock Enable ooooo ooooooommo ooo 46 VEDELE COde i ky ee rERM ER
164. Presque eu 359 Search Order Rules ose b e ERE RESTI RE T REX CE 359 Examples e diese vend teire REO ER RE LES EE AR Pr dee ed ER NU EE ae Se 360 Example PE 360 AA dati oped tienebek rv pepe 2460 Riese ie 360 Iocidgc ETE 361 Example s cedes tebe ods bebe ede vie ei wale ve euis need 361 Chapter 9 Log File Analysis Introduction 0 ccc cece cece e e ee 363 Reducing the Size of the LOG Hle cene coran creia res 364 Quiet Mode sexos dd IC eee IA Her PII RR RE RES 364 Silent Mode dat aec t cre Poe eed ee ene ERR 365 Hiding specific messages isses een 365 Timi g ES SPN rr ne ah in hc 366 FPGA Log File 2522522241 0x43 OE GER dl aa ee a Ke bd e td 366 CPLD Log File isaaaaodo dac kde ect ener Erde edere ee aee hia ae 375 Chapter 10 Command Line Mode IO OA i ove ves xw xod x EF UE Pn ELTE Mrd ERA FE Od riga Ee 381 File LV e seat PM MU t pu NE 381 Names With Spaces caesserer ee END its RE RN qoM bpdoo eiid tatis eleg tieien 382 Launching AS Ts rias e bn c de up Royan ons 382 Setting Up an XS Scripts id ii A RH ER aS 383 Run Commando oos dato dus A A 383 Getting Help cursar dd rial adea qa e 388 Set CoMo EY dd ea dba 390 Elaborate Cait anid di da EUN ES RA ed 391 Example 1 How to Synthesize VHDL Designs Using Command Line INOS oi tamente tie en dae dea adde nex ee Fade ercer od dU m dept 391 Example eae E 392 Script Mode iii m seb ab sedi a e E Av E CIR RAN Rr PEE Ex 393 Example 2 How to Synthesiz
165. Quiet Mode 364 Quiet mode allows you to limit the number of messages that are printed to the computer screen stdout Quiet mode can be invoked by using the intstyle command line switch with its value set to either ise or xflow as appropriate The ise option formats messages for ISE while the xflow option formats messages for XFLOW use You can also use the old quiet switch but Xilinx strongly recommends that you not use this method because it will become obsolete in coming releases Normally XST prints the entire log to stdout In quiet mode XST does not print the following portions of the log to stdout e Copyright Message e Table Of Contents e Synthesis Options Summary www xilinx com XST User Guide 1 800 255 7778 Reducing the Size of the LOG File XILINX e The following portions of the Final Report Final Results header for CPLDs Final Results section for FPGAs The following note in the Timing Report NOTE HESE IMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE AND ROUTE Timing Detail CPU XST run time Memory usage Note Device Utilization Summary Clock Information and Timing Summary are still available for FPGAs Silent Mode Silent mode allows you keep any messages from going to the computer screen std
166. Related Constraints XST has a BOX_TYPE constraint that can be applied to black boxes However it was introduced essentially for Virtex Primitive instantiation in XST Please read Virtex Primitive Support in Chapter 3 in before using this constraint VHDL Code XST User Guide Following is the VHDL code for a black box library ieee use ieee std_logic_1164 all entity black_b is port DI_1 DI_2 in std_logic DOUT out std_logic end black_b www xilinx com 195 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques architecture archi of black_b is component my_block port Il in std logic I2 in std logic O out std logic end component begin inst my block port map I1 gt DI_1 I2 gt DI_2 O gt DOUT end archi Verilog Code Following is the Verilog code for a black box module my_block inl in2 dout input inl in2 output dout endmodule module black_b DI_1 DI_2 DOUT input DI_1 DI_2 output DOUT my_block inst sand DTA in2 DI 2 dout DOUT endmodule Note Please refer to the VHDL Verilog language reference manuals for more information on component instantiation 196 www xilinx com 1 800 255 7778 XST User Guide 7 XILINX Chapter 3 FPGA Optimization Introduction XST User Guide This chapter contains the following sections Introduction Virtex Specific Synthesis Options Macro Gener
167. Report Macro Statistics Priority Encoders dl 3 bit l of 9 priority encoder 1 3 Bit 1 of 9 Priority Encoder Note For this example XST may infer a priority encoder You must use the PRIORITY_EXTRACT constraint with a value force to force its inference Related Constraint A related constraint is PRIORITY_EXTRACT VHDL Code 98 Following is the VHDL code for a 3 bit 1 of 9 Priority Encoder library ieee use ieee std_logic_1164 all entity priority is port sel in std_logic_vector 7 downto 0 code out std_logic_vector 2 downto 0 end priority www xilinx com XST User Guide 1 800 255 7778 Logical Shifters architecture archi begin code lt end archi Verilog Code Logical Shifters XST User Guide 900 901 010 011 100 101 110 111 XILINX of priority is wh wh wh wh wh wh wh DOPO A OP PF RAAD 000000000 wh YAO BWNE O I I I I I I I I H H H H H H H Qo 0 000000 Following is the Verilog code for a 3 bit 1 of 9 Priority Encoder module priority sel input 7 0 se output 2 0 c reg 2 0 code always G sel begin if sel 0 else if sel else if sel else if sel else if sel else if sel else if sel else if sel else end endmodule 1 ode code 1 YHA Of WD UA code 3 p000 code 3 b001 code 3 b010 code 3 b011 code
168. ST and lists supported architectures e Chapter 2 HDL Coding Techniques describes a variety of VHDL and Verilog coding techniques that can be used for various digital logic circuits such as registers latches tristates RAMs counters accumulators multiplexers decoders and arithmetic operations The chapter also provides coding techniques for state machines and black boxes e Chapter 3 FPGA Optimization explains how constraints can be used to optimize FPGAs and explains macro generation The chapter also describes the Virtex primitives that are supported e Chapter 4 CPLD Optimization discusses CPLD synthesis options and the implementation details for macro generation e Chapter 5 Design Constraints describes constraints supported for use with XST The chapter explains which attributes and properties can be used with FPGAs CPLDs VHDL and Verilog The chapter also explains how to set options from the Process Properties dialog box in Project Navigator e Chapter 6 VHDL Language Support explains how VHDL is supported for XST The chapter provides details on the VHDL language supported constructs and synthesis options in relationship to XST e Chapter 7 Verilog Language Support describes XST support for Verilog constructs and meta comments e Chapter 8 Mixed Language Support describes how to run an XST project that mixes Verilog and VHDL designs e Chapter 9 Log File Analy
169. ST in the Process window select Properties to display the Process Properties dialog box PS ilinx ar C Temp v2 rra vhd ETT File Edit View Project Source Process Simulation Window zd xl E A v2 filo vhd ise E readme E 3 xc2v40 4fg256 E M fifoctlr cc v24ifoctlr cc v2 hdl fifoctir_cc_v2 vhi M tb cc4b cc arch ffifoctir cc tb vhd wa Becr io se Pffnrtlr ic v2 hdl F nctr ic 17 ar MA Stop Open Without Updating 24 www xilinx com XST User Guide 1 800 255 7778 XST in Project Navigator 7 XILINX 3 Set the desired Synthesis HDL and Xilinx Specific Options in the Process Properties dialog box For a complete description of these options refer to General Constraints in Chapter 5 Process Properties x Synthesis Options HDL Options Xilinx Specific Options ok Camel bs We XST User Guide www xilinx com 25 1 800 255 7778 7 XILINX Chapter 1 Introduction 4 When a design is ready to synthesize you can invoke XST in Project Navigator With the top level source file selected double click Synthesize XST in the Process window PS xilinx Project Navigator C Templv2_fifo_vhd_258Y File Edit View Project Source Process Simulation Window xi B A v2 fio vhd ise E readme E 3 xc2v40 4g256 E fifoctir cc v24ifoctir cc v2 hdi ffifoctir cc v2 vh _ M tb cctb cc arch ffifoctir c
170. Spartan 3 devices See ROM STYLE in the Constraints Guide for details Shift Register Extraction The Shift Register Extraction SHREG EXTRACT constraint enables or disables shift register macro inference See SHREG EXTRACT in the Constraints Guide for details Slice Packing The Slice Packing slice packing option enables the XST internal packer The packer attempts to pack critical LUT to LUT connections within a slice or a CLB This exploits the fast feedback connections among the LUTs in a CLB Define this option globally with the slice packing command line option of the run command Following is the basic syntax slice packing yes no The default is yes In Project Navigator set slice packing globally with the Slice Packing option in the Xilinx Specific Options tab in the Process Properties dialog box Uselowskewlines The USELOWSKEWLINES constraint is a basic routing constraint From a Synthesis point of view it prevents XST from using dedicated clock resources and logic replication based on the value of the MAX FANOUT constraint It specifies the use of low skew routing resources for any net See USELOWSKEWLINES in the Constraints Guide for details www xilinx com XST User Guide 1 800 255 7778 FPGA Constraints non timing 7 XILINX XST User Guide XOR Collapsing The XOR Collapsing XOR_COLLAPSE constraint controls whether cascaded XORs should be collapsed into a single XOR See XOR_COLLAPSE
171. Statement The For statement is supported for e Constant bounds e Stop test condition using operators lt lt gt or gt e Next step computation falling within one of the following specifications e var var step var var step where var is the loop variable and step is a constant value e Next and Exit statements are supported Example 6 14 shows the use of a For loop statement Example 6 14 For Loop Description library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity countzeros is port a in std logic vector 7 downto 0 Count out std_logic_vector 2 downto 0 end mux4 architecture behavior of mux4 is signal Count_Aux std_logic_vector 2 downto 0 begin process a begin Count_Aux lt 000 for i in a range loop if a i 0 then Count Aux lt Count Aux 1 operator defined in std logic unsigned end if end loop Count Count Aux end process end behavior XST User Guide www xilinx com 303 1 800 255 7778 7 XILINX Chapter 6 VHDL Language Support Sequential Circuits Sequential circuits can be described using sequential processes The following two types of descriptions are allowed by XST e sequential processes with a sensitivity list e sequential processes without a sensitivity list Sequential Process with a Sensitivity List A process is sequential when itis not a combinator
172. Timing Constraints Constraints Summary Implementation Constraints Third Party Constraints Constraints Precedence Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit Constraints are available in XST to control various aspects of the synthesis process itself as well as placement and routing Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations In some cases however synthesis may fail to initially achieve optimal results some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs XST User Guide www xilinx com 233 1 800 255 7778 XILINX Chapter 5 Design Constraints The following mechanisms are available to specify constraints e Options provide global control on most synthesis aspects They can be set either from within the Process Properties dialog box in Project Navigator or by setting options of the run command from the command line e VHDL attributes can be directly inserted into your VHDL code and attached to individual elements of the design to control both synthesis and placement and routing e Constraints can be added as Verilog meta comments in your Verilog code e Constraints can be specified in a separate constraint file Typically global synthesis settings are defined within the Process Properties dialog b
173. UF with an input net name of DOUT the input OBUF net name is DOUT_OBUE Instance Naming Conventions These rules are listed in order of naming priority 1 Keep hierarchy in instance names using underscores as hierarchy designators Name register instances including state bits for the output signal 3 Name clock buffer instances clockbuffertype like BUFGP or IBUFG after the output signal 4 Maintain instantiation instance names of black boxes 5 Maintain instantiation instance names of library primitives 6 Name input and output buffers using the form _IBUF or OBUF after the pad name 7 Name Output instance names of IBUFs using the form instance name IBUF Name input instance names to OBUFs using the form instance name OBUF XST User Guide www xilinx com 399 1 800 255 7778 7 XILINX Appendix A XST Naming Conventions Name Generation Control You can control aspects of the way names are written using the following properties You can apply these properties by either using the ISE Synthesis Properties dialog box or using the appropriate command line options See Chapter 5 Design Constraints for more information on using these properties e hierarchy separator HIERARCHY_SEPARATOR e bus delimiter BUS_DELIMITER e case processing CASE e duplication suffix DUPLICATION SUFFIX 400 www xilinx com XST User Guide 1 800 255 7778 Index A accumulator 67 4 bit unsigned up accumulator with a
174. X Using Case Statement XILINX The following table shows pin definitions for a 4 to 1 1 bit MUX using a Case statement IO Pins Description a b c d Data Inputs s 1 0 MUX selector O Data Output XST User Guide www xilinx com 1 800 255 7778 89 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for a 4 to 1 1 bit MUX using a Case statement library ieee use ieee std_logic_1164 all entity mux is port a b c a in std_logic S in std logic vector 1 downto 0 o out std_logic end mux architecture archi of mux is begin process a b C d s begin case s is when 00 gt 0 lt a when 01 gt o lt b when 10 gt o lt Cc when others gt o lt d end case end process end archi Verilog Code Following is the Verilog Code for a 4 to 1 1 bit MUX using a Case statement module mux a input a b input 1 0 output o reg o b e S c d o d S always a or b or c or begin case s 2 b00 2 b01 2 b10 default endcase end endmodule d or s a C d Qo o D 90 www xilinx com XST User Guide 1 800 255 7778 Multiplexers XILINX 4 to 1 MUX Using Tristate Buffers The following table shows pin definitions for a 4 to 1 1 bit MUX using tristate buffers 10 Pins Description a b c d Data Inputs s 3 0 MUX Selector O Data Output V
175. XILINX 248 Chapter 5 Design Constraints Generate RTL Schematic The Generate RTL Schematic rtlview command line option enables XST to generate a netlist file representing an RTL structure of the design This netlist can be viewed by the RTL and Technology Viewers This option has three possible values yes no and only When the only value is specified XST stops the synthesis process just after the RTL view is generated The file containing the RTL view has an NGR file extension Generate RTL Schematic is defined globally with the tlview command line option of the run command Following is the basic syntax rtlview yes no only From the command line the default is no From Project Navigator the default is yes In Project Navigator specify tlview globally with the Generate RTL Schematic option in the Synthesis Options tab of the Process Properties dialog box Duplication Suffix The Duplication Suffix duplication suffix command line option controls how XST names replicated flip flops By default when XST replicates a flip flop it creates a name for the new flip flop by taking the name of the original flip flop and adding n to the end of it where n is an index number For example if the original flip flop name is my ff and this flip flop was replicated three times XST generates flip flops with the following names my ff 1 my ff 2 and my ff 3 Using the Duplication Suffix command line option you ca
176. XST some macros such as adders or counters can be implemented for signed and unsigned values For Verilog to enable support for signed and unsigned values you must enable Verilog 2001 You can enable it by selecting the Verilog 2001 option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator or by setting the verilog2001 command line option to yes See the VERILOG2001 section in the Constraints Guide for details 40 www xilinx com XST User Guide 1 800 255 7778 Registers XILINX For VHDL depending on the operation and type of the operands you must include additional packages in your code For example in order to create an unsigned adder you can use the following arithmetic packages and types that operate on unsigned values PACKAGE TYPE numeric_std unsigned std_logic_arith unsigned std_logic_unsigned std_logic_vector To create a signed adder you can use arithmetic packages and types that operate on signed values PACKAGE TYPE numeric_std signed std_logic_arith signed std_logic_signed std_logic_vector Please refer to the IEEE VHDL Manual for details on available types Registers XST recognizes flip flops with the following control signals e Asynchronous Set Clear e Synchronous Set Clear e Clock Enable Log File The XST log file reports the type and size of recognized flip flops during the Macro Recognition step Sy
177. XST User Guide XILINX 2005 Xilinx Inc All Rights Reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners NOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this feature application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose XST User Guide www xilinx com 1 800 255 7778 XILINX Preface About This Guide This manual describes Xilinx Synthesis Technology XST support for HDL languages Xilinx devices and constraints for the ISE software The manual also discusses FPGA and CPLD optimization techniques and explains how to run XST from Project Navigator Process window and command line Guide Contents This manual contains the following chapters and appendixes e Chapter 1 Introduction provides a basic description of X
178. XST User Guide www xilinx com 121 1 800 255 7778 XILINX 122 Chapter 2 HDL Coding Techniques XST can implement a multiply adder subtractor in a DSP48 block if its implementation requires only a single DSP48 resource If the macro exceeds the limits of a single DSP48 XST processes it as two separate Multiplier and Adder Subtractor macros making independent decisions on each macro Please refer to the Multipliers and Adders Subtractors Adders Subtractors sections for more information Macro implementation on DSP48 blocks is controlled by the USE_DSP48 constraint command line option with default value of auto Please note that when implementing multiply adders subtractors on DSP48 blocks XST does not perform any automatic DSP48 resource control and as a consequence the number of generated DSP48 blocks in the NGC netlist may exceed the number of available DSP48 blocks in a target device To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible If you want to shape a macro in a specific way you must use the KEEP constraint For example if you want to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers In the Log file XST reports the details of inferred multipliers adder subtractors and registers at the HDL Synthesis step XST reports about
179. _SEARCH_ORDER keyword XST searches the library files in the order in which they appear in the LSO file leaves the LSO file unchanged See Example 3 www xilinx com 359 1 800 255 7778 7 XILINX Chapter 8 Mixed Language Support e When the LSO file is empty XST generates a warning message stating that the LSO file is empty searches the files specified in the project file using the default library search order updates the LSO file by adding the list of libraries in the order that they appear in the project file e When the LSO file contains a library name that does not exist in the project or INI file and the LSO file does not contain the DEFAULT_SEARCH_ORDER keyword XST ignores the library See Example 4 Examples Example 1 For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib 1 v vhdl vhlib2 f3 vhd LSO file Created by ProjNav and an LSO file my proj 1so created by Project Navigator with the following contents DEFAULT_SEARCH_ORDER XST uses the following search order vhlibl rtfllib vhlib2 After processing the contents of my proj 1so will be vhlibl rtfllib vhlib2 Example 2 For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib fl v vhdl vhlib2 f 3 vhd and an LSO file my_proj 1so created with the following contents rtfllib vhlib2 vhlibl DEFAU
180. _logic end SINGLE_SRL architecture beh of SINGLE_SRL is signal shift_reg std_logic_vector SRL_WIDTH 1 downto 0 begin assert SRL_WIDTH lt 17 report The size of Shift Register exceeds the size of a single SRL severity FAILURE process clk begin if clk event and clk 1 then shift_reg lt shift_reg SRL_WIDTH 1 downto 1 amp inp end if end process outp lt shift_reg SRL_WIDTH 1 end beh www xilinx com XST User Guide 1 800 255 7778 Assert Statement XILINX library ieee use ieee std_logic_ entity TOP is port clk in std_lo inpl inp2 in outpl outp2 end TOP architecture beh of 1164 all gic std_logic out std_logic TOP is SRL is H integer 16 gic gic logic component SINGLE_ generic SRL_WIDT port elk in std_lo inp in std_lo outp out std end component begin instl SINGLE SRL port map clk gt clk inp gt inpl outp gt outpl inst2 SINGLE_SRL port map clk gt clk inp gt inp2 outp gt outp2 end beh generic map SRL_WIDTH gt 13 generic map SRL WIDTH gt 18 Running this example through XST results in the following error message generated by the Assert statement HDL Analysis Analyzing Enti Entity ty top analy Analyzing generic SRL WIDTH 13 Entity single srl Analyzing generic SRL WIDTH 18 ds the siz XC o
181. _logic_1164 all entity dec is port sel in std_logic_vector 2 downto 0 res out std_logic_vector 7 downto 0 end dec architecture archi of dec is begin res lt 00000001 when sel 000 else XXXXXXXX when sel 001 els unused decoder output 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi Verilog Code No Decoder Inference For the following Verilog code XST does not infer a decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always sel begin Case sel 3 b000 res 8 b00000001 3 b001 res 8 bxxxxxxxx unused decoder output 3 b010 res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100000 3 b110 res 8 b01000000 default res 8 b10000000 endcase end endmodule 96 www xilinx com XST User Guide 1 800 255 7778 Decoders XILINX VHDL Code Decoder Inference The following VHDL code leads to the inference of a 1 of 8 decoder library ieee use ieee std_logic_1164 all entity dec is port sel in std_logic_vector 2 downto 0 res out std_logic_vector 7 downto 0 end dec architecture archi of dec is begin res lt 00000001 when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 wh
182. a out This means that if your shift register does have for instance a synchronous parallel load no SRL16 is implemented XST uses specific internal processing which enables it to produce the best final results www xilinx com 71 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques The XST log file reports recognized shift registers when it can be implemented using SRL16 Log File The XST log file reports the type and size of recognized shift registers during the Macro Recognition step Synthesizing Unit lt shift gt Related source file is shift registers l vhd Found 8 bit shift register for signal lt tmp lt 7 gt gt Summary inferred 1 Shift register s Unit shift synthesized HDL Synthesis Report Macro Statistics Shift Registers 8 bit shift register Related Constraints A related constraint is SHREG_EXTRACT 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out Note For this example XST infers an SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a serial in and a serial out 10 Pins Description C Positive Edge Clock SI Serial In SO Serial Output 72 www xilinx com 1 800 255 7778 XST User Guide Shift Registers XILINX VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock a serial in an
183. a signal that defines the RAM or the instance name of the RAM This attribute can also be global If the RAM resources are limited XST can generate additional RAMs using registers To do this use the RAM EXTRACT attribute with the value set to no A ROM can be inferred when all assigned contexts in a Case or If else statement are constants Macro inference only considers ROMs of at least 16 words with no width restriction For example the following HDL equation can be implemented with a ROM of 16 words of 4 bits data if address 0000 then 0010 if address 0001 then 1100 if address 0010 then 1011 if address 1111 then 0001 A ROM can also be inferred from an array composed entirely of constants as in the following HDL example type ROM TYPE is array 15 downto 0 of std logic vector 3 downto 0 constant ROM rom type 0010 1100 1011 0001 data lt ROM conv integer address The ROM EXTRACT attribute can be used to disable the inference of ROMs Use the value yes to enable ROM inference and no to disable ROM inference The default is yes Two types of ROM are available in the inference and generation stages Distributed ROM and Block ROM e Distributed ROMs are generated by using the optimal tree structure of LUT MUXF5 MUXF6 MUXF7 and MUXES primitives which allows compact implementation of large inferred ROMs e Block ROMs are generated by using block RAM resources When a synchronous RO
184. ad MY LINE MY DATA end loop Data Types in VHDL XST accepts the following VHDL basic types e Enumerated Types BIT 0 1 BOOLEAN false true REAL to STD LOGIC U X 0 1 Z W L H where U means uninitialized X means unknown 0 means low T means high Z means high impedance W means weak unknown L means weak low H means weak high means don t care For XST synthesis the 0 and L values are treated identically as are 1 and H The X and values are treated as don t care The U and W values are not accepted by XST The Z value is treated as high impedance User defined enumerated type type COLOR is RED GREEN YELLOW XST User Guide www xilinx com 285 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Bit Vector Types BIT_VECTOR SID LOGIC VECTOR Unconstrained types types whose length is not defined are not accepted Integer Type INTEGER The following types are VHDL predefined types BIT BOOLEAN BIT VECTOR INTEGER REAL The following types are declared in the STD LOGIC 1164 IEEE package STD LOGIC STD LOGIC VECTOR This package is compiled in the IEEE library In order to use one of these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC 1164 a11 Overloaded Data Types 286 The following bas
185. aints apply to FPGAs CPLDs VHDL and Verilog You can set some of these options under the Synthesis Options tab of the Process Properties dialog box in Project Navigator See Constraints Summary for a complete list of constraints supported by XST e AddlI O Buffers Add IO Buffers iobuf enables or disables IO buffer insertion Allowed values are yes no By default buffer insertion is enabled XST automatically inserts Input Output Buffers into the design You can manually instantiate I O Buffers for some or all the I Os and XST will insert I O Buffers only for the remaining I Os If you do not want XST to insert any I O Buffers set this option to no This option is useful to synthesize a part of a design to be instantiated later on When the yes value is selected IBUF and OBUF primitives are generated IBUF OBUF primitives are connected to I O ports of the top level module When XST is called to synthesize an internal module which will be instantiated later in a larger design you must select no for this option If I O buffers are added to a design this design cannot be used as a submodule of another design Define this option globally with the iobuf command line option of the run command Following is the basic syntax iobuf yes no The default is yes In Project Navigator specify iobuf globally with the Add IO Buffers option in the Xilinx Specific Option tab of the Process Properties dialog box e Box Type The Box T
186. alog box within Project Navigator XOR Preserve The XOR Preserve pld xp constraint enables or disables hierarchical flattening of XOR macros Allowed values are yes check box is checked and no check box is not checked By default XOR macros are preserved check box is checked The XORs inferred by HDL synthesis are also considered as macro blocks in the CPLD flow but they are processed separately to give more flexibility for the use of device macrocells XOR gates Therefore you can decide to flatten its design Flatten Hierarchy yes Macro Preserve no but you want to preserve the XORs Preserving XORs has a great impact on reducing design complexity Two values are available for this option yes XOR macros are preserved no XOR macros are merged with surrounded logic Preserving the XORs generally gives better results that is the number of PTerms is lower The no value is useful to obtain completely flat netlists Sometimes applying the global optimization on a completely flat design improves the design fitting You obtain a completely flattened design when selecting the following options Flatten Hierarchy yes e Macro Preserve no XOR Preserve no The no value for this option does not guarantee the elimination of the XOR operator from the EDIF netlist During the netlist generation the netlist mapper tries to recognize and infer XOR gates in order to decrease the logic complexity This process is www xi
187. ane die ld osa eee Meal ue ea 88 Verilog Codes ii cc CA heat rx ati A Pascua s aate ected 89 4 to 1 MUX Using Case Statement 6 eee 89 AA A PR 90 Verilog Codere nieniu dd tail Es e a ich 90 4 to 1 MUX Using Tristate Buffers sicr eme cosido manosini nnn ee 91 VHDE Code sas ereeucre nets de EbLRERES LEE wkend beue sitee pops bou 91 Venlos Code source pride rel tea id tend ipee cde stet ie pes 91 Nostot MUX tigi emere rh rie a e es 91 VEDE Code ia 4 rectum eoe ted estin edem arde ea ate neice petto qus 92 XST User Guide www xilinx com 9 1 800 255 7778 XILINX Verilog Codeine AA Metres 92 Decoders ii teo Gen oat 93 Log Pile ii A E E PE ie eE eed 93 Related Constraints che ec edes eb eerte ott Re t Qoid eot e de due 93 VHDL On Hot LL hnereehebr eem x Ry ade esee a CR egre Rd Cede Ee deg 93 Menl g Ome Ob Ie er siesta que ee usce dc eoe e bd eae 94 VHDL One Cold oi cin per ERR ER rere Re RE Ce RE dU C ede 94 Verilog One Cold oes tet qe Uy er Ete ee en atico den regu sodes bag wud 95 Decoders with Unselected Outputs 066 95 VHDL Code No Decoder Inference 6 0 cece teen eens 96 Verilog Code No Decoder Inference 6 0 96 VHDL Code Decoder Inference 1 0 0 cece cette eee eens 97 Verilog Code Decoder Inference 2 6 ccc eee eens 97 Priority Encodes aerias esi eek VIE RO e cogido pe dp Aeon ein due d s 98 Eog el aa ear E 98 3 Bit 1 of 9 Priority Encoder 0 6 cence
188. aned by XST Names with Spaces Starting in release 7 1i XST supports file and directory names with spaces If a file or directory name contains spaces you must enclose this name in double quotes as in the following example C my project Due to this change the command line syntax for switches supporting multiple directories sd vlgincdir has changed If multiple directories are specified for these switches you must enclose them in braces as in the following example vlgincdir C my project C temp Note In previous releases multiple directories were included in double quotes This previous convention is still supported by XST if directory names do not contain spaces Xilinx strongly suggests that you change existing scripts to the new syntax Launching XST You can run XST in two ways e XST Shell Type xst to enter directly into an XST shell Enter your commands and execute them To run synthesis specify a complete command with all required options before running XST does not accept a mode where you can first enter set option 1 then set option 2 and then enter run All of the options must be set up at once Therefore this method is very cumbersome and Xilinx suggests that you use the script file method e Script File You can store your commands in a separate script file and run all of them at once To execute your script file run the following workstation or PC command xst ifn in fil
189. anguage Support Introduction XST User Guide This chapter explains how VHDL is supported for XST The chapter provides details on the VHDL language supported constructs and synthesis options in relationship to XST The sections in this chapter are as follows e Introduction e File Type Support e Data Types in VHDL e Record Types e Initial Values e Objects in VHDL e Operators e Entity and Architecture Descriptions e Combinatorial Circuits e Sequential Circuits e Functions and Procedures e Assert Statement e Packages e VHDL Language Support e VHDL Reserved Words For a complete specification of the VHDL hardware description language refer to the IEEE VHDL Language Reference Manual For a detailed description of supported design constraints refer to Chapter 5 Design Constraints For a description of VHDL attribute syntax see VHDL Attribute Syntax in Chapter 5 VHDL is a hardware description language that offers a broad set of constructs for describing even the most complicated logic in a compact fashion The VHDL language is designed to fill a number of requirements throughout the design process e Allows the description of the structure of a system how it is decomposed into subsystems and how those subsystems are interconnected e Allows the specification of the function of a system using familiar programming
190. as one single arithmetic operator if they are never used at the same time XST performs both resource sharing and if required reduces the number of multiplexers that are created in the process XST supports resource sharing for adders subtractors adders subtractors and multipliers If the optimization goal is SPEED then the disabling of resource sharing may lead to better results XST advises you to try to deactivate resource sharing at the Advance HDL Synthesis step in order to improve clock frequency XST User Guide www xilinx com 131 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Log File The XST log file reports the type and size of recognized arithmetic blocks and multiplexers during the Macro Recognition step Synthesizing Unit lt addsub gt Related source file is resource_sharing_1 vhd Found 8 bit addsub for signal lt res gt Found 8 1 bit 2 to 1 multiplexers Summary inferred 1 Adder Subtracter s inferred 8 Multiplexer s Unit lt addsub gt synthesized HDL Synthesis Report Macro Statistics Multiplexers 1 2 to 1 multiplexer 1 Adders Subtractors 1 8 bit addsub 1 Advanced HDL Synthesis INFO Xst HDL ADVISOR Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization For improved clock frequency you may try to disable resource sharing Related Cons
191. atch Q ooo oO o 9500x1 nn KKK KX KY Zw Hef OQ fs zZ n 20 378 www xilinx com 1 800 255 7778 XST User Guide CPLD Log File XILINX Macro Statistics Registers 8 1 bit register 8 Xors 6 1 bit xor2 6 Cell Usage BELS 390 AND2 108 AND3 8 AND4 2 INV 167 OR2 99 OR3 4 XOR2 7 FlipFlops Latches s dd FDC o3 FDCE 29 IO Buffers 27 IBUF 2 3 OBUF 24 Others sod tenths Sl CPU 3 57 4 88 s Elapsed 3 00 4 00 s Total memory usage is 87156 kilobytes Number of errors O O filtered Number of warnings 3 O filtered Number of infos O O filtered XST User Guide www xilinx com 379 1 800 255 7778 7 XILINX Chapter 9 Log File Analysis 380 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode This chapter describes how to run XST using the command line The chapter contains the following sections Introduction Introduction Launching XST Setting Up an XST Script Run Command Getting Help Set Command Elaborate Command Example 1 How to Synthesize VHDL Designs Using Command Line Mode Example 2 How to Synthesize Verilog Designs Using Command Line Mode Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode You can run synthesis with XST in command line mode instead of from the Process window in
192. ate C 0 lt CIN COUT lt C N 1 LOOP_ADD for I in 0 to N generate SUM I lt A I xor B I xor C I C I 1 lt A I and B I or A I and C I or B I and C I end generate end generate end ARCHI Combinatorial Process A process assigns values to signals differently than when using concurrent signal assignments The value assignments are made in a sequential mode The latest assignments may cancel previous ones See Example 6 9 First the signal 5 is assigned to 0 but later on for A and B 1 the value for S is changed to 1 XST User Guide www xilinx com 299 1 800 255 7778 XILINX 300 Chapter 6 VHDL Language Support Example 6 9 Assignments in a Process entity EXAMPLE is port A B in BIT S out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B begin S lt 0 if A and B 1 then S lt 1 end if end process end ARCHI A process is called combinatorial when its inferred hardware does not involve any memory elements Said differently when all assigned signals in a process are always explicitly assigned in all paths of the Process statements then the process in combinatorial A combinatorial process has a sensitivity list appearing within parentheses after the word process A process is activated if an event value change appears on one of the sensitivity list signals For a combinat
193. ation Using DSP48 Block Resources Mapping Logic onto Block RAM Flip Flop Retiming Incremental Synthesis Flow Speed Optimization Under Area Constraint Log File Analysis Implementation Constraints Virtex Primitive Support Cores Processing Specifying INITs and RLOCs in HDL Code PCI Flow XST performs the following steps during FPGA synthesis and optimization Mapping and optimization on an entity module by entity module basis Global optimization on the complete design The output of this process is an NGC file This chapter describes the following Constraints that can be applied to tune the synthesis and optimization process Macro generation Information in the log file Timing model used during the synthesis and optimization process Constraints available for timing driven synthesis Information on the generated NGC file Information on support for primitives www xilinx com 197 1 800 255 7778 XILINX Virtex Specific Synthesis Options XST supports a set of options that allows the tuning of the synthesis process according to the user constraints This section lists the options that relate to the FPGA specific optimization of the synthesis process For details about each option see FPGA Constraints non timing in Chapter 5 Following is a list of FPGA options 198 BUFGCE Buffer Type Clock Buffer Type Decoder Ext
194. ator character is then the name of the net will be INST1 TMP NET Using as a hierarchy separator is very useful in the design debugging process because this separator makes it much easier to identify a name if it is hierarchical www xilinx com XST User Guide 1 800 255 7778 General Constraints XST User Guide XILINX Define this option globally with the hierarchy_separator command line option of the run command Following is the basic syntax hierarchy separator _ The default is for newly created projects In Project Navigator specify hierarchy separator globally with the Hierarchy Separator option in the Synthesis Options tab of the Process Properties dialog box in the Project Navigator Iostandard Use the IOSTANDARD constraint to assign an I O standard to an I O primitive See TOSTANDARD in the Constraints Guide for details Keep The KEEP constraint is an advanced mapping constraint When a design is mapped some nets may be absorbed into logic blocks When a net is absorbed into a block it can no longer be seen in the physical design database This may happen for example if the components connected to each side of a net are mapped into the same logic block The net may then be absorbed into the block containing the components KEEP prevents this from happening See KEEP in the Constraints Guide for details Library Search Order The Library Search Order 1s0 command line option
195. by spaces and enclosed in braces slice packing Slice Packing yes no slice utilization ratio Slice Utilization Ratio integer Default 100 slice utilization ratio Slice Utilization Ratio Delta integer Default 5 maxmargin tristate2logic Replace Internal Tristates yes no with Logic use_clock_enable Use Clock Enable auto yes no use_sync_set Use Synchronous Set auto yes no use_sync_reset Use Synchronous Reset auto yes no write timing constraints Write Timing Constraints yes no The following options have become obsolete for the current version of XST Table 10 7 Obsolete Options Run Command Options Description Values complex clken Complex Clock Enable yes no Getting Help If you are working from the command line on a Unix system XST provides an online Help function The following information is available by typing help at the command line XST s help function can give you a list of supported families available commands switches and their values for each supported family e To get a detailed explanation of an XST command use the following syntax help arch family name command command name where e family name is a list of supported Xilinx families in the current version of XST command name is one of the following XST commands run set elaborate time 388 www xilinx com 1 800 255 7778
196. c tb vhd EA Uh facie ic u2Bfactie ic u hd ffaciic ic udi BS poj queue MEMGNON E I Module View Note To run XST from the command line refer to Chapter 10 Command Line Mode for details 26 www xilinx com XST User Guide 1 800 255 7778 XST in Project Navigator 7 XILINX 5 When synthesis is complete view the results by double clicking View Synthesis Report Following is a portion of a sample report el Xilinx Project Navigator C Temp v2_fifo_vhd_258 v2_fifo_vhd_258 ise fifoctir cc v2 syr READ ONLY E Fie Edit View Project Source Process Simulation Window Help 2 8 x ojsjujaj 2 sis pela is pel ele ole aly 9 v es gt pf Y Jal ope 410101101 six 1 Release 7 1i xst H 25 CETT 2 Copyright c 1995 2005 Xilinx Inc All rights reserved 5 v2 fifo vhd ise 3 Parameter TMPDIR set to projnav E readme 4 CPU 0 00 2 34 s Elapsed 0 00 2 00 s 3 xc2v40 4g256 5 EI teeth ee anh floc 6 Parameter xsthdpdir set to xst cotb cc arch fifoctk cc tb vhd 7 CPU 0 00 2 34 s Elapsed 0 00 2 00 s IL fifoctlr ic v24ifoctlr ic v2 hdl ffifoctlr ic v2 vhd 8 ld tb ictb ic arch fifoctir_ic_tb vhd 9 Reading design fifoctlr cc v2 prj TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilatio
197. cally chosen Use the MULT_STYLE constraint to force CSD implementation Note XST does not support KCM or CSD implementation for signed numbers Limitations If the either of the arguments is larger than 32 bits XST does not use KCM or CSD implementation even if it is specified with the MULT STYLE constraint www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations Log File XILINX The XST log file reports the type and size of recognized multipliers during the Macro Recognition step Synthesizing Unit lt mult gt Related source file is multipliers_1 vhd Found 8x4 bit multiplier for signal lt res gt Summary inferred 1 Multiplier s Unit lt mult gt synthesized HDL Synthesis Report Macro Statistics Multipliers toli 8x4 bit multiplier i d Related Constraints Related constraints are MULT STYLE USE DSP48 and KEEP Unsigned 8x4 bit Multiplier The following table shows pin descriptions for an unsigned 8x4 bit multiplier IO pins Description A 7 0 B 3 0 MULT Operands RES 7 0 MULT Result VHDL Code Following is the VHDL code for an unsigned 8x4 bit multiplier library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity mult is por A B R El in std_logic_vector 7 downto 0 in std_logic_vector 3 downto 0 ES out std_logic_vector 11 downto 0 end mult architecture archi of mu
198. ce localparam pulldown strong while config forever macromodule pulsestyle supply0 wire _ondetect deassign fork medium pulsestyle supply1 wor _onevent default function module rcmos table xnor defparam generate nand real task xor design genvar negedge realtime time disable highz0 nmos reg tran edge highz1 nor release tranif0 else if noshow repeat tranif1 cancelled These keywords are reserved by Verilog but not supported by XST www xilinx com XST User Guide 1 800 255 7778 Verilog 2001 Support in XST XILINX Verilog 2001 Support in XST XST 6 1i supports the following Verilog 2001 features For details on Verilog 2001 see Verilog 2001 A Guide to the New Features by Stuart Sutherland or IEEE Standard Verilog Hardware Description Language manual IEEE Standard 1364 2001 XST User Guide Generate statements Combined port data type declarations ANSI style port lists Module parameter port lists ANSIC style task function declarations Comma separated sensitivity list Combinatorial logic sensitivity Default nets with continuous assigns Disable default net declarations Indexed vector part selects Multi dimensional arrays Arrays of net and real data types Array bit and part selects Signed reg net and port declarations Signed based integer numbers Signed arithmetic expressions Arithmetic shift operators Automatic width extension past 32 bits Power operator N sized parameters Explicit in line pa
199. celldefine 350 endif 350 ent 385 entity declaration 292 entity header 314 entity name 385 enum 279 enum encoding 253 268 enumerated encoding 253 enumerated types 285 286 enumeration types 315 equivalent register removal 240 241 253 386 387 equivalent register removal 253 268 386 387 event or 327 F file 351 file declaration 316 file read 284 file type support 284 file types 381 final report 364 finite state machine 182 flatten hierarchy 261 262 flip flop optimization 386 Flip flop with positive edge clock 42 for statement 349 forever statement 349 fork join statement 349 format 391 FPGA constraints 254 HDL options 254 log file 366 target options 387 from to 266 FSM 182 FSM encoding algorithm 238 239 253 FSM flip flop type 253 FSM style 238 255 385 fsm encoding 253 269 385 fsm extract 253 269 385 fsm style 194 255 269 385 full case 86 247 full case 247 269 279 function 308 350 G gate level primitive 351 general constraints 246 generate case 340 generate for 340 generate if else 340 generate RTL schematic 237 248 384 generate statement 339 generic parameter declaration 295 generic attribute conflicts 296 glob opt 263 264 387 global constraints and options 234 global optimization goal 237 263 264 387 global options 384 globalreset 289 global timing constraints 263 H HDL analysis 363 compilation 363 constraints 253 options 238 synthesis
200. chine en ta begin da da da da da da da da da da da da da da da da da addr begin BS DB DDB DB BB DB DB GE BB B GB DB Bp p001 p001 p111 p001 oooo 0100 b1010 p1100 0000 p1010 p0010 p1110 p0010 p0100 p1010 b1100 0000 bXXXX data XST proposes a large set of templates to describe Finite State Machines FSMs By default XST tries to distinguish FSMs from VHDL Verilog code and apply several state encoding techniques it can re encode the user s initial encoding to get better performance or less area However you can disable FSM extraction by using the F5M EXTRACT design constraint Note XST can handle only synchronous state machines 182 www xilinx com 1 800 255 7778 XST User Guide State Machine XILINX There are many ways to describe FSMs A traditional FSM representation incorporates Mealy and Moore machines as in the following figure Please note that XST supports both of these models Output State Outputs Register Function Inputs Function Only for Mealy Machine X6993 For HDL process VHDL and always blocks Verilog are the most suitable ways for describing FSMs For description convenience Xilinx uses process to refer to both VHDL processes and Verilog always blocks You may have several processes 1 2 or 3 in your description depending upon how
201. chitecture lt hex2led_arch gt ntity lt hex2led gt analyzed Unit lt hex2led gt generated E i 66 C temp timer stopwatch vhd line 68 Generating a Black Box for component HDL Synthesis Synthesizing Unit lt smallcntr gt Related source file is C temp timer smallcntr vhd Found 4 bit up counter for signal lt qoutsig gt Summary inferred 1 Counter s Unit lt smallcntr gt synthesized 376 www xilinx com 1 800 255 7778 XST User Guide CPLD Log File 7 XILINX Synthesizing Unit lt hex2led gt Related source file is C temp timer hex2led vhd Found 16x7 bit ROM for signal lt LED gt Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt cnt60 gt Related source file is C temp timer cnt60 vhd Unit lt cnt60 gt synthesized Synthesizing Unit lt decode gt Related source file is C temp timer decode vhd Found 16x10 bit ROM for signal lt one_hot gt Summary inferred 1 ROM s Unit lt decode gt synthesized Synthesizing Unit lt statmach gt Related source file is C temp timer statmach vhd Found finite state machine lt FSM_0 gt for signal lt current_state gt States 6 Transitions 11 Inputs dl Outputs 2 Clock CLK rising_edge Reset RESET positive Reset type asynchronous Reset State clear Power Up State clear Encoding automatic Implementation automatic Summary
202. chniques architecture syn of ramrst is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal ram ram_type begin process clk begin if clk event and clk 1 then if en 1 then optional enable if we 1 then writ nabl ram conv integer addr lt di end if if rst 1 then optional reset do lt others gt 0 else do lt ram conv integer addr end if end if end if end process end syn Verilog Code Following is the Verilog code for a read first RAM with reset module raminfr clk en we rst addr di do input clk input en input we input rst input 4 0 addr input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if en optional enable begin if we write enable ram addr lt di if rst optional reset do lt reset_value else do lt ram addr end end endmodule 170 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Block RAM with Optional Output Registers For Virtex 4 devices XST supports block RAMs with optional output registers on the data outputs VHDL Code Following is the VHDL code for a Block Ram with optional output registers library IEEE library IEEE use IEEE STD_LOGIC_1164 ALL use IEEE STD_LOGIC_UNSIGNED ALL entity raminfr is port clk1 clk2 amp in std logic we e
203. clk 1 then if we 1 then RAM conv_integer a lt di end if end if end process do lt RAM conv_integer a end syn Verilog Code Following is the Verilog code for a single port RAM with asynchronous read module raminfr clk we a di do input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 always posedge clk begin if we ram a lt di end assign do ram a endmodule 142 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Single Port RAM with False Synchronous Read The following descriptions do not implement true synchronous read access as defined by the Virtex block RAM specification where the read address is registered They are only mappable onto distributed RAM with an additional buffer on the data output as shown below Distributed DO X8977 The following table shows pin descriptions for a single port RAM with false synchronous read 10 Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output VHDL Following is the VHDL code for a single port RAM with false synchronous read library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic a in std_logic_vector 4 downto 0 di in s
204. cocccccnonorrrrcna o 55 bAsip a cT 55 Verilog Codes ied ope eer characte ct tor dese P bee acne eed ee Phra dS I eret PRI UE i 55 ocn A eti Ei T a E E A ER 56 op E E ee Se A ene ea A 56 Related Coristraints 15 00 csdss ere bs ee c Te EE ER RE 56 4 bit Unsigned Up Counter with Asynchronous Clear oooooococcoccccco 57 VHDL Code iier ERR ER REC a E E CHPREV ER E EN 57 Verilog Codersi i ics a IW I eS A Ee Ie ieee ee 57 4 bit Unsigned Down Counter with Synchronous Set 066 e cece eee eee 58 VHDL Code saskee ARR RR E a e a deta obec RP RES 58 Verilog Codecs soto aac aia pd it aio ems 59 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input 59 VHDL Code sesion e Bes 59 Verilog Codesisrnaidd rias rai ta sad 60 4 bit Unsigned Up Counter with Synchronous Load with a Constant 60 VHDL Code coso gu sciences 61 Verilog Codes a A A be AA E ES 61 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable 62 VHDL Code sii A RARA RR 62 Verilog Code is vss ceti ps pu NE ate vex vro e gu reve vs 63 4 bit Unsigned Up Down counter with Asynchronous Clear 63 VHDL Codes isi tae ro sted rahe cred creas A EEG REY 63 Verilog Codes ida cita id is id d pu e et etd 64 4 bit Signed Up Counter with Asynchronous Reset ooooocccoccccccccc 64 VHDL Code sieci a gels SA PRE A EIE A Re A Fas 65 Venlog Code ics rescata cried en beme Eee e sve Dead aaa 65 4 bit
205. cord e Record types can contain other record types e Constants can be record types e Record types cannot contain attributes e XST supports aggregate assignments to record signals 288 www xilinx com XST User Guide 1 800 255 7778 Initial Values XILINX Initial Values In VHDL you can initialize registers when you declare them The value e Must be a constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to a register When you give a register an initial value in a declaration XST sets this value on the output of the register at global reset or at power up A value assigned this way is carried in the NGC file as an INIT attribute on the register and is independent of any local reset Example signal arb onebit std logic 0 signal arb priority std logic vector 3 downto 0 1011 You can also assign a set reset value to a register via your behavioral VHDL code Do this by assigning a value to a register when the register s reset line goes to the appropriate value as in the following example Example process clk rst begin if rst 1 then arb onebit lt 0 end if end process When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip flop whose output can be controlled by a local reset as such it is carried in the NGC file as an FDP or FDC flip flop Local Reset
206. ction or 326 reduction xnor 327 reduction xor 326 register 348 flip flop with positive edge clock 42 register balancing 240 258 387 register duplication 240 258 388 register power up 253 register balancing 258 271 387 register duplication 258 271 388 register powerup 253 271 registered multiplier 113 Registers 41 registers 41 4 bit register with positive edge clock asynchronous set and clock enable 47 DFF with positive edge clock 42 flip flop with positive edge clock and clock enable 46 flip flop with positive edge clock and synchronous set 44 relational 326 repeat statement 349 resetall 350 resolution functions 308 resource sharing 131 239 253 386 resource sharing 253 271 386 resource sharing directives 279 resynthesize 255 271 return_port_name 279 right shift 327 right shift signed 327 rloc 249 ROM extract 386 extraction 238 258 implementation 178 style 238 258 386 rom_extract 258 271 386 rom_style 178 258 271 386 rtlview 248 384 run command 383 S safe implementation 238 239 254 386 safe_implementation 254 386 safe_recovery_state 254 272 script file 382 sd 255 388 selected names 317 sequential block 349 sequential circuits 304 sequential process with a sensitivity list 304 sequential process without a sensitivity list 304 set command 390 set command options 390 set_dont_touch 279 set_dont_touch_network 279 set_dont_use_cel_name 279 set_prefer 279 shift regi
207. ctor 12 downto 0 A B in std logic vector 4 downto 0 S out std logic vector 16 downto 0 end top architecture bhv of top is component addern generic width integer 8 port A B in std logic vector width 1 downto 0 Y out std logic vector width 1 downto 0 end component for all addern use entity work addern bhv signal Cl std logic vector 12 downto 0 signal C2 C3 std logic vector 16 downto 0 begin Ul addern generic map n gt 13 port map X Y C1 C2 lt Cl amp A C3 lt Z B U2 addern generic map n gt 17 port map C2 C3 S end bhv Generic Attribute Conflicts Since generics and attributes can be applied to both instances and components in your VHDL code and attributes can also be specified in a constraints file from time to time conflicts will arise To resolve these conflicts XST uses the following rules of precedence 1 Whatever is specified on an instance lower level takes precedence over what is specified on a component higher level 296 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits XILINX 2 Ifa generic and an attribute are specified on either the same instance or the same component the generic takes precedence and XST issues a message warning of the conflict 3 An attribute specified in the XCF file will always take precedence over attributes or generics specified in your VHDL code Note When an a
208. d endmodule Considerations for Virtex 4 Devices The Virtex 4 family allows adders subtractors to be implemented on DSP48 resources XST supports the registered version of these macros and can push up to 2 levels of input registers and 1 level of output registers into DSP48 blocks If the Carry In or Add Sub operation selectors are registered XST pushes these registers into the DSP48 as well XST can implement an adder subtractor in a DSP48 block if its implementation requires only a single DSP48 resource If an accumulator macro does not fit in a single DSP48 XST implements the entire macro using slice logic Macro implementation on DSP48 blocks is controlled by the USE_DSP48 constraint command line option with a default value of auto In this mode XST implements adders subtractors using LUTs You must set the value of this constraint to yes to force XST to push these macros into a DSP48 Please note that when implementing adders subtractors on DSP48 blocks XST does not perform any automatic DSP48 resource control and as a consequence the number of generated DSP48 blocks in the NGC netlist may exceed the number of available DSP48 blocks in a target device To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible If you want to shape a macro in a specific way you must use the KEEP constraint For example if you wan
209. d a serial out library ieee use ieee std_logic_1164 all entity shift is port C SI in std_logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then for i in 0 to 6 loop tmp i 1 lt tmp i end loop tmp 0 lt SI end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock serial in and serial out module shift C SI SO input C SI output SO reg 7 0 tmp always posedge C begin tmp lt tmp lt lt 1 tmp 0 lt SI end assign SO tmp 7 endmodule XST User Guide www xilinx com 73 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out Note For this example XST infers an SRL16E_1 The following table shows pin definitions for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out 10 Pins Description C Negative Edge Clock SI Serial In CE Clock Enable active High SO Serial Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a negative edge clock a clock enable a serial in and a serial out library ieee use ieee std logic 1164 all entity shift is port C
210. d logic vector 7 downto 0 sell sel2 in std logic outmux out std logic vector 7 downto 0 end mux4 architecture behavior of mux4 is begin process a b c d sell sel2 begin if sell 1 then if sel2 1 then outmux lt a else outmux b end if else if sel2 1 then outmux lt c else outmux lt d end if end if end process end behavior Case Statement Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The Case statement evaluates the branches in the order they are written the first branch that evaluates to true is executed If none of the branches match the default branch is executed Example 6 13 shows the use of a Case statement Example 6 13 MUX Description Using the Case Statement library IEEE use IEEE std logic 1164 a11 entity mux4 is port a b c d in std logic vector 7 downto 0 sel in std logic vector 1 downto 0 outmux out std logic vector 7 downto 0 end mux4 302 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits XILINX architecture behavior of mux4 is begin process a b c d sel begin Case sel is when 00 gt outmux lt a when 01 gt outmux lt b when 10 gt outmux lt c when others gt outmux lt d case statement must be complete end Case end process end behavior For Loop
211. d synchronous set X3722 44 www xilinx com XST User Guide 1 800 255 7778 Registers XILINX The following table shows pin definitions for a flip flop with positive edge clock and synchronous set 10 Pins Description D Data Input C Positive Edge Clock S Synchronous Set active High Q Data Output VHDL Code Following is the equivalent VHDL code for the flip flop with a positive edge clock and synchronous set library ieee use ieee std logic 1164 a11 entity flop is port GC Dy S s im std logre Q out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then if S 1 then 0 e else Q lt D end if end if end process end archi Verilog Code Following is the equivalent Verilog code for the flip flop with a positive edge clock and synchronous set module flop C D S Q input C D S output Q reg Q always posedge C begin if S Q lt 1 b1 else Q lt D end endmodule XST User Guide www xilinx com 45 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Flip flop with Positive Edge Clock and Clock Enable The following figure shows a flip flop with positive edge clock and clock enable FDE X8361 The following table shows pin definitions for a flip flop with positive edge clock and clock enable 10 Pins Description D Data Input C Po
212. d then convert internally to USE_DSP48 Xilinx strongly recommends the use of the USE_DSP48 constraint for Virtex 4 designs to define FPGA resources used for multiplier implementation Xilinx recommends the use of the MULT_STYLE constraint to define the multiplier implementation method on the selected FPGA resources This means that if USE_DSP48 is set to auto or yes you may use mult_style pipe_block to pipeline the DSP48 implementation if the multiplier implementation requires multiple DSP48 blocks If USE_DSP48 is set to no you can use mult style pipe lut KCM CSD to define the multiplier implementation method on LUTs To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible If you want to shape a macro in a specific way you must use the KEEP constraint For example if you want to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers Multiplication with Constant When one of the arguments is a constant XST can create efficient dedicated implementations of a multiplier with constant There are two methods KCM and CSD Please note that dedicated implementations do not always provide the best results for multiplication with constants Starting in release 6 21 XST can automatically choose between KCM or standard multiplier implementation The CSD method cannot be automati
213. dance are not allowed Division Supported XST generates incorrect logic for the division operator between signed and unsigned constants Example 1235 3 b111 Relational gt lt gt lt Supported Logical Negation Supported Logical AND amp amp Supported Logical OR l l Supported Logical Equality Supported Logical Inequality I Supported Case Equality Supported Case Inequality l Supported Bitwise Negation Supported Bitwise AND amp Supported Bitwise Inclusive OR Supported Bitwise Exclusive OR Supported Bitwise Equivalence Supported Reduction AND amp Supported Reduction NAND amp Supported Reduction OR l Supported Reduction NOR Supported Reduction XOR A Supported www xilinx com 1 800 255 7778 XST User Guide Behavioral Verilog Features XST User Guide Table 7 1 Expressions Reduction XNOR c Supported Left Shift Supported Right Shift Signed gt gt gt Supported Left Shift Signed lt lt lt Supported Right Shift gt gt Supported Conditional 2 Supported Event OR or Supported XILINX The following table lists the results of evaluating expressions using the more frequently used operators supported by XST Note The and are special comparison operators useful in simulations to check if a variable is assigned a value of x or z They are treated as or in synthesis
214. de 1 800 255 7778 7 XILINX Chapter 4 CPLD Optimization This chapter contains the following sections CPLD Synthesis Options Implementation Details for Macro Generation Log File Analysis Constraints Improving Results CPLD Synthesis Options This section describes the CPLD supported families and their specific options Introduction XST performs device specific synthesis for CoolRunner XPLA3 II and XC9500 XL XV families and generates an NGC file ready for the CPLD fitter The general flow of XST for CPLD synthesis is the following es eee ST SES HDL synthesis of VHDL Verilog designs Macro inference Module optimization NGC file generation Global CPLD Synthesis Options This section describes supported CPLD families and lists the XST options related only to CPLD synthesis that can only be set from the Process Properties dialog box in Project Navigator XST User Guide Families Five families are supported by XST for CPLD synthesis CoolRunner XPLA3 CoolRunner II XC9500 XC9500XL XC9500XV www xilinx com 227 1 800 255 7778 XILINX Chapter 4 CPLD Optimization The synthesis for the CoolRunner XC9500XL and XC9500XV families includes clock enable processing you can allow or invalidate the clock enable signal when invalidating it is replaced by equivalent logic Also the selection of the macros which use the clock enab
215. der Extraction PRIORITY EXTRACT constraint enables or disables priority encoder macro inference See PRIORITY EXTRACT in the Constraints Guide for details www xilinx com 257 1 800 255 7778 XILINX 258 Chapter 5 Design Constraints RAM Extraction The RAM Extraction RAM_EXTRACT constraint enables or disables RAM macro inference See RAM EXTRACT in the Constraints Guide for details RAM Style The RAM Style RAM_STYLE constraint controls whether the macrogenerator implements the inferred RAM macros as block or distributed RAM See RAM STYLE in the Constraints Guide for details Register Balancing The Register Balancing REGISTER BALANCING constraint enables flip flop retiming See REGISTER BALANCINC in the Constraints Guide for details Register Duplication The Register Duplication REGISTER DUPLICATION constraint enables or disables register replication See REGISTER DUPLICATION in the Constraints Guide for details Note Register Duplication can be applied to modules entities as well as nets signals ROM Extraction The ROM Extraction ROM EXTRACT constraint enables or disables ROM macro inference See ROM EXTRACT in the Constraints Guide for details ROM Style ROM Style ROM STYLE controls the way the macrogenerator implements the inferred ROM macros The implementation style can be manually forced to use block ROM or distributed ROM resources available in Virtex series Spartan II and
216. ders subtractors on DSP48 resources in auto mode To push adder subtractors into a DSP48 set the USE_DSP48 constraint command line option value to yes XST performs automatic resource control in auto mode for multipliers and accumulators using the following general method e First XST implements all possible multiply adder subtractors and MACs on DSP48 without using DSP48 resource control e Next XST uses the remainder of DSP48 resources to implement multipliers and accumulators The biggest are processed first and the smaller ones later To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible If you want to shape a macro in a specific way you must use the KEEP constraint For example if your design has a multiplier with 2 register levels on each input and you would like to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers Please refer to Chapter 2 HDL Coding Techniques for detailed information on individual macro processing If your design contains several interconnected macros where each macro can be implemented on DSP48 XST attempts to interconnect DSP48 blocks using fast BCIN BCOUT and PCIN PCOUT connections Such situations are typical in filter and complex multiplier descriptions XST User Guide www xilinx com 203 1 800 255 7778 XILINX
217. e FROM groupl TO group2 value e TNM TNM is a basic grouping constraint Use TNM Timing Name to identify the elements that make up a group which you can then use in a timing specification TNM tags specific FFS RAMs LATCHES PADS BRAMS PORTA BRAMS PORTB CPUS HSIOS and MULTS as members of a group to simplify the application of timing specifications to the group The RISING and FALLING keywords may also be used with TNMs See INM in the Constraints Guide for details XCF Syntax INST NET PIN inst net or pin name TNM predefined group identifier e TNM Net TNM NET is essentially equivalent to TNM on a net except for input pad nets Special rules apply when using TNM NET with the PERIOD constraint for Virtex Virtex E Virtex II Virtex II Pro Virtex II Pro X Virtex 4 or Spartan 3 266 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX DLL DCMs See the PERIOD Specifications on CLKDLLs and DCMs subsection of PERIOD in the Constraints Guide A TNM NET is a property that you normally use in conjunction with an HDL design to tag a specific net All downstream synchronous elements and pads tagged with the TNM NET identifier are considered a group See TNM NET in the Constraints Guide for details XCF Syntax NET netname TNM NET predefined group identifier TIMEGRP TIMEGRP is a basic grouping constraint In addition to naming groups
218. e use ieee std_logic_1164 all entity three_st is port T in std logic I in std logic O out std logic end three st architecture archi of three st is begin O lt I when T 0 Ise Z end archi Verilog Code Following is the Verilog code for a tristate element using a concurrent assignment module three_st T I O input T 1 output 0 assign O T I 1 bZ endmodule XST User Guide www xilinx com 55 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Counters XST is able to recognize counters with the following control signals e Asynchronous Set Clear e Synchronous Set Clear e Asynchronous Synchronous Load signal and or constant e Clock Enable e Modes Up Down Up Down e Mixture of all of the above HDL coding styles for the following control signals are equivalent to the ones described in Registers in this chapter e Clock e Asynchronous Set Clear e Synchronous Set Clear e Clock Enable Moreover XST supports both unsigned and signed counters Log File The XST log file reports the type and size of recognized counters during the Macro Recognition step Synthesizing Unit lt counter gt Related source file is counters l vhd Found 4 bit up counter for signal tmp Summary inferred 1 Counter s Unit counter synthesized HDL Synthesis Report Macro Statistics Counters 1 4 bit up counter c Note During synthesis XST d
219. e BUFFER_TYPE is a new name for the CLOCK_BUFFER constraint Since CLOCK_BUFFER will become obsolete in future releases Xilinx strongly suggest that you use this new name This constraint selects the type of buffer to be inserted See BUFFER_TYPE in the Constraints Guide for details e BUFGCE The BUFGCE constraint implements BUFGMUX functionality by inferring a BUFGMUX primitive This operation reduces the wiring clock and clock enable signals are driven to n sequential components by a single wire See BUFGCE in the Constraints Guide for details 254 www xilinx com XST User Guide 1 800 255 7778 FPGA Constraints non timing 7 XILINX XST User Guide Clock Buffer Type The Clock Buffer Type CLOCK_BUFFER constraint selects the type of buffer to be inserted on the net In the current release this constraint has been renamed BUFFER_TYPE Since CLOCK_BUFFER will become obsolete in future releases Xilinx strongly suggest that you use this new name See BUFFER_TYPE in the Constraints Guide for details Cores Search Directories The Cores Search Directories command line switch sd tells XST to look for cores in directories other than the default one by default XST searches for cores in the directory specified in the ifn switch Define this option globally with the sd command line option of the run command Allowed values are names of directories Please refer to Names with Spaces in Chapter 10 for more
220. e 98 Related Constraint eec neri eresian ree ea cence ene n ene n een ene 98 VHDE Code suiviaor harian raras abad erated tenes 98 Verilog Code visi a E Ra a p Pu RE e E Seed 99 Logical SBIECOIS cours ikbteko id chebdunade e kedd tacens peace a 99 Log File pr 100 Related Constraints s Views ora la Pig S Vaden Bee Ye a 100 Example eya sraa tetto EM c MM UIDI ELI 100 VADC Code verb epe ER SEE ERRARE REEL HR ERE EEG Rx 101 Verilog Code pics ett duet diae ied duced adt eese le eae pet 101 Example Z ive aeree e en Y beate eae Aoi 101 VEHDL Code s rebrica e Re deena dak ani adel UR Shen UO SEE E E Xd 102 Verilog Code is rec kv n PEG ie bine BEA LER Ri eb eum sited pipa bed 102 Example S sescca ere eae ea a deuote S d E ed 102 VHDL Code eer ae tenen eta esed es adt an ers AS ee s 103 Verilog Codere a 103 Arithmetic Operations cesses eee eekes e P e Re E de RE Wed 104 Adders Subtractors Adders Subtractors 0 0 00 cece eee 104 Log Files ies ER othe tete ede ier be web e tpe dee ee 104 Related Constraints eoe ete e br Re bade oe eR RA Reo ere e deeds 104 Unsigned 8 bit Adder cere toe e ede e e e deae 105 Unsigned 8 bit Adder with Carry In 0 0 eee eee 105 Unsigned 8 bit Adder with Carry Out csse 106 Unsigned 8 bit Adder with Carry In and Carry Out 02 0 00 00 c ee eee ee eee 108 Simple Signed 8 bit Adder 26 cee cece een 109 Unsigned 8 bit SubtractoE ead oerte v oa 109 Unsigned 8 bit Adder Subtracto
221. e A E Deren Gates DE aha Pay ales alee ease at 328 Modules ener cesar decuedanvheuwewadalnvain tds tase iun pa oa 328 Module Declaration voii ei E DLE REX CE 328 Verilog Assignments ssssssseseessese e eee 329 Continuous Assignments oooooooooocrr nen 329 Procedural Assignments lsceeselssseeee nee 329 Combinatorial Always Blocks 1 6 ccc cece nee 329 IE Else Statement a bae e E Sa PER a re xd 330 CaseStatement i c eoa dU REG Cee gd EA ERREUR Aa RR eH CR Cd 330 Forand Repeat Loops sesse tosiaankin kii e ved cede RIEN HOPES PER opere 331 While Loops rpm 332 Sequential Always BlockS oooooccoococcorcarcrca teen eee eens 332 Assign and Deassign Statements 1 0 0 0 0c cece e 334 Assignment Extension Past 32 Bits cesses ee 336 Tasks and Functions 336 Blocking Versus Non Blocking Procedural Assignments 000 000s eee 337 Constants Macros Include Files and Comments llle sn 338 Constante amasar da da edere HUS A IDE 338 MATOS o a ERG RR ID GARE CER DR RD RA ROG E ER RR ERR RE REX RU 338 Include Files 1 222 4 eh ik edie Pete b qd x due DEO Rae os 338 COMIMENKS bs 6s uode yx d eee eee LRA XA A REG UR E ERE RESTER des 339 Generate Statement 339 Generate FOf is2 3aues a RRS G rre RE RR eed 340 Generate If else tive teret a ye ON GS GES x ae ad pio uds 340 Generate Cases iss sea gu ey a REG RE AA A du aed 340 Variable Part Selects peo ey wid Pick A CA e De cae eei
222. e Clock we Synchronous Write Enable active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port XST User Guide www xilinx com 151 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for a dual port RAM with false synchronous read library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std logic we in std_logic a in std_logic_vector 4 downto 0 dpra in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 spo out std logic vector 3 downto 0 dpo out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if spo lt RAM conv integer a dpo lt RAM conv_integer dpra end if end process end syn Verilog Code Following is the Verilog code for a dual port RAM with false synchronous read module raminfr clk we a dpra di spo dpo input clk input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 reg 3 0 spo reg 3 0 dpo always posedge clk begin if we ram a lt di spo ramla dpo ra
223. e Verilog Designs Using Command Line DOT AA 394 Example Ls Gee diy tuo ee qe mA RU NR tud E REEL cosets RR rado pinta 394 Script Modes eie ed ERI e des Ee bap kiere C edid RAE eR Eo ids 395 XST User Guide www xilinx com 17 1 800 255 7778 XILINX Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode 396 Script Mode iere id dp He eae e dia 397 Appendix A XST Naming Conventions Net Naming Conventions sierra REA XR 4 RERI HE EAR AVE ES 399 Instance Naming Conventions cortinas 399 Name Generation Control secs s cece einer rhe 400 ll J e 401 18 www xilinx com XST User Guide 1 800 255 7778 XILINX Chapter 1 Introduction This chapter contains the following sections Architecture Support XST Flow Architecture Support The software supports the following architecture families in this release XST Flow Virtex E II II Pro II Pro X 4 Spartan II IIE 3 CoolRunner XPLA3 II XC9500 XL XV XST is a Xilinx tool that synthesizes HDL designs to create Xilinx specific netlist files called NGC files The NGC file is a netlist that contains both logical design data and constraints that takes the place of both EDIF and NCF files This manual describes XST support for Xilinx devices HDL languages and design constraints The manual also explains how to use various design optimizat
224. e name ofn out file name intstyle silent ise xflow Note The ofn option is not mandatory If you omit it XST automatically generates a log file with the file extension srp and all messages display on the screen Use the intstyle silent option and the XIL XST HIDEMESSAGES environment variable to limit the number of messages printed to the screen See the Reducing the Size of the LOG File in Chapter 9 for more information 382 www xilinx com XST User Guide 1 800 255 7778 Setting Up an XST Script XILINX For example assume that the text below is contained in a file foo scr run ifn ttl prj top ttl ifmt MIXED opt mode SPEED opt level 1 ofn ttl ngc p lt parttype gt This script file can be executed under XST using the following command xst ifn foo scr You can also generate a log file with the following command xst ifn foo scr ofn foo log A script file can be run either using xst ifn script name or executed under the XST prompt by using the script script name command script foo scr If you make a mistake in an XST command command option or its value XST issues an error message and stops execution For example if in the previous script example VHDL is incorrectly spelled VHDLL XST gives the following error message ERROR Xst 1361 Syntax error in command run for option ifmt parameter VHDLL is not allowed Setting Up an XST Script An XST script is a set of co
225. e the following one ERROR Xst 1363 Option verilog2002 is not available for command run Custom Compile File List By using the Custom Compile File List property you can change the order in which source files are processed by XST With this property you select a user defined compile list file that XST uses to determine the order in which it processes libraries and design files Otherwise XST uses an automatically generated list This user defined file must list all design files and their libraries in the order in which they are to be compiled from top to bottom Type each file library pair on its own line with a semicolon separating the library from the file The format is as follows library name file name library name file name Following is an example work stopwatch vhd work statmach vhd Note This property is not connected to the Custom Compile File List property in the Simulation Properties dialog box which means that a different compile list file is used for synthesis than for simulation VHDL Attribute Syntax You can describe constraints with VHDL attributes in your VHDL code Before it can be used an attribute must be declared with the following syntax attribute AttributeName Type Example attribute RLOC string The attribute type defines the type of the attribute value The only allowed type for XST is string An attribute can be declared in an entity or architecture If declared in the ent
226. e we use the new project format To create a project file containing only VHDL files place a list of VHDL files preceded by keyword VHDL in a separate file The order of the files is not important XST can recognize the hierarchy and compile VHDL files in the correct order For the example perform the following steps 1 Openanew file called watchvhd prj 2 Enter the names of the VHDL files in any order into this file and save the file vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd vhdl work hex2led vhd 3 To synthesize the design execute the following command from XST shell or via script file run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Note It is mandatory to specify a top level design block via the top command line switch If you want to synthesize just hex2led and check its performance independently of the other blocks you can specify the top level entity to synthesize in the command line using the top option please refer to Table 10 2 page 385 for more details run ifn watchvhd prj ifmt mixed ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 top hex2led 392 www xilinx com XST User Guide 1 800 255 7778 Example 1 How to Synthesize VHDL Designs Using Command Line Mode 7 XILINX During VHDL comp
227. ea Primary Synchronous Write Enable Active High addra Write Address Primary Read Address addrb Dual Read Address dia Primary Data Input doa Primary Output Port dob Dual Output Port VHDL Code Following is the VHDL code for a dual port RAM with different clocks library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clka in std_logic clkb in std_logic wea in std_logic addra in std logic vector 4 downto 0 addrb in std_logic_vector 4 downto 0 dia in std_logic_vector 3 downto 0 doa out std_logic_vector 3 downto 0 dob out std_logic_vector 3 downto 0 end raminfr architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_addra std_logic_vector 4 downto 0 signal read_addrb std_logic_vector 4 downto 0 begin process clka begin if clka event and clka 1 then if wea 1 then RAM conv_integer addra lt dia end if read_addra lt addra end if end process 162 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX process clkb begin if clkb event and clkb 1 then read_addrb lt addrb end if end process doa lt RAM read addra dob lt RAM read_addrb end syn Verilog Code Following is the Verilog code for a dual port RAM with different clocks module raminfr clka clkb wea addra addrb
228. ecomposes Counters on Adders and Registers if they do not contain synchronous load signals This is done to create additional opportunities for timing optimization Because of this counters reported during the Macro Recognition step and in the overall statistics of recognized macros may not appear in the final report Adders registers are reported instead Related Constraints There are no related constraints available 56 www xilinx com XST User Guide 1 800 255 7778 Counters XILINX 4 bit Unsigned Up Counter with Asynchronous Clear The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous clear 10 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 3 0 Data Output VHDL Code Following is VHDL code for a 4 bit unsigned up counter with an asynchronous clear library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C CLR in std logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with asynchronous clear module counter C CLR Q input C CLR output 3 0 Q reg
229. ector values are presented 10 pins Description D 7 0 Data Input SEL Shift Distance Selector SO 7 0 Data Output XST User Guide www xilinx com 101 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee numeric_std all entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 2 when others end archi Verilog Code Following is the Verilog code module lshift DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 default SO DI lt lt 2 endcase end endmodule Example 3 XST does not infer a logical shifter for this example as the value is not incremented by 1 for each consequent binary value of the selector 10 pins Description D 7 0 Data Input SEL shift distance selector SO 7 0 Data Output 102 www xilinx com XST User Guide 1 800 255 7778 Logical Shifters XILINX VHDL Code Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee numeric_std all entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downt
230. eg 3 0 state These parameters can be modified to represent different state encoding schemes Next State Equations Next state equations can be described directly in the sequential process or in a distinct combinational process The simplest template is based on a Case statement If using a separate combinational process its sensitivity list should contain the state signal and all FSM inputs Unreachable States XST can detect unreachable states in an FSM It lists them in the log file in the HDL Synthesis step FSM Outputs Non registered outputs are described either in the combinational process or in concurrent assignments Registered outputs must be assigned within the sequential process FSM Inputs Registered inputs are described using internal signals which are assigned in the sequential process 190 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX State Encoding Techniques XST User Guide XST supports the following state encoding techniques e Auto e One Hot e Gray e Compact e Johnson e Sequential e User e Speed1 Auto In this mode XST tries to select the best suited encoding algorithm for each FSM One Hot One hot encoding is the default encoding scheme Its principle is to associate one code bit and also one flip flop to each state At a given clock cycle during operation one and only one bit of the state variable is asserted Only two bits toggle during a transition be
231. eger i XST User Guide www xilinx com 331 1 800 255 7778 XILINX 332 Chapter 7 Verilog Language Support always a begin Count Aux 3 b0 for i 0 i lt 8 i 1 1 begin if a i Count Aux Count_Aux 1 end Count Count_Aux end endmodule While Loops When using always blocks use the while statement to execute repetitive procedures A while loop executes other statements until its test expression becomes false It is not executed if the test expression is initially false e The test expression is any valid Verilog expression e To prevent endless loops use the loop_iteration_limit switch e While loops can have Disable statements The Disable statement must be use inside a labeled block since the syntax is disable lt blockname gt The following example shows the use of a While Loop Example 7 5 While Loop Description parameter P 4 always ID_complete begin UNIDENTIFIED integer i reg found unidentified 0 i 0 found 0 while found amp amp i lt P begin found ID complete i unidentified i ID complete i i i 1 end end Sequential Always Blocks Sequential circuit description is based on always blocks with a sensitivity list The sensitivity list contains a maximum of three edge triggered events the clock signal event which is mandatory possibly a reset signal event and a set signal event One and only one If else s
232. en sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 110 and 111 selector values are unused XXXXXXXX end archi Verilog Code Decoder Inference The following Verilog code leads to the inference of a 1 of 8 decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always ft sel or res begin case sel 3 b000 res 8 b00000001 3 b001 res 8 b00000010 3 b010 res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100000 110 and 111 selector values are unused default res 8 bXxxxxxxxx endcase end endmodule XST User Guide www xilinx com 97 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Priority Encoders Log File XST can recognize a priority encoder but in most cases XST does not infer it To force priority encoder inference use the PRIORITY_EXTRACT constraint with the value force Xilinx strongly suggests that you use this constraint on a signal by signal basis otherwise the constraint may guide you towards sub optimal results The XST log file reports the type and size of recognized priority encoders during the Macro Recognition step Synthesizing Unit lt priority gt Related source file is priority_encoders_1 vhd Found 3 bit 1 of 9 priority encoder for signal lt code gt Summary inferred 3 Priority encoder s Unit lt priority gt synthesized HDL Synthesis
233. eneration Control in Appendix A The default value for the Hierarchy Separator command line option HIERARCHY SEPARATOR for newly created projects in ISE Synthesis Properties is now See Hierarchy Separator and Constraints Summary in Chapter 5 Introduced new Use Clock Enable USE CLOCK ENABLE Use Synchronous Set USE SYNC SET and Use Synchronous Reset USE SYNC RESET constraints to www xilinx com 21 1 800 255 7778 XILINX FPGA Flow Log File Chapter 1 Introduction prevent the usage in the final netlist flip flops with clock enable synchronous set and synchronous reset See Use Clock Enable Use Synchronous Set Use Synchronous Reset and Constraints Summary in Chapter 5 Support for Period constraint on internal clocks Improved automatic support for third party constraints Synplicity See Third Party Constraints in Chapter 5 Introduced new Enable Automatic Floorplanning command line switch ENABLE_AUTO_FLOORPLANNING that affects Incremental Synthesis flow See Enable Auto Floorplanning in Chapter 5 New syntax for switches supporting multiple directories This change is related to the support of file and directory names with spaces See Names with Spaces in Chapter 10 Support for automatic inference of BUFGs and BUFRs on most critical internal clocks controlled by BUFFER TYPE constraint Improved support for Incremental Synthesis INCREMTENAL SYNT
234. erarchy yes soft no Macro Preserve yes no XOR Preserve yes no Design Statistics NGC Instances nb_of_instances I Os nb_of_io_ports XST User Guide www xilinx com 229 1 800 255 7778 XILINX Chapter 4 CPLD Optimization Macro Statistics n bit up FSMs nb_of_FSMs Registers nb_of_registers Tristates nb_of_tristates Comparators nb_of_comparators n bit comparator equal not equal greater less greatequal lessequal nb_of_n_bit_comparators Multiplexers nb_of_multiplexers n bit m to 1 multiplexer nb of n bit m to 1 multiplexers Adders Subtractors nb of adds subs n bit adder nb of n bit adds n bit subtractor nb of n bit subs Multipliers nb of multipliers Logic Shifters nb of logic shifters Counters nb of counters down updown counter nb of n bit counters 11 XORs nb_of_xors Usage BELS nb_of_bels AND nb_of_and OR aad no loft Or INV nb of inv XOR2 nb of xor2 GND nb of gnd VCC nb of vcc FlipFlops Latches nb of ff latch ED LB Tri States BUFE BUFT IO Buffers IBUF OBUF IOBUF OBUFE OBUFT Others nb_ nb_of_fd nb_of_ld nb_of_tristates nb_of_bufe nb of buft nb of iobuffers nb of ibuf nb of obuf nb of iobuf nb of obufe nb of obuft of others 230 www xilinx com XST User Guide 1 800 255 7778 Constraints XILINX Constraints
235. ere on a disk by Selecting the VHDL INI File menu in the Synthesis Options tab of the Synthesis process properties in Project Navigator or Setting up the xsthdpini parameter using the following command in stand alone mode set xsthdpini file name You can give this library mapping file any name you wish but it is best to keep the ini classification The format is library name path to compiled directory Note Use for comments Sample text for my ini workl H NUsersNconfWny lib Nworkl work2 C mylib work2 www xilinx com 251 1 800 255 7778 XILINX 252 Chapter 5 Design Constraints Work Directory The Work Directory xsthdpdir parameter defines the location in which VHDL compiled files must be placed if the location is not defined by library mapping files You can access this switch by Selecting the VHDL Working Directory menu in the Synthesis Options tab of the Synthesis process properties in Project Navigator or Using the following command in stand alone mode set xsthdpdir file name Example Suppose three different users are working on the same project They must share one standard pre compiled library shlib This library contains specific macro blocks for their project Each user also maintains a local work library but User 3 places it outside the project directory i e in c temp Users 1 and 2 will share another library lib12 between them but not wit
236. erent Clocks e Dual Port Block RAM with two write ports e Multiple Port RAM Descriptions e Block RAM with Reset e Initializing Block RAM e ROMs Using Block RAM Resources www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs Log File XILINX If a given template can be implemented using Block and Distributed RAM XST implements BLOCK ones You can use the RAM_STYLE constraint to control RAM implementation and select a desirable RAM type Please refer to Chapter 5 Design Constraints for more details Please note that the following features specifically available with block RAM are not yet supported e Dual write port e Parity bits except Virtex 4 devices e Different aspect ratios on each port Please refer to Chapter 3 FPGA Optimization for more details on RAM implementation Note Note that XST can implement State Machines see State Machine and map general logic see Mapping Logic onto Block RAM in Chapter 3 on block RAMs The XST log file reports the type and size of recognized RAM as well as complete information on its I O ports during the Macro Recognition step Synthesizing Unit lt raminfr gt Related source file is rams_1 vhd Found 128 bit single port distributed RAM for signal ram aspect ratio 32 word x 4 bit clock connected to signal clk rise write enable connected to signal we high address connected to signal a data in connec
237. erilog code for passing an INIT value via the parameters mechanism module vlut2_parameter 10 11 0 input 10 11 output 0 LUT2 4 h2 endmodule inst I0 10 11 11 0 0 Following is the Verilog code for passing an INIT value via the defparam mechanism module vlut2_defparam 10 11 0 input 10 11 output O LUT2 inst IO IO 11 11 0 0 5 defparam inst INIT 4 h2 endmodule 220 www xilinx com XST User Guide 1 800 255 7778 Cores Processing XILINX Log File XST does not issue any message concerning instantiation of Virtex primitives during HDL synthesis because the BOX_TYPE attribute with its value primitive is attached to each primitive in the UNISIM library Please note that if you instantiate a block non primitive in your design and the block has no contents no logic description or the block has a logic description but you attach a BOX_TYPE constraint to it with a value of user_black_box XST issues a warning message as in the following log file sample Analyzing Entity lt black_b gt Architecture lt archi gt WARNING VHDL 0103 c jm des vhd Line 23 Generating a Black Box for component my block Entity black b analyzed Unit black b generated Related Constraints Related constraints are BOX TYPE and the various PAR constraints that can be passed from HDL to NGC without processing Cores Processing If a design contains c
238. escription Values Options ent Entity Name name Note Valid only when old VHDL project format is used ifmt VHDL Please use project format ifmt mixed and top switch to specify which top level block to synthesize arch Architecture name Table 10 3 Verilog Source Options Run command Description Values Options top Top Module Name name Note Not Valid when old VHDL Project format is used ifmt VHDL vlgcase Case Implementation Style full parallel full parallel vlgincdir Verilog Include Directories Any valid path to directories separated by spaces and enclosed in braces verilog2001 Verilog 2001 yes no Table 10 4 HDL Synthesis Options VHDL and Verilog Run Command Description Values Options fsm extract Automatic FSM Extraction yes no fsm style FSM Style lut bram fsm encoding Encoding Algorithm auto one hot compact sequential gray johnson user XST User Guide www xilinx com 385 1 800 255 7778 XILINX 386 Chapter 10 Command Line Mode Table 10 4 HDL Synthesis Options VHDL and Verilog Run Command Options Description Values ram_extract RAM Extract yes no ram style RAM Style auto distributed block rom extract ROM Extract yes no rom style ROM Style auto distributed block mult style Multiplier Style auto block lut pipe lut mux extract Mux Extraction yes no force m
239. eset library ieee use ieee std_logic_1164 all entity latch is port D in std_logic_vector 3 downto 0 G PRE in std_logic Q out std logic vector 3 downto 0 end latch architecture archi of latch is begin process PRE G begin if PRE 1 then Q lt 1111 elsif G 0 then Q lt D end if end process end archi 52 www xilinx com XST User Guide 1 800 255 7778 Tristates XILINX Verilog Code Following is the equivalent Verilog code for a 4 bit latch with an inverted gate and an asynchronous preset module latch G D PRE 0 input G PRE input 3 0 D output 3 0 Q reg 3 0 Q always G or D or PRE begin if PRE Q lt 4 b1111 else if G Q lt D Al end endmodule Tristates Tristate elements can be described using the following e Combinatorial process VHDL and always block Verilog e Concurrent assignment Log File The XST log reports the type and size of recognized tristates during the Macro Recognition step Synthesizing Unit lt three_st gt Related source file is tristates l vhd Found 1 bit tristate buffer for signal o Summary inferred 1 Tristate s Unit three st synthesized HDL Synthesis Report Macro Statistics Tristates zi 1 bit tristate buffer ecd Related Constraints A related constraint is TRISTATE2LOGIC XST User Guide www xilinx com 53 1 800 255 7778 7 XILINX
240. esis Report Macro Statistics FSMs oL Registers gt l bit register L XST User Guide www xilinx com 193 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques RAM based FSM Synthesis Large FSMs can be made more compact and faster by implementing them in the block RAM resources provided in Virtex and later technologies You can direct XST to use block RAM resources for FSMs by using the FSM_STYLE constraint Values for FSM_STYLE are lut and bram The lut option is the default and it causes XST to map the FSM using LUTs The bram option directs XST to map the FSM onto block RAM In Project Navigator invoke this constraint by choosing either LUT or Bram from the drop down list to the right of FSM Style under the HDL Options tab of the Process Properties dialog box From the command line use the fsm_style command line switch You can also use the FSM_STYLE constraint in your HDL code See the Constraints Guide for more information If it cannot implement a state machine on block RAM XST e generates a warning message with the reason for the warning in the Advanced HDL Synthesis step of the log file e automatically implements the state machine using LUTs For example if FSM has a asynchronous reset it cannot be implemented using block RAM In this case XST informs the user Advanced HDL Synthesis E WARNING Xst Unable to fit FSM FSM 0 in BRAM reset is asynchronous Se
241. f full is used XST considers that Case statements are complete and avoids latch creation If parallel is used XST considers that the branches cannot occur in parallel and does not use a priority encoder If full parallel is used XST considers that Case statements are complete and that the branches cannot occur in parallel therefore saving latches and priority encoders The following table indicates the resources used to synthesize the three examples above using the four Case Implementation Styles The term resources means the functionality For example if you code the Case statement neither full nor parallel with Case Implementation Style set to none from the functionality point of view XST implements a priority encoder latch But it does not inevitably mean that XST infers the priority encoder during the Macro Recognition step Case Implementation Parameter Value Full Not Full Neither Full nor Parallel none MUX Latch Priority Encoder Latch parallel MUX Latch Latch full MUX MUX Priority Encoder full parallel MUX MUX MUX www xilinx com 87 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Note Specifying full parallel or full parallel may result in an implementation with a behavior that may differ from the behavior of the initial model Log File The XST log file reports the type and size of recognized MUXs during the Macro Recognition step Synthesizing Unit lt mux gt
242. fied order assuming that a VHDL design unit was stored with extended identifier See Library Search Order File for search order details If found XST binds the name XST selects the first VHDL entity matching the name and binds it XST has the following limitations when instantiating a VHDL design unit from a Verilog module e Explicit port association must be used That is formal and effective port names must be specified in the port map e All parameters must be passed at instantiation even if they are unchanged e The parameter override shall be named and not ordered The parameter override must be done though instantiation and not through defparams The following is an example of the correct use of parameter override ff init 2 b01 ul sel sel din din dout dout The following is an incorrect use of the of parameter override and is not accepted by XST ff ul sel sel din din dout dout defparam ul init 2 b01 www xilinx com 357 1 800 255 7778 XILINX Port Mapping Chapter 8 Mixed Language Support XST uses the following rules and limitations for port mapping in mixed language projects For VHDL entities instantiated in Verilog designs XST supports the following port types in out inout Note XST does not support VHDL buffer and linkage ports For Verilog modules instantiated in VHDL designs XST supports the following port types input output inout
243. from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB IOB n QOUT CLKIN Name Name N Horizontal ellipsis Repetitive material that has allow block block_name Online Document XST User Guide been omitted loci loc2 locn The following conventions are used in this document Convention Meaning or Use Example Cross reference link to a See the section Additional location in the current file or Resources for details Blue text io in another file in the current Refer to Title Formats in document Chapter 1 for details Cross reference link to a See Figure 2 5 in the Virtex Red text location in another document II Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files www xilinx com 1 800 255 7778 7 XILINX Preface About This Guide 6 www xilinx com XST User Guide 1 800 255 7778 Table of Contents Preface About This Guide Guide Contents uses eR e 3 Additional Resources cece cc ccc RR ee 4 Conventions esee rs 4 Typographical etss eeren bee A eek eese ees 4 Online Doc dadas 5 Chapter 1 Introduction Architecture SU
244. g File The XST log file related to FPGA optimization contains the following sections Copyright Statement Table of Contents Use this section to quickly navigate to different LOG file sections Note These headings are not linked Use the Find function in your text editor to navigate Synthesis Options Summary HDL Compilation See HDL Analysis below HDL Analysis During HDL Compilation and HDL Analysis XST parses and analyzes VHDL Verilog files and gives the names of the libraries into which they are compiled During this step XST may report potential mismatches between synthesis and simulation results potential multi sources and other issues HDL Synthesis During this step XST tries to recognize as many macros as possible to create a technology specific implementation This is done on a block by block basis At the end of this step XST gives an HDL Synthesis Report See Chapter 2 HDL Coding Techniques for more details about the processing of each macro and the corresponding messages issued during the synthesis process Advanced HDL Synthesis contains HDL Synthesis Report During this step XST performs advanced macro recognition and inference In this step XST recognizes dynamic shift registers implements pipelined multipliers codes state machines etc This report contains a summary of recognized macros in the overall design sorted by macro type www xilinx com 363 1 800 255 7778 XILINX C
245. gnizes the set command This command accepts the options shown in the following table Note See Chapter 5 Design Constraints for more information about the options listed in this table Table 10 8 Set Command Options set oma Description Values Options tmpdir Location of all temporary files Any valid path to a directory generated by XST during a session dumpdir Location of all files resulting Any valid path to a directory from VHDL compilation xsthdpdir Work Directory location of Any valid path to a directory all files resulting from VHDL Verilog compilation xsthdpini HDL Library Mapping File file_name INI File 390 www xilinx com XST User Guide 1 800 255 7778 Elaborate Command XILINX Elaborate Command The goal of this command is to pre compile VHDL Verilog files in a specific library or to verify Verilog files without synthesizing the design Taking into account that the compilation process is included in the run this command remains optional The elaborate command accepts the options shown in the following table Note See Chapter 5 Design Constraints for more information about the options listed in this table Table 10 9 Elaborate Command Options Flaborate Description Values Command Options ifn Project File file_name ifmt Format vhdl verilog mixed lso Library Search Order file_name lso work lib Work Library for Compilation
246. gt 1 1 0 Spartan I1 T1E 3 Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II case na na na na yes upper Spartan TI TIE 3 lower VirtexTM TI II Pro maintain II Pro X E 4 XC9500 CoolRunner XPLA3 II duplication suffix na na na na yes string dstring Spartan II ME 3 Virtex TI II Pro II Pro X E 4 hierarchy_separator na na na na yes EI Spartan TI TIE 3 default is Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II iobuf na na na na yes yes no Spartan II TIE 3 Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II iuc na na na na yes yes no Spartan TI TIE 3 Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II XST User Guide www xilinx com 273 1 800 255 7778 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options Constraint Name Iso Constraint Value na XCF Constraint Syntax Target na VHDL Target na Verilog Target na Cmd Line yes Cmd Value file_name Technology Spartan I TIE 3 Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II pld_ce na na na na yes no XC9500 CoolRunner XPLA3 II pld_mp na na na na yes yes no XC9500 CoolRunner XPLA3 II pld_xp na na na na yes
247. h User 3 The settings required for the three users are as follows User 1 Mapping file schlib z sharedlibs shlib 1ib12 z userlibs lib12 User 2 Mapping file schlib z sharedlibs shlib lib12 z userlibs lib12 User 3 Mapping file schlib z sharedlibs shlib User 3 will also set XSTHDPDIR c temp Define this parameter globally with the set xsthdpdir command line option before running the run command Following is the basic syntax set xsthdpdir directory The command can accept a single path only You must specify the directory you want to use There is no default In Project Navigator specify xsthdpdir globally with the VHDL Work Directory option of the Synthesis Options tab in the Process Properties dialog box www xilinx com XST User Guide 1 800 255 7778 HDL Constraints XILINX HDL Constraints This section describes encoding and extraction constraints Most of the constraints can be set globally in the HDL Options tab of the Process Properties dialog box in Project Navigator The only constraints that cannot be set in this dialog box are Enumerated Encoding Signal Encoding and Recovery State The constraints described in this section apply to FPGAs CPLDs VHDL and Verilog Note Please note that in many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances See Table 5 1 for valid constra
248. hapter 9 Log File Analysis e Low Level Synthesis During this step XST reports the potential removal of equivalent flip flops register replication etc For more information see Log File Analysis in Chapter 3 e Final Report The Final report is different for FPGA and CPLD flows as follows FPGA and CPLD includes the output file name output format target family and cell usage FPGA only In addition to the above the report includes the following information for FPGAs Device Utilization Summary where XST estimates the number of slices gives the number of flip flops IOBs BRAMS etc This report is very close to the one produced by MAP Clock Information gives information about the number of clocks in the design how each clock is buffered and how many loads it has Timing report contains Timing Summary and Detailed Timing Report For more information see Log File Analysis in Chapter 3 Encrypted Modules if a design contains encrypted modules XST hides the information about these modules Reducing the Size of the LOG File There are several ways to reduce the size of the LOG file generated by XST They are as follows e Quiet Mode e Silent Mode e Hiding specific messages When running XST from within Project Navigator you can use a Message Filtering wizard to select specific messages to filter out of the log file See Using the Message Filters in the ISE Help for more information
249. hical names Note Timing constraints are only written to the NGC file when the Write Timing Constraints property is checked yes in the Process Properties dialog box in Project Navigator or the write timing constraints option is specified when using the command line By default they are not written to the NGC file Independent of the way timing constraints are specified there are three additional options that affect timing constraint processing XST User Guide Cross Clock Analysis The Cross Clock Analysis command cross clock analysis allows inter clock domain analysis during timing optimization By default ro XST does not perform this analysis Define this option globally with the cross clock analysis command line option of the run command Following is the basic syntax cross clock analysis yes no The default is no In Project Navigator specify this option globally with the Cross Clock Analysis option in the Synthesis Options tab of the Process Properties dialog box www xilinx com 263 1 800 255 7778 XILINX Chapter 5 Design Constraints Write Timing Constraints The Write Timing Constraints option write timing constraints in one of your status reports enables or disables propagation of timing constraints to the NGC file that are specified in HDL code These timing constraints in the NCG file will be used during place and route as well as synthesis optimization Define Write Timing Constrai
250. i do input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 4 0 read a8 always 8 posedge clk begin if we ram a lt di read a lt a end assign do ram read a endmodule XST User Guide www xilinx com 147 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Single Port RAM with Enable The following description implements a single port RAM with a global enable A DO EN WE Block RAM DI CLK VA X9478 The following table shows pin descriptions for a single port RAM with enable IO pins Description clk Positive Edge Clock en Global Enable we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output VHDL Code Following is the VHDL code for a single port block RAM with enable library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk en we a di do 1 end raminf 148 in in in in in r std logic std logic std logic std logic vector 4 downto 0 std logic vector 3 downto 0 out std logic vector 3 downto 0 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_a std_logic_vector 4 downto 0 begin process clk begin if clk
251. ial process In other words a process is sequential when some assigned signals are not explicitly assigned in all paths of the statements In this case the hardware generated has an internal state or memory flip flops or latches Example 6 15 provides a template for describing sequential circuits Also refer to the chapter describing macro inference for additional details registers counters etc Example 6 15 Sequential Process with Asynchronous Synchronous Parts process CLK RST begin if RST lt 0 1 gt then an asynchronous part may appear here optional part elsif CLK EVENT not CLK STABLE gt and CLK lt 0 1 then synchronous part sequential statements may appear here end if end process Note Asynchronous signals must be declared in the sensitivity list Otherwise XST generates a warning and adds them to the sensitivity list In this case the behavior of the synthesis result may be different from the initial specification Sequential Process without a Sensitivity List Sequential processes without a sensitivity list must contain a Wait statement The Wait statement must be the first statement of the process The condition in the Wait statement must be a condition on the clock signal Several Wait statements in the same process are accepted but a set of specific conditions must be respected See Multiple Wait Statements Descriptions for details An asynchronous part cannot be specif
252. ic Operations XILINX Verilog Code Following is the Verilog code for an unsigned 8 bit greater or equal comparator module compar A B CMP input 7 0 A input 7 0 B output CMP assign CMP A gt B 1 b1 1 b0 endmodule Multipliers When implementing a multiplier the size of the resulting signal is equal to the sum of 2 operand lengths If you multiply A 8 bit signal by B 4 bit signal then the size of the result must be declared as a 12 bit signal Large Multipliers Using Block Multipliers XST can generate large multipliers using an 18x18 bit block multiplier available in Virtex II II Pro II Pro X For multipliers larger than this XST can generate larger multipliers using multiple 18x18 bit block multipliers Registered Multiplier For Virtex II II Pro II Pro X in instances where a multiplier would have a registered output XST infers a unique registered multiplier This registered multiplier is 18x18 bits Under the following conditions a registered multiplier is not used and a multiplier register is used instead e Output from the multiplier goes to any component other than the register e The MULT STYLE constraint is set to lut e The multiplier is asynchronous e The multiplier has control signals other than synchronous reset or clock enable e The multiplier does not fit in a single 18x18 bit block multiplier The following pins are optional for a registered multiplier e clock
253. ic types can be overloaded Enumerated Types STD_ULOGIC contains the same nine values as the STD LOGIC type but does not contain predefined resolution functions X01 subtype of STD ULOGIC containing the X 0 and 1 values X01Z subtype of STD ULOGIC containing the X 0 1 and Z values UX01 subtype of STD ULOGIC containing the U X 0 and 1 values UXOIZ subtype of STD ULOGIC containing the U X 0 1 and Z values Bit Vector Types STD ULOGIC VECTOR UNSIGNED SIGNED Unconstrained types types whose length is not defined are not accepted Integer Types NATURAL POSITIVE Any integer type within a user defined range As an example type MSB is range 8 to 15 means any integer greater than 7 or less than 16 The types NATURAL and POSITIVE are VHDL predefined types www xilinx com XST User Guide 1 800 255 7778 Data Types in VHDL XILINX The types STD_ULOGIC and subtypes X01 X01Z UX01 UX01Z STD_LOGIC STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR are declared in the STD_LOGIC_1164 IEEE package This package is compiled in the library IEEE In order to use one of these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC 1164 a11 The types UNSIGNED and SIGNED defined as an array of STD LOGIC are declared in the STD LOGIC ARITH IEEE package This package is compiled in the library IEEE I
254. idth of 8 causes the instance buf_373 to be 8 bits wide Parameter Attribute Conflicts Since parameters and attributes can be applied to both instances and modules in your Verilog code and attributes can also be specified in a constraints file from time to time conflicts will arise To resolve these conflicts XST uses the following rules of precedence 1 Whatever is specified on an instance lower level takes precedence over what is specified on a module higher level 2 Ifa parameter and an attribute are specified on either the same instance or the same module the parameter takes precedence and XST issues a message warning of the conflict 3 An attribute specified in the XCF file will always take precedence over attributes or parameters specified in your Verilog code Note When an attribute specified on an instance overrides a parameter specified on a module in XST itis possible that your simulation tool may nevertheless use the parameter This may cause the simulation results to not match the synthesis results Use the following matrix as a guide in determining precedence Parameter on an Instance Parameter on a Module Attribute Apply Parameter Apply Attribute on an Instance XST issues warning message possible simulation mismatch Attribute Apply Parameter Apply Parameter on a Module XST issues warning message Attribute in XCF Apply Attribute l Apply Attribute XST issues warning message
255. ied within processes without a sensitivity list Example 6 16 shows the skeleton of such a process The clock condition may be a falling or a rising edge 304 www xilinx com XST User Guide 1 800 255 7778 Sequential Circuits 7 XILINX Example 6 16 Sequential Process Without a Sensitivity List process begin wait until lt CLK EVENT not CLK STABLE gt and CLK lt 0 1 gt a synchronous part may be specified here end process Note XST does not support clock and clock enable descriptions within the same Wait statement Instead code these descriptions as in Example 6 17 Note XST does not support Wait statements for latch descriptions Example 6 17 Clock and Clock Enable Not supported wait until CLOCK event and CLOCK 0 and ENABLE 1 Supported wait until CLOCK event and CLOCK 0 if ENABLE 1 then Examples of Register and Counter Descriptions Example 6 18 describes an 8 bit register using a process with a sensitivity list Example 6 19 describes the same example using a process without a sensitivity list containing a Wait statement Example 6 18 8 bit Register Description Using a Process with a Sensitivity List entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process
256. ign Constraints for more information about the options listed in the following tables Table 10 1 Global Options Run Command Options Description Values ifn Input Project File Name file_name ifmt Input Project Format VHDL Verilog mixed top Top Level Block Name block name work lib Work Library library where dir name work the top level block was compiled lso Library Search Order file_name lso ofn Output File Name file_name ofmt Output File Format ngc duplication suffix Duplication Suffix string odstring case Case upper lower maintain hierarchy_separator Hierarchy Separator l opt mode Optimization Goal area speed opt level Optimization Effort 12 p Target Technology part package speed for example xcv50 fg456 5 xcv50 fg456 6 rtlview Generate RTL Schematic yes no only iuc Ignore User Constraints yes no uc Synthesis Constraints File file name xcf www xilinx com 1 800 255 7778 XST User Guide Run Command 7 XILINX Table 10 1 Global Options Run Command Options Description Values bus_delimiter Bus Delimiter lt gt 0 0 enable auto floorplanning Enable Auto Floorplanning no incremental design hdl compilation order Respect HDL file order auto user specified in XST project during compilation step Table 10 2 VHDL Source Options Run Command m D
257. ignal s std logic attribute NOREDUCE boolean attribute NOREDUCE of s signal is true S lt a or a and b You may specify the same attribute in the XCF file with the following lines BEGIN MODEL ENTNAME NET s NOREDUCE NE s KEEP END The following statements are written to the NGC file ET s NOREDUCE s KEEP Example 3 The PWR_MODE constraint available when targeting CPLD families controls the power consumption characteristics of macrocells The following VHDL statement specifies that the function generating signal s should be optimized for low power consumption attribute PWR_MODE string attribute PWR_MODE of s signal is LOW You may specify the same attribute in the XCF file with the following lines ODEL ENTNAME NET s PWR_MODE LOW NE s KEEP END 278 www xilinx com XST User Guide 1 800 255 7778 Third Party Constraints The following statement is written to the NGC file by XST NE NE ry s PWR_MOD s KEEP E LOW XILINX If the attribute applies to an instance for example IOB DRIVE IOSTANDARD and if the instance is not available not instantiated in the HDL source then the HDL attribute can be applied to the signal on which XST infers the instance Third Party Constraints This section describes cons
258. igure ADDRA DOA ADDRB ENA DOB Block ENB RAM WEA DIA CLK V X9476 The following table shows pin descriptions for a dual port RAM with enable on each port IO Pins Description clk Positive Edge Clock ena Primary Global Enable Active High enb Dual Global Enable Active High wea Primary Synchronous Write Enable Active High addra Write Address Primary Read Address addrb Dual Read Address dia Primary Data Input doa Primary Output Port dob Dual Output Port XST User Guide www xilinx com 159 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for a dual port RAM with enable on each port library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic ena enb in std_logic wea in std_logic addra in std_logic_vector 4 downto 0 addrb in std logic vector 4 downto 0 dia in std logic vector 3 downto 0 doa out std logic vector 3 downto 0 dob out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read addra std logic vector 4 downto 0 signal read addrb std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if ena 1 then if wea 1 then RAM conv_integer addra lt
259. ilation XST uses the library work as the default If some VHDL files must be compiled to different libraries then you can add the name of the library just before the file name Suppose that hexl2led must be compiled into the library called my_lib Then the project file must be vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work vhdl tenths vhd vhdl my_lib work hex2led vhd Sometimes XST is not able to recognize the order and issues the following message WARNING XST 3204 The sort of the vhdl files failed they will be compiled in the order of the project fil In this case you must do the following e Put all VHDL files in the correct order e Add hdl compilation order switch with value user to the XST run command run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 top hex2led hdl compilation order user Script Mode XST User Guide It can be very tedious work to enter XST commands directly in the XST shell especially when you have to specify several options and execute the same command several times You can run XST in a script mode as follows 1 Open a new file named xst txt in the current directory Put the previously executed XST shell command into this file and save it run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xcv5
260. in pipe_2 lt mult_res pipe_3 lt pipe_2 MULT lt pipe_3 end endmodule The following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as shift registers module mult3 clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a_in b_in wire 35 0 mult_res reg 35 0 pipe_regs 3 0 assign mult_res a_in b_in always posedge clk begin a_in lt A b_in lt B pipe_regs 3 pipe_regs 2 pipe_regs 1 pipe_regs 0 lt MULT pipe_regs 3 pipe_regs 2 pipe_regs 1 end endmodule 120 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Multiply Adder Subtractor The Multiply Adder Subtractor macro is a complex macro consisting of several basic macros such as multipliers adder subtractors and registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources available in Virtex 4 devices Log File In the Log file XST reports the details of inferred multipliers adder subtractors and registers at the HDL Synthesis step The composition of multiply adder subtractor macros happens at the Advanced HDL Synthesis step XST reports information about inferred MACs because they are implemented within the MAC implementation mechanism HDL Synthesis Synthesizing Unit m multaddsubl
261. in process CLK RST variable COUNT BIT_VECTOR 7 downto 0 begin if RST 1 then COUNT 00000000 elsif CLK EVENT and CLK 1 then COUNT COUNT 00000001 end if DO lt COUNT end process end ARCHI 306 www xilinx com XST User Guide 1 800 255 7778 Sequential Circuits 7 XILINX Multiple Wait Statements Descriptions Sequential circuits can be described with multiple Wait statements in a process When using XST several rules must be respected to use multiple Wait statements These rules are as follows e The process must only contain one Loop statement e The first statement in the loop must be a Wait statement e After each Wait statement a Next or Exit statement must be defined e The condition in the Wait statements must be the same for each Wait statement e This condition must use only one signal the clock signal e This condition must have the following form wait on clock signal until clock_signal EVENT not clock signal STABLE and clock signal 0 1 Example 6 22 uses multiple Wait statements This example describes a sequential circuit performing four different operations in sequence The design cycle is delimited by two successive rising edges of the clock signal A synchronous reset is defined providing a way to restart the sequence of operations at the beginning The sequence of operations consists of as
262. in order to reach the best frequency In the following example the 212 www xilinx com XST User Guide 1 800 255 7778 Speed Optimization Under Area Constraint 7 XILINX target area constraint is set to 70 XST was not able to satisfy it and so gives the corresponding warning message Low Level Synthesis Found area constraint ratio of 70 5 on block fpga_hm actual ratio is 64 Optimizing block lt fpga_hm gt to meet ratio 70 5 of 1536 slices WARNING Xst Area constraint could not be met for block lt tge gt final ratio is 94 Note 5 stands for the max margin of the area constraint This means that if the area constraint is not met but the difference between the requested area and obtained area during area optimization is less or equal then 5 then XST runs timing optimization taking into account the achieved area not exceeding it In the following example the area was specified as 55 XST achieved only 60 But taking into account that the difference between requested and achieved area is not more than 5 XST considers that the area constraint was met Low Level Synthesis Found area constraint ratio of 55 5 on block fpga_hm actual ratio is 64 Optimizing block lt fpga_hm gt to meet ratio 55 5 of 1536 slices Area constraint is met for block lt fpga_hm gt final ratio is 60 The SLICE_UTILIZATION_RATIO constraint can be attached
263. in the XST Constraints File XCF e Period PERIOD is a basic timing constraint and synthesis constraint A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other See PERIOD in the Constraints Guide for details XCF Syntax NET netname PERIOD value HIGH LOW value e Offset OFFSFT is a basic timing constraint It specifies the timing relationship between an external clock and its associated data in or data out pin OFFSET is used only for pad related signals and cannot be used to extend the arrival time specification method to the internal signals in a design OFFSET allows you to Calculate whether a setup time is being violated at a flip flop whose data and clock inputs are derived from external nets Specify the delay of an external output net derived from the Q output of an internal flip flop being clocked from an external device pin See OFFSET in the Constraints Guide for details XCF Syntax OFFSET IN OUT offset_time units BEFORE AFTER clk_name TIMEGRP group_namel e From To FROM TO defines a timing constraint between two groups A group can be user defined or predefined FFS PADS RAMS See FROM TO in the Constraints Guide for details Example XCF Syntax TIMESPEC TSnam
264. inferred MACs during the Advanced HDL Synthesis Step where the MAC implementation mechanism takes place Multiplier Adder with 2 Register Levels on Multiplier Inputs VHDL Code Use the following templates to implement Multiplier Adder with 2 Register Levels on Multiplier Inputs in VHDL library IEEE use IEEE STD_LOGIC_1164 ALL use IEEE STD_LOGIC_UNSIGNED ALL entity m_multaddsubl is generic p_width integer 8 port clk in std_logic A B C in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end m_multaddsubl www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX architecture beh of m_multaddsubl is signal A_regl A_reg2 B_regl B_reg2 std_logic_vector p_width 1 downto 0 signal multaddsub std_logic_vector p_width 2 1 downto 0 begin multaddsub lt A_reg2 B_reg2 C process clk begin if clk event and clk 1 then A_regl lt A A_reg2 lt A_regl B_regl lt B B_reg2 lt B_regl end if end process RES lt multaddsub end beh Verilog Code Use the following templates to implement Multiplier Adder with 2 Register Levels on Multiplier Inputs in Verilog module mvl_multaddsubl clk A B C RES input clk input 7 0 A input 7 0 B input 720 6G output 15 0 RES reg 7 0 A regl A reg2 B_regl B reg2 wire 15 0 multaddsub alwa
265. ing Flip flop Retiming is a technique that consists of moving flip flops and latches across logic for the purpose of improving timing thus increasing clock frequency Flip flop retiming can be either forward or backward Forward retiming moves a set of flip flops that are the input of a LUT to a single flip flop at its output Backward retiming moves a flip flop that is at the output of a LUT to a set of flip flops at its input Flip flop retiming can significantly increase the number of flip flops in the design and it may remove some flip flops XST User Guide www xilinx com 207 1 800 255 7778 XILINX Chapter 3 FPGA Optimization Nevertheless the behavior of the designs remains the same Only timing delays are modified Flip flop Retiming is part of global optimization and it respects the same constraints as all the other optimization techniques Retiming is an iterative process therefore a flip flop that is the result of a retiming can be moved again in the same direction forward or backward if it results in better timing The only limit for the retiming is when the timing constraints are satisfied or if no more improvements in timing can be obtained For each flip flop moved a message is printed specifying the original and new flip flop names and if itis a forward or backward retiming Note the following limitations e Hip flop retiming is not applied to flip flops that have the IOB TRUE property e Flip flops are
266. ing by selecting the Keep Hierarchy option under the Synthesis Options tab in the Process Properties dialog box within Project Navigator Preserve equivalent flip flops which XST removes by default Specify the Equivalent Register Removal setting by selecting the Equivalent Register Removal option under the Xilinx Specific Options tab in the Process Properties dialog box within Project Navigator Prevent logic and flip flop replication caused by high fanout flip flop set reset signals Do this by Setting a high maximum fanout value for the entire design via the Max Fanout menu in the Synthesis Options tab in the Process Properties dialog box within Project Navigator or Setting a high maximum fanout value for the initialization signal connected to the RST port of PCI core by using the MAX FANOUT attribute for example max fanout 2048 Prevent XST from automatically reading PCI cores for timing and area estimation In reading PCI cores XST may perform some logic optimization in the user s part of the design that does not allow the design to meet timing requirements or might even lead to errors during MAP Disable Read Cores by unchecking the Read Cores option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator Note By default XST reads cores for timing and area estimation www xilinx com 225 1 800 255 7778 7 XILINX Chapter 3 FPGA Optimization 226 www xilinx com XST User Gui
267. ins Description s 2 0 Selector res Data Output Related Constraints A related constraint is DECODER EXTRACT VHDL One Hot Following is the VHDL code for a 1 of 8 decoder library ieee use ieee std logic 1164 a11 entity dec is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end dec XST User Guide www xilinx com 93 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of dec is begin res lt 00000001 when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi Verilog One Hot Following is the Verilog code for a 1 of 8 decoder module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always sel or res begin case sel 3 b000 res 8 b00000001 3 b001 res 8 b00000010 3 b010 res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100000 3 b110 res 8 b01000000 default res 8 b10000000 endcase end endmodule VHDL One Cold Following is the VHDL code for a 1 of 8 decoder library ieee use ieee std_logic_1164 all entity dec is port sel in std_logic_vector 2 downto 0 res out std_logic_vector 7 downto 0 end dec 94 www xil
268. int targets e Automatic FSM Extraction The Automatic FSM Extraction FSM_EXTRACT constraint enables or disables finite state machine extraction and specific synthesis optimizations This option must be enabled in order to set values for the FSM Encoding Algorithm and FSM Flip Flop Type See FSM_EXTRACT in the Constraints Guide for details e Enumerated Encoding VHDL The Enumerated Encoding ENUM_ENCODING constraint can be used to apply a specific encoding to a VHDL enumerated type See ENUM_ENCODING in the Constraints Guide for details Note Because it must preserve the external design interface XST ignores the ENUM_ENCODING constraint when it is used on a port e Equivalent Register Removal The Equivalent Register Removal EQUIVALENT_REGISTER_REMOVAL constraint enables or disables removal of equivalent registers described at the RTL Level By default XST does not remove equivalent flip flops if they are instantiated from a Xilinx primitive library To allow optimization of instantiated flip flops and other primitives use the OPTIMIZE_PRIMITIVES constraint See EQUIVALENT REGISTER REMOVAL in the Constraints Guide for details e FSM Encoding Algorithm The FSM Encoding Algorithm FSM_ENCODING constraint selects the finite state machine coding technique to be used The Automatic FSM Extraction option must be enabled in order to select a value for the F5M Encoding Algorithm See FSM ENCODING in the Con
269. inx com XST User Guide 1 800 255 7778 Decoders XILINX architecture archi of dec is begin res lt 11111110 1ITVLTLTOL 11111011 WITT O14 WIT TA 11011111 10111111 OLIVA end archi Verilog One Cold Following is the Verilog code for a 1 of 8 decoder when when when when when when when module mux sel res input 2 0 sel output 7 0 res reg 7 0 res always sel begin case sel 3 p000 res 3 p001 res 3 p010 res 3 p011 res 3 p100 res 3 p101 res 3 p110 res default res 8 b011111 endcase end endmodule sel sel sel sel sel sel sel 000 001 010 011 100 101 110 8 bLT111110 8 b11111101 8 b11111011 8 b11110111 8 b11101111 8 b11011111 8 b10111111 113 Decoders with Unselected Outputs else else else else else else else In the current version XST does not infer decoders if one or several of the decoder outputs are not selected except when the unused selector values are consecutive and at the end of the code space Following is an example IO pins Description s 2 0 Selector res Data Output XST User Guide www xilinx com 1 800 255 7778 95 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code No Decoder Inference For the following VHDL code XST does not infer a decoder library ieee use ieee std
270. ion and coding techniques when creating designs for use with XST What s New The following is a list of the major changes to XST for release 7 1i HDL Language Support VHDL XST User Guide Support for configurations and nested configurations See VHDL Language Support in Chapter 6 Support for shared variables dual write block RAM inference only See VHDL Language Support in Chapter 6 Support for NULL arrays Improved support for File Read See File Type Support in Chapter 6 Support for hexadecimal values in read operations www xilinx com 19 1 800 255 7778 XILINX Verilog Chapter 1 Introduction Support for std ulogic type limited to values 1 and 0 Support for character and string type read functions Improved support for while loops See While Loops in Chapter 7 Support for variable part selects See Variable Part Selects in Chapter 7 Support of defparams for passing attributes for Xilinx library primitives See Virtex Primitive Support in Chapter 3 Macro Inference 20 Support for Dynamic Shift Registers without size limitations Inference of dual write port block RAM VHDL only See Dual Port Block RAM with Two Write Ports in Chapter 2 Support for parity bits usage for block RAM implementation limited to Virtex 4 devices See RAMs ROMs in Chapter 2 Support for Block RAM initialization via signal declaration
271. ion ports 26MHz 63 22 Delay Source Destination Source Clock Destination Clock 7 523ns sdstate_FFD1 sdstate_FFD2 clk rising clk rising Levels of Logic Data Path sdstate_FFD1 to sdstate_FFD2 Gate Net 2 Cell in gt out fanout Delay Delay Logical Name NetName FDC C gt Q 15 1 372 2 970 state_FFD1 state_FFD1 LUT3 11 gt 0 iL 0 738 1 26 LUT_54 N39 LUT3 11 gt 0 1 0 738 0 00 I_next_state_2 N39 FDC D 0 440 state_FFD2 Total 7 523ns 3 288ns logic 4 235ns route 43 7 logic 56 3 route Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name FDC C gt 0 15 1 372 2 970 I state 2 begin scope blockl LUT3 11 gt 0 1 0 738 1 265 LUT_54 end scope blockl LUT3 10 gt 0 1 0 738 0 000 I_next_state_2 FDC D 0 440 I_state_2 Total 7 523ns 216 www xilinx com XST User Guide 1 800 255 7778 Log File Analysis XILINX Timing Summary The Timing Summary section gives a summary of the timing paths for all 4 domains e The path from any clock to any clock in the design inimum period 7 523ns Maximum Frequency 132 926MHz e The maximum path from all primary inputs to the sequential elements inimum input arrival time before clock 8 945ns e The maximum path from the sequential elements to all primary outputs aximum output required time before clock 14 220ns e The maximum path from inputs to outputs aximum combinational path delay 10 899ns
272. ire tarrekin ieee nee eens 286 Multi dimensional Array Types sssese en 287 Record Types PTT doi ados pi Bl at li pane co lie 288 Initial Values oooosrmsisrianir rra aaa 289 Local Reset 4 Global Reset o oooooooooororoo RR RII 289 Default Initial Values on Memory Elements ooooooooccooccconrrrrrc 290 Default Initial Values on Unconnected Ports 0 0000 ccc ccc eee eee 291 Objects in VADs conocida 291 lcu MET 291 Entity and Architecture Descriptions 00 0 eee eee eee 292 Entity D claration ccd ies seed e A eRe ee b ar a Ree d aera 292 Architecture Declaration 0 00 00 ccc ccc cece cece et 292 Component Instantiation 6 66 eh 293 Recursive Component Instantiation 6 6 eee eee 294 Component Configuration ssie yssesssde drer enia te ee 295 Generic Parameter Declaration 0 00 00 c ccc cece n 295 Generic Attribute Conflicts isses s 296 Combinatorial Circuits esses e 297 Concurrent Signal Assignments esses es 297 Simple Signal Assignment ssssssseeeeeee ee 297 Selected Signal Assignment oooooooooccocooonconnrnrr e 298 Conditional Signal Assignment ese 298 Generate Statement 298 Combinatorial Process ci oekaki A EE da Rs aia ala a 299 It Else Statements oto re ia PIA FRE 301 Case Statement ic isse Ru pn ee qua Hedda REET d REP AR E RCRA EE REA 302 For Loop Statement ooooooooocorrrrr enne 303 Sequera Circ it
273. is an example of an XST log file for CPLD synthesis Release 7 1i xst H 37 Copyright c 1995 2004 Xilinx Inc All rights reserved TABLE OF CONTENTS Synthesis Options Summary 2 HDL Compilation 3 HDL Analysis 4 5 HDL Synthesis Advanced HDL Synthesis 5 1 HDL Synthesis Report 6 Low Level Synthesis 7 Final Report E Synthesis Options Summary Source Parameters Input File Name stopwatch prj Input Format mixed Ignore Synthesis Constraint File NO Verilog Include Directory Target Parameters Output File Name stopwatch Output Format NGC Target Device xc9500x1 Source Options Top Module Name stopwatch Automatic FSM Extraction YES FSM Encoding Algorithm Auto Mux Extraction YES Resource Sharing YES Target Options Add IO Buffers YES Equivalent register Removal YES ACRO Preserve YES XOR Preserve YES General Options Optimization Goal Speed Optimization Effort Meus Keep Hierarchy YES RTL Output Yes Hierarchy Separator Bus Delimiter lt gt Case Specifier maintain Other Options lso stopwatch lso verilog2001 YES Clock Enable YES wysiwyg NO XST User Guide www xilinx com 375 1 800 255 7778 XILINX Chapter 9 Log File Analysis HDL Compilation Compiling vhdl file C temp timer smallcntr vhd in Library work Architecture inside of Entity
274. is ignored for synthesis and hence this section describes modeling combinatorial logic with the statement A combinatorial always block has a sensitivity list appearing within parentheses after the word always Q An always block is activated if an event value change or edge appears on one of the sensitivity list signals This sensitivity list can contain any signal that appears in conditions If Case for example and any signal appearing on the right hand side of an assignment By substituting a without parentheses for a list of signals the always block is activated for an event in any of the always block s signals as described above Note In combinatorial processes if a signal is not explicitly assigned in all branches of If or Case statements XST generates a latch to hold the last value To avoid latch creation be sure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the process statements XST User Guide www xilinx com 329 1 800 255 7778 XILINX 330 Chapter 7 Verilog Language Support Different statements can be used in a process e Variable and signal assignment e Jf else statement e Case statement e For and while loop statement e Function and task call The following sections provide examples of each of these statements If Else Statement If else statements use true false conditions to execute statements If the expression evaluates to
275. is related to the use of mixed language VHDL Verilog projects support It allows you to specify the order in which various library files are used It can be invoked by specifying the file containing the search order in the value field to the right of Library Search option under the Synthesis Options tab in the Process Properties dialog box in Project Navigator or with the lso command line option See the Library Search Order File in Chapter 8 for details LOC The LOC constraint defines where a design element can be placed within an FPGA CPLD See LOC in the Constraints Guide for details Optimization Effort The Optimization Effort OPT LEVEL constraint defines the synthesis optimization effort level See OPT LEVEL in the Constraints Guide for details Optimization Goal The Optimization Goal OPT MODE constraint defines the synthesis optimization strategy Available strategies can be speed or area See OPT MODE in the Constraints Guide for details Parallel Case Verilog The PARALLEL CASE directive is used to force a case statement to be synthesized as a parallel multiplexer and prevents the case statement from being transformed into a prioritized if elsif cascade See Multiplexers in Chapter 2 of this guide Also see PARALLEL CASE in the Constraints Guide for details RLOC The RLOC constraint is a basic mapping and placement constraint This constraint groups logic elements into discrete sets and allows you
276. ith Positive Gate D Latch Latch with Positive Gate and Asynchronous Clear D Latch with Reset 4 bit Latch with Inverted Gate and Asynchronous Preset 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable Tristates Description Using Process Method VHDL Combinatorial Process and Always Block Description Using Concurrent Assignment Always Method Verilog Standalone Method VHDL and Verilog www xilinx com 1 800 255 7778 XST User Guide Introduction XST User Guide XILINX Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Counters Chapter Examples 4 bit Unsigned Up Counter with Asynchronous Clear 4 bit Unsigned Down Counter with Synchronous Set 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input 4 bit Unsigned Up Counter with Synchronous Load with a Constant 4 bit Unsigned Up Counter with Asynchronous Clear and Clock Enable 4 bit Unsigned Up Down counter with Asynchronous Clear 4 bit Signed Up Counter with Asynchronous Reset Language Templates 4 bit asynchronous counter with count enable asynchronous reset and synchronous load Accumulators 4 bit Unsigned Up Accumulator with Asynchronous Clear None www xilinx com 1 800 255 7778 35 XILINX 36 Chapter 2 HDL Coding Techniques Table 2 1 VHDL and Verilog Examples and Templates Macro Blocks Shift Registers
277. itive Instantiations and Ul out inl in2 bufifl U2 triout data trienable The following table shows which primitives are supported Table 7 10 Primitives and nand nor or xnor xor Supported buf not Supported bufif0 bufif1 notifO notif1 Supported Gate Level Primitives pulldown pullup Unsupported drive strength Ignored delay Ignored array of primitives Supported cmos nmos pmos remos rnmos Unsupported Switch Level TP OS Primitives rtran rtranif0 rtranif1 tran Unsupported tranif0 tranifl User Defined Unsupported Primitives www xilinx com 1 800 255 7778 XILINX Verilog Reserved Keywords The following table shows the Verilog reserved keywords 352 Chapter 7 Verilog Language Support Table 7 11 Verilog Reserved Keywords always end ifnone not rnmos tri and endcase incdir notifO rpmos tri0 assign endconfig include notif1 rtran tril automatic endfunction initial or rtranif0 triand begin endgenerate inout output rtranif1 trior buf endmodule input parameter scalared trireg bufif0 endprimitive instance pmos show use cancelled bufif1 endspecify integer posedge signed vectored case endtable join primitive small wait casex endtask large pullo specify wand casez event liblist pulli specparam weak0 cell for library pullup strong weak1 cmos for
278. ity it is visible both in the entity and the architecture body If the attribute is declared in the architecture it cannot be used in the entity declaration Once declared a VHDL attribute can be specified as follows attribute AttributeName of ObjectList ObjectType is AttributeValue 242 www xilinx com XST User Guide 1 800 255 7778 Verilog Meta Comment Syntax XILINX Examples attribute RLOC of ul23 label is R11C1 S0 attribute bufg of my_signal signal is sr The object list is a comma separated list of identifiers Accepted object types are entity component label signal variable and type Verilog Meta Comment Syntax Constraints can be specified as follows in Verilog code synthesis attribute AttributeName of ObjectName is AttributeValue Example synthesis attribute RLOC of u123 is R11C1 S0 synthesis attribute HU_SET ul MY_SET synthesis attribute bufg of my_clock is clk Note The parallel_case full_case translate_on and translate_off directives follow a different syntax described in Verilog Meta Comments in Chapter 7 Verilog 2001 Attributes XST supports Verilog 2001 attribute statements Attributes are comments that are used to pass specific information to software tools such as synthesis tools Verilog 2001 attributes can be specified anywhere for operators or signals within module declarations and instantiations and signal declarations Note Other attribute dec
279. ity mux is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end mux architecture archi of mux is begin process a b c d s begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt Cc end if end process end archi Verilog Code Following is the Verilog code for a 3 to 1 1 bit MUX with a 1 bit latch module mux a b C d S O input a b C d input 1 0 s output o reg o always a or b or c or d or s begin 1f s 2 b00 o a else if s 2 b01 o b else if s 2 b10 Oo C end endmodule 92 www xilinx com XST User Guide 1 800 255 7778 Decoders XILINX Decoders A decoder is a multiplexer whose inputs are all constant with distinct one hot or one cold coded values Please refer to Multiplexers in this chapter for more details This section shows two examples of 1 of 8 decoders using One Hot and One Cold coded values Log File The XST log file reports the type and size of recognized decoders during the Macro Recognition step Synthesizing Unit lt dec gt Related source file is decoders_1 vhd Found 1 of 8 decoder for signal res Summary inferred 1 Decoder s Unit dec synthesized HDL Synthesis Report Macro Statistics Decoders salt 1 of 8 decoder FH The following table shows pin definitions for a 1 of 8 decoder IO p
280. ive edge clock module flop C D Q input C D output Q reg Q always posedge C begin Q lt D end endmodule Flip flop with Negative Edge Clock and Asynchronous Clear The following figure shows a flip flop with negative edge clock and asynchronous clear The following table shows pin definitions for a flip flop with negative edge clock and asynchronous clear 10 Pins Description D Data Input C Negative Edge Clock CLR Asynchronous Clear active High Q Data Output XST User Guide www xilinx com 43 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the equivalent VHDL code for a flip flop with a negative edge clock and asynchronous clear library ieee use ieee std_logic_1164 all entity flop is port C D CLR in std_logic Q out std logic end flop architecture archi of flop is begin process C CLR begin if CLR 1 then Q 0 elsif C event and C 0 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a flip flop with a negative edge clock and asynchronous clear module flop C D CLR Q input C D CLR output Q reg Q always negedge C or posedge CLR begin if CLR Q lt 1 b0 else Q lt D end endmodule Flip flop with Positive Edge Clock and Synchronous Set The following figure shows a flip flop with positive edge clock an
281. iven optimization Some of these primitives can be generated through attributes e BUFFER_TYPE CLOCK BUFFER can be assigned to the primary input or internal signal to force the use of BUFGDLL IBUFG BUFR or BUFGP The same constraints can be used to disable buffer insertion e IOSTANDARD can be used to assign an I O standard to an I O primitive For example synthesis attribute IOSTANDARD of inl is PCI33 5 assigns PCI33 5 I O standard to the I O port The primitive support is based on the notion of the black box Refer to Safe FSM Implementation in Chapter 2 for the basics of the black box support There is a significant difference between black box and primitive support Assume you have a design with a submodule called MUXF5 In general the MUXF5 can be your own functional block or a Virtex primitive So to avoid confusion about how XST interprets this module use a special constraint called BOX TYPE This attribute must be attached to the component declaration of MUXF5 e Ifthe BOX TYPE attribute is attached to the MUXF5 with a value of primitive or black box XST tries to interpret this module as a Virtex primitive and use its parameters for instance in critical path estimation 218 www xilinx com XST User Guide 1 800 255 7778 Virtex Primitive Support XILINX e user_black_box XST processes it as a regular user black box If the name of the user black box is the same as that of a Virtex primiti
282. jo 225 Chapter 4 CPLD Optimization CPLD Synthesis Options rita A eol eei 227 XST User Guide www xilinx com 13 1 800 255 7778 XILINX Introduction iecur pa ov tala be et aa wea ped caved ea ved bd ra 227 Global CPLD Synthesis Options seces ascen cees nesd eded i 227 Families Perscawugetreteri e c bia eea aaa aa sales 227 Listot OPHONS 5 ad detto A A o a 228 Implementation Details for Macro Generation 00005 228 Log File Analysis eos eer RE a RA ri 229 oar cin cM 231 Improving Res lts va riprsrind ies eevee ioie AS A d Ee Pai 231 How to Obtain Better Frequency 6 6 6 231 How to Fit a Large Design 0 6 6 e eee 232 Chapter 5 Design Constraints Introduccion ete ee Eb Ole Ne eek bs Shee ra stu thes 233 Setting Global Constraints and Options 0c cee e eee 234 Synthesis Options suse ed et HW te ered 234 HDL Op HOnis EET 238 Xilinx Specific Options sse ss saiae rr 240 Other XST Command Line Options 6 0 0 e ene eee 242 Custom Compile File List 6 0 6 eee eens 242 VHDL Atributo Rda 242 Verilog Meta Comment Syntax eese 243 Verilog 2001 Attributes isse issscikdex ker eedem ebbe hdd kd dera a 243 pnr cc Cr 243 Example liston te br bie nrbs ee Ves vite qu ee ee eas e Va 243 Example Zeen 24 o estie acces tutes A gue endi aot ana tate tede ses 244 Example Sister diras ete idus teed esa 244 Example EE 244 Limutatons xw ER PP SSS oe ao Soe e
283. k RAM with the following synchronization modes can have resetable data ports e Read First Block RAM with Reset e Write First Block RAM with Reset e No Change Block RAM with Reset e Registered ROM with Reset e Supported Dual Port Templates Note Because XST does not support block RAMs with dual write in a dual read block RAM description both data outputs may be reset but the various read write synchronizations are only allowed for the primary data output The dual output may only be used in read first mode 168 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX The following example shows a Read First Block RAM with reset ADDR EN WE Block RAM with Reset DI CLK RST X10019 The following table shows pin descriptions for a block RAM with reset IO pins Description clk Positive Edge Clock en Global Enable we Write Enable active High addr Read Write Address rst Reset for data output di Data Input do RAM Output Port VHDL Code Following is the VHDL code for a read first RAM with reset library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity ramrst is port clk a in std logic en in std_logic we in std_logic rst in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end ramrst XST User Guide www xilinx com 169 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Te
284. l lt A 4 downto 0 sra 2 logically equivalent to sigl lt lt A 4 amp A 4 amp A 4 downto 2 Example rol Rotate Left sigl lt A 4 downto 0 rol 2 logically equivalent to sigl lt A 2 downto 0 amp A 4 downto 3 Example ror Rotate Right A 4 downto 0 ror 2 logically equivalent to sigl lt A 1 downto 0 amp A 4 downto 2 Entity and Architecture Descriptions A circuit description consists of two parts the interface defining the I O ports and the body In VHDL the entity corresponds to the interface and the architecture describes the behavior Entity Declaration Chapter 6 VHDL Language Support The I O ports of the circuit are declared in the entity Each port has aname a mode in out inout or buffer and a type ports A B C D E in the Example 6 1 Note that types of ports must be constrained and not more than one dimensional array types are accepted as ports Architecture Declaration Internal signals may be declared in the architecture Each internal signal has a name and a type signal T in Example 6 1 Example 6 1 Entity and Architecture Declaration Library IEEE td logic 1164 all PLE use enti po end 292 IEEE s ty EXA rt D E A B C is in std logic out std logic EXAMPLE www xilinx com 1 800 255 7778 XST User Guide Entity and
285. larations may be supported by the compiler but are ignored by XST Attributes can be used to e Set constraints on individual objects for example module instance net e Set FULL_CASE and PARALLEL_CASE synthesis directives Syntax Attributes must be bounded by the characters and and are written using the following syntax attribute_name attribute_value Where e The attribute must precede the signal module or instance declaration it refers to e The attribute value must be a string no integer or scalar values are allowed e The attribute_value must be between quotes e The default value is 1 attribute name is the same as attribute name 1 Example 1 clock_buffer IBUFG input CLK XST User Guide www xilinx com 243 1 800 255 7778 XILINX Chapter 5 Design Constraints Example 2 INIT 0000 reg 3 0 d_out Example 3 always current_state or reset begin parallel_case full_case case current_state Example 4 mult_style pipe_lut MULT my_mult a b c Limitations Verilog 2001 attributes are not supported for the following e signal declarations e statements e port connections e expression operators XST Constraint File XCF XST constraints can be specified in a file called the Xilinx Constraint File XCF The XCF must have an extension of xcf You can specify the constraint file in ISE by going to the Synthesis XST Proce
286. lators Shift Registers Dynamic Shift Registers Multiplexers Decoders Priority Encoders Logical Shifters Arithmetic Operators Adders Subtractors Adders Subtractors Comparators Multipliers Dividers RAMs State Machines Black Boxes For each macro both VHDL and Verilog examples are given There is also a list of constraints you can use to control the macro processing in XST Note For macro implementation details please refer to Chapter 3 FPGA Optimization and Chapter 4 CPLD Optimization Table 2 1 provides a list of all the examples in this chapter as well as a list of VHDL and Verilog synthesis templates available from the Language Templates in Project Navigator To access the synthesis templates from Project Navigator 1 Select Edit gt Language Templates 2 Click the sign for either VHDL or Verilog 3 Click the sign next to Synthesis Templates www xilinx com 33 1 800 255 7778 XILINX 34 Chapter 2 HDL Coding Techniques Table 2 1 WHDL and Verilog Examples and Templates Macro Blocks Chapter Examples Language Templates Registers Flip flop with Positive Edge D Flip Flop Clock Flip flop with Negative D Flip flop with Asynchronous Edge Clock and Reset Asynchronous Clear Flip flop with Positive Edge D Flip Flop with Synchronous Clock and Synchronous Set Reset Flip flop with Positive Edge D Flip Flop with Clock Enable Clock and Clock Enable Latch w
287. le counters for instance depends on the family type A counter with clock enable is accepted for the CoolRunner XC9500XL and XC9500XV families but rejected replaced by equivalent logic for XC9500 devices List of Options Following is a list of CPLD synthesis options that you can set from the Process Properties dialog box in Project Navigator For details about each option refer to CPLD Constraints non timing in Chapter 5 e Keep Hierarchy e Macro Preserve e XOR Preserve e Equivalent Register Removal e Clock Enable e WYSIWYG e No Reduce Implementation Details for Macro Generation 228 XST processes the following macros e adders e subtractors e add sub e multipliers e comparators e multiplexers e counters e logical shifters e registers flip flops and latches e XORs The macro generation is decided by the Macro Preserve option which can take two values yes macro generation is allowed no macro generation is inhibited The general macro generation flow is the following 1 HDL infers macros and submits them to the low level synthesizer 2 Low level synthesizer accepts or rejects the macros depending on the resources required for the macro implementations An accepted macro is generated by an internal macro generator A rejected macro is replaced by equivalent logic generated by the HDL synthesizer A rejected macro may be decomposed by the HDL synthesizer into component
288. lecting encoding for FSM_O Optimizing FSM lt FSM_0 gt on signal lt current_state gt with one hot encoding Safe FSM Implementation XST can add logic to your FSM implementation that will let your state machine recover from an invalid state If during its execution a state machine gets into an invalid state the logic added by XST will bring it back to a known state called a recovery state This is known as Safe Implementation mode To activate Safe FSM implementation select the Safe Implementation option from the Synthesis Properties dialog box in Project Navigator or apply the SAFE_IMPLEMENTATION constraint to the hierarchical block or signal that represents the state register See Safe Implementation in Chapter 5 for details about the SAFE_IMPLEMENTATION constraint By default XST automatically selects a reset state as the recovery state If the FSM does not have an initialization signal XST selects a power up state as the recovery state You can manually define the recovery state by applying the RECOVERY_STATE constraint See Recovery State in Chapter 5 for details about the RECOVERY_STATE constraint 194 www xilinx com XST User Guide 1 800 255 7778 Black Box Support XILINX Black Box Support Log File Your design may contain EDIF or NGC files generated by synthesis tools schematic editors or any other design entry mechanism These modules must be instantiated in your code to be connected to
289. linx com 81 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out library ieee use ieee std_logic_1164 all entity shift is port C SI LEFT_RIGHT in std_logic PO out std_logic_vector 7 downto 0 end shift architecture archi of shift is signal tmp std_logic_vector 7 downto 0 begin process C begin if C event and C 1 then if LEFT_RIGHT 0 then tmp lt tmp 6 downto 0 amp SI else tmp lt SI tmp 7 downto 1 end if end if end process PO lt tmp end archi Verilog Code Following is the Verilog code for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out module shift C SI LEFT_RIGHT PO input C SI LEFT_RIGHT output PO reg 7 0 tmp always posedge C begin if LEFT_RIGHT 1 b0 tmp lt tmp 6 0 SI else tmp lt SI tmp 7 1 end assign PO tmp endmodule Dynamic Shift Register XST can infer Dynamic shift registers Once a dynamic shift register has been identified its characteristics are handed to the XST macro generator for optimal implementation using SRL16x primitives available in Spartan II ITE 3 Virtex II II Pro II Pro X 4 or SRLC16x in Virtex II II Pro II Pro X 4 and Spartan 3 82 www xilinx com
290. linx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX architecture beh of m_mac2 is signal mult accum std_logic_vector p_width 2 1 downto 0 begin process clk begin if clk event and clk 1 then if reset 1 then accum lt others gt 0 mult lt others gt 0 else if add sub 1 then accum lt accum mult else accum lt accum mult end if mult lt A B end if end if end process RES accum end beh Verilog Code Usethe following templates to implement Multiplier Up Down Accumulate with Register After Multiplication in Verilog module mvl_mac2 clk reset add sub A B RES input clk reset add sub input 7 0 A input 7 0 B output 15 0 RES reg 15 0 mult accum always posedge clk begin if reset mult lt 16 50000000000000000 else mult lt A B end always posedge clk begin if reset accum lt 16 b0000000000000000 else if add_sub accum lt accum mult else accum lt accum mult end assign RES accum endmodule XST User Guide www xilinx com 129 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Dividers Dividers are only supported when the divisor is a constant and is a power of 2 In that case the operator is implemented as a shifter otherwise XST issues an error message Log File When you implement a divider with a constant with the power of 2 XST does n
291. linx com XST User Guide 1 800 255 7778 Timing Constraints XILINX independent of the XOR preservation done by HDL synthesis and is guided only by the goal of complexity reduction Define this constraint globally with the pld_xp command line option of the run command Following is the basic syntax pld xp yes no The default is yes In Project Navigator specify pld xp globally with the XOR Preserve option in the Xilinx Specific Options tab of the Process Properties dialog box within the Project Navigator Timing Constraints Timing constraints supported by XST can be applied either via the glob opt command line switch which is the same as selecting Global Optimization Goal from the Synthesis Options tab of the Process Properties menu in Project Navigator or via the constraints file Using the glob opt Global Optimization Goal method allows you to apply the five global timing constraints ALLCLOCKNETS OFFSET IN BEFORE OFFSET OUT AFTER INPAD TO OUTPAD and MAX DELAY These constraints are applied globally to the entire design You cannot specify a value for these constraints as XST optimizes them for the best performance Note that these constraints are overridden by constraints specified in the constraints file Using the constraint file method you can specify timing constraints using native UCF syntax XST supports constraints such as TNM NET TIMEGRP PERIOD TIG FROM TO etc including wildcards and hierarc
292. linx com XST User Guide 1 800 255 7778 VHDL Language Support Table 6 7 Specifications XILINX Attribute Only supported for some predefined attributes HIGH LOW LEFT RIGHT RANGE REVERSE_RANGE LENGTH POS ASCENDING EVENT LAST_VALUE Otherwise ignored Configuration default library Supported only with the all clause for instances list If no clause is added XST looks for the entity architecture compiled in the Disconnection Unsupported Table 6 8 Names Simple Names Supported Selected Names Supported Indexed Names Supported Slice Names Supported including dynamic ranges Note XST does not allow underscores as the first character of signal names for example _DATA_1 Table 6 9 Expressions Operators Logical Operators Supported and or nand nor xor xnor not Relational Operators Supported y lt lt gt gt amp concatenation Supported Adding Operators Supported 7 Supported rem Supported if the right operand is a constant power of 2 mod Supported Shift Operators Supported sll srl sla sra rol ror abs Supported dd Only supported if the left operand is 2 Sign Supported XST User Guide www xilinx com 1 800 255 7778 317 XILINX 318 Table 6 9 Expressions Chapter 6 VHDL Language Support Operands
293. llowing is the most general example it has different clocks enables and write enables library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity raminfr is port clka in std logic clkb in std logic ena in std logic enb in std logic wea in std logic web in std logic addra in std logic vector 7 downto 0 addrb in std logic vector 7 downto 0 dia in std logic vector 15 downto 0 dib in std logic vector 15 downto 0 doa out std logic vector 15 downto 0 dob out std logic vector 15 downto 0 end raminfr architecture syn of raminfr is type RAMtype is array 0 to 255 of std logic vector 15 downto 0 shared variable RAM RAMtype begin process CLKA begin if CLKA event and CLKA 1 then if ENA 1 then if WEA 1 then RAM conv_integer ADDRA DIA end if DOA lt RAM conv_integer ADDRA end if end if end process process CLKB begin if CLKB event and CLKB 1 then if ENB 1 then if WEB 1 then RAM conv_integer ADDRB DIB end if DOB lt RAM conv_integer ADDRB end if end if end process end syn Because of the shared variable the description of the different read write synchronizations may be different from templates recommended for single write RAMs Note that the order of appearance of the different lines of code becomes important 164 w
294. log 2001 Verilog Include Directories Verilog Only Custom Compile File List Other XST Command Line Options To view these options go to the Property Display Level drop down menu at the bottom of the window and click Advanced www xilinx com 1 800 255 7778 237 XILINX 238 HDL Options With the Process Properties dialog box displayed for the Synthesize XST process select the HDL Options tab For FPGA device families the following dialog box displays Chapter 5 Design Constraints Process Properties x Synthesis Options HDL Options xiinx Specific Options Safe Implementation Safe Implementation Cancel Default Help Figure 5 3 HDL Options Tab FPGAs Following is a list of all HDL Options that can be set within the HDL Options tab of the Process Properties dialog box for FPGA devices FSM Encoding Algorithm Safe Implementation Case Implementation Style FSM Style RAM Extraction RAM Style ROM Extraction ROM Style Mux Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction www xilinx com 1 800 255 7778 XST User Guide Setting Global Constraints and Options 7 XILINX Logical Shifter Extraction XOR Collapsing Resource Sharing Multiplier Style Use DSP48 To view these options go to the Property Display Level drop down menu at the bottom of the wi
295. logic is used to cascade the different stages of the macros Synchronous loading and count functions are packed in the same LUT primitive for optimal implementation For Up Down counters and accumulators XST uses the dedicated carry ANDs to improve the performance XST User Guide www xilinx com 199 1 800 255 7778 XILINX Chapter 3 FPGA Optimization Multiplexers For multiplexers the Macro Generator provides the following two architectures e MUXFx based multiplexers e Dedicated Carry MUXs based multiplexers For Virtex E MUXFx based multiplexers are generated by using the optimal tree structure of MUXF5 MUXF6 primitives which allows compact implementation of large inferred multiplexers For example XST can implement an 8 1 multiplexer in a single CLB In some cases dedicated carry MUXs are generated these can provide more efficient implementations especially for very large multiplexers For Virtex II Virtex II Pro Virtex II Pro X and Virtex 4 devices XST can implement a 16 1 multiplexer in a single CLB using a MUXF7 primitive and it can implement a 32 1 multiplexer across two CLBs using a MUXES To have better control of the implementation of the inferred multiplexer XST offers a way to select the generation of either the MUXF5 MUXF6 or Dedicated Carry MUXs architectures The attribute MUX_STYLE specifies that an inferred multiplexer be implemented on a MUXFx based architecture if the value is MUXE o
296. logic_bram_1 gt mapped on BRAM Device utilization summary Selected Devic 2v40cs144 6 Number of bonded IOBs 13 out of 88 14 Number of BRAMs 1 out of 4 25 Number of GCLKs 1 out of 16 6 In the following example an asynchronous reset is used instead of a synchronous one and so the logic is not mapped onto block RAM library ieee use ieee std_logic_1164 all use ieee numeric_std all entity no_logic_bram is port clk rst in std logic A B in unsigned 3 downto 0 RES out unsigned 3 downto 0 attribute bram map string attribute bram map of no logic bram entity is yes end no logic bram 206 www xilinx com XST User Guide 1 800 255 7778 Flip Flop Retiming XILINX architecture beh of no_logic_bram is begin process clk rst begin if rst 1 then RES 0000 elsif clk event and clk 1 then RES lt A B 0001 end if end process end beh VERILOG module no_vlogic_bram clk rst A B RES input clk rst input 3 0 A B output 3 0 RES reg 3 0 RES synthesis attribute bram map of no vlogic bram is yes always posedge clk or posedge rst begin if rst RES lt 4 b0000 else RES lt A B 8 b0001 end endmodule LOG Advanced HDL Synthesis INFO Xst 1789 Unable to map block no logic bram on BRAM Output FF RES must have a synchronous reset Flip Flop Retim
297. lt is begin RES lt A B end archi XST User Guide www xilinx com 115 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Following is the Verilog code for an unsigned 8x4 bit multiplier module compar A B RES input 7 0 A input 3 01 B output 11 0 RES assign RES A B endmodule Pipelined Multipliers To increase the speed of designs with large multipliers XST is capable of inferring pipelined multipliers By interspersing registers between the stages of large multipliers pipelining can significantly increase the overall frequency of your design The effect of pipelining is similar to flip flop retiming which is described in Flip Flop Retiming in Chapter 3 To insert pipeline stages describe the necessary registers in your HDL code and place them after any multipliers then set the MULT_STYLE constraint to pipe_lut If the target family is Virtex 4 and implementation of a multiplier requires multiple DSP48 blocks XST can pipeline this implementation as well You must set the MULT_STYLE constraint for this instance to pipe_block When XST detects valid registers for pipelining and MULT_STYLE is set to pipe_lut or pipe_block XST uses the maximum number of available registers to reach the maximum multiplier speed XST automatically calculates the maximum number of registers for each multiplier to get the best frequency If you have not specified sufficient register
298. m 31 0 reg 4 0 read addra reg 4 0 read addrb always 8 posedge clkl begin if we 1 begin ram addra lt di end read addra lt addra end assign doa ram read addra always 8 posedge clk2 begin read addrb lt addrb end assign dob ram read addrb endmodule Dual Port RAM with One Enable Controlling Both Ports The following descriptions are directly mappable onto block RAM as shown in the following figure ADDRA ADDRB DOA EN Block WB RAM DOB DI CLK V X9477 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs Z XILINX The following table shows pin descriptions for a dual port RAM with one enable controlling both ports IO Pins Description clk Positive Edge Clock en Primary Global Enable active High we Primary Synchronous Write Enable active High addra Write Address Primary Read Address addrb Dual Read Address di Primary Data Input doa Primary Output Port dob Dual Output Port VHDL Code Following is the VHDL code for a dual port RAM with one global enable controlling both ports library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic en in std_logic we in std_logic addra in std_logic_vector 4 downto 0 addrb in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 doa out std_logic_vector 3 downto 0 dob out std_logic_vector 3 downto 0 end
299. m std logic vector p width 2 1 downto 0 begin process clk begin if clk event and clk 1 then if reset 1 then accum lt others gt 0 mult lt others gt 0 else accum lt accum mult mult lt A B end if end if end process RES lt accum end beh www xilinx com 127 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Use the following templates to implement Multiplier Up Accumulate with Register After Multiplication in Verilog module mvl_macl clk reset A B RES input clk reset input 7 0 A input 7 0 B output 15 0 RES reg 15 0 mult accum always posedge clk begin if reset mult lt 16 50000000000000000 else mult lt A B end always posedge clk begin if reset accum lt 16 b0000000000000000 else accum lt accum mult end assign RES accum endmodule Multiplier Up Down Accumulate with Register After Multiplication VHDL Code Use the following templates to implement Multiplier Up Down Accumulate with Register After Multiplication in VHDL library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity m mac2 is generic p width integer 8 port Clk reset add sub in std logic A B in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end m mac2 128 www xi
300. m dpra end endmodule 152 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Dual Port RAM with Synchronous Read Read Through The following descriptions are directly mappable onto block RAM as shown in the following figure They may also be implemented with Distributed RAM DPRA WE DI Block SPO RAM DPO A CLK gt X8982 The following table shows pin descriptions for a dual port RAM with synchronous read read through 10 Pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Write Address Primary Read Address dpra Dual Read Address di Data Input spo Primary Output Port dpo Dual Output Port VHDL Code Following is the VHDL code for a dual port RAM with synchronous read read through library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk we a di spo dpo in std_logic in std_logic in std_logic_vector 4 downto 0 dpra in std_logic_vector 4 downto 0 in std_logic_vector 3 downto 0 out std_logic_vector 3 downto 0 out std logic vector 3 downto 0 end raminfr XST User Guide www xilinx com 153 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type signal read_a std_logic_vector 4 downto
301. mber of Clock Buffers option under the Xilinx Specific Options tab in the Process Properties dialog box Number of Regional Clock Buffers The Number of Regional Clock Buffers bufr constraint controls the maximum number of BUFRs created by XST The constraint value is an integer The default value depends on the target family and is equal to the maximum number of available BUFRs Define this option globally with the bufr command line option of the run command Following is the basic syntax bufr integer This constraint is available for Virtex 4 devices only The constraint value is an integer and the default value is different for each Virtex 4 device The number of BUFRs cannot exceed the maximum number of BUFRs for the target device In Project Navigator specify bufr globally by selecting the Number of Regional Clock Buffers option under the Xilinx Specific Options tab in the Process Properties dialog box Optimize Instantiated Primitives By default XST does not optimize instantiated primitives in HDL code The Optimize Instantiated Primitives OPTIMIZE PRIMITIVES constraint is used to deactivate the default See OPTIMIZE_PRIMITIVES in the Constraints Guide for details Pack I O Registers into IOBs The Pack I O Registers into IOBs IOB constraint packs flip flops in the I Os to improve input output path timing See IOB in the Constraints Guide for details Priority Encoder Extraction The Priority Enco
302. mechanism See Initializing Block RAM in Chapter 2 Initialization of dual port block RAMs in VHDL Initialization of single and dual port block RAMs in Verilog Support for Block RAM Block ROM initialization from an external text file See Initializing Block RAM in Chapter 2 Finite State Machine FSM Processing Support for Safe FSM implementation See Safe FSM Implementation in Chapter 2 Improved automatic FSM encoding selection Introduced new speed oriented encoding method called Speed1 See State Encoding Techniques in Chapter 2 and Constraints Summary in Chapter 5 Report of original and final FSM encoding See Chapter 9 Log File Analysis Introduced Automatic choice between standard and KCM implementation for multiplication with constants See Multiplication with Constant in Chapter 2 Support for CSD implementation for multiplication with constants See Multiplication with Constant in Chapter 2 Improved register balancing of multipliers XST can move registers with reset signal See Pipelined Multipliers in Chapter 2 Support for Macro inference for Virtex 4 devices and its control via USE_DSP48 constraint command line switch See Using DSP48 Block Resources in Chapter 3 Register balancing of DSP48 based multipliers for Virtex 4 devices See Pipelined Multipliers in Chapter 2 HDL Synthesis Report section of XST LOG file is now dis
303. mmands each command having various options XST recognizes the following commands e run e set e elaborate Run Command Following is a description of the run command e The command begins with a keyword run which is followed by a set of options and its values run option 1 value option 2 value e Each option name starts with dash For instance ifn ifmt ofn e Each option has one value There are no options without a value e The value for a given option can be one of the following Predefined by XST for instance yes or no Any string for instance a file name or a name of the top level entity There are options like vlgincdir that accept several directories as values The directories XST User Guide www xilinx com 383 1 800 255 7778 XILINX 384 Chapter 10 Command Line Mode must be separated by spaces and enclosed altogether by braces as in the following example vigincdir c vlg1 c vlg2 Please refer to Names with Spaces page 382 for more information An integer In the following tables you can find the name of each option and its values e First column the name of the options you can use in command line mode If the option is in bold it must be present in the command line e Second column the option description e Third column the possible values of this option The values in bold are the default values Note See Chapter 5 Des
304. mments 234 module declaration in 328 modules in 328 parameters in 343 primitives in 351 procedural assignments in 329 repeat loops in 331 reserved keywords in 352 sequential always blocks in 332 source options 385 while loops in 332 Verilog 2001 237 250 Verilog include directories 237 250 391 Verilog 2001 385 391 verilog2001 385 391 Verilog 2001 attribute 243 Verilog 2001 Support 353 VHDL attribute 242 attribute syntax 242 attributes 234 case statement in 302 combinatorial circuits 297 conditional signal assignment in 298 data types in 285 for loop statement in 303 generate statement in 298 if else statement in 301 language 283 language support 283 314 multi dimensional array types in 287 objects 291 objects in 291 operators 291 operators in 291 overloaded data types in 286 record types in 288 reserved word 320 selected signal assignment in 298 simple signal assignment in 297 source options 385 working directory 252 VHDL Verilog boundary rules 356 View Synthesis Report 27 Virtex 19 vlgcase 247 385 vlgincdir 250 385 391 W wait statement 318 what you see is what you get 386 What s New 19 while statement 349 work directory 237 252 390 work library 384 391 work_lib 384 391 write timing constraints 237 264 265 388 write_timing_constraints 264 277 388 wysiwyg 241 262 386 X xc_alias 281 xc_clockbuftype 281 xc_fast 281 282 xc_fast_auto 281 xc_global_buffers 281 xc_ioff
305. multiplier 113 pipelined multiplier 116 unsigned 8x4 bit multiplier 115 multiplier style 239 256 386 MUX 85 MUX extract 253 MUX extraction 238 239 386 MUX Style 238 MUX style 257 386 mux extract 85 253 270 386 mux style 257 270 386 N named events 348 names with spaces 382 native constraints 245 net naming conventions 399 net name 279 nets 348 NGC 227 231 381 no reduce 262 non blocking assignment 349 non timing constraints 245 noreduce 262 270 nounconnected drive 351 number of clock buffers 240 number of global clock buffers 257 number of regional clock buffers 240 O offset 266 offset in before 264 265 offset out after 264 265 ofmt 384 ofn 384 ohysical types 315 one cold 93 one hot 93 operator 317 opt level 249 270 384 opt mode 249 270 384 Optimization Effort 231 optimization effort 237 249 384 optimization goal 231 237 249 384 optimize instantiated primitives 240 257 387 optimize primitives 257 270 387 other XST command line options 237 242 XST User Guide www xilinx com 1 800 255 7778 403 XILINX output file format 384 output filename 384 overloaded data Types bit vector types 286 overloaded data types integer types 286 P p 384 pack I O registers into iob 387 pack I O registers into IOBs 257 package 315 packages 312 parallel block 349 parallel case 86 parallel_case 249 271 279 parameter 348 part select 341 period 266 pipe_l
306. must be coded in a particular way In Case statements do not use unsized integers in case item expressions as this causes unpredictable results In the following example the case item expression 4 is an unsized integer that causes unpredictable results To avoid problems size the 4 to 3 bits as shown below reg 2 0 conditionl always conditionl begin case conditionl 4 data_out 2 lt will generate bad logic 3 d4 data_out 2 lt will work endcase end 346 www xilinx com XST User Guide 1 800 255 7778 Verilog Meta Comments XILINX In concatenations do not use unsized integers as this causes unpredictable results If you must use an expression that results in an unsized integer assign the expression to a temporary signal and use the temporary signal in the concatenation as shown below reg 31 0 temp assign temp 4 b1111 2 assign dout 12 3 temp din Verilog Meta Comments XST supports meta comments in Verilog Meta comments are comments that are understood by the Verilog parser Meta comments can be used as follows e Set constraints on individual objects for example module instance net e Set directives on synthesis parallel case and full case directives translate on translate off directives all tool specific directives for example syn sharing refer to Chapter 5 Design Constraints for details Meta comments can be written using the C style
307. n 3 HDL Analysis 4 HDL Synthesis D Add Existing Source 5 Advanced HDL Synthesis E Create New Source 5 1 HDL Synthesis Report D View Design Summary 6 Low Level Synthesis f Design Utilities 7 Final Report H ce ppe 2 7 1 Device utilization summary iun lodelSim Simulator 7 2 TIMING REPORT E ef View Command Line Log File E View HDL Instantiation Template User Constraints CXV Smthesze XST B View Synthesis Report E View RTL Schematic Source Parameters E Vew Technology Schematic Input File Name fifoctir cc v2 prj Qe Check Syntax Input Format mixed O Generate Post Synthesis Simulation Mode Ignore Synthesis Constraint File NC Implement Design tu Q Translate Target Parameters Ma A SR o 2 VA p s hd Cal Design Sum fffoctir cc v E El console Eros Y Wamings Hierarchy is up to date lin 1Col 1 Text Figure 1 1 View Synthesis Report XST User Guide www xilinx com 27 1 800 255 7778 7 XILINX Chapter 1 Introduction 28 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Introduction XST User Guide This chapter contains the following sections e Introduction e Signed Unsigned Support e Registers e Latches e Tristates e Counters e Accumulators e Shift Registers e Dynamic Shift Register e Multiplexers e Decoders e Priority Encoders e Logical
308. n order to use these types the following two lines must be added to the VHDL specification library IEEE use IEEE STD LOGIC ARITH all Multi dimensional Array Types XST User Guide XST supports multi dimensional array types of up to three dimensions Arrays can be signals constants or VHDL variables You can do assignments and arithmetic operations with arrays You can also pass multi dimensional arrays to functions and use them in instantiations The array must be fully constrained in all dimensions An example is shown below subtype WORD8 is STD LOGIC VECTOR 7 downto 0 type TAB12 is array 11 downto 0 of WORD8 type TABO3 is array 2 downto 0 of TAB12 You can also declare an array as a matrix as in the following example subtype TAB13 is array 7 downto 0 4 downto 0 of STD LOGIC VECTOR 8 downto 0 The following examples demonstrate the various uses of multi dimensional array signals and variables in assignments Consider the declarations subtype WORD8 is STD LOGIC VECTOR 7 downto 0 type TABO5 is array 4 downto 0 of WORD8 type TABO3 is array 2 downto 0 of TABO5 signal WORD A WORD8 signal TAB A TAB B TABO5 signal TAB C TAB D TABO3 constant CST A TABO3 0000000 0000001 0000010 0000011 0000100 0010000 0010001 0010010 0100011 0010100 0100000 0100001 0100010 0100011 0100100
309. n directory to the newly created vhdl verilog directory hex2led v To synthesize the design which is now represented by six VHDL files and one Verilog file create a project To create a project file place a list of VHDL files preceded by keyword vhdl and a list of Verilog files preceded by keyword verilog in a separate file The order of the files is not important XST is able to recognize the hierarchy and compile HDL files in the correct order For our example 1 Openanew file called watchver prj 2 Enter the names of the files into this file in any order and save it vhdl work decode vhd vhdl work statmach vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd verilog work hex2led v 396 www xilinx com XST User Guide 1 800 255 7778 Example 3 How to Synthesize Mixed VHDL Verilog Designs Using Command Line Mode 7 XILINX Script Mode XST User Guide To synthesize the design execute the following command from the XST shell or via a script file run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 Note It is mandatory to specify the top level design block via the top command line switch If you want to synthesize just HEX2LED and check its performance independently of the other blocks you can specify it as the top level module to synthesize on the command line by using the t
310. n specify a text string to append to the end of the default name You can use the d escape character to specify where in the name the index number appears For example for the flip flop named my ff if you specify _dupreg_ d with the Duplication Suffix option XST generates the following names my ff dupreg 1 my ff dupreg 2 and my ff dupreg 3 Please note that d can be placed anywhere in the suffix definition For example if the Duplication Suffix value is specified as dup 7od reg XST generates the following names my ff dup 1 reg my ff dup 2 reg and my ff dup 3 reg Define this option globally with the duplication suffix command line option of the run command duplication suffix string dstring The default is _ d Note The duplication suffix option is not listed in the ISE Synthesis Properties dialog box You must specify it in the Other XST Command Line Options menu item Hierarchy Separator The Hierarchy Separator hierarchy separator command line option defines the hierarchy separator character that is used in name generation when the design hierarchy is flattened There are two supported characters and The default is for newly created projects If a design contains a sub block with instance INST1 and this sub block contains a net called TMP NET then the hierarchy is flattened and the hierarchy separator character is The name of TMP NET becomes INST1 TMP NET If the hierarchy separ
311. n std_logic_vector 15 downto 0 dol out std logic vector 15 downto 0 do2 out std logic vector 15 downto 0 end raminfr architecture syn of raminfr is type mem type is array 255 downto 0 of std logic vector 15 downto 0 signal mem mem type 255 downto 100 gt X B8B8 99 downto 0 gt X 8282 begin process clkl begin if rising edge clk1 then if we 1 then mem conv_integer addr1 lt di end if dol lt mem conv integer addr1 end if end process process clk2 begin if rising edge clk2 then do2 lt mem conv integer addr2 end if end process end syn XST User Guide www xilinx com 175 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques To initialize block RAM from values contained in an external file use a read function in your VHDL code Please refer to the File Type Support in Chapter 6 for more information Set up the initialization file as follows Use each line of the initialization file to represent the initial contents of a given row in the RAM RAM contents can be represented in binary or hexadecimal There should be as many lines in the file as there are rows in the block RAM array Below is a sample of the contents of a file initializing an 8 x 32 bit RAM with binary values 00001111000011110000111100001111 01001010001000001100000010000100 0000000001111100000000001000001 1111101010000011100010000100100 00011110000111
312. nal lt so gt Summary inferred 1 Combinational logic shifter s Unit lt lshift gt synthesized HDL Synthesis Report Macro Statistics Logic shifters fod 8 bit shifter logical left zd Related Constraints A related constraint is SHIFT EXTRACT Example 1 The following table shows pin descriptions for a logical shifter IO pins Description D 7 0 Data Input SEL Shift Distance Selector SO 7 0 Data Output 100 www xilinx com XST User Guide 1 800 255 7778 Logical Shifters XILINX VHDL Code Following is the VHDL code for a logical shifter library ieee use ieee std_logic_1164 all use ieee numeric_std all entity lshift is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 2 when 10 DI sll 3 when others end archi Verilog Code Following is the Verilog code for a logical shifter module lshift DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 2 b10 SO DI lt lt 2 default SO DI lt lt 3 endcase end endmodule Example 2 XST does not infer a logical shifter for this example as not all of the sel
313. ndow and click Advanced When working with Virtex 4 devices Use DSP48 replaces Multiplier Style on in this dialog box For CPLD device families the following dialog box displays Process Properties A Synthesis Options HDL Options Xtinx Specific Options Cancel D efault Help Figure 5 4 HDL Options Tab CPLDs Following is a list of all HDL Options that can be set within the HDL Options tab of the Process Properties dialog box for CPLD devices XST User Guide FSM Encoding Algorithm Safe Implementation Case Implementation Style Mux Extraction Resource Sharing www xilinx com 239 1 800 255 7778 XILINX 240 Xilinx Specific Options From the Process Properties dialog box for the Synthesize XST process select the Xilinx Specific Options tab to display the options Chapter 5 Design Constraints For FPGA device families the following dialog box displays Process Properties x Synthesis Options HDL Options Xiinx Specific Options ok Cancel bs Hep Figure 5 5 Xilinx Specific Options FPGAs Following is the list of the Xilinx Specific Options for FPGAs Add I O Buffers Max Fanout Number of Global Clock Buffers Number of Regional Clock Buffers Register Duplication Equivalent Register Removal Register Balancing Move First Stage Move Last Stage Convert Tristates to Logic Use Clock Enable Use Synchro
314. net in model signal signal Virtex M TI II Pro inst in model FF instance FF instance II Pro X E 4 name name use dsp48 auto yes no model entity module yes auto yes no Virtex 4 true false net in model signal signal use sync reset auto yes no model entity module yes auto yes no Spartan II IIE 3 true false net in model signal signal Virtex M TI II Pro inst in model FF instance FF instance II Pro X E 4 name name 272 www xilinx com 1 800 255 7778 XST User Guide Constraints Summary XILINX Table 5 1 XST Specific Non timing Options XCF Constraint Consiraint Constraint VHDL Verilog ins Cmd Technology Name Value Syntax Target Target Value Target use sync set auto yes no model entity module yes auto yes no Spartan II TIE 3 true false net in model signal signal Virtex M TI II Pro inst in model FF instance FF instance II Pro X E 4 name name uselowskewlines yes no net in model signal signal no na Spartan T TIE 3 true false VirtexTM TI II Pro II Pro X E 4 xor collapse yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro Il Pro X E 4 XST Command Line Only Options bufg na na na na yes integer XC9500 CoolRunner XPLA3 II bufr na na na na yes integer Virtex 4 bus_delimiter na na na na yes lt
315. net in model type signal no na Spartan TI TIE 3 containing VirtexTM TI II Pro space separated II Pro X E 4 binary codes XC9500 CoolRunner XPLA3 II equivalent register yes no model entity module yes yes no Spartan TI TIE 3 removal true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II 268 www xilinx com XST User Guide 1 800 255 7778 Constraints Summary XILINX Table 5 1 XST Specific Non timing Options XCF Cmd Constraint Constraint Constraint VHDL Verilog Cmd Technology Line Name Value Syntax Target Target Value Target fsm encoding auto one hot model entity module yes auto Spartan I TIE 3 compact net in model signal signal one hot VirtexTM TI II Pro sequential compact II Pro X E 4 gray johnson sequential XC9500 speed1 user gray CoolRunner johnson XPLA3 II speed1 user fsm_extract yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II fsm_style lut bram model entity module yes lut bram Spartan I TIE 3 net in model signal signal Virtex TI TI Pro II Pro X E 4 full case na na case case no na Spartan I TIE 3 statement statement Virtex M TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II
316. ng on the command line then use the XCF file to specify exceptions to these general constraints The constraints specified in the XCF file are applied ONLY to the module listed and not to any submodules below it www xilinx com XST User Guide 1 800 255 7778 XST Constraint File XCF XILINX To apply a constraint to the entire entity module use the following syntax MODEL entityname constraintname constraintvalue Examples MODEL top mux extract false MODEL my design max fanout 256 Note f the entity my design is instantiated several times in the design the max anout 256 constraint is applied to each instance of my design To apply constraints to specific instances or signals within an entity module use the INST or NET keywords BEGIN MODEL entityname INST instancename constraintname constraintvalue NET signalname constraintname constraintvalue END Examples BEGIN MODEL crc32 INST stopwatch opt mode area INST U2 ram style block NET myclock clock buffer true NET data in iob true END See Constraints Summary for the complete list of synthesis constraints that you can apply for XST Native vs Non Native UCF Constraints Syntax From a UCF syntax point of view all constraints supported by XST can be divided into two groups native UCF constraints and non native UCF constraints Only Timing and Area Group constraints use native UCF syntax
317. nisim vcomponents all entity single_stage is generic sh_st integer 4 port CLK in std_logic DI in std_logic DO out std_logic end entity single_stage 294 www xilinx com XST User Guide 1 800 255 7778 Entity and Architecture Descriptions 7 XILINX architecture recursive of single_stage is component single_stage generic sh_st integer port CLK in std_logic DI in std logic DO out std logic end component signal tmp std logic begin GEN FD LAST if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q DO end generate GEN FD INTERM if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q gt tmp inst sstage single stage generic map sh st gt sh st 1 port map DI gt tmp CLK gt CLK DO gt DO end generate end recursive Component Configuration Associating an entity architecture pair to a component instance provides the means of linking components with the appropriate model entity architecture pair XST supports component configuration in the declarative part of the architecture for instantiation_list component_name use LibName entity_Name Architecture_Name Example 6 2 Structural Description of a Half Adder shows how to use a configuration clause for component instantiation The example contains the following for all statement for all NAND2 use entity work NAND2 ARCHI This statement indicates that all NAN
318. nl en2 in std logic addr1 in std logic vector 6 downto 0 addr2 in std logic vector 6 downto 0 di in std logic vector 7 downto 0 resl out std_logic_vector 7 downto 0 res2 out std_logic_vector 7 downto 0 end raminfr architecture beh of raminfr is type mem type is array 127 downto 0 of std logic vector 7 downto 0 signal mem mem type signal dol std logic vector 7 downto 0 signal do2 std logic vector 7 downto 0 begin process clkl begin if rising edge clk1 then if we 1 then mem conv integer addrl lt di end if dol lt mem conv integer addr1 end if end process process clk2 begin if rising edge clk2 then do2 lt mem conv integer addr2 end if end process process clkl begin if rising edge clk1 then if enl 1 then resl lt dol end if end if end process XST User Guide www xilinx com 171 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques process clk2 begin if rising edge clk2 if en2 1 then res2 do2 end if end if end process end beh Verilog Code module raminfr clk1 clk2 we input clk1 input clk2 input we enl en2 input 6 0 addr1 input 6 0 addr2 input 7 0 di output 7 0 resl output 7 0 res2 reg 7 0 resl reg 7 0 res2 reg 7 0 RAM 127 0 reg 7 0 dol reg 7 0 do2 always 8 posedge clk1 begin if we 1 b1 RAM addrl lt di dol lt
319. nous Set Use Synchronous Reset Optimize Instantiated Primitives www xilinx com 1 800 255 7778 XST User Guide Setting Global Constraints and Options XILINX To view these options go the Property Display Level drop down menu at the bottom of the window and click Advanced Convert Tristate to Logic only appears when working with applicable devices For CPLD device families the following dialog box displays Process Properties x Synthesis Options HDL Options Xilinx Specific Options Figure 5 6 Xilinx Specific Options CPLDs Following is a list of the Xilinx Specific Options XST User Guide Add I O Buffers Equivalent Register Removal Clock Enable Macro Preserve XOR Preserve WYSIWYG www xilinx com 1 800 255 7778 241 7 XILINX Chapter 5 Design Constraints Other XST Command Line Options Any XST command line option can be set via the Other XST Command Line Options property in the Process Properties dialog box This is an advanced property Use the syntax described in Chapter 10 Command Line Mode Separate multiple options with a space While the Other XST Command Line Options property is intended for XST options not listed in the Process Properties dialog box if an option already listed as a dialog box property is entered precedence is given to the option entered here Illegal or unrecognized options cause XST to stop processing and generate a message lik
320. nsigned operation Verilog Code Following is the Verilog code for an unsigned 8 bit adder with carry out module adder A B SUM CO input 7 0 A input 7 0 B output 7 0 SUM output CO wire 8 0 tmp assign tmp A B assign SUM tmp 7 0 assign CO tmp 8 endmodule XST User Guide www xilinx com 107 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Unsigned 8 bit Adder with Carry In and Carry Out The following table shows pin descriptions for an unsigned 8 bit adder with carry in and carry out 10 pins Description A 7 0 B 7 0 Add Operands CI Carry In SUM 7 0 Add Result CO Carry Out VHDL Code Following is the VHDL code for an unsigned 8 bit adder with carry in and carry out library ieee use ieee use ieee use ieee std logic unsigned all std logic 1164 all std logic arith all entity adder is port A B CI SUM CO in std logic in std logic vector 7 downto 0 out std logic vector 7 downto 0 out std logic end adder architecture archi of adder is signal begin tmp std logic vector 8 downto 0 tmp lt conv std logic vector conv integer A conv integer B conv integer CI 9 SUM tmp 7 downto 0 CO lt tmp 8 end archi Verilog Code Following is the Verilog code for an unsigned 8 bit adder with carry in and carry out module adder A B CI input input
321. nstraint File XCF Table 5 3 XST Timing Constraints Supported Only in XCF Name Value Target Technology period See the See the Spartan II IE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E 4 details details offset See the See the Spartan TI IIE 3 Constraints Constraints Virtex M TI II Pro Guide for Guide for II Pro X E 4 details details timespec See the See the Spartan II IIE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E 4 details details tsidentifier See the See the Spartan II IIE 3 Constraints Constraints Virtex TI TI Pro Guide for Guide for II Pro X E 4 details details tmn See the See the Spartan IT TE 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E 4 details details tnm_net See the See the Spartan II 11E 3 Constraints Constraints Virtex TI TI Pro Guide for Guide for II Pro X E 4 details details timegrp See the See the Spartan I1 11E 3 Constraints Constraints Virtex TI II Pro Guide for Guide for II Pro X E 4 details details tig See the See the Spartan ITE 3 Constraints Constraints Virtex M TI II Pro Guide for Guide for II Pro X E 4 details details from to See the See the Spartan I1 11E 3 Constraints Constraints Virtex TI TI Pro Guide for Guide for II Pro X E 4 details details 276 www xilinx com
322. nsupported Table 7 4 Data Types wire Supported tri Supported supply0 Supported net type supply1 Nets wand wor Supported triand trior tri tril Unsupported trireg drive Ignored strength reg Supported integer Supported Registers real Unsupported realtime Unsupported net Supported reg Supported Epor vectored Supported scalared Supported Multi Supported Dimensional Arrays 23 dimensions Parameters Supported Named Events Unsupported www xilinx com 1 800 255 7778 XST User Guide Verilog Language Support Tables Table 7 5 Continuous Assignments Drive Strength Ignored Delay Ignored Table 7 6 Procedural Assignments Blocking Assignments Supported Non Blocking Assignments Supported assign Supported with dence limitations See CASSIEN Assign and Deassign Continuous Procedural Statements Assi t SEEMS force Unsupported release Unsupported if Statement if if else Supported case Statement case casex Supported casez forever Statement Unsupported repeat Statement Supported repeat value must be constant while Statement Supported for Statement Supported bounds must be static fork join Statement Unsupported delay Ignored event Unsupported pe ecd on Procedural Wal Unsupported named events Unsupported Sequential Blocks Supported Parallel Blocks Unsupported Specify Blocks Ignored
323. nthesizing Unit lt flop gt Related source file is ff_l vhd Found 1 bit register for signal lt q gt Summary inferred 1 D type flip flop s Unit lt flop gt synthesized HDL Synthesis Report Macro Statistics Registers 1 bit register XST User Guide www xilinx com 41 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Related Constraints Related constraints are IOB REGISTER_DUPLICATION EQUIVALENT REGISTER REMOVAL REGISTER_BALANCING Flip flop with Positive Edge Clock The following figure shows a flip flop with positive edge clock X3715 The following table shows pin definitions for a flip flop with positive edge clock 10 Pins Description D Data Input C Positive Edge Clock Q Data Output VHDL Code Following is the equivalent VHDL code sample for the flip flop with a positive edge clock library ieee use ieee std_logic_1164 all entity flop is port C D in std logic Q out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then Q lt D end if end process end archi When using VHDL for a positive edge clock instead of using if C event and C 1 then you can also use if rising edge C then 42 www xilinx com XST User Guide 1 800 255 7778 Registers XILINX Verilog Code Following is the equivalent Verilog code sample for the flip flop with a posit
324. nts globally with the write timing constraints command line option of the run command Following is the basic syntax write timing constraints yes no The default is no not to write timing constraints to the NGC file In Project Navigator specify this option globally with the Write Timing Constraints option in the Synthesis Options tab of the Process Properties dialog box Clock Signal If a clock signal goes through combinatorial logic before being connected to the clock input of a flip flop XST cannot identify what input pin or internal signal is the real clock signal The CLOCK SIGNAL constraint allows you to define the clock signal See CLOCK SIGNAL in the Constraints Guide for details Global Timing Constraints Support XST supports the following global timing constraints 264 Global Optimization Goal XST can optimize different regions register to register inpad to register register to outpad and inpad to outpad of the design depending on the global optimization goal Please refer to Incremental Synthesis Flow in Chapter 3 for a detailed description of supported timing constraints The Global Optimization Goal glob opt command line option selects the global optimization goal Note You cannot specify a value for Global Optimization Goal glob opt XST optimizes the entire design for the best performance The following constraints can be applied by using the Global Optimization Goal option ALLCLOCKNETS
325. o 0 SO out unsigned 7 downto 0 end lshift architecture archi of lshift is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 3 when 10 DI sll 2 when others end archi Verilog Code Following is the Verilog code module lshift DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO E always Q DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 2 b10 SO DI lt lt 3 default SO DI lt lt 2 endcase end endmodule XST User Guide www xilinx com 103 1 800 255 7778 XILINX Chapter 2 HDL Coding Techniques Arithmetic Operations 104 XST supports the following arithmetic operations e Adders with Carry In Carry Out Carry In Out e Subtractors e Adders Subtractors e Comparators lt lt gt gt e Multipliers e Dividers Adders subtractors comparators and multipliers are supported for signed and unsigned operations Please refer to Signed Unsigned Support in this chapter for more information on the signed unsigned operations support in VHDL Moreover XST performs resource sharing for adders subtractors adders subtractors and multipliers Adders Subtractors Adders Subtractors This section provides HDL examples of adders and subtractors Log File The XST log file reports the type and size of recognized adder subtractor and adder
326. o d sone eae 130 Resource Sharing vcd la Bede shh RE EE Se beds pa ate cd 131 Log Files Mp P 132 Related Constraint ira cia a ERREUR RES REPARARE Tee RE Ee Eu 132 ioci p AA AAA RS 132 RAMS ROMS ui dai A 134 A O OO 135 Related Constraints A Deer cse re gp E 135 Virtex II Spartan 3 RAM Read Write Modes 00 00 cece 136 Read First Mode iile aegra REALI a hee ea ar ed 136 WritesFitst Mode oem esc ed ete Boe dew Bk qn CR TR Red ee Ro os 137 No Charige Mode iie tea bre Coa xp AERE EE RE Ode d e eroe 139 Single Port RAM with Asynchronous Read ooooococooccccccoccrracccn 141 VEIDL Code ivi Yay nx PX dd Ede a Edd 142 MJRRIe rm 142 Single Port RAM with False Synchronous Read 0 00 c cece e eee 143 VOD Li oe er E EA a ee ae ee ae 143 MS A ROO an ae a a a aiaee arai ae 144 use P 145 Verlo Code ie cup pee E p ee dd ib at 146 Single Port RAM with Synchronous Read Read Through 146 VHDL Code void id a ba Rd hx a p HERO EU Rd heed tek 147 MOJgRple rm 147 Single Port RAM with Enable ssssssssseese e 148 ae rv 148 Verilog Code 4i edema tette eminet cade need dece baee d prede 149 Dual Port RAM with Asynchronous Read ooooooccccocoocccncrrccc 149 VEIDL Gode ui eecp bik peer e RP Re Re d RC A Wee 150 Verilog Codeso iuto sq ete qr e EP eu eeu del ada Qin uon 151 Dual Port RAM with False Synchronous Read 0 6 nananana rn eee eee 151 Ad UD Bee Gos r aerate mr mr a
327. o reduce the number of levels without increasing the complexity beyond certain limits e Optimization Goal Speed the priority is the reduction of number of levels The following tries in this order may give successively better results for frequency Try 1 Select only optimization effort 2 and speed optimization The other options have default values e Optimization effort 2 or High e Optimization Goal Speed Try 2 Flatten the user hierarchy In this case the optimization process has a global view of the design and the depth reduction may be better e Optimization effort 1 Normal or 2 High e Optimization Goal Speed e Keep Hierarchy no XST User Guide www xilinx com 231 1 800 255 7778 XILINX Chapter 4 CPLD Optimization Try 3 Merge the macros with surrounded logic The design flattening is increased e Optimization effort 1 or Normal e Optimization Goal Speed e Keep Hierarchy no e Macro Preserve no Try 4 Apply the equation shaping algorithm Options to be selected e Optimization effort 2 or High e Macro Preserve no e Keep Hierarchy no The CPU time increases from Try 1 to Try 4 Obtaining the best frequency depends on the CPLD fitter optimization Xilinx recommends running the multi level optimization of the CPLD fitter with different values for the pterms options starting with 20 and finishing with 50 with a step of 5 Statistically the value 30 gives the best results for frequency H
328. ock edge Such descriptions are directly mappable onto block RAM as shown below The same descriptions can also be mapped onto Distributed RAM WE _ DI Block DO A RAM cLK gt X8979 The following table shows pin descriptions for a single port RAM with synchronous read read through 10 pins Description clk Positive Edge Clock we Synchronous Write Enable Active High a Read Write Address di Data Input do Data Output 146 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX VHDL Code Following is the VHDL code for a single port RAM with synchronous read read through library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic a in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read a std logic vector 4 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if read a lt a end if end process do lt RAM conv integer read a end syn Verilog Code Following is the Verilog code for a single port RAM with synchronous read read through module raminfr clk we a d
329. ode Following is the VHDL code for a 4 bit signed up counter with an asynchronous reset library ieee use ieee std_logic_1164 all use ieee std_logic_signed all entity counter is port C CLR in std_logic Q out std logic vector 3 downto 0 end counter architecture archi of counter is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit signed up counter with an asynchronous reset module counter C CLR Q input C CLR output signed 3 0 Q reg signed 3 0 tmp always posedge C or posedge CLR begin if CLR tmp 4 b0000 else tmp tmp 1 b1 end assign Q tmp endmodule XST User Guide www xilinx com 65 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum The following table shows pin definitions for a 4 bit signed up counter with an asynchronous reset and a modulo maximum 10 Pins Description C Positive Edge Clock CLR Asynchronous Clear active High Q 7 0 Data Output VHDL Code Following is the VHDL code for a 4 bit signed up counter with an asynchronous reset and a maximum using the VHDL mod function library ieee use ieee std logic 1164 all use ieee std logic ari
330. of the behavioral features of Verilog Variable Declaration 322 Variables in Verilog may be declared as integers or real These declarations are intended only for use in test code Verilog provides data types such as reg and wire for actual hardware description The difference between reg and wire is whether the variable is given its value in a procedural block reg or in a continuous assignment wire Verilog code Both reg and wire have a default width being one bit wide scalar To specify an N bit width vectors for a declared reg or wire the left and right bit positions are defined in square brackets separated by a colon In Verilog 2001 both reg and wire data types can be signed or unsigned Example reg 3 0 arb_priority wire 31 0 arb_request wire signed 8 0 arb_signed where arb_request 31 is the MSB and arb_request 0 is the LSB Initial Values In Verilog 2001 you can initialize registers when you declare them The value e Must be a constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to the register When you give a register an initial value in a declaration XST sets this value on the output of the register at global reset or at power up A value assigned this way is carried in the NGC file as an INIT attribute on the register and is independent of any local reset Example reg arb_onebit 1 b0 reg 3 0 arb_priority
331. ogic This process of initialization is the same for both registers and RAMs Where possible XST adheres to the IEEE VHDL standard when initializing signal values If no initial values are supplied in the VHDL code XST uses the default values where possible as outlined in the XST column in Table 6 2 Table 6 2 Initial Values Type IEEE XST bit 0 0 std_logic U 0 bit_vector 3 downto 0 0000 0000 std_logic_vector 0000 0000 3 downto 0 integer unconstrained integer left integer left integer range 7 downto 0 integer left 7 integer left 7 coded as 111 integer range 0 to 7 integer left 0 integer left 0 coded as 000 Boolean FALSE FALSE coded as 0 enum S0 S1 S2 S3 typeleft S0 typeleft SO coded as 000 290 www xilinx com XST User Guide 1 800 255 7778 Objects in VHDL XILINX Default Initial Values on Unconnected Ports Output ports that are left unconnected default to the values noted in the XST column of Table 6 2 If the output port has an initial condition XST ties the unconnected output port to the explicitly defined initial condition According to the IEEE VHDL specification input ports cannot be left unconnected As a result XST always gives an error if an input portis not connected even the open keyword will not suffice for an unconnected input port Objects in VHDL VHDL objects include signals variables and c
332. ogic_vector 4 downto 0 dpra in std_logic_vector 4 downto 0 di in std_logic_vector 3 downto 0 spo out std logic vector 3 downto 0 dpo out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if end if end process spo lt RAM conv integer a dpo lt RAM conv integer dpra end syn 150 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Verilog Code Following is the Verilog code for a dual port RAM with asynchronous read module raminfr clk we a dpra di spo dpo input clk input we input 4 0 a input 4 0 dpra input 3 0 di output 3 0 spo output 3 0 dpo reg 3 0 ram 31 0 always posedge clk begin if we ram a lt di end assign spo ramla assign dpo ram dpra endmodule Dual Port RAM with False Synchronous Read The following description is mapped onto Distributed RAM with additional registers on the data outputs Please note that this template does not describe dual port block RAM SPO Distributed IVA DPO NA X8981 The following table shows pin descriptions for a dual port RAM with false synchronous read IO Pins Description clk Positive Edg
333. olvers Interactive tools that allow you to troubleshoot your design issues http www xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www xilinx com xlnx xil tt home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Literal ends mat you ngdbuild design_name enter in a syntactical statement iced that you select File gt Open Helvetica bold SEA Keyboard shortcuts Ctrl C 4 www xilinx com XST User Guide 1 800 255 7778 Conventions XILINX Convention Italic font Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items
334. om Primary Input The following table shows pin definitions for a 4 bit unsigned up counter with an asynchronous load from the primary input IO Pins Description C Positive Edge Clock ALOAD Asynchronous Load active High D 3 0 Data Input Q 3 0 Data Output VHDL Code Following is the VHDL code for a 4 bit unsigned up counter with an asynchronous load from the primary input library ieee use leee std_logic_1164 all use ieee std_logic_unsigned all entity counter is port C ALOAD in std_logic D in std_logic_vector 3 downto 0 Q out std logic vector 3 downto 0 end counter XST User Guide www xilinx com 59 1 800 255 7778 60 7 XILINX Chapter 2 HDL Coding Techniques architecture archi of counter is signal tmp std_logic_vector 3 downto 0 begin process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp lt tmp 1 end if end process Q lt tmp end archi Verilog Code Following is the Verilog code for a 4 bit unsigned up counter with an asynchronous load from the primary input module counter C ALOAD D 0 input C ALOAD input 3 0 D output 3 0 Q reg 3 0 tmp always G posedge C or posedge ALOAD begin if ALOAD tmp lt D else tmp lt tmp 1 b1 end assign Q tmp endmodule 4 bit Unsigned Up Counter with Synchronous Load with a Constant The following table shows pin definitions
335. om tristates can be combined and optimized with surrounding logic the replacement of internal tristates by logic for other devices can lead to better speed and in some cases better area optimization In some situations XST cannot make the tristate to logic replacement automatically as it may lead to wrong design behavior or to multi sources This can happen when the hierarchy is preserved or XST does not have full design visibility for example when the design is synthesized on a block by block basis In these cases XST issues a warning message during the Low Level Optimization step Depending on the design situation you can continue the design flow and the replacement can be done by MAP or you can force the replacement by applying the TRISTATE2LOGIC constraint set to yes ona particular block or signal See TRISTATE2LOGIC in the Constraints Guide for details Use Clock Enable The Use Clock Enable USE_CLOCK_ENABLE constraint enables or disables the use of the clock enable function in flip flops The disabling of the clock enable function is typically used for ASIC prototyping on FPGAs See USE_CLOCK_ENABLE in the Constraints Guide for details Use Synchronous Set The Use Synchronous Set USE_SYNC_SET constraint enables or disables the use of synchronous set function in flip flops The disabling of the synchronous set function is typically used for ASIC prototyping on FPGAs See USE_SYNC_SET in the Constraints Guide f
336. onous clear 10 Pins Description D Data Input G Positive Gate CLR Asynchronous Clear active High Q Data Output VHDL Code Following is the equivalent VHDL code for a latch with a positive gate and an asynchronous clear library ieee use ieee std_logic_1164 all entity latch is port G D CLR in std_logic Q out std logic end latch architecture archi of latch is begin process CLR D G begin if CLR 1 then Q lt 407 elsif G 1 then Q lt D end if end process end archi Verilog Code Following is the equivalent Verilog code for a latch with a positive gate and an asynchronous clear module latch G D CLR Q input G D CLR output Q reg Q always G or D or CLR begin if CLR Q lt 1 b0 else if G Q lt D end endmodule XST User Guide www xilinx com 51 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 4 bit Latch with Inverted Gate and Asynchronous Preset The following figure shows a 4 bit latch with an inverted gate and an asynchronous preset PRE X8376 The following table shows pin definitions for a latch with an inverted gate and an asynchronous preset 10 Pins Description D 3 0 Data Input G Inverted Gate PRE Asynchronous Preset active High Q 3 0 Data Output VHDL Code Following is the equivalent VHDL code for a 4 bit latch with an inverted gate and an asynchronous pr
337. onstants Signals can be declared in an architecture declarative part and used anywhere within the architecture Signals can also be declared in a block and used within that block Signals can be assigned by the assignment operator lt Example signal sigl std_logic sigl lt 1 Variables are declared in a process or a subprogram and used within that process or that subprogram Variables can be assigned by the assignment operator Example variable varl std_logic_vector 7 downto 0 varl 01010011 Constants can be declared in any declarative region and can be used within that region Their value cannot be changed once declared Example signal sigl std_logic_vector 5 downto 0 constant init0 std logic vector 5 downto 0 010111 sigl lt init0 Operators Supported operators are listed in Table 6 9 This section provides an example of how to use each shift operator Example sll Shift Left Logical sigl lt A 4 downto 0 sll 2 logically equivalent to sigl lt A 2 downto 0 amp 00 Example srl Shift Right Logical sigl lt A 4 downto 0 srl 2 logically equivalent to sigl lt 00 amp A 4 downto 2 XST User Guide www xilinx com 291 1 800 255 7778 XILINX Example sla Shift Left Arithmetic sigl lt A 4 downto 0 sla 2 logically equivalent to sigl lt A 2 downto 0 A 0 A 0 Example sra Shift Right Arithmetic sig
338. onstrained vectors in component declarations Example 6 2 gives the structural description of a half adder composed of four nand2 components Example 6 2 Structural Description of a Half Adder entity NAND2 is port A B in BIT Y Out BIT end NAND2 architecture ARCHI of NAND2 is begin Y lt A nand B end ARCHI entity HALFADDER is port X Y i in BIT C S out BIT end HALFADDER XST User Guide www xilinx com 293 1 800 255 7778 XILINX Chapter 6 VHDL Language Support architecture ARCHI of HALFADDER is component NAND2 port A B in BIT Y QUE BLE end component for all NAND2 use entity work NAND2 ARCHI signal S1 S2 S3 BIT begin NANDA NAND2 port map X Y S3 NANDB NAND2 port map X S3 S1 NANDC NAND2 port map S3 Y S2 NANDD NAND2 port map S1 S2 S C lt 83 end ARCHI The synthesized top level netlist is shown in the following figure X A O 1 NANDB Y B A A NANDA Y S3 NANDD Y Os B B A NANDC Y re y Q B Llc X8952 Figure 6 1 Synthesized Top Level Netlist Recursive Component Instantiation XST supports recursive component instantiation please note that direct instantiation is not supported for recursivity Example 6 3 shows a 4 bit shift register description Example 6 3 4 bit shift register with Recursive Component Instantiation library ieee use leee std_logic_1164 all library unisim use u
339. op option please refer to Table 10 3 page 385 for more information run ifn watchver prj ifmt mixed top hex2led ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 It can be very tedious work entering XST commands directly into the XST shell especially when you have to specify several options and execute the same command several times You can run XST in a script mode as follows 1 Open a new file called xst t xt in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 From the tcsh or other shell enter the following command to start synthesis xst ifn stopwatch xst During this run XST creates the following files watchver ngc an NGC file ready for the implementation tools xst srp the xst script log file If you want to save XST messages in a different log file for example wat chver 1log execute the following command xst ifn stopwatch xst ofn watchver log You can improve the readability of the xst scr file especially if you use many options to run synthesis You can place each option with its value on a separate line respecting the following rules The first line must contain only the run command without any options There must be no blank lines in the middle of the command Each line except the first one m
340. or Dual Port Synchronous Distributed RAM For Virtex II Virtex II Pro Virtex II Pro X Virtex 4 and Spartan 3 devices XST uses the following primitives e For Single Port Synchronous Distributed RAM For Distributed Single Port RAM with positive clock edge RAM16X1S RAM16X2S RAM16X4S RAM16X8S RAM32X1S RAM32X2S RAM32X4S RAM32X85 RAM64X1S RAM64X2S RAMI128X1S For Distributed Single Port RAM with negative clock edge RAM16X1S_1 RAM16X25_1 RAM16X4S_1 RAM16X85_1 RAM32X15_1 RAM32X25_1 RAM32X45_1 RAM32X85_1 RAM64X1S_1 RAM64X2S_1 RAMI28XIS 1 e For Dual Port Synchronous Distributed RAM For Distributed Dual Port RAM with positive clock edge RAM16X1D RAM32X1D RAM64X1D For Distributed Dual Port RAM with negative clock edge RAM16X1D_1 RAM32X1D_1 RAM64X1D_1 www xilinx com 201 1 800 255 7778 XILINX 202 ROMs Chapter 3 FPGA Optimization For block RAM XST uses e RAMBA Sn primitives for Single Port Synchronous Block RAM e RAMB4 8m 5n primitives for Dual Port Synchronous Block RAM In order to have better control of the implementation of the inferred RAM XST offers a way to control RAM inference and to select the generation of distributed RAM or block RAMs if possible The RAM_STYLE attribute specifies that an inferred RAM be generated using e Block RAM if the value is block e Distributed RAM if the value is distributed You can apply the RAM STYLE attribute either to
341. or can be up down or updown For an updown accumulator the accumulated data may differ between the up and down mode if updown 1 then a lt a t b else a lt a CG XST can infer an accumulator with the same set of control signals available for counters Refer to Counters in this chapter for more details XST User Guide www xilinx com 67 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Log File The XST log file reports the type and size of recognized accumulators during the Macro Recognition step Synthesizing Unit lt accum gt Related source file is accumulators 1l vhd Found 4 bit up accumulator for signal tmp Summary inferred 1 Accumulator s Unit accum synthesized HDL Synthesis Report Macro Statistics 4 Accumulators sU 4 bit up accumulator fo Note During synthesis XST decomposes Accumulators on Adders and Registers if they do not contain synchronous load signals This is done to create additional opportunities for timing optimization Because of this Accumulators reported during the Macro Recognition step and in the overall statistics of recognized macros may not appear in the final report Adders registers are reported instead Related Constraints Related constraints are USE DSP48 and KEEP which are available for Virtex 4 devices 4 bit Unsigned Up Accumulator with Asynchronous Clear The following table shows pin definitions for a 4 bit
342. or details Use Synchronous Reset The Use Synchronous Reset USE_SYNC_RESET constraint enables or disables the usage of synchronous reset function of flip flops The disabling of the Synchronous Reset function could be used for ASIC prototyping flow on FPGAs See USE_SYNC_RESET in the Constraints Guide for details Use DSP48 XST enables you to use the resources of the DSP48 blocks introduced in Virtex 4 devices You can control the use of these resources globally for all modules in the entire design by using the use_dsp48 option of the run command See USE_DSP48 in the Constraints Guide for details CPLD Constraints non timing This section lists options that only apply to CPLDs not FPGAs 260 Note Please note that in many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances See Table 5 1 for valid constraint targets Clock Enable The Clock Enable pld_ce constraint specifies how sequential logic should be implemented when it contains a clock enable either using the specific device resources available for that or generating equivalent logic This option allows you to specify the way the clock enable function will be implemented if presented in the design Two values are available www xilinx com XST User Guide 1 800 255 7778 CPLD Constraints non timing XILINX XST User Guide
343. or this purpose for lin 1 to N generate means that the bit slice description is repeated N times As an example Example 6 7 gives a description of an 8 bit adder by declaring the bit slice structure 298 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits XILINX Example 6 7 8 Bit Adder Described with a for generate Statement entity EXAMPLE is port A B in BIT VECTOR 0 to 7 CIN in BIT SUM out BIT VECTOR 0 to 7 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT VECTOR 0 to 8 begin C 0 lt CIN COUT C 8 LOOP ADD for I in 0 to 7 generate SUM I lt A I xor B I xor C I C 1 1 lt A I and B I or A I and C I or B I and C I end generate end ARCHI The if condition generate statement is supported for static non dynamic conditions Example 6 8 shows such an example It is a generic N bit adder with a width ranging between 4 and 32 Example 6 8 N Bit Adder Described with an if generate and a for generate Statement entity EXAMPLE is generic N INTEGER 8 port A B in BIT VECTOR N downto 0 CIN in BIT SUM out BIT VECTOR N downto 0 COUT s out BIT Jz end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT VECTOR N 1 downto 0 begin L1 if N gt 4 and N lt 32 gener
344. ores represented by an EDIF or an NGC file XST can automatically read them for timing estimation and area utilization control The Read Cores option in the Synthesis Options in the Process Properties dialog box in Project Navigator allows you to enable or disable this feature Using the read cores option of the run command from the command line you can also specify optimize This enables cores processing and allows XST to integrate the core netlist into the overall design By default XST reads cores In the following VHDL example the block my add is an adder which is represented as a black box in the design whose netlist was generated by CORE Generator library ieee use ieee std logic 1164 a1 use ieee std logic signed all entity read cores is port A B in std logic vector 7 downto 0 al bl in std logic SUM out std logic vector 7 downto 0 res out std logic end read cores architecture beh of read cores is component my add port A B in std logic vector 7 downto 0 S out std logic vector 7 downto 0 end component XST User Guide www xilinx com 221 1 800 255 7778 XILINX Chapter 3 FPGA Optimization begin res lt al and bl inst my_add port map A gt A B gt B S gt SUM end beh If Read Cores is disabled XST estimates Maximum Combinational Path Delay as 6 639ns critical path goes through a simple AND function and an area of one slice If Read Core
345. orial process this sensitivity list must contain all signals which appear in conditions if case etc and any signal appearing on the right hand side of an assignment If one or more signals are missing from the sensitivity list XST generates a warning for the missing signals and adds them to the sensitivity list In this case the result of the synthesis may be different from the initial design specification A process may contain local variables The variables are handled in a similar manner as signals but are not of course outputs to the design In Example 6 10 a variable named AUX is declared in the declarative part of the process and is assigned to a value with in the statement part of the process Examples 6 10 and 6 11 are two examples of a VHDL design using combinatorial processes Example 6 10 Combinatorial Process library ASYL use ASYL ARITH all entity ADDSUB is port A B in BIT_VECTOR 3 downto 0 ADD_SUB in BIT S out BIT VECTOR 3 downto 0 end ADDSUB architecture ARCHI of ADDSUB is begin process A B ADD SUB variable AUX BIT VECTOR 3 downto 0 www xilinx com XST User Guide 1 800 255 7778 Combinatorial Circuits XILINX begin if ADD SUB 1 then AUX A B else AUX A B end if S lt AUX end process end ARCHI Example 6 11 Combinatorial Process entity EXAMPLE is port A B in BIT S cout BIT end EXAMPLE
346. ory of the ISE installation directory stopwatch v statmach v decode v cnt60 v smallcntr v tenths v hex2led v This design contains seven modules Example 2 stopwatch statmach tenths a CORE Generator core decode cnt60 smallcntr hex2led Create a new directory named v1g m Copy the watchver design files from the ISEexamples watchver directory of the ISE installation directory to the newly created v1g m directory Note It is mandatory to specify the top level design block via the top command line switch To synthesize the design which is now represented by seven Verilog files create a project Please note that starting from the 6 1i release XST supports Mixed VHDL Verilog projects and therefore Xilinx strongly suggests that you use the new project format whether it is a www xilinx com XST User Guide 1 800 255 7778 Example 2 How to Synthesize Verilog Designs Using Command Line Mode XILINX real mixed language project or not In this example we use the new project format To create a project file containing only Verilog files place a list of Verilog files preceded by the keyword verilog in a separate file The order of the files is not important XST can recognize the hierarchy and compile Verilog files in the correct order For our example 1 Openanew file called watchver v 2 Enter the names of the Verilog files into this file in any order and save it verilog work decode v verilog work
347. ot issue any message during the Macro Recognition step In case your divider does not correspond to the case supported by XST the following error message displays ERROR Xst 719 filel vhd Line 172 Operator is not supported yet DIVIDE Related Constraints There are no related constraints available Division By Constant 2 This section contains VHDL and Verilog descriptions of a Division By Constant 2 divider The following table shows pin descriptions for a Division By Constant 2 divider IO pins Description DI 7 0 Division Operands DO 7 0 Division Result VHDL Following is the VHDL code for a Division By Constant 2 divider library ieee use ieee std logic 1164 all use ieee numeric std all entity divider is port DI in unsigned 7 downto 0 DO out unsigned 7 downto 0 end divider architecture archi of divider is begin DO lt DI 2 end archi 130 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Verilog Following is the Verilog code for a Division By Constant 2 divider module divider DI DO input 7 0 DI output 7 0 DO assign DO DI 2 endmodule Resource Sharing The goal of resource sharing also known as folding is to minimize the number of operators and the subsequent logic in the synthesized design This optimization is based on the principle that two similar arithmetic resources may be implemented
348. ote All variables are declared as integer or reg A variable cannot be declared as a wire Expressions An expression involves constants and variables with arithmetic logical amp amp amp 11 4 A lt lt gt gt lt lt lt gt gt gt relational lt lt gt gt and conditional operators The logical operators are further divided as bit wise versus logical depending on whether it is applied to an expression involving several bits or a single bit The following table lists the expressions supported by XST Table 7 1 Expressions Concatenation Supported Replication Supported uu Supported Arithmetic Supported only if second operand is a power of 2 Modulus Supported only if second operand is a power of 2 Addition Supported Subtraction Supported Multiplication Supported XST User Guide www xilinx com 325 1 800 255 7778 XILINX 326 Table 7 1 Expressions Chapter 7 Verilog Language Support Power TR Supported e Both operands must be constants with the second operand being non negative e Ifthe first operand is a 2 then the second operand may be a variable e XST does not support the real data type Any combination of operands that results in a real type causes an error e The values X unknown and Z high impe
349. out while XST continues to generate the entire LOG file Silent mode can be invoked using intstyle switch with value set to silent Hiding specific messages XST User Guide You can hide specific messages generated by XST at the HDL or Low Level Synthesis steps in specific situations by using the XIL XST HIDEMESSAGES environment variable This environment variable can have one of the following values e none maximum verbosity All messages are printed out This is the default e hdl_level reduce verbosity during VHDL Verilog Analysis and HDL Basic and Advanced Synthesis e low_level reduce verbosity during Low level Synthesis e hdl and low levels reduce verbosity at all stages The following messages are hidden when lid level and hdl and low levels values are specified for the XIL XST HIDEMESSAGES environment variable e WARNING HDLCompilers 38 design v line 5 Macro my macro redefined Nole Note this message is issued by the Verilog compiler only e WARNING Xst 916 design vhd line 5 Delay is ignored for synthesis e WARNING Xst 766 design vhd line 5 Generating a Black Box for component comp e Instantiating component comp from Library lib e Set user defined property LOC X1Y1 for instance inst in unit block e Set user defined property RLOC X1Y1 for instance inst in unit block e Set user defined property INIT 1 for instance inst in unit block e Register
350. ow to Fit a Large Design 232 If a design does not fit in the selected device exceeding the number of device macrocells or device P Term capacity you must select an area optimization for XST Statistically the best area results are obtained with the following options e Optimization effort 1 Normal or 2 High e Optimization Goal Area e Default values for other options Another option that you can try is wysiwyg yes This option may be useful when the design cannot be simplified by the optimization process and the complexity in number of P Terms is near the device capacity It may be that the optimization process trying to reduce the number of levels creates larger equations therefore increasing the number of P Terms and so preventing the design from fitting By validating this option the number of P Terms is not increased and the design fitting may be successful www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 5 Design Constraints This chapter describes constraints options and attributes supported for use with XST This chapter contains the following sections Introduction Introduction Setting Global Constraints and Options VHDL Attribute Syntax Verilog Meta Comment Syntax Verilog 2001 Attributes XST Constraint File XCF General Constraints HDL Constraints FPGA Constraints non timing CPLD Constraints non timing
351. ox in Project Navigator or with command line arguments while VHDL attributes or Verilog meta comments can be inserted in your source code to specify different choices for individual parts of the design Note that the local specification of a constraint overrides its global setting Similarly if a constraint is set both on a node or an instance and on the enclosing design unit the former takes precedence for the considered node or instance Setting Global Constraints and Options This section explains how to set global constraints and options from the Process Properties dialog box within Project Navigator For a description of each constraint that applies generally that is to FPGAs CPLDs VHDL and Verilog refer to the Constraints Guide Note Except for the Value fields with check boxes there is a pull down arrow or browse button in each Value field However you cannot see the arrow until you click in the Value field Synthesis Options 234 To specify the HDL synthesis options from Project Navigator 1 Select a source file from the Source file window 2 Right click on Synthesize XST in the Process window 3 Select Properties 4 When the Process Properties dialog box displays click the Synthesis Options tab www xilinx com XST User Guide 1 800 255 7778 Setting Global Constraints and Options 7 XILINX Depending on the device family you have selected FPGA or CPLD one of two dialog boxes displays P
352. p Ea e E e a aa E E aa 191 TONNS OM eond a e E E a A E aca it EEIE a AEREE 191 Sequential iii a aeiia a a a hae aaea 191 scm 191 Jc A A Ee ee 192 LOBOS A A REAPER t M peter etes qd ene ee Rese 192 RAM based FSM Synthesis 0 0 0 66 ene nee eee 194 Safe FSM Implementation sss e eee eee 194 Black Box SUPPOEDS dc A th aep Cera ee 195 Log Fil se 2seiresekcieereee ade treki ristes bad sige eins 195 Related Constraints 00 ccc cc ence hn 195 12 www xilinx com XST User Guide 1 800 255 7778 XILINX VHDL Coden CER 195 Verilog Cod eE o E E EE EEE EEE EUN 196 Chapter 3 FPGA Optimization Introduction 3 4 hho xa oH cane eee adore peri dio dai ds 197 Virtex Specific Synthesis Options 00 00 c eee eee eee 198 Et AOI T M 199 Arithmetic FUNCHONS sic ies cie a I ied RE ee RIPE ERN edad Reg edes 199 Loadable Functions 45 entere eb as dia Oo 199 Multiplexers eriperet bee RE pate EA b EEE he id 200 Priority Encoder oie ee ere paradise dpi dida sde 200 Dec cin et dp Et dea es id det ied Eder HEAR SEA Ede Eee eon 200 elata cari Em 201 RAMS 52k tee Ia RC Eee Eq e RU a dA e eo a eee deis 201 ROMS EET 202 Using DSP48 Block Resources oooooooocccoccoccococcnco cr 203 Mapping Logic onto Block RAM sssssssseese e 204 VEHDECOde ce tette eee aang cca eters agent a EE Ee Rs 205 VERLOG ekeswe ke e ERN WI ERR ORE E RR ER RN CLER DER aa C DER Deren 205 occ 206 VAD
353. played after Advanced HDL Synthesis step See Introduction and Dynamic Shift Register in Chapter 2 and Introduction in Chapter 9 www xilinx com XST User Guide 1 800 255 7778 What s New XILINX Design Constraints XST User Guide Removed support for old XST constraint file and private XST timing constraints Support for acceptance of LOC RLOC constraints on inferred block RAM when block RAM requires only a single primitive See Specifying INITs and RLOCs in HDL Code in Chapter 3 Introduced new csd and pipe_block options for Multiplier Style constraint MULT_STYLE See Multiplier Style and Constraints Summary in Chapter 5 Introduced new Safe Implementation constraint SAFE_IMPLEMENTATION See Safe Implementation and Constraints Summary in Chapter 5 and Run Command in Chapter 10 Introduced new Recovery State constraint SAFE_RECOVERY_STATE for Safe FSM Implementation See Recovery State and Constraints Summary in Chapter 5 New value speed1 for FSM Encoding FSM_ENCODING constraint See FSM Encoding Algorithm in Chapter 5 Support for control of macro implementation on DSP48 in Virtex 4 devices via USE_DSP48 constraint See Using DSP48 Block Resources in Chapter 3 Multiplier Style menu in Process Properties replaced by Use DSP48 menu when working with Virtex 4 devices See Considerations for Virtex 4 Devices in Chapter 2 and
354. positive edge clock synchronous parallel load serial in and serial out library ieee use ieee std logic 1164 all entity shift is port C SI SLOAD in std logic D in std logic vector 7 downto 0 SO out std logic end shift 80 www xilinx com XST User Guide 1 800 255 7778 Shift Registers XILINX architecture archi of shift is signal tmp begin process C begin std_logic_vector 7 downto 0 if C event and C 1 then if SLOAD 1 then tmp lt D else tmp tmp 6 downto 0 amp SI end if end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock a synchronous parallel load a serial in and a serial out module shift C SLOAD SI D SO input C SI SLOAD input 7 0 D output SO reg 7 0 tmp always posedge C begin if SLOAD tmp lt D else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out Note For this example XST does not infer an SRL16 The following table shows pin definitions for an 8 bit shift left shift right register with a positive edge clock a serial in and a serial out 10 Pins Description C Positive Edge Clock SI Serial In LEFT RIGHT Left right shift mode selector PO 7 0 Parallel Output XST User Guide www xi
355. primary clocksignal clock signal register duplication yes no model entity module yes yes no Spartan T TIE 3 true false net in model signal Virtex II II Pro II Pro X E 4 register_powerup string net in model type signal no na XC9500 CoolRunner XPLA3 II resource_sharing yes no model entity module yes yes no Spartan II TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II resynthesize yes no model entity module no na Spartan M T ITE 3 true false VirtexTM TI II Pro II Pro X E 4 rom extract yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal VirtexTM TI II Pro II Pro X E 4 rom style auto block model entity module yes auto block Spartan TI TIE 3 distributed net in model signal signal distributed Virtex TI II Pro II Pro X E 4 safe implementation yes no model entity module yes yes no Spartan TI TIE 3 true false net in model signal signal Virtex TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II XST User Guide www xilinx com 271 XILINX Chapter 5 Design Constraints Table 5 1 XST Specific Non timing Options XCF Cmd Constraint Constraint Constraint VHDL Verilog Cmd Technology Line Name Value Syntax Target Target Value Target safe recovery state string net in model signal signal
356. put Yes Write Timing Constraints NO Hierarchy Separator Bus Delimiter lt gt Case Specifier maintain Slice Utilization Ratio 100 Slice Utilization Ratio Delta Other Options lso stopwatch lso Read Cores YES cross clock analysis NO verilog2001 YES Optimize Instantiated Primitives NO tristate2logic No Setting FSM Encoding Algorithm to ONE XST User Guide www xilinx com 1 800 255 7778 XILINX 367 7 XILINX Chapter 9 Log File Analysis HDL Compilation x Compiling vhdl file C temp timer smallcntr vhd in Library work Architecture inside of Entity smallcntr is up to date Compiling vhdl file C temp timer statmach vhd in Library work Architecture inside of Entity statmach is up to date Compiling vhdl file C temp timer decode vhd in Library work Architecture behavioral of Entity decode is up to date Compiling vhdl file C temp timer cnt60 vhd in Library work Architecture inside of Entity cnt60 is up to date Compiling vhdl file C temp timer hex2led vhd in Library work Architecture hex2led_arch of Entity hex2led is up to date Compiling vhdl file C temp timer stopwatch vhd in Library work Architecture inside of Entity stopwatch is up to date HDL Analysis ty stopwatch Architecture lt inside gt Analyzing Enti t 766 C temp timer stopwatch vhd line 68 Generating a Black Box for component WARNING
357. r 66 cece cee eee 110 Considerations for Virtex 4 Devices 0 0 0 ccc cee eer 111 Comparators E lt e o m 6 ei a a al oii 112 Log File gt ieit m empRLPES LN dea ed pe ped Deom eos eed Bin eat 112 Unsigned 8 bit Greater or Equal Comparator 1 6 6 eee eee 112 Mu ltipliers ota di is 113 Large Multipliers Using Block Multipliers llle 113 Registered Mu ltiplier i esp he pepe wee ropas Rao 113 Considerations for Virtex 4 Devices 0 0 ccc cece eee nee eee 113 Multiplication with Constant sisse n 114 Log File e err Dt are ete yd etd E ed e eren id 115 Related Constraints e re scire dessine dederit dp ed e m ede dete ime dri 115 10 www xilinx com XST User Guide 1 800 255 7778 XILINX Unsigned 8x4 bit Multiplier 2 0 6 6 eee eee eens 115 Pipelined Multipliers cs certian ed edu dus ea ade A E a 116 Multiply Adder Subtractor 0 tatia tagia ossia eee eee tee nn 121 Multiplier Adder with 2 Register Levels on Multiplier nputs o 122 Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs 124 Multiply Accumulate MAC 0 0 n 125 Multiplier Up Accumulate with Register After Multiplication o o oo o o o 127 Multiplier Up Down Accumulate with Register After Multiplication 128 Dividers 4 esenee da A wowed 130 Log Hliva 130 Related Constraints scooter 4044000 cd di 130 Division By Constantlu asider
358. r a Dedicated Carry MUXs based architecture if the value is MUXCY You can apply this attribute to either a signal that defines the multiplexer or the instance name of the multiplexer This attribute can also be global The attribute MUX EXTRACT with respectively the value no or force can be used to disable or force the inference of the multiplexer Priority Encoder Decoder 200 The if elsif structure described in the Priority Encoders in Chapter 2 is implemented with a 1 of n priority encoder XST uses the MUXCY primitive to chain the conditions of the priority encoder which results in its high speed implementation You can enable disable priority encoder inference using the PRIORITY EXTRACT constraint Generally XST does not infer and so does not generate a large number of priority encoders Therefore Xilinx recommends that you use the PRIORITY EXTRACT constraint with the force option if you would like to use priority encoders A decoder is a demultiplexer whose inputs are all constant with distinct one hot or one cold coded values An n bit or 1 of m decoder is mainly characterized by an m bit data output and an n bit selection input such that n 2 1 lt m lt n 2 Once XST has inferred the decoder the implementation uses the MUXF5 or MUXCY primitive depending on the size of the decoder You can enable disable decoder inference using the DECODER EXTRACT property www xilinx com XST User Guide 1 800 255 77
359. r binding Verilog modules to a VHDL design unit Note Configuration specification direct instantiation and component configurations are not supported for a Verilog module instantiation in VHDL In supporting mixed projects VHDL and Verilog project files are unified VHDL and Verilog libraries are logically unified Specification of work directory for compilation xsthdpdir previously available only for VHDL is also available for Verilog The xhdp ini mechanism for mapping a logical library name to a physical directory name on the host file system previously available only for VHDL is also available for Verilog www xilinx com 355 1 800 255 7778 XILINX Chapter 8 Mixed Language Support e Mixed language projects accept a search order used for searching unified logical libraries in design units cells During elaboration XST follows this search order for picking and binding a VHDL entity or a Verilog module to the mixed language project Mixed Language Project File XST uses a dedicated mixed language project file to support mixed VHDL Verilog designs You can use this mixed language format not only for mixed projects but also for purely VHDL or Verilog projects If you use Project Navigator to run XST Project Navigator creates the project file and it is always a mixed language project file If you run XST from the command line you must create a mixed language project file for your mixed language projects To
360. r disables XST to read EDIF or NGC core files for timing estimation and device utilization control Please refer to Cores Processing in Chapter 3 for more information The Read Cores command line option has three possible values no disables cores processing yes enables cores processing but maintains the core as a black box and does not further incorporate the core into the design optimize enables cores processing and merges the core s netlist into the overall design Define this option globally with the read_cores command line option of the run command Following is the basic syntax read cores yes no optimize The default is yes In Project Navigator set read_cores globally with the Read Cores option in the Synthesis Options tab of the Process Properties dialog box Note that the optimize option is not available in Project Navigator Use Carry Chain XST uses carry chain resources to implement certain macros but there are situations where you can get better results by avoiding the use of carry chain The Use Carry Chain USE CARRY CHAIN constraint can deactivate carry chain use for macro generation See USE CARRY CHAIN in the Constraints Guide for details www xilinx com 259 1 800 255 7778 XILINX Chapter 5 Design Constraints Convert Tristates to Logic Since some devices do not support internal tristates XST automatically replaces tristates with equivalent logic Because the logic generated fr
361. r the example is to adjust the size of operands A and B to 9 bits using concatenation Res lt 0 amp A O amp B In this case XST recognizes that this 9 bit adder can be implemented as an 8 bit adder with carry out e Another solution is to convert A and B to integers and then convert the result back to the std_logic vector specifying the size of the vector equal to 9 106 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX The following table shows pin descriptions for an unsigned 8 bit adder with carry out IO pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result CO Carry Out VHDL Code Following is the VHDL code for an unsigned 8 bit adder with carry out library ieee use ieee std logic 1164 a11 use ieee std logic arith all use ieee std logic unsigned all entity adder is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 CO out std logic end adder architecture archi of adder is signal tmp std logic vector 8 downto 0 begin tmp lt conv std logic vector conv integer A conv integer B 9 SUM lt tmp 7 downto 0 CO tmp 8 end archi In the preceding example two arithmetic packages are used e std logic arith This package contains the integer to std logic conversion function that is conv std logic vector man e std logic unsigned This package contains the u
362. r with a positive edge clock a synchronous set a serial in and a serial out library ieee use ieee std_logic_1164 all entity shift is port QC SI S in std Logic SO out std logic end shift architecture archi of shift is signal tmp std logic vector 7 downto 0 begin process C S begin if C event and C 1 then if S2 1 then tmp lt others gt 1 else tmp lt tmp 6 downto 0 SI end if end if end process SO lt tmp 7 end archi Verilog Code Following is the Verilog code for an 8 bit shift left register with a positive edge clock a synchronous set a serial in and a serial out module shift C S SI SO input SI S output SO reg 7 0 tmp always 8 posedge C begin if S tmp lt 8 b11111111 else begin tmp lt tmp 6 0 SI end end assign SO tmp 7 endmodule XST User Guide www xilinx com 77 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out Note For this example XST does not infer SRL16 The following table shows pin definitions for an 8 bit shift left register with a positive edge clock a serial in and a parallel out 10 Pins Description C Positive Edge Clock SI Serial In PO 7 0 Parallel Output VHDL Code Following is the VHDL code for an 8 bit shift left register with a positive edge clock a serial in and a
363. raction FSM Style Global Optimization Goal Incremental Synthesis Keep Hierarchy Logical Shifter Extraction Map Logic on BRAM Max Fanout Move First Stage Move Last Stage Multiplier Style Mux Style Number of Global Clock Buffers Optimize Instantiated Primitives Pack I O Registers into IOBs Priority Encoder Extraction RAM Style Register Balancing Register Duplication Resynthesize Shift Register Extraction Signal Encoding Slice Packing Use Carry Chain Write Timing Constraints XOR Collapsing www xilinx com 1 800 255 7778 Chapter 3 FPGA Optimization XST User Guide Macro Generation XILINX Macro Generation The Virtex Macro Generator module provides the XST HDL Flow with a catalog of functions These functions are identified by the inference engine from the HDL description their characteristics are handed to the Macro Generator for optimal implementation The set of inferred functions ranges in complexity from simple arithmetic operators such as adders accumulators counters and multiplexers to more complex building blocks such as multipliers shift registers and memories Inferred functions are optimized to deliver the highest levels of performance and efficiency for Virtex architectures and then integrated into the rest of the design In addition the generated functions are optimized through their borders depending on the design context This section categorizes by function all available macro
364. ral statements occur in blocks that are defined inside modules There are two kinds of procedural blocks the initial block and the always block Within each block Verilog uses a begin and end to enclose the statements Since initial blocks are ignored during synthesis only always blocks are discussed Always blocks usually take the following format always begin statement end where each statement is a procedural assignment line terminated by a semicolon Module Declaration In the module declaration the I O ports of the circuit are declared Each port has a name and a mode in out and inout as shown in the example below module EXAMPLE A B C D E input A B C output D inout E wire D E assign E oe A 1 bz assign D B amp E endmodule The input and output ports defined in the module declaration called EXAMPLE are the basic input and output I O signals for the design The inout port in Verilog is analogous to a bi directional I O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer The preceding example describes E as a tristate buffer with a high true output enable signal If oe 1 the value of signal A is output on the pin represented by E If oe 0 then the buffer is in high impedance Z and any input value driven on the pin E from the external logic is brought into the device and fed to the signal represen
365. rameter passing Fixed local parameters Enhanced conditional compilation File and line compiler directives Variable part selects www xilinx com 353 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support 354 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter Mixed Language Support Introduction XST User Guide This chapter contains the following sections Introduction Mixed Language Project File VHDL Verilog Boundary Rules Port Mapping Generics Support in Mixed Language Projects Library Search Order File XST supports mixed VHDL Verilog projects This chapter explains how to create mixed language projects and what the current limitations are The following are key features of mixed language support Mixing of VHDL and Verilog is restricted to design unit cell instantiation only A VHDL design can instantiate a Verilog module and a Verilog design can instantiate a VHDL entity Any other kind of mixing between VHDL and Verilog is not supported Ina VHDL design a restricted subset of VHDL types generics and ports is allowed on the boundary to a Verilog module Similarly in a Verilog design a restricted subset of Verilog types parameters and ports is allowed on the boundary to a VHDL entity or configuration XST binds VHDL design units to a Verilog module during the Elaboration step Component instantiation based on default binding is used fo
366. rchitecture Virtex TI II Pro II Pro X E 4 max_fanout integer model entity module yes integer Spartan TI TIE 3 net in model signal signal Virtex TI TI Pro II Pro X E 4 move first stage yes no model entity module yes yes no Spartan I TIE 3 true false primary clock primary primary Virtex TI II Pro signal clocksignal clock signal II Pro X E 4 net in model move last stage yes no model entity module yes yes no Spartan II IIE 3 true false primary clock primary primary Virtex TI II Pro signal clock signal clock signal II Pro X E 4 net in model mult style auto block model entity module yes auto block Spartan 3 lut pipe_lut net in model signal signal lut pipe lut Virtex II II Pro kcm csd II Pro X mux extract yes no force model entity module yes yes no Spartan I TIE 3 true false net in model signal signal force VirtexTM TI II Pro II Pro X E 4 XC9500 CoolRunner XPLA3 II mux_style auto muxf model entity module yes auto muxf Spartan TI TIE 3 muxcy net in model signal signal muxcy Virtex TI II Pro II Pro X E 4 noreduce yes no net in model signal signal no na XC9500 true false CoolRunner XPLA3 II optimize primitives yes no model entity module no yes no Spartan TI TIE 3 true false instance instance instance VirtexTM TI II Pro in model II Pro X E 4 opt level 1 2 model entity module yes 1 2 Spartan M T
367. regi equivalent to reg2 has been removed www xilinx com 365 1 800 255 7778 XILINX Chapter 9 Log File Analysis The following messages are hidden when low_level and hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable e ARNING Xst e Regis e ARNING Xst constant in e ARNING Xst e ARNING Xst e ARNING Xst the consta bet Timing Report 382 Register regl is equivalent to reg2 ter regl equivalent to reg2 has been removed 1710 FF Latch reg block block 1293 1291 1426 The value init of the FF Latch reg hinders without init value is FF Latch reg is constant in block block FF Latch reg is unconnected in block block nt cleaning in the block block You could achieve ter results by setting this init to value At the end of synthesis XST reports the timing information for the design The report shows the information for all four possible domains of a netlist register to register register to outpad and inpad to outpad Mo to register moms input See the TIMING REPORT section of the example given in the FPGA Log File section for an example of the timing report sections in the XST log FPGA Log File The following is an example of an XST log file for FPGA synthesis Release 7 1i xst H 37 Copyright c 1995 2004 Xilinx inc All rights reserved TAB
368. remental Incremental Incremental unit unit unit unit unit synthesis synthesis synthesis synthesis lt my_sub gt lt my_add gt lt leva_1 gt lt leva_2 gt lt leva gt Unit Unit Unit Unit lt my_and gt lt my_and gt lt my_and gt lt my_and gt is is is is up xe up to up to up to date date date date 210 www xilinx com 1 800 255 7778 XST User Guide Incremental Synthesis Flow XILINX If you make no changes to the design during Low Level synthesis XST reports that all blocks are up to date and the previously generated NGC files are kept unchanged as shown in the following log file segment Low Level Synthesis Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni lt my_and gt is up to date lt my_or gt is up to date lt my_sub gt is up to date lt my_add gt is up to date lt levb gt is up to date lt leva_1 gt is up to date lt leva_2 gt is up to date lt leva gt is up to date lt top gt is up to date Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni Incremental synthesis Uni ct ct ct ct ct ct ct ct cd If you changed one timing constraint then XST cannot detect this modification To force XST to resynthesize the required blocks use the RESYNTHESIZE constraint For example
369. rocess Properties xj Synthesis Options HDL Options Xiinx Specific Options Use Synthesis Constraints File Property Enable Auto Floorplanning Read Cores Hierarchy Separator Bus Delimiter Work Directory Enable Auto Fooplannng amp amp 5 Use Synthesis Constraints Fle Global Generate RTL Schematic Y Read Cores Hierarchy Separator Bus Delimiter O 1 1 Figure 5 1 Synthesis Options FPGA XST User Guide www xilinx com 235 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Process Properties x Synthesis Options HDL Options Xilinx Specific Options ox Cancel Defaut Help Figure 5 2 Synthesis Options CPLD 236 www xilinx com XST User Guide 1 800 255 7778 Setting Global Constraints and Options XST User Guide XILINX Following is a list of the synthesis options that can be selected from the dialog boxes Optimization Goal Optimization Effort Enable Auto Floorplanning Use Synthesis Constraints File Synthesis Constraint File Library Search Order Keep Hierarchy Global Optimization Goal Generate RTL Schematic Read Cores Cores Search Directories Write Timing Constraints Cross Clock Analysis Hierarchy Separator Bus Delimiter Slice Utilization Ratio Case Work Directory HDL Library Mapping File INI File Veri
370. roperties dialog box Case Implementation Style The Case Implementation Style vlgcase command line option instructs XST how to interpret Verilog Case statements It has three possible values full parallel and full parallel Ifthe option is not specified then XST implements the exact behavior of the case statements Iffull is used XST assumes that the case statements are complete and avoids latch creation If parallel is used XST assumes that the branches cannot occur in parallel and does not use a priority encoder See Multiplexers in Chapter 2 of this manual as well as FULL CASE and PARALLEL CASE in the Constraints Guide for details Define this option globally with the vlgcase command line option of the run command vlgcase full parallel full parallel By default there is no value In Project Navigator specify vlgcase globally with the Case Implementation Style option in the HDL Options tab of the Process Properties dialog box Allowed values are Full Parallel and Full Parallel By default the value is blank Full Case Verilog The FULL CASE directive is used to indicate that all possible selector values have been expressed in a case casex or casez statement The directive prevents XST from creating additional hardware for those conditions not expressed See Multiplexers in Chapter 2 of this manual and FULL CASE in the Constraints Guide for details www xilinx com 247 1 800 255 7778
371. rrent file has the following syntax include path file name to be included Note The path can be relative or absolute 338 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Multiple include statements are allowed in a single Verilog file This feature makes your code modular and more manageable in a team design environment where different files describe different modules of the design To have the file in your include statement recognized you must identify the directory where it resides either to ISE or to XST e By default ISE searches the ISE project directory so adding the file to your project directory will identify the file to ISE e You can direct ISE to a different directory by including a path relative or absolute in the include statement in your source code e You can point XST directly to your include file directory by using the Verilog Include Directories option See Verilog Include Directories Verilog Only in Chapter 5 e Ifthe include file is required for ISE to construct the design hierarchy this file must either reside in the project directory or be referenced by a relative or absolute path The file need not be added to the project Be aware that conflicts can occur For example at the top of a Verilog file you might see the following timescale 1 ns 1 ps include modules v If the specified file in this case modules
372. s File iuc command line option allows you to ignore the constraint file during synthesis Define this option globally with the iuc command line option of the run command Following is the basic syntax iuc yes no The default is no In Project Navigator specify iuc globally by selecting the Use Synthesis Constraints File option under the Synthesis Options tab in the Process Properties dialog box Verilog Include Directories Verilog Only Use the Verilog Include Directories option vlgincdir to enter discrete paths to your Verilog Include Directories Define this option globally with the vlgincdir command line option of the run command Allowed values are names of directories Please refer to Names with Spaces in Chapter 10 for more information vlgincdir directory path directory path There is no default In Project Navigator specify this option with the Verilog Include Directories option of the Synthesis Options tab in the Process Properties dialog box Allowed values are names of directories There is no default Verilog 2001 The Verilog 2001 verilog2001 command line option enables or disables interpreted Verilog source code as the Verilog 2001 standard By default Verilog source code is interpreted as the Verilog 2001 standard Define this option globally with the verilog2001 command line option of the run command Following is the basic syntax verilog2001 yes no www xilinx com XST User Guide 1 800 2
373. s and briefly describes technology resources used in the building and optimization phase Macro Generation can be controlled through attributes These attributes are listed in each subsection For general information on attributes see Chapter 5 Design Constraints XST uses dedicated carry chain logic to implement many macros In some situations carry chain logic may lead to sub optimal optimization results Use the USE_CARRY_CHAIN constraint to direct XST to deactivate this feature Please refer to Chapter 5 Design Constraints for more information Arithmetic Functions For Arithmetic functions XST provides the following elements e Adders Subtracters and Adder Subtracters e Cascadable Binary Counters e Accumulators e Incrementers Decrementers and Incrementer Decrementers e Signed and Unsigned Multipliers XST uses fast carry logic MUXCY to provide fast arithmetic carry capability for high speed arithmetic functions The sum logic formed from two XOR gates is implemented using LUTs and the dedicated carry XORs XORCY In addition XST benefits from a dedicated carry ANDs MULTAND resource for high speed multiplier implementation Loadable Functions For Loadable functions XST provides the following elements e Loadable Up Down and Up Down Binary Counters e Loadable Up Down and Up Down Accumulators XST can provide synchronously loadable cascadable binary counters and accumulators inferred in the HDL flow Fast carry
374. s ir coe AL sewers ein bere nnam id erit eed epee ay ele den bed 304 Sequential Process with a Sensitivity List oooooococcccoorrromoonnr eee 304 Sequential Process without a Sensitivity List oooooooccooorrrormmmo 304 Examples of Register and Counter Descriptions 305 Multiple Wait Statements Descriptions 0 666 306 Functions and Procedures 00000 c cece ec cee e 308 Assert Statement i ico ec A ue DE Ye 310 Pat copo rcm 312 STANDARD Package sssi vended ed cronica 312 IEEE Packages icon cios n re Re eer Eee A era S E ER E Edd 312 Synopsys Packag s cesser br ee rk eee ee EDU CLAN Hope RES 313 VHDL Language Support use cep ecco pU dte eu ii doceat ip a 314 VHDL Reserved Words ssssssseee RR e 320 www xilinx com 1 800 255 7778 15 XILINX Chapter 7 Verilog Language Support Introduction 321 Behavioral Verilog Features ooooooococcccccccccoconc cr 322 Variable Declaration s lt cc5c2 90 iestcavtaie a e riada pira sive ls 322 Initial Values 00000 a LED UG RR REP EUG RACER d ER Ok RET T RET aE eS 322 ATIAVS es fee toi wea tein ovat ree yes ves ER Vea ere P RESP YE Ge ved 323 Multi dimensional Arrays eu kd CX eR P RET ERES ORE s 323 Data Types 4 ssepe Ren IAqr ERE TEPbe TERR Le AM beets gee PI Ga elegance 324 Legal Statements asii vote pedis basada aen tete i 325 EXPPCSSIONS 5o oss bes rl estos date vato eee an eee ae eas 325 BlockS s Sake baer rec
375. s is enabled then XST displays the following messages during Low Level Synthesis Low Level Synthesis Launcher Executing edif2ngd noa my add edn my add ngo INFO NgdBuild Release 6 1i dif2ngd G 21 INFO NgdBuild Copyright c 1995 2003 Xilinx Inc All rights reserved Writing the design to my add ngo Loading core my add for timing and area information for instance inst Estimation of Maximum Combinational Path Delay is 8 281ns with an area of five slices Please note that by default XST reads EDIF NGC cores from the current project directory If the cores are not in the project directory you must use the Cores Search Directories synthesis option to specify which directory the cores are in Specifying INITs and RLOCs in HDL Code 222 Using the UNISIM library allows you to directly instantiate LUT components in your HDL code To specify a function that a particular LUT must execute apply an INIT constraint to the instance of the LUT If you want to place an instantiated LUT or register in a particular slice of the chip then attach an RLOC constraint to the same instance It is not always convenient to calculate INIT functions and different methods that can be used to achieve this Instead you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block Attaching a LUT MAP constraint XST is able to automatically recognize
376. sbce begin scope msbcount FDCE CE 0 190 qoutsig O0 Total 3 321ns 1 333ns logic 1 988ns route 40 1 logic 59 9 route 372 www xilinx com XST User Guide 1 800 255 7778 FPGA Log File XILINX Default OFFS ET IN B EFOR Timing constraint for Clock CLK Total number of paths destination ports 13 13 Offset 2 779ns Levels of Logic 3 Source XCOUNTER Q THRESHO PAD Destination sixty msbcount qoutsig 2 FF Destination Clock CLK rising Data Path XCOUNTER Q THRESHO to sixty msbcount qoutsig 2 Gate Net Cell in out fanout Delay Delay Logical Name Net Name tenths Q THRESHO 1 0 000 0 608 XCOUNTER xtermcnt LUT2 10 gt 0 5 0 347 0 735 cnt60enablel cnt60enable begin scope sixty LUT2 11 gt 0 4 0 347 0 553 msbce2 msbce begin scope msbcount FDCE CE 0 190 qoutsig O0 Total 2 79ns 0 884ns logic 1 895ns route 31 8 logic 68 2 route Timing constraint Default OFFSET OUT AFTER for Clock CLK Total number of paths destination ports 58 16 Offset 5 835ns Levels of Logic 4 Source sixty lsbcount goutsig_0 FF Destination ONESOUT lt 6 gt PAD Source Clock CLK rising Data Path sixty lsbcount qoutsig_0 to ONESOUT lt 6 gt Gate Net Cell in out fanout Delay Delay Logical Name Net Name FDCE C Qhttp 12 0 449 0 914 qoutsig 0 Q
377. signing each of the four inputs DATA1 DATA2 DATA3 and DATAA to the output RESULT Example 6 22 Sequential Circuit Using Multiple Wait Statements library IEEE use IEEE STD LOGIC 1164 all entity EXAMPLE is port DATA1 DATA2 DATA3 DATA4 in STD LOGIC VECTOR 3 downto 0 RESULT out STD LOGIC VECTOR 3 downto 0 CLK in STD LOGIC RST in STD LOGIC end EXAMPLE architecture ARCH of EXAMPLE is begin process begin SEQ LOOP loop wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA1 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA2 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA3 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA4 end loop end process end ARCH XST User Guide www xilinx com 307 1 800 255 7778 XILINX Chapter 6 VHDL Language Support Functions and Procedures The declaration of a function or a procedure provides a mechanism for handling blocks used multiple times in a design Functions and procedures can be declared in the declarative part of an entity in an architecture or in packages The heading part contains the parameters input parameters
378. sis describes the XST log file and explains what it contains e Chapter 10 Command Line Mode describes how to run XST using the command line The chapter describes the XST run and set commands and their options e Appendix A XST Naming Conventions discusses net naming and instance naming conventions XST User Guide www xilinx com 3 1 800 255 7778 XILINX Additional Resources Preface About This Guide For additional information go to http www xilinx com support The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Tutorials Description URL Tutorials covering Xilinx design flows from design entry to verification and debugging http www xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http www xilinx com xlnx xil ans browser jsp Application Notes Descriptions of device specific design techniques and approaches http www xilinx com xlnx xweb xil publications index jsp c ategory Application Notes Data Sheets Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http www xilinx com xlnx xweb xil publications index jsp Problem S
379. sis ui Dynamic shift register inferenc HDL Synthesis Report Macro Statistics Shift Registers rl 16 bit dynamic shift register sc dl Related Constraints A related constraint is SHREG_ EXTRACT VHDL Code Following is the VHDL code for a 16 bit dynamic shift register library IEEE use IEEE std logic 1164 a11 o use IEEE std logic unsigned all entity shiftregluts is port CLK in std logic DATA in std logic CE in std logic A 0 out std_logic end shiftregluts in std_logic_vector 3 downto 0 84 www xilinx com 1 800 255 7778 XST User Guide Multiplexers XILINX architecture rtl of shiftregluts is constant DEPTH_WIDTH integer 16 type SRL_ARRAY is array 0 to DEPTH_WIDTH 1 of std_logic The type SRL ARRAY can be array 0 to DEPTH WIDTH 1 of std logic vector BUS WIDTH downto 0 or array DEPTH WIDTH 1 downto 0 of std logic vector BUS WIDTH downto 0 the subtype is forward see below signal SRL SIG SRL ARRAY begin PROC SRL16 process CLK begin if CLK event and CLK 1 then if CE 1 then SRL SIG lt DATA amp SRL SIG 0 to DEPTH WIDTH 2 end if end if end process Q lt SRL SIG conv integer A end rtl Verilog Code Following is the Verilog code for a 16 bit dynamic shift register module dynamic srl Q CE CLK D A inpu
380. sitive Edge Clock CE Clock Enable active High Q Data Output VHDL Code Following is the equivalent VHDL code for the flip flop with a positive edge clock and clock enable library ieee use ieee std logic 1164 a11 entity flop is port C D CE in std logic Q out std logic end flop architecture archi of flop is begin process C begin if C event and C 1 then if CE 1 then Q lt D end if end if end process end archi 46 www xilinx com XST User Guide 1 800 255 7778 Registers XILINX Verilog Code Following is the equivalent Verilog code for the flip flop with a positive edge clock and clock enable module flop C D CE Q input C D CE output 0 reg Q always posedge C begin if C Q lt end endmodule D I tH 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable The following figure shows a 4 bit register with positive edge clock asynchronous set and clock enable PRE 8 FDPE CE c p The following table shows pin definitions for a 4 bit register with positive edge clock asynchronous set and clock enable IO Pins Description D 3 0 Data Input C Positive Edge Clock PRE Asynchronous Set active High CE Clock Enable active High Q 3 0 Data Output XST User Guide www xilinx com 47 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is
381. smallcntr is up to date Compiling vhdl file C temp timer statmach vhd in Library work Architecture inside of Entity statmach is up to date Compiling vhdl file C temp timer decode vhd in Library work Architecture behavioral of Entity decode is up to date Compiling vhdl file C temp timer cnt60 vhd in Library work Architecture inside of Entity cnt60 is up to date Compiling vhdl file C temp timer hex2led vhd in Library work Architecture hex2led_arch of Entity hex2led is up to date Compiling vhdl file C temp timer stopwatch vhd in Library work Architecture inside of Entity stopwatch is up to date HDL Analysis Analyzing Entity lt stopwatch gt Architecture lt inside gt WARNING Xst 7 lt tenths gt Entity lt stopwatch gt analyzed Unit lt stopwatch gt generated Analyzing Entity lt statmach gt Architecture lt inside gt ntity lt statmach gt analyzed Unit lt statmach gt generated E Analyzing Entity lt decode gt Architecture lt behavioral gt ntity lt decode gt analyzed Unit lt decode gt generated E Analyzing Entity lt cnt60 gt Architecture lt inside gt ntity lt cnt60 gt analyzed Unit lt cnt60 gt generated E Analyzing Entity lt smallcntr gt Architecture lt inside gt ntity lt smallcntr gt analyzed Unit lt smallcntr gt generated E Analyzing Entity lt hex2led gt Ar
382. ss end archi Note If there are not enough lines in the external data file XST will issue the following message ERROR Xst raminitfilel vhd line 40 Line RamFileLine has not enough elements for target lt RAM lt 63 gt gt Verilog Code XST does not support block RAM initialization in Verilog Limitations e Initialization is only valid for block RAM resources If you attempt to initialize distributed RAM XST ignores the initialization and issues a warning message e Initialization of inferred RAMs from RTL code is not supported via INIT constraints Use of INIT constraints is only supported if RAM primitives are directly instantiated from the UNISIM library XST User Guide www xilinx com 177 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques ROMs Using Block RAM Resources XST can use block RAM resources to implement ROMs with synchronous outputs or address inputs These ROMs are implement as single port block RAMs The use of block RAM resources to implement ROMs is controlled by the ROM_STYLE constraint Please see Chapter 5 Design Constraints for details about the ROM_SYTLE attribute Please see Chapter 3 FPGA Optimization for details on ROM implementation Here is a list of VHDL Verilog templates described below e ROM with registered output e ROM with registered address The following table shows pin descriptions for a registered ROM 10 Pins Description clk
383. ss Properties clicking the Synthesis Options tab enabling the Use Synthesis Constraints File option by clicking the check box clicking the value field for the Synthesis Constraints File option and typing the constraint file name You can also browse for an existing file to use by clicking the box to the right of the value field Also to quickly enable disable the use of a constraint file by XST you can check or uncheck the Use Synthesis Constraint File option in this same menu By selecting this option you invoke the iuc command line switch To specify the constraint file in command line mode use the uc switch with the run command See Chapter 10 Command Line Mode for details on the run command and running XST from the command line XCF Syntax and Utilization 244 The XCF syntax enables you to specify a specific constraint for the entire device globally or for specific modules in your design The XCF syntax is basically the same as the UCF syntax for applying constraints to nets or instances but with an extension to the syntax to allow constraints to be applied to specific levels of hierarchy You can use the keyword MODEL to define the entity module that the constraint is applied to If a constraint is applied to an entity module the constraint is applied to each instance of the entity module In general users should define constraints within the ISE process properties dialog box or the XST run script if runni
384. stages and MULT_STYLE is coded directly on a signal XST guides you via the HDL Advisor to specify the optimum number of register stages XST does this during the Advanced HDL Synthesis step If the number of registers placed after the multiplier exceeds the maximum required and shift register extraction is activated then XST implements the unused stages as shift registers Limitations e XST cannot pipeline hardware Multipliers implementation using MULT18X185 resource e XST cannot pipeline multipliers if registers contain asynch set reset or synch reset signals XST can pipeline if registers contain synch reset signals 116 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Log File HDL Synthesis Synthesizing Unit my mult Related source file is pipe mult l vhd Found 36 bit register for signal MULT Found 18 bit register for signal a in Found 18 bit register for signal b in Found 18x18 bit multiplier for signal mult res Found 36 bit register for signal pipe 1 Summary inferred 108 D type flip flop s inferred 1 Multiplier s Unit lt my_mult gt synthesized Advanced HDL Synthesis Found pipelined multiplier on the signal mult res with 1 pipeline level s INFO Xst HDL ADVISOR You can improve the performance of this multiplier by adding 3 register level s VHDL Code Use the following templates
385. std_logic_unsigned all entity raminfr is port clk in std_logic we in std logic wa in std logic vector 4 downto 0 ral in std logic vector 4 downto 0 ra2 in std logic vector 4 downto 0 di in std logic vector 3 downto 0 dol out std logic vector 3 downto 0 do2 out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer wa lt di end if end if end process dol lt RAM conv_integer ral do2 lt RAM conv_integer ra2 end syn XST User Guide www xilinx com 167 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Verilog Code Following is the Verilog code for a multiple port RAM module raminfr clk we wa ral ra2 di dol do2 input clk input we input 4 0 wa input 4 0 ral input 4 0 ra2 input 3 0 di output 3 0 dol output 3 0 do2 reg 3 0 ram 31 0 always posedge clk begin if we ram wa lt di end assign dol ram ral assign do2 ram ra2 endmodule Block RAM with Reset XST supports block RAM with reset on the data outputs as offered with Virtex Virtex II and related block RAM resources Optionally you can include a synchronously controlled initialization of the RAM data outputs Bloc
386. std_logic_unsigned all entity subtr is port A B in std_logic_vector 7 downto 0 RES out std logic vector 7 downto 0 end subtr architecture archi of subtr is begin RES lt A B end archi Verilog Code Following is the Verilog code for an unsigned 8 bit subtractor module subtr A B RES input 7 0 A input 7 0 B output 7 0 RES assign RES A B endmodule Unsigned 8 bit Adder Subtractor The following table shows pin descriptions for an unsigned 8 bit adder subtractor IO pins Description A 7 0 B 7 0 Add Sub Operands OPER Add Sub Select SUM 7 0 Add Sub Result VHDL Code Following is the VHDL code for an unsigned 8 bit adder subtractor library ieee use ieee std logic 1164 al use ieee std logic unsigned all entity addsub is port A B in std logic vector 7 downto 0 OPER in std logic RES out std logic vector 7 downto 0 end addsub architecture archi of addsub is begin RES lt A B when OPER 0 else A B end archi 110 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Verilog Code Following is the Verilog code for an unsigned 8 bit adder subtractor module addsub A B OPER RES input OPER input 7 0 A input 7 0 B output 7 0 RES reg 7 0 RES always A or B or OPER begin if OPER 1 b0 RES lt A B else RES lt A B en
387. ster 70 8 bit shift left register with negative edge clock clock enable serial In and serial out 74 404 www xilinx com 1 800 255 7778 XST User Guide XILINX 8 bit shift left register with positive edge clock asynchronous clear serial in and serial out 75 8 bit shift left register with positive edge clock asynchronous parallel load serial in and serial out 79 8 bit shift left register with positive edge clock serial in and parallel out 78 8 bit shift left register with positive edge clock serial In and serial out 72 8 bit shift left register with positive edge clock synchronous parallel load serial in and serial out 80 8 bit shift left register with positive edge clock synchronous set serial in and serial out 76 8 bit shift left shift right register with positive edge clock serial in and parallel out 81 shift register extraction 238 258 386 shift_extract 256 386 shreg_extract 258 386 signal declaration 316 signal encoding 254 signal_encoding 254 signed values 41 signed unsigned support 40 silent mode 365 simple names 317 slice names 317 slice packing 258 388 slice utilization ratio 237 259 388 slice utilization ratio delta 259 388 slice_packing 258 388 slice_utilization_ratio 259 388 slice_utilization_ratio_maxmargin 259 388 source_node 262 Spartan 19 Spartan 3 19 Spartan II 19 specify block 349 SRL16E 71 SRLC16 71 standard package 312
388. straints Guide for details e Mux Extraction The Mux Extract MUX_EXTRACT constraint enables or disables multiplexer macro inference For each identified multiplexer description based on some internal decision rules XST actually creates a macro or optimizes it with the rest of the logic See MUX_EXTRACT in the Constraints Guide for details e Register Power Up XST does not automatically figure out and enforce register power up values You must explicitly specify them if needed with the Register Power Up REGISTER_POWERUP constraint See REGISTER_POWERUP in the Constraints Guide for details e Resource Sharing The Resource Sharing RESOURCE_SHARING constraint enables or disables resource sharing of arithmetic operators See the RESOURCE SHARING in the Constraints Guide for details XST User Guide www xilinx com 253 1 800 255 7778 7 XILINX Chapter 5 Design Constraints e Recovery State The Recovery State SAFE_RECOVERY_STATE constraint defines a recovery state for use when a finite state machine FSM is implemented in Safe Implementation mode This means that if during its work the FSM gets into an invalid state XST generates additional logic to force the FSM to a valid recovery state See SAFE RECOVERY STATE and SAFE IMPLEMENTATION in the Constraints Guide for details e Safe Implementation The Safe Implementation SAFE IMPLEMENTATION constraint implements finite state machines FSMs in
389. subtractor during the Macro Recognition step Synthesizing Unit lt adder gt Related source file is arithmetic_operations_1 vhd Found 8 bit adder for signal sum Summary inferred 1 Adder Subtracter s Unit lt adder gt synthesized HDL Synthesis Report Macro Statistics Adders Subtractors 2d 8 bit adder EN d Related Constraints Related constraints are USE DSP48 and KEEP which are available for Virtex 4 devices www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Unsigned 8 bit Adder This subsection contains a VHDL and Verilog description of an unsigned 8 bit adder The following table shows pin descriptions for an unsigned 8 bit adder 10 pins Description A 7 0 B 7 0 Add Operands SUM 7 0 Add Result VHDL Code Following is the VHDL code for an unsigned 8 bit adder library ieee use ieee std logic 1164 a1l use ieee std logic unsigned all entity adder is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 end adder architecture archi of adder is begin SUM lt A B end archi Verilog Code Following is the Verilog code for an unsigned 8 bit adder module adder A B SUM input 7 0 A input 7 01 B output 7 0 SUM assign SUM A B endmodule Unsigned 8 bit Adder with Carry In This section contains VHDL and Verilog descriptions of an unsigned 8 bit adder
390. synchronous clear 68 add I O buffers 240 241 246 386 387 adder 104 simple signed 8 bit adder 109 unsigned 8 bit adder 105 unsigned 8 bit adder with carry in 105 unsigned 8 bit adder with carry in and carry out 108 unsigned 8 bit adder with carry out 106 adder subtractor 104 unsigned 8 bit adder subtractor 110 addition 325 advanced HDL synthesis 363 alias declaration 316 allclocknets 264 265 always statement 350 arch 385 Architecture 19 architecture 385 architecture body 314 architecture declaration 292 architecture support 19 arithmetic 325 arithmetic operation 104 array of instances 350 assert statement 310 assign statement 334 assignment extension past 32 bits 336 attribute 317 attribute declaration 316 automatic FSM extraction 253 385 begin model end 245 bit vector types 286 bitwise equivalence 326 bitwise exclusive or 326 bitwise inclusive or 326 bitwise negation 326 black box support 195 black_box 279 black_box_pad_pin 279 black_box_tri_pins 279 block multiplier 113 block RAM initial contents 174 block statement 328 blocking and nonblocking assignments 346 blocking assignment 349 blocking versus von blocking 337 box type 246 box_type 195 268 bram_map 256 268 buffer type 254 buffer_type 254 268 bufg 257 387 bufgce 254 268 bufgmux 254 bus delimiter 237 246 385 bus_delimiter 385 400 C case 237 384 400 case equality 326 case implementation style 87 238 239
391. synthesis but may also be used for simulation STANDARD Package The Standard package contains basic types bit bit vector and integer The STANDARD package is included by default IEEE Packages 312 The following IEEE packages are supported e std logic 1164 defines types std logic std ulogic std logic vector std ulogic vector and conversion functions based on these types e numeric bit supports types unsigned signed vectors based on type bit and all overloaded arithmetic operators on these types It also defines conversion and extended functions for these types e numeric std supports types unsigned signed vectors based on type std logic This package is equivalent to std logic arith e math real supports the following Real number constants as shown in the following table Constant Value Constant Value math e e math log of 2 1n2 math_1_over_e 1 e math_log_of_10 In10 math_pi T math_log2_of_e log5e math 2 pi 2n math log10 of e log pe math_1_over_pi 1 7 math_sqrt_2 A2 math pi over 2 n 2 math 1 oversqrt 2 1 42 www xilinx com XST User Guide 1 800 255 7778 Packages XILINX Constant Value Constant Value math_pi_over_3 1 3 math_sqrt_pi An math pi over 4 n 4 math deg to rad 21 360 math 3 pi over 2 31 2 math rad to deg 360 27 Real number functions as shown in the following table ceil x realmax x y
392. t CLK D CE input 3 0 A output 0 reg 15 0 data assign Q data A always posedge CLK begin if CE 1 b1 data lt data 14 0 D end endmodule Multiplexers XST supports different description styles for multiplexers MUXs such as If Then Else or Case When writing MUXs you must pay particular attention in order to avoid common traps For example if you describe a MUX using a Case statement and you do not specify all values of the selector you may get latches instead of a multiplexer Writing MUXs you can also use don t cares to describe selector values During the Macro Inference step XST makes a decision to infer or not infer the MUXs For example if the MUX has several inputs that are the same then XST can decide not to infer it If you do want to infer the MUX you can force XST by using the design constraint called MUX_EXTRACT XST User Guide www xilinx com 85 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques If you use Verilog then you must be aware that Verilog Case statements can be full or not full and they can also be parallel or not parallel A Case statement is e FULL if all possible branches are specified e PARALLEL if it does not contain branches that can be executed simultaneously The following tables gives three examples of Case statements with different characteristics Full and Parallel Case module full sel il i2 i3 i4 o1 input 1 0
393. t to exclude the first register stage from the DSP48 you must place KEEP constraints on the outputs of these registers XST User Guide www xilinx com 111 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Comparators lt lt gt gt This section contains a VHDL and Verilog description for an unsigned 8 bit greater or equal comparator Log File The XST log file reports the type and size of recognized comparators during the Macro Recognition step Synthesizing Unit lt compar gt Related source file is comparators l vhd Found 8 bit comparator greatequal for signal n0000 created at line 10 Summary inferred 1 Comparator s Unit compar synthesized HDL Synthesis Report Macro Statistics Comparators Fai 8 bit comparator greatequal I Unsigned 8 bit Greater or Equal Comparator The following table shows pin descriptions for a comparator 10 pins Description A 7 0 B 7 0 Comparison Operands CMP Comparison Result VHDL Code Following is the VHDL code for an unsigned 8 bit greater or equal comparator library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity compar is port A B in std logic vector 7 downto 0 CMP out std logic end compar architecture archi of compar is begin CMP lt 1 when A gt B else 0 end archi 112 www xilinx com XST User Guide 1 800 255 7778 Arithmet
394. tatement is accepted in such an always block An asynchronous part may appear before the synchronous part in the first and the second branch of the If else statement Signals assigned in the asynchronous part must be assigned to the constant values 0 1 X or Z or any vector composed of these values www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX These same signals must also be assigned in the synchronous part that is the last branch of the if else statement The clock signal condition is the condition of the last branch of the if else statement The following example gives the description of an 8 bit register Example 7 6 8 Bit Register Using an Always Block module seql DI CLK DO input 7 0 DI input CLK output 7 0 DO reg 7 0 DO always posedge CLK DO lt DI endmodule The following example gives the description of an 8 bit register with a clock signal and an asynchronous reset signal Example 7 7 8 Bit Register with Asynchronous Reset high true Using an Always Block module EXAMPLE DI CLK RST DO input 7 0 DI input CLK RST output 7 0 DO reg 7 0 DO always posedge CLK or posedge RST if RST 1 b1 DO lt 8 b00000000 else DO lt DI endmodule The following example describes an 8 bit counter Example 7 8 8 Bit Counter with Asynchronous Reset low true Using an Always Block module seq2 CLK RST
395. tation style can be manually forced to use block multiplier or LUT resources available in the Spartan 3 Virtex II Virtex II Pro Virtex II Pro X and Virtex 4 devices Please note that pipe_block is supported for Virtex 4 devices only See MULT_STYLE in the Constraints Guide for details www xilinx com XST User Guide 1 800 255 7778 FPGA Constraints non timing 7 XILINX XST User Guide Mux Style The Mux Style MUX_STYLE constraint controls the way the macrogenerator implements the multiplexer macros See MUX_STYLE in the Constraints Guide for details Number of Global Clock Buffers The Number of Global Clock Buffers bufg constraint controls the maximum number of BUFGs created by XST The constraint value is an integer The default value depends on the target family and is equal to the maximum number of available BUFGs Define this option globally with the bufg command line option of the run command Following is the basic syntax bufg integer The constraint value is an integer and the default values are different for different architectures The defaults for selected architectures are 4 for Virtex Virtex E Spartan II Spartan IIE 8 for Spartan 3 16 for Virtex II Virtex II Pro Virtex II Pro X and 32 for Virtex 4 The number of BUFGs cannot exceed the maximum number of BUFGs for the target device In Project Navigator specify bufg globally by selecting the Nu
396. td logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 end mult architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 2 pipe 3 unsigned A port size B port size 1 downto 0 begin process clk begin if clk event and clk 1 then a in lt A b in lt B mult res lt a in b in pipe 2 lt mult res pipe 3 lt pipe 2 MULT lt pipe 3 end if end process end beh 118 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX The following VHDL template shows the multiplication operation placed outside the process block and the pipeline stages represented as shift registers library ieee use ieee std_logic_1164 all use ieee numeric_std all entity mult is generic A_port_size integer 18 B_port_size integer 18 port clk in std logic A in unsigned A_port_size 1 downto 0 B in unsigned B_port_size 1 downto 0 MULT out unsigned A_port_size B_port_size 1 downto 0 end mult architecture beh of mult is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 type pipe reg type is array 2 downto 0 of unsigned A port size B port size 1 do
397. td_logic_vector 3 downto 0 do out std_logic_vector 3 downto 0 end raminfr XST User Guide www xilinx com 143 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv_integer a lt di end if do lt RAM conv_integer a end if end process end syn Verilog Following is the Verilog code for a single port RAM with false synchronous read module raminfr clk we a di do input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram 31 0 reg 3 0 do always posedge clk begin if we ram a lt di do lt ram a end endmodule The following descriptions featuring an additional reset of the RAM output are also only mappable onto Distributed RAM with an additional resetable buffer on the data output as shown in the following figure RST Distributed DO RAM X8978 144 www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX The following table shows pin descriptions for a single port RAM with false synchronous read and reset on the output 10 Pins Description clk Positive Edge Clock we Synchronous Write Enable active High rst Synchronous Output Reset active High a
398. te nand pure srl buffer generic new range subtype bus group next record then case guarded nor register to component if not reject transport 320 www xilinx com XST User Guide 1 800 255 7778 7 XILINX Chapter 7 Verilog Language Support Introduction XST User Guide This chapter contains the following sections e Introduction e Behavioral Verilog Features e Variable Part Selects e Structural Verilog Features e Parameters e Parameter Attribute Conflicts e Verilog Limitations in XST e Verilog Meta Comments e Verilog Language Support Tables e Primitives e Verilog Reserved Keywords e Verilog 2001 Support in XST For detailed information about Verilog design constraints and options refer to Chapter 5 Design Constraints For information about the Verilog attribute syntax see Verilog Meta Comment Syntax in Chapter 5 For information on setting Verilog options in the Process window of Project Navigator refer to General Constraints in Chapter 5 Complex circuits are commonly designed using a top down methodology Various specification levels are required at each stage of the design process As an example at the architectural level a specification may correspond to a block diagram or an Algorithmic State Machine ASM chart A block or ASM stage corresponds to a register transfer block for example register adder counter
399. ted by D www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Verilog Assignments There are two forms of assignment statements in the Verilog language e Continuous Assignments e Procedural Assignments Continuous Assignments Continuous assignments are used to model combinatorial logic in a concise way Both explicit and implicit continuous assignments are supported Explicit continuous assignments are introduced by the assign keyword after the net has been separately declared Implicit continuous assignments combine declaration and assignment Note Delays and strengths given to a continuous assignment are ignored by XST Example of an explicit continuous assignment wire par_eq_l assign par eq 1 select b a Example of an implicit continuous assignment wire temp hold a b Note Continuous assignments are only allowed on wire and tri data types Procedural Assignments Procedural assignments are used to assign values to variables declared as regs and are introduced by always blocks tasks and functions Procedural assignments are usually used to model registers and FSMs XST includes support for combinatorial functions combinatorial and sequential tasks and combinatorial and sequential always blocks Combinatorial Always Blocks Combinatorial logic can be modeled efficiently using two forms of time control the and Verilog time control statements The time control
400. ted to signal di data out connected to signal do ram style Auto INFO Xst For optimized device usage and improved timings you may take advantage of available block RAM resources by Summary registering the read address inferred 1 RAM s Unit raminfr synthesized RAMs HDL Synthesis Report Macro Statistics 128 bit single port distributed RAM 1 Related Constraints XST User Guide Related constraints are RAM_EXTRACT RAM_STYLE ROM_EXTRACT and ROM_STYLE www xilinx com 135 1 800 255 7778 XILINX 136 Chapter 2 HDL Coding Techniques Beginning in release 7 1i XST accepts LOC and RLOC constraints on inferred RAMs that can be implemented in a single block RAM primitive The LOC and RLOC constraints are propagated to the NGC netlist Virtex II Spartan 3 RAM Read Write Modes Block RAM resources available in Virtex II II Pro II Pro X and Spartan 3 offer different read write synchronization modes This section provides coding examples for all three modes that are available write first read first and no change The following examples describe a simple single port block RAM You can deduce descriptions of dual port block RAMs from these examples Dual port block RAMs can be configured with a different read write mode on each port Inference supports this capability The following table summarizes support for read write modes according to the targeted famil
401. ter 227 231 fitter multi level optimization 231 log file 375 log file analysis 229 low level optimization 231 synthesis options 227 target options 386 cross clock analysis 237 263 cross_clock_analysis 263 387 CSD 114 custom compile file list 237 242 XST User Guide www xilinx com 1 800 255 7778 401 XILINX D data gate 261 data types 324 data_gate 261 deassign statement 334 decoder 93 one cold 94 95 one hot 93 94 unselected outputs 95 decoder extraction 238 255 386 decoder extract 255 268 386 defaultinitial values on memory elements 290 default initial values on unconnected ports 291 default nettype 350 default search order 359 define 350 defparam 350 delay 349 design constraints 233 design entities and configurations 314 device utilization summary 364 DFF with positive edge clock 42 disable statement 350 disconnection 317 divider 130 division by constant 2 130 division 326 drive strength 349 DSP48 122 203 DSP48 block resources 203 dump directory 382 dumpdir 390 duplication suffix 248 384 duplication suffix 248 384 400 dynamic shift register 82 16 bit dynamic shift register with positive edge clock serial in and serial out 83 E elaborate command 391 else 350 elsif 350 enable auto floorplanning 237 enable cross clock domain optimization 387 enable floorplanning 255 enable auto floorplanning 255 268 encoding algorithm 385 encrypted modules 364 end
402. th all use ieee std logic unsigned all entity counter is generic MAX integer 16 port C CLR in std logic Q out integer range 0 to MAX 1 end counter architecture archi of counter is signal cnt integer range 0 to MAX 1 begin process C CLR begin if CLR 1 then cnt lt 0 elsif rising edge C then cnt lt cnt 1 mod MAX end if end process Q lt cnt end archi 66 www xilinx com XST User Guide 1 800 255 7778 Accumulators XILINX Verilog Code Following is the Verilog code for a 4 bit signed up counter with an asynchronous reset and a modulo maximum module counter C CLR O parameter MAX SQRT 4 MAX MAX SQRT MAX SQRTI input C CLR output MAX SQRT 1 0 Q reg MAX SQRT 1 0 cnt always posedge C or posedge CLR begin if CLR cnt 0 else cnt lt cnt 1 MAX end assign Q cnt endmodule Related Constraints There are no related constraints available Accumulators An accumulator differs from a counter in the nature of the operands of the add and subtract operation e Jna counter the destination and first operand is a signal or variable and the other operand is a constant equal to 1 A lt A 1 e Inan accumulator the destination and first operand is a signal or variable and the second operand is either asignalor variable A lt A B aconstant not equal to 1 A lt A Constant An inferred accumulat
403. the name of top level block XST cannot detect design modifications and resynthesize the top level block Force resynthesis by using the RESYNTHESIZE constraint Speed Optimization Under Area Constraint XST performs timing optimization under area constraint This option Slice Utilization Ratio is available under the XST Synthesis Options in the Process Properties dialog box in Project Navigator By default this constraint is set to 100 of the selected device size This constraint has influence at low level synthesis only it does not control the inference process If this constraint is specified XST makes an area estimation and if the specified constraint is met XST continues timing optimization trying not to exceed the constraint If the size of the design is more than requested then XST tries to reduce the area first and if the area constraint is met then starts timing optimization In the following example the area constraint was specified as 100 and initial estimation shows that in fact it occupies 102 of the selected device XST starts optimization and reaches 95 Low Level Synthesis Found area constraint ratio of 100 5 on block tge actual ratio is 102 Optimizing block tge to meet ratio 100 5 of 1536 slices Area constraint is met for block tge final ratio is 95 If the area constraint cannot be met then XST ignores it during timing optimization and runs low level synthesis
404. the rest of your design You can do this in XST by using black box instantiation in the VHDL Verilog code The netlist is propagated to the final top level netlist without being processed by XST Moreover XST enables you to attach specific constraints to these black box instantiations which are passed to the NGC file In addition you may have a design block for which you have an RTL model as well as your own implementation of this block in the form of an EDIF netlist The RTL model is only valid for simulation purposes but by using the BOX_TYPE constraint you can direct XST to skip synthesis of this RTL code and create a black box The EDIF netlist is linked to the synthesized design during NGDBuild Please see General Constraints in Chapter 5 for more information Also see the Constraints Guide for details Note Remember that once you make a design a black box each instance of that design is a black box While you can attach constraints to the instance XST ignores any constraint attached to the original design From the flow point of view the recognition of black boxes in XST is done before the macro inference process Therefore the LOG file differs from the one generated for other macros Analyzing Entity lt black_b gt Architecture lt archi gt WARNING Xst 766 black_box_l vhd Line 15 Generating a Black Box for component lt my_block gt Entity lt black_b gt analyzed Unit lt black_b gt generated
405. ther signed or unsigned The content is similar to the combinatorial always block content Note Recursive function and task calls are not supported Example 7 9 shows a function declared within a module The ADD function declared is a single bit adder This function is called 4 times with the proper parameters in the architecture to create a 4 bit adder The same example described with a task is shown in Example 7 10 Example 7 9 Function Declaration and Function Call module comb15 A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT wire 1 0 SO S1 S2 S3 function signed 1 0 ADD input A B CIN reg S COUT begin S A B CIN COUT A amp B A amp CIN B amp CIN ADD COUT S end endfunction assign SO ADD A 0 B 0 CIN S1 ADD A 1 B 1 SO 1 S2 ADD A 2 B 2 1 1 S3 ADD A 3 B 3 S2 1 S S3 0 S2 0 S1 0 SOLO Jy COUT S3 1 endmodule 336 www xilinx com XST User Guide 1 800 255 7778 Behavioral Verilog Features XILINX Example 7 10 Task Declaration and Task Enable module EXAMPLE A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT reg 3 0 S reg COUT reg 1 0 SO S1 S2 S3 task ADD input A B CIN output 1 0 C reg 1 0 C reg S COUT begin S A B CIN COUT A amp B A amp CIN B amp CIN C COUT S end endtask always A or B or CIN begin
406. tiated primitive e Pass the INIT via the generics mechanism in VHDL or the parameters mechanism in Verilog Xilinx recommends this method as it allows you to use the same code for synthesis and simulation VHDL Code Following is the VHDL code for passing an INIT value via the INIT constraint library ieee use ieee std_logic_1164 all library unisim use unisim vcomponents all entity lut2_attribute is port 10 11 in std_logic O out std logic end lut2 attribute XST User Guide www xilinx com 219 1 800 255 7778 XILINX Chapter 3 FPGA Optimization architecture beh of lut2_attribute is attribute INIT string attribute INIT of inst label is 1 begin inst LUT2 port map I0 gt I0 I1 gt I1 0 gt 0 5 end beh Following is the VHDL code for passing an INIT value via the generics mechanism library ieee use leee std_logic_1164 all library unisim use unisim vcomponents all entity lut2_generics is port LQ II in std_logic O out std_logic end lut2_generics architecture beh of lut2_generics is begin inst LUT2 generic map INIT gt 1 port map I10 gt I0 11 gt I1 0 gt 0 end beh Verilog Code Following is the Verilog code for passing an INIT value via the INIT constraint module vlut2_attribute I0 I1 0 input 10 11 output 0 LUT2 inst IO IO 11 11 0 0 5 synthesis attribute INIT of inst is 2 endmodule Following is the V
407. tions Define this option globally with the pld_mp command line option of the run command Following is the basic syntax www xilinx com 261 1 800 255 7778 XILINX 262 Chapter 5 Design Constraints pld mp yes no The default is yes In Project Navigator specify this option globally with the Macro Preserve option in the Xilinx Specific Options tab of the Process Properties dialog box No Reduce The No Reduce NOREDUCE constraint prevents minimization of redundant logic terms that are typically included in a design to avoid logic hazards or race conditions This constraint also identifies the output node of a combinatorial feedback loop to ensure correct mapping See NOREDUCE in the Constraints Guide for details WYSIWYG The goal of the WYSIWYG option is to have a netlist as much as possible reflect the user specification That is all the nodes declared in the HDL design are preserved If WYSIWYG mode is enabled yes then XST preserves all the user internal signals nodes creates SOURCE NODE constraints in the NGC file for all these nodes and skips design optimization collapse factorization only boolean equation minimization is performed Define globally with the wysiwyg command line option of the run command Following is the basic syntax wysiwyg yes no The default is no The constraint can also be defined globally with the WYSIWYG option in the Xilinx Specific Options tab in the Process Properties di
408. to a specific block of a design Please refer to the Constraint Guide for more information XST User Guide www xilinx com 213 1 800 255 7778 XILINX Chapter 3 FPGA Optimization Log File Analysis The XST log file related to FPGA optimization contains the following sections 214 Design optimization Resource usage report Timing report Design Optimization During design optimization XST reports the following Potential removal of equivalent flip flops Two flip flops latches are equivalent when they have the same data and control pins Register replication Register replication is performed either for timing performance improvement or for satisfying MAX_FANOUT constraints Register replication can be turned off using the REGISTER_DUPLICATION constraint Following is a portion of the log file Starting low level synthesis Optimizing unit lt down4cnt gt Optimizing unit lt doc_readwrite gt Optimizing unit lt doc gt Building and optimizing final netlist Register doc_readwrite_state_D2 equivalent to doc_readwrite_cnt_ld has been removed Register I cci i2c wr l equivalent to wr_l has been removed Register doc reset I reset out has been replicated 2 time s Register wr l has been replicated 2 time s Resource Usage In the Final Report the Cell Usage section reports the count of all the primitives used in the design These primitives are classified in the following groups
409. to preserve the case of your Verilog module In Project Navigator select Maintain for the Case option under the Synthesis Options tab in the Process Properties dialog box or set the case command line option to maintain at the command line 2 Instantiate your Verilog component as if you were instantiating a VHDL component www xilinx com XST User Guide 1 800 255 7778 VHDL Verilog Boundary Rules XILINX Note Using a VHDL configuration declaration one could attempt to bind this component to a particular design unit from a particular library Please note that such binding is not supported Only default Verilog module binding is supported The only Verilog construct that can be instantiated in a VHDL design is a Verilog module No other Verilog constructs are visible to VHDL code During elaboration all components subject to default binding are regarded as design units with the same name as the corresponding component name In the binding process XST treats a component name as a VHDL design unit name and searches for it in the logical library work If a VHDL design unit is found then XST binds it If XST cannot find a VHDL design unit it treats the component name as a Verilog module name and searches for it using a case sensitive search XST searches for the Verilog module in the user specified list of unified logical libraries in the user specified search order See Library Search Order File for search order details XST selects
410. tomatic Recognition Available For xc_pullup Synplicity pullup pullup VHDL Verilog xc_rloc Synplicity rloc yes VHDL Verilog xc_fast Synplicity fast na VHDL Verilog xc_slow Synplicity na na na xc_uset Synplicity u set yes VHDL Verilog You must use the KEEP constraint instead of SIGNAL PRESERVE Verilog example module testkeep inl in2 out1 input inl input in2 output outl wire auxl wire aux2 synthesis attribute keep of auxl is true synthesis attribute keep of aux2 is true assign auxl inl assign aux2 in2 assign outl auxl amp aux2 endmodule The KEEP constraint can also be applied through the separate synthesis constraint file XCF Example Syntax BEGIN MODEL testkeep NET auxl KEEP true END These are the only two ways of preserving a signal net in an HDL design and preventing optimization on the signal or net during synthesis Constraints Precedence 282 Priority depends on the file in which the constraint appears A constraint in a file accessed later in the design flow overrides a constraint in a file accessed earlier in the design flow Priority is as follows first listed is the highest priority last listed is the lowest Synthesis Constraint File 2 HDL file 3 Command Line Process Properties dialog box in Project Navigator www xilinx com 1 800 255 7778 XST User Guide XILINX Chapter 6 VHDL L
411. traint The related constraint is RESOURCE SHARING Example For the following VHDL Verilog example XST gives the following solution B C RES A OPER OPER X8984 132 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX The following table shows pin descriptions for the example 10 pins Description A 7 0 B 7 0 C 7 0 Operands OPER Operation Selector RES 7 0 Data Output VHDL Code Following is the VHDL example for resource sharing library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity addsub port A B C OPER in end addsub architecture archi of addsub is begin RES lt A end archi Verilog Code Following is the Verilog code for resource sharing module addsub A B C OPER RE input OPER is in std_logic_vector 7 downto 0 std_logic RES out std_logic_vector 7 downto 0 B when OPER 0 input 7 0 A input 7 0 input 7 0 output 7 0 reg 7 0 RE always A o begin if OPER RES lt A else RES lt A end endmodule B C RES S r B or C or OPER 1 b0 Bs ls S XST User Guide www xilinx com 1 800 255 7778 133 XILINX RAMs ROMs 134 Chapter 2 HDL Coding Techniques If you do not want to instantiate RAM primitives to keep your HDL code technology independent
412. traints of third party synthesis vendors that are supported by XST For each of the constraints Table 5 4 gives the XST equivalent For information on what these constraints actually do please refer to the corresponding vendor documentation Note that NA stands for Not Available Table 5 4 Third Party Constraints Name Vendor XST Equivalent Automatic Recognition Available For black_box Synplicity box_type na VHDL Verilog black_box_pad_pin Synplicity na na na black_box_tri_pins Synplicity na na na cell list Synopsys na na na clock list Synopsys na na na Enum Synopsys na na na full_case Synplicity full_case na Verilog Synopsys ispad Synplicity na na na map_to_module Synopsys na na na net_name Synopsys na na na parallel_case Synplicity parallel_case na Verilog Synopsys return_port_name Synopsys na na na resource_sharing directives Synopsys resource_sharing na VHDL directives Verilog set_dont_touch_network Synopsys not required na na set_dont_touch Synopsys not required na na set_dont_use_cel_name Synopsys not required na na set_prefer Synopsys na na na state_vector Synopsys na na na syn_allow_retiming Synplicity register balancing na VHDL Verilog XST User Guide www xilinx com 1 800 255 7778 279 XILINX Table 5 4 Third Party Constraints Chapter 5 Design Constraints
413. transitions on those pins See DATA GATE in the Constraints Guide for details Keep Hierarchy This option is related to the hierarchical blocks VHDL entities Verilog modules specified in the HDL design and does not concern the macros inferred by the HDL synthesizer The Keep Hierarchy KEEP HIERARCHY constraint enables or disables hierarchical flattening of user defined design units and controls whether it is passed on as an implementation constraint See KEEP HIERARCHY in the Constraints Guide for details Macro Preserve The Macro Preserve pld mp option is useful for making the macro handling independent of design hierarchy processing This allows you to merge all hierarchical blocks in the top module while still keeping the macros as hierarchical modules You can also keep the design hierarchy except for the macros which are merged with the surrounding logic Merging the macros sometimes gives better results for design fitting Two values are available for this option yes check box is checked macros are preserved and generated by Macro no check box is not checked macros are rejected and generated by HDL synthesizer Depending on the Flatten Hierarchy value a rejected macro becomes a hierarchical block Flatten Hierarchy no or is merged in the design logic Flatten Hierarchy yes Very small macros 2 bit adders 4 bit multiplexers are always merged independent of the Macro Preserve or Flatten Hierarchy op
414. true the first statement is executed If the expression evaluates to false or x or z the else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested The following example shows how a MUX can be described using an If else statement Example 7 2 MUX Description Using If Else Statement module mux4 sel a b c d outmux input 1 0 sel input 1 0 a b c d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d begin if sel 1 if sel 0 outmux d else outmux Cc else if sel 0 outmux b else outmux 7 a end endmodule Case Statement Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The Case statement evaluates the branches in the order they are written The first branch that evaluates to true is executed If none of the branches match the default branch is executed Note Do not use unsized integers in case statements Always size integers to a specific number of bits or results can be unpredictable Casez treats all z values in any bit position of the branch alternative as a don t care Casex treats all x and z values in any bit position of the branch alternative as a don t care The question mark can be used as a don t care in either the casez or casex case statements The following example shows how a MUX can be described using
415. ttribute specified on an instance overrides a generic specified on a component in XST it is possible that your simulation tool may nevertheless use the generic This may cause the simulation results to not match the synthesis results Use the following matrix as a guide in determining precedence Generic on an Instance Generic on a Component Attribute Apply Generic Apply Attribute on an Instance XST issues warning message possible simulation mismatch Attribute Apply Generic Apply Generic on a Component XST issues warning message Attribute in XCF Apply Attribute Apply Attribute XST issues warning message Note Security attributes on the block definition always have higher precedence than any other attribute or generic Combinatorial Circuits The following subsections describe how XST uses various VHDL constructs for combinatorial circuits Concurrent Signal Assigaments Combinatorial logic may be described using concurrent signal assignments which can be defined within the body of the architecture VHDL offers three types of concurrent signal assignments simple selected and conditional You can describe as many concurrent statements as needed the order of concurrent signal definition in the architecture is irrelevant A concurrent assignment is made of two parts left hand side and right hand side The assignment changes when any signal in the right part changes In this case the result is
416. tween two states One hot encoding is very appropriate with most FPGA targets where a large number of flip flops are available It is also a good alternative when trying to optimize speed or to reduce power dissipation Gray Gray encoding guarantees that only one bit switches between two consecutive states It is appropriate for controllers exhibiting long paths without branching In addition this coding technique minimizes hazards and glitches Very good results can be obtained when implementing the state register with T flip flops Compact Compact encoding consists of minimizing the number of bits in the state variables and flip flops This technique is based on hypercube immersion Compact encoding is appropriate when trying to optimize area Johnson Like Gray Johnson encoding shows benefits with state machines containing long paths with no branching Sequential Sequential encoding consists of identifying long paths and applying successive radix two codes to the states on these paths Next state equations are minimized Speed1 Speed1 encoding is oriented for speed optimization The number of bits for a state register depends on the particular FSM but generally it is greater than the number of FSM states www xilinx com 191 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques User In this mode XST uses original encoding specified in the HDL file For example if you use enumerated types for a state register
417. ual Read Address di Data Input dol Primary Output Port do2 Dual Output Port VHDL Code Following is the VHDL code library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clkl in std logic Clk2 in std logic we in std logic addl in std logic vector 4 downto 0 add2 in std logic vector 4 downto 0 di in std logic vector 3 downto 0 dol out std logic vector 3 downto 0 do2 out std logic vector 3 downto 0 end raminfr architecture syn of raminfr is type ram type is array 31 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal read add1l std logic vector 4 downto 0 signal read add2 std logic vector 4 downto 0 begin process clkl begin if clkl event and clk1 1 then if we 1 then RAM conv_integer add1 lt di end if read_addl lt addl end if end process dol lt RAM conv_integer read addl process clk2 begin if clk2 event and clk2 1 then read add2 lt add2 end if end process do2 lt RAM conv_integer read_add2 end syn XST User Guide www xilinx com 155 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques 156 Verilog Code Following is the Verilog code module raminfr clkl clk2 we addra addrb di doa dob input clk1 clk2 input we input 4 0 addra input 4 0 addrb input 3 0 di output 3 0 doa output 3 0 dob reg 3 0 ra
418. ult to implement FSMs by using the FS5M STYLE design constraint See FSM STYLE in the Constraints Guide for details Resynthesize The RESYNTHESIZE constraint is related to Incremental Synthesis Flow It forces or prevents resynthesis of groups created via the INCREMENTAL SYNTHESIS constraint See RESYNTHESIZE and INCREMENTAL SYNTHESIS in the Constraints Guide for details www xilinx com 255 1 800 255 7778 XILINX 256 Chapter 5 Design Constraints Incremental Synthesis The Incremental Synthesis INCREMENTAL_SYNTHESIS constraint controls the decomposition of a design into several subgroups This can be applied on a VHDL entity or Verilog module so that XST generates a single and separate NGC file for it and its descendents See the Incremental Synthesis Flow in Chapter 3 as well as INCREMENTAL SYNTHESIS in the Constraints Guide for details Note The INCREMENTAL_SYNTHESIS switch is not accessible via the Synthesize XST Process Properties dialog box This directive is only available via VHDL attributes or Verilog meta comments or via an XST constraint file Keep Hierarchy XST may automatically flatten the design to get better results by optimizing entity module boundaries You can use the Keep Hierarchy KEEP_HIERARCHY constraint to preserve the hierarchy of your design In addition this constraint may be propagated to the NGC file as an implementation constraint depending on its value See KEEP
419. ust start with a dash For the previous command example the stopwatch xst file should look like the following run ifn watchver prj ifmt mixed ofn watchver ngc ofmt NGC p xcv50 bg256 6 opt mode Speed opt level 1 www xilinx com 397 1 800 255 7778 7 XILINX Chapter 10 Command Line Mode 398 www xilinx com XST User Guide 1 800 255 7778 XILINX Appendix A XST Naming Conventions This appendix discusses net naming and instance naming conventions The appendix contains the following sections e Net Naming Conventions e Instance Naming Conventions e Name Generation Control Net Naming Conventions These rules are listed in order of naming priority 1 Maintain external pin names 2 Keep hierarchy in signal names using underscores as hierarchy designators 3 Maintain output signal names of registers including state bits Use the hierarchical name from the level where the register was inferred 4 Ensure that output signals of clock buffers get _clockbuffertype like BUFGP or _IBUFG follow the clock signal name 5 Maintain input nets to registers and tristates names 6 Maintain names of signals connected to primitives and black boxes Name output net names of IBUFs using the form net name IBUF For example for an IBUF with an output net name of DIN the output IBUF net name is DIN IBUF Name input net names to OBUFs using the form net name OBUEF For example for an OB
420. ut 116 pld_ce 260 386 pld_ffopt 386 pld_mp 261 pld_xp 262 386 power 326 priority encoder 3 bit 1 of 9 priority encoder 98 priority encoder extraction 238 257 386 priority encoders 98 priority_extract 98 257 271 386 procedure 308 project file 391 project file name 384 Project Navigator 22 Q quiet mode 364 R RAM extract 386 RAM extraction 238 258 RAM style 238 258 386 RAM ROM 134 block RAM with reset 168 dual port block RAM with different clocks 161 dual port block RAM with two write ports 163 dual port RAM with asynchronous read 149 dual port RAM with enable on each port 159 dual port RAM with false synchro nous read 151 dual Port RAM with one enable con trolling both ports 156 dual port RAM with synchronous read read through 153 initializing block RAM 174 multiple port RAM 166 no change mode 139 ROM using block RAM resources 178 ROM with registered address 178 ROM with registered output 178 single port RAM with asynchronous read 141 single port RAM with enable 148 single port RAM with false synchro nous read 143 single port RAM with synchronous read read through 146 write first mode 137 ram extract 258 271 386 ram style 258 271 386 read cores 237 259 387 read cores 259 387 real constants 348 record types 288 recovery state 254 recovery state 194 254 recursive component instantiation 294 reduction and 326 reduction nand 326 reduction nor 326 redu
421. utp input clk reset xl output outp reg outp reg 1 0 state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 always posedge clk or posedge reset begin if reset begin state lt sl outp lt 1 b1 end else begin case state sl begin if x1 1 b1 begin state lt s2 outp lt 1 b1 end else begin state lt s3 outp lt 1 b1 end end s2 begin state lt s4 outp lt 1 b0 end s3 begin state lt s4 outp lt 1 b0 end s4 begin state lt sl outp lt 1 b1 end endcase end end endmodule XST User Guide www xilinx com 185 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques FSM with 2 Processes To eliminate a register from the outputs you can remove all assignments outp lt from the Clock synchronization section This can be done by introducing two processes as shown in the following figure State b Outputs ij Register Function Inputs Function Only for Mealy Machine PROCESS 1 PROCESS 2 X8986 VHDL Code Following is VHDL code for an FSM with two processes library IEEE use IEEE std logic 1164 a11 entity fsm is port clk reset xl IN std logic outp OUT std logic end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state state type begin processi process clk reset begin if reset 1 then state lt sl elsif
422. ux style Mux Style auto MUXF MUXCY decoder extract Decoder Extraction yes no priority extract Priority Encoder Extraction yes no force safe implementation Safe Implementation yes no shreg extract Shift Register Extraction yes no shift extract Logical Shift Extraction yes no xor collapse XOR Collapsing yes no resource sharing Resource Sharing yes no use dsp48 Use DSP48 Resources auto yes no Table 10 5 Target Options 9500 9500XL 9500XV XPLA3 CoolRunner II Run Command register_removal Options Description Values iobuf Add I O Buffers yes no pld_mp Macro Preserve yes no pld xp XOR Preserve yes no keep hierarchy Keep Hierarchy yes soft no pld ce Clock Enable yes no pld ffopt Flip Flop Optimization yes no wysiwyg What You See Is What You Get yes no equivalent Equivalent Register Removal yes no www xilinx com 1 800 255 7778 XST User Guide Run Command XILINX Table 10 6 Target Options Virtex Virtex E Virtex II Virtex Il Pro Virtex Il Pro X Virtex 4 Spartan II Spartan IIE Spartan 3 Run Command Options Description Values bufg Maximum Number of integer BUFGs created by XST Default 4 Virtex E Spartan II E Default 8 Spartan 3 Default 16 Virtex II II Pro II Pro X Default 32 Virtex 4 bufr Maximum
423. v has been added to an ISE project directory and is specified with an include conflicts may occur and an error message displays ERROR Xst 1068 fifo v line 2 Duplicate declarations of module RAMB4_S8_S8 Comments There are two forms of comments in Verilog similar to the two forms found in a language like C e Allows definition of a one line comment e You can define a multi line comment by enclosing it as illustrated by this sentence Generate Statement XST User Guide Generate is a construct that allows you to dynamically create Verilog code from conditional statements This allows you to create repetitive structures or structures that are only appropriate under certain conditions Structures that are likely to be created via a generate statement are e primitive or module instances e initial or always procedural blocks e continuous assignments e net and variable declarations e parameter redefinitions e task or function definitions www xilinx com 339 1 800 255 7778 XILINX Chapter 7 Verilog Language Support XST supports the following types of generate statements e generate for e generate if e generate case Generate For Use a generate for loop to create one or more instances that can be placed inside a module Use the generate for loop the same way you would a normal Verilog for loop with the following limitations e The index for a generate for loop must have a genvar
424. variable e The assignments in the for loop control must refer to the genvar variable e The contents of the for loop must be enclosed by begin and end statements and the begin statement must be named with a unique qualifier The following is an example of an 8 bit adder using a generate for loop generate genvar i for i 0 i lt 7 i i 1 begin for_name adder add a 8 i 7 8 i b 8 i 7 8 i ci i sum for 8 i 7 8 i cO or i 1 end endgenerate Generate If else A generate if statement can be used inside a generate block to conditionally control what objects get generated The following is an example of a generate If else statement The generate controls what type of multiplier is instantiated Please note that the contents of each branch of the if else statement must be enclosed by begin and end statements and the begin statement must be named with a unique qualifier generate if IF_WIDTH lt 10 begin if_name adder IF_WIDTH ul a b sum_if end else begin else_nam subtractor IF_WIDTH u2 a b sum_if end endgenerate Generate Case A generate case statement can be used inside a generate block to conditionally control what objects get generated Use a generate case statement when there are several conditions to be tested to determine what the generated code would be Please note that each test statement in a generate case statement must be enclosed by begin and end statements
425. vated Arrays Verilog allows arrays of reg and wires to be defined as in the following two examples reg 3 0 mem array 31 0 The above describes an array of 32 elements each 4 bits wide which can be assigned via behavioral Verilog code wire 7 0 mem array 63 0 The above describes an array of 64 elements each 8 bits wide which can only be assigned via structural Verilog code Multi dimensional Arrays XST supports multi dimensional array types of up to three dimensions Multi dimensional arrays can be any net or any variable data type You can code assignments and arithmetic operations with arrays but you cannot select more than one element of an array at one XST User Guide www xilinx com 323 1 800 255 7778 XILINX Chapter 7 Verilog Language Support time You cannot pass multi dimensional arrays to system tasks or functions or regular tasks or functions Examples The following describes an array of 256 x 16 wire elements each 8 bits wide which can only be assigned via structural Verilog code wire 7 0 array2 0 255 0 15 The following describes an array of 256 x 8 register elements each 64 bits wide which can be assigned via behavioral Verilog code reg 63 0 regarray2 255 0 7 0 The following is a three dimensional array It can be described as an array of 15 arrays of 256 x 16 wire elements each 8 bits wide which can be assigned via structural Verilog code wire 7 0 array3 0 15 0 255
426. ve XST renames it to a unique name and generates a warning message with the reason for the warning For example MUX5 could be renamed to MUX51 as in the following log sample Low Level Synthesis WARNING Xst 79 Model muxf5 has different characteristics in destination library WARNING Xst 80 Model name has been changed to muxf51 e If the BOX TYPE attribute is not attached to the MUXF5 Then XST processes this block as a user hierarchical block If the name of the user black box is the same as that of a Virtex primitive XST renames it to a unique name and then generates a warning message with the reason for the warning To simplify the instantiation process XST comes with VHDL and Verilog Virtex libraries These libraries contain the complete set of Virtex primitives declarations with a BOX_TYPE constraint attached to each component If you use e VHDL You must declare library unisim with its package vcomponents in your source code library unisim use unisim vcomponents all The source code of this package can be found in the vhdlNsrcNunisims vcomp vhd file of the XST installation e Verilog Starting in release 6 11 the unisim library is already precompiled and XST automatically links it with your design Some primitives like LUT1 enable you to use an INIT during instantiation There are two ways to pass an INIT to the final netlist e Attach an INIT attribute to the instan
427. with carry in The following table shows pin descriptions for an unsigned 8 bit adder with carry in 10 pins Description A 7 0 B 7 0 Add Operands CI Carry In SUM 7 0 Add Result XST User Guide www xilinx com 1 800 255 7778 105 7 XILINX Chapter 2 HDL Coding Techniques VHDL Code Following is the VHDL code for an unsigned 8 bit adder with carry in library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity adder is port A B in std_logic_vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto 0 end adder architecture archi of adder is begin SUM lt A B CI end archi Verilog Code Following is the Verilog code for an unsigned 8 bit adder with carry in module adder A B CI SUM input 7 0 A input 7 0 B input CI output 7 0 SUM assign SUM A B CI endmodule Unsigned 8 bit Adder with Carry Out This section contains VHDL and Verilog descriptions of an unsigned 8 bit adder with carry out If you use VHDL then before writing a operation with carry out please examine the arithmetic package you are going to use For example std_logic_unsigned does not allow you to write in the following form to obtain Carry Out Res 9 bit A 8 bit B 8 bit The reason is that the size of the result for in this package is equal to the size of the longest argument that is 8 bits e One solution fo
428. wnto 0 signal pipe regs pipe reg type begin mult res a in b in process clk begin if clk event and clk 1 then a in lt A b in lt B pipe regs lt mult res amp pipe regs 2 downto 1 MULT lt pipe regs 0 end if end process end beh Verilog Code Use the following templates to implement pipelined multipliers in Verilog The following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers module mult clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a in b in wire 35 0 mult res reg 35 0 pipe 1 pipe 2 pipe 3 assign mult res a in b in always posedge clk XST User Guide www xilinx com 119 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques begin a_in lt A b_in lt B pipe 1 lt mult res pipe 2 lt pipe 1 pipe 3 lt pipe 2 MULT lt pipe 3 end endmodule The following Verilog template shows the multiplication operation placed inside the always block and the pipeline stages are represented as single registers module mult clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a in b in reg 35 0 mult res reg 35 0 pipe 2 pipe 3 always posedge clk begin a_in lt A b_in lt B mult_res lt a_in b_
429. written in VHDL code they should be specified as follows attribute PropertyName of NetName InstName PinName signal label is PropertyValue In a Verilog description they should be written as follows synthesis attribute PropertyName of NetName InstNamelPinName is PropertyValue In Verilog 2001 where descriptions must precede the signal module or instance they refer to it should be written as follows PropertyName PropertyValue XST User Guide www xilinx com 277 1 800 255 7778 7 XILINX Chapter 5 Design Constraints Examples Following are three examples Example 1 When targeting an FPGA device use the RLOC constraint to indicate the placement of a design element on the FPGA die relative to other elements Assuming an SRL16 instance of name srl1 to be placed at location R9C0 S0 you may specify the following in your Verilog code synthesis attribute RLOC of srll R9CO SO You may specify the same attribute in the XCF file with the following lines BEGIN MODEL ENTNAME INST srll RLOC R9C0 SO END The binary equivalent of the following line is written to the output NGC file INST srll RLOC R9CO 50 Example 2 The NOREDUCE constraint available with CPLDs prevents the optimization of the boolean equation generating a given signal Assuming a local signal is assigned the arbitrary function below and a NOREDUCE constraint attached to the signal s s
430. ww xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX Write First Write first synchronization may be described using either of the following two templates Alternative 1 process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA DOA lt DIA else DOA lt RAM conv integer ADDRA end if end if end process Alternative 2 In this example the read statement necessarily comes after the write statement process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA end if DOA lt RAM conv integer ADDRA The read statement must come AFTER the write statement end if end process Although they may look the same except for the signal variable difference it is also important to understand the functional difference between this template and the following well known template which describes a read first synchronization in a single write RAM signal RAM RAMtype process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA lt DIA end if DOA lt RAM conv integer ADDRA end if end process XST User Guide www xilinx com 165 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques Read First A read first synchronization is described as follows where the read statement must come BEFORE the write statement
431. xtio read line std_ulogic_vector ieee std_logic_textio read line std_logic_vector ieee std_logic_textio Limitations 284 XST does not support file write capability Consequently when a file is opened the direction of the file is not checked and assumed to be in The only characters that may appear in the file are 0 and 1 Other characters are not yet supported for example spaces X Z are not supported If any line of the file includes characters other than 0 and 1 XST rejects the design Avoid using identical names for files placed in different directories www xilinx com XST User Guide 1 800 255 7778 Data Types in VHDL XILINX e Avoid using conditional calls to read procedures as shown in the following example This can cause problems during simulation if SEL 1 then read MY_LINE A 3 downto 0 else read MY LINE A 1 downto 0 end if e When using the endfile function if you use the following description style whil not endfil MY FILE loop readline MY FILE MY LINE read MY LINE MY DATA end loop XST rejects the design and generates the following error message Line MY LINE has not enough elements for target MY DATA To fix the problem add exit when endfile MY FILE to the while loop as shown in the following example whil not endfil MY FILE loop readline MY FILE MY LINE exit when endfile MY FILE re
432. y and how XST handles it Family Spartan 3 Virtex IITM Virtex II Pro Virtex II Pro X Inferred Modes write first read first no change Behavior e Macro inference and generation e Attach adequate WRITE MODE WRITE MODE A WRITE MODE B constraints to generated block RAMs in NCF Virtex Virtex E Spartan II M Spartan IIETM write first e Macro inference and generation e Noconstraint to attach on generated block RAMs CPLD none RAM inference completely disabled Read First Mode The following templates show a single port RAM in read first mode VHDL Code library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity raminfr is port clk Zn std logic we in std logic en in std logic addr in std logic vector 4 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end raminfr www xilinx com XST User Guide 1 800 255 7778 RAMs ROMs XILINX architecture syn of raminfr is type ram_type is array 31 downto 0 of std_logic_vector 3 downto 0 signal RAM ram_type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv_integer addr lt di end if do lt RAM conv_integer addr end if end if end process end syn Verilog Code module raminfr clk en we addr di do input clk input we input en
433. you consider and decompose the different parts of the preceding model Following is an example of the Moore Machine with Asynchronous Reset RESET e 4states sl s2 s3 s4 e 5 transitions e linput x1 e loutput outp This model is represented by the following bubble diagram RESET XST User Guide www xilinx com 183 1 800 255 7778 7 XILINX Chapter 2 HDL Coding Techniques FSM with 1 Process Please note in this example output signal outp is a register VHDL Code Following is the VHDL code for an FSM with a single process library IEEE use IEEE std_logic_1164 all entity fsm is port clk reset x1 IN std logic outp OUT std_logic end entity architecture behl of fsm is type state type is s1 s2 s3 s4 signal state state type begin process clk reset begin if reset 1 then state lt sl outp lt 1 elsif clk 1 and clk event then case state is when sl gt if x1 1 then state lt s2 outp lt 1 else state lt s3 outp lt 0 end if when s2 gt state lt s4 outp lt 0 when s3 gt state lt s4 outp lt 0 when s4 gt state lt sl outp lt 1 end case end if end process end behl 184 www xilinx com XST User Guide 1 800 255 7778 State Machine XILINX Verilog Code Following is the Verilog code for an FSM with a single process module fsm clk reset x1 o
434. ype BOX_TYPE constraint instructs XST not to synthesize the behavior of a model and to use some predefined set of characteristics for that model s behavior See BOX_TYPE in the Constraints Guide for details e Bus Delimiter The Bus Delimiter bus_delimiter command line option defines the format used to write the signal vectors in the result netlist The available possibilities are lt gt The default is lt gt 246 www xilinx com XST User Guide 1 800 255 7778 General Constraints XST User Guide XILINX Define this option globally with the bus delimiter command line option of the run command Following is the basic syntax bus delimiter lt gt 1 The default is lt gt In Project Navigator set bus_delimiter globally with the Bus Delimiter option in the Synthesis Options tab of the Process Properties dialog box in the Project Navigator Case The Case command line option case determines if instance and net names are written in the final netlist using all lower or upper case letters or if the case is maintained from the source Note that the case can be maintained for either Verilog or VHDL synthesis flow Define this option globally with the case command line option of the run command Following is the basic syntax case upper lower maintain The default is maintain In Project Navigator specify case globally with the Case option in the Synthesis Options tab of the Process P
435. ys posedge clk begin A_regl lt A A_reg2 lt A_regl B_regl lt B B_reg2 lt B_regl end assign multaddsub A_reg2 B_reg2 C assign RES multaddsub endmodule XST User Guide www xilinx com 1 800 255 7778 123 7 XILINX Chapter 2 HDL Coding Techniques Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs VHDL Code Use the following templates to implement Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs in VHDL library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity m multaddsub2 is generic p width integer 8 port clk add sub in std logic A B C in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end m multaddsub2 architecture beh of m multaddsub2 is signal A_regl A reg2 B regl B reg2 std logic vector p width 1 downto 0 signal mult multaddsub std logic vector p width 2 1 downto 0 begin mult lt A reg2 B reg2 multaddsub lt mult C when add sub 1 lse mult Ce process clk begin if clk event and clk 1 then A_regl lt A A_reg2 lt A_regl B_regl lt B B_reg2 lt B_regl end if end process RES lt multaddsub end beh 124 www xilinx com XST User Guide 1 800 255 7778 Arithmetic Operations XILINX Verilog Code Use the following templates to implement

XST User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents