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CLC-DRCS7-PCASM DRCS7 Evaluation Board User's Guide (Rev. E)

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2. KZ P LET 3b MW H 4 i 3 AZZ zy ML an Ly0 WHO wegl Jn zooo 2Hx l 18 c E s ojjep eju n E DNR D I NR HLGIMGNV s 2 AZZ 8 E i wees 118 SSNIVA LIN3NOdWOO 9217112 d001 ca 100 Nites 001 5 2 Ski se VNS N LOEZXNT oa aG Ww PS Malr 3 Viva aE mH ooz 3 t s in04o M Y 228 SUR caer Say 001 ZA ES e BU ama ot s woer vo en WTO 2o b m LOTO POU x GR VOM8A Ger S S ZHN 000 ZS v1902A z via 386 1 in door y ENE gt Vis 2 19 i T 338 pai sh v 92 T T pt ng vsecrra 19 clo la door v2 92 or o J GE 29 em ILLU Y v dA 99 d SWHO NI 38Y SINIYA YOLSISIY TIV G3LON SS3INN An NI 3NV SINIYA UOLIOYAVO TIV QO6ELNN4 JYY SUOLSISNYUL dNd OGLLNNJ 34V SYOLSISNVYL NdN 310N Figure 43 Circuit for a 52MHz VCXO Locked to a 13MHz Reference 26 2001 National Semiconductor Corporation Rev 2 01 January 25 2001 29v NOD NMO a OILvW3HOS ONIANLOVJNNVA B ALISUZAIO Zen 7110H 808 wo sl ee
3. n P ees T rla dem AMP 536511 1 43 28 GND B RECEPTACLE g 5V 6D 43 38 P 5V 60 Psi 68 PSO 6A J3 4A 2 5V 50 END 2 5V 50 GND PSEN 58 427 J3 4B Di PS2 A 3 3V 40 3 3V ac CONFIGS GND 48 GND 4A CONFIGT J3 5A GND 30 GND 3c GND 38 GND GND 3A AI CLK 20 AZ H H 43 58 D13 5V 2C CLK B 28 5V 2A J3 6A 5V 1D 5V 10 5V 18 43 88 09 5V JA CONFIGS n Aw 536511 3 CONFIGT J3 7A RECEPTACLE X DotoA23 240 EVI Configil 24 EV 43 78 Dm DatoB23 248 NRST 24a DatoA22 230 J3 8A GND 230 DataB22 238 A20 GND 23A E 43 88 og DotoA21 220 Contigo 220 cioB21 228 CONFIGS D OUTB 22A DatoA20 210 CONFIGT GND 21 J3 9A DataB20 218 D OUTA 21A AZ DataA19 200 AI Config9 20C J3 98 o DataBi9 208 SRDY OUT 204 DotoATB 19D 43 10A GND 190 EVI DatoBl8 198 E SES OUT 19A AE 43 108 08 DafoA17 180 ConfigB 18C DotoBl7 188 CONFIGS SCK OUT 18A DofaAl6 170 CONFIGT GND 17C DataB16 178 GND 17A Im DataA15 16D Config 166 DotoBi5 168 SD_INB 16A DataA14 150 GND 15C um 07 DotoBi4 158 SD INA 15A DataAl3 140 J3 12A Config 14C D DatoBl3 148 AIG SRDY IN 14A ME J3 128 06 DotoAi12 130 GND 13C DotoBI2 138 CONFIGS SFS IN 134 DatoAT 120 CONFIG7 J3 13A Configs 12c Data il 128 SCK IN 12A DatoAi0 D GND nc 43 138 D5 DotoBIO 116 GND MA DotoAS 100 J3 14A ein 10C AiG lataB9 108 Ais SPI_DO 104 AU J3 MB D DatgAB 90 GND sc DataBB 98 CONFIGS SPI D SA DatgA7 80 CONFIGT J3 15A Config3 8t
4. 0 05MHz Use the Rev 2 01 January 25 2001 DRCS Serial FFT menu option or run drcs ser fft m to plot the FFT A slight frequency offset may exist due to variations in the frequency of the on board 52MHz crystal oscillator Note that the output sample rate is 52MHz 192 270 8KHz The FFT will show the CLC5902 s filter bandwidth reflected in the shape of the noise floor If the signal source causes excessive phase noise at the base of the fundamental tone in the FFT the measured data will be wrong The routine drcs ser fft excl m Alt DRCS Serial from the analysis menu allows the data within 2kHz to be replaced by the average noise floor value This will allow correct measurements to be made The exclusion bandwidth can be set in the script This script must be used to verify the proper noise processing gain 17 Repeat steps 10 through 13 for input AIN2 replac ing all occurrences of Channel A with Channel B In step 11 set SW2 to 00000110 Next the DRCS Control Panel software and the serial interface will be verified 18 Press reset on the DRCS7 Board 19 On the Channels page of the DRCS Control Panel enter O for Freq within the Channel A box to set the frequency of the channel A NCO to zero Also check Debug Enabled and select Mixer Al from the Probe at pulldown menu within the Common box The screen should appear as in Figure 32 Click on the Send Page button Immediately following this a data transfer ind
5. 6 Go back to the Channels page of the DRCS Control Panel and change Scale Adjust back to O Next se lect 36dB from the Gain pulldown menu in the Channel A box The screen should look like Figure 36 Click on Send Page 7 Press Start on the front panel of the Data Capture Board software window 2001 National Semiconductor Corporation 19 Rev 2 01 January 25 2001 Connector Pinouts Table 5 describes the Futurebus connector J1 pinouts Pin JTAG DSP on the PROX Board Relevant signal names have been i TCK NIC overlaid on the generic pin assignments in Table 5 2 GND GND Unused pins are grayed out These pins are reserved for 3 TDO SCK future use 4 VCC GND Power is supplied through J1 If the Data Capture Board is 5 TMS BFSR connected to J1 power should be connected to J3 the 6 N C GND orange terminal block on the Data Capture Board 7 TRST BDR 8 SCAN_EN GND A B C D 9 TDI GND 1 TRST DataBO GND DataA0 10 GND GND 2 TCK DataB1 Config0 DataAl 11 N C 3 TMS DataB2 GND DataA2 12 GND 4 TDO DataB3 Configl DataA3 13 N C 5 TDI DataB4 GND DataA4 14 GND 6 GND DataB5 Config2 DataA5 15 N C 7 SPI CK DataB6 GND DataA6 16 GND 8 SPI CS DataB7 Config3 DataA7 Table 6 JTAG and DSP header pinouts SPI DO DataB8 GND POUT 0 A Operation with a 13MHz Reference
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7. DataB7 88 SPLCS BA D DatgA8 70 D GND 7C A 43 188 D3 DataB6 78 SPLCK JA ataA5 60 J3 16A Config 6 AU DatoB5 68 D GND 6A AW ep 02 DataA4 50 GND 5C DotoB4 58 CONFIGS TDO 5A Dato 40 TONFIGT J3 17A Gonfial 4 DatoB3 48 TDI 4A DatgA2 30 GND 3C J3 U8 Di DatoB2 38 TMS 3A DotoAi 20 J3 1BA Confiag 26 DataBt 28 TCK 2A 35 J3 188 00 DataA0 ID GND 1C DatoB 18 CONFIGE J3 19A GND TRST 1A CONFIGT 43 198 op CLKA 13 204 J3 20B ROY2 J3 2JA ses J3 218 sck J3 22A BOUT 13 228 AQUT J3 23A ps2 13 238 J3 24A ps 3 248 so E go J3 25A Pso 43 258 ROYI no 26A PSEN NIB J3 26A PSEN N28 o L HE J3 268 P ENS J3 27A eup RDY_IN Noa ja NA J3 27B GND f ol s Gei J3 28A GND ENA 43 288 GND so E S J3 29A 5V 74ACTIS3 Te SEN J3 30A 5V J3 308 5V J3 31A 45V J3 318 45V J3 32A 45V 43 328 45V Figure 42 Connector Adapter CLC ADAPT1 PCASM 2001 National Semiconductor Corporation 25 Rev 2 01 January 25 2001 RE ON ONIMVYO HOS V y 0L0 L W A38 80d TVAJ OXIA WZS S3IU4 uMASAVd 9 Y MN pOL0 L979 QNVOB 1VA3 OXIA ZHN ZS Jajuag ubisag suo 1494 JO INPUODIWAS DUOIJDN ETET 03A08ddV HIT 080238 NOISIA3H uu ii QN9 IONI SINIOd 1S31 ONNOMI
8. The ADC output noise in a 200kHz bandwidth after filter ing by the CLC5902 will then become 65dBFS 24 1dB 79 1dBFS EQ 3 General Description As seen in Figure 4 the DRCS7 Board accepts analog IF inputs on a pair of SMA connectors and processes these OUT PG 10x EE into baseband digital waveforms There are several analog T components that condition the signal prior to sampling PG 10x m DS with a pair of ADCs The most important of these is the 26MHz DVGA the gain control element of an AGC loop The sampled signals are applied to the CLC5902 which per PG 21 1dB a a forms a final mix to baseband digitally filters the wave roy forms and decimates to a lower output sample rate An as shown in Figure 3 automatic gain control AGC processor in the CLC5902 Trans 12 AINI f DVGA EN ADC p AOUT serial ormer BOUT serial A 150MHz 3 SCK n Input SMA RDY P CLK DDC AGC ParOut Connectors a It T j Digital Baseband Ee Outputs z AIN2 nen PYSA gt N ADC S 150MHz J9 Clock gt 2MHz Trans CORR Controller RS 232 Oscillator former Serial UO Figure 4 CLC DRCS7 PCASM Block Diagram 2001 National Semiconductor Corporation 3 Rev 2 01 January 25 2001 directs the DVGAs to extend the dynamic range of the analog signal paths Not
9. Typically the AGC reference level will be set such that the ADC will never see full scale and the lowest gain setting of the DVGA will not be used The total gain of the DRCS7 Board including both the analog and digital parts is best described by the equation GrorAL GxpFMRSDvGASLCSppC gt EQ 12 where the first term has already been introduced and the others will be in subsequent sections of this manual DVGA The DVGA is a 350MHz amplifier that has a digitally controlled voltage gain range from 12 to 30dB in 6dB steps It has a 3 order output intercept point of 24dB at 150MHz and an output noise spectral density of 69nV Hz At 150MHz the data sheet plots place the maximum gain at about 28 5dB or AGAIN Gpyga 021 2 EQ 13 where AGAIN is the 3 bit data word into the DVGA digi tal input of channel A Refer to the CLC5526 data sheet for further details The DVGA in conjunction with the DDC AGC forms an automatic leveling loop that compresses the dynamic range of the input IF signal prior to sampling by the ADC By doing so it extends the dynamic range of the ADC by as much as 42dB The loop dynamics and threshold of the AGC are set by programming the control registers within the CLC5902 It is also possible to inhibit the loop and force specific DVGA gain values ADC The ADC is a 12 bit wideband converter capable of inputs as high as 300MHz at sample rates of 7OMSPS The SNR for an input 3dB below th
10. z 8 z il a x o E gt a a z i Km X 4 a ls D i i 8 a s z I sit iu M e eae so ze Tr EI WAI Ot a A o o o m lt Figure 39 ADC Input AIN2 Rev 2 01 January 25 2001 22 2001 National Semiconductor Corporation y 3 as nos wa en as uv 83143ANOD0 NMOQ smu J9ju99 Ubised suog 3103 JO ONpuO2IWeS jbu noN no 20 vseLv10 za DEET mo ONVOS od 34L NO weng E weg DEER onvos as ES Th me Ra g mere me ine BS DG to E QuVOB od 3Hl if SS NO eine 38V LE SEN 310N 1 wL LO ep oT A y d Sweet ea SES 19480HSL91 aye 3 EI SO za D oa z066012 ZNIVOV CO voy E Cen ac Figure
11. AGC Disabled DVGA fixed at 6dB Figure 25 shows the ADC output with an EDGE mod ulated 150MHz IF input The DVGA is set to a fixed gain of 6dB The same signal skewed in time with 2001 National Semiconductor Corporation 13 the AGC enabled is shown in Figure 26 A symbol DVGA 6dB Step DVGA 6dB Step 1 m L 1 4 15 1 6 17 1 8 1 9 2 Figure 26 EDGE Modulation 150MHz IF ADC Output AGC Enabled by symbol comparison of these two signals at the CLC5902 output baseband I component is shown in Figure 27 This figure demonstrates the high degree of 0 08 L Error 0 02 0 04 L 0 06 I Samples with and without AGC 0 1 1 1 1 1 f L f 1 650 660 670 680 690 700 710 720 730 740 750 0 08 Figure 27 EDGE Modulation Baseband I Component AGC Fixed and AGC Enabled Compared linearity achieved by the CLC5902 CLC5526 AGC circuitry 15 How can the various evaluation boards be intercon nected Refer to the Evaluation Board Interoperability User s Guide at www national com under the Wireless Infra structure Product Site for this information 16 When the CLC5902 is in 16 bit output mode all of the serial output bits are zero Is something broken The theoretical noisefloor for a 16 bit digital word is about 98dBFS The output noisefloor of the DRCS7 Board is about 121dBFS for the default setup A sig nal must be applied to bring the o
12. Alt DRCS Serial or run drcs ser fft excl m to observe the change in both SFDR and the Integrated Noisefloor from Figure 16 to Figure 18 Editing the Matlab script dres ser fft excl m allows the exclu sion region to be set to the desired value It is 2kHz by default 32768 Point FFT Analysis 68dBc SFDR The signal generator phase noise limits the system performance Use the alternate FFT routine to exclude the excess phase noise for accurate 4 measurements ly um 4 95 4 96 4 97 4 98 4 99 5 5 01 5 02 5 03 5 04 5 0 FREQUENCY x 10 Figure 17 IF Input 150MHz at OdBm Close up Figure 19 shows an example of an input signal with extremely poor phase noise performance 4 Will the DRCS work with such a poor clock signal Yes this problem will not prevent the DRCS from easily recovering an EDGE signal For full rate EDGE the 23dB C I requirement is still met with margin At lower signal levels jitter from phase noise does not significantly affect the ADC s performance Take a look at the same signal at 80dBm Figure 20 instead of OdBm Figure 19 What happens changed when the filter coefficients are 2001 National Semiconductor Corporation 32768 Point FFT Analysis 20 T Alternate FFT Routine Results Se Pinput 19 3dBFS 7 T SFDR 845dBc Integrated Noisefloor ee 80 84 5dBc SFDR 90 0dBFS 7 E O 100 LU 2 E 120 z O Es Z 140 1
13. Data Capture Board is not available an alternate method of saving the data to a file must be used The default output format for the DRCS7 Evaluation Board is shown in Figure 5 If the data is stored in a two s comple ment integer format the supplied Matlab scripts may still be used to process it The sequence below requires an unmodulated sine wave source i e HP8644B or R amp S SME 03 to generate the input signal The DRCS Control Panel software will not be used until the first tests are successfully completed 1 If you have not already done so install the DRCS Control Panel and Data Capture Board software 2 Connect 5V to VCC and ground to GND of con nector J3 the orange terminal block on the Data Capture Board When the boards are connected to gether in the next step these connections will pow er both boards Note that VEE is not required because neither board needs a negative power sup ply 3 Connect JI of the DRCS7 Board to JI of the Data Capture Board with the connector adapter CLC ADAPT1 PCASM in between Be sure to remove the spare mating DIN connector if one is attached 2001 National Semiconductor Corporation 4 Connect a serial cable from the PC to J9 on the Data Capture Board 5 If two serial ports are available on the PC connect the other to J9 of the DRCS7 Board If not the sin gle port must be shared 6 Make sure that all DIP switches on both boards are set to off 7 Turn on the p
14. Debug within the Mode box and 18 Bits from the Bits box see Figure 31 Click on OK 5 Press Start on the front panel of the Data Capture Board software window As before the values in DATA DAT represent 24 bit 2 s complement integers and only the upper 18 bits are non zero Use the MATLAB script plot twos m Plot Twos from the analysis menu to convert the data to signed frac tional values and plot them Zoom in on the first 300 points to see something similar to Figure 35 This distor tion is caused by overflow in the CIC filter due to SCALE being set too large This overflow cannot be sensed and the only way to avoid it is by making sure that SCALE is 2001 National Semiconductor Corporation CV Diversity Receiver Chipset Control Panel ll E Diversity Receiver Chipset Control Panel ls File Help File Help Channels AGC Output Filter Date Registers Channels AGC Output Filter Date Registers Channel A Common gt gt gt rI Channel A Common gt 4 FCK 2 MHz FCK 2 MHz R 150 005 EN 5 Lc CIC Decimation 48 pos es CIC Decimation Fe Phase lo Deg Scale Calculated 22 Phase Eo Deg Scale Calculated 22 Scale Adjust JE Bits Scale Adjust fo Bits Gain s dB Y Dither Enabled F2 Decimation 2 sl Gain 36 x 7 Dither Enabled F2 Decimation 2 z Output Sample Rate 2 708E 001 MHz Output Sample Rate 2 708E 001 MH
15. an external pulse whose width defines the AGC active period Alternatively the gate can be an edge which starts a counter within the DDC AGC The AGC active period is then the time it takes for the counter to reach its terminal value By using the configuration registers it is possible to write the initial gain condition of the loop into the integra tor and also to read the final gain value from this integra tor Consult the CLC5902 data sheet for further details 2001 National Semiconductor Corporation 35 Rev 2 01 January 25 2001 DRCS7 Evaluation Board User s Guide CLC DRCS7 PCASM Customer Design Applications Support National Semiconductor is committed to design excellence For sales literature and technical support call the National Semiconductor Customer Response Group at 1 800 272 9959 or fax 1 800 737 7018 Life Support Policy National s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life
16. ano So UB peka o y res MER pe res oer oi wer L en ver a nA v 6 2 T 042 i ode es 2 aen 2 an ASEH AlddNS NO YOLWINIIY 30012NI Rev 2 01 January 25 2001 27 Figure 44 DRCS Reference Design 2001 National Semiconductor Corporation PC Board Layout Silk screen parts placement drawings are shown below The complete board layout package can also be provided Primary areas of concern are the analog inputs to the ADC and the ADC digital outputs Care has been exercised to prevent ground loops and noise coupling on the circuit board at the inputs Noise coupling is reduced by aligning the split between analog and digital planes across all layers The ADC outputs have been kept as short as possible to minimize capacitive loading The internal ground plane has been removed under these traces to reduce the para NATIONAL SEMICONDUCTOR LAYER1 SILK un 3 4 3 Be 3 e NATIONAL SEMICONDUCTOR amp A FORT COLLINS DESIGN CENTER 2 R12 C20 R5 P x a e EE MI L EG ee zo ee e z 3 GND3 GND4 e e D sitic capacitance Higher capacitance values will load the ADC output drivers causing additional noise on the inter nal analog signals This will degrade the ADC perfor mance Analog and digital grounds have been star common point connected t
17. cannot read the CLC5902 register values Except for the Registers page each page has a Send Page or Send button When pressed the register values associ ated with that page are down loaded to the CLC5902 In addition a Send All Data command is available under the File menu Note The Send buttons only send the data for their own pages The configuration data entered into the various pages can be saved to a dcp configuration file so they can be reloaded later The file is ASCII and has one line for each byte that is written to the CLC5902 The first column is the address and the second is the data Both are in hex for mat This hex data can be copied and used in the final sys tem to simplify the development process The Save Rev 2 01 January 25 2001 14 Configuration and Load Configuration commands can be found under the File menu When you start the DRCS Control Panel it will load the last used dcp file within the data subdirectory c nsc data If you have not yet created one it will look for default dcp If default dcp is not found it will use a set of hard coded defaults for everything except FIR Filters F1 and F2 For the filters the program will search for default fI and default f2 If they are not found zeros will be loaded for the coefficients The data entry fields are designed to allow values to be entered using pulldown menus or edit boxes in familiar engineering terms rather than the integer v
18. clock must be provided i e HP8644B or R amp S SME 03 The CLC5957 converts the differential input clock to a TTL clock suitable for driving the CLC5902 CK input At high input levels the CLC5957 ADC s SNR is limited by clock jitter Ina DRCS based receiver the effects of clock jitter can be reduced by operating the AGC ata lower threshold As the input signal level to the ADC decreases the degradation of the ADC s SNR will also decrease SNR degradation due to clock jitter only happens when the input signal is near full scale This large input signal will typically mask any SNR degradation that may occur This would not be the case if more than one carrier was digi tized IF Signal Inputs The AINI and AIN2 SMA connectors accept IF signals up to 20dBm and below 100dBm Always start with a sig nal at or below OdBm reset the DRCS7 Board then increase the signal if desired This allows the AGC loop to control the DVGA properly as it will in a receiver When measuring very small signals consider using an external attenuator in addition to the level control in the signal gen erator Some signal generators do not perform well at very low output levels For optimal performance a low jitter low phase noise signal source must be used i e HP8644B or R amp S SME 03 CLC5902 Serial Outputs The default setup of the DRCS7 Board is PACKED 1 MUX_MODE 1 and FORMAT c These settings provide a 24 bit serial output word a fr
19. filter and a clean power detec tion will not occur This problem can be avoided by choos 2001 National Semiconductor Corporation ing the IF and sample rates such that the alias frequency magnitude is greater than Fcx 16 The user interface software makes programming of the AGC very easy The user need only specify the loop time constant reference and deadband The lookup table val ues and shifter values can then be computed As shown in Figure 55 deadband in excess of 6dB shows up as hyster esis Hysteresis will eliminate excessive DVGA gain changes caused by the input signal level dwelling at a tran sition point 1 1 Deadband Reference DVGA Output Power 4 6dB K K la Hysteresis Deadband 6dB DVGA Input Power Figure 55 Relationship between deadband and hysteresis The AGC has several operating modes The simplest is the free run mode where the loop is closed continuously and the DVGA gain setting is constantly updated in response to the signal level applied to the board This mode is easi est to use and is suitable for most applications The default configuration of the DRCS7 Board and user software is for this mode The other mode is a gated mode and is useful for example in TDMA systems when one wishes the AGC to be active only during the power ramp up In this mode the loop is active when the gate signal is applied and then opens when the gate is removed The gate signal can be
20. is passed by the filter providing a low jitter test signal Tuning to 150 05MHz places the 150MHz signal at 50kHz in the DRCS output Adding a variable attenuator allows a wide range of measurements to be made without an expensive synthesized signal generator Can the ADC output be observed Yes The CLC5902 debug output allows the complex mixer outputs to be observed When the NCO is set to 0Hz the ADC output will be present at the I output The Q output will be zero unless a phase offset is introduced What if a scope is to be used to look at the ADC digi tal outputs 12 MAGNITUDE dBFS 32768 Point FFT Analysis Wrong Capture Settings Pinput 4 7dBFS SFDR 8 7dBe Integrated Noisefloo 3 0dBF 10 12 6 8 FREQUENCY x46 Figure 22 IF Input 150MHz at OdBm Bad Alignment Make a special scope probe by soldering a 1K ohm resistor to the center of a BNC connector Add a short ground clip to the outer conductor Now plug the BNC into a 50 ohm cable to the scope and set the scope to 50 ohm input mode This method will provide accu rate results since there is very little parasitic capaci tance How can the AGC operation be verified To verify the AGC operation both the ADC output and the CLC5902 output can be compared The ADC output will reveal the 6dB steps caused by the DVGA The CLC5902 output will be linear since the 6dB steps are precisely compensated in both amplitude and tim
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22. square wave ENCODE clock normally should not use the DAV signals When the two DAV sig nals are combined with an AND gate the CLC5902 input clock CK duty cycle can be affected If the duty cycle is further skewed by changes in the ENCODE clock duty cycle the data input setup tsy and hold typ times may be violated Bypassing the CLC5957 clock buffers can eliminate setup and hold dependence on clock duty cycle 2001 National Semiconductor Corporation 7 Combining the DAV signals with an AND gate is appro priate when a clean sine wave clock is available The sine wave will have a nearly perfect 50 duty cycle which will be converted to a square wave by the CLC5957 Both implementations will provide better SNR perfor mance if the CLC5957 ENCODE inputs are driven differ entially Driving ENCODE with a single ended clock can cause common mode noise to appear as clock jitter possi bly degrading the SNR ANDing the DAV Signals When the CLC5957 DAV signals are to be used they should be ANDed together to drive the CLC5902 CK input This AND gate is required to provide proper opera tion in the event that one CLC5957 has less propagation delay than the other Figure 10 shows detailed timing information for the ADC to CLC5902 clock interface with the AND gate This is the approach used on the DRCS7 Evaluation Board as shown by the schematics in Figure 38 Figure 39 and Figure 40 Table 1 summarizes the parameters from the CLC5
23. support device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 2501 Miramar Tower Tel 81 043 299 2309 Arlington TX 76017 E mail europe support nsc com 1 Kimberley Road Fax 81 043 299 2408 Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Hong Kong Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Tel 852 2737 1800 Francais Tel 49 0 180 532 93 58 Fax 852 2736 9960 Italiano Tel 49 0 180 534 16 80 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications National Semiconductor and 9 are trademarks of National Semiconductor Corporation All other trademarks are the property of their respective com panies 2001 National Semiconductor Corporation 36 Rev 2 01 January 25 2001 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice
24. the waveform is sinusoidal Verify that the amplitude is correct by plotting an FFT Either select DRCS Debug from the analysis_menu m script or run drcs par fft m The Pinput shown in the upper right should report either 10dBFS or 6dBFS and there should be a tone at 150MHz 3 52MHz 6MHz The next measurement will observe the output of the DDC 14 Set all the DRCS7 Board SW2 DIP switches to OFF and press reset 15 Choose Capture within the Mode box of the Config ure Capture screen of the Data Capture Board soft ware Then choose 24 Bits within the Bits box and Capture ist Bit within the 1st Bit box Finally choose Channel A from the Channel box and press OK The screen should appear as in Figure 15 see page 9 16 Click Start on the front panel of the Data Capture Board software window The values in the file again represent 24 bit 2 s comple ment integers except now all 24 bits are non zero Use the MATLAB script plot_twos m Plot Twos from the analy sis menu to convert the data to signed fractional values and plot them Note Regardless of the true width of the word being captured the Data Capture Board will always write 24 bit 2 s complement numbers to DATA DAT The only exception to this is when probing AGC CIC A B in which case each number represents two appended 9 bit numbers Verify with an FFT that the output is 28dBFS at fre quency 150 00MHz 150 05MHz
25. 10 SPI DI DataB9 Config4 POUT 1 K l The advantages of operating the DRCS at 52MHz make it o EN D END Route worthwhile to do so even in a 13MHz system This can be 12 SCK_OUT DataB11 Config5 POUTI3 done by either of these two methods I3 SFS_OUT DataB12 GND POUTI4 1 Replace the system oscillator with a 52MHz unit 14 RDY OUT DataB13 Config6 POUT 5 and divide down to 13MHz This is probably the 15 AOUT DataB14 GND POUTI6I lowest cost alternative since only one VCXO is re S quired Keep in mind that the phase noise of the T ko ek pesar Conti A 52MHz VCXO will also be divided down SNE Ge END a 2 Phase lock a 52MHz VCXO to the 13MHz clock 18 SCK IN DataB17 Config8 POUT 9 This approach reguires more additional components 19 SFS IN DataB18 GND POUT 10 but has the least impact on existing circuitry A cir 20 SRDY IN DataB19 Config POUTI cuit that can be used for this purpose is shown in Figure 43 21 SD INA DataB20 GND POUT 12 22 SD_INB DataB21 Config10 POUT 13 Schematics 23 GND DataB22 GND POUT 14 Figure 38 Figure 39 Figure 40 and Figure 41 are the za NE pu Configll POUTIIS CLC DRCS7 PCASM schematics Figure 42 is the Con nector Adapter CLC ADAPT 1 PCASM schematic 25 5V 5V 5V 5V E y m E sek Reference Design 27 GND GND GND GND The schematic for a complete reference design is provided in Figure 44 This circuit is the same as the DRCS7 Evalu 28 GND GND 3 3V 3 3V e ation Board without the COP8
26. 40 CLC5902 Dual Digital Tuner AGC Rev 2 01 January 25 2001 23 2001 National Semiconductor Corporation uv MOSS320Ud dOD Gsjuso ubis i eq Sue 1103 po I H o BONO LUND ag SONI SINIOd 1531 gunge OSKODNIKL QSHODATHL OSPODA1L Si v le E e DEEM en SEI ISPODATHL ISVODATHL k H H y T T a 6n i 6n zer o ier sia cor axy BO103NNOO O Nid 6 9 6r usq 9 HEN 319Nv 1H9lN V SI er per s19 zl 8L9 aunt UST ys SS g S BOR gos x kadi l tcu CEDE en Stu Lase dosel T 999 199 T 92 ti Fala dia SE A EME soy 57 amp VE EXE ENE ENS REN SW 8 3 3 3 2 LA N03 S370H y SY z VA Z S V E gt bP A EE NMOO Q10H te f v v Y ae gods 4095 ws P qm A s Hi is sa Wun Jak v ZE m ICH VNS LAdNI 419 3HL OL Q3193NNOO SI 34207109 IVNAJIXI ON dl 4 YO ZA AINO 3SN ALON 2001 National Semiconductor Corporation 24 Rev 2 01 January 25 2001 Figure 41 COP8 Microprocessor J3 1A 5v 5V 50 13 18
27. 60 180 200r i i i i i i J 2 4 6 8 10 12 FREQUENCY x 10 32768 Point FFT Analysis Low Level Results Pinput 98 9dBFS SEDR 34 8dBc J Integrated Noisefloor 121 0dBFS 140 100F 120r A o o MAGNITUDE dBFS 180 200 6 8 10 12 FREQUENCY x 10 Figure 18 IF Input 150MHz at OdBm Alternate FFT 32768 Point FFT Analysis 20F Very Bad Phase Noise Pinput 18 6dBFS SFDR 36 8dBc Integrated Noisefloor 80 H 46 5dBFS 4 ur 100 L 120 MAGNITUDE dBFS 140 160r 180r 6 3 i FREQUENCY x 10 Figure 19 IF Input 150MHz at OdBm The noisefloor in the FFT plots reflects the digital fil ter response Changing the filter coefficients will change the shape of the noisefloor Verify this by cap turing a new data record as follows 1 Connect the DRCS7 Board and Capture Board as described in the Quick Start section on page 9 2 Turn on the power and apply 150MHz at 80dBm to the AIN1 connector 3 Start Matlab and the Capture software 4 Configure the Capture software as in Figure 15 5 On the DRCS7 Board turn SW2 4 amp SW2 8 ON 6 Press the DRCS7 RESET button LEDs should al ternate 2001 National Semiconductor Corporation 11 Figure 20 IF Input 150MHz at 80dBm Alternate FFT 7 Capture new data and plot an FFT 32768 Point FFT Analysis Low Level Results GSM F
28. 7 Dither Enabled F2 Decimation 2 x Output Sample Rate 2 708E 001 MHz Test Register Value 4096 Channel B 2 Source T AGC Exponent Inhibit We Gig An Bin Phase 0 Deg C Test Register Pro Ss 1198 Dither Enabled Figure 33 DRCS Channel Configuration Serial Output Repeat steps 15 and 16 and review the results as before Changing the frequency with the DRCS Control Panel capturing more data and performing an FFT should cause the output tone on the FFT to move the same amount This completes the verification of the board operation DDC Large Signal Nonlinearity Exercise This exercise is intended to illustrate the two types of large signal nonlinearity that can be encountered when the CLC5902 is incorrectly configured Both can be observed at the input of filter F1 The same equipment is used as in the In Depth Operation section on page 16 1 Connect a 10dBm sinewave at 150 000MHz to the DRCS7 Board AIN1 input 2 Load default dcp by choosing Load Configuration from the File menu of the DRCS Control Panel 3 On the Channels page enter 150 005 5kHz offset for Freq within the Channel A box and enter 6 for Scale Adjust within the Common box Also check Debug Enabled select F1 In Al from the Probe at pulldown menu and set Channel Gains to 0 The screen should look like Figure 34 Click on the Send Page button 4 On the Configure Capture screen of the Data Cap ture Board software choose Capture
29. 957 and CLC5902 datasheets The objective of the timing diagram in Figure 10 is to determine the allowable range for the AND gate delay tar This parameter may be calculated as shown in Equa tion 8 feu ies Star Stpavi t ai gp pavz PU Parameter Symbol Timing Pulse width high CLC5957 ENCODE tp 9 615ns Pulse width low CLC5957 ENCODE tM 9 615ns Rising ENCODE to rising DAV CLC5957 tpavi 8 5ns Rising ENCODE to rising DAV CLC5957 tpav2 10 9ns DATA setup to rising DAV CLC5957 tsi tsa 7 215ns DATA hold after rising DAV CLC5957 tg tm 8 015ns Falling ENCODE to DATA invalid CLC5957 tony 7 0ns Falling ENCODE to DATA valid CLC5957 tpav 13 0ns A BIN setup to rising CK CLC5902 tsu 7 0ns A BIN hold after rising CK CLC5902 tgp 3 0ns 0 215ns to ci b AND gate rising edge delay tar 2 615ns AND gate falling edge delay tap tar Table 1 ADC to CLC5902 Timing Summary a Clock is 52MHz values are min max from the CLC5957 and CLC5902 datasheets Datasheet numbers take prece dence These numbers are only presented for convenience b Refer to Equation 8 C tapis not critical since the data is captured on the rising edge of CK The results in Table indicate that an AND gate with delays between 0 215ns and 2 615ns should be used The IDT74ALVC1GO8DY has a propagation delay spec of 1 2ns to 2 9ns with a 5OpF load Since the load in this case will be less than 10pF this part will
30. CLC DRCS7 PCASM CLC DRCS7 PCASM DRCS7 Evaluation Board User s Guide IA TEXAS INSTRUMENTS Literature Number SNOS945E National Semiconductor CLC DRCS7 PCASM January 2001 DRCS7 Evaluation Board User s Guide Overview The Diversity Receiver Chipset DRCS is an IF sampling receiver optimized for GSM EDGE systems It provides the extreme dynamic range required for EDGE through a novel AGC based architecture The chipset consists of two CLC5526 Digital Variable Gain Amplifiers DVGAs two CLC5957 Analog to Digital Con verters ADCs and one CLC5902 Dual Digital Tuner AGC The DRCS7 Evaluation Board CLC DRCS7 PCASM supports complete evaluation of the Diversity Receiver Chipset DRCS Configuration of the Digital Tuner AGC is controlled by a COP8 micro controller Several useful configurations can be directly loaded by the COP8 or specialized configurations can be created and loaded with the provided DRCS Control Panel software drc sCp exe A Data Capture Board CLC CAPT PCASM and accompanying software capture exe are available for use with the DRCS7 Evalu ation Board The Capture Board enables the user to capture and transfer data from the DRCS7 Evaluation Board into a file on a PC Matlab script files are provided to assist in data analysis Figure 1 shows a funetional block diagram of the DRCS The DVGA controls the ADC s input level to expand the dynamic range The ADC sub samples the input and feeds th
31. CLC5902 datasheet 2001 National Semiconductor Corporation 5 To facilitate testing of the parallel outputs SW1 can be used to force the state of POUT SEL and POUT EN Note All DRCS7 Board SW1 positions must be OFF if the Data Capture Board is used for parallel data capture CLC5902 Debug Output In some cases it may be desirable to look at signals inter nal to the CLC5902 The CLC5902 debug port is tied to an internal 20 bit bus which can tap into the internal nodes shown in Figure 7 When in debug mode the DSP serial port pins are reconfigured and the serial port is no longer functional SCK is used to clock out the debug data at the proper rate Additional information on the debug port is provided in the CLC5902 datasheet The debug port can be used to observe the ADC outputs prior to processing by the CLC5902 This can be done by selecting the mixer output tap for the I component and set ting the NCO frequency to zero This setup is included in the default COPS options COPS RS 232 Serial Interface The CLC5902 can be set to several default configurations by the COPS micro controller To support more flexibility in evaluation the CLC5902 may also be completely recon figured via an RS 232 serial port The DRCS Control Panel software running on a PC sends commands to the COPS serial port The COPS interprets these commands and programs the CLC5902 registers as required DRCS7 Block Interfaces DVGA to ADC I
32. Data Capture software from the included CDROM this also installs the DRCS Control Panel software 2 Connect the DRCS7 Evaluation Board to the Data Capture Board with the Connector Adapter in be tween Note Remove the spare mating connector shipped with the connector adapter if attached 3 Connect 5V and ground to J3 the orange terminal block on the Capture Board 4 Verify that a 52MHz oscillator module is installed at Y2 next to the CLK SMA connector 5 Set all the DIP switches OFF on both the DRCS7 Board and the Capture Board 6 On the Capture Board place the WCLK jumper in the PIN120 position and the VCCD jumper in the 5 position 7 Connect a OdBm 150MHz sinewave input signal to the AIN1 SMA connector 8 Connect the Capture Board J9 serial port to the PC serial port with the supplied cable 9 Turn on the 5V supply 10 Start the Capture software The Capture Software Panel shown in Figure 13 will be displayed Start Figure 13 Capture Software Panel 11 Click the right mouse button over the Capture soft ware panel do not click over the Start or but tons select Configure I O shown in Figure 14 then select your COM port 2001 National Semiconductor Corporation 9 Configure I O Selected Serial Port GER Com Port gi C Com Port 3 C ComPort 2 Com Port 4 T Serial Port n Timeout in mill
33. R Mux K Q Shifter amp Scale Fl Fl Q9 Figure 7 CLC5902 Debug Port Access Taps SCK tsesv SFS RDY tAND DELAY Le lpsP SETUP SFS amp RDY tsrsv LAND DELAY tpsp SETUP S 19 2ns CK 52MHz SCK CK 2 SCK_POL RDY_POL SFS_POL 0 tspsv 7ns max from CLC5902 datasheet Figure 6 CLC5902 Serial Port Timing Note The trace from pin 2 to pin 4 of U12 must be cut when U12 is used The default serial output configuration is compatible with the TI TMS320C54X serial input To interface to the C54X set the DSP serial port in continuous mode FSM bit set to 0 with frame ignore enabled FIG bit set to 1 In this mode the 24 bit words may be read as 3 groups of 8 bits The overall input stream of four 24 bit words is read as twelve 8 bit words for later reassembly by the DSP Additional serial port modes are discussed in the CLC5902 datasheet CLC5902 Parallel Output The CLC5902 parallel output port is available on JI It is a 16 bit port which can be mapped into the address space of a DSP Each output component AI AQ BI amp BQ is allocated 2 registers of 16 bits In 8 bit or 16 bit mode only a single register for each component needs to be read To access the data place the proper address on the three POUT_SEL lines and enable the outputs with POUT_EN The RDY signal can be used as an interrupt to indicate new data is ready Complete details are provided in the
34. ables and their sizes Clear will clear all the variables To create a new plot type figure 1 then plot the data to the figure with plot data Type zoom on grid on to enable zoom and draw a grid Click and hold the left mouse button to draw a zoom box Double click the right mouse button to zoom full Matlab includes a comprehensive set of help files Type help to get a list of available help files The tone in the FFT is not exactly 50kHz Why Since the 52MHz crystal oscillator is not locked to the signal generator the tone in the FFT may not be exactly 50kHz A second signal generator locked to 10 MAGNITUDE dBFS 110 the first can be used to clock the DRCS7 Board and remove the frequency error Set the clock signal gen erator to 52MHz at 16dBm Be sure to remove the crystal oscillator module from its socket The measured results are much worse than expected Why Observing the FFT plots in Figure 16 and Figure 17 close up the tone at 50kHz may show some spread ing near the noise floor This is typically caused by a signal generator with poor phase noise performance The phase noise will be translated into jitter which impacts the ADC sampling performance These phase noise skirts can be so large that the measured data on the FFT plot is incorrect An alternate FFT routine is provided to remove the effects of the phase noise by excluding the region near the fundamental tone Click
35. alues that are required by the CLC5902 The engineering values are con verted to the appropriate integer values and appear on the Registers page For example when 150 05 is entered into Freq Channel A the Registers page displays the value 491443374 for FREQ A Figure 28 When the mouse is held over a data entry field a balloon is displayed which describes the function If a value is entered that is outside the valid range a warning is displayed For the most part the data entry fields are intuitive given an understanding of the CLC5902 data sheet A few exceptions are noted below Channels Page Freq is the frequency of the NCO You can either enter the IF frequency at the ADC input or the aliased frequency at the ADC output To down convert without a phase inver sion use the plot in Figure 2 The signals with dashed lines should be entered with a negative sign For example an IF frequency of 150 05MHz requires an entry of 150 05 for no phase inversion An alternative is to recog nize that 150 05MHz aliases to 5 95MHz when FCK is 52MHz and for no phase inversion enter 45 95 FCK refers to the sample rate of the DRCS7 Board which has a factory default of 52MHz Scale refers to the bit shift prior to the CIC filter Figure 50 Scale Calculated is calculated by the program and is the value required of Scale to maintain the gain of the DDC up to and including the CIC filter to unity or just below It changes when CIC Decimati
36. ame sync output pulse once for each I Q pair and the outputs for channel A and B are muxed onto the single output pin AOUT as shown in Fig ure 5 Note This is the format expected by the Data Capture Board The serial outputs and control signals are available at the Futurebus connector J1 This connector mates with the Data Capture Board through an adapter These signals are also accessible on the DSP header for simple connection to a DSP In some cases it may be desirable to remove the second SFS pulse so that channel A and B can be identified An AND gate can be placed at U12 which allows the RDY signal to mask the second SFS pulse Figure 6 provides detailed timing information for this option ma 96 clocks gt RDY SCK SFS SEH Xo X 23K Xa XOX a KOK 23K Xa XOX 23K KI X9 X nisb lsb mab lsb msb lsb msb Isb Ichan A Qchan A Ichan B Q chan B Figure 5 DRCS7 Default Serial Port Format Rev 2 01 January 25 2001 4 2001 National Semiconductor Corporation Each channel is identical For each channel the I amp Q NCO paths are identical The debug tap is always aligned into the MSB of the NCO Cos A COS SIN NCO Sin A 20 bit debug port output Mixer Al Fl In AI F1 Out AI Input K I AGC CIC GAIN FIR FI
37. amp 12 which decimate by 96 541 66ksps b 2x Oversampled Outputs 541 66ksps c Mixer AI Debug d Mixer BI Debug e EXP_INH 1 AIN drives both channels f 2x Oversampled Outputs 541 66ksps Rev 2 01 January 25 2001 The complete COP8 programming tables are available in the file c nsc data dres7config_013100 txt after the DRCS Control Panel software is installed Function Sw2 0 1 FIR Coefficients 8 STD GSM AGC Dynamics 7 12dBFS 15dBFS Threshold Deadband 12dB 9dB AGC Mode 6 Run Stop NCO Dither 5 On Off Table 3 X Additional SW2 settings a SW2 4 and SW2 8 should always be in the same state b Both settings have a 1 5usec time constant Note The default LC noise filter on the DRCS7 Board has an 18MHz bandwidth centered at 150MHz Some of the SW2 tuning options will require modification of the LC filter to prevent attenuation of the desired signal Table 4 gives the configuration register values for each of the AGC modes associated with SW2 position 6 as men tioned in Table 3 SW2 Switch Position 6 Settings Register Name 0 Run 1 Stop AGC_HOLD_IC 0 0 AGC_RESET_EN 0 0 AGC_FORCE 1 0 EXP_INH 0 0 AGC_COUNT 2815 2815 AGC_IC_A B 32 32 Table4 Register values corresponding to SW2 switch position 6 Any of these default configurations can be modified by using the DRCS Control Panel software See the DRCS Control Panel Software
38. and its associated compo 29 POUT_SEL 2 POUT_EN ZON a nents In this example the LC filter is tuned to 71MHz and 30 POUT_SEL 0 POUT_SEL 1 5V 5V must be re tuned to the appropriate value Table 5 FutureBus Connector J1 pinout Table 6 describes 10 pin JTAG header and 16 pin DSP header pinouts The schematic in Figure 41 provides the pinout for J9 a female DB 9 used to connect the standard RS 232 serial cable from the PC Rev 2 01 January 25 2001 20 2001 National Semiconductor Corporation o E 2 5 ANS e its E e 3 E Bi E n uz D Ce 3 Dor s DO 3 E a 2 o lt gt IAE zie co o 9 PO ES 3 ze E NN FEN A N e ES ul ES Z 5 D z 3 e 0 bel 2 E r i to Or 0 Q o a o a lt Figure 38 ADC Input AINI 2001 National Semiconductor Corporation 21 Rev 2 01 January 25 2001 N d tu
39. ces any existing 2001 National Semiconductor Corporation 15 data Only the data for a single page is updated unless a Send All Data command is issued m Is there any non volatile storage on the DRCS7 Board Only in the COP8 EPROM No user accessible non volatile storage is available Default Configuration and SW2 Settings The CLC DRCS7 PCASM is configured for 52MHz oper ation A 52MHz crystal oscillator module is included so that only one signal generator is reguired for evaluation Table 2 describes the tuning frequencies and filter sets selected by SW2 with a 52MHz clock Additional SW2 settings positions 8 7 6 amp 5 are shown in Table 3 The Table 3 parameters operate independently from the Table 2 parameters except for SW2 position 8 Config sw2 Channel A B CIC F1 F2 Filter Number 87654321 Tuning Decimation Set 0 0XXX0000 Ro 48 4 STD 1 0XXX0001 Geen 48 4 STD 2 0XXX0010 GE 48 4 STD 3 0XXX0011 ES 48 4 STD 4b 0XXX0100 Se 24 4 STD 5 0XXX0101 2 N A N A 6d OXXX0110 GER N A N A Je 1XXX0111 KEE 24 8 GSM 8 1XXX1000 ES 24 8 GSM 9 1XXX1001 RE 24 8 GSM 10 1XXX1010 Ge 24 8 GSM 11 1XXX1011 op pus 24 8 GSM 12 1XXX1100 ES 12 8 GSM Table 2 SW2 Default Configurations a This column shows the CIC decimation and the F1 decima tion F2 decimation All cases provide a total decimation of 192 for GSM EDGE systems 270 833ksps output ex cept Config 4
40. d at the CLC5902 output by sweeping both the input frequency and the CLC5902 tuning so that they track The test signal must be input after the IF SAW to use this method The desired signal at 150MHz appears as a 6MHz signal at the ADC output The other sampling images at 162MHz 202MHz 214MHz will also appear as 6MHz signals at the ADC output The LC noise filter prevents extra noise from these sampling images from appearing at the ADC output 3X Sampling 4X Sampling Frequency Frequency TE Freguency TN Sampling mage O NL 202 208 214 tu 136 16 Frequency MHz Figure 8 Rev 2 01 January 25 2001 6 Illustration of the need for noise filter attenuation at the sampling images 2001 National Semiconductor Corporation ADC to CLC5902 Interface The CLC5957 ADC outputs are current limited DATA 2 5mA DAV 5mA to prevent crosstalk back to the analog input For this reason it is important to mini mize the parasitic capacitance on the data outputs and the DAV signal Excessive capacitance will degrade the ADC s SNR performance and may cause errors in the out put data A target for capacitive loading should be 5 7pF To meet this target all power and ground planes should be removed below the ADC output pins traces and CLC5902 input pins The area where the power and ground planes are removed should be the point where ana log and digital planes are split The included PCB layout on page 28 sh
41. e The operation of the AGC will be transparent at the DRCS output since the CLC5902 includes circuitry to digitally compensate for the DVGA gain steps The DRCS7 Board is factory configured for an IF of 150MHz a sampling frequency Fox of 52MSPS and an overall decimation of 192 This yields an output sample rate of 270 8KSPS which is suitable for GSM EDGE sys tems The CLC5902 features a high degree of programma bility Key parameters such as mixer frequency decimation ratio filter shape AGC operation etc can be configured by the user DRCS7 Evaluation Board I Os Power The DRCS7 Board requires 5V and ground which are supplied through J1 The Connector Adapter CLC ADAPT1 PCASM mates with J1 and includes a terminal block for power connections The Data Capture Board also includes a terminal block for power connections which feed through the Connector Adapter A 5V 1A power supply is sufficient for the DRCS7 Board with the Data Capture Board The terminal block may include a 5V position VEE but it is not required for the DRCS Clock Input The DRCS7 Board includes a 52MHz crystal oscillator module so that an external clock source is not required If a different sample rate is desired a 16dBm sinewave or a TTL level squarewave may be applied to the CLK input SMA The crystal oscillator module should be removed from its socket when an external clock is used For optimal performance a low jitter low phase noise
42. e In normal operation the AGC keeps the ADC input in the optimal range throughout the TDMA burst The AGC will adjust the DVGA at the beginning and end of each burst and perhaps during a fade This is true for GSM since the modulation is of a constant ampli tude Observing an AM modulated carrier through the debug port allows the steps in the ADC output to be observed Figure 23 shows the ADC output with an AM modulated input signal 3kHz modulation at 150MHz IF 15dBFS threshold 12dB deadband 1 5us tc Changing only the modulation frequency 300Hz and looking at the CLC5902 DDC output shows the reconstructed waveform Figure 24 When receiving an EDGE signal the AGC must prop erly reconstruct the AM content of the modulation The precise time alignment of the compensation cir cuitry enables EDGE data recovery with no loss in performance In some cases the AGC operation will 2001 National Semiconductor Corporation 7 DVGA Steps of 6dB 7 DVGA Steps of 6dB i 1 15 2 25 x 10 Figure 23 AM Modulation 150MHz IF ADC Output 7 DVGA Steps of 6dB 7 DVGA Steps of 6dB 14 15 1 6 17 1 8 Figure 24 AM Modulation 150MHz IF DDC Output increase the noisefloor slightly but since this only happens at high signal levels it does not impact the receiver s performance m f f L 2000 3000 4000 5000 6000 7000 8000 Figure 25 EDGE Modulation 150MHz IF ADC Output
43. e digitized IF to the CLC5902 The CLC5902 mixes the IF with a digital oscillator removes the DVGA gain steps and filters the result A final output of guadrature baseband signals is provided in both serial and paral lel formats Reguired Evaluation Items DRCS7 Board CLC DRCS7 PCASM 5V 1A power supply Signal generator DRCS Control Panel software PC running Windows 95 98 NT Matlab software or other data analysis software One PC serial port Suggested Evaluation Items Data Capture Board CLC CAPT PCASM Data Capture Board software Second PC serial port Reference Documents CLC5957 data sheet CLC5526 data sheet CLC5902 data sheet Data Capture Board User s Guide Evaluation Board Interoperability User s Guide PINO 5 19571 preog uonen eAg SOHO CLC5957 CLC5902 one channel of two CLC5526 Q AGC Channel gt Compensation Filter Complex IF Input DVGA SN Output Fot2Fot T AGC Channel A A 2 I s gt Compensation Filter Filter to remove 4 broadband DVGA SINE COSINE noise at sampling intervals 150MHz Input Clock NCO is the default tuning frequency The undersampling AGC process looks like Power Integrator amp mixing with multiples Detector Control Table of the input clock Figure 1 Diversity Receiver Chipset Single Chan
44. e filters at a sample rate of 52MSPS is shown in Fig ure 51 GSM blocker and interferer requirements Magnitude dB Frequency kHz Figure 51 Frequency Response of GSM Filter Set Although the ADC combined with the processing gain of the digital filters provides 92dB of instantaneous SNR this is not enough to meet the requirements of the GSM900 specification without some analog filtering to attenuate the blocker Nonetheless the digital filters can be used to relax the requirements on the analog filter In par ticular the digital filters can meet the reference interfer ence level of ETSI GSM 05 05 paragraph 6 3 without any assistance from the analog filter Further the blocker per 2001 National Semiconductor Corporation 33 formance of ETSI GSM 05 05 paragraph 5 1 can be met with only minor assistance from the analog filter DDC Output Output Power ADC Output Input Power _ _ Figure 52 ADC and DDC Output Level vs Input Level The FLOAT TO FIXED CONVERTER within the DDC will match any change in gain by the DVGA with a com pensating digital gain change It does this by treating the complement of the DVGA control word as an exponent to the ADC output The overall effect of this is to make the DRCS7 Board appear as a fixed gain channel with extremely large dynamic range as shown in Figure 52 This mode can also be inhibited by asserti
45. e full scale input of 2V pp differ ential is 62dBFS at an IF frequency in the range of 150MHz For levels much below this however the SNR Rev 2 01 January 25 2001 32 improves to 68dBFS or 55nV Hz at 52MSPS This behavior is due to the fact that the large signal high fre quency SNR is dominated by clock jitter GSM systems typically require no more than 9dB of SNR C I which can be achieved at input levels of 59dB below full scale EDGE systems typically require 23dB SNR for full rate operation This requirement can be met with an input signal at 45dBES still low enough to minimize the effects of clock jitter The ADC acts as though it were a 68dB device for these systems Figure 49 The digital filters following the ADC provide processing gain that improve further upon this by 24dB factory default configuration 200kHz output BW Assuming that a single sampling image interferes at a level of 4dB Figure 8 the total noise voltage density at the ADC input is 4 10 55 64100 98nV VEz EQ 14 When this is referred through the 33 8dB maximum gain to the input connector this yields a 13dB noise figure for the DRCS7 Board SNR vs Input Amplitude n SNR dBc Input Amplitude dBFS Figure 49 CLC5957 SNR Extrapolates to 68dBFS DDC The ADC outputs feed into the two channel DDC AGC This part consists of two down converter channels DDC and automatic gain control AGC loo
46. factor of the inductor at In addition to setting the center frequency of the filter capacitors Co and Cy absorb the transient current that is sourced out of the ADC coincident with the sampling instant It is recommended that C9 and Cy be no less than 20pF Baseband Filter Baseband Filter LC Noise Filter Translated To Sampling Images _DVGA Output ADC Input and Stray PCB Capacitance C93 A D cons Ll C99 ES 1K V C94 Figure 9 Noise filter components for AINI It is easy to calculate a new set of filter components using a spreadsheet program set up as follows A B C93 C94 0 00000000002 C99 0 000000000001 Parasitic 0 0000000000015 Ct B1 2 B2 B3 L1 0 000000033 1 2 3 14 B7 B5 0 5 VD GJ Ch Lh 4 WN ra Fcenter Start by selecting an inductor with a relatively high Q 30 40 Next iteratively try available capacitor values for Cy and Cat Use Con to fine tune the result This example uses 20pF and 1pF capacitors with a 33nH inductor for a center frequency of 247 9MHz Once the final PCB is available the center frequency should be checked to verify the effects of PCB parasitics The frequency response of the noise filter can be checked at spot frequencies by observing either the CLC5902 Mixer AI or BI outputs in debug mode with the NCO set to O frequency and O phase The tuning can be verifie
47. fety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Audio www ti com audio Communications and Telecom www ti com communications Amplifiers amplifier ti com Computers and Per
48. full scale dBFS with OdBm at the SMA input connector Rev 2 01 January 25 2001 MAGNITUDE dBFS 200 t i i i i i i j 32768 Point FFT Analysis Pinput 19 3dBFS gol SFDR 68 3dBc Integrated Noisefloor Phase Noise ZS 80 1dBFS 7 6 8 10 12 FREQUENCY Figure 16 IF Input 150MHz at OdBm Common Questions 1 Rev 2 01 January 25 2001 What are the basic operating instructions for Matlab The Matlab command window opens when Matlab is started All Matlab commands can be directly typed into the command window or saved in a script file for repeated execution Type 3 4 then hit enter to see Matlab display ans 7 Use the menu to create a new script file m file file gt new gt m file Type 3 4 on line 1 Save this file as my_test m in the default location Now type my test to see ans lt 7 Now that my test m exists simply type edit my test to load it in the editor To repeat a command hit the up arrow until the desired command is displayed then hit enter When the DRCS amp Capture software are installed all the m files are placed in c nsc mfiles by default This location should be added to the Matlab path Use the path browser file gt set path Browse to c nsc mfiles then path gt add to path and exit the path browser Now Matlab will be able to locate all the provided scripts The command whos will list all the vari
49. icator box will appear on the moni tor and all the LEDs on the DRCS7 Board will light momentarily N Diversity Receiver Chipset Control Panel File Help Channels AGC Output Filter Data Registers L Channel A Common H Source FCK 2 MHz p Fa Mt En Cic Decimation 48 C Bin Z Scale Calculated 22 Phase 0 Deg Test Register Scale Adjust fo Bits Gain o Je m Dither Enabled F2Decimation P 5 Output Sample Rate 2 708E 001 MHz Test Register Value 4096 Channel B 32 M Source T AGC Exponent Inhibit Freq H MHz C Ain Y Debug Enabled Bin Phase p Deg C Test Register Probe at Fl In Al x Gain fo 7 08 7 Dither Enabled Send Page Figure 32 DRCS Channel Configuration Debug Output Now repeat steps 12 and 13 and review the results as before 20 On the Channels page of the DRCS Control Panel enter 150 05 for Freq of Channel A uncheck Debug Enabled The screen should appear as in Figure 33 Click on the Send Page button Rev 2 01 January 25 2001 18 N Diversity Receiver Chipset Control Panel File Help Channels AGC Output Filter Data Registers JI Channel A Common H Source FCK 2 Miz Freg 150 05 MHz 6 An CIC Decimation 48 C Bin S Scale Calculated 22 AGR Deg Test Register AAA Scale Adjust A Bits Gain 6 x 4B
50. ilter 100F Pinput 99 0dBFS 120 SFDR 39 3dBe Integrated Noisefloor 123 0dBFS in re o T MAGNITUDE dBFS di co o T 200 220 6 8 1 FREQUENCY x 10 Figure 21 IF Input 150MHz at 80dBm Alternate FFT Notice in Figure 21 that the integrated noisefloor improved by 2dB over Figure 20 This is because the slightly reduced bandwidth increased the processing gain see the processing gain discussion on page 3 6 How are the two sets of filter coefficients different The STD coefficients are optimized for a narrow tran sition band about 50kHz with a flat pass band and stop band response The stop band rejection is about 80dBFS The 3dBFS point is at 119kHz placing the filter bandwidth at 88 of the output sample rate 119kHz 2 270 833kHz Rev 2 01 January 25 2001 10 11 12 13 Rev 2 01 January 25 2001 The GSM coefficients are optimized to meet the GSM blocking test requirements These filters sacrifice the narrow transition band response of the STD filters for an ultimate stop band rejection of 105dBFS beyond 800kHz The 3dBFS point is at 87kHz placing the fil ter bandwidth at 64 of the output sample rate The CLC5902 can meet the GSM 900 channel filter requirements totally in the digital domain with these filter coefficients Which filter coefficients should be used for GSM EDGE systems Since there is a SAW filter in fro
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52. isecof3000 OK Cancel Figure 14 Capture I O Dialog To proceed the Capture Board must have power a sample clock and be connected to the proper COM port LED1 on the Capture Board should be on LED6 should be on about half as bright as LED1 12 Click the right mouse button over the Capture soft ware panel select Configure Capture then select the options shown in the Capture Configuration Dialog Figure 15 Configure Capture HI Mode Capture Histogram Capture Debug Histogram Debug IN Bits JA Channel From 24 Bits Channel A AOUT 20 Bits Channel B C BOUT C Upper 18 Bits Parallel Outputs to FIO C Upper 16 Bits 1st Bit C Lower 16Bits C Skip 1st Bit Phase In Phase Only C Quadrature Phase Only C In Phase Then Quadrature Phase C Quadrature Phase Then In Phase OK Cancel Figure 15 Capture Configuration Dialog Serial Port 13 Now click Start to capture a 32k sample record The data will be saved in c temp data dat 14 Start Matlab and add c nsc mfiles to the path 15 Type analysis menu in the Matlab command win dow 16 Click DRCS Serial on the menu to plot an FFT or run drcs ser fft m from the Matlab command line The resulting FFT should be similar to Figure 16 showing a single tone at about 50kHz The measured Pinput should be about 20dB relative to
53. lated back to the corresponding analog input voltage 2Vpp dif ferential for the CLC5957 Rev 2 01 January 25 2001 2 Fundamental plot Desired input signal shown on an FFT Tone A signal shown on the FFT plot The fundamental will usually be the tone with the largest amplitude on the FFT plot dBc dB relative to carrier or fundamental level dBES dB relative to the ADC or DRCS Full Scale output level Pinput Magnitude of the largest signal found in the FFT Measured in dBFS since it is relative to the full scale out put value The DRCS and ADC FFT routines include vari ables to specify the full scale value appropriately SFDR Spurious Free Dynamic Range The difference between the fundamental amplitude and the next largest signal on the FFT excluding DC Includes all distortion terms Typically in dBc Integrated Noise Floor The sum of the FFT bins excluding DC the fundamental and the first 50 harmon ics Measured in dBFS The excluded information is replaced by the average noise floor level SNR Signal to Noise Ratio The sum of the FFT bins excluding DC the fundamental and the first 50 harmon ics Typically in dBc Add back the number of dB below full scale Pinput to get the noise floor or SNR in dBFS ENOB Effective number of bits Noise floor 1 76 6 02 Each bit represents 6 02dB in the analog domain This is of interest since a perfect 12 bit ADC would pro vide a 74dB noise fl
54. meet the requirements Rev 2 01 January 25 2001 tu gt 4 tp ENC toavi gt DAN ts sk DATA CD DAVe l k ts2 gt lt tye 4 DATAZ EE AEN lt tar ck lt lar tsu gt th 4 DAVL8RDAVE ua Figure 10 DRCS7 ADC to CLC5902 Clock Timing at 52MHz If a maximum propagation delay of 2 5ns is assumed for the inverter with a 10pF load the clock duty cycle can only change a small amount This condition allows the positive clock percentage to range from 49 5 to 60 In a real system it is unlikely that the two CLC5957s will be skewed the maximum amount in opposite directions Since the CLC5957 timing specifications are 3 sigma lim its that means only 2 3 parts per thousand will be at the limit The chance of having two parts with maximum opposite skew is 6 7 parts per million The statistical chance of timing violations is further reduced by the inverter propagation delay distribution and the fact that most CLC5957s will be placed from the same wafer lot Ignoring the DAV Signals When a square wave clock is available to drive ENCODE this same signal may be inverted to drive the CLC5902 CK input When this is done the duty cycle reguirements are those set by the CLC5902 The CLC5902 data input setup and hold times will be independent of clock duty cycle since all timing is now relative to the falling edge of ENCODE Figure 11 shows a si
55. nel Functional Block Diagram 2001 National Semiconductor Corporation Rev 2 01 January 25 2001 INSVOd LSOICG O IO Table of Contents Section Wl y ga Overview Required Evaliiation hens Suggested Evaluation Items Reference Documents Table of Contents Key Concepts Definition of Terms Sub Sampling Processing Gain General Description DRCS7 Evaluation Board 1 Os Power Clock Input IF Signal Inputs CLC5902 Serial Outputs CLC5902 Parallel Output CLC5902 Debug Output COP8 RS 232 Serial Interface DRCS7 Block Interfaces DVGA to ADC Interface LC Noise Filter ADC to CLC5902 Interface Clocking the DRCS Quick Start Common Questions DRCS Control Panel oido OO qaa L L K K E K K UD ad KA KA M M e EEG Channels Page 14 AGC Page 14 Output Page 15 Filter Data Page 15 Serial Communications 15 Control Panel Software Dusi 15 Default Configuration and SW2 Settings 15 Data Capture Board Settings 16 In Depth Operation 16 DDC Large Signal N amp ffinearity Pise 18 Connector Pinouts 20 Operation with a 13MHz Reference 20 Schematics 20 Reference Design 20 PC Board Layout 28 Appendix 32 DVGA 32 ADC 32 DDC 32 AGC 34 Key Concepts Definition of Terms Full Scale The maximum digital output level 2 or 2047 2048 for 12 bit ADCs Full scale for the CLC5902 can be set for 8 16 24 or 32 bits The DRCS7 Board defaults to 24 bit outputs This value is often re
56. ng EXP_INH An expression for the gain through the DDC channel A is 1 4 Gppc 3 DEC 1 aI SCALE 44 AGAIN 1 EXP INH EQ 15 GAIN 22 Gp Gp Rev 2 01 January 25 2001 AGC_TABLE Envelope Detector AGC_LOOP_GAIN Pour r EXP AIN ABSOLUTE VALUE v 2 STAGE DECIMATE BY 8 CIC FILTER L FIXED TO FLOAT CONVERTER 32X8 RAM Ho AGAIN 3 le v AGC HOLD IC K AGC IC A C SHIFT DOWN AGC FORCE AGC COUNT PERIOD AGC RESET EN AGC EN gt LOAD COUNTER EN FUNCTION PROGRAMMED INTO RAM y ONE SHOT gt LOG EN Figure 53 AGC Circuit Channel A 21 Y n Ege Gg 16 2 EQ 16 63 y o isl 16 2 Cus EQ 17 The numerators of Gp and Gp equal the sums of the impulse response coefficients of F1 and F2 respectively For the STD and GSM sets G and Gp are nearly equal to unity Observe that the AGAIN term in EQ 15 is can celled by the corresponding term appearing in EQ 13 so that the entire gain of the DRCS7 Board is independent of the DVGA setting when EXP_INH 0D The appearing in EQ 15 is the result of the 6dB conversion loss in the mixe
57. ngle ended clock circuit and Figure 12 shows the timing diagram for this approach For the IDT74ALVC1G04 inverter tppa is the minimum propagation delay of 1 0ns and tppp is the maximum value of 3 2ns In this case the setup and hold times are tsy tfpt ty fpgy fppA EQ 9 1923 13 41 7 23ns tHD tpnv pps EQ 10 z 7 3 2 3 8ns The margins of 230ps and 800ps are not dependent on the clock duty cycle CLC5902 Inverter A is Mo d ADC AIN ENC ENC osc H gt o 4 er CK All capacitors ENC ENC are 0 01uF ADC BIN Figure 11 Single Ended Clock Schematic toav gt ENC Ke iPDB INV EN C m tsu gt lup c DATA A Figure 12 Inverted ENCODE Clock Timing at 52MHz Rev 2 01 January 25 2001 8 2001 National Semiconductor Corporation Quick Start Initial performance measurements of the DRCS7 Evalua tion Board can be obtained very quickly with the Data Capture Board and associated Matlab scripts The equip ment required to verify the DRCS performance includes 1 DRCS7 Evaluation Board CLC DRCS7 PCASM 2 Data Capture Board CLC CAPT PCASM 3 Connector Adapter CLC ADAPT1 PCASM sup plied with CLC DRCS7 PCASM 5V 1A power supply 5 Signal generator 150MHz sinewave 0dBm PC with Windows 95 98 or NT4 and Matlab To make an FFT plot of the DRCS output 1 Install the
58. nt of the ADC either set of coefficients may be used Using the STD set may make it easier to recover the signal since it pro vides a little wider bandwidth Why are the Fl coefficients included with the DRCS Control Panel software and the COP8 configuration file different than those in the CLC5902 datasheet These coefficients have been uniformly scaled to cre ate 4dB of gain This compensates for the error in the SCALE and CIC filter combination when the CIC decimation is not a power of two These new coeffi cients are optimized for GSM EDGE systems What if SW2 4 and SW2 8 are not set the same SW2 4 sets the decimation and SW2 8 selects the fil ter coefficients Both must be either OFF for the STD coefficients or ON for the GSM coefficients If they are not the same the tone in the FFT plot may show up at the wrong frequency or the rolloff from the filter will not be observed Why does the FFT plot look like Figure 22 In the Capture software make sure that Capture Ist Bit is checked This option controls the deserializa tion of the DRCS output For some combinations of output and decimation this setting may change The DRCS Control Panel software will tell you how to set this option on the Output tab see page 15 Why is the default tuning at 150 05MHz An input signal at 150 0MHz can be easily generated by driving a 150MHz bandpass filter with a 50MHz crystal oscillator Only the third harmonic
59. nterface LC Noise Filter While the IF SAW filter allows only the desired signal to be sampled the DVGA introduces broad band noise at the ADC input A simple noise filter between the DVGA and ADC removes this noise Failure to attenuate noise from the DVGA appearing at the ADC sampling image frequen cies will degrade the system performance Figure 8 shows the response of the noise filter with respect to the sampling images Rev 2 01 January 25 2001 The nominal component values for the filter provide a cen ter frequency of 150MHz a 3dB bandwidth of 18MHz and an insertion loss of 0 7dB Assuming an ADC sample rate of 52MSPS the filter provides about 4dB of attenua tion at the closest image frequency which is at 162MHz Figure 8 More attenuation is possible by increasing the Q of the filter but this would make the center frequency tolerance more critical and increase the group delay through the filter the stability of the AGC loop is reduced by large group delays More attenuation will also be achieved if the IF is moved further away from 156MHz To change the IF frequency of the DRCS7 Board the noise filter components must be changed The equations below pertain to Figure 9 and provide a means of comput ing the new values o EQ 4 LC 0 EQ 5 Ry JC Gras tps EO 6 LC O Li Cr Cg472 Cog 1 5pF EQ 7 In these equations Cy Coy Ry 600 I IK 375Q G is the filter gain at and Q is the quality
60. o minimize crosstalk The supplies have series inductors for each section to provide extra isolation Figure 45 Figure 46 Figure 47 and Figure 48 show the DRCS7 Board parts placement and PC board layers PCB layout tips are annotated on the plots O Q DIVERSITY RECEIVER CHIPSET EVAL BOARD N EI LC730092 REV D S Y2 e e D e e e e ANI O D e e E e cu C26 C27 e ni 2 e e ce C63 o c6 054 d SC R28 a m Es R3 7 R 2 c3 SE Ble R29 See eel gt e eo ejo Wi EM Zn Z eg PETI e Figure 45 DRCS7 Board layout Top L1 Silk AND gate for the 2 Keep these traces DAV clock signals to the minimum Rev 2 01 January 25 2001 28 length possible 2001 National Semiconductor Corporation NATIONAL SEMICONDUCTOR LAYER2 e ef e AGND e E nee bd DGND Figure 46 DRCS7 Board layout GND L2 Line up split between analog and digital planes across all layers Common point ground where the analog and digital planes join Minimize parasitics at the LC filter since these are high impedance nodes Minimize capacitive loading on the ADC output by removing power and ground planes 2001 National Semiconductor Corporation 29 Rev 2 01 January 25 2001 CAIYAS AOTIUVOMODIM Z JAMOITAM O O O e e c Figure 47 DRCS7 Board layout Power L3 Line up spli
61. on changes Scale Adjust is a bit shift value added to Scale prior to down loading to the CLC5902 You can enter either a positive or negative value with the restriction that Scale Adjust Scale Calculated fall within the range of 0 to 44 inclu sive warning is issued for values entered outside this range Gain refers to the bit shift after the CIC filter Figure 50 AGC Page The popup menus for initial conditions and gains refer to the gain of the DVGA The loop dynamics for the AGC are set in the lower left box Press the Calculate button after entering values for Threshold Deadband and Time Constant and the AGC lookup table values and AGC LOOP GAIN are computed 2001 National Semiconductor Corporation Output Page SCK Rate must be selected low enough to allow all serial bits to exit within one output sample period If there is not enough time to transmit all the serial data an error message will be displayed See the CLC5902 data sheet for further discussion The proper setting of the 1st Bit option of the Capture software will be shown on the Output page Figure 29 N Diversity Receiver Chipset Control Panel File Help Channels AGC Output Filter Data Registers Set Capture software to capture 1st bit A Serial Setup IZ Serial Output Enable SCK Rate FS 2 Output I Output Format C app CP Cep CF Point Invert SCK Polarity JO Invert SFS Polarit
62. oor Real ADC performance falls short of this ideal and ENOB is a measure of the real perfor mance SINAD Signal to noise Distortion The sum of the FFT bins excluding only DC and the fundamental This metric approximates the root sum of squares of both SNR and SFDR For example if SNR 52 63dBc and SFDR 57 4dBc then SINAD will be about 52 6dBc domi nated by the SNR THD The sum of all harmonic energy relative to full scale Any non harmonic spurs will be excluded Sub Sampling The process of sub sampling can be thought of as mixing the input signal with the sampling frequency and its har monics This means that many signals can be mixed down to DC and their original frequency can no longer be deter mined For example if the sample frequency Fs is 52MHz then inputs at 6MHz 52 6 46 52 6 58 98 110 150 162 would all mix down to 6MHz The IF SAW fil ter will only allow a single frequency to be sampled by the ADC so the original input or carrier frequency is known Sub sampling cannot be used if the original input fre quency must be determined at the ADC output without an IF filter This is because the Nyquist criteria is violated Sub sampling still proves useful if there is no need to determine the carrier frequency at the ADC output This is true for the DRCS since the receiver only needs to recover 2001 National Semiconductor Corporation the information on the carrier and not the carrier itself Nyquist is no
63. ower supply 8 Start the DRCS Control Panel and Data Capture Board software 9 Configure the COM ports for the DRCS Control Panel and Data Capture Board software The COM port setup for the DRCS Control Panel is located under File Configure I O The COM port setup for the Data Capture Board software is accessed by right mouse button clicking anywhere on the pro gram window and selecting Configure I O Note that power must be applied to the Data Capture Board the clock must be present and the serial cable must be connected in order for the software to accept the COM port configuration 10 Connect a 10dBm sinewave at 150 00MHz to the DRCS7 Board AIN1 input The DVGA should servo to a gain of either 6dB AGAIN 3 or 12dB AGAIN 4 and the ADC should be operating at a level of 10dBFS or 6dBFS Because EXP_INH is not asserted for this configuration the DDC output which will be observed below should be at 28dBFS This can be computed from the gain equations presented in the Appendix page 32 and the register data provided in the Registers page of the DRCS Control Panel The first measurement will be to use the debug mode of the CLC5902 to probe the output of the ADC 11 Set SW2 on the DRCS7 Board to 00000101 87654321 then press reset This selects the Mixer AI debug output and sets the NCO to 0Hz Configure Capture Mode C Capture Histogram lt j C Hi
64. ows how this can be done Clocking the DRCS When providing a clock signal for the DRCS several con straints must be observed 1 The CLC5957 ENCODE specifications must be met 2 The CLC5902 CK specifications must be met and 3 The CLC5902 data input setup and hold times must be met The CLC5957 and CLC5902 datasheets contain all the timing parameters required to verify these conditions Now using the datasheet specifications consider each of the above constraints CLC5957 ENCODE Requirements The CLC5957 ENCODE specifications require that the ENCODE signal always be high tp for at least 7 1ns and low ty for at least 7 1ns The maximum time for tp and tm 1s limited by the minimum conversion rate This requires that 1 tp ty never be less than 10MHz With a clock rate of 52MHz as used in the DRCS for GSM EDGE systems the period is 19 23ns In this case if tp is reduced to 7 1ns then ty will be 19 23ns 7 1ns or 12 13ns This corresponds to an acceptable duty cycle variation of 37 63 CLC5902 CK Requirements The CLC5902 is specified to operate with a clock up to 52MHz with up to 40 60 duty cycle variation CLC5902 Input Setup and Hold Requirements In the DRCS the CLC5902 must be driven by two differ ent CLC5957 ADCs This can be accomplished by com bining the DAV signals with a fast AND gate or ignoring the DAV signals and clocking the CLC5902 with an inverted version of ENCODE Designs with a
65. ps The DDC per forms the final mix to baseband and baseband filtering see Figure 50 The NCO can tune across the full Nyquist band with 32 bit precision With phase dither enabled the spurious perfor mance is 101dBc or better and SNR is 84dBFS The fre quency and phase of the two channels are completely independent In addition the phase dither of the two are uncorrelated 2001 National Semiconductor Corporation EXP_INH x lt hi DN l EXP w z 2 m from AGC y z i Wir Ab a S e m E EXPONENT N x L LA gt gt gt N O La a gt gt 15 D 22 a co z a oc a E ga oe HH Du a DC ux H DI 2 HI LU g TO z nuc EE 2 o HE o HB ko E MUXA E 2 zu E s o E f z lt ka z so 3 EU faf o5 o5 IRCUIT z E o T NON x CH L4 26 Lu 0 lon o z H CL E E l a a 15 o 22 a o 21 a oH 21 a 7y 17 PREGA SIN COS NCO PHASE A gt y Figure 50 CLC5902 Digital Down Converter Channel A The baseband filtering is performed by a cascade of three decimating FIR filters The overall decimation ratio can be programmed from 8 to 16 384 The two final filters feature 21 and 63 user programmable taps respectively A set of tap coefficients are published in the CLC5902 data sheet which provide adequate filtering to meet the GSM blocker and interferer requirements The frequency response for thes
66. r AGC The AGC loop for channel A is shown in Figure 53 Each channel has its own loop The ADC output power is mea sured with an envelope detector and used to adjust the DVGA gain Envelope detection is performed by an abso lute value circuit followed by a lowpass filter whose response is shown in Figure 54 The filtered signal is used to address a lookup table which generates an error signal based on the programmed threshold deadband and loop time constant targets This error is integrated to produce the 3 bit control signal for the DVGA Integrator gain is programmable via the shifter preceding it to allow loop time constants that can be varied by factors of 2 Frac tional control of time constant can be achieved by altering Rev 2 01 January 25 2001 34 Magnitude dB 60 Frequency Normalized to Fo Figure 54 Response of Envelope Detector Filter the slope of the transfer function stored within the lookup table In the course of measuring ADC power the absolute value block within the envelope detector also generates a second harmonic of the aliased IF frequency For example an IF of 150MHz aliases to 6MHz at the ADC output when the sample rate is 52MHz The absolute value block produces from this a de term and a second harmonic at 12MHz the latter of which is rejected by the low pass filter If the alias frequency is too low though its second harmonic will fall within the passband of the
67. section on page 14 Data Capture Board Settings The Data Capture Board and companion software provide the ability to capture data from the DRCS7 Board as well as a variety of analog to digital converter products When evaluating the DRCS7 Board configure the Data Capture Board like this DIP switches all OPP e WCLK jumper Pin120 e VCCD jumper 5V Rev 2 01 January 25 2001 16 Figure 30 provides a quick reference for the Data Capture software configuration options Specifies the Serial Output pin on the CLC5902 to monitor Capture Serial data Capture Parallel To FIFO Capture Histogram Capture Debug T Histogram Debug Bits JJ Channel From 24 Bits Channel A AOUT C 205i C ChannelB C BOUT C Upper 18 Bits L Parallel Outputs to FIFO C Upper 16 Bits A 1st Bit C Lower 16 Bits C Skip st ei C In Phase Then Quadrature Phase C Quadrature Phase Then In Phase rd Phase A In Phase Only C Quadrature Phase Only Deserializer Control specified by DRCS Control Panel software Deserialize the VQ Options selected channel Figure 30 Capture Software Quick Reference In Depth Operation This procedure will verify proper operation of the DRCS7 Board and Data Capture Board Initial operation is cov ered in the Quick Start section on page 9 If a
68. stogram Debug Bits r Channel y rd From 24 Bits Channel 4 7 OUT C 20 Bits C Channel B BOUT Upper 18 Bits perete Outputs to Pro Upper 16 Bits 1st Bit Cl C Skip 1st Bit E Gaptire st Bit Phase C n Phase Only inPhe hen Quadrature Phase C Guadrature Phase Only C Guadrature Prase Henin Phase OK Cancel Figure 31 Capture Configuration Dialog Debug Port 2001 National Semiconductor Corporation 17 12 Use the right mouse button to access the Configure Capture screen of the Data Capture Board software and choose Capture Debug within the Mode box Then choose Upper 18 Bits within the Bits box Press OK The screen should appear as in Figure 31 13 Press Start on the front panel of the Data Capture software When the completion bar reaches 100 the captured data will be written to the file C TEMP DATA DAT If the TEMP directory did not previously exist the soft ware will create it You can also specify a different file name and directory by right mouse button clicking on the Data Capture Board software window and choosing the Change Data File command Keep in mind that the Matlab scripts will look for the data in the default location The values in DATA DAT represent 24 bit 2 s complement integers When Mixer Al is selected only the upper 15 bits are non zero These numbers can be converted to signed fractional values and plotted by running the Matlab script plot twos m Verify that
69. t between analog and digital planes across all layers Minimize parasitics at the LC filter since these are high impedance nodes Minimize capacitive loading on the ADC output by removing power and ground planes Rev 2 01 January 25 2001 30 2001 National Semiconductor Corporation MAJYAJ HOTOUOUODIM Z JAMOITAM d m Figure 48 DRCS7 Board layout Bottom L4 Line up split between analog and digital planes across all layers Minimize parasitics at the LC filter since these are high impedance nodes Minimize capacitive loading on the ADC output by removing power and ground planes 2001 National Semiconductor Corporation 31 Rev 2 01 January 25 2001 Appendix Input Circuit and Signal Levels The AIN1 and AINe IF inputs are transformer coupled into the DVGA inputs The transformers convert the sin gle ended input signal to differential and match the 2000 input of the DVGAs to the 50Q input connectors They have a voltage gain of 2 Geru 2 EQ 11 In a production system the transformer might be replaced by an IF SAW with differential output drive capability With the DVGA set to maximum gain 30dB the total analog gain from the input connector to the ADC is 33 8dB and an input level of 23 8dBm will drive a full scale input at the ADC With the DVGA set to minimum gain 12dB the total analog gain is 8 3dB and a 18 3dBm input level is required to drive the ADC to full scale
70. t violated for the required information band width of 200kHz for GSM EDGE systems Each sampling image folds back to lt Fg 2 A A A gt 8 8 E 8 B Cype ee oot m Pre i l j T t Hz h Fs 2 Pe 2Fs 3Fs Information 52 104 156 Bandwidth I O Phase reversal will occur for the dashed lines Figure 2 Sub Sampling Processing Gain ADC noise performance is typically limited by thermal noise When an ADC is specified the noise bandwidth is normally defined as the Nyquist bandwidth This leads to an integrated noisefloor measurement of 65dB relative to full scale dBFS in a 26MHz bandwidth for the CLC5957 at 52MSPS When the CLC5957 output is filtered by the CLC5902 a much narrower bandwidth is provided at the output This filtering process provides noise processing gain PG as a function of the bandwidth reduction For the DRCS7 Evaluation Board the sample rate Fs is 52MSPS and the output bandwidth defaults to roughly 200kHz 100kHz so the processing gain should be BW The CLC5902 removes the alias image that would normally appear here The noise is also removed Channel Filter Output Noise ADC Noise Fg 2 Figure 3 Processing Gain The CLC5902 filters provide an additional 3dB of pro cessing gain because they remove the alias image and noise near Fs The processing gain equations then become BW PG 10 xlog 97 S PG 10 x log 200EHz 52MHz PG 24 1dB EQ 2
71. utput above 98dBFS before the serial output will change Rev 2 01 January 25 2001 DRCS Control Panel Software The DRCS Control Panel drcscp exe requires Windows 95 98 NT and a free serial port to operate Run setup exe from the CD ROM to copy the appropriate files to your hard drive and build the necessary directory structure Run drcscp exe to start the program To configure the COM port choose Configure I O from the File menu The DRCS Control Panel is a user interface which allows the CLC5902 configuration registers to be programmed from a PC All register settings are controlled from the four tabs on the left The Registers page Figure 28 allows you to view a summary of the register values that are down loaded to the CLC5902 N Diversity Receiver Chipset Control Panel File Help Channels AGC Output Filter Data Registers DEC 47 DEC_BY_4 SCALE GAIN_A GAIN_B RATE 0 22 1 1 AGC_RESET_EN 1 SOUTEM 1 0 0 0 1 1 2 AGC_HOLD_Ic AGC_LOOP_GAIN AGC COUNT 2815 D 4 D AGC FORCE 1 D D 4 SCK_POL SFS POL AGC IC A 32 RDY POL AGC_IC_B 32 MUX_MODE AGC_RB_A 0 PACKED AGC_RB_B 0 FORMAT TEST_REG 4096 FREQ A 491443374 DEBUG EN 0 PHASE A 0 DEBUG TAP 12 FREQ E 491443374 DITH_A 1 DITH_B 1 PHASEB 0 Figure 28 Registers Page Note The DRCS Control Panel software can only write to the CLC5902 registers The software
72. y JO Invert RDY Polarity C Aout A Bout B Aout AB Bout disabled C 1 per Word 1 per I Q Pair Packed Frame Sync Send Page Figure 29 Output Page Filter Data Page The coefficient values for each of the symmetric FIR fil ters can be manually entered or loaded from an ASCII text file using the Load button The file must have a f7 exten sion for FIR Filter 1 and a f2 extension for FIR Filter 2 The file format is one signed integer coefficient per line and the number of lines must equal the number of unique coef ficients Also there must be no blank space before the val ues in the files Open one of the default coefficient files c nsc data default f1 in a text editor to see the format Serial Communications There is no handshaking between the DRCS7 Board and the PC If the system is operating correctly all the LEDs will light during transmission and only LEDI will remain lit at the completion of transmission If the transmit sequence is upset reset the DRCS7 Board and re send Control Panel Software Questions 1 Loading new filter coefficients did not change the response as expected Why If the new filter coefficients require a different deci mation value it must also be sent to the DRCS7 Board 2 What happens to the default configuration loaded by the COP8 when new data is sent When the DRCS Control Panel sends data to the DRCS7 Board the new data repla
73. z i E Test Register Value 4096 Channel B Test Register Value 4096 Channel B egi Source T AGC Exponent Inhibit T AGC Exponent Inhibit Freg 150 05 MHz C Ain Freg 150 05 MHz C Ain IV Debug Enabled IV Debug Enabled Bin Bin Phase 0 Dea ores Register Probe at Fi mal z Phase p Ded c Test Roaster Probe at Ft inal z Gain s 7 dither Enabied Send Page cr 7 lt dither Enabied Send Page Figure 34 DRCS Channel Configuration CIC Rollover Figure 36 DRCS Channel Configuration Saturation Use plot twos m Plot Twos from the analysis menu to convert the data to signed fractional values and plot them Zoom in on the first 300 points You should see the clip ping as shown in Figure 37 This represents the type of 4 nonlinearity at all stages of the DDC except for the CIC filter es EE Py ME Ei HD GEET 268 EE E URE DEE AA A A r e E Figure 35 CIC Overflow Distortion set consistent with the chosen CIC decimation value so that the CIC output is less than full scale Figure 35 may not look exactly the same as yours due to the frequency error between the on board clock oscillator and the input source The important characteristic of the distortion is that the positive sinusoid peaks have been translated to negative values and the negative peaks to positive values Figure 37 Datapath Saturation at the F1 Input

CLC-DRCS7-PCASM DRCS7 Evaluation Board User's Guide (Rev. E)

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