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XtremeDSP Development Kit User Guide

1. P FETE LEE qum Su uk ie ri FET Fi Puerta j iS rn 4 ru E mm tkm bee Lum PE ril EM Eua ua im papa ss P fires FR eee Vee IE Trus sy uar qam refer Figure 53 Assigned Bitfiles in FUSE Probe You should see the locked constellation appear almost immediately 9 14 Implementation Source The full implementation and source files produced stored the lt cdrom gt examples sysgen Q AM qam dplrisysgenQAM16 work Please note in System G enerator projects a complete ISE Project N avigator file is available Also there are two batch files included in the sysgenqam16 work folder namely xc2v3000f9676 16 batch bat xc2v2000fg676_qam16_batch bat These are setup for using xflow to create the implementation file and can be used if necessary to recreate the bitfiles or retarget the implementation as necessary 9 15 UCF Modification In this implementation there were some small modifications to the UCF produced from System Generator N amely 1 NET clk LOC AB14 This maps to CLK1 FB a This was added to pin lock the clock signal to the appropriate pin that was being driven by the 2v80 design being run in the clock FPGA This can be changed to another clock input as necessary 2 DAC2 D lt 10 gt LOC Constraint a needs to be modified d
2. 24 Signal Pinouts 135 141 169 pene 32 S DIME II Communication busses 118 DIME II System 5 119 Synthesis and Implementation Settings 71 Example Application Temperature 123 ADC to DAC feed through design 81 Modulator 86 SysgenQ AM 16 utput to DACs 93 DU fa Reis dc 40 User GA k 117 174 www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide X System 5 5 XtremeD SP Development Kit 5 Gere 6 Z SKE 5 Physical Layout 5 ZBT SRAM Memory 115 SDeCICQLIO 7 NT107 0132 Issue 9 23 05 2003 www nallatech com 175 XtremeDSP Development Kit User Guide 176 www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide NT107 0132 Issue 9 23 05 2003 www nallatech com 177 Remarks form W e welcome any comments you may have on our product and its documentation Your remarks will be examined thoroughly and taken into account for future versions of this product XtremeDSP Development Kit User Guide 21 05 2003 NT 107 0132 9 Errors detected
3. ws eosa YR mava wa vO Table 71 ADC Signal Pinouts 2V2000 11 6 7 User IO Header Signal Name User FPGA 2V2000FG676 PIN User IO 1 10 User 10 2 AD10 Table 72 User IO Header Pinouts 2 2000 11 7 XC2V3000 FG6 6 11 7 1 User FPGA to DIME II motherboard communication Local Bus Pinouts Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V3000FG 676 Connector 2V3000FG676 PIN No PIN No PIN No PIN No LBU S lt 0 gt PB1 LBUS 32 PB37 E10 LBUS 1 PB2 LBUS 33 PB38 F10 LBUS lt 2 gt PB3 LBUS lt 34 gt PB39 150 www nallatech com 107 0132 Issue 9 23 05 2003 DIMETI Dime Il Connector PIN No Signal Name User FPGA 2V3000FG 676 PIN No XtremeDSP Development Kit User Guide User FPGA 2V3000FG676 PIN No Dime Il C onnector PIN No Signal Name LBUS lt 9 gt LBUS lt 10 gt 7 4 3 6 5 LBUS lt 14 gt LBUS lt 46 gt i LBU S 16 LBUS lt 17 gt LBUS lt 18 gt LBUS lt 19 gt LBUS lt 20 gt LBUS lt 21 gt LBUS lt 22 gt LBUS lt 23 gt LBUS lt 24 gt LBUS lt 25 gt LBUS lt 26 gt LBUS lt 27 gt LBUS lt 28 gt LBUS lt 29 gt LBUS lt 30 gt LBUS lt 31 gt mm we Ws We mm ms ms 5 N4 a U7 D2 D1 H1 PB36 LBU 5 lt 63 gt PB72 Table 73 Local Bus Pinouts 2V3000 Adjacent IN Bus User FPGA communications User FPGA Signal Name Connector 2V3000FG 676 C onnector PIN No P
4. 3 BenADDA This part of the User Guide provides you with information on installing and using the BenAD DA DIME II module In the following Sections Section 7 BenADDA O verview Section 8 BenADDA Installation Guide Section 9 BenADDA Implementation Guide Section 10 BenADDA Reference Guide N T107 0132 Issue 9 23 05 2003 www nallatech com 61 XtremeDSP Development Kit User Guide FIANE TT 62 www nallatech com NT107 0132 Issue 9 23 05 2003 DINMEAI XtremeDSP Development Kit User Guide Section 7 BenADDA Overview 7 1 BenADDA BenADDA DIME II module provides high speed digital to analogue and analogue to digital conversion capability As part of the scalable DIME II family the BenADDA can be easily integrated into systems through the range of available D IME II motherboards and associated software firmware The module contains two high speed AD C and two high speed DAC channels which allow for flexible high resolution data conversion for both baseband and IF applications Key to the BenADDA s performance is the on board Xilinx Virtex II FPGA which provides you with a powerful data processing resource Some of the main application areas for the BenADDA include mobile communications systems infrared imaging wideband cable systems and multi channel multi mode receivers Figure 31 BenADDA NT107 0132 Issue 9 23 05 2003 www nallatech com 63 XtremeDSP Development Kit User Guide DIME 7 2 Ke
5. Suggested Improvements Please send this completed form to N allatech Boolean House O ne N apier Park Cumbernauld Glasgow G 68 OBH United Kingdom If you prefer you may send your remarks via E mail to support nallatech com or by fax to 44 0 1236 789599 If you want Nallatech to reply to your comments please include your name address and telephone number
6. NT107 0132 Issue 9 23 05 2003 www nallatech com 167 XtremeDSP Development Kit User Guide DIMET Table 105 ZBT Address Signals Pinouts Bank B 2V3000 6000 T hese are Expansion PIN s and may not be supported by the ZBT memory nly use the above address pins if the onboard ZBT memory is in the following list ZBTB A lt 18 gt use if ZBT Memory is 16Mb ZBTB lt 19 gt use if ZBT Memory is 32Mb ZBTB A lt 20 gt use if ZBT Memory is 64Mb ZBTB A lt 20 gt use if ZBT Memory is 128 0 ZBT Data Signals Bank B Signal Name User FPGA Signal Name User FPGA 2V3000 2V6000 PIN No ZBTB D lt 11 gt E8 ZBTB D lt 13 gt 11 ZBTB D lt 29 gt C7 Table 106 ZBT Data Signals Pinouts Bank 2V3000 6000 UJ ZBTB D 0 ZBTB D lt 1 gt ZBTB D lt 2 gt ZBTB D lt 3 gt ZBTB D 4 ZBTB D 5 UJ UJ UT c 71 1 UT ZBT Parity Bits Bank B Signal Name User FPGA Signal Name User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No Table 107 ZBT Parity Bits Pinouts Bank B 2V3000 6000 11 8 5 Clock signals relating to DACs andADCs Clock sources available at CLK FPGA Signal Name CLK FPGA 2V80 Pin User FPGA Signal Description NO 2V3000 2V6000 PIN No Op Amp 6 GCLK6S N a External CLK source via Op_Amp 6 Ampl C6 GCLK7P Complement of External 168 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit
7. Main FPGA Figure 37 Clock FPGA The design for the main FPGA takes the input data from both ADCs converts it from 2s complement to offset binary and outputs it to both DACS as illustrated in Figure 38 Figure 38 ADC to DAC feed through design 9 7 Configuring the ADC to DAC feed through example To start the GUI 1 BOn the Windows task bar click Start gt Programs gt FUSE gt Software gt FUSE Probe 82 Www nallatech com NT107 0132 Issue 9 23 05 2003 P13IMNMIE TI XtremeDSP Development Kit User Guide 2 In the FUSE Probe program window shown below select Control O pen card from the menu at the top of the window o LE Sis Ip CT RI Comm Du FJ ry Figure 39 Fuse System Software GUI 3 The Locate Card window is then displayed Select PCI in the Interface box and All Card Types in the Card Type box Then click on Locate Cards Figure 40 Dialogue box to locate cards 4 Inthe Selected Cards window check the BenO card box and click on Open Cards NT107 0132 Issue 9 23 05 2003 www nallatech com 83 XtremeDSP Development Kit User Guide DIME F rs el USB f rd Di
8. Adjacent IN Bus User FPGA communications Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA C onnector 2V1000 PIN C onnector 2V1000 PIN No No PIN No PIN No ADJIN lt 0 gt PA29 ADJIN lt 13 gt PA43 ADJIN lt 1 gt PA30 ADJIN lt 14 gt PA44 E12 ADJIN lt 2 gt PA31 ADJIN lt 15 gt PA45 ADJIN lt 3 gt PA 32 ADJIN lt 16 gt PA47 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide User FPGA Signal Name Dime ll User FPGA 2V1000 PIN C onnector 2V1000 No PIN No PIN No R1 T4 Connector PIN No ADJIN lt 4 gt PA33 Signal Name Dime ll ADJIN lt 9 gt PA39 ADJIN lt 22 gt PA53 Table 43 Adjacent IN BUS Pinouts 2V 1000 ADJIN 0 is connected to a clock pin GCLKOS on the Virtex ll ADJIN lt 1 gt is connected to a clock pin GCLK1P on the Virtex ll Adjacent OUT Bus User FPGA connections Signal Name User FPGA Signal Name User FPGA 2V1000 PIN 2V1000 No PIN No ADJO UT lt 4 gt E20 2 Table 44 Adjacent OUT BUS Pinouts 2 1000 PLINKS connected to the User FPGA PLINKS 0 2 5 7 Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA 2V1000 PIN Connector 2V1000 No PIN No PIN No 56 PPOLK lt 8 gt PP2LK lt 8 gt PPOLK lt 4 gt P N T107 0132 Issue 9 23 05 2003 www nallatech com 137 XtremeDSP Development Kit User Guide Signal Name PPOLK lt 9 gt PA12 E10 PPOLK l
9. PPOLK lt 5 gt PPOLK lt 6 gt PPOLK lt 7 gt PPOLK lt 8 gt PPOLK lt 9 gt PPOLK lt 10 gt PPOLK lt 11 gt mi mm mu 8m ms 6 m ms fm am mr o m F11 E11 10 B10 F10 E10 C5 4 PP2LK lt 0 gt PP2LK lt 1 gt PP2LK lt 2 gt PP2LK lt 3 gt 21 lt 4 gt 21 5 PP2LK 6 PP2LK lt 7 gt PP2LK 8 PP2LK lt 9 gt PP2LK lt 10 gt PP2LK 11 PD 2 PD 3 PD 4 PD5 PD7 PD8 11 12 13 14 NT107 0132 Issue 9 23 05 2003 Table 32 PLINK Pinouts 2 250 PPOLK 0 is connected to a clock GCLK6S on the Virtex ll www nallatech com 131 XtremeDSP Development Kit User Guide DINIE PPOLK 1 is connected to a clock pin G CLK7P on the Virtex ll PP2LK 0 is connected to a clock pin GCLK25 on the Virtex ll PP2LK 1 is connected to a clock pin G CLK3P on the Virtex ll 132 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide 11 4 2 DIME II control and monitoring signals DIME II Specific Pins Dime Ill Connector Signal Name PIN No CONFIG DONE FPGA DONE me CNW DONE Ws fa uu fem KH M Table 33 User FPGA Specific Pinouts 2V250 Dime ll Connector User FPGA 2V250 PIN No PIN CONFIG DONE is driven from the IO ofthe Virtex ll into the base of the transistor to signal that the on board User FPGA has been configured s
10. Section Generated Clock D GEN_CLKD N 7 GCLK7S Consult Pinout Information Section Table 20 Generated Clock Pinouts Generated Clock C GEN GCLK1S Consult Pinout Information Section pin locations for the Generated Clock signals are listed for each FPGA option in the following places For an XC2V250 FPGA see Clock sources available at CLK FPGA on page 134 For an XC2V1000 FPGA see Clock sources available at CLK FPGA on page 140 For an XC2V3000 or XC2V6000 FPGA see Clock sources available at CLK FPGA on page 168 10 6 5 2 External Clock source The BenADDA is designed to provide maximum flexibility W ith this in mind there is a special build option available that allows you to have two external clock input sources However when the option of using both external clocks is chosen the on board oscillator is removed from the BenADDA This 2 external clock source is an MCX connector that is populated on the BenADDA in place of the crystal oscillator The MCX connector is directly connected to the CLK FPGA and either a single ended or differential clock signal can be provided NT107 0132 Issue 9 23 05 2003 www nallatech com 113 XtremeDSP Development Kit User Guide DIME The Clock signal that is provided must be between OV to 3 3V Any deviation outside this range will damage the CLK FPGA Clock Signal Description Signal Name CLK FPGA Pin 2nd External Clock EXT2
11. Table 76 PLINK Pinouts User FPGA 2V 3000 www nallatech com 153 XtremeDSP Development Kit User Guide DIMET PLINKS connected to the User FPGA PLINKS 4 5 6 and 7 Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA C onnector 2V3000FG676 Connector 2V3000FG676 PIN No PIN No PIN No PIN No PPALK 0 SA48 PP6LK 0 SD 48 PPALK 1 SA49 NC PP6LK 1 SD 49 NC PPALK 3 PPOLK 3 us NC W 98 NC _ NC NC 1 1 TF Psa fen mne fsa A s fe jem s ME PP5LK lt 2 gt SB49 PP7LK lt 2 gt SC 49 C16 PP5LK 3 SB51 PP7LK 3 SC51 5 lt 4 gt PP7LK 4 mue ss m _ MI s Mo _ ss n _ mua sm 8 _ Table 77 PLINK Pinouts User FPGA 2V3000 154 www nallatech com NT107 0132 Issue 9 23 05 2003 PETE ete a Developer MEU GHideti 11 7 2 DIME II control and monitoring signals DIME II Specific Pins Dime II Connector Signal Name Dime Il Connector User FPGA PIN No PIN No 2V3000FG676 PIN No CONFIG DONE FPGA DONE PC 40 N 24 N C CONFIG DONE N23 CLKO CLKA PC 24 D13 Table 78 User FPGA Specific Pinouts 2V3000 CONFIG DONE is driven from the IO ofthe Virtex ll into the base of the transistor to signal that the on board User FPGA has been configured successfully User to drive this pin LOW once the FPGA is configured User LEDs Signal Name User FPGA 2V3000FG676 PIN No LED
12. le USB Status LEDs 811 3 ER oh Connector AK Additional PCI Back Adjacent B PCI Control Jacent BUS ontro Plate H eader Configuration LED 50 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI NT107 0132 Issue 9 23 05 2003 www nallatech com XtremeDSP Development Kit User Guide 51 XtremeDSP Development Kit User Guide DIME Hardware Features BenONE PCI Power Specifications BenONE PCI Clock Circuit Resets and LEDs 6 2 BenONE PCI Power Specifications Power specifications on the BenO NE PCI will vary depending on the type of modular power supply that has been populated to power the DIME II module slot these options are discussed further in the following Sections Several events happen when power is applied to the card Firstly each modular power supply is interrogated by the PCIFPGA to ascertain its output characteristics N ext the module is interrogated to ascertain its power requirements All requirements have to be met before power is switched on to the module this prevents inadvertent damage to any module populated on the BenO N E PCI 6 2 1 Modular fixed power supply FPS N allatech offer the fixed power supply option this has reduced output current capability and produces a fixed voltage output This option reduces the flexibility of the BenONE PCI card as only DIME II modules with the same power supply requirements will function Power supplies are conf
13. run the following program autorun exe DWE Xireme DSP Kit 3A Cee HIT Gea Poche Orrez inf murrh W az Lei E VEM Fres Clee Sl sl Eri piiniat Toll Trus F Figure 5 DSP Kit CD Autoplay Menu 1 Click on the first option Install Product FUSE Software 2 The installation process begins It uses a standard installation interface with which most users will be familiar W ork through the dialog boxes filling in details as required until the Finish dialog box is reached 3 It is then recommended to restart the PC at this stage 2 6 Confidence Test In order to verify the correct installation of the software and hardware a simple confidence test can be performed In the W indows Start Menu under Programs anew entry will have been created for FUSE Run the program FUSE gt Software gt FUSE Probe where refers to the distributed version number You will see the GUI shown in Figure 6 If it does not appear correctly make sure the window Is maximised NT107 0132 Issue 9 23 05 2003 www nallatech com 11 XtremeDSP Development Kit User Guide FIAMTETT AN ry 5 FY 5 FY Figure 6 FUSE Probe The simplest way to make sure that the software and hardware has been installed correctly is to open the card in FUSE Probe O pen the cards with the following steps 1 From the Card Control Menu select O pe
14. 1 FPGA Configuration using FU SE GUI 14 9 2 2 FPGA Configuration using D IM EScript 74 9 2 3 FPGA Configuration using the FU SE APls 75 FPGA Application Design 76 9 3 Interfacing to the FPGA 76 9 4 Synthesis and Implementation Settings 77 9 4 1 Synthesis O ptions 77 9 4 2 Implementation O ptions 77 Example Application 1 81 95 Introduction 81 9 6 Functional D escription 81 97 Configuring the ADC to DAC feed through example 82 Example Application 2 86 98 Introduction 86 9 9 Functional Description 06 9 9 1 Creation and Configuration of Sine W ave and Multiplier Components 87 9 9 2 Multiplier Component 90 9 10 Configuring the modulator example 92 Example Application 3 93 9 11 Introduction 93 9 12 Functional description 94 9 13 Running the implementation 95 9 14 Implementation Source 96 NT107 0132 Issue 9 23 05 2003 www nallatech com vil XtremeDSP Development Kit User Guide DIME 9 15 UCF Modification 96 Reference Guide 97 Physical Layout 98 101 BenADDA physical layout top 98 10 2 BenADDA physical layout bottom 99 Hardware Features 100 10 3 Digital to Analogue Converter 100 10 3 1 Architecture 101 10 3 2 PLL Clock Multiplier 101 10 3 3 2 250 FPGA DAC Control Signals 104 10 4 Output Configurations 107 10 4 1 Single Ended DC C oupling Using an O p Amp 107 10 4 2 Differential O utputs using Termination Resistors 107 1043 Clocking 108 10 5 Analogue to D igital Converter 109 10 5 1 ADC Architecture
15. 109 10 5 2 Analogue front end Input 110 10 5 3 ADC Clocking 110 10 6 Clocking the DACs and ADCs CLK FPGA 111 10 6 1 Overview of various Clocking Methods 111 10 6 2 External Clock Source 112 10 6 3 On board Oscillator 112 10 6 4 Generated Clock signals from User FPGA 113 10 655 2 External Clock source 113 10 6 6 Clock feedbacks for De skewing 114 10 6 7 DAC and ADC clocking 114 10 7 ZBT SRAM Memory 115 10 7 1 Hardware Details 115 10 7 2 7 SRAM Clocking 116 10 7 3 ZBT SRAM Clocking Example 116 10 3 User FPGA 117 10 8 1 Overview of User FPGA 117 10 8 2 DIME II Communication busses 118 10 83 DIME II System Clocks 119 10 9 Control and Monitoring Signals 120 10 9 1 BenADDA FPGA Reset 120 10 9 2 JTAG Chain 120 10 9 3 ConfigDONE 121 10 9 4 User LEDs 122 10 10 Temperature Sensor 123 Interfacing 125 11 1 Interfacing via MCX connectors 125 1111 Interfacing to MCX connectors via supplied cable 126 11 2 User lO header Interfacing 126 11 3 Design Partitioning 128 Pinout Information 130 114 XC2V250 FG 456 130 1141 User FPGA to DIME II motherboard communication 130 11 4 2 DIME II control and monitoring signals 133 11 4 3 Clock signals relating to DACs and ADCs 134 11 4 4 Signal Pinouts 135 11 45 ADC Signal Pinouts 135 11 4 6 User IO header 135 115 XC2V1000 FG456 136 Viii www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI NT107 0132 Issue 9 23 05 2003 11 5 1 11 5 2 11 5 3 11 5 4 11 5 5 11 5 6 XtremeDSP Dev
16. 169 XtremeDSP Development Kit User Guide Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No DACT D lt 6 gt AL27 DAC2 D lt 6 gt AN 24 DAC1 D lt 11 gt DAC2 D lt 11 gt Table 111 DACs Signal Pinouts 2V3000 6000 11 8 7 ADC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No ADC1 D lt 3 gt ADC2 D lt 3 gt ADC1 DRY AE15 ADC2 DRY ADC1 OVR AL13 ADC2 OVR Table 112 ADC Signal Pinouts 2V3000 6000 170 www nallatech com NT107 0132 Issue 9 23 05 2003 DEHATEGI EM NES DE Ope it Usen aider 11 8 8 User IO Header Signal Name User FPGA 2V3000 2V6000 PIN No Table 113 User IO Header Pinouts 2V3000 6000 NT107 0132 Issue 9 23 05 2003 www nallatech com 171 XtremeDSP Development Kit User Guide 172 Standard Terms and C onditions GENERAL These Terms and C onditions shall apply to all contracts for goods sold or work done by N allatech Limited hereinafter referred to as the company or Nallatech and purchased by any customer hereinafter referred to as the customer Nallatech Limited trading in the style N allatech the company submits all quotations and price lists and accepts all orders subject to the following conditions of contract which apply to all contracts for goods supplied or work done by them or their employees to the exclusion of all o
17. 2V3000 6000 www nallatech com 161 XtremeDSP Development Kit User Guide DIMET Adjacent OUT Bus User FPGA connections Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V3000 2V6000 Connector 2V3000 2V6000 PIN No PIN No PIN No PIN No A 19 GCLKOP ADJO UT lt 3 gt ADJOUT 35 ADJOUT 10 T28 AB29 ADJOUT 17 ADJOUT 49 ADJOUT 20 26 ADJO UT lt 22 gt V33 AE26 Table 93 Adjacent OUT BUS Pinouts User FPGA 2V3000 6000 PLINKS connected to the User FPGA PLINKS 0 1 2 and 3 Signal Dime ll User FPGA Signal Dime ll User FPGA Name Connector 2V3000 2V6000 Name Connector 2V3000 2V6000 PIN No PIN No PIN No PIN No 162 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Signal Dime ll User FPGA Signal Dime ll User FPGA Connector 2V3000 2V6000 Name Connector 2V3000 2V6000 PIN No PIN No PIN No PIN No PPOLK 11 PP2LK 11 1 0 PP3LK lt 0 gt PD 15 PP1LK lt 4 gt PP3LK lt 4 gt PD20 Table 94 PLINK Pinouts User FPGA 2V 3000 6000 PP1LK 1 PP3LK 1 PD 16 11 lt 2 gt 17 PP3LK lt 2 gt PD 17 PP1LK 3 18 PP3LK 3 PD 18 L34 33 1 PLINKS connected to the User FPGA PLINKS 4 5 7 Signal Dime ll User FPGA Signal Dime ll User FPGA Connector 2V3000 2V6000 Name Connector 2V3000 2V6000 PIN No PIN No PIN No PIN No PPALK 9 5 58
18. 3 3 Volts Supply Signal Ground TCK DIMEJTAG TCK Signal 4 N ot connected do not use 9 TDO DIMEJTAG Signal DIMEJTAG TDI Signal TRST DIMEJTAG TRST Signal TMS DIME JTAG TMS Signal Table 5 uP JTAG Connector pinouts 38 Www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEN XtremeDSP Development Kit User Guide Clock Configuration 5 6 BenO N E PCI clocking description Configuring clock sources Using external clocks System level clocking General Description The BenO NE PCI has a comprehensive and flexible clock management system The features available are as follows Two on board clocks for general use Two on board programmable clock sources Single Fixed oscillator socket on board clock source User clock input connector for on board use The PCI clock The clock nets on the BenO NE PCI have been designed to eliminate clock skew at the FPGA destination using clock nets of the same length between the on board clocks and the DIME II module slot 5 7 4 PT a T te EE i VE f re e E LEE m I I 1 Input Socket Fixed O scillator Programmable Connector not shown Socket Clock Drivers On board clocks The BenO NE PCI has two clocks A and B which can be used throughout the board The fixed oscillator socket is fitted with a 50MH z un
19. 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 XtremeDSP Development Kit User Guide List of Figures Hardware features relating to connection and installation Kit Case and C ontents BenADDA BenON E connectivity FUSE CD Autoplay Menu DSP Kit CD Autoplay Menu FUSE Probe Locate Cards prompt D etected Cards FUSE Probe Tool with O pen Cards Power LEDs BenO NE PCI Functional Diagram 5V top and 3 3V bottom signalling PCI Connectors LEDs indicating USB Successful Initialisation BenO NE PCI JTAG Configuration within DIME Software Example configuration 1 Diagram for FPGA Configuration Example 1 Example code to configure FPGAs in Example Configuration 2 DIME JTAG Chain ALT JTAG Connector J13 DIME JTAG Chain uP JTAG Connector X tremeD SP Development Kit Design Partitioning Implementation with PCI or USB to User FPGA Interface Core Implementation with own communications mechanism Single Read Transfer Burst Read Transfer Burst W rite Transfer Programmable Power Supplies on the BenONE PCI Programmable Power Supplies on the BenO NE PCI BenO NE PCI Clock Circuit BenO NE PCI Reset Circuit BenADDA BenADDA functional diagram Hardware features for installation Interfacing to User FPGA Implementation Configuration Se
20. Bus User FPGA connections Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V2000FG676 Connector 2V2000FG676 PIN No PIN No PIN No PIN ADJO UT lt 3 gt PD32 E23 ADJO UT lt 35 gt PD 68 M22 Q ADJOUT 17 ADJOUT 49 m L21 L26 5 Table 57 Adjacent OUT BUS Pinouts User FPGA 2V2000 PLINKS connected to the User FPGA PLINKS 1 2 and 3 Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA C onnector 2V2000FG676 Connector 2V2000FG676 PIN No PIN No PIN No PIN No rakas m6 144 www nallatech com 107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V2000FG676 Connector 2V2000FG676 PIN No PIN No PIN No PIN No gt H5 _ E 12 PPOLK lt 10 gt PA13 PP2LK 10 PD 13 PPOLK lt 11 gt PA14 E6 PP2LK lt 11 gt PD 14 NC IEEE qms NG fm mn NC Peas mu fa _ NC 15 19 20 20 NC NC NC 5 21 PP3LK 5 PD21 11 6 PA22 PP3LK 6 PD 22 NC N 11 10 PA26 PP3LK lt 10 gt PD 26 11 lt 11 gt 27 PP3LK lt 11 gt PD27 Table 58 PLINK Pinouts User FPGA 2V2000 m NC PLINKS connected to the User FPGA PLINKS 4 5 6 and 7 Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2v2000FG 676 Connector 2v2000FG 67
21. Figure 17 the header to access this chain is shown in Figure 18 and the header pinout is detailed in T able 4 PCI FPGA Drives JTAG a CPLD PSU Controller DIME JTAG DIME JTAG Chain Header J13 Drives JTAG o A lt LLI FF F F F F F F F iF a dF d F P dF iB PCI FPGA PCI FPGA DIME II Slot 0 Configuration Configuration PROM 1 PROM 0 Figure 17 DIME JTAG Chain penmi Figure 18 ALT JTAG Connector J13 Name Description 3 3 Volts Supply JE N ot connected do not use TCK ALT JTAG TCK Signal 1 2 3 4 36 www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide Pin Name Description N C N ot connected do not use 6 ALT TDI ALT JTAG TDI Signal a TRST ALT JTAG TRST Signal eee ALT JTAG TMS Signal Table 4 ALT JTAG header pinouts programming of either the PSU Controller or PCI Boot proms on your BenONE PCI Care must be taken when using this method of programming your module Inadvertent could render it inoperable or extreme cases damage to your module could occur 5 5 FPGA Configuration using uP JTAG Chain The uP JTAG chain facilitates the configuration of devices on DIME II modules hosted on the BenO N E PCI It should be noted that not all DIME II modules will necessarily support the uP JTAG chain please refer to the mo
22. Figure 3 BenADDA BenONE connectivity The connectivity to the FPGA on the specific resources such as FPGAs on the DIME II module will depend upon the DIME II module itself In the case of the XtremeD SP development kit the available 1 0 from the User FPGA on the BenADDA is defined in Table 1 N ote that certain configurations of the BenADDA DIME II module provide greater I O resources than can be supported on the BenO N E itself This is due to the fact that the BenO N E can be fitted to other N allatech D IME II carrier cards that have onboard resources with sufficient pin resources to make use of these additional bus signals Communication Bus 2V250 2V1000 FG456 2V2000 2V3000 2V3000 2V8000 FG456 FG 676 FF1152 C omm P Link 2 12 bits 12 bits 12 bits 12 bits Table 1 Communication Bus Summary 8 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEN XtremeDSP Development Kit User Guide In addition certain buses are in part used to provide a communications channel between the Interface FPGA Spartan ll and the DIME II module site in effect the User FPGA on the BenADDA On the BenO part of the Local Bus and the ADJO UT bus are used for this purpose 2 5 Installation Guide The installation process is essentially split into 3 stages 1 Install the N allatech FUSE environment software provided on the FUSE CD 2 Connecting the hardware to the PC and installing the device driver for the BenO N E when detected under
23. II modules such as the BenAD DA there are also additional accessories The StrathLED is an add on module that can be plugged into the adjacent bus header J10 to provide an array of LEDs that can be used for display purposes NT107 0132 Issue 9 23 05 2003 www nallatech com 57 XtremeDSP Development Kit User Guide DIMET Pin out Information In this Section External board connections 6 8 External Connectors 6 8 1 Standalone Power Connector This is a standard 8 way mini DIN connector Supply Pin Looking at connector Voltage e _ 3 6 8 2 Disk Drive Style Power C onnector If you are developing very large designs that may require high current ratings N allatech would advise the use of this connector to increase the power rating You will see however that this connector is limited to supplying only the positive supplies Supply Pin Looking at connector Voltage 58 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide If the XtremeD SP D evelopment Kit is located in a PCI slot then this connector if used must be connected to the same ATX power supply that is powering the slot Alternatively if the XtremeD SP D evelopment Kit is operating as a standalone unit this can be connected to any external source however ensure that if a power supply is also connected to the Mini DIN connector that it to is not attempting to power the 5V and 12V rails 6 8 3
24. Issue 9 23 05 2003 www nallatech com iii XtremeDSP Development Kit User Guide DIME Document Name XtremeD SP D evelopment Kit User Guide Document Number N 107 0132 Issue Number 9 Date of Issue 21 05 2003 Revision History Date Issue Revision Number 14 05 02 30 05 02 Initial release Pinout table fixes inclusion of information on Interface FPGA to User FPGA Communications 28 06 02 Pinout table fixes 15 07 02 25 08 02 Update to documentation various 26 09 02 Section 5 11 added Interface FPGA to User FPGA information added 04 10 02 Updated documentation 24 02 03 Clocking pinouts for DACs and ADCs updated in BenADDA section power supplies LED table updated in BenO NE section 21 05 03 Bg U pdate to FPS power calculation T rademark Information Pinout table fixes additional example application The Nallatech logo the DIME logo the DIME II logo FUSE Field U pgradeable Systems Environment DIME DIME II and the Bally Ben and Strath product name prefixes are all Trademarks of N allatech Limited The Algorithms to Hardware Company Making Hardware Soft FPGA C entric Systems the only logical solution and software defined systems are Service Marks of N allatech Limited All products or brand names mentioned herein are used for identification purposes only and are trademarks registered trademarks or service marks of their respective owners Copyright Information
25. PLink Bus Header J11 This header is connected to PLink0 on the DIME II module slot Header Pin DIME II Module Number C onnector md 6 PPOLK lt 5 gt 8 PPOLK lt T gt PM 9 PPOLK 10 PPOLK 11 6 8 4 Adjacent Bus Header 10 This header is a 28 bit general purpose bus and is connected to the Adjacent IN Bus on the DIM E II module slot The StrathLED is an optional module that can be plugged into this header to provide an array of LEDs that can be used for display purposes Header Pin Name DIME II Module Connector N T107 0132 Issue 9 23 05 2003 www nallatech com 59 XtremeDSP Development Kit User Guide DIME Header Pin Name DIME II Number Module Connector ADJIN lt 1 gt PA30 19 ADJIN lt 18 gt 30 N A ic ic ic N Table 12 Adjacent Bus Header 6 8 5 Fan Jumpers Table 5 lists all the necessary jumper configurations for each fan Note Each fan jumper is a 2 pin header one pin supplies 5 volts to the fan and the other provides a ground The silkscreen on the PCB for each fan jumper is white box with a corner missing Pin 1 is always nearest the missing corner Fan Jumper Name Description Supplies power to a 5 Volt Cooling Fan J7 Pin 1 Ground 1 2 Pin 2 5 Volts Supplies power to a 5 Volt Cooling Fan Pin 1 Ground Pin 2 5 Volts Table 13 Fan Jumpers 60 www nallatech com NT107 0132 Issue 9 23 05 2003 eR ty Oen Hide it
26. PP6LK lt 9 gt SD 58 AF28 PP4LK lt 10 gt SA59 PP6LK lt 10 gt SD59 AH 29 PP4LK lt 11 gt SA60 PP6LK lt 11 gt 5060 AG29 PP5LK 0 SB47 H16 GCLKOS PP7LK 0 SC 47 J18 GCLK 65 PP5LK 1 SB48 H17 GCLK1P PP7LK 1 SC48 K18 GCLK7P 2 NT107 0132 Issue 9 23 05 2003 www nallatech com 163 XtremeDSP Development Kit User Guide DIMET C onnector 2V3000 2V6000 Name Connector 2V3000 2V6000 Signal Dime ll User FPGA Signal Dime ll User FPGA PIN No PIN No PIN No PIN No PP5LK lt 7 gt SB55 PP7LK lt 7 gt SC55 AK32 Table 95 PLINK Pinouts User FPGA 2V3000 6000 General Purpose Signal Dime ll User FPGA Signal Dime ll User FPGA Name Connector 2V3000 2V6000 Name Connector 2V3000 2V6000 PIN No PIN No PIN No PIN No Bo E Table 96 GP IO Pinouts User FPGA 2V3000 6000 L26 33 i E34 GP 10 lt 5 gt PC67 3 GP 10 16 E33 3 K24 25 164 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide 11 8 2 DIME II control and monitoring signals DIME II Specific Pins Dime II Connector Signal Name Dime II Connector User FPGA PIN No PIN No 2V3000 2V6000 PIN No CONFIG DONE FPGA DONE PC 40 31 N C CONFIG DONE F32 CLKO CLKA PC 24 E17 GCLK3P Table 97 User FPGA Specific Pinouts 2V3000 6000 CONFIG DONE is driven from the IO ofthe Virtex Il into the base of the transistor to signal that the on board User FPGA has
27. Software Installation NT107 0132 Issue 9 23 05 2003 www nallatech com 21 XtremeDSP Development Kit User Guide DINIE Hardware Installation Hardware requirements Hardware installation features Hardware installation instructions for both PCI and U SB 4 1 BenONE PCI host PC requirements Pentium PII 233 32MB RAM IGB Hard Disk Windows 95 98 Me N T 2000 X P operating system or Red Hat Linux 6 2 or above 4 1 1 PCI C onnection PCI defines two types of signalling environment which operate at either 3 3v or 5v The N E PCI is a universal card and thus can be used in either signalling environment i Eji BELL E E p T E BEIDE LEGE ELT LEI ILI 44471212144 w a E a back bi id bl ed n He Df Ded guzzunmnruung PUUTTUU UJT DOG GOL DL a Le LG UL a LI Le LE LU g a ARAB AES LEEELUELL 11 1 1 LEREN OLEOLE AL EIL Figure 11 5V top and 3 3V bottom signalling PCI Connectors If you wish to install the BenO NE PCI card in a PC using a PCI slot please note that in the default configuration provided with the XtremeD SP D evelopment Kit User Guide the BenO N E will only function correctly in a 5V PCI Signalling environment This is because one of the X C 1800 proms is programmed with a 5VIO PCI bitstream and the
28. This document which is supplied in confidence is the copyright property of N allatech Limited N either the whole nor any extract may be disclosed loaned copied or used for any purpose other than those purposes for which written permission was given at the time of release Application for any uplifting or relaxation of these restrictions must be made in writing to Nallatech Limited who may at their discretion refuse such application or give it qualified or absolute approval Copyright 1993 2003 Nallatech Limited All Rights Reserved iV www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Contents INTRODUCTION 1 Preface 3 1 1 About this U ser G uide 3 1 2 User Guide Format 3 1 3 References 4 1 4 Abbreviations 4 Getting Started 5 2 1 O verview 5 2 2 5 Development Kit Requirements 5 2 3 Unpacking Your Starter Kit 5 2 3 1 H ardware Installation Features 5 2 3 2 X tremeD SP Development Kit Contents 6 2 3 3 Specifications 7 24 BenONE BenADDA connectivity 8 2 5 Installation Guide 9 25 1 FUSE Software Installation 9 2 5 2 Hardware Driver Installation 10 25 3 BenO BenADDA FUSE Supporting Software 11 2 6 Confidence T est 11 2 1 Support 14 2 1 1 Document References 14 2 1 2 FUSE CD Structure 14 2 1 3 XtremeD SP Development Kit CD Structure 14 2 14 Technical Support References 15 BENONE 17 BenONE Overview 19 3 1 D escription 19 3 2 Key Features 19 3 3 Functiona
29. ZBT CI8 Data ZBTA FB IN E18 User FPGA This net is the same physical length as the ZBT signal to the ZBT Memory This KR allows for de skewing Figure 70 ZBT SRAM Clocking Example BANK A The above arrangement ensures that the device is triggered in phase See Table 22 for pinout details for Bank A s Clocks 108 User FPGA 10 8 1 Overview of User FPGA The BenADDA module utilises the powerful processing capability of a Xilinx Virtex II FPGA to support various FPGA sizes and speed grades T his provides the flexibility to choose the most appropriate FPGA to meet processing requirements Figure 71 outlines all the possible DIME II communications NT107 0132 Issue 9 23 05 2003 www nallatech com 117 XtremeDSP Development Kit User Guide DIME 118 Analogue O utput Analogue Input DC Coupled OR Differential or Directly Coupled single ended External Clock re T gt gt gt 2 2 gt lt m m m r r n 00 ON MODULE XILINX VIRTEX II X C2V250 X C2V6000 DIME II MOTHERBOARD DIME II MOTHERBOARD TO Figure 71 User FPGA interfacing O verview Remember that not all DIME II communication busses are available all versions of the BenADDA The following Section details the purpose of these communication busses 10 8 2 DIME II Communication busses To support the large volume of communications between DIME II modules and DIME II motherboards the fol
30. ZBT CKEI ZBT CSI lt 0 gt A18 ZBT CSI lt 1 gt A19 ZBT Oel A15 ZBT Wel A14 Table 63 ZBT Clock and Control Signals Pinouts 2 2000 ZBT Address Signals Bank Signal Name User FPGA Signal Name User FPGA 2V2000FG676 PIN 2V2000FG676 PIN No No ZA mw fam 6 _ ZBT A lt 4 gt D9 ZBT A lt 15 gt A9 ras 8 was mw Table 64 ZBT Address Signals Pinouts 2V 2000 T hese are Expansion PIN s and may not be supported by the ZBT memory nly use the above address pins if the onboard ZBT memory is in the following list ZBT A lt 18 gt use if ZBT Memory is 16Mb ZBT A lt 19 gt use if ZBT Memory is 32Mb ZBT A 20 use if ZBT Memory is 64Mb ZBT A 20 use if ZBT Memory is 128Mb ZBT Data Signals Bank Signal Name User FPGA Signal Name User FPGA 2V2000FG676 PIN 2V2000FG676 PIN No No _ N T107 0132 Issue 9 23 05 2003 www nallatech com 147 XtremeDSP Development Kit User Guide Signal Name ZBT D lt 4 gt DIMETI User FPGA Signal Name User FPGA 2V2000FG676 PIN 2V2000FG676 PIN No No ZBT D lt 5 gt ZBT D lt 21 gt NC ZBT D lt 6 gt ZBT D lt 22 gt NC C DE ERES NC ZBT D 9 21 20 ZBT D lt 25 gt ZBT D lt 11 gt ZBT D lt 27 gt NC ZBT D lt 12 gt ZBT_D lt 28 gt ZBT_D lt 13 gt B23 ZBT_D lt 14 gt ZBT_D lt 30 gt NC Table 65 ZBT Data Signals Pinouts Bank 2V2000 ZBT Parity Bits Bank Signal Name ZBT_P
31. clocks are e CLKA available programmable oscillator on the BenON E e CLKB available programmable oscillator on the BenO NE e CLKC connected to a socket to support a crystal oscillator Please note that no oscillator is supplied and this option on the BenO N E is primarily intended to allow users fit a specific crystal if needed For full details of the generation of these clock signals prior to use on the module site consult the appropriate motherboard User Guide NT107 0132 Issue 9 23 05 2003 www nallatech com 119 XtremeDSP Development Kit User Guide DIME 10 9 Control and Monitoring Signals The BenADDA produces a range of signals that allow the user to control and monitor the on board module behaviour Reset The Reset signal is used to clear the memory of both on board FPGAs The JTAG chain is used for test and configuration purposes Config DONE This signal is related to the configuration of the on board FPGAs LEDs There two tri colour LEDs on the BenADDA that are free to be used for the chosen application Temperature Sensor Used to monitor the Temperature of the User FPGA 10 9 1 BenADDA FPGA Reset The BenADDA has a RESET I signal connected directly to both on board FPGAs RESET I is driven by the DIME II motherboard and is available through the FUSE Software This signal is active LOW will reset the on board FPGAs when a LOW is applied The pin locations
32. data bus REN W EN This signal is a read write enable signal W hen this signal is LO W if the R W signal is HIGH data is on the bus ready to be written to the Interface FPGA Ifthe signal is LOW and R W is LOW then data will be driven onto the data bus from the Interface FPGA on the next clock edge W hen this signal is HIGH there should be no data on the bus Lastly there is the data bus that is used to transfer data between the Interface FPGA and the User FPGA This bus is called ADIO and is a 32 bit bi directional bus that can be driven by both the Interface FPGA and the User FPGA The general functionality is similar to that of FIFOs The EMPTY and BUSY signals act similarly to FIFO EMPTY and FIFO FULL signals R W and REN W EN signals combine to give the REN and W EN signals of a FIFO The clock used for the Interface FPGA to User FPGA communications is always D SPC LK Reading from Interface FPGA to User FPGA Reading from the Interface FPGA is similar to reading from a FIFO The EMPTY signal goes LOW to indicate that there s data to be read The FIFO whose data is read from on the Interface FPGA is a First W ord Fall Through with a latency of one clock cycle W hen reading from the Interface FPGA the user must ensure that the read enable is not active until at least one clock after the EMPTY signal goes LOW The read enable should go inactive immediately after the EMPTY signal goes HIGH although no data
33. for this RESET 1 signal are listed for each FPGA option in the following places For an XC2V250 FPGA see Section 11 4 2 DIME II control and monitoring signals on page 133 For an XC2V250 FPGA see Section 11 5 2 DIME II control and monitoring signals on page 139 For XC2V3000 or XC2V6000 FPGA see Section 11 8 2 DIME II control and monitoring signals on page 165 The pin locations are also listed in the UCF on the BenADDA installation CD 10 9 2 Chain DIME II modules have JTAG based Plug and Play PnP facility to enable auto detection of the modules present in a system Each DIME II module has a unique ID number The BenADDA IDs are listed in Table 24 ID Numker Hex Description 30001033 User FPGA XC2V250 FG 456 CLK FPGA 2 80 30088033 User FPGA XC2V1000 FG456 CLK FPGA XC 2V80 30555033 User FPGA XC 2V6000 FF1152 CLK FPGA XC 2V80 Table 24 BenADDA Assigned MDF Code Listing 30044033 User FPGA XC 2V3000 FF1152 CLK FPGA XC 2V80 The physical order of the devices in the JTAG chain illustrated in Figure 72 is 1 User FPGA 2 CLK FPGA 120 Www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide To establish the module order in the JTAG chain N allatech s FU SE System Software is deployed The software initially scans the chain to identify and index the devices on the BenADDA module The device nearest the TDO output of the m
34. is applied to the input of a 5 bit coarse ADC ADC1 The digital output of ADC 1 is fed into the 5 bit DAC1 The output from the DAC1 is subtracted from the delayed analogue signal at the input of TH3 to generate a first residue signal The purpose of TH2 is to provide a pipeline delay to compensate for the digital delay of ADC 1 This first residue signal is then applied to the second conversion stage Again a similar process is achieved through this stage which finally leads onto obtaining a second residue signal that is applied to a third 6 bit ADC Finally the digital outputs of ADC1 ADC2 and ADC3 are added together and corrected in the digital error correction logic to generate the final output 10 5 2 Analogue front end Input The BenADDA has been designed to take either single ended or differential analogue inputs This feature is a build option and is specified at the time of ordering The analogue input signal is dc coupled through a differential op amp AD 8138 which is fed into the AD 6644 The op amp has been configured to support either single ended or differential inputs and will always output a differential signal This means that all data will be input to the AD 6644 differentially which helps to reduce noise induced on the input signal The BenADDA has also been designed with a 3 order filter on the front end of the AD6644 Again this filter helps to reduce the overall noise induced on the input signal thereby improving the reso
35. lt 0 gt 11 6 4 Table 66 ZBT Parity Bits Pinouts Bank 2V2000 User FPGA Signal Name User FPGA 2V2000FG676 2V2000FG676 PIN No No Clock signals relating to DACs andADCs Clock sources arriving at CLK FPGA Signal Name CLK FPGA 2V80 Pin User FPGA No 2V2000FG676 PIN Signal Description Op Amp GCLK6S N a External CLK source via Op_Amp N a CLK Op Ampl B6 C6 GCLK7P Complement of External CLK source via Op Amp EXT CLK B8 GCLK 05 N a External CLK source straight to CLK FPGA EXT CLKI 8 GCLK1P N a Complement of External CLK source straight to CLK FPGA LVTTL Clock O scillator GEN CLKA K7 GCLKOP AB12 Generated Clock Osc CLK M6 GCLK4P GEN CLKC N8 GCLK1S 12 G enerated Clock GEN CLKB AA 12 Generated Clock D 2nd External Clock Complement of 2nd External Clock M7 GCLK6P Generated Clock B GEN CLKD N 7 GCLK7S EXT2 CLK D7 GCLK5P 2 CLKI A6 GCLK4S N a Table 67 Clock Signals at CLK FPGA 2V2000 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide Clock Feedback signals CLK FPGA 2V80 Pin User FPGA No 2V2000FG676 PIN No CLK1 FB AB14 Feedback to User FPGA CLK3 FB AA14 Feedback to User FPGA CLK2 FB Signal Name Signal Description Table 68 Clock Feedback Signals 2V2000 Clocking Pinouts for DACs and ADCs Signal Nam
36. made by the company shall occur at the time of delivery The title however shall not pass to the buyer until payment has been received in full by the company And no other sums whatever shall be due from the customer to N allatech If the customer who shall in such case act on his own account and not as agent for N allatech shall sell the goods prior to making payment in full for them the beneficial entitlement of N allatech therein shall attach to the proceeds of such sale or to the claim for such proceeds The customer shall store any goods owned by N allatech in such a way that they are clearly identifiable as Nallatech s property and shall maintain records of them identifying them as N allatech s property The customer will allow N allatech to inspect these records and the goods themselves upon request In the event of failure by the customer to pay any part of the price of the goods in addition to any other remedies available to N allatech under these terms and conditions or otherwise N allatech shall be entitled to repossess the goods The customer will assist and allow N allatech to repossess the goods as aforesaid and for this purpose admit or procure the admission of N allatech or its employees and agents to the premises in which the goods are situated INTELLECTUAL PROPERTY The buyer agrees to preserve the Intellectual Property Rights IPR of the company at all times and that no contract for supply of goods involves loss o
37. onverter DAC Digital to Analogue Converter DIME D SP and Image Processing Modules for Enhanced FPGAs DLL D elay Locked Loop ESD Electro Static D ischarge FPGA Field Programmable Gate Array ILA X ilinx Integrated Logic Analyser PCI Peripheral Component Interconnect RAM Random Access Memory VHDL VHSIC Very High Speed IC Hardware Description Language ZBT Zero Bus Turnaround www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide Section 2 Getting Started 2 1 Overview XtremeD SP D evelopment Kit serves as an ideal development platform for Virtex Il and provides an entry into the scalable DIME II systems available from N allatech Its dual channel high performance ADCs and DACs as well as the user programmable Virtex Il device are ideal to implement high performance signal processing applications such as Software D efined Radio 3G W ireless N etworking HDTV or Video Imaging This G etting Started Guide covers the installation of the N allatech hardware and software components that are provided in the DIME II XtremeD SP kit This document details how to connect your DIME II XtremeD SP kit to your PC using the supplied U SB cable and the driver and software installation process that follows The hardware portion ofthe kit consists of a BenO N E PCI motherboard DIME II carrier card and a BenADDA DIME II module that is plugged into the available D IME II slot on the Ben
38. other PRO M that can contain the 3 3VIO PCI bitstream has been used for the USB bitstream 22 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETT XtremeDSP Development Kit User Guide 4 12 USB Connection If you will be using the USB connection to connect the BenO NE PCI to a host PC you will require in addition to the above minimum requirements USB v1 1 compatible port W indows NT or earlier versions of W in95 do not support USB oO Please note Although Linux supports USB at present N allatech do not support this option 4 2 Hardware Features procedures must be observed during the handling and installation of the BenO N E WD The BenO NE is an Electro Static Discharge ESD sensitive device ESD handling PCI card 4 3 PCI Installation 1 Ensure the PC you are using has the power switched off prior to installation 2 Having removed the PC cover locate a free PCI slot for the BenO NE PCI 3 Fitthe BenONE PCI into the PCI slot you have selected and push down firmly 4 Fitthe fixing screw to secure the backplate of the BenO N E PCI to the chassis of the PC 5 The PC power can then be switched on NT107 0132 Issue 9 23 05 2003 www nallatech com 23 XtremeDSP Development Kit User Guide DIMEAI 6 As a confidence test that the BenO NE PCI is correctly installed the power Status LED and PCl Control FPGA configuration LED s illuminate to indicate the card has configured correctly 7 On
39. pre designed GUI For users who require additional functionality and wish to have their own software front end the DIME Software Library provides functions for use in application programs These functions include FPGA configuration reset clock speed setting and data transfer Interface COMM General Bus Signal Name Dime ll Connector PB7 N T107 0132 Issue 9 23 05 2003 www nallatech com 41 XtremeDSP Development Kit User Guide DIMET Interface COMM General Bus Signal Name Dime ll Connector Signal PIN No ADIO 12 15 ADIO lt 17 gt LBUS lt 17 gt PB20 ADIO lt 18 gt LBU S lt 18 gt PB21 ADIO lt 19 gt PB22 ADI0 lt 20 gt PB24 ADIO 21 PB25 ADIO 23 PB27 ADIO 24 PB28 ADIO 25 PB29 ADIO 26 PB30 ADIO 28 PB33 ADIO 29 PB34 ADIO 30 PB35 ADIO 31 PB36 AS DSI ADJO UT 3 PD 32 W EN I ADJO UT lt 4 gt PD 33 INTI ADJOUT lt 5 gt PD34 RSTI ADJO UT lt 6 gt PD 35 Table 6 Interface FPGA to DIME II Slot Also DSP should be connected to CLK 1 sometimes referred to as CLKB Interface COMM General Bus Signal Name Dime Ill Connector PIN No Signal DSP PC31 Table 7 Interface Clock to DIME II 5 11 Interface Communications Bus The Interface Comms Bus is an important communications channel as it provides a path for data communication between the User FPGA the Interface PCI or USB FPGA and onto the host PC The Interface C omms bus
40. supplied in the folder lt C D RO M Documentation FU SE FUSE CD Structure The structure of the supplied FUSE CD takes the following format 2 7 3 Application Notes contains applications notes general to FUSE with some specific card examples D IMEScript contains further information and source on DIM EScript Documentation contains FUSE non card specific documentation as noted in section 2 7 1 FUSE API Examples Software XtremeDSP Development Kit CD Structure The structure of the supplied XtremeD SP D evelopment kit takes the following format Documentation contains documentation in the form of Adobe PDF documents Drivers contains driver files for use under various operating systems Examples provides examples in the form of VHDL source and pre generated bitfiles UCFs contains UCF User Constraint Files for the user FPGA provided on the BenADDA module Application N otes www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide 2 1 4 Technical Support References e Xilinx support available on the internet at http support xilinx com e Nalatech DSP Kit support lounge Access to this lounge is available on establishment of a maintenance agreement This lounge provides access to Nallatech software updates and relevant application notes as they become available NT107 0132 Issue 9 23 05 2003 www nallatech com 15 XtremeDSP Development Kit User Gui
41. words after the BUSY signal is asserted two further data samples can be written to the Interface FPGA NT107 0132 Issue 9 23 05 2003 www nallatech com 45 XtremeDSP Development Kit User Guide DINEAI The diagram in Figure 26 shows a Burst W rite function in operation and also demonstrates the maximum data over run of 2 Figure 26 Burst W rite Transfer Timing Information The information in the table below provides the timing information required to write the User s Constraints File U CF for implementing a design into an FPGA Signal In Ou Details t EMPTY Ons before clock Ons before clock AS D S 19ns before clock RD W R 11ns before clock REN W EN 11ns before clock ADIO 5ns before clock ADIO 12 5ns before clock Table 8 Timing Information Timing specifications should be written into the UCF as a N ET name FFSET spec specification in other words NET EMPTY OFFSET 9ns BEFORE DSPCLK Other signals There are two other signals between the User FPGA and the Interface FPGA These are RST and IN T RST This signal is driven by the PCI or USB FPGA Interface and be used as a global reset within the User FPGA device INT This signal is driven by the User FPGA and can be used to signal an interrupt to the Interface FPGA and cause a PCI interrupt Interface FPGA to User FPGA Communications From A Software Perspective W hen writing software for the X tremeD SP D evelopment Kit
42. 000 FPGA see Section 11 5 2 DIME II control and monitoring signals on page 139 For an XC2V3000 or XC 2V6000 FPGA see Section 11 8 2 DIME II control and monitoring Signals on page 165 10 9 4 User LEDs The BenAD DA has two LEDs which can be used for specific design purposes such as displaying status 122 www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide User LED D2 i hare oe iud 5 User LED D1 Figure 74 User LEDs location X C2V250 2V 1000 version shown The LEDs are illuminated when the corresponding pin is logic 0 otherwise the LED is not illuminated Active LOW The LEDs used on the BenADDA are Tri Colour each LED displays a total of three different colours meaning that each LED can act as three individual LEDs Each LED has a RED and GREEN diode inside their chip Applying logic 0 to either C athode will cause that colour to illuminate and applying logic 0 to both Cathodes green and red will cause a third colour yellow to illuminate Signal Description User LED Signal Name User FPGA Pin Green Diode for LED 2 D 2 LED2 Green Consult Pinout Information Section Red Diode for LED2 D2 LED2 Red Consult Pinout Information Section Green Diode for LED1 D 1 LED1 Green Consult Pinout Information Section Red Diode for LED 1 D1 LED1 Red Consult Pinout Information Section Table 25 LED signals This refers to the silksc
43. 07 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Signal Name User FPGA Signal Name User FPGA 2V3000FG676 PIN 2V3000FG676 PIN No No ZBT D lt 13 gt ZBT D lt 29 gt ZBT D lt 14 gt B22 ZBT D lt 30 gt NC ZBT D lt 15 gt B21 ZBT D lt 31 gt Table 83 ZBT Data Signals Pinouts Bank ZBT Parity Bits Bank Signal Name User FPGA Signal Name User FPGA 2V3000FG676 PIN 2V3000FG676 PIN No No ZBT lt 1 gt NT107 0132 Issue 9 23 05 2003 Table 84 ZBT Parity Bits Pinouts Bank www nallatech com 157 XtremeDSP Development Kit User Guide DIMET 11 7 4 Clock signals relating to DACs andADCs Clock sources arriving at CLK FPGA Signal Name CLK FPGA 2V80 Pin User FPGA Signal Description No 2V3000FG676 PIN No Op Amp B6 GCLK6S N a External CLK source via Op_Amp Op Ampl C6 GCLK7P N a Complement of External CLK source via Op Amp EXT CLK B8 GCLK 05 N a External CLK source straight to CLK FPGA EXT CLKI 8 GCLK1P C omplement of External CLK source straight to CLK FPGA Ti GEN CLKD 7 6 75 12 G enerated Clock 7 N EXT2 CLK D7 GCLK5P 2nd External Clock EXT2 CLKI GCLK4S N a Complement of 2nd External Clock Table 85 Clock Signals at CLK FPGA Clock Feedback signals Signal Name CLK FPGA 2V80 Pin User FPGA Signal Description No 2V3000FG676 PIN No CLK1 FB AB14 Feedback to User FPGA CLK3 FB CLK
44. 132 Issue 9 23 05 2003 www nallatech com 13 XtremeDSP Development Kit User Guide 2 7 2 7 1 2 7 2 DIMETI Support There are several other sources of information on using the N allatech hardware and FUSE software These are included on the CD in the documentation folder but may also be installed onto the local machine as part of the installation process Document References NT107 0068V2 FUSE System Software User Guide This document is intended to give detailed instructions on how to use N allatech s FUSE Field Upgradeable Systems Environment Software in particular the FUSE Probe tool This user Guide is included on the FUSE CD supplied in the folder lt C DRO M D ocumentation FU SE NT 107 0068 FUSE C C Developers Guide O This developers guide provides detailed information on installing and using the FUSE Field U pgradeable Systems Environment C C API The main focus of the guide is to provide information that allows the user to become acquainted with the FU SE and the functionality that it provides This user Guide is included on the FUSE CD supplied in the folder lt C D RO M gt D ocumentatio n FU SE NT107 0103 DIMEScript User Guide O This guide provides information on the use of a script language called D IM EScript that is installed with FUSE This is a simple yet powerful scripting tool that can be invoked from within FUSE Probe This User Guide is included on the FUSE CD
45. 2 FB Table 86 Clock Feedback Signals Clocking Pinouts for DACs and ADCs Signal Name CLK FPGA 2V80 Pin No ADC CLKA E4 ADC CLKAI D1 ADC CLKB G1 ADC CLKBI F1 DAC CLKA D13 DAC CLKAI D 12 DAC CLKB 510 DAC CLKBI F12 Table 87 Clocking Pinouts for DACs and ADCs 11 7 5 DAC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000FG676 PIN 2V3000FG676 PIN No No 158 www nallatech com 107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000FG676 2v3000FG 676 PIN No No DAC1 D 0 DAC2 D 0 AD21 gt DAC1 D lt 5 gt T19 DAC2 D lt 5 gt DAC1 D lt 13 gt DAC2 D lt 13 gt ru ss DAC1 PLLLOCK DAC2 PLLLOCK AB16 Table 88 DACs Signal Pinouts 11 7 6 ADC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000FG676 PIN 2V3000FG676 PIN No Y16 ADC1 OVR AA16 ADC2 OVR Table 89 ADC Signal Pinouts N T107 0132 Issue 9 23 05 2003 www nallatech com 159 XtremeDSP Development Kit User Guide DIMET 11 7 7 User IO Header Signal Name User FPGA 2V3000FG676 PIN No User 10 1 AC10 User 10 2 AD10 Table 90 User IO Header Pinouts 118 XC2V3000 XC2V6000 FF1152 11 8 1 User FPGA to DIME II motherboard communication Local Bus Pinouts Signal Dime ll User FPGA Signal Dime ll User FPGA C onnector 2V3000 2V6000 Na
46. 6 PIN No PIN No PIN No PIN No gt ms NC fee sm NC PPALK 9 SA 58 61 9 SD 58 NC PPALK 10 SA59 PP6LK 10 SD 59 pp 1 NT107 0132 Issue 9 23 05 2003 www nallatech com 145 XtremeDSP Development Kit User Guide DIMEJI Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2v2000FG 676 Connector 2v2000FG 676 PIN No PIN No PIN No PIN No PP5LK 7 SB55 PP7LK lt 7 gt SC55 Table 59 PLINK Pinouts User FPGA 2V2000 11 6 2 DIME II control and monitoring signals DIME II Specific Pins Dime II Connector Signal Name Dime II Connector User FPGA PIN No PIN No 2V2000FG676 PIN E Table 60 User FPGA Specific Pinouts 2V2000 CONFIG DONEisdrivenfromthelO ofthe Virtex ll into the base ofthe transistor to signal that the on board User FPGA has been configured successfully User to drive this pin LOW once the FPGA is configured User LEDs Signal Name User FPGA 2V2000FG676 PIN No LED Greenl Y11 LED Redl Table 61 User LED Pinouts User FPGA 2V2000 On board T emperature Sensor Signal Name User FPGA 2V2000FG676 PIN No DXN NC Table 62 User LED Pinouts User FPGA 2V2000 1 46 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide 11 6 3 ZBT SRAM BANK Clock and Control Signals for ZBT Bank Signal Name User FPGA 2V2000FG676 ZBT CLK ZBT FB IN ZBT ADV B15
47. 7 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide 11 4 4 DAC Signal Pinouts Signal Name DAC 1 User FPGA 2V250 Signal Name DAC 2 User FPGA 2V250 PIN No PIN No DAC1 D lt 1 gt R22 DAC2 D lt 1 gt DAC1 D lt 8 gt DAC2 D lt 8 gt W 21 DAC1 D lt 9 gt DAC2 D lt 9 gt W 20 Wn Table 39 DACs Signal Pinouts 2V250 11 4 5 ADC Signal Pinouts Signal Name DAC 1 User FPGA 2V250 Signal Name DAC 2 User FPGA 2V250 PIN No PIN No Table 40 ADC Signal Pinouts 2V250 11 4 6 User IO header Signal Name User FPGA 2V250 PIN No Table 41 User IO Header Pinouts 2V250 N T107 0132 Issue 9 23 05 2003 www nallatech com 135 XtremeDSP Development Kit User Guide DIMET 136 11 5 XC2V1000 FG456 11 5 1 User FPGA to DIME II motherboard communication Local Bus Pinouts Signal Name Dime ll User FPGA Signal Name Dime Il User FPGA 2V1000 PIN C onnector 2V1000 No PIN No PIN No LBU S lt 0 gt LBUS 1 LBUS lt 27 gt PB31 M5 LBUS lt 28 gt PB33 1 2 5 mr mm Luse Pee E2 B4 1 2 B3 LBUS lt 3 gt B4 B6 B7 LBUS lt 9 gt PB11 LBUS lt 36 gt PB42 F4 LBUS lt 10 gt PB12 LBUS lt 37 gt PB43 LBUS lt 11 gt PB13 H5 LBUS lt 38 gt PB44 F3 LBUS lt 12 gt PB15 LBUS lt 39 gt PB45 LBUS lt 13 gt PB16 LBUS lt 40 gt PB46 K K L LBUS lt 45 gt PB52 LBU S lt 46 gt PB53 1 4 Me 407 Table 42 Local Bus Pinouts 2V 1000
48. 7 0132 Issue 9 23 05 2003 www nallatech com 33 XtremeDSP Development Kit User Guide DIME opening process The DIME O penCard handle is passed to later functions in order to allow these functions to communicate with the card Having opened the board a number of software functions can then be called to perform a variety of different operations on the re programmable devices in the chain This stage covers functions such as configuration of individual devices setting bit filenames resetting FPGA devices and other functions listed in the above Section This will be dependent on the particular application O nce users have finished using the BenO N E PCI the handle returned from DIME O penC ard should be closed in order to free all the resources used to interface to the card This can be accomplished by using the DIME CloseCard DIME HANDLE CardHandle function Additionally the handle returned from DIME LocateCard should also be closed This can be achieved using the DIME CloseLocate LOCATE HANDLE LocateHandle function Please consult the FUSE C C API Developers Guide for further details on all the available DIME software functions Sample Configuration Example A sample configuration sequence for FPGA Configuration Example 1 from Section 5 2 2 is shown below Example Devices on Module 0 Sample 5V PCI Module Boot Primary FPGA 3 3V PCI PROM Device 1 z Device 1 PSU B Controll
49. 72A Recommended Presale Ratio Settings Pinout Information for External Clock source O n board Crystal O scillator Pinout Generated Clock Pinouts 2nd External CLK FPGA Pinouts Clock signals for ZBT Memory Communication Bus Summary BenADDA Assigned MDF Code Listing LED signals Pinouts of User IO header Interface to User FPGA Comms Signals Interface to User FPGA Clock Requirements Local Bus Pinouts 2V250 Adjacent IN BUS Pinouts 2V250 Adjacent OUT BUS Pinouts 2V250 PLINK Pinouts 2V250 User FPGA Specific Pinouts 2V250 User LED Pinouts 2V250 Temperature Sensor Pinouts 2V250 Clock Signals at CLK FPGA 2V250 Clock Feedback Signals 2V 250 Clocking Pinouts for DACs and ADCs DACs Signal Pinouts 2V250 ADC Signal Pinouts 2V250 User IO Header Pinouts 2V250 Local Bus Pinouts 2V1000 Adjacent IN BUS Pinouts 2V1000 Adjacent O UT BUS Pinouts 2V1000 PLINK Pinouts 2V1000 User FPGA Specific Pinouts 2V1000 User LED Pinouts 2V1000 Temperature Sensor Pinouts Clock Signals at CLK FPGA 2V1000 Clock Feedback Signals 2V 1000 Clocking Pinouts for DACs and ADCs DACs Signal Pinouts 2V1000 ADC Signal Pinouts 2V1000 User IO Header Pinouts 2V1000 Local Bus Pinouts 2V2000 Adjacent IN BUS Pinouts User FPGA 2V2000 www nallatech com DIMETI NT107 0132 Issue 9 23 05 2003 DIMETI Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Tab
50. AE TE gt 12 CLK FPGA Virtex II 2 80 CLKA These clocks come up through the DIME LI CLKB connector from the 3 sources on the BenONE CLKC Virtex II User FPGA XC2V250 XC2V6000 CLKA Programmable Oscillator CLKB Programmable Oscillator Crystal Oscillator or External Clock input on the BenONE Figure 67 Overview of CLK FPGA following folder lt C D RO M gt Examples C lock_ Designs PCB V2YSource O ne VHDL file shows how to use the crystal osicllator source on the BenADDA to clock the ADCs and DACs and the User FPGA The second example shows how to use the external clock input to the BenADDA The two example clock designs included on the XtremeD SP CD in the NT107 0132 Issue 9 23 05 2003 www nallatech com 111 XtremeDSP Development Kit User Guide DIME 10 6 2 External Clock Source Using a clock source centred around OV Default Build The BenADDA provides a facility for an external clock source to drive the CLK_FPGA In order to meet the signal input specifications for the CLK_FPGA an op_amp is used to provide DC biasing to level shift the input signal above OV At the heart of the external clock circuit is the AD 8131 Differential D river This converts single ended inputs into differential outputs suitable for the CLK_FPGA The AD8131 has internal feedback with a fixed gain of 2 which allows for better thermal matching and tolerance levels The commo
51. BenADDA is a single slot module so is compatible with any D IME II motherboard a range of which are available from N allatech 8 2 Hardware features applicable to installation BenADDA is Electro Static Discharge ESD sensitive device ESD handling procedures must be observed during the handling and installation of the BenADDA If the BenADDA is supplied as a separate unit mounting screws and a front panel will be supplied for fitting to the motherboard The physical features of the D IME II module referred to in the installation instructions are highlighted below Analogue and PT Qa aman se Interconnectors TTA DIME II epe imi ea Secondary p A Connectors Power Pin Sockets DIME II Module Primary Connectors Fixing Screws to Carrier Board Figure 33 Hardware features for installation 68 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMIE II XtremeDSP Development Kit User Guide 83 Fitting the BenADDA The XtremeD SP D evelopment Kit fitting instructions are given below In this example the images show an unspecified D IM E II module being fitted to N allatech BenERA cPCI DIME II motherboard but the instructions are valid for any combination of DIME II module or motherboard 1 Ensure ESD handling procedures are observed during installation 2 Ensure the power to the DIME II host motherboard is switched off 3 Remove the motherboar
52. C Interface The main features of the on board ADC channels are 14 bit ADC resolution 2 s complement format 65MSPS sampling data rate sampling rate up to 105MSPS if using AD 6645 D ifferential O R Single ended Analogue Inputs 3 order filter on Analogue Inputs ADCs clocked differentially The BenADDA uses ADCs from Analog Devices the AD 6644 or AD 6645 The datasheets for these ADCs can be found on the BenADDA installation CD 10 5 1 ADC Architecture The AD 6644 is straightforward to operate the user is only required to apply data and a clock input There are no set up or control signals as with the DACs Shown below is the functional diagram of the 6644 architecture NT107 0132 Issue 9 23 05 2003 www nallatech com 109 XtremeDSP Development Kit User Guide LIA ETT BenADDA AD6644 Architecture Bed P m ete Error Correction Logic Figure 66 AD 6644 Architecture Theory of AD 6644 operation The AD 6644 has complementary analogue inputs each input is centred at 2 4V and should swing 0 55V around this 2 4V reference This means that the differential analogue input signal will be 2 2V as both input signals AIN and AIN 180 degrees out of phase with each other W hen data arrives at the AD 6644 both analogue inputs are buffered prior to the first track and hold TH1 The analogue signals are held in TH1 while the ENCO DE CLK pulse is high and then data
53. CLK D7 GCLK5P Complement of 274 External Clock EXT2 CLK 6 GCLK4S Table 21 2nd External CLK FPGA Pinouts 10 6 6 Clock feedbacks for De skewing Feedback signals between the CLK FPGA and the User FPGA are necessary to allow all data going to and from the User FPGA to be clocked on the same clock edge as the data in the DACs and ADCs There are a total of three feedback pins from the CLK FPGA to the User FPGA These feedback signals ensure that the clock to the DACs or ADCs and the feedback pins have coincident clock edges with minimum skew The feedback signals from the CLK FPGA to the User FPGA are matched in physical length with the clock signals sent to the DACs and ADCs This design ensures minimum skew between the data clocked through the ADCs DACs and the data being clocked in the User FPGA Figure 68 outlines the set up between the CLK FPGA and User FPGA for these feedback signals There reason for there only being 3 clock feedback pins is simply sue to clock pin resource constraints BenADDA CLK FPGA to User FPGA Feedback LVPECL to the DACs and ADCs i CLK FPGA to DACs and ADCs Clock feedback Virtex II XC2V80 lenghts UJ Virtex ll User FPGA XC2V250 XC2V6000 Figure 68 Diagram of CLK FPGA feedback signals 10 6 7 DAC and ADC clocking The CLK FPGA is used to directly clock each ADC and DAC device independently The ADCs and DACsare clocked differentially from the C LK FPGA and can be clocked a
54. D evice Indexing 121 Figure 73 CONFIG DONE Circuit 122 Figure 74 User LEDs location X C 2V250 2V1000 version shown 123 Figure 75 Temperature Sensor Interface 124 Figure 76 MCX connectors 125 Figure 77 Diagram of supplied C able Assembly 126 Figure 78 XtremeD SP D evelopment Kit D esign Partitioning 128 NT107 0132 Issue 9 23 05 2003 www nallatech com xi XtremeDSP Development Kit User Guide List of Tables Table 1 Communication Bus Summary Table 2 Example configuration I module and device ID numbering Table 3 Example configuration I module and device ID numbering Table 4 ALT JTAG header pinouts Table 5 uP JTAG Connector pinouts Table 6 Table 7 Table 8 Table 9 T able 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 T able 19 Table 20 T able 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 T able 29 Table 30 Table 31 T able 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Interface FPGA to DIME II Slot Interface Clock to DIME II Timing Information Bus Speeds I O Module O ptions Power Supply O ptions Adjacent Bus H eader Fan Jumpers BenADDA specifications DAC Input D ata Rates Controlling D igital Modes of AD97
55. ESET P19 Table 52 DACs Signal Pinouts 2V1000 11 5 5 ADC Signal Pinouts Signal Name DAC 1 User FPGA 2V1000 Signal Name DAC 2 User FPGA 2V1000 PIN No PIN No Y5 Y6 mave vn Hoods e _ Table 53 ADC Signal Pinouts 2V 1000 NT107 0132 Issue 9 23 05 2003 www nallatech com 141 XtremeDSP Development Kit User Guide DIMET 11 5 6 User IO header Signal Name User FPGA 2V1000 PIN No User 10 1 AA8 User 10 2 AB8 Table 54 User IO Header Pinouts 2V 1000 116 XC2V2000 FG676 11 6 1 User FPGA to DIME II motherboard communication Local Bus Pinouts Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V2000FG 676 Connector 2V2000FG676 PIN No PIN No PIN No PIN No mo om LBUS 1 PB2 G10 LBUS 33 PB38 F10 LBUS lt 2 gt PB3 G9 LBUS lt 34 gt PB39 F9 se mm gt 6 me _ mu 80 mm B _ LBUS lt 10 gt LBUS lt 42 gt rum usa ma F w mu Ke lusa KS msan mm M mn 6 _ w _ 5 Ne LN m Luse M _ pasa ms 20 ma fur reef 8 Fl 05 lt 58 gt PB66 LBUS lt 59 gt PB67 LBUS lt 60 gt PB69 BUS lt 61 gt PB7O Foo o LBUS lt 26 gt PB30 s LBUS lt 27 gt PB31 LBUS lt 28 gt PB33 LBUS lt 29 gt PB34 LBUS lt 25 gt PB29 NS LBUS lt 57 gt PB65 142 www nallatech
56. GA Signal Name Dime ll User FPGA Signal Name C onnector 2V250 PIN C onnector 2V250 PIN PIN No PIN No No M1 U5 ADJIN lt 3 gt PA 32 ADJIN 11 41 ADJIN lt 4 gt PA33 ADJIN lt 12 gt PA42 ADJIN lt 6 gt PA35 ADJIN lt 14 gt PA44 ADJIN lt 7 gt PA36 ADJIN lt 15 gt PA45 Table 30 Adjacent IN BUS Pinouts 2V250 ADJIN lt 5 gt PA34 ADJIN lt 13 gt PA43 ADJIN lt 0 gt is connected to a clock pin GCLKOS on the Virtex ll ADJIN lt 1 gt is connected to a clock pin GCLK1P on the Virtex ll Adjacent OUT Bus User FPGA connections Dime ll User FPGA Signal Name C onnector 2V250 PIN C onnector 2V250 PIN PIN No PIN No ADJOUT lt 0 gt PD29 Bl9 2 ADJOUT lt 8 gt PD 38 ADJOUT lt 1 gt PD30 A19 ADJOUT lt 9 gt PD39 Signal Name Dime ll User FPGA ADJOUT lt 2 gt PD31 C22 ADJOUT lt 10 gt PD40 H22 ADJOUT lt 3 gt PD32 ADJOUT lt 11 gt PD41 ADJOUT lt 4 gt PD33 E20 ADJOUT lt 12 gt PD42 K22 ADJOUT lt 5 gt PD34 ADJOUT lt 13 gt PD43 ADJOUT lt 6 gt PD35 ADJOUT lt 14 gt PD44 ADJOUT lt 7 gt PD36 ADJOUT lt 15 gt PD45 Table 31 Adjacent OUT BUS Pinouts 2V250 PLINKS connected to the User FPGA PLINKS 0 2 and 7 Dime l User FPGA Signal Name C onnector 2V250 PIN PIN No No User FPGA 2V250 PIN Dime ll C onnector PIN No Signal Name PPOLK lt 0 gt gt PPOLK lt 1 gt PPOLK lt 2 gt PPOLK lt 3 gt PPOLK lt 4 gt
57. Greenl LED Redl Table 79 User LED Pinouts User FPGA 2V3000 On board T emperature Sensor Signal Name User FPGA 2V3000FG676 PIN No Table 80 Temperature Sensor Pinouts 2V 3000 11 7 3 ZBT SRAM BANK Clock and Control Signals for ZBT Bank Signal Name User FPGA 2V3000FG676 PIN No ZBT CLK A13 ZBT FB OUT A12 NT107 0132 Issue 9 23 05 2003 www nallatech com 155 XtremeDSP Development Kit User Guide DIMET Signal Name User FPGA 2V3000FG676 PIN No Table 81 ZBT Clock and Control Signals Pinouts Bank ZBT Address Signals Bank Signal Name User FPGA Signal Name User FPGA 2V3000FG676 PIN 2V3000FG676 PIN No No ZBT_A lt 0 gt ZBT_A lt 11 gt ZBT_A lt 1 gt ZBT_A lt 12 gt ZBT A lt 2 gt ZBT A lt 3 gt ZBT A lt 4 gt ZBT A lt 5 gt B3 ZBT A lt 16 gt B9 2 lt 7 gt 8 2 lt 18 gt 4 ZBT lt 9 gt ZBT A lt 20 gt G7 Table 82 ZBT Address Signals Pinouts Bank T hese are Expansion PIN s and may not be supported by the ZBT memory nly use the above address pins if the onboard ZBT memory is in the following list ZBT A lt 18 gt use if ZBT Memory is 16Mb ZBT A lt 19 gt use if ZBT Memory is 32Mb ZBT A 20 use if ZBT Memory is 64Mb ZBT A 20 use if ZBT Memory is 128Mb ZBT Data Signals Bank Signal Name User FPGA Signal Name User FPGA 2V3000FG676 PIN 2V3000FG676 PIN ZBT D lt 0 gt ZBTA D lt 16 gt www nallatech com 1
58. I motherboard BenADDA Provides detailed instructions for installing and using the BenADDA DIME II module NT107 0132 Issue 9 23 05 2003 www nallatech com 3 XtremeDSP Development Kit User Guide DIMEN The Parts and Sections of the document are summarised below PART 1 Introduction Section 1 Preface Section 2 Getting Started PART 2 BenONE PART 3 BenADDA 1 3 Section 3 BenONE Overview Section 4 Installation Guide Section 5 Implementation Guide Section 6 Reference Guide Section 7 BenADDA Overview Section 8 Installation Guide Section 9 Implementation Guide Section 10 Reference Guide References There are a number of additional sources of information about specific aspects of the products used in the XtremeD SP kit Generally these are included in the documents folder in the CDs indicated in brackets Analog D evices Analog D evices Maxim Micron Nallatech Ltd Nallatech Ltd Nallatech Ltd Nallatech Ltd AD6644 ADC Datasheet Rev 0 XtremeD SP Kit CD AD9772A DAC Datasheet Rev 0 XtremeD SP Kit CD 1617 Datasheet XtremeD SP Kit CD ZBT SRAM Datasheet XtremeD SP Kit CD NT107 0068 FUSE C C API Developers Guide FUSE CD NT107 0068V2 FUSE System Software User Guide FUSE CD NT107 0103 DIMEScript User Guide FUSE CD 302 0000 PCI to User FPGA Interface Application N ote FUSE CD X ilinx Virtex II D atasheet available on X ilinx W ebsite Abbreviations ADC Analogue to Digital C
59. IN No PIN No ADJIN lt 0 gt PA29 ADJIN lt 32 gt PA65 ADJIN lt 1 gt PA 30 ADJIN lt 33 gt PA 66 Signal Name Dime Ill Dime l User FPGA 2vV3000FG 676 PIN No PA69 AD2 ADJIN lt 6 gt PA35 ADJIN 38 71 AR 7 ADJIN lt 7 gt PA 36 ADJIN lt 39 gt PA72 ADJIN lt 8 gt PA38 ADJIN lt 9 gt PA39 AF2 1 NC ADJIN lt 41 gt SB1 NC NC ADJIN lt 12 gt PA 42 ADJIN lt 13 gt PA43 ADJIN lt 14 gt PA 44 NT107 0132 Issue 9 23 05 2003 www nallatech com NC NC 151 XtremeDSP Development Kit User Guide DIMEJI Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2V3000FG 676 Connector 2v3000FG 676 PIN No PIN No PIN No PIN No ADJIN lt 15 gt PA45 ADIN lt 47 gt NC 5 ADJIN lt 20 gt 51 ADJIN lt 52 gt SA8 NC v4 PASE NC W5 ADJIN lt 25 gt PA57 ADJIN lt 57 gt SB10 ADJIN lt 26 gt PA58 ADJIN lt 58 gt SA12 W 1 0 5812 Table 74 Adjacent IN BUS Pinouts User FPGA 2V3000 Adjacent OUT Bus User FPGA connections Signal Name Dime ll User FPGA Signal Name Dime ll User FPGA Connector 2v3000FG 676 Connector 2V3000FG676 PIN No PIN No PIN No PIN No ADJOUT 1 ADJOUT 33 mons sy NC 152 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI Signal Name Dime Il Connector PIN No XtremeDSP Development Kit User Guide User FPGA Dime Il 2V3000FG676 PIN No Signal Name PIN No Con
60. IVO DIVI JP3 MODO J MODI 7 DIVI JP4 Figure 59 Physical Location of Jumpers for DAC X C2V250 only MOD pins XC2V250 only W hen the on board Virtex ll is a X C2V250 device a fixed jumper controls the MO D pins The MOD pins are fixed either HIGH or LOW at the time of production using a 0 ohm resistor connected to either GND LOW or VCCO 10 HIGH DAC 1 located at edge of the POB has the MO D pins controlled by fixed jumpers J4forMODO J5forMOD1 D AC 2 the inner DAC on the PCB has the MO D pins controlled by fixed jumpers J6for MODO www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEHI XtremeDSP Development Kit User Guide J7 for MODI Ben ADDA AD9772A MOD pin Jumpers XC2V250 only VCCO_IO MOD1 DAC2 AD9772A MODO MOD1 DAC1 AD9772A MODO Figure 60 DAC Diagram of MOD fixed jumpers 2V250 only As shown in Figure 60 all MO D jumpers have pin 2 connected HIGH and pin 3 connected LOW So ifa 0 ohm resistor is placed between pads 1 and 2 of a jumper that particular MOD pin is set HIGH Alternately a 0 ohm resistor placed between pads 1 and 3 would set the MOD pin LOW DIV pins XC2V250 only W hen the on board Virtex ll is a X C 2V250 device a user selectable jumper controls the DIV pins The DIV pins are selected either HIGH or LOW by the use of a jumper connector The DIV pins are set either to logic high or low by connecting two pins of the 3 way jump
61. Name User FPGA Signal Name User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No www nallatech com 107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Signal Name User FPGA Signal Name User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No ZBTA D lt 12 gt ZBTA D lt 28 gt ZBTA D lt 14 gt ZBTA D lt 30 gt ZBTA D lt 15 gt ZBTA D lt 31 gt Table 102 ZBT Data Signals Pinouts Bank 2V3000 6000 ZBT Parity Bits Bank Signal Name User FPGA Signal Name User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No Table 103 ZBT Parity Bits Pinouts Bank A 2V3000 6000 11 8 4 ZBT SRAM BANK B Clock and Control Signals for ZBT Bank B Signal Name User FPGA 2V3000 2V6000 2 OUT 16 16 GCLKIS ZBTB ADV G17 Table 104 ZBT Clock and Control Signals Pinouts Bank B 2V3000 6000 ZBT Address Signals Bank B Signal Name User FPGA Signal Name User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No ZBTB lt 0 gt ZBTB lt 11 gt ZBTB lt 1 gt ZBTB lt 12 gt 2 lt 2 gt 15 2 lt 13 gt F8 F15 F14 ZBTB lt 3 gt F8 2878 lt 14 gt F9 ZBTB A lt 4 gt ZBTB lt 15 gt 2 lt 5 gt 13 2 lt 16 gt ZBTB lt 6 gt ZBTB lt 17 gt ZBTB A lt 7 gt EO ZBTB lt 18 gt ZBTB A lt 8 gt ZBTB A lt 19 gt ZBTB A lt 9 gt ZBTB A lt 20 gt ZBTB A lt 10 gt J14 ZBTB A lt 21 gt
62. O Full details of the board specifics are available in the full documentation provided on the XtremeD SP Development Kit CDROM 2 2 XtremeDSP Development Kit Requirements The following Minimum System requirements are recommended for the software and this card e Pentium PII 233 e 32MB RAM e 1GB Hard Disk e USB v1 1 compatible port e Windows 98 ME 2000 X P operating system N T4 is supported but not over USB If you wish to install the BenO N E PCI card in a PC using a PCI slot please note that in the default configuration provided with the D SP Kit the BenO N E will only function correctly in a 5V PCI Signalling environment 2 3 UnpackingYour Starter Kit 2 3 1 Hardware Installation Features The XtremeD SP D evelopment Kit contains Electro Static D ischarge ESD sensitive devices ESD handling procedures must be observed during handling of the cards The physical features of the XtremeDSP Development Kit referred to in these instructions are highlighted below NT107 0132 Issue 9 23 05 2003 www nallatech com 5 XtremeDSP Development Kit User Guide ZBT Memory Oscillator ADC Channels External Clock Source DAC Channels User FPGA 2 3 2 DINIE TI USB Connect MA PCI FPGA Figure 1 Hardware features relating to connection and installation XtremeDSP Development Kit Contents This kit provides a motherboard populated with a daughter card also called a DIME II module It is
63. Three of these signals are driven by the PCI or USB interface These are AS D S EMPTY and BUSY AS DS This is address strobe data strobe signal W hen this is HIGH the data being transferred to the User FPGA is an address and when this signal is LO W the data being transferred to the User FPGA is data from to the last address given Generally addresses are only sent from the Interface FPGA to the User FPGA This signal is always in sync with the data passed through the internal FIFO s of the Interface FPGA so that the internal FIFO can have a mixture of actual data and addresses This AS D 5 line will auto matically indicate the true type of data EMPTY This signal indicates that there is data waiting to be written from the PCI or USB FPGA interface to the User FPGA This signal will go HIGH when there is no more data to be written to the User FPGA BUSY This signal indicates that the PCI or USB FPGA interface can receive data from the User FPGA W hen this signal goes HIGH no more data should be written to the Interface FPGA The User FPGA drives the two remaining control signals These are R W and REN W EN RHW This signal determines the direction of the data transferred between the Interface FPGA and the User FPGA Ifthis signal is LO W data is being read from the Interface FPGA and so the Interface FPGA drives the data bus If the signal is HIGH data is being written to the Interface FPGA and so the User FPGA drives the
64. User FPGA Resetting PCI FIFOs This functionality is provided in the following guises FUSE GUI Application DIMEScript FUSE Software development APIs 9 2 1 FPGA Configuration using FUSE GUI The FUSE GUI Application is an easy to use software interface which allows users to access a subset of the functionality provided by FUSE Full instructions on how to use the GUI are provided in the FUSE System Software User Guide on the supplied FUSE CD 9 2 2 FPGA Configuration using DIMEScript D IM EScript is a high level scripting language which provides users with a simple and easy to use language for the configuration and control of DIME systems DIM EScript uses a simple command set eliminating the need for developers to use complicated programming interfaces to control and communicate with application designs running in FPGAs DIM EScript also offers platform portability through ASCII based scripts allowing users to use DIMEScript on both W indows and Linux installations www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Gui D IM EScript can be used either to write script files which can then be executed as a single process or it can be used from a command line interface with the user executing commands as required Full instructions on how to use the DIMEScript are provided in the D IMEScript User Guide which is on the supplied FUSE CD 9 2 3 FPGA Configuration using the FUSE APIs T
65. User Guide Signal Name CLK FPGA 2V80 Pin User FPGA Signal Description NO 2V3000 2V6000 No Pe LK source via Op_ CLK source via Op Amp EXT _ ST un CLK source straight to CLK FPGA EXT CLKI 8 GCLKIP Complement of External CLK source straight to CLK FPGA Ose CLK CLK GCLK4P GCLK4P Na EXT2 EXT2CLIK D7 GCLK5P Na 2nd External Clock External C lock EXT2_ r T LI GCLK 4S ELLE of 2nd External Clock Table 108 Clock Signals at CLK FPGA 2V3000 6000 Clock Feedback signals Signal Name CLK FPGA 2V80 Pin User FPGA Signal Description No 2V3000 2V6000 NE PIN No CLK1 FB AF18 Feedback to User FPGA CLK3 FB AG18 Feedback to User FPGA CLK2 FB AF17 Feedback to User FPGA Table 109 Clock Feedback Signals 2V3000 6000 Clocking Pinouts for DACs and ADCs Signal Name CLK FPGA 2V80 Pin No ADC_CLKA ADC CLKAI ADC CLKB ADC CLKBI DAC CLKA DAC CLKAI DAC CLKB DAC CLKBI Table 110 Clocking Pinouts for DACs and ADCs 11 8 6 DAC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V3000 2V6000 2V3000 2V6000 PIN No PIN No DAC1 D lt 0 gt AM26 DAC2 D lt 0 gt AL22 DAC1 D lt 1 gt AL26 DAC2 D lt 1 gt AJ22 DAC1 D lt 2 gt AK26 DAC2 D lt 2 gt AH22 DAC1 D lt 3 gt AH 26 DAC2 D lt 3 gt AP23 DACT D lt 4 gt AN 27 DAC2 D 4 AN 23 DACT D lt 5 gt AM27 DAC2 D 5 AM23 NT107 0132 Issue 9 23 05 2003 www nallatech com
66. W indow will appear or similar Click N ext farorna f Pers Nora nomo mms mr eG FE ee ar m H REN VTA 5 Choose the top option search for suitable drivers option Click N ext iio Bee uer LE en Oe ee l E ar eee here m gj mms ih Pe p eni jija Ge bep Jab DL reed fers um ee dnm eer Hen uren m EL AC um BT m walls I Besi s i i B iss p EP eg ILE bi Paq LRL LO Ll uu I El eie ee Em born pus ums cun rye um em ann vr fn sind an DD deem mcum ao VE 37 T nr Ed ug 7 5 Windows will inform you that it has located a valid USB driver BenO NE PCI Loader Firmware Click N ext NT107 0132 Issue 9 23 05 2003 www nallatech com 27 XtremeDSP Development Kit User Guide DINIE 8 The screen below should appear indicating that the installation has been completed successfully Click Finish re Fran Hes Hae TE DETT om lt 4 6 2 Checking USB Installation To ensure correct installation you may view the Device Manager window This is accessed by a right mouse click on the My Computer Icon on your desktop 1 Select Properties from the drop d
67. W indows 3 Install the FUSE supporting software for the BenO N E and BenA DDA boards provided on the XtremeD SP Development Kit CD 2 5 1 FUSE Software Installation Before installing FU SE ensure that the BenO N E motherboard is NOT powered up Insert the supplied FUSE CD which autoruns to load the CD menu If the CD does not auto run run the following program autorun exe W hen the program runs the screen shown below will appear FUSE Ferrer Jo 2 Friel FSC E m brass K bke Wee Goren IE feo Anrin Asie E CL T I ETE Eh A Figure 4 FUSE CD Autoplay Menu 1 Click the first option Install FUSE Application Software 2 The installation process begins It uses a standard installation interface with which most users will be familiar W ork through the dialog boxes filling in details as required until the Finish dialog box is reached 3 Press Finish to install the software 4 ThePC then needs restarted prior to continuing the installation NT107 0132 Issue 9 23 05 2003 www nallatech com 9 XtremeDSP Development Kit User Guide 10 2 5 2 Hardware Driver Installation The following driver installation can be performed on power up or with the host PC already powered and the operating system s desktop visible 1 10 11 12 13 14 C onnect the supplied power supply to a suitable mains supply The p
68. X P or Linux This example application describes a simple AD C to DAC feed through design on the BenADDA This design is included on the X tremeD SP Development Kit CD to illustrate the capture of data from the ADC and the output of data to the DAC The design also includes a led flash pattern In addition this example can be used as a confidence test for you to ensure correct operation of the module 9 6 Functional Description The Clock FPGA is used to route the clock signals to the other devices on the BenADDA The design takes the signal from the on board crystal oscillator and distributes it to both ADCs both DACs and the main FPGA as illustrated in Figure 37 8 The VHDL source code for this design is included on the X tremeD SP D evelopment Kit CD at the path lt CDROM Drive gt Examples Adc_to_Dac Source AdctoD ac vhd 8 For convenience a X ilinx ISE Project N avigator File for each implementation option is included at the path lt CDROM Drive gt Examples Adc_to_Dac Source lSE packages ne supports FF1152 and one 676 Note that the X C2V3000 Virtex ll part is supported in both packages Therefore care should be taken when selecting bitfiles Please note that the BenADDA supports two variants that support different FPGA for configuration that they are indeed for the correct target FPG package N T107 0132 Issue 9 23 05 2003 www nallatech com 81 XtremeDSP Development Kit User Guide DIMETT
69. XtremeDSP Development Kit User Guide 107 0132 Issue 9 XtremeDSP Development Kit User Guide FIANE TT ii www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide N allatech is the leading FPGA C entric Systems provider with unrivalled industry expertise in the provision of FERTS complete systems including hardware IP and software N allatech s industry leading products services used in many application areas including DSP amp Imaging Telecommunications amp RF Aerospace amp Defence and N etworking amp Storage N allatech offers design services for complete systems in addition to the modular DIMETM and NALLATECH product ranges for electronic systems Contacting Nallatech and Xilinx Support WWW If your DSP kit was purchased directly from Xilinx go to http support xilinx com If the kit was purchased via N allatech go to www nallatech com and click support Headquarters Europe amp Asia Pacific North America N allatech N allatech Inc Boolean House 12565 Research Parkway One Napier Park Suite 300 Cumbernauld O rlando Glasgow G 68 0BH Florida 32826 United Kingdom United States of America Phone Fax Europe amp Asia Pacific North America Phone 44 0 1236 789500 Phone 1 407 384 9255 44 0 1236 789599 1 407 384 8555 Email sales nallatech com WWW www nallatech com NT107 0132
70. allation A PCI driver installation USB driver installation FUSE software installation 4 5 PCI Driver Installation 4 5 1 Windows 95 98 2000 ME XP Pro Installation o Administrative Privileges are required for W indows 2000 XP installation 1 Power up PC with BenO NE PCI installed 2 During boot up the PC should report that a new device has been found a PCI co processor CPU 3 The following screen or similar should appear boni maa ea a a Times Focal 077 Pride iB pci 4 Click Next the following screen should appear NT107 0132 Issue 9 23 05 2003 www nallatech com 25 XtremeDSP Development Kit User Guide DIME 26 5 Choose the top option the recommended choice then press N ext the following screen should appear dei sapan m rak cun ur ci ee dele Dich Hand tar sat ras parche Tempo r Mori f rder pige FF specs a arman Am mes 6 If not already ticked select the bottom choice Browse and locate the CD DrivelDrivers folder on the installation C D then select the relevant folder W in9x W in2k W inN T W inX P as appropriate for your installation 7 6 Windows will now load the new drivers and acknowledge the installation 8 On the last screen Click finish 9 N ext click YES to restart the PC allowing the drivers to be loaded The PC will now res
71. allows the zero stuffing option to be selected under the same circumstances If the PLL is disabled then the input data rate must be half the reference clock frequency This is due to the interpolation filter that adds extra samples every other clock cycle Additionally if the zero stuffing option is selected then the input data must be one quarter of the reference clock frequency For example the maximum reference clock of 160MSPS with the PLL disabled and the zero stuffing option selected gives a maximum input data rate of 40M Hz The internal PLL also deals with the phase relationship between the data and the reference clock This means that when PLL is enabled you do not need to use the RESET input to ensure correct alignment of clock and data If the PLL is disabled consult the Analog Devices AD9772A datasheet provided on the BenADDA installation CD for more information on how the RESET input is used to ensure correct synchronisation See Table 15 below for a summary of the DAC input data rates 102 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide PLL Disabled PLL Enabled Zero stuffing O FF Zero stuffing O N Zero stuffing O FF Zero stuffing O N Input Data Rate reference clock reference clock reference clock 1x reference clock Table 15 DAC Input Data Rates As outlined earlier in this Section the interpolation filter can be set to either a low or high pass chara
72. at CLK FPGA Clock Feedback Signals Clocking Pinouts for DACs and ADCs DACs Signal Pinouts ADC Signal Pinouts User IO Header Pinouts Local Bus Pinouts 2V 3000 6000 Adjacent IN BUS Pinouts User FPGA 2V3000 6000 Adjacent OUT BUS Pinouts User FPGA 2V3000 6000 PLINK Pinouts User FPGA 2V3000 6000 PLINK Pinouts User FPGA 2V3000 6000 GP 10 Pinouts User FPGA 2V3000 6000 User FPGA Specific Pinouts 2V3000 6000 User LED Pinouts User FPGA 2V3000 6000 Temperature Sensor Pinouts 2V3000 6000 Table 100 ZBT Clock and Control Signals Pinouts Bank A 2V3000 6000 Table 101 ZBT Address Signals Pinouts Bank 2V3000 6000 Table 102 ZBT Data Signals Pinouts Bank A 2V3000 6000 Table 103 ZBT Parity Bits Pinouts Bank A 2V3000 6000 Table 104 ZBT Clock and Control Signals Pinouts Bank B 2V3000 6000 Table 105 ZBT Address Signals Pinouts Bank B 2V3000 6000 Table 106 ZBT Data Signals Pinouts Bank B 2V3000 6000 Table 107 ZBT Parity Bits Pinouts Bank B 2V3000 6000 Table 108 Clock Signals at CLK FPGA 2V3000 6000 Table 109 Clock Feedback Signals 2V3000 6000 Table 110 Clocking Pinouts for DACs and ADCs Table 111 DACs Signal Pinouts 2V3000 6000 Table 112 ADC Signal Pinouts 2V3000 6000 Table 113 User IO Header Pinouts 2V3000 6000 NT107 0132 Issue 9 23 05 2003 www nallatech com 144 145 146 146 146 xiii DINIE XtremeDSP Development Kit User Guide Part 1 Introduct
73. been configured successfully User to drive this pin LOW once the FPGA is configured User LEDs PIN No LED Greenl 8 LED Green2 AN 32 LED Red2 AJ26 Table 98 User LED Pinouts User FPGA 2V3000 6000 Signal Name User FPGA 2V3000 2V6000 On board T emperature Sensor Signal Name User FPGA 2V3000 2V6000 PIN No ALERTI AJ33 Table 99 Temperature Sensor Pinouts 2V3000 6000 11 8 3 ZBT SRAM BANKA Clock and Control Signals for ZBT Bank A Signal Name User FPGA 2V3000 2V6000 PIN No ZBTA_FB_IN E18 GCLK4S 2 CKEI 19 NT107 0132 Issue 9 23 05 2003 www nallatech com 165 XtremeDSP Development Kit User Guide DIMET 166 Signal Name User FPGA 2V3000 2V6000 PIN No Table 100 ZBT Clock and Control Signals Pinouts Bank 2V3000 6000 ZBT Address Signals Bank A Signal Name User FPGA Signal Name User FPGA 2V 3000 2V 6000 PIN 2V3000 2V 6000 PIN No No ZBTA A lt 2 gt J20 ZBTA A lt 13 gt H26 ZBTA A lt 10 gt ZBTA A lt 21 gt F2 Table 101 ZBT Address Signals Pinouts Bank 2V3000 6000 T hese are Expansion PIN s and may not be supported by the ZBT memory nly use the above address pins if the onboard ZBT memory is in the following list ZBTA A lt 18 gt use if ZBT Memory is 16Mb ZBTA A lt 19 gt use if ZBT Memory is 32Mb ZBTA lt 20 gt use if ZBT Memory is 64Mb ZBTA A lt 20 gt use if ZBT Memory is 128Mb ZBT Data Signals Bank A Signal
74. cable form either the host PC or the BenO NE PCI should dynamically remove the driver from this branch www nallatech com DIMETI loom be fee Pound rs ME d zl ora seed etc all deter es ba E ED Gs SS d 8 S EEE p nni ee STEP 2 ama dum Tisa E ZU m ES Er sem Roe kosa n i masmi Runs 24 LE lia curas RAR a GE IT Fu EEE UP SPE EEE PRE dr sa E r am a El maq 8 0 a En II rem rhim oe Fe am DONOR E rasen Exeter ires Fran Hie deara uud NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide 15 Reconnect the cable The driver should be added to this branch only this time it should read BenO NE PCI If the driver still reads BenO N E PCI Firmware Loader remove the USB cable then the power cable on the BenO NE card 16 Reconnect the power cable and USB cable to the BenONE the driver should now read BenO NE PCI 2 5 3 BenONE BenADDA FUSE Supporting Software Insert the supplied X tremeD SP Development Kit CD that contains the required files for the BenADDA and BenONE boards This CD should autorun and display the Menu screen If the CD does not auto run
75. can be used as single ended or differential either use of on board O scillator OR 2nd external clock source this is a special build option A total of 6 clocking methods will be available on the module at any one time 64 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide 7 4 BenADDA functional diagram Analogue O utput Analogue Input DC Coupled OR Differential or Directly Coupled single ended External Clock I3NNVHO 3 TANNVHOD CHEND AA ON MODULE XILINX VIRTEX II FPGA X C2V250 X C2V6000 DIME II MOTHERBOARD TO lt I O Figure 32 BenADDA functional diagram NT107 0132 Issue 9 23 05 2003 www nallatech com 65 XtremeDSP Development Kit User Guide FIANE TT 66 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Section 8 Installation Guide This part of the User Guide provides you with installation information for the BenADD A hardware and software In this Section Hardware Installation Software Installation NT107 0132 Issue 9 23 05 2003 www nallatech com 67 XtremeDSP Development Kit User Guide Hardware Installation Motherboard requirements BenADDA hardware installation features Hardware installation instructions 8 1 BenADDA motherboard requirements The BenADDA should be hosted on a DIME II motherboard The
76. ckaging or its direct equivalent and must be adequately insured by the buyer Any equipment sent to the company for any purpose including but not limited to equipment originally supplied by the company must be adequately insured by the buyer while on the premises of the company PAYMENT N allatech Ltd terms of payment are 30 days net Any charges incurred in making the payment either currency conversion or otherwise shall be paid by the buyer The company reservesthe right to charge interest at a rate of 290 above the base rate of the Bank of Scotland PLC on any overdue accounts The interest will be charged on any outstanding amount from said due date of payment until payment is made in full such interest will accrue on a daily basis TECHNICAL SUPPORT The company offers a dedicated technical support via telephone and an email address It will also accept faxed support queries Technical support will be given free of charge for 90 days from the date of invoice for queries regarding the use of the products in the system configuration for which they were sold Features not documented in the user manual or a written offer of the company will not be supported Interfacing with other products other than those that are pre approved by the company as compatible will not be supported If the development tools and system hardware is demonstrably working no support can be given with application level problems WARRANTY The company of
77. com NT107 0132 Issue 9 23 05 2003 DIMETI Signal Name XtremeDSP Development Kit User Guide User FPGA 2V2000FG676 PIN No User FPGA 2V2000FG676 PIN No Dime ll Connector PIN No Signal Name Connector PIN No LBUS lt 30 gt PB35 LBUS lt 62 gt PB71 LBUS lt 31 gt PB36 LBUS lt 63 gt PB72 Table 55 Local Bus Pinouts 2V2000 Adjacent IN Bus User FPGA communications Signal Name ADJIN lt 0 gt ADJIN lt 1 gt ADJIN lt 2 gt ADJIN lt 3 gt ADJIN lt 4 gt ADJIN lt 5 gt ADJIN lt 6 gt ADJIN lt 7 gt ADJIN lt 8 gt ADJIN lt 9 gt ADJIN lt 10 gt ADJIN lt 11 gt ADJIN lt 12 gt ADJIN lt 13 gt ADJIN lt 14 gt ADJIN 15 ADJIN lt 16 gt ADJIN lt 18 gt ADJIN lt 19 gt ADJIN lt 20 gt ADJIN lt 21 gt ADJIN lt 22 gt ADJIN lt 23 gt ADJIN lt 24 gt ADJIN lt 25 gt ADJIN lt 26 gt ADJIN lt 27 gt ADJIN lt 28 gt ADJIN lt 29 gt ADJIN lt 30 gt ADJIN lt 31 gt NT107 0132 Issue 9 23 05 2003 User FPGA Connector 2V2000FG676 User FPGA Dime ll C onnector 2V2000FG 676 PIN No PIN No PIN No PIN No puwa ma me _ ma Dime l Signal Name PA41 7 SB2 NC PA42 Y SA 4 NC PA43 Y SB3 44 4 SA 5 NC ADJIN lt 48 gt PA45 ADJIN lt 17 gt 48 ADJIN lt 49 gt SB6 Table 56 Adjacent IN BUS Pinouts User FPGA 2V2000 www nallatech com 143 XtremeDSP Development Kit User Guide Adjacent OUT
78. commicating properly with the PC USB interface In this case try unplugging the U SB cable from the BenO cycling the power to the BenO NE and then reconnecting the USB cable Indicates USB Initialisation Figure 12 LEDs indicating USB Successful Initialisation NT107 0132 Issue 9 23 05 2003 www nallatech com 29 XtremeDSP Development Kit User Guide DIME 4 7 FUSE Software Installation Prior to installing the product CD it is necessary to have installed the FU SE Software that is supplied on a separate CD Simply insert the FUSE CD into the drive and select Install to FUSE Application Software from the menu that appears See Getting Started Section on page 5 for more information 4 7 1 Linux Linux is supported for the XtremeD SP D evelopment Kit Support files for FUSE under Linux are included on this CD However it is necessary to purchase FUSE for Linux to use this Please contact N allatech for more details Tested on redhat Standard installation 6 2 l Insert the installation C D 2 Mount the installation C D gt mount t iso9660 dev cdrom mnt cdrom 3 Go to the root of the area in which you installed the FU SE software e g gt cd usr local nallatech 4 Unzip the files of the LinuxBenD SPK tgz gt tar xvzf mnt cdrom linux Ballynuey2 LinuxBenDSPK tgz 5 O nce you have installed them to test the BenD SPK installation assuming you have a BenD SPK card installed gt ca bin gt sh fuse This wi
79. cteristic depending on whether you wish to capture baseband or IF signals O n the BenADDA this feature of the AD 97724 and also the zero stuffing option is controlled by the FPGA see NOTE below The operation of the MOD pins is summarised in T able 16 Digital Mode MODO MOD1 Digital Filter Zero Stuffing ftw emm ow fm am N Table 16 Controlling Digital Modes of AD9772A The AD9772A contains an internal Voltage Controlled O scillator VCO which can operate at up to 400 5 5 To ensure the optimum phase noise and successful locking of the PLL a pre scalar stage is incorporated to allow the sampling clock to be divided down as required for slower data rates The divide by ratio is selected by the DIV0 and DIV1 inputs as shown below in Table 17 Input Data MOD1 DIV1 DIVO Zero stuffing Divide by N Rate MSPS ratio 9 qe qe po o n e R na p jw j o 0 e pf o n j an e 4 n 1 Pe F 3 12 5 Table 17 Recommended Presale Ratio Settings The DIV0 and DIV1 signals are controlled by the on board FPGA see NOTE PLL_LOCKED signal from each AD 9772A is connected to the FPGA see NOTE onthe BenADDA This signal goes high to indicate that the PLL has locked to the input reference clock If the PLL is not locked due to the PLL being disabled or an unstable clock PLL LO CKED toggles between high and low in an asynchronous manne
80. d from the host PC or rack and place on a flat surface with the module slots facing upwards 4 Locate the empty DIME II slot on the motherboard onto which the module is to be installed 5 DIME II power interconnects are not fitted to the module these should be fitted to the sockets located on the underside of the module Insert the power interconnects as shown here Power interconnects are now properly fitted Repeat step 5 again for the power interconnect sockets on the other side of the module NT107 0132 Issue 9 23 05 2003 www nallatech com 69 XtremeDSP Development Kit User Guide 6 Orient the module so that it is facing the correct way on the module slot Carefully line up the DIME II Connectors and the power interconnects paying special attention to ensure the power interconnect pins on both sides of the module are all lined up to the sockets on the motherboard 7 Apply light downward pressure to the module W hile still holding it in place proceed to step 8 8 Using aflat bladed screwdriver begin to tighten the D IME II Fixing Screws Tighten the screws alternately tightening each screw one turn before swapping and tightening the opposite screw by one turn until both are fully tightened Avoid tightening either screw more than the other this would result in the module being fixed to the motherboard at an angle resulting in connector and module damage 9 TheDIME Il motherboard can then b
81. de In the case of multiple deliveries separate invoices will be raised If requested at the time of ordering an alternative delivery service can be used but only if account details are supplied to the company so that the delivery can be invoiced directly to the buyer by the delivery service The buyer accepts that any to be advised scheduled orders not completed within twelve months from the date of acceptance of the original order www nallatech com orders held by the buyers lack of action regarding delivery be shipped and invoiced by the company and paid in full by the buyer immediately after completion of that twelve month period INSURANCE All shipments from the company are insured by them If any goods received by the buyer are in an unsatisfactory condition the following courses of action shall be taken If the outer packaging is visibly damaged then the goods should not be accepted from the courier or they should be signed for only after noting that the packaging has sustained damage If the goods are found to be damaged after unpacking the company must be informed immediately Under no circumstances should the damaged goods be returned unless expressly authorised by the company If the damage is not reported within 48 hours of receipt the insurers of the company shall bear no liability Any returns made to the company for any reason at any time shall be packaged in the original pa
82. de FIANE TT 16 www nallatech com NT107 0132 Issue 9 23 05 2003 DINEI XtremeDSP Development Kit User Guide Part 2 BenONE This part of the User Guide provides you with information on installing and using the BenO N E DIME I motherboard In the following Sections Section 3 BenO verview Section 4 BenO NE Installation Guide Section 5 BenO N E Implementation Guide Section 6 BenO N E Reference Guide NT107 0132 Issue 9 23 05 2003 www nallatech com 17 XtremeDSP Development Kit User Guide FIANE TT 18 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide Section 3 BenONE Overview In this Section BenONE PCI description BenONE PCI key features BenONE PCI functional diagram 3 1 Description The BenO NE PCI is a PCI single slot DIME II motherboard It is classed as an entry level motherboard and is capable of hosting a single width DIME II module The board has no FPGA resources available to the user all resources are addressed on an attached module It does however have the capability of a secondary connection to a host PC for example USB primary connection being PCI This is achieved the addition of an IO module on the motherboard Another feature of the BenO NE PCI is that it can be used in standalone solutions using C ompact Flash technology The C ompact Flash is a specific option that is not included as standard in the XtremeD SP D evelo
83. dule User Guide for details The uP JTAG Chain is driven by the uP JTAG pin header on the BenO NE PCI The uP JTAG chain has built in switches which only switches a DIME II module slot into the chain if a module is populated Therefore if a module is not populated in a slot the chain skips that slot The uP JTAG Connector is configured to match the pinout of the AD SP 21160 EZ ICE Emulator which utilises the IEEE 1149 1 JTAG test access port of the ADSP 21160 to monitor and control the target board processor during emulation The EZ ICE probe requires the ADSP 21160 s CLKIN TMS TCK TRST TDI TDO EMU and GND signals be made accessible on the target system via a 14 pin connector a 2 row x 7 pin strip header The uP JTAG chain configuration is shown in Figure 19 the frontplate connector to access this chain is shown in Figure 20 and the pinout for the connector is detailed in Table 5 uP JTAG DIME II Slot 0 Header uP JTAG TDO Return Path Figure 19 DIME JTAG Chain 123456789 Figure 20 uP JTAG Connector The reason for the set up is so that the software cannot drive the JTAG chain at the same time as a separate program using a download cable connected to the external JTAG header NT107 0132 Issue 9 23 05 2003 www nallatech com 37 XtremeDSP Development Kit User Guide FIANE TT Pin Name Description
84. e CLK FPGA 2V80 Pin No ADC CLKA E4 ADC CLKAI D1 ADC CLKB G1 ADC CLKBI F1 DAC CLKA D13 DAC CLKAI D12 DAC CLKB G10 DAC CLKBI F12 Table 69 Clocking Pinouts for DACs and ADCs 11 6 5 DAC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V2000FG676 mI 2V2000FG676 PIN No No DAC1 D lt 0 gt V24 DAC2 D lt 0 gt AD21 DAC1 D lt 1 gt U24 DAC2 D lt 1 gt AC21 DAC1 D lt 2 gt U23 DAC2 D lt 2 gt AB24 DACT D lt 3 gt U22 DAC2 D lt 3 gt AB23 DAC1 D lt 4 gt U21 DAC2 D lt 4 gt AB20 1 D lt 5 gt T19 DAC2 D 5 AB18 DAC1 D lt 6 gt R24 DAC2 D lt 6 gt AA24 DAC1 D 7 R23 DAC2 D 7 23 DAC1 D lt 8 gt R19 DAC2 D lt 8 gt AA22 DAC2 D lt 9 gt AA20 DAC2 D lt 10 gt AA18 DAC2 D lt 11 gt Y22 DAC2 D lt 12 gt Y20 DAC2 D lt 13 gt Y19 DACT D lt 9 gt P23 DAC1 D lt 10 gt P22 DAC1 D lt 11 gt P21 DAC1 D lt 12 gt P20 DAC1 D lt 13 gt P19 DAC1 DIVO T20 DAC2 DIVO DACI DIVI T24 DAC2 DIVI DAC1 MODO R21 DAC1 MODI R22 DACT PLLLOCK DACT RESET DAC2 MODO T22 DAC2 MODI T21 DAC2 PLLLOCK AB16 DAC2 RESET 020 Table 70 DACs Signal Pinouts 2V 2000 www nallatech com 149 XtremeDSP Development Kit User Guide DIMEJI 11 6 6 ADC Signal Pinouts Signal Name DAC 1 User FPGA Signal Name DAC 2 User FPGA 2V2000FG676 PIN 2V2000FG676 PIN monse ne _ cw ADL D 8 ADC2 D 8 mass muse wm mara ps fa mava
85. e CLK FPGA Pin External CLK source viaOp Amp CLK_Op Amp GCLK6S Complement of External CLK Op Amp C6 GCLK7P source via Op Amp External CLK source straight to EXT CLK B8 GCLK 05 CLK FPGA Complement of External CLK EXT CLK A8 GCLK1P source straight to CLK FPGA T able 18 Pinout Information for External Clock source 10 6 3 On board Oscillator An on board crystal oscillator that generates an LVTTL clock signal is supplied with the standard build of the BenADDA The LVTTL clock signal generated by this oscillator is driven directly into the CLK FPGA This clock signal can then be used to derive the differential clock signals that can be used to clock both the DACs and the ADCs The Crystal scillator supplied with the BenADDA has low jitter characteristic and its speed will be matched to the sampling frequency of the ADCs For the ADC AD6644 a 65MHz crystal oscillator is supplied the ADCs this part can easily be replaced with an alternative speed rating The oscillator Although the BenAD DA is supplied with a crystal oscillator that complements the speed of Q is fixed onto the BenAD DA via sockets and can simply be lifted out Any O scillator with 112 www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide similar characteristics can be brought and placed into the socket pins The O scillator supplied with the BenADDA is an 8 pin DIL package from Pletronics This osc
86. e given in Section 10 3 2 PLL Clock Multiplier on page 101 94 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Figure 52 DACs Subsystem 9 13 Running the implementation The design can be run on hardware by downloading the appropriate bitfiles to the FPGAs This is done using the FUSE Probe utility O pen the card assign bitfiles and then configure the module packages ne supports a FF1152 and one a FG 676 Note that the XC2V3000 Virtex ll part is supported in both packages Therefore care should be taken when selecting bitfiles Please note that the BenADDA supports two variants that support different FPGA for configuration that they are indeed for the correct target FPG package The bitfiles that need to be assigned are 1 osc clk 2v80 bit or osc 2v40 bit depending upon the clock FPGA fitted on the particular BenADDA 2 Sysgen qaml6 2v3000f9676 bit or sysgen qam16 2v2000f9676 bit again depending upon the particular FPGA fitted For convenience these bitflles are stored in bitfiles folder in install folder gt examples sysgen Q AMA qam dpirlbitfiles Please note that this design is only currently supplied for the FG 676 package devices but it can be ported or used as a basis for a design targeting a FF1152 package FPGA NT107 0132 Issue 9 23 05 2003 www nallatech com 95 XtremeDSP Development Kit User Guide PMINIE TI 34 ry ry ry
87. e re fitted to the host PC or rack 10 The PC rack power can now be switched on T his concludes the hardware installation instructions You should now proceed to the next Section for software installation instructions 70 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Software Installation Windows 95 98 2000 Driver installation Linux driver installation Software tools installation Remember you need to install the relevant software for the DIME II carrier card being used If you need to install the DIME II carrier card software make sure you have restarted your machine before installing the BenADDA module software as certain environmental settings need to be updated 8 4 Software Driver Installation There is no hardware driver necessary to be installed However BenADDA data files need to be installed for the associated FUSE Software that is supplied with compatible D IME II carrier cards Full software installation instructions can be found in the G etting Started Section at the start of this User Guide 8 4 1 Linux Tested on redhat Standard installation 6 2 For Linux installation procedures see the Linux installation procedures for the BenO N E motherboard Section on page 30 as this package contains files for the BenADDA in the DSP Development kit 8 4 2 Software Tools Installation There is no additional software that needs to be instal
88. eatures 64 Physical Layout 98 i Specification Variations 64 BenONE HIS CO s m 21 scena 20 56 BenADDA 68 COCK E MEU aca godere nna 54 BenADDA 71 57 BenO N E Hardware munnar 22 Key uu unu 19 BenO 25 LEDS oriin 55 Interfacing misc RITE m 57 Design 41 128 PA SE LOU vt rad RO ERR 50 User IO header on BenADDA 126 Reese 55 Via MCX Connectors BenADDA 125 C M ClOCK FPGA TE 111 Module ID u u ua uod 32 Control and Monitoring Signals 120 BenADDA FPGA 120 DONG Qaqa dados borsa 121 O TAG 120 S n s 122 On board O 5 112 P D DAC 100 PCI LYST OEI 23 Ach 101 130 us PLE Clock Multiplier aaa 101 C serge 104 Programmable scillators 40 utput Configurations 107 programmable power supplies
89. elopment Kit User Guide User FPGA to DIME II motherboard communication DIME II control and monitoring signals Clock signals relating to DACs and ADCs DAC Signal Pinouts ADC Signal Pinouts User 10 header 11 6 XC2V2000 FG676 11 6 7 User FPGA to DIME II motherboard communication DIME II control and monitoring signals ZBT SRAM BANK Clock signals relating to DACs and ADCs DAC Signal Pinouts ADC Signal Pinouts User IO Header 117 XC2V3000 FG 676 11 7 1 User FPGA to DIME II motherboard communication DIME II control and monitoring signals ZBT SRAM BANK Clock signals relating to DACs and ADCs DAC Signal Pinouts ADC Signal Pinouts User IO Header 118 XC2V3000 XC2V6000 FF1152 11 8 1 11 8 2 11 8 3 11 8 4 11 8 5 11 8 6 11 8 7 11 8 8 User FPGA to DIME II motherboard communication DIME II control and monitoring signals ZBT SRAM BANK A ZBT SRAM BANK B Clock signals relating to DACs and ADCs DAC Signal Pinouts ADC Signal Pinouts User IO Header www nallatech com 136 139 140 141 141 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure
90. emeDSP Development Kit User Guide The display box then shows the source type and source name If these are correct click Finish to display the Xilinx Core Generator window shown in Figure 45 mo ee mm m m sm s m ma mms 1 Dg Cu merear rn en 2 pamm Cees aun 5 Later n p Dna Er gd Fn 53 F Hu ma m w zs m i ie 8 Bee pee 8 Des ingre ari Hasse Peo Gre EG Hugs Pee gg Figure 45 Xilinx Core Generator W indow Sine wave component To create the sine wave generator component in the Target Family window double click on the Math Functions folder Click on the sub folder Sine Cosine Look up Table which displays the Sine Cosine Look upT able component as shown in Figure 46 A umma PMen Pada he Ce L ck iy lare mg u m w um cm ETEEN S Sipra GE E TE n B Ww T Aum gen ar le VI nes lacus Fi LEE pis ER TJ Jorn J A Bae t ia n i L Epner Fe Thn m E unap lia ike ps sess m s Lem I arr a ol ikk das rm dia A
91. enONE PCI Physical Layout front Hardware Features 6 2 BenO NE PCI Power Specifications 6 2 1 Modular fixed power supply FPS 6 2 2 Modular programmable power supply PPS 63 Clock Circuit 64 Reset and LEDs 6 4 1 Reset 6 4 2 PCI FPGA Configuration LED 6 4 3 DIME II Module Bulk Supply LED s 6 4 4 User LEDs Build O ptions and Jumper Settings 65 Build Options 6 5 1 I O Modules 6 5 2 Compact Flash C F 6 5 3 VAUX Battery B 6 5 4 Power Supplies 6 5 5 Standalone Power Connection SPC 6 6 Jumper Settings 6 7 Peripherals Pin out Information 6 8 External Connectors 6 8 1 Standalone Power Connector Vi www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide 6 3 2 Disk Drive Style Power C onnector 58 6 8 3 PLink Bus Header 11 59 6 8 4 Adjacent Bus Header 10 59 6 3 5 Fan Jumpers 60 BENADDA 61 BenADDA Overview 63 7 1 BenADDA 63 1 2 Key Features 64 73 BenADDA specification variations 64 74 BenADDA functional diagram 65 Installation Guide 67 Hardware Installation 68 81 BenADDA motherboard requirements 68 8 2 Hardware features applicable to installation 68 8 3 Fitting the BenADDA 69 Software Installation 71 8 4 Software Driver Installation 71 8 4 1 Linux Tested on redhat Standard installation 6 2 1 8 4 2 Software Tools Installation 71 Implementation Guide 7 FPGA Configuration 74 9 1 FPGA Configuration 74 9 2 FPGA Configuration using FU SE 74 9 2
92. epending upon whether a XC2V3000FG676 or XC2V2000FG676 part is being targeted Please refer to Section 11 Pinout Information on page 130 for further details of the specific pins depending upon the device package 96 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Section 10 Reference Guide In this Section Physical Layout Hardware Features Interfacing Pinout Information NT107 0132 Issue 9 23 05 2003 www nallatech com 97 XtremeDSP Development Kit User Guide DIMEAI Physical Layout Physical features of the BenADDA are identified 10 1 BenADDA physical layout top DAC Channel 2 ADC Channel 1 DAC Channel 1 ADC Channel 2 User LED mik te User LED User FPGA i H I tl Oscillator ZBT Memory Figure 54 BenADDA layout top 98 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide 102 BenADDA physical layout bottom Serial Number Clock FPGA XC2V80 Bare board Issue m MSN Populated Board Number Issue Number Figure 55 BenADDA layout bottom NT107 0132 Issue 9 23 05 2003 www nallatech com 99 XtremeDSP Development Kit User Guide DIME Hardware Features BenADDA Digital to Analogue Converter DAC Output Configurations BenADDA Analogue to D igital C onverter Clockingthe DACs and ADCs ZBT SRAM Memory User FPGA Control and Monit
93. er Device 0 a LJ LJ A a PCI FPGA BENONE PCI Figure 15 Diagram for FPGA Configuration Example 1 FPGA Device Module ID Number Device ID Number NN Table 3 Example configuration 1 module and device ID numbering The code written in C for the example configuration described above is illustrated as follows in Figure 16 34 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Finclude dimesdl h contains the API functions Declare variables DWORD Statusl Status2 Status3 Status4 DIME HANDLE hBenONE LOCATE HANDLE hLocate if hLocate DIME LocateCard dlPCI mbtTHEBENONE NULL dldrDEFAULT dLDEFAULT NULL Error Could not locate the BenONE PCI return 1 Exit the app if hBenONE DIME OpenCard hLocate 1 dccOPEN DEFAULT NULL Error Could not open the PCI return 1 Exit the app Boot the secondary FPGA device 1 on Module 1 with the bit file BitfileC bit Statusl ConfigDevice hBenONE BitfileC bit 1 1 NULL 0 Boot the primary FPGA device 2 on Module 1 with the bit file Bitfile bit Status2 DIME ConfigDevice hBenONE Bitfile bit 1 2 NULL 0 DIME CloseCard hBenONE DIME CloseLocate hLocate Figure 16 Example C code to configure FPGAs in Example Configuration 2 5 2 4 FPGA Configuration using FUSE Probe The FUSE GUI Application is an easy to use so
94. er together DAC1 located at edge of the PCB has the DIV pins controlled by selectable jumpers 1 for DIVO JP3 for DIVI DAC2 the inner DAC on the PCB has the DIV pins controlled by selectable jumpers JP2 for DIVO JP4 for DIVI NT107 0132 Issue 9 23 05 2003 www nallatech com 105 XtremeDSP Development Kit User Guide DIME BenADDA AD9772A DIV pin Jumpers XC2V250 only VCCO_IO 2 O4 JP4 3 1 2 GND 1 JP2 1 2 O1 JP3 3 1 2 GND O1 JP1 Figure 61 DAC Diagram of DIV selectable jumpers 2V 250 only Figure 61 shows that all DIV jumpers have pin 2 connected HIGH and pin 3 connected LOW This allows you to manually choose between setting 1 and 2 DIV High or between 1 and 3 DIV Low PLL LOCK pins XC2V250 only W hen the on board Virtex ll isa X C 2V250 device the PLLLO CK signal is unavailable at the User FPGA therefore a LED is tied to the PLLLO CK signal to indicate its current operation Figure 62 shows the set up of the LED BenADDA AD9772A PLLLOCK LED indicator 2V250 only VCCO 10 VCCO IO Figure 62 PLLLOCK LED indicator 2V250 only W hen a XC2V250 FPGA is populated the LED is switched on when PLLLO CK pin is HIGH For example when PLLLO CK is sending out a HIGH signal it will turn on the base of the transistor and the LED will light So when PLLLO CK is sending out a LOW signal the LED will be switched off For full details on PLLLO CK status for a specific desi
95. es The AD 9772A generates a variety of clock frequencies to operate its elements at the correct rates To achieve these frequencies it utilises an internal PLL whose VCO can generate clock rates of up to 400MSPS The AD9772A can be operated with the PLL enabled or disabled both operations are supported on the BenADDA 10 3 2 PLL Clock Multiplier Figure 58 illustrates how the BenADDA supports having the PLL enabled or disabled NT107 0132 Issue 9 23 05 2003 ww w nallatech com 101 XtremeDSP Development Kit User Guide DINIE NOTE PLL is enabled by default Please contact N allatech to disable the PLL function To supply the PLLVD D pin you can populate a jumper to supply the pin with a 3 3v signal or else tie the pin to ground The supply for the PLLVDD pin is shared with the supply of the CLKVDD pin and both the CLK and PLL grounds on the chip share the same separate ground plane W hen the PLL is disabled and the PLLVDD pin is tied to ground the filter components for the LPF pin internal loop filter for the PLL on the DAC are not populated This leaves the LPF with an open connection BenADDA AD9772A PLL Jumper AD9772A PLLVDD CLK_GND Figure 58 PLL Jumper Option W hen the PLL is set to the default value enabled the AD 9772A will generate its own 2x clock from the reference clock T his allows you to transmit data at the same rate as the reference clock T he internal PLL can also generate another phase clock that
96. et on the BenO NE PCI is shown Figure 30 DIME II PCI FPGA PC15 Slots RESET Figure 30 BenONE PCI Reset Circuit 6 4 2 PCI FPGA Configuration LED LED D10 will illuminate when the PCI FPGA is fully configured 6 4 3 DIME II Module Bulk Supply LEDs Each of the bulk power supplies has a single tri colour LED showing the status of the power supply Silk Screen Colour Description Identifier LED P a En Kao PSUD Off Please note that individual modules do not use all power supplies For example when a BenADDA is fitted to a BenO N E it is normal for only three ofthe LEDs to change from RED to GREEN to indicate they have been turned on 6 4 4 User LEDs Please note that on Version 1 BenO NE PCB there are only three available tri colours D3 D4 D5 Version 2 of the BenO NE PCB there are 4 tri colours LEDs D3 D4 D5 and NT107 0132 Issue 9 23 05 2003 www nallatech com 55 XtremeDSP Development Kit User Guide DIMET Build O ptions and Jumper Settings BenONE PCI Build O ptions Jumper Settings 6 5 Build Options 6 5 1 I O Modules This option allows the user to select an appropriate standalone IO module There is currently only one option but this will increase to three Option Module Nallatech Part Number USB 1 11 O Module NT101 0134 1 Table 10 I O Module Options 6 5 2 Compact Flash CF Allows the BenO NE PCI card to be booted from a compact flash module located on t
97. f IPR by the company unless expressly offered as part of the contract by the company GOVERNING LAW This agreement and performance of both parties shall be governed by Scottish law Any disputes under any contract entered into by the company shall be settled in a court if the company s choice operating under Scottish law and the buyer agrees to attend any such proceedings action can be brought arising out of any contract more than 12 months after the completion of the contract INDEMNITY The buyer shall indemnify the company against all claims made against the company by athird party in respect of the goods supplied by the company SEVERABILITY www nallatech com XtremeDSP Development Kit User Guide If any part of these terms and conditions is found to be illegal void or unenforceable for any reason then such clause or Section shall be severable from the remaining clauses and Sections of these terms and conditions which shall remain in force NOTICES Any notice to be given hereunder shall be in writing and shall be deemed to have been duly given if sent or delivered to the party concerned at its address specified on the invoice or such other addresses as that party may from time to time notify in writing and shall be deemed to have been served if sent by post 48 hours after posting Software Licensing Agreement N allatech Ltd software is licensed for use by end users under the following conditions By installing t
98. fers as part of a purchase contract 12 months warranty against parts and defective workmanship of hardware elements of a system The basis of this warranty is that the fault be discussed with the companies technical support staff before any return is made If it is agreed that a return for repair is necessary then the faulty item and any other component of the System as requested by those staff shall be returned carriage paid to the company Insurance terms as discussed in the IN SURAN CE Section will apply The company will not accept returned goods unless this has been expressly authorised After warranty repair goods will be returned to the buyer carriage paid by the company using their preferred method Faults incurred by abuse ofthe product as defined by the company are not covered by the warranty Attempted repair or alteration ofthe goods as supplied by the company by another party immediately invalidates the warranty offered NT107 0132 Issue 9 23 05 2003 LIM ETT NT107 0132 Issue 9 23 05 2003 The said warranty is contingent upon the proper use of the goods by the customer and does not cover any part of the goods which has been modified without Nallatech s prior written consent or which has been subjected to unusual physical or electrical stress or on which the original identification marks have been removed or altered N or will such warranty apply if repair or parts required as a result of causes other than ordinary auth
99. ftware interface which allows users to access a subset of the functionality provided by FU SE Full instructions on how to use the GUI are provided in the FU SE System Software User Guide 5 2 5 FPGA Configuration using DIMEScript DIMEScript is a high level scriptinglanguage which provides users with a simple and easy to use language for the configuration and control of DIME systems DIMEScript uses a simple command set eliminating the need for developers to use complicated programming interfaces to control and communicate with application designs running in FPGAs DIMEScript also offers platform portability through ASCII based scripts allowing users to use DIMEScript on both W indows and Linux installations D IM EScript can be used either to write script files which can then be executed as a single process or It can be used from a command line interface with the user executing commands as required Full instructions on how to use the DIMEScript are provided in the D IM EScript User Guide which is on the XtremeD SP D evelopment Kit CD 5 3 FPGA Configuration using the FUSE APIs The FUSE Software development enables users to call functions to control DIME hardware in their own programs This allows users to develop software applications to complement the FPGA application designs running on DIME hardware FUSE APIs are available to support a number of development languages including C C Matlab and Java Full instructions
100. gn please refer to the AD9772A Analog D evices datasheet provided on the BenADDA installation CD 106 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMET XtremeDSP Development Kit User Guide 10 4 DAC Output Configurations The AD9772A DAC supports two output configurations The following are supported as build options on the BenADDA e Single ended output DC coupling using an op amp e Differential outputs using termination resistors 10 4 1 Single Ended DC Coupling Using an Op Amp The op amp configuration is useful for applications requiring DC coupling Figure 63 illustrates the set up adopted to use an op amp configuration at the output of the AD 9772A BenADDA AD9772A DC coupled Output Final Output to user via MCX connector 4144 Figure 63 AD9772A DC coupled O utput The op amp used in the design is an instrumentation amplifier with a X 2 gain from MAXIM This means that the output configuration will drive an output voltage of 1V into a 500 load 10 4 2 Differential Outputs usingTermination Resistors It is also possible to drive differential outputs using a pair of termination resistors BenADDA AD9772A Directly coupled Output Differential Output to MCX connector NT107 0132 Issue 9 23 05 2003 ww w nallatech com 107 XtremeDSP Development Kit User Guide DIME 108 Figure 64 AD9772 directly coupled option W hen terminated into a 50Q load this option will provide a fully differential 0 5V
101. has a pre defined communications protocol to facilitate communications to the Interface FPGA In order to communicate with the Interface FPGA from the User FPGA the User FPGA application design must incorporate a mechanism to communicate over this bus This communications mechanism can be implemented directly by the user in the design or by using N allatech s drop in IP core the PCI to User FPGA Interface Core This core implements the Interface to User FPGA Comms communications mechanism and offers the user a simplified interface to which they can connect their own designs 42 www nallatech com NT107 0132 Issue 9 23 05 2003 Ee EE 5 11 1 Interface to User FPGA Interface Core The Interface to User FPGA Interface Core is a drop in IP core which can be incorporated into the User FPGA Application Design This core implements a mechanism which deals with the protocol to communicate over the Interface Comms Bus This abstracts the complexities of the protocol and provides a simplified user interface offering a memory mapped address space for registers peripherals and DMA channels for high speed data transfer A block diagram for the implementation of this core is shown below in Figure 22 User FPGA User FPGA Application Design PCI or USB Interface in FPGA Interface Interface User portion of Comms Bus User FPGA P K K KT E H Application Interface to Design User FPGA Core Figure 22 Implementation wi
102. he FUSE Software development API is a software development enabling users to call functions to control DIME hardware in their own programs This allows users to develop software applications to complement the FPGA application designs running on DIME hardware FUSE APIs are available to support a number of development languages including C C Matlab and Java Full instructions on how to use the APIs are provided in the FUSE C C API Developers Guide on the supplied FUSE CD NT107 0132 Issue 9 23 05 2003 www nallatech com de 75 XtremeDSP Development Kit User Guide DIME FPGA Application Design Interfacing to the User FPGA User FPGA design synthesis and implementation Communication between the User and PCI FPGAS 9 3 Interfacing to the FPGA It is assumed that most users will be familiar with the principles of FPGA design or have appropriate resources support to complete FPGA designs The following information is intended to detail any BenAD DA specific issues in the design process A User Constraints File UCF for the user accessible connections to the FPGA is provided with the BenA DDA on the product CD This allows you to quickly and easily link top level HDL code to the FPGA 1 0 for implementation purposes times by writing your top level HDL code using the same port naming convention as the Q Since the supplied U CF names are pre defined you can save nuisance and development N allatech UCF This sa
103. he rear of the card The BenO NE PCI card utilises the Xilinx System ACE chipset to control the compact flash however a third party programmer is required to download designs to a compact flash card 6 5 3 VAUX Battery B Located on the rear of the card this option is required if you wish to use the encryption bit stream format to protect your designs 56 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide 6 5 4 Power Supplies The default option for DIME II module power supplies is the fixed voltage module This offers the customer a cost saving by trading off the flexibility of a full programmable supply N allatech would recommend the full programmable supply option if a customer were to use the BenONE PCI with several different modules Special options can be offered with a mixture of fixed and programmable supplies please contact N allatech for more information on these options Power supply Configuration Power supply option Fixed Voltage Power Supply FPS Programmable Voltage Power Supply PPS Table 11 Power Supply O ptions 6 5 5 Standalone Power Connection SPC This option is required if you to use the BenO NE PCI in its standalone configuration See Section 6 8 1 Standalone Power Connector for the pin out of this connector 6 6 Jumper Settings The BenO NE PCI requires no jumpers to be set by the user 6 7 Peripherals Apart from standard DIME
104. he software you agree to be bound by the terms of this license If you do not agree with the terms of this license do not install the Software and promptly return it to the place where you obtained it L Licence N allatech Ltd grants you a licence to use the software programs and documentation in this package Licensed materials if you have a single license on only one computer at atime or by only one user at a time if you have acquired multiple licenses the Software may be used on either stand alone computers or on computer networks by a number of simultaneous users equal to or less than the number of licenses that you have acquired and if you maintain the confidentiality of the Software and documentation at all times 2 Restrictions This software contains trade secrets in its human perceivable form and to protect them except as permitted by applicable law you may not reverse engineer disassemble or otherwise reduce the software to any human perceivable form You may not modify translate rent lease loan or create derivative works based upon the software or part thereof without a specific run time licence from N allatech Ltd 3 Copyright The Licensed Materials are Copyrighted Accordingly you may either make one copy of the Licensed Materials for backup and or archival purposes or copy the Licensed Materials to another medium and keep the original Licensed Materials for backup and or archival purposes Additionally if the
105. igured at the time of manufacture voltages in the range of 1V to 3 3V are available with a maximum output current of abs max This is the power supply that is fitted as standard in the XtremeD SP D evelopment kit Even though the unit is capable of supplying 7A abs max the actual output voltage and more importantly the drop from the input to the output will limit to operating range of the unit due to its ability to dissipate the heat generated by the conversion The following calculations can be used to calculate the max power that can be drawn There for a FPS that is supplying 1 5V to the system under the conditions of an ambient temperature TA of 25 C and a thermal coefficient of 35 W I Pax 0 where 35 C W T 125 C max T 25 C gt 125 25 35xP ax gt Pax 2 8510 Prax Iout yax Vin Vo 2 857 Tout yax X 5 1 5 gt lout 816 33 For FPS that is supplying 3 3V system 52 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide TP 0 XP ay 35 C W T 2125 C max T 25 2123 2344 35 22 gt P ar 2 89707 Puax Tout yax Vour 2 857 Iout ax x 5 3 3 gt louty x 1 681A As part of the characterisation process it has been proved that a design targeted at an X C 2V3000 using 80 of the chip with a 1596 toggle rate can be run 65MHz whilst rema
106. illator is powered from 3 3V and any replacement oscillator should follow the same criteria Please contact N allatech for advice on replacing the standard oscillator Clock Signal Description Signal Name CLK FPGA Pin LVTTL Clock O scillator CLK M6 GCLKAP Table 19 On board Crystal Oscillator Pinout 10 6 4 Generated Clock signals from User FPGA Another method of clocking the DACs and ADCs is by using clock signals generated by the User FPGA W ithin the User FPGA there are three DIME II system clocks CLKB CLKC See Section 10 8 3 D IME II system C locks for more information Please note that in the X tremeD SP kit only C LKA and C LKB clock sources are programmable and is connected to a socket for a crystal oscillator These system clocks can be used to derive an appropriate clock frequency within the User FPGA and then driven into the CLK FPGA where they can be forwarded out to the appropriate DACs and or ADCs These generated Clock signals are forwarded from the User FPGA to the CLK FPGA as four single ended signals From the CLK FPGA the forwarded clock signals can then be sent out to the DACs ADCs as differential signals Table 20 shows the generated clock signals Clock Signal Signal Name CLK FPGA Pin User FPGA Pin Description Generated Clock A GEN CLKA 7 GCLKOP Consult Pinout Information Section N 8 Generated Clock B GEN CLKB M7 GCLK6P Consult Pinout Information
107. ining within the capability of the FPS units For significantly higher power requirements PPS units should be considered due to their higher power capabilities Please contact N allatech for details of the PPS units and upgrade options These power factors should be taken into account when designing the system using the BenO N E with associated DIME II modules It may be necessary to make use of the PPS modules rather than the FPS option for the higher power situations 4 PPSs 7 Amps each supply Figure 27 Programmable Power Supplies on the BenO NE PCI 4 LEDs on the BenO NE PCI indicate the status of each power supply unit They will only illuminate when the slot is populated with a module the BenO NE PCI card has been opened by the host system and power to the module slot is switched on Please note that if a power supply is not used then the power indicator for that supply will remain RED indicating it is not switched on For example on the BenADDA only three supplies are required and so only three of the four LEDs will change from red to green The power requirements of the FPGA devices on the attached module will depend upon the density and speed of the application design running in them T he X ilinx Power Estimator can be used to estimate the power requirements of application designs Xilinx Power Estimator http support xilinx com support techsup powerest index htm NT107 0132 Issue 9 23 05 2003 www nallatech co
108. ion This part of the User Guide provides an introduction to the X tremeD SP D evelopment Kit and contains information on the structure of the User Guide followed by a Getting Started Guide The following Sections include Section 1 Preface Section 2 Getting Started NT107 0132 Issue 9 23 05 2003 www nallatech com l XtremeDSP Development Kit User Guide FIANE TT 2 www nallatech com NT107 0132 Issue 9 23 05 2003 Datel XtremeDSP Development Kit User Guide Section 1 Preface In this Section About this User Guide User Guide format References Abbreviations 11 About this User Guide This User Guide provides detailed information on using the DIME II XtremeD SP Kit The User Guide is designed to provide information that allows you to become acquainted with the kit and the functionality it provides Throughout this document there are symbols to draw attention to important information i The blue i symbol indicates useful or important information The red symbol indicates a warning which requires special attention 1 2 User Guide Format The User Guide is divided into Sections which are grouped into Parts The Parts divide the document as follows Introduction Provides an introduction to the User Guide and a Getting Started Section so you can get the kit up and running as quickly as possible BenONE Provides detailed instructions for installing and using the BenONE DIME I
109. it 107 0132 Issue 9 23 05 2003 www nallatech com 39 XtremeDSP Development Kit User Guide DINIE 5 8 Source Descriptions Programmable Oscillators The Programmable O scillators are controlled via FUSE Software through any of the available interfaces A PIs The available operating frequencies of the programmable oscillators is as follows 20 MHz 25 MHz 30 MHz 33 33 MHz 40 MHz 45 MHz 50 MHz 60 MHz 66 66 MHz 70 MHz 75 MHz 80 MHz 90 MHz 100 MHz 120 MHZ W hen a frequency is requested using FU SE which does not exactly match one of the fifteen frequencies supported by the oscillators the firmware will select the frequency from the available frequencies which is numerically closest to the frequency requested External Clock Source External clock sources can be brought onto the BenO N E PCI for on board use Please refer to Section 5 9 Using external clocks on page 40for further details Software Derived Clock The Software D erived Clock can be used for debugging and is controlled from the FUSE APIs Please refer to the FUSE System Software User Guide for more details N ote that this facility it not currently available in the firmware until a future firmware release Fixed Oscillator A 50MHz fixed oscillator is fitted to the X tremeD SP Development Kit providing a high accuracy clock source 5 9 Using external clocks The XtremeD SP D evelopment Kit is provided with Clock utput functionality enabling o
110. ker inierface is ha BB Bus He sert rymber o 61007 Figure 41 Dialogue box to open cards 5 Right click the Clock FPGA in the device tree under the BenADDA module and select Assign and Configure DM Es Pete Ste a 5 37 Fili k Fre alas t i JESSE GER sma ma m E m EIEX E mimm E E E oe i I E a aa FEST N 1 gt gt Er Ho gt gt Figure 42 GUI showing open 6 dialogue box is displayed which allows you to browse and select the correct bitfile for the device The bitfile for this device is named osc clk 2v80 bit and is located at the path lt CDROM Drive gt Examples C lock DesignsPCB V2V on the XtremeD SP D evelopment Kit CD Please note that the BenADDA supports two variants that support different FPGA packages O ne supports a FF1152 and one FG 676 Note that the X C2V3000 Virtex Il part is supported in both packages Therefore care should be taken when selecting bitfiles for configuration that they are indeed for the correct target FPG package 84 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide In a similar way assign and configure the main FPGA The bitfile
111. l D iagram 20 Installation Guide 21 Hardware Installation 22 4 1 BenO N E PCI host PC requirements 22 4 1 1 PCI Connection 22 4 1 2 USB Connection 23 4 2 Hardware Features 23 4 3 PCI Installation 23 4 4 USB Installation 24 Software Installation 25 4 5 PCI Driver Installation 25 4 5 1 W indows 95 98 2000 ME X P Pro Installation 25 4 5 2 PCI Windows NT Installation 26 4 6 USB Driver Installation 27 4 6 1 W indows 98 2000 Installation 27 4 6 2 Checking U SB Installation 28 NT107 0132 Issue 9 23 05 2003 www nallatech com v XtremeDSP Development Kit User Guide 4 7 FUSE Software Installation 4 7 1 Linux Implementation Guide 5 1 FPGA Configuration O ptions 5 2 FPGA Configuration using FU SE 5 2 1 D evice Module ordering for configuration 5 2 2 FPGA Configuration Example 1 5 2 3 Key Steps for FPGA Configuration 5 2 4 FPGA Configuration using FUSE Probe D 2 5 FPGA Configuration using D IM EScript 5 3 FPGA Configuration using the FUSE APIs 54 FPGA Configuration using DIME JTAG Chain 55 FPGA Configuration using uP JTAG Chain Clock Configuration 5 6 General Description 5 7 On board clocks 5 8 Source Descriptions 59 Using external clocks System Level Design 5 10 Design Partitioning 5 11 Interface Communications Bus 5 11 1 Interface to User FPGA Interface Core 5 11 2 Implementing the Comms Communications Mechanism 5 113 Comms Bus Protocol 5 12 DIME II Communication Bus Speeds Reference Guide Physical Layout 61 B
112. le 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 T able 80 Table 81 Table 82 Table 83 T able 84 Table 85 Table 86 Table 87 Table 88 T able 89 T able 90 T able 91 T able 92 T able 93 T able 94 T able 95 T able 96 T able 97 T able 98 T able 99 XtremeDSP Development Kit User Guide Adjacent OUT BUS Pinouts User FPGA 2V2000 PLINK Pinouts User FPGA 2V2000 PLINK Pinouts User FPGA 2V2000 User FPGA Specific Pinouts 2V 2000 User LED Pinouts User FPGA 2V2000 User LED Pinouts User FPGA 2V2000 ZBT Clock and Control Signals Pinouts 2V2000 ZBT Address Signals Pinouts Ban 2V2000 ZBT Data Signals Pinouts Bank 2V2000 ZBT Parity Bits Pinouts Bank 2V2000 Clock Signals at CLK FPGA 2V2000 Clock Feedback Signals 2V2000 Clocking Pinouts for DACs and ADCs DACs Signal Pinouts 2V2000 ADC Signal Pinouts 2V2000 User IO Header Pinouts 2V2000 Local Bus Pinouts 2V 3000 Adjacent IN BUS Pinouts User FPGA 2V3000 Adjacent OUT BUS Pinouts User FPGA 2V3000 PLINK Pinouts User FPGA 2V3000 PLINK Pinouts User FPGA 2V3000 User FPGA Specific Pinouts 2V3000 User LED Pinouts User FPGA 2V3000 Temperature Sensor Pinouts 2V3000 ZBT Clock and Control Signals Pinouts Bank ZBT Address Signals Pinouts Bank ZBT Data Signals Pinouts Bank ZBT Parity Bits Pinouts Bank Clock Signals
113. led for the BenADDA module However in order to make full use of the module s potential the following software components are recommended e DIME II Carrier Card Software e FPGA Synthesis Software e Xilinx FPGA Implementation Software e HDL Simulation Software NT107 0132 Issue 9 23 05 2003 www nallatech com 71 XtremeDSP Development Kit User Guide FIANE TT 72 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI Implementation Guide XtremeDSP Development Kit User Guide Section 9 This part ofthe User Guide contains information on how to use the BenADDA module In this Section FPGA Configuration FPGA Application Design Example Application 1 Example Application 2 N T107 0132 Issue 9 23 05 2003 www nallatech com 73 XtremeDSP Development Kit User Guide DIME 74 FPGA Configuration In this Section FPGA Configuration using the FUSE Software GUI FPGA Configuration using the FUSE Software API 9 1 FPGA Configuration The User FPGA on the BenADDA can be configured via the following methods Using the FUSE Software GUI Graphical User Interface Using DIMEScript Using FUSE Software APIs 9 2 FPGA Configuration using FUSE The FUSE Software provides the following functionality Configuring FPGAs on the BenADDA Controlling reset signals Controlling programmable clock frequencies Sending data to designs running in the User FPGA Reading data from designs running in the
114. ll load up the FUSE configuration and probe tool Use this tool to open the BenD SPK See the FUSE System Software User Guide for more details on how to do this This installation also covers LINUX support for the BenADDA module start up This be done by typing the command gt insmod windrvror putting this command in the start up script etc profile N ote also that this must be done with root privilege The device created dev windrvr has root access For other users the permissions will have to be changed 4 N ote that the driver is a reloadable module which should be installed at 30 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide Section 5 Implementation Guide In this Section FPGA Configuration Clock Configuration 5 1 FPGA Configuration O ptions Any FPGAs on the DIME II module can be configured via a variety of methods Using the FUSE Software GUI Graphical User Interface Using DIMEScript Using FUSE Software APIs Using an external JTAG programmer via the ALT JTAG chain and pin header Additionally on module FPGAs can also be configured as follows Usingexternal JTAG programmer via the uP JTAG chain and pin header assuming the module supports uP JTAG 5 2 FPGA Configuration using FUSE The FUSE Software provides the following functionality Configuring FPGAs on DIME II modules Controlling reset signals Controlling pr
115. lopment Kit is shown in Figure 21 PCI USB Interface in BenONE FPGA FIFO FIFO e Nallatech Low Level DIME II Module PCI BUS i e BenADDA External Sources Software running on host PC XtremeD SP D evelopment Kit eee eee eee eee eee ee eee eee eee ee eee ee ee eee eee eee eee eee eee eee eee eee Lee eee eee ee eee eee eee eee ee ee eee eee eee ee ee eee eee eee eee ee eee eee eee eee ee eee eee eee eee ee eee eee ee eee eee eee eee eee eee ee eee eee eee eee eee eee ee ee eee ee eee eee eee eee ee ee eee ey Figure 78 XtremeDSP Development Kit Design Partitioning The Green blocks do not require any further design from a user perspective The interface is pre configured with either PCI or USB and the external sources are assumed to be in place The user needs to design application designs for any FPGAs on the hosted DIME II module the BenADDA in this case The Software running on the host PC is available as a pre designed GUI For users who require additional functionality and wish to have their own software front end the FUSE Software Library provides functions for use in application programs These facilitate functionality such as FPGA configuration reset clock speed setting data transfer In order to make use of these software interfacing functions for specific data transfer to thei
116. lowing busses provide a robust infrastructure for these communications Adjacent In Bus Adjacent O ut Bus Comm Links 0 7 busses Local Bus GP IO Bus The infrastructure of these communication busses is described in the relevant Motherboard U ser G uide Communication Bus 2 250 2V 1000 FG456 2V2000 2V3000 2V3000 2V8000 FG456 FG676 FF1152 Comm Link 2 12 bits 12 bits 12 bits 12 bits www nallatech com NT107 0132 Issue 9 23 05 2003 ERE EES ote SR Development EU Communication Bus 2V250 2V1000 FG456 2V2000 2V3000 2V3000 2V8000 FG456 FG 676 FF1152 T able 23 outlines the size of each communication bus relative to FPG size Communication Bus 2V250 i 2V1000 FG456 2V2000 2V3000 23000 2V8000 FG456 Foo FF1152 Table 23 Communication Bus Summary 10 8 3 DIME II System Clocks The BenADDA has three system clocks available for use in the User FPGA CLKA CLKB and CLKC All of these clock signals are generated on the DIME II motherboard and are routed into the module site where the BenADDA is placed Generally these C locks can be freely controlled by the user are routed to Global Clock pins to provide maximum flexibility on the User FPGA However it should be noted that therefore that the available functionality of these DIME II clocks is determined by carrier card W hen the BenADDA is fitted to the BenO N E carrier as in the XtremeD SP kit it should be noted that the available
117. lusion of a System Generator set of blocks to produce a sample QAM source for demonstration purposes and connecting the output from the carrier recovery stage to the DACs on the X tremeD SP kit The example is stored in install folder examples sysgen gqam full_ model packages ne supports a FF1152 and one 676 Note that the X C2V3000 Virtex ll part is Supported in both packages Therefore care should be taken when selecting bitfiles Please note that the BenADDA supports two variants that support different FPGA for configuration that they are indeed for the correct target FPG package N T107 0132 Issue 9 23 05 2003 www nallatech com 93 XtremeDSP Development Kit User Guide DIMETT 9 12 Functional description The model is shown below in Figure 50 Figure 50 Modified sygen qam16 mdl The DACs are connected as shown from the output of the carrier recovery stage ww EE pem m T R F B T s m pm Figure 51 Modified Carrier Recovery Subsystem The internal of the DACs subsystem is shown in Figure 52 Please note that the actual output from the System Generator design is signed 2 s complement but the DAC s interpret an input value of 0 to be 1V and 2 to be 1V Therefore the conversion is necessary A part from this conversion there are other control signals which are used to set the DACs operation mode such as the DIV and MOD control signals D etails of these options ar
118. lution at the output of the AD 6644 105 3 ADC Clocking As with the DACs each ADC device Is clocked directly by an independent differential LVPECL signal This LVPECL signal is driven from a second on board FPGA CLK FPGA solely dedicated to managing the various methods for clocking each ADC and DAC device The speed at which the ADCs are clocked is dependent on what bit file is assigned to this dedicated CLK FPGA 110 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide Please refer to Section 10 6 Clockingthe DAC and ADC devices for a full description of the clocking options available 10 6 Clocking the DACs andADCs CLK FPGA 10 6 1 Overview of various Clocking Methods The populated BenADDA has a total of 6 methods for clocking the DACs and ADCs User external Clock source via MC X connector On board Oscillator or 274 External Clock source via MCX connector This is a special build Option and can be chosen instead of the on board oscillator 4User programmable clocks from on board User FPGA Can either be used as 4 single ended Signals R 2 differential signals All the above clock signals are fed directly into a second on board FPGA CLK FPGA This CLK FPGA is a Virtex ll XC 2V80 or XC2V40 and is solely dedicated to the use of clocks Figure 67 gives an overview of the CLK FPGA BenADDA CLK FPGA LVPECL to the DACs External and CLK Socketed IL TE
119. m Die Sira Cog Leio EE im Fart om adim mi ra F dien HER EQ UC galli guber Figure 46 Math Functions Folder 88 www nallatech com Him NT107 0132 Issue 9 23 05 2003 To configure this component double click the name in the top right window to bring up a dialogue box From here it is also possible to bring up the component s data sheet which explains general operation and customisable options Figure 47 shows the options chosen for this design Figure 47 Sine C osine Look up Table nce the options have been selected click Generate to save the net list into the design folder NT107 0132 Issue 9 23 05 2003 www nallatech com 89 XtremeDSP Development Kit User Guide 9 9 2 Multiplier Component The multiplier component can be created in a similar way In the Target Family window double click the Math Functions folder and select the sub folder Multipliers Then double click the component Multiplier in the Contents of window as shown in Figure 48 Gets Tar HL le kaimi fr ELLE F is B rius d ark w hi DLE a TE iyu Bh HE E irure dam l bre Lene Lipie B n barene H Skrape Eran Ep REG Corbett d mires Liri ia ag he spe EEE Pq ig Terek ce ge Figure 48 Multiplier folder C onfigure this c
120. m 53 XtremeDSP Development Kit User Guide DIME 6 2 2 Modular programmable power supply PPS Using on board DC DC converters dynamic adjustment of the voltages applied to the module slot is possible reacting as required for different modules within the DIME II range Each supply is capable of supplying voltages in the range 1V to 3 3V at a maximum current of 15A abs max The PCI FPGA has a dedicated power supply fixed at 2 5V DIME II Module Slot 3 Amp 2 5V Power Supply 4 PPSs 15 Amps on each supply Figure 28 Programmable Power Supplies on the BenONE PCI It should be noted that no user intervention is required to set up the PPSs these will be automatically configured by the system The PPS that supplies the core voltage to the FPGA can supply up to 15A on any of the core FPGA power supplies In this situation consideration of system power supplying the PPP s should be made Additionally the end user should consider the thermal capability of the FPGA Please refer to appropriate X ilinx resources 6 3 Clock Circuit The following diagram provides a basic overview of the BenO N E clock circuit PCI CLK Prog Oscillator Clock 0 DIME II PCIFPGA SLOT Prog Clock 2 Oscillator Connector Figure 29 BenONE PCI Clock Circuit 54 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide 6 4 Reset and LEDs 6 4 1 Reset The configuration of the res
121. mbering I 5 2 3 Key Steps for FPGA Configuration W hen developing applications incorporating FPGA configuration using FU SE APIs or DIMEScript there are a number of key steps that need to be performed The key steps are shown here as an example In the example the FUSE C C API is used but the principle is the same for any of the FUSE APIs or DIMEScript Further and more detailed explanations are available in the API User Guides or DIMEScript User Guide To communicate with the BenO NE PCI the software must find the card in the host system This can be achieved by using the DIME LocateCard int LocateType DWORD MBType void LocateT ypeArgs DW ORD DriverVersion DW ORD Flags function Various arguments required by the function to locate the card For example LocateType and MBType respectively determine which interface and motherboard type should be searched for Once the software has found the BenONE PCI the next step is to open the card using DIME OpenCard LOCATE HANDLE LocateHandle int CardN umber DW ORD Flags This is required to open the card and performs all the necessary set up procedures in order to interface to the BenO NE This function requires several arguments to open the card LocateH andle is the handle returned by the DIME LocateC ard function CardN umber is the index of the card within the locate handle that the user wishes to open while Flags is a parameter which allows users to customise the card NT10
122. me C onnector 2V3000 2V6000 PIN No PIN No PIN No PIN No PB6 R4 1 LBUS lt 4 gt LBUS lt 36 gt PB42 K2 LBUS lt 6 gt PB8 N 4 LBUS 38 44 L1 z z LBUS lt 16 gt PB19 05 lt 48 gt 55 3 4 LBUS lt 15 gt PB18 3 LBUS lt 47 gt PB54 3 LBUS lt 17 gt PB20 4 LBU S lt 49 gt PB56 LBU S lt 18 gt PB21 LBU S lt 50 gt PB57 LBUS lt 19 gt PB22 LBUS lt 51 gt PB58 E 160 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI LBUS lt 29 gt PB34 Signal Name XtremeDSP Development Kit User Guide User FPGA 2V3000 2V 6000 PIN No Dime ll C onnector PIN No Signal Connector PIN No 2V3000 2V6000 PIN No Dime ll User FPGA LBUS lt 31 gt PB36 Table 91 Local Bus Pinouts 2V3000 6000 Adjacent IN Bus User FPGA communications AKT GCLKOP ADJIN lt 3 gt w ADJIN lt 12 gt n NT107 0132 Issue 9 23 05 2003 Signal User FPGA 2V3000 2V6000 PIN No Dime ll User FPGA Connector PIN No Signal Name Connector 2V3000 2V6000 PIN No PIN No Dime ll 32 10 ADJIN lt 35 gt 68 V10 6 Y6 AB5 5 Y9 AA9 AC6 A A A F F ADJIN lt 44 gt SA4 PA42 5 B6 7 8 5 ADJIN lt 54 gt 4 E4 B9 1 E2 E6 E9 AC10 AB10 i c 10 0 7 7 6 8 9 2 P5 R P1 8 U U 6 U U V6 W V Table 92 Adjacent IN BUS Pinouts User FPGA
123. n Card 2 This will open the dialog box for selecting the type of card and interface over which you wish to open In this case please select USB and All card types as show in Figure 7 3 Press the Locate Cards button to carry out the search for cards on the selected interface 4 You should then be presented with the location results specifying what cards were found on the selected interface W ith the kit you should see the BenO NE listed Figure 7 Locate Cards prompt Detected Cards 5 Press the O pen Cards button to open the selected cards These will then be listed in the card viewer in the FUSE Probe GUI In the case of the DSP kit you will see the BenADDA and the BenO NE listed in the tree structure window 12 www nallatech com NT107 0132 Issue 9 23 05 2003 EE DER Orr KE 9 dA i i am t om Figure 8 FUSE Probe Tool with Open Cards O nce the BenO NE and BenADDA have been opened the power LEDs for the supplies used change from red to green as shown below in Figure 9 _ B 7 kas Figure 9 Power LEDs Note that if a power supply is not used then the power indicator for that supply will remain RED indicating it is not switched on For example on the BenADDA only three supplies are required and so only three of the four LEDs will change from red to green NT107 0
124. n board clocks A B amp C to be outputted to a pin header for use externally Also provided is the Clock Input functionality enabling external clocks to be inputted onto the XtremeD SP Development Kit from the clock input connector for on board use or an external clock as the external clock connector is located under the fixed frequency XtremeD SP Development Kit will allow either a fixed frequency oscillator to be used oscillator socket 40 www nallatech com NT107 0132 Issue 9 23 05 2003 EE EEE RK NEEDS RDP KU SRS REN System Level Design Design Partitioning DIME II Communication Bus Speeds 5 10 Design Partitioning The XtremeDSP Development Kit allows the user to partition the functionality of their application between software and hardware easily and effectively Below the design partitioning of the X tremeD SP Development Kit is shown in Figure 21 PCI USB Interface in i BenONE FPGA DIME II Module Nallatech FIFO i e BenADDA Low Level Drivers PCI BUS EO M Software running on host PC Host PC XtremeD SP Development Kit Figure 21 XtremeDSP Development Kit Design Partitioning The green blocks do not require any further design from a user perspective The PCI interface is pre configured and the external sources are assumed to be in place The user needs to design application designs for any FPGAs the hosted DIME II module The software running on the host PC is available as a
125. n mode level of the differential output is set by VO CM thereby level shifting the input signal suitable for driving the CLK FPGA VO CM is set at 1 25V to comply with the typical VIC M value for the Virtex Il FPGA using LVDS voltage specifications The Differential Driver Output Voltage for LVDS is specified as 250 450mV typ 350mV It is therefore advised to limit the magnitude of the clock input signal to 125mVpp 225mV pp The maximum input signal the CLK_FPGA can accommodate is 3 3Vpp In order to ensure that the FPGA cannot be accidentally blown the supply of the AD 8131 is limited between OV to 3 3V Using a DC bias Clock Source Customer Specified Build The BenAD DA has a second external clock source option that feeds straight to the FPGA This is a special build option and must be specified at time of ordering This second option will supply an external clock signal straight to the CLK_FPGA Ifthis option is chosen a signal within the range of OV to 3 3V MUST BE USED Ifa signal lower than OV or greater than 3 3V Is supplied while in this configuration the Clock FPGA will be damaged It is recommended that the LVTTL signalling standard be used W hen using this set up for the external clock circuit it is still possible to use a single ended source or a differential source as long as the signal is within the operating ranges of the CLK_ FPGA Pinouts for External Clock Source Clock Signal Description Signal Nam
126. ncluded in future versions of this document Information within this manual may include technical typing or printing inaccuracies or errors and no liability will arise there from This User Guide is supplied without warranty or condition either expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose regarding the information provided herein Under no circumstances will N allatech Limited be liable for any incidental or consequential damage or expense of any kind including but not limited to loss of profits arising in connection with the use of the information provided herein 173 XtremeDSP Development Kit User Guide Index F BI 109 FPGA Application D 5 0 76 EE 109 FPGA 31 74 CAO CK REE 110 9 33 Signal Pinouts 135 141 170 using DIME JTAG 36 Theory of 110 USING DIMESCEIDE itii S ltem 35 usma 35 2 using the FUSE 5 35 B using uP JTAG 37 BenADDA FPGA Configuration using FU SE 74 Key F
127. nector User FPGA 2V3000F G 676 PIN No KD jo fa ADJOUT lt 26 gt PD58 SD 12 ADJOUT lt 27 gt ADJO UT 59 ADJOUT lt 28 gt PD60 r SD 13 ADJOUT lt 29 gt PD61 ADJOUT lt 30 gt PD62 ADJOUT lt 61 gt SC12 026 ADJOUT lt 62 gt SD14 ADJOUT lt 31 gt PD63 1 5 ADJOUT lt 63 gt SC13 Table 75 Adjacent OUT BUS Pinouts User FPGA 2V3000 PLINKS connected to the User FPGA PLINKS 0 1 2 and 3 Signal Name Dime ll Connector PIN No Dime ll Connector PIN No User FPGA 2V3000FG 676 PIN No Signal Name User FPGA 2vV3000FG 676 PIN No PPOLK lt 2 gt PA4 H13 PP2LK lt 2 gt PD 4 H14 poe foe PPOLK lt 6 gt PP2LK lt 6 gt D15 PPOLK 8 PP2LK 8 PPOLK 9 PA12 PP2LK 9 PD 12 PPOLK 10 PA13 E PP2LK 10 PD 13 PPOLK 11 PA14 E6 PP2LK lt 11 gt PD14 PP1LK 0 PA15 PPILK lt 1 gt PA16 PPILK 2 PA17 PP3LK lt 0 gt PD 15 PP1LK 3 18 PP3LK 3 PD 18 4 PA20 PPILK lt 5 gt PA21 PP1LK 6 PA22 PPILK lt gt PA23 PPILK 8 PA24 1 9 25 PP1LK 10 26 NC Paka PD20 NC PP3LK lt gt PD 23 PP3LK 8 PD 24 PP3LK 9 PD 25 NC Pe KL uw JE iS I NC NC NC NC NC 7 11 lt 11 gt 27 PP3LK lt 11 gt PD27 NT107 0132 Issue 9 23 05 2003
128. nt Kit User Guide DIMET 11 5 3 Clock signals relating to DACs and ADCs Clock sources available at CLK FPGA Signal Name CLK FPGA 2V80 Pin User FPGA 2V1000 Signal Description No PIN No Op Amp GC LK6S External CLK source via Op_Amp Op Ampl 6 GCLK7P Complement of External CLK source via Op Amp EXT CLK 8 GCLKOS External CLK source straight to CLK FPGA EXT CLKI 8 GC LK1P Complement of External CLK source straight to CLK FPGA GEN n LKD 7 GCLK7S Generated Clock D EXT2_ EXT2CLIK LK 7 GCLK D7 GCLK5 N Na 2nd 244 External Clock Clock EXT 2_ LE A6 E EE ER of 2nd External Clock Table 49 Clock Signals at CLK FPGA 2V1000 Clock Feedback signals Signal Name FPGA 2V80 Pin User FPGA 2V1000 Signal Description PIN No C LK2 FB AA11 Feedback to User FPGA Table 50 Clock Feedback Signals 2V1000 Clocking Pinouts for DACs and ADCs Signal Name CLK FPGA 2V80 Pin No Breen Acc um Table 51 Clocking Pinouts for DACs and ADCs 140 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide 11 5 4 DAC Signal Pinouts Signal Name DAC 1 User FPGA 2V1000 Signal Name DAC 2 User FPGA 2V1000 PIN No PIN No DAC1 D lt 1 gt R22 DAC2 D lt 1 gt DAC1 D lt 8 gt DAC2 D lt 8 gt W 21 DAC1 D lt 9 gt DAC2 D lt 9 gt W 20 Wn DAC1 PLLLOCK DAC2 PLLLOCK DAC1 RESET DAC2 R
129. odule is identified as device 0 on that module For each device upstream on the JTAG chain the index is incremented Figure 72 shows the device numbers that are assigned for this BenADDA module CLK FPGA XC2V80 JTAG DEVICE 0 USER FPGA XC2V250 XC2V6000 JTAG DEVICE Figure 72 JTAG Device Indexing 109 3 Config DONE The DIME II standard allows a design to be implemented based on the status of the entire system CONFIG DONE signal provides built in control that can be used if the System D esigner wishes This feature allows a designer to synchronise all aspects of the complete system NT107 0132 Issue 9 23 05 2003 www nallatech com 121 XtremeDSP Development Kit User Guide FIA ET MMUN22ILTI DIME II CONNECTOR CONFIG DONE CLKFPGA to DIME II Motherboard i PC40 FPGA_DONE SPON 4x7 MMUN221LTI CONFIG DONE_USERFPGA Figure 73 CONFIG DONE Circuit Figure 73 shows the set up of the CONFIGURATION DONE operation on the BenADDA The FPGA DONE signal to the two on board FPGAs determines the status ofthe FPGAs on the module The FPGA DON E signal is connected directly to the carrier motherboard where it is then connected to all other module sites and the PCI FPGA This signal has a weak pull up applied to it on the motherboard When the FPGAs the BenADDA NOT configured the base of the two transistors MMUN221LT1 will be switched on by the 3 3V pull up W ith the base of the transisto
130. ogrammable clock frequencies Sending data to designs running in the User FPGA A Reading data from designs running in the User FPGA Resetting PCI FIFOs This functionality is provided in the following guises FUSE Probe Application DIMEScript FUSE Software development APIs 5 2 1 Device Module ordering for configuration W hen configuring FPGAs using FUSE Software it is necessary to use Module ID and Device ID numbers to target the correct FPGAs for configuration as most systems will have multiple FPGAs The NT107 0132 Issue 9 23 05 2003 www nallatech com 31 XtremeDSP Development Kit User Guide 32 only exception to this is when using the FUSE GUI where the software allows FPGAs to be targeted graphically Each FPGA must be uniquely identified in order that the user can target the correct bit file to each device The system used for identifying FPGAs and also any PRO Ms in the DIME JTAG chain consists of a module ID identifying the module the FPGA is on and a device ID identifying the device within that module The module ID and device ID are determined by the order in which the devices are configured and how many modules and devices are present The module ID always starts at 0 and increments for each additional module to be configured It should be noted therefore that the maximum module ID depends upon the number of modules fitted The device ID works in a similar way to the module ID The device ID always sta
131. omponent as shown in Figure 49 90 www nallatech com 21 7 OR bog 17 NT107 0132 Issue 9 23 05 2003 DIMETIL XtremeDSP Development Kit User Guide Eh seem eR HET Figure 49 Multiplier C onfiguration Settings After choosing the appropriate settings click Generate to save the net list into the design folder W hen the sine wave and multiplier components have been created close X ilinx Core Generator and return to Xilinx ISE To declare and instantiate these components in the code click the light bulb in the top right toolbar to bring up the language templates window In the language templates window expand the Coregen folder and then expand the relevant language folder VHDL or VERILO W ithin each of these folders there is atemplate for each component which contains a declaration and an instantiation These can simply be copied and pasted into your code NT107 0132 Issue 9 23 05 2003 www nallatech com 91 XtremeDSP Development Kit User Guide DINIE 9 10 Configuring the modulator example The card can be opened and configured in the same way as described for the ADC to DAC feed through design on page 82 8 The bit file for the Clock FPGA is located at the path lt CDROM D rive gt Examples C lock Designs PCB V2Yosc clock 2v80 bit on XtremeDSP Development Kit CD The bit file for the Main FPGA can be f
132. on Settings C ont The common settings shown in Figure 35 and Figure 36 are intended for illustrative purposes and are captures taken from X ilinx Foundation implementation tools The figure shows the location of each of the options and shows a common selection of settings that have been used to create the example bit files provided with the product They do not take into account any additional requirements of the design which may apply in specific user applications Failure to enable readback will result in the value being returned from the status register of 0x0 This will manifest itself in the configuration software reporting an error of DONE LOW INIT LOW No CRC errors If reconfiguration has not been enabled and you configure once it is necessary to cycle the power to the FPGAs in order to clear the security protection on the FPGA 80 www nallatech com NT107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide Example Application 1 This Section covers ADC to DAC feed through design 9 5 Introduction The screenshots in this Section display FPGA configuration procedures for aBenADDA module populated on a BenO NE motherboard However these procedures can be applied to any DIME II motherboard This Section necessitates that all software required by the BenADDA has been installed as previously detailed and the operating system running on the host PC is either W indows 9x N T Me 2000
133. on how to use the APIs are provided in the relevant FUSE User Guide NT107 0132 Issue 9 23 05 2003 www nallatech com 35 XtremeDSP Development Kit User Guide 5 4 FPGA Configuration using DIME JTAG Chain The DIME JTAG chain is the principal JTAG chain on the BenO N E PCI and facilitates the configuration of the FPGAs on the DIME II module hosted on the BenO N E PCI The DIME JTAG Chain is driven by the PCI FPGA or can be driven from the ALT JTAG pin header on the BenO NE PCI via a JTAG programmer such as the X ilinx Parallel IIl programmer Therefore this is where you would connect the Parallel IIl or IV cables in order to use products such as C hipscopelLA The DIME JTAG chain has built in switches which only switch a D IM E I module slot into the chain if a module is populated therefore if a module is not populated in a slot the chain skips that slot If an external power supply is required for a programmer 3 3 V supply is available on the populated as the User FPGA or on modules DIME JTAG Connector A maximum supply of 3 3 V should be used to supply a configuration device as higher voltages will irreparably damage the Virtex E device The DIME JTAG chain connected to the DIME JTAG Header is the same as that used by Q the FUSE software during FPGA configuration If FUSE is being used a JTAG controller cannot be used during FPGA configuration using the software The DIME JTAG chain configuration is shown in
134. onnectors General Purpose I O Bus 4 General Purpose I O Bus 5 111 Interfacing via MCX connectors The BenADDA has five through hole MCX connectors that allow interfacing to and from the module All Analogue Input and O utput signals to the BenAD DA are conducted viafour MCX connectors onthe top of the module The fifth MCX connector is available to provide an input source for an external clock Figure 76 outlines the positioning of these connectors ADC2 Analogue Input External Clock DAC1 Input Analogue Output ADC1 Analogue Input DAC2 Analogue Output Figure 76 MCX connectors Figure 76 show there are two Analogue Input channels two Analogue O utput channels and one external clock source input NT107 0132 Issue 9 23 05 2003 www nallatech com 125 XtremeDSP Development Kit User Guide DIME 126 11 1 1 Interfacing to MCX connectors via supplied cable The BenADDA is supplied with cables that are suitable for connecting between the on board MCX connectors and a user input output BNC connection BenADDA MCX to BNC Cable jen w 7 Internal Identity 100cm of RG 174 NT501 1340 Cable MCX Straight BNC Crimp Plug Crimp Plug Gold Figure 77 Diagram of supplied Cable Assembly The MCX connectors are a push fit design therefore the MCX crimp plug on the supplied cable pushes into the MCX connector 11 2 User 1O header Interfacing The BenADDA has a two pin 0 1th pitch header
135. or memory space Some of the bits of this bus are used to provide a software interface communication mechanism as described in Section 5 10 DIME II Bus Description P Link Bus 125 MHz 200MHz A 12 bit point to point communications bus W hen a Source Synchronous data transfer is employed a maximum frequency of 200 MHz may be achieved otherwise the maximum frequency possible is 125 MHz Adjacent Bus 150 MHz Due to the small transmission distance between adjacent buses a maximum frequency of 200 MHz may be achieved Local Bus 66 MHz This bus is common to and distributes to all DIME II modules and the User FPGA Speeds of 66 MHz may be realised Table 9 Bus Speeds NT107 0132 Issue 9 23 05 2003 www nallatech com 47 XtremeDSP Development Kit User Guide FIANE TT 48 www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide Section 6 Reference Guide In this Section Physical Layout Hardware Features Build Options and Jumper Settings Pin out Information N T107 0132 Issue 9 23 05 2003 www nallatech com 49 XtremeDSP Development Kit User Guide DIME Physical Layout In this Section Physical features of the BenO NE in the XtremeD SP Development Kit are identified 61 PCI Physical Layout front Plink Standalone Header Power DIME Module Slot General Connector JTAG TEEST K K K K Power Supply pasas n TELD Nu
136. oring Signals Temperature Sensor 10 3 Digtal to Analogue Converter The BenADDA has two analogue output channels each provided with independent data and control signals from the FPGA Two sets of 14 bit wide data are fed to the two AD9772A devices each of which has an isolated supply and ground plane T he diagram below illustrates the interfacing between one ofthe DACs and the FPGA BenADDA FPGA DAC Interface Data 0 13 Xilinx Virtex ll User FPGA AD9772A 2 250 2 6000 Data Divide 0 1 CLK FPGA Virtex II FPGA 2V40 2V80 Clock Feedback Figure 56 Functional Diagram of DAC Interface AD9772A device offers 14 bit resolution and a sampling rate of 160MSPS Additional control signals exist between the DAC and the FPGA to enable full control of the DACs functionality The main features of the AD9772A are e 14 bit DAC resolution note that they are offset binary input e 160MSPS input data rate 100 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide e LVPECL clock inputs e Internal Phase Locked Loop PLL clock multiplier e Differential current outputs e Choice oftwo output configurations build option input should give an approx 1Volt output and a 2 1 value input should give an approx Q Please note that the input to the DACS is offset binary format This means that a 0 value 1V output N ote that the input to the DACs is therefore n
137. orised use including without limitation accident air conditioning humidity control or other environmental conditions Under no circumstances will the company be liable for any incidental or consequential damage or expense of any kind including but not limited to personal injuries and loss of profits arising in connection with any contract or with the use abuse unsafe use or inability to use the companies goods The company s maximum liability shall not exceed and the customer s remedy is limited to either i repair or replacement ofthe defective part or product or at the companies option ii return of the product and refund ofthe purchase price and such remedy shall be the customer s entire and exclusive remedy W arranty of the software written by the company shall be limited to 90 days warranty that the media is free from defects and no warranty express or implied is given that the computer software will be free from error or will meet the specification requirements of the buyer The terms of any warranty offered by a third party whose software is supplied by the company will be honoured by the company exactly No other warranty is offered by the company on these products Return of faulty equipment after the warranty period has expired the company at its discretion make a quotation for repair of the equipment or declare that the equipment is beyond repair PASSING OF RISK AND TITLE The passing of risk for any supply
138. ot two s complement The BenADDA supports two output configurations a single ended DC coupled output and a differential directly coupled output These are both described later in this Section The internal PLL clock multiplier of the AD9772A is also described to provide you with an insight into the internal operations of the DAC 10 3 1 DAC Architecture The AD9772A s architecture comprises four key areas as shown below CLK Clock Distribution LK gt p and Mode Select MUX Control 14 bit d Edge EN Triggered Interpolation 4 bit DAC x Current Latches Filter Outputs BenADDA AD9772A Architecture Figure 57 AD9772 Architecture Figure 57 shows the internal architecture of the AD 97724 Initially the user feeds the14 bits of data into the AD9772A This data is latched into edge triggered latches on the rising edge of the reference clock interpolated by a factor of 2 by the digital filter and then fed to the 14 bit DAC The filter characteristic can be set to either low pass or high pass for baseband and IF applications respectively The MODO input is used to control this function of the AD9772A The interpolated data can feed the DAC directly or undergo a zero stuffing process enabled using MO D1 This process involves inserting a mid scale sample after every data sample originating from the digital filter which improves the passband flatness of the DAC and also allows for the extraction of higher frequency imag
139. ound at the path lt C DRO MDrive gt Examples Modulator D SP KitV packages ne supports a FF1152 and one 676 Note that the X C2V3000 Virtex ll part is supported in both packages Therefore care should be taken when selecting bitfiles Please note that the BenADDA supports two variants that support different FPGA for configuration that they are indeed for the correct target FPG package These bit files have the naming convention modulator 2v bit where represents the device size and represents the package Ensure the device is configured with the correct bitfile to avoid any damage to the FPGA After both devices have been configured select the reset tab in the bottom left of the main screen You should tick both reset check boxes and then un tick both boxes to carry out a full reset on the system W ith Engineering Silicon X C2V3000 FPGAS configuration procedures should be carried out twice order to successfully start up A LED flash pattern should now be displayed the LEDs and any data fed into the ADC should be modulated and seen at the output of the DAC 92 www nallatech com NT107 0132 Issue 9 23 05 2003 PETE erie a Developer MEU Example Application 3 In this Section SysgenQAM16 Output to DACs 9 11 Introduction The model is simply a variant on the sysgen qam16 model that is included with the demos supplied with System Generator 2 2 The only modifications are the inc
140. outputs Linear or Interleaved Burst modes Burst feature optional Pin function compatibility with 2Mb 4Mb 8Mb 16Mb 32Mb 64Mb amp 128Mb ZBT SRAM 1077 2 7 SRAM Clocking The ZBT SRAM is clocked directly by an independent output from the FPGA Each Bank has its own clock signal that has been de skewed within the User FPGA This ensures that the clock at the ZBT SRAM Banks and the feedback pin have coincident clock edges with minimum skew Ultimately this process ensures that the internal logic is clocked in phase with the data entering the ZBT chips Driving the ZBT SRAM clock from the FPGA ensures maximum flexibility in the clocking mechanism during system design as it can be derived from any of the DIME II system clocks CLKA or CLKC which enter the module through the DIME II connectors The pinouts for the various clock signals associated with the ZBTs are shown in Table 22 Signal Name User FPGA Pin No 2V3000 2V6000 ZBTA FB IN E18 GCLK4S 2 CLK D17 ZBTB FB IN E16 GCLK2S Table 22 Clock signals for ZBT Memory 10 7 3 ZBT SRAM Clocking Example An example of atypical clock arrangement for driving the ZBT SRAM with the input clock at the FPGA e g CLKA CLKB or CLKC is illustrated in Figure 70 116 www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide DIME II Clock System CLK Distribution IBUFG 2 De skewed for ZBTA CLK clocking
141. ower supply accepts mains input from 90 264Vac Apply power to the BenO N E card see Figure 1 Connect the BenO card to your host PC with the supplied USB cable Found New Hardware Window will appear followed by the Step 1 screen or similar Press N ext Step 2 screen should appear Choose the top option search for suitable drivers option then press N ext Step 3 screen should appear If not already ticked select the CD ROM choice Press N ext W indows will inform you that it has located a valid USB driver BenO N E PCI Loader Firmware Press Next If you are presented with an intermediate error that it is not a Windows Certified driver please continue anyway Step 4 screen should appear indicating that the installation has been completed successfully Press Finish At this stage you will notice that one of the bank of 3 LEDs on the BenONE will switch off to indicate that the hardware is successfully initialised in terms of the USB interfacing to the PC To ensure correct installation you may view the Device Manager window This is accessed by a right mouse click on the My Computer Icon on your desktop Select Properties from the drop down list that appears Click on the Device Manager button or TAB Screen opposite will appear At the bottom ofthe tree structure expand the Universal Serial Bus Controllers branch You should see BenONE PCI Firmware Loader driver present Remove the USB
142. own list that appears 2 Click on the Device Manager button or TAB 3 The screen below will appear At the bottom of the tree structure expand the Universal Serial Bus Controllers branch You should see BenO N E Firmware Loader driver present 4 Removing the USB cable from either the host PC or the BenO NE should dynamically remove the driver from this branch 5 Reconnect the cable The driver should be added to this branch only this time it should read BenO NE If the driver reads BenO N E Firmware Loader remove the USB cable then remove power from the BenO N E card 6 Reconnect the power cable and USB cable to the the driver should now read BenO An additional visual indicator of the card being successfully initialised over USB is the bank of 3 LEDs on the BenO N E Initially when the card boots on power being applied all three of these LEDs should be illuminated W hen the USB cable is connected and the OS successfully communicates with the USB interface on the board one of these LEDs will turn off as shown below in Figure 12 This process normally takes around 5 seconds If the LED never turns off on connection of the U SB cable there are two common causes 1 The USB drivers have not be installed properly as described in U SB Driver Installation on page 2 28 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETT XtremeDSP Development Kit User Guide 2 It isnot
143. p p output signal swing 10 4 3 DAC Clocking Each DAC device is clocked directly by an independent differential LVPEC L signal This LVPEC L signal is driven from a second on board FPGA CLK FPGA The second FPGA is solely dedicated to managing the clocking methods for each DAC and ADC device The speeds at which the DACs are clocked depend on what bit file is assigned to this dedicated CLK FPGA Please refer to Section 10 6 Clocking the DACs and ADCs CLK FPGA for a full description of the clocking options available Www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI 10 5 XtremeDSP Development Kit User Guide Analogue to Digital Converter Throughout this Section all diagrams and text will refer to the AD 6644 However this information is also applicable to the AD6645 The main difference between these devices is the sampling rate AD 6644 samples at 65 5 5 A D 6645 samples at 80MSPS 105MSPS The BenADDA has two analogue input channels with each channel providing independent data and control signals to the FPGA Two sets of 14 bit wide data are fed from two A D 6644 devices each of which has an isolated supply and ground plane Figure 65 illustrates the interfacing between one of the ADCs and the FPGA BenADDA ADC FPGA Interface Xilinx Virtex ll User FPGA AD6644 pu XC2V250 2V6000 Data CLK FPGA Virtex Ill FPGA 2V40 2V80 Clock Feedback Figure 65 Functional Diagram of DA
144. package contains multiple versions of the Licensed Materials then you may only use the Licensed Materials in one version on a single computer In no event may you use two copies of the Licensed Materials at the same time 4 Warranty N allatech Ltd warrants the media to be free from defects in material and workmanship and that the software will substantially conform to the related documentation for a period of ninety 90 days after the date of your purchase N allatech Ltd does not warrant that the Licensed Materials will be free from error or will meet your specific requirements 5 Limitations N allatech Ltd makes no warranty or condition either expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose regarding the Licensed Materials N either N allatech Ltd nor any applicable Licenser will be liable for any incidental or consequential damages including but not limited to lost profits 6 Export Control The Software is subject to the export control laws ofthe U nited States and ofthe United Kingdom The Software may not be shipped transferred or re exported directly or indirectly into any country prohibited by the United States Export Administration Act 1969 as amended and the regulations there under or be used for any purpose prohibited by the A ct User Guide Conditions Information in this User Guide is subject to change without notice Any changes will be i
145. pment Kit The BenO N E also performs housekeeping functions of the Programmable Power Supplies and PCI bus Finally connection to further N allatech motherboards and modules is made possible by the inclusion of a pin header connection direct to the module site 3 2 Key Features The key features of the BenO N E PCI are PCI Control Xilinx Spartan Il FPGA pre configured with PCI Control Firmware Single DIME II module expansion slot 32 bit 33MHz PCI interface with expansion to 64bit 33Mhz via firmware upgrade Two on board clock nets 2 Programmable clock sources 1 Fixed Oscillator socket Status LEDs JTAG configuration headers selectable pin headers Fixed or fully programmable power supplies Nallatech FUSE Software for FPGA configuration over PCI Nallatech FUSE Software Library for board interfacing amp control NT107 0132 Issue 9 23 05 2003 www nallatech com 19 XtremeDSP Development Kit User Guide DIMETT Build O ptions USBI II O Module interface Battery Backup for Virtex II Encryption Keys Compact Flash using X ilinx System Ace chipset External oscillator input via mini coax connector 3 3 Functional Diagram PCI Coma Ba 40 bir 12 bit Figure 10 BenONE PCI Functional Diagram 20 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Section 4 Installation Guide In this Section Hardware Installation
146. r NOTE W henaXC2V250 FPGA is populated on the BenAD DA the signals MO D DIV and PLLLO CK are not available for use via the FPGA Please refer to XC 2V250 FPGA DAC Control Signals below for details on how these control signals are connected for use NT107 0132 Issue 9 23 05 2003 www nallatech com 103 XtremeDSP Development Kit User Guide DIME 104 For more information on the zero stuffing process interpolation filter and all aspects of the AD 9772A device refer to the XtremeD SP Development Kit CD 10 3 3 XC2V250 FPGA DAC Control Signals The following Section is only appropriate to BenADDA s that have a X C2V250 on board User FPGA W hen an X C2V250 FPGA is populated on the BenADDA there is a physical limit to the number of U ser IO available which results in certain control and monitoring signals of the on board DACs being unavailable for use through the FPGA The signals no longer accessed through the FPGA are MODO MODI DIVO DIVI PLL LOCKED However the DACs can still be fully utilised by various jumpers The location of these jumpers on the PCB is shown below in Figure 59 BenADDA AD9772A Jumpers XC2V250 only oci Beer ont d oc CE pn d a fut RC gaj apr OF mar gm gt emt ms T BAKERS LS di t n wid k i 4 MODO JA DACI DACI DACI DAC2 DAC2 MODI 5 D
147. r designs certain signals must be connected into the design These signal are listed in the Interface COMM Signal column in Table 27 and Table 28 A core for use in the user FPGA is provided to aid the process of integration and communication with these signals Please see PCI to User FPGA Interface Application note that is provided on the FUSE Software CD for further details Interface General Bus i User User User User User COMM Signal Name FPGA FPGA FPGA FPGA FPGA Signal 2V1000 2v2000 2v3000 2V3000 PENA mE FG676 FG676 6000 0 Pin No Pin No FF1152 Pin No NEN 20 GUN NEM NN NEN 2 ET 2 MN ADIO lt 10 gt LBU S lt 10 gt PB12 mr 1e es eo 2 m desc me D qoe po 5 125 sz C NN NN m n quu LEN NEN NEN LN LEN CJ 68 2 B 1 ge ue C www nallatech com NT107 0132 Issue 9 23 05 2003 DINIE XtremeDSP Development Kit User Guide User User User User FPGA FPGA FPGA FPGA 2V250 2V1000 2V3000 2V3000 FG456 FG456 FG676 FG676 6000 Pin No PIN No Pin No Pin No FF1152 Pin No K1 K4 L5 L4 L3 L2 M5 1 2 P6 AA4 3 L3 M5 1 2 6 r ms u usas mm 0 _ 5 LN LN M6 K3 M5 ADIO 27 LBUS lt 27 gt PB31 ADIO lt 28 gt LBUS lt 28 gt PB33 ADIO 29 LBUS 29 PB34 ADIO lt 30 gt LBUS lt 30 gt ADIO 31 LBUS 31 PB36 P5 Usos woms
148. reen marking on the PCB see Figure 74 The pin locations for the User LED signals are listed for each FPGA option in the following places For an XC2V250 FPGA see User LEDs on page 133 For an XC2V1000 FPGA see User LEDS on page 139 For XC2V3000 or XC2V6000 FPGA see User LEDs on page 165 10 10 Temperature Sensor The BenADDA can be supplied with various sizes of User FPGAs which can become very hot when running at full potential As a result the BenAD DA is fitted with a temperature device that monitors the heat levels within the User FPGA Figure 75 shows the BenADDA temperature sensor interface NT107 0132 Issue 9 23 05 2003 www nallatech com 123 XtremeDSP Development Kit User Guide DIMEJI BenADDA Temperatue Sensor Interface User FPGA Temperature Sensor Figure 75 Temperature Sensor Interface The Temperature Sensor used on the BenADDA is supplied from MAXIM Part Number 1617 For full details the specification of this device please refer to its datasheet 1617 which is supplied on the XtremeD SP D evelopment Kit CD Please note that this feature is not supplied as standard with the XtremeD SP Development Kit For more information on the temperature sensor please contact N allatech 124 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETT XtremeDSP Development Kit User Guide Section 11 Interfacing In this Section Interfacing via MCX c
149. reference designs are also made available on the Xilinx web site http www xilinx com dsp Figure 2 Kit Case and Contents 2 3 3 Specifications The dual channel high performance AD C s and DACs as well as the user programmable Virtex II FPGA are ideal for implementing high performance signal processing applications such as Software D efined Radio 3G W ireless networking HDTV or video imaging Motherboard BenONE card e Supports one DIME II slot for any DIME II Module e Spartan 2 FPGA for 3 3V 5V PCI or USB interface e Host interfacing via 3 3V 5V PCI 32 bit 33 MHz or USB v1 0 interfaces Daughter Board BenADDA module e Virtex Il user FPGA XC2V2000 4FG 456 e 2ADC channels AD664 ADC 14 bits up to 65 MSPS e 2DAC channels AD9772 DAC 14 bits up to 160M SPS Support for external clock on board oscillator and programmable clock ne bank of ZBT SSRAM 133Mhz 256K x16 bits NT107 0132 Issue 9 23 05 2003 www nallatech com 7 XtremeDSP Development Kit User Guide IDIAMETT 2 4 BenONE BenADDA connectivity The XtremeD SP kit consists of the BenO N E and the BenAD DA DIME II module The following diagram shows the connectivity between the BenO NE motherboard and a DIME II module site Spartan ll Interface FPGA Configured with Appropriate Interface Control Firmware i e USB PCI Programmable x Clock Source A Programmable Clock Source B Clock Crystal or External
150. rs switched on the FPGA DONE signal connected to the motherboard via the DIME II connector will be pulled LO W through the transistor Once the FPGA has been configured the user should send out a LOW signal on the appropriate CONFIG DONE pin i e a LOW would be driven out of B on the FPGA This turns the base of the transistor off and the FPGA DONE value is now subject to the status of the complete system Once all other FPGAs in the system are configured the FPGA DONE signal will be HIGH via the pull up on the motherboard However if one FPGA is not configured the FPGA DONE signal from that device will still be pulled LO W meaning that FPGA DONE for the entire system would be LOW The System designer will therefore be able to read the value of FPGA DONE via FUSE software at the IO B A input on the various FPGAs to determine the overall state of the system If the CONFIG DONE signal is to be utilised in a system the user should ensure that IO B is driven low once the FPGA has been successfully configured Alternatively if a system initialisation sequence is required then IO B B can be driven low after this The FPGA then polls IO B A to see that all other FPGAs in the system have been configured The pin locations for this Config DO NE signal are listed for each FPGA option in the following places For an XC2V250 FPGA see Section 11 4 2 DIME II control and monitoring signals on page 133 For anXC2V1
151. rts at 0 and increments for each additional device to be configured within a module or virtual module It should be noted therefore that the maximum device ID depends upon the number of device present The ordering of the module configuration on the BenO NE is shown in Figure 13 In order to clarify this concept some example configurations follow in this Section Example Devices on 5V PCI Sample Boot Module DIME II SLOT 0 Primary FPGA Device 2 3 3V PCI Boot PROM Device 1 Secondary FPGA Device 1 PSU Controller Device 0 BENONE PCI Figure 13 BenONE PCI JTAG Configuration within DIME Software www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI DIET XtremeDSP Development Kit User Guide 5 2 2 FPGA Configuration Example 1 Example Module 0 Devices on i Sample 5V PCI Boot I Module eter DIME II SLOT 0 Primary FPGA Device 2 3 3V PCI Boot PROM PnP Device 1 CPLD Device 0 Device 1 PSU gt B Controller Device 0 BENONE PCI Figure 14 Example configuration 1 Configuration example 1 assumes the DIME II slot to be populated and the module to have two FPGA devices The module ID and device ID numbers for this configuration are identified in Figure 14 and listed for each device A in Table 2 below FPGA Device Module ID Number Device ID Number 1 i Table 2 Example configuration 1 module and device ID nu
152. s for this FPGA can be found at the path lt CDROM Drive gt Examples Adc_to_Dac DSP_Kit and have the naming convention _2 bit where represents the device size and represents the package Ensure the device is configured with the correct bitfile to avoid any damage to the FPGA A LED flash pattern should now be displayed on the LEDs and any data fed into the ADC should be seen at the output ofthe DAC This data can also be viewed on an oscilloscope After both devices have been configured select the reset tab in the bottom left of the main screen Tick both reset check boxes and then un tick both boxes to carry out a full reset on the system W ith Engineering Silicon X C2V3000 FPGAS configuration procedures should be carried out twice in order to successfully start up www nallatech com 85 XtremeDSP Development Kit User Guide DIWEL Example Application 2 In this Section Modulator Example 9 8 Introduction This Section necessitates that X ilinx Integrated Software Environment ISE 4 21 software has been installed and the operating system running on the host PC is either W indows 9x N T M e 2000 X P or Linux The second example application provides a basic introduction to using Coregen for the rapid creation of D SP designs This example involves modulating the input waveform from both AD C s and outputting the modulated waves on the corresponding DAC The 8 MHz sine wave that modula
153. se tools are available in a variety of formats including Alliance Foundation and ISE W hen performing the implementation stage of the design process some settings are mandatory and need to be specified for the design to configure and run on N allatech hardware This Section details these settings Also detailed are some common additional settings for the implementation options it should be stressed however that the common settings are optional and that the developer should select the settings as appropriate for their design Necessary Settings i Enable Readback and Reconfiguration ii Select the JTAG Start up Clock Selected configuration clock iii The pull down option should be enabled for unused pins NT107 0132 Issue 9 23 05 2003 www nallatech com 77 XtremeDSP Development Kit User Guide DIME Optional Settings If you are targeting a Virtex II Engineering Silicon Part it is advised to set the following environmental variable XIL BITGEN_VIRTEX2ES YES Engineering silicon parts are identified by the ES marking on the face of the chip Please see the X ilinx answers database if you require further details It is worth also noting that when using Engineering Silicon parts some care should be taken when using in that the DCM should be placed in the same quadrant as the BUFGMUX Setting the above environmental variable will not explicitly carry out the location of these components for you but the switch en
154. shipped in a stand alone case and includes all necessary power supplies as well a U SB cable In addition it includes the FUSE software for configuration and control as well as a set of evaluation software for the design and implementation tools Hardware BenO N E Motherboard populated with a BenADDA DIME II module in a stand alone Case o External power supply US Mains cable with separate UK European or Australian mains adaptors o Wide ranging input 90 264V ac multiple output power supply generating 45Volts 2A 12 Volts 1A 12 Volts 200mA o USB v1 1 compatible cable 2 metres long o 3 MCX to BNC cables for connecting to the ADC DAC and external clock connectors o Carrying Case Software Nallatech FUSE Field U pgradeable Systems Environment Software CD Provides the ability to control and configure FPGA and provides facilities to transfer data between the N E motherboard and a host o Nallatech XtremeD SP Development Kit CD that provides documentation on the BenO N E and BenADDA products as well as supporting files for their use within the FUSE framework o Xilinx Evaluation CD kit www nallatech com NT107 0132 Issue 9 23 05 2003 DENMEN EE 30 days evaluation for the X ilinx Foundation ISE 00 days evaluation for the X ilinx System Generator for D SP 30 days evaluation for Matlab Simulink e Reference Design o A design example is provided with the kit and
155. some considerations should be made with regards to how this affects the Interface FPGA to User FPGA communications DataRead DataReadSingle The DIME DataRead and DIME D ataReadSingle commands are used to read data from the BenO NE PCI These commands read data from the internal FIFOs of the Interface FPGA For this reason the User FPGA must send data to the Interface FPGA before it can be read DataW rite DataW riteSingle The DIME DataW rite and DIME DataW riteSingle commands used to write data to the BenO NE PCI These commands write data to the internal FIFO s but they also write to the buffer that controls 46 www nallatech com NT107 0132 Issue 9 23 05 2003 DEHNTE Gg VE a Developm MEU the AS D S bit and ensures that this bit will be LOW W hen data is written the EMPTY signal will go LOW AddressW riteSingle The DIME AddressW riteSingle command writes a single address to the Interface FPGA This is written into the internal buffers along with a HIGH bit for the AS DS Again when the address is written the EMPTY signal will go LOW to indicate that data is available Interface Core Design N allatech has developed an interface core design to be used to control the Interface FPGA to User FPGA communications This application note PCI to User FPGA Interface can be found on the supplied FUSE CD For further details on e FUSE Development API please refer to the FUSE C C Developers Guide provided on the
156. supplied FUSE CD 5 12 DIME II Communication Bus Speeds The BenO NE on the XtremeD SP Development Kit has a variety of different types of buses that allow the Interface PC I U SB FPGA and the DIME II module slot to communicate with each other There are three main communication bus types e Parallel Link e Adjacent Bus Local Bus These three buses permit data to be transferred to all the various devices being used in the DIM E II system Below is a brief introduction to these buses The Parallel Link P Link bus is a 12 bit bi directional point to point bus which will allow the D IM E II module to directly communicate with external data Some of the bits of this bus are used to provide a software interface communication mechanism as described in Section 5 10 There are two types of adjacent buses available on the X tremeD SP D evelopment Kit the A djacent In Bus and Adjacent O ut Bus These buses are designed to facilitate the use of Pipelined architectures where the resultant data processed on one DIME II module can be passed to the next module for further processing The Adjacent In Bus is 28 bits wide and the Adjacent ut Bus is 40 bits wide The Local Bus is coupled from the Interface FPGA and the DIME II module The Local Bus is a 64 bit wide bus and may be used as either an overall system control or broadcast bus Such a bus can typically be utilised to memory map internal registers and memory space in the FPGA into microprocess
157. sures that when the D RC D esign Rule Check is carried out a bitsfile generation it will check that these have been placed in the same quadrant N ote also that for the ES parts the Triple DES bit stream encryption and partial reconfiguration features are not compatible with standard bit stream generation See the following X ilinx answer database records Answer Record 12521 4 1i Virtex II BitGen BitGen 218 warning message is issued when XIL BITGEN VIRTEX2ES is set Answer Record 13223 4 11 SP3 4 1 03i Service Pack 3 update Answer Record 12719 4 1i BitGen ERROR DesignRules 557 Blockcheck Invalid connection used between BUFGMUX DCM Answer Record 12671 4 1i SP2 4 1 02i Service Pack 2 update Answer Record 12518 4 11 SP1 4 1 01i Service Pack 1 update Answer Record 12326 4 1i Virtex II BitGen A patch is available to correct Virtex II bit stream generation Does it affect bit stream size Answer Record 11756 4 1i Virtex II Are there restrictions on IBUFG DCM and BUFG BUFGMUX routing in Virtex II devices 78 www nallatech com 107 0132 Issue 9 23 05 2003 XtremeDSP Development Kit User Guide e Common Settings See next figure for these options Figure 35 Implementation Configuration Settings NT107 0132 Issue 9 23 05 2003 www nallatech com 79 ees neu oe Figure 36 Implementation Configurati
158. t 10 gt PA13 PP2LK lt 10 gt PD13 PPOLK 11 PA14 PP2LK 11 PD 14 Table 45 PLINK Pinouts 2V 1000 Dime Il Connector PIN No DIMETI User FPGA Dime ll User FPGA 2V1000 PIN C onnector 2V1000 No PIN No PIN No PP2LK lt 9 gt PD12 B17 Signal Name PPOLK 0 is connected to a clock pin GCLK6S on the Virtex ll PPOLK 1 is connected to a clock pin G CLK7P on the Virtex ll PP2LK 0 is connected to a clock pin GCLK25 on the Virtex ll PP2LK 1 is connected to a clock pin CLK3P on the Virtex ll www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide 11 5 2 DIME II control and monitoring signals DIME II Specific Pins Dime Ill Connector Signal Name PIN No CONFIG DONE FPGA DONE me CNW DONE Ws fa uu fem KH M Table 46 User FPGA Specific Pinouts 2V 1000 Dime II Connector User FPGA 2V1000 PIN No PIN CONFIG DONE is driven from the IO ofthe Virtex II into the base of the transistor to signal that the on board User FPGA has been configured successfully User to drive this pin LOW once the FPGA is configured User LEDs Signal Name User FPGA 2V1000 PIN No LED Green2 V21 Table 47 User LED Pinouts 2V1000 On board Temperature Sensor Signal Name User FPGA 2V1000 PIN No Table 48 Temperature Sensor Pinouts NT107 0132 Issue 9 23 05 2003 www nallatech com 139 XtremeDSP Developme
159. t various speeds The speed at which the ADCs and DACs are clocked depends on what bit file is downloaded into the CLK FPGA 114 www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide The BenADDA is supplied with various bit files The user is simply required to choose the Clocking option most suited to the end application 10 7 ZBT SRAM Memory The BenADDA supports up to four ZBT SRAM devices when a X C 2V3000 FPGA or higher is populated This memory can provide on board storage capabilities of 4 Mbytes Higher Density Devices supported via a 32 bit data bus The BenADDA supports various memory sizes all of which are supplied from Micron in the 165 pin FBGA package The memory chips are driven exclusively by the USER FPGA Figure 69 illustrates the inter connect between one Bank of ZBT SRAM and the USER FPGA 10 7 1 Hardware Details BenADDA User FPGA to one Bank of ZBT SRAM Interface Chip Select Top 4 bit Parity ZBT SRAM From I Mbyte Top of PCB ZBT SRAM From Mbyte BankA Bottom of PCB Chip Select Bottom Figure 69 Functional Block Diagram of ZBT SRAM BANK A Interface The four devices are split into two independent Banks Bank A and B The two devices that make up a single bank share all data address and control signals with the exception of the chip select signals U sing the chip select input allows access to each device individually but not simultaneousl
160. tart and the driver installation is complete Under W indows XP Pro you may see the warning W indows cannot initialise the device o driver for this hardware This is expected and the warning is taken care of when installing the DIME software as directed in FUSE Software Installation on page 30 CEU pe ra TEE Ea w m om nce you have installed the drivers you should proceed to FUSE Software Installation on page 30 to install the DIME Software that is required to communicate with the card 4 5 2 PCI Windows NT Installation Q Administrative Privileges are required for W indows NT installation TheW indowsNT drivers need to be installed by runningthe N allatech software from W indows These drivers are now installed automatically during the installation of the card software www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide 4 6 USB Driver Installation The following driver installation can be performed on power up or with the host PC already powered and the operating system s desktop visible 4 6 1 Windows 98 ME 2000 X P Installation 1 Connectthe supplied power supply to a suitable mains supply T he power supply accepts mains input from 100 240vac 2 Apply power to the BenO NE PCI card see Figure 1 3 Connect the BenO N E PCI card to your host PC with the supplied USB cable 4 5 Found New Hardware
161. tes the input waveform is internally generated in the FPGA This design also includes an LED flash pattern 9 9 Functional Description The design for the Main FPGA takesthe data from the AD C s and multiplies it by an internally generated sine wave The outputs from both multipliers are converted from 2s complement to offset binary and then output to the DACs as illustrated in Figure 43 8 The VHDL source code for this design is included on the XtremeD SP Development Kit CD at the path lt C DRO MDrive gt Examples M odulator Source Modulator vhd 8 For convenience a X ilinx ISE Project N avigator File for each implementation option is included at the path lt CDROM Drive gt Examples M odulator Source SE On board Oscillator Main FPGA 86 www nallatech com NT107 0132 Issue 9 23 05 2003 Figure 43 Modulator Design 9 9 1 Creation and Configuration of Sine Wave and Multiplier Components The source code declares and instantiates the sine wave generator and multipliers created in Coregen Coregen components are inserted into a design by right clicking on the top level of the design and selecting N ew source This brings up the dialogue box shown in Figure 44 Select Coregen IP enter file name and then click Next to proceed Planch fa savn EMM Skal scan ama Figure 44 New Source Dialogue Box NT107 0132 Issue 9 23 05 2003 www nallatech com 87 Xtr
162. th PCI or USB to User FPGA Interface Core For full details of the Interface to User FPGA Interface please refer to Application N ote N T 302 0000 which is available on the supplied FUSE CD The necessary VHDL code and an EDIF file for the core are also provided on the CD Please note that this is generic A pplication N ote whether PCI or USB interfacing is used 5 11 2 Implementing the Comms Communications Mechanism Instead of communicating over the Interface Comms bus using the Interface to User FPGA Interface Core a mechanism to communicate over this bus using the appropriate protocol can be implemented directly by the user in their design A block diagram for the implementation of this core is shown in Figure 23 User FPGA User FPGA Application Design PCI USB Interface in FPGA interface Interface V User FPGA Application Design Comms Bus incorporating own PCI Commis Bus communications mechanism Figure 23 Implementation with own communications mechanism NT107 0132 Issue 9 23 05 2003 www nallatech com 43 XtremeDSP Development Kit User Guide DINIE 5 11 3 Comms Bus Protocol The information in this section only applies to users who wish to implement the Comms communications protocol directly in their own FPGA applications design without using the N allatech Interface to User FPGA Interface Core D ata is transferred between the User FPGA and the Interface FPGA with the use of 5 control signals
163. that connects directly to the User FPGA There is no assigned function for this two pin header which is therefore free to be used for your desired application applied to this MUST be within the range of OV 3 3V Virtex ll devices are NOT 5V The two pin header is connected directly to the Virtex Il User FPGA and therefore signals tolerant Table 26 contains the pinout information for the User IO header Signal Description Signal Name User FPGA Pin Unassigned User IO connection to User 10 1 Consult Pinout Information USER FPGA Section Unassigned User IO connection to User 10 2 Consult Pinout Information USER FPGA Section Table 26 Pinouts of U ser IO header The pin locations for the User IO signals are listed for each FPGA option in the following places The XC2V250 FPGA has no available pin locations for the User IO Header For XC2V1000 FPGA see User IO header on page 142 For an 2 3000 or X C2V6000 FPGA see www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI NT107 0132 Issue 9 23 05 2003 User IO Header on page 171 www nallatech com XtremeDSP Development Kit User Guide 127 XtremeDSP Development Kit User Guide DIME 128 11 3 Design Partitioning The XtremeD SP Development Kit allows the user to partition the functionality of their application between software and hardware easily and effectively Below the design partitioning of the X tremeD SP D eve
164. the BenONE PCI the 3 3V status LED on the front of the card also illuminates to indicate that a 3 3V supply is available from the PCI slot The illuminated LEDs are shown below The hardware installation of the BenO NE PCI is now complete It should be noted that at this stage the card will not function until the BenO N E PCI drivers and software have been installed Instructions on how to do this are given in Software Installation on page 25 4 4 USB Installation The following installation can be performed on power up or with the host PC already powered with the operating system s desktop visible W indows 98 M E 2000 X P Installation 1 Connectthe supplied power supply to a suitable mains supply The power supply accepts mains input from 90 264Vac 2 Apply power to the BenO NE 3 Asaconfidence test that the BenO N E PCI is correctly installed the power Status LED and PCl Control FPGA configuration LEDs illuminate to indicate the card has configured correctly 4 Connect the BenO card to your host PC with the supplied USB cable The hardware installation ofthe BenO N E is now complete It should be noted that at this stage the card will not function until the BenO N E PCI drivers and software have been installed Instructions on how to do this are given in Software Installation on page 25 24 www nallatech com NT107 0132 Issue 9 23 05 2003 DIME XtremeDSP Development Kit User Guide Software Inst
165. ther representations conditions or warranties express or implied The buyer agrees to execute and return any license agreements as may be required by the company in order to authorise the use of those licensable items If the licensable item is to be resold this condition shall be enforced by the re seller on the end customer Each order received by the company will be deemed to form a separate contract to which these conditions apply and any waiver or any act of non enforcement or variation of these terms or part thereof shall not bind or prejudice the company in relation to any other contract The company reserves the right to re issue its price list at any time and to refuse to accept orders at a price other than at the price stated on the price list in force at the time of order The company reserves the right to vary the specification or withdraw from the offer any of its products without prior warning The company reserves the right to refuse to accept any contract that is deemed to be contrary to the company s policies in force at the time PRICING All prices shown on the company s price list or on quotations offered by them are based upon the acceptance of these conditions Any variation of these conditions requested by the buyer could result in changes in the offered pricing or refusal to supply All quoted pricing is in Pounds Sterling and is exclusive of Value Added T ax VAT and delivery In addition to the invoiced val
166. ttings Implementation Configuration Settings Cont Clock FPGA ADC to DAC feed through design Fuse System Software GUI Dialogue box to locate cards Dialogue box to open cards GUI showing open card Modulator D esign N ew Source Dialogue Box Xilinx Core Generator W indow Math Functions Folder Sine C osine Look up T able Multiplier folder Multiplier Configuration Settings Modified sygen qam16 mdl Modified Carrier Recovery Subsystem DACs Subsystem Assigned Bitfiles in FUSE Probe BenADDA layout top BenADDA layout bottom Functional Diagram of DAC Interface www nallatech com DIMETI NT107 0132 Issue 9 23 05 2003 FATET XtremeDSP Development Kit User Guide Figure 57 AD 9772 Architecture 101 Figure 58 PLL Jumper O ption 102 Figure 59 Physical Location of Jumpers for DAC XC2V250 only 104 Figure 60 DAC Diagram of MOD fixed jumpers 2V250 only 105 Figure 61 DAC Diagram of DIV selectable jumpers 2V250 only 106 Figure 62 PLLLO CK LED indicator 2V250 only 106 Figure 63 AD9772A DC coupled utput 107 Figure 64 AD 9772 directly coupled option 108 Figure 65 Functional Diagram of DAC Interface 109 Figure 66 AD 6644 Architecture 110 Figure 67 O verview of CLK FPGA 111 Figure 68 Diagram of CLK FPGA feedback signals 114 Figure 69 Functional Block Diagram of ZBT SRAM BANK A Interface 115 Figure 70 ZBT SRAM Clocking Example BANK A 117 Figure 71 User FPGA interfacing O verview 118 Figure 72 JTAG
167. uccessfully User to drive this pin LOW once the FPGA is configured User LEDs Signal Name User FPGA 2V250 PIN No LED Green2 V21 Table 34 User LED Pinouts 2V250 On board Temperature Sensor Signal Name User FPGA 2V250 PIN No Table 35 Temperature Sensor Pinouts 2V250 NT107 0132 Issue 9 23 05 2003 www nallatech com 133 XtremeDSP Development Kit User Guide DIMET 11 4 3 Clock signals relating to DACs and ADCs Clock sources available at CLK FPGA Signal Name CLK FPGA 2V80 Pin User FPGA 2V250 Signal Description No PIN No Op Amp GC LK6S External CLK source via Op_Amp Op Ampl 6 GCLK7P Complement of External CLK source via Op Amp EXT CLK 8 GCLKOS External CLK source straight to CLK FPGA EXT CLKI 8 GC LK1P Complement of External CLK source straight to CLK FPGA GEN n LKD 7 GCLK7S Generated Clock D EXT2_ EXT2CLIK LK 7 GCLK D7 GCLK5 N Na 2nd 244 External Clock Clock EXT 2_ LE A6 E EE ER of 2nd External Clock Table 36 Clock Signals at CLK FPGA 2V250 Clock Feedback signals Signal Name FPGA 2V80 Pin User FPGA 2V250 Signal Description PIN No C LK2 FB 11 Feedback to User FPGA Table 37 Clock Feedback Signals 2 250 Clocking Pinouts for DACs and ADCs Signal Name CLK FPGA 2V80 Pin No a TER Acc CT Table 38 Clocking Pinouts for DACs and ADCs 134 www nallatech com NT10
168. ue the buyer is liable for all import duty as may be applicable in the buyer s location If there is any documentation required for import formalities whether or not for the purposes of duty assessment the buyer shall make this clear at the time of order Q uotations are made by N allatech upon the customer s request but there is no obligation for either party until N allatech accepts the customer s order N allatech reserves the right to increase the price of goods agreed to be sold in proportion to any increase of costs to Nallatech between the date of acceptance of the order and the date of delivery or where the increase is due to any act or default of the customer including the cancellation or rescheduling by the customer of part of any order N allatech reserves the right without prejudice to any other remedy to cancel any uncompleted order or to suspend delivery in the event of any of the customer s commitment with N allatech not being met DELIVERY All delivery times offered by the company are to be treated as best estimates and no penalty can be accepted for non compliance with them D elivery shall be made by the company using a courier service of its choice The cost of the delivery plus a nominal fee for administration will be added to the invoice issued Payment of all inward customs duties and fees are the sole responsibility of the buyer If multiple shipments are requested by the buyer multiple delivery charges will be ma
169. ves changing the UCF retrospectively to match your code There are a number of user accessible interfaces from the User FPGA to other devices on the BenADDA which you can utilise for design purposes User FPGA DIME II Signals User FPGA ADCs User FPGA DACs User FPGA Clock FPGA User FPGA ZBT Memory These interfaces are shown and highlighted below in Figure 34 76 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEAI XtremeDSP Development Kit User Guide Analogue O utput Analogue Input DC Coupled OR Differential or Directly Coupled single ended External CAEN D AA fe TANNVH O 4e ON MODULE XILINX VIRTEX II X C2V250 X C2V6000 DIME II MOTHERBOARD TO BE lt 28 BE n 2 Figure 34 Interfacing to User FPGA 9 4 Synthesis and Implementation Settings This Section details the synthesis and implementation settings which should be used for the development of FPGA designs to run on Nallatech hardware 9 4 1 Synthesis O ptions W hen developing FPGA designs to run on Nallatech hardware it is not necessary to select any specific settings for the synthesis of HDL code for FPGA designs 9 4 2 Implementation O ptions Developing FPGA designs to run on Nallatech hardware with on board Xilinx FPGAS will ultimately require use of the Xilinx Implementation tools to take the synthesised design to the hardware device The
170. will be read if EMPTY is HIGH and the read enable is active 44 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMEJI XtremeDSP Development Kit User Guide The diagram in Figure 24 shows a functional representation of data reads in operation These are single word transfers ATAJE Figure 24 Single Read Transfer The first read sends an address from the Interface FPGA to the User FPGA The second read sends the data across The DATA int bus shows the internal data waiting to be driven onto the ADIO bus The diagram in Figure 25 shows a burst read in operation RENAE Me DA TAS eS a I Figure 25 Burst Read Transfer This example shows a single address being sent from the Interface FPGA to the User FPGA followed by a burst of data Again the DATA int bus shows the internal data waiting to be driven onto the ADIO bus It should be noted that after the first read the next set of data will not be available until one clock cycle after the read So long as the reads are continuous data will then follow every clock cycle Writing to Interface FPGA from User FPGA W riting to the Interface FPGA is similar to writing to a FIFO If the Interface FPGA can receive more data the BUSY signal is LOW and when the Interface FPGA cannot receive any more data the BU SY signal is HIGH To help meet timing specifications the User FPGA application is allowed to over run by two further data samples In other
171. wx ea fem fas un Table 27 Interface to User FPGA Comms Signals Also DSP should be connected to 1 sometimes referred to as CLKB Interface General Bus Signal User User User User User COMM Name FPGA FPGA FPGA FPGA FPGA Signal 2V250 2 1000 2v2000 2v3000 2V3000 FG456 FG456 FG676 FG676 6000 Pin No PIN No Pin No Pin No FF1152 Pin No Table 28 Interface to User FPGA Clock Requirements N T107 0132 Issue 9 23 05 2003 www nallatech com 129 XtremeDSP Development Kit User Guide Pinout Information DIMETI This Section provides you with the following pinout information for each User FPGA option XC2V250FG456 XC2V1000FG456 XC2V2000FG676 XC2V3000FG676 XC2V3000FF1152 X C 2V6000FF1152 User FPGA to DIME II motherboard communication D IME II control and monitoring signals ZBT SRAM interface to user FPGA Clock signals relating to DAC s and ADCs DAC Signal Pinouts ADC Signal Pinouts 1L4 XC2V250FG456 11 4 1 User FPGA to DIME II motherboard communication Local Bus Pinouts Signal Name Dime ll User FPGA Signal Name Dime ll C onnector 2V250 PIN C onnector PIN No No PIN No LBUS lt 15 gt Table 29 Local Bus Pinouts 2V250 User FPGA 2V250 PIN No H3 H2 H1 K K K K 4 M5 1 2 www nallatech com NT107 0132 Issue 9 23 05 2003 DIMETI XtremeDSP Development Kit User Guide Adjacent IN Bus User FPGA communications Dime Il User FP
172. y which provides you with 32 bit access to 2Mbytes of memory twice the depth of one chip Each ZBT device integrates from 256K x 32 core with advanced synchronous periphery circuitry and a 2 bit burst counter The SRAM is optimised for 100 bus utilization eliminating any turnaround cycles for READ to WRITE or WRITE to READ transitions All synchronous inputs pass through registers controlled by a positive edge triggered single clock input The synchronous inputs include all addresses all data inputs chip enable synchronous clock enables write enables and Read Write The asynchronous inputs include the output enable clock and snooze enable and a burst mode that can select between interleaved and linear modes Each Bank is clocked directly by an independent clock signal from the User FPGA This means that Bank A has two ZBT devices that share the same clock signal while Bank B has another separate clock signal shared between its two ZBT devices Access to 2Mbytes of memory if ZBT chips are 8Mbit devices So one chip would give IM byte of memory NT107 0132 Issue 9 23 05 2003 www nallatech com 115 XtremeDSP Development Kit User Guide DIME The main features of the ZBT Memory include Fast cycle times 6ns 7 5ns and 10ns 100 bus utilisation Advanced control for minimum signal interface Single R W Read W rite control pin Clock controlled and registered addresses data I O s and control signals Common data inputs and data
173. y Features The key features of the XtremeD SP Development Kit are On board Xilinx Virtex II FPGA Various FPGA device packages sizes and speed grade options available Compatible with N allatech s FUSE reconfigurable computing operating system Two independent analogue capture channels 2x 14 Bit ADC Resolution up to 105MSPS per channel sampling rate Two independent channels to extract analogue data 2x 14 Bit DAC Resolution up to 160MSPS per channel sampling rate Up to 8MB of ZBT SRAM memory in two independent banks Nallatech ZBT SRAM interfacing IP Core available Multiple Clocking O ptions Internal amp External Example designs and source code included Status LEDs 7 3 BenADDA specification variations The BenADDA module is available in the following specifications FG456 FG456 FG676 FG676 FG1152 FG1152 Board Programmable 3 3 3 3 3 3 Clock s in User FPGA Features 2 250 2 1000 2 2000 2V3000 72 3000 2V6000 ADCs DACs User FPGA Status LEDs B Table 14 BenADDA specifications 7 Figures quoted are in M bytes and represent the maximum total size of memory on board Please note that t the actual populated memory size may differ from the max value and will depend upon the specific configuration Figures here list the maximum available size at time of print C locking options include external Clock source available through front panel 4 user programmable clocks from User FPGA

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