Daedalus/Daedalus11RT User Manual - Daedalus framework
Contents
1. Project S009 A Bus Interfaces Ports Addresses Bus interface Filters A z 5 Platform F x Name Bus Name IP Type IP Version By Connection Project Files CB_axi yy axi_inter 1 03 a md _ MHS File system mhs DDR_axi yr axi_inter 1 03 a vi Unconne UCF File data system ucf host_if_ ty axi_inter 1 03 a Ey eae aes iMPACT Command File etc download cmd HENTEZ I Y AXI Implementation Options File etc fast_runtime opt mB ax axi inter 1 03 a LMB Bitgen Options File etc bitgen ut AET f Janen a Xilinx Point To Point amp Elf Files DBUS_m ve Imb v10 2 00 b dle DBUS m r Imb_v10 2 00 b AE t mb_2 DBUS m r Imb_v10 2 00 b a _ f mb_3 PBUS m r Imb v10 2 00 b i om Le 5 host_if_mb PBUS_m jr Imb_v10 2 00 b SS AEBIBCe ype Imp Executable home mohamed tests daedalus exa PBUS m r Imb v10 2 00 b _ Y Slaves _ _ Sim Executable 3 host if r Imb v10 2 00 b Project Options host if r Imb_v10 2 00 b saecains cc Device xc6vIx240tff1156 1 host_if_mb wr microblaze 8 20 a _ 5 Manas 7 E mb_1 r microblaze 8 20 a Bati 4 D H mb_2 r microblaze 8 20 a Vinha IP Catalog Onas mb_3 tr microblaze 8 20 a O H BRAM1 tr bram_bl 1 00 a Se z T DCTRL_B r Imb_bra 3 00 b Description IP Version IP Type PCTRL B r Imb_bra 3 00 b EDK Install BRAM1_ tir bram_bl 1 00 a Analog DC2. Send file Plain LF line end Char delay 1ms Figure 4 8 The output from pipeline and split_join running on FPGA 25 Chapter 5 Contributing to Daedalus Daedalus All the individual parts of Daedalus and Daedalus are available as open source software However the develop ment of these tools and the access to their code repositories is limited We provide here a quick overview on how you can contribute to each tool 5 1 PNgen The PNgen compiler is maintained by Sven Verdoolaege at the following git repository http repo or cz w isa git Therefore anyone with Internet access can follow the latest developments in PNgen For bug reports please contact the maintainer 5 1 1 Building PNgen from the git repository To build PNgen from the git repository you need to clone the repository and follow the instructions in the INSTALL file accompanying the cloned repository Installing PNgen requires installing several packages and libraries The instructions in the INSTALL file show you how to build each library from its sources However on modern Linux distributions these libraries can be installed using the pre built packages provided by the distribution vendor For example on 64 bit Ubuntu machines you can install PNgen by performing the commands shown in Figure 5 1 mkdir pngen cd pngen sudo apt get install pkg config libtool bison flex libgmp3 dev libyaml dev libntl dev libxml2 dev wget
3. my Debug for project P_1 mr all Change Referenced BSP C C Build Settings Figure 3 13 Step 8 Changing the build settings Properties for P_1 lEn Settings gt Resource Builders Configuration Debug Active gt Manage Configurations C C Build Build Variables Discovery Options Tool Settings Build Steps PBuild Artifact Binary Parsers Error Parsers Environment Logging Settings Tool Chain Editor gt C C General Project References Run Debug Settings v MicroBlaze gcc assembler Optimization Level Optimize for size Os General v MicroBlaze g compiler Symbols Warnings Optimization Debugging Profiling Directories Miscellaneous v Inferred Options Software Platform Processor Options v MicroBlaze g linker General Libraries Miscellaneous Linker Script v Infarrad Antianc Other optimization flags Figure 3 14 Step 9 Changing optimization and debugging options 2 Run BRAM INIT which will update the bitstream with the ELF files 3 Under etc directory in the XPS project directory rename the file download_ML605 cmd to download cmd 4 Open a terminal in the directory DAEDALUS_DIR examples sobel serial_m1605 and run make This will build the program that will communicate with the FPGA from the computer side using UART 5 Connect and start the FPGA board Then run the Download bitstream t
4. S P_2 fin_ctrl_P1 0x 9000000 0xf900000f gt P3 LMB_CTRL_CM_mb_1 0 gt i sobel_hw_platform DCTRL_BRAM1_mb_1 0 mb_1_timer 0xf1 host_if_mb_RS232_Uart 0xb1 DDR3_SDRAM 0 AXI_CTRL_CM_mb_1 0 AXI_CTRL_CM_mb_2 0 AXI_CTRL_CM_mb_3 0 mb_1_ddr_axi2axi_connector 0 mb_1_axi2axi_connector 0x80000000 0x8fffffff Address Map for processor mb_2 fin_ctrl_P2 0x 9 LMB_CTRL_CM_mb_2 0 DCTRL_BRAM1_mb_2 0 PCTRL_BRAM1_mb_2 0 Overview Source er E Problems Tasks E console X N E Properties Terminal 1 Ee BE et fv 8 SDK Log 16 25 41 INFO Restoring global repository preferences home mohamed tools FreeRTOS FreeRTOSV7 1 0 Demo MicroBlaze Spartan 6 EthernetLite KernelAwareBSPRepository ith Figure 4 4 Importing FreeRTOS BSP into Xilinx SDK c Now you will see a window like the one shown in Figure 4 5 Add a new Global Repository by clicking on New next to Global Repositories Now browse to FREERTOS_DIR FreeRTOS_Xilinx_SDK_BSP and click OK Then click on Apply and OK in the window shown in Figure 4 5 Preferences Add remove or change the order of SDK s software repositories gt General gt C C gt Help gt Install Update gt Remote Systems gt Run Debug gt Team Local Repositories available to the current workspace Terminal aaa z v Xilinx SDK Global Repositories available across workspaces Flash Programming home mohamed tools FreeRTOS_Xilinx_SDK_BSP New Hardware Specificati N Lo
5. host interface is essentially another MB with minimum resource usage in terms of data and program memory 8 KB each The purpose of having host interface is to communicate with host PC e g after host PC transfers some input data to the DDR and then notifies host interact to start MBs specified in the platform file It also specifies the FPGA board in use via attribute type ML605 Besides ML605 XUPV5 LX110T board is also supported and can be used via attribute type XUPV5 LX110T Attribute interface UART indicates that the FPGA board communicates with host PC through UART Once we have the platform file we explain how to specify a mapping file Figure 3 4 shows an example of a mapping file The two instances of gradient PPN processes ND_1 and ND_2 are mapped to MB mb_2 and mb_3 All the other PPN processes are mapped to MB mb_1 On MB mb_1 all PPN processes are statically scheduled according to the schedule computed in PNgen e schedule_type Besides statically schedule all PPN processes mapped onto the same MB dynamic schedul ing of the PPN processes is also supported Dynamic scheduling includes round robin and round robin with yielding using Xilinx Xilkernel Deriving Platform and Mapping files using Sesame 12 lt xml version 1 0 standalone no gt lt DOCTYPE platform PUBLIC LIACS DTD ESPAM 1 EN http www liacs nl cserc dtd espam_1 dtd gt lt platform name myPlatform gt lt processor name mb_1 type
6. 1 amp imagelj 1 i amp image j 1 i 1 amp image j 1 i 1 amp image j 1 i amp image j 1 i 1 amp Jy j i for j 2 j lt M 1 j for i 2 i lt N 1 i absVal amp Jx j i amp Jy j i amp av j i for j 2 j lt M 1 j for i 2 i lt N 1 i writePixel amp av j i return 0 Figure 1 3 Example of a SANLP implementing the Sobel filter Chapter 2 Installing Daedalus Daedalus In this chapter we explain the steps to install Daedalus Daedalus and their tools 2 1 Prerequisites Daedalus Daedalus are available only on Linux platforms and tested using the Linux distributions listed in Table 2 1 Installing Daedalus Daedalus requires the tools shown in Table 2 2 to be installed on the system Table 2 1 Tested Linux distributions Distribution 10 4 GZD 12 04 64 bit openSUSE 11 4 64 bit 10 G2 bi0 Table 2 2 Tools required to install Daedalus Daedalus 24 1 Oracle Java JDK 1 6 0_22 GNU Weei The listed versions are the ones that have been tested while developing this manual A higher older version might cause compilation installation errors in some cases especially with GCC The Daedalus framework instal lation consumes around 900 MB of disk space while the Daedalus framework installation consumes around 1 2 GB of disk space 2 2 Obtaining the Frameworks The Daedalus and Daedalus frameworks to
7. 6 Click on Browse and set the location to be DAEDALUS_DIR examples sobel parallel sobel SDK Then click on OK 1 Workspace Launcher Select a workspace Eclipse Platform stores your projects ina Folder called a workspace Choose a workspace folder to use For this session ail Workspace pdeplex daedalus examples sobel parallel sobel SDK Browse Use this as the default and do not ask again Figure 3 6 Step 1 Setting the workspace location 2 Now you should see a window like the one shown in Figure 3 7 3 In SDK click on File gt Import as shown in Figure 3 8 4 A new window will appear as shown in Figure 3 9 Select General Existing Projects into Workspace Then click on Next 5 You will see a window like the one shown in Figure 3 10 Click on Browse to select the root directory which contains the SDK projects This directory is DAEDALUS_DIR examples sobel parallel sobel SDK 6 After setting the directory correctly you should see a window like the one shown in Figure 3 11 Now click on Finish 7 After clicking on Finish in the previous step SDK will build all the imported projects However there are a few issues that we need to fix manually First the host interface project host_if will show an error This is because the project contains the files needed to interface with both of AXI and PLB system To get rid of this error you need to del
8. Exhibition DATE 2012 pp 941 946 March 2012 G Bilsen M Engels R Lauwereins and J Peperstraete Cyclo static data flow IEEE Trans Signal Pro cess Vol 44 pp 397 408 1996 S Verdoolaege H Nikolov and T Stefanov pn a tool for improved derivation of process networks EURASIP Journal on Embedded Systems vol 2007 January 2007 A Pimentel C Erbas and S Polstra A systematic approach to exploring embedded system architectures at multiple abstraction levels IEEE Transactions on Computers vol 55 pp 99 112 February 2006 H Nikolov T Stefanov and E Deprettere Systematic and Automated Multiprocessor System Design Pro gramming and Implementation IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems vol 27 pp 542 555 March 2008 S Stuijk M Geilen and T Basten SDF SDF For Free in Proceedings of the 6th International Conference on Application of Concurrency to System Design ACSD 2006 Los Alamitos CA USA pp 276 278 IEEE Computer Society Press June 2006 28
9. j jdk path h c d Figure 2 2 Commands needed to install the Daedalus framework The setup script accepts several options The full list of options and usage can be shown by passing h option which shows a help message 2 5 Installing the individual tools We explain here the steps to install the individual tools of the Daedalus Daedalus frameworks 2 5 1 Installing the PNgen Compiler To install the PNgen compiler open a command line terminal and execute the commands shown in Figure 2 3 mkdir pngen cd pngen wget http daedalus liacs nl pngen release_yyyymmdd setup_pngen sh chmod x setup_pngen sh setup_pngen sh clean nocheck Figure 2 3 Commands needed to install PNgen After invoking the commands PNgen will be installed in pngen directory The setup script setup_pngen sh takes two optional arguments clean which cleans the pngen directory from all the generated installed files and nocheck which ignores invoking make check for all the packages leads to reduced installation time When setup_pngen sh is executed with no options it builds PNgen from scratch and invokes make check for all the packages mkdir pntools cd pntools wget http daedalus liacs nl pntools release_yyyymmdd setup_pntools sh chmod x setup_pntools sh setup_pntools sh pngen_path clean Figure 2 4 Commands needed to install pntools 2 5 2 Installing pntools pntools is a set of tools for working with PPNs To in
10. 0x00000000 PCTRL_BRAM1_mb_2 0x0000000 Overview Source E Problems 4 Tasks E console X N E Properties Terminal 1 Ee BE et fiv OO SDK Log 16 32 27 INFO Processing command line option hwspec home mohamed workspace codeplex daedalus examples sobel parallel sobel SDK SDK Export hw system xml g Figure 3 8 Step 3 9 Now a new window will appear as shown in Figure 3 14 Click on Optimization and change it to Os Then click on Debugging and change it to None 10 Now after changing the optimization debugging options for all the projects you need to set up the correct linker script for each P_ project This can be done by right click on each P_ project and selecting Gen erate Linker Script After that you will see a new window as the one shown in Figure 3 15 Change the location of the Stack and Heap from LMB_CTRL_CM_mb_ into PCTRL_BRAM1_mb_ _DCTRL_BRAM1_mb_ Moreover increase the Stack and Heap size into a reasonable value e g 8 KB Then click on Generate 11 Now we are done and the correct ELF files are generated 15 Select Create new projects from an archive file or directory Select an import source Y amp General G Archive File Existing Projects into Workspace File System E Preferences gt amp C C gt amp Remote Systems gt amp Run Debug gt amp Team Finish Figure 3 9 Step 4 import Projects ez 3 Select a directory to searc
11. AEDALUS_RT_DIR examples synthetic output xps_project SDK After performing step 1 from Section 3 1 3 return here and perform the following 22 a Download FreeRTOS Board Support Package BSP for MicroBlaze This can be downloaded from the following URL http daedalus liacs nl daedalus rt release_20120907 FreeRTOS 7 1 0 zip Unzip this file and you will get a folder named FreeRTOS_Xilinx_SDK_BSP which contains two sub directories called bsp and sw_apps Move the FreeRTOS_Xilinx_SDK_BSP directory to a directory where it will not be deleted or modified The location of FreeRTOS_Xilinx_SDK_BSP will be denoted FREERTOS_DIR b Go back to SDK and click on Xilinx Tools gt Repositories as shown in Figure 4 4 C C sobel_hw_platform system xml Eclipse Platform File Edit Source Refactor Navigate Search Run Project Xilinx Tools Window Help rv lo a mlga ey By Ge Generate linker script re Rac c Board Support Package Settings amp Project Explorer X system x Repositories A JE Ou X Ma O E amp Y sobel_hw_platform Program FPGA An outline is not available Program Flash gt 0 BSP_host_if Design Information gt gb BSP_P_1 Serene ea XMD Console gt wih BSP_P 2 Target FPGA Device xc6 Uaunch shell gt wh BSP P 3 Created With EDK a s l A S Created On Wed Configure JTAG Settings gt iS host_if System Generator Co Debug Settings gt P1 Address Map for processormb_ 1
12. Chapter 2 WARNING If you have used the auto run script to run the FPGA backend in Section 3 1 then please be careful that using the auto run script to run the SystemC backend will delete the parallel directory generated by the FPGA backend Therefore you have to either copy it or rename it 3 2 1 Using the auto run script To invoke the Daedalus flow on the Sobel example using the timed SystemC backend execute the following command DAEDALUS_DIR scripts daedalus sh p DAEDALUS_DIR examples sobel o systemc timed The command in Figure 3 2 1 will generate a directory called parallel under the DAEDALUS_DIR examples sobel directory Under the parallel directory you will find another directory called sobel_systemc which contains the SystemC files The script will also run automatically the simulation and present the resulting images and waveforms 3 2 2 Running the Timed SystemC Backend Manually To use the timed SystemC backend you need to perform the same steps for parallelization as you have done for the FPGA backend in Section 3 1 The only difference is in invoking ESPAM To invoke ESPAM with the SystemC backend execute the command shown in Figure 3 2 2 ESPAM_DIR bin espam adg sobel kpn platform sobel pla mapping sobel map systemc timed libsystemc ESPAM_DIR src espam libSystemC A directory named DAEDALUS_DIR examples sobel parallel sobel_systemc will be generated Copy all the header and images files together
13. Daedalus Daedalus User Manual The Daedalus Daedalus Team csartem liacs nl September 10 2012 Contents Overview 1 1 A tomatic Par ce heme PA BMAD Be TE PREECE edan dreka 1 2 Design Space Exploration ewe eee ERE ee RE eRe ER ewe EHe EERE EES 1 3 Hard Real Time Schedulability Analysis 0 0 20 0000 00 2 eee eee ee eee LA System Synthesis kk he CHa wee OR BH AET ES BERS ae whe dbo ee bees Installing Daedalus Daedalus eel PO a a ee Ee eh ee ee ee he Se ee ee ee eee 22 Obtaining the Frameworks kk ce we SEES EEE SS Ee HEE ESE YOY 2 3 Installing the Daedalus Framework 2 2 202 020 eee eee ee ee ees 2 4 Installing the Daedalus Framework 1 0 000 000 0000 a 2 5 Installing the individual tools 2 2 1 Installing the Pigen Compiler 2644 6 6654 eH HEE REE RG BES OH ee Hw Zoe ANSI Ole e eera nenna RARER RES ADHERED ESR OR eR ES Bote SUIS SOSA a eK we we ERE SERS ee REED ERE ORE RRO Ew 2 5 4 Installing darts 1 5 4 46 2b we PERSE MAE Oe EES eH ESSERE SEE EES Dono DENIM ESM 4 onc Bee whee RE ee BRS OS EO eee Ye Using Daedalus 3 1 Example I Single Application FPGA Backend 0 0 00002 eee eee 3 1 1 Using the auto run script ee e e Ewe ee Deh Ewe RO ERE YS 3 1 2 Running the Daedalus Framework manually o a aaa 3 1 3 Building the Project using Xilinx Tools 0 0 0 2 02 00 eee ee ee 3 1 4 Programming the FPGA and Running the Application 3 2 Example II
14. MB data_memory 65536 program_memory 65536 gt lt port name I0_1 gt lt processor gt lt processor name mb_2 type MB data_memory 65536 program_memory 65536 gt lt port name I0_1 gt lt processor gt lt processor name mb_3 type MB data_memory 65536 program_memory 65536 gt lt port name I0_1 gt lt processor gt lt network name CS type AXICrossbarSwitch gt lt port name I0_1 gt lt port name I0_2 gt lt port name I0_3 gt lt network gt lt host_interface name HOST_IF type ML605 interface UART gt lt host_interface gt lt link name BUS1 gt lt resource name mb_1 port I0_1 gt lt resource name CS port I0_1 gt lt link gt lt link name BUS2 gt lt resource name mb_2 port I0_1 gt lt resource name CS port I0_2 gt lt link gt lt link name BUS3 gt lt resource name mb_3 port I0_1 gt lt resource name CS port I0_3 gt lt link gt lt platform gt Figure 3 3 An example of a platform file lt xml version 1 0 standalone no gt lt DOCTYPE mapping PUBLIC LIACS DTD ESPAM 1 EN http www liacs nl cserc dtd espam_1 dtd gt lt mapping name myMapping gt lt processor name mb_1 gt lt process name ND_0O lt process name ND_3 lt process name ND_4 lt processor gt lt processor name mb_2 gt lt process name ND_1 lt processor gt lt processor name
15. Modifying the maximum number of priorities in FreeRTOS 5 Now proceed with steps 7 11 from Section 3 1 3 6 After building the software perform steps 2 3 and 5 from Section 3 1 4 to program the FPGA 7 Now open a UART terminal and you should observe periodic messages from the applications together with the output computed by them This is illustrated in Figure 4 8 The period of the message from pipeline is around 500 ms while the messages from split_join have a period equal to around 1000 ms 24 CuteCom Open device Device l Close device Baud rate About Data bits Quit Stop bits Pipeline produced a Pipeline produced a Split join produced Pipeline produced a Pipeline produced a Split join produced Pipeline produced a Pipeline produced a Split join produced Pipeline produced a Pipeline produced a Split join produced Pipeline produced a Pipeline produced a Split join produced DNimnalina nxaduaand token 10 token 12 tokens 10 token 14 token 16 tokens 30 token 18 token 20 tokens 50 token 22 token 24 tokens 70 token 26 token 28 tokens 90 talan LINN Cear Hex output a5a5a5a5 12345678 10 30 50 70 90 dev ttyUSBO 115200 Parity None Handshake Software Open for Reading Apply settings when lt Hardware Writing pening 0D Append to A home mohamed cutecom log Input
16. Sobel filter SystemC Backend 0 000002 pees 3 2 1 Using the GNI as kee OEE REO BK OY Se He ES 3 2 2 Running the Timed SystemC Backend Manually Using Daedalus 4 1 Example I Multiple Applications FPGA Backend 2 2 2 000 GAN Uang the autotan senpt o ca sacr bee PED eS eee eee ee 4 1 2 Running the Daedalus Framework Manually 0 0 0 0 000000000 4 1 3 Building and Running the Generated Project 000000 ea Contributing to Daedalus Daedalus L Pe ea tho hee eee ee eh eae Ue hee eee ee eG eae eS 5 1 1 Building PNgen from the git repository 0 0 0 0 eee ee ee eee fee VAIS ga ee ee Shas Se ee ke ties eh bee TOPE R EE Ge EHR EEE eee 5 2 1 Building pntools from the git repository ono aoa aoa e e e See Aa earar aere eer a ee See DA EPAM essessirsdh he Epaian ikka reERE bE sa ekers bri 5 4 1 Building ESPAM from the git repository 2 0 eee ee ee ee 11 11 11 11 14 16 19 20 20 21 21 21 21 22 Table 1 Revisions of this user manual Author s 2012 09 10 Mohamed A Bamakhrama and Jiali Teddy Zhai Introduction This document serves as a manual for Daedalus and Daedalus users and developers Chapter 1 gives an overview of the frameworks Chapter 2 provides instructions on how to install them Chapter 3 explains how to use the Daedalus framework while Chapter 4 explains how to use the Daedalus framework Chapter 5 exp
17. TRL_B tie Imb_bra 3 00 b Bus and Bridge PCTRL_B tir Imb_bra 3 00 b Clock Reset and Interrupt BRAM1 ty bram_bl 1 00 a Communication High Speed DCTRL B ty Imb_bra 3 00 b Communication Low Speed PCTRL_B ti Imb_bra 3 00 b DMA and Timer ball CM_mb_1 yy bram_bl 1 00 a Debug 4 1 AXI_ CTR r axi bra 102a lw FPGA Reconfiguration Legend General Purpose IO WiMaster Slave Master Slave Target CInitiator Connected OUnconnected M Monitor 1O Modules Wf Production license paid License eval Q Local Upre Production B Beta XDevelopment Interprocessor Communication Superseded Discontinued KI i gt z Design Summary x amp System Assembly View x Console Hoes QINFO iMPACT 579 2 Completed downloading bit file to device a JINFO iMPACT 188 2 Programming completed successfully JpINFO iMPACT 2 Checking done pin done 2 Programmed successfully Elapsed time 21 sec Done v K gt Console Warnings Enrors Figure 3 16 Associating the host interface processor with its ELF file 7 You should now see the processed image being sent from the FPGA 3 2 Example II Sobel filter SystemC Backend In this example we show a step by step example of simulating the Sobel filter shown in Figure 1 3 using the timed SystemC backend of Daedalus We assume that you configured the SystemC installation path correctly during the 19 installation phase see
18. _if main_PLB cpp Figure 3 12 Step 7 Removing the un used PLB file 1 Associate the host interface processor host_if_mb with the correct ELF file which can be found under DAEDALUS_DIR examples sobel parallel sobel SDK host_if Debug host_if elf This is il lustrated in Figure 3 16 17 C C sobel_hw_platform system xml Eclipse Platform Edit Source Refactor Navigate Search Project Run Xilinx Tools Window Help ray a B ae Be dy Gy E Gy My Br Hr Ov ar amp He es E er amp Y o G system xml X A 8 outline 2 Make Target ja An outline is not available gt b BSP_host_if gt b BSP_P_1 gt th BSP_P_2 gt th BSP_P_3 y Ghost_if gt Binaries gt ia Includes gt amp Debug gt main_AXI cpp sobel_hw_platform Hardware Platform Specification Design Information Target FPGA Device xc6vlx240t Created With EDK 13 2 Created On Tue Jul 24 16 29 10 2012 New eb 1 Go Into Open in New Window Copy gt P3 0x 2000000 0x 200ffff Y sobel_hw_platform Delete Oxf1000000 0xf100ffff 0xb1000000 0xb100ffff xa0000000 O0xafffffff G system xml Rename 80010000 0x8001ffff Import x80020000 0x8002ffff Clean Project Refresh lose Projec Close Project 100000 0xf900000f 0ffff 0000 Oxe Build Configurations Make Targets ndex Show in Remote Systems view ple X N E Properties Terminal 1 2 F is GH AE Ee ef Gv civ 0
19. ally To run the Daedalus flow on the synthetic directory which can be found also under DAEDALUS_RT_DIR examples execute the following command DAEDALUS_RT_DIR scripts daedalus rt sh p DAEDALUS_RT_DIR examples synthetic The user will be asked to enter two parameters per application 1 the period scaling factor which is an integer multiplied by the minimum period of each actor in the application and 2 the maximum token size in 32 bit words in the application For both applications use period scaling factor 50 and maximum token size 1 The com mand in Figure 4 1 1 will generate a directory called output under the DAEDALUS_DIR examples synthetic directory The output directory contains the FPGA project in a directory called xps_project Now proceed to Section 4 1 3 for instructions on how to build and run the generated project 4 1 2 Running the Daedalus Framework Manually Daedalus shares the same steps for parallelization and system synthesis with Daedalus Therefore we show here only the steps specific for Daedalus The user can always refer to the auto run script to see the exact steps executed by the flow 21 Running pntools Daedalus replaces the DSE performed by Sesame with CSDF model derivation and hard real time multiproces sor schedulability analysis on the resulting CSDF graphs The first step is to derive the CSDF model required by the analysis To do that parallelize the applications using the instruc
20. apping spec Application spec in XML System level Pas a i in XML in Polyhedral Process Network specification ie Eo ett Models S gt Automated system level synthesis ESPAM SE c Platform IP cores RIL l 2 netlist in VHDL specification 5 S lt RTL synthesis commercial tool e g Xilinx Platform Studio E MOE EEOAE a uP HW IF g gt Gate level oe EEA p __ _Inter P gt a g connec H specification mea IN Mem MPSoC Figure 1 1 Overview of the Daedalus framework There is also a variant of Daedalus called Daedalus 3 which is targeted for designing hard real time embedded streaming systems Daedalus derives Cyclo Static Data Flow CSDF 4 graphs equivalent to PPNs used in the Daedalus framework and then uses hard real time multiprocessor scheduling theory in the Design Space Exploration DSE phase to determine the platform size and the mapping of tasks to processors Application i Parallelization PNgen _ User Input e g scheduler type WCET Analysis Analysis Model Analysis Model CSDF Derivation Mapping Spec Application Spec PPN System Synthesis ESPAM Platform Spec Figure 1 2 Overview of the Daedalus framework In the following sections we will describe in details each phase and the associated tools implementing it 1 1 Automatic Parallelization The first phase in the flow is the automatic paral
21. ding it The user can directly use the tools 5 4 ESPAM ESPAM is maintained by Todor Stefanov at the following git repository csartem ssh liacs nl espam git The access to this repository is restricted to selected users only For bug reports or any other inquiries please contact the maintainer 5 4 1 Building ESPAM from the git repository To build ESPAM from the git repository you need to clone the repository and follow the instructions in the README md file accompanying the cloned repository pa Bibliography 1 2 3 4 5 6 7 8 M Thompson H Nikolov T Stefanov A D Pimentel C Erbas S Polstra and E F Deprettere A frame work for rapid system level exploration synthesis and programming of multimedia MP SoCs in Proceed ings of the Sth IEEE ACM international conference on Hardware software codesign and system synthesis CODES ISSS 07 New York NY USA pp 9 14 ACM 2007 H Nikolov M Thompson T Stefanov A Pimentel S Polstra R Bose C Zissulescu and E Deprettere Daedalus toward composable multimedia MP SoC design in Proceedings of the 45th annual Design Au tomation Conference DAC 08 New York NY USA pp 574 579 ACM 2008 M Bamakhrama J Zhai H Nikolov and T Stefanov A methodology for automated design of hard real time embedded streaming systems in Proceedings of the 15th Design Automation and Test in Europe Conference and
22. eam Compare With Restore from Local History P ties Terminal 1 g amp mf Gy rv o Board Support Package Settings nee ee ot S GH BH Ex e ri Properties Compiling tmrctr Compiling cpu Running execs generate Finished building libraries th gb BSP_P_1 Figure 4 6 Opening the Board Support Package Settings window 4 Now click on freertos gt kernel_behavior gt max_priorities then change it to 10 as shown in Figure 4 7 Board Support Package Settings Board Support Package Settings Control various settings of your Board Support Package v Overview Configuration For OS freertos Freertos v drivers Name Value Default Type Description cpu stdin host_if_mb_RS232_U none peripheral Specify the instance name stdout host_if_mb_RS232_U none peripheral Specify the instance name systmr_interval 1000 10 integer Specify the time interval f Vv kernel_behavior true true boolean Parameters relating to th use_preemption true true boolean Set to true to use the pret idle_yield true true boolean Set to true if the Idle task max_priorities integer The number of task priori minimal_stack_size integer The size of the stack alloc total_heap_size integer Only used if heap_1 c or h max_task_name_len integer The maximum number of kernel_features boolean Include or exclude kernel hook_functions boolean Include or exclude applicz software_timers boolean Options relating to the so Figure 4 7
23. ete the main_PLB cpp file as shown in Figure 3 12 8 Next we need to set up the linker scripts and debugging optimizations options for the P_ projects Note Correct ELF files will NOT be generated without performing this step To change the optimization debugging options right click on each P_ project and select C C Build Settings as shown in Figure 3 13 14 C C sobel_hw_platform system xml Eclipse Platform Project Run Xilinx Tools rv BE a Bd Gv Gv iy Gr Ov Q a g7 E ac rF Project Explorer X B amp Y o E system xml X A B Outline X Make Target m v sobel_hw_platform sobel_hw_platform Hardware Platform Specification An outline is not available amp Design Information Target FPGA Device xc6vlx240t Created With EDK 13 2 Created On Tue Jul 24 16 29 10 2012 Address Map for processor mb_1 fin_ctrl_P1 0x 9000000 ox 9000 LMB_CTRL_CM_mb_1 0xe0000000 0xe000ffff DCTRL_BRAM1_mb_1 0x0000000 ffff PCTRL_BRAM1_mb_1 0x0000000 f mb_1_intc 0x 200000 mb_1_timer 0x 1000000 0 host_if_mb_RS232_Uart 0xb1i00000 DDR3_SDRAM 0xa0000000 Oxafffffff AXI_CTRL_CM_mb_1 0x80010000 0 O1ffft AXI_CTRL_CM_mb_2 0x80020 AXI_CTRL_CM_mb_3 0x8003000 mb_1_ddr_axi2axi_connector 9x20000000 0 mb_1_axi2axi_connector 0x80000000 Ox8ffftttt 0 ooo o oo a Address Map for processor mb_2 fin_ctrl_P2 0x 9000000 oxf900000f LMB_CTRL_CM_mb_2 0xe0000000 0xe000ffff DCTRL_BRAM1_mb_2 0x000 f O
24. g Information Levi Repositories Target Manager Remove SDK Installation Repositories Rescan Repositories Note Local repository settings take precedence over global repository settings Restore Defaults Apply Figure 4 5 Specifying the BSP location 23 2 Now continue with steps 2 6 from Section 3 1 3 After Step 6 return here 3 After importing the projects successfully we need to modify the maximum number of priorities supported by FreeRTOS The default value is 4 however in this example we map 8 tasks onto a single processor Right click on BSP_P_1 and then click on Board Support Package Settings as shown in Figure 4 6 C C xps_project_hw_platform system xml Eclipse Platform Edit Source Refactor Navigate Search Run Project Xilinx Tools Window Civ mm G amp Bd giv r iv Gv ty Ov Q e g7 e vy E Tac A Ge system xml 8 0 52 Ou X Mma O xps_project_hw_platform Hardware Platform Specification An outline is not available Design Information New Go Into gt xps_project_hw_platform ies anaes AAE AS Copy Delete Rename Import Export DO Ox8001FFFE Clean Project JO oxbfffffff Build Project Refresh BO ox8fffffff Close Project 0x00003fff 000 0x0a00000f O3ffE offft offff Build Configurations Make Targets Index Show in Remote Systems view ooffft afffffff Oxbfffffff Run As pi Debug As Profile As T
25. gether with the individual tools of the frameworks can be downloaded for free from http daedalus liacs nl All the releases have names of the form release_yyyymmdd where yyyymmdd is the date of the release Therefore the user can easily determine the latest release Please note that we provide support only for problems related to the latest releases of the tools 2 3 Installing the Daedalus Framework We provide a script that installs the whole Daedalus framework automatically on a Linux machine To run this script open a command line terminal and execute the commands shown in Figure 2 1 mkdir daedalus cd daedalus wget http daedalus liacs nl daedalus release_yyyymmdd setup_daedalus sh chmod x setup_daedalus sh setup_daedalus sh s systemc path j jdk path h c d Figure 2 1 Commands needed to install the Daedalus framework yyyymmdd stands for the release date The setup script accepts several options The full list of options and usage can be shown by passing h option which shows a help message 2 4 Installing the Daedalus Framework We provide a script that installs the whole Daedalus framework automatically on a Linux machine To run this script open a command line terminal and execute the commands shown in Figure 2 2 mkdir daedalus rt cd daedalus rt wget http daedalus liacs nl daedalus rt release_yyyymmdd setup_daedalus rt sh chmod x setup_daedalus rt sh setup_daedalus rt sh s systemc path
26. h for existing Eclipse projects d _ Select archive file Browse Projects SelectAll Deselect All Refresh _ Copy projects into workspace Working sets _ Add project to working sets Working sets Select Next gt Finish Figure 3 10 Step 5 3 1 4 Programming the FPGA and Running the Application Now go back to XPS and perform the following steps 16 Import Projects amp Some projects cannot be imported because they already exist in the 1 workspace Select root directory jedalus examples sobel parallel sobel SDK Browse Select archive file Browse Projects BSP_host_if home mohamed workspace codeplex daedalus e Select All BSP_P_1 home mohamed workspace codeplex daedalus exa BSP_P_2 home mohamed workspace codeplex daedalus exa Deselect All BSP_P_3 home mohamed workspace codeplex daedalus exa Refresh host_if home mohamed workspace codeplex daedalus exam P_1 home mohamed workspace codeplex daedalus examples P_2 home mohamed workspace codeplex daedalus examples P_3 home mohamed workspace codeplex daedalus examples _ Copy projects into workspace Working sets Add project to working sets Select Figure 3 11 Step 6 C C sob xml Eclipse Platform a O X I S W ow Help riv ale ml a Gy E Ge s Be Hr Or Q leg m agde r B amp Y ol system xml X A 2 Outl
27. ine X Make Target gt sobel_hw_platform Hardware Platform Specification An outline is not available Design Information Target FPGA Device xc6vlx240t Created With EDK 13 2 Created On Tue Jul 24 16 29 10 2012 v igs host_if gt K Includes gt Debug gt main_AXI cpp gt el Address Map for processor mb_1 fin_ctrl_P1 0x 9000000 oxf900000f me0000000 0xe000ffff 00000000 0x0001ffff 00000000 0x0001ffff met 2000000 0xf200ffff 1000000 Oxf100fFFE b1000000 0xb100ffff 20000000 Oxafffffft 80010000 0x8001ffff 80020000 0x8002ffff 80030000 0x8003ffff a0000000 Oxbfffffff 80000000 Ox8fffffff v sobel_hw_platform 3p system xml mt 9000000 0xf900000f r 0000000 Oxe000ffff 00000000 0x0001ffff i 00000000 0x0001ffff 2000000 Oxf200ffff l z E Properties Terminal 1 YF s GE BE Ee rf Gv iv 0 at UNSIJV_SENUDY LE Was NUC UEC tareu IN MIS Stupe XUartNs550 SendByte was not declared in this scope XUartNs550 SendByte was not declared in this scope xUartNs550 SendByte was not declared in this scope main PLB cpp 128 error main PLB cpp 135 error XUartNs550 SendByte was not declared in this scope main PLB cpp 150 error XUartNs550 SendByte was not declared in this scope main_PLB cpp 34 warning unused variable PARAM main PLB cpp 52 warning unused variable timel make main PLB o Error 1 mh es host
28. ity analysis 3 This phase contains analysis model derivation and analysis as shown in Figure 1 2 pntool1s is used to derive analysis model in the form of CSDF darts toolbox performs analysis based on hard real time multiprocessor scheduling theory to derive the minimum number of processors needed to schedule the applications while guaranteeing a certain throughput together with the mapping of tasks to processors 1 4 System Synthesis The last step is the system synthesis which is implemented using the ESPAM tool 7 The inputs to this step are 1 a set of PPNs 2 the platform specification and 3 the mapping specification After that After that ESPAM generates an MPSoC platform that can run the parallelized applications The generated platform consists of the hardware specifications together with the parallel C code include sobel_func h define N 450 image width define M 275 image height int main void int i j static int image M N static int Jx M N static int Jy M N static int av M N for j 1 j lt M j for i 1 i lt N i readPixel amp image Lj i for j 2 j lt M 1 j for i 2 i lt N 1 i gradient amp image j 1 i 1 amp image j i 1 amp image j 1 i 1 amp image j 1 i 1 amp image j i 1 amp image j 1 i 1 amp Jx j i for j 2 j lt M 1 j for i 2 i lt N 1 i gradient amp image j 1 i
29. l o fpga The command in Figure 3 1 1 will generate a directory called parallel under the DAEDALUS_DIR examples sobel directory The parallel directory contains the FPGA project in a directory called sobel Now proceed to Section 3 1 3 for instructions on how to build the generated project using Xilinx tools 3 1 2 Running the Daedalus Framework manually For the reader interested in understanding the inner workings of the Daedalus flow we provide here a detailed description of the commands executed by the auto run script The user can always refer to the auto run script to see the exact steps executed by the flow 1 Running PNgen First copy the contents of directory DAEDALUS_DIR examples sobel sequential into a new directory called DAEDALUS_DIR examples sobel parallel Inside the parallel directory make a new directory called func_code and copy the following files into it sobel_func h and sobel_func cpp Then to produce the PPN specifications open a command line terminal and execute the commands shown in Figure 3 1 cd parallel PN_DIR bin c2pdg func main sobel c PN_DIR bin pn lt sobel yaml gt sobel pn yaml PN_DIR bin pn2adg xml lt sobel pn yaml gt sobel kpn Figure 3 1 Commands to generate the PPN of the Sobel example The resulting sobel kpn file is an XML file containing the PPN representation of the application This file represents the input to ESPAM The resulting PPN can be visualized using the dotty too
30. l as shown in Figure 3 2 PN_DIR bin pn2dot lt sobel pn yaml gt sobel pn dot dotty sobel pn dot Figure 3 2 Visualizing the resulting PPN Specifying Platform and Mapping files Daedalus provides the ability to either specify the platform mapping specifications manually or derive them using Sesame We start by showing the first option We can manually specify the platform specification sobel pla to be used and the assignment sobel map of PPN processes to processing resources 1 e Xilinx MicroBlaze MB in this case In the next subsection we show how to generate sobel pla and sobel map files automatically using Sesame Figure 3 3 shows an example of a platform file containing three MBs interconnected via AMBA AXI crossbar Here we explain the important attributes to be specified in the platform file and their meaning e MB type of processor Xilinx MicroBlaze MB e data_memory 65536 size of local data memory in bytes 65536 in this case e program_memory 65536 size of local program memory in bytes 65536 in this case e lt network name CS type AXICrossbarSwitch gt type of interconnection AXICrossbarSwitch denotes AMBA AXI crossbar Otherwise if no network is specified Xilinx Fast Simplex Link FSL FIFOs are assumed to interconnect MBs FSL FIFOs are automatically instantiated between MBs according to the given mapping file explained later on e lt host_interface name HOST_IF type ML605 interface UART gt
31. lains how to contribute to the development of the tools Acknowledgments The work on Daedalus framework has been supported by the following Dutch and European organizations Nether lands Organisation for Scientific Research NWO Technology Foundation STW European Union EU Seventh Framework Programme FP7 CATRENE MEDEA and others List of Contributors Many people have contributed over the years to the Daedalus Daedalus frameworks Below we provide an incomplete list of the contributors in alphabetical order We would like to apologize in advance from anyone whom we forgot to add his her name Mohamed Bamakhrama Ed Deprettere Cagkan Erbas Ji Gu Sven van Haastregt Kai Huang Joris Huizer Dmitry Nadezhkin Hristo Nikolov Andy Pimentel Simon Polstra Todor Stefanov Ying Tao Mark Thompson Sven Verdoolaege Jiali Teddy Zhai Wei Zhong Chapter 1 Overview Daedalus 1 2 is a system level design flow for designing multiprocessor systems on chip MPSoC running embedded streaming applications Sequential Functional programin C specification Manually creating a PPN e System level design space exploration Parallelization z ei Sesame PNgen 2 High level amp Models S Platform spec M
32. lelization shown in Figure 1 1 The PNgen compiler 5 is used to derive a parallel specification of the applications in the form of Polyhedral Process Networks PPN 5 from a C program The input to the PNgen compiler is a set of C files The top level C file has to conform to a constrained form known as static affine nested loop programs SANLP 5 This constrained form allows to determine the data dependencies and in turn derive a parallel specification of the program in the form of Polyhedral Process Networks PPN 5 An example of a SANLP program is shown in Figure 1 3 The program shown in Figure 1 3 implements the edge detection Sobel filter This constrained form does not apply to the set of C files implementing all functions in the top level C file For example for the Sobel filter the implementation of functions readPixel gradient absVal and writePixel may contain arbitrary C code and they are stored in a header file called sobel_func h 1 2 Design Space Exploration The second phase is the design space exploration which accepts as an input a set of PPNs and their equivalent CSDF graphs in case of Daedalus Daedalus uses the Sesame framework 6 to perform the DSE The timing guarantees provided by the resulting platform are best effort 1 3 Hard Real Time Schedulability Analysis Once designing a hard real time embedded streaming systems using Daedalus is desired the second phase is replaced by hard real time schedulabil
33. mb_3 gt lt process name ND_2 lt processor gt lt mapping gt Figure 3 4 An example of a mapping file Running ESPAM To run ESPAM and generate the MPSoC implementation open a terminal and execute the command shown in Figure 3 5 After invoking ESPAM a directory called sobel will be generated which contains a Xilinx Platform Stu 13 ESPAM_DIR bin espam adg sobel kpn platform sobel pla mapping sobel map xps libxps ESPAM_DIR src espam 1libXPS sdk libsdk ESPAM_DIR src espam 1ibSDK funcCodePath func_code Figure 3 5 Running the system synthesis tool is used to break the command over multiple lines dio XPS project containing the MPSoC implementation Currently ESPAM supports generating XPS projects compatible with XPS 13 2 and later 3 1 3 Building the Project using Xilinx Tools After you generate the Xilinx Platform Studio XPS project using ESPAM through either the auto run script or manual steps you will find the generated project under DAEDALUS_DIR examples sobel parallel sobel Open the project using Xilinx Platform Studio 13 2 or later and perform the FPGA synthesis After the synthesis is completed and you have a bitstream export the project to Xilinx SDK Upon exporting the project to SDK SDK will launch You need to perform the following steps to import and build the software projects 1 Upon launching SDK you will prompted for the workspace location as shown in Figure 3
34. ng Daedalus In this chapter we provide several examples on how to use the Daedalus framework Throughput this chapter we assume that the variables shown in Table 3 1 store the full paths pointing to the corresponding tools in the Daedalus framework Table 3 1 Variables storing the full paths to Daedalus tools DAEDALUS_DIR The full path to the directory where Daedalus is installed The full path to the directory where PNgen is installed The full path to the directory where Sesame is installed The full path to the directory where ESPAM is installed The examples in this chapter refer to Daedalus release release_20120907 The source code of the examples can be found under DAEDALUS_DIR examples 3 1 Example I Single Application FPGA Backend In this example we show a step by step example of implementing the Sobel filter shown in Figure 1 3 on an FPGA based MPSoC The MPSoC platform consists of three Xilinx MicroBlaze processors running on Xilinx ML605 FPGA board 3 1 1 Using the auto run script In the directory where Daedalus is installed a script called daedalus sh can be found at the following loca tion DAEDALUS_DIR scripts daedalus sh This script can be used to invoke all the different components of Daedalus automatically To run the Daedalus flow on the Sobel example which can be found also under DAEDALUS_DIR examples sobel execute the following command DAEDALUS_DIR scripts daedalus sh p DAEDALUS_DIR examples sobe
35. o FPGA command in XPS 6 After the FPGA programming is done run the command serial_m1605 which you built previously 18 Generate a linker script Generate linker script Control your application s memory map Output Settings Project P_1 Output Script aedalus examples sobel parallel sobel SDK P_1 lscript ld Browse Modify project build settings as Follows Set generated script on all project build configurations Hardware Memory Map Memory Base Address Size PCTRL_BRAM1_mb_1_DCTRL 0x00000000 128 KB LMB_CTRL_CM_mb_1 0xE0000000 64KB DDR3_SDRAM_S_AXI_BASEA 0xA0000000 256 MB AXI_CTRL_CM_mb_1_S_AXI_ 0x80010000 AXI_CTRL_CM_mb_2_S_AXI_ amp 0x80020000 AXI_CTRL_CM_mb_3_S_AXI_f 0x80030000 64KB 64KB 64KB Basic Advanced Place Code Sections in Place Data Sections in PCTRL_BRAM1_mb_1_DCTRL_BRA PCTRL_BRAM1_mb_1_DCTRL_BRA Place Heap and Stack in PCTRL_BRAM1_mb_1_DCTRL_BRA Heap Size Stack Size 8 KB 8 KB gt Fixed Section Assignments Figure 3 15 Step 10 Generating the correct linker script Xilinx Platform Studio EDK_O 61xd home mohamed tests daedalus examples sobel parallel sobel system xmp System Assembly View Device Configuration Debug Simulation Window Help ales a Rok Z File Edit View Project Hardware Hog SAO DEN
36. o graphs are passed pipeline and split_join Each graph is preceded by a period scaling factor e g 50 and the maximum token size in 32 bit words in the applica tion The period scaling factor is an integer that gets multiplied by the minimum period of each actor in the application For both applications we use period scaling factor 50 and maximum token size 1 After invoking PlatformGenerator py two files will be generated in 0UTPUT_DIR 1 platform pla which contains the platform specification and 2 mapping map which contains the mapping specification These two files serve as the input to ESPAM Now you can invoke ESPAM using the command shown in Figure 4 3 ESPAM_DIR bin espam adg pipeline kpn adg split_join kpn platform platform pla mapping mapping map xps libxps ESPAM_DIR src espam 1ibXPS sdk libsdk ESPAM_DIR src espam 1libSDK funcCodePath DAEDALUS_RT_DIR examples func_code Figure 4 3 Running ESPAM to synthesize the platform with multiple applications is used to break the command over multiple lines Now proceed to Section 4 1 3 for instructions on how to build and run the generated project 4 1 3 Building and Running the Generated Project To build and run the generated project perform the following steps 1 Follow the steps from Section 3 1 3 for building the hardware part of the generated project using Xilinx tools For the software part perform step 1 by setting the workspace to D
37. q http nl archive ubuntu com ubuntu pool universe s syck libsyck0 dev_0 55 svn270 1_amd64 deb sudo dpkg i libsyck0O dev_0 55 svn270 1_amd64 deb wget q http daedalus liacs nl pngen release_20120706 clang llvm 2 9 x86_64 linux tar bz2 tar xvjf clangt llvm 2 9 x86_64 linux tar bz2 CWD pwd git clone git repo or cz isa git cd isa get_submodule sh autogen sh configure prefix CWD pngen with clang prefix CWD pngen clangt llvm 2 9 x86_64 linux tar make make check make install Figure 5 1 Steps to install PNgen on 64 bit Ubuntu without building the libraries required by PNgen 5 2 pntools pntools is maintained by Sven van Haastregt and Jiali Teddy Zhai at the following git repository csartem ssh liacs nl pntools git The access to this repository is restricted to selected users only For bug reports or any other inquiries please contact one of the maintainers 26 5 2 1 Building pntools from the git repository To build pntools from the git repository you need to clone the repository and follow the instructions in the README md file accompanying the cloned repository 5 3 darts darts is maintained by Mohamed Bamakhrama at the following git repository csartem ssh liacs nl darts git The access to this repository is restricted to selected users only For bug reports or any other inquiries please contact the maintainer darts is developed in Python and therefore does not require any steps for buil
38. stall pntools open a command line terminal and execute the commands shown in Figure 2 4 setup_pntools sh takes two options The first option is pngen_path which is the full path to an existing PNgen installation If pngen_path is not specified then the script will install PNgen from scratch The second option is clean which cleans the pntools directory from all the generated installed files 2 5 3 Installing Sesame TBD 2 5 4 Installing darts darts stands for Dataflow Analysis for Hard Real Time Scheduling is a tool set for performing hard real time multiprocessor scheduling analysis on CSDF graphs To install it open a command line terminal and execute the commands shown in Figure 2 5 mkdir darts cd darts wget http daedalus liacs nl darts release_yyyymmdd setup_darts sh chmod x setup_darts sh setup_darts sh clean Figure 2 5 Commands needed to install darts 2 5 5 Installing ESPAM ESPAM is the system synthesis tools of Daedalus and Daedalus To install it open a command line terminal and execute the commands shown in Figure 2 6 j option can be used to pass the path to Java JDK installation while mkdir espam cd espam wget http daedalus liacs nl espam release_yyyymmdd setup_espam sh chmod x setup_espam sh setup_espam sh j jdk path s systemc path c h Figure 2 6 Commands needed to install ESPAM the s option can be used to pass the path to SystemC installation 10 Chapter 3 Usi
39. tions given in Section 3 1 2 Then open a terminal and execute the commands shown in Figure 4 1 PN_DIR bin pn2adg lt pipeline pn yaml gt pipeline adg yaml PNTOOLS_DIR adg2csdf lt pipeline adg yaml gt pipeline gph PNTOOLS_DIR adg2csdf 3 lt pipeline adg yaml gt pipeline xml Figure 4 1 Deriving CSDF from PPN Steps shown only for pipeline The resulting pipeline gph and pipeline xm1 files contain the CSDF graph representation The gph file contains the graph in a format derived from the StreamIt format while the xm1 file contains the graph in the XML format support by SDF 8 You have to repeat the steps shown in Figure 4 1 for the split_join application Running darts darts allows deriving the platform and mapping specifications for a given set of CSDF graphs To generate the platform and mapping specifications open a terminal and execute the commands shown in Figure 4 2 DARTS_DIR PlatformGenerator py o m RM FF a 50 1 pipeline gph a 50 1 split_join gph Figure 4 2 Deriving the platform and mapping specifications PlatformGenerator py takes the following input arguments e o which sets the directory where the platform and mapping specifications will be generated to the current directory e The scheduling and allocation method In Figure 4 2 it is set to fixed priority preemptive scheduling with rate monotonic priority assignment and first fit allocation e A set of CSDF graphs In Figure 4 2 tw
40. verview Source amp Problems 4 Tasks E Console X E Properties Terminal 1 Ee BE rf fiv O DK Log 16 32 27 INFO Processing command line option hwspec home mohamed workspace codeplex daedalus examples sobel parallel sobel SDK SDK Export hw system xml g Figure 3 7 Step 2 The imported hardware platform in SDK C C sobel_hw_platform system xml Eclipse Platform Project Run Xilinx E a c r B Outline 3 Make Target m An outline is not available Open File m Close Close All pel hw_platform Hardware Platform Specification ign Information get FPGA Device xc6vlx240t Created With EDK 13 2 Created On Tue Jul 24 16 29 10 2012 dress Map for processor mb_1 Fin_ctrl_P1 0x 9000000 ox 900000 Convert Line Delimiters To LMB_CTRL_CM_mb_1 0xe0000000 0xe000fffE DCTRL_BRAM1_mb_1 0x 00001 O1ffft PCTRL_BRAM1_mb_1 0x0000000 Switch Workspace mb_1_intc 0x 200000 mb_1_timer 0x 1000000 Restart host_if_mb_RS232_Uart 0xb100000 OOffft Import DDR3_SDRAM 0xa0000000 0xafffffff Export AXI_CTRL_CM_mb_1 0x80010000 0x8001ffff AXI_CTRL_CM_mb_2 0x8002000 AXI_CTRL_CM_mb_3 0x80030000 0 system xml sobel_hw_platform D_1_ddr_axi2axi_connector 09x20000000 02 mb_1_axi2axi_connector 0x80000000 0x8fffffff Properties cbfffffff Address Map for processor mb_2 fin_ctrl_P2 0x 9000000 0 LMB_CTRL_CM_mb_2 0xe0000000 0 DCTRL_BRAM1_mb_2
41. with sources to this directory Then invoke make and make run under sobel_systemc 20 Chapter 4 Using Daedalus In this chapter we provide an example on how to use the Daedalus framework Throughput this chapter we as sume that the variables shown in Table 4 1 store the full paths pointing to the corresponding tools in the Daedalus framework Table 4 1 Variables storing the full paths to Daedalus tools The full path to the directory where Daedalus is installed The full path to the directory where PNgen is installed PNTOOLS_DIR The full path to the directory where pntool1s is installed The full path to the directory where darts is installed The full path to the directory where ESPAM is installed The examples in this chapter refer to Daedalus release release_20120907 The source code of the exam ples can be found under DAEDALUS_RT_DIR examples synthetic 4 1 Example I Multiple Applications FPGA Backend In this example we show a step by step example of implementing two synthetic applications called pipeline and split_join on an FPGA based MPSoC The MPSoC platform uses Xilinx MicroBlaze processors running on Xilinx ML605 FPGA board 4 1 1 Using the auto run script In the directory where Daedalus is installed a script called daedalus rt sh can be found at the following location DAEDALUS_RT_DIR scripts daedalus rt sh This script can be used to run all the different parts of the flow automatic
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