AT 1212R User Guide and Specifications
Contents
1. Figure 4 CLIP Relationship The AT 1120 ships with socketed CLIP items that are used to add module I O to the LabVIEW project The AT 1120 ships with the following CLIP item AT_1120_IOModule_CLIP AT 1120 User Guide and Specifications 10 www activetechnologies it AT 1120 CLIP DESIGN The DAC contains two parallel LVDS input ports consisting of 14 differential LVDS signals DB 13 0 Each data port runs internally at half the speed of the DAC Clock 2 GHz so the user needs to guarantee them the correct data rate The installed multiplexer selects the DAC clock source it can be internal from Clock Generator circuit output or external from SMA connector The adapter module has a Clock Generator circuit that provides the 2 GHz clock to the DAC the clock generator source clock can be provided by 25 MHz onboard TCXO or by PXI_e DSTAR A backplane connection The uController write read the DAC parameters the Clock Gen registers and control the multiplexer output It performs also the Power up sequencing 500MHZ Data Bus 1 with Clock uController Clock Gen 12C Memory Ae ei H E OU Le E el UO ll D as De me Ae bal 2 O co x E LU loModSyncClk 125MHz This CLIP provides read write access to all FPGA look up tables that are included in the project The data read from the look up tables are serialized by the CLIP to provide the requested data rate to the DAC Clip files AT_1120_lOModule_CL2. sample reference waveform representing one cycle of our repetitive waveform The core component of a DDS waveform generator is the accumulator The accumulator is a running counter which stores the current phase value of the generated waveform Increment parameter represents the value the accumulator is updated determining the frequency of the generated waveform A more detailed description of DDS can be found in Understanding Direct Digital Synthesis DDS AT 1120 User Guide and Specifications 15 www activetechnologies it LabView Interface Host Side Host VI CLIP Description InitWModule1120 Host vi Initialize the 1120 adapter module If the adapter has been correctly initialized DAC A Aligned and DCM Locked indicators must be true To enter in Debug mode set DEBUG as true Input Parameters FPGA VI Reference IN FPGA reference RIO Device CLOCK SELECTION DAC Clock source selection INTERNAL CLOCK Clock Generator input source Error in Output Parameters FPGA DCM LOCKED if true the FPGA DCM has locked DAC A Aligned if true the DAC has been correctly initialized and aligned Error out IMPORTANT NOTE the user should NOT hit the ABORT button during the initialization SetVocm vi Set the Vocm voltage AT 1120 User Guide and Specifications 16 www activetechnologies it Host VI Target Example Description WriteTables Host vi The WavefArray contains the wavef
3. AT 1120 C Program Files National Instruments Shared FlexRIO IO Modules AT 1212 Example Code Review for AT 1120 adapter module DACModuleControl Host exe Software requirements Labview 2012 Modulation Toolkit This LabView application gives the user full access to all the main 1120 1212 features The control panel provides a waveform generator style approach to the FAM allowing to set the parameters of the signals that will be load and generated by the FAM The source file DACModuleControl Host vi is located into the folder LabViewDesigns AT_HS_Signal_GeneratorLV2012 and it needs the NI Modulation toolkit http sine ni com nips cds view p lang en nid 210568 to run properly otherwise it is possible to make some modifications on the code to exclude the QAM BPSK modulations and run it without the toolkit AT 1120 User Guide and Specifications 18 www activetechnologies it Edit Operate Tools Window Help p leie d ADAPTER NAME Selected Channel lo oa10m ov AO 0 S www activetechnologies i DDS Frequency Ld DDS MODE ARB MODE 976 562k Sweep Freq Incr iM Sweep Freq Max 200M m Amplitude 4500 Phase degrees Zo Order Waveform mplig Fr JO Clock Selection Reset amp INIT Internal af RUN SELECTED CH Trig OUTSND Trig INF C Internal Clock Source MODULE READY v From Oscillator d 3 2 DAC Aligned LOAD WAVEFORM d e Select the resource name t
4. Bit Paths C Program Files x86 National Instruments Shared FlexRIO IO Modules AT 1120 C Program Files x86 National Instruments Shared FlexRIO IO Modules AT 1212 32 Bit Paths C Program Files National Instruments Shared FlexRIO IO Modules AT 1120 C Program Files National Instruments Shared FlexRIO IO Modules AT 1212 The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get you started creating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA example project to generate signals with the AT 1120 This example requires at least one SMA cable for connecting signals to your AT 1120 ei Note The examples available for your device are dependent on the version of the software and driver you are using Each AT 1120 example project includes the following components e A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware This VI is referred to as the FPGA Target VI e A VI that runs on Windows that interacts with the LabVIEW FPGA VI This VI is referred to as the Host VI Complete the following steps to run an example that generates a waveform on AO 0 of the AT 1120 1 Connect one end of an SMA cable to AO 0 on the front panel of the AT 1120 and the other end of the cable to your oscilloscope input 50 Tap the unused output AO 0 with a 50 Q load 2 Launch LabVIEW AT 1120 User Guide and Specifications 23 www activetec
5. User Guide and Specifications 32 www activetechnologies it 15 16 17 18 19 20 21 ticks p Gu WM 540 MHz Onboard Clock H SysReset 10 Module lockedfast k z ETE 10 Module trig_out O Module reset_in_ 10 Module trig_in CikEnable s Ga ReadDatal2c Wire controls and indicators from the input output terminals datai2c0 datai2c1 datai2c2 datai2c3 datai2c4 datai2c5 readdatal2c startrdi2c startwri2c reset_in trig_in trig_out clkenable clocksel and lockedfast Wire the 40MHz Onboard Clock to the clock loop Add another Timed Loop as shown in the figure below and right click to open the LabView palette Select the FPGA I O palette and add an I O node O ticks ZG 0 510 Module Clock 0 START CHANNELS Gf False vP e PA Memory 87 Read Address Data Wire the datadac_chO_inO_ datadac_chO_in15 connectors as in the picture above Wire the IO Module Clock 0 to the clock loop Right click to open the LabView palette Select the Memory amp FIFO palette and add a Memory Method node Right click on the Memory method Select Memory gt gt Memory1 Left click on the Memory1 Memory Method and select the Read method Insert a new shift register in the Timed
6. an NI FlexRIO FPGA module and the AT 1120 This document contains tutorial sections that demonstrate how to generate signals using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the AT 1120R 3 Note Before configuring your AT 1120 you must install the appropriate software and hardware Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation instructions Figure 1 shows an example of a properly connected NI FlexRIO device NI FlexRIO H NI FlexRIO Adapter Module FPGA Module NI FlexRIO Device Figure 1 NI FlexRIO Device 3 Note AT 1120R refers to the combination of your AT 1120 adapter module and your NI FlexRIO FPGA module AT 1120 refers to your AT 1120 adapter module only WARNING NI 7965R cannot be used with AT 1120 It is recommended to use the NI 7966R instead WARNING LabVIEW 2012 must be used with AT 1120 adapter module AT 1120 User Guide and Specifications 4 www activetechnologies it Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility EMC as stated in the product specifications These requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in its intended operational electromagnetic environment This product is intended for use in industrial locations There is no guarantee
7. connector on the AT 1120R can damage the device and the chassis Active Technologies is not liable for any damage resulting from such signal connections For the maximum input and output ratings for each signal refer to the Specifications sheet AT 1120 User Guide and Specifications 9 www activetechnologies it AT 1120 Component Level Intellectual Property CLIP The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP NI FlexRIO devices support two types of CLIP user defined and socketed User defined CLIP allows users to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI eSocketed CLIP provides the same IP integration functionality of the user defined CLIP but it also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface Figure 4 shows the relationship between an FPGA VI and CLIP NI FlexRIO FPGA Module FPGA User Defined CLIP Adapter Module CLIP Socket LabVIEW FPGA VI User Defined CLIP Adapter Module Socketed z m CLIP Fixed UO External UO Connector DRAM 0 DRAM 1 CLIP Socket CLIP Socket Socketed Socketed CLIP CLIP Fixed UO Fixed UO DRAMO DRAM1
8. structure inside the loop 24 Place an Event Structure inside a While Loop Connect and Add an Event Case on the Stop button value change Place the StopGeneration Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the FPGA VI Reference IN gt FPGA Reference and place Close FPGA VI Reference block located on FPGA Interface wiring it like in the picture below The second frame contains the True constant to stop the VI AT 1120 User Guide and Specifications 29 www activetechnologies it 1 STOP Value Change 7 Running the Host VI 1 Connect one end of an SMA cable to AO O on the front panel of the AT 1120 and the other end to the oscilloscope 50 Q input Tap the unused input AO 0 with a 500 load Open the front panel of GenerateSine1120 Host vi Click the Run button to run the VI Wait for module initialization The AT 1120 generates one 128 points sine waveform Click the STOP button on the front panel to stop the module and the VI AT 1120 User Guide and Specifications 30 www activetechnologies it Creating a Custom FPGA Target This section explains how to create your custom target and setup an host VI for waveform generation PLEASE NOTE THE FOLLOWING The custom FPGA Target of this tutorial reads a sine waveform data from the Memory1 lookup table 2048 samp
9. that harmful interference will not occur ina particular installation when the product is connected to a test object or if the product is used in residential areas To minimize the potential for the product to cause interference to radio and television reception or to experience unacceptable performance degradation install and use this product in strict accordance with instructions in the product documentation Furthermore any changes or modifications to the product not expressly approved by Active Technologies could void your authority to operate it under your local regulatory rules UN Caution To ensure the specified EMC performance you must install PXI EMC Filler Panels National Instruments part number 778700 01 in adjacent chassis slots For more information about installing PXI EMC filler panels on your NI 5762R refer to the Appendix Installing EMI Controls section of this document A N Caution To ensure the specified EMC performance operate this product only with shielded cables and accessories Caution This product is sensitive to electrostatic discharge ESD gt AT 1120 User Guide and Specifications 5 www activetechnologies it How to Use Your NI FlexRIO Documentation Set Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set INSTALL Hardware and Software CONNECT Signals and Learn About Your Adapter Module LEARN About LabVIEW FPGA Module N
10. 0 1CH in the Adapter Name pull down menu Select AO 0 in the Selected Channel pull down menu Select ARB in the DDS ARB control Select Internal in the Clock Selection pull down menu and From Oscillator in the nternal Clock Source pull down menu 10 Click the Run button to run the VI 11 Wait until Module Ready and DAC Aligned leds become green 12 Select the Waveform you want to generate by using Waveform pull down menu and choose its parameters 13 Press the Apply button to update the Waveform Graph 14 Press the Load Waveform button to load the samples into the FAM AT 1120 User Guide and Specifications 24 www activetechnologies it 15 Press the RUN SELECTED CH button to start the waveform generation 16 Press the STOP button to stop the generation 17 Press the EXIT VI button to stop the VI AT 1120 User Guide and Specifications 25 www activetechnologies it Creating a Host VI on an FPGA Target This section explains how to set up your target and create an host VI for waveform generation Note the following tutorial can be found under the directory AT_HS_SignalGenerator GenerateSine1120 Host vi 1 Inthe Project Explorer window right click My Computer and select New VI A blank VI opens 2 Add a Waveform Graph indicator in the front panel 3 Add the RIO Device control located on Modern gt 1 0 palette 4 Adda STOP button located on Express gt Buttons amp Switches 5 Adda LED indicator INIT
11. 0 User Guide and Specifications 21 www activetechnologies it Once the VI has started the pulse waveform will be uploaded into the FPGA look up tables on all available channels e Press the RUN button to start the waveform generation DDS and Trigger Route vi Software requirements LabView 2012 This VI gives the user access to the clock generated by PXle 6674T NI Timing board and to the DSTARA DSTARB clock global trigger routing e Set the DDS frequency to 125 MHz and fill the Destination Terminal Array The Destination Terminal Array should contain all the PXle_DSTARA connection to the FlexRIO boards that will provide the same reference clock to the adapter module refer to the chassis manual e Pill the Destination Trigger Array with the PXle_DSTARB global trigger routing connections The FlexRIO boards will receive now the same trigger signal e Press the Send Trigger button to send it to all connected FAMs AT 1120 User Guide and Specifications 22 www activetechnologies it Using Your AT 1120 with a LabVIEW FPGA Example VI i Note You must install the software before running this example Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for more information about installing your software You must copy the following files tbc xml and vhdl in the FlexRIO working paths a Open the installation folder KML_VHDL b Copy the XML_VHDL AT 1120 and KML_VHDL AT 1212 folders into the following paths 64
12. Active Technologies SC AT AT 1120 1 Channel 2 GS s 800 MHz Analog BW 14 Bit High Speed Signal Generator Adapter Module for NI FlexRIO E AT 1120 Adapter Module for NI FlexRIO User Manual January 2013 Rev 1 3 Active Technologies S r l Via Bela Bartok 29 B 44124 Ferrara ITALY Tel 39 0532 91456 Fax 39 0532 970134 Internet www activetechnologies it E mail info activetechnologies it 2013 by Active Technologies All rights reserved AT 1120 User Guide and Specifications www activetechnologies it AT 1120 User Guide and Specifications cecccsessscccccecseseaesecececsesesaseeeecscseseasseseesceeseseaeseaees 4 Electromagnetic Compatibility Guidelines 0 ice ccccssececccsesessecececececseseseceeececeeeaaeseeseseseseaaes 5 How to Use Your NI FlexRIO Documentation Set 6 Front Panel and Connector Pinoute 8 AT 1120 Component Level Intellectual Property CUP 10 AT IT20 CLIP DESIG Nos eege Seege ee 10 FPGA I O Int rfa Cenere Age eh 11 Clocking Scheme e Sege deeded a a aE Cosdunncde ENEE dE dE EEN 12 EI 12 LabView Interface enient RER NEEN Ea E EEEE AS EAEE E EEEE EEEn 13 LabView Interface Host Sides iisnisiiietnrisrn ieietu oesie denau inisial sieves a retretas 16 Software PEE dU i E Oa ar e E aaea E E A EE E E ee EA ee 18 Example Code Review for AT 1120 adapter module 18 DACModulecControllHost eye 18 GeneratePulse HOSt Vi eana E deed ee 21 DDS and Trigger Route vi 22 Using You
13. I FlexRIO FPGA Module Installation Guide and Specifications DEEA T NI xxxxR User Guide and Specifications Are You New to in LabVIEW FPGA abVIEW FPG Module odule Y No PROGRAM Your NI FlexRIO System LabVIEW FPGA 4 gt NI FlexRIO Module Help Help bi LabVIEW Examples Figure 2 How to Use Your NI FlexRIO Documentation Set Table 1 NI FlexRIO Documentation Locations and Descriptions Document Location Description INI FlexRIO FPGA Module Installation Guide and Specifications Available in your FPGA module hardware kit and from the Start Menu Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI Adapter Module User Guide and Specifications Available in your adapter module hardware kit and from the Start Menu Contains signal information examples and specifications for your adapter module LabVIEW FPGA Module Help Embedded in LabVIEW Help Contains information about the basic functionality of LabVIEW FPGA Module INI FlexRIO Help Embedded in LabVIEW FPGA Module Help Contains FPGA module adapter module and CLIP configuration information LabVIEW Examples Available in NI Example Finder Contains examples of how to run FPGA VIs and Host VIs on your device Other Useful Information on ni com ni com ipnet Contains La
14. IP xml AT_1120_lOModule_CLIP vhd PLL_125M vhd i2c_ctrl vhd OSerdes8_1 vhd AT_1120_Constraints ucf AT1120_lOModule tbc AT 1120 User Guide and Specifications 10 www activetechnologies it FPGA I O Interface datadac_ch0_in0O datadac_ch0_in2 Input 13 0 Data for DAC Port 1 datadac_ch0_in4 datadac_ch0_in6 The user needs to send data to the Clip Inputs datadac_ch0_in8 datadac_ch0_in10 at IO Module Clock rate 125 MHz the datadac_ch0O_in12 datadac_ch0O_in14 datadac_ch0O_inO datadac_chO_in14 are internally serialized by 8 to obtain a data rate of 1GS s datadac_ch0_in1 datadac_ch0_in3 Input 13 0 Data for DAC Port 2 datadac_ch0_in5 datadac_ch0_in7 The user needs to send data to the Clip Inputs datadac_ch0_in9 datadac_chO_in11 at IO Module Clock rate 125 MHz the datadac_ch0O_in13 datadac_chO_in15 datadac_chO_in1 datadac_chO_in15 are internally serialized by 8 to obtain a data rate of 1GS s datai2c0 datai2c5 Input Data transferred by 12C write readdatal2C Output Data retrieved by 12C read startRDI2C Input Start 12C bus read startWRI2C Input Start 12C bus write reset_in Input Reset the DCMs and FAM lockedfast Output Check if the FPGA DCM has locked or not trig_in Output Check if the SMA Trigger IN signal is high or low trig_out Output Send the Trigger Output to the FAM clkenable Input Enable Disable the FPGA DCM clock outputs clocksel Input Select the clock sour
15. Loop and wire the connectors like in the picture above AT 1120 User Guide and Specifications 33 www activetechnologies it 22 23 24 Add the START CHANNELS control insert it into the Timed Loop and wire it to a new shift register Set true the START CHANNELS control to start the waveforms generation Add two case structures and wire them as in the picture above The case on the left controls the data values 8192 that have to be send to the serializers when the module is stopped The second case checks if the last address of the Memory1 2047 has been reached If true it puts the memory address to the initial value 0 Save the VI Running the Host VI 1 Connect one end of an SMA cable to AO 0 on the front panel of the AT 1120 and the other end to the oscilloscope 50 Q input Tap the unused input AO 0 with a 500 load Open the front panel of CustomFPGAExample1120 Host vi Click the Run button to run the VI Wait for module initialization Click the START CHANNELS button to start the waveform generation The AT 1120 generates one 2048 points sine waveform AT 1120 User Guide and Specifications 34 www activetechnologies it Filter Options If necessary images and sample clock feed through can be largely removed using a low pass filter Active Technologies suggests the following filters depending on the application and the user needs e Mini Circuit RLP 470 e Mini Circuit SBPL 467 Maximally Fl
16. Module in the Project Explorer window and select Properties Select the Active Technologies AT 1120 from the IO Module list The available CLIP items for the AT 1120 are displayed in the General category of the Component Level IP panel If AT 1120 User Guide and Specifications 31 www activetechnologies it the information in the General category is dimmed select the Enable IO Module checkbox 9 Select Active Technologies AT 120 to use the connector based CLIP 10 Click on the Clock Selections category and select DStarA Clock as clockin and 40 MHz Onboard Clock as clockin40m 10 Module Properties ax Category J Clock Selections General jock Selections Geng Component Level IP Clock Details clockin DStarA Clock EN clockin40m 40 MHz Onboard Clock 7 OK Cancel Help Click OK 11 Copy the Memory1 element in the FPGA Target 1212 and paste it in the FPGA Target you have just created E FPGA Target RIOO PXle 7962R D gt IO Module AT 1120 AT_1212 IOModule_CLIP B 40 MHz Onboard Clock JO Module Clock 0 DStarA Clock Memoryl Dependencies d E Build Specifications EE 12 Right click the FPGA Target and select New VI to create a VI for the FPGA 13 Inthe Project Explorer window expand the IO Module tree view 14 Add a Timed Loop as shown in the figure below and right click to open the LabView palette Select the FPGA I O palette and add an I O node AT 1120
17. OK located on Express gt LEDs RIO Device IN Waveform Graph Pito MA l I RIO0 ei 13000 INIT OK 1 1 1 i 1 90 100 110 120 130 6 Select Window Show Block Diagram to open the VI block diagram 7 Adda Stacked Sequence Structure 8 Place the GetFPGA1120Reference vi to get the reference to the 1120 FPGA Target AT_HS_Signal_Generator FPGA Bitfiles AT1120SignalGenerator_FPGATarget vbitx 9 Connect resource name gt RIO Device IN and error in gt error in control 10 Place the InitModule1120 Host vi located on AT_HS_Signal_Generator 1120Module folder AT 1120 User Guide and Specifications 26 www activetechnologies it 11 Wire InitModule1120 H ost vi controls and indicators like the picture below 1120 Module FPGA 1120 VI Eege BE RIO Device gt RIO Device IN CLOCK SELECTION gt Internal INTERNAL CLOCK gt From Oscillator Master gt TRUE DAC A Aligned and FPGA DCM Locked gt case structure The FPGA DCM Locked and DAC A Aligned monitor if the initialization stage has been correctly terminated 12 Add a Frame After in the stacked sequence we will generate the waveform samples 13 Add Sine Pattern vi from Signal Generation Palette 14 Samples 3128 Amplitude gt 4000 Cycle 31 Phase 20 add 8192 to the waveform array and connect the samples array to the Waveform Graph If the VI execution arrives a
18. a rate of 1GS s The Clip provides also access to DDS Arbitrary mode selection Clock Selection Trigger In and Trigger Out resources and START Generation command The Clip has a built in 12C bus interface that we developed to speed up the 12C transfers The user has to load each look up tables with the same waveform and the CLIP reads them updating the Start Stop Address and Increment parameters to convey parallel data stream at the converter at high speeds AT 1120 User Guide and Specifications 13 www activetechnologies it Control Indicator Description START Start the waveform generation SysReset System reset 10 Module lockedfast indicator If the indicator is true the FPGA DCM has locked 10 Module trig_out It sets the Trigger Out value 10 Module trig_in indicator It reads the Trigger In value Trig Selection If Trig Selection is true the global software trigger signal is incoming from Die backplane PXI_TrigO It generates the synchronized RUN for multiple modules If Trig Selection is false the software trigger is incoming from START signal Trig Reset If Trig Reset is true it resets the trigger start condition Write DATA Memory data Write Address Memory address ClockSEL Select the clock source for DAC OSerdes If false it selects the Inst_DCM_CLOCK_DIV4 outputs if true it selects the Inst_PLL DCM clock outputs The user should set it to false if he ne
19. at Group Delay e Mini Circuit SCLF 550 e Mini Circuit SLP 550 e Mini Circuit VLF 530 e Mini Circuit VLFX 500 e Mini Circuit SBPL 933 Maximally Flat Group Delay Calibration Service for AT 1120 OPTIONAL e Perform the calibration procedure Store the calibration parameters into the EEPROM module e Verification of measurements according to specification Adjustment of performance if found outside specification AT 1120 User Guide and Specifications 35 www activetechnologies it Specifications Note Specifications are subject to change without notice Please refer to the Active Technologies website at www activetechnologies it for the most current specification information regarding your product J Caution To avoid permanent damage to the AT 1120 disconnect all signals connected to the AT 1120 before powering down the module and only connect signals after the module has been powered on by the NI FlexRIO FPGA module 3 Note All numeric specifications are typical unless otherwise noted Typical values describe useful product performance that are not covered by warranty Typical values cover the expected performance of units over ambient temperature ranges of 23 5 C with an 95 confidence level based on measurements taken during development or production Configuration EEPROM Map Byte Address Size Bytes Field Name 0x0 2 Vendor ID 0x2 Product ID 0x4 4 Serial Number 0x20 14 Calibr
20. ation Parameters Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use e CEI EN 61326 1 2007 01 Radiated field strength emission from enclosure port class A equipment QPK limit line according to CEI EN 55011 standard corrected for 3m measurement distance AT 1120 User Guide and Specifications 36 www activetechnologies it e CEI EN 61326 1 2007 01 Conducted voltage emission from AC mains input port class A equipment QPK amp AVG limit lines according to CEI EN 55011 standard e CEI EN 61000 4 2 ESD Immunity Test 4 0kV contact direct method 4 0kV HCP VCP indirect method e CEI EN 61000 4 3 Radiated RF electro magnetic field immunity test Level 10V m mod 1kHz AM 80 at 3m of distance frequency range 80 1000MHz Level 3V m mod 1kHz AM 80 at 3m of distance frequency range 1 4 2 0 GHz Level 1V m mod 1kHz AM 80 at 3m of distance frequency range 2 0 2 7 GHz CE Compliance This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC AT 1120 User Guide and Specifications 37 www activetechnologies it Appendix Installing EMI Controls To ensure specified EMC performance PXI EMC filler panels must be properly installed
21. bVIEW FPGA functions and intellectual property to share ni com flexrio Contains product information and data sheets for NI FlexRIO devices AT 1120 User Guide and Specifications 6 www activetechnologies it D S These documents are also available at ni com manuals AT 1120 User Guide and Specifications 7 www activetechnologies it Front Panel and Connector Pinouts Table 2 shows the front panel connectors and signal descriptions for AT 1120 Refer to the Specifications sheet for additional signal information Caution To avoid permanent damage to the AT 1120 disconnect all signals connected to the AT 1120 before powering down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module Signal Description SMA input connector for Trigger IN SMA output connector for Trigger Out Differential analog output channel 0 Differential analog output channel 0 Device Front Panel Connector TRIG IN i SS TRIG OUT L aan J AO 0 AO 0 TRIG IN CLK IN TRIG OUT SMA input connector for external clock When using single ended output terminate the unused output with a 50 Q terminator Table 2 AT 1120 Front Panel Connectors AT 1120 User Guide and Specifications www activetechnologies it UN Caution Connections that exceed any of the maximum ratings of any
22. ce for DAC OSerdes If false it selects the Inst_DCM_CLOCK_DIV4 outputs if true it selects the Inst_PLL DCM clock outputs The user should set it to false if he needs to use the TCXO onboard clock or set it to true if he needs to use the clock coming from the AT 1120 User Guide and Specifications 11 www activetechnologies it Timing Board PXle backplane Clocking Scheme The DAC clock can be sourced from the internal Clock Generator circuit on the adapter module or from the outside using the SMA CLK IN external clock The Clock Generator clock can be sourced from the internal TCXO oscillator 25 MHz or from the PXI Express backplane clock In software use the ClockSelection vi to select from the different clock sources If the user selects Internal and From Oscillator the 25 MHz onboard TCXO will provide the clock to the Clock Generator input The clock generator generates 2GHz the DAC divides it by 4 and it provides 500 MHz clock to FlexRIO FPGA The BUFR and PLL_125M instances divide the 500 MHz clock by 4 and provide the 500 MHz and 125 MHz clocks to the OSerdes and FlexRIO interface If the user selects Internal and From FPGA Clock the FAM takes the 125M from the PXI Express backplane so the user should provide the clock through DSTARA clock by using the NI timing board If the user selects External the DAC clock 2 GHz has to be provided by outside using the SMA CLK IN bypassing the clock generator ci
23. eds to use the TCXO onboard clock or set it to true if he needs to use the clock coming from the Timing Board PXle backplane ClkEnable It enables the FPGA DCM clock output StartAddress1 StartAddress16 Start Address represents the starting pointer address of the look up tables StartAddress is 0 15 depending on the look up table StopAddress1 StopAddress16 Stop Address represents the stopping pointer address of the look up tables StopAddressN NumSamples Increment N 1 Increment AT 1120 User Guide and Specifications In Arbitrary mode the Increment is fixed at 16 in DDS it depends on the DAC sampling rate the output frequency and on the number of samples Please refer to 14 www activetechnologies it ReadTables Host vi Data1 Data16 Retrieved data from memories DDS ARB DDS ARB set to false enters in DDS mode waveform generation set to true enters in Arbitrary mode In Arbitrary mode the Increment is fixed at 16 and Start Stop Address represent the start end point of the look up tables Datal2c0 Datai2c5 Data transferred by DC write transfer ReadDatal2c Data retrieved by 12C read transfer StartRDI2c Start I2c read transfer StartWRI2c Start 12c write transfer 1 In DDS mode the lookup table contains one cycle of the waveform to be generated and typically contains 1024 to 8192 sample points which represent the waveform For our examples we are using a 2048
24. he adapter name 1120 or 1212 the RIO DEVICE and the analog output channel to control AO 0 for 1120 FAM AO 0 AO1 for 1212 FAM e Set the parameters of the most common waveforms selectable by Waveform enum control a samples number must be multiple of 16 duty cycle amplitude from 0 to 8191 b phase and number of cycles related to the waveform output frequency c Waveform type and the standard deviation of the gaussian noise that it is possible to add to the waveform The user can also import a waveform from file or generate a Chirp pattern BPSK signals and QAM modulation adding AWGN IQ Impairments Phase Noise to the output pattern e Press the APPLY button to display the changes on the graph e Press the LOAD WAVEFORM button to upload the data into the FPGA look up tables AT 1120 User Guide and Specifications 19 www activetechnologies it e Dress RUN SELECTED CH button to start the waveform generation Clock Selection select the DAC clock source It can be Internal from Clock Generator circuit or External from SMA connector 2GHz Internal Clock Source select the source clock for the Clock Generator circuit It can be From Oscillator onboard TCXO or From FPGA Clock from PXle Backplane DSTARA Timing board DDS mode waveform generation parameters When the FAM works in DDS mode the user should upload a 2048 samples waveform and set its parameters using DDS frequency Sweep Freq Incr and Sweep Freq Ma
25. hnologies it 3 Select and open AT1120_1212 GE Ivproj LabView project jsa mt mge ES AT1120_1212 _SignalGenerator lvproj Project ge eegene wer Bitte File Edit View Project Operate Tools Window Help lerim Items Files H My Computer E Project AT1120_1212 SignalGenerator lvproj d g proj ei GenerateSinel120 Host vi ei GenerateSinel212 Host vi ei DDSClock and Trigger Route vi e E FPGA Target 1120 Si FPGA Target 1120 o E FPGA Target 1120 c E FPGA Target 1120 Si FPGA Target 1120 E FPGA Target 1212 E FPGA Target 1212 E FPGA Target 1212 o EI FPGA Target 1212 E FPGA Target 1212 E FPGA Target 1212 5 FPGA Target 1212 o S FPGA Target 1212 Dependencies 7951R RIO1120 PXI 7951R 7952R RIO1120 PXI 7952R 7953R R101120 PXI 7953R 7954 RIO1120 PXI 7954R 7961R RIO1120 PXle 7961R 7962R RIO1120 PXle 7962R 7966R RIO1120 PXIe 7966R 7951R RIO1212 PXI 7951R 7952R RIO1212 PXI 7952R 7953R RIO1212 PXI 7953R 7954R RIO1212 PXI 7954R 7961R RIO1212 PXle 7961R 7962R RIO1212 PXIe 7962R 7965R RIO1212 PXle 7965R 7966R RIO1212 PXIe 7966R 4 5 In the Project Explorer window open DACModuleControl Host exe under My Computer On the front panel in the resource pull down menu select an AT 1120 resource that corresponds with the target configured in step 4 6 9 Select 112
26. les and send the same data to the OSerdes The data rate for the DAC has not been respected to simplify the code implementation the same data have been sent to all the serdes so the sine output rate will be divided by 8 Note the following tutorial can be found under the directory AT_HS_SignalGenerator FPGA_Tutorial_1120 vi and AT_HS_SignalGenerator CustomFPGAExample1120 Host vi In the Project Explorer window right click My Computer and select New Targets and Devices In the Add Targets and Devices on My Computer dialog box select the Existing Target or Device option button and expand FPGA Target The target is displayed Select your device and click OK The target and target properties are loaded into the Project Explorer window Right click FPGA Target in the Project Explorer window and select New gt gt FPGA Base Clock Select the IO Module Clock 0 resource Compile for single frequency and set the frequency at 125 MHZ Click OK Right click FPGA Target in the Project Explorer window and select New gt gt FPGA Base Clock Select the DStarA Clock Compile for single frequency and set the frequency at 125 MHZ Warning on the NI PXle 7966R the DSTAR Clock frequency should be set at 124 98MHz Click OK Click on the button to add the Component Level IP File Path browse the AT_1120_ OModule_CLIP xml file in the XML_VHDL folder Click OK to confirm and exit from the FPGA Target Properties panel Right click IO
27. on your NI system PXI EMC filler panels National Instruments part number 778700 01 must be purchased separately For more installation information refer to the NI FlexRIO FPGA Module Installation Guide and Specifications Installing PXI EMC Filler Panels Complete the following instructions to install PXI EMC filler panels National Instruments part number 778700 01 in your PXI chassis 1 Remove the captive screw covers 2 Install the PXI EMC filler panels by securing the captive mounting screws to the chassis as shown in Figure 15 Make sure that the EMC gasket is on the right side of the PXI EMC filler panel 1 Captive Screw Covers 2 Captive Mounting Screws 3 EMC Gasket Figure 15 PXI EMC Filler Panels and Chassis AT 1120 User Guide and Specifications 38 www activetechnologies it iy Note You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 Ib in maximum For additional information about the use of PXI EMC filler panels in your PXI system visit ni com info and enter emcpa AT 1120 User Guide and Specifications 39 www activetechnologies it
28. orm samples that need to be stored into the look up tables The VI stores the samples into the tables on the selected channel ReadTables Host vi The vi calculates the Start Stop Addresses and the Increment parameter and sends them to the target side Those parameters are necessary for look up tables reading see section above Input parameters NumSamples the waveform length in samples DDS ARB DDS false or Arbitrary true generation mode FSampleDAC DAC sampling rate FoutDDS DDS waveform frequency requested by the user The vi calculates the Increment parameter using FSampleDAC and FoutDDS resource name FlexRIO resource name error in Output parameter error out StartGeneration Host vi Start the waveform generation on the selected channels If Sync is true the adapter modules waits for global software trigger PXle DSTARB to start the generation StopGeneration Host vi Stop the waveform generation on the selected channels AT 1120 User Guide and Specifications 17 www activetechnologies it Software Prerequisites 1 Open the installation folder KML_VHDL 2 Copy the XML_VHDL AT 1120 and XML_VHDL AT 1212 folders into the following paths 64 Bit Paths C Program Files x86 National Instruments Shared FlexRIO IO Modules AT 1120 C Program Files x86 National Instruments Shared FlexRIO IO Modules AT 1212 32 Bit Paths C Program Files National Instruments Shared FlexRIO IO Modules
29. r AT 1120 with a LabVIEW FPGA Example Vl cccccccccccecsessssssecccecsesseaeeeeeesceeseeaees 23 Creating a Host VI ON an FPGA Target ccccccccscecececececececececeeececececececeeececeeeeeseceseceeecececeseeeeeeess 26 RUNNING THETA OSt Vliacs case cticcccosttcscevesescetecdcgscacetes vedaced dacncesieds Slestehacadecessuguvelancdees EE 30 Creating a Custom FPGA Target ccccccccscececececececscecececscececececscececececececececscecececececececececeseeecass 31 RUMMINSASTHOSTM Ms engen EE e Ee ee Ee 34 EUEeE OPTIONS eege ENEE gege nedasten weneicaenased cae nese eo cnseduatervedcesenseeteee 35 Calibration Service for AT 1120 IOPTIONALL 35 SPECIFICATIONS 2 assess e ee obser Rech We ious Geet owed A EE 36 AT 1120 User Guide and Specifications 2 www activetechnologies it Configuration EEPROM Mapes eer Sed eedeg dE ae A eria i Ae AE 36 Electromagnetic Compatibility on a eai er e E essentensdevect Sovedxeubedeceebbaeeceas 36 EE om plage e a a a ouch dee Ee Ee 37 Appendix Installing EMI Control 38 Installing PXI EMC Filler Banels 38 AT 1120 User Guide and Specifications 3 www activetechnologies it AT 1120 User Guide and Specifications The AT 1120 is a one channel 2 GS s 14 bit 800 MHz Analog Bandwidth High Speed Signal Generator adapter module designed to work in conjunction with your NI FlexRIO FPGA module This document contains signal information and specifications for the AT 1120R which is composed of
30. rcuit Component Level IP Clocks Name Connection Clockin DSTAR Clock 125 MHz see above for clocking scheme usage Warning on the NI PXle 7966R the DSTAR Clock frequency should be set at 124 98MHz Clockin40m 40 MHz FlexRIO Clock used on the LabView interface of the clip ReadWriteTablesTest vi IO Module Clock 125 MHz clock from FAM Cables Use any shielded GO Q coaxial cable with an SMA plug end to connect to the AO 0 AO O TRIG IN TRIG OUT and CLK IN connectors on the AT 1120 front panel For more information about connecting I O signals on your device refer to the Specifications sheet AT 1120 User Guide and Specifications 12 www activetechnologies it LabView Interface Target Side ReadWriteTablesTest vi The DAC contains two parallel LVDS input ports consisting of 14 differential LVDS signals DB 13 0 Each data port runs internally at half the speed of the DAC Clock 2 GHz so the user needs to guarantee them the correct data rate PORT 1 DATA The LabView interface of the CLIP reads data from the look up tables Memory1 Memory7 at 1O Module Clock rate 125 MHz the datadac_ch0O_inO datadac_chO_in7 are internally serialized by 8 to obtain a data rate of 1GS s PORT 2 DATA The LabView interface of the CLIP reads data from the look up tables Memory8 Memory16 at 1O Module Clock rate 125 MHz the datadac_chO_in8 datadac_chO_in15 are internally serialized by 8 to obtain a dat
31. t the second frame it means that the adapter module has been AT 1120 User Guide and Specifications 27 www activetechnologies it correctly initialized so connect True to the INIT OK led indicator Generate the samples Waveform Graph 15 Add a Frame After in the stacked sequence we will load the generated samples into the channels module 16 Add a For Loop structure and wire 2 to the Loop count 17 Place the WriteTables Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the RIO Device and Wavel Array like in the picture below Store the samples into the module 18 Add a Frame After in the stacked sequence we will start the waveform generation 19 Add a Flat Sequence Structure AT 1120 User Guide and Specifications 28 www activetechnologies it 20 In the first frame add a For Loop structure and wire 2 to the Loop count 21 Place the ReadTables Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the NumSamples D128 DDS ARB gt True In the second frame place the StartGeneration Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the SYNC gt False 30 4 gt EE EE EE BEE be EE EE 22 Add a Frame After in the stacked sequence 23 Add a While Loop structure and a Case
32. x controls It is also possible to generate a frequency sweep setting the increment and the stop frequency and then pressing the SWEEP ON OFF button AT 1120 User Guide and Specifications 20 www activetechnologies it GeneratePulse Host vi Software requirements LabView 2012 This VI is an user friendly example that generates pulse signals On AT 1212 adapter modules it starts stops both channels r J GeneratePulse Host vi File Edit View Project Operate Tools Window Help EECH Waveform Graph RIO Device IN ZS EI ADAPTER NAME 1212 2 CHs f CLOCK SELECTION Internal Z INTERNAL CLOCK From Oscillator e Amplitude NumSamples a22 J SKIP INIT Module Init OK q gt 9 e AT1120_1212_SignalGenerator lvproj My Computer lt e Select the resource name and the adapter name 1120 or 1212 e Clock Selection select the DAC clock source It can be Internal from Clock Generator circuit or External from SMA connector 2GHz Internal Clock Source select the source clock for the Clock Generator circuit It can be From Oscillator onboard TCXO or From FPGA Clock from PXle Backplane DSTARA Timing board e Set the NumSamples the samples number of the pulse waveform It must be multiple of 16 Module Init OK indicator that states if the module is properly initialized or not SKIP INIT if true the FAM skips the initialization phase AT 112
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