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User Guide DN8000K10PCIEe

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1. DIMM_VREF vet zT DIMMB_DQ4 DIMMB_DQo pa 6 DIMMB_DO5 Dar al VSS Fag DIMMB_DMo DIMMB_DQSnO DMO 5 T VSS 74 DIMMB_DQ6 Das is DilmttB Der DIMMB_DQ2 Da7 Fag DIMM_VTT DOS VSS 155 DIMMB_DQ12 Da12 75 DIMMB_DO13 RN25 DIMMB_DQ8 pars 57 DIMMB_Sno 2 r Da9 an 26 DIMMB_DM1 PiMMg opto 2 fa 283 J VSS ni 5 DIMMB_Dasnt YSS 30 DIMMB_CKO DIMMB_CKo rer s Cko 132 DIMMB_CKno 56R DIMMB_DQ10 VSS 36 __ _DIMMB_DQ14 DIMME DOTT D914 ss Omme DOTS 40 DIMM_VTT vss m2 7 DIMMB_DQ16 4 vss vss 441 pvp Da20 DIMMB_A15 DIMME DOT 45 pare oe 46 DIMME DO2t DIMMB_DQSn2 f a vs vss Et DIMMB_Das2 51 nasa ao E82 X DIMMB DM2 54 56R DIMMB Dots TR tas oe 56 _DIMMB_Da22 DIMM De Dass 58 a DIMMB_DQ24 VSS 52 _DIMMB_Da28 RN37 I Dass 6a Dimma Doze 66 7 DIMMB_DM3 VSS 55 DIMMB_DASn3 DIMMB_CKE1 pasa 70 DIMMB_DOS3 DIMME CREO 4 A DIMMB_DQ26 Bu 74 DIMMB_DQ30 SOR DNI Daz coe 76 DIMMB_DO31 78 DIMMB_CKEO VSS a0 DIMMB_CKE1 DIMMB_CKEO lt cKE 8 TTE O gt DIMMB_CKE1 VDD 87 DIMME ATS R348 DIMMB_BA2 NC ae omme Aa R347 DIMM_VTT 1K 18 NG ag 18 1K 9 DIMME A12 VDD Tao DIMME AT RN23 E A11 Has DIMMB A7 DIMMB_A6 DIMMB_AS AT 53 DIMME RA aa
2. Samtec cable Er Ve 25 Mhz Xtal 1CS843020 an RCLK1 FPGA C 2 LVPECL RCLK2 Rockall low jitter ESS Oscillators RCLK3 2 s 250Mhz or other speeds SYSCLK 48Mhz 3 Samtec FBACLK _ cable FBBCLK SCLK1 _ _ DDR SCLK2 FPGAC sODimm ge co 1088442 xM N ACLK gt DEK U7 N gt BCLK Bii ACLK y une 14 3 1CS8442 a xM N BCLK gt panes y u9 BCLK Daughtercard ALK Header 16 0 HB76 Mhz 1CS8442 Xtal I xM N DCLK gt un pd SYSCLK 48Mhz gt pope FBACLK NM FBBCLK gt DDR ScLKi 4 FPOAB SODimm SCLK gt 48 Mhz Osc EEE DCLK ch g BCLK gt Buffer gt ACLK SYSCLK 48Mhz gt gt Spartan2 __________ ___D DRFBCLK SYSCLK 48Mhz PE a SYSCLK 48Mhz 4 BCLK _Daughtercard MCU ACLK Header se k MCU N CLK HA76 PCIUCLK 75Mhz oanthz 2 75 Mhz PCIUCLK 75Mhz Osc PCIUCLK 75Mhz gt Quicklogic SYSCLK 48Mhz 5064 FBACLK PCICLK 66 or 33Mhz gt FBBCIK FPGA A SCLK1 4 SCLK2 4 TED UCLK V4 YY DCLK 4 PCI Connector BCLK IH SMA Connector ACLK _ FBACLK
3. DA Buttons JTAG Header Figure 20 Spartan II IO Connections 4 2 1 Spartan Configuration The Spartan 2 FPGA is configured from a Xilinx serial prom The Spartan s configuration mode is hard wired into Master Serial mode After power up the Spartan automatically clocks an external PROM U41 which programs the FPGA over the serial configuration data pin DIN A green LED DS24 lights when the DONE pin is high This signal is driven by the Spartan 2 FPGA when it is configured and running Both the Spartan and the serial prom are connected in a JTAG chain attached to J14 This header is used when performing firmware updates to update the PROM DN8000K10PCIE User Guide www dinigroup com 44 Spartan Configuration Prom u4 CFPGA_CCLK CFPGA_Do 43 c k oo 3g An Dre FPGA DOR 2 RESETn be Ks CEn D3 150 i JTAG_PROM_TCK 7 D4 35 Spartan Configuration Re PRO o TOK Ds HO Interface TAG PROM IMS 5 TD D6 j9 0 STAG CFPGA Tor 31 TNS le ape 10 __CFPGA PROGn vaiK 30 crn ere J wiz PCLUCLKM Da NC CEOn pS 4 Geko Yri SYS CLK O34 NC 2 EN 5 GCK1 A11 MGU_CLKS Bese voco Ts CCLK 1 GCK2 AH SYS CRS DJ Nc voco 1365 aog HI O37 Nc VECO 15 DONE 3 t ne veco o H ne 43 3V og pour 2 mo ABZ Master o H ne vecint 38 CEPGA DO D20 Us z2 es ee Mi ya Serial EZ Nc VCGINT 97 M2 O77 Nc VCCINT CFPGA_INITh v19 Base FPGA
4. 20 20 TANT TANT 1 2V_VTRIM R177 1 8M ann YNCO5S20 0 R176 R2 10K 43k The DN8000K10PCIE is shipped with a fun mounted above the power supplies to help keep them cool If you need to remove this fan the DN8000K10PCIE will function properly without it but be careful not to touch the power supplies with your fingers because they will burn Each power supply is protected with a 15A fuse on the inputs If you need to operate the DN8000K10PCIE with more than 15A of current for a power supply you can change this fuse but you need to find a heatsink solution for keeping the Virtex 4 FPGAs cool The heatsink and fan provided are appropriate for a power consumption of about 10 15W per FPGA Each of the primary power rails 5 0 3 3 2 5 1 8 1 2 is monitored for undervoltage If the voltage monitor circuit detects a low voltage it will hold the board in reset until the supply is back within 5 of its setpoint See section X Reset Circuit for information on reset 1 2V 0 1 8V 25V 5 0V 43 3V 5 0V 5 0V 43 3V Reset Circuit cape oi R359 124R R367 R358 B45R S OR R364 R371 1K 88 7R F370 t 28 0K SYS_RSTn ol ol l ln lt S R360 28 0K R368 4 Ei 7 3 110R ola fof SR R361 CRT ae Esel FR m Hz
5. gt Figure 31 DN8000K10 clocking From the above diagram the global clocks are listed here RCLK1 An ICS frequency synthesizer either an ICS8442 ICS84321 100 250Mhz or ICS84020 667Mhz This clock is configured from the MCU using the USB controller or the SmartMedia card This clock is supplied to MGT_CLK pins on FPGA C and can be used as an MGT reference clock for any MGT tile on the left column The Synthesizer can also be configured to use an external clock input from the QSE DP Samtec RocketIO connector J3 DN8000K10PCIE User Guide www dinigroup com 62 RCLK2 3 An Epson 250Mhz oscillator This clock can be used to supply an MGT reference clock to FPGA C in either the right of left columns ACLK BCLK DCLK These global clocks are supplied by ICS8442 frequency synthesizers They are configured from the MCU to output a user specified frequency from 31 to 700Mhz They are each distribuited to FPGAs A B and C SCLK1 2 These single ended clocks run at low speed and are controllable from the USB interface allowing for software that controls single stepping designs Both clocks are delivered to FPGAs A B and C The clock is sourced directly from the Spartan 2 configuration FPGA Sysclk this 48Mhz single ended clock is driven from the configuration FPGA at a fixed frequency It is delivered to FPGAs A B C and the configuration FPGA This clock is used by the Dini Group reference design to cloc
6. io a et r z m ae mm H XFP Connector nmmn 1777 alala IMIM BEEE FPGA C N 0121 10 B R s i mem N ns DIMM C 1 8V DOR SODIMM Eo See Ma eats TH sks 12 5 1 SFP SFP modules support 1 4 5Gbs serial trasmission rate Two red LEDs show the status of the channel The LOS LED indicates that the far end transmitter is not operating the cables are not secured or matched to the transmitter wavelength The INT LED indicates The FAULT LED indicates a transmission laser failure or an unsecured module DN8000K10PCIE User Guide www dinigroup com 86 VCCR_SFP1 D VCCT_SFP1 u10 17 SFP1 Connector VCCR_SFP1 Virtex 4 FX 1152 OPT C332 0 01uF R141 Tag AVCOAUXRXA 105 BXPPADA 105 LAGE cr0s0 Pr me wok AVCCAUXTX_105 RXNPADA 105 N31 0 01uF OPT 20 1 AVGGAUXRXB_105 c333 CSFP1_TxDn 19 VEET VEET E SFP1_TxFAULT RENT 0 01uF CSFP1_TxDp ig_ TD LT TE SEPT TxDIS x 17 TD TxDISABLE gt T MOD DEFZ SFP1_TxDIS rages AB Sr heg eee eee Meese aan Sees g SFPT_TxD 3 VCCR_SFPT H SFP1_MOD DEFO Mob TXNPADA 105 AXS4 xe LOE SEED 16 voor
7. Rocket 2 MGTCLK Rocket M M34 N34 s MUX H 10405 k 1 Optical Module 1 y Rocket 1 MUX H lo 106 f 108843020 gt MUX H pee tp 4 optical Module 2 MGTCLK sa PL ex ono ff sm T gt U sma 1 1 SMA PT gt H sma Rocket 1 epson MGTCLK MUX H 10112 k SMA a APA AP3 gi 1 SMA 250Mhz 4 r mux Rocket LMA Foma EENEN 10 113 rT 2 gt Rocket gt SAMTEC cable MUX H 10114 2 The RocketIOs on the Virtex 4 FPGA is divided into two columns X0 and X1 The clock network of each column is separate and clocks may not be shared between the two columns Each column has two clock distribution trees and two clock inputs Each tree can be driven by a clock input by a clock from a global clock input not recommended or by a recovered clock Finally each tile has a multiplexer than can select from one of the two clock trees to clock that entire tile The diagram above shows the two RocketIO columns and the connectivity of each Once a clock is routed to an MGT tile that clock can be multiplied and divided by the MGT tile Most users will want to use the frequency synthesizer for generating RocketIO reference clocks The ICS843020 01 synthesizer is very low jitter and should suitable for operation up to 6Gbs RocketIO operation The frequency of the synthesizer can be adjusted through the main txt file on the SmartMedia card or through the USB GUI program DN8000K10PCIE User Guide w
8. ie PR DEN HARD RESET The above circuit shows how two LTC2900 voltage monitors are daisy chained together to monitor 5 different voltages Each FPGA is also connected to a temperature monitor The Virtex 4 FPGA can easily overheat if a heatsink and fan are not used The recommended operating temperature for the Virtex 4 is 85 degrees C The absolute maximum temperature for operation is 125 degrees C If at any time the junction temperature of the Virtex 4 exceeds 85 degrees the Microcontroller will reset the FPGAs causing them to lose their configuration data An overheating FPGA could be the result of a misconfiguration a clock that is set incorrectly or an inadequate heatsink unit The heatsink and fan assembly that comes with the DN8000K10PCIE is appropriate for dissipating the amount of heat energy available through a PCI slot without the auxiliary power connector 25W total for the card If you are operating the DN8000K10PCIE at very high speeds in stand alone mode and you are causing heat overload resets you may need to install a V1 3 3V v2 2 5V v3 1 8V v4 ADJ 0 5 V larger heatsink or increase the system airflow U11 1 Virtex 4 LX 1513 CCLK HSWAPEN PROGRAM_B INIT CS B DONE PWRDWN_B RDWR_B DOUT_BUSY Mo M1 M2 D_IN VBATT TMS TCK VCCO_0 TDI VCCO_0 TDO VCCO_0 R165 1K U4 TEMPA_STBY 151 SmBY vcc gt FPGA DXP A IIC
9. TANT Figure 26 TCK buffer The INIT signal is not used U11 1 FPGA_CCLK_A PKA w2o Fook Mode selection Slave FPGA_PROGn_A _ A wee PROGRAM_B Hswapen 234 Select FPGA_INITN A ern yas INIT o electmap FPGA_CSn_A y a CS_B 5 CHS DONE T Fron povan a D a FPGA foie A E oae 5 Punom Peto p gt FPGA_BUSY_A DOUT_BUSY Y23 MSELAO 1K GND x Mo 54 MSELAT RaR VV 25v Lise MSELAZ KV V 25V oe p N Mo 22 iK wm R214 JTAG_FPGA_TMS IR ITACFPGATCRA ARTS TMS vearr Wer JTAG_FPGA_LTCK amp I 2 TCK JTAG_FPGA_TDI G FPGA TDI _ A817 ro veco o MAH TDO veco_0 yon ao vcco_o Pu R223 Ze OR DNI aS JTAG_FPGA_TDIB lt TAG FPGA TDIB zT Figure 27 FPGA A Configuration Bank DN8000K1OPCIE User Guide www dinigroup com 48 If you ordered your DN8000K10PCIE with one or more FPGAs not installed Option FPGA A NONE FPGA B NONE or FPGA C NONE then a bypass resistor is installed connecting the TDI pin to the TDO pin of the uninstalled FPGA This is so the JTAG chain will remain intact when FPGAs are missing 4 3 2 SmartMedia When the DN8000K10PCIE powers on the microcontroller reads the contents of any SmartMedia card that is in the SmartMedia slot The microcontroller by default opens a file on the root directoy named Main txt if it exists This file contains instructions for the configuration circuitry to configure the Virtex 4 FPGAs To create a SmartMedia card to control the DN8000K10PCIE configuration in
10. The DN8000K10PCIE only has one serial port Port 1 Changing ports 2 4 will have no effect 3 6 Check LED status lights The DN8000K10PCIE has many status LEDs to help the user confirm the status of the configuration process DN8000K10PCIE User Guide www dinigroup com 21 Configuration Activity Y 10060090608 iii th hes mm u A e 886800000 Al N LITT Configuration Control status FPGA B status H FPoa a m DNBOOOKIOPCIFL l COPYRIGHT 2005 on THE DINI GROUP LA JOLLA INC oo m WADE m usa Larry 2 rs IAW 4 mun ES eS A Spartan FPGA status Figure 9 Configuration Status LEDs 1 Check the power voltage indication LEDs to confirm that all voltage rails of the DN8000K10PCIE are present From the top the LEDs indicate the presence of 5V 3 3V 2 5V and ATX POWER OR Green lit LED s on the voltage present LEDs indicate the rails are greater than 1 7V A green lit ATX power OR indicates that the voltage monitors inside the ATX power supply are within acceptable operating ranges 5V is 4 5 5 5V 3 3V is 3 0 3 6V If this LED is not lit green the DN8000K10PCIE might not function properly 2 Check the Configuration status LEDs These LEDs are visible from outside the case when the DN8000K10PCIE is installed in an ATX case Under error conditions all four red LEDs will blink 3
11. Web based HDL generation methodology e SRAM based in system configuration O O O O O O Fast Select MAP configuration Triple Data Encryption Standard DES security option bitstream encryption IEEE1532 support Partial reconfiguration Unlimited reprogrammability Readback capability DN8000K10PCIE User Guide www dinigroup com 96 INTRODUCTION TO VIRTEX 4 AND ISE e Supported by Xilinx Foundation and Alliance series development systems o Integrated VHDL and Verilog design flows o ChipScope Pro Integrated Logic Analyzer e 0 13 um nine layer copper process with 90 nm high speed transistors e 1 5V VCCINT core power supply dedicated 25V VCCAUX auxiliary and VCCO power supplies e JEEE 1149 1 compatible boundary scan logic support e Flip Chip and Wire Bond Ball Grid Array BGA packages in standard 1 00 mm pitch e Each device 100 factory tested 17 Foundation ISE 7 11 ISE Foundation is the industry s most complete programmable logic design environment ISE Foundation includes the industry s most advanced timing driven implementation tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes ProActive Timing Closure technologies and seamless integration with the industry s most advanced verification products ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design so
12. F R149 DNI ApS VTTXB 109 TXNPADB 109 CAGE CAGE N PAL ans VTRXA_109 CAGE MG CAGE DANS VrTxA toa Ans CAGE U CAGE PRA Fee RXPPADB_109 LARIE CAGE kd CAGE 508 tet RXNPADB 109 CAGE 5 CAGE CAGE CAGE CAGE u CAGE IRSFP2_FAULT RSFP2_LOs 28838 Gace GG NM AVCCAUXMGT_108 ee CAGE CAGE BED amp 5 5 4 5 1367073 OPT 10 ps4 Dse 85855 mA Re Mebuen opry Py RED LED oPT ER harpa rautt 28 8 SFP2_TsFAULTI amp 2 2 RED a p2 Los 10 al mA SFP2 LOS Figure 39 SFP modules 12 5 2 XFP XFP modules are the fastest optical modules that do not require a The XFP specification allows for an optional 5 2V power supply to be provided by the host board for ECL transmitter modules The DN8000K10PCIE provides no 5 2V power so a mounting point U1 is provided for the use of a bench supply if ECL signaling is required VEES_XFP j L5 U1 VEES XFP 5 nn LVEES_XFP 2 C453 4 7UH 1 22uF C496 10V DNI TANT OF 20 Mounting Holes for 5 2V _ support XFP DN8000K10PCIE User Guide www dinigroup com 87 Some XFP modules may requite a reference clock to retime the transmitted signal The REFCLK signal in the XFP specification The REFCLK signal is connected to a RocketlO output on FPGA C The REFCLK signal should be 1 64 of the data rate driven onto the XFP s TX pins To drive this signal See Xilinx Application note XAPP656 To meet the input requirements of the XFP modu
13. i2 DINME DOST 4 83 Vss vss 184 4 DIMMB_DM7 185 DM7 Das se DIMMB_DQSn7 56R 187 188 DIMMB_DQS7 DIMMB_DQ58 189 VSS DQS7 Tao DIMM_VTT DIMMB_D059 191 2258 VSS 92 DIMMB_Das2 9 193 DOS9 Dae2 Isa DIMME DSF R349 1C_SDA IC_SDA 195 VSS DQ63 H96 noi DIMMB_BAO I SDR Set 197 SDA VSS 98 DDRB_SAO DIMMB_W S 33 199 SCL SAO 7200 DDRE_SAT 333 VDDSPD SA1 R350 CONN_DDR2_SODIMM200 10K 10 Headers There are two daughtercard headers on the DN8000K10PCIE one attached to FPGA A Header A and one attached to FPGA B Header B Header A contains 135 user IOs designed to operate as 134 differential pairs Header B has 154 user IOs that can be used as 77 differential pairs The signals RESET_FPGAs is driven by the Spartan Configuration FPGA This signal is the same as the RESET FPGAs driven to FPGAs A B and C PDETECTA and PDETECTB are signle ended signal with an external pull up resistor The daughtercard can ground these signals to indicate the daughtercard s presence DN8000K10PCIE User Guide www dinigroup com 76 The HAp nCC and HBp nCC signals are connected to global clock input pins on the FPGAs These can be used as differential clock inputs from the daughtercard headers to the FPGAs They can also be used as outputs The ACLK and BCLK signals are copies of the DN8000K10PCIE global differential clocks ACLK and BCLK The signals are synchronized at the daughtercard connector with the ACLK and BCLK signals at the pins
14. in bus specifications such as bus 7 0 they are required ngdbuild opron_name design_name Braces A list of items from which you must choose one ot more lowpwr on off Vertical bar Vertical ellipsis Separates items in a list of choices Repetitive material that has been omitted lowpwr on off IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block_name loct loc2 locn Prefix Ox or suffix h Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h Letter H ort _n DN8000K10PCIE User Guide Signal is active low INT is active low fpga_inta_n is active low Www dinigroup com 3 2 Content 3 2 1 File names Paths to documents included on the User CD are prefixed with D This refers to your CD drive s root directory 3 2 2 Physical orientation and Origin By convention the board is oriented as show on page 3 with the top of the board being the edge near Headers A and B and the edge with the optical module connectors The tight edge is near the SMA connectors the left side is the side with the PCI bezel topside refers to the side of the PWB with FPGAs soldered to it backside is the side with the daughtercard connectors The reference origin of the board is the center of the lower PC
15. 4 x AR DS46 R125 LEDC13 RLEDC13 120 I AR DS47 R126 LEDC14 RLEDC14 120 J vara DS48 R127 LEDC15 4 RLEDC15 120 vara Figure 33 FPGA C LEDs FPGA A is connected to 8 green LEDs FPGA C is connected to 16 LEDs These LEDs can be used for the user design The brightness of these LEDs can be controlled by changing the output standard on the LED signals from 2 4 12 16 or 24mA 12 RocketlO 12 1 RocketlIO Clock Resources Since it is impossible to determine during manufacturing the clocking requirements of every possible end application the DN8000K10PCIE comes with a flexible clock network capable of a wide range of serial frequencies while maintaining the tight jitter requirements of the 10 Gigabit serial trancievers The RocketlO clock tree is driven by a synthesizer and two oscillators and dedicated multiplexers inside the Virtex 4 FPGA allow the user to switch between these clock sources DN8000K10PCIE User Guide www dinigroup com 80 Rocket Figure 34 Internal MGT clocking y es MUX H 10101 2 gt Rocket p MUX H 10102 SAMTEC cable Epson MGTCLK Oscillator apoo Ap28 7 Pocket Ra 250Mhz R mux
16. 68 70 72 74 76 78 80 82 84 86 88 92 96 100 104 108 12 16 120 124 128 132 136 140 14 148 152 156 160 164 168 172 176 184 192 200 208 216 24 232 240 248 256 264 272 280 288 296 304 312 320 328 336 336 34 352 368 384 400 416 432 48 464 480 496 512 528 54 560 576 59 608 624 640 656 672 688 3 Change Text Editor This options allows the user to select a text editor to use the default editor is notepad 4 FPGA Stuffing Information This option will display the type of FPGAs that are stuffed on the DN8000K10PCIE 5 MCU Firmware Version This option will display the MCU Firmware version in the log window 6 BOARD SPARTAN Version This option will display the Board Version along with the Spartan Config Fpga Version 2 Updating the Firmware Dini Group may release firmware bug fixes or added features to the DN8000K10PCIE If a firmware update is released you will need to There are two firmware files that Dini Group may release the first is a Micro controller MCU software update that is stored in a flash memory This update can be accomplished easily from within the USBController application The second update that may be required is a Spartan FGPA core update The configuration data for the Spartan FPGA is contained in a Xilinx configuration PROM This update can be accomplished with the Xilinx JTAG programming program iMpact 2 1 Updating the MCU flash firmware To protect against accidental erasure the MCU fi
17. AG S6 18 DIMMB AZ UINMES von ces DIMMB_AO DIMMB A3 As 100 DIMMB_AZ DIMMB A1 102 DiE AT 18 vos 104 FTE 56R DIMMB_A10 106 DIMME_EAT DIMME WEN Jog BAO Rast 498 DIMME RASN DIMMB_RASn DIMMB_WEn HI 109 we so 419 DIMMB_Sn DIMMB_Sno DIMMB_CASn 113 YOD VDD Prig x DMMB CASS J DIMME SAT Te sas aoro Hiet oma arg gt DImMB_oDro FTE AZ Sio uns Eig 1 8 pimmB opr ME 0T opti no 488 DIMMB_DQ32 Soc VSS VSS 754 DIMMB_DQ36 DIMM_VTT DIMMB_DOSS 125 pas 126 DIMMB_DO3 21er 128 DIMMB_DQSn4 129 VSS VSS 730 DIMMB_DM4 DIMMB_A5 1 _DIMMB_DOSt 131 pes m 132 DMMB A 4 4132 vss pase 134 DIMUS DOSS FE DIMMB_DQ34 135 V gt 136 DIMMB_DQ39 DMMB ATO 4 DIMMB DQ35 137 Bee 082 Tag 4139 140 DIMMB_DQ44 DIMMB_DQ40 141 VSS DQ44 722 DIMME DOF DQ40 DQ45 56R 143 Daat 144 115 a6 DIMMB_Dasns DIMM_VTT DIMMB DM5 rrak Bae na DIMMB_DQS5 149 150 RN24 DIMMB_DQ42 751 VSS VSS 55 DIMMB_DQ46 DQ42 DQ46 DIMMB_BA1 DIMME DOIS 153 D Dads iss DINIMB_DOA7 DIMMB_RASn 1155 0943 047 est DIMMB_DQ48 157 VSS VSS 58 DIMMB_DQ52 DIMMB_A13 DIMMB_DQ49 159 Der De 160 DIMME DASS L781 yss yss 62 J 163 Nc TesT cki HS4 en DIMMB_CK1 zu 165 vss xt HSS a DIMMB_CKnt DIMMB_DQSn amp 167 SS CK 168 a DIMM_VTT DINNE DOSE 169 BS 6 US 7a DimMB_Dms 177 29986 6 172 DIMMB_DQ50 1738 VSS VSS 1474 DIMMB_DO54 DIMMB_BA2 DIMIMB_DOST 175 Da ee 176 DIMME DOSS 1771 ves vss 8 4 AS DIMMB_DQ56 T Vee paso 180 DIMMB_DQ60 DIMMB_A8 DIMMB 0057 1 Dass bas
18. DONE kE k CONFIGURING FPGA De a a a k Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA_A BIT FILE SIZE 003A943B bytes PART 4v1x100ff151317 09 38 DATA 2005 07 25 TIME 17 09 38 Sanity check passed The global clocks ACLK BCLK DCLK are frequency configurable The M binary sequence represents the multiplication applied to the installed crystal The N represents the division applied See Appendix X Clocks and Schematics U6 U14 U20 U31 and the ICS8442AY datasheet The MCU is setting the clocks to their default values ACLK 200Mhz BCLK 108 8Mhz DCLK 128Mhz R1CLK not available on DN8000K10PCIE R2CLK DEFAULT The MCU detects which FPGAs ate present The MCU detects if a SmartMedia card is present The MCU tries to access the SmartMedia card If the MCU is not successful in reading the files on the SmartMedia card be sure you have not formatted the card in Windows Windows uses a non standard format for media cards and will make the card unreadable You can download a format utility from dinigroup com to repair your incorrectly formatted SM card The MCU reads the contents of the file MAIN TXT and executes each instruction line Here the MCU is setting the clocks according to instructions in MAIN TXT The MCU is configuring FPGA A according to instructions in MAIN TXT The sanity check option reads the design bit file headers and verifies that th
19. FPGA configuration The program memory space of the MCU is directly mapped to the external Flash memory When the Cypress MCU is reset which happens after the Spartan 2 is configured it loads its boot code into its 8kB of internal memory from a serial EEProm U13 The code in the EPROM instructs the MCU to execute code located on the FLASH memory U19 The code in the EEPROM and FLASH is located on the user CD 3 3 33 EEPRO R251 S R250 U13 22K 2 2K 3 3V___R240 1K 1 8 R239 IK 2 A0 vcc j6 IIC_SCL_MCU FJA scl g 7 R238 1K IC_SDA_MCU 4a 22 SDA S MCU EPROM WF GND WP 24LC64 TSSOPS R252 1K Address 00000001 0x01 RAM Space 0x0000 to Ox1FFF DN8000K10PCIE User Guide www dinigroup com 57 Communication over the MCU memory bus to the Spartan 2 is synchronized to the 24Mhz MCU_CLK X3 For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual MCU 40Mhz agninz PLL 24Mhz q i IFCLK Spartan 2 Memory Mapped 10 48Mhz Main Bus SYS_CLK FPGA A FPGAB FPGA C The Configuration FPGA is connected to the MCU_DATAJ7 0 signals the MCU_ADDR 15 0 signals and the MEM_OE signal allowing it to decode addre
20. L 27 28 TICTORS 29 30 31 32 MICTOR1 ETORT 33 34 VICTOR 35 36 37 38 2 GND LOC GND GND CONN_MICTOR38 Figure 32 Mictor Header MICTOR13 a OMICTORTS __ 6 PPC_TRC_TCK LE ee aaa 12 x PPC_TRC_VSENSE R101 AA 1K_ 3 3V H4 x L18 x L20 x L22_ x PPC_TRC_TS10 I ji Ji n PPC_TRC_TS1E PPC_TRC_TS4 DN8000K10PCIE User Guide www dinigroup com 79 11 LEDs 3 3V Green 10mA DS33 R112 LEDCO RLEDCO 1A J 73 DS34 R113 LEDC1 RLEDC1 120R 4 Ke DS35 R114 U10 2 LEDC2 RLEDC2 120 G18 LEDCO Eri AR 1 IO_LIP_D31_LC_1 FFie TEDCT IO_LIN_D30LC_1 Hpg TEDCE DS36 R115 10 L2P_D29 LC 4 120R IO LEN D28 L01 His ie LEDC3 al RLEDC3 4 IO_L3P_D27_LC_1 Ferg TEDCS IO_L3N_D26_LC_1 G15 TEDCE DS37 R116 IO_L4P_D25_LC_1 120R 1O Lan D24 VREF Loi He TEBE Ea HLEDCA 4 1O _L5P_D23_LC_1 FE17 TEDCS IO_LSN_D22LC_1 FES LEDCTO DS38 R117 1O_L6P_D21_LC_1 120 Io Len Deo Le H4 TEDCTT LEDCS RLEDCS OR al Gia E16 TEDTTZ 72 OR Veco IO_L7P_D19_LC 1 Fig TEDCTI Oo veco 1O_L7N_D18_LC1 Fig TEDCTZ Ds39 R118 1O_L8P_D17_CC_LC_1 EDC 20R OIA DAI a ols TEDCT LEDC6 e RLEDCS AK i E E Ke DS40 R119 Virtex 4 FX 1152 LEDC7 RLEDC7 120R i ie DS41 R120 LEDC8 RLEDC8 TOR i 72 DS42 R121 LEDC9 RLEDC9 120 DS43 R122 LEDC10 RLEDC10 120R vara DS44 R123 LEDC11 RLEDC11 120R 1 Ke DS45 R124 LEDC12 4 RLEDC12 120
21. OL19P 5 10_L27P_5 Han AENT ABn o Gr OL 20F 6 lo t2er 6 JS ABn21 ABP J29 O L19N_5 10_L27N_5 Gaga ABP25 kat Di5 O_L20N_VREF_6 10_L28N_VREF 6 Fis ABr gt ABNT Kog O L20P 5 10_L28P_5 035 ABNF aao TE OIF 6 10_L29P_6 HE HE SEPT B30 O L20N_VREF_5 1O_L28N_VREF 5 Fass ABP20 ABp T Gio IO_L2IN 6 10_129N_6 Fig ABp23 ABN 7 Ba1 O L21P_5 IO_L2SP_5 A36 ABN20 ABn t H10 O L22P_6 10_L30P_6 Tag ABn23 R17 ABP19_C33 O L21N_5 10_L29N_5 Jai ABP21 ao OOR O UNAS AS O L22N_6 10_L30N_6 K ABp24 49 9R ABN19_ C34 0_L22P_5 10_L30P_5 Kat ABN2T VRP_A6 Ag O L23P_VRN_6 1O 1316 117 ABn24 2 5V VAN B5 _F31 O122N 5 10 Leon 5 Bas ABPTO Eg 10_L23N_VRP_6 IOL31N 6 Eig ABp25 VRP B5 GST 0_L23P_VRN_5 IO_LS1P_5 E37 AENT R7 49 9R fg 0_L2aP_cc ic 6 IO_L32P_6 kg ABn2E B35 0_L23N_VRP5 IO L31N 5 130 ABp2a 2 io_le4n_cc_1c 6 1O_L32N_6 Rie 2635 I0_LeaP_cc ic 5 IO_L32P_5 HOT AERZE pa OSS 1024n cC_LC_5 10 18a 5 i 2 5V Clocking incoming data at high speeds required the used of the each input s delay buffer to align each bit The incoming clock needs to be adjusted and used to clock the inputs within its lane This process can be automated by the use of the new Virtex 4 feature IDELAYCTL For detailed description of the required user design to achieve 1Gbs operation see Xilinx Application note XAPP704 High Speed SDR LVDS Tranceiver Synchronus clocking and single ended
22. SEBERERRERREETEI Virtex 4 FX 1152 Beate Patel ea bepa ea Fa dR THIS BANK DOES NOT CONNECT ON FX 60 x 100 Only myn e i E12_RxP A20 RXPPADA 101 AVCCAUXRXA_101 Beh RXNPADA_101 AVCCAUXRXB_101 pss T AVCCAUXTX 101 FEO SE12_TxP Seer 4 TXNPADA_101 QSE11_TxP vraxe_101 PAZ 11_Txf SEN RN a3 TXPPADB 101 VTRXA 101 632 0 SEON A26 TXNPADB_101 VTTXA_101 Hss T vTTXB 101 8 5 QSE11_RxP OSEN RN Ab RXPPADB_101 lan 29 RXNPADB 101 B28 anpa 101 avecauxmeT_to1 P2285 Bei GNDA_101 Bes GNDA_101 Bes GNDA_101 B20 GNDA 101 A2 GNDA_101 ID mu peac ooe MO m mM am gt BERHE rm EERBER RRER Virtex 4 FX 1152 Figure 38 QSE Connector Each connector also has a clock input that can be routed to the MGT CLK of FPGA C to allow standards that require transmitting at an exact frequency such as PCI Express DN8000K10PCIE User Guide www dinigroup com 85 12 5 Optical Modules The DN8000K10PCIE comes with two optical module connectors If you need to interface to a specific standard the easiest way is to buy an SFP or XFP module that supports that standard Te RI e o E a als mm e 29022 gi i o e 5a f e 3 OEE e 3 be EE e SFP Connector eo e ojia o oo leg je mmn 5 mm bl
23. SelectMap signals connected point to point to the Spartan 2 except for FPGA B and C who share signals D 0 7 All signals are 2 5V CMOS signals except for D 0 7 of FPGA A Signals SELECTMAP_3V_DJ0 7 which are 3 3V CMOS All commands required to configure a Virtex 4 FPGA are created and embedded in the bit files created by the Xilinx Bitgen program The DN8000K10PCIE does not interact with the SelectMap interface other than to reset the FPGA using the PROGn INTn PROGn tesetr sequence described in UG071 and to copy a bit stream file unaltered to the FPGA over the data pins D 7 0 Select map commands can be issued to the Virtex 4 FPGA from the host using the same interface used to configure and FPGA After a Virtex 4 FPGA is configured it asserts the signal DONE On the DN8000K10PCIE these signals have an LED attached to each DONE signal placed near the upper corner of each FPGA DN8000K10PCIE User Guide www dinigroup com 54 FPGA A s LED is DS18 B is DS14 C is DS16 3 3V fe R169 120R IRFPGAA_DONE DS18 1K JOFPGAA_DONE FPGA DONE A FPGA_DONE_A Pg11 If your Virtex 4 FPGA design is failing to produce the intended or any results you should check the DONE light above the FPGA to make sure it is configured correctly The design files created by Xilinx bitgen software contain a CRC check so if the Virtex 4 FPGA detects a CRC failure there was a trasmission error during configuratio
24. XFP modules Intel part TXN181070850X18 from insight com 692 XFP heatsink clip Tyco part 1542992 2 5 2V bench supply for powering ECL based XFP modules if required Xilinx Parallel IV cable LVPECL oscillators for RocketIO MGT clocking The DN8000K10PCIE is supplied with a 250Mhz oscillator Epson Part EG 2102CA PECL Synplicity Identify or Xilinx Chipscope for embedded logic analyzer functionality 116
25. and Header B there is a bank that is dedicated entirely to the Headers For details about Virtex 4 IO banks see the Virtex 4 user guide This bank can be used for standards requiring a threshold volrage reference such as SSTL You can also use this bank for source synchronous clocking 10 3 10 Power The IOs connected to the headers on the Virtex 4 FPGAs are powered with a 2 5V power rail 10 4 Physical Micropax part number FCI 91294 003 The standard Dini Group mounting hole location for all 200 pin Micropax connections is 430 mils 10 5 Daughtercard Power Power is supplied to the daughtercard though dedicated power supply pins The maximum allowed current for each of the daughtercard supplies is 5 0V 1A 33V 1A 2 5V 1A DN8000K10PCIE User Guide ww w dinigroup com 78 12V 250mA 12V 250mA The 12V and 12V supplies are by default disconnected by removing the series jumper resistors R413 R412 R411 R414 This help prevent accidental damage due to careless probing The 12V and 12V supplies may be able to source as much as 0 5A of current if the current can be supplied by the host PC 10 6 The Mictor There is a Mictor connected designed to be used with an aginlent logic analyzer Riscwatch power PC debugger can also be used over this connection J4 MICTORO GND 4 MOTOR oR 7 8 9 10 PP C JTAG TOO 13 14 15 16 PP TI gL L417 18 19 20 OR 21 22 ET 23 24 25 26 NESTOR
26. by reading the setup file on the SmartMedia card If you wish to change the frequency after power on or do not want to use a SmartMedia card you can set the frequency in the USB program ACLK ACLK is generated from a 25MHz crystal Available frequencies are 31 25 34 375 37 5 40 625 43 75 46 875 50 53 125 56 25 59 375 62 5 65 625 68 75 71 875 75 78 125 81 25 84 375 87 5 93 75 100 106 25 112 5 118 75 125 131 25 137 5 143 75 150 156 25 162 5 168 75 175 187 5 200 212 5 225 237 5 250 262 5 275 287 5 300 3125 325 337 5 350 375 400 425 450 45 500 525 550 575 600 625 650 675 700 BCLK BCLK is generated from a 14 318 Mhz crystal Supported frequencies are 32 22 34 01 35 80 37 58 39 37 41 16 42 95 44 74 46 53 48 32 50 11 51 90 53 69 55 48 57 27 59 06 60 85 62 64 64 43 66 22 68 01 69 80 71 59 73 38 75 17 7696 78 75 80 54 82 33 84 12 85 91 89 49 93 07 96 65 100 2 103 8 1074 111 0 114 5 118 1 121 7 125 3 1289 1324 136 0 139 6 143 2 1468 150 3 153 9 157 5 161 1 164 7 1682 171 8 1790 186 1 193 3 200 5 207 6 214 8 221 9 229 1 236 2 243 4 250 6 257 7 264 9 272 0 279 2 286 4 293 5 300 7 307 8 315 0 322 2 329 3 336 5 343 6 358 0 372 3 386 6 400 9 415 2 429 5 443 9 4582 472 5 486 8 501 1 515 4 529 8 544 1 5584 572 7 587 0 601 4 615 7 630 0 644 3 658 6 672 9 687 3 DN8000K10PCIE User Guide www dinigroup com 34 DCLK DCLK is generated from a 16 0 Fundamental crystal Supported frequencies 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66
27. can be used to verify board functionality before beginning development A build utility described in the section Compiling The Reference Design can be used to generate new bit files or to generate bit files for less common configurations of the DN8000K10PCIE The reference design was created using Here are the default main txt file lines verbose level 2 sanity check y clock frequency AN 4 M 16 100 MHz not used for PCI MB test header test uses this clk clock frequency B N 2 M 28 200 MHz clock frequency DN 2 M 25 200 MHz clock frequency 1 N 2 M 25 312 MHz clock frequency 2 N 2 M 25 312 MHz 2 Reference Design Memory Map The Dini Group reference design memory maps the main features of the DN8000K10PCIE to the host interfaces PCI USB and RS232 The Main Bus interface is used to access the reference design memory map Addresses are 32 bits Each address contains a 32 bit word FPGA A 0x08000002 IDCODE 0x05000121 FPGA A 0x08000004 INITERCONTYPE 0x34561111 FPGA A 0x08000006 RWREG Scratch Register for testing FPGA A 0x08000010 LED OE Controls LED output enables FPGA A 0x08000011 LED OUT Controls LED outputs FPGA A 0x08100001 CLK_COUNTER Contains contents of ACLK counter FPGA A 0x08100002 CLK COUNTER Contains contents of BCLK counter FPGA A 0x08100003 CLK_COUNTER Contains contents of DCLK counter FPGA A 0x08100004 CLK COUNTER Contains contents of SYSCLK counte FPGA A 0x0C000000 ABPO OUT W the output state
28. in the 200 pin SODIMM socket 64x16Mb 300Mhz DDRII e Flash module for use in the 200 pin SODIMM header e Mictor module for use in the 200 pin SODIMM header 2 Mictor 38 connectors for use with logic analyzer 114 E DiNi Products USB Controller File Edit FPGA Configuration FPGA Memory Settings Info Refresh Enable USB gt FPGA Com FT PPC Port 1 Clear Log BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 Maximum packet size is 0x00000200 512 MCU FLASH VERSION Ox4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 MCU ERROR REGISTER 0x0 Maximum packet size is O0x00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 The Dini Group can optionally provide the following accessories 115 DN3k10SD Daughter card Provides tenth inch pitch test points DNMictor Daughter card Provides 5 Mictor connectors compatible with logic analyzers Memory modules for use in the DN8000K10PCIE DDR2 SODIMM sockets A and B Available Q4 05 QDRII SRAM 64x1Mb 300Mhz Flash memory 32x4Mb 2x4Mb serial flash Reduced Latency DRAM RLDRAM 64x8Mb 300Mhz Standard SRAM 64x2M Select ZBT Pipelined Flowthrogh Test connection module with two Mictor38 You may also want to obtain from a third party vendor 200 pin DDR2 SODIMM s SFP modules for Gigabit Ethernet infiniband IBM part 13N1796 from insight com 180
29. in the FPGA fabric see Appendix X FPGA pins 5 2 User Clock The DN8000K10PCIE has an SMA pair reserved specifically for inputing a clock The SMA pair is connected to a differential clock input on FPGA A LVDS_DCI is a preferred input standard but LYVCMOS_25 will work also User CLK Input Note these have been changed to SMA J6 UCLK 4 TE i CONN_SMA J5 UCLKn 4 5 Si H CONN_SMA 2 5V R3 49 9R lt R4 sen II OSS SSS O User Clock inputs VRNA3 VRPA3 P20 N20 J19 K19 N22 M22 J21 J20 M21 M20 L2 L19 P22 P21 ran IO_L8N_GC_LC_3 I K20 N21 Lc 3 IO_L5SN_GC_LC_3 IO_L6N_GC_LC_3 IO_L7ZN_GC_LC_3 veco_3 vcco_3 IO_L4N_GC_VREF_LC IO_LSN_GC_LC_3 1O_L6P_GC_LC 3 g IO_LIP_GC_CC_LC IO_LIN_GC_CC_LC3 IO_L2P_GC_VRNLC lt 10_L2N_GC_VRP_LC IO_L3P_GC_LC 3 IO_L4P_GC_LC 3 IO_L5P_GC_LC 3 IO_L7P_GC_LC 3 IO_L8P_GC_LC 3 1174 AR DNSOOOKI0PCI Virtex 4 LX 1513 S z To use this clock in a synchronous design send a copy of the clock out through the FBA Feedback A clock output pairs A B and C For a chart of clock input pad sites on FPGA A See Appendix X FPGA pins 5 3 Feedback Clocks User FPGA A and B each are capable of sourcing a clock that is distributed to all FPGAs including back to itself These feedback clocks allow the user to control a clock from inside the user design for single s
30. is slower than SelectMap You can still use the SmartMedia or USB interfaces to control clock settings if you plan to configure through JTAG To configure using JTAG we recommend using Xilinx Parallel cable IV or Xilinx platform USB cable The Xilinx program You should set the configuration speed of your JTAG cable to 4Mhz or below DN8000K10PCIE User Guide www dinigroup com 47 FPGA JTAG Cable IV 2 5V 2 5V O J13 3 A JTAG FPGA TMs JTAG_FPGA_TMS g Ana FPGA Tor gt 7 JTAG_FPGA_TD g JTAG_FPGA_TDI JTAG_FPGA_TDO 71 Te C S JTAG FPGA TDI 13 14 JTAG_FPGAINITA JTAG_FPGA_INITn 87332 1420 R263 1K Figure 25 FPGA JTAG Header The JTAG signals TMS is bussed to all three Virtex 4 FPGAs TDO connects to FPGA A the TDO of FPGA is connected to TDI of FPGA B the TDO of FPGA B connects to the TDI of FPGA C and TDO of FPGA C is connected to the TDI of J13 TCK is buffered and passed to each FPGA in a point to point fassion Note These signals should be matched length JTAG Clock Buffer u32 BUFIN CLKO RFPGA_TCK_A__ R278 33R JTAG_FPGA_TCKA CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 FB100 JTAG_FPGA_TCKA REPGA_ICK_B R279 33R FPGA AFPGATCKT VA FPGA JTAG_FPGA_TCKB ICRC R271 YAY SR JTAG_FPGA JTAG_FPGA_TCKC 2 5V oO c914 0 1uF
31. lt WORDADDR gt 4 digit 32 bit hex number representing a main bus address lt WORDDATA gt 4 digit 32 bit hex number containing data for a main bus transaction DN8000K10PCIE User Guide www dinigroup com 50 The following table describes the function of each of the available main txt commands DN8000K10PCIE User Guide www dinigroup com 51 Instruction Function lt comment gt The MCU performs no operation and moves to the next command VERBOSE LEVEL lt level gt This command will set the amount of output the MCU will produce over the RS232 port during configuration When level is set to 0 the MCU will produce only error output Before this command is executed the level is set to the default value 3 FPGA A lt filename gt The Virtex 4 FPGA A will be configured with the file named by lt filename gt FPGA B lt filename gt The Virtex 4 FPGA B will be configured with the file named by lt filename gt FPGA C lt filename gt The Virtex 4 FPGA C will be configured with the file named by lt filename gt SANITY CHECK lt yn gt If lt yn gt is set to y then the MCU will examine the headers in the bit files on the SmartMedia card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before thi
32. of FPGA IOs connected to the ABPO interconenct bus FPGA A 0x0C000004 ABPO OE W The ouput enable of each FPGA DN8000K10PCIE User Guide Www dinigroup com 102 INTRODUCTION TO THE SOFTWARE TOOLS FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGAC FPGA C FPGA C FPGA C FPGA C 0x0C000008 Ox0CO0000C Ox0C000010 Ox0C000014 Ox0C000018 Ox0C00001C Ox0CO00X X0 Ox0CO00X X4 Ox0CO00XX8 Ox0CO00XXC 0x10000000 0x17FFFFFF 0x18000002 0x18000004 0x18000006 0x18000010 0x18000011 0x18100001 0x18100002 0x18100003 0x18100004 0x18000001 0x18000003 0x18000005 0x18000007 0x18000008 0x1C000XX0 0x1C000XX4 0x1C000XX8 0x1C000XXC 0x20000000 0x27FFFFFF 0x28000002 0x28000004 0x28000006 DN8000K10PCIE User Guide ABPO IN ABPO Name ABP1 OUT ABP1 OE ABP1 IN ABP1 Name BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 B space IDCODE INTERCONTYPE RWREG LED_OE LED_OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER DDR2HIADDR HIADDRSIZE DDR2SIZEHIADDR DDR2TAPCNTO DDR2TAPCNT1 BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 C space IDCODE INTERCONTYPE RWREG IO on the ABPO interconnect bus The input state of each FPGA IO on the ABPO interconnect bus AB
33. of the FPGA Header B has more signals than Header A A daughtercard designed to work with header A will work with header A 10 1 3000K10 Compatibility The DN8000K10PCIE headers use pinout similar to that on the DN3000K10 A compatibility chart with the DN3000K10SD and Mictor daughtercards is given in the Appendix Pins The 1 5V power supplies MBCLKA F are not present 10 2 FPGA Connection On the DN8000K10PCIE all header signals are connected to LC pins on the Virtex 4 FPGA See the Virtex 4 User s Guide for detail about these signals The main result of this is that the headers on the DN8000K10PCIE may not be used with the Virtex 4 s current mode LVDS drivers Virtex 4 LVDS receivers may still be used Outputs compatible with LVDS can still be achieved using the proper selectIO driver settings and termination DN8000K10PCIE User Guide www dinigroup com 77 FPGA A Header Pins u11 2 HEE T lo P oae 5 Fae 1O_L1N_D30_LC a Sd O Lap Das LC D EISH 10L2N_D28 1G ass 5 101s 027 o Ioan p26 Lo 5 LP DSL 5 HT IO_L4N_D24_VREF_LC 10 L5P 023 LC N24 10 L5N_D22 101 pa anor Se 10 16P D21 10 1 8 NDR Ic 5 Haas OP Disc PEE 1O_L7N_D18_LC_1 aes A oLeP D17 cC LC_1 a8 Io Lan DI6LCCLC1 6201 Io L9P_GC_LC_1 10 Lesp_tc_1 3 HAp34 Bis IO_LSN_GC_LC_1 10 125N 101 ase Erg 10L10P_0 1 1 10_L26P_LC_1 PATS HAD n EH IO LION GC LC 1OL26N
34. of this amount supplying the power for PCI cards directly from the ATX power supply In high power applications exceeding 25W you may need to connect the Auxiliary power connector P3 1008080006 e e eo os AKII esil The Aux Power connector is a standard IDE hard es drive power connector and should be supplied by the ATX power supply that is in your computer P PpYy y P 2m z EET HEADER A EHRE EEEE cn ooo 1 wm w w Ww dinigroup com 90 as case Aux power connector 12V is shorted to the PCI slot 12V The power suppy driving the PCI slot and IDE power cable must be the same unit 14 FPGA System monitor ADC The System Monitor and ADC functions of the Virtex 4 FPGA are no longer supported by Xilinx The most important responsibility of the System Monitor temperature sensing has been moved to the configuration circuitry The DN8000K10PCIE will automatically monitor and prevent thermal overload in the three Virtex 4 FPGAs No user action is required FPGA A LX 200 Reserved pins U11 18 9 Avzo VREFN_SM VCCAUXA_2 5V Aw21 VREFP_SM Aw g AVDD_SM AW20 VN_SM Avis VEM ak AVSS_SM is m vern ADe VCCAUXA_2 5V B22 VREFP_ADC A20 AVDD_ADC VN_ADC a VP_ADC AVSS_ADC Virtex 4 LX 1513 DN8000K10PCIE User Guide www
35. or es TO2S00IMSOP10 2 7nF ae 71 5K TC2900 MSOP10 C1018 pale 2 70F 3 3V v 3 3v gt L _ V2 2 5V Be v3 1 8V vl 3 3V gex V4 ADJ V2 2 5V epee 0 5 V v3 1 8V v4 ADJ 0 5 V HARD RESET 7 2 Secondary Power Supplies The secondary power supplies are derived from a primary supply 7 2 1 DDR2 Termination Power DDR2 memory modules use the SSTL18 signaling standard Properly terminating SSTL18 requires a termination power supply of 0 9V Since as much as 1 6 Amps of termination current are needed a switching power supply is required DN8000K10PCIE User Guide www dinigroup com 70 DDR Switching Power Supply VTT 0 9V 3A c980 C967 c981 3 3V 100uF DNI 100uF DNI 100uF 10V 10V 10V TAI TANT TANT 0 9V_AVCC_IN R328 100R t t 1 8V coas c982 10uF L 100uF 2 u40 Ae tov E alr T 18 16 1 10 R325 AVGG VDD rg TANT 1K 1 15 VOS PE veca PVDD1 HZ TPE PVDD2 VREF_IN Ui eens is ja DIMM_VTT 957 R326 3 3V_R327 10K 0 9V_SHDN 12 _ 3 LOIMM_VTT_ A DIMM_VTT tur 1K 1 SHDN Mia tee T C998 cosa f c34 O SVFB 10 yep 3 3uH 2 150uF S 150uF 0 1uF eles 6 3V 6 3V C956 4 20 20 ae PGND1 E 7 0 001uF E PenD2 vrer our H4 TANT TANT AGND 17 DIMM_VREF nom S DGND PKG GND z boovrs L6554 PSOPT6 F Dimm vREF R316 1K The ML6554 produces u
36. pin power cable can be connected to the board from the same ATX power supply to reduce the voltage droop on 12V Please note that the board is capable of exceeding the 25W limit of the PCI connector depending on the desity of the FPGAs utilized and the operating frequency 5V This voltage supplies some RocketlO power The DN8000K10PCIE also has these secondary rails 0 9V This voltage is used to terminate the SSTL18 signaling of the DDR2 memory module Current is drawn from 3 3V RocketIO 1 2V top 1 2V right 1 2V bottom These linear regulated rails are very low noise supplies for the RocketIO CML inputs and outputs and RocketIO logic They are isolated from each other to improve the isolation of multiple RocketIO channels operating simultaneously DN8000K10PCIE User Guide www dinigroup com 68 RocketlO 1 5V This linearly regulated voltage rail supplies the internal digital logic of the RocketIOs RocketIlO 2 5V this linearly regulated voltage rail supplies the internal analog circuits of the RocketIO 12V This rail is passed directly from the PCI edge connector and ATX power connector to the Micropax expansion header See Chapter X Section X Expasion Headers Note that the fuse between 12V and the expansion headers is not installed on the board XFP VEE5 Power for this rail is not supplied by the DN8000K10PCIE but is required for the operation of ECL optical modules To power this rail you
37. provide sufficient airflow for high power applications DN8000K10PCIE User Guide www dinigroup com 92 INTRODUCTION TO VIRTEX 4 AND ISE Chapter Introduction to Virtex 4 and ISE 16 Virtex 4 The Virtex 4 FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry The goal was to revolutionize system architecture from the ground up To achieve that objective the best circuit engineers and system architects from IBM Mindspeed and Xilinx co developed the world s most advanced FPGA silicon product Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm The result is the first FPGA solution capable of implementing high performance system on a chip designs previously the exclusive domain of custom ASICs yet with the flexibility and low development cost of programmable logic The Virtex 4 family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures in networking applications deeply embedded systems and digital signal processing systems It allows custom user defined system architectures to be synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and software systems to be co developed
38. the DN8000K10PCIE and learned all of the features that you must know to start your emulation project If you are new to Xilinx FPGA you might want move to chapter 4 introduction to ISE and Virtex 4 and start adding your Verilog code to the reference design You will want to use Appendix X FPGA pins to place the IOs in your design All of the source code for the reference design in Verilog including embedded PowerPC code and utility is included on the provided CD DN8000K10PCIE User Guide www dinigroup com 30 Chapter Controller Software 1 USB Controller USBController application is used to communicate with the DN8000K10PCIE All USBController source code is included on the CD ROM shipped with the DN8000K10PCIE The USBController can be installed on Windows 98 ME 2000 XP There is a command line version called AETEST_USB that can be installed on Linux and Solaris The USBController Application contains the following functionality Verify Configuration Status Configure FPGA s over USB Configure FPGAs via Smartmedia card Clear FPGA s Reset FPGA s Set Global clocks frequency Set RocketIO CLK Frequency Update MCU FLASH firmware The following function interface with the Dini Group reference design Read Write to FPGA s see Appendix A for address maps Test DDRs FLASH Reigsters FPGA Interconnect 1 1 Menu Options 1 1 1 File Menu The File Menu has the following 2 options a Open opens a fi
39. to 111 232 look up tables LUTs or cascadable variable 1 to 16 bits shift registers o Wide multiplexers and wide input function support o Horizontal cascade chain and Sum of Products support o Internal 3 state busing e High performance clock management circuitry o Up to eight Digital Clock Manager DCM modules Precise clock de skew Flexible frequency synthesis DN8000K10PCIE User Guide www dinigroup com 95 INTRODUCTION TO VIRTEX 4 AND ISE O High resolution phase shifting 16 global clock multiplexer buffers in all parts e Active Interconnect technology O O O Fourth generation segmented routing structure Fast predictable routing delay independent of fanout Deep sub micron noise immunity benefits e Select I O Ultra technology O O O Q O Up to 960 user I Os 57 supported IO standards including eight differential standards Programmable LVTTL and LVCMOS sink source current 2 mA to 48 mA per I O Digitally Controlled Impedance DCI I O on chip termination resistors for single ended I O standards PCI support 1 Differential signaling 840 Mb s Low Voltage Differential Signaling I O LVDS with current mode drivers Bus LVDS I O HyperTransport LDT I O with current driver buffers Built in DDR input and output registers Proprietary high performance SelectLink technology for communications between Xilinx devices Hish bandwidth data path Double Data Rate DDR link
40. will need to connect an external power connector to the board from a low noise voltage supply There are test points for measuring the voltage levels of each rail near the top left of the DN8000K10PCIE Each rail is monitored by a voltage monitor circuit and will cause a reset if any of the primary supplies drop 5 or more below their setpoints There are also LEDs next to each testpoint to indicate the presence of each voltage rail These LEDs do not indicate that a rail is within 5 of its setpoint only that the rail is present and above 1 6V A power OK led shows the status of the ATX power supply s PWR_OK signal If this LED is lit then 5 0V and 3 3V and 12V 12V are within 5 of their setpoints PWR_OK R155 287R IRPWR_OK 10 mA ety green Ww gt 5 0V 2 5V 3 3V 1 8V 0 fo fo fo R129 R131 R130 R134 390R 82R 150R 30R R5 0V R2 5V 93 3V fQ1 8V DS9 DS11 DS10 DS12 N X X x S NO NM 7 1 Switching power supplies The main power rails for the Virtex 4 FPGAs are produced on board with three 20A switching power supplies one for each of 1 8V 2 5V and 1 2V DN8000K10PCIE User Guide www dinigroup com 69 Switching Power Supply 1 2V 20A Vout E sense 2 1 2V_ONOFF 1 Yo 0 5r ON OFF TANT TANT vout TRIM 3 PSU2 VIN C357 10uF 5V_IN_1 2V a gt 7 C340 H 150uF 6 3V c310 c279 10UF 10uF
41. you must compile the source code included on the User CD Instructions for compiling AETest are found in chapter 3 4 3 2 Use AETest The Aetest application should display it s main menu mulator PCI Controller Driver d on Jul 22 2005 at 12 58 24 6 P PCI Menu M Memory Menu FPGAs stuffed AB 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 HGT Menu Q Quit 6 e1008080 1 e0000006 2 df 660080 3 de000000 4 d000000 5 dc860000 Please select option Figure 13 AETEST Main Menu Run one of the tests Choose option 1 Remember the FPGA you test has to be loaded with the reference design or the test will fail gossceness gt TEST WITH ANY DAUGHTER BOARDS PLUGGED INttt iit trees Eitri tree Verbose output 0 none 9 al1 72 P on Errors default N y M y Loop default Y Y n n Random test data default N for walking bit test ya y Drive rest of board to test short circuit yn n Enter all FPGA s to be tested fo by a return example ABDEF AB Loop 1 of 1 rive from FPGA_A d 468 pins 104 single ended on FPGA_A drive from FPGA_B gt d 514 pins 150 single ended on FPGA_B finished with testing ALL TESTS PASSED press any key Figure 14 AF Test Interconnect Menu For more information on the AETEST program see Chapter 3 DN8000K10PCIE User Guide www dinigroup com 29 4 4 Moving On Congratulations You have just programmed
42. 0 AK1 VTRXB_110 apa VTTXA 110 RETO VTRXA_110 Ap O VTTXB 110 20 AVCCAUXMGT_110 ales MGTVREF_110 ans RTERM_110 PANS AP3 MGTCLK_P_110 Ap MGTCLK_N_110 AK2 o AN1 ACi ne OANA And AP5 ED GNDA_110 Virtex 4 FX 1152 OPT www dinigroup com 89 13 PCI Express interface 13 1 PCI zuge connector C4 me at I e E wis 2 9 68 TTE m an ne FH N8000K10PCIe COPYRIGHT 2005 THE DIN GROUP LA JOLLA INC MADE IN USA 2 4a 2 tt BERR t mow ET BD EEE TE MB 1 8V DDR2 SODIMM i SMART MEDIA 13 2 The Phillips PX1011A The Phillips PX1011A is a 1x PCI Express PHY chip providing an 8 bit 250Mhz interface to FPGA A Since this chip does nothing more than serializing and 8B 10B encoding the PCI express protocol will have to be implemented in the logic of FPGA A 13 3 Virtex 4 FPGA Communication 13 4 PCI clocking The PX1011A recovers a 100Mhz clock from the PClexpress edge connector This clock is used to capture the 2 5Gbs PCI express signal The parallel interface of the PX1011A is synchronous to the RXCLK signal that 13 5 PCI Power In some applications the DN8000K10PCIE can draw its power from the PCI Express slot The PCI express specification guarentees that the motherboard provide 25W of 12V power for the DN8000K10PCIE to use Most motherboards provide well in excess
43. 1 or plug the DN8000K10PCI into a PCI slot Do not plug an external power supply into J1 if the DN8000K10PCI is in a PCI slot Turn on the ATX power supply When the DN8000K10PCIE powers on it automatically loads Xilinx FPGA design files ending with a bit extension found on the SmartMedia card in the SmartMedia slot into the FPGAs 3 5 View configuration feedback over RS232 As the DN8000K10PCIE powers on your RS232 terminal connected to P2 will display useful information about the Configuration process 3 5 1 Watch the configuration status output DN8000K10PCIE User Guide www dinigroup com 16 No USB cable detected rebooting from FLASH please wait Setting ACLK N 01 M 000001000 DONE Setting BCLK N 01 M 000001000 DONE Setting DCLK N 01 M 000001000 DONE Setting RICLK N 01 M 000001000 DONE Setting R2CLK N 01 M 000001000 DONE DN8000K10PCIe MCU FLASH BOOT FPGAS STUFFED AB SMART MEDIA INFO MAKER ID EC DEVICE ID 75 SIZE 32 MB FILES FOUND ON SMART MEDIA CARD FPGA_B BIT FPGA_A BIT MAIN 1 TXT MAIN TXT CONFIGURATION FILES FPGA A FPGA_A BIT FPGA B FPGA_B BIT OPTIONS Message level set to default 2 Sanity check is set to default ON N 00 M 000001010 DONE Setting BCLK N 01 M 000001100 DONE Setting DCLK N 01 M 000001000 DONE Setting RICLK N 01 M 000001000 DONE Setting R2CLK N 01 M 000001000
44. 3 ball package to give the user extremely high IO count for high bandwidth and low latency interconnect between FPGAs Three hundred eighty nine differential links between FPGAs A and B allow for as much as 189 Gb s communication between the two FPGAs In order to support enough bandwidth to deliver real time data to your design at speed the DN8000K10PCIE is equipped with an optional Xilinx Virtex 4 FX100 with RocketIO Multi Gigabit Tranceivers Serial connections over Fibre Coax ribbon cable and Coax SMA cables allow for a total aggregate 150 Gb s off board communication To allow you to connect the FPGA to the resources that will be on your end product the DN8000K10PCIE also has highspeed expansion capabilities Below is a block diagram of the DN8000K10PCIE DN8000K10PCIE User Guide www dinigroup com 41 _ Samtec Cable PROM JTAG com emma l ae Expansion Connector Expansion ector SFP XFP Module 1 loro 50 50 orol Configuration FGPA MB Spartan I Pr Xilinx Xilinx Xilinx us FPGA A Bw FPGA FPGA ne LX100 160 200 1 LX100 160 200 FX60 100 oen FF1513 FF1513 FF 1152 uP Contig Virtex 4 N ii Control 5 nag aa te CY7C68013 3 TADATA 7 TK RADATA 7 9 s RICK Y 2 eier g Fes or singo onda Cable a gt ama a 3 Philips DDR2 SODIMM DDR2 SODIMM PX1011A up to AGB addressing up to 4GB addressing PCI Express Phy 1 lane 2 ocx I 1 lane Pod Tx 1 PC
45. 3 sh SAMTEC cable VITXA 103 aaa VTTXB_103 AAS 5 QSE15_TxP VTRXA_103 Use a cable with pins 1 and En TXPPADB_103 40 swapped m TXNPADB 103 J3 QSE15_RxP AC34 OSETE RN az RXPPADB_103 re 1 H 2 eune TEBAN M RKNPADE 103 AvccauxmeT_103 ASS QSE14 TxP 3 4 OSE14 RN 5 6 aannan QSE13 TxN 7 8 QSE13_RxP 888888 QSE13 TxP 3 10 OSETIS AxN tal ai 2 448846 QSE12 TxN 13 14 QSE12_RxP 222222 QSE12 TxP 15 16 QSE12_RxN oogogoo 17 18 Virtex 4 FX 1152 SI EJEARAEIKE CABLE_COUTn Fa 20 1 CABLE_CINp FASIESEIEIEN CABLE_COUTH 4 a ABEE ENE CABLE_CINp CABLE COUT 2 2 CABLE_CINn QSE11_TxN 5 26 OSE11 RxP uii OSET TAP 27 28 OSET AxN E r QSE14_AxP QSE16_TxN 31 32 QSE16_AxP 14_Rx A31 B32 OSETS_T P 33 34 OSEI6 RxN OSETIA RN Az RXPPADA 102 AVCCAUXAXA_102 Rag C 35 RXNPADA_102 AVCCAUXRXB_102 ps3 0 Qseis xN f 37 38 _ QSE15 RxP AVCGAUXTX_102 SEIA_TXP QSE15 TxP 39 Eid OSES AN QSE14 1x D34 Txapana 102 re SSE E84 NPADA 102 peu x vrrxe_102 Ho VITxB_ 102 5550 QSE13 TxP VTTXA_102 e320 HEARERS Seen HJ TXPPADB_102 VTRXA 102 S345 DEN 4 TXNPADB_ 102 QSE13_RxP Sethe 34 RXPPaDB 102 AVCCAUXMGT_102 820 Note These signals should be routed So lt lt o8 an as differential pairs Each of the airs shall be matched length Each ine ea Bee MGTCLK_P_102 Haar pair must be 100 ohm controlled METGLKN 102 N345 differential impedance 383333333333838 lt ddd dda didi S6SS4668SS68456 22222222222 222 GCOUOOOODOOOO0000
46. 5 J27 ABP 2 Aapa Di1 O L3N_6 ONE og ABpIa BACLKno_D27 O L3P_ADCS5_5 10_L11P_5 H27 ABNI2 ABna D10 O IO_L12P_6 Dg ABnia _ABPS A30 O L3N_ADC5_5 1O_L11N_5 c32 ABPS Apa Dig O_LAN_VREF_6 10_L12N_VREF 6 Big ABIS i sr OS 10_L12P_5 H Ae ABpa Di4 B1S ABpi5 ABN5 A31 D32 ABN8 And C1a 1O L5P 6 10_L13P_6 Ae ABS ABpes G25 O LAN_VREF_5 10_L12N_VREF_5 B25 AB ABos ATi O L5N_6 IO_LISNS eit ABpi6_ ABn22 G26 9 L5P_ADC4_5 IO L13F_S C28 ABN3 ABn5 Ato O L6P_6 10_L14P_6 GIT _ABn16 apps D29 9 L5N_ADC4_5 IOL19N_5 Asa ABPi6 Ao es OLN 6 1OL14N 6 Her ABY ABNe E25 O_L6P_ADC3_5 1O_L14P_5 aap AEN ABp6 E13 B12 pT ABN6 E29 A34 ABNIS IO_L7P_6 1O_L1SP_6 IO_L6N_ADC3 5 IOLI S oag Aep ABN6 F13 BIT ABnI7 A28 C29 ABPO B10 IO_L7N_6 IO_LISN_6 HBs ape ABNO A29 O_L7P_ADC2_5 10_L15P 5 e30 Ahk Sto O L8P_CC_LC_6 10_L16P_ amp es aor IO_L7N_ADC2_5 IO LISN 5 He en o0 io_lsN_cc_Lc 6 lo_Lien6 Pe Spar O_L8P_CC_ADC1_LC_5 1O_L16P_5 E39 ABN7 P81 I0_L8N_CC_ADC1_LC_5 10_L16N_5 Abe 10 L17P e 10 L2sp_ cc Lc 6 HE BAC Kp AEn Ht 10 Li7n 6 1O LESN Co Lc 6 Hae BAGLK nO io Li7P 5 10_L25P_cc_ Lo s Ho Sao FOLE 10_L26P_6 Es en REP a OUS OLAN OCLC S Fess aBPp23 ABe re OLI8N_6 1O_L26N_6 Fae Sa RENTS N O_LISP_ 5 10_L26P_5 FS AEN2S Ana D12 Oare 10_L27P_6 B6 ABN2O ABP a_Ba2 O L18N_5 10_L26N_5 H30 ABP ABAT B7 O L19N 6 1O L27N_6 jio EE SENT Bas
47. 8V 3A Bew rk us 5 3 VPOWER VOUT ag as 4 a 240R VCONTROL 1 SENSE jy ADJ m T15800Q R21 150R 100R e 2 5V 1 8V 1 21V VCC_MGT15 3A u15 5 3 25V 1 8V VCC_MGT12_right YRONER MOON SE SEE o i TAB u17 VCONTROL 4 es 3 TT SENSE ro 100R VPOWER VOUT 9 ADJ oyt CTAB R 4 VCONTROL i 240R TTSBOCO SENSE 5 ADJ ae Le T158000 R57 150R 100R ci7 ra 0 1uF 22R 42 5V 1 8V VCC_MGT12_bottom u9 5fvypowern vout H TAB R 4 TAB 240R VCONTROL i SENSE 5 ADJ Re LT158000 150R R24 100R Rework Figure 37 MGT 1 1V rework This rework drops the 1 2V RocketIO supply from 1 25V to 1 14V 12 3 The connections The following sections list the individual RocketIO connections For a complete pinout of the RocketIO connections See Appendix X Pins 12 4 Samtec Multi Gigabit ribbon cable For board to board high density connections two Samtec ribbon cable connectors J2 and J3 are connected to RocketIO The pinouts on the cable allow two DN8000K10PCIE boards to be connected to each other for a total of 10 bi directional channels operating at 5Gbs per channel per direction The Samtec part number J2 J3 QSE 014 01 F D DP A An appropriate crossover cable for cabling two DN8000K10PCIEs together is the Samtec EQDP 014 09 00 TBR TBL 4 DN8000K10PCIE User Guide www dinigroup com 84 U10 16 SE16_AxP a 103 AVCCAUXRXA_103 Heg En T9 RXNPADA 103 AVCCAUXRXB_103 57 AVCCAUXTX 103 SE16_TxP SEDONA ET TXNPADA 103 vTRxB_10
48. 999 CAGE GND 35 mA RED LED OPT RED LED OPT 555555556 SAGE eno F2 x y 4 EAEN CAGE ano HA azaalazaa z GAGE GND Tx XFP1_RX LOS CAGE GND RED GFI7Si7 XFP OPT 38 8 10 9B DB ne xepi interrupt N 1 993 98 ms 8 8 E 2 ABAV RSV agav sB3V 7 Vase 7 Vase av Sav S XFP2 Connector T Ries Ri83 Riez Ria7 R21 RIES miss R184 SIK Q 51K Q 51K SS SEK 51K 51K 51K idi Virtex 4 FX 1152 OPT ur ANZ T AVCCAUKRXA 100 te ln _ fm moD peseL L yep fb MOD_DESEL xeP2 MOD DESEL NTS AVCCAUXAXB 109 RXPPADA_109 HABS To INTERRUPT_N E aie XFP2_INTERRUPT_N AVCCAUXTX_109 RXNPADA_109 XFP2_RXp 18 TX_DIS XFP2_TX_DIS FPZ ARN RD XFP2 SCL N I Ro sc HP FP2 SDA XFP2_SCL TXPPADA_109 AES ES SDA XFP2_SDA TXNPADA 109 REFCLK x c1058 27 12 XFP2_MOD_ABS o o1uF OPT REFGLK Mon ass Ha FPZ MON N XFP2 MOD ABS Pis vraxe 109 Txppane 109 ABl rt x Los HA c Sepa mx TOS WE VTTXB 100 TXNPADB 109 AP 12 AEP2 BEFOIK p pown 2 ETET IOR XFP2_P_DOWN DANG VTRXA 109 C1059 0 01uF OPT 2 vees xee SP ANE Vrrxan1oo A vees et rz Per abe 108 Lari s ___vecss xFPo RXNPADB_109 E R189 3 3V 3 3V 22 voo1s_xFP2 5 1K 20 N14 83858 R108 R102 AVCCAUXMGT_109 eiae aalala a F 150R 150R 83355 99999 85955 Dss pst pagaq RED LED OPT Jg RED LED OPT XEP2 AX LoS RED g o g 8 8 RED 10 5 tA a XFP2 INTERRUPT Nma 1 993 1 a3 T m mA Figure 40 XFP Modules 12 6 The SMAs The easiest way to connect two Roc
49. C1028 3 3V 0 1uF 0 1uF Figure 22 Smart Media interface The Smart Media data bus D 0 7 also connects to the microcontroller Currently the MCU connection is not used The Microcontroller is able to read from the Smart Media interface by accessing the Spartan s memory mapped data over the MCU memory interface for the purposes of reading instructions from SmartMedia cards DN8000K10PCIE User Guide www dinigroup com 45 For instructions on creating a Smart Media card for configuring the DN8000K10PCIE see the section Configuration Options Smart Media 4 2 3 MCU communication The MCU communicates to the Spartan 2 FPGA over it s external memory interface pins DO 7 and A0 15 The Spartan 2 is assigned the address range OxDFOO to OxDFFF in the Microcontrollers memory space The 480Mbs data rate of USB 2 0 is too fast for the microcontroller to control so the MCU s hardware passes USB bulk transfer data to the MCU GPIF interface These signals SM 0 7 and GPIF_CTL GPIF_RDY connect to the Spartan FPGA The SM 0 7 signals also connect to the SmartMedia card socket although the MCU does not communicate with the SmartMedia interface directly The MCU_IFCLK signal provides a clock for this interface The signal is driven from the Spartan 2 FPGA 4 2 4 RS232 The DN8000K10PCIE has two RS232 headers One P2 is used by the microcontoller unit to provide configuration feedback and control The other P1 is connected to
50. Check the Spartan FPGA status LED DS24 This LED indicates that the Spartan II FPGA has been configured If this LED is not lit soon after power on then there may be a problem with the firmware on the DN8000K10PCIE This LED off or blinking may indicate a problem with one of the board s power supplies DN8000K10PCIE User Guide www dinigroup com 22 Check the FPGA A status LED DS18 to the upper left of FPGA A This green LED is lit when FPGA A is configured and operational This light should be on if you loaded the reference design from the SmartMedia card Check the FPGA B status LED DS14 directly above FPGA B This light should be lit green if your DN8000K10PCIE was installed with the FPGA B option and the reference design is loaded Check the FPGA C status LED DS16 to the upper left of FPGA C This green LED will light if you have the FPGA C option and the FPGA is configured Check the FPGA A User LEDs on the bottom side of the DN8000K10PCIE If you have successfully loaded the Dini Group s DN8000K10PCIE reference design these should flash all 8 green LEDs Check the FPGA C User LEDs on the bottom side of the DN8000K10PCIE If you have ordered the FX FPGA C option and the reference design is loaded these will flash all 16 LEDs If you suspect one or more FPGAs did not configure properly check the configuration circuitry s status lights These are four right angle mounted LEDs viewable out the side of the PC case I
51. FPGA C option you may select one of the following options OPTICAL SFP SFP default OPTICAL XFP XFP OPTICAL SFP XFP 7 Other Options 7 1 3 3 V Headers The DN8000K10PCIE can be configured to accept 3 3V input and output on a subset of expansion header pins These IOs are not voltage selectable by the software You must specify on your order that you would like this option For a list of header pins that can be used in 3 3V interfaces see Appendix A FPGA pins Select any of the following options The default option is all 2 5V header IO 3 3V Header A 3 3V Header B 7 2 12V Power Daughtercard supply voltages 12V and 12V are by default disabled by jumpers R411 Header A 12V R412 Header B 12V R414 Header A 12V R413 Header B 12V This default setting reduces the chance of damage to the Virtex 4 FPGA IO buffers due to user error or careless use of probes Specify this option to have the jumpers factory installed 8 Optional Equipment 113 The Dinigroup supplies standard daughtercards and memory modules that you can use with the DN8000K10PCIE e SE card 80 signals on 1 pitch headers e Mictor Card 5 Mictor38 headers for use with logic analyzers e SRAM module for use in the 200 pin SODIMM sockets of the DN8000K10PCIE QDRII 300Mhz 64x2Mb e SRAM module for use in the 200 pin SODIMM socket 64x2Mb Standard SDR SRAM Pipelined or Flowthrough NoBL available e RLDRAM module for use
52. GA RS232 It is located right next to the configuration RS232 port P2 If you have the reference design loaded the FPGA RS232 port runs at 19200 bps 8 bit no parity By default the FPGA RS232 port is connected to FPGA A One the computer s terminal the reference design is programmed to digitally loopback the input to the output If on the terminal you can read your own output then the reference design was able to capture the RS232 signal and generate an RS232 signal that your computer could capture If you are familiar with previous Dini Group products the reference design test outputs could be read from this serial port On the DN8000K10PCIE you must use the AETEST application to read the results of self test 4 3 Using AETEST to run hardware tests AETest is the program that you can use to verify the hardware on the DN8000K10PCIE as well as to demonstrate the reference design function The following instructions assume you have a PC running the Windows XP operating system The user CD includes a Windows version of the AETest program If you plan to use the DN8000K10PCIE in stand alone mode connect the DN8000K10PCIE to your WindowsXP computer and use aetest_usb in D aetest_usb aeusb_wdm exe If the computer asks for a driver click Have Disk and browse to D AETest_sb driver win_wdm dndevusb inf DN8000K10PCIE User Guide www dinigroup com 28 4 3 1 AETest on Linux or Solaris To use the AETest application on Linux or Solaris
53. I Express 20A 20A JTAG e 20A OOO 3A DN8000K1 0PCle Figure 19 DN8000K10PCIE Block Diagram The following sections describe in detail each circuit on the DN8000K10PCIE Note that Schematics appearing in this section are illustrative and may have had details omitted or have been modified for clarity and brevity If you need to probe modify or design around the DN8000K10PCIE you will need to examine the complete schematics See Appendix Schematics An assembly drawing has also been provided to help you find probe points on the DN8000K10PCIE See Appendix Assembly DN8000K10PCIE User Guide www dinigroup com 42 4 Configuration Circuit 4 1 Overview The goal of the configuration circuit on the DN8000K10PCIE is to allow the user to configure his FPGAs using any host interface The configuration system on the DN8000K10PCIE allows configuration over PCI USB JTAG or automatic configuration from a SmartMedia card m FPGAA XxC18V02 Master Serial _____ JTAG Header SelectMap 2 5V Spartan 2 200 FPGAB el FPGAC JTAG Header st SRAM Memory Map Flash Memory Smart Media A L MicroController Clocks ICS84421LOFP32 5 EPROM Ht The circuit is designed to provide an easy configurat
54. I bezel mounting hole 3 2 3 Part Pin Names Pin names are given in the form lt X gt lt Y gt lt Z gt The lt X gt is one of U for ICs R for resistors C for capacitors P or J for connectors FB or L for inductors TP for test points MH for mounting structures FD for fiducials BT for sockets DS for diodes F for fuses HS for mechanicals PSU for power supply modules Q for discreet semiconductors RN for resistor networks X for oscillators Y for crystals lt Y gt is a number uniquely identifying each part from other parts of the same X class on the same PWB lt Z gt is the pin or terminal number or name as defined in the datasheet of the part Datasheets for all standard and optional parts used on the DN8000K10PCIE are included in the Document library on the provided User CD 3 2 4 Schematic Clippings Partial schematic drawings are included in this document to aid quick understanding of the features of the DN8000K10PCIE These clippings have been modified for clarity and brevity and may be missing signals parts net names and connections Unmodified Schematics are included in the User CD document library as Appendix Schematics Please refer to this document Use the PDF search feature to search for nets and patts 3 2 5 Terminology Abbreviations and pronouns are used for some commonly used phrases MGT and RocketIO are used interchangeably MGT is multi gigabit transceiver RocketIO is the Xilinx trademark on their multi gig
55. Jul 22 2005 at 12 58 24 P PCI Menu M Memory Menu FPGAs stuffed AB 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 HGT Menu Q Quit 0 e1000000 1 e0000000 2 df 660000 3 de000009 4 dd000000 5 dc668000 Please select option _ You can easily loopback the SMA channels by connecting the RX and TX connectors of each MGT pair together with an SMA cable The SFP modules can be tested with an LR loopback attenuator Option 5 of the MGT menu allows you to invert the polarity of one of the SFP channels For the test to pass this must be done since SFP2 is recetved with inverted polarity The MGT tiles are connected as follows MGT A MGTB COLO TILEO QSE 1 QSE 1 COLO TILE1 QSE 1 QSE 1 COLO TILE2 SFP 1 XFP REFCLK1 XFP1 COLO TILE3 LOOPBACK SMA J22 COLI TILEO QSE 0 QSE 0 COLI TILE1 SMA J31 SMA J25 COLI TILE2 NC SMA J17 COL1 TILE3 XFP 2 SFP 2 REFCLK2 250MHz EPSON DN8000K10PCIE User Guide Www dinigroup com 105 INTRODUCTION TO THE SOFTWARE TOOLS REFCLK1 ICS 84020 Synthesizer DN8000K1O0PCIE User Guide www dinigroup com 106 INTRODUCTION TO THE SOFTWARE TOOLS KKKKKKKKKKKKKKKKKKK FPGA_A MAIN MENU KKKKKKKKKKKKKKKKKKK a Run Full Test Suite b Test Registers c Test SRAM d Test DDR e Test Interconnect f Write Memory Location g Read Memory Location h Disp
56. LO BSS tt 10_L11P_GC_LC 14 10 L27P LC es lt _PDETECTA 5 BIH IO_L1iN_GCLC1 1OL27N Lot HOSO Hapas Ana gie Q_LI2R GO LO IO L28P_ LO 1 Fuge mams Hapis BY IOLL12N_GC_VREF_LC_1 1O_L2BN VREFLO ast an 1 P GC LC 1 10_L29P_LC_1 Has ra eee en _LI3N_GC_LC 1 10_L29N_LC_1 M GE 2 FO 10_L14P_GO_LC 1 10_L30P_LC_1 Fe A FY OLLIan_ CC LC 10130 101 HE nr HANSE 45 1O_L15P_GC_LC1 10_L31P_LC_1 Hios rary TEE IOLLISN GCLO 10 131N 101 HE 120 10_L16P_GC_CG_LC 1 10_L32P_co L01 Har pae IO_L16N_GC_cc_LC1 1O_L32N_CC_LC_1 HAp41 G22 L24 HAp44 een 5 0 7P cC LC 1 10_L33P_CC_LC 1 T _LI7P_CC LC_ _L33P_CC_LC_ avora CS SSR gag 2 OLIN CC te oian ccici R23 Fans IO_L18P_VAN_LG_1 10_L34P_L _1 an VRPAT NIS N17 HAn17 NIB 1O_L18N_VAP_LC_1 VO LBAN LO Heos ra ne gan rnar a OLPC i 10_L35P_tc_1 St naa F as 10_LisN_LC1 10L35N_Lc1 484 gt Hansz rte 9 b20P_Lc 1 10 L36P_LC_1 k17 HAn28 Ver LC_1 10_L36N_VREF LC 1 m OLP LC 1 O L37P LG H i HAPS 221 10 L2iN LC 1 10 La7N Lot 688 7 a rich 10_L38P_LC_1 HH ra A 10122N ic IO_L38N LO Hass ORs 1O L23P IC 1 10_L39P_LC_1 Fass HARSI HAp29 THE IO 123N LC 1OL39N LC1 Far ta IC 10_L40P_LC_1 Henes E18 10 L24N LO 1 io L4on Lc HEZ Haer ba jara aba ba RTP pepe agoddooldddoald da 99899999099590 99999999999999 SSSSSSSSSSSSSS SEEENPESR SERS Salas SS Ses VHDRA 2 5V VHDRA R9 o 3 3V R171 o On both Header A
57. MoD DEF 0 F SPM SEE SFP1_MOD DEFO M33 SFP1_RxDp VEER IRATE_SELECT 5 ro SFP1_RATE_SEL H34 VITXB_105 FPI PADA RD Los 5 SFP1_LOS Nag VTRXA_105 RD VEER 33 VTRXB_105 VEER VEER VITXA_105 GAGE GAGE VCCT_SFP1 TXPPADB_105 HALS CAGE w CAGE z E Ay 4 ___ TXNPADB_105 CAGE U CAGE ro PR DNi CAGE A CAGE Nae CAGE 5 CAGE AVCCAUXMGT_105 CAGE CAGE Rigs CAGE CAGE axppana_1os LAEST Ge Se 150R 38 eu RXNPADB_105 3 CAGE a CAGE ipaa MGTCLK P 15 nm CAGE CAGE lasFP1_FAULT MGTCLK_N_105 888888888 1367073 OPT R109 dnar nenm aos 358353358 a me MGTVREF 105 999999999 10 WwW ose 000000000 mA Sa RED LED OPT RSFP1_LOS agea ads Ld EST Sa zakeela jajajajajaja JOsFP1_FAULT RED W oss 10 Ny RED LED OPT mA SFP1_TxFAULT jQsFP1_Los o o A SFP1 LOS 1 a w S o vocT_SFP2 voor sFP2 VOCR_SFP2 SFP2 Connector R221 Uto 19 Vitex 4 FX 1152 OPT J9 R151 S R148 1K 1056 TE A 1K 1K 0667 0 01uF OPT 20 DH veer VEET SFP2 TxFAULT Ang AVCCAUXRXA_109 Ape U SFP2_RxDp 424 To TXFAULT en SFP2_TXFAULT AVCCAUXTX_109 RXNPADA 109 C1057 _vect_srpa Hre VEET MOD DEF 2 REENER SFP2 MOD DEF2 C617_0 01uF 0 01uF OPT _ VCCR_SFP 15 VOC MOD DEF FPZ MOD DEFO SEPo MOD DEEO APS SFP2_TxDn 14 VEER MOB DEEID SEP2 RATE SEL NATE TXPPADA 109 ABTT SFP2 an 13 VEER RATE_SELECT SFP2 RATE SEL TXNPADA 109 _ 12 RD Los SFP2_LOS RD VEER R150 1K_VCCT SFP2 P13 API VEER VEER 43 3V an ee ee Eira VTRXB_109 TXPPADB_109 wars
58. OES Y4 ia oo ge 99 og go go go gg gy 30 VDDQ Yan 2 TP10 De ga el ale 1 aa i ad 23 VDDQ 34 DDRB_CK_TEST 88 of oe od gg 5g of Z gg vopa vs H 1 as 98 98 88 g3 33 5E 89 on BND pRB PuL AVDD ven Po amp ZR Z6 25 7 2 oo c202 8 33 34 55 55 48 gS 39 88 39 Azur 210 Foss e207 e208 e204 avoD ie 2 oo oo oo oo Jo 99 zu zs ur ur ur ur Dur R79 Reo sr a a de S y7 He DIMMB_ cKO gt DImMB_cko og vn DIMMB_CKnO g a z AGND 19 DIMMB_CK1 ve DIMMB_CKt PLL Bypassed m yen 18 DIMUE Cent DIMMB_CKnt u12 4 Virlex41X 1513 GND vo 16 FPGA B Clock yon HZ Inputs 27 24 z FBIN FBOUT U25 _Virex 4 Lx 1513 26 FEIN FBOUT 35 a cocusrr x i rs Er g Ml ws ro a g9 ad 100R ee a SS ge ia g9 g9 ga ef ey ga 85 88 g9 go g9 99 gy 99 gol g 38 os 99 38 38 as 83 833 t DDRB_PLL_FBn az az az az az az az 42 pa DDRBE PILL FBp So 39 898 33 J9 oe mo 45 88 je a aah tae a SN a a d od do od od oo od od 88 BE ee 2 22 98 Sa ae Se Set 38 Ec i El ZIERT EN NE 1250 DDRB FB Cn P SODIMM interfaces See Appendix X FPGA pins 9 2 Serial presence detect The EEPROM on the SODIMM is accessable by PCI USB or configuration UART DN8000K10PCIE User Guide www dinigroup com 75
59. PO ascii W ABP1 IO output values W Output enable of ABP1 bus R ABP1 input values ABP1 acsii XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte upper address bits for DDR2 interface number of bits in DDR2HIADDR The size of the DDR2 module Current IDELAY values of DDR2 interface XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing www dinigroup com 103 INTRODUCTION TO THE SOFTWARE TOOLS FPGA C 0x28000010 LED _OE Controls LED output enables FPGA C 0x28000011 LED _OUT Controls LED outputs FPGA C 0x28100001 CLK_COUNTER Contains contents of ACLK counter FPGA C 0x28100002 CLK COUNTER Contains contents of BCLK counter FPGA C 0x28100003 CLK_COUNTER Contains contents of DCLK counter FPGA C 0x28100004 CLK_COUNTER Contains contents of SYSCLK counte FPGA C 0x28000001 DDR2HIADDR upper address bits for DD
60. R2 interface FPGA C 0x28000003 HIADDRSIZE number of bits in DDR2HIADDR FPGA C 0x28000005 DDR2SIZEHIADDR The size of the DDR2 module FPGA C 0x28000007 DDR2TAPCNTO Current IDELAY values of DDR2 FPGA C 0x28000008 DDR2TAPCNT1 interface tebe MENT Map PED _wcurses rroanszsarot Requests bi AP PEI USB Oxat CONFIG 0x90 CLEAR_FPGA Oxad REBOOT u Oxbb SET_EP6TC 0x 65 CHECK_FPGA_CONFIG 0xb7 SETUP CONFIG Oxbd END_CONFIG oo 01 10 MB interface DN8000K10P CI FPGAB J 31 28 DOT KRKY IZ een 7 26 3 11 1 4 Internal Regs 3 11 4 31 0 250Mhz 200Mhz BCLK 200Mhz BCLK DDR2 DDR2 Host PCI Express 2 1 Using the Reference Design 2 1 1 Built In RocketlO test From the AETest main menu select option 4 MGT Menu The MGT test sends a repeating test pattern out all of the RocketIO transmit pairs and compares the input of each RocketlO channel to that pattern To run the test you must loop back each RocketIO pair DN8000K1O0PCIE User Guide www dinigroup com 104 INTRODUCTION TO THE SOFTWARE TOOLS mulator PCI Controller Driver a on
61. SmartMedia Card This option allows the user to use a SmartMedia card to configure the FPGAs Please section Creating Configuration File main txt for information on what files should be on the SmartMedia card to use this option Clear All FPGAs This option will deconfigure all FPGAs Reset This options sends an active low reset active for approx 20ns to all FPGAs on the signal called RESET_FPGASn which is connected to the following I O pins FPGA A AK19 FPGA B K21 FPGA C AG18 DN8000K10PCIE User Guide www dinigroup com 33 1 1 4 Settings Info Menu The Settings Info Menu has the following options 1 Set FPGA RocketlO CLK Frequency When the DN8000K10PCIE is first powered 2 ae up the RocketIO CLK inputs to the FPGAs are inactive The RocketIO CLK Inputs are connected to the following FPGA Differential CLK inputs on all FPGAs F21 G21 and AT21 AU21 This menu option allows the user to specify what frequency the RocketIO CLKs should be set at for each FPGA The supported frequency range is 31 25MHz 700MHz After selecting this option a pop up window will ask which FPGA s RocketlO Frequency you want to set or you can choose to set all to the same frequency and then what frequency you want Check the log window to verify what frequency the CLKs were actually set at Set Global clock frequencies The clocks on the DN8000K10PCIE are automatically adjusted to the user s desired frequency
62. The Pint Group LOGIC Emulation Source User Guide DN8000K10PCIEe LOGIC EMULATION SOURCE DN8000K 1OPCIEe User Manual Version 0 0 The Dini Group 2005 1010 Pearl Street Suite 6 La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com www dinigroup com Table of Contents List of Figures List of Table Chapter About This Manual Wekome to DN8000K10PCIE Loge Ermmlation Board Congratulations on your purchase of the DN8000KIOPCIE LOGIC Emulation Board If you are unfarml ar with Dini Group products you should read Chapter 2 Quick Start Guide to fanaharrze yourself with the user interfaces the DN8000KTOPCIE provides Figure 1 DN8000K10PCIE 1 Manual Contents This manual contains the following chapters About This Manual List of available documentation and resources available Reader s Guide to this manual Quick Start Guide Step by step instructions for powering on the DN8000K10PCIE loading and communicating with a simple provided FPGA design and using the board controls Board Hardware Detailed description and operating instructions of each individual circuit on the DN8000K10PCIE Controller Software A summary of the functionality of the provided software Implementation details for the remote USB board control functions and instructions for developing your own USB host software Reference Design Detailed description of the provided DN8000K10PCIE reference design Implement
63. USBController exe DN8000K10PCIE User Guide www dinigroup com 26 E DiNi Products USB Controller File Edit FPGA Configuration Settings Info Refresh Enable USB gt FPGA Com PPC Port 1 Clear Log BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 Maximum packet size is 0x00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 MCU ERROR REGISTER 0x0 Maximum packet size is 0x00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 Figure 11 USB Controller Window 6 This window will appear showing the current state of the DN8000K10PCIE Next to each FPGA a green light will appear if that FPGA is configured successfully The above window shows the USB Controller connected to a DN8000K10PCIE with a single FPGA in the B position If you have the reference design loaded and a DDR2 SODIMM installed you can use the USB Controller to run tests of the SODIMM From the FPGA Memory menu select Test DDR 7 Clear the FPGAs of their configurations Right click on an FPGA and select from the popup menu Clear FPGA The green light above the FPGA on the GUI and on the board should stop shinning green 8 Configure an FPGA using the USB Controller program Right click on an FPGA and select Configure FPGA via USB from the popup menu The program will open a dialog box for you to s
64. Virtex 4 FX 1152 OPT GND VCC CS843020 01 Figure 35 MGT 8442 Connections The LVPECL outputs of the ICS843020 are scaled down to meet the input requirements of the MGTCLK inputs An output from the ICS843020 01 is also converted to LVDS and driven to J3 pins 19 and 21 the Samtec QSE DP connector This can be used to forward a RocketlO clock off board along with rocketIO signals to support standards that require an exact reference clock like PCI Express J3 may also drive pins 20 and 22 The ICS843020 01 can receive this clock and use it to generate a frequency for the MGTCLK inputs For 10Gb serial transmission rates you should use one of the low jitter fundamental frequency SAW oscillators These oscillators operate at 250Mhz and so cover the gaps in the frequency synthesis options given by the ICS843020 01 DN8000K10PCIE User Guide ww w dinigroup com 82 NEAR OSC2_3 3VREG FPGA NEAR OSCILLATOR 2 FB103 NL FOR EG 2101CA R432 10 0K R433 1K NOTE VC 1 4V IS O PPM PULL R435 R436 ist 240R 240R osc2 vc 1 6 ISES TO USE AC COUPLING ON OE Nee NPUTS UNTIL THEY HAVE DONE FURTHER OSC2_PU i papak a ale cure ES OSC2_Yn WITH DC COUPLING OSC2_Y 2 GND our Es EG 2101CA 250Mhz R439 R440 U10 20 33R 33R C1048 0 01uF ana MGTCLK_N_110 MGTCLK_P_110 C1049 R441 R442 0 01
65. WAITE Aso INIT 3 7 OH nc GND CEPGAPrOGT W20 WRITEn 1 2 TDO E Ae m oy NG GND a CFPGA CSn Cie PROGRAMN TD pee oI nc cnp 28 ey D3 _ JTAG PROM IMS O33 Nc GND IMS ca JTAG_PROM_TCK oc TCK nz xc2s200 XCTBVO2 Vast j 3 3V 43 3V 43 3V G R365 100R pli K_fik_ fik 1 2 267 R269 R270 3 4 JTAG PROM TMS 5 6 JTAG PROM TCK DS24 7 Ei T JTAG_PROM TDO Ww 3 10 JTAG PROMTDI a Ti ia 73 fang 87332 7420 o g R268 Do 1K CFPGA DONE 1 Q aie Figure 21 Spartan II Configuration As soon as the Spartan II FPGA is configured it resets the Cypress microcontroller Pull downs on the PROG pin of FPGAs A B and C ensure that the FPGAs cannot be active unless the Spartan IT is successfully configured 4 2 2 Smart Media The Smart Media card interface is connected to the IOs of the Spartan 2 FPGA J24 SMCLE 2 u2ic SM_ALE 3 CLE voi AAB ALE 102 10 io Heo Wen a vo WE 108 10 10 Hegg 0 MW 5 ABE SM CEn 219 WE 104 10 10 teu SM REn 209 CE Lied 10 10 Tape RE vos 10 10 yg 2 107 10 10 Ay 108 10 10 Haag SM cbn id a5 1a o PaAeS 10 10 Sm wein 27 WP CARD INS 10 el WP CARD_INS 10 10 Mrd 10 10 AATE 1 19 SM_RDYBUSYn RAT O 10 Hm 7 GND RB 47 W110 ne Jg GND LVD x Dye 10 10 Hyd 55 1 GND 7 Oye 10 io Ho Sa CanDo VCC a5 o o0 CGND VCC 888888 SmarlMedia 333888 gt gt gt gt gt gt xC25200 oj IS F4 FAAS 5 5 5 3 3V p VCC SM POLYSWITCH C1027
66. X100 10 11 12 LX160 10 11 12 LX200 10 11 5 3 FPGAC Select an FPGA part to be supplied in the C position This fpga is connected to a momory module socket This FPGA is required to provide Multi Gigabit serial communication In order to achieve 10 Gbs selectIO operation the 12 speed grade is required NONE FX40 10 11 11x 12 This option makes the 200 pin SODIMM memory socket one SMA channel and one QSE cable channel unusable FX60 10 11 11x 12 This option makes one channel of SMA and one channel of 5Gb QSE cable unusable FX100 10 11 11x 12 6 Multi Gigabit Serial Options 6 1 Serial Clock Crstals If you need to interface to a specific Multi gigabit serial IO protocol you may want to specify a compatible crystal For information on the impact of the selected crystal option see Appendix X Clock configuration Chose one of the following frequencies in Mhz 9 8304 12 890 14 318 16 000 21 477 24 576 25 000 The default option is 25 000 Mhz 112 6 2 Module Sockets XFP and SFP Modules provide 1 0 10 5 Gb optical serial communications to FPGA C DN8000K10PCIE has two optical ports each can be installed with either an SFP or XFP connector XFP modules operate only in the 9 5 10 5 Gb s range Available SFP modules operate between 1 4 25 Gb s For 10Gb operation a 12 speed grade FX part may be required These parts may not yet be available before If you have the
67. _SCL i SDR 12 SMBCLK C280 llic_SDA lt gt SMBDATA DXP 1100pF 1000pF IIC_IRQn DAN IIC_IROn ALERT FPGA DXN A TEMPA_SAO ADDO nc H x ADD1 NC 3 X NC Mma x GND Me Sie DN8000K10PCIE User Guide www dinigroup com 67 This circuit shows the MAX1617 temperature monitor The IIC bus is connected to the Cypress microcontroller 7 Power The DN8000K10PCIE gets is power from the 12V and 3 3V rails of the PCI Express card edge connector It can also be operated in stand alone mode with a 20 pin ATX power supply connector The PCI slot is capable of sourcing 25W The main rails of the DN8000K10PCIE are 1 2V This is the main power supply rail used for the internal digital logic of Virtex 4 FPGAs 1 8V This is used for IO signaling and interal logic of DDR2 SDRAM memory It is also used to supply some Gigabit optical modules and is used as a low power current source to supply RocketIO isolated power rails 2 5V This is used to power FPGA interconnect with low power LVDS It is also used as the analog power supply on the Virtex 4 FPGAs 3 3V This voltage supplies the LVDS clock distribution trees It is also used to power the LVTTL interfaces of the Cypress microcontroller 12V This voltage is used to supply power to the 1 2 2 5 5 0 and 1 8V switching power supplies It also powers the FPGA cooling fans If the PCI slot isn t providing enough power then a Hard Drive 4
68. abit transceiver hardware MCU is the Cypress FX2 Microcontroller U39 DN8000K10PCIE User Guide www dinigroup com 8 Chapter Quick Start Guide The Dini Group DN8000K10PCIE is the user friendhest board available with multiple Virtex 4 FPGAs However due to the number of features and flexibility of the board it will take some time to become familiar with all the control and monitoring interfaces equipped on the DNS8000K10PCIE Please follow this quick start guide to become familiar with the board before starting your ASIC emulation project 1 Provided Materials Examine the contents of your DN8000K10PCIE kit It should contain e DN8000K10PCIE board e Two Smart Media cards e USB SmartMedia card reader e RS232 IDC header cable to female DB9 e USB cable e CDROM containing Virtex 4 Reference Design User manual PDF Board Schematic PDF USB program usbcontroller exe Source code for USB program and DN8000K10PCIE firmware 2 ESD Warning The DN8000K10PCIE is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm There are two large grounded metal rails on the DN8000K10PCIE The DN8000K10PCIE has been factory teste
69. and B This interconnect was routed as tightly coupled differential LVDS to provide the best immunity to power supply and crosstalk noise so that your interconnect can operate at the full switching speed of the output buffers Following Xilinx recommendations the interconnect on the DN8000K10PCIE was designed to operate at 1Gb s for every LVDS pair Note 1Gb s operation requires the fasted speed grade part LX200 12 In order to achieve such breakneck speeds you will need to operate the busses of signals using a source synchronous clocking scheme The interconnect signals on the DN8000K10PCIE have been optimized to operate in lanes There are 7 lanes between FPGAs A and B three between B and C and two between FPGAs A and C Each lane has a differential LVDS source synchronous clock in each direction For a complete pinout of the Virtex 4 FPGA interconnect along with a breakdown of lane assignments see Appendix X FPGA pins DN8000K10PCIE User Guide www dinigroup com 73 FPGA A v7 FPGA B u12 6 paai A i0 Lips 10_L9P_cc_Lc_6 Heto Sao ANS IO_LIN_6 IO_L9N_CC_LC 6 Hia ABp12 i IO_L1P_ADC7_5 10_L9P_CC_LC_5 5H Asp E12 HZ ABpi2 ABNI5 A26 B27 _ABCLKNO Jen EiT 10_l2P 6 io_LioP_6 75 Enz ABPA E2 OLIN ADG7 5 ON CCC S HFa ABPIE ABp2 Bia 10 12N 6 IO_LIONE G13 ABpIs ABN4 Fee O L2P_ADC6_5 10_L10P_5 G28 ABNI6 ABn2 cig 9_12P_ amp IO_L1P 6 Giz ABni3 BACLKpO E27 O L2N_ADC6_5 10_L10N_
70. ata transfer to and from the User design The RS232 interface allows low speed data transfers to and from the User design and control and monitoring of the configuration process This section will get you started and show you how to operate the provided software For detailed information about the reference design and implementation details see Chapter X The Reference Design 4 1 Operating the USB controller program Use the provided USB monitoring software to verify that the design is loaded into the FPGAs 1 Insert the CDROM that came with your DN8000K10PCIE into the CDROM drive of your computer Connect the USB cable to your DN8000K10PCIE and a Windows XP PC Before or after the DN8000K10PCIE has powered on When you connect the USB cable to your PC for the first time Windows detects the DN8000K10PCIE and asks for a driver The board should identify itself as a DiNi Prod FLASH BOOT When the new device detected window appears select the option install from a list gt select search for the best driver in these locations Select include the location in the search and browse to the product CD in Source Code AETEST_USB driver win_wdm gt select finish After Windows installs the driver you will be able to see the following device in the USB section of Windows device mananger DiniGroup DN8000K10PCIE FLASH boot Run the USB controller application found on the product CD in Source Code USBController
71. atasheet the maximum recommended operating temperature of the die is 85C degrees If the microcontroller measures a temperature above 80 degrees it will reset the DN8000K10PCIE If you think your DN8000K10PCIE is resetting due to temperature overload you can use the temperature monitor menu to measure the current junction temperature of each FPGA ENTER SELECTION g FPGA TEMPERATURES Degrees Celsius 4 B 29 Set FPGA Temerature Alarm Threshold degrees C decimal values range 1 127 Old Threshold 80 New Threshold 85 Threshold Updated 85 Degrees C Figure 7 Temperature Threshold Menu The Virtex 4 FPGA can operate as hot as 120C degtees before damaging the part although timing specifications are not guaranteed The MCU allows you to change the reset threshold DN8000K10PCIE User Guide www dinigroup com 20 although we recommend improving your heat dissipation to maintain a low junction temperature 3 5 4 Multiplex Serial port The DN8000K10PCIE has one serial port P1 for user use This single port is multiplexed so that any FPGA can access it through its RX and TX signals You can use the RS232 MCU interface to change the FPGA to which P1 is connected ENTER SELECTION 7 PORT 1 D PORT 2 A PORT 3 A PORT 4 A Enter Port to change 1 4 q to quit 1 Enter FPGA to set port to A I B Do you want to change more RS232 Ports y or n n Figure 8 RS232 Port Menu
72. ation details of the reference design interaction with DN8000K10PCIE hardware features FPGA Design Guide Information needed to use the DN8000K10PCIE with third party software including Xilinx ISE Synplicity Synplify Certify and Identify Some commonly asked questions and problems specific to the DN8000K10PCIE Ordering Information Contains a list of the available options and available optional equipment Some suggested parts and equipment available from third party vendors 2 Additional Resources For additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs DN8000K10PCIE User Guide www dinigroup com 5 Resource Descripti on URL UserDN8000K10PCI E User Guide This is the main source of technical information The manual should contain most of the answers to your questions Dini Group Web Site The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Virtex 4 User Guide Xilinx publication UG070 http www xilinx com bvdocs userguides ug070 pdf Most of your questions regarding usage and capabilities of the Virtex 4 devices will be answered here including readback boundary scan configuration and debugging E Mail You may direct ques
73. cle the board 2 2 Updating the Spartan EEPROM firmware Connect a Xilinx Parallel IV configuration cable to the parallel port of your computer The Parallel IV cable requires external power to operate so you may need to connect the keyboard connector power adapter When the Parallel IV cable has power the status LED on Parallel IV turns amber Use a 2mm IDC cable to connect the Parallel IV cable to the DN8000K10PCIE connector J14 DN8000K10PCIE User Guide www dinigroup com 37 Figure 17 Firmware Update Header Power on the DN8000K10PCIE When the Parallel IV cable is connected to a header the status light turns green Open the Xilinx program Impact usually found at Start gt programs gt Xilinx ISE 7 1 gt Accessories gt impact Impact may ask you to open an impact project Hit cancel Choose the menu option File gt Initialize Chain Impact should detect 2 devices in the JTAG chain Xc18v02 and Xc2s200 For each item in the chain Impact will direct you to select a programming file for each For the xc18v02 device select the Spartan Firmware update file provided by Dini Group This file should be named prom mcs Hit Open Impact will then ask for a programming file to program the xc2s200 Press Bypass DN8000K10PCIE User Guide www dinigroup com 38 7 Untitled Configuration Made IMPACT OSA sR Ra olMueom sr Boundary Scan Stave Serial SeleciMAP Desktop Configuration F Ense Belone Progamming f F Vai
74. contains the files FPGA_A bit FPGA_B bit FPGA_C bit main txt The files FPG_A C bit are files created by the Xilinx program bitgen part of the ISE 7 1 tools The file main txt contains instructions for the DN8000K10PCIE configuration circuitry including which FPGAs to configure and to which frequency the global clock networks should be automatically adjusted 2 Insert the SmartMedia card labeled Reference Design into the DN8000K10PCIE s SmartMedia slot contacts down 3 4 Connect cables The configuration circuitry can accept user input to control FPGA configuration or provide feedback during the configuration process The configuration circuitry IO can also be used to transfer data to and from the user design 1 Use the provided ribbon cable to connect the MCU RS232 port P2 to a computer serial port to view feedback from the configuration circuitry during FPGA configuration Run a serial terminal program on your PC On Windows you can use HyperTerminal Start gt Programs gt Accessoties gt Communications gt HyperTeminal and make sure the computer serial port is configured with the following options e Bits per second 19200 e Data bits 8 e Parity None e Stop Bits 1 e Flow control None e Terminal Emulation VT100 2 Use the provided USB cable to connect the DN8000K10PCIE to a Windows computer Windows XP is recommended DN8000K10PCIE User Guide www dinigroup com 15 3 Plug an ATX power supply into J
75. d and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the provided CD and SmartMedia card The 200 pin connectors are not 5V tolerant According to the Virtex 4 datasheets the maximum applied voltage to these signals is VCCO 0 5V 3 0V while powered on These connections are not buffered and the Virtex 4 part is sensitive to ESD Take care when handling the board to avoid touching the daughtercard connectors DN8000K10PCIE User Guide www dinigroup com 11 3 Power On Instructions The image below represents your DN8000K10PCIE You will need to know the location of the following parts referenced in this chapter tre HH DDR2 Sodimm A Figure 3 DN8000K10PCIE configuration controls To begin working with the DN8000K10PCIE follow the steps below 3 1 Verify Switch Settings The DN8000K10PCIE uses a DIP switch to program the FPGA configuration circuitry The function of these DIP switches is Listed in Table 2 Verify that the switch settings on your board match the default settings Table 2 Switch Description Switch Default Signal Name On setting Off setting Position S1 1 Off Reserved si2 jor Reed S1 3 Off Bootmode Firmware update Normal operation default DN8000K10PCIE User Guide www dinigroup com 12 Switch Default Signal Name On set
76. dinigroup com 91 15 Mechanical The dimensions of the PWB are 312mm long by 135mm tall plus a 8 25mm PCI edge connector This is taller than the PCI specification allows although the DN8000K10PCIE fits easily inside most ATX computer cases nam 2 444444 N Hr FF Te TR EEE Tr 4 ty HHHH HHHH FHHAH AHHH EET Pang ia at UHRE a 4 4t E He HEHE HEHE er x kta E PE Th ii Heo ot ei Hi 7 ae t oe ga st oa Peer t 3 SH Ar AR 3 ER te A Ptt F h T es at hh hh hh 4 Per Tete a Fie Hog Hy DER te K hk x h ah te EN ah h FR ah 4h sit k Ar eth 3 45mm TYP ee ath hh hh 4 af ht ht th ht hh hh hk ae B mm R TYP 22 50mm x 45 TYP er in uwgg Fot o ni w N 33 50 The topside clearance with the factory installed active heatsinks is 23mm This leaves just enough room for airflow if the adjacent PCI slot is left unoccupied or the DN8000K10PCIE is the last PCI card in the row The default heatsinks can be removed if you do not require high power operation allowing the DN8000K10PCIE to meet the PCI height restriction The back side clearance is 3 5mm This exceeds the PCI specification by 1 5mm If it is required that the DN8000K10PCIE use only one PCI slot the fan can be removed from the active heatsink assembly as long as sufficient airflow is provided Most PC cases do not
77. e design is compiled for the same type of FPGA that the MCU detects on your DN8000K10PCIE If the design and FPGA do not match the MCU will reject the file and flash the Error LED You may need to disable to sanity check option See Chapter X section X if you want to encrypt or compress your configuration Sanity check passed files Senasa DONE WITH CONFIGURATION OF FPGA A BEES CONFIGURING FPGA The MCU is configuring FPGA B according to instructions in Bebe bbb ebb EEEE Kk MATNTXT Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA_B BIT FILE SIZE 003A943B bytes PART 4v1x100ff151317 05 01 DATA 2005 07 19 TIME 17 05 01 Sanity check passed RTS DONE WITH CONFIGURATION OF FPGA B The MCU is setting the temperature threshold to cause a board reset TEMPERATURE SENSORS A YES B YES FPGA Temperature Alarm Threshold 80 degrees C DN8000K10PCIe MAIN MENU Jul 27 2005 10 38 05 1 Configure FPGAs using MAIN TXT 2 Interactive configuration menu 3 Check configuration status 4 Change MAIN configuration file 5 List files on Smart Media 6 Display Smart Media text file 7 Change RS232 PPC Port 8 Set FPGA Address 9 Write to FPGA at current address a Read from FPGA at current addres Here is the MCU main menu g Display FPGA Temperatures h Set FPGA Temperature Alarm Threshold ENTER SELECTION Options 8 9 and A ate only available whe
78. ections are on J3 and or J4 on the daughtercard make sure the OE pins on the daughtercard buffers are active VVVVVVV VV DN8000K10PCIE User Guide Www dinigroup com 100 INTRODUCTION TO THE SOFTWARE TOOLS Chapter Introduction to the Reference Design This chapter introduces the DNS000K10PCIE Reference Design indud ng information on what the reference design does how to build t from the source files and how to modify t 1 Exploring the Reference Design 1 1 What is the Reference Design The reference design is a fully functional Virtex 4 FPGA design capable of demonstrating most of the features available on the DN8000K10PCIE Features exercised in the reference design include e Access to the DDR2 SDRAM Modules At 200Mhz e UART Communication e FPGA Interconnect e Interaction with the Configuration FPGA and MCU e Use of Embedded PowerPC Processors eventually e Memory Mapped Access Between PPC And User Design eventually e Access to external LEDs e Communication via Rocket I O Transceivers e Instantiation of Daughter Card Test Headers e USB memory map to DDR2 memory e Pin multiplexed FPGA interconnect using LVDS at 650Mbs per signal pair DN8000K10PCIE User Guide www dinigroup com 101 INTRODUCTION TO THE SOFTWARE TOOLS All source code for the reference design is included on the CD and may be used freely in customer development Precompiled bit files for the most common stuffing options are also included and
79. ed Development Kit EDK The Reference Design uses the Xilinx EDK to instantiate an embedded PowerPC Processor The EDK project can be found at DN8000K10PCIE PPC system xmp and can be opened and modified with the Xilinx Embedded Development Kit software 3 1 2 Synplicity Synplify The Dini Group uses Synplicity s Synplify software to for design synthesis The Synplicity projects for each of the 3 FPGAs on the DN8000K10PCIE can be found at DN8000K10PCIE synthesis prj These projects have been compiled using Synplify Pro version 7 3 3 1 3 Xilinx ISE 3 1 4 The Build Utility Make bat The Build Utility is found at DN8000K10PCIE build make bat This batch file is used to set system parameters to the desired configuration i e V4FX60 vs V4FX100 etc and to invoke all of the above tools from the command line Instructions for invoking the batch file can be DN8000K10PCIE User Guide www dinigroup com 108 INTRODUCTION TO THE SOFTWARE TOOLS found by viewing the batch file with a text editor Additional information about using the batch file to build the reference design is found below Taking the reference design through all of the various tools for several FPGA s can be very tedious and time consuming this batch file can do it all in one command The command line utility Make bat is an MS DOS batch file compatible with Windows 2000 and later operating systems Make bat should be run from the command line wit
80. elect the configuration file to use for configuration Browse to the provided user s CD USERCD BitFiles 8000K10PCI MainTest LX100 fpga_a bit If you are configuring an LX200 or FX60 devices you should select a bit file from the LX200 or FX60 directories instead If you are configuring FPGA B or FPGA C you should select fpga_b bit or fpga_c bit instead Done FPGA B cleared successfully DN8000K10PCIE User Guide www dinigroup com 27 FPGA A cleared successfully Doing a sanity check Sanity Check passed Configuring FPGA B via USB please wait File D dn_BitFiles DN8000K10PCIE MainTest LX100 fpga_b bit transferred Configured FPGA B via USB Figure 12 USB Controller Log Output 9 The message box below the DN8000K10PCIE graphic should display some information about the configuration process The USB Controller program also allows you to easily configure and transfer data to and from the user design on the emulation board More information is provided in Chapter X The USB program 4 2 Communicating to the User Design over the Serial Port You may want to communicate with your design over the user serial port P1 Only one FPGA can use Pl at a time Before you can communicate to your design change the RS232 multiplexing settings as described in Section 3 6 4 You can also change the RS232 multiplexing settings using the USB Controller software Connect a second RS232 cable to Pl the FP
81. en 540 and 680Mhz See datasheets for parts ICS8442AY and ICS843020 01 The reference frequencies are ACLK 25Mhz BCLK 14 18Mhz a DCL Mz ww wiki goMipz com 52 An example main txt file VERBOSE LEVEL 0 This will prevent the MCU output over RS232 to speed up configuration FPGA A a bit this will load the configuration a bit into FPGA A CLOCK FREQUENCY AN 4 M 10 This will cause Aclk frequency to be 25 10 250 4 62 5Mhz MAIN BUS 0x0000 0x0001 Writes to a register in FPGA A Even if you are not planning to configure your Virtex 4 FPGAs using a SmartMedia card you may want to leave a SmartMedia card in the socket to automatically program your global and rocketlO clock Clocks may also be programmed using the provided USB application or over the MCU RS232 terminal 4 3 3 USB The USB interface on the DN8000K10PCIE is provided by the Cypress microcontroller unit The Cypress microcontroller is programmed to interrupt when it recetves a USB vendor request When the MCU receives over USB a Bulk Transfer type request it does not interrupt The raw data contained in the bulk transfer is driven out on the GPIF pins of the MCU the SM 0 7 signals to the Spartan 2 The data is clocked out using the MCU_IFCLK clock signal to the Spartan 2 As long as the signal GPIF_CTL is held high by the MCU the Spartan 2 clocks MCU_IFCLK to receive the USB data When data is written to the Spartan 2 from a bulk transf
82. er over the MCU s GPIF interface the Spartan 2 either writes that data onto the SelectMap interface of the Vitex4 FPGAs or onto the Main bus using the Main Bus interface described in the Reference Design chapter The control register FPGA_SELECT within the Spartan 2 determine to which interface this data is routed to 4 4 FPGA configuration Process For information regarding the JTAG interface and configuration See Xilinx publication UG071 Virtex 4 configuration guide When configuring over USB or SmartMedia the FPGAs are configured over the Virtex 4 SelectMap bus All SelectMap signals are connected directly to the Spartan2 FPGA The SelectMap signals are D 0 7 SelectMap data signals DN8000K10PCIE User Guide www dinigroup com 53 PROGRAM_B Active low asynchronous reset to the configuration logic This will cause the FPGA to become unconfigured The documentation refers to this signal as PROGn DONE After the FPGA is configured it is driven high by the FPGA INIT Low indicates that the FPGA configuration memory is cleared After configuration this could indicate and error RDWR_B Active low write enable The Documentation refers to this signal as RDWR BUSY When busy is high the SelectMap configuration stream must stop until BUSY goes low CS_B SelectMap chip select The documentation refers to this signal as CSn CCLK Signals D 0 7 DONE RDWR_B and CS_B are clocked on CCLK Each Virtex 4 FPGA has a complete set of
83. f there has been an error the four LEDs will blink If there has been no error the two lower LEDs will be ON and the upper two OFF If there was an error the easiest way to determine the cause of the error is to connect a terminal to the RS232 port P2 and try to configure again Configuration feedback will be presented over this port You should also notice the Fans mounted above the 3 Virtex 4 FPGAs and the Fan mounted above the power supplies spinning Assembly Number Signal Comment DS9 5 0V_PRESENT The 5 0V power rail is present above 1 7V DS10 3 3V_PRESENT The 3 3V power rail is present abobe 1 7V DS11 2 5V_PRESENT The 2 5V power rail is present above 1 7V DS12 1 8V_PRESENT The 1 8V power rail is present above 1 7V DS13 ATX POK The ATX power supply is generating 5 0V and 3 3V DN8000K10PCIE User Guide www dinigroup com 23 within 5 at the source DS15 SPARTAN_LED3 DS17 SPARTAN_LED2 This LED will flicker when there is Main Bus activity See section X X X DS19 SPARTAN_LED1 This LED will flicker when there is USB activity Bulk Transfer DS20 SPARTAN_LEDO This LED will flicker when there is SmartMedia card activity DS21 1 top MCU_LEDO MCU_LEDJ 1 0 Codes DS21 2 MCU_LED1 01 FPGA A is configuring 10 FPGA B is configuring 11 FPGA C is configuring DS21 3 DS21 4 bottom MCU_LED2 MCU_LED3 The last FPGA configurati
84. fig rd BIT6 BITS_2 DF08 BIT4 FPGA_DONE BIT3 CPLD idle BIT2 SM_SIGNALS DFO09 MCU_XADDR DFOA Address register for upper FLASH SRAM bits MCU_CNTL DFOB Addtess register for upper FLASH SRAM bits FPGA_SELECT DFOC FPGA_ select 5 0 bits 5 0 PPC_RS232_ABSELECT DFOD PPC_RS232_CDSELECT DFOE FPGA_CNTRL DFOF bits 1 0 01 write address 10 data write 11 FPGA_BE DF10 select byte in addr read and data bytes FPGA_RD_DATA DF11 FPGA_WR_DATA DF12 FPGA_ADDR DF13 FPGA_ERROR DF14 GPIF_DATA DF20 GPIF_ERROR DF21 HOLD_DONES DF22 STATES DF23 7 4 GPIF_STATE 3 0 FPGA_STATE FPGA_FREQ_H DF24 FPGA_FREQ_SEL DF25 FPGA_FREQ_L DF26 MCU_STUFFING1 DF27 MCU_STUFFING2 DF28 SERIAL_CLK_CTRL_O DF29 SERIAL_CLK_CTRL_1 DF30 MB80_1_CTRLO DF36 MB80_1_CTRL1 DF37 MB80_2_CTRLO DF38 FPGA_COMMUNICATION DF39 MB80_2_CTRL1 DF40 MB64_1_CTRL DF41 MB64_2_CTRL DF42 MB64_3_CTRL DF43 CPLD_CS_N_CTRL DF44 CPLD_DATA DF45 CPLD_ADDR DF46 GCLK_MSEL_CTRL DF47 DN8000K10PCIE User Guide www dinigroup com 59 FPGA_PH0O_DVAL DF48 FPGA_PH1_DVAL DF49 FPGA_PH2_DVAL DF50 CF_REG_OFFSET DFE NEW_CONFIG_VERSION DFFD NEW_BOARD_VERSION DFFE OLD_BOARD_VERSION DFFF These registers can be written to from the USB interface See USB Software Programmers Guide 4 5 5 USB The Cypress CY7C68013 has a built in USB 2 0 interface The USB type B connector on the DN8000K10PCIE J12 is connected d
85. frequencies provided by their reference crystals The MCU loads the user s desired multiplication M value and division N value into the settings registers in the ICS8442 chip 4 5 3 LEDs The MCU is connected to 4 red LEDs that are visible from outside the PC case when the DN8000K10PCIE is plugged into a PCI slot The LEDs flash a status code during and after configuration All four flashing LEDs means there has been an error configuring at least one FPGA 4 5 4 Memory space The XDATA memory space of the MCU is partitioned into four sections 0x0000 0x1 FFF internal data program memory 0x2000 OxCFFF external SRAM OxDFFO 0x DFFF memory mapped registers no external memory accesses OxE000 OxPFFF reserved by MCU RD WR strobes not active in this region The internal data memory region is mapped to an internal SRAM in the Cypress MCU When the microcontroller code calls memory access from this region the external Address and Data busses are not used After power on reset the MCU reads from the IC Eprom connected to the MCU_EPROM signals and fills this internal memory before allowing the PC to run The code in this section of memory contains core functions of the Dini Group firmware like setting up the interrupt registers communicating with USB and allowing firmware updates The external SRAM is used for heap data The memory mapped register region The DF region contains registers in the Spartan 2 FPGA that control
86. h command line parameters It should not be double clicked from the windows environment A command prompt shortcut is provided in the same directory as Make bat and can be double clicked to open a command prompt window with the proper working directory 4 Getting More Information 4 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Virtex 4 datasheet and a DN8000K10PCIE User Guide 4 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 4 3 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com DN8000K1O0PCIE User Guide www dinigroup com 109 DN8000K10PCIE User Guide www dinigroup com 110 Chapter Ordering Information Part Number DN8000K10PCIE 5 FPGA Options 5 1 FPGAA Select an FPGA part to be supplied in the A position This FPGA is connected to the PCI bus an expansion header and can source global clocks The 12 speed grade is required for full speed operation 1Gbs pair of the interconnect between fpgas NONE LX100 10 11 12 LX160 10 11 12 LX200 10 11 5 2 FPGAB Select an FPGA part to be supplied in the B position This FPGA is connected to an expansion header a memory module socket and can source global clocks The 12 speed grade is required for full speed operation 1Gbs pait of the interconnect between FPGAs NONE L
87. he DN8000K10PCIE DN8000K10PCIE User Guide www dinigroup com 71 XFP power filtering 5 0V a ae VCC50_XFP1 0 5A 4 7uH Tr 0520 C337 0317 O 1uF eur O 1uF 20 TANT VCC33_XFP1 0 750 5 0V c519 case c316 50V u T O 1uF i 0 1uF 2 5V 1 8V 20 Q 2 5V j L7 TANT 1 8V EN a VCC18_XFP1 3 3V 1A Q 3 3V L 4 7uH T c89 4 0594 C619 GND 22uF 0 1uF 10V 0 1uF ll _L 20 STANT Since the DN8000K10PCIE has no negative voltage supply it cannot generate the 5 2V required to supply ECL based optical tranciever modules An auxiliary power connector is supplied to connect to an external voltage supply if ECL signaling is required eo Mounting Holes for 5 2V support XFP L5 U1 VEES_XFP gt rn LVEES_XFP C453 4 7uH 22uF gt C496 10V JMPR DNI TANT 0 1uF 20 7 3 Heat dissipation Virtex 4 FPGAs are capable of drawing incredible amounts of current from their 1 2V and 2 5V power supplies According to Xilinx online power estimator tool a fully utilized FPGA running at 300Mhz can draw more than 30W of power With this much power used in each FPGA the DN8000K10PCIE can dissipate 75 or more Watts of heat For all but the most trivial designs a heatsink must be used with the Virtex 4 FPGA The DN8000K10PCIE comes with a forced air heatsink rated at 2 degrees per Watt Since the maximum operating junction temperature of a Virtex 4 FPGA is 85 degrees as
88. ilities 16 3 RocketlO 10 3 Gbps Transceivers Full duplex serial transceiver SERDES capable of baud rates from 622 Mb s to 10 3 Gb s please reference the Xilinx publication DS302 for speed grade limitations Initial availability is 3 125Gb s Monolithic clock synthesis and clock recovery CDR Fibre Channel 10 Gigabit Ethernet PCI Express 10 Gb Attachment Unit Interface XAUD and Infiniband compliant transceivers DN8000K10PCIE User Guide www dinigroup com 94 INTRODUCTION TO VIRTEX 4 AND ISE e 8 16 32 or 64 bit selectable parallel internal FPGA interface e 8B 10B and 64B 68B encoder and decoder e 50 75 on chip selectable transmit and receive terminations e Programmable comma detection e Channel bonding support two to sixteen channels e Rate matching via insertion deletion characters e Four levels of selectable pre emphasis e Five levels of output differential voltage e Per channel internal loopback modes e 2 5V transceiver supply voltage 16 4 Virtex 4 FPGA Fabric Description of the Virtex 4 Family fabric follows e SelectRAM memory hierarchy o Upto 9 Mb of True Dual Port RAM in 18 Kb block SelectRAM resources o Upto 1 7 Mb of distributed SelectRAM resources o High performance interfaces to external memory e Arithmetic functions o Dedicated 18 bit x 18 bit multiplier blocks o Fast look ahead carry logic chains e Flexible logic resources o Up to 111 232 internal registers latches with Clock Enable o Up
89. ion solution that will work out of the box for most users For special configuration requirements the configuration circuitry is programmable The verilog code for the configureation FPGA and the C code for the microcontroller are both provided on the reference CD The C code for the USB Windows GUI controller program are also included on the User CD 4 2 The Spartan 2 FPGA The configuration circuitry of the DN8000K10PCIE is built around a Xilinx Spartan II Fpga The SelectMap interface of the user FPGAs is connected directly to the general purpose IOs of the Spartan 2 allowing the maximum flexibility of configuration The Spartan 2 also shares connectivity with the three user FPGAs over a 40 bit Main bus allowing fast transfers from a computer to the user design over USB The Spartan 2 FPGA also provides IO expansion for the Cypress Microcontroller The Spartan II FPGA comes preloaded with a core that provides a way to program the Virtex 4 FPGAs over PCI USB and SmartMedia DN8000K10PCIE User Guide www dinigroup com 43 The Spartan FPGA is connected to the Cypress microcontroller s address and data busses and the control registers within the Spartan II FPGA that control FPGA configuration are memory mapped into the MCU s address space 24Mhz CFPGAREQ 73 SYS_CLK 3 LEDs 4 Swit E 2FPGA RS232 7 R5232 Cable RS232 TET e
90. irectly to the USB pins on the Cypress MCU VBUS VBUS_PWR_VALID VS US_PWR 3 9K R249 6 34K J12 VBUS D MCU_USB MCU_USB D GND 3 3V GND SHIELD 2 U28 USBp_OV GND SHIELD E Paes To pve 2 vp i USB TYPE B a 2 2uF USBp_OV 3 ae gt CM1213 01ST SOT23 3 3 3V 0 U27 USBn_OV 2 C620 VP 1 2 2uF USBn_OV 3 CHI VN CM1213 01ST SOT23 3 USB Transient Protection The USB protocol is completed by the Cypress CPU The Cypress recetves a 24Mhz clock from an oscillator X3 The Cypress internally multiplies this clock to 480Mhz for USB 2 0 and 48Mhz for GPIF operation The core runs at 24Mhz along with the external memory interface Communication over this external memory interface is clocked using the MCU_IFCLK signal driven from the MCU at 48Mhz Ihe Spartan communicates over main bus with the Virtex 4 FPGAs using a separate 48Mhz oscillator X1 and distributes this clock to each FPGA including itself DN8000K10PCIE User Guide www dinigroup com 60 MCU 40Mhz 48Mmhz PLL 24Mhz i IFCLK Spartan 2 Memory Mapped 10 48Mhz Main Bus SYS_CLK FPGA A FPGAB FPGA C 4 5 6 Smart media The SmartMedia card socket pins are bussed a
91. k the Main Bus interface MCU clk this reference clock is used by the MCU to generate frequencies required for the USB protocol It is not available to the user UCLK This differential clock input is delivered to FPGA A FBACLK This differential clock is driven from FPGA A and delieverd to FPGA A Band C This clock can be used for controlled clocks odd clock division and multiplication or forwarding a clock from on FPGA to another FBBCLK This differential clock is driven from FPGA B and recived at FPGA A Band C HACLK This differential clock is driven from the daughtercard header A to FPGA A HBCLK This differential clock is driven from the daughtercard header B to FPGA B DDRACLK DDRBCLK This differential clock is driven by the FPGA to its associated DDR2 Sodimm header A copy of the clock is externally buffered and the clock is recived on the FPGA synchronized with its arrival at the SODIMM on the signal DDR_FBCLK 5 1 Global Clocks The three main global clocks are driven by ICS8442 clock synthesizers each capable of producing frequencies of 700Mhz or greater The clock synthesizers can be programmed from a SmartMedia card from the GUI application See Chapter X the USB Application or left at their default values ACLK 100Mhz BCLK 57 2Mhz DCLK 64Mhz DN8000K10PCIE User Guide www dinigroup com 63 Each ICS8442 has an interal multiplication PLL that can operate between 250 and 700 Mhz With 1 2 4 or 8
92. ketIO channels is through the use of SMA cables The SMA connections on the DN8000K10PCIE were designed to operate at the full 11Gb potential of the Virtex 4 RocketlO trancievers DN8000K10PCIE User Guide www dinigroup com 88 J20 CONN_SMA a Rag U10 18 Bank not present in FX 40 Part RIO_SMA_TXp0 AP21 RIO_SMA_RXp0 J21 CONN_SMA ei J22 CONN_SMA 5 i 4 J23 CONN_SMA Rag he s 1 a J16 CONN_SMA an 4 J17 CONN_SMA PE 1 4 J18 CONN_SMA RIO_SMA_TXp1 RIO_SMA_RXn0 RIO_SMA_RXp1 RXPPADA_106 RXNPADA_106 TXPPADA_106 TXNPADA_106 TXPPADB_106 TXNPADB_106 RXPPADB_106 RXNPADB_106 AVCCAUXRXB_106 AVCCAUXRXA_106 AVCCAUXTX_106 8888 AVCCAUXMGT_106 aaa aa qaqqaqa Pe A 0000 AERIS Wirtex 4 FX 1152 OPT LLL FPGA C RocketIO U10 20 AVCCAUXRXA_110 Hans RXPPADA_110 AVCCAUXRXB_110 HAMT RXNPADA_110 AVCCAUXTX_110 ec TXPPADA_110 TXNPADA_110 TXPPADB_110 TXNPADB_110 Figure 41 SMA Connections The loopback pair AP26 and AP25 can be used to test your Virtex 4 fabric design You may want to get the loopback pair working before attempting to transmit high data rates over a cable system DN8000K1OPCIE User Guide RIO_SMA_RXnT RXPPADB_110 RXNPADB_110 0 0 0 GNDA_11 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_11 GNDA_11
93. l trigger the reset signal SYS_RSTn which is monitored by the Spartan FPGA When SYS_RST is asserted the Spartan FPGA resets the Virtex 4 FPGAs causing them to lose their configuration data and deactivate The Spartan also causes a reset on the Microcontroller unit which will cause the microcontroller to reload configuration instructions from the Smart Media card USB contact will be lost with the USB host and the DN8000K10PCIE will have to re enumerate There is a second button S2 called Soft Reset When this button is pressed the signal RESET_FPGAs is asserted This signal is sent to the Virtex 4 FPGAs on a user IO pin and could be used by the user design as a reset signal This signal is also asserted to all FPGAs after any FPGA becomes configured RESET_FPGAs is an asynchronous signal DN8000K10PCIE User Guide www dinigroup com 66 12V 0 1 8V 2 5V 5 0V 3 3V Reset Circuit R359 124R R373 1K U44 3 3V 5 0V 5 0V F 7 43 3V R367 845R R358 oR R371 88 7R R364 1K A370 js 1 28 0K RST SYS_RSTn VREF A360 o N foja R361 100R CRT gl gI 8 8 S z l 2 3 vo 38 ns Ir R372 71 5K 28 0K k I foja 110R biis T R363 100R 2 o 1 R368 E SBR car 6 R357 END 71 5K TC2500 MS0P10 C1018 2 7nF av Vl 3 37 res V2 2 5V s3 Raa f K V3 1 8V v4 ADJ
94. lay Memory in 8 DWORDS per Line Format i Fill Memory with specified DWORD pattern j Toggle Mem Owner INTERNAL User k Interconnect Test Menu q Quit 3 Memory Mapped Data flow All memory mapped transactions in the reference design occur over the MB bus This 40 signal bus connects to all Virtex 4 FPGAs and to the Spartan II configuration FPGA All access to the MB bus is initiated by the Spartan II FPGA when the reference design is in use USB_CLK SYS_CLK RD Spartan MB 34 WR Spartan MB 33 DONE FPGA MB 36 AD 31 0 Bi MB 31 0 ALE Spartan MB 32 VALID FPGA MB 35 PTA PTB PTC PTD PTE PTF DN8000K10PCIE User Guide Www dinigroup com 107 INTRODUCTION TO THE SOFTWARE TOOLS Here is a write USB_CLK SYS_CLK RD Spartan MB 34 WR Spartan MB 33 DONE FPGA MB 36 AD 31 0 Bi MB 31 0 ALE Spartan MB 32 VALID FPGA MB 35 3 1 Compiling the Reference Design This section deals with the source code to the Reference Design which can be found on the CD ROM All file references are with respect to the root directory of the Reference Design soutce code source FPGA Files that are specific to the DN8000K10PCIE design ate found in the DN8000K10PCIE subdirectory whereas general application code is found in the common subdirectory 3 1 1 The Xilinx Embedd
95. le you must increase the differential swing voltage of the MGT transmitter outputs Set TXDAT_TAP_DAC to 800mV u10 17 433V 433V 433V 493V 493V 493V 493V av o co o o o o Virtex 4 FX 1152 OPT XFP1 Connector a Mie ne ee aa S38 VCCAUXRXA 105 een Hk 51K Q 51K Q 51K Q 51K S51K S 51K SEK 51K 3 AVCCAUXTX 105 RXNPADA 105 us AVCCAUXRXB_105 XFP1_MOD_DESEL TD INTERRUPT_N 15 FPI TX DI XFP1_INTERRUPT_N AJ34 _XFPi_REFCLK 18 TX_DIS XFPIIXDIS TXPPADA 105 AK34_ XFPT REFCIKT 17 AD 10 XFP1_SCL TXNPADA_105 RD sc H AREN 4 gt xFP1_sot SDA I XFP1_SDA MS VTTXB_105 2 25 REFCLK 34 VTRXA 105 iaaii 24 REFCLK mon ass H SH 4 XFP1_MOD_ABS SS VTRXB 105 MOD NR H SPORES 4 XFP1_MOD_NR VITKA 105 RX Los Hof en 4 XFP1_RX_LOS Als4_XFP1_TxDp P_DOWN J XFP1_P_DOWN TXPPADB_105 FPTTxDn VEES XFP x TXNPADB 105 M4 ob By go Je ie eve Bw N32 2 79 5 1K AVCCAUXMGT_105 CAGE vecs Hz VCC18_XFP1 Riis XEP1_Rxd CAGE vcc2 RXPPADB _105 AP31 XEPT RuD CAGE vocz H we En en RXNPADB_105 CAGE ps MGTCLK_P_105 CAGE GND j RXFP1 INT RXFP1_Los ZBI MGTCLK N05 989889298988 CAGE no Ha Ben a i N29 pe ten patha yea fan ara CAGE GND 5 rar REMS 333333338 CAGE exo Hg 10 087 wo MGTVREF 105 999999
96. le with the selected text editor notepad by default To change the text editor see Settings Info Menu section b Exit Closes the USBController application 1 1 2 Edit Menu The Edit Menu performs the basic edit commands on the command log in the bottom half of the USBController window 1 1 3 FPGA Configuration Menu The FPGA Configuration Menu has the following options 1 2 3 4 5 Configure via USB individually After selecting this option a window will pop and ask which FPGA you want to configure and then what bitfile you want to configure the selected FPGA with The status of the FPGA configuration will detailed in the log window and the DN8000K10PCIE will be updated after the bitfile has been transferred Configure via USB using file This option allows the user to configure more than one FPGA over USB at a time To use this option you must create a setup file that contains information on which FPGA s should be configured and what bitfiles should be used for each FPGA The file should be in the following format the first character of each line represents which FPGA you want configured a f or A F this letter should be followed by a colon and then the path to the bitfile to use for this FPGA The path to the bitfile is realative to the directory where this setup file is or you can use the full path Below is an example of an accepted setup file A fpga_a bit B fpga_b bit C fpga_c bit Configure via
97. lution 17 1 Foundation Features 17 1 1 Design Entry ISE greatly improves your Time to Market productivity and design quality with robust design entry features ISE provides support for today s most popular methods for design capture including HDL and schematic entry integration of IP cores as well as robust support for reuse of your own IP ISE even includes technology called IP Builder which allows you to capture your own IP and reuse it in other designs ISE s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi Gigabit I O technology ISE also includes a tool called PACE Pinout Area Constraint Editor which includes a front end pin assignment editor a design hierarchy browser and an area constraint editor By using PACE designers are able to observe and describe information regarding the connectivity and resource requirements of a design resource layout of a target FPGA and the mapping of the design onto the FPGA via location area This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design 17 1 2 Synthesis Synthesis is one of the most essential steps in your design methodology It takes your conceptual Hardware Description Language HDL design definition and generates the logical or physical DN8000K10PCIE User Guide www dinigroup com 97 INTRODUCTION TO VIRTEX 4 AND ISE representation for the targe
98. mong the Cypress MCU GPIF pins the Spartan 2 FPGA IOs and the SmartMedia card socket After reset the MCU uses this connection to look for and read the contents of the file main txt on the SmartMedia card The main txt file contains instructions for configuring the user design into the three Virtex 4 FPGAs After reading the configuration instructions the MCU reads the headers of the user s FPGA design bit files and verifies that they target the correct type of FPGA that are installed on yout DN8000K10PCIE This will prevent damage to the FPGA from an incorrect or corrupt bit file This behavior can be turned off If this check is passed MCU uses its memory mapped interface with the Spartanll to instruct the SpartanII to read the SmartMedia card and configure the Virtex 4 FPGAs over SelectMap bus 5 Clocking The clocking circuitry on the DN8000K10PCIE is designed for high speed operation The flexible clock design should meet the most difficult clocking needs allowing 8 totally asynchronous controllable clock sources for each FPGA All clocks operating above 100Mhz are fully differential LVDS signaled low skew low jitter clocks DN8000K10PCIE User Guide www dinigroup com 61
99. n and the DONE light will not glow The DN8000K10PCIE microcontroller also checks the design files you send to make sure they are compiled for the FPGAs that are installed on your board If they are not then the microcontroller unit halts the configuration process As a result when the DONE light goes on you will know that the configuration process was successful 4 5 MCU The operation of the Spartan II is monitored and controlled by a Cypress CY7C68013 microcontroller The microcontroller also has a USB 2 0 interface that can be used to monitor the board control configuration or transfer data to and from the user FPGA design Basic operation can be controlled over an RS232 link from a computer terminal 4 5 1 RS232 The primary method of user interaction with the DN8000K10PCIE configuration circuitry is the MCU s RS232 port P2 The Cypress CY7C68013 has two RS232 pins that are buffered through a 12V voltage translation buffer for use with a standard computer serial port DN8000K10PCIE User Guide www dinigroup com 55 PPC RS232 Interface MCU and A I RS232 ppc RS232_TXD3 RS232_TXD4 RS232_TX_S MOCU_TX RS232_RX_S RS232_RXD3 MCU_RX RS232_RXD4 GND Figure 29 RS232 Buffer and Headers The RS232 port will be able to communicate with a standard PC serial port set to 19200 baud 8 data bits no parity no handshaking When you connect a computer terminal to the po
100. n the DN8000K10PCIE reference design is loaded For more information on how the MCU communicates with the reference design see Chapeter X The Reference Design Figure 5 RS232 Output You should see the DN8000K10PCIE MCU main menu If the reference design is loaded in the Virtex 4 FPGAs then you should see the above on your terminal Try pressing 3 to see see if the configration circuit was successful in programming the FPGAs ENTER SELECTION 3 KKK KKK KKK KKK KKK KKKEKK CONFIGURATION STATUS KKK KKK KKK KKK KKK KEK FPGA B NOT configured The easiest way to verify your FPGAs are configured is to look at DS18 DS14 DS16 located above each FPGA When the green LEDs are lit the FPGA under it is successfully configured DN8000K10PCIE User Guide www dinigroup com 19 3 5 2 Interactive configuration If you want to put multiple designs on a single Smart Media card you can use the interactive configuration menu to select which bit file to use on each FPGAs Select menu option 2 ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 3 Enable sanity check for bit files M Main Menu Enter Selection Figure 6 Interactive Config Menu 3 5 3 Read temperature sensors The DN8000K10PCIE is equipped with temperature sensors to measure and monitor the temperature on the die of the Virtex 4 FPGAs According to the Virtex 4 d
101. on was successful Blinking There was a configuration error Use the RS232 port to read the error Off Configuring On The last configuration command was successful DS24 SPARTAN_DONE The Spartan 2 configuration FPGA is configured This light will turn off if the board is in power reset DN8000K10PCIE User Guide www dinigroup com 24 DS18 FPGA_A DONE The Virtex 4 FPGA A is configured DS14 FPGA_B_ DONE The Virtex 4 FPGA B is configured DS16 FPGA_C_DONE The Virtex 4 FPGA C is configured DS8 SFP2_ LOS SFP module 2 Loss of signal DS4 SFP2_FAULT SFP module 2 transmitter fault DS5 XFP2_INT XFP module 2 error DS1 XFP2_FAULT XFP module 2 transmitter fault DS6 SFP1_LOS SFP module 1 Loss of signal DS2 SFP1_FAULT SFP module 1 transmitter fault DS7 XFP1_INT XFP module 1 error DS3 XFP1_LOS XFP module 1 Loss of signal DS48 DS47 DS46 DS45 User LEDs from FPGA C DS44 DS43 DS42 DS41 DS40 DS39 DS38 DS37 User LEDs from FPGA A DS36 DS35 DS34 DS33 DS32 DS31 DS30 DS29 User LEDs from FPGA A D828 DS27 DS26 DS25 Figure 10 DN8000K10PCIE LEDs DN8000K10PCIE User Guide www dinigroup com 25 4 Using the Reference Design with the Provided Software To communicate with the reference design on the DN8000k10PCIE you should use the USB interface The USB interface allows configuration of the FPGAs and bulk d
102. p to 3A of the required 0 9V termination power rail along with a stable 0 9V reference voltage supply 7 2 2 RocketlO power wigs CC MGT12_top FBI0 R34 RXPPADA_103 AVCCAUXRXA_103 IS eeM NGG N A 08 r Eu FB17 g J 00 MaT 2 top RXNPADA 103 AVCCAUXAXB 103 733 VCC MGT 3103 vce menz S10 AVCCAUXTX_103 T O v34 c26 c o Was TXPPADA_103 Rees W34 TXNPADA_103 iga veo_Mar s FB15 AB34 VCC MGTIS 1 103 VCC_MGTIS 1 103 VTRXB_103 733 CC MOTIS 2 103 MOTIS 2105 VETKA_103 Ass CC MOTIS 3 103 CC MOTIS 3103 D c28 VTTXB_103 ga VCC MOTIS 4103 c25 FB12 0 22uF eb VTRXA 103 car Faia o2ur Raga TXPPADB_103 c24 Fett 0 22uF AASA TXNPADB_103 GBur vec MGT25 ACH RXPPADB 103 94 RXNPADB_103 AVCCAUXMGT_103 AC33 VCC MGT25 1 103 FB16 VCC _MGT25 rt 833333 PEN 888846 222222 550585 Viren 4 FX 1152 ii asjale 1 21V 42 5V 3A ig VCC_MGT12_top 1 8V tw 5 vrower vout Sag T T ce 1 vcontro 7 Sores 2 c301 300 cag c52 c51 c53 c50 c312 ee sl 150uF 150uF 2 2UF 2 2UF 2 2uF 2 2uF 2 2uF 2 2UF 20 6 3V 6 3V c54 TANT 10V T158000 R21 20 20 20 100R TANT TANT TANT s 4 4 4 4 4 Five linear rails 7 2 3 Optical Module Power Optional optical modules have a variety of power supply requirements most of which are met by t
103. r I Pead Protect r Vitew st Honufecturer INFO INPACT 1777 Reading C Xi linx 1 xc18v00 dat INFO iMPACT 501 2 Added Den done Validating chain zy scan chain validated s PROGRESS_END End Operation Elapsed tine 0 sec Device 1 selected Device 2 selected Device 1 selected set ttribute position 1 attr devicePartNane value xclv02 u setAttribute position 1 attr configFilelone value blackhorseP DiniProd DN500015 1 Loading file SSblackhorse F DiniProd DN5000121 Scurce Conf igFPGANIHPLEHENT pron acs done Device 1 selected Figure 18 Impact Window To program the prom Right click on the prom and select Program from the popup menu In the options dialog that follows the options Erase before programming should be selected and Verify should be deselected Press OK The programming process takes about 35 seconds over the parallel port Power cycle the DN8000K10PCIE The new firmware is now loaded You can close impact and disconnect the Parallel IV cable DN8000K10PCIE User Guide www dinigroup com 39 Chapter Hardware 3 Overview The DN8000K10PCIE was designed to maximize the number of useful gates in your emulation project running at speed by providing the densest interconnect possible To achieve this goal the DN8000K10PCIE is equipped with the highest capacity FPGAs available today the Xilinx Virtex 4 LX200 The FPGAs on the DN8000K10PCIE are in the largest 151
104. rapidly with in system debug at system speeds Together these capabilities usher in the next programmable logic revolution 16 1 Summary of Virtex 4 Features The Virtex 4 has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs e High performance FPGA solution including o Up to Sixteen RocketIOTM embedded multi gigabit transceiver blocks based on Mindspeed s SkyRail technology o Two IBM PowerPC RISC processor blocks DN8000K10PCIE User Guide www dinigroup com 93 INTRODUCTION TO VIRTEX 4 AND ISE Based on Virtex 4 FPGA technology o Flexible logic resources up to 200 448 Logic Cells o SRAM based in system configuration o SelectRAM memory hierarchy o Up to 556 Dedicated 18 bit x 18 bit multiplier blocks o High performance clock management circuitry o SelectIOTM Ultra technology o Digitally Controlled Impedance DCI 1 O 16 2 PowerPC 405 Core Embedded 300 MHz Harvard architecture core Low power consumption 0 9 mW MHz Five stage data path pipeline Hardware multiply divide unit Thirty two 32 bit general purpose registers 16 KB two way set associative instruction cache 16 KB two way set associative data cache Memory Management Unit MMU o 64entry unified Translation Look aside Buffers TLB o Variable page sizes 1 KB to 16 MB Dedicated on chip memory OCM interface Supports IBM CoreConnect bus architecture Debug and trace support Timer fac
105. rmware cannot be updated unless the board is put in firmware update mode during power on Find Switch block 1 on the DN8000K10PCIE DN8000K10PCIE User Guide www dinigroup com 35 a om i r r T r Figure 15 Switchblock 1 Move switch S1 3 to the ON position Power on the DN8000K10PCIE Open the USB Contoller program If the DN8000K10PCIE powered on in firmware update mode there will be an Update Flash button near the top of the USB Controller window Click on this button www dinigroup com 36 DN8000K10PCIE User Guide W DiNi Products USB Controller Settings Info Clear Log Maximum packet size is 0x00000200 512 MCU FLASH VERSION Ox4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION Oxa USB to fpga communieatsen enabled Maximum packet size is 0x00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION Oxa Figure 16 USB Controller Firmware Update Mode When the Open dialog box appears navigate to the Firmware image file supplied by Dini Group The file name should be flash_flp hex Press OK The USB Controller should freeze for about 10 seconds while the firmware update is taking place When the download is complete the Log window should print Update Complete Move Switchblock 1 3 to the OFF position to put the DN8000K10PCIE back into normal operation mode Power cy
106. rt and power on the DN8000K10PCIE the firmware loaded on the microcontroller unit will display a menu on the terminal This menu will allow you to control the basic configuration options of the DN8000K10PCIE including configuration clock frequencies and the Virtex 4 FPGA RS232 ports 4 5 2 Clocks The Cypress CY7C68013 is also responsible for configuring the global clocks and RocketlO clock of the DN8000K10PCIE The Cypress CY7C68013 MCU treads the file main txt from the SmartMedia card in the socket J24 and follows the users clock configuration commands U20 ACRYS ACLKI 24 TALI EouTo Hi wk C852 18pF e 25 xraL2 gour Hs T 25MHz 3 FOUTI X 9 ACLKTEST TP11 C934 18pF ACRYSn 30 M1 TEST 4 x ms 7 ACLK Nc x x 21 no generator HY x test clk DH xTAL_SEL 24 vco SEL ACLK_SCLK ACLK SCLK 18 soLk vopa 215 ALLCLK SDATA 19 ALLCLK_SDATA 18 SDATA ALLCLK_SLOAD SLOAD R281 PLOAD ALLCLK_SRST 1K ALLCLK_ SRST 17 RST 7844 GND vec bag GND vec I CS8442 LOFP32 Figure 30 8442 Clock synthesizer The 3 ICS8442 clock synthesizers on the DN8000K10PCIE used for generating the global clocks ACLK BCLK and DCLK share a serial configuration bus connected to the MCU to DN8000K10PCIE User Guide www dinigroup com 56 program them The ICS8442 frequency synthesizers are capable of multiplying and dividing the reference
107. s command is executed lt yn gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt yn gt to n Encrypting bit files is not supported or recommended by Dini Group Previous revisions of Xilinx parts have been vulnerable to permanent damage caused by bugs in the encryption circuitry MAIN BUS 0x lt WORDADDR gt 0x lt WORDDATA gt Writes data in lt WORDDATA gt to the address on the main bus interface at lt WORDADDR gt This command only makes sense in the context of the Dini Group reference design unless your design implements a compatible controller on the main bus pins See Appendix Pins Other The Specification for this interface is in the Referece Design Chapter CONFIG REG 0x lt SHORTADDR gt Ox lt BYTE gt Writes to an address in the MCU XDATA memory space RS232 lt port gt lt fpga gt The RS232 port P1 will be controlled by the FPGA lt fpga gt if lt port gt is 1 CLOCK FREQUENCY lt clockname gt N lt number gt M lt number gt Figure 28 Main txt Commands DN3000K1O0PCIE User Guide The MCU will adjust the clock synthesizer producing clock lt clockname gt to multiply it s reference frequency by lt M gt and divide it by lt N gt Note that the clock synthesizers have a limited bandwidth and for clocks A B and D the reference frequency M must fall in the range 250Mhz 700Mhz For clock 2 RocketIO reference M must fall betwe
108. sert the SmartMedia card into a card reader provided and connect it to a PC Create a file on the root directory of the card and call it Main txt In main txt write a series of configuration commands separated each by a new line A valid command is one of the following lt comment gt FPGA A lt filename gt FPGA B lt filename gt FPGA C lt filename gt CLOCK FREQUENCY lt clockname gt N lt number gt M lt number gt SANITY CHECK lt yn gt VERBOSE LEVEL Jevel gt RS232 lt portnumer gt lt fpganame gt CONFIG REG 0x lt SHORTADDR gt O0x lt BYTE gt MAIN BUS 0x lt WORDADDR gt 0x lt WORDDATA gt lt comment gt can be any string of characters except for newline lt filename gt can be the name of a file on the root directory of the SmartMedia Card lt number gt can be any one or two digit positive integer in decimal lt clockname gt can be A B D 2 A is ACLK B is BCLK D is DCLK and 2 is the RocketlO clock synthesizer lt yn gt can be the letter y or the letter n lt level gt can be 0 1 2 or 3 lt portnumber gt can be 1 2 3 or 4 The DN8000K10PCle only has 1 user RS232 port 1 so 2 4 will cause no operation lt fpganame gt can be A B C D E F G H I The DN8000K10PCIE only has 3 fpgas A B C so D I will cause the RS232 port to not function lt SHORTADDR gt is a 2 digit hex number 16 bits DN8000K10PCIE User Guide www dinigroup com 49 lt BYTE gt is a 1 digit hex number 8 bits
109. signaling are still possible on the DN8000K10PCIE you are not required to use highspeed serial design techniques Single ended interconnect is recommended for signaling below 133Mhz Because of the DN8000K10PCIE s excellent low skew clocking network global synchronous clocking should work fine for your interconnect at speeds lower than 300Mhz The source synchronous clock signals can also be used as single ended or differential interconnect or to forward clocks from one FPGA to another The total interconnect counts between FPGAs e A B378 e B C154 e A C 164 9 Memory interface There are two standard 200 pin DDR2 SODIMM module sockets on the DN8000K10PCIE These sockets are supplied with 1 8V power and keyed for use with DDR2 SDRAMs One socket is connected to FPGA B and the other is connected to FPGA C DN8000K10PCIE User Guide www dinigroup com 74 9 1 Clocking DIMM_VTT place near u54 DDR Buffer R296 475R R297 475R our 0937 u37 DDRB_PLL_CkKOUTp J DDRB PLL CKp 4 38 DDRB_PLL CKOUTR 17 DORB PLLCRn 5 ck Yo 37 IT CKn Yon E C938 21 39 Suk 2z OS yi HE A OE yin 28 ve BE 22 vona van 25 31 vona a A ex a ala ole sie H vona ve eo sel sel ziel olel ac ele alo g vopa Yan a9 SIS S SIS 28 S6 SIs SE Sh T Vona Ai an i y a hc ee e a e pa e aT a W
110. ss accesses of the MCU The Configuration FPGA is programmed to respond to accesses in the XDATA address space in the address range of OxDF00 to OxDFFF Communication over the MCU memory bus to the Config FPGA is synchronized to the 24Mhz MCU_CLK X3 For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual MCU 40Mhz agninz PLL 24Mhz IFCLK Spartan 2 Memory Mapped 10 48Mhz Main Bus SYS_CLK FPGA A FPGAB FPGA C The following registers implemented in the Configuration FPGA are accessible as part of the MCU s XDATA address space Register Name XDATA Description Address DATA DFO00 Used when reading from SM but not configuring COMMAND DF01 Commands for the SM DN8000K10PCIE User Guide www dinigroup com 58 ROW_LADDR DFO2 Holds lower 8 bits of SM address ROW_HADDR DFO3 Holds upper 8 bits of SM address ROW_XADDR DF04 Holds extra bits of SM address NUM_BYTES_0 DF05 Holds lower 8 bits of the number of bytes to read NUM_BYTES_1 DF06 Holds upper bits of number of bytes to read in BITS_1 DFO07 BIT7 mcu_fpga_con
111. suming an ambient temperature of 50 degrees the inside of your computer case the most amount of energy dissipated by the FPGA using the standard fan is 85 30 2 27 5W This should be sufficient for most applications If you intend to operate the Virtex 4 FPGA at very high speeds or are getting overheating issues with your design you will need to install a larger heatsink DN8000K10PCIE User Guide ww w dinigroup com 72 U11 1 Virtex 4 LX 1513 cc k PY22n HI HSWAPEN PROGRAM_B Her INIT Fyq7 O cS B HgO Y21 DONE yra O H pwRown_B RDWR_B anzi Y23 DOUT_BUSY Oy37 Mo Oyz M1 Yi6 chs me pun Fo 24 VBArt Tus Aa TCK 17 ABI AAI vcco_o TDI baste 43 3V I Vecozo tbo ABI Oo vcco_0o ra FF R165 1K H20 H19 U4 STBY vec MI TEMPA_STBY FPGA DXP A ies 14 1C_SCL SMBCLK bs IC_SDA 12 3 C280 C428 IIC_SDA SMEDATAN DE Ira 1100pF 1000pF ic IRA IIC_IRQn 11 PN ran lt rar ALERT rpcA_oxn A TEMPA_SAO 1 TEMPA SAT 15 ADDO NC 5X Riga ADD NC 78 amp 1K R167 7 NC Tig 1K 5 GND No 45 GND Nc H x MAX1617A QSOP16 Above The FPGA temperature monitor circuit The MAX1617 s IIC bus is connected to the Cypress MCU 5 0V O Cooling Fan Above Colling fan power connector 8 FPGA interconnect The DN8000K10PCIE was designed to maximize the amount of interconnect between the two primary Virtex 4 FPGAs A
112. ted silicon device A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time To meet this requirement the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device In addition cross probing between the physical design report and the HDL design code will further enhance the turnaround time Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics Synopsys and Synplicity You can use the synthesis engine of your choice In addition ISE includes Xilinx proprietary synthesis technology XST You have options to use multiple synthesis engines to obtain the best optimized result of your programmable logic design 17 1 3 Implementation and Configuration Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically been used to describe the implementation process for FPGA devices and fitting has been used for CPLDs Implementation is followed by device configuration where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device To ensure designers get their product to market q
113. tepping multiplication division or distributing a clock to which only one FPGA has access like a header clock or the user clock input FPGA A has 6 feedback outputs one differential pair to each Virtex 4 FPGA FBACLKAp FBACLKAn FBACLKBp FBACLKBn FBACLKCp FBACLKCn FPGA B has 6 feedback outputs one differential pair to each Virtex 4 FPGA DN8000K10PCIE User Guide www dinigroup com 65 FBBCLKAp FBBCLKAn FBBCLKBp FBBCLKBn FBBCLKCp FBBCLKCn For the pad site locations of the inputs and outputs see Appendix X FPGA pins Clocks can also be exchanged from one FPGA to another on the source Synchronous clock inputs See Chapter X Section X FPGA interconnect 6 Reset Topology The DN8000K10PCIE is protected from undervoltage and over temperature by a reset circuit When the board powers on a voltage monitor waits until all voltages are above their minimum voltage levels then deasserts reset The Spartan 2 distributes the reset signal to all FPGAs and the Microcontroller unit so until the Spartan 2 is configured reset remains asserted NIC Temperature Monitors 85 deg C i FPGAA FPGA A 7 lt PROG Soft PROG DE SENeNnenz Reset PROG u x NINE Spartan II FPGA md aa V rm73 Hard g Voltage Monitor FPGAA Reset RESET_FGPAS N RESET je The user may also assert reset by pressing S3 Hard reset This wil
114. the Spartan 2 FPGA The Spartan 2 FPGA has one RX and one TX signal connected to each Virtex 4 FPGA The Spartan FPGA will multiplex the RX and TX signals to the Virtex FPGAs to the RS232 header P1 The Spartan 2 internally multiplexes the signals on the user RS232 header P1 to one of these three sets of signals To change the Virtex 4 FPGA that has access to the RS232 headers you can use the provided USB application program or you can change the setting on a terminal connected to the Microcontroller unit s RS232 port P2 Since RS232 uses a 12V signal levels the RS232 signals from the SpartanII are first buffered through a voltage translation buffer shown below RS232 ppe u2 Pi 7 21 RS232_TXD3 1 2 RS232_TX_S TIIN TIOUT R5232 TXD oY TaN T30uT Hx 3 S ox x RS232_RX_S 134 Rtour run HS an x 10 MCU_RX R2OUT R2IN gt 10 16 GND x24 tout un HE __ F ah RS232 MCU x H swour swn H5 __ 24 P2 c2 0 1uF meS SHDA 1 2 1 23 Ss 4 Hc vec 2 4 C1 14 7 ae C2 v Ha x x C2 3 x x c1 O 1uF P ale 22 v Ka ne AX338BE TSOP24 Figure 23 RS232 buffer On the back side of the DN8000K10PCIE there are two duplicate RS232 ports P7 and P8 that can be used if an installed daughter card is covering the headers on the front These duplicate headers are not installed by default but can be installed on req
115. ting Off setting Position S1 4 Off Reserved DN8000K10PCIE User Guide www dinigroup com 13 3 2 Memory and heatsinks There should be an active heatsink installed on each FPGA on the DN8000K10PCIE and a fan over the power supply units Virtex 4 FPGAs are capable of dissipating 15W or more so you should always run them with heatsinks installed The DN8000K10PCIE comes packaged without memory installed If you want the Dini Group reference design to test your memory modules you can install them now in the 1 8V DDR2 DIMM sockets L nmm t ongoogciopci ky THE ONI CEIP LA JOLLA NE Figure 4 FPGA Names The socket DIMMB is connected to FPGA B The socket can accept any capacity DDR2 Sodimm module Note that DDR1 modules will not work in these slots since they are supplied with 1 8V power and DDR1 requires 2 5V power and a completely different pin out 3 3 Prepare configration files The DN8000K10PCIE reads FPGA configuration data from a SmartMedia card To program the FPGAs on the DN8000K10PCIE FPGA design files with a bit file extension put on the root directoty of the SmartMedia card file using the provided usb card reader The DN8000K10PCIE ships with a 32 MB SmartMedia card preloaded with the Dini Group reference design DN8000K10PCIE User Guide www dinigroup com 14 1 Insert the provided SmartMedia card labeled Reference Design into your usb card reader Make sure the card
116. tions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ Figure 2 Support Resources The download section of the web page contains a document called DN8000K10PCIE Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Messages prompts and speed grade program files that the system 100 displays Courier bold Literal commands that you ngdbuild enter in a syntactical statement design_name DN8000K10PCIE User Guide www dinigroup com Convention Meaning or Use Example Garamond bold Italic font Commands that you select from a menu File gt Open Keyboard shortcuts Variables in a syntax statement for which you must supply values Ctrl C ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Braces An optional entry or parameter However
117. uF 49 9R 49 9R Virtex 4 FX 1152 OPT OSC3_3 3VREG NEAR FPGA NEAR OSCILLATOR OSC3_3 3VFILT FB102 NL FOR EG 2101CA R419 10 0K R421 1K NOTE VC 1 4V IS O PPM PULL R422 R423 w 100R 100R osc3_vc 1 6 OE vec OSC3_PU 2 ve sur OSC3 Yn L 3 ano aun OSC3_Yp ll EG 2101CA 250Mhz R426 R427 U10 17 88 7R 88 7R C1053 0 01uF AP29 rt MGTCLK_P_105 BEZE MGTCLK_N_105 C1054 R428 R429 0 01uF 49 9R 49 9R Vinex 4 FX 1752 OPT Figure 36 MGT PECL Oscillators There are two Epson2101CA SAW oscillators U51 and U48 Each one drives a MGTCLK on to one side of the The 1CS843020 01 Frequency Synthesizer is a very low phase noise With the default 25Mhz oscillator the frequency synthesizer is capable of producing frequencies in the ranges 71 875 84 375 143 75 168 75 287 5 337 5 and 575 675 Mhz 12 2 MGT Power network The RocketIO strict power supply constraints require the use of heavy power supply filtering The RocketIO s three power rails are each generated by a linear voltage regulator 12 2 1 FX CES2 rework If your DN8000K10PCIE came with the option FPGA C FX60CES2 then a late breaking Virtex 4 erratum required the following rework This rework is not shown in Appendix X Schematic DN8000K10PCIE User Guide www dinigroup com 83 VCG_MGT12_top o 1 21V 2 5V 1
118. uest They are compatible with a surface mount 5x2 0 1 header DN8000K10PCIE User Guide www dinigroup com 46 4 2 5 IIC There is a single IIC bus on the DN8000K10PCIE connecting all IIC enabled chips on the board On this bus are three MAX1617A temperature sensing chips U3 U4 U24 two DDR2 SODIMM sockets and a serial eprom The temperature sensors on the IIC bus are polled about once per second by the MCU to read the temperature of each FPGA 4 3 Configuration Options The DN8000K10PCIE allows FPGA configuration from any of four methods When a Virtex 4 FPGA is configured the DONE pin on the FPGA is pulled high The DN8000K10PCIE has a green LED attached to the DONE signal of each to indicate the state of the DONE pin on the three Virtex 4 FPGAs and on the SpartanlI configuration FPGA 3 3V 0 R169 120R IRFPGAA_DONE 2 5V Q DS18 x R17 1K JQFPGAA_DONE ER Q3 a BSS138 FPGA_DONE A FPGA_DONE_A lt _ gt Pg11 Figure 24 DONE LEDs 4 3 1 Jtag Jtag is the only configuration method on the DN8000K10PCIE that does not use the Virtex 4 SelectMap configuration interface When programming the user FPGAs over a JTAG cable plugged into J13 the DN8000K10PCIE configuration circuitry is not used A JTAG connection is required to use some Xilinx configuration tools like ChipScope and readback from Impact Also this header can be used with Synplicity s Identify Configuration over JTAG
119. uickly Xilinx ISE software provides several key technologies required for design implementation e Ultra fast runtimes enable multiple turns per day e ProActive Timing Closure drives high performance results e Timing driven place and route combined with push button ease e Incremental Design e Macro Builder 17 1 4 Board Level Integration Xilinx understands the critical issues such as complex board layout signal integrity high speed bus interface high performance I O bandwidth and electromagnetic interference for system level designers To ease the system level designers challenge ISE provides support to all Xilinx leading FPGA technologies e System IO e XCITE DN8000K10PCIE User Guide www dinigroup com 98 INTRODUCTION TO VIRTEX 4 AND ISE e Digital clock management for system timing e EMI control management for electromagnetic interference To really help you ensure your programmable logic design works in context of your entire system Xilinx provides complete pin configurations packaging information tips on signal integration and various simulation models for your board level verification including e IBIS models e HSPICE models e STAMP models 18 Virtex 4 Developer s Kit V2PDK is the Virtex 4 Developer s Kit and is included to provide an existing framework of hardware and software code to explore the capabilities of the Virtex 4 as well as a basis to build new systems A wide variety of soft
120. ware and hardware tools are used to build a Virtex 4 design V2PDK The design flow is a tool chain methodology that exists to simplify the entire design process by providing integration between the tools and automating tasks The main focus of the design flow is integrating the programs with each other to accomplish the system design The system design process can be loosely divided into the following tasks e Builds the software application e Simulates the hardware description e Simulates the hardware with the software application e Simulates the hardware into the FPGA using the software application in on chip memory e Runs timing simulation e Configures the bitstream for the FPGA DN8000K10PCIE User Guide www dinigroup com 99 INTRODUCTION TO VIRTEX 4 AND ISE 19 Helpful Hints Make sure that the clock your design uses is running gt Check the pinout in your constraint file Check the PAR report file to gt make sure that 100 of your IOBs used have LOC constraints Use the PAD report to make sure your constraints were applied correctly Double check that the connections match between your FPGA pins and the daughtercard pins Make sure that none of the other FPGAs are driving those MB pins Check for logic in your source code and make sure that the Unused IOBs option in the ISE settings is set to Float If it is set to Pulldown then those FPGAs ate driving any pin that is not assigned in the source code If the conn
121. ww dinigroup com 81 3 3V 3 3V CABLE_COUTOn CABLE COUTOp R443 R444 R445 R446 100R 100R 100R 100R CABLE_COUTO U10 15 38 u31 TL c671 13pF 24 14 C1046 i e p TAL FOUTO 75 T 0 01uF 3 7 FOUTO 4 Nia MGTCLK_P_102 5 6 _ 25 11 R447 R448 R449 R450 N34 P 7 8 fa erate EQUT 2 88 7R 88 7R 88 7R 88 7R MGTCLI_N_102 9 10 28 FOL C1047 MO 9 0 01uF 11 12 C850 j 13pF e 20 MO der 13 14 R77 I a 30 M2 P3 3VAFXO Ai 15 16 1001 u34 499R 5mh Bar Me I Liz is Suen Fanta R61 araz Me N 19 20 ze Fein R415 T Virtex 4 FX 1152 OPT T B ser ih me 25 26 T 33V DIN BAUT P3 3VAFXO 4 Me Petr ed Ra5P 2 R452 R453 R454 27 28 P3 3VAEXO ee Ns 49 9R Y 49 9R 49 925 49 9R r so 1 veo ano H x n 31 32 R62 R231 R416 dioe 33 34 49 9R PISOLV179W R255 1K 23 1K TEST_CLK 3 24 1 100_XTALSEL 2 e as ale taii TEF RIO0_VCOSEL XTAL_SEL 39 40 27 bee BEI 0 01UF 41 42 lt FB72 J1 Hkr MaToLk P 113 t 43 i 7 RCLK2_SCLK Borie SELE 2 SCLK vopa 21 O m K1 MGTCLK N1113 x AICI ODATA a a SATA P3 3VAFXO C1045 Ar p3 avarxo ALLCLK_SLOAD ORT SLOAD E el R244 TK PLOAD HEADER 23x2 ALLCLK srst gt ALLOLK SRST 12l sare P3 3VAFXO S H onp voc H2 10R
122. x division on the output the possible output frequencies are 31 25 700Mhz VCO_SEL can be used to disable the PLL so ACLK BCLK and DCLK can operate at their fundamental 25Mhz 14 3Mhz and 16Mhz respectively The Serial configuration bus is connected to the Cypress MCU GPIF pins and controlled through software The crystal inputs are parallel resonant fundamental mode DCLK generator 341 160 181 T 100R u26 U6 14 DCLKA poLK g pa oom S BEKA ea 22 TALI zouro H CRS 424 cik nao FS a DELKAn PF 16 0Mhz FOUTO nCLK 12 DCLKB at DCLKB C455 18pF 4 AE cours Ht at at 7 DLKB ae Four Hx TP7 DCLKC j e Mo 9 DCLKTEST a Hi DCLKC RY MI TEST 1 Pr na2 DCLKCn Sa M3 a OE z x ma wE SH ms a3 Ha Em 3 3V 6 To xy m ao FPGA x ms ie Pe GAs xE ne 20 ved 4 ah 17 Vdd as pg x H n 0379 Vdd nQ5 o x test_cik OsuF a ale u 3 3V_R179 1K 22 5 GND nos o SS ZT KTALL BEL GND 24 x vco SEL o7 34 5 z nor F DCLK_SCLK 784 sc k vopa Ho ALLCLK_SDATA 20 SDATA ALLCLKSLOAD ra 6 S189 R180 ALLCLK_SRST gt l psy o 784 GND vec Hjo GND vec Ha OSBAA2LGFP3Z The 8442 outputs are connected to a 1 8 LVDS buffer and distributed to the FPGAs Aclk and Belk are also distributed to the expansion headers as well DN8000K10PCIE User Guide www dinigroup com 64 For the input pad sites used for accessing the global clocks

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