Z80 CPU User's Manual
Contents
1. Table 3 16 Bit Load Group LD to ourc PUSH op and POP op Source Register Imm Ext Ext Addr Reg Indir Register BC DE HL SP IX IY m nn SP AF BC DE HL SP DD FD F9 F9 IX n n n n IY FD FD FD 21 2A El n n n n EXT nn ED ED ED DD FD ADDR 43 53 73 22 22 n n n n n n n n n n PUSH REG SP DD FD Instructions gt IND E6 E6 NOTE The Push amp Pop instruction adjust the SP after every execution POP UM008003 1202 Z80 CPU Instruction Description Instructions 55 58 280 CPU User s Manual Z 2 E oe Table 5 Block Transfer Group Destination Source Reg Indir DE Reg Indir HL ED A0 LDI Load DE HL Inc HL and DE Dec BC ED BO LDIR Load DE HL Inc HL and DE Dec BC Repeat until BC 0 ED A8 LDD Load DE HL Inc HL and DE Dec BC ED B8 LDDR Load DE gt HL Dec HL and DE Dec BC Repeat until BC 0 Table 6 Block Search Group Search Location Reg Indir HL Note Reg HL points to source Reg DE points to destination Reg BC is byte counter ED Al CPI Inc HL Dec BC ED Bl CPRI Inc HL Dec BC Repeat until BC 0 or find match ED A9 WD Dec HL and BC ED B9 CPDR Dec HL and BC Repeat until BC 0 or find matc2. During a read I O operation the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read For I O write operations the WR line is used as a clock to the I O port UM008003 1202 Overview Z80 CPU User s Manual ziLo G 15 asza AC ems Automatically inserted WAIT state Figure 7 Input or Output Cycles Bus Request Acknowledge Cycle Figure 8 illustrates the timing for a Bus Request Acknowledge cycle The BUSREQ signal is sampled by the CPU with the rising edge of the last clock period of any machine cycle Ifthe BUSREO signal is active the CPU sets its address data and tristate control signals to the high impedance state with the rising edge of the next clock pulse At that time any external device can control the buses to transfer data between memory and I O devices This operation is generally known as Direct Memory Access DMA using cycle stealing The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external controller can maintain control of the bus for as many clock cycles as is required If very long DMA cycles are used and dynamic memories are used the external controller also performs the refresh function This situation only occurs if very large blocks of data UM008003 1202 Overview 280 CPU User s Manual 16 Zt Og are transferred under DMA control During a bus reguest cycle the CPU cannot be interr
3. Y d A B IC D HL ADD ADD W CARRY ADC SUBTRACT SUB SUB w CARR SBC AND XOR UM008003 1202 Z80 CPU Instruction Description UM008003 1202 Z80 CPU User s Manual Z ZiLOG Table 7 8 Bit Arithmetic and Logic Source Register Addressing Reg Indir Indexed Immed OR DD FD B6 B6 d d COMPARE DD FD CP BE BE d d INCREMENT DD FD INC 34 34 d d DECREMENT DD FD DEC 35 35 d d Table 8 General Purpose AF Operation Decimal Adjust Acc DAA Complement Acc CPL Negate Acc NEG 2 s complement 44 Complement Carry Flag CCF Set Carry Flag SCF Table 9 16 Bit Arithmetic Z80 CPU Instruction Description 61 280 CPU User s Manual Z 62 ZiLOG Table 9 16 Bit Arithmetic Destination Source HL ADD IX DD DD DD DD 09 19 39 29 IY FD FD FD FD 09 19 39 29 ADD with carry and set flags ADC HL ED ED ED ED 4A 5A 6A TA SUB with carry and set flags SBC HL ED ED ED ED 42 52 62 72 Increment INC DD FD 23 23 Decrement DEC DD FD 2B 2B Rotate and Shift A major feature of the Z80 is to rotate or shift data in the accumulator any general purpose register or any memory location All the rotate and shift Op Codes are depicted in Figure 10 Also included in the Z80 are arithmetic and logical shift operations These operations are useful in a wide range of appli
4. Rotate oP E b3 bo b7 ba b3 bo HL Digit SRL CB CB CB CB CB CB CB CB DD FD ACC A Left 3F 38 39 3A 3B 3C 3D 3E CB CB d d 3E 3E N ED HL Rotate 6F Digit ACC Right ED 67 Bit Manipulation The ability to set reset and test individual bits in a register or memory location is needed in almost every program These bits may be flags in a general purpose software routine indications of external control UM008003 1202 Z80 CPU Instruction Description 280 CPU User s Manual 66 ZiLOG Table 11 Bit Manipulation Group Continued Register Addressing Reg Indir Indexed Test 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 Bit 47 40 41 42 43 44 45 46 d d 46 46 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 4F 48 49 4A 48 4C 4D 4E d d 4E 4E DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 57 50 51 52 53 54 55 56 d d 56 56 DD FD 3 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 SF 58 59 SA 5B SC 5D SE d d 46 46 DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 67 60 61 62 63 64 65 66 d d 66 66 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 6F 68 69 6A 68 6C 6D 6E d d 6E 6E DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 77 70 71 72 73 74 75 76 d d 76 76 DD DD 7 C8 C8 C8 C8 C8 C8 CS C8 C8 C8 7F 78 79 7A 78 7C 7D 7E d d 46 46 UM008003 1202 Z80 CPU Instruction Description Z80 CPU User s Manual ziLOG Table 11 Bit Manipulatio
5. Bits 3 and 5 are not used Four of these bits C P V Z and S may be tested for use with conditional JUMP CALL or RETURN instructions Two flags may not be tested H N and are used for BCD arithmetic Carry Flag The Carry Flag C is set or cleared depending on the operation performed For ADD instructions that generate a Carry and SUB instructions that generate a Borrow the Carry Flag sets The Carry Flag is reset by an ADD instruction that does not generate a Carry and by a SUB instruction that does not generate a Borrow This saved Carry facilitates software routines UM008003 1202 Z80 Instruction Set Z80 CPU User s Manual ziLOG Table 2 8 Bit Load Group LD our Source Implied Register Reg Indirect 11indexed Ext Addr Imme Destination I R HL BC DE 1X d 1Y d Inn Register A ED ED FD DD 57 SF TE TE d d B DD FD Reg Indirect 46 d 46 INDEXED IX d DD DD DD DD DD DD m 72 73 74 75 36 a ja d a d d n TY d FD FD FD FD FD FD FD FD 77 70 71 72 73 74 75 36 a Id ja Ja ld ld la d n EXT nn ADDR IMPLIED I ED 47 R ED 4F UM008003 1202 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG
6. Instruction Description 280 CPU User s Manual 72 ZiLOG Table 14 Input Group Register Immed Indir n c Input Input IN Register A ED Destination Address 7B INI input amp Register HL ED Block inc HL Dec B Indir A2 Input INIR INP Inc HL ED Commands Dec B repeat IF B 0 B2 IND input amp Inc ED Dec HL Dec B AA INDR input Dec HL ED Dec B repeat IF B 0 BA UM008003 1202 Z80 CPU Instruction Description Z80 CPU User s Manual Table 16 Miscellaneous CPU Control NOP HALT Disable INT El IMO IM1 IM2 UM008003 1202 Enable INT EI Set INT mode 0 Set INT mode 1 Set INT mode 2 8080A mode Call to location 0038H ZiLOG Table 15 Output group Source Register Register Indir A B Ic D JE JH L AL OUT Ihmed 14 Reg c ED ED JED ED ED ED ED Ind 79 41 49 51 59 61 69 OUT output ED Block inc HL dec B A3 Output OUT output ED Command dec B repeat if B 0 B3 OUT output ED dec HL and B AB OUTDR output dec HL and B ED repeat IF B 0 BB Port Destination Address indirect call using register I and B bits from INTER device as a pointer Z80 CPU Instruction Description 73
7. line also goes active to indicate that the memory read data should be enabled onto the CPU data bus The CPU samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals Thus the data has already been sampled by the CPU before the RD signal becomes inactive Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories The CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time During T3 and T4 the lower seven bits of the address bus contain a memory refresh address and the RFSH signal becomes active tindicating that a refresh read of all dynamic memories must be accomplished An RD signal is not generated during refresh time to prevent data from different memory UM008003 1202 Overview CLK Ais Ag MREQ Z80 CPU User s Manual Z ziLOG segments from being gated onto the data bus The MREQ signal during refresh time should be used to perform a refresh read of all memory elements The refresh signal can not be used by itself because the refresh address is only guaranteed to be stable during MREQ time M1 Cycle Figure 5 Instruction Op Code Fetch Memory Read Or Write Figure 6 illustrates the timing of memory read or write cycles other than an Op Code fetch cycle These cycles are generally three clock perio
8. lists the eight Op Codes for the restart instruction This instruction is a single byte call to any of the eight addresses listed The simple mnemonic for these eight calls is also listed This instruction is useful for frequently used routines because memory consumption is minimized Table 13 Restart Group Op Code CALL Address 0000H RST 0 0008H RST 8 0010H RST 16 0018H RST 24 0020H RST 32 0028H RST 40 0030H RST 48 0038H RST 56 Input Output The Z80 has an extensive set of input and output instructions as shown in Table 14 and Table 15 The addressing of the input or output device can be either absolute or register indirect using the C register In the register indirect addressing mode data can be transferred between the I O devices and any of the internal registers In addition eight block transfer instructions have been implemented These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to the memory source output commands or destination input commands while register B is used as a byte counter Register C holds the address of the port for which the input or output command is required Because register B is eight bits in length the I O block transfer command handles up to 256 bytes In the instructions IN A and OUT n A the I O device address n appears in the lower half of the address bus A7 A0 while the accumulator content UM008003 1202 Z80 CPU
9. 280 CPU User s Manual Z ZiLOG i 13 CPU and System Control Signals Figure 1 UM008003 1202 Data Bus Control TAA Inst ee Register Internal Data Bus ALU n gt CPU CPU Control Registers 5V GND CLK Z80 CPU Block Diagram Address Control 16 Bit Address Bus Overview 280 CPU User s Manual ZiLOG zu 27 30 MT AO 31 w MREQ 2 A2 System IORQ 21 34 A3 Control RD A4 WR 22 35 e 36 AG Beau 28 37 RFSH AT Address 38 A8 Bus HALT 18 m A9 ai i A10 WAIT pI F A11 CPU A12 Control INT 54 280 CPU 3 A13 17 4 yy A14 NMI E A RESET Sp CPU BUSRQ I Bus RTE 23 Control BUSACK 14 DO 15 D1 GIK Fa 1 D2 11 a 7 gt D3 Data GND gt a D4 Bus 3 D5 10 de 13 D7 Figure 3 Z80 I O Pin Configuration UM008003 1202 Overview 12 Z80 CPU User s Manual ZiLOG CLK Machine Cycle M1 Opcode Fetch M2 Memory Read M3 Memory Write Instruction Cycle Figure 4 Basic CPU Timing Example Instruction Fetch Figure 5 depicts the timing during an M1 opcode fetch cycle The PC is placed on the address bus at the beginning of the M1 cycle One half clock cycle later the MREQ signal goes active At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories The RD
10. 6 d d F6 F6 DD FD 7 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 FF F8 F9 FA FB FC FD FE d d FE FE UM008003 1202 Z80 CPU Instruction Description Z80 CPU User s Manual ziLo G Table 12 Jump Call and Return Group Condition Un Carry Non Zero Non Parity Parity Sign Sign Reg Cond Carry Zero Even Odd Neg Pos B 0 JUMP JP IMMED nn EXT JUMP JR RELATIVE PC e 18 38 30 28 20 e 2 e 2 e 2 e 2 e 2 JUMP JP Register HL INDIR IX dY FD E9 CALL IMMED nn EXT Decrement B Jump RELATIVE PC e 10 If Non Zero DJNZ e 2 Return RE REGISTER SP Return From INDIR SP 1 ED INT RETI 4D Return From ED Non Maskable 45 INT RETN The instruction DJNZ is used to facilitate program loop control This two byte relative jump instruction decrements the B register and the jump occurs if the B register has not been decremented to zero The relative displacement is expressed as a signed two s complement number A simple example of its use is Address N N 1 N 2 to N 9 N 10 N 11 N 12 UM008003 1202 Instruction LD B 7 Perform a sequence of instructions DJNZ 8 Next Instruction Comments set B register to count of 7 loop to be performed 7 times to jump from N 12 to N 2 Z80 CPU Instruction Description 69 280 CPU User s Manual 70 ZiLOG Table 13
11. cations including integer multiplication and division Two BCD digit rotate instructions RRD and RLD allow a digit in the accumulator to be rotated with the two digits in a memory location pointed to by register pair HL See Figure 10 These instructions allow for efficient BCD arithmetic UM008003 1202 Z80 CPU Instruction Description Z80 CPU User s Manual ZiLOG 63 Table 10 Rotates and Shifts Source T A B Cc D E FF L HL X d IY d Rotate are te CY b7 a bo Left Circular Rotate Shift Rotate RCL CB CB CB CB CB CB CB CB DD FD RLCA Right Circular 07 00 01 02 03 04 06 OE CB CB d d 06 06 Rotate RRC CB CB CB CB CB CB CB CB DD FD RRCA t a Len OF 08 09 0A 06 OC OD 0OE CB CB d d ve dE Rotate RL CB CB CB CB CB CB CB CB DD FD RLA gt Right 17 10 11 12 13 14 15 16 CB CB d d 16 16 Shift CY lt lt A A RR CB CB CB CB CB CB CB CB DD FD RRA Left Arithmetic IF 18 19 IA IB 1C ID 1E CB CB d d IE IE Shift gt Right Arithmetic SLA CB CB CB CB CB CB CB CB DD FD 27 20 21 22 23 24 25 26 CB CB d d 26 26 Shift gt Right Logical SRA CB CB CB CB CB CB CB CB DD FD m 2F 28 29 2A 2B 2C 2D 2E CB CB 0 d d P gt y
12. ds long unless wait states are requested by the memory through the WAIT signal The MREQ signal and the RD signal are used the same as in the fetch cycle In a memory write cycle the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories The WR line is active when data on the data bus is stable so that UM008003 1202 Overview 13 280 CPU User s Manual ZiLOG it can be used directly as a R W pulse to virtually any type of semiconductor memory Furthermore the WR signal goes inactive one half T state before the address and data bus contents are changed so that the overlap requirements for almost any type of semiconductor memory type is met Memory Read Cycle Memory Write Cycle CLK A15 Ao MREQ RD WR Dy Do WAIT Figure 6 Memory Read or Write Cycle Input or Output Cycles Figure 7 illustrates an I O read or I O write operation During I O operations a single wait state is automatically inserted The reason is that during 1 0 operations the time from when the IORQ signal goes active until the CPU must sample the WAIT line is very short Without this extra state sufficient time does not exist for an I O port to decode its address and activate the WAIT line if a wait is required Also without this wait state it is difficult to design MOS I O devices that can operate at full CPU speed During this wait state time the WAIT request signal is sampled
13. h Note HL points to location in memory to be compared with accumulator contents BC Is byte counter Arithmetic and Logical Table 7 lists all the 8 bit arithmetic operations that can be performed with the accumulator also listed are the increment INC and decrement DEC UM008003 1202 Z80 CPU Instruction Description 60 Z80 CPU User s Manual ZiLOG Five general purpose arithmetic instructions operate on the accumulator or carry flag These five are listed in Table 8 The decimal adjust instruction can adjust for subtraction as well as addition making BCD arithmetic operations simple Note that to allow for this operation the flag N is used This flag is set if the last arithmetic operation was a subtract The negate accumulator NEG instruction forms the two s complement of the number in the accumulator Finally notice that a reset carry instruction is not included in the Z80 because this operation can be easily achieved through other instructions such as a logical AND of the accumulator with itself Table 9 lists all the 16 bit arithmetic operations between 16 bit registers There are five groups of instructions including add with carry and subtract with carry ADC and SBC affect all the flags These two groups simplify address calculation operations or other 16 bit arithmetic operations Table 7 8 Bit Arithmetic and Logic Source Register Addressing Reg Indir Indexed Immed IX d
14. maskable one is acknowledged since it has highest priority The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active Each cycle in the HALT state is a normal M1 fetch cycle except that the data received from the memory is ignored and a NOP instruction is forced internally to the CPU The HALT acknowledge signal is active during this time indicating that the processor is in the HALT state UM008003 1202 Overview 280 CPU User s Manual Z ziLOG 3 Main Register Set Alternate Register Set WM AN Accumulator Flags Accumulator Flags A F A F B e B B General D E D E Purpose H L H L Registers Interrupt Vector Memory Refresh I R Index Register IX Special Purpose Index Register IY Registers Stack Pointer SP Program Counter PC Figure 2 280 CPU Register Configuration UM008003 1202 Overview 280 CPU User s Manual 76 ZiLOG Z80 Status Indicator Flags The flag registers F and F supply information to the user about the status of the Z80 at any given time The bit positions for each flag is listed below Symbol Field Name C Carry Flag N Add Subtract P V Parity Overflow Flag H Half Carry Flag Z Zero Flag S Sign Flag X Not Used Each of the two flag registers contains 6 bits of status information that are set or cleared by CPU operations
15. n Group Continued Register Addressing Reg Indir Indexed Rest DD FD e 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 87 80 81 82 83 84 85 86 d d 86 86 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 8F 88 89 8A 88 8C 8D 8E d d 8E 8E DD FD 2 C8 C8 CS C8 C8 C8 C8 C8 C8 C8 97 90 91 92 93 94 95 96 d d 96 96 DD FD 3 C8 C8 C8 C8 CS C8 C8 C8 C8 C8 9F 98 99 9A 98 90 90 9E d d 9E 9E DD FD 4 C8 C8 C8 C8 C6 C8 C8 C8 C8 C8 A7 AO AI A2 A3 A4 AS A6 d d A6 A6 DD FD 5 C8 C8 C8 C8 08 C8 C8 C8 C8 C8 AF A8 A9 AA AB AC AD AE d d AE AE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 B7 BO BI 82 B3 B4 BS B6 d d B6 B6 DD DD 7 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 BF B8 89 8A B8 8C BD 9E d d BE BE UM008003 1202 Z80 CPU Instruction Description 67 280 CPU User s Manual 68 ZiLOG Table 11 Bit Manipulation Group Continued Register Addressing Reg Indir Indexed Set DD FD nn 0 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 C7 Co CI C2 C3 C4 C5 C6 d d C6 C6 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 CF C8 C9 CA C8 CC CD CE d d CE CE DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 D7 DO DI D2 D3 D4 DS D6 d d D6 D6 DD FD 3 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 DF D8 09 DA DS DC DD DE d d DE DE DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 E7 EO El E2 E3 E4 ES E6 d d E6 E6 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 EF E8 E9 EA EB EC ED EE d d EE EE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 F7 FO F1 F2 F3 F4 FS F
16. signal is sampled at the same time as the interrupt line but this line takes priority over the normal interrupt and it can not be disabled under software control Its usual function is to provide immediate response to important signals such as an impending power failure The CPU response to a non maskable interrupt is similar to a normal memory read operation The only difference is that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location 0066H The service routine for the non maskable interrupt must begin at this location if this interrupt is used UM008003 1202 Overview 18 280 CPU User s Manual 2 E oe Last M Cycle CLK NMI A15 Ag Figure 10 Non Maskable Interrupt Request Operation HALT Exit Whenever a software HALT instruction is executed the CPU executes NOPs until an interrupt is received either a non maskable or a maskable interrupt while the interrupt flip flop is enabled The two interrupt lines are sampled with the rising clock edge during each T4 state as depicted in Figure 11 If a non maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable flip flop is set then the HALT state is exited on the next rising clock edge The following cycle is an interrupt acknowledge cycle corresponding to the type of interrupt that was received If both are received at this time then the non
17. upted by either an NMI or an INT signal Any M Cycle Bus Available Status Last T State CLK BUSREQ BUSACK A5 A D7 Do MREQ RD WR IORQ RFSH Figure 8 Bus Request Acknowledge Cycle Interrupt Request Acknowledge Cycle Figure 9 illustrates the timing associated with an interrupt cycle The CPU samples the interrupt signal INT with the rising edge of the last clock at the end of any instruction The signal is not accepted if the internal CPU software controlled interrupt enable flip flop is not set or ifthe BUSREQ signal is active When the signal is accepted a special M1 cycle is generated During this special M1 cycle the IORQ signal becomes active instead of the normal MREQ to indicate that the interrupting device can place an 8 bit vector on the data bus Two wait states are automatically added to this cycle These states are added so that a ripple priority interrupt scheme can be easily implemented The two wait states allow sufficient time for the ripple signals to stabilize and identify which I O device must insert the response vector Refer to Chapter 6 for details on how the interrupt response vector is utilized by the CPU UM008003 1202 Overview Z80 CPU User s Manual Z ziLo G 17 Last M Cycle of Instruction M1 Figure 9 Interrupt Request Acknowledge Cycle Non Maskable Interrupt Response Figure 10 illustrates the request acknowledge cycle for the non maskable interrupt This
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