Chapter 11, Programmable Timers and I/O Ports
Contents
1. width count 1 enable period count CADIS 0 cache 1 disable cache TIMENO 0 disable timer 1 enable timer BUSLK 0 ext bus lock 1 ext bus lock 11 10 ADSP 21065L SHARC User s Manual Programmable Timers I O Ports The STKY Register Table 11 2 shows the CNT_EXPx and the PULSE_CAPx status bits in the STKY register Table 11 2 Timer status bits in the STKY register Bit Name Description 2 PULSE CAPO Pulse captured bit for timer 0 3 CNT EXPO CNT OVFO Counter expired counter over flowed bit for timer 0 4 PULSE_CAP1 Pulse captured bit for timer 1 5 CNT_EXP1 CNT_OVF1 Counter expired counter over flowed bit for timer 1 Timer Registers and their Values at Reset The TCOUNTx TPWIDTHx and TPERIODx registers are memory mapped While TPERIODx and TPWIDTH x are read write registers TCOUNT is read only The timer enable signal gates the timer clock interrupts and the edge detect logic In PWMOUT mode TPWIDTHx and TPERIODx must be initialized before the timer is enabled The timer is disabled at reset and at that time TPERIODx TCOUNTXx TPWIDTHx are unknown ADSP 21065L SHARC User s Manual 11 11 Timer Control Bits and the Interrupt Vectors Table 11 3 summarizes the IOP register addresses for the timer registers Table 11 3 IOP register addresses Register Address TPERIODO 02. 11 PROGRAMMABLE TIMERS AND I O PORTS The processor has two identical timer blocks each of which has two basic functions Pulse Width Waveform Generation PWMOUT PWMOUT mode Pulse Width Count Capture WIDTH CNT mode You can configure the timer in either mode The timer has one input out put pin PWM EVENT This pin functions as an output pin in the PWMOUT mode and as an input pin in the WIDTH mode implement these functions each timer has three registers TPERIODx TPWIDTHx and TCOUNTx All timer counters are 32 bits wide and use the processor s 2xCLKIN internal clock which evaluates to a maximum period of 71 5 sec 232 1 16 67 ns internal clock cycles for the timer count To enable or disable the timer you set or clear the TIMENXx bit in the register Figure 11 1 on page 11 2 shows the timer s enable and disable timing ADSP 21065L SHARC User s Manual 11 1 Timer Enable T TIMEN Timer MODE2 Enabled 2xCLK PWMOUT XXXXXXXXXXXXXXXKKXN TCOUNT xxI TCOUNT x TCOUNT 11 TCOUNT 2 TCOUNT 3 TCOUNT 4 TPERIOD 0x4 x TPWIDTH 0x2 Timer Disable TCOUNT 1 Clear TIMEN MODE2 Disabled 2xCLK Tcount m rcouwr rcouwr tcounT M 1 M 1 M 1 Figure 11 1 Timer enable and disable timing 11 2 ADSP 21065L SHARC User s Manual Programmable Timers I O Ports PWMOUT Mode In PWMOUT
3. ENTx Figure 11 4 Timer Flow Diagram WIDTH CNT Mode ADSP 21065L SHARC User s Manual 11 7 Timer Control Bits and the Interrupt Vectors Timer Control Bits and the Interrupt Vectors This section describes the timer control bit definitions and the MODE2 register definitions TIMENx Timer enable x 0 1 0 Disable 1 Enable PWMOUTx PWMOUT WIDTH_CNT control x 0 1 1 PWM_EVENT is a PWMOUT output 0 PWM_EVENT is an WIDTH_CNT input default PULSE HIx x 0 1 Applies to the WIDTH mode only 0 1 transition is leading edge in the WIDTH mode 1 1 to 0 transition is leading edge in the WIDTH CNT mode PERIOD CNTx Enable period count applicable only to the WIDTH CNT mode 0 Enable width count Interrupt and the PULSE_CAPx bits are set when pulse width is captured 1 Enable period count 11 8 ADSP 21065L SHARC User s Manual Programmable Timers I O Ports Interrupt and the PULSE_CAPx bits are set when pulse period is captured INT HIx Interrupt vector location x 0 1 The two timers generate interrupts and these can be latched either at bit 4 TMZHI or at bit 23 TMZLI of the IRPTL register as shown in Table 11 1 In addition these interrupts can be masked using the IMASK register Table 11 1 Timer status INT HI1 INT HIO Status 0 0 Both timers latch to TMZLI 0 1 gt TMZLI timerO gt TMZHI 1 0 timeri g
4. ed is generated when the timer captures either the pulse width or the pulse period value which depends on the value of the PERIOD CNTx bit in the MODE2 register If the PERIOD CNTx is set high the interrupt and the PULSE CAPx bits in the STKY register get set when the pulse period value is captured If the PERIOD CNTx is set low then the interrupt and the PULSE are set when the pulse width value is captured A timer interrupt if enabled is also generated if the counter TCOUNTx reaches a value of OxFFFF FFFF e Before the edge for the pulse period is detected if PERIOD CNTx is high e Before the edge for the pulse width is detected if the PERIOD CNTx is low In addition the status bit OVFx in the STKY register is set indicating that TCOUNTx overflowed before the timer counted the maximum 222 2 intervening clock cycles PULSE CAPxand CNT EXPx CNT OVEx are sticky bits and software has to explicitly clear them Note that the TPERIODx TPWIDTHx and TCOUNTx x 0 1 are all IOP memory mapped registers not universal registers Figure 11 4 on page 11 7 shows the timer flow 11 6 ADSP 21065L SHARC User s Manual Programmable Timers and I O Ports Cee D am F TCOUNTx Set COUNT_OVF bit E Trailing Edge Detect PWM_EVENTx RESET COUNT Interrupt Interrupt PERIOD CNT D Leading Set PULSE CAP bit Edge 2 Detect PERIOD CNT PWM_EV
5. ers I O Ports WIDTH_CNT Mode In the WIDTH_CNT mode the is an input pin To select this mode you set the PWMOUT x bit low in the MODE2 register When enabled in this mode the timer resets TCOUNT x to 0x0000 0001 when it detects the leading edge of the PWM_EVENT x pin and starts counting increments When it detects the trailing edge the timer captures the current value of the into the TPWIDTHx register At the leading edge the timer transfers the current value of the TCOUNT x into the TPERIODx register This timing shown in Figure 11 3 assumes the leading edge is set as 0 gt 1 1st Leading Framing 2nd Leading Edge Edge Edge Detected Detected Detected 2xCLK d b Pod PWM EVENT NC REN C D D Transfered Transfered TPWIDTH TPERIOD Figure 11 3 WIDTH_CNT mode timing In this case your software application can measure both the pulse width and the pulse period values which are available in the TPWIDTH x and the TPERIODx registers respectively ADSP 21065L SHARC User s Manual 11 5 To control the definition of leading edge and trailing edge of the PWM_EVENT x you set the PULSE_HIx bit in the register TPERIODx and TPWIDTHx are read only registers when the timer is enabled in WIDTH CNT mode A timer interrupt if enabl
6. mode the _ is an output pin To select it you set the PWMOUT lt x bit high in the MODE register The registers TPERIODx and TPWIDTH x contain the values of the timer count period and PWM output pulse width respectively To avoid unpredictable results of the PWM_EVENTx signal e Initialize TPWIDTHx TPERIODx before enabling the timer Do not alter TPWIDTHx and TPERIODx while the timer is enabled Make sure the value of TPWIDTHXkx is less than the value of TPERIODx When the timer is enabled in this mode the PWM_EVENT x is pulled low each time the TCOUNT x up counter value equals the TPERIODx value and it is pulled high when the TCOUNT x value equals the TPWIDTH x value TCOUNTX is reset once to 0x0000 0001 when the timer is enabled and each time TCOUNTX reaches the TPERIODx value See Figure 11 1 on page 11 2 When TCOUNT equals TPERIODx a timer interrupt if enabled is generated and the CNT EXPx CNT OVFEFx bit in the STKY register is set The OVFx bit is a sticky bit and software must reset it explicitly At reset its value is 0 Figure 11 2 shows the timer flow ADSP 21065L SHARC User s Manual 11 3 TPERIODx TPWIDTx gt Interrupt Set PWMOUNT High Set CNT_EXP bit PWMOUT PWM EVENTx Logic Set PWMOUNT Low ll Figure 11 2 Timer Flow Diagram PWMOUT Mode 11 4 ADSP 21065L SHARC User s Manual Programmable Tim
7. s are set see Chapter 10 SDRAM Interface For a description of the IOSTAT register see Figure 11 6 The IOP address locations for the IOCTL and the IOSTAT registers are 0x2e and 0x2f respectively 11 14 ADSP 21065L SHARC User s Manual
8. t TMZHI timerO gt TMZLI 1 1 Both timers latch to TMZHI Timer Interrupts and the Status Stack Only the timer interrupt on the TMZHI bit pushes the status stack so in the above combinations 00 will not push the status stack but both 01 and 10 will push the status stack depending on which timer is programmed to cause the TMZHI interrupt When using the 11 combination interrupts generated by either timer push the status stack When using the 00 and 11 combinations the processor latches a logical OR function of the two timer interrupts into the interrupt latch register The software checks CNT_EXPx and the EDGE_CAP x bits deter mines the source of the interrupt and takes appropriate action Figure 11 5 on page 11 10 shows the mapping of the MODE2 register ADSP 21065L SHARC User s Manual 11 9 Timer Control Bits and the Interrupt Vectors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Silicon Rev Processor ID 15 14 1312 11109 8 7 6 5 4 3 2 1 FLGOO PULSE_HI1 Leading edge trans WIDTH_CNT mode 0 0 1 transition 1 1 0 transition INT PWMOUT 1 TIMEN1 PERIOD CNT1 PULSE HIO INT HIO Intrpt vector location PWMOUTO 0 WIDTH_CNT input 1 PWMOUT output Figure 11 5 MODE2 Register FLG10 O input 1 output FLG20 FLG30 CAFRZ O cache updates 1 cache freeze IRQOE O level sensitive 1 edge sensitive IRQ1E IRQ2E PERIOD_CNTO
9. x28 PWIDTHO 0x29 COUNTO 0x2a TPERIODI 0x2b PWIDTHI 0x2c COUNTI 0x2d 11 12 ADSP 21065L SHARC User s Manual Programmable Timers I O Ports Programmable I O Ports The processor has twelve flag pins FLAG 1 0 which are programmable general purpose I O ports The MODE 2 register configures the functionality or direction of the pins FLAG and ASTAT register reflects the value of these flag bits The functionality of the FLAG 4 pins is similar to that of the FLAG o but the IOP registers IOCTL and IOSTAT contain their control and sta tus bits You cannot execute the bitwise operations such as BIT TST BIT CLR and so on directly on the IOP registers To perform these operations on the FLAG pins you must first transfer the contents of IOSTAT register shown in Figure 11 6 to the Register File or to another universal register 31 30 29 28 27 26 25 24 283 22 21 20 19 18 17 16 15 14 1312 11109 8 7 6 5 4 3 2 1 0 FLG4 FLG5 FLG6 FLG7 FLG8 FLG9 FLG10 FLG11 FLGx FLAGx pin value Figure 11 6 IOSTAT register ADSP 21065L SHARC User s Manual 11 13 Programmable I O Ports ASTAT is a universal register so the status on FLAGs o can be checked and manipulated using the bitwise operations directly This is the differ ence between the FLAG 0 and the rest of the FLAG pins For detailed description of the IOCTL register where the directions on the I O port
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