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User's Manual 686LCD/S & 686LCD/MG CPU Board

1. 5 5 5 5 5 5 5 5 5 II 0092h is u vu EE Keyboard controller status Bi No parity error Parity error on last byte of transmission from keyboard Bi No timeout Received a timeout on last transmission No timeout Transmission from keyboard controller to keyboard timed out Keyboard inhibited Keyboard not inhibited Data System writes to input buffer via I O port 0060h Command System writes to input buffer via I O port 0064h System flag status Set to 0 after a power on reset The keyboard controller sets this bit according to the command from the system Input buffer 0060h or 0064h is empty Input buffer full Output buffer has no data Output buffer full W Keyboard Command Write 070h 0071h are used by the RTC clock and CMOS RAM Real Time Clock CMOS RAM address register and NMI mask Bit 7 0 NMI disabled 1 NMI enabled Bits 6 0 CMOS RAM index address register R W CMOS RAM data register port 0080h is used for power on diagnostics port Manufacturing test port POST checkpoints can be accessed via this port Temporary storage for additional DMA page register 0081h 008Fh are used for DMA control DMA channel 2 Address bits 23 16 DMA c
2. i 5 201 GND 22422002 BUSY GND PE GD 00 c _ OND INSIDE Technology A S Page 86 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 10 2 1825 Printer Port Connector Pull PIN Pull Note U D Ioh Iol Type Signal Signal Ioh Iol U D Note 4K7 d2 24 OC 0 1 mm EY NENNEN NM ro 2 Hr DEBER l1 224 4K7 M O o NM Jjoc ___ 1 Cd 7 1 208 NM BM I 10 BU jp m 1 INSIDE Technology A S Page 87 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 10 3 Signal Description Printer Port The following signal description covers the signal definitions when the printer port is operated in standard Centronic mode The printer port controller also supports the fast EPP and ECP modes please refer to reference 2 for further information PD7 0 SLIN SLCT STB BUSY INIT AFD PER Paral
3. ze INSIDE Technology A S Page 134 of 134
4. 4 1024 by 768 pixels Font size Small Fonts Custom 8 In order to use new driver computer must be restarted Further configuration of the display adapter may be made from the Display Properties window follow step 1 above The Settings tab allows you to change resolution number of colours etc and the Refresh tab allows you to set the display type refresh rate etc as shown below INSIDE Technology A S Page 66 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Display Properties Background Screen Saver Appearance Plus Refresh Settings Refresh Rate Display Device G E Windows Default C LcD BOTH Information Current Mode 1024x768 colors 451 6 2 2 Windows NT 4 0 Display installation A display driver for Windows NT 4 0 is supplied with the system on the floppy disk labelled Display Driver Disk The driver installation may be performed by the following steps 1 Start the control panel by clicking the Start button click settings and Control Panel from the sub menu Double click the Display Icon in the control panel as shown below Control Panel File Edit View Help Accessibility Add Remove Console Date Time Options Programs Licensing 6 Devices Adsanters 2 Changes display se
5. 5 BALE VCC oc COMPONENTSIDE C S SOLDERSDE Memcsis P fix EESTI 215 VCC 277 GD INSIDE Technology A S Page 105 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7171 Signal Description PC AT PC104 Bus ADDRESS LA23 17 The address signals LA23 17 define the selection of a 128kB section of memory space within the 16MB address range of the 16 bit data bus These signals are active high The validity of the 16 depends on these signals only These address lines are presented to the system with tri state drivers The permanent master drives these lines except when an alternate master cycle occurs in this case the temporary master drives these lines The LA signals are not defined for I O accesses SA19 0 The address signals SA 0 define the selection with the granularity of one byte within section of memory defined by the LA address lines The address lines SA19 17 that are coincident with LA19 17 are defined to have the same value as LA19 17 for all memory cycles These signals are active high These address lines are presented to the system with tri state drivers The permanent master drives these lines except when an alternate master cycle occur
6. cc 14 14 10 PWR DIG GND DDCCLK 10 Note 1 Vout 1 5 10 10 mA Io 21 mA for 1 V Rload 37 5 2 VCC supply is on board fused with a 5A resetable fuse 7 13 2 Signal Description CRT Connector HSYNC CRT horizontal synchronisation output VSYNC CRT vertical synchronisation output DDCCLK Display Data Channel Clock Used as clock signal to from monitors with DDC interface DDCDAT Display Data Channel Data Used as data signal to from monitors with DDC interface RED Analog output carrying the red colour signal to the CRT For 75 cable impedance GREEN Analog output carrying the green colour signal to the CRT For 75 cable impedance BLUE Analog output carrying the blue colour signal to the CRT For 75 cable impedance DIG GND Ground reference for HSYNC and VSYNC ANA GND Ground reference for RED GREEN and BLUE INSIDE Technology A S Page 93 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 3 Flat Panel Connector JPLCD Pull PIN Pull Note 00 Ioh Iol Type Signal Signal Ioh Iol U D Note 7 8 ENVEE 88 5 G S 3 17 2 4 NOK 3 cv 0 0 2
7. This active high signal indicates that the adapter should be brought to an initial reset condition This signal will be asserted by the permanent master on the bus for at least 100 ms at power up or watchdog time out to ensure that adapters in the system are properly reset When active all adapters should turn off or tri state all drivers connected to the bus INTERRUPTS IRQ3 7 IRQ9 12 14 15 These signals are active high signals which indicate the presence of an interrupting PC AT PC104 bus adapter Due to the use of pull ups unused interrupt inputs must be masked BUS ARBITRATION DRQO 3 DRQS 7 These signals are active high signals driven by a DMA bus adapter to indicate a request for a DMA bus operation DRQO 3 request 8 bit DMA operations while DRQ5 DRQ7 request 16 bit operations All bus DMA adapters will drive these lines with a tri state driver The permanent master monitors these signals to determine which of the DMA devices if any are requesting the bus DACKO 3 7 These signals are active low signals driven by the permanent master to indicate that a DMA operation can begin They are continuously driven by a totem pole driver for DMA channels attached INSIDE Technology A S Page 108 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 This signal is an active high totem pole signal driven the permanent master to indicate that the address lin
8. Desktop area High Color 16 bit Less More z 1024 by 768 pixels Eont size rate 3 Custom Change Display Type 3 Click the Change Display Type button to change the driver This will show the following window INSIDE Technology A S Page 64 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Change Display Type BEI Adapter Type Chips and Tech 65554 PCI Change Manufacturer Chips And Technologies Inc Version 40 Current Files chips95 drv vdd vilatd chips95 vxd Monitor Type Hitachi CM1798M Change Monitor is Energy Star compliant Click the Change button in the Adapter Type frame to select another driver Your display will probably have another driver then the Chips and Tech 65554 PCT installed at this moment otherwise your configuration is already correct 4 A display driver may now be chosen as shown below or it may be supplied from a disk To use a driver from disk click the Have disk button Install From Disk x Insert the manufacturer s installation disk into the drive selected and then click Lk Cancel Browse Copy manufacturer s files from jc 35 Enter the directory on the floppy disk A WIN95 where the drivers may be found and click OK see above 5 The drivers will now be shown To see all the drivers click the Show all devices
9. Reserved for MDA Hercules MDA CRTC index register MDA CRTC data register Reserved for MDA Hercules Hercules mode register Status register Feature control register IW IW W 03BCh 03BFh may be used for off board Parallel port 3 03BC 03BFh 03COh 03CFh The bit definitions for these addresses are the same as those for addresses 0378h 037Fh R W Available for off board parallel port 3 are used by on board Video controller in color and monochrome modes 03COh 03 03C2h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C7h 03C8h 03C9h 03CAh 03CCh 03CEh 03CFh 5 5 Attribute controller Index Data Attribute Alternate controller Data Input Status Register Miscellaneous Output Register Video Subsystem enable Sequencer index Sequencer data Color palette mask Color palette state Color palette read mode index Color palette write mode index Color palette data Feature Control register Miscellaneous output register Graphics controller index Graphics controller data es W W R R 03D0h 03D3h are used by Flat Panel and Multimedia Extension INSIDE Technology A S Flat Panel Extensions Index Flat Panel Extensions Data Multimedia Extensions Index Multimedia Extensions Data Page 42 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 03D4h
10. 98 7 13 8 Flat Panel Utility Connector 99 7 13 9 Signal Description Flat Panel Utility Connector LCDADP 99 7 13 10 Video Capture Port IPY UV iieedaasecc iei ctore cepta etia suras eee edd 100 7 13 11 Signal Description Video Capture Port 7 101 7 14 Ethernet connector 10BASE crece e eee eese eee sane sese see e sese 102 7 14 1 Signal Description Ethernet connector 1OBASE see 102 7 15 AUF Connector JPA UL 103 7 15 1 Signal Description AUI Connector 103 7 16 PC104 Connector PC104XT amp 4 104 7 17 Edge Connector unito inier iis 105 7 17 1 Signal Description PC AT 104 106 8 MAIN 686 COMPONENTS 110 9 MEASUREMENT DRAWING 686_ 0 5 111 APPENDIX A BIOS 5 2 2222222 4 2 2 a anna ananas ed Cu a tra aa aua naa nn au uaa aa Rua 112 APPENDIX B 686LCD MG CPU 113 INSIDE Technology A S 6
11. PCNET PCI Ethernet Adapter This driver may be installed in two ways During the installation process where the network may be configured as an integrated part In this case the adapter may be chosen or auto detected when the network adapter is to be installed nthe network settings after Windows NT 4 0 is installed INSIDE Technology A S Page 57 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 In the following the steps for an installation on an existing NT installation are described 1 Click the Start button on the task bar Select Settings and Control Panel to start the control panel shown below Control Panel x File Edit View Help B s Accessibility Add Remove Date Time Display Options Programs D Modems Printers i Adantars Configures network hardware and software 2 2 Double click Network icon and click Adapters tab on following window window as the one below should now appear L2 1x Network Network Adapters Add Update Jtem Notes 3 Click the Add button and the following window should appear INSIDE Technology A S Page 58 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Select Network Adapter x Click the Network Adapter that matches your hardware and then click OK If you have an installation disk for thi
12. olo 6 0 olo x Hoes oo olo SE role lo UF uude 5 Ho o o o o o OT o uso d 5 00006000500 0005000050000 900000000 55 9 Gh Ao 00000000000 70000000 000000000000 oo 000000000000 a 0doooopooooooooooo ooooooodoooooooooo o S oooldooooooooooo d 5 E booodooooooooooo 00000000f000000000 O 5 2 JE EPY odooo pooooooooooo 000000040000000000 5 gt E El 9 n ooploodoooooooooo m Tod eoo o oo d 9 c o o plo
13. Read IOW Write IOCS 16 This signal is driven by the peripheral hard disk to indicate that the current I O address needs a 16 bit data transfer IORDY This signal may be driven by the hard disk to extend the current I O cycle RESET Reset signal to the hard disk The signal is similar to RSTDRV in the PC AT bus 14 Interrupt line from hard disk Connected directly to PC AT bus DDREQO Disk DMA Request might be driven by the IDE hard disk to request bus master access to the PCI bus The signal is used in conjunction with the PCI bus master IDE function and is not associated with any PC AT bus compatible DMA channel DDACKO Disk DMA Acknowledge Active low signal grants IDE bus master access to the PCI bus HDACT Signal from hard disk indicating hard disk activity The signal level depends on the hard disk type normally active low The signal is routed directly to the connector JPFEAT INSIDE Technology A S Page 92 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 Video Connectors 7 13 1 CRT Connector CRT Pull Pull type sum suma Ub EN La 1 u weew wwR s pwr ss 3 13 SYNC eee
14. Bits 7 0 0 1 No active request for the corresponding interrupt line Active request for the corresponding interrupt line Interrupt in service register Bits 7 0 1 Mask 0 1 The corresponding interrupt line is not being serviced The corresponding interrupt line is being serviced Initialization Command Word 2 4 Following a write to the ICW1 a initialization sequence with three writes to respectively ICW2 ICW3 and ICW4 Initialization Command Word 2 INSIDE Technology A S Technology A S nnnnn o0ih w imitialization Command Word 2 4 Following a write to the a initialization sequence with three Bits 7 3 Bits 2 0 Initialization Command Word 3 Bits 7 3 Reserved Must be Os Bit 2 Cascaded Mode Enable Bit 0 Reserved Must be all Os Initialization Comand Word 4 Bits 7 5 000 Reserved should be zeroes Bit4 0 No special fully nested mode 1 Special fully nested mode it 3 2 00 Buffered Mode Must be programmed to 00 selecting Non buffered mode it 1 0 Normal EOI 1 Auto EOI it 0 0 8085 mode 1 8086 and 8080 mode Intel Architecture Based system 0021h PCI ISA Operation Command Word 1 OCWI Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 000 0 Address lines A7 A3 of base vector address for interrupt controller Interrupt Request Level Must be programmed to all 05 Enable IRQ7 interrupt Enable IRQ6 interr
15. EUN IN Erea Sie 32 ESE aie 32 aa 32 3 12 E3125 Eaz EA 2404 EL Q OWS 12V 5 1 3 12 NM RESETDRV p 3 12 lies _______ IOC PN INSIDE Technology A S Page 104 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 17 PC AT Edge Connector Pull PIN Pull Note U D Ioh Iol Type Signal 5 Signal Type Note ET IOCHCHK lt 07 RESETDRV _ 5 5 G cov eee v ows 3308 soo ov IOC IOCHRDY E AEN MEMW OT 32 10K 55 S 5 low 55 DRQ SALA DACKi SAG DRQ 55 REFRESH 100 1 4 308 2 a o MEN 5 5 IRQS I 5 9 DACOR O
16. Set by master device if transaction is terminated with Target Abort Set by target device if it terminates transaction with Target Abort Fast timing for assertion of DEVSEL allowed Medium timing for assertion of DEVSEL allowed Slow timing for assertion of DEVSEL allowed Reserved Agent asserted or observed PERR asserted acting as bus master in the erronous transfer with the Parity Error Response bit set Target capable of accepting back to back transactions Device supports user definable features 33MHz operation Reserved Revision ID This register specifies a device specific revision identifier chosen by the vendor INSIDE Technology A S Page 49 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 e Class Code This read only register identifies the generic function of the device The register is divided in three byte size fields The upper byte at offset OBh is a base class code which broadly identifies the type of function the device performs The lower bytes specify more precisely the function the codes can be found in the PCI local bus specifications The Base class codes can be seen below Base Class Meaning 00h Device was built before class codes were defined Olh Mass storage controller 02h Network controller 03h Display controller 04h Multimedia device 05h Memory controller 06h Bridge device 07h Simple communication controller 08h Base system peripherals 09h Inp
17. driver selection presented in bottom of the screen indicate the display number to lock with if using the BFLASH utility Panel Interface By changing this setting the user can specify the Panel Interface voltage The settings are 3 3 Volts or 5 0 Volts The Default and Fail Safe settings are 3 3 Volts Warning Always check the Panel specifications to make sure it can handle a higher voltage before changing the default parameter JPLCD Pin 5 This feature is added to ease the connection to plasma displays which requires an inversion of the data clock signal SHFCLK The default setting is where pin 5 on the LCD connector outputs the signal GPIO2 The other option is SHFCLK Selecting this option does not affect the original SFKCLK signal pin 13 e SSD Drive This option sets up the Solid State Disk Drive The options are Off A B C or Last DRV If set to Off the Solid State Disk cannot be accessed If set to the system will attempt to boot on the SSD if the 1st boot device in the Advanced setup is floppy If a A floppy drive exists it will be remapped to B If set to B the SSD will be accessed through B and will overrule any B floppy drives present If set to C the system will attempt to boot on the SSD and any harddisk present will be remapped to D This selection has to be chosen if preparation of a bootable SSD emulating drive C is desired If set to Last DRV the SSD will be assigned the last availa
18. 73 7 3 Keyboard Connectors 74 7 31 Pin row Keyboard Connector 74 7 3 2 MINI DIN Keyboard Connector KBD ice ee Rei es nets 74 733 Signal Description Keyboard Connectors 74 74 PS 2 Mouse Connector JPMSE ccccccccscscscsssssssecsccscccssssscsssecsccccsssssssssesccscsssssssesees 75 7 4 1 Description PS 2 Mouse te ee 75 7 5 USB Connector USBCON scccccccccsssssssssscsscsccssssssssecscccccesssssssssececcsccssssssssecececesecsescees 76 7 5 1 Signal Description USB Connector 76 7 6 Power Connector ccccccccccsssssssecsscscccsssssssscscsscccsssssssssessccccssesecsscssecescsssses 77 T Serial Port dob eva Rao 78 771 DB9 Serial Port 1 Connector COMI in RS232 Mode 78 7 1 2 Signal Description Serial Port 1 COMI in RS232 79 77 3 DB9 Serial Port 1 Connector COMI RS422 80 7 7 4 Signal Description Serial Port 1 COMI in RS422 80 7 7 5 DB9 Serial Port 1 Connector COMI in RS485 81 7 7 6 Signal Description Serial Port 1 COMI in RS485 81 7 8 Pin Header Serial Port 2 Connector 2 scccccssssssssssssssseccsccccsssscssscceccscseeees 82 7 8 1 Serial Port 2 with external DB9 Connector 82 7 8 2 Signal Description Serial Port 2
19. SHFCLK 3 44 BEEN o 16 1242 BETON Low mA GND o GND GND 3 12 12 OT 12 2 12 2 OT 220 PWR Pis GD eee 12 12 4 i p cw Po 2 _ Ea E ESSE EE EE rcu BEGIN a 12 12 12 12 12 12 1 1 1 1 12 12 12 12 1 In PCB revision 20100161 this supply will be 5V DC External 3 3V DC regulator must be used when connecting 3 3V DC flat panels This is not needed for all future PCB revisions 2 VEE only supported when FPUM module is installed 3 These 3 signals might be used by INSIDE Technology for flat panel contrast controlling purposes FPUM module for support of STN or monochrome Panels INSIDE Technology A S Page 94 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 4 Signal Description Flat Panel Connector P23 0 Flat panel data output for 8 9 12 16 18 or 24 bit panels Refer to table below for configurations for various panel types The flat panel data and
20. a 66 68 89 5 445879 e WW LEZ 5 9 gt 00000000 999999999 0600000000 0000000000 CEER EREE 0090000 __ 99999999999 9 0000004 oe oe 9690090000000 29999999999 9060000000000 ai E 555409555 H Page 111 of 134 INSIDE Technology A S 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Appendix A BIOS Revisions BIOS release 110 306 627 Nov 97 New features Display selection More than 14 different display types now available in the same BIOS Wait for F1 option now present Added feature to output an inverted SHFCLK in JPLCD connector mainly used by plasma screens Storage of the CMOS parameters in flash Secure CMOS option added Power management does now take care of the FPUM backlight 233Mhz now also an option SSD prepare will now also affect on the Atmel flash by wiping the boot sector Updated version of the SCSI bios extension gt 1 32 Function 23h setup GPIO s added to the INSIDE interrupts Xs Bugs Problems solved Improv
21. 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 Connector Definitions 7 1 Connector layout on Half Size PCB oj ooo od e oo o moo o ol 2 0000000400000 999099 0000 N Att LL 9 Flat Panel o 0 0 0 9 Feature HDD 686LCD S DRAM Processor Cache ee INSIDE Technology A S Page 72 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 2 Symbol Descriptions Pin Signal Type Ioh Iol Pull U D Note TBD Shows the pin numbers in the connector The graphical layout of the connector definition tables is made similar to the physical connectors The mnemonic name of the signal at the current pin The notation states that the signal XX is active low AO Ire IO 15 IOC NC O OC OT PWR Toh 101 Analog Output Input TTL compatible if nothing else stated Input Output TTL compatible if nothing else stated Bi directional tristate IO pin Schmitt trigger input TTL compatible Input open collector Output TTL compatible Pin not connected Output TTL compatible Output open collector or open drain TTL compatible O
22. C 5422 mode is typically used in point to point communication Data and control signal pairs should be terminated in the receiver end with a resistor matching the cable impedance typ 100 120 9 The resistors could be placed in the connector housing RS485 mode is typically used in multi drop applications where more than 2 units are communicating The data and control signal pairs should be terminated in each end of the communication line with a resistor matching the cable impedance typical 100 120 Stubs to substations should be avoided 7 7 1 DB9 Serial Port 1 Connector COM1 in 5232 Mode Pull Pull Note U D Ioh Iol Type I Signal Type Ioh Iol U D em 1 The CPU board is equipped with RS232 drivers operating with capacitor charge pumps The RS232 channel will operate from 5 V supply only 3 Please note that the RI Ring Indicator signal is not supported in Serial port 1 due to the multi function RS232 RS422 RS485 capabilities Do not connect anything to this signal in RS232 mode as it acts as output The Thevenin equivalent for an output is specified below for RS232 mode DC Rth Ohm Vth V DC Rth Ohm INSIDE Technology A S Page 78 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 7 2 Signal Description Serial Port 1 COMI RS232 Mode TxD Serial output This signal sends serial data to the communication link The signal
23. CMOS setup menus no fight with several jumpers will be necessary INSIDE Technology A S Page 1 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 2 System specification short form The 686LCD S is a new standard for half size PENTIUM Computing Power The 686LCD S CPU Board is a fully featured PENTIUM computer implemented on a half size PC AT slot board It can be used in commercial and industrial environments especially in applications where very compact mechanical construction and low power consumption are required It contains all the necessary functional modules like CPU DRAM memory video controller Ethernet and peripheral interfaces on a single board to implement a PENTIUM stand alone computer system The 686LCD S is designed for maximum flexibility It can be equipped with different PENTIUM Processors and memory components and several configuration parameters are freely re program mable A versatile 64 Bit on board Video Controller with 2 MB Video Ram supports a large number of different Flat Panel interfaces as well as standard VGA analogue monitors For Flat Panel interface LVDS Low Voltage Differential Signal is implemented via PanelLink Multimedia interface with YUV connector for direct Video input is also available The 686LCD S has two RS232C or x RS232C and 1 x RS422 485 serial interface channels one parallel printer port one EIDE compatible hard disk interface and one flo
24. Extended write selection Fixed priority Rotating priority Normal timing Compressed timing Enable controller Disable controller Disable memory to memory transfer Enable memory to memory transfer Reserved DMA channel 4 7 write request register DMA channel 4 7 write single mask register bit Bits 7 3 Reserved should all be zeroes Bit2 0 Clear mask bit 1 Set mask Bit 1 0 Channel select 00 Channel 4 01 Channel 5 10 Channel 6 11 Channel 7 Bi 00246 INSIDE Technology A S Page 38 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access 5 00086 00D 00DAh 00DCh 00DEh Description DMA channel 4 7 mode register Bits 7 6 Mode select Demand mode Single mode Block mode Cascade mode Address increment Address decrement Disable autoinitialization Enable autoinitialization Select type of operation Verify operation Write to memory Read from memory Reserved Channel select Channel 4 Channel 5 Channel 6 Channel 7 00 01 10 11 0 1 0 1 00 01 10 11 DMA channel 4 7 clear byte pointer flip flop DMA channel 4 7 read temporary register DMA channel 4 7 master clear DMA channel 4 7 clear mask register DMA channel 4 7 write mask register Watch Dog Service 0 Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Fan current exceeded
25. LBA Large Mode Block Mode 32Bit Mode and PIO Mode All parameters relate to IDE drives except Type Please note that Secondary Master and Slave Hard Disk drives are not supported in hardware and changing these settings will have no effect Configuring MFM Drive If configuring an old MFM hard disk drive you must know the drive parameters number of heads number of cylinders number of sectors the starting write pre compensation cylinder and drive capacity Choose Type and choose the appropriate hard disk drive type 1 46 The old MFM hard drive types are listed in table b User Defined Drive If you are configuring a SCSI drive or a MFM RLL ARLL or ESDI drive with drive parameters that do not match drive types 1 46 you can select the User in the Type field You must then enter the drive parameters as listed in table a on the window that appears INSIDE Technology A S Page 8 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Table A Drive Parameters Write The size of a sector gets progressively smaller as the track Precompensation diameter diminishes Yet each sector must still hold 512 bytes Write precompensation circuitry on the hard disk compensates for the physical difference in sector size by boosting the write current for sectors on inner tracks This parameter is the track number where write precompensation begins Landing Zone This number is the cylinder location where the heads will norma
26. PIIX3 function 0 an IDE Interface PIIX function 1 Universal Serial Bus USB PIIX function 2 Ethernet and VGA On the 686LCD MG board an additional onboard SCSI function is available as well as any external boards added in the off board PCI slots The PCI to ISA bridge supports PCI master initiated I O and memory cycles to the ISA bus as well as DMA compatible cycles between main memory and ISA I O The IDE interface is capable of accelerated PIO transfers but can also act as a PCI Bus master on behalf of an IDE DMA slave device if the PCI IDE Bus Master option is enabled in the PCI PnP setup in the BIOS The following PCI Configuration Register dumps are included as an example of possible register settings for a typical system The actual settings depend on the actual system and the PnP manager and are subject to change from the below mentioned Intel PIIX3 PCI to ISA bridge Register dump for device 7 function 0 Confg 00 70008086 Confg 0280000F Confg 08 06010001 Confg 00800000 Confg 10 00000000 Confg 14 00000000 Confg 18 00000000 Confg 1C 00000000 Confg 20 00000000 Confg 24 00000000 Confg 28 00000000 Confg 2C 00000000 Confg 30 00000000 Confg 34 00000000 Confg 38 00000000 Confg 00000000 Confg 40 00000000 Confg 44 00000000 48 00000000 Confg 0170004D Confg 50 00000000 Confg 54 00000000 Confg 58 00000000 Confg 5C 00000000 Confg 60 0B09800A Confg 64 00000
27. PIN Pull Signal Ioh Iol Note 1 2 Note 1 PS 2 Mouse VCC supply is on board fused with a 5A resetable fuse 7 4 1 Signal Description PS 2 Mouse MSECLK Bi directional clock signal used to strobe data commands from to the PS 2 mouse MSEDAT Bi directional serial data line used to transfer data from or commands to the PS 2 mouse INSIDE Technology A S Page 75 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 5 USB Connector USBCON Pull Pull Note U D Ioh Iol Type Signal ah Signal U D Note 1 Pem fg oo pw Oo L 0 25 2 10 gt pr 0 10 252 15 eee Note 1 The USB VCC supply is on board fused with a 5A resetable fuse 7 5 1 Signal Description USB Connector USBCON DO Differential bi directional data signal for USB channel 0 Clock is transmitted along with the data using NRZI encoding The signalling bit rate is up to 12 Mbs 1 1 Differential bi directional data signal for USB channel 1 Clock is transmitted along with the data using NRZI encoding The signalling bit rate is up to 12 Mbs 5 DC supply for external devices Maximum load according to USB standard INSIDE Technology A S Page 76 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4
28. SHFCLK INSIDE Technology A S Page 96 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 6 Panel Link FPDI Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note 2 15 2 Oo 51 TOC o 22200 _ ll o GND eos uz Tx ong exp TxD G vec INSIDE Technology A S Page 97 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 7 Signal Description Panel Link FPDI TXC TXC Low voltage swing differential output clock pair For twisted pair cable with 100 characteristic balanced impedance TX0 TX0 Low voltage swing differential output data pair For twisted pair cable with 100 characteristic balanced impedance This pair transmits the flat panel signals PO 7 LP and FLM TX1 TX1 Low voltage swing differential output data pair For twisted pair cable with 100 characteristic balanced impedance This pair transmits the flat panel signals P8 15 TX2 TX2 Low voltage swing differential output data pair For twisted pair cable with 100 characteristic balanced impedance This pair transmits the flat panel signals P16 23 TxD RS422 Serial data output This differential signal pair sends serial data to the communication link The
29. ap _ ao e R 20000 COMPONENTSIDE _____ O ADOS J oD PR GND eee vo ro Eo EE ACK64 F60 E60 REQ64 EE vv INSIDE Technology A S Page 129 of 134 686LCD S 6861 CPU Board Version 1 4 0 8 Dec 1997 Note 1 The 3 3V supply can be used to power 3 3V adapter cards However signalling level has to 5V The 3 3V supply is not available default in the connector Note 2 Signals used for JTAG testing to perform Boundary Scan are not supported Note 3 The system does not support PCI cacheable memory 6 2 2 Signal Description PCI interface The PCI pin definitions are organized in the functional groups A symbol at the end of a signal name indicates that the active state occurs when the signal is at a low voltage When the symbol is absent the signal is active at a high voltage SYSTEM PINS CLK Clock provides timing for all transactions on PCI and is an input to every PCI device All other PCI signals except RST INTA INTB INTC and INTD are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge PCI operates at 33 MHz and in general the minimum frequency is 0 Hz Reset is used to bring PCI specific registers sequencers and signals to a co
30. shown below Insert Disk e Please insert the disk labeled Windows 95 CD ROM and then click OK Insert the disk CD ROM and click button An entry of the directory for the files may then be required Copying Files x The netapi dll on Windows 95 CD ROM ces could not be found Cancel Insert Windows 95 CD ROM into the drive selected below and click OK Skip File Copy files from Details After typing path name click OK button 9 To complete the installation reboot the computer by clicking the Yes button in the window shown below System Settings Change To finish setting up your new hardware you must restart your computer Wt Do you want to restart your computer now 10 After the restart the network adapter should be installed Protocols clients etc may now installed for the network in use Further configuration of the adapter may be made in the Advanced section of the driver properties These options may be accessed through the Network icon in the control panel Select the network adapter click the Properties button and select the Advanced tab The options available are described in the chapter on driver options 6 1 2 Windows NT 4 0 Ethernet installation A driver for the AMD Ethernet controller on the board is included in the Windows NT 4 0 distribu tion The driver for this adapter is denoted
31. w w N N N N N E gt j GND SA4 3 12 GND 1 4 3 12 SD15 DACK2 SD14 IRQ3 SD13 IRQ4 SD12 1205 5011 IRQ6 SD10 IRQ7 2 gt 2 gt 2 6 n z al tri E 5 5 N N N N N gt gt gt gt N N N N N 2 a E ON a N N N gt 3 12 SYSCLK gt R 20 3 12 1 4 3 12 REFRESH MEMW DRQI SMEMR 1 LA17 DRQ3 LA18 DACK3 19 IOR LA20 IOW LA21 MEMR LA22 MEMW LA23 N SBHE 12V gt 1 E 1 w E 3 12 gt 112 ies ON E ON 12 w 2 3 12 3 12 3 12 3 12 3 12 3 12 3 12 3 12 5 gt gt N gt N ER a Q n n Nn IE oo gt 5 Z 95 e SIAS Q gt E NJN JU gt SIO Dlx N N N N N N res EUN Sax Sa a
32. 0 8 December 1997 7 6 Power Connector PWRCON Pull PIN Pull Note U D Ioh Iot Type Signal Signal Type Ioh Iot U D Note 2 4 GND 5 0 L6 3 Eaa o Note 1 12 DC is required on board if 12 V Solid State Disk Module is used 2 12 V DC is not used on board but only fed to the PC104 and PC AT connectors 3 The 5V DC supply MUST be within 3 measured on the Power Connector If excessive cable lengths are used the supply voltage should be increased to account for this INSIDE Technology A S Page 77 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 7 Serial Port 1 Serial Port 1 is a software selected multi protocol interface port which is able to operate in RS232 5422 or RS485 mode Due to the different signal levels used in each mode the port will be disabled at power up During the BIOS initialisation the port will be set to the mode selected by the user in the BIOS setup menu and the port will be enabled With BIOS defaults loaded the port will remain disabled until the user has selected mode in the BIOS setup menu Warning Do not select a mode different from the one used by the connected peripheral as this may damage CPU board and or peripheral The transmitter drivers in the port are short circuit protected by a thermal protection circuit The circuit disables the drivers when the die temperature reach 150
33. 1 4 0 8 December 1997 Function 23h Setup GPIO s This function allows the user to control the definitions on the GPIO pins could be used in e g a multi drop application The states are only changed dynamically when booting next time the definition will be overwritten by the CMOS setup values Input AL 23h AH Port definition GPIOO in bit 0 of AH where 1 s present an input state Function 30h Set the default display contrast Sets the default contrast level for the connected LCD panel This feature is useful only if the Flat Panel Utility Module FPUM is present Input AL 30h AH 8 bits value 00 is lowest contrast OFFh highest Function 31h Read the default display contrast This function reads the previous contrast value written by function 30h This feature is useful only if the Flat Panel Utility Module FPUM is present Input AL 31h Output The value read Function 32h Turn on backlight This feature is useful only if the Flat Panel Utility Module FPUM is present Input AL 32h Function 33h Turn off backlight This feature is useful only if the Flat Panel Utility Module FPUM is present Input AL 33h INSIDE Technology A S Page 29 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 System Resources 5 1 1 Architecture Functions and External connections CPU PROCESSOR BUS EXTERNAL PCI CONN YU
34. 124 5 1 Installing Device Driver for DOS 124 5 2 Installing Device Driver for Windows 3 41 124 5 3 Installing Device Driver for Windows 95 1 2 11 11 seen 124 5 4 Installing Device Driver for Windows 2 sosta 124 6 CONNECTOR DEFINITIONS 126 6 1 SCSE Interface T E 126 6 1 1 68 Wide Internal and External SCSI 0 126 6 1 2 50 pin Internal SCSI connector 1 11 1 eee eese eee esee ette setenta tone toss 127 6 1 3 Signal Description P 128 6 2 PCI Interface 129 6 2 1 PCIE Edge COnnDector e ren ertt eti urn Ule en D usen iss pte 129 6 22 Signal Description e Uie n RR UIN RE REA ei 130 7 MEASUREMENT 5 3 33 repr nena nnne kane gu sre 134 INSIDE Technology A
35. 1516 eee 8 co 10 j co Gnd Sense PWR 23 24 5 26 27 28 o0 MN oe ATN OC 1 0 0 Gnd 1 1 11 c 9 1 Ee Note 1 Active Termination 110 Typical pull up to Termpwr Note 2 Termpwr supplied through Schottky diode to prevent backflow of power INSIDE Technology A S Page 127 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 6 1 3 Signal Description DATA DB 0 DB 7 SCSI Low Byte Data Lines Used for 8 bit transfers while DB 8 DB 15 are floated The SCSI Data Lines DB O DB 15 drive the ID during Arbitration and Selection and command and data information as well as status and messages DB 8 DB 15 SCSI High Byte Data Lines Used with Low Byte for 16 bit transfers COMMAND DB PL SCSI Low Byte Parity This bit provides odd parity for DB 0 DB 7 DB PH SCSI High Byte Parity This bit provides odd parity for DB 8 DB 15 Floated for 8 bit transfers C D Command Data This control line is received when in Initiator mode or driven when in Target mode It indicates Command or Mes
36. 1997 If an existing undesired network adapter is installed it can be removed by clicking the Remove Button 5 Click the Add Adapter button to install the driver for the network adapter This brings you to the screen below Add Network Adapter Select a Network Adapter to Install FF Unlisted or Updated Network Adapter 3Com EtherLink 16 3Com EtherLink or 8 16 bit 3Com EtherLink EtherLink MC Advanced Micro Devices 2100 1500 Amplicard 210 6 From the list of adapters select the line with the text Unlisted or Updated Network Adapter and click the OK button 7 Driver information now has to be read In the Install driver dialogue box enter the directory of the files for the driver i e a WFW311 and click OK The dialogue box is shown below Install Driver Insert unlisted updated or vendor provided network driver disk in AAWFW311 8 Accept the choice of Ethernet adapter for 686LCD S in the list by clicking the OK button as shown below Unlisted or Updated Network Adapter Network Adapters E Ethernet adapter for 686LCD S CPU Board 3 Microsoft NetBEUI IPX SPX Compatible Transport with NetBIOS Set Default Protocol Default Protocol Microsoft NetBEUI INSIDE Technology A S Page 61 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 10 Clic
37. 78xx PCI NT from the list and click Install Reboot the computer for the effects to take effect go If the driver you are updating controls the boot host adapter from which Windows NT loads you must update the device driver in two locations because Windows NT boots in a two stage process the Windows NT device driver directory i e winnt system32 drivers aic78xx sys and c ntbootdd sys In the first stage of booting no software configuration is available and Windows NT loads the device driver from the file c ntbootdd sys Therefore when you perform the steps described above to update a driver you must also explicitly copy the aic78xx sys driver to c ntbootdd sys 1 Click the Command Prompt icon in the Programs Menu 2 Switch to the root directory of c 3 Since the c ntbootdd sys file is system hidden and read only you must use a attribute change program to disable the hidden and read only attributes so that the files can be modified To disable the attributes type attrib ntbootdd sys r h s 4 To copy aic78xx sys device driver to ntbootdd sys type copy systemroot system32 drivers aic78xx sys ntbootdd sys 5 change the attributes of the ntbootdd sys back to the original type attrib ntbootdd sys r h s INSIDE Technology A S Page 125 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 6 Connector Definitions 6 1 SCSI Interface 6 1 1 68 Pin Wide Internal and Exter
38. AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL OF THE GENERAL MANAGER OF INSIDE Technology A S As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labelling can be reasonably expected to result in significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 1 INTRODUCTION seisieisccccsaiicasccasscntscatacntacatsciacatacatasetavatavataveiavetavatavetivedssedaveisveissetasedis 1 2 SYSTEM SPECIFICATION SHORT FORM ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 2 2 1 System specification Main data 1 Lee Leere eere eere ee ee eese eese e eese e ees tete sete 3 3 5 4 AMIBIOS SETUP sea ek nun En RV EXR Ex RYE NR Rx RR YR RN RR NR Ru RR NR Ru RR NR Ru RE RR RR 6 41 AMIBIOS Setup Main Menu eoe
39. All disks All removable media drives supported by the BIOS are treated as hard disk drives Disabled No removable media drives are treated as hard disk drives In this situation software drivers are needed because the drives are not controlled by the BIOS Note Do not remove media from a removable media drive if it is under BIOS control Set this option to Disabled and install a removable media device driver Display CTRL A during BIOS initialisation This option determines whether the Press Ctrl lt A gt for SCSISelect Utility message appears on the screen The default setting is Enabled BIOS Support for Bootable CD ROM This option determines whether the host adapter BIOS provides support for booting from a CD ROM drive The default setting is Enabled BIOS Support for Int 13 Extensions This option determines whether the host adapter BIOS supports disks with more than 1024 cylinders The default setting is Enabled INSIDE Technology A S Page 122 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 4 2 SCSI Disk Utilities To access the SCSI disk utilities select the SCSI Disk Utilities option from the menu that appears after starting SCSISelect Once the option is selected SCSISelect immediately scans the SCSI bus to determine the devices installed and displays a list of all SCSI IDs and the devices assigned to each ID Format Disk This utility allows you to perform a low level format on a
40. An external primary cell battery can be connected between this pin and GND The battery will not be recharged from the on board charging circuit The battery voltage should be within the range 2 5 4 0 V DC Typical current is 1 VCC VTR 5 V DC supply output for connection to LEDs or switches No more than 100 mA DC may be drawn from this pin Alternately this pin could be used as trickle supply input for the Smart Power Control logic The requirement for this purpose is 5 V DC 2 mA PWRON Active low output signal that could be used to turn power supply ON The signal will go low when BUTIN is pulsed high or a RTC Alarm wakeup event occur BUTIN This active high input signal is a part of the Smart Power Control logic and could be connected to an external Power On button The signal is internally debounced INSIDE Technology A S Page 85 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 10 Printer Port Connectors 7 101 Pin Header Printer Port Connector JPLPT Pull PIN Pull Note U D Ioh Iol Type Signal Signal IO Ioh Iol U D Note 4K7 12 4 OCO 2 1224 4 7 3 4 _ 1224 I Pp 487 1224 7 467 GND eee POS 13 14 Ee kita GND
41. Channel 1 10 Channel 2 11 Channel 3 DMA Channel Mode Register 000Bh PCI DMA channel 0 3 write mode register Bits 7 6 Transfer Mode select Demand mode Single mode Block mode Cascade mode Address increment Address decrement Disable auto initialization Enable auto initialization Select type of operation Verify operation Write to memory Read from memory Reserved Channel select Channel 0 Channel 1 Channel 2 Channel 3 Misc DMA 000Ch ws DMA 1 Clear byte pointer flip flop Command enabled with a write to the I O port address Lm TON DMA 1 Master Clear Register Same effect as HW reset Command enabled with a write to the port address Mos GN RUM DMA 1 Clear Mask Register Enables acceptance of DMA requests for all four channels Command enabled with a write to the port address 000Fh DMA 1 Mask Register read write all mask bits Bits 7 4 Reserved Must be 0 Channel Mask Bits Bit3 Disable ch 3 DREQ Enable ch 3 DREQ Bi Disable ch 2 DREQ Enable ch 2 DREQ Bi Disable ch 1 DREQ Enable ch 1 DREQ Bi Disable ch 0 DREQ Enable ch 0 DREQ 0020h 0021h are used by the 8259 compatible Programmable interrupt controller 1 by the 8259 compatible Programmable interrupt controller 1 Int 1 Control 0020h PCI ISA Initialization Command Word 1 Register Set Bit 4 to 1 to access ICWI Bit 7 5 000 ICW OCW select These bits should be 000 when programming the PIIX Bi 0 Must be 0 during writes to OCW2 and OCW
42. Confg 8C 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg A0 00000000 Confg A4 00000000 Confg A8 00000000 Confg AC 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg BC 00000000 Confg 00000000 Confg C4 00000000 Confg C8 00000000 Confg CC 00000000 Confg DO 00000000 Confg D4 00000000 Confg D8 00000000 Confg DC 00000000 Confg EO 00000000 Confg E4 00000000 Confg E8 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000000 Confg FC 00000000 INSIDE Technology A S Page 54 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 6 Driver Installation 6 1 Driver installation for Ethernet Adapter 6 1 1 Windows 95 The preferred way to install the driver for the Ethernet controller is to use the plug and play system of Windows 95 The steps required for this installation procedure is described below 1 If a driver for the Ethernet controller is already installed this must be removed first This be done by the following steps Click the start button click on Settings and on Control panel to open the control panel Your display should now look as below possibly with different size and icons Control Panel File Edit View Help sil Control Panel fe 2 rt um m 0 Accessibility Add Remove ChipsCPL Da
43. Fail Safe default settings are all Ignore The Optimal settings are all Ignore except on IRQ12 and IRQ14 which are Monitor INSIDE Technology A S Page 17 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 2 5 PCI PnP Setup PCI PnP Setup options are displayed by choosing the PCI PnP Setup icon from the AMIBIOS Setup main menu All PCI PnP Setup options are described in this section e Plug and Play Aware OS Set this option to Yes if the operating system installed in the computer is Plug and Play aware AMIBIOS only detects and enables PnP ISA adapter cards that are required for system boot The Windows 95 operating system detects and enables all other PnP aware adapter cards Windows 95 is PnP aware Set this option to No if the operating system such as DOS OS 2 Windows 3 x does not use PnP You must set this option correctly or PnP aware adapter cards installed in your computer will not be configured properly The settings are No or Yes The Optimal and Fail Safe default settings are No PCI Latency Timer in PCI Clocks This option sets latency of all PCI devices on the PCI bus The settings are in units equal to PCI clocks The settings are 32 64 96 128 160 192 224 or 248 The Optimal and Fail Safe default settings are 64 PCI VGA Palette Snoop This option must be set to Enabled if any ISA adapter card installed in the computer requires VGA palette snooping When set to Enabled multiple VGA de
44. Fail Safe settings are 75 50 To activate a new selection the machine must be powered down Secure CMOS This feature gives the opportunity to save the contents of the CMOS in the flash providing a failsafe system independent of the battery state backup of CMOS memory The default setting is Disabled The CMOS will be stored in the flash when set to Activated and the setup is exit by Save changes and Exit e Ethernet Controller Here the Ethernet controller can be set On or Off The default settings are On By disabling the Ethernet controller the resources are freed e SCSI Controller This option can enable or disable the SCSI controller the settings are On or Off This setting is only valid on 686LCD MG boards have no meaning on S boards disabling the SCSI controller the resources are freed VGA Controller With this option the attached VGA device can be set to minimise the overall power consumption of the board when only one VGA device is connected By disabling the VGA controller the resources are freed To use an off board VGA controller the on board controller must be set to Off The default settings are On Display Type The possible settings of the display type are CRT only Panel only or CRT and Panel with default settings CRT only Notice that a CRT device is needed to change the BIOS settings for flat panel use or when the CMOS settings are lost Note that an erroneous choice can mean blank screen e
45. OK 11 Click OK The driver is copied and scanned 12 You must restart the computer for the changes to take effect Click Yes to restart your computer Click No to return to the system properties window 5 4 Installing Device Driver for Windows NT This section describes how to install the aic78xx sys driver at the same time you install NT 1 After initiating the installation select Custom setup when prompted 2 Windows NT Setup displays all recognised host adapters If no host adapters are installed Windows NT displays None Press S to configure additional SCSI adapters 3 From the list of additional SCSI adapters select Other and press Enter 4 Insert the Adaptec driver diskette in drive A and press Enter INSIDE Technology A S Page 124 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 5 The screen displays adapter drivers supported diskette Use down arrow to select Adaptec AHA 294x AIC78xx PCT NT and press Enter 6 Press Enter to continue the operating system setup To install the driver aic78xx sys on an existing NT installation or to update the driver 1 Start Windows NT 2 Enter the Control Panel 3 Double click on SCSI Adapters The Adaptec 2940 AIC 78xx controller should now be seen 4 Click the Drivers tab Click Add Click Have disk and insert Adaptec driver disk in A Enter a winNT as the location Select the Adaptec AHA 294x AIC
46. Port is not Auto or Disabled The settings are 5 or 7 where 7 is the default Optimal and Fail Safe setting Parallel Port DMA Channel This option is only available if the setting for the Parallel Port Mode option is ECP and the On Board Parallel Port option is not Auto or Disabled The settings are DMA channel 0 or 3 The default settings are 3 On Board Speaker Sets the speaker On Off Default settings are On General Purpose IO 0 Will be occupied by FPUM if module is present General Purpose IO 1 General Purpose IO 2 Will be occupied by FPUM if module is present General Purpose IO 3 Will be occupied by FPUM if module is present General Purpose IO 4 Can also be setup to indicate Low temp General Purpose 5 Can also be setup to indicate High temp General Purpose IO 6 Can also be setup to indicate Low current General Purpose IO 7 Can also be setup to indicate High current Each GP IO can be setup to one of the following Input Output low or Output high Default setting is Input If Output is selected the value in x indicate the startup state GP IO 4 7 also have an additional option this can be used to control the environment or indicate alarms with LED etc Low temp and Low current are determined by hardware and can not be changed e Watch Dog Timeout Action By setting this option to Reset a hardware supervision of the software is activated and the software will need
47. Windows 3 11 environment The experienced user may change this list by changing the inf file for the installation The values indicated are written to the LED register in the Am79C970A Ethernet controller See the data sheet for the controller for further details 6 1 42 10 Connection It is possible to force the Ethernet controller to use the 10Base T connection for the network This is done with the setting The Auto Detect setting will use auto detection to determine which socket to use This is the default setting INSIDE Technology A S Page 63 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 6 2 Driver installation for Display Adapter 6 2 1 Windows 95 The following steps will install a display driver for the Chips amp Technologies 65554 PCT display controller 1 Click the Start button select Settings and select Control Panel from the sub menu This should start the Control Panel as shown below Control Panel ojx File Edit View Help Add Remove ChipsCPL Date Time Hardware Programs 9 4 e Desktop Display Find Fast Fonts Internet Themes 9 3 Keyboard Microsoft Mall Modems Mouse Postoffice Mili adis 23 object s Display Properties BE Background Screen Saver Appearance Plus Refresh Settings Color palette
48. automatically Fail Safe You can load the Fail Safe AMIBIOS Setup option settings by selecting the Fail Safe icon from the Default section of the AMIBIOS Setup main menu The Fail Safe settings provide far from optimal system performance but are the most stable settings Use this option as a diagnostic aid if the system is behaving erratically 4 6 AMIBIOS Power On Self Test Every time the system is powered on AMIBIOS executes a power on self test In case of errors they are reported in one of two ways If the error occurs before the display device is initialised a series of beeps sound Beep codes indicate that a fatal error has occurred AMIBIOS Beep Codes are described in the table below If it beeps Then 1 2 or 3 times Re insert the memory SIMMs If the system still beeps replace the memory 6 times Try a different keyboard or replace the keyboard fuse if the keyboard has one 8 times There is an error on the Video adapter or the Video RAM 9 times The BIOS ROM chip is bad The system probably needs a new BIOS ROM chip 11 times Re insert the cache memory on the board it still beeps replace the cache memory 4 5 7 or 10 times Fatal error If the error occurs after the display device is initialised an error message is displayed INSIDE Technology A S Page 27 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 47 INSIDE Interrupts
49. be high Temperature Violation Action This option gives the user three choices for actions to be taken when the high temperature limit is reached as set in the previous option The choices are Nothing Speaker and CPU speed The default settings are Nothing If Speaker is selected the speaker will beep if a violation is detected If CPU speed is selected the CPU is clocked down e High Current Limit From PCB revision 20100192 686LCD MG boards and revision 20100164 686LCD S boards a current measuring circuit is included on board that measures the actual current to the fan supplied through the JPFAN connector The actual current is displayed in the Actual field in the BIOS setup The maximum limit for this current can be set by clicking on the right field The Low current limit is predefined to be 10mA and will also cause a violation The desired action is chosen in the next option When this limit is exceeded GPIO 7 can be setup to be high Current Violation Action This option gives the user two choices for actions to be taken when the high current limit is reached as set in the previous option The choices are Nothing and Speaker The default settings are Nothing If Speaker is selected the speaker will beep if a violation is detected Hint When making the adjustment for the high limits do not set the limit close to the normal operating temperature The trimming is aided by up and down arrows next to the measured value On Board ID
50. bit is received first Only this register function when DLAB is 0 03F8h PCI ISA wW Transmitter buffer register contains the character to be sent Bit 0 the least significant bit is send first Only this register function when DLAB is 0 R W Divisor latch LSB when DLAB is 1 Settings shown below 03F9h PCI ISA R W Divisor latch MSB when DLAB is 1 Settings shown below Desired Baud rate Divisor Used Divisor latch MSB Divisor latch LSB 50 2304 75 1536 110 1047 150 768 300 384 600 192 1200 96 2400 48 4800 9600 19200 38400 56000 115200 03F9h PCI ISA R W Interrupt enable register when DLAB is 0 Bits 7 4 xxxx Reserved 1 Modem status interrupt enable Bit 2 1 Receiver line status interrupt enable Bit 1 1 Transmitter holding register empty interrupt enable Bit 0 1 Received data available interrupt enable R Interrupt identification register information about a pending interrupt is stored here When the ID register is addressed the highest priority interrupt is held and no other interrupts are acknowledged until the microprocessor services that interrupt Bits 7 4 xxxx Reserved Bit 3 0 interrupts 0110 Receiver line status highest priority 0100 Received data available 1100 Character timeout indication FIFO mode only 0010 Transmitter holding register empty 0000 Modem status lowest priority wW FIFO control register Bits 7 6 Receive FIFO inte
51. control outputs are all on board controlled for secure power on off sequencing SHFCLK Shift Clock Pixel clock for flat panel data LP Latch Pulse Flat panel equivalent of HSYNC horizontal synchronisation FLM First Line Marker Flat panel equivalent of VSYNC vertical synchronisation M Multipurpose signal function depends on panel type VGA BIOS May be used as AC drive control signal or as BLANK or Display Enable signal GPIOO GPIO3 General Purpose Input Output signals Identical to signals in the Feature Connector JPFEAT May be reserved for INSIDE Technology use 2 Multipurpose output signal Depending on the BIOS setup of the JPLCD Pin 5 in the Inside Utilities menu this signal is used either as Inverted SHFCLK signal or the signal will follow the level of the GPIO2 signal in the JPFEAT connector ENVCC Enable VCC Signal to control the panel power on off sequencing A high level may be used externally to turn on the VCC 5 V DC or 3 3V DC supply to the panel ENVEE Enable VEE Signal to control the panel power on off sequencing A high level may turn on the VEE LCD bias voltage supply to the panel LCDVCC VCC supply to the flat panel This supply includes onboard power on off sequencing PCB Version 20100161 This supply will always be 5V DC Future PCB Versions The flat panel supply may be either 5 V DC or 3 3 V DC depending on the VGA BIOS or selection made in the BIOS setup Maximum external
52. control over the device s ability to generate and respond to PCI cycles INSIDE Technology A S Page 48 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Command Register Reserved Back to back transactions are only allowed to the same agent Allow master to perform fast back to back transactions to different agents Disable SERR driver Enable SERR driver Device does not do address data stepping Device does address data stepping Must be on to report parity errors Ignore parity errors Device must take normal action when a parity error occurs Device should treat VGA palette snooping like other accesses Palette snooping is enabled The device does not respond to palette register writes Memory Write must be used Memory Write and Invalidate command enabled Ignore Special Cycle operations Monitor Special Cycle operations Disable device from generating PCI accesses Allow device to act as a bus master Disable device response to Memory space accesses Allow device to respond to Memory space accesses Disable device response to I O space accesses Allow device to respond to I O space accesses 0 1 0 1 0 1 0 1 0 1 EC C dg C eS Status status register is used to record information for PCI bus related events Status Register Parity error detected SERR on device asserted Set by master device if transaction is terminated with Master Abort
53. detected and the remaining files will be copied This will be indicated by a dialogue box as the one shown below New Hardware Found PCI Ethernet Controller mS Select which driver you want to install for your new hardware C Do not install a driver Windows will not prompt you again Select from a list of alternate drivers Cancel 5 Click the OK button 6 An indication of the placement of the files is requested Enter the directory for the drivers A Win95 as shown below and insert the driver disk in the floppy drive and click OK Install From Disk x Insert the manufacturer s installation disk into _ ces the drive selected and then click OK EL Cancel Copy manufacturer s files from Y Browse 7 You may now select the driver Since there is only one driver and this is the one that is selected accept by clicking the OK button This dialogue box is shown below Select Device x N Click the that matches your hardware and then click OK If you don t know lt gt which model you click This list shows only what was found on the installation disk Models Ethernet adapter for B86LCD S CPU Board INSIDE Technology A S Page 56 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 8 Depending on the configuration a request for the windows disks or CD ROM may appear as
54. internal external or 15 standard wide internal external SCSI devices The default setting for the Host adapter is SCSI ID 7 which has the highest priority on the bus 8 bit devices should be given IDs lt 7 and 16 bit devices gt 7 The IDs must be set on the individual devices The Onboard SCSI host adapter supports SCSI Configured Automatically SCAM protocol which assigns SCSI IDs dynamically and resolves SCSI ID conflicts automatically at boot up If your system includes SCSI disk drives or other devices that support SCAM you do not need to manually assign SCSI Ids to these devices To enable SCAM support set the Plug and Play SCAM support option to enabled in the SCSI setup The cabling required is a 50 pin internal SCSI cable type A for connection of 8 bit devices to the onboard 50 pin universal header use only keyed connectors like AMP P N 1 746195 2 or equal For Wide SCSI devices a 68 pin internal external cable type P is used with a DB68HP connector AMP P N 786090 7 or equivalent The requirements regarding termination in the SCSI standards prescribe the use of active termina tion at the extreme ends of the SCSI bus Depending on how the 686MG board is connected the termination onboard should be asserted not asserted as shown in the following table The termination enabling disabling is handled automatically by a ground sensing onboard circuit detecting if one or both connectors are used To use 8 bit devices on the 68 pi
55. is set to a marking state on hardware reset when the transmitter is empty or when loop mode operation is initiated RxD Serial input This signal receives serial data from the communication link DTR Data Terminal Ready This signal indicates to the modem or data set that the on board UART is ready to establish a communication link DSR Data Set Ready This signal indicates that the modem or data set is ready to establish a communication link RTS Request To Send This signal indicates to the modem or data set that the on board UART is ready to exchange data CTS Clear To Send This signal indicates that the modem or data set is ready to exchange data DCD Data Carrier Detect This signal indicates that the modem or data set has detected the data carrier OE INSIDE Technology A S Page 79 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 7 3 DB9 Serial Port 1 Connector COM1 RS422 Mode Pull Pull Note 00 Ioh Iol Type e Signal Type Ioh Iol U D m 7 7 4 Signal Description Serial Port 1 COMI in RS422 Mode TxD Serial output This differential signal pair sends serial data to the communication link Data is transferred from Serial Port 1 Transmit Buffer Register to the communication link if the TxD line driver is enabled through the Serial Port 175 DTR signal Modem control register RxD Serial input This differential signal pair receives serial data from
56. load is 5V 1A or 3 3V 0 25A The level of the panel control signals P23 0 SHFCLK LP FLM M ENVCC and ENVEE will follow the panel supply selection VEE VEE supply or VEE control voltage This supply signal is included only if the CPU board is configured with a Flat Panel Utility Module FPUM The supply signal is power on off sequencing controlled INSIDE Technology A S Page 95 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 5 Signal Configuration Flat Panel Displays Mono Mono Mono Colour Colour STN SS 2 v e ii 9 12 16 8 bit bit i i X4bP o Un SHFCLK SHFCLK SHFCLK SHFCLK B00 i e a 8c pe mm cz mr Um Um Bire 085 URL ORD Drusi sors mrs tn 7e rever 7631 Re Gi Um sm ora enrow eror x om mum ROT mr wer 7575 qe SHFCLK 5 5 SHFCLK
57. may be performed in the advanced section of the driver properties This configuration can be changed by executing step 1 4 above click the button Setup and the button Advanced on the following window The driver options are described in the following chapter 6 1 4 Driver options In the advanced settings for the driver it is possible to make more detailed configuration for the Ethernet Adapter The options that may be configured are the following e Function of LED s on board Force use of 10Base T Connection These options are described in the following two chapters INSIDE Technology A S Page 62 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 6 1 4 1 LED Two LED s Light Emitting Diode is mounted on the PCB behind the RA45 socket Two colours are provided a red and a green LED These LED s may be used to provide information about the status and activity of the Ethernet Adapter The function of the LED s may be defined individually and may have one of the functions shown below Wfw311 OFF 0 disabled Turns off LED Jabber Heceive Polarity Indication of current receive polarity The LED will be on if the polarity of the signal is as expected not reversed Data Out Transmit activity on network Data In 54 Datta activityonnetwork For the Windows 95 environment names are used for the functions whereas values are used in the
58. mode supported by the IDE drive being configured INSIDE Technology A S Page 9 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Hard Disk Drive Types Table B MFM types Type Cylinders Write Landing Sectors Capacity Zone poe o Lx pee 612 2 128 612 USER DEFINED HARD DRIVE Enter user supplied parameters INSIDE Technology A S Page 10 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 2 2 Advanced Setup Advanced Setup options are displayed by choosing the Advanced icon from the AMIBIOS Setup main menu All Advanced Setup options are described in this section Quick Boot Set this option to Enabled to instruct AMIBIOS to boot quickly when the computer is powered on This option replaces the old Above 1 MB Memory Test Advanced Setup option The settings are Disabled AMIBIOS test all system memory AMIBIOS waits up to 40 seconds for a READY signal from the IDE hard disk drive AMIBIOS waits for 0 5 second after sending a RESET signal to the IDE drive to allow the IDE drive time to get ready again AMIBIOS checks for a lt Del gt key press and runs AMIBIOS Setup if the key has been pressed Enabled AMIBIOS does not test system memory above 1 MB AMIBIOS does not wait up to 40 seconds for a READY signal from the IDE hard disk drive If a READY signal is not received immediately from the IDE drive AMIBIOS do
59. peripheral controller as Floppy disk controller port 1 Depends on choice made in INSIDE setup R R 03F2h PCI ISA R W Floppy disk controller output register Bits 7 6 Reserved should be zeroes Bi Enable motor on floppy drive B Bi Enable motor on floppy drive A Bi Enable Interrupt and DMA for floppy drives Bi Controller reset Bi Reserved should be zero Bi Select floppy drive A Select floppy drive B 03F4h PCI ISA R Floppy disk controller status register Bi Data register is ready Bi Transfer from system to controller Transfer from controller to system Bi Non DMA mode Bi Floppy disk controller busy Bits Reserved Bi Drive B is busy Bi Drive A is busy 03F5h PCI ISA R W Floppy disk controller data register FIFO 03F7h PCI ISA R Digital input register Bit 7 n Diskette change line inverted Bits 6 0 nx7 These bits may be driven by the hard disk status register depending on configuration 03F4h 03F7h may be used by on board IDE controller as Primary IDE Control Block INSIDE Technology A S Page 43 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 03F8h 03FFh may be used by on board peripheral controller as Serial port 1 Depends on choice made in INSIDE setup R Receiver buffer register contains the received character Bit 0 the least significant
60. second which have already been realised by most hard disk manufactures as an extension to the SCSI 2 Fast and Wide Shown in the table is also the Ultra2 option which doubles the Ultra Bus speed by using low voltage differential transceivers LVD This rate is not possible for single ended and high power differential transceiver applications yet The SCSI standards supported by Inside Technology s 686MG board are the ones shown shaded in the table As the single ended and differential drivers cannot be mixed without resorting to expensive converters the board only supports single ended operation with its limitations in bus length The chart shows the corresponding bus length and maximum number of devices on a single SCSI line Both Asynchronous and Synchronous devices can be used SCSI standard Maximum Bus Length Meters Maximum number of Devices SCSI 1 Fast SCSI 1 Fast Wide SCSI 15 8 Ultra SCSI Ultra SCSI Wide Utra SCSI aaa INSIDE Technology A S Page 117 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 3 SCSI Installation Inside Technology s 686MG board provides a PCI to Ultra SCSI host adapter onboard with a Pentium computer The board utilise Adaptec s AIC 7880 chip for the SCSI operations and is supported major operating systems DOS Windows and NT The SCSI host adapter can handle up to 15 devices either 7 standard narrow internal and 8 standard wide
61. signals are hardwired from the Serial Port 1 connector pin 3 4 Data is transferred from Serial Port 1 Transmit Buffer Register to the communication link if the TxD line driver is enabled through the Serial Port 15 DTR signal Modem control register RxD RS422 Serial data input This differential signal pair receives serial data from the communication link The signals are hardwired from the Serial Port 1 connector pin 1 2 Received data is available in Serial Port 1 Receiver Buffer Register LCDVCC VCC supply to the flat panel This supply includes onboard power on off sequencing PCB Version 20100161 This supply will always be 5V DC Future PCB Versions The flat panel supply may be either 5 V DC or 3 3 V DC depending on the VGA BIOS or selection made in the BIOS setup Maximum external load is 1A The level of the panel link signals TX1 and TX2 will follow the panel supply selection VEE VEE supply or VEE control voltage This supply signal is included only if the CPU board is configured with a Flat Panel Utility Module FPUM The supply signal is power on off sequencing controlled INSIDE Technology A S Page 98 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 8 Flat Panel Utility Connector LCDADP The Flat Panel Utility Connector is designed for adaptation of a power supply module FPUM generating the necessary supplies for different flat panels Pull P
62. system memory read operations The settings are x222 x333 or x444 The Optimal and Fail Safe default settings are x333 Write Burst Timing This option specifies the access timings for DRAM system memory write operations The settings are x222 x333 or x444 The Optimal and Fail Safe default settings are x333 INSIDE Technology A S Page 14 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 e Fast RAS to CAS Delay Clocks This option specifies the length of a delay inserted between the assertion of the RAS and CAS signals The settings are 2 clocks or 3 clocks The Optimal and Fail Safe default settings are 3 LeadOff Timing This option sets the leadoff timings for system memory access The settings are 6 5 3 4 6 5 4 5 7 6 3 4 or 7 6 4 5 The Optimal and Fail Safe default settings are 7 6 3 4 Turbo Read Pipelining Set this option to Enabled to enable turbo read pipelining The settings are Enabled or Disabled The Optimal and Fail Safe default settings are Disabled Speculative LeadOff Set this option to Enabled to enable the speculative leadoff feature The settings are Enabled or Disabled The Optimal and Fail Safe default settings are Disabled Turn Around Insertion Set this option to Enabled to enable the turnaround insertion feature The settings are Enabled or Disabled The Optimal and Fail Safe default settings are Disabled Memory Address Drive Strength This option specifies th
63. the communication link Received data is available in Serial Port 1 Receiver Buffer Register RTS Request To Send The level of this differential signal pair output is controlled through the Serial Port 15 RTS signal Modem control register The RTS line driver is enabled through the Serial Port 178 CSE signal in INSIDE control register CTS Clear Send The level of this differential signal pair input could be read from Serial Port 175 CTS signal Modem control register INSIDE Technology A S Page 80 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 7 5 DB9 Serial Port 1 Connector COM1 RS485 Mode Pull PIN Pull Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note E LL por __ 1 ERE o oro 24K VOT CTS RTS ees ecce CET 7 _ xc 1 7 7 6 Signal Description Serial Port 1 COMI in RS485 Mode RxD TxD Bi directional data signal pair Received data is available in Serial Port 1 Receiver Buffer Register Data is transferred from Serial Port 1 Transmit Buffer Register to the communication line if the TxD line driver is enabled through the Serial Port 175 DTR signal Modem control register The data transmitted will simultaneously be received the i
64. upper limit Fan current exceeded lower limit CPU temperature exceeded upper limit CPU temperature exceeded lower limit External Request line input Low Line Reserved Reset type Power On Reset type Watch Dog 00F2h 5 PAL Version Register 5 Watch Dog Service 1 OOF4h OOFFh PCI ISA Reserved for Inside Technology Use 0100h 03FFh On board peripherals and PC AT PC104 Adapter boards 0170h 0177h may be used by on board hard disk controller for secondary 1 IDE port Depends on choice made in INSIDE setup The bit definitions for these addresses are the same as those for addresses 01FOh 01F7h 0170h 0171h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0177h 2 lt x INSIDE Technology A S Hard disk data register base port Hard disk 1 error register Hard disk 1 write pre compensations register Hard disk 1 sector count Hard disk 1 sector number Hard disk 1 number of cylinders low byte Hard disk 1 number of cylinders high byte Hard disk drive head register Hard disk 1 status register Hard disk drive 1 command register Page 39 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Description 01F 0h 01F7h may be used b
65. 0 8 December 1997 7 14 Ethernet connector Pull Ioh Iol Note Note 1 Shielded 10Base T cable with twisted transmitter and receiver pairs must be used Shield should be connected to connector house 7141 Signal Description Ethernet connector 10 TXD TXD Ethernet 10Base T differential transmitter outputs RXD RXD Ethernet 10Base T differential receiver inputs INSIDE Technology A S Page 102 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 15 Connector JPAUD Pull PIN Pull Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note vc o vx c 516 6 24 1 This signal is used for INSIDE Technology test purposes Do connect anything to this signal 7 15 1 Signal Description AUI Connector JPAUI IRTX Infrared transmitter data output The infrared module use the UART normally assigned for Serial Port 2 for IrDA modes Sir A Sir and ASK IR IRRX Infrared receiver data input This pin is used when low data rates 1 25 Mbps are used This applies to the modes Sir A Sir B ASK IR IrDA HDLC Consumer and RAW IR IRFRX Infrared receiver data input This pin is used when high data rate 4 Mbps is used This applies to the IrDA mode IrDA4PPM DO DO Differential data output for Ethernet A
66. 00 000FFFFFh 64 KBytes AMI System BIOS ROM 00100000 1FFFFFFFh 511 MBytes Application Memory Accessable through EMM handler or as Extended memory FFFF0000 FFFFFFFFh 64 KBytes AMI System BIOS ROM mirrored Note 1 Used by the on board VGA controller if enabled 2 Location of BIOS are depending on Video BIOS ROM size e g if an external VGA card is used BIOS might be moved due to the PnP manager 3 Expanded Memory Managers EMM may require manual forced setting of the location of the EMM page while some handlers uncritically include the E0000 segment INSIDE Technology A S Page 31 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 3 The board incorporates a fully ISA Bus Compatible master and slave interface The drive capabilities allow for up to five external ISA slots to be driven without external data buffers The accessable I O area on the ISA bus is 64Kbytes with 16 address bits whereas the accessable Memory area is 16Mbytes with 24 address bits Certain I O addresses are subject to change during boot as PnP managers may relocate devices or functions The addresses shown in the table are typical locations I O Port Access Read Description Write 0000h 001Fh are used by the 8237 Compatible DMA Controller 1 DMA Current Address and Byte Count Registers DMA channel 0 Address bits 15 0 byte low byte followed by byte 1 000 1h PCI R W 0002h PCI R
67. 000 Confg 68 OOFOF200 Confg 6C 00000000 Confg 70 0000000C Confg 74 0 0 0000 Confg 78 000000F0 Confg 7C 00000000 Confg 80 000F0000 Confg 84 00000000 Confg 88 00000000 Confg 8 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg A0 01800009 Confg A4 00000000 Confg A8 0000000F Confg AC 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg BC 00000000 Confg 00000000 Confg C4 00000000 Confg C8 00000000 Confg CC 00000000 Confg DO 00000000 Confg D4 00000000 Confg D8 00000000 Confg DC 00000000 Confg EO 00000000 Confg E4 00000000 Confg 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000F10 Confg FC 00000000 Intel PIIX3 IDE interface Register dump for device 47 function 41 Confg 00 70108086 Confg 04 02800005 Confg 08 01018000 Confg 00002000 Confg 10 00000000 Confg 14 00000000 Confg 18 00000000 Confg 1C 00000000 Confg 20 0000FFA1 Confg 24 00000000 Confg 28 00000000 Confg 2 00000000 Confg 30 00000000 Confg 34 00000000 Confg 38 00000000 Confg 00000000 Confg 40 0000A307 Confg 44 00000000 Confg 48 00000000 Confg 4C 00000000 Confg 50 00000000 Confg 54 00000000 Confg 58 00000000 Confg 5C 00000000 Confg 60 00000000 Confg 64 00000000 Confg 68 00000000 Confg 6C 00000000 Confg 70 00000000 Confg 74 00000000 Con
68. 00000 Confg 7C 00000000 Confg 80 00000000 Confg 84 00000000 Confg 88 00000000 Confg 8C 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg A0 00000000 Confg A4 00000000 Confg A8 00000000 Confg AC 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg BC 00000000 Confg 00000000 Confg C4 00000000 Confg C8 00000000 Confg CC 00000000 Confg DO 00000000 Confg D4 00000000 Confg D8 00000000 Confg 00000000 Confg EO 00000000 Confg E4 00000000 Confg E8 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000000 Confg FC 00000000 AMD AM79C970 Ethernet Controller Register dump for device 10 function 0 Confg 00 00E4102C Confg 04 02800183 Confg 08 030000C2 Confg 0C 00000000 Confg 10 FD000000 Confg 14 00000000 Confg 18 00000000 Confg 1C 00000000 Confg 20 00000000 Confg 24 00000000 Confg 28 00000000 Confg 2 00000000 Confg 30 0000 Confg 34 00000000 Confg 38 00000000 Confg 00000000 Confg 40 00000000 Confg 44 00000000 Confg 48 00000000 Confg 4C 00000000 Confg 50 00000000 54 00000000 Confg 58 00000000 Confg 5C 00000000 Confg 60 00000000 Confg 64 00000000 Confg 68 00000000 Confg 6C 00000000 Confg 70 00000000 Confg 74 00000000 Confg 78 00000000 Confg 7C 00000000 Confg 80 00000000 C
69. 0377h 0378h 0379h 5 Reserved Reserved RW 5 W Alt Status Device control R PCI ISA Forward to ISA floppy 0378h 037Fh may be used by on board peripheral controller as Parallel port 1 PCI ISA Depends on choice made in INSIDE setup Parallel port 1 data Parallel port 1 status Bit 7 0 Busy Bit 6 0 Acknowledge INSIDE Technology A S Page 41 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 037Ah 5 037Bh of paper Printer is selected Error Reserved EPP timeout Parallel port 1 control Bits 7 6 00 Reserved Bi 0 Data port direction output data to printer Data port direction input data from printer Enable IRQ Select printer Initialize printer Bi Automatic line feed Bi Strobe Parallel port 1 EPP address port Bi Bi Bi W 037Ch 5 W Parallel port 1 EPP data port 0 5 037Dh W Parallel port 1 EPP data port 1 037Eh 5 W Parallel port 1 EPP data port 2 037Fh PCI ISA R W Parallel port 1 EPP data port 3 03B0h 03DCh may be used by on board Video controller Depends on choice made in INSIDE setup 03B0h 03BFh are used by on board Video controller in monochrome modes 03B0h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h
70. 03DFh are used by on board Video controller in color modes CRTC Index CRTC Data Chips amp Tech Extension index Chips amp Tech Extension data CGA mode register CGA color register Status register Feature control register Clear light pen FF ignored Set light pen FF ignored 03E8h 03EFh be used by on board peripheral controller as Serial port 3 Depends on choice made in INSIDE setup The bit definitions for these addresses are the same as those for addresses 03F8h 03FFh Receiver buffer register when DLAB is 0 Transmitter buffer register when DLAB is 0 Divisor latch LSB when DLAB is 1 Divisor latch MSB when DLAB is 1 Interrupt enable register when DLAB is 0 Interrupt identification register FIFO control register Line control register PCI ISA Modem control register 03EDh Line status register R W Modem status register 03EFh R W Scratch pad register 03F0h 03F 1h are used by SMC peripheral controller in Configuration Mode Configuration Mode is entered by two successive writes of 0x55h to the CONFIG port Configuration state is exited by a write of to the CONFIG port 5 9588227 03E8h 5 03 8 03 8 5 03E9h 5 03E9h 5 2 25485 2 03F0h 03F7h may be used by on board
71. 278h 027Fh may be used by on board peripheral controller as Parallel port 2 Depends on choice made in INSIDE setup The bit definitions for these addresses are the same as those for addresses 0378h 037Fh 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh PCI ISA R W Parallel port 2 EPP data port 3 INSIDE Technology A S Page 40 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 02E8h 02EFh may be used by on board peripheral controller as Serial port 4 Depends on choice made in INSIDE setup The bit definitions for these addresses are the same as those for addresses 03F8h 03FFh Receiver buffer register when DLAB is 0 Transmitter buffer register when DLAB is 0 Divisor latch LSB when DLAB is 1 Divisor latch MSB when DLAB is 1 Interrupt enable register when DLAB is 0 Interrupt identification register FIFO control register Line control register Modem control register Line status register 02 8 02E9h 02E9h 02EAh 02 02EBh 02ECh 02EDh 02 02 0288 0288 0288 02F9h 02F9h 02FAh 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 5 28 2254 2 Modem status register 5 R W Scratch pad register 02F8h 02FFh may be used by on board peripheral controller as Serial port 2 Depends on choice made in INSIDE setup The bit definitions for these addresses are the same as those for a
72. 3 1 Select ICW1 Edge Level Bank Select This bit is disabled Its function is replaced by the Edge Level Triggered Control Registers ADI Ignored for Single or Cascade Must be 0 ICW4 Write Required Must be set to 1 INSIDE Technology A S Page 33 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Write 000 001 010 011 100 101 110 111 Description Rotate in automatic EOI mode clear Non specific EOI No Action Specific EOI Rotate in automatic EOI mode set Rotate on non specific EOI command Set priority command Rotate on specific EOI command OCW2 Select Must be 00 to select OCW2 0020h PCI ISA Operational Control Word 2 Register Set Bits 4 and 3 to 00 to access OCW2 Bits 7 5 ate ati its 2 The interrupt request to which the command applies Operational Control Word 3 Register Set Bits 4 and 3 to 01 to access OCW3 Bit 7 Bit 6 5 0020h Reserved Must be 0 No Action Normal mask mode No Action Enter special mask mode Must be programmed to 01 to select No poll command Poll command Next I O read to irq controller is treated as highest priority request No Action No Action Read interrupt request register on next read of port 0020h Read interrupt in service register on next read of port 0020h IRQ and IS read to port 0020h following write to OCW3 Interrupt request register
73. 3 4 16 0 20 0 26 8 32 0 and 40 0MB ytes sec When disabling Wide negotiation in the SCSI Device Menu this default number is changed to 20 0 MBytes sec with the options of 5 6 7 8 10 13 4 16 0 and 20MB ytes sec If your device is a Ultra SCSI device you can use the maximum value of 40 Mbytes sec otherwise the transfer rate should be set to 20MB ytes sec If the host adapter is set not to negotiate for synchronous data transfers then maximum synchronous data transfer rate is the maximum rate the host adapter accepts from the device during negotiation e Enable Disconnect This option determines whether the host adapter allows the SCSI device to disconnect from the SCSI bus sometimes called Disconnect Reconnect Enabling disconnection allows the host adapter to perform other operations on the SCSI bus while the SCSI device is temporarily disconnected You should leave Enable Disconnect set to yes if two or more SCSI devices are connected to the host adapter If only one SCSI device is connected set Enable Disconnect to No to achieve slightly better performance The default setting is Yes Initiate Wide Negotiation This option determines whether the host adapter attempts 16 bit transfer Wide negotiation instead of 8 bit data transfer The effective transfer rate is doubled when 16 bit data transfer is used because the data path for Wide SCSI is twice the size of 8 bit SCSI The default setting is Yes for all devices Some 8 bit d
74. 4 IRQ6 m N ees gt N 5 3 e 5 to Q 1 The usage of these interrupts depends choices made in the INSIDE setup screen The interrupts are fully useable in PC AT or PCI bus as IRQA IRQD if the corresponding on board unit is disabled in the BIOS setup 2 These interrupt lines are managed by PnP handler and are subject to change during system initialisation 3 IRQ14 is routed directly from the IDE hard disk connector to bus Disabling the hard disk controller in the INSIDE setup screen may not release the interrupt line INSIDE Technology A S Page 46 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 5 DMA channel Usage The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven programmable channels The controllers are referenced DMA Controller 1 for channels 0 3 and DMA Controller 2 for channels 4 7 Channel 4 is by default used to cascade the two controllers Channels 0 3 are hardwired to 8 bit count by bytes transfers and channels 5 7 to 16 bit count by bytes transfers The onboard PIIX3 provides 24 bit addressing with the 16 least significant bits 15 0 in the Current register and the most significant bits 24 16 in the Page register DMA channel Note DRQO Available in PC AT bus DRQI Available in PC AT bus DRQ2
75. 86LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Document revision history 1 0 0 July 95 KEA CMU First preliminary version of manual created for the 686LCD S Board The manual contains preliminary connector signal descriptions 1 0 1 12 Dec 96 SJA Revised preliminary version Connector signal descriptions revised Specifications and Drawings updated Installation procedure added 1 1 0 29 Jan 97 PJA SST Revised preliminary version BIOS setup added Driver installation for Ethernet and VGA controller added 1 2 0 14 Mar 97 LJO Ethernet installation and Display installation for Windows NT 4 0 added 1 3 0 2 Jul 97 LJO PJA Addition about 686LCD MG added 686LCD S part corrected 8 Dec 97 PJA JLA BIOS Setup updated Resource map added INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 1 Introduction This manual describes the 686LCD S CPU Board made by INSIDE Technology A S Use of the manual implies a basic knowledge of PC AT hard and software This manual is focused on describing the 686LCD S CPU Board s special features and is not intended to be a standard PC AT textbook New users are recommended to study the short installation procedure stated in chapter 3 before switching on the power All configuration and setup of the CPU board is either done automatically or by the user in the
76. CD MG CPU Board Version 1 4 0 8 December 1997 7 11 1 Signal Description Floppy Disk Connector RDATA Read Disk Data active low serial data input from the floppy disk drive WDATA Write Disk Data active low serial data output to the floppy disk drive WGATEf This output signal enables the head of the selected disk drive to write to the disk This output signal enables motor in floppy disk drive This output signal enables the motor in floppy disk drive B DRVA Active low output signal to select floppy disk drive A DRVB Active low output signal to select floppy disk drive B SIDE 1 This output signal selects side of the disk in the selected drive DIR This signal controls the direction of the floppy disk drive head movement during a seek operation A low level request steps through centre STEP This output signal supplies step pulses to move the head during seek operations DENSELO 1 This output indicates whether a low data rate 250 300kbps at low level or a high data rate 500 1000kbps at high level has been selected TRKO Floppy Disk Track 0 active low input to indicate that the head of the selected drive is at track 0 INDEX Floppy Disk Index active low input indicates the beginning of a disk track WPT Active low input signal indicating that the selected drive contains a write protected disk DSKCHG Input pin that senses whether the
77. E This option specifies the channel used by the IDE controller on motherboard The settings are Disabled Primary Secondary or Both with default settings as Primary INSIDE Technology A S Page 24 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 3 Utilities The following icons appear in this section of the AMIBIOS main screen 431 Detect IDE 4 4 Security Three icons appear in this part of the AMIBIOS Setup screen e Supervisor Password e User Password and e Anti Virus Two Levels of Passwords Both the Supervisor and the User icons configure password support If you use both the Supervisor password must be set first The system can be configured so that all users must enter a password every time the system boots or when AMIBIOS Setup is executed using either or both the Supervisor password or User password 4 41 AMIBIOS Password Support The Supervisor and User icons activate two different levels of password security If AMIBIOS Setup has an optional password feature The system can be configured so that all users must enter a password every time the system boots or when AMIBIOS Setup is executed 4 4 2 Setting a Password The password check option is enabled in Advanced Setup by choosing either Always the password prompt appears every time the system is powered on or Setup the password prompt appears only when AMIBIOS is run The password is encrypted and stored in CMOS memory
78. Enabled The default setting is Disabled Reset SCSI Bus at IC Initialisation This option determines whether the SCSI bus is reset when the onboard AIC 7880 chip is initialised The default setting is Enabled Extended BIOS translation for DOS drives gt 1 Gbyte This option determines whether extended translation is available for SCSI hard disks with capacities greater than 1 GByte The default setting is Enabled The standard translation scheme for SCSI host adapters provides a maximum accessible capacity of 1 GByte To support drives up to 8 GBytes under MS DOS an extended translation scheme is included Extended BIOS Translation is used only with MS DOS 5 0 or above You do not need to enable this option if you are using another operating system such as Windows NT Host Adapter BIOS This option enables or disables the host adapter BIOS The default setting is Enabled If you are booting from a SCSI disk drive connected to the host adapter the BIOS must be enabled You should disable the host adapter BIOS if the peripherals on the SCSI bus for example CD ROM drives are all controlled by device drivers and do not need the BIOS Support Removable Drives under BIOS as fixed Disk This option controls which removable media drives are supported by the host adapter BIOS The default setting is Boot Only The following choices are available Boot only Only the removable media drive designated as the boot device is treated as a hard disk drive
79. IN Pull Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note 1 121 o BEIM N L en e 15 6 2K7 88 ENVEE 9 100 10 48 AOK 2 VEE GPIOO JO 24 eee 1 eee VCC 7 13 9 Signal Description Flat Panel Utility Connector LCDADP 0 2 3 General Purpose Input Output signals Identical to signals in the Feature Connector JPFEAT May be used to control DAC on adapted Flat Panel Utility Module FPUM Enable VCC Signal to adapted Flat Panel Utility Module FPUM to control the panel power on off sequencing A high level may be used externally to turn on the VCC 5 DC or 3 3V DC supply to the panel ENVEE Enable VEE Signal to adapted Flat Panel Utility Module FPUM to control the panel power on off sequencing A high level may turn on the VEE LCD bias voltage supply to the panel LCDVCC VCC supply from adapted Flat Panel Utility Module FPUM to the flat panel This pin may be used to boost the onboard LCDVCC switch in case of heavy load requirements VEE VEE supply output from adapted Flat Panel Utility Module FPUM The pin is connected to the JPLCD and FPDI connectors INSIDE Technology A S Page 99 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 10 Video Cap
80. MIBIOS The IRQs used by onboard I O are configured as PCI PnP The settings are PCI PnP or ISA EISA The Optimal and Fail Safe default settings are PCI PnP Reserved Memory Size This option specifies the size of the memory area reserved for legacy ISA adapter cards The settings are Disabled 16K 32K or 64K The Optimal and Fail Safe default settings are Disabled Reserved Memory Address This option specifies the beginning address in hex of the reserved memory area The specified ROM memory area is reserved for use by legacy ISA adapter cards The settings C0000 C4000 C8000 D0000 4000 28000 or DC000 The Optimal and Fail Safe default settings are 8000 Note that CO000h CAFFFh are used by Video BIOS ROM and CB000h D1FFFh by SCSI Bios Extension if enabled on MG boards INSIDE Technology A S Page 19 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 2 6 Peripheral Setup Inside Utility Peripheral Setup options are displayed by choosing the Peripheral Setup icon from the AMIBIOS Setup main menu All Peripheral Setup options are described in this section Processor Clock INT EXT This option should be set to the clock frequencies corresponding to the installed CPU The options are 75 50 90 60 100 50 100 66 120 60 133 66 150 60 166 66 or 200 66 The number before the slash is the Internal Processor Clock and the number after is the External Clock The Optimal and
81. Page 106 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 IOR This is an active low signal driven by the current master to indicate an I O read operation I O mapped devices using this strobe for selection should decode addresses SA15 0 and AEN Additionally DMA devices will use IOR in conjunction with to decode a DMA transfer from the I O device The current bus master will drive this line with a tri state driver IOW This is an active low signal driven by the current master to indicate an I O write operation I O mapped devices using this strobe for selection should decode addresses SA15 0 and AEN Additionally DMA devices will use IOR in conjunction with to decode a DMA transfer from the I O device The current bus master will drive this line with a tri state driver SMEMRz This is an active low signal driven by the permanent master to indicate a memory read operation in the first of system memory Memory mapped devices using this strobe should decode addresses SA19 0 only If an alternate master drives MEMR the permanent master will drive SMEMR delayed by internal logic The permanent master ties this line to VCC through a pull up resistor to ensure that it is inactive during the exchange of bus masters This is an active low signal driven by the permanent master to indicate a memory write operation in the first 1 of system memory Memory mapped devic
82. Panel Driver This option give the user a choice between 14 standard configured Chips amp Technologies panels Changing this setting will reset the Panel Interface setting to 3 3 V The Default and Fail Safe settings are 1024 768 STN This interface is only present if the display data block is not uploaded to flash Note that the display data block in this case V 1 00 can be updated independently of the other BIOS files If display data block is present together with BIOS release 110 306 627 or newer the following menu will appear INSIDE Technology A S Page 20 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Display module V1 00 Resolution Manufacturer Code 320 x 240 Standard x LCA4VEO2A X 640 X 480 Fujitsu 800 600 IBM 854 X 480 FPD 1024 X 768 Sharp 1280 X 1024 Goldstar Toshiba Technology Hitachi STN Mono Hosiden EL Mono Kyocera TFT Mono STN Color Optrex EL Color Planar Color Samsung Plasma Torisan Driver selection 05 Selections can be made either by keyboard with the keys Enter or simply by clicking the checkbox with the mouse When the 3 criteria are selected Resolution Technology and Manufacturer different Codes or NON will appear in the right side of the screen Simply select the exact display code according to the display The
83. S Page 114 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 Document revision history 1 0 0 Feb 97 First preliminary version of manual created for the 686MG Board The manual contains preliminary connector signal descriptions 2 July 97 Revised preliminary version Connector signal descriptions updated BIOS setup added SCSI Driver Installation added Revised version BIOS setup updated INSIDE Technology A S Page 115 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 1 Additional system specifications for 6861 Wide Ultra SCSI interface Supports operation with SCSI 1 Fast and Wide SCSI 2 and Ultra SCSI single ended Devices Maximum transfer rate of 40 MBytes second Automatic Active Termination depending on external internal connected devices Standard Wide SCSI Half Pitch DB68 connector and 50 pin universal header on board Upto 16 Devices on the SCSI Bus Supports the SCSI Configured Automatically SCAM protocol Supported by major operating systems DOS Windows and NT PICMG interface Compliant to the PCI 2 1 Specifications e Support Master capabilities for two PCI slots on passive backplanes Support for up to four PCI local bus slots INSIDE Technology A S Page 116 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 2 SCSI Standards To help understand the terminology of the many different SCSI
84. Technology A S Page 45 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 4 Interrupt Usage The onboard Intel provides an ISA compatible interrupt controller with functionality as two 82C59 interrupt controllers The two controllers are cascaded to provide 13 external interrupts Most of these are used by onboard devices but a few are available through the PC AT interface the feature port JPFEAT or as IRQA D on PCI bus The actual interrupt settings depend on the PnP handler the scheme below indicates the typical settings The shaded text is for 686LCD MG boards only Interrupt ote Used on board on DRAM parity errors and IOCHCHK signal activation Q Used on board for TIMER 0 interrupt Q Used on board for keyboard interrupt Used for cascading IRQ8 IRQI5 Used on board for serial port 1 or communication Device Used on board for serial port 2 or serial port 1 Might be used for on board printer port Used on board for floppy disk controller Q Might be used for on board printer port 8 Used on board for real time clock alarm Q9 Available in PC AT bus or on PCI bus as IRQA IRQD Used on board for Ethernet controller Used on board for SCSI controller Might be used for on board PS 2 mouse support Used on board for co processor support Used on board for hard disk controller Available in PC AT bus or on PCI bus as IRQA IRQD Z NMI IRQ
85. The interrupt number is selected in the INSIDE Utilities setup menu By loading the desired function number in the AL CPU register and generating a software interrupt with the INT X instruction the function is called X is the interrupt number specified in the Inside utility setup Some of the functions will require an additional value loaded in the AH register The software interrupt is used to control the following Function 00h Diagnostic call This call can be used to test whether the interrupt is setup correct Input AL 00h Output AL 5Ah Function 10h Enable displays This call enables or disables the CRT and Flat panel outputs Input AL 10h 00h Disable both CRT and Flat panel outputs 01 Enable CRT and disable Flat panel output 02h Disable CRT and enable Flat panel output 03h Enable both CRT and Flat panel outputs Function 20h Write to general purpose digital outputs This function is used to access the general purpose pins GPIO7 0 in the JPFEAT connector Input AL 20h The port value to be written GPIOO in bit 0 of AH Function 21h Read back from general purpose digital outputs This function is used to read back values directly on the GPIO pins Input AL 21h Output The read port value GPIOO in 0 of Function 22h Same as function 21h for compatibility reasons INSIDE Technology A S Page 28 of 134 686LCD S amp 686LCD MG CPU Board Version
86. Used on board for floppy disk controller DRQ4 QUsedforcascadimg jAvaiablein PC AT bus DRQ6 jAvaiablein PC AT bus _ DRQ7 j Availablein PC ATbus Note 1 The usage of these DMA channels depends choices made in the INSIDE setup screen The DMA channels are fully usable in PC AT bus if the corresponding on board unit is disabled in the setup screen INSIDE Technology A S Page 47 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 6 PCI Resources The onboard Intel TXC Host to PCI bridge supports up to four general purpose masters by the integrated arbiter For external use on the PCI connector on 686LCD MG boards are two master channels located in slot 1 and 2 in a standard PCI Local Bus PICMG backplane Up to 4 slots are supported in passive backplanes 5 6 1 PCI Configuration Space The PCI bus onboard the 686LCD board is a 32 bit wide bus with multiplexed address and data lines compliant to the PCI Local Bus Specification Revision 2 1 The following onboard functions VGA Controller Ethernet Controller SCSI Controller PCI ISA Interface PCI Bus Master Registers System Power Management Registers and USB Registers are setup through PCI configuration Space Each function has a separate Configuration space of 256 Bytes configuration registers intended for configuration initialization and certain types of error handling At boot up the c
87. User s Manual 686LCD S amp 686LCD MG CPU Board Ver 1 4 0 8 December 1997 INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Copyright Notice Copyright 1996 INSIDE Technology A S ALL RIGHTS RESERVED No part of this document may be reproduced or transmitted in any form or by any means electronic or mechanical for any purpose with out the express written permission of INSIDE Technology A S Trademark Acknowledgement Brand and product names are trademarks or registered trademarks of their respective owners Disclaimer INSIDE Technology A S reserves the right to make changes without notice to any product including circuits and or software described or contained in this manual in order to improve design and or performance INSIDE Technology assumes no responsibility or liability for the use of the described product s conveys no license or title under any patent copyright or mask work rights to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Applications that are described in this manual are for illustration purposes only INSIDE Technology A S makes no representation or warranty that such application will be suitable for the specified use without further testing or modification Life Support Policy INSIDE Technology s PRODUCTS ARE NOT FOR USE
88. V PORT USB CONN IDE CONN AT PC104 CONN SERIAL PORTS INSIDE AT BUS SSD PARALLEL FLASHDISK PORT gt 2 p Z CONN SMC WATCH DOG PAL IO CNTRL FLOPPY DISKCONN TEMPERATURE KEYBOARD SENSOR CONN FAN CURRENT PS2 MOUSE MONITORING CONN FEATURE SPEAKER PORT INSIDE Technology A S Page 30 of 134 5 20 Memory 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 The following table indicates memory map for the 686LCD board The address ranges specifies the runtime code length Address Range Length Description Note 00000000 000002FFh 768 Bytes BIOS Interrupt Vector Table 00000300 000003FFh 256 Bytes BIOS Stack Area 00000400 000004FFh 256 Bytes BIOS Data Area 00000500 0009FFFFh 639 KBytes Application Memory Used by the operating system device drivers and TSRs 000A0000 000BFFFFh 128 KBytes Video memory page 1 000C0000 000C9FFFh 40 KBytes Video BIOS ROM 1 000CA000 000CE7FFh 18 KBytes Occupied by SCSI BIOS extension if enabled or the Ethernet 2 BIOS extension if enabled in the given order 000CE800 000D27FFh 16KBytes Occupied by Ethernet BIOS extension if both SCSI and Ethernet 2 are enabled 000D2800 000DFFFFh 54 KBytes Available for external ROM BIOS Extensions 3 000E0000 000EFFFFh 64 KBytes INSIDE Technology BIOS Extension AMI System 3 000F00
89. W 0003h PCI R W 0004h PCI R W 0005h PCI R W 0006h PCI R W 0007h PCI R W DMA Status and Command Register Ch 0 3 0008h PCI R DMA channels 0 3 status register Bi Channel 3 request Bi Channel 2 request Bi Channel 1 request Bit 4 Channel 0 request Bit 3 Terminal count on channel 3 Bit 2 Terminal count on channel 2 Bit 1 Terminal count on channel 1 Bit 0 Terminal count on channel 0 0008h DMA channels 0 3 command register Bit 7 0 sense active low DACK sense active high DREQ sense active low DREQ sense active high Late write selection Extended write selection Fixed priority Rotating priority Normal timing Compressed timing Enable controller Disable controller Disable memory to memory transfer Enable memory to memory transfer Reserved 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 DMA Request Register 0009h PCI DMA write request register Bits 7 3 0 Reserved Must be 0 Bit 2 0 Resets individual DMA Channel Service SW Request 1 Sets the request bit Bit 1 0 00 DMA Channel 0 select 01 DMA Channel 1 select 10 DMA Channel 2 select 11 DMA Channel 3 select INSIDE Technology A S Page 32 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Description DMA Mask Register 000Ah PCI DMA channel 0 3 mask register Bits 7 3 Reserved Must be 0 Bit2 0 Enable DREQ for the selected channel 1 Disable DREQ for the selected channel Bit 1 0 Channel select 00 Channel 0 01
90. You are prompted for a 1 6 character password You can either type the password on the keyboard or select each letter of the password one at a time using the mouse The password does not appear on the screen when typed Make sure you write it down If you forget it you must drain CMOS memory and reconfigure If You Do Not Want to Use a Password Press lt Enter gt when the password prompt appears 4 43 Changing a Password Select the Supervisor or User icon from the Security section of the AMIBIOS Setup main menu Enter the password and press lt Enter gt The screen does not display the characters entered After the new password is entered retype the new password as prompted and press lt Enter gt If the password confirmation is incorrect an error message appears If the new password is entered without error press lt Esc gt The password is stored in CMOS memory after AMIBIOS completes The next time the system boots a password prompt appears if the password function is present and enabled Remember the Password Keep record of the new password when the password is changed If you forget the password you must erase the system configuration information in CMOS memory This can be done by pressing Del during boot or taking the battery out for 5 minutes _ INSIDE Technology A S Page 25 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 44 Anti Virus When this icon is selected from the Security
91. be read 004 1h PCI ISA R Programmable timer counter 1 status byte format register Equivalent to counter 0 byte 0041h US Counter 1 Access Ports register Equivalent to counter 0 byte 0042h PCI ISA Programmable timer counter 2 status byte format register Equivalent to counter 0 byte 0042h PCI ISA Counter 2 Access Ports register Equivalent to counter 0 byte Timer Counter 1 Command Mod 0043h 5 W Programmable timer mode port Control word register for counters 0 1 and 2 Bits 7 6 00 Counter 0 select 01 Counter 1 select 10 Counter 2 select 11 Read Back Command 00 Counter latch command 01 R W counter bits LSB only 10 R W counter bits MSB only 11 R W counter bits LSB first then bits MSB Counter Mode Selection 000 Mode 0 Out signal on end of count 001 Mode 1 Hardware retriggerable one shot Mode 2 Rate generator divide by n counter X11 3 Square wave output 100 Mode 4 Software triggered strobe 101 Mode 5 Hardware triggered strobe 0 Binary counter is 16 bits count max 2 1 Binary code decimal BCD counter count max 24 16 Read Back Command 0043h Read Back Command for counters 0 1 and 2 Must follow a write to Control word register The requested count or status may be read by access to the counter s I O address Bit 7 6 00 Read Back Command Bit 5 Current count will be latched Current count will not be latched it 4 Status of selected counters will be latched Statu
92. ble drive designator If for example a hard disk is attached as C the SSD will be assigned D INSIDE Technology A S Page 21 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 The Optimal and Fail Safe settings are Off The Solid State Disk can be used as both B C and Last DRV under DOS To use the Disk under Windows 95 the disk must be set as C or Last DRV To use EMM handlers remember to exclude the E0000 segment or the Solid State Disk may be inaccessible The SSD drive is not supported under Windows NT e SSD Prepare Option is used for preparing the Solid State Disk The options are Off or Activated If Activated the SSD will be low level formatted at next boot up and are hereafter automatically reset to Off The Optimal and Fail Safe settings are Off On Board FDC This option enables the floppy drive controller on the motherboard The settings are Auto Enabled or Disabled The Optimal and Fail Safe default settings are Auto On Board Serial Port 1 This option enables serial port 1 on the motherboard and specifies the base I O port address for serial port 1 The settings are Auto Disabled 3F8h 2F6h 3ESh or 2E8h The Optimal default setting is 3F8h The Fail Safe default setting is Auto Serial Port 1 Interface This option is only available if the On Board Serial Port 1 is not Disabled The possible settings for the serial interface standard are Disabled RS232 RS422 or RS485 Notic
93. board PCI IDE controller The settings are Disabled INTA INTB INTC INTD or Hardwired The Optimal and Fail Safe default settings are Disabled Off board PCI IDE Secondary IRQ This option specifies the PCI interrupt used by the secondary IDE channel on the off board PCI IDE controller The settings are Disabled INTA INTB INTC INTD or Hardwired The Optimal and Fail Safe default settings are Disabled INSIDE Technology A S Page 18 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 DMA Channel 0 DMA Channel 1 DMA Channel 3 e D D MA Channel 5 MA Channel 6 DMA Channel 7 These options specify if the named DMA channel is available for use on the ISA EISA bus or for PnP Plug and Play The settings SA EISA or PnP The Optimal and Fail Safe default settings are PnP e IRQ4 5 IRQ7 IRQ9 IRQ10 14 IRQ15 These options specify the bus that the named interrupt request lines IRQs are used on These options allow you to specify IRQs for use by legacy ISA adapter cards These options determine if AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS configurable devices The available IRQ pool is determined by reading the ESCD CMOS memory If more IRQs must be removed from the pool the end user can use these PCI PnP Setup options to remove the IRQ by assigning the option to the SA EISA setting Onboard I O is configurable by A
94. ce deasserts its INTx signal PCI defines one interrupt line for a single function device and up to four interrupt lines for a multi function device or connector For a single function device only INTA may be used while the other three interrupt lines have no meaning INTA Interrupt A is used to request an interrupt INTB Interrupt B is used to request an interrupt and only has meaning on a multi function device _ INSIDE Technology A S Page 132 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 INTCH Interrupt C is used to request an interrupt and only has meaning on a multi function device INTD Interrupt D is used to request an interrupt and only has meaning on a multi function device Since most devices are single function and therefore can only use INTA on the device the interrupts are distributed evenly among the interrupt controller s input pins For the device in the PCI slot to function the routing in the passive backplane has to follow the specifications as outlined in the PCI ISA Card Edge Connector proposal for Single Board Computer Revision Number 2 0 October 10 1994 The table below specify the connection from Inside s PCI Card Edge Connector to the PCI expansion connectors PCI Connector 1 PCI ISA Connector PCI Connector 2 PCI ISA Connector Signal Pin Signal Pin PCI Connector 3 PCI ISA Connector PCI Connector 4 PCI ISA Connector The 3 slotted PICMG backp
95. ce supported by NS16550 comp UART s x Parallel printer interface Centronic ECP EPP mode EIDE hard disk interface Floppy drive interface 2 x 360kB to 1 44MB Standard VGA Controller with Flat Panel Port On board protection Peripheral interfaces intended for connection to exter nal equipment are protected with EMI Suppression filters System Bus Connectors 98 pin PC AT bus edge connector PC104 connector On board Bus PCI for Ethernet VGA EIDE etc Power Supply 5 12 Volt 3 Can operate at 5 volt only 3 6 Volt Battery Lithium Power Consumption 10 20W typical Dependent on processor type Environmental Conditions 0 C 60 C operating temperature forced cooling 10 90 relative humidity non condensing Dimensions 190 9 mm x 122 9 mm x 20 0 35 0 mm 686LCD S 249 7 mm x 122 9 mm x 20 0 35 0 mm 686LCD MG INSIDE Technology A S Page 4 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 3 Installation procedure 1 Turn off the power supply 2 Insert the system BIOS if not already installed Socket pin 1 is located nearest to the Cache socket The chip must be placed so eventually unconnected socket pins are nearest the Cache socket 3 Insert the DRAM be careful with the orientation 4 Insert Cache Module if applicable 5 Install the processor be careful with the orientation pin 1 closest to the center of the Cache socket 6 Mount the Fan on the top of
96. ceo sia ea seva an np ru Veo Eo P RE FEN EE n toT E Fera YU 7 13 Default 7 4 2 8 22 1 Standard aaa de see 8 45225 Advanced eti tois imd eve et doe ieiuno ts 11 ADS Chipset a 14 424 Power Management 2 PRENNE KE eR 16 429 18 4 2 6 Peripheral Setup Inside Utility see oe ree hood 20 43 EE 25 2 3 Iota bee oq 25 42 IQ 25 441 AMIBIOS Password Support oer 25 q42 a PASS WOU esi ud uh oe hene 25 44 3 Changing 25 a oR 26 4 5 27 4 6 5 Power On Self Test 27 427 INSIDE Interrupts 28 5 SYSTEM ceu ctu 30 5 1 1 Architecture Functions and External connecti
97. chnology A S Page 6 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 For example the Serial Port options in Peripheral Setup can be set to 2F8h 3F Sh 2E8h or 3E8h If 2F 6h is chosen by the end user for Serial Port 1 AMIBIOS disables 2F 8h for Serial Port 2 Invalid options are greyed and cannot be selected 41 AMIBIOS Setup Main Menu The AMIBIOS Setup main menu is organised into four windows Each window corresponds to a section in this chapter Each section contains several icons Clicking on each icon activates a specific function The AMIBIOS Setup icons and functions are described in this chapter The sections are Setup The setup window has six icons that permit you to set system configuration options such as date time hard disk type floppy disk type and many others Utilities The utility window has one icon that performs system functions Security security window has three icons that control AMIBIOS security features Default The default window has three icons that permit you to select a group of settings for all AMIBIOS Setup options 4 1 1 Default Settings Each AMIBIOS Setup Option has two default settings These settings can be applied to all AMIBIOS Setup Options when you select the Default window on the AMIBIOS Setup main menu The types of defaults are Optimal These settings provide the optimal performance characteristics Fail Safe The Power On default sett
98. ddresses 03F8h 03FFh PCI ISA R Receiver buffer register when DLAB is 0 W Transmitter buffer register when DLAB is 0 Divisor latch LSB when DLAB is 1 PCI ISA 2 Divisor latch MSB when DLAB 151 Interrupt enable register when DLAB is 0 Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register PCI ISA R W Scratch pad register 222 2 0364h 0367h 036Ch 036Fh 0370h 0371h 0372h 0373h 0374h 0374h 0375h 0376h 0377h 0377h 0364h 0367h and 036Ch 036Fh are used by AMIBIOS Reserved for special use by AMIBIOS Reserved for special use by AMIBIOS 0370h 0377h may be used by on board peripheral controller as Floppy disk controller R port 2 Depends on choice made in INSIDE setup The bit definitions for these addresses the same as those for addresses 03FOh 03F7h Status Register A SRA Status Register B SRB Floppy disk controller output register DOR Tape Drive Register TSR Floppy disk controller status register MSR Data Rate Select Register DSR 5 R W Floppy disk controller data register FIFO Reserved R Digital input register DIR PCI ISA WwW Hard disk status register CCR 0374 0377h may be used by on board IDE controller as Secondary IDE Control Block 0374h 0375h 0376h
99. drive door has been opened or the diskette has been changed INSIDE Technology A S Page 90 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 12 IDE Hard Disk Connector JIDE Pull m Note U D Ioh Iol Type Signal Signal Type Ioh Iol Note rr 2 015 EEE 7 31 ee LL eae 11118 D o o 191200 NC 121 GND GND 6 PWR on cc DDACKO GND 1OCS16 GND eee GND ai aii SS iE 3308 Ea INSIDE Technology A S Page 91 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 12 1 Signal Description IDE Hard Disk Connector The fast IDE interface supports PIO from 0 to 5 and Bus Master IDE Data transfer rates up to 22 MB Sec is possible 8 x 32 Bit buffer for Bus Master IDE PCI burst transfers DA2 DAO Address lines used to address the I O registers in the IDE hard disk HDCS1 0 Hard Disk Chip Select HDCSO selects the primary hard disk D15 8 High part of data bus 07 0 Low part of data bus IOR
100. e PC 104 connector INSIDE Technology A S Page 2 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 2 1 System specification Main data Processor CPU Clock Rate System Clock Rate Cache Memory Program Memory System Core Plug and Play Features Video Controller Video Resolution Video Memory Flat Panel Interface PanelLink Ethernet USB INTEL PENTIUM 75 233MHz MMX AMD K6 166MHz 233MHz AMD 5 75 166MHz System management mode is supported 75 233 MHz Processor PCI 66 33 60 30 50 25 MHz Internal 16 kB with Intel External COAST 3 0 Module with 256 kB or 512 kB Pipelined Burst SRAM Up to 256MB DRAM memory EDO or Fast Page Up to 512MB DRAM on 686LCD MG Boards INTEL 430HX TRITON All configuration is done by software Automatic or user setup Automatic processor type detection and setup Automatic remapping of on board peripherals if conflicts with off board controllers are detected 64 Bit SVGA controller connected to PCI bus for fast access Controls CRT monitors and Flat panel 1280 x 1024 pixel 256 colors SXGA 1024 x 768 pixel 64 k colors XGA 800 x 600 pixel 16Mil colors SVGA 640 x 480 pixel 16Mil colors VGA 2MB Plasma or EL SS 8 bit Monochrome LCD SS or DD 8 16 bit Passive colour STN LCD SS or DD 8 16 24 bit Active colour TFT SS 9 12 15 16 18 24 bit PanelLink 65 MHz 650 Mbit sec 3 3 Volt Twi
101. e Parity PCI2 1 Passive Release Enable Set this option to Enabled to enable the PCI passive release feature defined in Version 2 1 of the PCI specifications The settings are Enabled or Disabled The Optimal and Fail Safe settings are Enabled Delayed Transaction Enable Set this option to Enabled to enable delayed transactions The settings are Enabled or Disabled The Optimal and Fail Safe settings are Enabled North Bridge Retry Enable Setthis option to Enabled to enable North Bridge Retry The Optimal and Fail Safe settings are Enabled INSIDE Technology A S Page 15 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 2 4 Power Management Setup Power Management Setup options are displayed by choosing the Power Management icon from the AMIBIOS Setup main menu All Power Management Setup options are described in this section The Advanced Power Management specification defines four power states ready for use The computer can be active or idle Standby The Standby State is an intermediate system dependent state that tries to conserve power The state is entered when the CPU is idle for a pre specified length of time The computer does not return to the Ready state until a device raises a hardware interrupt or a device is accessed All data and operational parameters are preserved Suspend Suspend is the lowest level of power consumption available that still preserves operational data and param
102. e arrow keys to move the cursor to a desired position and Enter to select To exit SCSISelect press Esc until a message prompts you to exit if you changed any settings you are prompted to save the changes before you exit Any changes you made in SCSISelect take effect after the computer boots 4 1 Configure View Host Adapter Settings 4 1 1 SCSI Bus Interface definitions These basic settings are the SCSISelect settings most likely to require any modification Host Adapter SCSI ID This option sets the host adapter s SCSI ID The default setting is SCSI ID 7 which gives the host adapter the highest priority on the SCSI bus e SCSI Parity Checking This option determines whether the host adapter verifies the accuracy of data transfer on the SCSI Bus The default setting is Enabled SCSI Parity checking should be disabled if any SCSI devices connected to the 686MG card does not support SCSI parity otherwise leave it enabled Most SCSI devices do support SCSI parity Host Adapter SCSI Termination This option sets termination on the host adapter However the hardware on INSIDE s MG card implements automatic detection and termination of the low and high byte of the SCSI Bus The default setting Automatic should not be changed 4 1 2 Additional Options 4 1 2 1 Boot Device Options The boot device settings allow you to specify the device you wish to boot your computer from e Boot SCSI ID This option specifies the SCSI ID of the device y
103. e current strength in milliamps for system memory The settings are SmA 8mA 8mA 12mA 12mA 8mA or 12 12 The Optimal and Fail Safe settings are SmA SmA Type F DMA Buffer Control 1 Type F DMA Buffer Control 2 These options specify the DMA channel that uses Type F DMA buffer control The settings are Disabled Channel 0 Channel 1 Channel 2 Channel 3 Channel 5 Channel 6 Channel 7 The Optimal and Fail Safe settings are Disabled Disable NAD for Ext Cache Set this option to Enable the NAD instruction for L2 secondary external cache memory The settings are Enabled or Disabled The Optimal and Fail Safe settings are Enabled Peer Concurrency Set this option to Enabled to enable PCI peer to peer concurrency The settings are Enabled or Disabled The Optimal and Fail Safe settings are Enabled DRAM Data Integrity Mode This option can only be implemented when the system is populated with a 72 bit wide memory The DRAM interface can either be ECC or Parity checked If Parity is selected the DRAM parity protection is 8 bit based even parity Selecting ECC will detect all single and dual bit errors during DRAM reads The corrected data is transferred to the requester and is not back written to DRAM If not all DRAM modules are 72 bit wide but some are 64 bit it is important to disable all error checking by Disabling ECC Test and selecting the ECC DRAM Data Integrity Mode The Default and Fail Safe settings ar
104. e settings are Disabled 1 Min 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled e Slow Clock Ratio This option specifies the speed at which the system clock runs in power saving modes The settings are expressed as a ratio between the normal clock speed and the power down clock speed The settings 7 1 1 2 half as fast as specified in Peripheral Setup 1 4 1 6 1 16 1 32 1 64 or 1 128 The default settings are 1 8 Display Activity This option specifies if AMIBIOS is to monitor activity on the display monitor for power conservation purposes When this options is set to Monitor and there is no display activity for the length of time specified in the value in the Full On to Standby Timeout Min option the computer enters a power saving state The settings are Monitor or Ignore The default settings Ignore e IRQ4 e IRQS 7 IRQ9 10 IRQI2 IRQ13 14 15 When set to Monitor these options enable event monitoring on the specified hardware interrupt request line If set to Monitor and the computer is in a power saving mode AMIBIOS watches for activity on the specified IRQ line The computers enters the full on power state if any activity occurs AMIBIOS reloads the Standby and Suspend timeout timers if activity occurs on the specified IRQ line The settings for each of these options are Monitor or Ignore The
105. e that the default settings are both Disabled to prevent potential conflicts and damaging voltage levels when connecting serial devices before running AMIBIOS Caution Always check the serial device interface standard and this setting before connecting the device On Board Serial Port 2 This option enables serial port 2 on the motherboard and specifies the base I O port address for serial port 2 The settings are Auto Disabled 3F6h 2F amp h 3E8h 2EGh The Optimal and Fail Safe default settings are Auto Serial Port 2 Mode This option is only available if the On Board Serial Port 2 is not Disabled The settings for the serial interface standard are Normal RS232 IrDA SIR A ASK IR IrDA SIR B IrDA HDLC IrDA 4PPM Consumer Raw The default settings are Normal IR Duplex mode Receiver polarity Transmitter polarity Fast IR Fast IR port Normal N A N A N A N A N A N A N A N A IrDA SIR A Full Half Active Active Active Active N A N A High Low High Low ASK IR Full Half Active Active Active Active N A N A High Low High Low IrDA SIR B Full Half Active Active Active Active Auto N A High Low High Low IrDA HDLC Full Half Active Active Active Active Auto Auto High Low High Low IrDA 4PPM Full Half Active Active Active Active Auto Auto High Low High Low Consumer Half Active Active Active Active Auto Auto High Low High Low Raw IR Full Half Active Act
106. ed detection of corrupt CMOS added Now each BIOS version has a version stamp in the CMOS Insertion of external VGA cards will take precedence over onboard controller Boot from SCSI disk in Windows NT now works SCSI are running SSD running as and last drive again Un Known problems 1 Power management does not restore timer in Win95 when waked up 2 careful with the option quick boot some types of DRAM might result in incorrect memory sizing if quick boot is disabled default set to Enabled BIOS release 109 306 200 Oct 97 New features New AMI core included core V2 4 bios ver 6 27 02 5 support now working with 512Kb of L2 cache Network boot BIOS included It will require a special boot server for this purpose USB keyboard support added It is possible to run with 2 keyboards simultaneously Modified display selection an will be shown as selection before the menu is entered This is due to an AMI limitation and the future display selection menu Due to the future display menu system the size of the SSD is decreased by 64Kb and 96Kb when using an Atmel chip Therefore the Flash disk must be prepared again when upgrading to this BIOS 6 Added setup of the IrDA interface Added S M A R T support for Hard disk drives A method of predicting crashes 8 Added Flex boot setup apa Bugs Problems solved 1 Improved detection of corru
107. eoo re QNS 83 7 9 Feature Connector 1 tasa sese eee esa sese 84 7 9 1 Signal Description Feature 85 7 10 Printer Port ConBeCUFS de pee ecce arro pea pari aep ETUR pea on 86 7 10 1 Pin Header Printer Port Connector 86 DB25 Printet Port C One ClO Go 87 7 10 3 Signal Description Printer cp ttp iiie tuts 88 INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 11 Floppy Disk Connector 89 7 11 1 Signal Description Floppy Disk Connector eene en 90 7 12 IDE Hard Disk Connector 91 7 12 1 Signal Description IDE Hard Disk Connector eene 92 7 13 Vid o Connectors ne Ee Ro NEPOS PE SU eene 93 Jo CC 93 7 13 2 Signal Description CRT Connector iuueni oeil rd e alte 93 7413 2 Flat Panel Connector GPL deckt N a edited 94 7 13 4 Signal Description Flat Panel Connector 95 7 13 5 Signal Configuration Flat Panel 96 T1336 Pane Link s tie tv tuit i iE ES 97 7 13 7 Signal Description Panel Link FPDLD eerte rdc ote
108. ers 2 You are about to install a third party driver This driver was written by the hardware vendor and is only provided here as a convenience For any problem with this driver please contact the hardware vendor Do you wish to proceed Yes 10 In order to proceed with the installation click the Yes button The driver will now be installed and the following message should be shown shortly after Installing Driver x The drivers were successfully installed You must exit from the Display Properties window and reboot in order for the changes to take effect 11 Click OK and close Display and Display Properties windows by clicking the Close button in each window 12 After closing the Display Properties window the computer must be restarted for the changes to take effect 13 After the reboot display resolution etc may be changed in the Display Properties window opened by following steps 1 and 2 above An example is shown below _ INSIDE Technology A S Page 69 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Display Properties Background Screen Saver Appearance Plus Settings Color Palette p Desktop Area 25665 H Less More 1024 by 768 pixels Font Size Refresh Frequency List All Modes Display Type 14 Before accepting new settings by
109. es are driven by the DMA controller The assertion of AEN disables response to I O port addresses when I O command strobes are asserted AEN being asserted only the device with active DACK should respond REFRESH This is an active low signal driven by the current master to indicate a memory refresh operation The current master will drive this line with a tri state driver The INSIDE 486 586LCD S CPU board does not support off board DRAM refresh so the REFRESH signal timing will be tighter than normal TC This active high signal is asserted during a read or write command indicating that the controller has reached a terminal count for the current transfer DACK must be presented by the bus adapter to validate the TC signal MASTERS This signal is not supported by the chipset INSIDE Technology A S Page 109 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 8 Main 686 components NH s 91 PC FDC37C932FR PERIPH PQFP160 SMC CONTROLLER 92 PC PCIETHERNET AM79C970AVC ETHER TQFP144 AMD CONTROLLER BRIDGE 588237158 PCHA 208 INTEL CHIPSET CONTROLLER PROCESSOR PENTIUM 200 INTEL INSIDE Technology A S Page 110 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Measurement Drawing 686LCD S 9 9661 86 67 71 06 qod zpioo9g9 061 5 061 9
110. es not configure that drive AMIBIOS does not wait for 0 5 second after sending a RESET signal to the IDE drive to allow the IDE drive time to get ready again AMIBIOS checks for a lt Del gt key press and runs AMIBIOS Setup if the key has been pressed The Optimal setting is Enabled The Fail Safe setting is Disabled 1st Boot Device flexboot Selects the priority between the different boot devices The options are IDEO IDE3 Floppy Floptical Cdrom SCSI Network or Disabled Network boot supports the following networks Novell server IBM lan server and Microsoft lan Manager server The floptical drive is supported in BIOS as next available floppy drive and can be accessed through INT13 interface using the assigned drive letter BIOS can support maximum 2 floptical drives through the INT13 interface The standard 1 44MB 720KB 120MB media and 1 2MB NEC format 1 2 Toshiba format 1 7 DMF format media can be used in the floptical drive Note that 2 88MB media is not supported in floptical drive The default setting is IDE 0 e 2nd Boot Device This device is the next boot device if the Ist boot device failed The following options are available IDE 0 Floppy Floptical Cdrom and Disabled The default setting is Floppy e 3rd Boot Device Same as above with default setting to Cdrom Try other Boot Devices If set to Yes boot devices will be tried that was not selected in the Ist to 3rd boot device options The default set
111. es not guarantee control of LOCK Control of LOCK is obtained under its own protocol in conjunction with GNT It is possible for different agents to use PCI while a single master retains ownership of LOCK If a device implements Executable Memory it should also implement LOCK and guarantee complete access exclusion in that memory A target of an access that supports LOCK must provide exclusion to a minimum of 16 bytes aligned Host bridges that have system memory behind them should implement LOCK as a target from the PCI bus point of view and optionally as a master IDSEL Initialization Device Select is used as a chip select during configuration read and write transactions DEVSEL Device Select when actively driven indicates the driving device has decoded its address as the target of the current access As an input DEVSEL indicates whether any device on the bus has been selected ARBITRATION PINS BUS MASTERS ONLY REQ Request indicates to the arbiter that this agent desires use of the bus This is a point to point signal Every master has its own REQ which must be tri stated while RST is asserted INSIDE Technology A S Page 131 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 Grant indicates to agent that access to bus has been granted This is point to point signal Every master has its own GNT which must be ignored while RST is asserted Since only four dev
112. es using this strobe should decode addresses SA19 0 only If an alternate master drives the permanent master will drive SMEMR delayed by internal logic The permanent master ties this line to VCC through a pull up resistor to ensure that it is inactive during the exchange of bus masters MEMRz This is an active low signal driven by the current master to indicate a memory read operation Memory mapped devices using this strobe should decode addresses LA23 17 and SA19 0 All bus masters will drive this line with a tri state driver The permanent master ties this line to VCC through a pull up resistor to ensure that it is inactive during the exchange of bus masters MEMWS3 This is an active low signal driven by the current master to indicate a memory write operation Memory mapped devices using this strobe should decode addresses LA23 17 and SA19 0 All bus masters will drive this line with a tri state driver The permanent master ties this line to VCC through a pull up resistor to ensure that it is inactive during the exchange of bus masters TRANSFER RESPONSE IOCS 16 This is an active low signal driven by an PC AT PC104 adapter indicating that the I O device located at the address is a 16 bit device This open collector signal is driven based on SA15 0 only not IOR and IOW when AEN is not asserted MEMCS 16 This is an active low signal driven by a memory mapped PC AT PC104 adapter indicating t
113. eters When the computer is in Suspend mode no computation is performed until normal activity is resumed Activity cannot resume unless signalled by an external event The computer is powered down and inactive in Off state Data and operational parameters may or may not be preserved in this state Power Management APM Set this option to Enabled to enable the power management and APM Advanced Power Management features The settings are Disabled Enabled or Inst on Selecting the option nst on is not supported unless external hardware is added The default Optimal setting is Enabled The Fail Safe setting is Disabled Instant On Timeout This option specifies the length of a period of system inactivity while the computer is in Full power on state When this length of time expires AMIBIOS takes the computer to a lower power consumption state but the computer can return to full power instantly when any system activity occurs The settings are Disabled 1 Min 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled Green PC Monitor Power State This option specifies the power management state that the Green PC compliant video monitor enters after the specified period of display inactivity has expired The settings are Standby Suspend or Off The default settings are Standby Video Power Down Mode This option specifies the power management state that the video subsystem enters after the speci
114. evices may have trouble handling Wide negotiation which may result in erratic behaviour or hang conditions Set Initiate Wide Negotiation to No for these devices Send Start Unit command This option determines whether the Start Unit Command is sent to the SCSI device at boot up most devices do not require this The default setting is No Setting this option to Yes reduces the load on the power supply allowing the host adapter to start SCSI devices one at a time when you boot your computer Most devices require a jumper setting to respond to this command e BIOS Multiple LUN Support This option determines whether booting from a SCSI device that has multiple LUNs is supported The default setting is No Include in BIOS scan This option controls if a given device ID should be included in the BIOS scan during Boot up Hard disks should always be included in the BIOS scan whereas CD ROM drives and the like under device driver control can be excluded The default setting of Yes will in most cases cause no problems with any devices INSIDE Technology A S Page 121 of 134 4 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 1 2 3 Advanced Configuration Options The advanced host adapter settings should not be changed unless absolutely necessary Plug and Play SCAM Support If your system includes devices that supports the SCSI SCAM protocol which assigns SCSI IDs dynamically at boot up set this option to
115. fg 78 00000000 Confg 7C 00000000 Confg 80 00000000 Confg 84 00000000 Confg 88 00000000 Confg 8 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg AO 00000000 Confg A4 00000000 Confg 00000000 Confg 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg BC 00000000 Confg 00000000 Confg C4 00000000 Confg C8 00000000 Confg CC 00000000 Confg DO 00000000 Confg D4 00000000 Confg D8 00000000 Confg DC 00000000 Confg 00000000 Confg E4 00000000 Confg 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000F10 Confg FC 00000000 Intel PIIX3 USB interface Register dump for device 47 function 42 Confg 00 70208086 Confg 04 02800005 Confg 08 0C030001 Confg 00004000 Confg 10 00000000 Confg 14 00000000 Confg 18 00000000 Confg 1C 00000000 Confg 20 0000EFA41 Confg 24 00000000 Confg 28 00000000 Confg 2 00000000 Confg 30 00000000 Confg 34 00000000 Confg 38 00000000 Confg 00000409 Confg 40 00000000 Confg 44 00000000 Confg 48 00000000 Confg 4C 00000000 Confg 50 00000000 Confg 54 00000000 Confg 58 00000000 Confg 5C 00000000 60 00000010 Confg 64 00000000 Confg 68 00000000 Confg 6C 00000000 Confg 70 00000000 Confg 74 00000000 Confg 78 00000000 Confg 7C 00000000 Confg 80 00000000 Confg 84 00000000 Conf
116. fied period of display inactivity has expired The settings are Disabled Standby or Suspend The default settings are Disabled Hard Disk Power Down Mode This option specifies the power management state that the hard disk drive enters after the specified period of display inactivity has expired The settings are Disabled Standby or Suspend The default settings are Disabled Hard Disk Time Out Minutes This option specifies the length of a period of hard disk drive inactivity When this length of time expires the computer enters power conserving state specified in the Hard Disk Power Down Mode option The settings are Disabled 1 Min 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled INSIDE Technology A S Page 16 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 e Standby Time Out Minutes This option specifies the length of the period of system inactivity when the computer is in Full On mode before the computer is placed in Standby mode In Standby mode some power use is curtailed The settings are Disabled 1 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled e Suspend Time Out Minutes This option specifies the length of the period of system inactivity when the computer is already in Standby mode before the computer is placed in Suspend mode In Suspend mode nearly all power use is curtailed Th
117. g 88 00000000 Confg 8 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg A0 00000000 Confg A4 00000000 Confg A8 00000000 Confg AC 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg 00000000 Confg 00000530 Confg C4 00000000 Confg C8 00000000 Confg CC 00000000 Confg DO 00000000 Confg D4 00000000 Confg D8 00000000 Confg DC 00000000 Confg 00000000 Confg E4 00000000 Confg 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000F10 Confg FC 00000000 INSIDE Technology A S Page 53 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Chips and Technologies 65554 VGA Controller Register dump for device 9 function 0 Confg 00 20001022 Confg 04 02800107 Confg 08 02000016 Confg 00004000 Confg 10 0000EF81 Confg 14 FEBBEFEO Confg 18 00000000 Confg 1 00000000 Confg 20 00000000 24 00000000 Confg 28 00000000 Confg 2 00000000 Confg 30 FEB90000 Confg 34 00000000 Confg 38 00000000 Confg 3C FF06010A Confg 40 00000000 Confg 44 00000000 Confg 48 00000000 Confg 4C 00000000 Confg 50 00000000 Confg 54 00000000 Confg 58 00000000 Confg 5C 00000000 60 00000000 Confg 64 00000000 Confg 68 00000000 Confg 6C 00000000 Confg 70 00000000 Confg 74 00000000 Confg 78 000
118. hadow These options control the location of the contents of the 16 of ROM beginning at the specified memory location If no adapter ROM is using the named ROM area this area is made available to the local bus The settings are Enabled The contents of the video ROM area are copied shadowed from ROM to RAM for faster program execution contents of the RAM area can be written to or read from cache memory default read from or written to cache memory INSIDE Technology A S Page 13 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 2 3 Chipset Setup This Setup menu configures features specific to the utilised chipset USB Function Enable Set this option to enable the BIOS USB Universal Serial Bus functions The settings are Enabled or Disabled By disabling the USB the USB resources are freed for other purposes The Optimal and Fail Safe settings are Disabled USB Keyboard Support Set this option to Enabled to enable USB support for USB keyboards in AMIBIOS The settings are Enabled or Disabled The Optimal and Fail Safe settings are Disabled USB Passive Release Enable Set this option to Enabled to enable passive release on the universal serial bus The settings are Enabled or Disabled The Optimal and Fail Safe settings are Enabled Global Triton2 Enable Set this option to Enabled to permit AMIBIOS to automatically configure the global features of the Intel82439HX chipset to opt
119. hannel 3 Address bits 23 16 DMA channel Address bits 23 16 Additional DMA page register Reserved Additional DMA page register Reserved Additional DMA page register Reserved DMA channel 0 Address bits 23 16 Additional DMA page register Reserved DMA channel 6 Address bits 23 16 DMA channel 7 Address bits 23 16 DMA channel 5 Address bits 23 16 Additional DMA page register Reserved Additional DMA page register Reserved Additional DMA page register Reserved R W DMA low page register refresh 6 sed for Peripheral controller GateA20 and Keyboard reset 0092h Port 92 Register Bits 7 2 Reserved Bit 1 Fast gate A20 option 0 CPU address wrap around 1MB boundary 1 No wrap around 1 Force Fast CPU reset for protected mode switchings INSIDE Technology A S Page 37 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 00A0h 00A 1h are used for Programmable interrupt controller 2 Except for the differences noted below the bit definitions are the same as those for addresses 0020h 0021h Int 2 Control 00A0h R W Programmable interrupt controller 2 Int 2 Mask PCI ISA Programmable interrupt controller 2 mask OCW1 Bit 7 0 Enable IRQ15 interrupt Bit 6 Enable 14 interrupt Bit 5 Enable 13 interrupt Bit4 Enable IRQ12 inte
120. hard disk drive Most SCSI disk devices are preformatted at the factory and do not need to be formatted again The Adaptec Format Disk utility is compatible with the vast majority of SCSI disk drives You cannot abort a low level format once it is started Verify Disk Media This utility allows you to scan the media of a hard disk drive for defects If the utility finds bad blocks on the media it prompts you to reassign them if you select yes these blocks are no longer used You can press Esc at any time to abort the utility INSIDE Technology A S Page 123 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 5 Installing SCSI Device Drivers Some operating systems include the AIC 7880 Ultra Wide SCSI host adapter device drivers as part of their installation software These drivers work fine with the onboard SCSI controller however to make the host adapter perform at its optimum level the most recent version of the driver should be installed Following Inside s 686MG card is a diskette containing Adaptec s EZ SCSI Lite device drivers 5 1 Installing Device Driver for DOS 1 Install DOS 6 x or above and start it running on your computer 2 Insert the Adaptec EZ SCSI Lite Setup Diskette in your floppy drive 3 At the DOS prompt type a dosinst if you using the A drive 4 Follow the instructions that appear on the screen 5 2 Installing Device Driver for Windows 3 11 Install Windows 3 1x and sta
121. hat the memory device located at the address is a 16 bit device This open collector signal is driven based on LA23 17 only INSIDE Technology A S Page 107 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 OWS This signal is an active low open collector signal asserted by a 16 bit memory mapped device that may cause an early termination of the current transfer It should be gated with MEMR or MEMW and is not valid during DMA transfers IOCHRDY precedes OWS IOCHRDY This is an active high signal driven inactive by the target of either a memory or an I O operation to extend the current cycle This open collector signal is driven based on the system address and the appropriate control strobe IOCHRDY precedes OWS IOCHCK This is an active low signal driven active by a PC AT PC104 adapter detecting a fatal error during bus operation When this open collector signal is driven low it will typically cause a non maskable interrupt CONTROLS SYSCLK This clock signal may vary in frequency from 2 5 MHz to 25 0 MHz depending on the setup made in the AMI BIOS Frequencies above 16 MHz are not recommended The standard states 6 MHz to 8 33 MHz but most new adapters are able to handle higher frequencies The PC AT PC104 bus timing is based on this clock signal OSC This is a clock signal with a 14 31818 MHz 50 ppm frequency and a 50 590 duty cycle The signal is driven by the permanent master
122. ices can utilize master mode on a PCI local bus and the onboard SCSI and Ethernet controller take up one channel each master capabilities are only supported in slot 1 and 2 on the backplane While RST is asserted the arbiter must ignore all REQ lines since they are tri stated and do not contain a valid request The arbiter can only perform arbitration after RST is deasserted A master must ignore its GNT while RST is asserted REQ and GNT are tri state signals due to power sequencing requirements when 3 3V or 5 0V only add in boards are used with add in boards that use a universal I O buffer ERROR REPORTING PINS The error reporting pins are required by all devices and maybe asserted when enabled PERR Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle The PERR pin is sustained tri state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected The minimum duration of PERR is one clock for each data phase that a data parity error is detected If sequential data phases each have a data parity error the PERR signal will be asserted for more than a single clock PERR must be driven high for one clock before being tri stated as with all sustained tri state signals There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed An agent cannot report a u
123. imal values based on the CPU frequency The settings are Enabled or Disabled The Optimal and Fail Safe default settings are Enabled Memory Hole Use this option to specify an area in memory that cannot be addressed on the ISA bus The settings are Disabled 512 640K or 15 16 The default settings are Disabled 8 Bit I O Recovery Time SYSCLK This option specifies the length of the delay in SYSCLKs inserted between consecutive 8 bit I O operations The settings are Disabled 5 1 2 3 4 5 6 or 7 The Optimal and Fail Safe default settings are 16 Bit O Recovery Time SYSCLK This option specifies the length of the delay in SYSCLKs inserted between consecutive 16 bit I O operations The settings are Disabled 4 1 2 or 3 The Optimal and Fail Safe default settings are 7 DRAM Timings This option specifies the RAS Access Time parameter for the installed DRAM SIMMs The settings are Manual 60ns or 70ns The Optimal default setting is 7005 The Fail Safe default setting is 70ns Refresh Rate This option specifies the refresh rate frequency for the installed DRAM SIMMs The settings are 50 MHz 60 MHz 66 MHz The Optimal and Fail Safe default settings are 66 MHz Turbo Read LeadOff Set this option to Enabled to enable the turbo read leadoff feature The settings are Enabled or Disabled The Optimal and Fail Safe default settings are Disabled Read Burst Timing This option specifies the access timings for DRAM
124. ings consist of the most basic set of parameters They are to be used as a reference in case the system is behaving erratically They should always work but do not provide optimal system performance characteristics The system BIOS automatically loads these values if the system parameters in the CMOS Memory is lost ex after shipping the CPU board with disconnected battery INSIDE Technology A S Page 7 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 42 Setup Types AMIBIOS Setup have six separate windows Different types of system configuration parameters are set on each window Standard Setup Set the time and date Configure disk drives Advanced Setup Configure basic system performance parameters 4 2 1 Standard Setup Standard Setup options are displayed by choosing the Standard icon from the AMIBIOS Setup menu All Standard Setup options are described below Date Time Select the Date Time option to change the date or time The current date and time are displayed Enter new values through the displayed window Floppy Drive Choose the Floppy Drive icon to specify the floppy drive type The settings are 360 514 1 2 5 720 KB 312 1 44 MB 312 2 88 MB 3 Master Pri Slave Sec Master e Sec Slave Choose these icons to configure the hard disk drive named in the option When you click on an icon the following parameters are listed Type
125. install the driver for the windows for workgroups 3 11 system 1 Make the Program Manager the active application 2 Open the Main group and double click on the Windows Setup icon as shown below INSIDE Technology A S Page 59 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Program Manager Bg Eile Options Window Help Manager Control Panel Print Manager Viewer PIF Editor Read Me Accessories Network StartUp The windows setup program should now be running as shown below Windows Setup Options Help Display VGA Keyboard Enhanced 101 or 102 key US and Non US Mouse Logitech Network Microsoft Windows Network version 3 11 3 Select Change Network Settings from the Options menu and the window below should appear Network Setup Network Settings Sa Setup will install Windows support for the following Networks network s on your computer Microsoft Windows Network version 3 11 es You can share your files and printers with others Network Drivers 4 Click the Drivers button to get access to installation removal or configuration of the network The window below should appear Network Drivers Network Drivers Set Default Protocol Default Protocol No Default Protocol INSIDE Technology A S Page 60 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December
126. ive Active Active Auto Auto High Low High Low Indicate default setting INSIDE Technology A S Page 22 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 On Board Parallel Port This option enables the parallel port on the motherboard and specifies the parallel port base I O port address The settings are Auto Disabled 378 2761 or 3BCh The Optimal and Fail Safe default settings are Auto Parallel Port Mode This option specifies the parallel port mode ECP and EPP are both bi directional data transfer schemes that adhere to the IEEE P1284 specifications The settings are Normal The normal parallel port mode is used default The parallel port can be used with devices that adhere to the Enhanced Parallel Port EPP specification EPP uses the existing parallel port signals to provide asymmetric bi directional data transfer driven by the host device The parallel port can be used with devices that adhere to the Extended Capabilities Port ECP specification ECP uses the DMA protocol to achieve transfer rates of approximately 2 5 Mbs ECP provides symmetric bi directional communications EPP Version Sets the EPP version revision to either 9 or 1 7 The default settings 1 9 This option is only valid if the Parallel Port Mode option is EPP e Parallel Port IRQ This option sets the Parallel Port IRQ number and is only available if On Board Parallel
127. k Close and the previous dialogue box will be shown with the new adapter Network Setup Network Settings Setup will install Windows support for the following 5 on your computer Microsoft Windows Network version 3 11 Cancel You can share your files and printers with others E Network Drivers Ethernet adapter for 686LCD S CPU Board NDI Microsoft NetBEUI IPX SPX Compatible Transport with NetBIOS BEL 5 11 Click and the installation process will begin This will usually require files from Windows installation disk s When the files for the network adapter is required the computer will ask you to insert the Inside Technology Driver Disk The path for the drivers must be specified as shown below A WFW311 Click after entry Install Driver Insert Inside Technology Driver Disk or a disk with the updated or vendor provided 3 386 file in WFW311 12 The configuration files will be modified in order to include the network adapter and the installation is completed For the change to take effect the computer must be restarted Windows Setup You need to quit Windows and restart your computer O so that the changes you made will take effect Do not press CTRL ALT DEL to restart your computer this may cause you to lose your work Restart your computer now Further configuration of the network adapter
128. lane from Advantec PCA 6106P3 Rev A1 01 supports this configuration INSIDE Technology A S Page 133 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 7 Measurement Drawing D 5 uu zc S 6 uy QO E Gesesesessq ty 07 0000000000000 N 4059 E gt O on 540 2999 4059 wwg ozz 4900 od 945906 Jogo o olo o ojo als Pad oo ooo 6595 olo Y Sle loo o olo olo d loo IL E 999 m 04 0209 wwe gel 2015 Slo loo 4 oo old seo o olo old Biolog old 22122128 s oo olo blo og
129. lel data bus from PC board to printer The data lines are able to operate in PS 2 compatible bi directional mode Signal to select the printer sent from CPU board to printer Signal from printer to indicate that the printer is selected This signal indicates to the printer that data at PD7 0 are valid Signal from printer indicating that the printer cannot accept further data Signal from printer indicating that the printer has received the data and is ready to accept further data This active low output initialises resets the printer This active low output causes the printer to add a line feed after each line printed Signal from printer indicating that an error has been detected Signal from printer indicating that the printer is out of paper INSIDE Technology A S Page 88 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 711 Floppy Disk Connector JFLP Note 00 Ioh Iol Type Signal Signal Type Ioh Iol U D Note eee cp 2 f DENSELO eee 13 eee cp 15 6 PWR __ GND INDEX GND morar oc a cv 14 EE 4 DRvA OC GND 6 oc ware 7 6 IS 3 were AEN E IS OC co DSKCHG IS INSIDE Technology A S Page 89 of 134 686LCD S amp 686L
130. lly park when the system is shut down Sectors The number of sectors per track MFM drives have 17 sectors per track RLL drives have 26 sectors per track ESDI drives have 34 sectors per track SCSI and IDE drives have more sectors per track Capacity The formatted capacity of the drive is Number of heads x Number of cylinders x Number of sectors per track x 512 bytes per sector Configuring IDE Drives If the hard disk drive to be configured as an IDE drive select the appropriate drive icon Pri Master Pri Slave Sec Master or Sec Slave By selecting Auto under types the IDE drive parameters are automatically detected including ATAPI CD ROM drives and displayed Click on the OK button to accept these parameters or you can set the parameters manually if you are absolutely certain that you know the correct IDE drive parameters Click on LBA Large Mode and choose On to enable support for IDE drives with capacities greater than 528 MB Click on Block Mode and choose On to support IDE drives that use Block Mode Click on 32Bit Mode and click on On to support IDE drives that permit 32 bit accesses Click on PIO Mode to select the IDE Programmed I O mode PIO programming also works with ATAPI CD ROM drives The settings are Auto 0 1 2 3 4 or 5 Click on Auto to allow AMIBIOS to automatically find the PIO mode that the IDE drive being configured uses If you select 0 5 you must make absolutely certain that you are selecting the PIO
131. n Serial Port 1 Receiver Buffer Register CTS RTS Bi directional control signal pair The level of this differential signal pair could be read from the Serial Port 1 s CTS signal Modem control register The level of this differential signal pair could be controlled through the Serial Port 1 s RTS signal Modem control register The control signal line driver is enabled through the Serial Port 175 CSE signal in INSIDE control register INSIDE Technology A S Page 81 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 8 Pin Header Serial Port 2 Connector JPCOM2 Pull PIN Pull Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note BEEN 1 2 LL 1 The CPU board is equipped with RS232 drivers operating with capacitor charge pumps The RS232 channel will operate from a 5 V supply only The Thevenin equivalent for an output is specified below for RS232 mode at 5V Vth V DC Rth Ohm Vth V DC Rth Ohm 700 560 INSIDE Technology A S Page 82 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 8 22 Signal Description Serial Port 2 TxD Serial output This signal sends serial data to the communication link The signal is set to a marking state on hardware reset when the transmitter is empty or when loop mode operation is initiated RxD Serial input This signal receives serial data from the communication link DTR Data Termi
132. n Wide SCSI connector special consideration must be taken if external devices are used The high byte must be active terminated in the converter connector going from 68 pins to 50 pins Here Adaptec s ACK 68 50 could be used For internal devices connected 68 pin Wide SCSI connector the high byte should not be terminated before the end of the cable If the last device is not Wide a terminator should be placed at the end of the cable ACK W2W SIT A converter connector going from 68 pins to 50 pins without termination could be ACK 68P 50P IU The configurations are illustrated in the figure on the following page INSIDE Technology A S Page 118 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 Internal Devices connected i 686MG High Byte Terminated Low Byte Not Terminated L Terminated External Devices connected LH High Byte e erminated High Byte Terminated Low Byte Not Terminated INSIDE Technology A S Page 119 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 4 SCSI BIOS Setup Adaptec s menu driven SCSISelect configuration utility is a bios extension that allows the user to change host adapter settings without changing jumpers or to format verify a hard disk drive media The utility is started by pressing Ctrl A when the message Press Ctrl A for SCSISelect Utility appears on the screen Use th
133. nal Ready This signal indicates to the modem or data set that the on board UART is ready to establish a communication link DSR Data Set Ready This signal indicates that the modem or data set is ready to establish a communication link RTS Request To Send This signal indicates to the modem or data set that the on board UART is ready to exchange data CTS Clear To Send This signal indicates that the modem or data set is ready to exchange data DCD Data Carrier Detect This signal indicates that the modem or data set has detected the data carrier RI Ring Indicator This signal indicates that the modem has received a telephone ringing signal INSIDE Technology A S Page 83 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 9 Feature Connector JPFEAT Pull PIN Pull Note U D Ioh Iol Type Signal Signal Ioh Iol U D Note eee VCCVTR EXTRST 5 6 PWRON 4 7 5 0 sun ee 10 GND JO 24 JO 24 cro nok 24 10 crio 24 i PWR Note 1 These 3 signals might be used by INSIDE Technology for flat panel contrast controlling purposes FPUM module for support of STN or monochrome Panels 2 In the first pr
134. nal SCSI Connector Pull Pull Note U D Ioh Iol Type Signal PIN Signal Type Ioh Iol 00 ll lll Gni Gni EEWR Gni 161 BEA ox 1 ox ane Gi 760 E EZA ES aa EU Sa a qu eae al 29 30 31 32 33 34 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 1 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd nd 29 1307 32 83 DB 11 Note 1 Active Termination 110 Typical pull up to Termpwr Note 2 Termpwr supplied through Schottky diode to prevent backflow of power 25 EEE AEEA AENEA EE E Sis INSIDE Technology A S Page 126 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 6 1 2 50 pin Internal SCSI connector Pull Pull Note Ioh Iol Type Signal PIN Signal Type Ioh Iol U D Note Gnd
135. nsistent state What effect RST has on a device beyond the PCI sequencer is beyond the scope of this specification except for reset states of required PCI configuration registers Anytime RST is asserted all PCI output signals must be driven to their benign state In general this means they must be asynchronously tri stated SERR open drain is floated REQ and GNT must both be tri stated they cannot be driven low or high during reset To prevent AD C BE and PAR signals from floating during reset the central resource may drive these lines during reset bus parking but only to a logic low level they may not be driven high RST may be asynchronous to CLK when asserted or deasserted Although asynchronous deassertion is guaranteed to be a clean bounce free edge Except for configuration accesses only devices that are required to boot the system will respond after reset ADDRESS AND DATA AD 31 00 Address and Data are multiplexed on the same PCI pins A bus transaction consists of an address phase followed by one or more data phases PCI supports both read and write bursts The address phase is the clock cycle in which is asserted During the address phase AD 31 00 contain a physical address 32 bits For I O this is a byte address for configuration and memory it is a DWORD address During data phases AD 07 00 contain the least significant byte Isb and AD 31 24 contain the most significant byte msb Write da
136. ntil it has claimed the access by asserting for a target and completed a data phase or is the master of the current transaction SERR System Error is for reporting address parity errors data parity errors on the Special Cycle command or any other system error where the result will be catastrophic If an agent does not want a non maskable interrupt NMI to be generated a different reporting mechanism is required SERR is pure open drain and is actively driven for a single PCI clock by the agent reporting the error The assertion of SERR is synchronous to the clock and meets the setup and hold times of all bused signals However the restoring of SERR to the deasserted state is accomplished by a weak pullup same value as used for s t s which is provided by the system designer and not by the signaling agent or central resource This pull up may take two to three clock periods to fully restore SERR The agent that reports SERR s to the operating system does so anytime SERR is sampled asserted INTERRUPT PINS OPTIONAL Interrupts on PCI are optional and defined as level sensitive asserted low negative true using open drain output drivers The assertion and deassertion of INTx is asynchronous to CLK A device asserts its INTx line when requesting attention from its device driver Once the INTx signal is asserted it remains asserted until the device driver clears the pending request When the request is cleared the devi
137. oduction batch of the 686LCD s board PCB no 20100161 these signals have been exchanged All following revisions will be as described above INSIDE Technology A S Page 84 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 9 1 Signal Description Feature Connector EXTRST External reset input A logic low level at this pin will reset the entire CPU board PWRGD Power good output A logic high level at this output pin indicates that the CPU board is being reset The reset may be caused by a VCC supply below 4 55 V DC typical an external reset or software watchdog time out WDSER Watchdog service indicator This output signal will toggle logic level for each user software watchdog service action The signal is fed through a 330R series resistor for direct connection of a LED EXTREQ External Request Switch This active low input signal can activate either NMI SMI or a standard AT Bus IRQ interrupt This feature requires a vendor code EXTSPK An external speaker may be connected between this pin and ground The speaker impedance must be 8 ohms or higher HDACT Hard Disk Activity This pin is connected directly to the HDACT signal in the JPIDE connector The signal is fed through a 330R series resistor for direct connection of a LED GPIO7 0 General Purpose Inputs Outputs These Signals might be controlled or observed through the INSIDE Utility Interrupt function EXTBATT
138. of PCI devices require local for expansion ROM The Expansion ROM Base Address register is intended for the base address and size information The number of bits a device actually implements depends on how much address space the device requires The upper 21 bits correspond to the upper 21 bits of the Expansion ROM Base Address A demand of 128 KB would mean an implementation of the top 20 bits leaving the 4 remaining bits equal to zero Device dependent software may determine the required address space by writing all 1 s to the upper 21 bits and then read back the value The device returns 05 in all don t care bits specifying the size and alignment requirements The amount of address space a device requests must not be greater than 16 MB Bit 0 in the register is used by the device to control access to the Expansion ROM When it is zero the expansion ROM address space is disabled while a one enables address decoding This way a device can be with or without an Expansion ROM depending on the system configuration The Memory Space bit in the Command register has precedence over the Expansion ROM Base Address Enable bit INSIDE Technology A S Page 51 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Expansion ROM Base Address register Bit 31 11 Expansion ROM Base Address Bit 10 1 Reserved Bit 0 Address decode disable Address decode enable Post code detects the presence of a Expansion ROM in t
139. onfg 84 00000000 Confg 88 00000000 Confg 8C 00000000 Confg 90 00000000 Confg 94 00000000 Confg 98 00000000 Confg 9C 00000000 Confg A0 00000000 Confg A4 00000000 Confg A8 00000000 Confg AC 00000000 Confg BO 00000000 Confg B4 00000000 Confg B8 00000000 Confg BC 00000000 Confg 00000000 Confg 00000000 Confg C8 00000000 Confg CC 00000000 Confg 00000000 Confg 04 00000000 Confg D8 00000000 Confg 00000000 Confg EO 00000000 Confg E4 00000000 Confg E8 00000000 Confg EC 00000000 Confg FO 00000000 Confg F4 00000000 Confg F8 00000000 Confg FC 00000000 e Adaptec AIC 7880 SCSI Controller Register dump for device 8 function 0 Confg 00 80789004 Confg 02800117 Confg 08 01000000 Confg 00004008 Confg 10 0000 01 Confg 14 00 Confg 18 00000000 Confg 1C 00000000 Confg 20 00000000 Confg 24 00000000 Confg 28 00000000 Confg 2 00000000 Confg 30 0000 Confg 34 00000000 Confg 38 00000000 Confg 0808010B Confg 40 00001580 Confg 44 00001580 Confg 48 00000000 Confg 00000000 Confg 50 00000000 54 00000000 Confg 58 00000000 Confg 5C 00000000 Confg 60 00000000 Confg 64 00000000 Confg 68 00000000 Confg 6C 00000000 Confg 70 00000000 Confg 74 00000000 Confg 78 00000000 Confg 7C 00000000 Confg 80 00000000 Confg 84 00000000 88 00000000
140. onfiguration software uses the registers to determine how much space a device requires in the given space I O or memory and for manipulating the device registers 5 6 2 Configuration Space Registers Generally the PCI configuration space for a particular device consists of a header and a device dependent region The header take up 16 bytes accessed with byte read writes in little endian ordering The predefined header consists of fields that uniquely identify the device and allow the device to be generically controlled The first 16 bytes are defined the same for all devices The remaining can have different layouts depending on the base functions that the device supports 31 16 15 0 Device ID Vendor ID 00h Status Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line OCh Size 10h 14h Base Address Registers 18h 1Ch 20h 24h Cardbus CIS Pointer 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address 30h Reserved 34h Reserved 38h Max_Lat Min Gnt Interrupt Pin Interrupt Line 3Ch devices support the Vendor ID Device ID Command Status Revision ID Class Code and Header Type fields in the header e Vendor ID This field identifies the manufacturer of the device DeviceID This field identifies the particular device as allocated by the vendor Command command register provides a coarse
141. ons eese 30 5 2 M 31 33 cc 32 5 4 Interrupt tandi oi Dea 46 55 Se c EN 47 5 0 PCT 48 SOT Configuration ue anda 48 5 6 2 Configuration Space Registers ed yo dabo eeu pesi quaii ges oeuvre gos ordei ecd ger 48 INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 7 Onboard Devices 53 6 DRIVER INSTALEATIQN 55 6 1 Driver installation for Ethernet Adapter ccsssscssssscssssscsssccsssescssssscesscssssssscsssssees 55 6 11 Windows 95 55 0 1 2 Windows NT 4 0 Ethernet installation 57 6 1 5 Windows for workgroups 59 OLA DDyeropOllscs tuu iustas etui tis 62 6 2 Driver installation for Display Adapter 4 eese eee esee 64 MUIBdONS DO secessu oi hm 64 6 2 2 Windows NT 4 0 Display installation 67 02 3 MINUOWS 70 DEFINITIONS rae Eccc Spende 72 7 1 Connector layout on Half Size 72 72 Symbol DOS
142. ou wish to boot from The default setting is SCSI ID 0 The SCSI ID selected here must correspond to the ID configured on the boot device e Boot LUN Number If your boot device has multiple LUNs Logical Unit Numbers and Multiple LUN Support is enabled this option allows you to specify which LUN to boot from on your boot device The default setting 15 LUN number 0 4 1 2 2 SCSI Device Configuration The SCSI Device settings allow you to configure certain parameters for each device on the SCSI Bus To configure a specific device you must know the SCSI ID assigned to that device If you are not sure of the SCSI ID see SCSI Disk Utilities INSIDE Technology A S Page 120 of 134 686LCD S 6861 CPU Board Version 1 4 0 8 Dec 1997 e Initiate Syncronous Negotiation This option determines whether synchronous data transfer negotiation between the device and the host adapter is initiated by the host adapter Synchronous negotiation is a SCSI feature that allows the host adapter and the attached SCSI device to transfer data in synchronous mode which is faster than asynchronous transfers Older devices that do not support Sync Negotiation can cause the system to hang set Sync Negotiation to No for use of these devices The default setting is Yes Maximum Sync Transfer Rate This option sets the maximum synchronous data transfer rate that the host adapter supports The default setting is 40 0 MBytes Sec with the options of 10 0 1
143. ppy disk controller for peripheral support The 686LCD S include PCI Ethernet with and interface USB Universal Serial Bus and IrDA interface are implemented directly on the board The 686LCD S is equipped with a keyboard port that supports standard AT compatible keyboards and a separate port for connection of a PS 2 mouse For single board applications an optional Solid State Disk SSD with up to 8MB is available on board The system can boot from Flash and is configured to behave just like any standard hard disk or floppy disk A programmable watchdog timer and the power supply supervisor complement the standard board features to allow the use of the 686LCD S in critical industrial environments Processor temperature and fan supervision circuit is included Onboard 3 3 Volt programmable switch mode power supply Mixed voltage design with 3 3 volt Chipset VGA and PanelLink controller The CMOS memory containing the system parameters and date time values is backed up by an on board Li battery Permanent selected system parameters may alternatively be secured in the BIOS Flash The 686LCD S is equipped with a standard AMI System BIOS a customised C amp T VGA BIOS and INSIDE Technology s BIOS handling system set up configuration and solid state disk support Additional controllers and or user specific I O extension adapters may be added to the 686LCD S CPU via the standard passive PC AT backplane or th
144. pressing a test should be performed by clicking button 6 2 3 Windows 3 1X The following steps will install a display driver for the Chips amp Technologies 65554 PCT display controller The display adapter is compatible with Windows 3 1 as well as Windows for workgroups 3 11 If Windows is running exit windows in order to install the drivers 2 Insert the Inside Technology Display Driver disk in drive a and type the following at the DOS prompt A Enter CD WIN31X Enter Setup Enter Where Enter means Press enter 3 This should start the setup program Follow the instructions to copy drivers to the hard disk The installation directory will be C WINDOWS for a standard windows installation After the drivers are copied press lt ESC gt and answer to leave the installation program 4 Enter the windows directory typically C lt Enter gt CD Windows lt Enter gt and start the setup program setup lt Enter gt Move the bar to the Display line use the up arrow and press lt Enter gt Select one of display drivers for Chips and Technologies and press lt Enter gt The new configuration is now shown Accept by pressing lt Enter gt The current drivers may be used accept by pressing lt Enter gt tA Start windows display driver you have chosen should now be the one in use Further configuration of the di
145. pt CMOS added Now each BIOS version has a version stamp in the CMOS Known problems Running with an MMX CPU and the SCSI will hang up the system this will be fixed in the next BIOS release Problem arises when running SSD as a hard drive probably caused by the new flex boot feature SSD is only able to emulate floppy drive in this release INSIDE Technology A S Page 112 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 Appendix 686LCD MG CPU Board Rev 1 1 1 8 Dec 1997 INSIDE Technology A S Page 113 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 List of Contents 1 ADDITIONAL SYSTEM SPECIFICATIONS FOR 686LCD MQG 116 ECelbBSgspillpc 117 3 SCSI INSTALLATION coi seve acra seve neve xara Reve ces neve n re x Fran rex evan r x kV a rex CY dria 6e 118 4 SCSI BIOS SETUP err 120 4 1 Configure View Host Adapter Settings 120 4 1 1 SCSI Bus Interface 120 41 2 Additional Options bi eee ee a nm tiene eer eve ese 120 4 2 9 Disk Utilities eissis ean 123 5 INSTALLING SCSI DEVICE
146. r As a Target it is driven also as a handshake during Arbitration and then it is driven for the rest of the transfer Used for 8 and 16 bit transfers ATN Attention This line is driven as an Initiator when a special condition occurs It is received by the Target Used for 8 and 16 bit transfers POWER TERMPWR Termination Power INSIDE Technology A S Page 128 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 Dec 1997 6 2 PCI Interface 6 2 1 PCI Edge Connector er CLKD _ ___ 5 40 D PR svo E S ee eee S ay AD26 405 024 OT O PR O AD20 O I J GD ___ TRDY _ GD _ k STOP ocx GND __ PAR _ ADIS O I 4204 PR A
147. radio button select the Chips and Tech 65554 PCT line model and click OK button This is shown below m Click the Display adapters that matches your hardware and then click OK If you don t know which model you have click OK This list shows only what was found on the installation disk Models Cy Chips and Tech 64310 PCI new Chips and Tech 65545 new m Chips and Tech 65548 PCI new Chips and Tech 65550 Chips and Tech 65554 Chips And Technologies Accelerator Show compatible devices Show all devices 6 The driver files will now be read and the display adapter is shown in the previous window as shown below Click the Close button INSIDE Technology A S Page 65 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Change Display Type BE Adapter Chips and Tech 65554 Change Manufacturer Chips And Technologies Inc Version 40 Current Files chipsS5 drv vdd vflatd chips95 vd Monitor Type Hitachi CM1798M Change Monitor is Energy Star compliant 7 This takes you back to the display properties window as shown below Click the Close button Display Properties BE Background Screen Saver Appearance Plus Refresh Settings High Color 18 bit Less More Color palette Desktop
148. rrupt Enable IRQ11 interrupt Bit2 Enable interrupt Bit 1 Enable IRQO interrupt Bit 0 Enable 08 interrupt 00B2h 00B3h are used for Advanced Power Management 00B2h PCI R W Advanced Power Management Control Writes to this port store data in the APMC register and generates an SMI if the SMIEN and SMICNTL registers have been set up Reads cause the 5 signal to be asserted if set up in the SMICNTL register Advanced Power Management Status The register passes information between the OS and the SMI handler 00COh 00DFh are used by DMA controller 2 DMA channel 4 Address bits 15 0 byte 0 low byte followed by byte 1 00C2h 00C4h 00C6h DMA channel 5 Byte count 15 0 byte 0 low byte followed by byte 1 00C8h 00 00CCh DMA channel 7 Address bits 15 0 byte 0 low byte followed by byte 1 DMA channel 7 Byte count 15 0 byte 0 low byte followed by byte 1 00DOh DMA channel 4 7 status register Bi Channel 7 request Bi Channel 6 request Bi Channel 5 request Bi Channel 4 request Bi Terminal count on channel 7 Bi Terminal count on channel 6 Bi Terminal count on channel 5 Bi Terminal count on channel 4 PCI R W PCI R W PCI R W PCI R W PCI R W PCI R W PCI R W PCI R PCI wW DMA channel 4 7 command register Bit 7 0 DACK sense active low PCI W PCI W DACK sense active high DREQ sense active low DREQ sense active high Late write selection
149. rrupt trigger level 00 1 Byte 01 4 Bytes 10 8 Bytes 14 Bytes its Reserved it2 Clears the transmit FIFO self clearing bit it 1 Clears the receive FIFO self clearing bit it 0 Enable transmit and receive FIFOs e 7 PCI ISA Line control register Bi Divisor Latch Access Bit DLAB Access receiver buffer transmitter holding register Access divisor latches i Set break control Serial output forced to spacing state and remains there i Odd parity Even parity select Parity enable Number of stop bits per character 0 One stop bit 1 stop bits if 5 bit word length is selected 2 stop bits if 6 7 or 8 bit word length is selected i Number of bits per character 5 bit word length 6 bit word length 7 bit word length 8 bit word length INSIDE Technology A S 44 of 134 Technology A S Page 44 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Description 03FCh PCI ISA Modem control register Bits 7 5 xxx Reserved Bit 4 1 Loop mode enabled The output from the transmitter shift register is looped back to the receiver shift register input Bi Enable PC AT interrupt OUT2 Bi Force OUTI active no function at this bit Bi Force Request To Send active Bi Force Data Terminal Ready active 03FDh PCI ISA R W Line status register Bi In FIFO mode this bit indicates at least one receive error in the FIFO It is cleared
150. rt it running on your computer Insert the Adaptec EZ SCSI Lite Setup Diskette in your floppy drive Select File Run from the Program Manager menu When the run dialogue box appears type a setup if you are using the A drive Follow the instructions that appear on the screen POR 5 3 Installing Device Driver Windows 95 A version of the aic7800xx mpd driver is embedded on the Windows 95 installation CD During a normal Windows 95 installation the 7800 Family host adapter is detected in your system and the embedded aic78xx mpd driver is automatically installed Once the Windows 95 installation is complete you can update the driver with the most recent version To install the aic78xx mpd on an existing Windows 95 installation follow these guidelines 1 Start Windows 95 Click the Start button on the Windows 95 task bar and then point to Settings Click Control Panel Double click the system icon On the Device Manager tab click the plus sign next to the SCSI controller icon Double click the 2940UW host adapter or if a yellow question mark appears labelled PCI SCSI Bus Controller double click the question mark 7 On the Driver tab click Change Driver You may be asked to select the hardware type if asked to do so select SCSI controller 8 Click the Have Disk button and enter a win95 as the location to copy the manufacturer s file from 9 Click OK 10 Select the 7800 Family host adapter and click
151. s in this case the temporary master drives these lines SA7 0 are not driven during refresh initiated transfer while INSIDE 486 586LCD S CPU board supports on board DRAM only SBHE This signal is an active low signal that indicates that a byte is being transferred on the upper byte SD15 8 of the 16 bit bus All bus masters will drive this line with a tri state driver DATA 5015 8 These signals are defined for the high order byte of 16 bit data bus Memory or I O transfers this part of the bus are defined when 5 is active 507 0 These signals are defined for low order byte of 16 data bus being only bus for 8 bit PC AT PC104 adapter boards Memory or I O transfers on this part of the data bus are defined for 8 bit operations with even or odd addresses and for 16 bit operations for odd addresses only The signals SAO and are used to define data present on this bus ODD EVEN jWordtanser ______ ODD ODD transfer on SD15 SD8 L1 0 EVEN transfer on 507 500 L1 1 ODD _ Byte transfer on 507500 COMMANDS BALE This is an active high signal used to latch valid addresses from the current bus master on the falling edge of BALE During DMA refresh and alternate master cycles BALE is forced high for the duration of the transfer BALE is driven by the permanent master with a totem pole driver INSIDE Technology A S
152. s option Parity check Set this option to Enabled to enable parity check on DRAM The default setting is Disabled Boot to OS 2 Set this option to Enabled to permit AMIBIOS to run with IBM OS 2 The settings are Enabled or Disabled The default settings are Disabled Wait For If Error AMIBIOS POST runs system diagnostic tests that can generate message followed by Press F1 to continue If this option is set to Enabled AMIBIOS waits for the end user to press F1 before continuing If this option is set to Disabled AMIBIOS continues the boot process without waiting for F1 to be pressed The settings are Enabled or Disabled The Optimal default and Fail Safe default settings are Disabled INSIDE Technology A S Page 12 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 e Internal Cache This option specifies the caching algorithm used for L1 internal cache memory The settings are Disabled L1 internal cache memory on the CPU cache memory is disabled WriteBack Use the write back caching algorithm default e External Cache This option specifies the caching algorithm used for L2 secondary external cache memory The settings are Disabled L2 secondary cache memory is disabled Use the write back caching algorithm WriteThru Use the write through caching algorithm default C000 16K Shadow 00 16 Shadow D000 16K Shadow e D400 16K Shadow D800 16K S
153. s component click Have Disk Network Adapter 8 Allied Telesyn AT1700 Ethemet Adapter Allied Telesyn 2560 Series PCI 100 Ethemet Adapter AMD PCNET Family Ethernet Adapter BY Andrew ISA Token Ring Adapter 88 Arcnet TCNS Types m 21577 Eileen et Adseker Have Disk 4 Select the PCNET Family Ethernet Adapter from the list as shown above and click OK button 5 Files from your NT distribution will now be needed You may have to insert the CD ROM and specify a directory for the files An example is shown below the CD ROM is drive D Windows NT Setup g Setup needs to copy some Windows NT files Setup will look for the files in the location specified below If you want Setup to look in a different place type the new location When the location is corect click Continue Cancel 6 The port for the Ethernet adapter may now be chosen In the standard configuration the 10Base T port should be used the cable which looks similar to a telephone cable This configuration is shown below AMD PCNET PCI Ethernet Adapter v3 11 xi Full Duplex Default E 7 Click OK to accept settings 8 The network driver should now be installed Protocols Services etc may now be installed and configured for the network in use 6 1 3 Windows for workgroups 3 11 The following steps will
154. s of selected counters will not be latched Counter 0 Select Counter 1 Select Counter 2 Select Reserved Must be 0 INSIDE Technology A S Page 35 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Description Counter Latch Command 0043h PCI ISA Counter Latch Command for counters 0 1 and 2 Must follow a write to Control word register The requested count or status may be read by access to the counter s I O address Bit 7 6 00 Latch counter 0 select 01 Latch counter 1 select 10 Latch counter 2 select 11 Read back command 00 Counter Latch Command 0 Reserved Must be 0 0060h amp 0064h are used by the 8042 compatible keyboard controller Keyboard controller data port 0060h PCI ISA Keyboard input buffer A read of address 60h resets IRQ1 and IRQ12 if enabled Bit 7 0 Keyboard inhibited Bit 6 0 Primary display is VGA 1 Primary display is MDA 0 System BIOS performs diagnostics on the motherboard in an infinite loop Any other diagnostic function Motherboard RAM 256 kB gt 512 Reserved The motherboard passed the diagnostics tests when diagnostic mode was enabled Bit 5 0060h PCI ISA Keyboard output port Bi 0 Keyboard data is being transferred Bi 0 The keyboard clock signal is being used in data transfer Bi 0 PC type mouse being used 1 PS 2 type mouse being used Bi 0 Output buffer full generated 1 Output buffer not full Reserved The
155. sage phase when asserted and Data phase when deasserted Used for 8 and 16 bit transfers I O In Out This control line is received when in Initiator mode or driven when in Target mode It indicates the In direction when asserted and the Out direction when deasserted Used for 8 and 16 bit transfers MSG Message This control line is received when in Initiator mode or driven when in Target mode It indicates a Message phase when asserted and a Command or Data phase when deasserted Used for 8 and 16 bit transfers REQ Request This control line is received by the device when in Initiator mode or driven when in Target mode A target will assert REQ to indicate a byte is ready or is needed by the Target Used for 8 and 16 bit transfers ACK Acknowledge This control line is received by the device when in Target mode or driven when in Initiator mode An Initiator will assert ACK to indicate a byte is ready for or was received from the Target Used for 8 and 16 bit transfers RST Reset This line is received and or driven It is interpreted as a hard reset and will clear all commands pending on the SCSI bus Used for 8 and 16 bit transfers SEL Select This line is driven after a successful arbitration to Select as an Initiator or Reselect as a Target otherwise it is received Used for 8 and 16 bit transfers BSY Busy This line is driven by the Initiator as a handshake during arbitration and received for the rest of the transfe
156. se registers are placed in the predefined header of the PCI configuration space PCI devices can be mapped either to memory or I O space depending on bit 0 in the Base Address register as outlined below INSIDE Technology A S Page 50 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Base Address in I O space Base Address register 0 Reserved 1 VY O Space indicator Base Address in Memory space Base Address register Data is not prefetchable Data is prefetchable No side effects on reads Base register is 32 bits wide and mapping can be done anywhere in the 32 bit Memory space Base register is 32 bits wide but mapping must be below 1M in Memory space Base register is 64 bits wide and mapping can be done anywhere in the 64 bit Memory space N A Reserved I O Space indicator The address space requirement can be determined by writing 1 s to the register and then read the value back The device will return 0 s in all don t care address bits The requirement will be built from the top for example a requirement of 1 address space will be implemented with 1 s in the 12 most significant bits and zero in the rest The first base address is always located at 1Oh in the configuration space whereas the second may be located at either 14h or 18h Subsequent base addresses are placed dependent on the size of the previous base addresses Expansion ROM Base Address Certain types
157. section of the AMIBIOS Setup main menu AMIBIOS issues a warning when any program or virus issues a Disk Format command or attempts to write to the boot sector of the hard disk drive The settings are Enabled or Disabled If enabled the following appears when a write is attempted to the boot sector You may have to type N several times to prevent the boot sector write Boot Sector Write Possible VIRUS Continue Y N _ The following appears after any attempt to format any cylinder head or sector of any hard disk drive via the BIOS INT 13 Hard Disk Drive Service Format Possible VIRUS Continue Y N _ INSIDE Technology A S Page 26 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 5 Default The icons in this section permit you to select a group of settings for all AMIBIOS Setup options Not only can you use these icons to quickly set system configuration parameters you can choose a group of settings that have a better chance of working when the system is having configuration related problems Original Choose the Original icon to return to the system configuration values present AMIBIOS Setup when you first began this AMIBIOS Setup session Optimal You can load the optimal default settings for the AMIBIOS by selecting the Optimal icon The Optimal default settings are best case values that should optimise system performance If CMOS memory is corrupted the Optimal settings are loaded
158. splay may be performed from a program placed in the control panel This program is accessed as follows INSIDE Technology A S Page 70 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 1 In the program manager open the Main group and double click the Control Panel icon This is shown below Print Manager A Read Me Control Panel PIF Editor ClipBook Manager Viewer Windows Accessories Network ___________ f File Options Window Help MS DOS Prompt 2 In the Control Panel double click the ChipsCPL icon as shown below E Control Panel Color Fonts Ports Mouse Desktop Keyboard 2 m Printers International Date Time Enhanced Drivers Fax Sound _ ChipsCPL Changes the configuration of your display driver 3 The Display Driver Control Panel is now started where the options for the display driver can be changed Display Driver Control Panel Screen Size DPI i Refresh 640 X 480 Small 800 X 600 Large 1280 X 1024 Cursor Animation Big Cursor Monitor Selection 013 Universal Sync Current Driver Interlaced 56 Hz 60 Hz 70 Hz 72 He 75 Hz 85 Hz Cancel Version 65554 1024x768 64K Colors Small Font INSIDE Technology A S Page 71 of 134
159. standards this chapter outlines the terms as endorsed by the SCSI Trade Association The SCSI standards are grouped based on two parameters the SCSI Bus Width and Bus Speed refer to the table STA Terms SCSI Bus Width Bits SCSI Bus Speed Bu ipee 2 T gt Fast SCSI PE CE LR Fast Wide SCSI Ultra SCSI Wide Ultra SCSI Ultra2 SCSI Wide Ultra2 SCSI Eodem _ To describe the available bandwidth the terms Fast Ultra and Ultra2 are used where each new term indicates a doubling in bandwidth compared to the previous So the maximum transfer rate of the Ultra SCSI is twice that of a Fast SCSI and the Ultra2 rate twice the rate of an Ultra The Bus Width is described by either the absence of a word or the word Wide The absence means a 8 bit bus and Wide a 16 bit bus where the difference is a doubling in transfer rate In the world of SCSI standards the names SCSI 1 SCSI 2 and SCSI 3 are often used as well The borders between these are often fuzzy for example as manufactures have implemented parts of the suggested SCSI 3 standards in their SCSI 2 devices The major additional functions of the SCSI 2 standard compared to SCSI 1 is the option of Fast and Wide SCSI enabling transfer rates of up to 20 Mbytes sec Also the SCSI 2 standard demands that active termination is used The SCSI 3 standards are still in development but some of the features included will be the Ultra SCSI option allowing for transfers of up to 40 Mbytes
160. sted pair IEEE 1284 Cable up to 10 m distance to LCD bit IOBASE T and AUT Controller on PCI bus with master access capabilities Universal Serial Bus 12 Mbit INSIDE Technology A S Page 3 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Solid State Disk SSD Supports DIP32 Flash or SSD module with up to 8M byte Flash Software driver handles SSD as normal hard disk drive BIOS System American Megatrends Industry standard 128kB Video Chips amp Technologies 44kB INSIDE BIOS extens Setup utility amp SSD code 64kB SCSI BIOS extension Adaptec SCSI Select 24kB 686LCD MG only Watchdog circuit Supervision of power supply and program execution Startup delay Service interval can be selected Real Time Clock and CMOS Memory Date time and system config with battery backup Secure CMOS option Security backup of CMOS memory within Flash BIOS for auto reload if CMOS memory is lost Battery Circuit Exchangeable Li battery CAUTION Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions Note The battery is protected against internal and external shorting On board Peripheral interfaces AT keyboard interface PS 2 mouse interface 2 x RS232C or 1 x RS232C amp 1 x RS 485 serial communi cation interfa
161. system processor address 20 line is inhibited on the system bus Address line 20 in not inhibited Reset system processor This bit should always be kept at 1 NMI Status and Control it 7 This bit must be 0 when writing to port 61h This bit is set if PCI device or main memory detects a system board error and pulses the PCI SERR line This bit must be 0 when writing to port 61h This bit is set if an expansion board asserts IOCHK on the ISA Bus This bit must be 0 when writing to port 61h This bit reflects the Counter 2 OUT signal state This bit must be 0 when writing to port 61h The Refresh Cycle Toggle bit toggles from 0 to 1 or 1 to following every refresh cycle Enable IOCHK NMIs Clear and disable IOCHK NMIs Enable PCI SERR Clear and disable PCI SERR Speaker Output is 0 Speaker Output is the Counter 2 OUT signal value Timer Counter 2 Disable Timer Counter 2 Enable INSIDE Technology A S Page 36 of 134 Port Access 0064h 0064h 0070h 007 1h 0080h 0080h 008 1h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008 008Fh Po i 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Description 0060h amp 0064h are used by the 8042 compatible keyboard controller 0
162. ta is stable and valid when IRDY is asserted and read data is stable and valid when TRDY is asserted Data is transferred during those clocks where both IRDY and TRDY are asserted C BE 3 0 Bus Command and Byte Enables are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 are used as Byte Enables The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data C BE 0 applies to byte 0 Isb and C BE 3 applies to byte 3 msb PAR Parity is even parity across AD 31 00 and C BE 3 0 Parity generation is required by all PCI agents PAR is stable and valid one clock after the address phase For data phases PAR is stable and valid one clock after either IRDY is asserted on a write transaction or TRDY INSIDE Technology A S Page 130 of 134 686LCD S amp 6861 CPU Board Version 1 4 0 8 Dec 1997 is asserted read transaction Once is valid it remains valid until one clock after completion of the current data phase PAR has the same timing as AD 31 00 but it is delayed by one clock The master drives PAR for address and write data phases the target drives PAR for read data phases INTERFACE CONTROL PINS FRAMES Cycle Frame is driven by the current master to indicate the beginning and duration of an access FRAME is asserted to indicate a b
163. te Time ptions Hardware Programs Fonts Internet Keyboard Microsoft Postoffice Network Passwords Power Printers Regional Settings Desktop Display Themes Modems Sounds Find Fast 54 Multimedia Provides system information and changes advanced settings Double click the System icon highlighted above Select the Device Manager tab e Ifthe Network adapters line is present expand the line and remove the AMD network adapters This is done by selecting the line and clicking the Remove button Before removal of the adapter s your screen might look like this lara Derim US tee be uA Flepps diri Harz conii 4 3 i i Fy havol 3 Othe Poy OOM LPT T Speen desine e When all adapters are removed or none were present a new driver can be installed INSIDE Technology A S Page 55 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 2 In order to provide information about the device copy the file NET_IT INF located in the WIN9S directory on the floppy disk to C WINDOWS INF Reboot the computer 4 During the boot the network adapter should be
164. the lt del gt key during the start up sequence when the following appears Hit lt DEL gt if you want to run SETUP The AMIBIOS Setup can be accessed via keyboard mouse or pen Help Screens AMIBIOS Setup provides Help Screens for Advanced Setup Chipset Setup Power Management Setup and Peripheral Setup Help on mouse and keyboard are also available Choose Help by pressing lt Alt gt lt H gt Using a Mouse with AMIBIOS Setup Point and Click Interface AMIBIOS Setup uses the familiar point and click navigation technique The end user can point with the mouse anywhere on the screen click the left mouse button and AMIBIOS Setup control is transferred to the new location The mouse click functions are e single click to change or select both global and current fields and e double click to perform an operation in the selected field Using the Keyboard with AMIBIOS Setup AMIBIOS Setup has a built in keyboard driver that uses simple keystroke combinations ER E Returns to previous page Advances to the next page Automatic AMIBIOS Setup Option Selection If selecting a certain setting for a specific AMIBIOS Setup option that determines the settings for one or more other AMIBIOS Setup options AMIBIOS automatically assigns the dependent settings and does not permit the end user to modify these settings unless the setting for the parent option is changed INSIDE Te
165. the processor and connect it to JPFAN connector 7 Remove the battery protection strip 8 Insert all external cables for hard disk floppy keyboard etc except for flat panel A CRT monitor must be connected in order to change CMOS settings to flat panel support 9 Connect power supply to the CPU Card via the PWRCON 10 Turn on the power 11 Enter the BIOS setup by pressing the delete key during boot up Use the Load BIOS Optimal Defaults feature The Peripheral Setup and the Standard Setup Window must be entered and configured correctly to match the particular system configuration 12 If Flat Panel Display is to be utilised make sure the Panel voltage in the BIOS setup is correct before turning off the power and connecting the display cable and optionally the FPUM Note The CMOS memory may be in a undefined state at power on after a period of no battery back up To load the fail safe CMOS settings press and hold down the lt lt Esc gt gt key during power up INSIDE Technology A S Page 5 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 4 AMIBIOS Setup AMIBIOS Setup configures system information that is stored in CMOS RAM AMIBIOS Setup has an easy to use graphical user interface that will be immediately recognisable to anyone who has ever used Microsoft Windows This AMIBIOS Setup sets a new standard in BIOS user interfaces The Main Setup Screen of the system BIOS is entered by pressing
166. ting is Yes Display Mode at Add On ROM The options are Forced BIOS and Keep Current The selection of this setup question determines the display mode during add on ROM except Video add on ROM initialization If selected as Forced BIOS then before giving control to any add on ROM POST will force the display to be changed to BIOS mode But if no add on ROM is found then the current display mode will remain unchanged even if this setup question is selected as Forced BIOS If selected as Keep Current then the current display mode will remain unchanged EAE INSIDE Technology A S Page 11 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 e Floppy Access Control Setting this option to Read only prevents the system to write to the floppy if the system uses the BIOS for disk access Default is Read Write e Hard disk Access Control Setting this option to Read only prevents the system to write to the hard drive if the system uses the BIOS for disk access Default is Read Write S M A R T for Hard disks Self Monitoring Analysis and Reporting Technology is technology developed to manage the reliability of the hard disks by predicting some but NOT ALL of the future device failures This feature helps BIOS warn the user of the possible device failure thereby giving user a chance to back up the device and replace the device before act
167. to service the watchdog in order to avoid system reset When active the software must service within 1 5 minute after power on and then within the period set up in the next option The service is executed by dummy writing to 2 I O addresses subsequently namely and F3h INSIDE Technology A S Page 23 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Watch Dog Timeout Periods Only valid if above selection is set to Reset The following set up the allowed time between the each service 0 2 0 8 1 2 1 6 2 0 2 4 or 2 8 seconds e Inside Interrupt This option specifies a software interrupt that can be used for backlight and contrast control for flat panels presently it can also access the GP IO s Special drivers are needed for this purpose The options are 45h 47h 461 49h 65h 66h 6 amp h or Off Select Off to disable Inside Interrupt See chapter for usage e High Temperature Limit From PCB revision 20100192 686LCD MG boards and revision 20100164 686LCD S boards a temperature monitoring circuit is included on board The actual temperature close to the CPU is displayed in the Actual field in the BIOS setup The maximum limit for this temperature can be set by clicking on the right field The Low temperature limit is predefined to be lt 5 and will also cause a violation The desired action is chosen in the next option When this limit is exceeded GPIO 5 can be setup to
168. ttachment Unit Interface AUT The signals operate in a pseudo ECL levels The signals could be used externally in conjunction with the DI and CI pairs to make 10 2 Coax BNC Ethernet interface DI DL Differential data input from external Ethernet Attachment Unit Interface AUI The signals operate in a pseudo ECL levels CI CL Differential input pair from external Ethernet Attachment Unit Interface AUI The signal is used to indicate that a collision has been detected on the network media INSIDE Technology A S Page 103 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 16 PC104 Connector PC104XT amp 104 Pull PIN PIN Pull Note U D Ioh Iol Type Signal Signal Type Ioh Iol U D Note ees cp EV eser so oc 542 8 SA3 EE D17 MASTER 546 SAT DRQ7 SA8 4 2 2149 DACK7 O 14 5 9 24 24 D13 DRQ6 SA10 4 2 DACK6 14 SA11 24 24 DRQ5 SA12 4 2 DACK5 SA13 24 24 DRQO SA14 4 2 SA15 4 2 IRQI4 SA16 4 2 IRQIS SA17 4 2 IRQI2 SA18 4 2 IRQII 5 19 4 2 IRQIO AEN 3 12 10 16 3 12 IOCHRD 3 12 MEMCS 16 3 12 500 3 12 10K GND SD1 3 12 SD2 3 12 SD3 3 12 SD4 3 12 SD5 3 12 ive gt gt S 2 Q z 8 iN w w
169. ttings 2 On the Display properties window select the Settings tab as shown below Page 67 of 134 INSIDE Technology A S 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Display Properties 3 Click the Display button and following window should appear Display Type 4 Click the Change button to select another driver The following window should then appear Change Display Actix Chips amp Technologies Cirrus Logic 5 Since the driver should be supplied separately click the Have button 6 The directory for the drivers may now be entered Type A WINNT40 as shown below 7 Insert the Display driver disk and click OK INSIDE Technology A S Page 68 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 Install From Disk xi Insert the manufacturer s installation disk into the drive selected and then click OK Cancel Copy manufacturer s files from Browse 8 The display driver should now listed as shown below Click to accept Change Display x M Choose the manufacturer and model of your display adapter If your display adapter came with an installation disk click on HaveDisk Display 9 Since this driver is not a part of NT4 0 package following message will be shown Third party Driv
170. ture Port JPYUV EJ 00 Ioh Iol Signal Signal Ioh Iol U D Note v TT VPCLK GND 10 HREF 13 144 VRDY GND 17 18 VR 0 x 19 PWE 21122 D Bocce 1732 PWR ex NX NX PWR 20002 c INSIDE Technology A S Page 100 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 13 11 Signal Description Video Capture Port JPYUV 15 Video Capture Data bus input This bus could accept data from external multimedia systems in different YUV and RGB formats The data is transferred directly into video memory and could be shown on line in a scaled window on the screen Video Capture Input Clock VREF Video Capture Vertical Reference Input HREF Video Capture Horizontal Reference Input VRDY Video Capture System Ready Input General Purpose Input Output port controlled by VGA controller DDCCLK Display Data Channel Clock Same signal as in CRT connector Could be used as I2C bus for control of external multimedia systems DDCDAT Display Data Channel Data Same signal as in CRT connector Could be used as I2C bus for control of external multimedia systems INSIDE Technology A S Page 101 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4
171. ual failure hap pens S M A R T capable devices should predict an impending failure and return that information through the Return 5 Status command Note that S M A R T can not predict all future device failures and it should be used as an warning tool not as a tool to predict the device reliability The settings are enabled or disabled The default setting is Disabled Boot Up Num Lock Set this option to Off to turn the Num Lock key off when the computer 15 booted so you can use the arrow keys on both the numeric keypad and the keyboard The settings are On or Off The default settings are On e PS 2 Mouse support Function Set this option to Enabled to specify that IRQ12 will be used for the mouse The settings are Disabled or Enabled This option should be Enabled to use a PS 2 type mouse The Optimal and Fail Safe default settings are Enabled e Primary Display This option specifies the type of display monitor and adapter in the computer The settings are Absent VGA EGA CGA40x25 CGA80x25 or Mono The Optimal and Fail Safe default settings are VGA EGA Password Check This option enables password checking every time the computer is powered on or every time AMIBIOS Setup is executed If Always is chosen a user password prompt appears every time the computer is turned on If Setup 15 chosen the password prompt appears if AMIBIOS is executed The Optimal and Power On default is Setup See setting a password before using thi
172. upt Enable IRQS interrupt Enable IRQ4 interrupt Enable IRQ3 interrupt Enable IRQ2 interrupt Enable IRQI interrupt Enable IRQO interrupt Page 34 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 Port Access Read Description Write 0040h 0043h are used by the 82C54 compatible Programmable timer 1 Timer Timer Counter 1 Counter 0 2 Count 1 Counter 0 2 Count 0040h Programmable interval timer counter 0 status byte format register This status byte can be read following PCI ISA Programmable interval timer counter 0 status byte format register This status byte can be read following an Interval Timer Read Back Command Counter Out Pin State 0 Pin is 0 Pin is 1 Count Register Status Count has been transferred from CR to CE and is available for reading Count has not been transferred from CR to CE and is not yet available for reading Read Write Selection Status Counter Latch Command R W Least Significant Byte LSB R W Most Significant Byte MSB R W LSB then MSB Mode Selection Status Mode 0 selected Mode selected Mode 2 selected Mode 3 selected Mode 4 selected Mode 5 selected Countdown Type Status 0 Binary countdown Binary coded decimal BCD countdown 0040h PCI ISA Counter 0 Access Ports register Bits 7 0 Used to program 16 bit Count register The order of programming LSB and 5 is defined with the Interval Counter Control Register The current count can
173. us transaction is beginning While is asserted data transfers continue When 15 deasserted the transaction 15 in the final data phase or has completed IRDY Initiator Ready indicates the initiating agent s bus master s ability to complete the current data phase of the transaction IRDY is used in conjunction with TRDY A data phase 15 completed on any clock both IRDY and TRDY are sampled asserted During a write IRDY indicates that valid data is present on AD 31 00 During a read it indicates the master is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together TRDY Target Ready indicates the target agent s selected device s ability to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed on any clock both TRDY and IRDY are sampled asserted During a read TRDY indicates that valid data is present on AD 31 00 During a write it indicates the target is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together STOP Stop indicates the current target is requesting the master to stop the current transaction LOCK Lock indicates an atomic operation that may require multiple transactions to complete When is asserted non exclusive transactions may proceed to an address that is not currently locked A grant to start a transaction on PCI do
174. ut device Docking stations OBh Processors OCh Serial bus controllers ODh FEh Reserved FFh Device does not fit in any class Cache Line Size System Cacheline size in units of 32 bits words Latency Timer This register specifies the value of the Latency Timer for this PCI Bus master in units of PCI bus clocks Masters has a programmable timer limiting its maximum tenure on the bus during times of heavy bus loads e Header Type This byte defines the layout of the second part of the predefined header beginning at 10h in Configuration Space and whether the device contains multiple functions as shown below Header Type Bit 7 0 The device is single function device 1 The device contains multiple functions Bit6 0 00h Header Type for all PCI devices except PCI to PCI bridges Olh Header Type is for PCI to PCI bridge BIST Builtin self test Used to invoke self test of devices Does not prevent normal operation of the PCI bus e Base Addresses At power up device independent software needs to build a consistent address map before booting the machine to an operating system This includes determining how much memory is in the system and how much address space is required by the I O controllers With this information the I O controllers are mapped into reasonable locations and system boot proceeds For the BIOS to determine this information in a device independent manner the ba
175. utput with tri state capability TTL compatible Power supply or ground reference pins Typical current in mA flowing out of an output pin through a grounded load while the output voltage is gt 2 4 V DC if nothing else stated Typical current in mA flowing into an output pin from a VCC connected load while the output voltage is lt 0 4 V DC if nothing else stated On board pull up or pull down resistors on input pins or open collector output pins Special remarks concerning the signal To Be Determined INSIDE Technology A S Page 73 of 134 686LCD S amp 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 3 Keyboard Connectors 7 31 Pin row Keyboard Connector JPKBD PIN Pull Signal Type Note 1 KBDCLK 2K7 1 2 Note 1 These signals are connected in parallel to both keyboard connectors The CPU board will not be able to handle two simultaneously connected keyboards 22 Keyboard VCC supply is on board fused with 5A resetable fuse 7 3 3 Signal Description Keyboard Connectors KDBCLK Bi directional clock signal used to strobe data commands from to the PC AT keyboard KBDDAT Bi directional serial data line used to transfer data from or commands to the PC AT keyboard INSIDE Technology A S Page 74 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 7 4 5 2 Mouse Connector JPMSE
176. vices operating on different buses can handle data from the CPU on each set of palette registers on every video device The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Disabled PCI IDE Bus Master Set this option to Enabled to specify that the IDE controller on the PCI local bus has bus mastering capability The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Disabled Off board PCI IDE Card This option specifies if an off board PCI IDE controller adapter card is used in the computer You must also specify the PCI expansion slot on the motherboard where the off board PCI IDE controller card is installed If an off board PCI IDE controller is used the on board IDE controller the motherboard is automatically disabled The settings are Auto 51011 Slot2 Slot3 Slot4 Slot5 or Slot6 If Auto is selected AMIBIOS automatically determines the correct setting for this option The Optimal and Fail Safe default settings are Auto In the AMIBIOS for the Intel Triton chipset this option forces IRQ 14 and 15 to a PCI slot on the PCI local bus This is necessary to support non compliant PCI IDE adapter cards If an off board PCI IDE controller adapter card is installed in the computer you must also set the options Off board PCI IDE Primary and Secondary IRQ Off board PCI Primary IRQ This option specifies the PCI interrupt used by the primary IDE channel on the off
177. when the CPU reads LSR if the are no more errors in the FIFO Bi Transmitter shift and holding registers empty Bi Transmitter holding register empty The controller is ready to accept a new character Bi Break interrupt The last received character was a break character Bi Framing error The stop bit that follows the last parity or data bit is zero Bi Parity error The character has incorrect parity Bi Overrun error A character was sent to the receiver buffer before the previous character was read by the CPU Bi Data Ready A complete incoming character has been received and sent to the receiver buffer register PCI ISA R W Modem status register Bi Data Carrier Detect Bi Ring Indicator Bi Data Set Ready Bi Clear To Send Bi Delta Data Carrier Detect Bit 2 Trailing edge Ring Indicator Bit 1 Delta Data Set Ready Bit 0 Delta Clear To Send PCI ISA R W Scratch pad register 04D0h 04D 1h are used by onboard Interrupt Controller 04D0h PCI ISA R W Interrupt Cntrl 1 Edge level control 04D1h R W Interrupt Cntrl 2 Edge level control OCF9h PCI R W Reset Control 0FEOh 0FE7h may be used by on board Peripheral controller as Synchronous Communications Engine SCE for IrDA communication Depends on choice made in INSIDE setup OFEOh OFE6h Access controlled by Master Block Control register OFE7h Master Block Control register Refer to the SMC IrCC Manual INSIDE
178. wo steps first the code determines if the device has implemented the Expansion ROM Base Address register in the configuration space If so the POST must map and enable the ROM in an unused part of the address space and check the first two bytes for the AA55 signature After finding the proper image POST copies the data into RAM e Interrupt Line The 8 bit interrupt line register is used to communicate which input of the system interrupt controller the device s interrupt pin is connected to and are implemented by all devices that uses an interrupt pin POST software will write the routing information into the register as it initializes and configures the system e Interrupt Pin The Interrupt Pin register tells which interrupt pin the device or device function uses Interrupt Pin register No interrupt pin used INTA pin used INTB pin used INTC pin used INTD pin used MAX LAT and MIN GNT These read only registers specify the devices desired settings for Latency Timer values The value is specified in units of 1 4 us zero means no requirements for the settings MAX LAT is used to specify how often the device needs to gain access to the PCI bus MIN LAT specify how long a burst period the device needs at 33MHz INSIDE Technology A S Page 52 of 134 686LCD S 686LCD MG CPU Board Version 1 4 0 8 December 1997 5 7 Onboard PCI Devices Five PCI devices are embedded on 686LCD S board PCI to ISA bridge
179. y on board hard disk controller for primary 1 IDE port Depends on choice made in INSIDE setup R W Hard disk 0 data register base port O1FIh PCI ISA R Hard disk 0 error register Diagnostic mode Bits 7 3 Reserved Bits 2 0 Diagnostics mode errors No errors Controller error Sector buffer error ECC device error Control processor error Operation mode i Block is not bad Bad block detected i No error Uncorrectable ECC error i Reserved i ID not found ID found i Reserved i Command aborted Command completed i Track 000 found Track 000 not found i DAM found CP 3002 is always 0 DAM not found 1 1 5 W 2 5 R W 01F3h 5 R W 01F4h 5 01F5h 5 R W 01F6h PCI ISA R W Hard disk 0 drive head register Bit 7 1 Reserved Bit 6 0 Reserved Bit 5 1 Reserved Bit 4 Drive select 0 First hard disk drive 1 Second hard disk drive it 3 0 nnnn Head select bits 01F7h PCI ISA R Hard disk 0 status register Bit 7 1 Controller is executing a command Bit 6 Drive is ready Bit 5 Write fault Bi Seek complete Bi Sector buffer requires servicing Bi Disk data read corrected Bi An index Set to 1 each disk revolution Bit 0 Previous command ended with an error 01F7h WwW Hard disk drive 0 command register 020Ch 020Dh and 021Fh are used by AMIBIOS 020Ch R W Reserved for special use by AMIBIOS 020Dh 021Fh Reserved for special use by AMIBIOS 0

User's Manual 686LCD/S & 686LCD/MG CPU Board

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User's Manual 686LCD/S &amp; 686LCD/MG CPU Board

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User's Manual 686LCD/S & 686LCD/MG CPU Board