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SerialLite III Streaming MegaCore Function User Guide

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1. rx frame lock asserted for all the lanes Ix is lockedtodata asserted for all the lanes IX ready stable Deasserted Toggling Indicating transceivers are properly reset Verify that the reconfiguration controller RC is properly hooked up Make sure that the latencies of the reset going into the RC and into the cores phy mgmt clk reset are equal Table 5 3 Sink Link Debug Signals Check the transceiver reference clock Check the cables rx aligned sink rx aligned This active high signal indicates that the lanes are properly aligned This signal should remain asserted for proper operation rx ready sink rx ready An asserted value for this active high signal indicates that the reset sequence for the sink PCS is complete SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback Altera Corporation 5 10 Error Handling UG 01126 2015 05 04 rx crc32 sink rx crc32 This active high signal indicates CRC 32 error from the CRC checker rx frame lock l1anes 1 0 sink rx frame lock This active high signal indicates that four Interlaken synchronization words are found for a given lane rx is lockedto data lanes L5 sink Interlaken phy ip rx sv ilk inst This active high signal indicates that the transceiver channel PLL has locked itself to the incoming data rx
2. Input This signal indicates that all external transceiver PLLs are locked If more than one external transceiver PLL is required for higher lanes each instantiation outputs a bit that indicates whether the PLL providing the high speed clock for a corresponding transceiver has achieved its lock status The pll_locked output signal from the external transceiver PLLs should be ANDed together before being input to the IP core Arria 10 devices only Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Signals Mo gore reset Input Asynchronous master reset for the core Assert this signal high to reset the MAC layer except for the fPLL that is available in Standard Clocking Mode xcvr pll ref f N A Input Reference clock for the transceivers clk Geer Glock Ld 1 N A Input Clock for data transfers across the transmit Output interface e Input Using advanced clocking mode e Output Using standard clocking mode user elock 1 user cock tx Input In the standard clocking mode the core Pucci Output asserts this signal when the core reset signal is high and deasserts this signal when the reset sequence is complete In the advanced clocking mode the core asserts this signal to reset the adaptation module FIFO buffer e Input Using advanced clocking mode e Output Using standard clocking mode interface 1 core_clock
3. Altera Corporation About the SerialLite Ill Streaming IP Core C Send Feedback UG 01126 TN 2015 05 04 Performance and Resource Utilization 2 3 Related Information Standard Clocking Mode on page 4 12 e Advanced Clocking Mode on page 4 13 Performance and Resource Utilization The following table lists the resources and expected performance for different SerialLite III Streaming IP core variations These results are obtained using the Quartus II software targeting the Stratix V GX 5SGXMA7H2F35C2 the Arria V GZ BAGZME7K2FA40I3L and the Arria 10 1OAX115S1F45I1SGES FPGA device Note The numbers of ALMs and logic registers in the following table are rounded up to the nearest 100 Table 2 2 SerialLite Ill Streaming IP Core FPGA Performance and Resource Utilization Date DIISCHOn MAU Number Per Lane ECC ALMs Primary Mode ofLanes Data Rate Mbps 48 Source Standard 24 17400 Disabled 1984 3937 Standard 24 17400 Enabled 2818 5696 902 72 Advanced 24 17400 Disabled 2378 4009 219 87 Advanced 24 17400 Enabled 4003 8412 910 121 Sink Standard 24 17400 Disabled 2930 7409 373 48 Arria Standard 24 17400 Enabled 3673 9047 1052 72 10 Advanced 24 17400 Disabled 4060 7363 452 0 Advanced 24 17400 Enabled 3860 9084 1083 72 Duplex Standard 24 17400 Disabled 4226 10838 561 96 Standard 24 17400 Enabled 5775 14442 1726 144 Advanced
4. Clock Direction Description Domain Clock input for the Avalon MM PHY management interface within the Interlaken PHY IP core or Native PHY IP core This signal also clocks the transceiver reconfiguration interface and sequences the reset state machine in the clock phy mgmt clk Input generation logic phy mgmt clk reset clk phy_mgmt_ Input Global reset signal that resets the entire IP including MAC fPLL available in standard clocking mode and Interlaken PHY IP core or Native PHY IP core This signal is active high and level sensitive phy_mgmt_ addr 8 0 clk phy_mgmt_ Input Control and status register CSR address for Stratix V and Arria V GZ devices SerialLite Ill Streaming IP Core Functional Description C Send Feedback Altera Corporation 4 30 Signals UG 01126 2015 05 04 Clock Direction Description Domain phy_mgmt_addr N 9 Stratix V Phy_mgmt_ Input Control and status register CSR address 01 and Arria V clk for Arria 10 devices Qu The width depends on the number of 11 16 lanes The parameter editor determines Arria 10 the required width for you You have to manually tie this extra bit e phy mgmt addr msb 1 for Transceiver reconfiguration usage phy mgmt addr msb 0 for soft CSR the transceiver reset and loopback control CSR phy_mgmt_ 32 phy_mgmt_ Input CSR write data writedata 31 0 clk phy_mgmt_ 32 phy_mgm
5. Related Information SerialLite III Streaming IP Core Design Example for Stratix V Devices on page 5 1 FIFO ECC Protection In the Quartus II software version 13 1 and higher the SerialLite III IP core can be protected from Single Event Upset SEU changes using error correcting code ECC protection You enable this feature using the ECC protection option in the parameter editor The ECC protection provides additional error status bits that tell you if the ECC was able to perform a correction from the SEU change or if an uncorrectable error has occurred Note Enabling ECC protection incurs additional logic and latency overhead User Data Interface Waveforms The following waveforms apply to the source user interface in source only and duplex cores Figure 4 10 Source Waveform for Burst Mode data 127 0 start_of_burst end_of_burst valid Figure 4 11 Source Waveform for Burst Mode Sync data 127 0 1800 0020 0000 06 18 18 18 18 18 18 18 18 18 1800_0021_0000_06e1_2000_0021_0 18 18 18 18 18 18 synd70 0 Ysfalolol3 clalof3 e 0 alffals e start_of_burst j i i end_of_burst valid The source sync data are picked up at the start_of_burst and end of burst cycle SerialLite Ill Streaming IP Core Functional Description Altera Corporation LJ Send Feedback UG 01126 4
6. then the directory name is snk sim for Stratix V and Arria V GZ devices and snk for Arria 10 devices 3 For duplex mode set the following environment variable e SIM LOCATION to the location where the simulation files for the duplex core are generated For instance if the name of the duplex core is duplex then the directory name is duplex sim for Stratix V and Arria V GZ devices and duplex for Arria 10 devices 4 Setthe parameters in the test env v file to override the testbench default value optional 5 Run the provided scripts to simulate the testbench in the ModelSim Altera SE AE VCS VCS MX NCSim or Aldec Riviera simulators The following table lists the provided scripts Getting Started Altera Corporation LJ Send Feedback 3 14 Simulating and Verifying the Design Table 3 4 Testbench Simulation Scripts UG 01126 2015 05 04 example design name gt example_testbench vsim Attia 10 ModelSim vsim c do Altera SE variation name gt _example seriallite_iii_sv Stratix V id AE run vsim do example testbench vsim Arria V GZ example design name example testbench vcs Arria 10 VCS VCS MX lt variation name gt _example seriallite_iii_sv Stratix V run_vcs sh example_testbench vcs Arria V GZ lt example design name gt example_testbench Arria 10 ncsim NCSim run ncsim sh variation name example seriallite iii sv Stratix V example_testbench ncsim Arria V GZ lt exam
7. 24 17400 Disabled 6032 10836 623 87 Advanced 24 17400 Enabled 7266 16808 1996 193 About the SerialLite Ill Streaming IP Core Altera Corporation CJ Send Feedback UG 01126 2 4 Performance and Resource Utilization 2015 05 04 Parameters Logic Registers Device Direction Clocking Number Per Lane e a Mode ofLanes Data Rate Mbps Source Standard 24 10312 50 Disabled 6257 4511 48 Standard 24 10312 50 Enabled 7191 6636 459 p Advanced 24 10312 50 Disabled 6265 4482 196 87 Advanced 24 10312 50 Enabled 8038 9013 761 121 Stratix Sink Standard 24 10312 50 Disabled 5159 7962 267 48 te Standard 24 10312 50 Enabled 3779 9761 802 72 Arra Advanced 24 10312 50 Disabled 6058 7995 258 0 VGZ Advanced 24 10312 50 Enabled 5891 9789 905 72 Duplex Standard 24 10312 50 Disabled 4680 111819 482 96 Standard 24 10312 50 Enabled 6419 15829 1249 144 Advanced 24 10312 50 Disabled 5582 111779 514 87 Advanced 24 10312 50 Enabled 7018 18393 1410 193 Related Information Fitter Resources Reports More information about Quartus II resource utilization reporting Altera Corporation About the SerialLite Ill Streaming IP Core C Send Feedback Getting Started 2015 05 04 UG 01126 amp Subscribe L J Send Feedback Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your prod
8. Interlaken PHY IP RX Core or Native PHY IP RX Core Interlaken Mode For Arria 10 devices this block is an instance of the Native PHY IP core configured for Interlaken RX only operation For lane rates from 15 625 to 17 4 Gbps the PMA width for Interlaken mode is 64 bits For lane rates up to 15 625 Gbps the PMA width is 40 bits For Stratix V and Arria V GZ devices the Interlaken module is an instance of the Interlaken PHY IP core configured for RX only operation and is generated by the Quartus II parameter editor The core requires a Stratix V Transceiver Reconfiguration Controller for transceiver calibration The interface size is initially equal to the number of transceiver channels that the sink core uses which is the number of lanes Related Information e Arria 10 Transceiver PHY User Guide For more information about the Arria 10 Native PHY IP core e Altera Transceiver PHY IP Core User Guide For more information about the Interlaken PHY IP core Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 SerialLite Ill Streaming Duplex Core 4 9 SerialLite Ill Streaming Duplex Core For Arria 10 devices the duplex core is composed of source and sink cores interfaced with the Native PHY IP core in Interlaken mode For Stratix V and Arria V GZ devices the duplex core is composed of source and sink cores interfaced with the Interlaken PHY IP in duplex mode Interla
9. Some IP cores also simultaneously generate a testbench or example design for hardware testing The top level IP variation is added to the current Quartus II project Click Project Add Remove Files in Project to manually add a qsys file to a project Make appropriate pin assignments to connect ports SerialLite Ill Parameter Editor Based on the values you set the SerialLite III streaming parameter editor automatically calculates the rest of the parameters and provides you with the following values or information e Input data rate per lane e Transceiver data rate per lane e A list of feasible transceiver reference clock frequencies one of which you select to provide to the core e Information related to the core overheads Important If your design targets Stratix V or Arria V GZ devices you cannot migrate your design to Arria 10 devices automatically For Arria 10 devices the transceiver reconfiguration functionality is embedded inside the transceivers Therefore you must re instantiate the IP core to target Arria 10 devices Related Information SerialLite III Streaming IP Core Parameters on page 3 3 Altera Corporation Getting Started C Send Feedback UG 01126 2015 05 04 Arria 10 Designs 3 3 Arria 10 Designs If your design targets Arria 10 devices The parameter editor displays a message about the required output clock frequency of the external TX PLL IP clock For source or duplex modes connect the Transceiver P
10. Guidelines C Send Feedback Altera Corporation 5 8 Source Core Link Debugging UG 01126 2015 05 04 tx_sync_done source tx_sync_done This active high signal indicates that all the lanes are bonded by the Native PHY or Interlaken PHY IP core This signal should be properly asserted for normal operation A rapidly toggling signal indicates that the source FIFO is having either too much or too little data or the core reset is having issues tx_cal_busy source Interlaken_phy_ip_tx sv_ ilk inst Sink transceiver calibration status This active high signal can be used for debugging if the reconfiguration controller is actively calibrating during the initialization sequence Altera Corporation SerialLite Ill Streaming IP Core Design Guidelines CJ Send Feedback UG 01126 2015 05 04 Sink Core Link Debugging Sink Core Link Debugging 5 9 Figure 5 5 Sink Core Link Debugging Flow Chart Sink Link rx_aligned properly asserted yes Signal Integrity Issues Check the transceiver analog parameters Manually visualize and open up the link eye Are there Indicating that the lanes are properly aligned Refer to the Altera Transceiver PHY IP User Guide on how to measure and set the transceiver analog parameters The Transceiver Toolkit provides a reference design that can be used to sweep for proper transceiver analog settings any CRC 32 errors
11. Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Signals 4 23 cee rece SE OCE core_clock Output Clock for data transfer across the sink core interface in the advanced clocking mode interface 1 core_clock Output The core asserts this signal when the core_ clock reset reset signal is high and deasserts this signal when the reset sequence is complete in the advanced clocking mode link_up 1 Standar d Output The core asserts this signal to indicate that clocking user_ the core initialization is complete and is clock ready to transmit user data Advanced clocking core_ clock date 64xN Standar d Output This vector carries the transmitted streaming clocking user_ data from the core clock N represents the number of lanes Advanced clocking core_ clock syne 8 Standar d Output The sync vector is an 8 bit bus The data clocking user_ value at the start of a burst and at the end of a clock burst are captured and transported across the Advanced link clocking core_ Note This vector is not associated with clock Interlaken channelization or flow control schemes valid 1 Standar d Output This single bit signal indicates that the data is clocking user_ selbst clock Advanced clocking core_ clock start_of_burst Standar d Output When the core is in burst mode operation clocking user_ assertion of this signal indicates that the clock information on the data vector is the Advanced
12. Instead the sink application module deasserts the output valid signal to indicate an absence of data coming from the sink adaptation module Sink Adaptation Module The sink adaptation module provides rate adaptation logic between the application module and the Native PHY IP core or Interlaken PHY IP core The adaptation module implements the following functions e Rate adaptation Uses the lane FIFO buffers to do rate matching and absorb any data jitter between the lanes on the recovered clock The FIFO buffers also transfer data between the lanes on the recovered clock It also handles the Interlaken core s bursty write requests to present the user with the streaming interface In standard clocking mode the FIFO buffers also help transfer data between the rx coreclkin and user clock domains e Interlaken framing layer stripping Strips Interlaken framing layer symbols and diagnostic control words from the data stream e Non user idle deletion Strips off any non user idle control words that the source adaptation module inserts Lane Alignment Module The lane alignment module interfaces with the Native PHY or Interlaken PHY IP core to access incoming data This module removes lane skew from the incoming serial data streams and aligns various lanes using the Interlaken s synchronization marker After alignment is achieved the module continuously monitors the synchronization markers in the Interlaken metaframes for any loss of alignment
13. Output In the advanced clocking mode the core clock_reset_tx asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete Limi wip ts 1 Standard Output The core asserts this signal to indicate that clocking the core initialization is complete and is user_clock ready to transmit user data Advanced clocking core_clock data p 64xN Standar d Input This vector carries the transmitted streaming clocking data to the core user_clock N represents the number of lanes Advanced clocking core_clock SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback 4 26 Signals UG 01126 2015 05 04 Standard c Input The sync vector is an 8 bit bus The data clocking value at the start of a burst and at the end of a user iclock burst are captured and transported across the Advanced link clocking Note This vector is not associated with core_clock Interlaken channelization or flow control schemes incra Standard Input This vector indicates that the data is valid clocking user clock Advanced clocking core clock QN E MES Input When the core is in burst mode operation i clocking assertion of this signal indicates that the user_clock information on the data vector is the Advanced beginning of a burst clocking Because continuous mode is one long burst core_clock in this mode the signal is asserted only once at the start of the
14. an NCSIM simulation submodules Contains HDL files for the IP core submodule child IP cores gt For each generated child IP core directory Qsys generates synth and sim sub directories Files Generated for Altera IP Cores Legacy Parameter Editor The Quartus II generates the following output for IP cores that use the legacy MegaWizard parameter editor Altera Corporation Getting Started C Send Feedback UG 01126 ae 2015 05 04 Simulating A Figure 3 3 IP Core Generated Files Ba lt Project Directory gt lt your_ip gt qip Quartus II IP integration file lt your_ip gt v or vhd Top level IP synthesis file your ip bb v Verilog HDL black box EDA synthesis file AL ALA lt your_ip gt bsf Block symbol schematic file lt your_ip gt _syn v or vhd Timing amp resource estimation netlist lt your_ip gt vo or vho IP functional simulation model 2 f your ip inst v or vhd Sample instantiation template P your ip cmp VHDL component declaration file Ta greybox_tmp 3 Notes 1 If supported and enabled for your IP variation 2 f functional simulation models are generated 3 Ignore this directory Simulating Simulating Altera IP Cores in other EDA Tools The Quartus II software supports RTL and gate level design simulation of Altera IP cores in supported EDA simu
15. are another four clock domains in isolation within the transceivers Table 4 3 SerialLite Ill Streaming IP Core Clock Domains and Signals Source Core Standard Advanced Clock Domain Description Clocking Clocking Mode Mode user_clock Source user interface clock phy meme ells Source Native PHY or Interlaken PHY IP core Yes Yes reconfiguration interface clock pll_ref_clk Source transceiver reference clock Stratix V Yes Yes and Arria V GZ only tx_coreclkin Source core clock in standard clocking mode Yes tx clkout Source core clock in advanced clocking mode Yes tx serial clk Transmit transceiver clock Arria 10 only Yes Yes Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Core Clocking 4 11 Clock Domain Description Standard Advanced Clocking Clocking Mode Mode user_clock Sink user interface clock in standard clocking Yes mode pu igus elis Sink Native PHY or Interlaken PHY IP core Yes Yes reconfiguration interface clock Sink Core cvr pll_ref_cik Sink transceiver reference clock Yes Yes rx_coreclkin Sink core clock in standard clocking mode Yes Ex clkout Sink core and user interface clock in advanced Yes clocking mode user clock tz Source user interface clock Yes Yes user_clock_rx Sink user interface clock in standard clocking Yes mode E w
16. based on a fixed ratio however the tx coreclkin operates at the same frequency as tx clkout Related Information Sink Clock Generator on page 4 7 Source Application Module The application module performs the following functions e Burst encapsulation Inserts burst control words into the data stream to define the beginning and the end of streaming data bursts e Idle insertion Inserts idle control words in the standard clocking mode into all lanes of the data stream interface Source Adaptation Module This module provides adaptation logic between the application module and the Native PHY IP core Arria 10 devices or Interlaken PHY IP Stratix V and Arria V GZ devices core The adaptation module performs the following functions e Rate adaptation Includes a dual clock FIFO buffer to cushion the Interlaken PHY IP core s bursty read requests and to provide a streaming user write interface The FIFO also transfers streaming data between the user_clock and tx coreclkin clock domains in standard clocking mode e Control signal translation The state machines maps the control signal semantics on the framing interface to the semantics of the Native PHY or Interlaken PHY IP core TX interface e Non user idle insertion Inserts non user idle control words in the absence of user data to manage the minimum data rate requirements of the Interlaken protocol The control words are removed by the sink adaptation module in the SerialLi
17. file 5 Compile the seriallite iii streaming demo project in the Quartus II software 6 If you have the supported development kit download the project name gt sof file onto the board Refer to the Development Kits Cables page of the Altera website for more information To compile the design example Nios II processor system perform the following steps 1 In a Nios II command window change the directory to demo_control software 2 Type the following command to compile the Nios II processor source batch script sh The script generates a demo_control elf file under the app directory This file can later be downloaded into the FPGA To download the design example and subsystem and operate the design perform the following steps 1 Start the Quartus II software 2 In the Tools menu click Qsys 3 In the Qsys Tools menu click Nios Command Shell gcc4 to launch the Nios II command shell 4 Type the following command to download the demo control elf file into the FPGA on the board and to specify the USB cable number CABLE NUMBER nios2 download g r CABLE NUMBER demo control software app demo control elf 5 Type the following command to start a terminal connection with the board using the same cable number gt nios2 terminal CABLE NUMBER SerialLite Ill Streaming IP Core Design Guidelines Altera Corporation C Send Feedback UG 01126 5 6 Design Example Operation 2
18. output on the sync vector of the sink The sync vector can also be used to include empty information which indicates invalid data at the end of burst In this case the empty value is multiplexed into the sync vector during end o burst The data is again embedded inside and sent over to the receiving party The sink extracts the informa tion and output on the sync vector of the sink Signals The following tables list all the input and output signals of the SerialLite III Streaming IP core Table 4 6 SerialLite Ill Streaming IP Core Source Core Signals Clock Direction Description Domain tx_serial_clk Input This high speed serial clock input from the external transceiver PLL The width is the same as the number of lanes specified in the parameter editor Each bit of the vector corresponds to serial clock of the transmit channel Arria 10 devices only N represents the number of lanes SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback 4 20 Signals UG 01126 2015 05 04 Clock Description Domain tx pll locked Input This signal indicates that all external transceiver PLLs are locked If more than one external transceiver PLL is required for higher lanes each instantiation outputs a bit that indicates whether the PLL providing the high speed clock for a corresponding transceiver has achieved its lock status The p11 locked output signal from the external transcei
19. the Arria 10 simulation testbench for the sink or duplex direction Related Information SerialLite III Streaming IP Core Parameters on page 3 3 Arria 10 Simulation Testbench on page 3 12 Arria 10 versus Stratix V and Arria V GZ Variations on page 4 9 SerialLite Ill Streaming IP Core Parameters Table 3 1 SerialLite Ill Streaming IP Core Parameters Parameter vae Defaut Description O O General Design Options Direction Source Sink Duplex Indicates the direction of the core s variant Duplex Lan s 1 24 4 Specifies the number of lanes equal to physical transceiver links that are used to transfer the streaming data Device speed 1 4 2 Specifies the device speed grade Stratix V and grade Arria V GZ devices only PLL type ATX CMU CMU Selects the transceiver PLL type Stratix V and Arria V GZ devices only Getting Started Altera Corporation CJ Send Feedback SerialLite Ill Streaming IP Core Parameters UG 01126 2015 05 04 eee nt eens Meta frame 200 8191 8191 Specifies the metaframe length in 8 byte words length ECC Yes No No Select to use error correcting code ECC Protection protection to strengthen the FIFO buffers from single event upset SEU changes Clocking and Data Rates Advanced Yes No No Select to use the advanced clocking mode for your clocking mode design The default setting is standard clocking mode Required user Minimum 50 MHz 146 484375 Sp
20. the fPLL reference dock For data rates gt 15 625 Gbps and 17 4 Gbps Arria 10 devices the Core Clock Transceiver User Clock Native PHY or Interlaken PHY IP core generates a clock serial data rate 64 that is used as the fPLL reference clock Domain Clock Domain Domain 3 The PLL generates the source user and core clocks The source and sink user interfaces are driven through the fPLL generated user clock For RX into the Native PHY or Interlaken PHY IP core the transceiver reference clock is only provided as a parameter Note The SerialLite III Streaming IP core uses the transmit serial clock bus tx_serial_c1k and the tx_pll_locked signal to connect the external transmit PLL to the Arria 10 Native PHY IP core Related Information Transmission Overheads and Lane Rate Calculations on page 4 15 Advanced Clocking Mode The advanced clocking mode allows the user to use a user specified clock to interface with the source core This mode is useful when PPM differences between the user clock generated by the fPLL and the user s interface clock are intolerable In the advanced clocking mode the source core is generated with the PPM absorption FIFO wrapper module Similar to the standard clocking mode you must specify the user clock frequency through the SerialLite III Streaming parameter editor Based on the user clock frequency value the Quartus II software automat ically calculates the lane rate and the core clock The p
21. 015 05 04 The terminal should now display an interactive session for the SerialLite III Streaming IP core design example Related Information Development Kits Cables Quartus II Incremental Compilation for Hierarchical and Team Based Design More information about the design compilation Nios II Processor More information about the Nios II processor and its use Design Example Operation Once you download the design and accompanying software into the FPGA you can test the design operation through the interactive session The interactive session provides helpful statistics as well as controls for controlling various aspects of the design You can control the following operations through the interactive session OV Ui WN Enable source Enables the traffic generator and start sending out data Disable source Disables traffic generation Reset source Resets the source core and traffic generator Reset sink Resets the sink core and traffic checker Display error statistics Displays the error statistics Toggle burst continuous mode Resets the source and sink MACs and toggles the traffic generator to generate a burst or continuous traffic stream Toggle CRC error injection for lane 0 Turns CRC error injection off or on for lane 0 SerialLite Ill Streaming Link Debugging The following section describes the link up sequence that you can use when debugging the SerialLite III Streaming IP core Al
22. 18 User Data Interface Waveforms 2015 05 04 Figure 4 12 Source Waveform for Continuous Mode datal127 0 JEDE C X0 snd70 0 TITRE G3 LE lt lt lt Lx LE LOK co gt start of burst end of burst d valid d start of burst pulses for one clock cycle indicating that the data burst starts at that clock cycle end of burst pulses for one clock cycle indicating that the data burst ends at that clock cycle The valid signal indicates valid data It should be turned off between two data bursts that are between the current data burst s end o burst clock cycle and next data burst s start o burst clock cycle The valid signal can be pulled low in the middle of a data burst transferring between the same data burst s start o burst and end o burst indicating non valid data at that clock cycle e The sync vector is used in burst mode It is valid only when start o burst and valia are high Multiple logical channel is time multiplexed into physical channels Sync vector can be used to store the logical channel number that the burst targets The logical channel number is multiplexed into the sync vector during the start of burst The value is embedd
23. 3125 Gbps The effective data rate at the output of the data rate per Overheads transceivers incorporating transmission and other lane overheads The parameter editor automatically calculates this value by adding the input data rate with transmis sion overheads to provide you with a selection of user clock frequency Aggregate Lanes x Input data 36 6210938 Aggregate input data rate that the core can input data rate Gbps support rate Related Information SerialLite III Parameter Editor on page 3 2 Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs If your design targets Stratix V or Arria V GZ devices the transceiver reconfiguration controller is not included in the generated IP core To create a complete system refer to the design example block diagram on how to connect the transceiver reconfiguration controller 2 The clock frequency value is useful if you want to simulate designs at different data rates You should apply the displayed value in your testbench parameters Getting Started CJ Send Feedback Altera Corporation UG 01126 3 6 Files Generated for Altera IP Cores 2015 05 04 Note If your design targets Arria 10 devices the transceiver reconfiguration functionality is embedded inside the transceivers The phy_mgmt bus interface connects directly to the Avalon MM dynamic reconfiguration interface of the embedded Arria 10 Native PHY IP core This interface is provided
24. 7 FIFO ECC Protecti ti T 4 17 User Data Interface W AVELOT IIS sic eceiesio nnitbun ipaa isitvepet ld brise DR Era SE ASNS 4 17 Di E E E A EE E 4 19 Altera Corporation TOC 3 SerialLite III Streaming IP Core Design Guidelines 5 1 SerialLite III Streaming IP Core Design Example for Stratix V Devices 5 1 Design Example CORTDORPEES sssini asri Praeses nasa ioiii 5 3 Design iiu PE M 5 4 Design Example Compilation and Dowload sy cassissccscsonsssstasnscinassiessasacsussiovessesucavisssessndessnisivesecs 5 5 Design Example pera hon acs iscesenivssstanestivcteasctidcacawotesdavesd ied pere ente ve Mer sorely ai 5 6 Serial Lite III Streaming Link Debugging esso tete tbt hrbt rines i kid siente cpu epo tiia adiu Re 5 6 Source Cor Link De rg EIE cerae PRU up RUE xvin D Dati qub eru MR NAMEN E 5 7 Sink Core Link boe T MS 5 9 Error Handling m E 5 10 Additional InfortiatiQno iie eerie ERREUR EE PRISES ERES HERO EUS PIEBU USES oa ba PRESE 6 1 Document Revision History ue erm HOHER REOR ERE SEHE NNI MEE tere RR 6 1 How to Contact Alter si 6 1 Altera Corporation SerialLite Ill Streaming MegaCore Function Quick Reference 2015 05 04 UG 01126 GQ subscribe Send Feedback The Altera SerialLite III Strea
25. Core Generated Files HeMme o Delon O O lt my_ip gt qsys The Qsys system or top level IP variation file lt my_ip gt is the name that you give your IP variation Altera Corporation Getting Started G send Feedback UG 01126 2015 05 04 Files Generated for Altera IP Cores 3 7 lt system gt sopcinfo Describes the connections and IP component parameterizations in your Qsys system You can parse its contents to get requirements when you develop software drivers for IP components Downstream tools such as the Nios II tool chain use this file The sopcinfo file and the system h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave Different masters may have a different address map to access a particular slave component lt my_ip gt cmp The VHDL Component Declaration cmp file is a text file that contains local generic and port definitions that you can use in VHDL design files lt my_ip gt html A report that contains connection information a memory map showing the address of each slave with respect to each master to which it is connected and parameter assignments lt my_ip gt _generation rpt IP or Qsys generation log file A summary of the messages during IP generation lt my_ip gt debuginfo Contains post generation information Used to pass System Console and Bus Analyzer Toolkit information ab
26. HY Reset Controller to the TX PLL to ensure the appropriate HSSI power up sequence For source only Arria 10 implementations the parameter editor does not provide the transceiver reference clock frequency because the user is expected to provide the transmit serial clock If you use an on chip PLL to generate the transmit serial clock you can use the same PLL reference clock frequency that you provide to the core in the sink direction operating at the same user clock frequency or equivalent transceiver lane data rate The SerialLite IP core expects the user to provide the transmitter s serial clock If you compile the IP without the proper serial clock the Quartus II Compiler issues a compilation error Refer to Arria 10 Simulation Testbench for an example design When generating the example testbench the SerialLite IP core instantiates an external transceiver ATX PLL for the transmit serial clock based on the required user clock only when configured in sink or duplex mode The Arria 10 simulation testbench uses the external transceiver ATX PLL The transceiver ATX PLL core is configured with the transceiver reference clock specified in the parameter editor and transmit serial clock To generate the SerialLite III Arria 10 example testbench using the parameter editor select Generate gt Example Designs gt seriallite iii a10 0 example alternatively turn on the Example Design option in the parameter editor Altera recommends that you generate
27. Module in Source F M Sink User gt gt gt 4 gt User Interface Interface Source User Clock Core Clock Core Clock Sink Interface Clock Transceiver Reference Clock or Transmit Serial Clock s Erud Transceiver Transceiver Reconfiguration Reconfiguration Clock Clock For Stratix V and Arria V GZ devices the transceiver reference clock is provided to the Interlaken PHY IP core For Arria 10 devices the transmit serial clock tx_serial_clk is provided to the Native PHY IP Core for TX only For data rates lt 15 625 Gbps Arria 10 Stratix V and Arria V GZ devices the Native PHY or Interlaken PHY IP core generates the core clock Legend serial data rate 40 tx_clkout at the source core and rx_clkout at the sink core For data rates gt 15 625 Gbps and lt 17 4 Gbps Arria 10 devices the Native PHY or Interlaken PHY IP core generates the core clock serial data rate 64 tx_clkout at the source core and rx clkout at the sink core Core Clock Transceiver User Clock The source user interface is derived through the source user dock Domain Clock Domain Domain The sink user interface is driven through the sink interface clock For RX into the Native PHY or Interlaken PHY IP core the transceiver reference clock is only provided as a parameter Note The SerialLite III Streaming IP core uses the transmit serial clock bus tx_serial_c1k and the tx_pll_locked signal to connect
28. P Cores Legacy Parameter Editor 2015 05 04 SS El lt my_ip gt regmap If the IP contains register information the regmap file generates The regmap file describes the register map information of master and slave interfaces This file complements the sopcinfo file by providing more detailed register information about the system This enables register display views and user customizable statistics in System Console lt my_ip gt svd Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system During synthesis the svd files for slave interfaces visible to System Console masters are stored in the sof file in the debug section System Console reads this section which Qsys can query for register map information For system slaves Qsys can access the registers by name my ip v Or my ip vhd HDI files that instantiate each submodule or child IP core for synthesis or simulation mentor Contains a ModelSim script msim_setup tel to set up and run a simulation aldec Contains a Riviera PRO script rivierapro setup tcl to setup and run a simulation synopsys vcs Contains a shell script ves_setup sh to set up and run a VCS simulation synopsys vcsmx Contains a shell script vcsmx setup sh and synopsys sim setup file to set up and run a VCS MX simulation cadence Contains a shell script ncsim setup sh and other setup files to set up and run
29. SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Advanced Clocking Mode 4 13 Figure 4 8 SerialLite Ill Streaming IP Core Block Diagram in Standard Clocking Mode SerialLite Ill SerialLite III Streaming Source Core Streaming Sink Core Native PHY or Native PHY or Application Adaptation Interlaken PHY SerialLite III Interlaken PHY Lane Alignment Adaptation Application Module Module IP Core Streaming Link IP Core Module Module Module Source t Sink User gt F L gt l gt I gt User Interface Interface pes Lt iam Core Clock al Core Clock Source Clock Clock User Clock Generator Generator y Sink User Clock Transceiver Reference Clock Transceiver or Transmit Serial Clock Reference Clock Transceiver Transceiver Reconfiguration Reconfiguration Clock Clock For Stratix V and Arria V GZ devices the transceiver reference clock is provided to the Interlaken PHY IP core For Arria 10 devices the transmit serial clock tx_serial_clk is provided to the Native PHY IP Core for TX only For data rates lt 15 625 Gbps Arria 10 Stratix V and Arria V GZ devices the Native PHY or Interlaken PHY IP core generates a clock Legend serial data rate 40 that is used as
30. SerialLite Ill Streaming MegaCore Function User Guide Last updated for Altera Complete Design Suite 15 0 X subscribe UG 01126 2015 05 04 C Send Feedback 101 Innovation Drive LJ San Jose CA 95134 N DTE BJAN www altera com TOC 2 Contents SerialLite III Streaming MegaCore Function Quick Reference 1 1 About the SerialLite III Streaming IP Core eere 2 1 SerialLite III Streaming PfOLIOCOL a oscisiesetiburden tk kr ert EAMA URN aadi 2 1 SerialLite III Streaming Protocol Operating Modes eet tret aet tias 2 2 Performance and Resource Ut Za thon s ycssussscasacausasiassvnnannsnisedsvesasinsedunpuniaunia ibo tuspbt re Lis pt Da E E 2 3 Ge tting Started Me 3 1 Installing and Licensing IP Cores cssissasissisnsnchsessensnach svanienessdasnitennsavecstiviandsogasphessancvachsnvnnineavedasattuassanesvansas 3 1 OpenCore Plus IP Eval ation eter ee tri eget ei tede KREE E EEEE E EEE aei erre EENE E 3 1 Specifying IP Core Parameters and ODOBRS au bene epus apa al ev ied Ue e A URN LE due 3 2 Sertalbue TIT Parameter EGO ooo ir ie en teet dais ierat Ft p 3 2 PT Ta NOMI ESI SNS E A E E AEN 3 3 SerialLite III Streaming IP Core DAtamelelsss concedant as CI DTE MES Ep abu M 3 3 Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs 3 5 Files Generated for Altera IP Oo1es sccisasenisisaiaroinsiniegeanciaiatesonunntuuieanqiamdaimanaionants 3 6 Files Genera
31. Traffic Generator The traffic generator generates traffic in a deterministic format to verify that data is transmitted correctly across the link Traffic consists of sets of sample words one for each lane on the link that are presented to the source user interface Figure 5 3 Traffic Generator Sample Word Format This figure shows the format of the sample words generated for each lane 3121110 l8 ris s i32 nlolola rl 54 i lo alrla ha ala v olala ruo l4 3 2ltlolo alle 514 l3l2l1 0 B8 7 6 5j 92 1o Byte7 Byte 6 Byte 5 Byte4 Byte3 Byte 2 Byte 1 Byte 0 7 6542076 543 2 1o 7e 5 42 to 7e 5 4 s 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 21 0 Word ID Burst Count Word Count Table 5 1 Traffic Generator Sample Word Fields EINIUEEEER S ERNMMANMMNM WordID _ 63 59 Contains a static value to distinguish which 64 bit word on the user interface that this sample was presented on The Word ID value ranges from 0 to lanes 1 SerialLite Ill Streaming IP Core Design Guidelines J send Feedback Altera Corporation 5 4 Traffic Checker UG 01126 2015 05 04 e a MN Burst 58 32 Tracks the number of bursts used to transfer the sample data This field value Count starts with one after reset and is incremented each time the start_of_burst signal is asserted on the source user interface Word 31 0 Tracks the number of valid sample words that have been transferred across all Count
32. about Altera simulation models refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Related Information Simulating Altera Designs Getting Started CJ Send Feedback Altera Corporation SerialLite Ill Streaming IP Core Functional Description 2015 05 04 UG 01126 GX subscribe send Feedback The SerialLite III Streaming IP core implements a protocol that defines streaming data encapsulation at the link layer and data encoding at the physical layer This protocol integrates transparently with existing hardware and provides a reliable data transfer mechanism in applications that do not need additional layers between the data link and application IP Core Architecture The SerialLite III Streaming IP core has three variations e Source Formats streaming data from the user application and transmits the data over serial links e Sink Receives the serial stream data from serial links removes any formatting information and delivers the data to the user application e Duplex Composed of both the source and sink cores The streaming data can be transmitted and received in both directions All three variations include the Altera Transceiver Native PHY IP core Arria 10 devices or Interlaken PHY IP core Stratix V and Arria V GZ devices that utilizes hardened PCS and PMA modules The source and sink cores use the Native PHY or Interlaken PHY IP core in simplex mode and the duplex core uses
33. agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYAN UG 01126 6 2 How to Contact Altera 2015 05 04 Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical General Email nacomp altera com support Software licensing authorization altera com Related Information e www altera com support e www altera com training e www altera com literature 9 You can also contact your local Altera sales office or sales representative Altera Corporation Additional Information C Send Feedback
34. and easily e Generate time limited device programming files for designs that include IP cores e Program a device with your IP core and verify your design in hardware O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 T UG 01126 3 2 Specifying IP Core Parameters and Options 2015 05 04 OpenCore Plus evaluation supports the following two operation modes e Untethered run the design containing the licensed IP
35. arameter editor provides guidance in selecting a source user clock frequency that meets the transceiver data rate constraints For more information about the lane rate calculation refer to the Transmission Overheads and Lane Rate Calculations section In advanced clocking mode the core clock is faster than the source user clock when data is inserted in the core Therefore the sink user interface may run out of valid data to transmit The valid signal at the sink user interface is deasserted to indicate an absence of data at the sink core since the core clock is greater than the user clock SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback Em UG 01126 Core Latency 2015 05 04 Note The core operates at higher clock rates in Advanced Clocking Mode Therefore when operating in this mode it may be difficult to close timing at higher data rates e g 12 to 15 G and or number of lanes Figure 4 9 SerialLite Ill Streaming IP Core Block Diagram in Advanced Clocking Mode SerialLite Ill SerialLite III Streaming Source Core Streaming Sink Core Native PHY or d Native PHY or Lane PPM Absorption Application Adaptation Interlaken PHY Seriallite mM Interlaken PHY Alignment Adaptation Application Streaming g Module Module Module IP Core Uk IP Core Module Module
36. at the top level Files Generated for Altera IP Cores The Quartus II software generates the following IP core output file structure Figure 3 2 IP Core Generated Files lt your_ip gt qsys System or IP integration file lt your_ip gt sopcinfo Software tool chain integration file lt testbench gt _tb testbench system f lt your_ip gt cmp VHDL component declaration file t Fon iui Fi f your ip bb v Verilog HDL black box EDA synthesis file f your ip inst v or vhd Sample instantiation template testbench tb f lt your_ip gt ppf XML 1 0 pin information file testbench files f lt your_ip gt qip Lists IP synthesis files f your testbench tb csv f lt your_ip gt sip Contains assingments for IP simulation files lt your_testbench gt _tb spd f lt your_ip gt _generation rpt IP generation report lt your_ip gt debuginfo Contains post generation information sim lt your_ip gt html Connection and memory map data simulation files f lt your_ip gt bsf Block symbol schematic l f lt your_ip gt spd Combines simulation scripts for multiple cores lt EDA tool setup scripts ps lt your_ip gt v or vhd Top level simulation file lt your_ip gt v or vhd Top level IP synthesis file f HDI files f simulator setup scripts Table 3 2 IP
37. ation Sink Core Burst code word received during normal operation The sink core asserts error 1 flag for one clock cycle The sink interface receives a burst control word after achieving normal operation Normally the sink interface receives only a single burst control word at the end of link initialization Rate adaptation FIFO buffer underflow in sink interface The sink core asserts error 0 flag for one clock cycle There is an underflow on the rate adaptation FIFO buffer in the sink interface The core behavior depends on the operation mode e Continuous mode error is flagged once an underflow is detected e Burst mode error is flagged only when an overflow occurs during burst data transfer across the user interface SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback Altera Corporation 2015 05 04 UG 01126 Additional Information SX subscribe GC Send Feedback Additional information about the document and Altera Document Revision History ERENEINMENME KH May 2015 2015 05 04 Updated the Performance and Resource Utilization table e Changed the width of sync_rx and sync_tx signals from 4 to 8 bits in Table 6 8 e Added external serial loopback in Figure 6 5 and Figure 6 6 December 2014 12 15 Described Arria 10 support for up to 17 4 Gbps transceiver data rate 2014 Updated core latency numbers Updated the Transmission Overhead
38. beginning of a burst clocking core_ Because continuous mode is one long burst clock in this mode the signal is asserted only once at the start of the data SerialLite Ill Streaming IP Core Functional Description C Send Feedback Altera Corporation 4 24 Signals UG 01126 2015 05 04 end ot burst Standard Output When the core is in burst mode operation clocking user_ assertion of this signal indicates that the clock information on the data vector is the end of a Advanced burst clocking core_ clock vero N 5 Standar d Output This vector indicates the state of the sink clocking user_ adaptation module s FIFO buffer N clock represents the number of lanes Advanced clocking core_ clock e N 4 An SEU error occurred and could not be corrected ECC enabled Don t care ECC disabled e N 3 An SEU error occurred and was corrected ECC enabled Don t care ECC disabled N 2 FIFO buffer overflow N 1 FIFO buffer underflow e N Loss of alignment N 1 0 RX CRC 32 error Table 4 8 SerialLite Ill Streaming IP Core Duplex Core Signals tx_serial_clk Input This high speed serial clock input from the external transceiver PLL The width is the same as the number of lanes specified in the parameter editor Each bit of the vector corresponds to serial clock of the transmit channel Arria 10 devices only N represents the number of lanes tx_pll_locked N A
39. bursts to the source user interface Traffic Checker The traffic checker performs the following inspections to verify that the received data conforms to the expected format Checks each sample word to verify that the expected word ID was received Checks each sample word to verify that the word count value is higher than the word count value from the last valid sample word Verifies that lane de skew has been properly performed by validating that the word count and burst count values from the sample word are the same as the values received from the adjacent lane If the start_of_burst signal is asserted on the user interface verifies that the burst count value in the current sample word is higher than the burst count value from the last valid sample word Otherwise it verifies that the burst count value has not changed Demo Control The demo control module is a Nios II processor system generated in Qsys to control the demo hardware In addition to the Nios II processor system this module also includes reconfiguration control lers for the transceivers and PLL channels in the SerialLite III Streaming IP core The number of reconfi guration interfaces equal to the number of transceivers plus PLL channels for the source and duplex cores and the number of transceivers for the sink cores Demo Management The demo management module implements CSRs to control and monitor the design operation This includes CSRs to monitor and log er
40. cal busy sink Interlaken phy ip rx sv ilk inst Sink transceiver calibration status This active high signal can be used for debugging if the reconfiguration controller is actively calibrating during the initialization sequence Error Handling Table 5 4 Error Conditions and Core Behavior This table lists the error conditions that the core detect and their behavior in response to each condition Source Rate adaptation FIFO The source core Core buffer overflow in asserts the error flag source interface for one clock cycle There is an overflow on the rate adaptation FIFO buffer in the source interface The core behavior depends on the operation mode e Continuous mode error is flagged once an overflow is detected e Burst mode error is flagged only when an overflow occurs during burst data transfer across the user interface Altera Corporation SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback UG 01126 2015 05 04 Error Handling 5 11 Diagnostic code word CRC 32 error The sink core asserts error lanes 3 lane flag for one clock cycle The sink interface detects a metaframe CRC 32 error on one of the lanes These errors are reported on a per lane basis for diagnostic purposes Lane alignment failure during normal operation The sink core asserts error 2 flag for one clock cycle The sink interface detects a loss of lane alignment during normal oper
41. ces Lane rate 67 See description Arria 10 15 625 Gbps lt lane rate lt 17 4 Gbps Lane rate 64 to Lane rate 67 Arria 10 lt 15 625 Gbps and all Stratix V and Arria V GZ Lane rate 40 to Lane rate 67 0 The parameter editor automatically calculates this parameter value based on the general design options Altera Corporation Getting Started C Send Feedback UG 01126 2015 05 04 Transceiver Reconfiguration Controller for Stratix V and Arria V GZ T eer ee ee fPLL Lane rate 64 257 812500 Specifies the fPLL reference clock frequency in reference MHz standard clocking mode clock Lane rate 40 E Me Arria 10 15 625 Gbps lt lane rate lt 17 4 Gbps lane q y ee description rate 64 Arria 10 lt 15 625 Gbps and all Stratix V and Arria V GZ Lane rate 40 Transceiver Range supported 644 53125 Specifies the transceiver reference clock frequency reference by the transceiver MHz The default value for the Input clock frequency is clock PLLs Lane rate N lane rate 16 Sample values of N include 80 64 50 frequency 40 32 25 20 16 12 5 10 and 8 Altera recommends that you select the highest frequency among the available options in the drop down list For Arria 10 source designs set this parameter to none Input data 64 x User clock 9 375 Gbps Input data rate that the core can support rate per lane frequency Transceiver Input data rate x 10
42. data iE andaa Input When the core is in burst mode operation clocking assertion of this signal indicates that the user_clock information on the data vector is the end of a Advanced burst clocking core_clock Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 ess 2015 05 04 Ignals error tx 30r4 Standard clocking user_clock Advanced clocking 4 27 Output This vector indicates an overflow in the source adaptation module s FIFO buffer e Bit 0 Source adaptation module s FIFO buffer overflow e Bit I Source PPM absorption module s core clock FIFO buffer overflow ECC option e MSB 1 An SEU error occurred and was corrected ECC enabled This bit is bit 2 in advanced clocking mode and bit 1 in standard clocking mode Don t care ECC disabled e MSB An SEU error occurred and could not be corrected ECC enabled This bit is bit 3 in advanced clocking mode and bit 2 in standard clocking mode Don t care ECC disabled The width of this signal depends on the clocking mode e 3 Using standard clocking mode e 4 Using advanced clocking mode user_clock_rx 1 N A Output Clock for data transfers across the sink core interface in the standard clocking mode teer plock 1 user_clock_rx Output In the standard clocking mode the core asserts this signal when the core_reset signal is high and deasserts this signal when the reset
43. eady to transmit user data Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Signals 4 21 Clock Direction Description Domain data user_ Input This vector carries the transmitted streaming clock data to the core N represents the number of lanes Syne user_ Input The sync vector is an 8 bit bus The data value at clock the start of a burst and the end of a burst are captured and transported across the link Note This vector is not associated with Interlaken channelization or flow control schemes valid user_ Input This single bit signal indicates that the clock transmitted streaming data is valid SR er eE SUE user_ Input When the core is in burst mode operation clock asserting this signal indicates that the informa tion on the data vector is the beginning ofa burst Because continuous mode is one long burst in this mode the signal is asserted only once at the start of the data end of_burst Pa Input When the core is in burst mode operation cloc SerialLite Ill Streaming IP Core Functional Description C Send Feedback asserting this signal indicates that the informa tion on the data vector is the end of a burst You can optionally send an end of burst signal at the end of continuous mode Altera Corporation 4 22 Signals UG 01126 2015 05 04 Clock Direction Description Domain Serene 3or4 u
44. ecifies the clock generator s fractional PLL clock M MHz fPLL output frequency used to drive the user_ frequenc Esca Las o clock signal This range is device specific and is E y by the supported m 8 b qu qr tied with the lane data rate and fPLL minimal clocking constraints rates In advanced clocking mode this signal specifies the frequency required for the user_clock input Generated Minimum 50 MHz 146 484375 Specifies the actual user clock frequency as user clock aid MHz produced by the fPLL and is ideally the same as frequency Meson Lanie the required clock frequency In certain very high by the supported precision situations where the desired user clock is transceiver data provided up to higher decimal places this value rates can vary slightly due to the fPLL constraints Change the required clock frequency to correct the issue if the minute variation is intolerable Interface Lane rate 64 205 078125 Specifies the clock frequency of the source sink or clock Lane rate 40 MHz duplex user interface in advanced clocking mode frequency See description Arria 10 15 625 Gbps lt lane rate lt 17 4 Gbps Lane rate 64 Arria 10 lt 15 625 Gbps and all Stratix V and Arria V GZ Lane rate 40 Core clock Lane rate 64 to 205 078125 The core clock is used internally between the user frequency Lane rate 67 MHz domain and the Native PHY IP core Arria 10 Fanera devices or Interlaken PHY IP core Stratix V and Arria V GZ devi
45. ed into the data and sent over to the receiving party The sink can extract the channel number from start o burst data bus to output on the sync vector of the sink The sync vector can also be used to include empty information which indicates invalid data at the ena o burst In this case the empty value is multiplexed into the sync vector during end o burst The data is again embedded inside and sent over to the receiving party The sink extracts the information and output on the sync vector of the sink The following waveforms apply to the sink user interface in sink only and duplex cores Figure 4 13 Sink Waveform for Burst Mode Source data 127 0 1800 BEEE iad Ged fied i Gad al al ic Gal Cac IeTe Gal Gia Ua ea ea ia ic Mad ia Gal iad Gl il ia ba a i id bal all i xem Ie synci70 0 d v ofe e e 3 2 oJele 1l2 7 lloll 5 MoBlo lels 4T ofa Te eT t 4 olblsloltlal o al2 al4lal start of burst H end of burst valid Sink i data 127 0 T Fc 6 2 GaGa Gl a a Ga ee espe Ke Gat E Gud e o a e fal p EE Addy EEE Cal Gal d ic Gl a 1800 0003 BERZE synd7 0 i 5 e 3 d start_of_burst end_of_burst valid The source sync data d is picked The sink sync data d is sent up atthestart of burst cycle out at the start_of_burst cycle Altera Co
46. empty cycles where no valid variation output data appears accompanied by data is present at the output are exactly as it was input numerous empty clock _ intolerable use pure streaming cycles standard clocking mode Alternatively create your own sink interface to remove the empty cycles Sink interface Fixed You can include your Advanced Clocking Mode on own logic or FIFO to page 4 13 receive the output data Standard Clocking Mode In the standard clocking mode the SerialLite III Streaming IP core operates in a pure streaming manner exactly replicating the source input data at the sink end The SerialLite III Streaming IP core generates the user clock at both the source and sink to drive the user interface In this mode you initially specify the user clock frequency through the SerialLite III Streaming parameter editor The Quartus II software then automatically calculates the reference clock coming from the Native PHY or Interlaken PHY IP core and the two clock outputs from the fPLL in the clock generator module After the calculation the Quartus II software provides a list of transceiver reference clock values for you to select Depending on the clock constraints the generated value for the user clock should be very close if not identical to the user clock frequency that you specify The Quartus II software shows the generated user clock value as well as transceiver reference clock values Altera Corporation
47. for a limited time e Tethered run the design containing the licensed IP for a longer time or indefinitely This requires a connection between your board and the host computer Note All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times out Specifying IP Core Parameters and Options Follow these steps to specify IP core parameters and options 1 In the Qsys IP Catalog Tools IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation This name identifies the IP core variation files in your project If prompted also specify the target Altera device family and output file HDL preference Click OK 3 Specify parameters and options for your IP variation e Optionally select preset parameter values Presets specify all initial parameter values for specific applications where provided e Specify parameters defining the IP core functionality port configurations and device specific features e Specify options for generation of a timing netlist simulation model testbench or example design where applicable e Specify options for processing the IP core files in other EDA tools 4 Click Finish to generate synthesis and other optional files matching your IP variation specifications The parameter editor generates the top level qsys IP variation file and HDL files for synthesis and simulation
48. g Management Duplex T M lt iH l l RC tahoe eae ene ef Y Y Character Transceiver lt LOD Avalon Master Reconfiguration Controller lt Reset Controller Avalon Master JTAG Export Export UART CD Control Only for Stratix V Devices JTAG Interface i i i i i interface Y Avalon Interconnect Interval NIOS II RAM Ter uM Demo Control Qsys Subsystem Altera Corporation SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback UG 01126 2015 05 04 Design Example Components 5 3 Related Information Arria 10 Simulation Testbench on page 3 12 e SerialLite III Errata Design Example Components The design example consists of following components e Seriallite III Streaming IP core variation e Source fPLL to generate source user clock in advanced clocking mode Traffic generator e Traffic checker Demo control e Demo management SerialLite III Streaming IP Core The SerialLite III Streaming IP core variation accepts data from the traffic generator and formats the data for transmission It also receives data from the link strips the headers and presents it to the traffic checker for analysis The core is generated using the parameter editor in the Quartus II software Source User Clock The fPLL is available only in designs utilizing the advanced clocking mode to generate a user clock for sourcing data into the SerialLite III Streaming IP core
49. gura Not required Required tion Controller Example Testbench Generated dynamically same Generated dynamically same configuration configuration as the IP core as the IP core instance instance Hardware Demonstration Not included Included Design Example When you create an instance of the IP core it generates an example testbench dynamically This testbench has the same configuration as the IP core instance For Arria 10 devices the Native PHY IP core Interlaken mode requires an external transmit PLL Instantiate the external transceiver PLLs and then connect the transmit serial clock output to the SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback 4 10 Clock Domains UG 01126 2015 05 04 tx serial clk input see Signals The Seriallite III Streaming IP core uses a transmit serial clock input bus tx serial clk andtx pl1l locked input to connect the external transmit PLL to the Arria 10 Native PHY IP core Refer to the Arria 10 Transceiver PHY User Guide for more information Related Information Signals on page 4 19 Arria 10 Transceiver PHY User Guide For more information about the Arria 10 Native PHY IP core Altera Transceiver PHY IP Core User Guide For more information about the Interlaken PHY IP core Clock Domains The SerialLite III Streaming IP core contains different clock domains depending on the clocking mode In addition to these clock domains there
50. he Interlaken PHY IP core and how to dynamically reconfigure the PHY Source PPM Absorption Module UG 01126 2015 05 04 This module is implemented when the SerialLite III Streaming IP core is instantiated with advanced clocking mode This module allows you to use your own clock to interface data or to compensate the clock difference between the user clock and source interface clock interface_clock Related Information Advanced Clocking Mode on page 4 13 SerialLite Ill Streaming Sink Core The sink core consists of five major functional blocks Figure 4 6 SerialLite Ill Streaming Sink Core Standard Clocking Mode Native PHY IP RX core Interlaken mode Arria 10 devices Interlaken PHY IP RX core Stratix V or Arria V GZ devices Lane alignment module Clock generator standard clocking mode only Sink adaptation module Sink application module SerialLite Ill Streaming Sink 1 Seriall ite III PHY IP Adaptation RR Streaming Link Core 1 Alignment Module Module woe AA Core Clock j Clock Generator Note 1 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices Altera Corporation P Sink User Interface P Sink User Clock Transceiver Reconfiguration Clock Transceiver Reference Clock Clock Domains SerialLite Il
51. he reconfiguration controllers phy mgmt clk The Native PHY or Interlaken PHY IP core requires the assertion of this reset signal to synchronize with the reconfiguration controller reset signal Note Altera recommends using the same reset signals for both the Native PHY or Interlaken PHY IP core and the reconfiguration controller Link Up Sequence Refer to the topics on source and sink core link debugging for information about the transmit and receive core link up sequence Related Information e Source Core Link Debugging on page 5 7 e Sink Core Link Debugging on page 5 9 Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 CRC 32 Error Injection 4 17 CRC 32 Error Injection In the Quartus II software version 13 1 and higher the SerialLite III IP core supports CRC error injection with the 10G PCS CRC 32 generator This feature enables corruption of the CRC 32 value of the CRC 32 generator To insert CRC errors for a given lane the IP interface includes a CRC error injection control signal Asserting this control signal inserts CRC errors for all the lanes and transceivers that have enabled support for error injection You can enable the CRC error injection for a specific transceiver channel SerialLite III lane by programming the appropriate transceiver PCS CRAM bit The provided example design demonstrates how set the respective CRAM bits using the NIos II processor
52. ion 7 Function Transmission Media Support PCB Chip to Chip Backplane Board to Board SerialLite Ill Streaming Protocol The SerialLite III Streaming IP core implements a protocol which supports the transfer of high bandwidth streaming data over a unidirectional or bidirectional high speed serial link The SerialLite III Streaming IP core has the following protocol features e Simplex and duplex operations e Support for single or multiple lanes e 64B 67B physical layer encoding e Payload and idle scrambling e Error detection O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised t
53. isude eli Native PHY or Interlaken PHY IP core reconfi Yes Yes guration interface clock xcvr pll ref Cclk Transceiver reference clock Yes Yes Duplex Core tx_coreclkin Source core clock in standard clocking mode Yes tx clkout Source core clock in advanced clocking mode Yes rx coreclkin Sink core clock in standard clocking mode Yes rx clko t Sink core and user interface clock in advanced Yes clocking mode tx serial clk Transmit transceiver clock Arria 10 only Yes Yes Core Clocking The SerialLite III Streaming IP core comes with standard and advanced clocking modes select the mode in the parameter editor SerialLite Ill Streaming IP Core Functional Description C Send Feedback Altera Corporation 4 12 Standard Clocking Mode Table 4 4 Comparing Standard and Advanced Clocking Modes UG 01126 2015 05 04 Source user Core generated User provided If the PPM difference between the clocking generated and user clocks is not acceptable use the advanced clocking mode MAC fPLL Uses one fPLL per Does not use fPLLs If the design uses many fPLLs and direction clock crossing is an issue in the user environment use the advanced clocking mode Transmission 1 1 x lt input data rate gt lt Interlaken Overhead gt x The advanced clocking mode overhead lt input data rate gt overhead is less than the standard clocking mode overhead Streaming Pure streaming where the Output streaming data is If
54. it on the user interface at the receiving link at the same rate and without gaps in the stream When operating in this mode a link implementing the protocol looks like a data pipe that can transparently forward all data presented on the user interface to the far end of the link Continuous mode is appropriate for applications that require a simple interface to transmit a single high bandwidth data stream An example of this application is sensor data links for radar and wireless infrastructure With this mode data converters can connect to either end of the link with minimal interface logic This mode requires both ends of the link to operate from a common transceiver reference clock Burst Mode A SerialLite III Streaming link operating in burst mode accepts bursts of data across the user interface and transmits each burst across the link as a discrete data burst Burst mode is appropriate for applications where the data stream is divided into bursts of data An example of this application is uncompressed digital video where the data stream is divided into lines of display raster This mode provides more flexibility to the clocking and also supports multiplexing of multiple data streams across the link Note The minimum required gap between bursts is 2 user clock cycles in standard and advanced clocking modes on the transmit side Therefore the user must provide two extra user clock cycles between an end of burst and the start of the next burst
55. k 1 Transceiver Reconfiguration Clock Transceiver Reference Clock Clock Domains Note 1 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices Source PPM Absorption Module on page 4 6 Source Clock Generator The clock generator in the source core synthesizes the user clock user_clock and core clock signals tx coreclockin from the Native PHY IP core Arria 10 devices or Interlaken PHY IP Stratix V and Arria V GZ devices core s output clock signal tx_clkout This clock generator consists of a fractional PLL and a state machine responsible for clocks generation and reset sequencing The usez clock reset is not released until the fPLL is locked The module is used in the standard clocking mode only Figure 4 5 Clock Generator Block Diagram tx clkout phy mgmt ck reset user clock Fractional j tx_coreclkin PLL Reset State user clock reset Machine e For lane rates lt 15 625 Gbps and all Stratix V and Arria V GZ devices the fPLL generates the user clock user clock tx and tx coreclkin based on fixed ratios determined by the SerialLite III Streaming parameter editor Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Source Application Module 4 5 e For 15 625 Gbps lt lane rates lt 17 4 Gpbs the fPLL outputs the user clock user clock tx
56. ken PHY IP Duplex Core or Native PHY IP Duplex Core Interlaken Mode For Arria 10 devices this block is an instance of the Native PHY IP core configured for duplex Interlaken operation For lane rates from 15 625 to 17 4 Gbps inclusive the PMA width for Interlaken mode is 64 bits For lane rates less than 15 625 Gbps the PMA width is 40 bits For Stratix V and Arria V GZ devices the Interlaken module is an instance of the Interlaken PHY IP core configured for duplex operation and is generated by the Quartus II parameter editor The core requires a Stratix V Transceiver Reconfiguration Controller for transceiver calibration The duplex core initially requires as many reconfiguration interfaces as the number of lanes that the IP core usesplus one for the TX PLL Related Information e Arria 10 Transceiver PHY User Guide For more information about the Arria 10 Native PHY IP core e Altera Transceiver PHY IP Core User Guide For more information about the Interlaken PHY IP core Arria 10 versus Stratix V and Arria V GZ Variations The Arria 10 transceiver is different than the Stratix V or Arria V GZ transceiver Therefore the SerialLite III IP core is implemented differently for these device families and the example testbenches are also different Table 4 2 Differences between Arria 10 and Stratix V or Arria V GZ Transceivers Implementation re Stratix V or Arria V GZ Transceiver PLL Not included Included Transceiver Reconfi
57. l Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Sink Clock Generator 4 7 Figure 4 7 SerialLite Ill Streaming Sink Core Advanced Clocking Mode SerialLite Ill Streaming Sink re 1 SerialLite II PHY IP Adaptation b Sine User interface Streaming Link Core 1 Alignment Module Module D odule I Core Clock i i D gt Sink User Clock Transceiver Reconfiguration Clock Transceiver Reference Clock Clock Domains Note 1 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices Sink Clock Generator The clock generator is similar to the clock generator in the source core and is only instantiated in standard clocking mode The clock generator synthesizes the user clock user_clock and core clock xx_coreclkin signals from the Native PHY IP core Arria 10 devices or Interlaken PHY IP Stratix V and Arria V GZ devices core s output clock signal The clock generator consists of a fractional PLL and a state machine responsible for clock generation and reset sequencing e For lane rates lt 15 625 Gbps and all Stratix V and Arria V GZ devices the fPLL outputs the user clock user clock rx and rx coreclkin based on fixed ratios determined by the SerialLite III Streaming parameter editor e For 15 625 Gbps lt lane rates lt 17 4 Gpbs the fPLL ou
58. lators Simulation involves setting up your simulator working environment compiling simulation model libraries and running your simulation You can use the functional simulation model and the testbench or example design generated with your IP core for simulation The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts generated with the testbench You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts NativeLink launches your preferred simulator from within the Quartus II software Getting Started Altera Corporation LJ Send Feedback UG 01126 3 10 Simulation Parameters 2015 05 04 Figure 3 4 Simulation in Quartus Il Design Flow Design Entry HDL Qsys DSP Builder Altera Simulation Models Quartus II Design Flow g Gate Level Simulation Post synthesis functional Post synthesis simulation netlist functional simulation Analysis amp Synthesis EDA Fitter Netlist Post fit functional a Post it functional lace and route gt F p Writer simulation netlist simulation Post fit timing simulation netlist Optional Post fit timing simulation TimeQuest Timing Analyzer Device Pr
59. ming MegaCore IP function is a lightweight protocol suitable for high bandwidth streaming data in chip to chip board to board and backplane applications The SerialLite III Streaming IP core is part of the MegaCore IP Library which is distributed with the Quartus II software and is downloadable from the Altera website at www altera com Note For system requirements and installation instructions refer to the Altera Software Installation and Licensing Manual Table 1 1 SerialLite Ill Streaming MegaCore Function o mem 0 o Beeh on S O Version 15 0 Release Date May 2015 IP Catalog e Arria 10 SerialLite III Streaming Arria 10 devices Name e SerialLite III Streaming Stratix V and Arria V GZ devices Release Inf ti MENS Ordering IP SLITE3 ST Code Product ID 010A Vendor ID 6AF7 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any E iin egistere products and ser
60. n Getting Started C Send Feedback UG 01126 2015 05 04 Simulating and Verifying the Design 3 13 Figure 3 6 SerialLite Ill Streaming Example Testbench Simplex for Arria 10 Devices Test Environment Device Under Test Source Source Source Source Native Transceiver Absorber Application Adaptation PHY IP TX PLL ee ee eee TX Source Esp Interlaken IP Clock Mode Generator Testbench Device Under Test Sink I i Sink Sink Sink tie Skew m gt Application Adaptation Alignment PHY IP Insertion ies RX pl Sink Interlaken p Clock Mode Generator Simulating and Verifying the Design 1 Set the environment variables e QUARTUS ROOTDIR to the location of the Quartus II software directory e For ModelSim Altera only MODELSIM ALTERA LIBS to the location of the precompiled simulation libraries 2 For simplex mode set the following environment variables e SRC SIM LOCATION to the location where the simulation files for the source core are generated For instance if the name of the source core is src then the directory name is src sim for Stratix V and Arria V GZ devices and src for Arria 10 devices e SNK SIM LOCATION to the location where the simulation files for sink core are generated For instance if the name of the sink core is snk
61. n Testbench for details The IP core variations were generated using the parameter editor These designs serve as a demonstration platform for highlighting the core s features and also show how to integrate the core in a typical system environment O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 5 2 SerialLite Ill Streaming IP Core Design Example for Stratix V Devices Figure 5 1 Design Example for Simplex C
62. o obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 T UG 01126 2 2 SerialLite Ill Streaming Protocol Operating Modes 2015 05 04 e Low protocol overhead Low point to point transfer latency e Uses the hardened Native PHY IP core Arria 10 devices or Interlaken PHY IP core Stratix V and Arria V GZ devices to reduce soft logic resource utilization SerialLite Ill Streaming Protocol Operating Modes The protocol defines two operating modes for different applications continuous and burst mode This section defines these two operating modes and describes the targeted application models and their key characteristics The following table shows the key differences of the two operating modes Table 2 1 Continuous vs Burst Mode Characteristics Characteristics Continuous Mode Burst Mode Buffering Minimal Burst size Can connect directly to a data converter ADC Yes No DAC Asynchronous clock and data recovery support No Yes The IP core that you generate can be in either mode There is no parameter option to select between continuous and burst modes The selection depends on how you provide data at the Avalon ST TX interface Continuous Mode A SerialLite III Streaming link operating in continuous mode accepts and transmits user data over the link and presents
63. ogrammer Note Post fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current version of the Quartus II software Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models support fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Related Information Simulating Altera Designs Simulation Parameters After design generation simulation files are available for you to simulate your design To simulate your design ensure that the SerialLite III Streaming IP core source and sink cores are both generated with the same parameters or are duplex cores e Stratix V and Arria V GZ files are located in the variation name sim directory e Arria 10 files are located in the variation name gt directory The example testbench simulates the core using the user specified configuration Altera Corporation Getting Started C Send Feedback UG 01126 2015 05 04 Simulation Parameters 3 11 Table 3 3 Stratix V and Arria V GZ Testbench Default Simulation Parame
64. ore in Standard Clocking Mode UG 01126 2015 05 04 Simplex Normal Clocking Variation poA ce 3 T Seriallite Il a alas Traffic Streaming gt Generator ia Source Demo Management SerialLite lll Streaming Traffic i_ lal A i k l Link Rx Checker 1 lt E A reaming Sink A Transmit PLL Ge ase er Seal Ae ec ee Sees Sink Transceivers Source Transceivers Reconfiguration Demo Management Reconfiguration Interfaces mgmt reset n Interface Interfaces Y Y Character Avalon Master Transceiver Transceiver Avalon Master JTAG lt LO E Reconfiguration 4 Reset Controller gt Reconfiguration E UART LCD xport xport JTAG Control Controller Controller Interface k f interface i i i i Avalon Interconnect Y Interval NIOS II RAM Timer CPU Demo Control Qsys Subsystem Figure 5 2 Design Example for Duplex Core in Advanced Clocking Mode Duplex Advanced Clocking Variation pencil ete E 3 Traffic l 4 Generator fPLL gt t gt l Traffic SerialLite Ill Demo Checker M Streamin
65. out the Qsys interconnect The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect lt my_ip gt qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software lt my_ip gt csv Contains information about the upgrade status of the IP component lt my_ip gt bsf A Block Symbol File bsf representation of the IP variation for use in Quartus II Block Diagram Files bdf lt my_ip gt spd Required input file for ip make simscript to generate simulation scripts for supported simulators The spd file contains a list of files generated for simulation along with information about memories that you can initialize lt my_ip gt ppf lt my_ip gt _bb v The Pin Planner File ppf stores the port and node assignments for IP components created for use with the Pin Planner You can use the Verilog black box _bb v file as an empty module declaration for use as a black box lt my_ip gt sip Contains information required for NativeLink simulation of IP components You must add the sip file to your Quartus project lt my_ip gt _inst v or _inst vhd HDL example instantiation template You can copy and paste the contents of this file into your HDL file to instantiate the IP variation Getting Started LJ Send Feedback Altera Corporation UG 01126 3 8 Files Generated for Altera I
66. ple design name gt example_testbench aldec Arria 10 Aldec Riviera lt variation name gt _example seriallite_iii_sv Stratix V run_aldec sh example_testbench aldec Arria V GZ By default the parameter editor generates simulator specific scripts containing commands to compile elaborate and simulate Altera IP models and simulation model library files You can copy the commands into your simulation testbench script or edit these files to add commands for compiling elaborating and simulating your design and testbench Table 3 5 Altera IP Core Simulation Scripts ModelSim lt Variation name gt _sim mentor Stratix V Altera SE Arria V GZ msim_setup tcl AE lt variation name gt sim mentor Arria 10 lt variation name gt _sim synopsys vcs Stratix V VCS Arria V GZ vcs_setup sh lt variation name gt sim synopsys vcs Arria 10 lt variation name gt _sim synopsys vcsmx Stratix V vcsmx_setup sh VCS MX Arria V GZ synopsys_sim setup lt variation name gt sim synopsys vcsmx Arria 10 Altera Corporation Getting Started C Send Feedback UG 01126 2015 05 04 Simulating and Verifying the Design 3 15 variation name sim cadence Stratix V NCSim Arria V GZ ncsim setup sh variation name gt sim cadence Arria 10 variation name sim aldec Stratix V Al iu Ri ao Arria V GZ rivierapro_set tcl iviera lt variation name gt sim aldec Arria 10 For more information
67. ree channels because three channels share an Avalon MM slave interface which connects to the Transceiver Reconfiguration Controller IP core Conversely you cannot connect the three channels that share an Avalon MM interface to different Transceiver Reconfiguration Controller IP cores or you will receive a Fitter error Note The clocks in the design generated SDC file seriallite_iii_streaming sdc are set to static frequency You should adjust these clocks to the frequency used for the design Related Information Altera Transceiver PHY IP Core User Guide More information about the Interlaken PHY IP core Design Example Compilation and Download After generating the IP core design example you can compile the design example for a SerialLite III Streaming two lane loopback design The design example files are located in the lt variation name gt _example seriallite_iii_sv directory Note The design example consists of a Qsys subsystem and Nios II processor system You must compile both systems for the design example to operate correctly To compile the design example Qsys subsystem perform the following steps 1 Open a Nios II command window 2 Change the project directory to demo_control 3 Type the following command to set up the required libraries and compile the generated design example gt source build_demo_control sh 4 In the Quartus II software change the directory to demo and open the seriallite_iii_streaming_ demo qpf
68. refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Related Information Simulating Altera Designs Getting Started Altera Corporation J send Feedback UG 01126 3 12 Arria 10 Simulation Testbench 2015 05 04 Arria 10 Simulation Testbench If your design targets Arria 10 devices the generated example testbench is dynamic and has the same configuration as the IP except for the metaframe length When you choose the sink or duplex direction the parameter editor generates an external transceiver ATX PLL for use in the Arria 10 testbench Therefore Altera recommends that you generate the Arria 10 simulation testbench for designs using the sink or duplex direction Note The Arria 10 example testbench includes the external transceiver PLL the IP core does not include the transceiver PLL for these devices Figure 3 5 SerialLite III Streaming Example Testbench Duplex for Arria 10 Devices Test Environment Device Under Test Duplex Mode Source Source Source Transceiver Absorber Application Adaptation TXPLL SS Loopback lt Clock Native A Generator PHY IP estbenc ss Duplex l Interlaken Sink Sink Sink Mode Pi sow m gt Application Adaptation Alignment TE p nsertion I PSS See eee ee Sink 4 Clock Generator Altera Corporatio
69. ria V 92xN GZ devices only cs N represents the number of lanes core 46xN Duplex core 92xN tx serial data F Output The serial output data from the core N represents the number of lanes zx serial data u Input The serial input data to the core N represents the number of lanes Note For Arria 10 devices the phy_mgmt bus interface connects to the reconfiguration interface of the instantiated Native PHY IP core Related Information Altera Transceiver PHY IP Core User Guide More information about the Interlaken PHY IP core signals SerialLite Ill Streaming IP Core Functional Description C Send Feedback Altera Corporation 2015 05 04 SerialLite Ill Streaming IP Core Design Guidelines UG 01126 amp Subscribe L J Send Feedback SerialLite Ill Streaming IP Core Design Example for Stratix V Devices The SerialLite III Streaming IP core for Stratix V devices includes design examples for its four variations SerialLite III Streaming simplex core in standard clocking mode SerialLite III Streaming duplex core in standard clocking mode SerialLite III Streaming simplex core in advanced clocking mode SerialLite III Streaming duplex core in advanced clocking mode Note In ACDS 15 0 the SerialLite III streaming IP core only includes a preset variant of hardware design example for Arria 10 devices Use the provided Arria 10 example testbench design as a guide to implement your design Refer to Arria 10 Simulatio
70. rors that occur during the operation Nios II Processor Code The Nios II processor controls the options exercised in the design example The code also enables CRAM bits for CRC 32 error injection support The error injection support in 10G PCS is based on groups of three channels or triplets Setting the corresponding bit for a given channel in the triplet enables CRC error injection for all of the lanes that use any channel in the given triplet The design example sets the bit for channel 0 that is connected to lane 0 in the example design Therefore CRC error injection is exercisable for lane 0 only Refer to the Nios II processor source code demo_control c for information on setting bits for other channels Design Setup The design example targets the Transceiver Signal Integrity Development Kit Stratix V GT Edition The design includes an SDC script as well as a QSF with verified constraints and settings for a 2 lane design in Altera Corporation SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback UG 01126 2015 05 04 Design Example Compilation and Download 5 5 loopback If you use the design example with another device or development board you may need to update the device setting and constraints You must use correct pin constraints when using the core in simplex mode or when using more than one reconfiguration controller The synthesized design typically includes a reconfiguration interface for at least th
71. rporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Signals 4 19 Figure 4 14 Sink Waveform for Continuous Mode data 127 0 f EEE e e EEGOLTD sync 7 0 0 8 qq 8 d start of burst end of burst valid d e start of burst pulses for one clock cycle indicating that the data burst starts at that clock cycle end of burst pulses for one clock cycle indicating that the data burst ends at that clock cycle e The valid signal indicates valid data It is turned off between two data bursts that are between the current data burst s end o burst clock cycle and the next data burst s start o burst clock cycle The valid signal can be pulled low in the middle of a data burst after a data burst s start o burst and before the data burst s end o burst indicating non valid data at that clock cycle e The sync vector is used in burst mode The sync data picked up at the source s start o burst high cycle is sent out at the sink as shown in the waveform Multiple logical channel is time multiplexed into physical channels Sync vector can be used to store the logical channel number that the burst targets The logical channel number is multiplexed into the sync vector during the start o burst The value is embedded into the data and sent over to the receiving party The sink can extract the channel number from start of burst data bus to
72. rting this signal indicates that the user clock information on the data vector is the Advanced beginning of a burst docking Because continuous mode is one long burst core clock in this mode the signal is asserted only once at the start of the data ene of burst rz j Standar d Output When the core is in burst mode operation clocking asserting this signal indicates that the user_clock information on the data vector is the end of a Advanced burst clocking You can optionally send an end of burst core_clock signal at the end of continuous mode Altera Corporation SerialLite IIl Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Signals 4 29 Standard Srror Tx Output This vector indicates the state of the sink clocking adaptation module s FIFO buffer N user_clock represents the number of lanes Advanced e N 4 An SEU error occurred and could clocking not be corrected ECC enabled Don t core_clock care ECC disabled e N 3 An SEU error occurred and was corrected ECC enabled Don t care ECC disabled e N 2 FIFO buffer overflow e N 1 FIFO buffer underflow e N Loss of alignment e N 1 0 RX CRC 32 error crc error Standard Input This signal is used for CRC 32 error inject clocking injection user clock tx Advanced clocking core_clock_tx Table 4 9 Interlaken PHY IP Core Signals and Native PHY IP Core Signals Interlaken Mode
73. s and Lane Rate Calculations on page 4 15 Minor text changes August 2014 2014 08 18 Added information about Arria 10 support June 2014 2014 06 30 Replaced references to MegaWizard Plug In Manager with IP catalog or parameter editor Minor text changes November 2013 11 04 Added information on CRC 32 error injection 201 HS Added information on the FIFO ECC protection option May 2013 2019 0519 atal reas How to Contact Altera Table 6 1 Altera Contact Information Technical support Website www altera com support 9 You can also contact your local Altera sales office or sales representative 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly
74. sequence is complete reset_rx interface 1 core_clock Output Clock for data transfers across the sink core clock CER interface in the advanced clocking mode interface 1 core_clock Output In the advanced clocking mode the core clock reset rx asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete SerialLite Ill Streaming IP Core Functional Description Altera Corporation GJ send Feedback 4 28 Signals UG 01126 2015 05 04 Standard Link_up_rx Output The core asserts this signal to indicate that clocking the core initialization is complete and is user_clock ready to transmit user data Advanced clocking core_clock cata Tz 64xN Standar d Output This vector carries the transmitted streaming clocking data from the core user_clock N represents the number of lanes Advanced clocking core_clock SYBC EX 8 Standar d Output The sync vector is an 8 bit bus The data docking value at the start of a burst and at the end ofa user clock burst are captured and transported across the Advanced link clocking Note This vector is not associated with core_clock Interlaken channelization or flow control schemes valid rz 1 Standard Output This vector indicates that the data is valid clocking user_clock Advanced clocking core_clock start_of_burst_ Standar d Output When the core is in burst mode operation n docking asse
75. ser clock Output This vector indicates an overflow in the source adaptation module s FIFO buffer e Bit 0 Source adaptation module s FIFO buffer overflow e Bit 1 Source PPM absorption module s FIFO buffer overflow e Bit 2 An SEU error occurred and was corrected ECC enabled Don t care ECC disabled e Bit3 An SEU error occurred and could not be corrected ECC enabled Don t care ECC disabled The width of this signal depends on the clocking mode e 3 Standard clocking mode e 4 Advanced clocking mode crc error inject user clock Input This signal forces CRC 32 errors when CRC 32 error injection is enabled in the transceiver channels The CRC 32 error injection is enabled via the transceiver reconfiguration controller Table 4 7 SerialLite Ill Streaming IP Core Sink Core Signals Core TeSEL Input Asynchronous master reset for the core Assert this signal high to reset the MAC layer except for the fPLL that us available in standard clocking mode weve pli ref lt j N A Input Reference clock for the transceivers elk user_elock 1 N A Output Clock for data transfers across the sink core interface in the standard clocking mode User clock 1 user_clock Output The core asserts this signal when the core_ reset reset signal is high and deasserts this signal when the reset sequence is complete in the standard clocking mode Altera Corporation SerialLite
76. services ANU S p AN 101 Innovation Drive San Jose CA 95134 UG 01126 ba IP Core Architecture 2015 05 04 Duplex e Data encapsulation and decapsulation e Generation and removal of Idle Control Words e User synchronization and burst marker insertion and deletion The simplex and duplex cores support the following clocking schemes e Standard clocking This mode is for pure streaming designs in which the core provides input output clocks to drive the user logic Pure streaming operation ensures an exact replica of the output data as it was presented at the input without any idle cycles at the output continuous data valid e Advanced clocking This mode allows the core s input interface to be clocked with the user preferred clock by trading off pure streaming operation Figure 4 1 SerialLite Ill Streaming Simplex Core Standard Clocking SerialLite Ill Streaming Source SerialLite Ill Streaming Sink N PHY IP Lanes PHY IP i T Application Adaptation Adaptation En Application gt Sink User Source User Module P Module gt Transmit 4 Receive Alignment Module Module Interface Core 1 Core 1 kg Interface Module Source 4 t p gt Sink Reconfiguration Reconfiguration Controller Note Con
77. t the higher range data rates from 15 625 to 17 Gbps Lane Data Rate in Standard Clocking Mode User Clock Frequency x 1 1 x 64 gt Input Data Rate Interlaken Overheads Note Calculations with 40 and 64 for the lane data rate in standard clocking mode are for the PMA width interfaces Using these calculations the following overhead can be derived Transmission Overheads in standard clocking mode 1 1 Note Assuming maximum metaframe overhead with a metaframe size of 200 the standard clocking mode overheads are independent of Interlaken overheads For more details refer to the SerialLite III data efficiency calculator Tip You can obtain the SerialLite III Streaming MegaCore Function Data Efficiency Calculator for 28 nm Altera devices from your local Altera sales representative or by emailing SLITI_support altera com Therefore the lane rate in the standard clocking mode equals Lane Rate Input Data Rate x 1 1 In the advanced clocking mode the transmission overheads equals the Interlaken overheads because no PLL is present Therefore the lane rate in advanced clocking mode equals Lane Rate Input Data Rate x Interlaken overheads Reset Each core has a separate active high reset signal core_reset that asynchronously resets all logic in the core Each core also includes the Native PHY or Interlaken PHY IP reset signal phy_mgmt_clk_reset This reset signal must be on the same clock domain as the clock used to drive t
78. t_ Output CSR read data readdata 31 0 clk phy mgmt write E ee Input Active high CSR write signal c DhY mom Teac 1 ea Input Active high CSR read signal c phy_mgmt_ 1 phy_mgmt_ Output CSR read or write request signal When WEEPEISCIQURSE clk asserted this signal indicates that the Avalon MM slave interface is unable to respond to a read or write request zeconfig busy 1 ee Input For Stratix V and Arria V GZ devices c when asserted this signal indicates that a reconfiguration operation is in progress and no further reconfiguration operations should be performed You can monitor this signal to determine the status of the Transceiver Reconfiguration Controller For Arria 10 devices this signal is present but unused tie this signal to 1 b0 9 For more information about this bit refer to the Interlaken PHY Registers table in the Altera Transceiver PHY IP Core User Guide Altera Corporation SerialLite Ill Streaming IP Core Functional Description GJ send Feedback UG 01126 2015 05 04 Signals 4 31 Clock Direction Description Domain reconfig_to_ Source Phy_mgmt_ Input Dynamic reconfiguration input for the XCVr core clk Interlaken PHY IP Stratix V and Arria V 140xN GZ devices only Sink N represents the number of lanes core 70xN Duplex core 140xN reconfig fron Source Phy_mgmt_ Output Dynamic reconfiguration output for the ee core clk Interlaken PHY IP Stratix V and Ar
79. te III link partner Interlaken PHY IP TX Core or Native PHY IP TX Core Interlaken Mode For Arria 10 devices this block is an instance of the Native PHY IP core configured for Interlaken TX only operation For lane rates from 15 625 to 17 4 Gbps inclusive the PMA width for Interlaken mode is 64 bits For lane rates less than 15 625 Gbps the PMA width is 40 bits For Stratix V and Arria V devices the Interlaken PHY IP TX core is an instance of the Interlaken PHY IP core configured for TX only operation The core requires a Transceiver Reconfiguration Controller for transceiver calibration The number of channels programmed for configuration in the Transceiver Reconfiguration Controller depends on the IP core s operation mode For example e if the design is a simplex RX only design the reconfiguration interfaces is equal to the number of lanes e ifthe design is a simplex TX only design or a duplex design the reconfiguration interfaces is equal to the number of lanes x 2 Related Information e Arria 10 Transceiver PHY User Guide For more information about the Arria 10 Native PHY IP core 9 The framing interface is to frame every data burst with the Start of Burst Sync and End of Burst and sequence them to the PHY interface SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback 4 6 Source PPM Absorption Module Altera Transceiver PHY IP Core User Guide For more information about t
80. ted for Altera IP Cores Legacy Parameter Editor sse 3 8 EDLC LIAS D 3 9 Simulating Altera IP Cores in other EDA TO0l iei tenente oa eti x idit eiit urit ede 3 9 Sim latior Paramete S aseo ci oerte bai o dida fpa en o date dipaiqqd deb cd 3 10 Axria 10 Simulation Teste lscisscscssieachavianassssussivsancvecasnacvas anini 3 12 Simulating and Verifying the D SIBH serenus toit nin erai b Ru tein UD Y up Rn binis 3 13 SerialLite III Streaming IP Core Functional Description 4 1 TP Core Vii M 4 1 SerialLite III Streaming Stree LUTB ooo ubeoRo pn E RERO DI teas RUD MUI DE 4 3 SerialLite LII Streaming Sink COT sanctus atl I eH PR trn tla eb f ik EAM dpa aani 4 6 SerialLite IIT Streaming Duplex COT ioo EH Ip CX RON SION MI IIS ARR IM I RN IE 4 9 Arria 10 versus Stratix V and Arria V GZ Variations netter tentiae tes 4 9 Clock DOMAIN M PM 4 10 orci iu 4 11 Core Datency rensie a EE a Er deli ine n erede eid 4 14 Transmission Overheads and Lane Rate Calculations sssssissssssssssssasnisnsssssscassssnivasesnasv ssansensnvansess 4 15 MM 4 16 Link BI ilr T 4 16 CRC 32 Error Injection eie ee CE I EHE QUI EGRE EDETRG quU LUE Ue Da HH e HEAR DRR FRU 4 1
81. tera Corporation SerialLite Ill Streaming IP Core Design Guidelines C Send Feedback UG 01126 2015 05 04 Source Core Link Debugging Figure 5 4 Source Core Link Debugging Flow Chart link_up asserted Data pass through to the transceivers pll_lock asserted Indicating that the transceiver PLLs are locked to input frequency tx_ready asserted yes Source Core Link Debugging 5 7 tx_sync_done properly asserted Are the transceivers properly reset Are the channels properly bonded Check the Transceiver Verify that the reconfiguration controller RC Make sure the Core clock is in between Reference Clock is properly hooked up lane rate 40 and lane rate 67 Make sure that the latencies of the reset going into the Make sure that phy_mgmt_clk_reset remains RC and into the cores phy_mgmt_clk_reset are equal de asserted Table 5 2 Source Link Debugging Signals link up Top level source signal The core asserts this signal to indicate that initialization sequence is complete and the core is ready to transmit the data xcvr_pll_locked source xcvr pll locked tx ready source tx ready This active high signal indicates that the transceivers are locked to the reference clock This active high signal indicates that the reset sequence for the source PCS is complete and is ready to accept data SerialLite Ill Streaming IP Core Design
82. ters Generated user clock Standard clocking 145 98375 frequency user_clock_ MHz ERSA Advanced clocking 146 484375 Lanes lanes 2 Transceiver reference clock 644 53125 MHz frequency p11 ref freq Transceiver data rate per 10312 5 Mbps lane data rate Meta frame length meta 200 frame length fPLL reference clock 257 8125 MHz Not used in advanced clocking mode frequency re erence clock frequency Core clock frequency 205 078125 MHz Not used in advanced clocking mode coreclkin frequency Simulation specific parameters Total samples to transfer 2000 Total samples to transfer during simulation total samples to transfer Mode mode Continuous burst The testbench environment may automati cally choose one of the modes depending on the random seed with which it is provided Refer to the simulation scripts listed in Table 3 4 for details Skew insertion enable Yes Skew testing is enabled The testbench skew insertion enable environment randomly inserts skew in the lanes within the range 0 107 UI ECC protection enabled 0 When set the core is simulated with the ecc enable ECC enabled variant Use the ECC enabled variant in the test environment When ECC mode is disabled the two most significant bits of the error buses in the source or sink direction are don t care For more information about Altera simulation models
83. the Native PHY or Interlaken PHY IP core in duplex mode Table 4 1 IP Core Variant and Function Source e Data encapsulation e Generation and insertion of Idle Control Words e Lane striping for multi lane link e User synchronization and burst marker insertion Sink e Multi lane alignment e Data encapsulation removal e Idle Control Words removal e Lane de striping e User synchronization and burst marker demultiplexing O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
84. the external transmit PLL to the Arria 10 Native PHY IP core Related Information Transmission Overheads and Lane Rate Calculations on page 4 15 Core Latency The table below lists the latency measurement for the SerialLite III Streaming duplex core in standard and advanced clocking mode An average value is taken from a set of samples during hardware testing For a loopback scenario the core latency measurement is based on the round trip latency from the TX core input to RX core output Altera Corporation SerialLite Ill Streaming IP Core Functional Description C Send Feedback UG 01126 2015 05 04 Table 4 5 Latency Measurement for Duplex Core pense Sa of Lanes Per Transmission Overheads and Lane Rate Calculations 4 15 Parametes o O rameters Lane Data Rate Latency ns Mbps Standard 5 10 312 50 Advanced 5 10 312 50 213 Arria 10 Standard 5 17 400 202 21795 Advanced 5 17 400 181 978483 Stratix V Standard 5 10 312 50 362 Arria V GZ Advanced 5 10 312 50 281 Note To calculate the latency for 17 400 Mbps per lane data rate an average value was taken from a set of samples For duplex advanced clocking mode the latencies varied more in simulation Transmission Overheads and Lane Rate Calculations SerialLite Ill Streaming IP Core Functional Description The SerialLite III Streaming IP core lane data rate transceiver data rate is composed of the input data rate and
85. tor in the Quartus II software for IP design instantiation and compilation TimeQuest timing analyzer in the Quartus II software for timing analysis ModelSim Altera software MATLAB or third party tool using NativeLink for design simulation or synthesis Related Information e Altera Software Installation and Licensing e What s New in Altera IP Altera Corporation SerialLite Ill Streaming MegaCore Function Quick Reference G Send Feedback About the SerialLite III Streaming IP Core 2015 05 04 UG 01126 amp Subscribe LJ Send Feedback The SerialLite III Streaming IP core is a high speed serial communication protocol for chip to chip board to board and backplane application data transfers This protocol offers high bandwidth low overhead frames low I O count and supports scalability in both number of lanes and lane speed The SerialLite III Streaming IP core incorporates a physical coding sublayer PCS a physical media attachment PMA and a media access control MAC block The IP core transmits and receives streaming data through the Avalon ST interface on its FPGA fabric interface Figure 2 1 Typical System Application FPGA Serial Data FPGA Up to Interface Board 24 Channels Control Board ialLi SerialLite Ill AK User uL il F User Data Processing or Logic Streaming e Sion Logic or System Board MegaCore MegaCore n Management Board Funct
86. tputs the user_clock user_clock_rx based on a fixed ratio however the xx coreclkin operates at the same frequency as rx_clkout Related Information Source Clock Generator on page 4 4 Sink Application Module The sink application module performs the following functions Strips the Interlaken protocol bursts encapsulation from the received serial data stream and presents the data to the user interface e Decodes idle control words inserted by the source application module when the data stream is not available and mirrors the data unavailability at the source by deasserting the output valid signal at the user interface The encapsulation stripping process removes burst control words that define the beginning and the end of streaming data bursts from the data stream This process adjusts the received data stream to repack the data words into a contiguous sequence SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback UG 01126 4 8 Sink Adaptation Module 2015 05 04 e Inthe standard clocking mode pure streaming the decoding process checks the received data stream to detect idle control words that the source application module inserts When the sink application module detects the idle control words it deasserts the valid signal on the user interface until it receives valid user streaming data e In the advanced clocking mode the sink application module does not insert or delete any idle words
87. transmission overheads Lane Rate Input Data Rate x Transmission Overheads The parameter editor uses the above equation to ensure that the lane rate is within the maximum supported transceiver lane rates This puts an upper limit on the input data rate or the user clock frequency where the user clock frequency equates to User Clock Frequency Input Data Rate 64 The SerialLite III Streaming IP core uses the Interlaken protocol for transferring data and therefore incurs encoding and metaframe overheads In the standard clocking mode the IP core employs an fPLL for clock generation To ensure that the fPLL generates the clock as close as possible to the user clock specified by you the fPLL incurs additional overheads The transmission overheads can thus be derived in the following functions Transmission Overheads Maximum Interlaken Overheads fPLL Overheads where Interlaken Overheads 67 64 x MetaFrame Length MetaFrame length 4 To ensure the Interlaken interoperability as well as user clocking requirements the PLL overheads in the standard clocking mode are chosen to be slightly higher than the Interlaken overheads The 40 bit PMA interface supports the lower range data rates up to 15 625 Gbps Lane Data Rate in Standard Clocking Mode User Clock Frequency x 1 76 x 40 gt Input Data Rate Interlaken Overheads Altera Corporation C Send Feedback UG 01126 4 16 Reset 2015 05 04 The 64 bit PMA interface suppor
88. troller Interface 1 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices Interface Figure 4 2 SerialLite Ill Streaming Duplex Core Standard Clocking SerialLite Ill Streaming Source SerialLite Ill Streaming Sink N Application Adaptation tanes Adaptation Application Source User Module gt Module gt Alignment Module gt Module P Sink User Interface Interface Module PHY IP PHY IP Duplex N Duplex Core 1 lanes Core 1 Sink User lt 4 Application PE Adaptation ii Adaptation PE Application Lei User Module Module Alignment Module Module Interface gt Interface Module Source amp i t gt Sink Reconfiguration Reconfiguration Controller Note Controller Interface 1 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices Interface The block diagram for advanced clocking is similar to standard clocking however it also includes a PPM absorption FIFO at the source user interface Related Information Altera Transceiver PHY IP Core User Guide SerialLite Ill Streaming IP Core Functional Description C Send Feedback Altera Corporation UG 01126 E m 2015 05 04 SerialLite Ill Streaming Source Core SerialLite Ill Streaming Source Core The source core consists of five major functional blocks the implementation varies depending on the clocking mode e Clock generator in the standard clocking mode e So
89. uction use without purchasing an additional license Some Altera MegaCore IP functions require that you purchase a separate license for production use However the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software After you are satisfied with functionality and perfformance visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 3 1 IP Core Installation Path C acds quartus Contains the Quartus II software a ip Contains the Altera IP Library and third party IP cores altera Contains the Altera IP Library source code 1 IP core name gt Contains the IP core source files Note The default IP installation directory on Windows is drive altera version number on Linux it is home directory altera version number Related Information e Altera Licensing Site e Altera Software Installation and Licensing Manual OpenCore Plus IP Evaluation Altera s free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase You need only purchase a license for MegaCore IP cores if you decide to take your design to production OpenCore Plus supports the following evaluations e Simulate the behavior of a licensed IP core in your system e Verify the functionality size and speed of the IP core quickly
90. urce application module e Source adaptation module e Native PHY IP TX core Interlaken mode Arria 10 devices e Interlaken PHY IP TX core Stratix V and Arria V GZ devices e PPM Absorption module in the advanced clocking mode only Figure 4 3 SerialLite Ill Streaming Source Core Standard Clocking Mode SerialLite Ill Streaming Source z ay Application Adaptation PHY IP SerialLite Ill SDUIESUSSHIRESHade gt Module Eg Module Core 2 u Streaming Link e Core Clock A Source User Clock lt C lock Generator Transceiver Reconfiguration Clock Transceiver Reference Clock or Transmit Serial Clock 1 Clock Domains Notes 1 Transceiver reference clock for Stratix V and Arria V GZ devices transmit serial clock for Arria 10 devices 2 Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices SerialLite Ill Streaming IP Core Functional Description Altera Corporation C Send Feedback UG 01126 4 4 Source Clock Generator 2015 05 04 Figure 4 4 SerialLite Ill Streaming Source Core Advanced Clocking Mode SerialLite Ill Streaming Source gt PPH Application Adaptation PHY IP SerialLite Ill Source User Interface d Hd Module Module P Core n Streaming Link Module e User Interface Clock 1 i jm loc
91. ver PLLs should be ANDed together before being input to the IP core Arria 10 devices only core reset N A Input Asynchronous master reset for the core Assert this signal high to reset the MAC layer except for the fPLL that is available in standard clocking mode Xeve jell L eer cilik N A Input For Stratix V and Arria V GZ devices this signals is the reference clock for the transceivers For Arria 10 devices this signal is present but unused in source only variations tie this signal to 1 b0 user_clock N A Input Output Clock for data transfers across the source core interface e Input Using advanced clocking mode e Output Using standard clocking mode user_clock_ reset user clock Input Output In the standard clocking mode the core asserts this signal when the core reset signal is high and deasserts this signal when the reset sequence is complete In the advanced clocking mode the core asserts this signal to reset the adaptation module FIFO buffer e Input Using advanced clocking mode e Output Using standard clocking mode reconfig clk N A User application to IP core This clock is for the transceiver reconfiguration interface It also sequences the reset state machine in the clock generation logic link up user clock Output The core asserts this signal to indicate that the core initialization is complete and is r
92. vices at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of p AN 101 Innovation Drive San Jose CA 95134 UG 01126 1 2 SerialLite Ill Streaming MegaCore Function Quick Reference 2015 05 04 o em o Been O Core Features Up to 17 4 Gbps lane data rates for Arria 10 devices Supports 1 24 serial lanes in configurations that provide nominal bandwidths from 3 125 gigabits per second Gbps to over 300 Gbps Avalon Streaming Avalon ST user interfaces on the transmit and receive datapaths Simplex and duplex operations Support for single or multiple lanes 64B 67B physical layer encoding Payload and idle scrambling Error detection Low overhead framing Low point to point transfer latency Protocol Features IP Core Information Typical Application e High resolution video Radar processing Medical imaging Baseband processing in wireless infrastructure Device Family Arria 10 Arria V GZ and Stratix V FPGA devices Support Refer to the What s New in Altera IP page of the Altera website for detailed information Design Tools Parameter edi

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