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(CvP) Implementation in Altera FPGAs User Guide

1. CvP Pins 2 5 Connect the nPERSTLO nPERSTL1 to nPERSTI 1 the PERST pin of the PCIe slot This pin may be driven by 3 3V regardless of the VCCIO voltage level of the bank without a level translator as long as the input signal meets the LVTTL VIH VIL specifi cation and as long as it meets the NEN overshoot specifications for 100 This pin is connected i i operation as defined in Table 1 2 in to the Hard IP for PCI p odi E the DC and Switching Characteris xpress IP Coreasa M f tics for Stratix V Devices chapter of dedicated fundamental i f the Stratix V handbook reset pin for PCIe usage If the signalis Only one nPERST pin is used per low the transceivers PCIe HIP The Stratix V Input and dedicated PCle components always have all four hard IP block that you pins listed even when the specific use for CvP operation component might have 1 or 2 PCIe are in the reset mode Hard IPs Ifthe Hard IP for PCI nPERSTLO Bottom Left PCIe Express IP Core is not HIP amp CvP in use you can use this nPERSTLI Top Left PCIe Hard pin as a user I O pin IP when available e nPERSTRO Bottom Right PCIe Hard IP when available e nPERSTRI Top Right PCIe Hard IP When available For maximum compatibility we recommend to use the bottom left PCIe Hard IP first as this is the only location that supports CvP Related Information e Pin Connection Guidelines Provides more information a
2. Configuration data input to the slave FPGAs through PS or FPP configuration pins Set the MSEL 4 0 pins tothe PS or FPP configuration scheme Altera Corporation UG 01101 3 4 Configuring Slave FPGAs with a Single Configuration File 2015 01 12 Configuring Slave FPGAs with a Single Configuration File To configure slave FPGAs with the same configuration file connect the ncEo pin of the master FPGA to the nce pins of all slave FPGAs in the chain In this topology all the slave devices are configured at the same time You can leave the nceo pin of the slave FPGAs in the chain unconnected or use it as a GPIO pin Figure 3 4 Mixed Chain Topology with Single Configuration File The following figure shows the connections required to configure slave FPGAs with the same configuration file using the FPP scheme Veram Configuration Device Veeam v or Configuration Host 10kW CCPGM and Flash s wik Vecpam Configuration Veeam Veeam 4 Vecoam Interface T aw kw OW 10KW First FPGA Second FPGA nth FPGA Host nSTATUS CONFDONE nSTATUS CONFDONE nSTATUS CONFDONE nCONFIG CvP CONFDONE nCONFIG nCONFIG nCEO Root PCle Link End CE CEO p nCE Complex Point User IP CT d i 4 T DCLK_out gt DCLK gt gt DCK GPlOpinsusedtofetchthe ATA out n 0 n elc MSEL
3. v Mode aciveseraxa vj File name pcie quartus fiestop a cse Advanced Remote Local update difference file NONE Ed M Create Memory Map File Generate top map IV Create CvP files Generate top periph jic and top core rbf Create config data RPD Generate top auto rpd Input files to convert File Data area Properties Start Address Add Hex Data Flash Loader 5SGXEA7K2 AguSot page SOF Data Page_0 lt auto gt Add File top sof 5SGXEA7K2F40 Remove Up Down Properties daddi Generate Close Help 4 Now turn on the Create CvP files Generate top periph jic and top core rbf parameter in the Output Programming Files section Note If you do not check this box the Quartus II software does not create separate files for the periphery and core images 5 Click Save Conversion Setup to save these settings For this exercise call your settings cvp_base cof The Quartus II software does not automatically save your choices 6 Click Generate to create top periph jic and top core rbf Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Understanding the Design Steps for CvP Initialization Mode with the Revision Design 5 9 Flow Note The generated CvP peripheral file size matches the size of the configuration device chosen Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow The CvP initialization mode with the revision design flow allow
4. Copyright lt c gt 2889 Microsoft Corporation All rights reserved iC Nalteras12 1 quartusNbin64 5quartus cup vid 1172 did e881 C cup tests 121 icup exanple core rbf Info 9993939393990 Info Running Quartus II 64 Bit CuP Programmer Info Version 12 1 Build 177 11 67 2612 SJ Full Version Info Copyright lt C gt 1991 2612 Altera Corporation All rights reserved Info Your use of Altera Corporation s design tools logic functions Info and other software and tools and its AMPP partner logic Info functions and any output files from any of the foregoing Info Cincluding device programming or simulation files and any Info associated documentation or information are expressly subject Info to the terms and conditions of the Altera Program License Info Subscription Agreement Altera MegaCore Function License Info Agreement or other applicable license agreement including Info without limitation that your use is for the sole purpose of Info programming logic devices manufactured by Altera and sold by Info Altera or its authorized distributors Please refer to the Info applicable agreement for further details Info Processing started Fri Dec 21 16 65 19 2612 Info Command quartus_cup vid 1172 did e i C cup_tests_121 cup_example co ie bf Found 1 matching device Vendor ID x1172 Device ID xE 1 1 1 Vendor ID 8x1172 Device ID xE 1 INFO Now starting CuP INFO Reached t
5. pcie lib synthesis top v T7 Table of Contents n8 E Fiow Summary f Flow Settings amp S Flow Non Default Gic E5 Flow Elapsed Time ff Flow OS Summary Entity Stratix V SSGXEA7K2F40C2 Bid top hw Wd top top gt Flow Status Successful Tue Oct 29 17 59 58 201 Quartus Il 64 Bit Version 13 1 0 Build 162 10 23 2013 SJ Full Ver Revision Name top Top level Entity Name top_hw Family Stratix V amp Device 5SGXEA7K2F40C2 Jd Hierarchy Z Files Design Units X IP Components 8 Flow Log 4 _ nanna y Analysis amp Synthesis Timing Models Final Tasks EX EB summary Logic utilization in ALMs N A until Partition Merge Lj Settings Total registers N A until Partition Merge Flow Full Design vJ Customize Task E ul gt Compile Design v Analysis amp Synthesis 4 x Quartus II Tcl Console tcl Parallel Compilati Source Files Reac ff IP Cores Summar Lj Design Partition S 9 Parfitian fordan u Total pins N A until Partition Merge Total virtual pins N A until Partition Merge Total block memory bits N A until Partition Merge Total DSP Blocks N A until Partition Merge dete HSSI STD RX PCSs N A until Partition Merge E ESEREKE Compilation Hierarchy Path v Netlist Type Ignore Source File Changes Fitter Preservation Level x j 8 Partition Name Netlist Type Allow Multiple Personas Preserve High
6. Follow these to program and test the CvP functionality 1 Plug the Stratix V GX FPGA Development Kit into the PCI Express slot of the DUT PC and power it on Altera recommends that you use the external power supply that the development kit includes 2 On the host PC open the Quartus II Tools menu and select Programmer The Programmer appears CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 40 Programming CvP Images and Validating the Link 2015 01 12 Figure 5 23 Quartus II Programmer Settings p Programmer Chaini cdf File Edit View Processing Tools Window Help 5 earch altera con w Hardware Setup USB Blaster USB 0 Mode JTAG x Progress 100 Successful T N Enable real time ISP to allow background programming for MAX II and MAX V devices X File Device Checksum Usercode Program Verify Blank E wu Start Configure Check pem Factory default enhanced SFL image SSGXEA7K2 031E5C76 FFFFFFFF v sj swnas0 1b data lbland projects 13 0 cvp hip s5gx 92 x8 ast128 restored pcie quartus files cv EPCQ256 FD150AEB vi FE ja Gil Auto Detect none 5M22102 00000000 lt none gt r J amp Delete 3 Click Auto Detect to verify that the USB Blaster recognizes the Stratix V FPGA 4 Follow these steps to program the periphery image a Select Stratix V device then right click None under File column b Navigate to pcie_quartus_files top periph
7. AR ee 00 00 00 00 00 00 00 00 01 80 03 00 00 00 00 00 BARG 0x00000000 10 00 02 00 02 80 64 00 20 28 00 00 11 60 40 01 Fe estore as ae 090 40 00 11 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 1F 00 10 00 00 00 00 00 00 00 00 00 0B0 02 00 OO OO 00 00 O0 00 OO 00 OO 00 OO OO OO 00 0C0 oo 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 OE0 00 OO 00 00 00 00 00 00 OO 00 OO 00 OO 00 O00 O00 oFo oo 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Hardwar _ M 8 Follow these steps to program the core image top core rbf into FPGA a Open a DOS command window b Change to appropriate Quartus II bin install directory Both 64 bit and 32 bit bin directories are available This example uses C Valtera 13 0 quartus bin64 c Type the following command to program the core image The value of Vendor ID vid and Device ID vid are in hexadecimal and must match the values you specified on the Device Identification Registers tab of the Stratix V Hard IP for PCI Express IP Core GUI quartus cvp vid 1172 did e001 lt path gt top core rbf d The figure below shows the results of successful CvP programming Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 CvP Debugging Check List 5 43 Figure 5 26 Transcript from quartus_cvp Command El quartus cvp Shortcut lt Jm Microsoft Windows Version 6 1 7601
8. Configuration scheme Passive Serial Configuration mode Standard Configuration device Auto Configuration device I O voltage Auto Force VCCIO to be compatible with configura Leave this option off tion I O voltage Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Parameter Value Compiling the Design for the CvP Update Mode 5 33 Generate compressed bitstreams Leave this option on Active serial clock source 100 MHz Internal Oscillator Enable input tri state on active configuration pins Leave this option off in user mode Under Category select CvP Settings Specify the settings in the following table Table 5 18 CvP Update Category Settings Parameter Value CvP via Protocol Subsequent core configuration Enable CvP CONFDONE pin Turn this option on Enable open drain on CvP CONFDONE pin Turn this option on 4 Click OK to close the Device and Pin Options dialog box 5 Click OK to close the Device dialog box 6 Save your project Compiling the Design for the CvP Update Mode 1 To compile the design on the Processing menu select Start compilation Compilation creates a pof file in the pcie quartus files subdirectory You might need to go through a few iterations of compiling your designs to separate all of the periphery components from the core logic As a result the final design might not maintain the functional relationships between logic blocks that you or
9. 4 0 PS or FPP configuration data SETI DDATA En DAN R E89 en dtocmet ERR nCONFIG out pins used to connect T WM to the nCONFIGand nCE Lu i aya pins of the next slave FPGA 1 Set the MSEL 4 0 pins E Mem Ee DD e J NNN RANE to the PS or FPP o fetch data from the Root Port through Configuration data input to the slave configuration scheme the PCle link which is sent to the slave FPGAs through PS or FPP configuration pins PGAs in the chain through a PS or FPP configuration interface Daisy Chain Use the daisy chain topology to configure multiple FPGAs that are connected in a PCIe chain Each FPGA in the daisy chain has an Endpoint and a Root Port Connect the Root Port in the host to the Endpoint of the first FPGA in the chain the Root Port of the first FPGA to the Endpoint of the second FPGA and so forth Each FPGA in this chain is connected to a configuration device which you use to store the periphery image in the CvP initialization mode and the full configuration image in the CvP update mode In this topology the ncE nSTATUS nCONFIG CONF DONE and CvP CONFDONE pins are not tied together allowing each FPGA to receive the configuration data from their respective configuration devices You must design a user IP as part of the core image The user IP routes the configuration data from the host to the FPGA Root Port applications You initialize or update the core image of the first FPGA in th
10. Table 6 3 Altera defined Vendor Specific Header Register Byte Offset 0x204 15 0 VSEC ID 0x1172 RO A user configurable VSEC ID 19 16 VSEC Revision 0 RO A user configurable VSEC revision CvP Driver and Registers CJ Send Feedback Altera Corporation UG 01101 6 4 Altera Marker Register 2015 01 12 HEMEN REOR CNN 31 20 VSEC Length 0x044 RO Total length of this structure in bytes Altera Marker Register Table 6 4 Altera Marker Register Byte Offset 0x208 31 0 Altera Marker Device Value An additional marker If you use the standard Altera Programmer software to configure the device with CvP this marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC CvP Status Register Table 6 5 CvP Status Register Byte Offset Ox21C 31 26 0x00 Reserved 25 PLD CORE READY Variable RO From FPGA fabric This status bit is provided for debug 24 PLD CLK IN USE Variable RO From clock switch module to fabric This status bit is provided for debug 23 CVP CONFIG DONE Variable RO Indicates that the FPGA control block has completed the device configuration via CvP and there were no errors 22 Variable RO Reserved 21 USERMODE Variable RO Indicates if the configurable FPGA fabric is in user mode 20 CVP EN Variable RO Indicates if the FPGA control block has enabled CvP mode 19 CVP CONFIG ERROR
11. c 100 Minimum PERST signal active time from the host d 20 Minimum PERST signal inactive time from the host before the PCIe link enters training state e 120 Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode f 100 Maximum time PCIe device must enter L0 after PERST is deasserted PCle Wake Up Time Requirement for CvP Update Mode For CvP update mode you initialize the FPGA by configuring it using one of the conventional configura tion schemes upon device power up An open system requires that the FPGA initialization completes within 120 ms To ensure that this requirement is met choose the right conventional configuration scheme for your system To ensure successful configuration all POR monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp up time PERST is one of the auxiliary signals specified in the PCIe electromechanical specification The PERST signal is sent from the PCIe host to the FPGA The PERST signal indicates whether the power supplies of the FPGA are within their specified voltage tolerances and are stable The Pens signal also initializes the FPGA state machines and other logic after Altera Corporation Design Considerations C Send Feedback UG 01101 2015 01 12 Recommended Configuration Schemes 4 5 power supplies are stabilized The PCIe link supports PCIe applications in user mode for CvP updat
12. configur b make su d make install disable usb support 3 You can change the permissions for the device file For example chmod 666 dev windrvr6 4 For 64 bit Linux systems set the Quartus 64B1T environment variable before you run quartus cvp using the following command e export QUARTUS 64BIT 1 5 You can use the quartus cvp command to download core rbf files to your FPGA The following table lists the quartus cvp commands for all modes Table 5 23 Syntax for quartus cvp Commands Uncompressed quartus cvp vid Vendor ID did Device ID Core rbf file Unencrypted path gt Compressed quartus_cvp c vid Vendor ID did Device ID Core rbf file path Encrypted quartus cvp e vid Vendor ID did Device ID Core rbf file path Compressed and encrypted quartus cvp c vid lt Vendor ID did Device ID Core rbf file path Modifying MSEL for Active Serial x4 Flash on Stratix V Dev Kit The MSEL switch labeled SW4 on the back of the Stratix V GX FPGA Development Kit PCB specifies the flash type The correct setting for an active serial x4 flash is 5b10010 as shown in the following figure The factory default value is 5 b01000 Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Programming CvP Images and Validating the Link 5 39 Figure 5 22 Switch 4 SW4 Configuration for MSEL 4 0 5 b10010 on t
13. using Open Conversion Setup Data in the Convert Programming File window The following figure illustrates these options 5 Click Generate This conversion process creates the alternate core logic cvp app core rbf and the periphery logic cvp_app periph jic The periphery logic cvp app periph jic should be identical to the periphery logic created when splitting the base revision Note The generated CvP peripheral file size matches the size of the configuration device chosen Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Understanding the Design Steps for CvP Update Mode 5 23 Figure 5 13 CvP Revision Design Flow Convert Programming Files Convert Programming File data nikshah CvP hip_s5gx_x1_g1_ast64_5SGXEA K2F40 restored CvP GIxIl restored top top File Tools Window Search altera com eg Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type JTAG Indirect Configuration File jic z Options Configuration device EPCQ256 TT TT v Mode Active Serial xa r File name pcie_quartus_files evp app jic TL Oo ome Advanced Remote Local update difference file NONE x Iv Create Memory M
14. 10kW Veram 10kW nSTATUS nCONFIG CvP CONFDONE End Point nCE MSEL 4 0 Altera Corporation Design Considerations 2015 01 12 UG 01101 X subscribe Send Feedback Data Compression You can choose to compress the core image by turning on the Generate compressed bitstream option in the Configuration page of the Device and Pin Options dialog box in the Quartus II software The periphery image cannot be compressed Compressing the core image reduces the storage requirement If you configure the FPGA using a compressed core image you must use a compressed image when updating the core image of the FPGA Data Encryption You can choose to encrypt the core image The periphery image cannot be encrypted To configure the FPGA with an encrypted core image you must pre program the FPGA with a security key This key is then used to decrypt the incoming configuration bitstream A key programmed FPGA can accept both encrypted and unencrypted bitstreams if you configure the FPGA using the AS PS or FPP scheme However if you use CvP a key programmed FPGA can only accept encrypted bitstreams Use the same key to encrypt all revisions of the core image Table 4 1 Supported Clock Source for Encrypted Configuration Data The following table lists the supported clock source for each conventional scheme used in a CvP system Key Types External Clock Internal Clock External Clock External Clock Yes Yes Ye
15. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 UG 01101 1 2 Autonomous Mode 2015 01 12 Figure 1 1 CvP Block Diagram Configuration device or configuration host and flash 1 Configuration interface 1 Host Configuration control block internal PCle link Root Complex A CvP system typically consists of an FPGA a PCIe host and a configuration device Most Arria V Cyclone V and Stratix V FPGAs include more than one Hard IP for PCI Express IP Cores Only the bottom left PCIe Hard IP block can be used for the CvP configuration scheme It must be configured as an Endpoint The configuration device is connected to the FPGA using the conventional configuration interface The configuration interface can be any of the supported schemes such as active serial AS passive serial PS or fast passive parallel FPP The choice of the configuration device depends on your chosen configura tion scheme Autonomous Mode In autonomous mode the Hard IP for PCI Express sends configuration retry status CRS messages to the Root Port indicating that the device is not ready for configuration access Because the Hard IP for PCI Express is part of the periphery image it can respond to configuration requests fr
16. Auto restart configuration after error If this option is enabled CvP restarts after an error is detected b Enable autonomous PCIe HIP mode Checking this box has no affect if you have enabled CvP by turning on Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI The Quartus II software automatically enables autonomous mode by default In autonomous mode the control block takes the Hard IP for PCI Express out of reset after periphery image is loaded The Hard IP for PCI Express responds to configuration requests and memory requests with the normal successful status The core image is loaded using PCIe link in both CvP initialization and CvP update mode The Enable autonomous PCIe HIP mode option only has effect if your design has the following two characteristics e You are using something other than the PCIe link to load the core image for example a flash device or Ethernet controller e You have not checked Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI CvP Example Designs Altera Corporation LJ Send Feedback i UG 01101 5 28 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for 2015 01 12 CvP Revision If both of these conditions are true the following two options are available Ifyou checked Enable autonomous PCIe HIP mode the control block takes the Hard IP for PCI Express out of reset after the periphery image is loaded The Hard IP responds
17. Create Memory Map File Turn this option on Create CvP files Turn this option on This box is greyed out until you specify the SOF Data file under Input files to convert 2 Under Input files to convert specify the options in the following table Table 5 22 CvP Revision Design Flow Input Files to Convert Parameter Value Click SOF Data Click Add Fileand navigate to pcie_quartus_files cvp_app sof If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box you must specify the same options in the Conversion Programming File window To enable these settings click cvp_app sof then click Properties and check the appropriate boxes 3 Now turn on the Create CvP files Generate cvp_app periph jic and cvp_app core rbf parameter in the Output Programming Files section 4 To save the Conversion Programming File parameters click Save Conversion Setup and type an output file name Saving your conversion setup saves time on subsequent conversions For this exercise call your settings cvp_update_revision_setup cof You can reload the conversion parameters by opening the Conversion Setup File cof using Open Conversion Setup Data in the Convert Programming File window The following figure illustrates these options 5 Click Generate This conversion process creates the alternate core logic cvp app core rbf and the periphery logic cvp app periph pof Note The generated CvP peripheral file size
18. Design Considerations CJ Send Feedback Altera Corporation UG 01101 4 8 Estimating PCle Wake Up Time Requirement 2015 01 12 D3 FPP x8 FPP x16 FPP x32 Stratix V GS D4 FPP x16 D5 FPP x32 D6 FPP x32 Estimating PCle Wake Up Time Requirement Figure 4 4 Estimating PCle Wake Up Time Requirement Equation configuration file size 1 x P POR delay ti Number of data line DCLK GS Lad dd Biu EN Conventions used for the equation Full configuration file size refer to uncompressed rbf sizes e Number of data line refer to the width of data bus For example the width of data bus for FPP x16 is 16 e DCLK frequency refer to fmax for the DcLK frequency e Power ramp up must be within 10 ms PORdelay use fast POR maximum time is 12 ms You can use the equation above to make estimation if your device could meet the PCIe wake up time requirement The following figure shows the example of calculating the PCIe wake up time requirement for Arria V GX A5 device Figure 4 5 Example of Calculating PCle Wake Up Time Requirement 101 740 640 1 10 12 T 125 000 000 50 ms 22 ms 72 ms The estimation for Arria V GX A5 device is 72 ms which is able to meet the PCIe wake up time require ment of 120 ms Altera Corporation Design Considerations C Send Feedback UG 01101 2015 01 12 Design CvP for a Closed System 4 9 Related Information Arria V Device Datasheet Provides
19. FPGA fabric is reinitialized and reconfigured with the new core image During the core image update through a PCIe link the nconric and nstatus pins of the FPGA remain at logic high When the core image update completes the cvP_CONFDONE pin is released high indicating the FPGA has entered user mode CvP Pins The following table lists the CvP pin descriptions and connection guidelines FPGA Configuration using CvP Altera Corporation CJ Send Feedback 2 4 CvP Pins UG 01101 2015 01 12 CvP_CONFDONE Output Driven low during core image configuration and released or driven high after the completion of the core image configuration During FPGA configu ration in CvP initializa tion mode you must observe this pin after the CoNF_DONE pin goes high to determine if the FPGA is successfully configured If you are not using the CvP modes you can use this pin as a user I O pin If this pin is set as dedicated output the VccpaM power supply must meet the input voltage specification of the receiving side If this pin is set as an open drain output connect the pin to an external 10 kO pull up resistor to the Vccpcm power supply or a different pull up voltage that meets the input voltage specification of the receiving side This gives an advantage on the voltage leveling Altera Corporation FPGA Configuration using CvP C Send Feedback UG 01101 2015 01 12 10 3
20. Flow To compile your project click Compile All Using Compile All guarantees that the Quartus II software compiles the top revision and cvp app revision in the correct order Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Splitting the SOF File for the CvP Initialization Design Mode 5 19 Figure 5 11 Compile Both Base and cvp_app Revisions Using the Compile All Option in Quartus 13 0 Project Navigator gt Compile All dil top Base f Done Sj cvp app CVP s Done You might need to go through a few iterations of compiling your designs to separate all of the periphery components from the core logic As a result the final design might not maintain the functional relation ships between logic blocks that you originally planned Adding extra comments in your design will help you to trace the HDL You must compile your project to update the reconfigured core image if any of the following conditions are true e The CvP revision has never been compiled e You have changed the periphery logic e You have changed the wrapper file for any of the core revisions e You have migrated to a new version of the Quartus II software You have changed any project settings in the Quartus II Settings File qsf Splitting the SOF File for the CvP Initialization Design Mode Follow these steps to split your sof file into separate images for the periphery and core logic 1 On the File menu select Co
21. Speed Tiles 4 3s Design Partitions v Color lt lt new gt gt Source File Status 4j Top Source File A 3 user lod user led Soe Post Fit Netlist Status Imported Last Imported From 8 v Allow Multiple Personas Input Persona 2 ASD Region 2 Boundary Optimizations amp Strict Preservation 8 Click the core instance user led user led and set Allow Multiple Personas to On 9 Click in the Netlist Type column and set the user led user led Netlist Type to Source File 10 Follow these steps to create a CvP revision for the modified project a Under the Revisions tab right click on the Revision top and select Create CvP Revision The Create CvP Revision dialog box appears b For the Revision name type cvp_app and click OK to create a CvP revision as illustrated in the following figure CvP Example Designs LJ Send Feedback Altera Corporation m n ev z UG 01101 5 18 Compiling Both the Base and cvp_app Revisions in the CvP Revision Design Flow 2015 01 12 Figure 5 9 Specifying Revision Name Project Navigator fax Compilation Report top EZ Flow Summary Flow Settings Flow Non Default Global Sett f Flow Elapsed Time 8 Flow OS Summary 2 Flow Log LJ Restore Archived Project L3 Analysis amp Synthesis i Flow Messages Compile All dill top Base 5 Partition Merge SH cvp app CVP amp Analysis amp Synthesis Hierarchy amp Files a Design Units IP Components
22. The Enable autonomous PCIe HIP mode option only has effect if your design has the following two characteristics e You are using something other than the PCIe link to load the core image for example a flash device or Ethernet controller e You have not checked Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI If both of these conditions are true the following two options are available Ifyou checked Enable autonomous PCIe HIP mode the control block takes the Hard IP for PCI Express out of reset after the periphery image is loaded The Hard IP responds to configura tion requests with Configuration Retry Status CRS and memory requests with UR status until the FPGA enters user mode Ifyou did not check Enable autonomous PCIe HIP mode the Hard IP remains in reset until FPGA enters user mode Link training only occurs after the FPGA enters user mode Note This parameter only controls functionality for the initial configuration It allows open PCI Express systems to meet the configuration time requirement defined in the PCI Express Base Specification After the initial configuration it has no significance because the core image has already been configured Leave all other options disabled 3 Under Category select Configuration to specify the configuration scheme and device Specify the settings in the following table Table 5 17 CvP Update Mode Configuration Settings Parameter Value
23. Variable RO Reflects the value of this signal from the FPGA control block checked by software to determine if there was an error during configu ration Altera Corporation CvP Driver and Registers C Send Feedback UG 01101 2015 01 12 CvP Mode Control Register 6 5 HEME EKE KAZA KA HEKAXEEE 18 CVP_CONFIG_READY Variable Reflects the value of this signal from the FPGA control block checked by software during programming algorithm 17 0 Variable RO Reserved CvP Mode Control Register Table 6 6 CvP Mode Control Register Byte Offset 0x220 31 16 0x0000 RO Reserved 15 14 0x0 RO Reserved 13 8 CVP_NUMCLKS 0x00 RW This is the number of clocks to send for every CvP data write Set this field to one of the values below depending on your configu ration image e 0x01 for uncompressed and unencrypted images e 0x04 for uncompressed and encrypted images e 0x08 for all compressed images 7 3 0x0 RO Reserved 2 CVP_FULLCONFIG 1 b0 RO A value of 1 indicates a request to the control block to reconfigure the entire FPGA including the Hard IP for PCI Express and bring the PCIe link down CvP Driver and Registers Altera Corporation LJ Send Feedback UG 01101 6 6 CvP Data Registers 2015 01 12 et oe ene ee TET HIP_CLK_SEL 1 b0 Selects between PMA and fabric clock when USER_MODE 1 and PLD_CORE_READY 1 The following encodings are defi
24. Vechi wow ow FPGA Host nSTATUS CONFDONE nCONFIG CvP CONFDONE Root PCle Link Complex MSEL 4 0 nCE Multiple Endpoints O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 3 2 Multiple Endpoints UG 01101 2015 01 12 Use the multiple Endpoints topology to configure multiple FPGAs through a PCIe switch This topology provides you with the flexibility to select th
25. Wake Up Time Requirement 4 3 Figure 4 1 Power Supplies Ramp Up Time and POR Volts A First Power Supply r ere tte Last Power l Supply gt Time i 10 ms PORDelay Related Information Power Management in Arria V Devices Power Management in Cyclone V Devices Power Management in Stratix V Devices PCle Wake Up Time Requirement For an open system you must ensure that the PCIe link meets the PCIe wake up time requirement as defined in the PCI Express CARD Electromechanical Specification The transition from power on to the link active 10 state for the PCIe wake up timing specification must be within 200 ms The timing from FPGA power up until the Hard IP for PCI Express IP Core in the FPGA is ready for link training must be within 120 ms Related Information PCI Express Card Electomechanical 3 0 Specification PCle Wake Up Time Requirement for CvP Initialization Mode For CvP initialization mode the Hard IP for PCI Express IP Core is guaranteed to meet the 120 ms requirement because the periphery image configuration time is significantly less than the full FPGA configuration time Therefore you can choose any of the conventional configuration schemes for the periphery image configuration To ensure successful configuration all POR monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp up time PERST reset input signal indicates whether the FPGA power sup
26. a user I O pin Figure 3 3 Mixed Chain Topology with Different Configuration Files EO pin low to enable configuration for the next slave FPGA This process continues until the last slave FPGA in the chain is configured You can leave the nceo pin of the last The following figure shows the connections required to configure slave FPGAs with different configuration files using the FPP scheme Vom Veeam 10kW 10kW Host or Configuration Host Configuration Device and Flash Configuration Interface PCle Link Root Complex GPIO pins used to fetch the PS or FPP configuration data GPIO pins used to connect to the nCONFIG and nCE pins of the next slave FPGA CvP Topologies C Send Feedback End Point First FPGA nSTATUS nCONFIG User IP nCE CONFDONE CvP_CONFDONE nCEO out DCLK out DATA out n 0 nCONFIG out MSEL 4 0 Vecpem 10kW Veeam 10kW Veem 10kW Varam 10kW Varam 10kW To fetch data from the Root Port through the PCle link which is sent to the slave FPGAs in the chain through a PS or FPP configuration interface Second FPGA nSTATUS nCONFIG nCE DCLK DATA n 0 CONFDONE ME MSEL 4 0 nth FPGA nSTATUS nCONFIG nCE DCLK DATA n 0 CONFDONE nCE0 MSEL 4 0
27. box Click OK to close the Device dialog box Save your project Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow This section provides the instructions to create CvP revisions for the reconfigured core logic region that can be updated The remainder of the design is treated as a static core region Follow these steps to create the base version of the core logic 1 On the Assignments menu select Settings and then select Files 2 In the File name box Browse and select user_led v then click Add 3 4 Run Analysis amp Synthesis so that the Quartus II software parses the design to create a design hierarchy Click OK that includes the user_led instance To set user_led as a design partition right click user_led user_led in the design hierarchy and select Design Partition A small red box appears next to user_led user led indicating that it is a separate partition If you perform the same steps again you remove the separate design partition from user_led user_led The following image illustrates this step Figure 5 7 Setting a Design Partition Entity Table of Contents s EE ly Stratix V SSGXEA7K2F40C2 Ez Flow Summary aj Flow Status Successful Tue Oct 29 17 59 58 2013 5 Bd top hw 4 8 Flow Settings Quartus II 64 Bit Version 13 1 0 Build 162 10 23 2013 SJ Full Version Bhd top top Flow Non Default GIc Revision Name top How
28. matches the size of the configuration device chosen Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Bringing Up the Hardware 5 37 Figure 5 21 CvP Revision Design Flow Convert Programming Files Ly Convert Programming File data nikshah CvP hip s5gx x1 gl asto4 5SGXEAZ7K2F40 restored CvP_Gixl restored top B X File Tools Window Search alteracon Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Programmer Object File pof kuz Qptions Configuration device CFI_128Mb Mode 1 bit Passive Serial bA File name pcie_quartus_files cvp_app pof n Advanced Remote Local update difference file NONE Iv Create Memory Map File Generate cvp app map Iv Create CvP files Generate cvp app periph pof and cvp app core rbf Create config data RPD Generate cvp app auto rpd Input files to convert File Data area Start Address Add Hex Data Options 0x00000000 Add Sof Page SOF Data Page O0 lt auto gt cvp app sof 5SGXEA7K2F40 Add File Remove Up Down VERI Properties Generate Close Help E J 6 Now proceed to Bringing Up the Hardware on page 5 37 The file top cof provided in cvp designs is a template for CvP initialization mode You can open this file in the Open Conversion Setup Data of Convert Programming File window to retrieve the parameters shown in figure above Bringing Up th
29. power down CvP allows the FPGA fabric to be updated through the PCIe link without a host reboot or FPGA full chip reinitialization e Provides a simpler software model for configuration A smart host can use the PCIe protocol and the application topology to initialize and update the FPGA fabric e Facilitates hardware acceleration e Reduces system size You can use a single PCIe link to configure multiple FPGAs CvP System The following figure shows the setup for the CvP system 0 CvP is an advanced feature for the Arria V and Cyclone V device families For details contact Altera support O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera
30. scheme Active Serial x4 Configuration mode Standard Configuration device EPCQ256 Configuration device I O voltage Auto Force VCCIO to be compatible with configura Leave this option off tion I O voltage Generate compressed bitstreams Turn this option off Because this is a small example design it does not use a compressed bitstream For larger designs using a compressed bitstream signifi cantly reduces configuration time In addition a compressed bitstream requires a smaller flash device Active serial clock source 100 MHz Internal Oscillator Enable input tri state on active configuration pins Leave this option off in user mode Under Category select CvP Settings For CvP Initialization mode specify the following settings in the following table Table 5 9 CvP Initialization Category Settings Parameter Value CvP Initialization Power up and subsequent core configuration Enable CvP CONFDONE pin Turn this option on Enable open drain on CvP CONFDONE pin Turn this option on CvP Example Designs Altera Corporation LJ Send Feedback 5 16 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 4 5 6 UG 01101 2015 01 12 These Configuration settings use the configuration devices available on the Stratix V GX FPGA Development Board The EPCQ256 flash device is far larger than required to load a periphery image Click OK to close the Device and Pin Options dialog
31. v The Transceiver Reconfiguration Controller instance includes 32 lines of Verilog HDL code 3 Add the 5 lines of Verilog HDL shown in below after the commented out instance alt_xcvr_reconfig wire 69 0 reconfig_to_xcvr_bus 24 h0 2 b11 44 h0 assign pcie reconfig driver 0 reconfig mgmt waitrequest 1 b0 gn p g q assign pcie_reconfig_driver_0_reconfig_mgmt_readdata 32 h0 gn p g assign alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy 1 b0 assign alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcv r 2 reconfig_to_xcvr_bus Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Creating An Alternate user_led v File for the Reconfigurable Core Region 5 27 In this example the first statement hardwires the reconfig_to_xcvr_bus to the correct values per channel The first three assignment statements specify the correct values for the wait request readdata reconfig_busy signals The final assignment statement for alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcvr represents the full reconfiguration bus for all active transceiver channels This bus is replicated 2 times because 2 channels are active in the Genl x1 instance Creating An Alternate user led v File for the Reconfigurable Core Region This example design creates a new version of the PCI Express High Performance Reference Design The original version of this reference design includes an LED which turns on wheneve
32. Add Hex Data Options 0x00000000 Add Sof P SOF Data Page 0 auto LESE top sof 5SGXEA7K2F40 Add File Remove U Down didis Note The Configuration scheme and Configuration device in Device and Pin Options must match with Configuration Device and Mode in Convert Programming File respectively Splitting the SOF File for CvP Update Mode with the CvP Revision Design Flow To implement the CvP Revision Design Flow with CvP update mode you must replace the base sof top sof with the revision sof cvp app sof You must also specify a different file name for the CvP revision This example uses cvp app The periphery and the core images created for the CvP revision are cvp app periph pof and cvp_app core rbf respectively Follow these steps to create the periphery and core images for the CvP revision 1 On the File menu select Convert Programming File Under Output programming file specify the options in the following table These settings are illustrated in the figure below Table 5 21 CvP Revision Design Flow Output Programming File Options Parameter Value Programming file type Programmer Object File pof CvP Example Designs Altera Corporation send Feedback UG 01101 5 36 Splitting the SOF File for CvP Update Mode with the CvP Revision Design Flow 2015 01 12 Configuration device CH 128Mb Mode 1 bit Passive Serial File name Click browse and specify pcie quartus files cvp app pof
33. CIe hiperf s5gx zip file from the PCI Express Avalon ST High Performance Reference Design web page This design includes the correct pin assignments and project settings to target the Stratix V GX FPGA Development Kit Unzip PCIe hiperf s5gx zip Copy hip s5gx x1 gl ast64 5SGXEAZ7K2FAO qar to your working directory Start the Quartus II software and restore hip s5gx x1 gl ast 4 5SGXEA7KOFAO qar Onthe Tools menu select Qsys Open top qsys On the System Contents tab right click DUT and select Edit CNA QI d WN figure Figure 5 15 Hard IP for PCI Express GUI r System Settings Number of lanes x E Lane rate Gent 2 5 Gbps Port type Native endpoint PCI Express Base Specification version 24 j A Application interface Avalon ST 64 bit v RX buffer credit allocation performance for received requests Low vw Reference clock frequency 100 MHz E Use 62 5 MHz application clock Wi Use deprecated RX Avalon ST data byte enable port rx st be Enable byte parity ports on Avalon ST interface Enable multiple packets per cycle M Enable configuration via the PCle link _ Use credit consumed selection port tx cons cred sel Enable Configuration Bypass Enable Hard IP reconfiguration LJ Send Feedback Under System Settings turn on Enable configuration via the PCIe link as shown in the following Altera Corporation UG 01101 5 26 Workaround for a Known Issue with
34. Configuration via Protocol CvP Implementation in Altera FPGAs User Guide GX subscribe UG 01101 2014 12 29 LJ Send Feedback 101 Innovation Drive San Jose CA 95134 N OPS BJAN www altera com TOC 2 Configuration via Protocol CvP Implementation in Altera FPGAs User Guide Contents OVER VIGW oi sccssoicacssidins vac scasvoadennetensicsransiaccentisedi HERE HERS EW KH SER k UW AR O DA EK HW HVH N GO SU G W RA G 1 1 Benefits Of Using d a a E NE a ar Waa Erk MN A 1 1 judo 1 1 Autonomos M DH 1 2 CV D LL excuses EE 1 rend KRA K Heel E e cogs e H d k 1 3 Prepare the Design for CvP Revision Design FlOW E eee reee erer rexek keen hie id et perta AK 1 4 CVT SUL M 1 5 Additional Information about PCI Express seras bii peivupt t rae o Oasis QS NRI S trs INNER Ret DEED qvx HAK TA 1 5 FPGA Configuration using CyD rne ono ee Reo eobu ur EERE PEN RR APR TUE 2 1 CVP Configuration Ta SS u 401544 40 e n tei Quae an m EU ac r ein di wanre r n Ne NA ed 2 1 rg i m 2 1 CyP Initialization Mode rin pret td EV NEU EROR EU ERI QUT RES dba DES 2 1 EVP Update MG de DD 2 2 CV PAPI e M M osteitis 2 3 eadinnhhum c n 3 1 PEA FETC OGU
35. Fiansea Time Topevel Ertty Name tp _ Settings Ctri Shift E Family Stratix V Device 5SGXEA7K2F40C2 d Hierarchy J Design Units 4 IP S Set as Top Level Entity Ctrl Shift lis Timing Models Final Logic utilization in ALMs N A until Partition Merge Tasks irum Total registers N A until Partition Merge Bas Far Design LogicLock Region hti Total pins N A ze iod nee EL eum mis until Partition Merge gt Compile Design Za Copy Ctrl C Design Partition Properties pim lal PAE Analysis amp Synthesis ND i Y E Expand All Import Design Partition until Partition Merge J Collapse All Export Design Partition until Partition Merge x Quartus II Tcl Console a hta Print Hierarchy Incremental Compilation Tools 2 Print All Design Files amp Design Partitions Window Alt D E T Properties 6 Click the Design Partitions Window at the bottom of the menu cascade shown in the figure above The Design Partitions Window appears 7 To add the Allow Multiple Personas column to the Design Partitions Window right click on the top Altera Corporation bar of Design Partition Window next to the Color heading and select Allow Multiple Personas from the list as shown in the following figure CvP Example Designs C Send Feedback UG 01101 2015 01 12 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5 17 Figure 5 8 Allowing Multiple Personas Home 4 Compilation Report top K
36. Protocol Subsequent core configuration Enable CvP CONFDONE pin Turn this option on Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5 29 Enable open drain on CvP CONFDONE pin Turn this option on 4 Click OK to close the Device and Pin Options dialog box 5 Click OK to close the Device dialog box 6 Save your project Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow This section provides the instructions to create CvP revisions for the reconfigured core logic region that can be updated The remainder of the design is treated as a static core region Follow these steps to create the base version of the core logic 1 On the Assignments menu select Settings and then select Files 2 In the File name box Browse and select user led v then click Add 3 Click OK 4 Run Analysis amp Synthesis so that the Quartus II software parses the design to create a design hierarchy that includes the user led instance 5 To set user led as a design partition right click user led user led in the design hierarchy and select Design Partition A small red box appears next to user led user led indicating that it is a separate partition If you perform the same steps again you remove the separate design partition from user led user led The following image illustrates this step Figure 5 16 Setting
37. RA UMEN D X 3 1 Multiple Endpoints ea t ERI GERE ENORMI E rue ect a Ka ekle lsa ae dts 3 1 Mixed CHAIN P 3 3 Configuring Slave FPGAs with Different Configuration Files see 3 3 Configuring Slave FPGAs with a Single Configuration File sss 3 4 par duri M 3 4 Design Consid rattolls cene reves etra RE bx DES LUPIS UP APRES ce nme KHK KA HERK HHR He 4 1 Data Compres E 4 1 Datta Encryption 4 1 2512101111 20222 4 1 Core Image pd al 4 2 Partial Recon s EXER otc slnd linin dinay pud prar pretende du EEA ESE uidi e brique d kek r ne 4 2 Designing CvP for an Open SYSt Is a si454 epp om testet base edat Regie n puel Reda RA 4 2 FPGA Power Supplies Ramp Time Requirement eese ettet 4 2 PCIe Wake Up Time Requirement ane hdan eo ER N Hal sh nb bna cin eek ds 4 3 Disp CvP fora Closed Syste engine irpo Ub nest lel i yela DH P IN Horton CUR RR anii 4 9 Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller 4 9 CvP Exampl DeSl9tis oieeveeise pes denke kak Kake ke C VR SRWA U asesi issus SN ERE KURKE URL H E S RE HERS EKR kO 5 1 Understanding the Design Steps
38. SEC registers occupy byte offset 0x200 to 0x240 in the PCIe Configuration Space The PCIe host uses these registers to communicate with the FPGA control block The following table shows the VSEC register map Subsequent tables provide the fields and descriptions of each register Altera Corporation CvP Driver and Registers C Send Feedback UG 01101 2015 01 12 Table 6 1 VSEC Registers for CvP Altera defined Vendor Specific Capability Header Register 6 3 0x200 Altera defined Vendor Specific Capability Header 0x204 Altera defined Vendor Specific Header 0x208 Altera Marker 0x20C 0x218 Reserved 0x21C CvP Status 0x220 CvP Mode Control 0x224 CvP Data 2 0x228 CvP Data 0x22C CvP Programming Control 0x230 Reserved 0x234 Uncorrectable Internal Error Status Register 0x238 Uncorrectable Internal Error Mask Register 0x23C Correctable Error Status Register 0x240 Correctable Error Mask Register Altera defined Vendor Specific Capability Header Register Table 6 2 Altera defined Vendor Specific Capability Header Register Byte Offset 0x200 15 0 PCI Express Extended 0x000B PCIe specification defined value for Capability ID VSEC Capability ID 19 16 Version 0x1 RO PCle specification defined value for VSEC version 31 20 Next Capability Offset Variable RO Starting address of the next Capability Structure implemented if any Altera defined Vendor Specific Header Register
39. TART_XFER bit in the CvP programming control register v Write 0tothe CVP_CONFIG bit in the CvP programming control register v Set the CVP_NUMCLKS byte to 0x01 in the CvP mode control register and issue 244 dum my memo ry writes to the hard IP for the control block sense if system is reset Dummy memory writes can be config writes to CVP_DATA reg or memory writes to any address defined by a BAR for this device v Poll the CVP_CONFIG_REA DY bit from the CvP status register CVP_CONFIG_READY 0 yes v Read the CVP CONFIG ER ROR L ATCHED bit in the uncorrectable internal error status register Set the CVP_NUMCLKS byte to 0x01 in the CvP mode control register and issue 244 dum my memo ry writes to the hard IP causing the control block to switch from the inte rnal clo ck to the CP clo ck Dummy memory writes can be config writes to the CVP_DATA register of memory writes to any addr defined by a BAR for this device Y Write I to the S TART_XFER bit in the VP pro gramming control register VSEC Registers for CvP CVP CONFIG ERROR L ATCHED yes v Write 0 to CVP MODE and HIP CLK SEL v Poll the PLD_CLK_IN_USE and USER_MODE from the CvP status register PLD_CLK_IN_USE 1 and USER_MODE 1 yes UG 01101 2015 01 12 The Vendor Specific Extended Capability V
40. Transceiver Reconfiguration Controller IP Core 2015 01 12 9 Click Finish 10 On the Generation tab specify the settings in the following table Then click Generate at the bottom of the window Table 5 14 Qsys Generation Tab Settings Parameter Value Create simulation model None Create testbench Qsys system None Create testbench simulation model None Create HDL design files for synthesis Verilog Create block symbol file bsf Leave this entry off Path lt working_dir gt top Simulation Leave this entry blank Testbench lt working_dir gt top synthesis 11 After successful compilation close Qsys Related Information PCI Express Avalon ST High Performance Reference Design Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core If you plan to perform almost continuous updates of the reconfigurable core logic in stress tests or in your actual system you may encounter an issue with the Transceiver Reconfiguration Controller This issue might cause the PCIe link to downtrain in Quartus II 13 0 release and earlier versions of the Quartus II software If you are using Quartus II 13 0 SP1 or later versions of the Quartus II software then you may not encounter this issue Complete the following steps to avoid this issue 1 Open pcie lib top v 2 Search for the Reconfiguration Controller instance named alt_xcvr_reconfig and comment out the entire reconfig_controller in top
41. Update Mode in Table 2 1 Added Table 5 3 to include the supported clock source for encrypted configuration data in CvP mode Added Table 6 2 to include the quartus_cvp command for compres sion and encryption modes Added Table 6 3 to include the cvp_NUMCLKS settings Updated Bit 1 and Bit 0 to reserved bits in Table 6 8 Updated the cvp_NuMCLKs settings in Figure 6 1 Altera Corporation Additional Information C Send Feedback UG 01101 2015 01 12 How to Contact Altera 7 3 Powe KAR changes July 2012 1 2 Updated Data Compression and Data Encryption sections Moved Table 5 6 Uncompressed rbf sizes to Stratix V Arria V and Cyclone V Configuration Design Security and Remote System Upgrades chapters Added Jungo WinDriver and the Linux based Plain Text C CvP driver in Software Support chapter Updated cvp_numcixs byte settings in Table 6 8 and Figure 6 1 January 2012 1 1 Added Arria V and Cyclone V devices Removed references to the CvP Off mode Updated Chapter 6 Software Support with PCIe driver and CvP programming information Added Generating Periphery Image and Fabric Image and VSEC for CvP sections May 2011 1 0 Initial release How to Contact Altera Table 7 2 Altera Contact Information Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature W
42. a Design Partition Entity Table of Contents ae ly Stratix V SSGXEA7K2F40C2 Ez Flow Summary Flow Status Successful Tue Oct 29 17 59 58 2013 Bd top nw 8 Flow Settings Quartus ll 64 Bit Version 13 1 0 Build 162 10 23 2013 SJ Full Version Bhd top top Flow Non Default GIc Revision Name top FA Flow Flansed Time Top level Entity Name top_hw Settings Ctrl Shift E Family Stratix V Device 5SGXEA7K2F40C2 A Hierarchy F Design Units Vip Set as Top Level Entity Ctrl Shift J jis Timing Models Final Logic utilization in ALMs N A until Partition Merge Tasks AES Z Total registers N A until Partition Merge Flow Full Design TT LogicLock Region p gon Bb E NA TE SE nu GB until Partition Merge v Setas Design Partition until Partition Merge gt Compile Design Za Copy Ctrl C Design Partition Properties A neb MEE until Partition Merge Expand All Import Design Partition until Partition Merge until Partition Merge gt BE SER ee 771 Edit Cattinae Collapse All Export Design Partition x Quartus II Tcl Console B tcl Print Hierarchy Incremental Compilation Tools Print All Design Files 4x Design Partitions Window Alt D S Properties 6 Click the Design Partitions Window at the bottom of the menu cascade shown in the figure above The Design Partitions Window appears 7 To add the Allow Multiple Personas column to the Design Partition
43. ad the core image for example a flash device or Ethernet controller e You have not checked Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI If both of these conditions are true the following two options are available Ifyou checked Enable autonomous PCIe HIP mode the control block takes the Hard IP for PCI Express out of reset after the periphery image is loaded The Hard IP responds to configura tion requests with Configuration Retry Status CRS and memory requests with UR status until the FPGA enters user mode e If you did not check Enable autonomous PCIe HIP mode the Hard IP remains in reset until FPGA enters user mode Link training only occurs after the FPGA enters user mode Note This parameter only controls functionality for the initial configuration It allows open PCI Express systems to meet the configuration time requirement defined in the PCI Express Base Specification CvP Example Designs C Send Feedback UG 01101 2015 01 12 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode 5 15 After the initial configuration it has no significance because the core image has already been configured c Leave all other options disabled 3 Under Category select Configuration to specify the configuration scheme and device Specify the settings in the following table Table 5 8 CvP Initialization Mode Configuration Settings Parameter Value Configuration
44. ample Designs Altera Corporation LJ Send Feedback 5 10 Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow Figure 5 5 Design Flow for the CvP Initialization Mode with the Revision Design Flow GP Initialization Mode Specify General Configuration amp CvP Initialization Device amp Pin Options Revision Design Flow v v Program Periphery via JTAG using periph jic v Confirm Link and Data Rate wv Program Core via PCle Link with top core rbf v Update Core Logic C9 UG 01101 2015 01 12 Note When you select CvP initialization mode you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP In the following walkthrough the CvP initialization mode includes the following steps Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 9 Downloading and Generating the High Performance Reference Design 5 11 Downloading and Generating the High Performance Reference Design on page 5 3 Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core on page 5 13 Creating An Alternate user_led v File for the Reconfigurable Core Region on page 5 13 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode on page 5 5 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow on
45. ap File Generate cvp app map M Create CvP files Generate cvp_app periph jic and cvp app core rbf Create config data RPD Generate cvp app auto rpd Input files to convert File Data area Properties Start Address Add Hex Data Flash Loader Add Sof P dd 5o age 5SGXEA7K2 jc EB SOF Data Page 0 auto Add File cvp app sof 5SGXEA7K2F40 o Remove Up Down Properties Generate Close Help 6 Now proceed to Bringing Up the Hardware on page 5 37 The file top cof provided in _cvp designs is a template for CvP initialization mode You can open this file in the Open Conversion Setup Data of Convert Programming File window to retrieve the parameters shown in figure above Understanding the Design Steps for CvP Update Mode CvP update mode divides the design into periphery and core images Initially you program the entire image using conventional programming options Subsequently you can download alternative versions of the core image using the PCI Express link You specify this mode in the Quartus II software by selecting the CvP Setting Subsequent Core Reconfi guration The following figure provides the high level steps for CvP update mode CvP Example Designs Altera Corporation CJ Send Feedback UG 01101 5 24 Understanding the Design Steps for CvP Update Mode 2015 01 12 Figure 5 14 Design Flow for CvP Update Mode CvP Update Mode Revision Design Flow Note When yo
46. arget the Stratix V GX FPGA Development Kit Unzip PCIe hiperf s5gx zip Copy hip s5gx x1 gl ast64 5SGXEA7K2FAO qar to your working directory Start the Quartus II software and restore hip s5gx x1 gl ast64 5SGXEA7KO2FAO qar On the Tools menu select Qsys Open top qsys Onthe System Contents tab right click DUT and select Edit Under System Settings turn on Enable configuration via the PCIe link as shown in the following figure Figure 5 3 Hard IP for PCI Express GUI System Settings Number of lanes x RI Lane rate Gen1 2 5 Gbps E Port type Native endpoint PCI Express Base Specification version 2 Application interface Avalon ST 64 bit v RX buffer credit allocation performance for received requests ow vw Reference clock frequency 100 MHz v Lt Use 62 5 MHz application clock W Use deprecated RX Avalon ST data byte enable port rx st be C Enable byte parity ports on Avalon ST interface Enable multiple packets per cycle M Enable configuration via the PCle link Lt I _ Use credit consumed selection port tx_cons_cred_sel _ Enable Configuration Bypass Enable Hard IP reconfiguration 9 Click Finish 10 On the Generation tab specify the settings in the following table Then click Generate at the bottom of the window Table 5 2 Osys Generation Tab Settings Parameter Value Create simulation model None Cr
47. ated the Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller section dynamic reconfigura tion usage guidelines e Added a new section called Using MSI X in CvP Initialization Mode under Known Issues and Solutions 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S p AN 101 Innovation Drive San Jose CA 95134 7 2 Document Revision History UG 01101 2015 01 12 oae KATE changes November 2013 2013 11 04 A
48. bout PCI Express The following links provide information about the PCI Express specifications and Altera s offerings for PCI Express Related Information Overview PCI Express Base 2 1 Specification PCI Express Base 3 0 Specification LJ Send Feedback Altera Corporation zs UG 01101 1 6 Additional Information about PCI Express 2015 01 12 e PCI Express CEM 2 0 Specification Arria V Hard IP for PCI Express User Guide Arria V GZ Hard IP for PCI Express User Guide e Cyclone V Hard IP for PCI Express User Guide e Stratix V Hard IP for PCI Express User Guide Altera Corporation Overview C Send Feedback FPGA Configuration using CvP 2015 01 12 UG 01101 amp Subscribe LJ Send Feedback CvP Configuration Images In CvP you partition your design into two images core image and periphery image You use the Quartus II software to generate the images e Periphery image periph jic contains general purpose I Os GPIOs I O registers the GCLK QCLK and RCLK clock networks and logic that is implemented in hard IP such as the Hard IP for PCI Express IP Core These components are included in the periphery image because they are controlled by I O periphery register bits The entire periphery image is static and cannot be reconfig ured e Core image core rbf contains logic that is programmed by configuration RAM CRAM This image includes LABs DSP and embedded memory The core image consists of a si
49. bout related configuration pins Refer to the respective device family pin connection guidelines e PCI Express Base Specification Provides more information about PCIe link signals e Arria V Hard IP for PCI Express User Guide Arria V GZ Hard IP for PCI Express User Guide This pin is used in Arria V and Stratix V device families 9 This pin is used in Cyclone V device family FPGA Configuration using CvP send Feedback Altera Corporation 2 CvP Pins d n a1 1 e Cyclone V Hard IP for PCI Express User Guide e Stratix V Hard IP for PCI Express User Guide Arria V Device Datasheet Provides more information about the overshoot specification e Cyclone V Device Datasheet Provides more information about the overshoot specification e Stratix V Device Datasheet Provides more information about the overshoot specification Altera Corporation FPGA Configuration using CvP C Send Feedback CvP Topologies 2015 01 12 UG 01101 amp Subscribe LJ Send Feedback CvP supports several types of topologies that allow you to configure single or multiple FPGAs Single Endpoint Use the single Endpoint topology to configure a single FPGA In this topology the PCIe link connects one PCIe Endpoint in the FPGA device to one PCIe Root Port in the host Figure 3 1 Single Endpoint Topology Configuration Device or Configuration Host and Flash Vececm 10kW Veem Configuration Vapen kW Interface
50. ck Add 16 Click OK 17 In the Partition Name window select user led user led and change the Netlist Type to Source File and turn On Allow Multiple Personas 18 Change back to the top revision in the Quartus II software design revision list Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for CvP Revision Follow these steps to specify CvP parameters using the Quartus II software CvP Example Designs Altera Corporation LJ Send Feedback 5 32 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for UG 01101 2015 01 12 CvP Revision 1 On the Assignments menu select Device and then click Device and Pin Options 2 Under Category first select General and then enable following options a b c Auto restart configuration after error If this option is enabled CvP restarts after an error is detected Enable autonomous PCIe HIP mode Checking this box has no affect if you have enabled CvP by turning on Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI The Quartus II software automatically enables autonomous mode by default In autonomous mode the control block takes the Hard IP for PCI Express out of reset after periphery image is loaded The Hard IP for PCI Express responds to configuration requests and memory requests with the normal successful status The core image is loaded using PCIe link in both CvP initialization and CvP update mode
51. ctable Internal Error Mask Begisteg si aneese sit petieiteneibertpea tud sata Cos dite 6 8 Correctable Internal Error Status Register sees emm chasissassascasaessnansnerhaswsassnssasabeneese 6 9 Correctable Internal Error Mask RegiSter E eintreten du e ra KAK 6 10 Additional Information ccccccssscccssscccssccccesccccsscccceccccssccecesccccsccsccscescesee 7 1 Altera Corporation Document Revision FlistOty entretenir i to evene sinere Robe a V RAE ISP 3 k ees ea Ke a kk ke ek 7 1 How to Contact Altera oL aa 7 3 Overview 2015 01 12 UG 01101 amp Subscribe Send Feedback Configuration via Protocol CvP is a configuration scheme supported in Arria eV Cyclone V Stratix V and Arria 10 devices families The CvP configuration scheme creates separate images for the periphery and core logic You can store the periphery image in the configuration device and the core image in host memory reducing system costs and increasing the security for the proprietary core image CvP is available for Endpoint variants Benefits of Using CvP CvP configuration scheme has the following advantages e Reduces system costs by reducing the size of the flash device to store the periphery configuration data Improves security for the proprietary core bitstream CvP ensures the PCIe host can exclusively access the FPGA core image e Enables dynamic core updates without requiring a system
52. dded optional cvP_para2 register for use when configuration data is 64 bits wide Added design constraint for input reference clock when more than one Transceiver Reconfiguration Controller connects to the transceivers on one side of the device Corrected errors in software driver flow diagram Added clarification that you must select either CvP Initialization mode or CvP Update mode The two modes cannot be combined Updated CvP Pins section Updated CvP Example Designs chapter Updated CvP Features section in Design Considerations chapter August 2013 2013 08 26 Added support for 64 bit data Changed supported clock frequencies for CvP updates using encrypted data and a non volatile key Only 12 5 MHz is supported Added reasons for using a compressed bitstream Clarified process to create separate design hierarchy for periphery and core logic Added table showing supported features in CvP Initialization and Update Mode and CvP Update Mode Clarified use of dummy writes for CvP driver in the teardown flow May 2013 2013 05 15 Added CvP Example Designs Added Partitioning a Design for the CvP Design Flow section Updated the Power Supplies Ramp Up Time and POR PCle Timing Sequence in CvP Initialization Mode and PCIe Timing Sequence in CvP Update Mode figures Moved all links in all topics to the Related Information section for easy reference December 2012 1 3 Removed Gen 3 support from the CvP
53. demark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 5 2 Understanding the Design Steps for CvP Initialization Mode UG 01101 2015 01 12 Table 5 1 Key Files for the CvP Qsys Example Design EEE ee NNN DELE altpcied_sv sdc Synopsys Design Constraints sdc for the Hard IP for PCI Express IP Core top hw sdc Top level timing constraint file sdc for the complete design top hw v Top level wrapper for the PCI Express High Performance Reference Design top cof CvP conversion file for CvP initialization mode This file specifies the input and output files that Quartus II software requires to split the original so
54. e chain through the PCIe link between the Root Port in the host and the Endpoint of the FPGA device When the initialization or update completes the first FPGA enters user mode The user IP in the first FPGA then initiates the core image initialization or update of the subsequent device The process continues until the core image of the last FPGA in the chain is initialized or updated Altera Corporation CvP Topologies C Send Feedback UG 01101 Configuration Device Y or Configuration Host Ke Vecpem and Flash m Vaen Yere Vam 10kW Configuration Ti Interface M 10kW 10kW Second FPGA i nSTATUS CONFDONE nCONFIG vP_CONFDONE PCle Link End User IP P To fetch data from the Root 3 Port through the PCle link nce H Whichissenttotheslave i FPGAs in the chain through MSEL 4 0 the FPP configuration interface 2015 01 12 Figure 3 5 Daisy Chain Topology Configuration Device or Configuration Host and Flash Veron Configuration Verem Interface 10kW 10kw First FPGA Host nSTATUS CONFDONE nCONFIG CyP CONFDONE Root PCle Link End KALP Root Complex Point Complex co nt MSEL 4 0 CvP Topologies LJ Send Feedback Verem Vecpem 10k Varem 10kW 10kW PCle Link Daisy Chain Configuration Device or Configuration Host and Flash Configuration Interface nth FPGA CONFDONE Veem
55. e mode therefore you can use the PCIe link for core image update Note For Gen 2 capable Endpoints after loading the core sof Altera recommends that software verify that the link has trained to the expected Gen 2 rate If the link is not operating at Gen 2 software can trigger the Endpoint to retrain Figure 4 3 PCle Timing Sequence in CvP Update Mode Only after power on reset the Control Block mE takes Hard IP for PCle out of reset when a J lt 4 gt CONF_DONE 1 FPGA Power Supplies PERST CvP Update a Full image configuration Core image update RP Konfiguration tatus through conventional method through the PCle Link Link Inactive Link Training Link Active LO PCle Link Status FPGA enters user mode Table 4 3 Power Up Sequence Timing in CvP Update Mode ms a 10 Maximum ramp up time requirement for all POR monitored power supplies in the FPGA to reach their respective operating range b 4 12 FPGA POR delay time 100 Minimum PERST signal active time from the host d 20 Minimum PERST signal inactive time from the host before the PCIe link enters training state e 120 Maximum time from the FPGA power up to the end of the full FPGA configuration in CvP update mode f 100 Maximum time PCIe device must enter L0 after PERST is deasserted Recommended Configuration Schemes For CvP initialization mode y
56. e Hardware Before testing the design in hardware you must install Jungo WinDriver in your DUT system For Windows the procedure is described in Installing Jungo WinDriver in Windows Systems on page 5 38 For Linux the instructions are Installing Jungo WinDriver in Windows Systems on page 5 38 You can also install RW Utilities or other system verification tools to monitor the link status of the Endpoint and to observe traffic on the link You can download these utilities for free from many web sites The test setup includes the following components e Stratix V GX FPGA Development Kit e USB Blaster e A DUT PC with PCI Express slotto plug in the Stratix V GX FPGA Development Kit e A host PC running the Quartus II software to program the periphery image sof or pof file Although a separate host PC is not strictly necessary it makes testing less cumbersome CvP Example Designs Altera Corporation CJ Send Feedback 5 38 Installing Jungo WinDriver in Windows Systems UG 01101 2015 01 12 Installing Jungo WinDriver in Windows Systems 1 Navigate to Quartus Il installation path gt quartus drivers wdrvr windows lt 32 or 64 gt 2 Run the command e wdreg inf windrvr6 inf install 3 Copy the wdapi1021 dll file to the windir system32 directory Installing Jungo WinDriver in Linux Systems 1 Navigate to Quartus Il installation path gt quartus drivers wdrvr linux lt 32 or 64 gt 2 Run the following commands a
57. e chain to the PCIe Root Port in the host The slave FPGAs are connected in the chain using the PS or FPP configuration scheme The configuration device which you use to store the periphery image in the CvP initialization mode and the full configuration image in the CvP update mode is only connected to the master FPGA The master FPGA is configured first followed by the slave FPGAs You must design a user IP for the master FPGA to fetch the configuration data from the Root Port to the slave FPGAs in the chain The data is latched out from the master device through the GPIOs and latched into the slave devices through the PS or FPP configuration pins DCLk DATA line or DATA bus By tying DCLK nCONFIG nSTATUS CONF DONI E pins and pata bus of the slave devices together the slave devices enter user mode at the same time If any device in the chain detects an error the slave device chain reinitializes and reconfigures by pulling its nstatus pin low You must ensure there is a suitable line buffering on the DcLK and para bus if you are configuring more than four slave devices in the chain Configuring Slave FPGAs with Different Configuration Files To configure the slave FPGAs with different configuration files connect the nci Eo pin of one slave FPGA to the nce pin of the next slave FPGA in the chain When the first slave FPGA completes configuration the slave FPGA pulls the nc device unconnected or use the pin as
58. e device to configure or update through the PCIe link You can connect any number of FPGAs to the host in this topology The PCIe switch controls the core image configuration through the PCIe link to the targeted PCIe Endpoint in the FPGA You must ensure that the Root Port can respond to the PCIe switch and direct the configuration transaction to the designated Endpoint based on the media access control MAC address of the Endpoint specified by the PCIe switch Figure 3 2 Multiple Endpoints Topology Altera Corporation Configuration Device or Configuration Host Host Root Complex and Flash VcceeM Configuration Vecpcm m Interface j Varom 10kW 10kW Vam 10kW 10kW First FPGA nSTATUS CONFDONE nCONFIG CvP CONFDONE PCIe Link El MSEL 4 0 nCE Configuration Device or Configuration Host and Flash Vcpam Configuration Vecpcm Vecpam 10KW Interface 10kW Vecpam wow ww nth FPGA nSTATUS CONFDONE nCONFIG CvP CONFDONE PCle Link El MSEL 4 0 nCE wv CvP Topologies C Send Feedback UG 01101 2015 01 12 Mixed Chain Mixed Chain 3 3 Use the mixed chain topology to configure multiple FPGAs that are connected in a chain using both the PCIe link and conventional configuration scheme In this topology the PCIe link connects the Endpoint of the master FPGA the first FPGA in th
59. eate testbench Qsys system None Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode 5 5 Create testbench simulation model None Create HDL design files for synthesis Verilog Create block symbol file bsf Leave this entry off Path lt working_dir gt top Simulation Leave this entry blank Testbench working dir top synthesis 11 After successful compilation close Qsys Related Information PCI Express Avalon ST High Performance Reference Design Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode Follow these steps to specify CvP parameters using the Quartus II software 1 On the Quartus II Assignments menu select Device and then click Device and Pin Options 2 Under Category select General and then enable following options a Auto restart configuration after error If this option is enabled CvP restarts after an error is detected b Enable autonomous PCIe HIP mode Checking this box has no affect if you have enabled CvP by turning on Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI The Quartus II software automatically enables autonomous mode by default In autonomous mode the control block takes the Hard IP for PCI Express out of reset after periphery image is loaded The Hard IP for PCI Express responds to configuration re
60. ebsite www altera com literature General Email nacomp6altera com Nontechnical support Software licensing Email apgcs altera com Related Information http www altera com support http www altera com training http www altera com literature 9 You can also contact your local Altera sales office or sales representative Additional Information LJ Send Feedback Altera Corporation
61. eedback UG 01101 2015 01 12 Compiling the Design for the CvP Initialization Mode 5 7 These Configuration settings use the configuration devices available on the Stratix V GX FPGA Development Board The EPCQ256 flash device is far larger than required to load a periphery image 4 Click OK to close the Device and Pin Options dialog box 5 Click OK to close the Device dialog box 6 Save your project Compiling the Design for the CvP Initialization Mode 1 To compile the design on the Processing menu select Start compilation Compilation creates a sof file in the pcie_quartus_files subdirectory Splitting the SOF File for the CvP Initialization Design Mode Follow these steps to split your sof file into separate images for the periphery and core logic 1 On the File menu select Convert Programming File 2 Under Output programming files to convert specify the options in the following table Table 5 5 CvP Initialization Output Programming Files Settings Parameter Value Programming file type JTAG Indirect Configuration File jic Configuration device EPCQ256 Mode Active Serial x4 File name Browse to and select the pcie_quartus_files directory Type the file name top jic Then click Save Create Memory Map File Turn this option on Create CvP files Turn this option on This box is greyed out until you specify the SOF Data file under Input files to convert 3 Under Input files to convert specif
62. egister to observe behavior not to drive custom logic Table 6 9 Uncorrectable Internal Error Status Register Byte Offset 0x234 31 12 0x00 Reserved 11 1 b0 RW1CS A value of 1 indicates an RX buffer overflow condition in a posted request or Completion segment 10 1 b0 RW1CS A value of 1 indicates a parity error was detected on the R2CSEB interface 9 1 b0 RWICS A value of 1 indicates a parity error was detected on the Configuration Space to TX bus interface 1 b0 RW1CS A value of 1 indicates a parity error was detected on the TX to Configuration Space bus interface 1 b0 RW1CS A value of 1 indicates a parity error was detected in a TX TLP and the TLP is not sent 1 b0 RW1CS A value of 1 indicates that the Application Layer has detected an uncorrectable internal error 5 1 b0 RW1CS A value of 1 indicates a configuration error has been detected in CvP mode which is reported as uncorrectable This bit is set whenever a CVP_ CONFIG_ERROR is asserted while in CVP_MODE 4 1 b0 RW1CS A value of 1 indicates a parity error was detected by the TX Data Link Layer 3 1 b0 RW1CS A value of 1 indicates a parity error has been detected on the RX to Configuration Space bus interface 1 b0 RW1CS A value of 1 indicates a parity error was detected at input to the RX Buffer 1 b0 RW1CS A value of 1 i
63. f or pof file into periphery and core images pcie lib Design files that are used by synthesis tools Understanding the Design Steps for CvP Initialization Mode CvP initialization mode divides the design into periphery and core images The periphery image is stored in a flash device on the PCB You program the periphery via JT AG The core image is stored in host memory You download the core image to the FPGA using the PCI Express link Note If you plan to create multiple versions of the core logic for the same periphery I O the new core images might not work with the previous periphery image You can use the Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow on page 5 9 to create reconfigurable images that connect to the same periphery image You specify CvP initialization mode in the Quartus II software by selecting the CvP Settings Power up and subsequent core configuration You might choose CvP initialization mode for any of the following reasons To satisfy the PCIe initial power up requirement for plug in cards if FPGA programming time exceeds this limit To save cost by storing the core image in external host memory To prevent unauthorized access to the core image by using encryption The following figure provides the high level steps for CvP initialization mode Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Downloading and Generating t
64. figure shows the flow of the provided CvP driver The flow assumes that the FPGA is powered up and the control block has already configured the FPGA with the periphery image which is indicated by the cvP_ N bit in the CvP status register As this figure indicates the third step of the Start Teardown Flow requires 244 dummy configuration writes to the cvP DATA register or 244 memory writes to an address defined by a memory space BAR for this device Memory writes are preferred because they are higher throughput than configuration writes The dummy writes cause a 2 ms delay allowing the control block to complete required operations O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly a
65. for CvP Initialization Mode seen 5 2 Downloading and Generating the High Performance Reference Design 5 3 Altera Corporation Configuration via Protocol CvP Implementation in Altera FPGAs User Guide TOC 3 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode E EE E E E E dicted Uere svolte NAT HER waye K dea forecast lvii vede etre abad ease 5 5 Compiling the Design for the CvP Initialization Mode sse 5 7 Splitting the SOF File for the CvP Initialization Design Mode sss 5 7 Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5 9 Downloading and Generating the High Performance Reference Design 5 11 Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5 13 Creating An Alternate user led v File for the Reconfigurable Core Region 5 13 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode T 5 14 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow T 5 16 Compiling Both the Base and cvp app Revisions in the CvP Revision Design Flow 5 18 Splitting the SOF File for the CvP Initialization Design Mode sss 5 19 S
66. gh Performance Reference Design It instantiates user_led v as a separate module Move or copy the cvp app src to a subdirectory of your working directory This alternate version of user_led v turns on the LED whenever bit 23 of a counter is one Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode Follow these steps to specify CvP parameters using the Quartus II software 1 On the Quartus II Assignments menu select Device and then click Device and Pin Options 2 Under Category select General and then enable following options Altera Corporation a b Auto restart configuration after error If this option is enabled CvP restarts after an error is detected Enable autonomous PCIe HIP mode Checking this box has no affect if you have enabled CvP by turning on Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI The Quartus II software automatically enables autonomous mode by default In autonomous mode the control block takes the Hard IP for PCI Express out of reset after periphery image is loaded The Hard IP for PCI Express responds to configuration requests and memory requests with the normal successful status The core image is loaded using PCIe link in both CvP initialization and CvP update mode The Enable autonomous PCIe HIP mode option only has effect if your design has the following two characteristics e You are using something other than the PCIe link to lo
67. gramming File Options Parameter Value Programming file type JTAG Indirect Configuration File jic Configuration device EPCQ256 Mode Active Serial x4 File name Click browse and specify pcie_quartus_files cvp_ app jic Create Memory Map File Turn this option on Create CvP files Turn this option on This box is greyed out until you specify the SOF Data file under Input files to convert 2 Under Input files to convert specify the options in the following table Table 5 13 CvP Revision Design Flow Input Files to Convert Parameter Value Flash Loader Click Add Device and select Stratix V and then 5SGXEA7K2 Click SOF Data Click Add File and navigate to pcie_quartus_ files cvp_app sof If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box you must specify the same options in the Conversion Programming File window To enable these settings click cvp_app sof then click Properties and check the appropriate boxes 3 Now turn on the Create CvP files Generate cvp_app1 periph jic and cvp_app1 core rbf parameter in the Output Programming Files section 4 To save the Conversion Programming File parameters click Save Conversion Setup and type an output file name Saving your conversion setup saves time on subsequent conversions For this exercise call your settings cvp_revision cof You can reload the conversion parameters by opening the Conversion Setup File cof
68. greed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 6 2 VSEC Registers for CvP Figure 6 1 CvP Driver Flow Can v Read the CVP_EN bit from the CvP status register yes Write 1 to the HIP_CLK_SEL by the CVP_MODE bits in the CvP mode control register followed Y Set the CVP_NUMCLKS byte to 0x01 in the CvP mode control register and issues 244 dum my memo ry writes to the hard IP forthe control block sense if the system is reset Dummy memory writes can be config writes to the CVP_DATA register or memory writes to any address defined bya BAR for this device v Write 1 to the CVP CONFIG bit in the VP pro gramming control register v Poll the CVP_CONFIG_REA DY bit from the CvP status register CVP_CONFIG_READY 1 Start Transfer v Set the CVP_NUMCLKS byte v pof to the CvP data register Write 32 bit fabric configuration data v Read the CVP CONFIG ERROR bit in the CvP status register CVP_CONFIG_ERROR 1 End of fabric configuration file core rbf Go to Teardown Log configuration error no Start Teardown v Write 0 totheS
69. gs Flow Non Default Global Sett f Flow Elapsed Time 8 Flow OS Summary 2 Flow Log LJ Restore Archived Project L3 Analysis amp Synthesis i Flow Messages dill top Base 5 Partition Merge SH cvp app CVP amp Analysis amp Synthesis Hierarchy amp Files Design Units IP Components g Revisions b of Contents Create CvP Revision Flow Full Design Revision name cvp_app Start Project _ cance Hep Ct t Tasks li c Save the Quartus II project 11 Now change to the CvP revision in the Quartus II software design revision list as shown in the following figure Figure 5 19 Changing the CvP Revision Quartus II 64 Bit data File Edit View Project Assignments Processing Tools Window Help 5 g li ll amp a 2 2 C cvp_app x 7 12 To remove user led v from the cvp app revision on the Assignments menu select Settings then select Files This is the original user led v file that turns on the LED when the LTSSM enters the Polling Compliance state 13 In the Files list click user led v then click Remove 14 To add cvp app src user led v for the cvp_apprevision in the File name box click Browse and browse to cvp app src user led v then click Add This is the modified user led v file that turns on the LED when the bit 23 of a counter is one 15 In the File name box click Browse and browse to cvp app src user led v then cli
70. he High Performance Reference Design 5 3 Figure 5 2 Design Flow for CvP Initialization Mode Specify General Configuration amp Cup Initialization Device amp Pin Options Compile Design Program Periphery via JTAG using periph jic Confirm Link and Data Rate Program Core via PCle Link with top core rbf Note When you select CvP initialization mode you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP In the walkthrough CvP initialization mode includes the following steps 1 2 3 4 5 Downloading and Generating the High Performance Reference Design on page 5 3 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode on page 5 5 Compiling the Design for the CvP Initialization Mode on page 5 7 Splitting the SOF File for the CvP Initialization Design Mode on page 5 7 Bringing Up the Hardware on page 5 37 Downloading and Generating the High Performance Reference Design Follow these steps to regenerate the PCI Express High Performance Reference Design with CvP enabled CvP Example Designs Altera Corporation LJ Send Feedback Downloading and Generating the High Performance Reference Design 1 9 MO uU 9M UG 01101 2015 01 12 Download the PCIe hiperf s5gx zip file from the PCI Express Avalon ST High Performance Reference Design web page This design includes the correct pin assignments and project settings to t
71. he back view of Stratix V Device Kit Unused Bit Up 0 Down 1 E 2 3 4 6 5 b01000 MSEL 011 213 4 X default value 0100 0 correct value for EPCQ256 In this figure the switch head outlined in by a green rectangle The up position signifies logic zero and the down position signifies logic one The MSB of the switch SW4 6 is on the far right This bit is unused and must be set to zero SW4 6 up The MSB bit of MSEL 4 is position 5 the second bit from the right To set the unused bit to 0 and MSEL 4 0 5 b10010 the SW4 6 1 sequence is up 0 down 1 up 0 up 0 down 1 up 0 reading from right to left Related Information Stratix V GX FPGA Development Kit Reference Manual Programming CvP Images and Validating the Link For CvP initialization mode you must program the periphery image top periph jic and then download the core image core image top core rbf using the PCIe Link After loading the periphery image via the JT AG port the link should reach the expected data rate and link width You can confirm the PCIe link status using the RW Utilities Then you can update the core image top core rbf using the quartus cvp command For In CvP update mode you first program the FPGA using the sof or pof image After the program ming completes the FPGA enters user mode You can now reconfigure the core image core rbf the quartus cvp command or your own driver
72. he end of the core programming file a total of 8419329 32 hi t words were sent SUCCESS CuP has finished the Application Layer is ready for normal operation INFO CuP programming took 2 seconds to complete Info Quartus II 64 Bit CuP Programmer vas successful B errors warnings Info Peak virtual memory 117 megabytes Info Processing ended Fri Dec 21 16 65 21 2612 Info Elapsed time 66 66 62 Info Total CPU time Con all processors 66 66 62 C altera 12 i quartus bin64 gt _ If you implement your own software driver to program the core image refer to the CvP Driver Support section in Chapter 6 of CvP User Guide You are now ready to run your own tests Related Information CvP Driver Support on page 6 1 CvP Debugging Check List 1 Check the PCIe configuration to ensure that it supports CvP For instance Stratix V does not support Gen3 CvP Genl x2 and Gen2 CvP are currently not available 2 Confirm that the current Quartus II software version supports CvP 3 Check physical pin assignments support CvP For Example for Stratix V only the bottom left Stratix V Hard IP for PCI Express supports CvP Other Hard IP cores in the same device do not support CvP 4 Check the PCB connections for PERST and refclk CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 44 CvP Debugging Check List 2015 01 12 5 Make sure the reset and clock connections to the Transceiver Reconfiguration Controller IP C
73. ication interface Avalon ST 64 bit RX buffer credit allocation performance for received requests ow ve Reference clock frequency Use 62 5 MHz application clock Wi Use deprecated RX Avalon ST data byte enable port rx st be Enable byte parity ports on Avalon ST interface Enable multiple packets per cycle Wi Enable configuration via the PCle link C Use credit consumed selection port tx cons cred sel Enable Configuration Bypass Enable Hard IP reconfiguration 9 Click Finish 10 On the Generation tab specify the settings in the following table Then click Generate at the bottom of the window Table 5 7 Osys Generation Tab Settings Parameter Value Create simulation model None Create testbench Qsys system None Create testbench simulation model None Create HDL design files for synthesis Verilog Create block symbol file bsf Leave this entry off Path lt working_dir gt top Simulation Leave this entry blank Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5 13 Testbench lt working_dir gt top synthesis 11 After successful compilation close Qsys Related Information PCI Express Avalon ST High Performance Reference Design Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core If you plan to perform almost co
74. iginally planned Adding extra comments in your design will help you to trace the HDL Splitting the SOF File for the CvP Update Design Mode Follow these steps to split your to create file into periphery and core images for CvP update mode You use the core image top core rbf to perform CvP updates 1 On the File menu select Convert Programming File 2 Under Output programming file specify the options in the following table These options are illustrated in the figure below Table 5 19 Output Programming File Parameter Value Programming file type Programmer Object File pof Configuration device CFI_128Mb CvP Example Designs CJ Send Feedback Altera Corporation UG 01101 5 34 Splitting the SOF File for the CvP Update Design Mode 2015 01 12 Mode 1 bit Passive Serial File name Click browse and specify pcie_quartus_files top pof Create Memory Map File Turn this option on Create CvP files Turn this option on This box is greyed out until you specify the SOF Data file under Input files to convert 3 Under Input files to convert specify the options in the following table Table 5 20 Input files to convert Click SOF Data Click Add File and navigate to pcie_quartus_ files top sof If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box you must specify the same options in the Conversion Programming File window To enable these settings click
75. ign is still not working file a Service Request SR In your SR include the following information a Describe what you have tried and the results of your tests b List the Quartus II software version the target device information about the system under test and what CvP modes are being used c Specify where the failure occurs Does it occur after loading the periphery on the first CvP update or on subsequent CvP updates d If possible attach your design so that we can review the reset and clock connections and try to replicate your failure e Describe the steps necessary to run your design 21 For CvP subsequent update you must compile both revisions for any changes to any of the following logic Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Known Issues and Solutions 5 45 a The periphery logic b The I O ports or core wrapper c The Quartus II software version Related Information e Stratix V PCI Express User Guide Stratix V GX High Development Board e Stratix V Device Handbook for MSEL 4 0 settings Known Issues and Solutions 1 CvP designs with Genl x2 configurations fail to link up after loading the periphery image One way to work around this issue is to use Gen1 x4 configuration and let the link downtrain to Gen1 x2 2 You cannot use the Transceiver Reconfiguration Controller IP Core in CvP update mode Refer to Workaround for a Known Issue with Transceiver Reco
76. ing out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 Iso 9001 2008 Registered JA DTE RYA UG 01101 2 2 CvP Update Mode 2015 01 12 After the periphery image configuration is complete the CONF_DONE signal goes high and allows the FPGA to start PCIe link training When PCIe link training is complete the PCIe link transitions to 0 state The PCIe host then initiates the core image configuration through the PCIe link After the core image configuration is complete the cvP coNFDONE pin goes high indicating the FPGA is fully configured After the FPGA is fully configured the FPGA enters user mode If you enabled the NIr_DONE signal the INIT DONE signal goes high after initialization is complete and the FPGA enters user mode In user mode the PCIe links are available for normal PCIe applications You can also use the PCIe link to change the core image To change the core image create multiple FPGA core images in the Quartus II software that have identical connections to the periphery image If the core image contains the reconfigur able core region implement the CvP revision design flow CvP Update Mode In thi
77. ization Mode on page 2 1 e CvP Update Mode on page 2 2 e CyP Example Designs on page 5 1 e Partial Reconfiguration IP Core User Guide e Design Planning for Partial Reconfiguration Prepare the Design for CvP Revision Design Flow The CvP revision design flow requires separate bitstreams for design elements implemented in the I O ring periphery and FPGA core fabric To use an I O bitstream with multiple FPGA core fabric bitstreams separate periphery from the reconfigurable core logic e The I O ring periphery partition I O ports I O registers e General purpose I Os GPIOs e Transceivers e Phase locked loops PLLs e Hard IP for PCI Express Hardened memory PHY e Global clocks GCLK e Regional clocks RCLK e The core partition Core logic to program the FPGA fabric The core logic contains both the static core region and the reconfigurable core region The core logic is stored in configuration RAM CRAM bits that program the logic array blocks LABs digital signal processing DSP and RAM of the core You may create one or more partitions for the core fabric however only one partition can include the logic that you plan to reconfigure You must ensure the reconfigurable core logic does not contain any periphery components Failure to make these connections results in the following Quartus II compilation error Error 142040 Detected illegal nodes in reconfigurable partitions Only core logic is reconfig
78. jic and click Open c Under Program Configure column select S5SGXEA7K2 and EPCQ256 d Click Start to program the periphery image to EPCQ256 flash 5 To force the host PC to re enumerate the link with the new image power cycle the DUT PC and the Stratix V GX High Performance FPGA Development Kit 6 You can use RW Utilities or another system software driver to verify the link status The following figure shows that the RW Utilities enumeration includes an Altera PCIe on Bus 01 CvP Example Designs C Send Feedback Altera Corporation UG 01101 2015 01 12 Figure 5 24 RW Utilities Transcript Bus 00 Device 1C Function 04 Intel Corporation PCI to PCI Bridge PCIE Bus 00 Device 1C Function 05 Intel Corporation PCI to PCI Bridge PCIE Bus 00 Device 1C Function 07 Intel Corporation PCI to PCI Bridge PCIE Bus 00 Device 1D Function 00 Intel Corporation EHCI USB Controller Bus 00 Device 1E Function 00 Intel Corporation PCI to PCI Bridge Bus 00 Device 1F Function 00 Intel Corporation ISA Bridge Bus 00 Device 1F Function 02 Intel Corporation AHCI Controller Bus 00 Device 1F Function 03 Intel Corporation SMBus Controller Bus 00 Device 1F Function 06 Intel Corporation Data Acquisition Signal Processing Ci Bus 01 Device 00 Function 00 Altera Corporation Controller PCIE Bus 02 Device 00 Function 00 nVidia Corporation VGA Controller PCIE Bus 02 Device 00 Function 01 nVidia Corpora
79. jjjl Revisions b of Contents Create CvP Revision Flow Full Design Revision name cvp_app Start Project _ cance Hep Ct t Tasks li c Save the Quartus II project 11 Now change to the CvP revision in the Quartus II software design revision list as shown in the following figure Figure 5 10 Changing the CvP Revision Quartus II 64 Bit data File Edit View Project Assignments Processing Tools Window Help 5 z li ll amp a 2 2 C cvp_app x 7 12 To remove user led v from the cvp app revision on the Assignments menu select Settings then select Files This is the original user led v file that turns on the LED when the LTSSM enters the Polling Compliance state 13 In the Files list click user led v then click Remove 14 To add cvp app src user led v for the cvp_apprevision in the File name box click Browse and browse to cvp app src user led v then click Add This is the modified user led v file that turns on the LED when the bit 23 of a counter is one 15 In the File name box click Browse and browse to cvp app src user led v then click Add 16 Click OK 17 In the Partition Name window select user led user led and change the Netlist Type to Source File and turn On Allow Multiple Personas 18 Change back to the top revision in the Quartus II software design revision list Compiling Both the Base and cvp app Revisions in the CvP Revision Design
80. ll use Altera Corporation FPGA Configuration using CvP C Send Feedback UG 01101 2015 01 12 CvP Pins 2 3 Figure 2 1 Periphery and Core Images Storage Arrangement for CvP Core Image Update The periphery image remains the same for different core images If you change the periphery image you must reprogram the configuration device with the new periphery image Configuration Device Periphery Image Configuration Interface PCle Host Core Images 1 ton Core Image Cas Update via mage Root PCle Link Complex You can use CvP revision design flow to create multiple reconfigurable core images that connect to the same periphery image The core logic consists of a single reconfigurable region or both static and reconfigurable regions e Reconfigured core logic This region can be programmed in user mode while the PCIe link is up and fully enumerated It must contain only resources that are controlled by CRAM such as LABs embedded RAM blocks and DSP blocks in the FPGA core image It cannot contain any periphery components such as GPIOs transceivers PLL I O blocks the Hard IP for PCI Express IP Core or other components included in the periphery image e Static logic This region cannot be modified When you initiate a core image update the cvP coNFDONE pin is pulled low indicating a core image update has started The
81. more information about uncompressed rbf sizes for entire FPGA and IOCSR DCLK frequency and POR delay Cyclone V Device Datasheet Provides more information about uncompressed rbf sizes for entire FPGA and IOCSR DCLK frequency and POR delay Stratix V Device Datasheet Provides more information about uncompressed rbf sizes for entire FPGA and IOCSR DCLK frequency and POR delay Design CvP for a Closed System When designing CvP for a closed system estimate the periphery configuration time for CvP initialization mode or full FPGA configuration time for CvP update mode You must ensure that the estimated configuration time is within the time allowed by the PCIe host Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller If your design includes the following components An Arria V Cyclone V or Stratix V device with CvP enabled Any additional transceiver PHY connected to the same Transceiver Reconfiguration Controller then you must connect the PLL reference clock which is called refc1k to the mgmt cik cix signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY In addition if your design includes more than one Transceiver Reconfiguration Controllers on the same side of the FPGA they all must share the mgmt_clk_clk signal Notes For Stratix V and Arria V GZ devices when CvP is enabled you cannot use dynamic transceiver reconfiguration for the transceiver channel
82. ndicates a retry buffer uncorrectable ECC error 1 b0 RW1CS A value of 1 indicates a RX buffer uncorrectable ECC error Uncorrectable Internal Error Mask Register Altera Corporat ion CvP Driver and Registers C Send Feedback UG 01101 2015 01 12 Correctable Internal Error Status Register 6 9 This register controls which errors are forwarded as internal uncorrectable errors With the exception of the configuration errors detected in CvP mode all of the errors are severe and may place the device or PCIe link in an inconsistent state The configuration error detected in CvP mode may be correctable depending on the design of the programming software Table 6 10 Uncorrectable Internal Error Mask Register Byte Offset 0x238 31 12 0x00 Reserved 11 1 b1 RWS Mask for RX buffer posted and completion overflow error 10 1 b1 RWS Mask for parity error on the R2CSEB interface 9 1 b1 RWS Mask for parity error on the Configuration Space to TX bus interface 8 1 b1 RWS Mask for parity error on the TX to Configuration Space bus interface 7 1 b1 RWS Mask for parity error in the transaction layer packet 6 1 b1 RWS Mask for parity error in the application layer 5 1 b0 RWS Mask for configuration error in CvP mode 4 I b1 RWS Mask for data parity errors detected during TX Data Link LCRC generation 3 l bl RWS Mask for data parity errors detected
83. ne Size Latency Timer Interrupt Pin Memory Range None Expansion ROM Subsystem ID OxD 2400000 Q D24FFFFF Prefetchable Memory Range OxB5 0x060400 0x10 0x00 INTA IRQ17 000000000 000000000 0x00 0x00000000 0x84EF1043 7 You can also confirm expected link speed and width For this Gen1 x1 example design the following figure shows that both Altera EP Link Capability Register at 0x8C and Link Status register at 0x92 have value 0x11 which confirms the link successfully comes up as Genl x1 CvP Example Designs LJ Send Feedback Altera Corporation UG 01101 5 42 Programming CvP Images and Validating the Link 2015 01 12 Figure 5 25 Checking Link Status BC L d es 2 d l BS ss md eed o il el Refresh Bus 01 Device 00 Function 00 Altera Corporation Controller PCIE Info Text Summary 0 qo 01 oz 03 04 os 06 07 08 09 0A oB OC OD OE or Device WendorlD 0 E0011172 ooo 72 11 01 EO 00 00 10 00 01 00 00 FF 10 00 00 00 eren Er an 00 00 00 CO 00 00 00 00 00 00 00 DO 00 00 00 00 TEE Yen 020 00 00 00 00 00 00 00 00 00 00 00 00 72 11 O1 18 teruptPin INT 030 00 00 00 00 50 00 00 00 00 00 00 00 OB O1 00 00 InteruptLine IRQ11 040 00 00 00 00 00 00 00 00 00 oo 00 00 00 00 00 00 B EE 0S0 05 78 84 00 00 00 00 00 00 00 00 00 00 00 00 00 BAR3 OxDOD00000 060 00 00 00 00 00 00 00 00 11 78 00 00 00 00 oo 00
84. ned e 1 Selects internal clock from PMA which is required for CVP_MODE e 0 Selects the clock from soft logic fabric This setting should only be used when the fabric is configured in USER MODE with a configuration file that connects the correct clock To ensure that there is no clock switching during CvP you should only change this value when the Hard IP for PCI Express has been idle for 10 us and wait 10 us after changing this value before resuming activity 0 CVP MODE 1 b0 RO Controls whether the Hard IP for PCI Express IP Core is in CVP_ MODE or normal mode The following encodings are defined e 1 CVP_MODE is active Signals to the FPGA control block active and all TLPs are routed to the Configuration Space This CVP_MODE cannot be enabled if CVP_EN 0 e 0 The IP core is in normal mode and TLPs are route to the FPGA fabric CvP Data Registers Altera Corporation CvP Driver and Registers C Send Feedback UG 01101 2015 01 12 CvP Programming Control Register 6 7 Table 6 7 CvP Data Register Byte Offsets 0x224 0x228 This table defines the CvP Data register 31 0 CVP DATA2 0x00000000 Contains the upper 32 bits of a 64 bit configuration data Software must ensure that all Bytes in both dwords are enabled Use of 64 bit configuration data is optional 31 0 CVP DATA 0x00000000 RW Write the configuration data to this register The data is transferred to the FPGA control bl
85. nfiguration Controller IP Core on page 5 13 for more a workaround Using MSI X in CvP Initialization Mode If you are using message signaled interrupts MSI X in CvP Initialization mode you must ensure that the MSI X table loads after the Quartus II software loads the core image To ensure that MSI X tables are set up correctly follow the steps below Setup the MSI X in the Quartus II software and enable MSI X Load the periphery image Load the core image AUC Nom Ifa driver was set up previously uninstall and reinstall the driver using your application software after the quartus cvp core image has been loaded Or disable and re enable the driver after the quartus cvp core image has been loaded 5 The MSI X table is set up You can now observe interrupts on the link CvP Example Designs Altera Corporation LJ Send Feedback CvP Driver and Registers 2015 01 12 UG 01101 amp Subscribe L J Send Feedback CvP Driver Support You can develop your own custom CvP driver for Linux using the sample Linux driver source code provided by Altera The sample driver is written in C and can be downloaded from the Configuration via Protocol webpage You can also develop your own CvP driver using the Jungo WinDriver tool You need to purchase a WinDriver license for this purpose Related Information Configuration via Protocol Provides more information about sample Linux device source code CvP Driver Flow The following
86. ngle reconfigurable region or both static and reconfigurable regions Related Information e I O Features in Arria V Devices Provides more information about the location of the transceiver banks and I O banks e I O Features in Cyclone V Devices Provides more information about the location of the transceiver banks and I O banks e I O Features in Stratix V Devices Provides more information about the location of the transceiver banks and I O banks CvP Modes CvP Initialization Mode In this mode the periphery image is stored in the external configuration device and is loaded into the FPGA through the conventional configuration scheme The core image is stored in a memory that is accessible by the PCIe host and is loaded into the FPGA through the PCIe link O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability aris
87. ntinuous updates of the reconfigurable core logic in stress tests or in your actual system you may encounter an issue with the Transceiver Reconfiguration Controller This issue might cause the PCIe link to downtrain in Quartus II 13 0 release and earlier versions of the Quartus II software If you are using Quartus II 13 0 SP1 or later versions of the Quartus II software then you may not encounter this issue Complete the following steps to avoid this issue 1 Open pcie_lib top v 2 Search for the Reconfiguration Controller instance named alt_xcvr_reconfig and comment out the entire reconfig_controller in top v The Transceiver Reconfiguration Controller instance includes 32 lines of Verilog HDL code 3 Add the 5 lines of Verilog HDL shown in below after the commented out instance alt_xcvr_reconfig wire 69 0 reconfig_to_xcvr_bus 24 h0 2 b11 44 h0 assign pcie reconfig driver 0 reconfig mgmt waitrequest 1 b0 assign pcie reconfig driver 0 reconfig mgmt readdata 32 h0 assign alt xcvr reconfig 0 reconfig busy reconfig busy 1 b0 assign alt xcvr reconfig 0 reconfig to xcvr reconfig to xcv r 2 reconfig to xcvr bus In this example the first statement hardwires the recont ig to xcvr bus to the correct values per channel The first three assignment statements specify the correct values for the waitrequest readdata reconfig busy signals The final assignment statement for alt xcvr reconfig 0 reconfig to xcvr reconfig t
88. nvert Programming File 2 Under Output programming files to convert specify the options in the following table Table 5 10 CvP Initialization Output Programming Files Settings Parameter Value Programming file type JTAG Indirect Configuration File jic Configuration device EPCQ256 Mode Active Serial x4 File name Browse to and select the pcie_quartus_files directory Type the file name top jic Then click Save Create Memory Map File Turn this option on CvP Example Designs Altera Corporation send Feedback sae UG 01101 5 20 Splitting the SOF File for the CvP Initialization Design Mode 2015 01 12 Create CvP files Turn this option on This box is greyed out until you specify the SOF Data file under Input files to convert 3 Under Input files to convert specify the options in the following table Table 5 11 CvP Initialization Input Files to Convert Settings Parameter Value Click Flash Loader Click Add Device and select Stratix V and then 5SGXEA7K2 and click OK Click SOF Data Click Add File and navigate to pcie_quartus_ files top sof If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box you must specify the same options for Conversion Programming File window To enable these settings click top sof Then click Properties and check the appropriate boxes Mode Active Serial x4 The following figure illustrates the opti
89. ny of the following reasons To change core algorithms e To perform standard updates as part of a release process To customize core processing for a different components that are part of a complex system To debug the CvP initialization mode Notes e The CvP update mode works after the FPGA enters the user mode In the user mode the PCIe link is available for normal PCIe applications and you can use the PCIe link to perform an FPGA core image update In Arria 10 devices you can the PCIe bus to perform Partial Reconfiguration For Arria 10 use the Partial Reconfiguration feature instead of CvP Update Refer to the Partial Reconfiguration IP Core User Guide for more details Table 1 1 CvP Support for Device Families CvP Modes Supported Device PCle Gen 1 PCle Gen 2 Arria 10 e CvP Initialization Contact Altera support Stratix V e CvP Initialization Contact Altera support e CvP Update 9 For Arria 10 devices use Partial Reconfiguration over the PCIe link instead of CvP Update Overview LJ Send Feedback Altera Corporation UG 01101 1 4 Prepare the Design for CvP Revision Design Flow 2015 01 12 CvP Modes Supported Device PCle Gen 1 PCle Gen 2 Arria V GZ e CvP Initialization Contact Altera support e CvP Update Arria V e CvP Initialization Contact Altera support e CvP Update Cyclone V e CvP Initialization Contact Altera support e CvP Update Related Information CvpP Initial
90. o xcvr represents the full reconfiguration bus for all active transceiver channels This bus is replicated 2 times because 2 channels are active in the Genl x1 instance Creating An Alternate user led v File for the Reconfigurable Core Region This example design creates a new version of the PCI Express High Performance Reference Design The original version of this reference design includes an LED which turns on whenever the Link Training and Status and State Machine LTSSM enters the Polling Compliance state 0x3 The alternate version of user led v turns on the LED whenever bit 23 of a counter is one The LED is instantiated as a separate module in the High Performance Reference Design to demonstrate the steps necessary to create a design with multiple versions of the core logic CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 14 Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode 2015 01 12 Complete the following steps to create the alternate version of the High Performance Reference Design 1 Download user_led zip from http www altera com literature ug user_led zip and save it to your desktop Open and unzip user_led zip Copy user_led v and top_hw v to your working directory This version of user_led v turns on when the Link Training and Status and State Machine LTSSM enters the Polling Compliance state 0x3 top_hw v is the top level wrapper for the PCI Express Hi
91. ock to configure the device Every write to this register sets the data output to the FPGA control block and generates lt n gt clock cycles to the FPGA control block as specified by the cvP NuM crus field in the CvP Mode Control register Software must ensure that all bytes in the memory write dword are enabled You can access this register using configuration writes Alternatively when in CvP mode this register can also be written by a memory write to any address defined by a memory space BAR for this device Using memory writes are higher throughput than configuration writes CvP Programming Control Register Table 6 8 CvP Programming Control Register Byte Offset 0x22C 31 2 0x0000 Reserved 1 START XFER 1 b0 RW Sets the CvP output to the FPGA control block indicating the start of a transfer 0 CVP_CONFIG 1 b0 RW When set to 1 the FPGA control block begins a transfer via CvP CvP Driver and Registers Altera Corporation LJ Send Feedback 6 8 Uncorrectable Internal Error Status Register UG 01101 2015 01 12 Uncorrectable Internal Error Status Register This register reports the status of the internally checked errors that are uncorrectable When specific errors are enabled by the Uncorrectable Internal Error Mask register they are handled as Uncorrect able Internal Errors as defined in the PCI Express Base Specification 3 0 This register is for debug only Use this r
92. om a Root Port before the core image is programmed and the device enters user mode This mode is useful when you are not using CvP to configure the FPGA but still need to satisfy the 100 ms PCIe wake up time requirement Arria V Cyclone V and Stratix V are the first devices to offer autonomous mode In earlier devices the PCI Express IP Core was released from reset only after the FPGA core was fully configured Related Information Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode on page 5 5 Altera Corporation Overview C Send Feedback UG 01101 2015 01 12 CvP Modes 1 3 CvP Modes The CvP configuration scheme supports the following modes e CvP initialization mode e CvP update mode CvP Initialization Mode This mode configures the core of the FPGA through the PCle link upon system power up Initialization refers to the initial fabric configuration image loaded in the FPGA fabric after power up Benefits of using CvP initialization mode include e Satisfying the PCIe wake up time requirement e Saving cost by storing the core image in the external host memory Preventing unauthorized access to the core image CvP Update Mode This mode assumes that you have configured the FPGA with the full configuration image from a configu ration device after the initial system power up The PCIe link is used for subsequent core image updates Choose this mode if you want to update the core image for a
93. on the RX to Configuration Space Bus interface 2 I b1 RWS Mask for data parity error detected at the input to the RX Buffer 1 1 b1 RWS Mask for the retry buffer uncorrectable ECC error 0 1 b1 RWS Mask for the RX buffer uncorrectable ECC error Correctable Internal Error Status Register This register reports the status of the internally checked errors that are correctable When these specific errors are enabled by the Correctable Internal Error Mask register they are forwarded as Correct able Internal Errors as defined in the PCI Express Base Specification 3 0 This register is for debug only Use this register to observe behavior not to drive custom logic Table 6 11 Correctable Internal Error Status Register Byte Offset 0x23C 31 7 0x000 Reserved 6 1 b0 RW1CS A value of 1 indicates that the Application Layer has detected a correctable internal error CvP Driver and Registers CJ Send Feedback Altera Corporation 6 10 Correctable Internal Error Mask Register UG 01101 2015 01 12 1 b0 RWICS A value of 1 indicates a configuration error has been detected in CvP mode which is reported as correct able This bit is set whenever a CVP_CONFIG_ ERROR occurs while in CVP_MODE 4 2 0x0 RO Reserved 1 1 b0 RWICS A value of 1 indicates a retry buffer correctable ECC error 0 1 b0 RWICS A value of 1 indicates an RX buffer correctable ECC error Cor
94. ons that you specified Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design 5 21 Flow Figure 5 12 CvP Initialization Mode Convert Programming File Settings Convert Programming File data nikshah CvP hip s5gx x1 gl ast64 5SGXEAZK2F40 restored CvP GIxl restored top top File Tools Window earchalteracom Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Output programming file Programming file type JTAG Indirect Configuration File jic Y Configuration device EPCQ256 vJ Mode Active Serial x4 Y File name pcie quartus files top jic ES Advanced Remote Local update difference file None z Iv Create Memory Map File Generate top map Options IV Create CvP files Generate top periph jic and top core rbf Create config data RPD Generate top auto rpd Input files to convert File Data area Start Address Flash Loader 5SGXEA7K2 j SOF Data Page_0 lt auto gt RSE top sof 5SGXEA7K2F40 Remove Properties Add Hex Data Up Down Properties Generate Close Help 4 Now turn on the Create CvP files Generate top periph jic and top core
95. ore are correct For CvP mode you must use re c1k to drive reconfig_clk PERST must drive reconfig_reset to the Hard IP for PCI Express IP Core 6 Confirm that the design meets timing constraints for setup hold time and recovery for multi corners 7 Check that test_in bus is hardwired to 0xA8 The following test_in signals are most important when debugging a Setting test_in 7 1 disables support for the lower power state b Setting test_in 5 1 prevents the core from entering the Compliance Mode Setting test in 3 1 indicates that the Hard IP for PCI Express is implemented in an FPGA 8 Disable power management support in the host BIOS settings 9 If CvP fails try a similar Altera CvP example design to determine if the symptoms remain the same If the failure still persists try a non CvP design and take note of the differences 10 Determine if the example CvP design with similar configuration works on the same platform 11 Confirm that the Vendor ID and Device ID arguments specified as arguments to the quartus cvp exe command match the values specified in the Stratix V Hard IP for PCI Express IP Core GUI 12 If you are designing an open system test with different PCs and compare the results 13 If the first CvP update fails check that the correct quartus cvp exe command is used For 32 bit systems you must use quartus bin quartus_cvp exe For 64 bit systems the correct quartus cvp version is quartus bin64 14 Befo
96. ou can configure the FPGA with the periphery image using the AS PS or FPP configuration scheme Design Considerations Altera Corporation Send Feedback UG 01101 4 6 Recommended Configuration Schemes 2015 01 12 For CvP update mode you can configure the FPGA fully using one of the configuration schemes listed in the table below The table lists the configuration schemes based on the fastest DcLK frequency with data compression and encryption features disabled in the CvP update mode These features require different data to clock ratios which prolongs total configuration time Consequently total configuration time does not meet the 200 ms PCle wake up timing specification Table 4 4 Recommended Configuration Schemes for CvP Update Mode FPP x8 FPP x16 Arria V GX FPP x16 FPP x8 FPP x16 Arria V GT FPP x16 FPP x16 FPP x32 Arria V GZ FPP x32 Arria V SX FPP x16 Arria V ST FPP x16 Altera Corporation Design Considerations C Send Feedback UG 01101 2015 01 12 Recommended Configuration Schemes 4 7 C3 AS x4 FPP x8 FPP x16 Cyclone V GX C4 C5 FPP x8 FPP x16 FPP x16 FPP x8 FPP x16 Cyclone V GT FPP x16 TBD Cyclone V SX FPP x8 FPP x16 FPP x8 FPP x16 Cyclone V ST FPP x16 FPP x32 FPP x32 Stratix V GX FPP x32 B6 B9 BB C5 Stratix V GT FPP x32 C7
97. page 5 16 Compiling Both the Base and cvp app Revisions in the CvP Revision Design Flow on page 5 18 Splitting the SOF File for the CvP Initialization Design Mode on page 5 7 Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow on page 5 21 Bringing Up the Hardware on page 5 37 Downloading and Generating the High Performance Reference Design Follow these steps to regenerate the PCI Express High Performance Reference Design with CvP enabled 1 CNA QI d UO WN Download the PCIe hiperf s5gx zip file from the PCI Express Avalon ST High Performance Reference Design web page This design includes the correct pin assignments and project settings to target the Stratix V GX FPGA Development Kit Unzip PCIe hiperf s5gx zip Copy hip s5gx x1 gl ast64 5SGXEAZ7K2FAO qar to your working directory Start the Quartus II software and restore hip s5gx x1 gl ast64 5SGXEA7K2FAO qar Onthe Tools menu select Qsys Open top qsys On the System Contents tab right click DUT and select Edit Under System Settings turn on Enable configuration via the PCIe link as shown in the following figure CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 12 Downloading and Generating the High Performance Reference Design 2015 01 12 Figure 5 6 Hard IP for PCI Express GUI Number of lanes 5L Lane rate Gent 2 5 Gbps PCI Express Base Specification version 2 18 Appl
98. plies are within their specified voltage tolerances and are stable The embedded hard reset controller triggers after the internal status signal and indicates that the periphery image has been loaded This reset does not trigger off of PERST For CvP initialization mode the PCIe link supports the FPGA core image configuration and PCIe applications in user mode Design Considerations Altera Corporation LJ Send Feedback f UG 01101 4 4 PCle Wake Up Time Requirement for CvP Update Mode 2015 01 12 Note For Gen 2 capable Endpoints after loading the core sof Altera recommends that software verify that the link has trained to the expected Gen 2 rate If the link is not operating at Gen 2 software can trigger the Endpoint to retrain Figure 4 2 PCle Timing Sequence in CvP Initialization Mode Only after power on reset the Control Block i il takes Hard IP for PCle out of reset when j b ie Program periphery and calibrate gt CONF_DONE 1 FPGA enters user mode FPGA Power Supplies PERST CvP Update 4 gt 4 Jakin J ee ee PCle Link Status j Link Inactive Link Training Link sd LO Table 4 2 Power Up Sequence Timing in CvP Initialization Mode Timing Sequence Timing Range Description ms a 10 Maximum ramp up time requirement for all POR monitored power supplies in the FPGA to reach their respective operating range b 4 12 FPGA POR delay time
99. plitting the SOF File for the CvP Initialization Mode with the CvP Revision Design lj 5 21 Understanding the Design Steps for CvP Update MOde seite trito etd t dae 5 23 Downloading and Generating the High Performance Reference Design 5 25 Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5 26 Creating An Alternate user led v File for the Reconfigurable Core Region 5 27 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for EE US H 5 27 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow H 5 29 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for ud usn 5 31 Compiling the Design for the CvP Update Mode etre tette serta etti 5 33 Splitting the SOF File for the CvP Update Design Mode sse 5 33 Splitting the SOF File for CvP Update Mode with the CvP Revision Design Flow 5 35 Bringing Up the Parc wane uico erii pn LAMP EO UO ETUR EAR Hese NNE RRA k areais 5 37 Installing Jungo WinDriver in Windows Systems sees 5 38 Installing Jungo WinDtriver in Linux Systems sssscsasccsssssessssssasevsenssosnssponssnssecnspansevsasedesnsanca
100. quests and memory requests with the normal successful status The core image is loaded using PCIe link in both CvP initialization and CvP update mode The Enable autonomous PCIe HIP mode option only has effect if your design has the following two characteristics e You are using something other than the PCIe link to load the core image for example a flash device or Ethernet controller e You have not checked Enable Configuration via the PCIe link in the Hard IP for PCI Express GUI If both of these conditions are true the following two options are available Ifyou checked Enable autonomous PCIe HIP mode the control block takes the Hard IP for PCI Express out of reset after the periphery image is loaded The Hard IP responds to configura tion requests with Configuration Retry Status CRS and memory requests with UR status until the FPGA enters user mode e Ifyou did not check Enable autonomous PCIe HIP mode the Hard IP remains in reset until FPGA enters user mode Link training only occurs after the FPGA enters user mode CvP Example Designs LJ Send Feedback Altera Corporation Note Setting up CvP Parameters in Device and Pin Options GUI for CvP Initialization Mode UG 01101 2015 01 12 This parameter only controls functionality for the initial configuration It allows open PCI Express systems to meet the configuration time requirement defined in the PCI Express Base Specification After the initial configuration it has no
101. r the Link Training and Status and State Machine LTSSM enters the Polling Compliance state 0x3 The alternate version of user led v turns on the LED whenever bit 23 of a counter is one The LED is instantiated as a separate module in the High Performance Reference Design to demonstrate the steps necessary to create a design with multiple versions of the core logic Complete the following steps to create the alternate version of the High Performance Reference Design 1 2 3 Download user_led zip from http www altera com literature ug user_led zip and save it to your desktop Open and unzip user_led zip Copy user_led v and top_hw v to your working directory This version of user_led v turns on when the Link Training and Status and State Machine LTSSM enters the Polling Compliance state 0x3 top_hw v is the top level wrapper for the PCI Express High Performance Reference Design It instantiates user_led v as a separate module Move or copy the cvp_app_src to a subdirectory of your working directory This alternate version of user_led v turns on the LED whenever bit 23 of a counter is one Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for CvP Revision Follow these steps to specify CvP parameters using the Quartus II software 1 2 On the Assignments menu select Device and then click Device and Pin Options Under Category first select General and then enable following options a
102. rbf parameter in the Output Programming Files section Note If you do not check this box the Quartus II software does not create separate files for the periphery and core images 5 Click Save Conversion Setup to save these settings For this exercise call your settings cvp base cof The Quartus II software does not automatically save your choices 6 Click Generate to create top periph jic and top core rbf Note The generated CvP peripheral file size matches the size of the configuration device chosen Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow To implement the CvP Revision Design Flow in CvP initialization mode you must replace the base sof top sof with the revision sof cvp appl sof You must also specify a different file name for the CvP revision This example uses cvp_app jic The periphery and the core images created for the CvP revision are cvp_app periph jic and cvp_app core rbf respectively Follow these steps to create the periphery and core images for the CvP revision 1 On the File menu select Convert Programming File Under Output programming file specify the options in the following table These settings are illustrated in the figure below CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 22 Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design 2015 01 12 Flow Table 5 12 CvP Revision Design Flow Output Pro
103. re executing the quartus cvp command make sure that the Memory Space Enable bitis set in the Command register of PCI Express Configuration Space If the BIOS does not enable this bit you must use a system tool such as RW Utilities to write a value of 0x0006 to the Command register at offset 0x4 Writing this value will set both Memory Space Enable andMaster Bus Enable bits 15 If encryption or compression is enabled disable them and retry Record the symptoms 16 Check if the design works after configuring the FPGA with the SOF via JTAG and then doing a warm reboot The sof file contains both periphery image and the core image consequently this test not determine which type of image causes the failure 17 Use a PCI Express analyzer to capture the PCIe trace of the failing scenarios Observe the transitions of LTSSM if it fails to get insight into the link failures 18 Use the Power On Trigger of the SignalTap II Embedded Logic Analyzer and record the LTSSM transitions Determine whether LTSSM goes to LO 0xF or toggles between Detect states and Polling states 19 Disable the Transceiver Reconfiguration Controller and hardwire other inputs as described in to zero except the xecon ig to xcvr bus which requires to drive high bit 44 of each channel The remaining bit of reconfig to xcvr are tied to low The sample file is top wo reconfig v under altera pcie cvp hw devkit ed directory 20 If you have tried all these suggestions and your des
104. rectable Internal Error Mask Register This register controls which errors are forwarded as Internal Correctable Errors This register is for debug only Table 6 12 Correctable Internal Error Mask Register Byte Offset 0x240 31 7 0x000 Reserved 6 1 b0 RWS Mask for corrected internal error reported by the Application Layer 5 1 b0 RWS Mask for configuration error detected in CvP mode 4 2 0x0 RO Reserved 1 1 b0 RWS Mask for retry buffer correctable ECC error 0 1 b0 RWS Mask for RX buffer correctable ECC error Altera Corporation CvP Driver and Registers C Send Feedback Additional Information 2015 01 12 UG 01101 X subscribe Send Feedback Additional information about the document and Altera Document Revision History Table 7 1 Document Revision History ERCENEI INE MN December 2015 01 12 Updated the CvP Modes section to indicate difference between CvP 2014 Initialization and CvP Update modes e Added Table CvP Support for Device Families in the CvP Modes section e Added a new section called Autonomous Mode Corrected a typographical error in Figure Switch 4 SW4 Configu ration for MSEL 4 0 5 b10010 on the back view of Stratix V Device Kit to indicate that down position signifies logic one Corrected modes supported for Arria V and Cyclone V Gen2 variants Gen2 supports CvP initialization mode Gen2 does not support CvP update mode e Upd
105. s Yes Non volatile key No 12 5 MHz Yes Yes Volatile key CvP Features 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01101 4 2 Core Image Update 2015 01 12 The following features are supported in CvP Initialization and in CvP Update mode e Compression Decompression e Encryption Decryption Partial Reconfiguration e Remote System Upgrade Note Contact Altera support to use the Remo
106. s Window right click on the top bar of Design Partition Window next to the Color heading and select Allow Multiple Personas from the list as shown in the following figure CvP Example Designs Altera Corporation send Feedback UG 01101 5 30 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 2015 01 12 Figure 5 17 Allowing Multiple Personas Project Navigator pau r Home E Compilation Report top E 4j pcie tib synthesistop v Table of Contents n8 GETENNEM f Flow Settings amp S Flow Non Default Gic E5 Flow Elapsed Time ff Flow OS Summary ly Stratix V SSGXEA7K2F40C2 Bid top hw 4h B top top gt Flow Status Successful Tue Oct 29 17 59 58 201 Quartus Il 64 Bit Version 13 1 0 Build 162 10 23 2013 SJ Full Ver Revision Name top Top level Entity Name top hw Family Stratix V amp Device 5SGXEA7K2F40C2 Jd Hierarchy Files 3 Design Units X IP Components 8 Flow Log 4 _ annem y Analysis amp Synthesis Timing Models Final Tasks EX EB summary Logic utilization in ALMs N A until Partition Merge Lj Settings Total registers N A until Partition Merge Flow Full Design vJ Customize Task E ul gt Compile Design v 3 gt EREY TINEN 4 x Quartus II Tcl Console tcl Parallel Compilati Source Files Reac ff IP Cores Summar J Design Partition S 9 Parfitinn far ios
107. s in CvP enabled Hard IP For Cyclone V and Arria V devices when CvP is enabled in PCIe Gen1 mode you cannot use dynamic transceiver reconfiguration for the transceiver channels in CvP enabled Hard IP Design Considerations Altera Corporation LJ Send Feedback CvP Example Designs 2015 01 12 UG 01101 amp Subscribe LJ Send Feedback The example designs in this chapter illustrate the steps required for CvP initialization mode CvP initialization with subsequent changes the core logic and CvP update mode All start with the PCI Express High Performance Reference Design that you can download from the Altera website The example designs show how to use the CvP revision design flow to prepare the design for reconfigurable core logic The CvP process involves the interactions between the PCI Express host the FPGA Control Block the Stratix V Hard IP for PCI Express IP Core and the CRAM in FPGA as indicated in the following figure The Control Block and FPGA CRAM are hidden You cannot access them Consequently you cannot simulate the CvP functionality Figure 5 1 Key Components in a CvP Design CvP Hidden Logic Control Block The following table describes some of the key files included in the example design O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Tra
108. s mode the FPGA device is initialized after initial system power up by loading the full configuration image from the external configuration device to the FPGA device through the conventional configuration scheme After the full FPGA configuration image is complete the cour pou signal goes high After the FPGA is fully configured the FPGA enters initialization and user mode If you enable the INIT DONE signal the INIT_DONE signal goes high after initialization is completed and the FPGA enters user mode In user mode the PCIe links are available for normal PCIe applications You can use the PCIe link to perform an FPGA core image update To perform the FPGA core image update you create multiple FPGA core images in the Quartus II software that have identical connections to the periphery image If the core image contains the reconfigurable core region you must implement the CvP revision design flow Notes e You cannot combine the features of CvP Update Mode and CvP Initialization Mode in a single design For example you cannot create a CvP Update image for your Quartus II project and then specify a CvP Initialization periphery image in your configuration scheme e You must choose the same bitstream settings for all core images For example if you have selected either encryption compression or both encryption and compression features for the first core image you must turn on the same features for the other core images that you wi
109. s you to create a reconfigurable core image that work with the single periphery image The core image is stored in host memory You download the core image to the FPGA using the PCI Express link By using the Revision Design Flow you can change the core image after the initial download to run alternate versions of the core logic You specify this mode in the Quartus II software by selecting the CvP Settings Power up and subsequent core configuration When the FPGA is fully programmed the FPGA enters user mode In user mode you can reprogram the original static core image The following are typical reasons to choose CvP initiali zation mode To satisfy the PCIe initial power up requirement for plug in cards if FPGA programming time exceeds this limit To save cost by storing the core image in external host memory To prevent unauthorized access to the core image by using encryption To change the core logic the following reasons To customize the core logic for different tasks e To provide periodic revisions for routine maintenance of the core logic If you plan to create multiple versions of the core logic for the same periphery I O the new core images might not work with the previous periphery image You can use the CvP Revision Design Flow to create reconfigurable images that connect to the same periphery image The following figure provides the high level steps for CvP initialization mode with the CvP Revision Design Flow CvP Ex
110. significance because the core image has already been configured c Leave all other options disabled 3 Under Category select Configuration to specify the configuration scheme and device Specify the settings in the following table Table 5 3 CvP Initialization Mode Configuration Settings Parameter Value Configuration scheme Active Serial x4 Configuration mode Standard Configuration device EPCQ256 Configuration device I O voltage Auto Force VCCIO to be compatible with configura tion I O voltage Leave this option off Generate compressed bitstreams Turn this option off Because this is a small example design it does not use a compressed bitstream For larger designs using a compressed bitstream signifi cantly reduces configuration time In addition a compressed bitstream requires a smaller flash device Active serial clock source 100 MHz Internal Oscillator Enable input tri state on active configuration pins in user mode Leave this option off Under Category select CvP Settings For CvP Initialization mode specify the following settings in the following table Table 5 4 CvP Initialization Category Settings Parameter Value CvP Initialization Enable CvP CONFDONE pin Power up and subsequent core configuration Turn this option on Enable open drain on CVP_CONFDONE pin Turn this option on Altera Corporation CvP Example Designs C Send F
111. te System Upgrade feature Core Image Update If you are not using CvP you can update the FPGA image using the remote system upgrade feature that is supported in conventional configuration schemes Partial Reconfiguration You can design your system for CvP and partial reconfiguration Partial reconfiguration is an advanced feature If you are interested in using partial reconfiguration contact Altera for support Designing CvP for an Open System When designing a CvP system for an Open System ensure that you observe the guidelines provided in this section FPGA Power Supplies Ramp Time Requirement For an open system you must ensure that your design adheres to the FPGA power supplies ramp up time requirement The power on reset POR circuitry keeps the FPGA in the reset state until the power supply outputs are within the recommended operating range A POR event occurs when you power up the FPGA until the power supplies reach the recommended operating range within the maximum power supply ramp time tRaMP For CvP the total tramp must be less than 10 ms from the first power supply ramp up to the last power supply ramp up You must select fast POR by setting the PORSEL pin to high The fast POR delay time is in the range of 4 12 ms allowing sufficient time after POR for the PCIe link to start initialization and configuration Altera Corporation Design Considerations C Send Feedback UG 01101 2015 01 12 PCle
112. tion HD Audio Device PCIE Bus 07 Device 00 Function 00 VIA Technology IEEE 1394 OpenHCI Controller PCIE Bus 08 Device 00 Function 00 Marvell Technology AHCI Controller PCIE Bus 09 Device 00 Function 00 ASMedia Technology USB Controller PCIE Bus 0A Device 00 Function 00 ASMedia Technology USB Controller PCIE Bus 0B Device 00 Function 00 Intel Corporation Ethernet Controller PCIE Bus FF Device 08 Function 00 Intel Corporation System Device Bus FF Device 08 Function 03 Intel Corporation System Device PCIE Bus FF Device 08 Function 04 Intel Corporation System Device PCIE Bus FF Device 09 Function 00 Intel Corporation System Device Bus FF Device 09 Function 03 Intel Corporation System Device PCIE Bus FF Device 09 Function 04 Intel Corporation System Device PCIE Bus FF Device 0A Function 00 Intel Corporation System Device Bus FF Device 0A Function 01 Intel Corporation System Device Bus FF Device 0A Function 02 Intel Corporation System Device Bus FF Device 0A Function 03 Intel Corporation System Device Bus FF Device 0B Function 00 Intel Corporation System Device Bus FF Device 0B Function 03 Intel Corporation System Device Bus FF Device 0C Function 00 Intel Corporation System Device Programming CvP Images and Validating the Link Info Text Summary 5 41 Device VendorID 0 1D188086 Revision ID Class Code Cacheli
113. to configura tion requests with Configuration Retry Status CRS and memory requests with UR status until the FPGA enters user mode e If you did not check Enable autonomous PCIe HIP mode the Hard IP remains in reset until FPGA enters user mode Link training only occurs after the FPGA enters user mode Note This parameter only controls functionality for the initial configuration It allows open PCI Express systems to meet the configuration time requirement defined in the PCI Express Base Specification After the initial configuration it has no significance because the core image has already been configured c Leave all other options disabled 3 Under Category select Configuration to specify the configuration scheme and device Specify the settings in the following table Table 5 15 CvP Update Mode Configuration Settings Parameter Value Configuration scheme Passive Serial Configuration mode Standard Configuration device Auto Configuration device I O voltage Auto Force VCCIO to be compatible with configura Leave this option off tion I O voltage Generate compressed bitstreams Leave this option on Active serial clock source 100 MHz Internal Oscillator Enable input tri state on active configuration pins Leave this option off in user mode Under Category select CvP Settings Specify the settings in the following table Table 5 16 CvP Update Category Settings Parameter Value CvP via
114. top sof then click Properties and check the appropriate boxes 4 Now turn on the Create CvP files Generate top periph jic and top core rbf parameter in the Output Programming Files section 5 Click Generate to create top periph pof and top core rbf The periphery file top periph pof is generated but it is not used Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Splitting the SOF File for CvP Update Mode with the CvP Revision Design Flow 5 35 Figure 5 20 Base Revision of CvP Update Mode Convert Programming File Settings Lj Convert Programming File data nikshah CvP hip_s5gx_x1_gl1_ast64 5SGXEA 7K2F40 restored CvP_G1ixl _restored top 0 x File Tools Window Search altera com Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Programmer Object File pof Options Configuration device CFI_128Mb Mode 1 bit Passive Serial File name pcie_quartus_files top pof 1 Advanced Remote Local update difference file NONE Iv Create Memory Map File Generate top map IF Create config data RPD Generate top auto rpd Input files to convert File Data area Start Address
115. u Total pins N A until Partition Merge Total virtual pins N A until Partition Merge Total block memory bits N A until Partition Merge Total DSP Blocks N A until Partition Merge ioral HSSI STD RX PCSs N A until Partition Merge E a Compilation Hierarchy Path v Netlist Type Ignore Source File Changes Fitter Preservation Level 4 3s Design Partitions v Color A lt lt new gt gt Source File Status 4j Top Source File A 3 See Post Fit Netlist Status Imported Last Imported From 8 v Allow Multiple Personas Input Persona a ASD Region 2 Boundary Optimizations amp Strict Preservation 8 Click the core instance user led user led and set Allow Multiple Personas to On 9 Click in the Netlist Type column and set the user led user led Netlist Type to Source File 10 Follow these steps to create a CvP revision for the modified project a Under the Revisions tab right click on the Revision top and select Create CvP Revision The Create CvP Revision dialog box appears b For the Revision name type cvp_app and click OK to create a CvP revision as illustrated in the following figure Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for 5 31 CvP Revision Figure 5 18 Specifying Revision Name Project Navigator fax ER Compilation Report top gt Compile All a Flow Summary Flow Settin
116. u select CvP initialization mode you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP In the walkthrough CvP update mode includes the following steps 1 Downloading and Generating the High Performance Reference Design on page 5 3 2 Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core on page 5 13 3 Creating An Alternate user led v File for the Reconfigurable Core Region on page 5 13 4 Setting up CvP Parameters in Device and Pin Options GUI for CvP Update Mode for CvP Revision on page 5 27 Altera Corporation CvP Example Designs C Send Feedback UG 01101 2015 01 12 Downloading and Generating the High Performance Reference Design 5 25 Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow on page 5 16 CvP Example Designs 5 6 Compiling the Design for the CvP Update Mode on page 5 33 7 Splitting the SOF File for the CvP Update Design Mode on page 5 33 8 Bringing Up the Hardware on page 5 37 By default once the FPGA enters user mode you can reprogram the original static core image If you want to have multiple core images in user mode you can use the CvP Revision Design Flow to create multiple core images that connect to the same periphery image Downloading and Generating the High Performance Reference Design Follow these steps to regenerate the PCI Express High Performance Reference Design with CvP enabled 1 Download the P
117. urable in this version of the Quartus II software Altera Corporation Overview C Send Feedback UG 01101 2015 01 12 Figure 1 2 Recommended Design Hierarchy CvP Topologies 1 5 The following figure shows the recommended design hierarchy for a design including the Hard IP PCI Express IP Core an interface to DDR3 SDRAM and core logic Hard IP for PCle Top Level Design Periphery Logic Core Logic ee DDR3 SDRAM Interface Custom Logic DDR3 Glue Logic PCle Gasket Logic This design hierarchy represents the actual partition after the Quartus II compilation You may have to run Quartus II compilation several times to ensure that the reconfigurable core logic does not contain any periphery elements It may take several Quartus II compilatioins for you to completely separate the periphery and core logic CvP Topologies You can configure the FPGA using the following topologies Single endpoint to configure a single device Multiple endpoints to configure multiple devices using a PCIe switch Mixed chain to configure multiple devices using a single configuration file or multiple configuration files for slave devices in the chain Daisy chain to configure multiple devices with two PCIe hard IP cores in the FPGA configured as an Endpoint and a Root Port Related Information CvP Topologies on page 3 1 Additional Information a
118. vensse 5 38 Modifying MSEL for Active Serial x4 Flash on Stratix V Dev Kit sss 5 38 Programming CvP Images and Validating the Link ertet 5 39 CyP Debupbing Check LiSi i 58 i40 yol nayen ley erer dale dev ayak eke ay re b b der pita 5 43 Known 1 s es arid Solution M 5 45 Using MSI X in CvP Initialization NIBUO een quitan pte tana en rek erke tutis eia inde 5 45 CyP Driver and RegisSl r8 in l ser esso EUN eke eke ra Hal Her k key keya NIE UM n 6 1 CvP Driver SUP POL 6 1 CyP Driver Ny rr n en eae ka rr 6 1 VSEC Registers for OY TL Y 6 2 Altera defined Vendor Specific Capability Header Register sss 6 3 Altera defined Vendor Specific Header Register isiswiosssssassisesassssiisisnssaavssesssnecsasisususversndiaunssess 6 3 Alter Marker RESIS VET RM 6 4 CYP Status Register eee edere oit diera ite ists a eve ratos 6 4 GyP Mode Control BepISEet aca ya Hln denn R RO cia dey Heidi ni d p TES 6 5 A nEb gol e 6 6 Altera Corporation TOC 4 Configuration via Protocol CvP Implementation in Altera FPGAs User Guide CvP Programming Control RegiSt ives cscessszsicasavsasbvnasnsvsvenanvanuabinssacdonenstqnesstnieesaiiescuaaeranseenaionees 6 7 Uncorrectable Internal Error Status Resistant ettet idit rrr Len AR dE 6 8 Unicorre
119. y the options in the following table Table 5 6 CvP Initialization Input Files to Convert Settings Parameter Value Click Flash Loader Click Add Device and select Stratix V and then 5SGXEA7K2 and click OK CvP Example Designs Altera Corporation LJ Send Feedback UG 01101 5 8 Splitting the SOF File for the CvP Initialization Design Mode 2015 01 12 Click SOF Data Click Add File and navigate to pcie_quartus_ files top sof If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box you must specify the same options for Conversion Programming File window To enable these settings click top sof Then click Properties and check the appropriate boxes Mode Active Serial x4 The following figure illustrates the options that you specified Figure 5 4 CvP Initialization Mode Convert Programming File Settings Convert Programming File data nikshah CvP hip_s5gx_x1_gl1_ast64_5SGXEA7K2F40 restored CvP_G1ixl1_restored top top File Tools Window Search alteracom Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Output programming file Programming file type TAG Indirect Configuration File jic hd Options Configuration device pcq256

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