PCLD-788 RELAY MULTIPLEXER BOARD USER'S MANUAL
Contents
1. 3ms 1 Chiebarelay son Y n Start to close Ch B i Channel closed 6ms Groin elosed Channel not closed x Output signal Ch B voltage Ch A voltage Bounce 11 Operations A PCLD 788 When channel close is low do not measure signal through this multiplexer since the relay contacts are not stable 3 2 Signal Connection PCLD 788 can multiplex up to 16 analog input signals Input channel selection and board selection are controlled by an 8 bit TTL CMOS digital signal issued by the data acquisition control card 12 CHAPTER 4 SOFTWARE PROGRAMMING PCLD 788 is a Relay Multiplexer Daughter Board which can be connected with PCL 711 PCL 718 PCL 812 and PCL 860 which attach with D O port and 5V 12V power supply A flat cable which has 20 pins always be used to connect from the board s Digital Output Port to PCLD 788 CN2 or CN3 digital input For instance following diagram is that PCL 860 be connected with PCLD 788 using 20 pin s flat cable PCLD 788 Flat Cable 20 pir fe s 2899999 9909990909 9999899999 9999999 BOBDSBEBB5DBSBBS5SBDDBDDB555BSSSS5 Fig 4 1 1 In the above diagram shows that PCL 860 D O PORT connect with PCLD 788 DI PORT so PCL 860 D O PORT can use to control PCLD 788 The PCL 860 D O PORT bit 0 to bit 3 select PCLD 788 channel and bit 4 to bit 7 select PCLD 788 address Following is an example program shows how to pro2. the board please store it in the package for protection Discharge any static electricity by touching the back of the system unit before you handle the board You should avoid contact with materials that create static electricity such as plastic vinyl and styrofoam The board should be handled only by the edges to avoid static electric discharge which could damage the integrated circuits on the PCLD 788 2 2 Connector CNI Sixteen channels of input CHO to CH15 CN2 amp CN3 CN2 and CN3 are 20 pins connectors and the both have same pins assignment The signals on these connectors are multiplexer control signals and the pin assignments are described as Fig 2 2 1 The bits C3 to CO are used as multiplexer channel selection control The binary value of C3 to CO corresponds Installation PCLD 788 CN4 CNS CN6 amp CN7 CN8 to the channel number selected For example when C3 to CO are 1010 channel 10 is closed The bits C7 to C4 are board selection Signals The output of PCLD 788 is enabled only when the bit pattern of C7 to C4 is matched with the setting of SW1 Card ID Pin 17 to pin 20 are power supply from PC Others pins are not used co ci c2 23 c4 c5 c ri GND GND 5V 12v Fig 2 2 1 CJC signal output OV at 0 C 24 4mV C Channel close signal output It offers both inversed and non inversed logic The output signal of the relay multiplexer External power input terminal Exte
3. AMMING 13 APPENDIX A BLOCK DIAGRAM nda kao aos da 17 APPENDIX B CONNECTOR JUMPER AND VR LOCATION ra ete ei 19 CHAPTER 1 GENERAL INFORMATION 1 1 Introduction PCLD 788 Relay Multiplexer Board is a daughter board controlled by the digital output port of PCL 711 PCL 718 PCL 812 and other data acquisition card with digital output port The PCLD 788 can multiplex sixteen analog inputs to one output and can be cascaded up to 16 boards and 256 channels The multiplexer has break before make mechanism which makes two channels never short together This board also offers channel close signal for measurement devices to make correct measurement PCLD 788 also contains cold junction sensing circuit and allows the measurement of thermocouple transducer All types of thermocouple can be handled with software compensation and linearization 1 2 Product Features Asummary of PCLD 788 features are as follow 16 channel input and 1 channel output Break before make switching 3 milliseconds between opening and closing Channel close signal output Cold junction temperature output Expandable to 256 input channels maximum Using PC power or external power selectable Input voltage isolation withstand 100V DC maximum General Information PCLD 788 1 3 Specifications Input Channel Output Channel Maximum switching power Maximum switching voltage Maximum switching current Maximum carry curr
4. F OFF OFF vi OFF ON ON ON 8 OFF ON ON OFF 9 OFF ON OFF ON 10 OFF ON OFF OFF li OFF OFF ON ON 12 OFF OFF ON OFF 13 OFF OFF OFF ON 14 OFF OFF OFF OFF 15 Installation The control signals bit C7 to bit C4 on connector CN2 CN3 are used to select the board vyhich format of bit C7 to C4 is as following Bit C7 Bit C6 tr txi tz tr t Iz I tm tata tata ta a ta ta t m t m tt ta tt ta eee tr t t t t m tt tt m m t ta m m ta ta the multiplexer output is enabled If the board is not selected the output is disabled and is left open The tu t tz tt tz tt m tt m ae Bit C5 Bit C4 ADDR ep UB ONKPOVOJNMUSUNHKHO When more than one PCLD 788 boards are cascaded as following figure every PCLD 788 boards has its individual address To access Installation PCLD 788 the PCLD 788 with address 1 and channel 2 the control signals on CN2 CN3 bit C7 to bit CO should be 00010010 hex12 D O DA D I D I Data Acquistion PCLD 788 KI PCLD 788 PCLD 788 Board ADDR 0 ADDR 1 ADDR 2 Fig 2 4 1 2 5 CJC Output PCLD 788 provides cold junction compensation for the thermocouple applications CN4 is for the CJC output Then the data acquisition card can measure the voltage and transfer it to cold junction temperature The formula to calculate temperature is T V 1000 24 4 T Temperature of cold junction V CJC output voltage VRI see Appendix B is used to adjust CJC output If the data of temperat
5. PCLD 788 RELAY MULTIPLEXER BOARD USER S MANUAL COPYRIGHT NOTICE This documentation is copyrighted I990 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements to the products described in this manual at any time vvithout notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use mor for any infringements of rights of third parties which may result from its use ACKNOWLEDGEMENTS PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation Part No 2003788000 Rev A1 Printed in Taiwan Mar 1990 TABLE OF CONTENTS CHAPTER 1 GENERAL INFORMATION Ub Introduction Ga S Gara ae ia e or NO Produ Pesbireg atra ns T S NSpECINCAHONS A u E E I CHAPTER 2 INSTALLATION iia ceo 21 Initial Inspection nare ti io PO CONNECION See SS 2 3 Channel Selection maa e u a m 2 4 Board Address Setting adi i dad oa ZS CJC Output ae a ee mr Saa 216 Power Source Selection aeir cnn en re KA ae se 00 0 DDN UY UL Neee CHAPTER 3 OPERATIONS O sss 11 3 1 Function Description sasana kos n 11 3 2 SipnaliGoanectigp dl os aje ss 12 CHAPTER 4 SOFTWARE PROGR
6. ent Life Expectancy Maximum switch time Isolation Resistance Cold junction compensation Power consumption Connection type Multiplexer control signals Others Dimensions 16 differential channels 3 output terminals 10 VA 100 VDC or Peak AC 0 50A 1 00A 100 million operations at 10 VDC ImA 6 milliseconds including break before make and bounce 100 Mega Ohms 24 4 mV Deg c 0 0V at 0 0 Deg c 5V 380mA Maximum 12V 100mA Maximum 20 pin flat cable connectors Screw terminal 20 5 cm L 11 43 cm W or 8 07 L 4 5 W CHAPTER 2 INSTALLATION 2 1 Initial Inspection Inside the shipping container you should find this operating manual and the PCLD 788 card The PCLD 788 was carefully inspected both mechanically and electrically before shipment It should be free of marks and scratches and in perfect electrical order on receipt When unpacking check the unit for signs of shipping damage damaged box scratches dent etc If there is damage to the unit or it fails to meet specifications notify our service department or your local sales representative immediately Also call the carrier immediately and retain the shipping carton and packing material for the inspection by the carrier We will make arrangements to repair or replace the unit Remove the PCLD 788 interface card from its protective packaging carefully Keep the anti vibration package Whenever you are not using
7. extcolor 1 wo quit textbackground 0 textcolor 7 getch clrscr 1S K DIAGRAM LS dal APPENDIX A BLOC 2 6 G ZAw p LNdNI WeLISId leh KRER SS S R w LNdLNO DL ssssssseesessessasassssesesesasesg ss AAAA AAAA AAAA AAAA AAAA AAAA AAAA OS 2 A AO A Gs ki URA Ae SE qu an A DK Ok O Dk u jD a NO TND TIA a Lndino I inarno 9NI NO eno leo BARBS 929 DON CALLA aal AAA j BBS NR S APPENDIX B CONNECT OR JUMPER AND VR LOCATIONS 19
8. gram PCLD 788 13 Programming a 2 PCLD 788 PCL 860 DVM Card DEMO PROGRAM 3 I combine with PCL 788 example include stdio h include conio h include dos h finclude time h char dvm 5 DVM char volt 11 main FILE fli struct time timep int aly textbackground 1 elrscr gotoxy 20 1 textcolor 1 cprintf gotoxy 10 2 cprintf n if 1 fopen dvm r NULL open DVM driver xi printf Can t open DVM sys n goto quit fprintf fl set 20 v dc set speed 10 wait on hold on n fflush fl range 20v DC gotoxy 10 4 speed 2 5 reading sec textcolor 13 cprint Time Channel 0 Voltage Time Channel 1 Votage n gotoxy 10 5 cprintf textcolor 14 for i 1 i lt 11 i rewind f1 fprintf 1 out lo ONn PCL 788 channel 0 delay 6 je PCL 788 relay responce time 6 ms fprintf f1 trig read valueNn rewind fl fgets volt 10 fl fflush fl gotoxy 12 i 6 gettime amp timep pre d 2 2d4 2d 2d gs i timep ti_hour timep ti_min timep ti_sec volt rewind f1 fprintf fl out lo DA delay 6 14 PCLD 788 Programming fprintf fl trig read valueNn rewind fl fgets volt 10 f1 fflush f1 revind fl gotoxy 44 i 6 gettime amp timep eprint Sd t 2d 8 8 2d 8 2d s i timep ti hour timep ti min timep ti sec volt y gotoxy 10 2 t
9. rnal power input is used when not using PC power The jumper JP1 needs position as following Using PC power PC EXT Using External power PC PC EXT o e Ea Fig 2 2 2 Installation PCLD 788 Fig 2 2 3 OTIHOTIH INDI No TNO SNO OIH OTIHONIH On GH TA LNS END ENO tar 2n N 294 0 19d Installation y PCLD 788 2 3 Channel Selection PCLD 788 has 16 input channels CN1 One of sixteen channels will be chosen according to CN2 CN3 bit CO to bit C3 Following is the relation of bit C3 to bit CO and channel selected Bit 3 Bit 2 Bit 1 Bit 0 Channel ran O O co 1 O n gt N gt O t ti t tt ta ti mm mee ee eee tr tz t m t tt t t ta tr t ta tata tata Meteo ta t tx t eee e _ tr t t t ES ta Z tt tt m m tt a Per CESTO The bit 0 to bit 3 signals are controlled by Digital Output of Data Acquisition Board and determine the channel to be closed 2 4 Board Address Setting PCLD 788 has 16 channels and can expand up to 256 channels so the maximum expansion can use up to 16 PCLD 788 boards and each board has its own address The DIP Switch SW1 is used to select PCLD 788 board address The address format is as following PCLD 788 Switch Position SW1 1 2 3 4 ADDR ON ON ON ON 0 ON ON ON OFF g ON ON OFF ON z ON ON OFF OFF 3 ON OFF ON ON 4 ON OFF ON OFF 5 ON OFF OFF ON 6 ON OF
10. ure is not correct VRI needs to be adjusted to get the correct temperature data 2 6 Power Source Selection PCLD 788 requires both 12V and S5V power supply The connector 2 pin 19 and 20 are used for power supply connection Since the PC offers 5V and 12V power supply the PCLD 788 can be powered directly from the PC I O bus by connecting the PCLD 788 with the PCL 718 711 and 812 Please refer to each product s PCLD 788 fo Installation connector pin assignment for proper connections PCLD 788 can also use external power source The CN8 is the power input connector and the jumper JP1 selects the power source PC or External to be used The 12V power input is converted by a DC DC converter to generate 15V DC outputs This device greatly reduce the input power noise and offer stable output of CJC compensation CHAPTER 3 OPERATIONS 3 1 Function Description PCLD 788 is a Relay Multiplexer Board which can be used to select one of sixteen input channels to output When the multiplexer changes from channel A to channel B see Fig 3 1 1 3 milliseconds break before make and 6 milliseconds channel not close will occur at this moment CNS is a connector which offers channel close and channel not close signals output The timing sequence is shown as following Fig 3 1 1 Break Before Make Timing Diagram Channel control C3 CO Ch A addr X Ch B addr Ch A relay control Oe Start to open Ch A
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