TDR Pattern Register User Manual
Contents
1. 31 30 29 28 27 to 16 15to 0 1 1 0 0 Data Source Ident Pattern data 31 to 28 27 to 0 0 Time Stamp 27 0 Other Information 31 30 29 to 24 23 to 20 19 to 0 1 0 Module Number Information Information Field Code 31 to 28 27 to 0 0 Time Stamp 27 0 The Module number identifies the source of the information The Information codes used in the Pattern Register are as follows Information Type Code Information Field Definition Undefined Data 0 Pause Timestamp Timestamp bits 47 28 2 Resume Timestamp 3 Timestamp bits 47 28 SYNC100 Timestamp 4 Timestamp bits 47 28 3 Setting Up a VME Address Jumpers Refer to the picture of the module shown in Appendix A The VME address jumpers are in two eight jumper blocks at the middle of the top of the pcb The address of location 0 of the module address space is specified by placing or not shorting links ion the jumpers Placing a shorting link on a jumper will select that address bit to be seen as a logic 0 For example to select address 0x 80000000 for the base address shorting links should be placed on every jumper except the one for A31 This is the jumper at the left most end of the row as indicated by the white writing b Input Selection Each of the 32 inputs can be selected to interface to signals of one of three types Fast NIM Differential ECL and Single ended ECL The following jumper diagrams show how to select ea2. A AND B Group A input only 12 Single Stretched A AND B AND GateA Group A input only 13 Single Stretched A AND B Group A input only a Single Input mode In this mode each input operates alone Each input must be enabled via the MIDAS interface The Group Gate input can be selected to be ANDed with the inputs This selection operates for the whole of a group b Gated Group The front edge of the Group Gate input will latch the master 100MHz counter and all inputs which are active at any time during the Group Gate will be included in the pattern The Group Gate input is a Fast NIM signal c GroupA AND GroupB or Using the TDR Pattern Register for providing timed suppression data The purpose is to combine the VETO signal from the Eurogam Phase 1 BGO detectors and electronics with a Ge CFD to give a timestamped data item indicating the co incidence of the two signals The Pattern Register 32 inputs are allocated as two groups of 16 Group B is used for the Single Ended ECL VETO signals from the BGO electronics and Group A is used for the Fast NIM Ge CFDs from the LeCroy CFD modules The Ge CFD signals are stretched in the Pattern Register to align them with the slower VETO signals Fig 1 shows when the timestamped Item is generated for a single CFD and VETO It should be noted that a timestamped Item will be generated for every coincidence between the VETO and CFD Fig 2 shows how this can occur during multiple VETOs
3. ojojo oo en o o s JPBOUp74e ooi ojoo 5i RT724188 oo O08 SPT P82 zsp7a Sj DER cad o o o goo EE ANO o o 188575 ojo 05 0 0 00 0000 Q ot 1eup5s gy pua tns 900 JPS4 pa NBT o o o heres ojo on e ar ES o o 3 o oj S od O o ooo 0 0 00 ei PS6 JPS7 R131RZ5JPSB lar o o O oo o ojojo 0 5 mune 9 9 E 72 08 2 9 0 9 9 9 o o mem B Bar Ke O oo oo gl hast o o CREB 00000000000000000 90000000000000000 prssrisa oo O o8 at ti JPS1JP62c 8197 R134JP52 ps3 00000000 19a oo s oo glo oloJo o a ee CREFBI go gt 00000900 DC DC2 o miS aea oooo oooon o PCAP2 R29 28 TS_RG_CAP2 4 i kis m RIS zs 00000000 0239 c2so C235 WE SET Foie oooooon ooooooo A Lin R39 oo0o0000000 cose oooooooooo oooon HORT 00000 me pz S ea t Dome o c36 Ja asn o Tia t u26 M i 9 dj me Ogee Qoo cet o i o t MEE 1 o Lo R255 o e Lo nad ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo 4 ooo ooo ooo
4. 0 select the pulse stretch value in steps of 5Ons value 200 Group B input Bits 15 gt 0 enable an input when set enable 204 Group B Invert Bits 15 gt 0 invert the logic of the input bit when set 208 Group B mode Selects registered free free amp Gate mode 300 Inspection Line 0 Selects the signal source 304 Inspection Line 1 Selects the signal source 308 Inspection Line 2 Selects the signal source 30C Inspection Line 3 Selects the signal source 400 Input Chip control 0 Reset input FIFOs 1 Count Enable 1 Enable Time stamp counter 2 SYNC error reset 3 SYNC to Error STARY connect 4 No effect but registered 5 Run Enable 1 Enable input of SYNC and Data to the FIFOs 6 gt 15 registered data but no action 16 gt 31 always return 0 404 Input Status Timestamp errors and others NYI 500 Time FIFO LS 0 gt 31 Time stamp bits 0 gt 31 504 Time FIFO MS 0 gt 15 Timestamp bits 32 gt 47 16 gt 31 0 508 Time FIFO word 0 gt 8 Number of words in the Timestamp FIFO count 50C 510 Group A fifo data 0 gt 15 Group A Pattern 16 gt 31 0 514 518 Group A fifo word 0 gt 8 Number of words in the Group A FIFO count 16 gt 31 0 51C 520 Group B fifo data 0 gt 15 Group B Pattern 16 gt 31 0 524 528 Group B fifo word 0 gt 8 Number of words in the Group B FIFO count 16 gt 31 0 52C 530 Type fifo data 0 gt 7 Event type data 8 gt 31 0 534 538 Type fif
5. EDOC503 The GREAT 32 Channel Peak Sensing ADC User Manual EDOCS504 The GREAT data format EDOCS507 The GREAT TDR system Error recovery and experiment timing EDOCS511 Metronome User Manual Version6 C1100 P J Coleman Smith dl ac uk 2 GREAT 14 1 2004 2 Function The function of the module is carried out by two Altera FPGA devices programmed at power up from serial EPROMs There is an LED for each FPGA which is lit when the programming has completed successfully The user of the module must decide the interface type for each of the 16 inputs in the two Groups The jumpers must then be set accordingly Refer to section 3 b and appendix A for setting the different interface choices The inputs to be registered are chosen by using the MIDAS interface window See appendix C for an example of the window for the Pattern Register The sense of each input can be inverted controlled via MIDAS prior to being applied to the Register timestamp logic This allows the user to decide which edge of the input signal causes the timestamp It is always the rising edge of the input that is timestamped As mentioned in the introduction each group operates in one of two modes The mode must be selected via the MIDAS interface To operate the module must be connected to a TDR Metronome output or a similar source of 100Mhz and SYNC pulses a Block Diagram The block diagram shows the path of data from input signal to SHARC output 32 sig
6. P J Coleman Smith dl ac uk 6 GREAT 14 1 2004 Delayed BGO VETO Stretched Ge CFD Item Generated Fig 1 Single CFD Aligned with VETO Delayed BGO VETO L TL Stretched Ge CFD EE Item Generated i Fig 2 Multiple VETOs align with one CFD When setting up for an experiment it will be necessary to check the alignment of the Ge CFD and VETO signals as well as the width of the CFD Logic Inspection Lines are provided in each Pattern Register for this job The width of the CFD output pulse will also affect the number of co incidences 5 Software Interface Access to the registers on the Pattern Register are via the VME bus interface using A32 D32 commands The registers are defined in the table in Appendix E at the end of this document For further information about register function contact the author via email The normal method of control is via the MIDAS control window The module should be initialized after power up with registers set as follows 6 Front Panel Interface The front panel layout is shown in a diagram in Appendix B The connections are detailed in the following Tables SHARC Link Pin Function Source 1 Clock Pattern Register 2 Acknowledge VME Processor 3 GND 4 Data 0 Pattern Register 3 Data 1 Pattern Register 6 Data 2 Pattern Register 7 Data 3 Pattern Register 8 GND P J Coleman Smith dl ac uk T GREAT Group Inputs A B Dif
7. Interrupt Select 0 gt 3 Select Interrupt source 0 Lost Track 1 FIFO half full 2 gt 15 not defined 4 Method 0 Edge triggered 1 Level Triggered 5 Edge 0 Rising edge falling edge 6 Level 0 High Level 1 Low level 7 Enable 0 Disabled 1 Enabled 8 gt 15 registered data but no action 16 gt 31 always return 0 10 Read FIFO 0 gt 31 FIFO output data 14 Read Tracking 0 gt 3 Readout track Counter Registers 4 gt 7 Track number from FIFO 8 gt 11 ID track number from last ID word 12 gt 15 Track number from last Time stamp 16 gt 31 0 18 FIFO Flags All these flags are active low 0 Almost full 7 spaces remaining 1 Almost empty 7 words written 2 Half full 131 072 words written 3 Empty 4 Full 262 144 words written 52 231 0 IC Spare Bus 0 gt 31 VME chip end of Spare connections between the two Alteras 100 Group A input Bits 15 gt 0 enable an input when set enable P J Coleman Smith dl ac uk 11 GREAT 14 1 2004 104 Group A Invert Bits 15 gt 0 invert the logic of the input bit when set 108 Group A mode Selects registered free free amp Gate mode 0 Free Transition Mode 1 enabled 1 Registered Mode 1 enabled 2 AND mode CFD VETO 1 enabled 3 Stretch input pulses 1 enabled 110 Group A Stretch Bits 3 gt
8. The operation of the module is handled by the MIDAS interface and would normally only require the user to select the inputs their polarity and the Group Modes If the module is to be operated in an environment not controlled by MIDAS then a much deeper understanding of the module function is required than is covered in this version of the user manual Contact the author for help To operate within the MIDAS environment the module must be configured in the VME address space and the correct Group Interface jumper settings selected for the inputs The module is entered in the VME configuration table accessed via the VME control window This allows the MIDAS to set up and control the module With the SHARC link connected to the TDR Collator processor and the Metronome interface connected the module will be set up by the MIDAS with initial values in all the registers and valid entries for the module readout identifiers Use the Experiment Control window Setup and Go buttons The mode of operation of the two groups of inputs is controlled by menu selection in the MIDAS interface The table below gives the valid modes A refers to the input number within the group A P J Coleman Smith dl ac uk 5 GREAT 14 1 2004 Value Mode name Comment 0 Single input A B AND Gate A B 1 Single input A B 2 Gated Group 4 Single A AND B AND GateA Group A input only 5 Single A AND B Group A input only 6 Gated Group
9. GREAT 14 1 2004 TDR Pattern Register User Manual Contents 1 Introduction 2 Function a Block Diagram b VME interface specification c SHARC interface data format 3 Setting up a VME Address Jumpers b Input selection 4 Operation a Single input mode b Gated Group c GroupA AND GroupB Software Interface Front Panel Interface Logic Inspection Signal examples What can stop the module working or Error management 9o Qv tA Appendices A Layout of the PCB with Jumper locations B Front Panel Layout C MIDAS control window Refers to pcb 25 9275A P J Coleman Smith dl ac uk 1 GREAT 14 1 2004 1 Introduction The Pattern Register is a single width VME module designed to operate in the GREAT TDR environment There are two groups of 16 inputs A and B The purpose of the module is to register the changes on the inputs and send a timestamped 16 bit pattern to the Data Acquisition system via a SHARC link The timestamp refers to the selected edge of the input The two groups can be set to one of three specific digital interface types Fast NIM Differential ECL and Single ended ECL The Pattern input is operated as two Groups each in one of three operating modes All the pattern inputs are AND ed with a programmable mask bit which allows individual bits to be disabled for example where one input is firing in noise GroupA can be pulse stretched under computer control l Gated Group The front edg
10. al 96 Sharc data2 97 Sharc data3 98 9f NYI AO Fifo pafn FIFO programmable almost full Al Fifo paen FIFO programmable almost empty A2 Fifo hfn FIFO Half empty A3 Fifo ffn FIFO full A4 Fifo efn FIFO empty A5 Fifo erclk Fifo erclk A6 Fifo erenn Fifo erenn A7 Fifo rclk Fifo read clock A8 Fifo rcsn Fifo read chip select A9 Fifo renn Fifo read enable Aa Fifo oen Fifo output enable Ab Fifo prsn Fifo partial reset Ac Fifo mrsn Fifo master reset Ad Fifo ready Fifo data has been read and is ready for use Ae Fifo rdreq Request from sharc software for a fifo read Af Vme req Request from vme for a read of fifo data BO Lost track Output of the track comparison system P J Coleman Smith dl ac uk
11. ch of the possible types Differential ECL does not require a specific reference voltage selected but the Fast NIM and Single Ended ECL do P J Coleman Smith dl ac uk 4 GREAT 14 1 2004 It is important to note that all the inputs for a group should be set to the same interface type Failure to do this will result in incorrect reference voltages being used and unpredictable register operation S g 2 zog m JP85 E 5 E wn olo olo o Top of Board 1 Differential ECL 1O OU Group A O OO OJo O o Single Ended ECL a did Group B O ollo o o s z Fast NIM 2 O O d Input Selection Jumper Positions Voltage Reference selection When connecting to the front panel inputs use the following signal allocations with the 34 pin IDC connectors Input 0 in Differential ECL mode pinl is the ve input and pin 2 the ve This carries on through the connector with Input 15 on pin 31 for ve and pin 32 for ve Pins 33 and 34 are not connected on both Group A and B input connectors Input 0 in Fast NIM and Single Ended ECL mode pinl is the Signal input and pin 2 the GND This carries on through the connector with Input 15 on pin 31 for Signal input and pin 32 for GND Pins 33 and 34 are not connected on both Group A and B input connectors 4 Operation The mode of operation applies to all the inputs of a Group The mode is selected using the MIDAS interface
12. d FIFO read request signal for the Type FIFO 59 Type FIFO full Flag 5A Type FIFO Flag empty 5B SYNC SYNC pulse from the Metronome 5C STARX STARX Reset from the Metronome 5D Out of step Internal FIFOs are out of step 5E Ext FIFO write FIFO Write clock to the external FIFO clock SF Ext FIFO write FIFO Write request to the external FIFO 60 Ext FIFO almost Flag active low full 6l Ext FIFO full Flag active low 62 Group A Hit Group A Pattern hit 63 Group A End Group A Gated mode End signal 70 gt 7F Group A The Stretched inputs for Group A stretched 0 gt 15 80 Loadreg Load signal enables registers when selected to load data 8l Chip select Active to select vme access to the input chip 82 Asn VME address strobe 83 DSOn VME Data strobe 0 84 DS1n VME Data strobe 1 85 86 DTACK VME data acknowledge 87 STARX 88 Iackn VME Interrupt acknowledge cycle identifier 89 Irgl Interrupt line 8a Irq2 Interrupt line 8b Irq3 Interrupt line 8c Irq4 Interrupt line P J Coleman Smith dl ac uk 14 GREAT 14 1 2004 8d Irq5 Interrupt line 8e Irq6 Interrupt line 8f Irq7 Interrupt line 90 Iackinn Interrupt cycle chain token in 9 Iackoutn Interrupt cycle chain token out 92 Sharc clock SHARC bus clock pulses 93 Sharc ack SHARC bus acknowledge 94 Sharc dataO SHARC data bit 95 Sharc dat
13. e of the Group Gate input will latch the master 100MHz counter and all inputs which are active at any time during the Group Gate will be included in the pattern The pattern and timestamp is output at the end of the Gate 2 Individual inputs a The 16 pattern inputs of the Group are individually sampled on every clock Those that became active since the previous clock generate a timestamp along with a label to say which of the 16 inputs caused the timestamp b In this mode the user may choose under computer control to AND the input with the Group Gate c GroupA AND GroupB This mode uses the GroupA and GroupB inputs to provide 16 bits of co incidence pattern A timestamp is generated when the input from GroupA AND GroupB are true to gether The Timestamp is based on a counter incremented by a 100Mhz clock and kept in synchronism with the rest of the TDR system by the SYNC pulse provided by the GREAT TDR system Metronome module The Pattern Register is designed to operate at an average input rate of 10Khz per input The maximum burst rate into one input is 10Mhz The minimum input pulse width for reliable operation is 50ns however much smaller input pulses can be registered The following documents will help in understanding the terms discussed in this manual They can be found at the Nuclear Physics Group web site http npg dl ac uk EDOC502 The GREAT Triggerless Total Data Readout Method IEEE TNS VOL 48 NO 3 JUNE 2001
14. ferential ECL Interface Pin Function Pin Function 1 Input 0 ve 2 Input 0 ve Input 1 ve 4 Input 1 ve 31 Input 15 ve 31 Input 15 ve 33 No Connection 34 No Connection Group Inputs A B Single Ended ECL Interface Pin Function Pin Function 1 Input 0 2 Ground Input 1 4 Ground 31 Input 15 31 Ground 33 No Connection 34 No Connection Group Inputs A B Fast NIM Interface Pin Function Pin Function 1 Input 0 2 Ground Input 1 4 Ground 31 Input 15 31 Ground 33 No Connection 34 No Connection 7 Logic Inspection Signal examples 14 1 2004 During normal use of the module the inputs and Gate signals are the most likely to be required The examples show which edge of the signal as seen through the Inspection Lines generates the Timestamp 8 What can stop the module working or Error management 1 Lost Track Refer to the block diagram in section 2 a There is a FIFO between the timestamping input stage and the formatting and SHARC link stage The data is placed into the FIFO with a four bit count to keep track of the data through the FIFO If the data coming through the FIFO is not in step then the module will stop working the Lost Track LED will light and the relevant bit is set in the status register The operation of the module is re started by a system STOP SETUP GO action 2 Using the wrong edge of the input for timin
15. g P J Coleman Smith dl ac uk GREAT 3 Appendix A Jumper Layout VME Address Jumpers 14 1 2004 102 0000 VME Address Selection Jumper in Address Bit A31 A24 A23 A16 RRE HHE o0000000j3 oo0o00000 F csH4 0000 lbs 0000000090 HOR ooooooooQj Xie o oooon ooooo 90000000 Nn 60000 oo JP97 TRST control JP1 18 00000000 oooooon 0000000 o no CVTERMI CREFAT 9 oo amp o PEN CK ES 00 0000 Lect oo az Ke arg RS ane naa R97 JP O Ore Lear ol 34 JP26 oo 5 00000000 ojojo o ool o n sj R09 Jp27Jp7e 79 fos Evar ol o O oo oo Fl E oo n PTB Jp 1 32110 R82 JP dar oo oo lo ojojo o ssinen oo Sup2os 555 868 JPIB P19 ES o O o o S O o o o o 5 Input type Jumpers o R71 RSG JPTO JPT cu QO 09009900 ziar o ol o PTB are Ron jojo o o o 3 o oi 0000000000000000 RPA 4o RAG o00000000000000000 J e oo PA JPS ol di ool oc R Voltage Reference oes PRI IP86 PS3 Pgs 2 3200 00 o O s Si oo Selection A g 99 ul ooe JPBB Joa 6dr
16. n 0 gt IF Disconnected Allows other units to drive the line 20 gt 2F Group A inputs Input monitors for Group A 0 2 15 30 gt 3F Group B inputs Input monitors for Group B 02 15 40 Group B Hit Group B Pattern hit 41 Group B End Group B Gated mode End signal 42 Gate A Group A Gate input 43 Gate B Group B Gate input 44 Sync pulse Sync detected 10nS pulse 45 Sync error Sync error flag 46 Aneb Output of Timestamp sync comparator 47 Re load window Window after SYNC pulse during which a re load can occur 48 Load stamp Re load pulse Loads the new value into the Timestamp counter 49 Load Enable Indicates a re load has been programmed 4A Time FIFO read FIFO read request signal for the Timestamp FIFO 4B Time FIFO full Flag 4C Time FIFO Flag empty 4D Group A FIFO FIFO read request signal for the Group A FIFO read 4E Group A FIFO Flag P J Coleman Smith dl ac uk GREAT 14 1 2004 full 4F Group A FIFO Flag empty 50 Group B FIFO FIFO read request signal for the Group B FIFO read 51 Group B FIFO Flag full 52 Group B FIFO Flag empty 53 Time FIFO FIFO write request for the Timestamp FIFO write 54 Group A FIFO FIFO write request for the Group A FIFO write 55 Group B FIFO FIFO write request for the Group B FIFO write 56 Pause Pause signal 57 Resume Resume signal 58 Type FIFO rea
17. nal inputs reg ECL 2 Gate inputs Fast NIM Register S EECLto L Format and TIL Pattern mud pou Fro gt SHARC output i timestamp Link to DAQ conversion 100Mhz clock SYNC 48 bit Timestamp RESET counter ERROR VME output memory Parameter header store Metronome Interface General and specific controls and status Data and address paths VME slave interface GREAT Pattern Register P J Coleman Smith b VME interface specification The Pattern Register is an A32 D32 slave The interface will respond to accesses made using D16 and D08 however they will not return the correct values The Pattern Register occupies 2 bytes in A32 memory space The address of location 0 is specified by jumpers set on the pcb See section 3 a and appendix A for setting the address base P J Coleman Smith dl ac uk 3 GREAT 14 1 2004 c SHARC interface data format The Pattern Register outputs two 32 bit words for every Item An Item can be for an input transition from GroupA or GroupB a SYNC pulse a flow control Pause or a flow control Resume Refer to EDOC504 for more information about the bit allocation of these two words Here is an outline of the Item format extracted from the EDOC Group Pattern Data format
18. o word 0 gt 8 Number of words in the Event type FIFO count 16 gt 31 0 53C 540 Group A Ident 0 gt 31 Ident for Group A pattern 544 Group B Ident 0 gt 31 Ident for Group B pattern 548 SYNC Ident 0 gt 31 Ident for SYNC 54C Pause Ident 0 gt 31 Ident for Pause 550 Resume Ident 0 gt 31 Ident for Resume 554 Undefined Ident 0 gt 31 Ident for Undefined P J Coleman Smith dl ac uk 12 GREAT 14 1 2004 558 Write to FIFO 0 gt 31 write to FIFO 55C 560 FIFO flags 0 Group A FIFO empty 1 Group A FIFO full 2 Group B FIFO empty 3 Group B FIFO full 4 Control FIFO empty 5 Control FIFO full 6 Timestamp FIFO empty 7 Timestamp FIFO full 8 External FIFO almost full 9 External FIFO full 10 gt 31 0 600 Load Timestamp Load a new value into the Timestamp counter for loading at a re sync SYNC pulse 0 gt 31 Data for new Timestamp 16 gt 47 value A write to this register sets the Re_SYNC enable 700 Spare bus read 0 gt 31 Input chip end of Spare connections between the two Alteras Appendix F Logic Inspection Line signal selection Logic Inspection Line Signal selection This information is provided for completeness it is not intended for a user to need to view the majority of these signals Code Signal Name Descriptio
19. ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo ooo Outline of the Pattern Register for location of Jumpers P J Coleman Smith dl a c uk GREAT 14 1 2004 Appendix B Front Panel Layout Pattern Register SHARC O CUT OUT O pa 9 a a 3 z z Q va CUT OUT Q Group A 15 pucr CUT OUT Q Group B 15 Metronome C C L R C Front Panel for 25 9275 All Dimensions in mm All hole sizes are for finished size P J Coleman Smith dl ac uk 10 GREAT 14 1 2004 Appendix C MIDAS control window Appendix D Logic Inspection signal examples Appendix E Software Register definitions Register definitions Address offset Name Function Hexadecimal 0 Module Control 0 ignore track 1 Ignore the tracking data when reading FIFO 1 SHARC enable 1 Enable SHARC link readout of the FIFO 2 Reset FIFO 3 STARX enable 1 Enable STARX to reset FIFO 4 Soft Reset input chip 5 gt 15 registered data but no action 16 gt 31 always return 0 4 Module Status 0 interrupt 1 lost track 2 FIFO Half full 3 gt 31 Always return 0 8 Interrupt Control 0 gt 7 Interrupt vector 8 2 10 Select IRQ line to drive on VME bus 11 gt 15 registered data but no action 16 gt 31 always return 0 C
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