Home

20A020-00 E1 User Manual - University of Manchester

Contents

1. 23 2519 BOO baci o ober mee Prid eben eom bao d us 23 De EEPROM SL LS Galo Pasado 23 2 8 Mass StOFABes e rA ERR ERE P 24 2 8 1 Parallel IDE PATA 24 262 SeHnalADA SATA UAE 04 10 28 2 9 31 2 9 4 Connection vla VOS is ves duas eie dcn doas b e ewes 21 2 10 USB Interfaces tans 32 2 101 ProntsPanel Connection serv ua uu puas aeta 32 2 10 2 Rearl O e e Rye 32 Bthernet ac mon 4 etm b at on baee sepes 33 LILI Pront ConmecltOb uiua bansa apan u saq bans 33 2 12 U ART Interface 34 2 135 AMC S OUS iu den Ded d aue ie ee pi pt sena 35 ZAZA REIR eren es 35 2 13 2 Installing an Mezzanine 40 DAA durada bud 41 2 14 1 Installing PMC Mezzanine 42 2 15 PCOLExXpISSSQ TERI ERE TERRE RE EUR aden oS agua 43 2 15 1 General ERR RE ee 43 2 15 2 Implementation on the A20 43 2 16 VMEbus Interface i nhe m t RR ganas meee maqa 44 MEN Mikro E
2. Mezzanine Module Perform the following steps to install an XMC module Power down your system and remove the A20 from the system Remove the filler panel from the board s front XMC slot if installed The XMC module is plugged on the A20 with the component sides of the PCBs facing each other Put the module s front connector through the A20 s front slot at a 45 angle Carefully put it down making sure that the connectors are properly aligned Press the XMC module firmly onto the A20 Make sure that the gasket around the XMC front panel is properly in its place Screw the XMC module tightly to the A20 using the two mounting standoffs and four matching oval head cross recessed screws of type M2 5x6 Figure 2 Installing an XMC mezzanine module XMC module Mounting standoff 114 pin connector CPU board A A 2 M2 5x6 oval 2 M2 5x6 oval head cross head cross recessed screws recessed screws MEN Mikro Elektronik GmbH 40 20A020 00 E1 2008 12 08 Functional Description 2 14 PMC Slots The A20 board provides one or two PMC X slots for extension such as graphics Fast Ethernet etc The signaling voltage is set to 3 3V i the CPU board has a 3 3V voltage key see Figure 3 Installing a PMC mezzanine module on page 42 and can only carry PMC mezzanines that support this keying configuration Mezzanine cards may be designed to accept either or bo
3. On the A20 the Gigabit Ethernet channel is permanently connected via one PCIe x1 link Another three x1 links are used for the connection of the and one x1 link is available for the via a PCI Express to PCI X bridge The sixth x1 link is used for connection of the Tundra PCI to VMEbus bridge MEN Mikro Elektronik GmbH 43 20A020 00 E1 2008 12 08 Functional Description 2 16 VMEbus Interface 2 16 1 General The A20 s VMEbus interface conforms to the VME64 specification It uses the Tundra 51148 controller as a PCI to VMEbus bridge The Tundra TSI148 is currently the highest bandwidth bridge available providing PCI X to VME 2eSST performance levels while maintaining backwards compatibility with older standards TSI148 s decoupled architecture and proper buffer sizing allows a very large number of simultaneous transactions to take place TSI148 is also a full featured master slave and system controller which allows it to be used in any VME application Main features e Supports VME32 VME64 2eVME and 2eSST 1 5 Slot 1 function with auto detection e Master D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT RMW Slave D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT DMA Mailbox functionality Bus timer Location Monitor Interrupter D08 O I 7 1 ROAK Interrupt handler D08 O IH 7 1 Single level 3 fair requester Single level 3 arbiter Low power consumption Since the Tundra TSI148 c
4. USB 2 0 seven ports PMC rear I O for one PMC One SATA channel Mezzanine Slot Two slots usable for PMC or XMC XMC slots Compliant with XMC standard VITA 42 3 2006 Two x1 PCI Express links for slot 2 One x1 PCI Express link for slot 1 PMC slots Compliant with PMC standard IEEE 1386 1 PCI PCI X 32 64 33 66MHz 3 3V V I O One x1 PCI Express link via PCI Express to PCI X bridge PMC I O module PIM support for PMC Current limited to 2A for 5V and 3 3V MEN Mikro Elektronik GmbH 4 20A020 00 E1 2008 12 08 Technical Data Miscellaneous Board controller Real time clock buffered by a GoldCap and a battery Watchdog timer Temperature measurement One user LED Reset button PCI Express amp One xl link to connect local 1000Base T Ethernet controller Three x1 links to connect XMC One xl link to connect via PCI Express to PCI X bridge One x1 link to connect the Tundra VME bridge via a PCI Express to PCI X bridge Data rate up to 250MB s in each direction 2 5 Gbits s per lane VMEbus Tundra TSI148 controller Compliant with VME64 Specification Supports VME32 VME64 2eVME and 2eSST VITA 1 5 Maximum data rate 250 MB s limited by PCI Express link Slot 1 function with auto detection Master D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT RMW Slave D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT DMA Mailbox functional
5. 0 0061 1 byte Standard speaker sound 0x 0070 0073 4 bytes Real time clock 0x 0081 0083 3 bytes DMA controller 0x 0087 0087 1 byte DMA controller 0x 0089 008B 3 bytes DMA controller 0x 008F 0091 3 bytes DMA controller 00A0 00A1 2 bytes Interrupt controller Ox 00C0 00DF 32 bytes DMA controller 00F0 00FF 16 bytes Math coprocessor Ox 0170 0177 8 bytes ICH7 IDE controller 01 0 01 7 8 bytes ICH7 IDE controller 0279 0279 1 byte Plug n Play 0376 0377 2 bytes ICH7 IDE controller 03B0 03BB 12 bytes 945GME express chipset 03C0 03DF 32 bytes 945GME express chipset 03F6 03F6 1 byte ICH7 IDE controller 0400 04BF 192 bytes PCI bus 0400 0401 2 bytes PCI bus 0x 0500 051F 32 bytes ICH7 SMBus controller Ox 0A79 0A79 1 byte Plug n Play OCF8 0CFF 8 bytes PCI Subsystem PCI bus Ox B000 BFFF 4096 bytes ICH7 PCI Express Root Port C000 CFFF 4096 bytes ICH7 PCI Express Root Port D000 DFFF 4096 bytes ICH7 PCI Express Root Port E000 EFFF 4096 bytes Hub interface to PCI bridge Ox FA00 FAOF 16 bytes ICH7 IDE controller 32 bytes ICH7 USB UHCI controller 32 bytes ICH7 USB UHCI controller FDOO FDIF 32 bytes ICH7 USB UHCI controller FEOO FEI1F 32 bytes ICH7 USB UHCI controller Ox FF00 FF07 8 bytes 945GME express chipset MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Organization
6. 16 GND GND GND GND 17 u 18 GND GND GND GND 19 IREFCLKEp REFCLKEn MEN Mikro Elektronik GmbH 38 20A020 00 E1 2008 12 08 Functional Description Table 15 Signal mnemonics of 114 pin XMC connector Signal Direction Function Power 12 12V out 12 supply voltage 3 3V out 3 3V supply voltage 5V VPWR out 5V supply voltage GND Ground PCI PER2p n 0 out PCI Express link 2 lane O differential Express receive Link2 PET2p n 0 in PCI Express link 2 lane 0 differential transmit REFCLKEp n out Differential reference clock link 2 ROOTO out Root Complex enabling WAKE out Reactivation of power rails and refer ence clocks PCI PER8p n 0 out PCI Express link 3 lane 0 differential Express receive Link3 pET3p n o in PCI Express link 3 lane 0 differential transmit REFCLKCp n out Differential reference clock link 3 PCI PER4p n 0 out PCI Express link 4 lane O differential Express receive Link 4 in PCI Express link 4 lane 0 differential transmit REFCLKAp n out Differential reference clock link 4 Other GA O 2 out I2C channel select MBIST in XMC built in self test MRSTI out XMC reset in MSCL out SMBus clock MSDA in out SMBus data MVMRO out XMC EEPROM write prohibit MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description 2 13 2 Installing an
7. 2008 12 08 About this Document About this Document AN This user manual describes the hardware functions of the board connection of peripheral devices and integration into a system It also provides additional information for special applications and configurations of the board The manual does not include detailed information on individual components data sheets etc A list of literature is given in the appendix History Issue Comments Date of Issue E1 First issue 2008 12 08 Conventions This sign marks important notes or warnings concerning proper functionality of the product described in this document You should read them in any case italics Folder file and function names are printed in italics bold Bold type is used for emphasis monospace A monospaced font type is used for hexadecimal numbers listings C function descriptions or wherever appropriate Hexadecimal numbers are preceded by Ox hyperlink Hyperlinks are printed in blue color globe will show you where hyperlinks lead directly to the Internet so you can look for the latest information online IRQ Signal names followed or preceded by a slash indicate that this signal 18 either active low or that it becomes active at a falling edge in out Signal directions in signal mnemonics tables generally refer to the corresponding board or component in meaning to the board or component out meaning coming fro
8. Signal mnemonics of VMEbus rear I O connector 2 49 Memory map processor VIEW esi seas end md 74 Memory ioca RE sedis ba mdse 75 PCI E 76 SMBUS devices csi eh arr TER UP RARE TI 15 Getting Started 1 Getting Started This chapter gives an overview of the board and some hints for first installation in a system 1 1 Map of the Board Figure 1 Map of the board front panel and top view Battery Holder YT x 5 2 gt gt 3 i USB i ai i 1 Ethernet 5 8 8 i i p Heat Sink gt VGA Compact Flash i Holder MEN Mikro Elektronik GmbH 16 20A020 00 E1 2008 12 08 Getting Started 1 2 Configuring the Hardware You should check your hardware requirements before installing the board in a system since most modifications are difficult or even impossible to do when the board is mounted in a system The following check list gives an overview on what you might want to configure CompactFlash The board is shipped without a CompactFlash card You should check your needs and install a suitable CompactFlash card Refer to Chapter 2 8 1 2 Inserting and Extracting a CompactFlash Card on page 27 for details on the IDE interface or XMC The board offers
9. Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Processor core options OD AQ 2 55 deua sme d dapes 22 Pin assignment of 40 pin IDE ZIF 25 Signal mnemonics of 40 pin 26 Pin assignment of 15 pin HD Sub receptacle connector 31 Signal mnemonics of 15 pin HD Sub VGA connector 31 Pin assignment of USB front panel 0 32 Signal mnemonics of USB front panel connectors 32 Signal mnemonics of Ethernet 10 100 1000Base T connector 33 Pin assignment and status LEDs of 8 pin RJ45 Ethernet 10 100 1000Base T connectors LAN 4 74 e ird rm Ree REX ER 33 Pin assignment of RS232 34 Signal mnemonics of UART 34 Pin assignment of 114 pin connector J15 slot 1 36 Pin assignment of 114 pin connector 125 slot 2 37 Pin assignment of 114 pin connector 26 38 Signal mnemonics of 114 pin connector 39 Pin assignment of VME64 bus connector 46 Pin assignment of VMEbus rear I O connector P2 PMC signals 48
10. directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that MEN was negligent regarding the design or manufacture of the part Unless agreed otherwise the products of MEN Mikro Elektronik are not suited for use in nuclear reactors or for application in medical appliances used for therapeutical purposes Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product ESM ESMini MDIS MDIS4 MENMON M Module M Modules SA Adapter SA Adapters UBox USM and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH is a registered trademark of MEN Micro Inc and SBS Technologies Inc MEN Mikro Elektronik amp ESMexpress and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH Intel Atom and Intel Core are trademarks of Intel Inc Celeron Intel Pentium and Xeon are registered trademarks of Intel Inc Microsoft and Windows are registered trademarks of Microsoft Corp Windows Vista is a trademark of Microsoft Corp PCI Express and are registered trademarks of PCI SIG PXI is a trademark of National Instruments Corp QNX is a registered trademark of QNX Ltd CompactFlash is a registered trademark of SanDisk Corp T
11. 0n USB KB WakeUp From 53 54 Disabled Reload Global Timer Events Primary IDE 0 Disabled Primary IDE 1 Disabled Secondary IDE 0 Disabled Secondary IDE 1 Disabled PCI PIRQLA DJ Disabled HPET Support Enabled HPET Mode 32 bit mode Fb Previous Values F6 Fail Safe Defaults F Optimized Defaults Power Supply Type Description Selects the type of power supply Options AT ATX ACPI Function Description Enables disables support of Advance Configuration and Power Interface Options Enabled Disabled ACPI Suspend Type Description Selects the ACPI state used for System Suspend Options 51 8 Activates Power On Suspend function S3 STR Activates Suspend To RAM function S1 amp S3 Activates both S1 POS and S3 STR MEN Mikro ElektronikGmbH 65 20A020 00 E1 2008 12 08 BIOS Run VGABIOS if S3 Resume Description Selects whether to run VGA BIOS if resuming from 53 state This is only necessary for older VGA drivers Only selectable if Sus pend Type is set to S3 STR 51853 Options Auto Yes No Power Management Description Selects the type of power saving management modes Options User Define Set each mode individually Select time out peri ods in the section for each mode Min Saving Minimum power savings Inactivity period is 1 hour in each mode except the hard drive Max Saving Maximum power savings Inactivity period is 1 m
12. Elektronik GmbH 20A020 00 E1 2008 12 08 Sets the maximum TLP payload size for the PCI Express devices The unit is byte 128 512 2048 256 1024 4096 Bitte nites ett este Soe BIOS 3 9 PC Health Status Phoenix AwardBIOS CMOS Setup Utility PC Health Status Shutdown Temperature Item Help Current System Temp 4620 Current 1 Temperature 7226 Menu Level gt CPU FAN 0 RPM Die Digital Temp 6 9 0 7 F5 Previous Values F6 Fail Safe Defaults F Optimized Defaults Shutdown Temperature Description Sets the temperature by which the system automatically shuts down once the threshold temperature is reached This function can help prevent damage to the system that is caused by overheating The operating system reads the temperature according to a method which is determined by the BIOS in ACPI tables The function is supported under ACPI compliant operating systems Options Decimal value from 60 to 120 The default value is 115 The value 120 disables the temperature reading method so that the operating system cannot carry out the shutdown other values are read only values as monitored by the system 3 10 Frequency Voltage Control Phoenix AwardBIOS CMOS Setup Utility Frequency Voltage Control Anca Detect CL CK Disabled Item Help Spread Spectrum Enabled Menu Level gt F5 Previous Values F6 Fail
13. GmbH 83 20A020 00 E1 2008 12 08 You can request the circuit diagrams for the current revision of the product described in this manual by completely filling out and signing the following non disclosure agreement Please send the agreement to MEN by mail We will send you the circuit diagrams along with a copy of the completely signed agreement by return mail 5 MEN reserves the right to refuse sending of confidential information for any reason that MEN may consi mikro elektronik der substantial gmbh n rnberg Non Disclosure Agreement for Circuit Diagrams provided by MEN Mikro Elektronik GmbH between MEN Mikro Elektronik GmbH Neuwieder Stra e 5 7 D 90411 N rnberg Recipient We confirm the following Agreement MEN Recipient Date Date Name Name Function Function Signature Signature MEN Mikro Elektronik GmbH Neuwieder Strafe 5 7 90411 N rnberg Deutschland The following Agreement is valid as of the date of the MEN signature Tel 49 911 99 33 5 0 Fax 49 911 99 33 5 901 E Mail info Non Disclosure Agreement for Circuit Diagrams page 1 of 2 www men de 1 Subject The subject of this Agreement is to protect all information contained in the circuit diagrams of the follo wing product A Article Number filled out by recipient MEN provides the recipient with the circuit diagrams requested through this Agreement only
14. Safe Defaults F Optimized Defaults Auto Detect PCI Description Enables disables auto detection of the PCI clock Options Disabled fixed Spread Spectrum Description Sets the value of the spread spectrum If enabled this setting improves CE behavior Options Disabled Enabled MEN Mikro Elektronik GmbH 72 20A020 00 E1 2008 12 08 BIOS 3 11 Load BIOS Default Values If this option is selected a verified factory setup is loaded On the first BIOS setup configuration this loads safe values for setup which make the board boot up This state is achieved again when the board is reprogrammed with the necessary parameters using the related Flash program 3 12 Load Last Saved Values If this option is selected the BIOS configuration of the last session is loaded 3 13 Set Password This lets you set a password Please note that this often leads to problems since passwords are easily forgotten 3 14 Save amp Exit Setup This option saves the settings made and exits setup 3 15 Exit without Saving This exits setup without saving any settings MEN Mikro Elektronik GmbH 73 20A020 00 E1 2008 12 08 Organization of the Board 4 Organization of the Board To install software on the board or to develop low level software it is essential to be familiar with the board s address and interrupt organization 4 1 Memory Mappings 4 1 1 Processor View of the Memory Map The memory map is allocated dynami
15. ZIP Disabled Boot Other Device Description Selects your boot device priority Options Enabled Disabled LAN Boot ROM Description 1x The option ROM for LAN boot is called once then the boot procedure continues with the normal boot order Endless The option ROM for PXE LAN boot is called until it is suc cessful i e until an operating system is booted over LAN Options Disabled Endless 1x Preboot Execution Environment PXE provides a way for a system to initiate a network connection to various servers prior to loading an OS This network connection supports a number of standard IP protocols such as DHCP and TFTP and can be used for purposes such as software installation and system inventory maintenance MEN Mikro Elektronik GmbH 56 20A020 00 E1 2008 12 08 BIOS Boot Up NumLock Status Description Selects power on state for NumLock Options Off On Security Option Description Selects whether the password is required every time the system boots or only when you enter setup Options Setup System APIC Mode Description APIC mode extends the number of available IRQs up to 23 IRQs for operating systems which can use this Windows XP 2000 Options Enabled Disabled MPS Version Control For OS Description Selects the multiprocessor specification MPS revision Options 1 4 1 1 OS Select For DRAM 64MB Description Select OS2 only if you are running an OS 2 operating system with greater than 64MB
16. beso aa beeen 76 452 SMBUS DEVICES duod dod sua v 44 Interrupt Handling s RR Re 78 S Malfifenance iuda 19 34 Lithium Battery EROS 79 80 6 1 Literature and Web Resources i e sees erret ee me 80 Gd Nom S quoad S Badia 80 DES 80 6 13 Rd dob Bo ea lp Eu at died 80 6 14 USB eA s TEE 80 81 O10 SMC PMG 0 44048 bdo aha aqa aba ear 82 6 1 7 aer hide bue ach 82 6 1 8 isse RR RR 82 6 2 Finding out the Board s Article Number Revision and Serial Number83 MEN Mikro Elektronik GmbH 13 20A020 00 E1 2008 12 08 Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Map of the board front panel and top View 16 Installing an mezzanine 40 Installing a PMC mezzanine module 42 Position of battery on 20 sans euma can e 79 Labels giving the board s article number revision and serial number 83 Tables Table 1 Table 2 Table 3 Table 4
17. connectors for rear I O See Chapter 2 16 VMEbus Interface on page 44 The SATA interface supports transfer rates up to 150 MB s The A20 offers the possibility to connect a SATA hard disk instead of one XMC PMC See Chapter 2 8 2 1 Installing a SATA Hard Disk for further information See Chapter 6 1 8 VMEbus on page 82 for rear I O 2 8 2 1 Installing a SATA Hard Disk MEN provides a mounting kit for easy connection of a SATA hard disk required screws and standoffs are included in the delivery See MEN s website for ordering information Carry out the following steps to install a SATA hard disk on the A20 If the A20 is already installed in a system Power down the system and remove the A20 Remove the XMC PMC if installed Connect the SATA connector and the ribbon cable to the hard disk SATA connector v MEN Mikro Elektronik GmbH 28 20A020 00 E1 2008 12 08 Functional Description Standoff Connect the SATA connector on the hard disk to the SATA connector on the A20 Make sure to match the pins correctly Turn the hard disk around MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description Screw the hard disk to the board using the four screws highlighted in red included in the delivery L Li L L La Reinsert the board into your system MEN Mikro Elektronik GmbH 20 020 00 E1 2008 1
18. for informa mikro elektronik tion gmbh n rnberg 2 Responsibilities of MEN Information in the circuit diagrams has been carefully checked and is believed to be accurate as of the date of release however no responsibility is assumed for inaccuracies MEN will not be liable for any consequential or incidental damages arising from reliance on the accuracy of the circuit diagrams The information contained therein is subject to change without notice 3 Responsibilities of Recipient The recipient obtaining confidential information from MEN because of this Agreement is obliged to pro tect this information The recipient will not pass on the circuit diagrams or parts thereof to third parties neither to individuals nor to companies or other organizations without the written permission by MEN The circuit diagrams may only be passed to employees who need to know their content The recipient protects the confiden tial information obtained through the circuit diagrams in the same way as he protects his own confiden tial information of the same kind 4 Violation of Agreement The recipient is liable for any damage arising from violation of one or several sections of this Agreement MEN has a right to claim damages amounting to the damage caused at least to 100 000 5 Other Agreements MEN reserves the right to pass on its circuit diagrams to other business relations to the extent permitted by the Agreement Neither MEN nor the recipi
19. month year and century Options mm Month dd Day yy Year Time hh mm ss Description Change the internal clock Options MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 hh Hours mm Minutes SS Seconds BIOS IDE Channel 0 1 Master Slave Sub menu IDE HDD Auto Detection Press Enter IDE Channel 0 Master Auto Access Mode Auto Capacity 0 MB Cylinder 0 Head 0 Precomp 0 Landing Zone 0 Sector 0 IDE HDD Auto Detection Description Auto detects the HDD s size head etc on this channel Options None IDE Channel 0 1 Master Slave Options None Manual Auto Access Mode Options CHS Large LBA Auto Capacity Cylinder Head Precomp Landing Zone Sector Options None Base Memory Extended Memory Total Memory Description You cannot change any values in the Memory fields They are only for information MEN Mikro Elektronik GmbH 53 20A020 00 E1 2008 12 08 BIOS Advanced BIOS Features Phoenix AwardBIOS CMOS Setup Utility Advanced BIOS Features Item Help Menu Level gt gt CPU Feature Press Enter gt Hard Disk Boot Priority Press Enter CPU Cache Enabled Quick Power On Self Test Enabled First Boot Device Hard Disk Second Boot Device ZIP100 Third Boot Device 255 Boot Other Device Enabled LAN Boot ROM Disabled Boot Up NumLock Status 0n Security Option Setup APIC Mode Enabled MPS Version Control For OS 1 4 05 Sele
20. of RAM on the system Options Non OS2 OS2 HDD S M A R T Capability Description Enables the hard disk drive SMART capability The Self Monitoring Analysis And Reporting technology monitors the hard disk s condi tion and allows early prediction and warning of the hard disk failing In order to use S M A R T you have to enable it and keep the S M A R T aware hardware monitoring utility running in the back ground all the time Options Disabled Enabled Full Screen LOGO Show Description Reserved to select between boot logos Options Disabled Enabled Summary Screen Show Description Show summary screen Options Enabled Disabled MEN Mikro Elektronik GmbH 57 20A020 00 E1 2008 12 08 BIOS 3 4 Advanced Chipset Features You should make changes in this menu only if you have thorough knowledge of your system Setting wrong values in this section may cause the system to malfunction Phoenix AwardBIOS CMOS Setup Utility Advanced Chipset Features DRAM Timing Selectable CAS Latency Time DRAM RAS to 5 Delay DRAM RASZ Precharge Precharge delay tRAS System Memory Frequency SLP 548 Assertion Width System BIOS Cacheable Video BIOS Cacheable Memory Hole At 15M 16M 5 foo Pei Ire WEA oes PEG Onchip VGA Control On Chip Frame Buffer Size DVMT Mode DVMT FIXED Memory Size Boot Display By SPD Auto Auto Auto Auto Auto 2 2 See Ena
21. select the best available mode Options Auto Mode 1 Mode 3 Mode 0 Mode 2 Mode 4 IDE Primary Secondary Master Slave UDMA Description These fields allow your system to improve disk throughput to 5 with the Ultra DMA 33 feature Options Auto Disabled On Chip Serial ATA Description Selects the function of on chip SATA Options Disabled Disables SATA controller Auto Auto arrange by BIOS Combined Mode PATA and SATA are combined Max of 2 IDE drives in each channel Enhanced Mode Enable both SATA and PATA Max of 6 IDE drives are supported SATA Only SATA is operating in legacy mode SATA Mode Description Selects the on chip SATA mode Only available if On Chip Serial ATA is set to Combined Mode or Enhanced Mode Options IDE IDE mode RAID RAID mode AHCI Advanced Host Controller Interface mode SATA PORT Speed Settings Description Selects the SATA port speed setting Only available if On Chip Serial ATA is set to Enhanced Mode Options Force GEN fixed PATA IDE Mode Description Selects the parallel ATA channel Only available if On Chip Serial ATA is set to Combined Mode and SATA Mode is set to IDE Options Secondary fixed MEN Mikro Elektronik GmbH 62 20A020 00 E1 2008 12 08 BIOS SATA Port Description This feature allows users to view the SATA port as primary or secondary channel Options P0 P2 is fixed Primary Delay for HDD Description This feature allows users to set a hi
22. the data sheets or data books of the semiconductor manufacturer concerned Chapter 6 1 Literature and Web Resources on page 80 2 1 Power Supply The board is supplied via VMEbus with 5V only 3 3V is not connected to the backplane It is possible to power the board with 12V and 12V which may be required by some PMC or XMC modules The CPU operates between 0 85V and 1 3V core voltage depends on CPU type and CPU load The DDR2 SDRAM memory works with 1 8V These voltages are generated on the board The PCI I O voltage is 3 3V 2 2 Board Supervision The A20 provides an intelligent board controller BC The BC supervises 5V and 3 3V and holds the CPU in reset condition until all supply voltages are within their nominal values It has the following main features System watchdog Software reset Voltage monitoring Emergency temperature shutdown at 125 C processor die temperature Error state logging SMBus interface The watchdog device monitors the board on operating system level If enabled the watchdog must be triggered by application software If the trigger is overdue the watchdog initiates a board reset and this way can put the system back into operation when the software hangs The watchdog uses a configurable time interval or is disabled Settings are made through BIOS or via an MEN software driver See also Chapter Onboard Device Sub menu on page 63 In addition an LM63 supervision device is impleme
23. www men de Phone 33 0 450 955 312 Fax 33 0 450 955 211 E mail info men france fr www men france fr Fax 215 542 9577 E mail sales menmicro com www menmicro com MEN Mikro Elektronik GmbH 11 20A020 00 E1 2008 12 08 Contents Contents 1 Getting Started Jl oso eX E I shan PIC eoe ore 16 LI Mapotthe Bod asa d ouo uid otis pma 16 1 2 Configuring the Hardware 0 0 cee eee eee 17 1 3 Integrating the Board into a System 18 1 4 Troubleshooting at 19 15 Conhiguring BIOS te ies ak a 19 1 6 Installing Operating System Software 19 161 Installing Windows 2000 via USB 19 127 Installing Driver 19 2 Functional Description 555 5 4 E EE eee ele 20 21 Power Supply 20 2 2 Board SUpeEvislODos dou seawall age d das 20 2 3 Reset and Power Off Behavior E Tes 2 244 Real Time Clock eR ataq 2 2 5 Processor Cores vk eka canoa 22 2 5 1 Thermal Considetatuons 22 2 6 Bus Str ct te occi eh Ret e bas RUE e akad a 22 2 1 vui qd enc ono idque d Pos rie m n eie 23 2 4 DRAM System Memory
24. 0 20A020 00 E1 2008 12 08 Appendix 6 1 5 Ethernet Ethernet in general The Ethernet A Local Area Network Data Link Layer and Physical Layer Specifications Version 2 0 1982 Digital Equipment Corpora tion Intel Corp Xerox Corp 802 3 1996 Information Technology Telecommunications and Information Exchange between Systems Local and Metropolitan Area Networks Specific Requirements Part 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Phys ical Layer Specifications 1996 IEEE www ieee org www ethermanage com ethernet links to documents describing Ethernet components media the Auto Negotia tion system multi segment configuration guidelines and information on the Eth ernet Configuration Guidelines book www iol unh edu training ethernet html collection of links to Ethernet information including tutorials FAQs and guides ckp made it com ieee8023 html Connectivity Knowledge Platform at Made IT technology information service with lots of general information on Ethernet MEN Mikro Elektronik GmbH 81 20A020 00 E1 2008 12 08 Appendix 6 1 6 XMC PMC XMC PCI Express Protocol Layer Standard VITA 42 3 2006 June 2006 VMEbus International Trade Association www vita com XMC Switched Mezzanine Card Auxiliary Standard VITA 42 0 200x September 2005 Draft 0 29 VMEbus International Trade Association www vita com PMC specificati
25. 17 IACKIN 22 A16 IACKOUT GND 23 A15 GND AM4 24 A14 IRQ7 A7 GND 25 A13 IRQ6 A6 26 A12 IRQ5 A5 GND 27 A11 IRQ4 A4 28 A10 IRQ3 A3 GND 29 A9 IRQ2 A2 30 A8 IRQ1 A1 GND 31 GND 12V 12V 32 5V 5V 5V GND MEN Mikro Elektronik GmbH 46 20A020 00 E1 2008 12 08 Functional Description 2 16 2 2 Rear using VMEbus P2 The standard version of A20 provides VME64 signals and rear I O for as well as seven USB interfaces and a SATA channel The PMC signals are directly connected to connector P2 The following table gives the pin assignment for P2 MEN Mikro Elektronik GmbH 47 20A020 00 E1 2008 12 08 Functional Description C B A Z PMC 1 45V PMC 2 3 4 GND PMC 5 RETRY PMC_6 7 A24 PMC 8 GND PMC 9 A25 PMC 10 PMC 11 26 12 GND PMC 13 A27 PMC 14 15 28 16 GND HH PMC 17 A29 PMC 18 000 19 20 GND 000 21 A31 PMC 22 000 23 GND PMC 24 GND 000 PMC 25 45V PMC 26 Hn PMC 27 D16 PMC 28 GND TH PMC 29 D17 PMC 30 M 31 D18 PMC 32 GND 7 PMC_33 D19 PMC 34 TH 35 D20 PMC 36 GND T PMC 37 D21 PMC 38 000 _39 022 _40 GND 000 41 023 42 000 _43 GND PMC 44 GND 000 000 _45 024 _46 HH 47 025 48 GND 25 49 D26 PMC 50 26 TX PMC 51 D2
26. 2 08 Functional Description 2 9 Graphics The graphics subsystem is part of the Intel 945GME Express Northbridge and supports a 200 250 MHz 256 bit graphics core 2 9 1 Connection via VGA You can connect a VGA monitor directly at the A20 s front panel The pinout of the 15 pin HD Sub connector is standard VGA Connector types e 15 HD Sub receptacle according to DIN41652 MIL C 24308 with thread bolt UNC 4 40 Mating connector 15 HD Sub plug according to DIN41652 MIL C 24308 available for ribbon cable insulation piercing connection hand soldering connection or crimp con nection Table 4 Pin assignment of 15 pin HD Sub VGA receptacle connector 15 SCL 10 GND 5 GND 14 VSYNC 9 4 13 HSYNC 8 GND 3 B 12 SDA 7 GND 2 G 11 6 GND 1 R Table 5 Signal mnemonics of 15 pin HD Sub VGA connector Signal Direction Function GND Ground HSYNC out Horizontal synchronization out Analog monitor interface red green blue SCL out Monitor interface SDA in out VSYNC out Vertical synchronization MEN Mikro ElektronikGmbH os eee ee 3 1 20A020 00 E1 2008 12 08 Functional Description 2 10 USB Interfaces The A20 provides up to eight USB 2 0 ports controlled by the Southbridge One USB interface is routed to standard front panel connectors and seven can be accessed via rear I O The USB interfaces support UHCI 2 10 1 Front Panel Conn
27. 20A020 00 E1 2008 12 08 A20 60 2eSST Intel 2 Duo BC User Manual man mikro elektronik gmbh n rnberg A20 6U VME 2eSST Intel Core 2 Duo SBC A20 6U VME 2eSST Intel Core 2 Duo SBC The A20 60 single slot VMEbus SBC supports a variety of Intel amp Duo and Core 2 Duo processors from the high end 1 5 GHz L7400 to the low voltage dual core versions down to a selection of single core Celeron M types It is designed especially for systems which require high computing and graphics performance and low power consumption in a typical Windows environment under VxWorks Linux Using the new Tundra 151148 bridge controller it provides 2eSST performance levels while maintaining backwards compatibility with older standards such as VME64 and VME32 The standard I O available at the front panel of the A20 includes graphics on a VGA connector one Gigabit Ethernet and one USB 2 0 interface As an option a COM interface on an RJ45 connector can be provided instead of the USB interface As rear I O the A20 provides seven USB interfaces one SATA port and PMC rear I O A second SATA interface for connection of an on board hard disk or for building up RAID systems is provided on board instead of one PMC or XMC One PATA interface supports the on board CompactFlash slot The working memory comprises up to 4 GB DDR2 DRAM which is soldered to guarantee optimum shock and vibration r
28. 7 PMC 52 GND 27 SATAO TX PMC 53 D28 PMC 54 28 LED PMC 55 D29 _56 GND 29 SATAO RX PMC 57 D30 58 30 5 59 031 _60 GND 31 GND PMC 61 GND PMC 62 32 PMC_63 5V PMC_64 GND MEN Mikro Elektronik GmbH 48 20A020 00 E1 2008 12 08 Functional Description Table 18 Signal mnemonics of VMEbus rear connector P2 Signal Direction Function Power 5V 5 power supply GND Digital ground IDE SATAO in Differential pair of SATA receive lines SATA RX port 0 SATAO out Differential pair of SATA transmit lines SATAO TX port 0 SATA out SAIA activity VME64 31 24 in out VME64 address lines D 31 16 in out VME64 data lines RETRY out VME64 retry for postponed data transfer USB USB_D 1 in out Differential pair of USB lines port 1 USB_D 1 0 2 in out Differential pair of USB lines port 2 USB_D 2 USB_D 3 in out Differential pair of USB lines port 3 USB_D 3 USB_D 4 in out Differential pair of USB lines port 4 USB_D 4 USB_D 5 in out Differential pair of USB lines port 5 USB_D 5 USB_D 6 in out Differential pair of USB lines port 6 USB_D 6 USB_D 7 in out Differential pair of USB lines port 7 USB_D 7 USB_OC1 in USB overcurrent port 1 USB_OC2 in USB overcurrent port 2 USB OC3 in USB ove
29. After Boot Enabled Menu Level gt Flow Control Signals Ignore SMI Handler AT F5 Previous Values F6 Fail Safe Defaults F Optimized Defaults Console Redirect Description Enables control via terminal program on serial port Options Enabled default Disabled Serial Port Mode Description Selects the serial port settings Options 9600 8 n 1 19200 8 n 1 115200 8 n 1 default After Boot Description Console Redirect also active after Boot Up Only supported by some OS Options Enabled default Disabled Flow Control Signals Description Enables hardware handshake Ignore means hardware hand shake is disabled Options Ignore default Tested SMI Handler Description To enable or disable SMI Handler at the end of the BIOS POST Options Enabled Disabled MEN Mikro Elektronik GmbH 64 20A020 00 E1 2008 12 08 CENE d PIDEN BIOS 3 7 Power Management Setup Phoenix AwardBIOS CMOS Setup Utility Power Management Setup Power Supply Type Item Help ACPI Function Enabled ACPI Suspend Type S1 P0S 1 Menu Level gt x Run VGABIOS if S3 Resume Auto Power Management User Define Video Off Method DPMS Video Off In Suspend Yes Suspend Type Stop Grant Suspend Mode Disabled HDD Power Down Disabled Soft Off by PWR BTTN Instant Off Energy Lake Function Disabled PWRON After PWR Fail
30. Load BIOS Default Values on page 73 and Chapter 3 12 Load Last Saved Values on page 73 3 1 Main Menu Phoenix AwardBIOS CMOS Setup Utility gt Standard CMOS Features PC Health Status gt Advanced BIOS Features gt Frequency Voltage Control Advanced Chipset Features Load BIOS Default Values gt Integrated Peripherals Load Last Saved Values gt Special Features Set Password gt Power Management Setup Save amp Exit Setup gt PnP PCI Configurations Exit Without Saving see dut o G v Select 5 FIO s Save amp Exit Seuwp The gt character in front of a menu item means that a sub menu is available An x in front of a menu item means that there is a configuration option which needs to be activated through a higher configuration option before being accessible MEN Mikro Elektronik GmbH 51 20A020 00 E1 2008 12 08 Phoenix BIOS Standard CMOS Features Standard CMOS Features AwardBIOS CMOS Setup Utility Date mm dd yy Time hh mm ss IDE Channel IDE Channel IDE Channel IDE Channel 0 Master 0 Slave 1 Master 1 Slave WV OW w Base Memory Extended Memory Total Memory Mon Jan 23 2006 10 957 22 None None None None 640 2086912 2087936 Menu Level gt F5 Previous Values F6 Fail Safe Defaults Date mm dd yy F Optimized Defaults Description Change the day
31. Master UDMA Auto DE Primary Slave UDMA Auto On Chip Secondary PCI IDE Enabled DE Secondary Master Auto DE Secondary Slave PIO Auto DE Secondary Master UDMA Auto DE Secondary Slave UDMA Auto ees 0 Serial ATA STETIT On Chip Serial ATA Auto SATA Mode IDE SATA PORT Speed Settings Disabled PATA IDE Mode Secondary SATA Port PO P2 is Primary Delay for HDD Secs 0 IDE HDD Block Mode Description If your IDE hard drive supports block mode select Enabled for automatic detection of the optimal number of block read writes per sector the drive can support Options Enabled Disabled IDE DMA transfer access Description Enables or disables IDE transfer access Options Enabled Disabled On Chip Primary Secondary PCI IDE Description The integrated peripheral controller contains an IDE interface with support for two IDE channels Select Enabled to activate each channel Options Enabled Disabled MEN Mikro Elektronik GmbH 61 20A020 00 E1 2008 12 08 BIOS IDE Primary Secondary Master Slave PIO Description These fields allow your system hard disk controller to work faster Rather than have the BIOS issue a series of commands that transfer to or from the disk drive PIO Programmed Input Output allows the BIOS to communicate with the controller and CPU directly The system supports five modes numbered from 0 to 4 which primarily differ in timing When Auto is selected the BIOS will
32. WAKE ROOTO MEN Mikro Elektronik GmbH 36 20A020 00 E1 2008 12 08 Functional Description Table 13 Pin assignment of 114 pin XMC connector J25 slot 2 A B C D E F 1 2 PER2nO 3 3 5 2 GND GND F GND GND MRSTI 3 5 3 3V 45V 4 GND GND GND GND MRSTO ABCDEF 5 s 3 3V 45V sess 6 GND GND GND GND 12 OOOOOO 7 3 3V 5V 823823 999000 8 GND GND F GND GND 12V _ Bu EM 10 GND GND GND GND GAO 222288 11 PET2p0 PET2n0 45V EE 12 GND GND 1 GND GND 13 45V 14 GND GA2 GND GND MSDA 15 i 5 5V 16 GND GND MVMRO GND GND MSCL 17 R 18 GND GND GND GND 19 REFCLKCp REFCLKCn i WAKE ROOTO MEN Mikro Elektronik GmbH 37 20A020 00 E1 2008 12 08 Functional Description Table 14 Pin assignment of 114 pin XMC connector J26 A B C D E 1 PER3p0 PER3nO 2 GND GND GND GND 3 5 4 GND GND GND GND ABCDEF 5 5 2 6 GND GND GND GND 000000 000000 7 525225 GND GND GND GND 000000 9 888883 200000 11 PET3nO ESSE GND GND GND GND 000000 000000 13 I I 000000 14 GND GND GND GND 000000 15
33. XD feature flag to always return 0 Options Enabled Disabled Virtualization Technology Description When enabled a VMM can utilize the addional hardware capa bilities provided by Vanderpool Technology Options Enabled Disabled Core Multi Processing Description Enables or disables the core multi processing feature Options Enabled Disabled Hard Disk Boot Priority Sub menu 1 CaO mese CIF 2 Bootable Add in Cards Boot priority Dynamic Description Selects the boot device priority of any hard disk recognized MEN Mikro Elektronik GmbH 55 20A020 00 E1 2008 12 08 BIOS Options Dynamic The BIOS scans the IDE controller and if the con figuration has been changed the priority is reas signed 1 HDD from 1st controller 2 HDD from 2nd controller 3 USB HDD devices Fixed The BIOS uses the stored sequence CPU L1 amp L2 Cache Description Allows to enable or disable the processor cache memory You should disable cache only if absolutely necessary e g for test ing purposes since this slows down the system considerably Options Enabled Disabled Quick Power On Self Test Description Allows the system to skip certain tests while booting This will decrease the time needed to boot the system Options Enabled Disabled First Boot Device Second Boot Device Third Boot Device Description Selects your boot device priority Options LS120 ZIP100 USB CDROM Hard Disk USB FDD LAN CDROM USB
34. as a standard Tundra TSI148 PCI to VME bridge for connection to the VMEbus The bridge uses one PCI Express link from the Southbridge via a PCI Express to PCI bridge 1 The Northbridge is the component of the chip set that is located closely to the CPU for fast data transfer 2 Southbridge is the component of the chip set that connects to PCI devices and controls data exchange with peripherals and other interfaces MEN Mikro Elektronik GmbH 22 20A020 00 E1 2008 12 08 Functional Description 2 7 Memory The standard board versions provide a memory configuration suitable for many applications However memory on the A20 can also be configured for your needs For standard memory sizes and ordering options please see MEN s website 7 2 7 1 DRAM System Memory The board provides up to 4 GB on board soldered DDR2 double data rate SDRAM The memory bus is 2x64 bits wide dual channel and operates at 667 MHz 2 7 2 Boot Flash The A20 has an 8 Mbit SPI Serial Flash implemented as on board Flash for BIOS data 2 7 3 EEPROM The board has a 2 kbit serial EEPROM for factory data MEN Mikro Elektronik GmbH 23 20A020 00 E1 2008 12 08 Functional Description 2 8 Mass Storage 2 8 1 Parallel IDE PATA The parallel IDE PATA interface is controlled by the Southbridge and provides one ATA channel with master and slave support Devices can be operated in PIO mode 0 up to UDMA mode 5 UDMA100 The A20 provides a
35. bled Disabled Disabled Press Enter Auto 8MB DVMT 128MB Item Help Menu Level gt gt F5 Previous Values F6 Fail Safe Defaults F Optimized Defaults DRAM Timing Selectable Description Sets the method by which the DRAM timing is selected If you select By SPD the values for the following five items are configured from the contents of the SPD Serial Presence Detect device It is recommended to use By SPD Options Manual By SPD CAS Latency Time DRAM RAS to CAS Delay DRAM RAS Precharge Precharge delay tRAS System Memory Frequency Description Sets the timing values for DRAM if DRAM Timing Selectable is set to Manual These options should not be changed Options CAS Latency Time DRAM RAS to CAS Delay DRAM RAS Precharge Precharge delay tRAS System Memory Frequency MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Auto 5 4 3 6 Auto 234 5 6 Auto 234 5 6 Auto 45678 9 10 11 12 13 14 15 Auto 583MHz 667 2 BIOS SLP 544 Assertion Width Description Selects the period of time during which the power button must be Options pressed to power off the system This will prevent the system from powering off in case you accidentally hit the power button 4 to 5 Sec 2 to 3 Sec 3 to 4 Sec 1 to 2 Sec System BIOS Cacheable Description Selecting Enabled allows caching of the system BIOS ROM at Optio
36. cally and may vary depending on the system configuration Table 19 Memory map processor view CPU Address Range Size Description 0000 0000 0009 FFFF 640 System board 000A 0000 0008 FFFF 128 945 express chipset E 39 Motherboard registers System board 0000 0000 DFFF FFFF 256 945GME express chipset 22 m Motherboard resources FD60 0000 FD6F FFFF 1 ICH7 controller hub FD80 0000 FD8F FFFF 1 Hub interface to PCI bridge FD90 0000 FD9F FFFF 1 ICH7 controller hub Ox FDAO 0000 FDAF FFFF 1MB ICH7 controller hub FDBO 0000 FDCF FFFF 2 ICH7 controller hub FDDO 0000 FDDF FFFF 1 ICH7 controller hub FDEO 0000 FDEF FFFF 1 ICH7 controller hub FDFO 0000 FDF7 FFFF 1512 945 express chipset Ox FDF8 0000 FDFB FFFF 256KB 945 express chipset Ox FDFF F000 FDFF F3FF 1KB ICH7 controller hub 0x FREE FREF m System board MEN Mikro Elektronik GmbH 74 20A020 00 E1 2008 12 08 Organization of the Board 4 1 2 Memory Table 20 Memory map Address Range Size Description 0x 0000 000F 16 bytes ICH7 IDE controller 0 0020 0021 2 bytes Interrupt controller 0040 0043 4 bytes System timer
37. ct For DRAM gt 64MB Non 0S2 HDD S M A R T Capability Disabled Full Screen 1060 Show Disabled Summary Screen Show Disabled F5 Previous Values F6 CPU Feature Sub menu Delay Prior to Thermal Thermal Management CHE 11 20 On Demand TCC Execute Disable Bit Virtualization Technology Core Multi Processing Delay Prior to Thermal Fail Safe Defaults Optimized Defaults 4 Min Thermal Monitor 2 Auto Disable Enabled Enabled Enabled Description Controls the activation of the Thermal Monitor s automatic mode It allows you to determine when the processors Thermal Monitor should be activated in automatic mode after the system boots 4 Min 8 Min Options MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 16 Min 32 Min BIOS Thermal Management Description Shows the active thermal management Options are available only with Core Duo versions of the board With Celeron versions Thermal Management is fixed to Thermal Monitor 1 Options Thermal Monitor 1 die throttling Thermal Monitor 2 Ratio amp VID transi tion Disabled TM1 and TM2 enabled C1E Function Description Enables the enhanced halt state for power saving Options Auto Disabled On Demand TCC Description When enabled it indicates the clock on to clock off interval ratio Options Disable 50 0 12 5 62 5 25 0 75 0 37 5 87 5 Execute Disable Bit Description When disabled forces the
38. ection One USB interface is accessible at the front panel Connector types 4 pin USB Series A receptacle according to Universal Serial Bus Specification Revision 1 0 Mating connector 4 pin USB Series A plug according to Universal Serial Bus Specification Revi sion 1 0 Table 6 Pin assignment of USB front panel connectors 1 45V 2 USB 3 USB 0 4 GND Table 7 Signal mnemonics of USB front panel connectors Signal Direction Function 45V out 5 V power supply GND Digital ground USB USB D in out USB lines differential pair 2 10 2 Rear Connection Seven USB interfaces are accessible via rear I O on VMEbus connector P2 See Chapter 2 16 VMEbus Interface on page 44 for rear I O pin assignments MEN Mikro Elektronik GmbH 32 20A020 00 E1 2008 12 08 MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description 2 11 Ethernet Interfaces The A20 offers one Ethernet interface It is accessible at the front panel The Ethernet interface is connected to the Southbridge via one x1 PCI Express PCIe link It is controlled by an Intel 82573 Ethernet controller It supports 10 Mbits s up to 1000 Mbits s as well as full duplex operation and autonegotiation The controller uses a part of the boot Flash to store the MAC address The unique MAC address is set at the factory and should not be changed Any attempt to change this address may crea
39. ent acquire licenses for the right of lectual possession of the other party because of this Agreement This Agreement does not result in any obligation of the parties to purchase services or products from the other party 6 Validity of Agreement The period after which MEN agrees not to assert claims against the recipient with respect to the confi dential information disclosed under this Agreement shall be months filled out by MEN Not less than twenty four 24 nor more than sixty 60 months 7 General If any provision of this Agreement is held to be invalid such decision shall not affect the validity of the remaining provisions and such provision shall be reformed to and only to the extent necessary to make it effective and legal This Agreement is only effective if signed by both parties Amendments to this Agreement can be adopted only in writing There are no supplementary oral agree ments This Agreement shall be governed by German Law MEN Mikro Elektronik GmbH The court of jurisdiction shall be Nuremberg Neuwieder Strafe 5 7 90411 N rnberg Deutschland Tel 49 911 99 33 5 0 Fax 49 911 99 33 5 901 E Mail info Non Disclosure Agreement for Circuit Diagrams page 2of2 www men de
40. esistance A total of six PCI Express lanes for high speed communication such as Gb Ethernet are supported on the A20 One x1 PClIe link is used for the on board Ethernet interface three x1 links support the XMC slots one x1 link supports the PMC slots via a PCI Express to PCI X bridge and one x1 link is used for connection of the VMEbus bridge The PMC slots support 64bit 66MHz PCI X Supervision of the processor and board temperature as well as a watchdog for monitoring the operating system complete the functionality of the SBC The A20 comes with a tailored passive heat sink within 4 HP height However forced air cooling is always required inside the system Equipped with Intel components exclusively from the Intel Embedded Line the A20 has a guaranteed minimum standard availability of 5 years MEN Mikro Elektronik GmbH 2 20A020 00 E1 2008 12 08 Technical Data Its robust design make the A20 especially suited for rugged environments with regard to extended operation temperature shock and vibration according to applicable DIN EN or IEC industry standards It is also ready for coating for use in humid and dusty environments The wide range of industrial applications include for example monitoring vision and control systems as well as test and measurement Main target markets comprise industrial automation security and infotainment traffic and transportation shipbuilding medical engineering and robotics Tec
41. est IDE IRQ in IDE interrupt request IDE RD out IDE read strobe IDE RDY in IDE ready IDE_RST out IDE reset IDE_WR out IDE write strobe 1 The IDE fuse used on A20 is a PolyFuse and therefore needs no maintenance MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description 2 8 1 2 Inserting and Extracting a CompactFlash Card The A20 supports standard CompactFlash cards For CompactFlash cards available MEN see MEN s website The A20 is shipped without a CompactFlash card installed To install CompactFlash please stick to the following procedure Power down your system and remove the A20 from the system Put the board on a flat surface Lift the CompactFlash holding bracket VMEb Heat Sink VGA i Insert the CompactFlash card carefully as indicated by the arrow on top of the card Make sure that all the contacts are aligned properly and the card is firmly con nected with the card connector Push the CompactFlash holding bracket back down until it clicks into place Observe manufacturer notes on usage of CompactFlash cards MEN Mikro Elektronik GmbH 27 20A020 00 E1 2008 12 08 ia Functional Description 2 8 2 Serial ATA SATA The serial ATA SATA interface is controlled by the Southbridge and provides two channels One channel can be used to connect an on board hard disk The other channel is led to the VMEbus
42. g the power button In the De ay 4 Sec mode the system powers off when the power button is pressed for more than four seconds or enters the suspend mode when pressed for less than 4 seconds Options Instant Off Delay 4 Sec Energy Lake Function Description Enable or disable the energy lake energy management technology Options Disabled Enabled PWRON After PWR Fail Description Sets the system power status when power returns to the system from a power failure situation Options Former Sts On Off USB KB WakeUp From S3 S4 Description When enabled allows to wake up the system by USB keyboard when you shut down the computer in S3 mode Options Enabled Disabled Reload Global Timer Events Primary Secondary IDE 0 1 PCI PIRQ A D Description The IDE and PCI PIRQ are I O events which can prevent the sys tem from entering a power saving mode or can awaken the system from such mode When device wants to gain the attention of the operating system it signals this by causing an IRQ to occur When the operating system is ready to respond to the request it interrupts itself and performs the service Options Enabled Disabled MEN Mikro Elektronik GmbH 67 20A020 00 E1 2008 12 08 MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 eu 2 HPET Support Description Enables disables the high precision event timer Options Enabled Disabled HPET Mode Description Selects the high precision event
43. gher delay for HDD detection Options 0 15 seconds Onboard Device Sub menu USB Controller Enabled USB 2 0 Controller Enabled USB Keyboard Support Auto HD Audio Select Enabled Onboard LAN Controller Enabled Watchdog Disabled USB Controller Description Enables disables the USB controller Options Enabled Disabled USB 2 0 Controller Description This entry is for disable enable EHCI controller only This BIOS itself may may not have high speed USB support If the BIOS has high speed USB support built in the support will be automat ically turned on when high speed devices were attached Options Enabled Disabled USB Keyboard Support Description Enables disables USB keyboard support Options Enabled Disabled Auto HD Audio Select Description Enables or disables HD Audio Options Enabled Disabled Onboard LAN Controller Description Enables disables the LAN controller Options Enabled Disabled Watchdog Description If the watchdog is active the system will be rebooted after the configured time while no application triggers the watchdog Options Disabled default 1 min 2 5 10 15 20 30 MEN Mikro Elektronik GmbH 63 20A020 00 E1 2008 12 08 MR NEED EET PSOE BIOS 3 6 Special Features Phoenix AwardBIOS CMOS Setup Utility Power Management Setup Console Redirect Enabled Item Help Serial Port Mode 115200 8 n 1 7 7 1
44. hnical Data CPU Up to Intel Core 2 Duo 17400 Dual core 64 bit processor Up to 1 5GHz processor core frequency Up to 667MHz front side bus frequency Chipset Northbridge Intel 9454 Express Southbridge Intel ICH7 M DH Memory 4MB L2 cache integrated in Core 2 Duo Up to 4GB SDRAM system memory Soldered DDR2 667MHz memory bus frequency Dual channel 2x64 bits CompactFlash card interface Via on board IDE TypeI True IDE DMA support 8Mbits boot Flash Serial EEPROM 2kbits for factory settings Mass Storage Parallel IDE PATA One IDE port for local CompactFlash Serial ATA SATA One channel for on board hard disk One channel via rear I O connector P2 Transfer rates up to 150 8 RAID level 0 1 support MEN Mikro Elektronik GmbH 3 20A020 00 E1 2008 12 08 Technical Data Graphics ntegrated in 945GME Express chipset 200 250MHz 256 bit graphics core connector at front panel VO USB One USB 2 0 port via Series connector at front panel Seven USB 2 0 ports via rear I O UHCI implementation Data rates up to 480Mbits s Ethernet One 10 100 1000Base T Ethernet channel at front panel RJ45 connector at front panel Ethernet controller connected by one x1 PCIe link On board LEDSs to signal activity status and connection speed Front Connections VGA One USB 2 0 Series A One Ethernet RJ45 Rear
45. inute in each mode Video Off Method Description Determines the manner in which the monitor is blanked Options Blank Screen System only writes blanks to the video buffer V H System turns off vertical and horizontal synchro SYNC Blank nization ports and writes blanks to the video buffer DPMS Allows BIOS to control the video display Select this option if your monitor supports the VESA Dis play Power Management Signaling DPMS stan dard Video Off In Suspend Description When enabled the video is off in suspend mode Options No Yes Suspend Type Description Selects the suspend type Stop Grant wakes up by IRQ while PwrOn Suspend wakes up by ACPI wake up event Options Stop Grant PwrOn Suspend Suspend Mode Description When enabled and after the set time of system inactivity all devices except the CPU will be shut off Options Disabled 4 Min 20 Min 1 Hour 1 Min 8 Min 30 Min 2 Min 12 Min 40 Min MEN Mikro Elektronik GmbH 66 20A020 00 E1 2008 12 08 BIOS HDD Power Down Description When enabled and after the set time of system inactivity the hard disk drive will be powered down while all other devices remain active Options Disabled 4 Min 8 Min 12 Min 1 Min 5 Min 9 Min 13 Min 2 Min 6 Min 10 Min 14 Min 3 Min 7 Min 11 Min 15 Min Soft Off by PWR BTTN Description This field defines the power off mode when using an ATX power supply The nstant Off mode allows powering off immediately upon pressin
46. ity Bus timer Location Monitor Interrupter D08 O I 7 1 ROAK Interrupt handler D08 O IH 7 1 Single level 3 fair requester Single level 3 arbiter Electrical Specifications Supply voltage power consumption 5V 3 5 3 24 idle 6 6A full load 33V for XMC PMC are generated on board Mechanical Specifications Dimensions standard double Eurocard 233 3mm x 160mm Front panel 4HP with ejector Weight Without XMC PMC 525g MEN Mikro Elektronik GmbH 5 20A020 00 E1 2008 12 08 Technical Data Environmental Specifications Temperature range operation 0 60 Airflow min 1 5m s Temperature range storage 40 85 Relative humidity operation max 95 non condensing Relative humidity storage max 95 non condensing Altitude 300m to 3 000m Shock 15g 11ms EN 60068 2 27 Bump 10g 16ms EN 60068 2 29 Vibration sinusoidal 1g 10 150Hz EN 60068 2 6 Conformal coating on request MTBF 40 C according to IEC TR 62380 RDF2000 Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manu facturers EMC Tested according to EN 55022 Class A radio disturbance EN 61000 4 2 ESD EN 61000 4 4 burst and EN 61000 4 5 surge BIOS Award BIOS Software Support Windows Linux VxWorks on request ntel amp Virtualization Technology allows a platform to run multiple operating syste
47. lektronik GmbH 12 20A020 00 E1 2008 12 08 Contents 2 10 1 General pa Re REDE Re hapa ai 44 2 10 2 Taka aaa DRE OSS 45 2 17 Reset Button and Status LED 50 BIOS 51 31 Man T UEM 51 3 2 Standard CMOS Features 52 5 3 Advanced BIOS rods epar pas 54 3 4 Advanced Chipset 58 3 5 Integrated Peripherals eas dees caw es 61 2 6 Special Beatles a wei oS epu b gr NES ge us 64 3 7 Power Management Setups isse sya sama l Re Rye 65 3 8 PNP PCI Configurations omm 69 39 Health Stas usu odd iae basen 72 3 10 Frequency Voltage 1 72 3 11 Load BIOS Default VallleS ru uy 73 3 12 Load Last Saved 2 73 Il PaSSWOFIO E usia Saves Exit Setups SERE EROR EA RON 73 3 15 Exit without REPE esl 4 Organization of the 74 Memory Mappings Q u sss RR RE RR RE RR 74 4 1 1 Processor View of the Memory 74 4 12 Memory ao or tn rr rans 75 42 PCMMCVICES 6 iate vog od
48. les team for further information MEN Mikro Elektronik GmbH 21 20A020 00 E1 2008 12 08 22212110 Functional Description 2 5 Processor Core The A20 is equipped with an Intel Core Duo Core 2 Duo or single core Celeron M processor core The following table gives a performance overview Table 1 Processor core options on A20 Processor Type Core Frequency Power Class L2 Cache Front Side Bus Core 2 Duo 1 5 GHz 17W 4 MB 667 MHz L7400 Core Duo L2400 1 66 GHz 15 W LV 2 MB 667 MHz Core Duo U2500 1 2 GHz 9 W ULV 2 MB 533 MHz Celeron M 423 11 07 GHz 5 5 W ULV 1MB 533 MHz 1 ULV Ultra Low Voltage LV Low Voltage 2 5 1 Thermal Considerations A suitable heat sink is provided to meet thermal requirements For special requirements a larger heat sink is also available on request Please contact MEN sales for more information sink at all warranty on functionality and reliability of the A20 may cease If you Please note that if you use any other heat sink than that supplied by MEN or no heat have any questions or problems regarding thermal behavior please contact MEN 2 6 Bus Structure The A20 uses an Intel 945GME Express component as the Northbridge that connects to the processor core and controls memory and graphics and an Intel ICH7 M DH Controller Hub as the Southbridge Any I O is directly controlled by this chipset there is no local PCI bus The board h
49. m it MEN Mikro Elektronik GmbH 10 20A020 00 E1 2008 12 08 About this Document Legal Information MEN Mikro Elektronik reserves the right to make changes without further notice to any products herein MEN makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does MEN assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts MEN does not convey any license under its patent rights nor the rights of others Unless agreed otherwise MEN products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur Should Buyer purchase or use MEN products for any such unintended or unauthorized application Buyer shall indemnify and hold MEN and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of
50. ms and applications in independent partitions one computer system can function as multiple virtual systems For more information on supported operating system versions and drivers see online data sheet do MEN Mikro Elektronik GmbH 6 20A020 00 E1 2008 12 08 Block Diagram Intel Core 2 Duo 945GME Express Memory Controller Graphics Controller ICH7 M DH Controller Hub MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 System Memory DDR2 SDRAM System Memory DDR2 SDRAM VGA Watchdog IDE PATA _ IDE SATA USB 2 0 gt USB 2 0 a USB 2 0 Ex USB 2 0 USB 2 0 Ethemet n Pl Boot Flash PCI X PCI Express Block Diagram Front panel connector Rear connector CompactFlash On board Hard Disk Shared slot XMC or PMC to PCI Bria 9 riage PMC or SPI M PCI Express PCI Bridge PCI X Boot Flash VME P1 VMEbus VME P2 gt Configuration Options Configuration Options CPU Core 2 Duo L7400 1 5GHz LV Core Duo L2400 1 66GHz LV Core Duo U2500 1 2GHz ULV Celeron amp M 423 1 06 GHz Memory System RAM 512 1 GB 2 4 GB e CompactFlash up to maximum available UART instead of front USB and one PCI Express link One RJ45 connector at front panel Data
51. n on board CompactFlash slot You can connect one device to a 40 pin ZIF connector By standard a CompactFlash slot is assembled using a small adapter card in the heat sink area The slot is ready to use with the ZIF connection already in place Even with CompactFlash the board needs only one slot in the system Please see MEN s website for ordering options 2 8 1 1 Connection The 40 pin PATA connector is located at the top side of A20 Connector types 40 pin ZIF receptacle 0 5mm pitch for ribbon cable connection MEN Mikro Elektronik GmbH 24 20A020 00 E1 2008 12 08 40 38 IDE_RST GND IDE_D 7 IDE 0181 IDE 0161 IDE D 9 IDE D 5 IDE D 10 IDE D 4 IDE D 11 IDE 0131 IDE D 12 IDE D 2 IDE D 13 IDE D 1 IDE D 14 IDE 0101 IDE D 15 GND IDE DRQ GND IDE_WR IDE_RD GND IDE_RDY GND IDE_DAK IDE_IRQ IDE A 1 IDE 0 IDE A 2 IDE 51 IDE 43 3V 3 3V MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description Functional Description Table 3 Signal mnemonics of 40 pin IDE PATA connector Signal Direction Function 3 3V out 3 3 V power supply current limited to 2 A by a fuse GND Digital ground IDE A 2 0 out IDE address 2 0 IDE 514 out IDE chip select 1 IDE 53 out IDE chip select 3 IDE D 15 0 in out IDE data 15 0 IDE DAK out IDE DMA acknowledge IDE DRQ in IDE DMA requ
52. ns OxF0000 to OxFFFFF resulting in better system performance However if any program writes to this memory area a system error may result Enabled Disabled Video BIOS Cacheable Description Selecting Enabled allows caching of the video BIOS ROM Options 0xC0000 to OxF7FFF resulting in better video performance How ever if any program writes to this memory area a system error may result Enabled Disabled Memory Hole At 15M 16M Description Options In order to improve performance certain space in memory can be reserved for ISA cards This memory must be mapped into the memory space below 16 MB Enabled Disabled PCI Express Root Port Func Sub menu PCI PGI PCI PCI PCI PCI PEI Express Port 1 Auto Express Port 2 Auto Express Porc 9 Auto Express Port 4 Auto Auto Express Port 6 Auto E Compliancy Mode v1 0a PCI Express Port 1 2 3 4 5 6 Description Controls the activity of the PCI Express ports Options Enabled Disabled Auto PCI E Compliancy Mode Options MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 v1 0a v1 0 BIOS VGA PEG Onchip VGA Control Description Selects whether to use the onboard graphics processor an exter nal PCI graphics card PEG Port in the PMC slot The configuration also depends on the setting of the parameter nit Display First see Chapter Init Display First on page 69 Options Onchip VGA Select this to use
53. nted for thermal monitoring It checks the processor die temperature and the board temperature MEN provides dedicated software drivers for the board controller and LM63 device For a detailed description of the functionality of the driver software please refer to the drivers documentation You can find any driver software and documentation available for download on website MEN Mikro Elektronik GmbH 20 20A020 00 E1 2008 12 08 do Functional Description 2 3 Reset and Power Off Behavior The A20 generates its own reset signal You can wake it up from reset state by externally switching the power supply off and on When turning on the power supply the BIOS generates one of these states Off Reset On or Former State The executed event depends on the BIOS setting The VME bridge if it receives a reset signal from the VMEbus and the recessed button on the front panel generate a board reset signal 2 4 Real Time Clock The board includes a real time clock connected to the Southbridge For data retention during power off the RTC is backed up by a GoldCap capacitor The GoldCap gives an autonomy of approx 14 hours when fully loaded Under normal conditions replacement should be superfluous during lifetime of the board The RTC can generate interrupt requests to the Southbridge For retention of time date data after a power off of more than 8 10 hours the RTC is also backed by a battery Please contact MEN s sa
54. of the Board 4 2 PCI Devices Table 21 PCI devices Bus Vendor ID Device ID Function 0 0x00 0x0 0x8086 0x27AC Host bridge 0x02 0x0 0x8086 27 Display controller 0 1 0 0 0 8086 0 2700 PCI Express port 0 1 0 8086 0 2702 PCI Express port 0x5 0x8086 0 27 2 0 10 0 0 0 8086 0x27C8 USB UHCI controller 1 0 1 0 8086 0 27 9 USB UHCI controller 2 0x2 0x8086 0 27 USB UHCI controller 3 0x3 0x8086 0x27CB USB UHCI controller 4 0x7 0x8086 0x27CC USB 2 0 EHCI controller Ox1E 0x0 0x8086 0x2448 PCI to PCI bridge Ox1F 0x0 0x8086 0x278D LPC controller 0 1 0 8086 0x27DF IDE controller 0x3 0x8086 0x27DA SMBus controller 0x00 0x0 0 10 0 8114 bridge 3 0x00 0x0 0 10 0 8114 PCI Express to PCI bridge for VME 0x0C 0x0 0 10 0 0148 VME bridge 0 00 0x0 0x8086 0x109A Ethernet controller 1 MEN Mikro Elektronik GmbH 76 20A020 00 E1 2008 12 08 Organization of the Board 4 3 SMBus Devices Table 22 SMBus devices Address Function 0x98 LM63 CPU temperature sensor OxA4 SPD of SO DIMMs OxAE ID EEPROM 0xD2 Clock generator 0x9A Board Controller 0xA8 EEPROM on XMC2 OxAC EEPROM on XMC1 S l l 77 20A020 00 E1 2008 12 08 Organization of the Board 4 4 Interrupt Handling Interrupt handling is done by the inter
55. on Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC 1386 1 1995 TEEE www ieee org on CompactPCI Specification 2 3 PCI Industrial Computers Manufacturers Group PICMG www picmg org 6 1 7 PCI Express PCI Special Interest Group WW pcisig com 6 1 8 VMEbus VMEbus General The VMEbus Specification 1989 The VMEbus Handbook Wade D Peterson 1989 VMEbus International Trade Association www vita com Tundra Tsil48 Product information downloads and resources www tundra com products vme bridges tsi 148 MEN Mikro Elektronik GmbH 82 20A020 00 E1 2008 12 08 Appendix 6 2 Finding out the Board s Article Number Revision and Serial Number MEN user documentation may describe several different models and or hardware revisions of the A20 You can find information on the article number the board revision and the serial number on two labels attached to the board Article number Gives the board s family and model This is also order ing number To be complete it must have 9 characters Revision number Gives the hardware revision of the board Serial number Unique identification assigned during production If you need support you should communicate these numbers to MEN Figure 5 Labels giving the board s article number revision and serial number Complete article number 01A020 00 O 00 00 00 Revision number Serial number MEN Mikro Elektronik
56. onboard VGA The parameter Init Display First has to be set to Onboard PEG Port Select this to use a PCI graphics card in the PMC slot via the PCI Express to PCI Bridge The parameter nit Display First has to be set to PCI Slot VGA On Chip Frame Buffer Size Description Sets the On Chip Frame Buffer Size This memory is shared with the system memory Options 1MB 8MB VGA DVMT Mode Description Selects how memory is allocated DVMT Dynamic Video Mem ory Technology Options FIXED BOTH DVMT VGA DVMT FIXED Memory Size Description Specifies the size of system memory if DVMT Mode is set to FIXED or DVMT memory if DVMT Mode is set to DVMT to allo cate for video memory Options 64MB 224MB 128MB VGA Boot Display Description Selects the type of boot display Options VBIOS Default CRT CRT EFP MEN Mikro Elektronik GmbH 60 20A020 00 E1 2008 12 08 BIOS 3 5 Integrated Peripherals Phoenix AwardBIOS CMOS Setup Utility Integrated Peripherals gt On Chip IDE Device CPress Enter Item Help gt Onboard Device Press Enter Menu Level gt F5 Previous Values F6 Fail Safe Defaults F Optimized Defaults On Chip IDE Device Sub menu DE HDD Block Mode Enabled DE DMA transfer access Enabled On Chip Primary PCH IDE 91601 DE Primary Master 10 Auto DE Primary Slave Auto DE Primary
57. ontroller is a very complex component we have not included any details on register access etc here Please refer to the bridge s manufacturer data sheet which is available as a PDF download from Tundra s website www tundra com lt For more literature on the VMEbus see Chapter 6 1 Literature and Web Resources on page 80 MEN Mikro Elektronik GmbH 44 20A020 00 E1 2008 12 08 Functional Description 2 16 2 Connection Connector types 160 pin 5 row plug performance level according to DIN41612 part 5 Mating connector 160 pin 5 row receptacle performance level according to DIN41612 part 5 2 16 2 1 Bus Connection VMEbus P1 The pin assignment of P1 conforms to the VME64 specification ANSI VITA 1 1994 R2002 and VME64 Extensions Standard ANSI VITA 1 1 1997 R2003 MEN Mikro Elektronik GmbH 45 20A020 00 E1 2008 12 08 Table 16 Pin assignment of VME64 bus connector P1 Functional Description D C B A 2 1 08 BBSY DO 2 GND D9 BCLR D1 GND 3 D10 ACFAIL D2 4 D11 BGOIN D3 GND 5 D12 BGOOUT D4 6 D13 BG1IN D5 GND 7 D14 BG1OUT D6 8 D15 BG2IN D7 GND 9 GND BG2OUT GND 10 GAO SYSFAIL BG3IN SYSCLK GND 11 GA1 BERR BG3OUT GND 12 SYSRESET BRO DS1 GND 13 GA2 LWORD BR1 DSO 14 AM5 BR2 WRITE GND 15 GA3 A23 BR3 GND 16 A22 AMO DTACK GND 17 GA4 A21 AM1 GND 18 A20 AM2 AS GND 19 A19 AM3 GND 20 A18 GND 1 GND 21 A
58. ornado and VxWorks are registered trademarks of Wind River Systems Inc other products or services mentioned in this publication are identified by the trademarks service marks or product names as designated by the companies who market those products The trademarks and registered trademarks are held by the companies producing them Inquiries concerning such trademarks should be made directly to those companies other brand or product names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or design MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document Copyright 2008 MEN Mikro Elektronik GmbH rights reserved Please recycle Germany France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder StraBe 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Chatelaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 E mail info men de
59. rates 300bit s 230kbit s FIFO receive and transmit buffers for high data throughput Handshake lines full support Please note that some of these options may only be available for large volumes Please ask our sales staff for more information For available standard configurations see online data sheet MEN Mikro Elektronik GmbH 8 20A020 00 E1 2008 12 08 Product Safety Product Safety Lithium Battery This board contains a lithium battery There is a danger of explosion if the battery is incorrectly replaced See Chapter 5 Maintenance on page 79 Electrostatic Discharge ESD Computer boards and components contain electrostatic sensitive devices Electrostatic discharge ESD can damage components To protect the board and other components against damage from static electricity you should follow some precautions whenever you work on your computer Power down and unplug your computer system when working on the inside Hold components by the edges and try not to touch the IC chips leads or cir cuitry Use a grounded wrist strap before handling computer components Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system Store the board only in its original ESD protected packaging Retain the original packaging in case you need to return the board to MEN for repair MEN Mikro Elektronik GmbH 9 20A020 00 E1
60. rcurrent port 3 USB in USB overcurrent port 4 USB OC5 in USB overcurrent port 5 USB OC6 in USB overcurrent port 6 USB OC7 in USB overcurrent port 7 PMC PMC xx in out Signal xx PMC rear I O connector J14 MEN Mikro Elektronik GmbH 20A020 00 E1 2008 12 08 Functional Description 2 17 Reset Button and Status LED The A20 has a reset button and one status LED at the front panel The reset button is recessed within the front panel and requires a tool e g paper clip to be pressed preventing the button from being inadvertently activated The yellow status LED shows board status messages The LED is controlled by a GPIO pin of the I O Controller Hub When the board is powered up it switches on the LED During operation the state of the LED can be controlled by software See MEN s website for available driver software MEN Mikro Elektronik GmbH 50 20A020 00 E1 2008 12 08 BIOS On each setup page there are two functions to load defaults F6 loads fail safe defaults and F7 loads optimized default values for each setup entry These standard values are independent of whether the board has already booted successfully with a setup configuration However it makes a difference if these defaults are called from the Main Menu If a setup configuration was already saved that led to a successful boot both menu functions will load these values as the defaults for the setup pages See also Chapter 3 11
61. rupt controller of the chip set Every interrupt can be enabled or disabled and can be masked by software Interrupts are prioritized by the BIOS or by the operating system and these settings are normally not altered by application software MEN Mikro Elektronik GmbH 78 20A020 00 E1 2008 12 08 Maintenance 5 Maintenance 5 1 Lithium Battery The board contains a lithium battery There is a danger of explosion if the battery is incorrectly replaced Replace only with the same or equivalent type Manufacturer Renata Type CR2032 Capacity 235 mAh Dispose of used batteries according to the manufacturer s instructions Figure 4 Position of battery on the A20 Battery Holder VMEbus P1 MEN Mikro Elektronik GmbH 79 20A020 00 E1 2008 12 08 Appendix 6 Appendix 6 1 Literature and Web Resources A20 data sheet with up to date information and documentation www men de 6 1 1 CPU ntel Embedded Processors developer intel com products embedded processors htm 6 1 2 IDE EIDE Information Technology AT Attachment 3 Interface ATA 3 Revision 6 working draft 1995 Accredited Standards Committee X3T10 6 1 3 SATA e Serial ATA International Organization SATA IO www serialata org 6 1 4 USB USB Universal Serial Bus Specification Revision 1 0 1996 Compaq Digital Equip ment Corporation IBM PC Company Intel Microsoft NEC Northern Telecom www usb org MEN Mikro Elektronik GmbH 8
62. sket around the PMC front panel is properly in its place Screw the module tightly to the A20 using the two mounting standoffs and four matching oval head cross recessed screws of type M2 5x6 Figure 3 Installing a PMC mezzanine module PMC module Mounting standoff y 64 pin 3 3 connectors voltage key A CPU board A 2 M2 5x6 oval 2 M2 5x6 oval head cross head cross recessed screws recessed screws MEN Mikro Elektronik GmbH 42 20A020 00 E1 2008 12 08 Functional Description 2 15 PCI Express 2 15 1 General PCI Express PCIe succeeds PCI and AGP and offers higher data transfer rates As opposed to the PCI bus PCIe is no parallel bus but a serial point to point connection Data is transferred using so called lanes with each lane consisting of a line pair for transmission and a second pair for reception Individual components are connected using switches PCIe supports full duplex operation and uses a clock rate of 1 25 GHz DDR This results in a data rate of max 250 MB s per lane in each direction The standard PCI bus with 32 bits 33 MHz only allows a maximum of 133 MB s If you use only one lane you speak of a PCIe x1 link You can couple several lanes to increase the data rate e g x2 with 2 lanes up to a x32 link using 32 lanes In terms of software most operating systems can handle PCI Express boards just as well as the old PCI 2 15 2 Implementation on the A20
63. t based operating systems DOS Linux etc The terminal can be connected to the COM interface via a special RJ45 to 9 pin D Sub adapter cable available from MEN For ordering options see MEN s website It is possible to use the COM interface for console redirection i e to maintain the BIOS from a remote location The UART interfaces support transfer rates from 300bit s to 230kbit s Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 10 Pin assignment of RS232 connector 1 DSR DCD Table 11 Signal mnemonics of UART interface DTR GND RXD TXD CTS RTS oo N O Q Iv Signal Direction Function CTS in Clear to send DCD in Data carrier detected DSR in Data set ready DTR out Data terminal ready GND Digital ground RTS out Request to send RXD in Receive data TXD out Transmit data MEN Mikro Elektronik GmbH 34 20A020 00 E1 2008 12 08 Functional Description 2 13 XMC Slots The A20 board provides up to two XMC slots for extension such as high speed graphics Ethernet etc XMC modules have the same form factor as PMC modules however they do not use a PCI bus but a high speed PCI Express connection and therefore have a different carrier board connector According to the XMC standard there is only one link on each XMC connector XMC slot 1 offers one connec
64. te node or bus contention and thereby render the board inoperable 2 11 1 One standard RJ45 connector is available at the front panel There are two status LEDs for the channel at the front panel Front Connection The pin assignment corresponds to the Ethernet specification IEEE802 3 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 8 Signal mnemonics of Ethernet 10 100 1000Base T connector Signal Direction Function in out Differential pairs of data lines for 1000Base T in Differential pair of receive data lines for 10 100Base T out Differential pair of transmit data lines for 10 100Base T Table 9 Pin assignment and status LEDs of 8 pin RJ45 Ethernet 10 100 1000Base T connectors LAN1 1000Base T 10 100Base T Lights up when a link is L BI_DA established and blinks 1 2 DA TX whenever there is transmit 3 RX or receive activity 4 BI DC 5 BI DC On Link 100Mbits s 2 6 BI DB RX Off Link with 10Mbits s e 7 BI 8 DD Functional Description 2 12 UART Interface Option As an option the A20 can be equipped with a COM interface at the front panel instead of the USB It is accessible via an RJ45 connector A VT100 terminal can be connected to the COM interface to control the BIOS and tex
65. th signaling voltages 3 3V 5V The PMC X slots support 32 64 bit and 33 66 MHz They are connected to a PCI Express to PCI X bridge which converts one PCI Express x1 link from the Southbridge PMC slot 1 supports rear I O via VMEbus connector P2 See Table 17 Pin assignment of VMEbus rear I O connector P2 PMC signals on page 48 for the pinout The connector layout is fully compatible to the IEEE1386 specification For connector pinouts please refer to the specification see Chapter 6 1 Literature and Web Resources on page 80 Connector types 64 pin 1 mm pitch board to board receptacle according to IEEE 1386 Mating connector 64 pin 1 mm pitch board to board plug according to IEEE 1386 MEN Mikro Elektronik GmbH 41 20A020 00 E1 2008 12 08 Functional Description 2 14 1 Installing a PMC Mezzanine Module Perform the following steps to install a module Make sure that the voltage keying of your PMC module matches the A20 Power down your system and remove the A20 from the system Remove the filler panel from the board s front slot if installed The module is plugged on the A20 with the component sides of the PCBs facing each other Put module s front connector through the A20 s front slot at a 45 angle Carefully put it down making sure that the connectors are properly aligned Press the PMC module firmly onto the A20 Make sure that the EMC ga
66. the option of connecting one or two PMCs or It detects automatically whether a PMC or XMC is plugged Refer to Chapter 2 13 XMC Slots on page 35 or Chapter 2 14 PMC Slots on page 41 for more details on the mezzanine cards SATA hard disk The board offers the option of installing a SATA hard disk instead of one XMC PMC A special mounting kit is available from MEN SS Refer to Chapter 2 8 2 1 Installing a SATA Hard Disk on page 28 for more details MEN Mikro Elektronik GmbH 17 20A020 00 E1 2008 12 08 Getting Started 1 3 Integrating the Board into a System You can use the following check list when installing the A20 in a system for the first time and with minimum configuration Power down the system Remove all boards from the VMEbus system Insert the A20 into slot 1 of the system making sure that the VMEbus connec tors are properly aligned Connect a USB keyboard and mouse to the USB connectors at the front panel Connect a CRT or flat panel display to the connector at the front panel Power up the system You can start up the BIOS setup menu by hitting the DEL key see Chapter 3 BIOS on page 51 Now you can make configurations in BIOS see Chapter 3 BIOS on page 51 Observe the installation instructions for the respective software MEN Mikro Elektronik GmbH 16 20A020 00 E1 2008 12 08 Getting Started 1 4 Troubleshooting at Start up If you have an
67. the other PCI devices queuing up may be stalled for too long The optimum latency time depends on your system configuration Options Decimal value between 0 and 255 PCI Clock Line Size Description Selects the clock line size Options 16 48 32 64 VME Memory Size Description This BIOS feature determines the size of the memory space used by the Tundra TSI148 bridge Options Disabled 128 MByte 512 MByte 64 MByte 256 MByte 1 GByte MEN Mikro Elektronik GmbH 70 20A020 00 E1 2008 12 08 BIOS Incoming VME SYSReset Description Options If the Incoming VME SYSReset feature is enabled the A20 is reset whenever another board in the system sends a SYSReset If the A20 is not the system master it does not trigger a SYSRESET in order to avoid reset loops If the feature is disabled the board is not reset when another board in the system sends a SYSReset Disabled Enabled INT Pin 1 2 3 4 5 6 7 8 Assignment Description Options INT Pin 1 assigns PCI INTA to IRQ line x INT Pin 2 assigns PCI INTB to IRQ line x INT Pin 3 assigns PCI INTC to IRQ line x INT Pin 4 assigns PCI INTD to IRQ line x INT Pin 5 assigns PCI INTE to IRQ line x INT Pin 6 assigns PCI INTF to IRQ line x INT Pin 7 assigns PCI INTG to IRQ line x INT Pin 8 assigns PCI INTH to IRQ line x INTE to INTH are only used internally Auto 5 10 14 3 7 11 15 4 9 12 Maximum Payload Size Description Options MEN Mikro
68. timer mode Options 32 bit mode 64 bit mode BIOS 3 8 PNP PCI Configurations Phoenix AwardBIOS CMOS Setup Utility PnP PCI Configurations H Mui Disolay First Onboard Item Help Reset Configuration Data Disabled Menu Level gt Resources Controlled By Auto ESCD x IRQ Resources Press Enter PCI VGA Palette Snoop Disabled PCI Latency Timer CLK 22 PCI Clock Line Size 32 VME Memory Size 128 MByte ncoming VME SYSReset Enabled T Pin 1 Assignment Auto Pin 2 Assignment Auto T Pin 3 Assignment Auto T Pin 4 Assignment Auto T Pin 5 Assignment Auto T Pin 6 Assignment Auto Pin 7 Assignment Auto T Pin 8 Assignment Auto xe PCI Exoress relative itens s Maximum Payload Size 4096 H F5 Previous Values F6 Fail Safe Defaults F Optimized Defaults Init Display First Description Selects which graphics controller the system initializes when the system boots See also Chapter VGA PEG Onchip VGA Control on page 60 Options PCI Slot Onboard Reset Configuration Data Description Select Enabled to reset Extended System Configuration Data ESCD when you exit Setup if you have installed a new add on and the system reconfiguration has caused such a serious conflict that the OS cannot boot Disabled is the default Options Enabled Disabled Resources Controlled By Description BIOS can automaticall
69. tor 715 with one x1 PCI Express link XMC slot 2 provides two connectors J25 and J26 which support one x1 PCI Express link each The connector layout is fully compatible to the standard for XMC 3 connectors See also Chapter 6 1 Literature and Web Resources on page 80 It is possible to use the PCI Express interface of the XMC connectors and the PCI interface of the PMC connectors at the same time which makes it possible to use hybrid PMC XMC modules 2 13 1 Connection Connector types 114 XMC receptacle connector Mating connector 114 pin XMC plug connector e g SAMTEC ASP105885 01 MEN Mikro Elektronik GmbH 35 20A020 00 E1 2008 12 08 Functional Description Table 12 Pin assignment of 114 pin XMC connector J15 slot 1 A B C D E F 1 4 4 0 43 3V 45V 2 GND GND F GND GND MRSTI 3 43 3V 45V 4 GND GND GND GND MRSTO ABCDEF 5 s 3 3V 45V sess 6 GND GND GND GND 12 OOOOOO 7 5 3 3 5V 823823 999000 8 GND GND F GND GND 12V 909999 Bu 11113 10 GND GND GND GND GAO 99900999 11 PET4p0 PET4nO 45V EE 12 GND GND 1 GND GND 13 45V 14 GND GA2 GND GND MSDA 15 i 5 5V 16 GND GND MVMRO GND GND MSCL 17 18 GND GND GND GND 19 REFCLKAn
70. y configure all the boot and Plug amp Play com patible devices If you choose Auto you cannot select IRQ DMA and memory base address fields since BIOS automatically assigns them Options Auto ESCD Manual MEN Mikro Elektronik GmbH 69 20A020 00 E1 2008 12 08 BIOS 1 Resources Description When resources are controlled manually you must assign each system interrupt a type depending on the type of device using the interrupt i e either a PCI ISA Plug amp Play device default or a Leg acy ISA device PCI VGA Palette Snoop Description Some non standard VGA display cards may not show colors prop erly This field allows you to set whether or not MPEG ISA VESA VGA cards can work with PCI VGA When this field is enabled a PCI VGA can work with an MPEG ISA VESA VGA card When this field is disabled a PCI VGA cannot work with an MPEG ISA VESA card Options Enabled Disabled PCI Latency Timer CLK Description This BIOS feature controls how long a PCI device can hold the PCI bus before another takes over The longer the latency the longer the PCI device can retain control of the bus before handing it over to another PCI device Normally the PCI Latency Timer is set to 32 cycles This means the active PCI device has to complete its transactions within 32 clock cycles or hand it over to the next PCI device For better PCI performance a longer latency should be used but a long latency can also reduce performance as
71. y problems at start up of the A20 you can start the board with BIOS default settings for troubleshooting Please refer to Chapter 3 BIOS on page 51 1 5 Configuring BIOS The A20 is equipped with an industry standard BIOS Normally you won t need to make any changes in the BIOS setup If you do however you find further details on the A20 s BIOS in Chapter 3 BIOS on page 51 1 6 Installing Operating System Software The board supports Windows Linux VxWorks and QNX By standard no operating system is installed on the board Please refer to the operating system installation documentation on how to install the software You can find any software available on MEN s website 7 1 6 1 Installing Windows 2000 via USB If you want to install Windows 2000 using a USB CD ROM drive you must install from a Windows 2000 CD including Service Pack 4 to avoid problems This is a known Windows problem 1 7 Installing Driver Software For a detailed description on how to install driver software please refer to the respective documentation You can find any driver software and documentation available for download on MEN s website MEN Mikro Elektronik GmbH 19 20A020 00 E1 2008 12 08 Functional Description 2 Functional Description The following describes the individual functions of the board and their configuration on the board There is no detailed description of the individual controller chips and the CPU They can be obtained from

Download Pdf Manuals

Related Search

Related Contents

WH12VE  //////W///i///////  Siemens SN 25 M 230 EU dishwasher  - Fujitsu  

Copyright © All rights reserved. Failed to retrieve file