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5-Meg Hard Disk Service Manual (1982)(Tandy)

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2. o Go UU s s EE lt 5 RE SENG ONT WER E CUSTOM MANUFACTURED IN U S A BY RADIO SHACK A DIVISION OF TANDY CORPORATION 5 Meg Hard Disk Service Manual TOS QO rss TRS 80 5 Meg Hard Disk Service Manual Catalog Number 26 1130 ES Radie fhaek eege 5 Meg Hard Disk Service Manual TRS 80 CIA RENI TRS 80 5 Meg Hard Disk Service Manual Copyright 1982 Tandy Corporation All Rights Reserved Reproduction or use without express written permission from Tandy Corporation of any portion of this manual is prohibited While reasonable efforts have been taken in the preparation of this manual to assure its accuracy Tandy Corporation assumes no liability resulting from any errors or omissions in this manual or from the use of the information obtained herein Radio Shack 5 Meg Hard Disk SM TRS 80 Contents Warnings 1 OVELVIS WN EN Ed a hdi a a a 2 Technical Specifications man 37 COMNECEIONS 6 65555 NU SURE et inn Model I TT TE V Kw AA ew E dis 15 4 Power Up and Power DOWN ooooooooooooo o ced oes LO 5 Replacement ProcedureS o o
3. ice Manual Serv k 1S Meg Hard D 5 o 00800 Se oe 2000800 o 90000 o 80000900 dh 9 0000000000 06000000000000000000000000 0000088 S o 9 B 0000000000 o vuong 60 006606060000060000660060000 6 oe 08800fb gennana e 9099 ounen 9969800 o e 0000000000 0000 UNTBEEE 9000 o 00000060000 o 00000000000000000 888888 8089888 9 0 A 09000000808000000 d e oe 96 k o ga anan d ee TEGE e e 0 o o 0000000000 999 oe gt o 00000090 TY WITT MILL e o6dgunne s m Qe So panenan LUK o o a e 9 TIT 808 g 8800088 8888870 TI 9999996009 e annag
4. 1982 MADE IN U S A 06060000090 6606060606060606 ol 99 TANDY CORP R22 er jenm er 106 R24 caaer eer
5. FORT WORTH TEXAS 76102 CANADA BARRIE ONTARIO LAM 4W5 TANDY CORPORATION AUSTRALIA BELGIUM U K 280 316 VICTORIA ROAD PARC INDUSTRIEL DE NANINNE BILSTON ROAD WEDNESBURY RYDALMERE N S W 2116 5140 NANINNE WEST MIDLANDS WS10 7JN 8749403 PRINTED IN U S A
6. a sa w a s m m sa s m e am se m wa se ms ms s s s ar m af f s s r m s s a as am s sma a zapen f a wangian agg see Qam dtm u a reia vm rr s m w s s w m s t rm a e s s s u a a r s s a s w s r s s v lt r m I a s s s om 209 s mp s s rm s a m e w s s a m w jm s s W our ro Y n _ A a r _ a s s m s v neman emm men MEER vom mom mn DE MED MED DOI anata emm EER em O O wem mami O e wm vum m m m s r Min Typ Max Units Vin Range Input Select 115V 95 115 135 Vrms Input Select 230V 180 230 264 Vrms Line Freguency 47 50 60 63 Hz Output Voltages 5V 4 75 5 5 25 Volts 12V 11 4 12 12 6 Volts 12V 11 12 15 Volts Output Current 5V 45 2 5 Amps 12V 75 2 0 Amps 12V 005 10 Amps Load Regulation measured by varying load on considered output from typ to either min or max rated load 5V 5 5 12V 5 5 S 12V 8 3 25 5 Meg Hard Disk Service Manual Ripple Voltages 5 50 mV 12V 150 mV 12V 150 mV Efficiency 65 Over Voltage Protection 5 80 6 80 Volts Dimensions Height 5 50 in 13 97 cm Width 14 00 in 35 56 cm Length 15 00 in 38 10 cm Weight Primary 15 5 lbs 33 10 kg Secondary 12 5 lbs 27 5 kg Environment Ambient Temperature 50 to 95 degrees F 10 to 35 degrees C Relative Humidity 8 to 80 Maximum Wet Bulb 78 non condensing Heat Dissipation Altitude operating 0 to 6000 feet 0 to 1829 meters storage 1000 to 12000 feet 305 to 3656 me
7. g4 mea ADIN pee SHFCLK IBLA Ze a BAONE CRCLK A JCRCOR RITZ tot pl ell WRITE oe 5 pout pl aux p Boone ple un CRCIZ hoes mess WELK WPD DRS SE T me E gt HDWPINT HIS SEL b 4 WIS 240 Ha 2 Lo D DUDAT gt 03 up 87 i RS y 4 i 2 Un men De E lu 5 BI 15 Baler Mn 12 nam LATE D3 abi LATE RWE time q us TRTR 04 Ao SKPEN pro mu M n A J AH IB WOM R AI IB DWG NO REV 8000154 SCALE SHEET Z OF A u ti FN 7DM S e AND EE ELE l L TPS RIE 33B n be PAY C24 KE Lk MM RUI c 580 o ROLK TPG 09C4 DHOLD 1100 03 IBl v QOUTH HERO RST A cat HIS RCLK AMDET E i HIC gt a Lin AMDET P sri E 12 18 TIMCLK MC 2487 2 N a l HH MFMD ENDET 1 P 1 i ES An cote EE P TIMCLK LINA A 14 L MEMD ELE guz Y LS SA L C SRCH p ABUS EARLY el US pm cas 32 DYL DAT i ag 3 INC B l 4 i S86 Fi HIC I I Se wsh as gi Le 14 t l 15 a TPH l LR TAPC can 3 ie i v ia lm i 9 B L Be wG 19 pet ae pic A aa a LIA TIMCLK 13 14 DWG NO REV 8000154 SCALE i F 5 Meg Hard Disk Service Manual 13 Supplement This supplement to the Hard Disk Drive Service Manual was reproduced by permission of Tandon 20320 Prairie Street Chatworth CA 91311 RADIO SHACK A DIVISION OF TANDY CORPORATION U S A
8. gt SELDCR I unas Pe 10 2 A2 1B gt _Lla TD 57 EVEN gt IVB ar AS a U 8 LL IVA 02 NG RO 1B EN ES D RIT TE k Li 73 7 TNI IVB l x xm gt g w v p c SEL DIE 53 a gt Dicci Ve 4 502 gt RO IB _ ii RA E NR S 134 35 HDBwR 44 lk 3 JRXIB 175 ole SELDIR 49 HDBIORG JA 12 TORQ IE HDSEL 3 gt pl JA Aa al rara IA Tao PH HDWAZT xy ae E gt ARE Se usa Gal MCL KY zu AE n dt ep he MCLK PR AS dino ell 04 VLAG Zu gre 425 FARI lag AE uss pron AAS alaa ag al CROS MORAL EL ope ORO UNLESS OTHERWISE SPECIFIED L PENLANN b 72 82 34 gt HDBINTRA H TOLERANCES DATE 544 HARD DISK 3a gt HPBINTRQ XX OO XXX 005 CONTROLLER ANGLES sti HOLE DIA TOLERANCES FINISH 014 250 261 760 751 UP DIMENSIONS ARE IN INCHES AND APPLY AFTER PLATING 1 4 gt H gt DO NOT SCALE THIS DRAWING NEXT ASSY USED ON Nissi TILEDYMI FOS RA ff RA A R43 Ad TR AZ Dg lt HOBO Y M IB x HOED AZ TB EA m 4 S lt HDBD 3 ROK RE OMNI HDBD 4 poe A 9 WR T lt HOED o RONE m m3 AN WORD 7 b fs DE wc K LA z MOLL od WRELB gt DERES Ae N LL S ts gt R03 IB SY wu v i p E M 1B lt WC x 01 IB creg D2 IB HD BRD ee g uD BAD HOBAD DA IB LO i S HORMI SC s nostoa 2 Do IB z D7 IB LAM z MCLK 4PIN CL og gt WAEN X JB aj
9. 8429104 8569126 8569098 8569040 8589018 8569026 8896905 8559010 8539025 8896906 8790202 8709348 8709355 8729131 8589018 8569098 8896909 8790025 8569098 8589018 8569159 8579004 8896615 8759131 ii emm gp vm wm emm og emm mp mmm emm vm man em omg om mm om MED wm emm emm emm wm wm wo om oam mmm awan As emm wm O I vm sQ wem vom wg wm s Q el emp emp mm op wett w mp wm n m mm emm mmm mm em En vm s wen s emm eem open emm m vg atan e e emp lt emm mh mmh wm mm omg ARME vom Ms o am lt lt mg am mp vm am om wm vam wem m em s van e em m mmm om mg EER mmm em emp mm mmm rawan mm mg mmm emp epp remm emp vom emm mem mm vom ef ve pay vm app E eg Em wm ap om mm ML mm wm wn EER mm w ia weg om vm am wem am emm wm wm s V wm s s mmm emp omg mm mm erg emm emm mm mmm wm mmm oe mem lt em mp mm mmm omg mm op omg emp iak ss mp mm mmm ms wm s emm emm w n wm mm EE wm omg vm A am ms am wem mm sa wm emm lt f s HOLDER PLASTIC MAP OPO60 5M HDS OPO75 TESTING 5M OPO85 BURN IN 5M COVER TOP CLIP GRD SCREW 6 32 X 3 8 PPH SCREW 8 32 X 3 8 WASHER 8 FLAT LOGO STRIP BEZEL OPO90 5M HDS OPO95 Q C 5M HDS OP105 Q A 5M HDS LABEL WARRANTY NOT BAG 6X15X22 LABEL LINE TERMINATOR CARTON SECONDARY COMPONENT A COMPONENT B FILM P 180 PACKAGING CARTON 5M HDS F A 62 Service Manual 8590109 8896908 8896908 8896908 8729123 8559040 8569026 8569107 85
10. ACCESSORY HDS PRODUCT DESCRIPTION 5 1 4 HARD DISK CAT NO 26 1131 F2 Ka gt e gt CASE BOTTOM LABEL FCC PART 15 LABEL FCC ID HDS FOOT FASTENER 10 X 1 2 WASHER 1 2 O D LABEL S N 26 1131 PLUG 2 1 2 DIA OPO10 5M HDS CABLE INT CNTRLR CABLE INT CNTRL SLV SCREW 6 X 5 16 BRICO IND SCREW 4 40X3 4 PPH NUT 4 40 KEPS LOCK 60 Pm ven WED m vm dies 2000 u pg weem ian Q ts M dc ren ho E S t Qs s Service Manual PART NUMBER 8896503 8207210 8110222 Rp sal sis emp ie ede omr Q samah emm s lt ss s 8709021 8896650 wun wq n ws van maba emm Qum wna tt nb uqi sm arm Q as s m s Q m 8690002 8719027 8789810 8898428 8749411 8896653 8896652 8896651 8779031 8779118 8769172 8709252 8709329 8709057 8709326 8769164 8789820 8896904 8729129 8789287 8789773 8590123 8569062 8589074 8789783 8729148 8896901 8709325 8709328 8569130 8569059 8579003 EA om mmm it mm om OAR h mm om Qm n om mt GREEP lt rm EE em s om m vm e s EEND ot Q mm s 202 s mm er eme ss sm ss Q wana mmm aman s Ceu omg aamiin m sanan emm ro emm or rr ama atma ran r n mmm Qm v t a m s t cumin t s e mn u mt x em Q s s op mang vm een s s lt VINO wm GMUCD wem emp br v s t V s s eem wm vw lt s dem mann oC am ah m Q s emm a s s QG E J at samian at OK mg emt sa a E aan mo we lt
11. DRQ is reset 45 46 5 Meg Hard Disk 8 Troubleshooting the Power Supply Secondary Drive Only Section 1 Equipment for Test Set Up Li Isolation Transformer minimum of 500 VA rating CAUTION Dangerously high voltages are present in this power supply For the safety of the individual doing the testing please use an isolation transformer The 500 VA rating is needed to keep the AC waveform from being clipped off at the peaks These power supplies have peak charging capacitors and draw full power at the peak of the AC waveform 2 0 140 Variable Transformer Variac Used to vary input voltage Recommend 10 Amp 1 4 KVA rating minimum 3 Voltmeter Needed to measure DC voltages to 50 VDC and AC voltages to 200 VAC Recommend two digital multimeters 4 Oscilloscope Need X10 and X100 probes Die Load Board with Connectors See Table l for values of loads required The entry on the table for Safe Load Power is the minimum power ratings for the load resistors used 6 Ohmmeter Set Up Procedure Set up as shown in Figure 8 You will want to monitor the input voltage and the output voltage of the regulated bus which is the 45 output with DVM s Also monitor the 45 output with the oscilloscope using 50mv div sensitivity The DVM monitoring the 5 output can also be used to check the other outputs See text of Section III for test points within power supply 47 Servi
12. Hard Disk Expansion Cable from the I O bus card edge of the Model III to this jack Control Out 34 pin Connect one end of a Secondary Hard Disk Expansion Cable to this connector The other end connects to the first secondary drive Data Out A 20 pin Connect one end of the Data Cable from the First secondary drive to this connector Data Out B 20 pin Connect one end of the pata Cable from the second secondary drive to this connector Data Out C 20 pin Connect one end of the Data Cable from the third secondary drive to this connector Filter 5 Meg Hard Disk Service Manual Connecting Secondary Drives The secondary drives are connected to the computer via the primary disk drive The drives must be stacked with the primary drive on top of the secondary drives Locate the secondary hard disk expansion cable Connect one end to the Control In jack of the secondary drive and the other end to the Control Out jack of the previous drive in the chain If you have only two hard disk drives this connector connects to the primary drive If you have another secondary drive connect the second secondary hard disk expansion cable to the Control Out jack and the other end to the Control In jack of the next drive in the chain Locate the data cable Connect one end to the appropriate data jack A for the first secondary drive B for the second and C for the third Connect the other end to the Data In jack on the seconda
13. IO vm RATIO lt waria de aa CM COTE vumm A ar mama mmm m vumm wajan mm omg OED EE eS EE ee t Qasa amiin vm pn Qua sQ abr a vm v matt nm MED s Q s mmm mmm s s s ss AC Power Requirements 50 60 Hz 0 5 Hz 100 115 VAC installations 90 to 127 V 200 230 VAC installations 100 to 253 V Fuse 2 5 at 250 Volts Internal I ro ER omg awanan raum ese ed as ntar ere A vagy vs emt MORA Y AS pong p O ER ARO SER reg A 8 s sihung u manen AD mak wem vd omg gem maran mg ar re c pt a lt s t ng re vam mmm AED MOTTA sami sarahan lt nM vi wt s se A mawang SD wam su ss mg as amiin wu TA CD s mmm ro mp em a A s AAA A AA om KD mmm om emm wm CLAD MC satia vm aaa mmm emm ep xs ep emm mm ANZIO wem vm emm lt xw emm s Min Typ Max Units Vin Range Input Select 115V 90 115 135 Vrms Input Select 230V 198 230 264 Vrms Line Freguency 47 50 60 63 Hz 5 Meg Hard Disk Service Manual Output Voltages Vl 5V 4 95 Sul 5 25 Volts V3 12V 11 4 12 12 6 Volts V4 12V 11 12 15 Volts Output Current Vl 45V 2 50 5 0 Amps V3 12V 75 2 0 Amps V4 12V 005 LO Amps Ripple Voltages Vl 5V 50 mV V3 12V 150 mV V4 12V 150 mV Efficiency 70 Hold Up Time Full Load Low Line 10 mSec Full Load Nom Line 16 mSec Over Voltage Protection 5 80 6 80 volts AA enen MD AI AMD ap mmm remp s vs e w e em s w a a a a s mas AO s mah s malah mmm u za oam ia vad swt a m m w mm lt e t w O s NR s e s m v w s pep m am am lt s s
14. RESET In a few seconds the screen shows a large LDOS logo If the LDOS logo does not appear repeat the above E T 5 Meg Hard Disk Service Manual steps making sure you inserted the diskette properly At the bottom of the screen LDOS asks you for the date Type today s date in the mm dd yy form and press lt ENTER gt For example for June 17 1982 type 06 17 82 SENTER LDOS then displays the name and date of the diskette above the logo It also displays the expanded date below the logo The screen then shows this prompt LDOS Ready Since you ve not yet initialized your Hard Disk System your computer is now operating as a Floppy Disk System the only way it can operate until you initialize it If you have already initialized your Hard Disk System you can remove the START UP diskette created during initialization You only need it to start up or reset To operate the system for floppy disk only hold down the lt CLEAR gt key and press the RESET button You must keep the lt CLEAR gt key down until LDOS Ready appears Model I System Power Down L The LDOS Ready prompt should be the last line on your screen If not press ENTER or exit your program so that it appears Remove all floppy diskettes from their drives Turn off any peripheral equipment Turn off the primary hard disk drive by turning the POWER KEY counterclockwise This also turns off all existing secondary drives Turn off t
15. as the frequency range centered about the VCO free running frequency over which the loop can acquire lock with the incoming data signal The free running frequency of the VCO is always twice that of the RCLK rate In fact RCLK is produced by the VCO through a divide by two counter Ul4 Power for the VCO s internal oscillator as well as for the error amplification filter is supplied from a 78MO5 5 volt regulator This insures good noise separation for these stages from the power supply Error Amplifier Control of the VCO is accomplished by the error amplifier filter and Data Separator chip The error amplifier is a balanced current mirror whose output sources or sinks current to the filter stage Whenever the VCO is running too slow the error amplifier receives pulses from data bits before pulses from the VCO clock This causes the error amplifier to produce pump up pulses to the filter The filter integrates these UP pulses and raises the overall voltage of the voltage control input TP8 to the VCO When the VCO is running too fast the error amplifier produces pump down pulses to the filter There will always be some error present because without pulses of UP and DN the filter would float causing the VCO to drift off center freguency Phase Detector The circuitry which feeds the error amplifier is called the phase detector This consists of several D latches U20 U21 and a delay line U31 The function of this circuit is
16. instruction instead of the normal 5 bit immediate moves provided for by the instruction set All instruction fetches occur late in the second cycle of the preceding instruction This time is marked by the generation of a 65 ns nominal active high pulse calleq MCLK which occurs every instruction MCLK is used to latch data prior to being input on the IO bus to ensure stability during reads MCLK is also used to disqualify read strobes which would otherwise remain true into the second clock cycle of any instruction which does not write to a port There are two more bus control signals produced by the 8X300 Left Bank select LB and Right Bank select RB However due to the implementation of the Fast IO Select logic only RB which is used as the chief enable signal for U17 and U18 is needed Reset Circuit The 8X300 is held reset for approximately 40 milliseconds after initial power on This is accomplished by an RC network R42 and C52 After this power up sequence there are two ways to reset the processor both of which are controlled by the host computer One method of resetting the processor is by resetting of the host i e reset switch which drives the signal HDMR low The other method of resetting the processor is by software control This is accomplished by setting bit D4 of port Cl HEX This latches the signal SFTRESET which in turn triggers a one shot U76 to drive RESET low The one shot duration is set for approxi
17. remembered that prior to an AM there is always a field of zeros all data bits low so the first non zero data bit into the device will always be the most significant bit of the AM HEX Al The CRC device when enabled by the first non zero data bit will shift succeeding data bits into a feedback shift register string with Exclusive or gates tied to the feedback nodes on the first fifth twelfth and sixteenth registers As each RCLK occurs the registers will divide the incoming data and a unique pattern of ones and zeros will appear across the registers When the last bit of an ID or data field is processed the pattern in the registers should be equivalent to the 16 bits appended to the fields during original recording The appended bits are also entered into the CRC device If all of the bits in the appended field are identical to the bits in the registers then the Exclusive or Gates in the register string will have flipped all of the ones to zeros and the CRC will have been satisfied The output of each register stage is tied to a 16 bit comparator which goes true when all of its inputs are zeros The output of the comparator is retimed to remove any decoding slivers and is output as CRCOK The processor can read CRCOK through U61 to see if a CRC error has occurred After the CRC bits are processed the data stream will contain at least one more byte of zeros It is the nature of the CRC polynomial that if no bits are set to ones in
18. the registers and if a constant input of zeros is shifted into the registers no bits will be flipped This provides a convenient latching function for the CRCOK flag which will remain true for at least one byte after the last CRC check byte giving the processor time to read the flag The data clock and BDONE are supplied to the CRC device on a 3 bit mini bus During read operations the serial to parallel device U9 will be sourcing these lines Since the WRITE control line from MAC CNTRL U29 is low and this enables tri state drivers on these lines The 40 5 Meg Hard Disk Service Manual Parallel to Serial device U7 will have its tri state drivers disabled Serial Data Generation The Controller records data on the disk in MFM format In order to produce the proper data format the Controller uses several specialized devices to process the parallel data supplied by the host into a serial MFM data stream The data supplied by the host is temporarily stored in the buffer RAM until the correct sector is located for the data to be written The process of writing is essentially the opposite of reading except that the data separator circuitry is not required and the generation of the MFM data stream is produced by synchronous clocking techniques The functional sections of the serial data generation section are listed below 1 Parallel to Serial conversion U7 2 CRC generation U6 3 MFM and precompensation
19. to provide time windows during which the leading edges of the incoming MFM data can be compared to the leading edges of the VCO clock These windows are approximately 50 nanoseconds in length and are initiated by the leading edge of any data bit as it enters the detector The windows are terminated by the same data bit edge delayed by a net of 50 nanoseconds 60 nanoseconds in the delay line minus approximately 10 nanoseconds in propagation delays When both the delayed data bit and the nearest VCO clock edge arrive at the detector the detector is reset until the next data bit arrives on the MFM data stream The delayed data bit sets its half of the detector latches to produce the VP 35 5 Meg Hard Disk Service Manual pulses The VCO clock edge sets its half of the detector to produce the DN pulse Window Extension Once the VCO has been locked onto the phase of the incoming data the actual separation of data and clocks can occur This is accomplished by using a technique called window extension This technique causes data bits to first have their leading edges shifted into the center of the RCLK half cycles then to have them latched or extended until the next rising edge of the RCLK The shift is accomplished by tapping the data of the Sample on Phase Detector delay line at the 60 nanosecond tap and inverting the VCO clock to the RCLK divider Ul4 The delayed data clocks a pair of latches Ul2 and Ul3 The data lat
20. 2 Load 12 Load VOLTAGE AND RIPPLE SPECIFICATION OUTPUT MIN MAX NO LOAD RIPPLE 128V AC 120V AC 128VAC 95VAC 5 475V 5 25V 50mV P P 12 11 40V 12 60V 150mV P P 12 11 00V 15 00V 150mV P P Applies to resistive load only Not under system operating conditions ice Manual Serv 5 Meg Hard Disk t Boards ircui 9 printed C 12000002002 60000000
21. 89027 8719221 8719209 8896910 8896910 8896910 8789090 8590124 8789597 8769166 8669001 8669002 8659014 8896903 as Radio fhaek 5 Meg Hard Disk Service Manual 11 Schematics L4 12 D4 i AE EA 12 n 1 D2 cu 7 C15 L5 A Wai ii A EER dee ca e A cs Z 01 41 2 L2 png Ll 3 N a SE ni 9 2 H r Y Ta MEME 4 a 2 Ed hm POWER SUPPLY SCHEMATIC DIAGRAM Radio Shaek ESAS IS NR A 63 5 Meg Hard Disk Service Manual TOS ESO ta G os DESCRIPTION T DATE APPROVED LAD WA RDZ hi Og TE c n2 gt RD 2 ne gt 1NTCLK i gt RD 4 2 DI IB Mi bs UL 3G K E RDS gt RD bo 3 RD gt DE IB MCLK pi 1 iOS TR S174 CLR 3 D4 TB A Viii a gt D5 IB dE cac WR A WRZ Hee MAE Da IB AQ E 45 hi2 wR A IA a ean H WRS A A 41 nit eS WEG O7 18 A3 48 na NRT 4 ii Sr 44 AS nk o A RE an d L gt Ab i n 15 i IFDEN IA7 4 A7 IE 3 Ya O HAS c IAB lad SE n g AG AZ al al So 5244 ROG ME ia HOBA 18 gt Ad IB SIORG IB 4 Ze 19 19 DA e HIS 21 HOBA2 k amp gt A7IB RA m m 21 25 HiJOA 4 p gt A4 IB R FIS 148 ME 24 2q _HOBA GIL ND 7 SAGIE EE 10 107 a MBATIN Ny Jarre 2 ok SELODCR E 2T 109 dG IVETA A 10 Yip p pe enon i 1 0 Et B i MED
22. 9008808 q 0098000 e hi gt 0988899 88888000 c c 6 o em m e 9 ee e 00 090 e o Le e 9 ae o 08 o 00888880 aaasa00000 9 gt 8888888 8000085 8900000 Q ae 6 80028080 o 0900620000 o 8855888 e 880998 0088900 5 Meg Hard Disk Service Manual 10 Wiring Diagrams BROYYIU 19 WHITE 5 O e Y 3 mo 6 LUGS AMP 3 550815 2 187 FASTOL BEAU 7000 SERIES BLACK 5 HOUSIUG AUP 206637 4 i au AMP 200038 2 L GREEN A ie GROUUD MP 350981 BLACK 16 STRIPPED f PRE TIUUED UOTE LALL WIRE 18GA STRAUDED UL TYPE 1061 SPARE LUGS AC Wiring Harness Primary Master 4 AMP 8 2000 37 1 WHITE 5 1 3 MOLEX TYPE 09 06 1030 AMP 2 5Z00B3 2 BLACK 5 REF FAN CADLE MOLEX TYPE 0A Ob 1030 PINS AMP Z2OLLIG T AMP 350481 2 NOTES 4 AU WIRE 18 STRANDED UL TYPE 1061 SPARE LUGS A BEAU 10000 SERIES TERMINAL BLOCK AMP 25 06 5 2 FASTON 61 4 USED 5 Meg Hard Disk Service Manual ALL 10 ALL 18 i YELLOYY BLACK H ses AUP 1 480 424 O HOUSIUG 2 USED wE 1514 1 PIUS 8 USED MOLEX 09 50 313 HOUSIUG 08 50 0106 TERMIUALS UOTE ALL WIRE 18 GA SE UL TYPE 1060 EXCEP RED WIRES WHICH ARE Ifo GA e ta a 13 12 DC Power Harness Primary Master ED se se 18 BYG BLACK 19 STRIPPED TIUUED 20GA STRUD RED 19 SPARE LUGS 2 PLACES BEAU 7600 SENESLTERMIUAL
23. AM Addressing The RAM address bus RAO RA9 uniquely addresses one of 1024 memory locations As each counter chip reaches a count of 0 it will set a borrow condition to the next higher counter which will be decremented at the end of the next access to RAM When all bits of the address have been reset the ROVF bit on the last counter U26 will be reset providing overflow status which can be read by the processor on U26 By setting various beginning address values ROVF can be used to mark the end of any RAM access loop from 1 to 1024 bytes in length The controller board uses this function to set sector buffer lengths of 128 256 or 512 bytes Sector Buffering All data read from or written to the disk is passed through the RAM to provide buffering required for asynchronous data transfer between the host and disk The counters are post decremented which means that the effective addresses are stable to the RAM by at least the instruction prior to BD ar 5 Meg Hard Disk Service Manual the actual access This pre selection feature effectively reduces RAM access time to the output enable and propagation time of the RAM for read operations This feature also reduces the width of the minimum WR strobe pulse for write operations RAM Accessing RAM access is initiated by RCS which is the logical or by U59 of RDO and WRO which are generated by the Fast IO decoders U44 and U45 Data to be read from RAM will be placed
24. AN COOLING TAB FASTON FAN 5M S A BEZEL SWITCH SWITCH KEYLOCK SWITCH ON OFF INDICATOR LIGHT BEZEL ASSY DRIVE 5 1 4 HARD HARNESS LAMP MOUNT DRIVE WASHER LOCK 6 SCREW 6 32 X 1 4 PPH DRIVE S A FILTER NUT LOCK 46 32 SCREW 6 32 X 2 F CNTSK SCREW 6 32 X 1 2 SCREW 6 32 X 1 4 THD FM SCREW 6 32 X 1 4 PPH WASHER 6 CLIP CORD 38 DIA TUBING 1 8DX1 2 PCB ASSY CONTROLLER IC P2114 Ul7 Ul8 IC 8X300 MICRO CONT IC 28886 BPROM IC 28886 BPROM U34 PRGMD IC 28886 BPROM IC 28886 BPROM U40 PRGMD IC 28886 BPROM IC 28586 BPROM U41 PRGMD IC WD 1100 01 U9 IC WD 1100 12 U5 IC WD 1100 03 Ull 58 Service Manual 8709332 8569098 8569033 8579003 8790401 8529008 8896620 8719230 8489047 8489048 8469009 8896610 8790202 8709347 8729131 8589018 8569098 8896609 8739010 8579004 8569155 8569126 8569040 8569098 8589018 8559010 8539025 8896130 8042114 8040300 8040086 8896603 8040086 8896602 8040086 8896604 8040111 8041112 8040113 RR KA KA KA KA pp duc vn s a Qs OED em m s s f m wem lt TEE a v vm s vert vm o em vm x ENE wm mm rem mm mmm mmm mm v mm emm MENER om WEE em s mmm MEE emp e v EE e es s s s s emm warih wanan 90 var emt mt weg s lt s ms wem ven vum em vm emm we wm am eme wem wem vun ss wm wem 0 SOURED vm wm vm wm emm wem vnan mmm MAKER op emm emm vm zem pm emm em em em mp eem em ep em m
25. BLOCK AMP 9 3 50815 2 FASTOL 187 14 USED BUP 3 480424 0 HOUSILG AUP 615141 PILIS UOTE LALL WIRE 18GA STRAUDED UULESS UOTED OTHERWISE P MOLEX 22 01 dode t 308 50 015 PIUS DC Power Harness Secondary Slave JUMPER RANGE JUMPER 2 00 ORANGE NOTES STRIPPED PRE TINNED WIR MOLEN PART NO 22 04 dog HOoWING 06 50 0119 Fus 5 Lamp Driver Wiring Harness Primary 5 Meg Hard Disk Service Manual CABLE 1 PIN 1 BLUE 10 PIN 2 NE PIN 3 ORANGE 14 PIN 4 BROWN 15 CABLE 1 MOLEX 22 01 ES ES rei WA ORANGE BLUE BROWN TIE WRAP Es LA SE ETN EES MW 4 TINNED gt o LA Gres N 25 STRIPPED MEN N B 4 HE F REF MOLEX 22 01 3067 CABLE 22 CABLE 2 V PIN f BLACK PIN 2 YELLOW LED Driver Board Harness Secondary e Radio Shaek PEA 56 5 Meg Hard Disk 11 Parts Lists PRODUCT DESCRIPTION HARD DISK 5 1 4 CAT NO 26 1130 AAA A A A D D A A D D E ER o id am sawa wem em em maa am A a anan A vg mm D am a a Ms aan wem we mm a RE OD wm Q s rr s Ee vg em Sonor T ua ee aert di s s IS Ka Ka Ka L wata vg vm ama m aan s mt sas 09 m vm mmm wem wm EEE EEE ms A A a ss i ss ss a mp e omg s mm aan A emp NOM bK N Kd Oh 0 DESCRIPTION MANUAL START UP REFERENCE MANUAL ADDENDUM BINDER MANUAL SPLINE INSERT DISKETTE SYSTEM 5M F A DISKETTE BOOT 5M F A HOLDER VINYL 5 1 4 DISKETTE CARD S
26. CLIP GRD SCREW 8 32X3 8 WASHER 8 FLAT LOGO STRIP BEZEL COVER TOP S A LABEL WARRANTY NOT BAG 6X15X22 LABEL LINE TERMINATOR 59 Service Manual 8040114 8040115 8789732 8896600 8896600 8896600 8896600 8896600 8729132 8539026 8790043 8569098 8589018 8569153 8589072 8569003 8896608 8709334 8569098 8589018 8759131 8590109 8709324 8729123 8559040 8569107 8589027 8719221 8719209 8898403 8789090 8590124 8789597 OTY DESCRIPTION mn n NN em mm man eg o mm mp ss ass rs es e em es is ren ep em za mm vm CARE lt om EE emm Mat vm mm em wm Q om em s s s vm wm emm mm t WEEN s a em wm ve we ve ven vm we ww sm N s Pm rn wasa rr em em em oe em rem em omg vm GARD em es zm emm mmm zg emm wm mm sem om r m cawan om rm am mm zum Q mm emm re am OD wm om wm vom mm ws wem wem ve ve vm mm mm wm wen vm ve vm vm vm ss Zem 02 e em em em mmm em om en e e mp em rm emm mm Q mp remm mm wm op I vumm wem wem s mm Am UND PCB M I HD ADAPTER RESISTOR 1K OHM 1 4 WATT 5 TRANSISTOR 2N2222 CABLE M I HD PC BOARD M1 ADPTR W CABLE TAPE FOAM 1 4X1X1 ENCLOSURE LABEL ADAPTER ADAPTER F A SUPPLEMENT MODEL I DISKETTE INTLATN SYS S A DISKETTE XTRA S A DISKETTE OPRTR SYS S A FOAM FOAM DIE CUT 26 1132 CARTON INDIVIDUAL CABLE EXT DATA 20POS CABLE EXT CNTRL 34POS CORD 8 POWER CABLE INT DATA 20 POS BOX ACCESSORIES LABEL ACCESSORY KIT
27. MAC CNTRL port U29 This signal will cause the CRC generator U6 to begin dumping the computed CRC onto the NRZ data stream at the conclusion of the last data byte synchronized with the BDONE signal In this fashion the device is able to append the proper CRC information to the end of a field of data lBLA is maintained at a low state for the duration of the unloading process which lasts for 16 bit times During the unloading process the CRC registers back fill with zeros This feature is handy because by leaving 1BLA low for additional time zeros will always be written after the CRC which is a requirement for the proper operation of 42 5 Meg Hard Disk Service Manual the CRC device during read operations The NRZ data with CRC appended is then sent to the MFM generator device U5 MFM Generation The conversion from NRZ write data to MFM write data takes place in the MFM Precompensation device U5 This device accepts NRZ data and a complimentary WCLK and produces MFM data and clocks by sending the data through circuitry which decides when and where to write clocks on the data stream under the MFM encoding rules The proper encoding of the data into MFM requires the device to apply three rules to the data 1 If the current data cell contains a data bit no clock bit will be generated 2 If the previous data cell contained a data bit no clock bit will be generated 3 If the previous data cell and th
28. OFTWARE REG MANUAL ASSY LABEL TOP H D CONN CORD 8 POWER CABLE EXT BAG 4 1 2 X 4 X 2 MIL KEY BOX ACCESSORIES LABEL ACCESSORY KIT ACCESSORY HDM CASE BOTTOM PLUG 2 1 2 DIA LABEL FCC PART 15 LABEL FCC ID HDM LABEL S N 26 1130 FOOT WASHER 1 2 O D FASTENER 10 X 1 2 PLATE COVER SCREW 4X1 4 PPH CABLE INT CNTRL CABLE INT CNTRLR SCREW 6 X 5 16 SCREW 4 40 X 3 4 PPH NUT LOCK 4 40 WASHER STAR 4 BI Service Manual PART NUMBER rr EED am lt et vm emm O am en aana s gp om saat gang W s ai eed IO mp EET OCA wem em en em wes 8749389 8749394 8759191 8754082 8789785 8896621 8896907 8719082 8759177 8896613 8789613 8709057 8709341 8590056 8769164 8789817 8896612 8729124 8729148 8789287 8789772 8789775 8590123 8589074 8569062 8729147 8569120 8709330 8709331 8569130 8569059 8579003 8589075 MUETRA ee em MEER mem wis wm moug Wm CR wt wt EE am es END GNU q ses o om mah om mt mt we anak vm oft om sm a gp ov Server s m ss ts em wem wm Wants at van mmm wem mm lt s ep mp sss emm women wer wat vm gen wem wem o CANA vu om mm vm mon mem om mt em ag s t wg mm wem mm wu gn emp wem om o samata wat za emm mme eem mama een em en mp um open wm AMTNGR wem wm vw e oa wt xs a mt wem ER em VE ms op om at em we wett att opt ve E vk emt mm samia am tr am wm wt vm em aaa om vm mm em mt s MIND emp oeh emp wm mmm ver oam t w ege
29. U5 Parallel to Serial Conversion Parallel data is converted into a serial NRZ data stream by the parallel to serial device U7 The processor enables this conversion by lowering the WRITE signal on MAC CNTRL U29 WRITE causes the tri state buffers present on the parallel to serial device to become active supplying the CRC device with data clocks and BDONE strobes The processor presents parallel data on the IO bus along with the WR4 write strobe which latches the data into the parallel port on the BDONE Inside the parallel to serial device the parallel latches are loaded into a serial shift register on every eighth WCLK transition As the data is transferred to the shift registers the BDONE status flag is set The processor reads this flag through U6l to determine when to write the next parallel byte to the device The timing of the parallel accesses is at a rate one eighth that the bit rate of the NRZ data stream The output of the last register in the shift string is brought out of the device as a NRZ serial data stream The shifting clock is also brought out as SHFTCLK to be used as the clock for the CRC device ae WE ue 5 Meg Hard Disk Service Manual Whenever it is desired to write a repetitive string of identical data bytes the processor can simply ignore the BDONE flag and permit the device to reload the data from its latches over and over again for as long as required to generate the field This featu
30. a em w Ma a Q om m h Qam om st s Q sn MEE wm Ma eP em watan x ERED w ws mm a pm anat samt sa lt Fom em MEN M M Mol ls Ml mt s s vm G M d dll M pt or om vom ll m s w diii lE ot vm Qm ng mg ew QG et emm eme mn mn wm wS sss wem emt emt opt mb wot wm O s sm in s ore a geg sas u on wem mp qa oe a mawan aian aun O mk o n A eg s emt sm Q lt s a ws wa weg m s AMEN wat Qm weg a w Am s e s om met emt mmm wm P N E pP WASHER 4 STAR FAN COOLING TAB FASTON FAN 5M S A SCREW 6 32 X 2 FCNTR FILTER NUT 46 32 LOCK HARNESS AC SLV SCREW 44 40 X 1 2 PPH NUT LOCK 44 40 OPO30 5M HDS BEZEL SWITCH INDICATOR PWR ON SWITCH ON OFF INDICATOR LIGHT BEZEL ASSY HARNESS DC ASSY RELAY l2V 70MA SCREW 46 32 X 1 2 SCREW 46 32 X 1 4 SCREW 6 32 X 1 4 THD FM WASHER 6 LOCK SCREW 6 32 X 3 8 OPO40 5M HDS CLIP CORD 38 DIA TUBING 1 8 DIA X 1 2 OPO50 5M HDS SOLDER DRIVE 5 1 4 HARD HARNESS LED DRIVER HARNESS RELAY MOUNT DRIVE WASHER 6 LOCK SCREW 6 32 X 1 4 PPH DRIVE 5M HDS S A POWER SUPPLY SCREW 6 32 X 1 4 PPH WASHER 6 LOCK SCREW 6 32X1 PPH ZINC NUT 6 32 KEPS PCB DRIVER F A 5M MAP MEDIA ERROR Radio Shaek 61 Service Manual 8589075 8896900 8790401 8529008 8896620 8569155 8739010 8579004 8709333 8569033 8579003 8896902 8719230 8469011 8489048 8469009 8896611 8709335
31. and enter into a re try condition If the controller cannot get correct data after attempting to read it 16 times the read will be aborted and the host informed that the data in the buffer is questionable The Controller board uses the same device to generate and check CRC s for data being written to or read from the disk The polynomial used is 16 12 5 X X X 1 commonly called the CRC CCITT polynomial The processor polls the condition of the DRUN circuitry during read operations When DRUN is true it begins to search for an address mark Once the AM is located the processor will start to read parallel data which has been converted from NRZ data by the serial to parallel device The processor will terminate this activity when it has received the information it is looking for or if an error is detected While the processor is reading the parallel data the CRC generator is reconstructing the CRC check value The CRC generator is initialized by the processor setting CRCIZ low 39 5 Meg Hard Disk Service Manual for at least 250 nanoseconds during the search for the AM CRCIZ is originated on the MAC CNTRL port U29 Upon receiving the CRCIZ signal the CRC generator checker will preset all 16 of its internal polynomial division shift registers to logic ones and arm an internal latch which will enable the checking function on the leading edge of the first non zero data to enter the device It should be
32. applied to the input of the delay line and depending on which of the three precompensation signals is present the U37 selects a different tap on the delay line Nominal data is actually tapped from the second tap early data from the first and late data from the third From U37 the MFMW data is sent to the input of a quad driver U35 or U36 where it is converted to a differential form and then sent to the disk drive The AND OR INVERT gate U37 has one other function If the controller is not writing the WGI Write Gate Internal signal will be low This is inverted by U19 and applied to the fourth section of U37 This resulting high input effectively inhibits the gate from accepting MFMW data Host Interface The interface bus to the controller is pin for pin compatible with the standard Model III I O port This 44 5 Meg Hard Disk Service Manual includes an 8 bit bidirectional data bus U70 and 8 address lines U71 For systems using interrupts and or DMA the controller also provides Interrupt Request HDBINTRO and Data Request HDBDRQ Accessing the controller is like other I O devices Address decoding is done on the controller board by U69 This decode can be jumpered to recognize four different address ranges Standard setting is jumpered from 17 to 19 which utilizes port locations CO to CF HEX Further decoding to allow access of specific ports is done by U66 U67 and U68 Data bus direction is d
33. arallel device also include SHFTCLK and DOUT SHFTCLK is actually RCLK propagated through the device DOUT is the Q output of the last stage of the shift register string DOUT and SHFTCLK are routed to the CRC generator checker device and also are tri stated 38 5 Meg Hard Disk Service Manual along with BDONE These signals are active only when WRITE is high which indicates a read mode of operation CRC Checking Circuit Data recorded on magnetic media is prone to several types of errors which could render data unusable if some form of error detection were not employed Therefore a cyclic redundancy check CRC is performed on all data transfers from the disk The CRC is an error detection code consisting of 16 additional bits which are appended to every ID field and data field on the disk These bits are produced by dividing the data stream serially with a large polynomial This division produces a unique 16 bit value for any information passed through the CRC generator As data is being read from the disk the CRC generator U6 re computes the original CRC bits The value in the CRC generator must always be zero after the last two bytes which contain the orginal recorded CRC are read When this happens the data was correctly read and the controller will not flag an error If however the CRC generator is not zeroed after it has checked all bytes of the recorded data the controller will flag the data as erroneous
34. as the result of one bit on the disk a flux reversal influencing an adjacent bit The effect is to shift the leading edge of both bits closer together or further apart than recorded The net result is that enough jitter is added to the data recorded on the inside tracks to make them harder to recover without error In any event there is a method called write precompensation which can be applied to reduce the effect of this shift on the data Write Precompensation is a way of predicting which direction a particular bit will be shifted and intentionally writing that bit out of position in the opposite direction to the expected shift This is done by examining the next two data bits the last bits and the present bits to be written and producing three signals depending on what these bits are The three signals are EARLY LATE and NOM They are used in conjunction with a delay line to cause the leading edge of a data clock bit to be written early late or on time As with MFMW these signals are subject to decoding slivers and must be retimed by Ul6 The processor can enable or disable the generation of these signals by controlling the RWC Reduce Write Current line from U52 When RWC is high precompensation is in effect When RWC is low no precompensation is generated and the NOM output of the device is held true The delay line U31 actually performs the precompensation with the help of an AND OR INVERT gate U37 The MFMW pulses are
35. atch At the instant AM occurs the exact relationship between data and clocks is known It is also known that data is being clocked by RCLK so CLKS can actually be discarded their purpose was in detecting AM The AMDET signal is used as a synchronization signal to start subsequent conversion circuitry The AMDET signal remains true until the processor again de asserts the Search control line Serial to Parallel Conversion After an AM has been detected the serial to parallel convertor U9 takes over NRZ data and RCLK are used to shift data bits into an 8 bit serial to parallel shift register As each bit is shifted a divide by 8 counter circuit is incremented After every eighth bit of data is shifted the counter produces an overflow pulse marking byte boundaries in the serial data stream The overflow bit from the counter resets the counter clocks the data from the shift register into an 8 bit parallel latch and sets a tri state flag register called BDONE The flag can be read by the processor to see if any converted data is ready to be read from the latches When the processor sees BDONE in the true state it services the device by gating data onto the IO bus using read strobe 4 RD4 in conjunction with a tri state buffer U8 The act of reading the latches also clears off the pending BDONE flag As successive bytes are processed the BDONE is serviced by the processor as data becomes available Outputs from the serial to p
36. ate the system for floppy disk only hold down the CLEAR key and press the RESET button You must keep the lt CLEAR gt key down until LDOS Ready appears Model III System Power Down s VI 5 Meg Hard Disk Service Manual The LDOS Ready prompt should be the last line on your screen If not press lt ENTER gt or exit your program so that it appears Remove all floppy diskettes from their drives Turn off any peripheral equipment Turn off the hard disk drive by turning the power key on the primary drive counterclockwise This turns off all the drives Turn off the computer Model I System Power Up These are the steps to power up and power down the Model I Hard Disk System Please use these steps Ls Dis Make sure all floppy diskette drives are empty Turn on all peripheral equipment such as printer and floppy diskette drives Turn on the primary hard drive by turning the POWER KEY clockwise This also turns on all existing secondary drives Wait for the power lights on all the secondary drives to come on Turn the Expansion Interface ON Turn the CPU Keyboard ON Wait until all floppy disk drive motors stop then carefully insert the HARD DISK OPERATING SYSTEM INITIALIZATION diskette or the START UP diskette in Drive 0 The START UP diskette is a modified copy of your INITIALIZATION diskette created during initialization Initialization procedures are described later in this supplement Press
37. ce Manual 5 Meg Hard Disk POWER SUPPLY kel ISOLATION id d S woo Euro transronmen 45V mme AC F INPUT ster 12V feme Figure 8 Test Set Up Section II Visual Inspection Check power supply for any broken burned or obviously damaged components Visually check fuse resistor if any question check with ohmmeter LOAD BOARD VALUES SAFE MAX SAFE OUTPUT MIN LOAD LOAD R LOAD POWER LOAD LOAD R LOAD POWER 5 0 45A 11 11 ohm 5W 2 5A 2 ohm 25W 12 1 3A 0 40 ohm 8W 2 02A 24 24 ohm 50W 12 0 0 0 0 120 ohm 2W Table 1 Load Board Values Start Up Load power supply with minimum load as specified om Table 1 Bring power up slowly with Variable Transformer while monitoring 5 output with scope and DVM Supply should start with approximately 40 60 VAC applied and should regulate when 95 VAC is reached If output has reached 5 volts do a Radio Shaek EEE 40 5 Meg Hard Disk Service Manual performance test as shown in Section IV If there is no output refer to Section III Section III NO OUTPUT A Check Fusable Resistor If fusable resistor is blown replace it but do not apply power until cause of failure is found Preliminary Check on Major Primary Components Check diode bridge BR1 power transistor T2 and catch diode D3 for shorted junctions If any component is founded shorted replace it Primary Check on Major Secondary Components Using
38. ch has its D input and CLEAR connected to RCLK and the clock latch has its D input and CLEAR connected to RCLK If an MFM data bit enters the latches while RCLK is high it will be extended as a data bit If RCLK is high it will be extended as a clock bit Due to this extension technique bits can jitter approximately one fourth the RCLK period without being lost The output of each latch is then further extended by being fed directly into the second half of the latches and clocked on alternate edges of RCLK The final outputs of the data extension separation stage are two separate signals one signal consists solely of NRZ non return to zero data and the other of NRZ non return to zero clocks The NRZ data and clocks are finally in a form suitable for processing by subsequent circuitry on the Controller board Clock Detection Due to the nature of MFM data encoding it is impossible to know exactly if MFM bits are data or clocks This ambiguity results in having to create circuitry to assume that bits on RCLK are actually data bits until the VCO is locked on and a unique data clock pattern is detected This is accomplished by holding the VCO to RCLK divider Ul4 reset until it is fairly certain that bits on the data stream are actually clocks belonging to a field of zero data Once this assessment has been made the processor releases the AM detector Ull by raising the SRCH signal This signal releases a latch Ull which w
39. cuitry which processes incoming MFM data from the drive by a method called data S s 5 Meg Hard Disk Service Manual separation Here some background information may be helpful In order to provide maximum data recording density and therefore maximum storage efficiency data is recorded on the disk uSing a Modified Frequency Modulation MFM technique This technique requires clock bits to be recorded only when two successive data bits are missing in the serial data stream This reduces the total number of bits required to record a given amount of information on the disk This results in an effective doubling of the amount of the data capacity hence the term double density Because clock bits are not recorded with every data bit cell circuitry that can remain in sync with data during the absence of clock bits is required Synchronous decoding of MFM data streams requires the decoder circuitry to synthesize clock bits when they are present This is accomplished by using a phase locked oscillator employing an error amplifier filter to sync onto and hold a specific phase relationship at the data and clock bits in the data stream The synthesized clock called RCLK can then be used to separate data bits from clock bits and to shift the resultant serial data into registers for parallelization into bytes Incoming Data Selection Serial data is input from up to four radially connected drives via a quad RS 422 differential
40. e present data cell are vacant a clock bit will be produced in the current clock cell The terms data cell and clock cell are defined by the state of WCLK While WCLK is low 1t is a data cell and while high it is a clock cell It can be seen then that both clock and data cells are one half the period of WCLK or 100 nanoseconds Also note that by the rules started above a clock and data bit can never occur within the same WCLK period and legal spacings for bits can be one one and a half or two times the WCLK period only The rules are implemented within the device by shift registers that hold the next two last and present data bits and combinational logic The state of WCLK is considered and the appropriate bit cells are filled and combined on the MFMW output line of the device This line is subject to decoding slivers so it is run through a re timing latch Ul6 to clean it up Write Precompensation The MFM data stream is now totally compatible with the recording rules and may be sent to suitable line drivers for transmission to the drive except for one modification Due to the decreasing radius on the physical surface of the disk the inside tracks have less circumference and therefore exhibit an increase in recording flux density over the outside tracks This increase in flux density aggravates a problem in magnetic recording known as dynamic bit shift 43 5 Meg Hard Disk Service Manual Dynamic bit shift occurs
41. etermined by U56 using standard bus as well as decoded signals Wait Enable The generation of the WAIT signal is controlled by a bit in the MAC latch U29 called Wait Enable WAEN If the controller is ready to accept random access to its task file WAEN will be asserted After WAEN is clocked through a latch U43 to insure WAIT is not asserted during a bus access in progress DCRCS BIC or BOC in some applications causes WAIT to be asserted to the bus The WAIT line is released on the trailing edge of any Read or Write Strobe to the communications latch U60 This release is caused by the logical OR of RDG and WRG on U38 which presets the wait latch U43 to a non wait request condition Interrupts and DRO s The controller produces INTRQ to signal the end of all disk operations and DRQ s to signal data ready to DMA controllers INTRQ and DRQ originate on the MFM generator U5 as an auxiliary function of that chip The INTRQ signal is set using INTCLK and the the DRQ signal is set using DROCLK both of which are produced by U44 Interrupts are cleared by CSAC a 200 nanosecond version of the CSAC signal and A0 Al whenever the host reads the status register issues a command or accesses the sector number register Data requests DRQ s are cleared when the host accesses the data or cylinder low registers DRO s will be reissued for each byte to be transferred During power on or Master Resets MR INTRO is set and
42. f 2 times RCLK Any variations in this rate due to variations in disk rotational speed must be compensated for by the VCO but instantaneous shifts in data due to the effects of adjacent bit cells on the disk and minor noise must be ignored Also the response of the VCO must be adjusted to effectively ride over missing clock bits which occur as a result of MFM recoding technique The resultant compromise between response and reject requirements of the VCO cause the VCO to have a tendency to become locked onto harmonics of the data rate rather easily This is likely to occur if the VCO is connected to a data stream over a field of data which has data bits spaced at one and a half or two times the actual RCLK time intervals To provide protection against this undesirable condition the VCO is always held locked onto a stable clock running at two times the RCLK frequency whenever the controller is not actually reading data Furthermore great care is taken to switch in read data to the VCO error detector only when it is known that the data stream frequency is equal to the RCLK frequency This can occur only when the data is a solid stream of all ones or all zeros High Frequency Detector The switching function is initiated immediately after RGATE goes true and will only switch read data into the VCO after 16 consecutive ones or zeros high frequency are detected by a one shot Ul and counter U2 connected directly to the raw MFM data The one
43. g emp rg mg OTE emm maqa mm wem mg sm emt wm wg emp ER geg D mp r em pm vn mn ve vg mm vumm em pm wem wm mm ven em vm pm mmm mmm mmm om vm emm mg vam mm mm mm om mm em zm em o om mmm es e eg lt em wanan m em s ss m mm mam um s as as qa AMMER eh A vom mn WEE wem vumm rem m vr wem vm A zm MEET un mm OTD vm e em mm WEER lt emm zeg ep lt rem eg s ep e eg EER s s s em eman wam wm ven wu CAMS mn wem w wm a v a m m lt n s lt m em s a vumm am wenn vm wm AMAT og m lt s vm WEER mmm CAMIS e zm zem app zem mmm mem em mm em em ep em em em en s eg e An vm vn um ma vu vm x lt lt s um s r f wal ve OVNER lt w MEE s emm ER lt emm WEE lt emm lt mm Q em mm vm lt em mm mm mm s VEER s OE Q lt em EED em s ER v cre EE EE EE d Ae ven wa wem une ve mg vm vu wm vm vm m f vm s s s s s s s s s s vumm mm mmm zum mmm emm mmm lt mmm mm mm vm om emm em em reg s WER mm s ER es e es eee m aem e TE TEE MANUAL SERVICE 5 Meg Hard Disk IC WD 1100 04 U6 IC WD 1100 05 U7 LABEL CONTROL S N ASSEMBLY VISUAL TESTING REPAIR PCB CONTROLLER 5M F A SHIELD POWER SUPPLY INSULATOR POWER SUPPLY SCREW 6 32 X 1 4 PPH WASHER LOCK SCREW 10 X 1 4 PH WASHER 141 1DX 167 OD SCREW 6 32X3 8 PPH SHIELD PCB S A HARNESS DC MSTR SCREW 6 32X1 4 PPH WASHER 6 LOCK MAP MEDIA ERROR HOLDER PLASTIC MAP CABLE INT DATA MSTR COVER TOP
44. he first ten address lines IAO through IA9 limiting onboard program storage to 1K words 5 Meg Hard Disk Service Manual Program data is input to the 8X300 U30 on the Instruction Data bus IAO IA130 which is capable of directly accessing 8K words of program storage however the controller uses only the first ten address lines IAO through IA9 limiting onboard program storage to 1K words Fast IO Select An extension byte has been added onto the instruction data memory to provide port access decoding on an instruction by instruction basis This Fast IO Select byte is not processed by the 8X300 but it is decoded by auxiliary hardware U39 U44 U45 to provide eight read strobes and eight write strobes which route data to the various devices distributed along the interface vector bus The Fast IO byte is latched into a 6 bit latch U39 trailing edge of MCLK to ensure that the data remains stable during the entire instruction This data selects a read strobe and eight write strobes which route data to the various devices distributed along the interface vector bus The Fast IO byte is latched into a 6 bit latch U39 trailing edge of MCLK to ensure that the data remains stable during the entire instructions This data selects a read strobe and a write strobe through two l of 8 decoders U44 and U45 which are alternately enabled by the WC control strobe produced by the 8X300 THe read strobe decoder U45 is always d
45. he Expansion Interface Turn off the CPU Keyboard 9 2 22 5 Meg Hard Disk Service Manual 5 Replacement Procedures Replacement procedures contained in this manual are limited to case disassembly removal and replacement of subassemblies and case assembly Before beginning repair disconnect all external cables from the rear connector panel pisassembly ba Remove the top row of screws 3 from the rear panel and lift off the case Za To remove the hard disk controller board remove all cables from the board data cables hard disk expansion cable controller connecting cables power harness and lamp controller harness NOTE At the time of disassembly be sure that the nylon washer on center stand off is saved for reassembly de To remove the hard disk power supply remove the 4 screws which secure the power supply mount and shield to the bottom of the unit and lift off the cover Loosen all cables Disconnect the power harness from the drive unit Remove the six screws which hold the power supply board Reassembly I Fasten the power supply in the bottom of the unit by using 4 6 screws and 2 10 screws Reconnect the power cables Le Replace the pover supply shield and mount and fasten it using 4 6 screws Reconnect the power harness on drive Position the clear insulating sheet on the power supply mount and shield 34 Be sure and replace nylon washer between the hard disk controller boa
46. he card edge end to the card edge connector of the Hard Disk Expansion Cable 50 pin The Hard Disk Expansion Cable should exit the bottom of the connector 4 Connect the other end of the Hard Disk Expansion Cable to the COMPUTER IN connector of the primary hard drive The cable should exit towards the bottom of the connector The primary hard disk drive is now connected gt TB a 5 Meg Hard Disk Service Manual 4 Power Up and Power Down Model III System Power Up 1 23 Make sure all power is OFF and all floppy diskette drives are empty Turn on all peripheral equipment such as a printer or additional floppy diskette drives Turn on the primary hard drive by turning the POWER KEY clockwise This also turns on all secondary drives All secondary drives power lights should come on Turn the computer ON Insert either the INITIALIZATION diskette or the START UP diskette in floppy Drive 0 Press RESET Ina few seconds the screen shows a large LDOS logo If the LDOS logo does not appear repeat the above steps making sure you inserted the diskette properly The screen then shows this prompt LDOS Ready Since you ve not yet initialized your Hard Disk System the computer is now operating as a Floppy Disk System the only way it can operate until you initialize it If you ve initialized the Hard Disk System you can remove the START UP diskette You only need it to start up or reset To oper
47. ill remove DHOLD from the RCLK divider Ull on the next rising edge of a MFM data 36 5 Meg Hard Disk Service Manual bit so that CLOCKS will be on the RCLK phase and DATA will be on the RCLK phase The processor makes its assessment of the state of the data stream solely on the occurrence of a significant run of zeros which is detected by the one shot UL in the DRUN circuit Once released the phase of RCLK vs data and clocks will remain stable throughout the read of an ID field or data field Whenever SRCH is dropped the VCO to RCLK divider is once again reset and no RCLKS are produced Data Conversion and Checking MFM data which has been separated to form NRZ data and clocks is processed through specialized circuitry to prepare it for parallel processing by the 8X300 This processing consists of three functional circuits 1 AM detection Ull 2 Serial to Parallel conversion U9 3 CRC checking circuit U6 Each function will be discussed separately but bear in mind that many interdependencies exist AM Detection As previously stated it is impossible to know whether serial data bits are actually data or clock bits by just looking at the data stream Furthermore it is equally impossible to determine byte boundaries The problem is solved by a uniquely recorded data clock pattern called an Address Mark AM The AM consists of a data pattern of HEX Al with a missing clock pattern of HEX 0A Normall
48. isqualified at the end of instructions by MCLK MCLK prime a delayed copy of MCLK to provide edges on read strobes during sequential read operations from various ports This delay compensates for timing races through the Fast IO latch U39 and the control signals Because each decoder has a unique input it is possible to select any read port with any write port during each instruction Data is transferred between the processor and its ports on a separate 8 bit bus called the IO bus This bus is active low It must be noted that this bus is in no way related to the instruction data bus and should be thought of as simply an 8 bit bidirectional IO bus of the 8X300 In fact it has been renamed as IOO 107 to reflect this distinction Internal Bus Control Several bus control signals are produced by the 8X300 to identify and strobe the data on the IO bus Write Control 28 5 Meg Hard Disk Service Manual WC is a signal which determines the direction of the data to and from peripherals When WC is false during the first half cycle data is being input to the 8X300 from the IO bus When WC is true during the second half cycle data is being output to the IO bus from the 8X300 Select Control SC becomes active during the second half cycle instead of WC if the IO bus contains an 8 bit IO address the WC and SC signals are combined by a NOR gate U33 to initiate all accesses from the 8X300 to any output port within one
49. mately 100 u sec pulse width RESET is used to clear the drive control latches U62 and U52 and the host interface WAIT U43 Processor Power Supply Power is supplied to the 8X300 from the 5 volt Vcc power bus Due to the internal operation of the 8X300 an on chip DO 5 Meg Hard Disk Service Manual voltage reference is provided to produce bias to an external pass transistor 02 which drops Vcc to the 8X300 to approximately 3 volts All signals into and out of the 8X300 are internally level shifted to be TTL compatible Read and Write Ports Throughout the circuit output ports are formed by D type latches using write strobes WRO WR7 to latch data into the ports Reading of ports is universally accomplished by using read strobes RDO RD2 RD4 RD6 that enable selected tri state output devices on the I O bus Additionally two read strobes are used to clock the host DRO and INTRQ latches U5 and one read strobe is left unused as a dummy port for glitch free operation of the Fast IO port decoders Read Write Memory Since the 8X300 does not permit data to be saved or retrieved from dedicated program storage RAM must be installed on the IO bus RAM must be accessed just like other port accesses via the IO bus by I0 instructions To provide for addressing the RAM three latch counters U26 U27 U28 are connected to the IO bus to receive and store addresses required to access the RAM U17 U18 R
50. n ep sep ep n we vom ep mamaqa AN TERE raont eg N EER ot wm vm em LE OE ARE ama ss s a ant m wh wt emt wg mt mp mt wt at om ert em wm E em eem em vam vm dii iie met spar mrs mn Sab em JE me lt om vw par emt emt or em ru zem ew vu at wm mn mm gem emt vm emp we Leen wem en ver nina mt st em wa t em ve vam emm Em Em w en zm wen em en wem ses 9402 wm RAAD ep vm emp ve 18 emm wan en eum gt wn eat s om vom aaa an MEER way rms wat d m wem am men wem opp ER Et mem ot wama van est emt wg a eet 0 at wa wm oC 900 op a em mm wem m et m s se gem emm emm saten wm wiar ms w wat EE mmm br wem Em og emm Q Qa emt vinh ms tt ss at wem man 0 atan vn sg rett wacan sa For o ve mm MOER ven H w mem WREED mmm EED wen vm am aam emm em wm wm IL mC ween wan we emm emm I O wem emm mmm mmm emt oe mmh emt EED emm iss m s E em vom w emt em on wm P mp wana engt Qm emp emm emt its mmm or emm t ver emt zsm va ven wm em J lt emp s i ap gp wun emp se vp vg wm A A om XI ERWEE emm mm m AER ent wan og om gh wm va lH ors s d lb omg am vam ML a mp 089 ep sem eat em m sakan s m mama m emm mm ue att om emt ven pm een mg s s dnd SWD PE M P A em om lt vm Ae TE RE OE EER vam emm wm mm E A9 satak 0 vm raen wt Fo ent i Jm En MES QQ em emm vam ap om mt fr m Q aaa ve am omg om app op emm am mes La 5 Meg Hard Disk HARNESS AC MSTR SCREW 6 32 X 1 4 GRD SCREW 4 40 X 1 2 PPH NUT LOCK 4 40 F
51. nd low power Schottky devices All I O connections are made using standard ribbon cable connectors Standard pin out configurations for disk interface connectors permit direct pin for pin connections to the drives All host to disk data transfers are buffered by onboard RAM to achieve totally asynchronous transfers to and from the disk by the host The disk controller is built around five basic sections Processor Functions All functions of the controller are ultimately disciplined by the onboard processor Due to the high data rates associated with hard disk drives a processor capable of extremely fast execution speed is required for processing of data and controlling machine functions within the circuitry The processor used is the 8X300 a bipolar micro controller particularly well suited for handling data efficiently at high rates The 8X300 operates at a basic clock rate of 8MHz and performs all operations within two clock cycles giving it a speed of 4 MIPSS Million Instructions Per Second or one instruction executed every 250 nanoseconds The architecture of the processor is different from most popular microprocessors in that no common data or address bus is provided to be shared by RAM ROM or peripheral devices Instructions are fetched from ROM via a dedicated instruction address and data bus The Instruction Address bus IAO IA13 is capable of directly accessing 8K words of program storage however the controller uses only t
52. nnector in the middle See Figure 4 5 Meg Hard Disk Service Manual Din Plug Modification Buffered Cable Modification cS Figure 4 Expansion Interface Keyboard with Buffered Modification If the computer does not have these cables then you must look inside the Expansion Interface through the bottom cover Look through the vents on the bottom cover for two rows of eight memory chip sockets The sockets may or may not contain memory chips If the ROWS of sockets run long ways in the interface parallel to the keyboard then the computer is buffered and is ready to be connected to the hard disk See Figure 5 Manual Service 5 Meg Hard Disk Buffered Expansion Interface as Viewed From the Bottom Figure 5 o o llustration below lar to the keyboard 1 lcu See the t buffered If the ROWS of sockets run perpend is no the computer ud q Figure 6 Non buffered Expansion Interface Viewed From the Bottom 5 Meg Hard Disk Service Manual Figure 7 Connecting the Hard Disk to Your Model I La Locate the Model I Adapter Cable One end has a connector 40 pin The other end has a black box with a card edge exiting it 25 Connect the 40 pin connector the end with the cable to the Bus Extension port also called screen printer port of your Expansion Interface The cable should exit towards the bottom of the expansion interface 9v Connect t
53. ohmmeter from output commmon to each output with output loads disconnected check for shorted rectifiers or capacitors If 5 output is shorted also check crowbar SCR SCR1 and zener Z1 Check for B Set power supply and attach X100 scope probe ground to end of R10 nearest DB1 Slowly turn up power and check for B on end of R9 nearest mounting hole With input at 95 VAC this point should be between 120 140 VDC If this is not correct check BRl and if necessary check R21 D2 and finally input capacitors C5 and C6 Check 02 Waveforms Using X100 probe on heatsink of 02 check collector waveform The collector of Q2 is the pin closest to the large capacitors C5 and C6 Transistor should be switching correct waveform is shown in Figure 12 If this is not present check for shorted junction on 02 If OK check the base waveform Base of 02 is pin of transistor nearest the edge of PCB The correct waveform is shown in Figure 12 If this waveform is not present check L2 Ql and Dl and secondary components Q3 D8 D9 D10 and L3 If any of the semiconductors are found shorted or inductors open replace them 50 V DIV 5 Usec DIV Input 120VAC Loads 50 2A 12 1A 12 0 1A 1 0 V DIV 5 Usec DIV Input and Loads same as above Figure 10 Q2 Base Waveform Section IV Performance Test Each of these test conditions should be set up and noted to be within the limits Input 5 Load 1
54. on the IO bus whenever RCS is low and WC is high Data is written into a selected RAM cell on the trailing edge of WC if RCS is low During writes both WC and RCS will be low for at least 120 nanoseconds so that data setup time requirements are met Scratchpad Operations Because the RAM address counters can be pre set direct reads and writes to a specific address are possible This function is used for scratchpad storage during program execution This mode of RAM access requires two or three instruction cycles for each random access to the RAM as opposed to one for sequential access using the post decrement feature MAC Control Port Basic control of the various Functional sections of the controller is accomplished by a dedicated 6 bit control port called MAC CNTRL U29 MAC CNTRL enables CRC generation CRCIZ functions of the WAIT control circuitry WAEN gating of read or write functions WRITE control of CRC check word output 1BLA and AM detection SRCH MAC CNTRL output states are latched into the port by a write strobe WR7 Additionally any time MAC CNTRL is loaded with a new byte the lower two data bits IOO and IOI are strobed into the upper two address counter latch bits RAS and RA9 All remaining ports are distributed among the basic functional sections of the controller and will be described in detail within the discussion of those functions Serial Data Separation The controller board contains cir
55. oooooooooo AS 6 Maintenance caos RRA DO 7 Theory of Operation s UC UOTE 29 Hard Disk Controller Board Kake See J 8 Troubleshooting the Power Supply Secondary Drive OnIyV seri s ons galtes massissos ES 47 9 Printed Circuit Boards aaa EF 51 10 Wiring Diagrams Flair 53 ILI Par ES Wis Cedi leek huqkaq yg as ee es a ie 57 12 Schematics ere ee ee ETE EE a T E 63 13 Supplement ELE EI ED IE uses 69 Radio Shaek 5 Meg Hard Disk Service Manual KAKAK KK KAKAK KA KAKA KA KAKA KAKAK KK KAKAK AKK e KAKE RR RR RR kk Warnings k k k amp k KK KAKA k k KAKAK KAKA KAKAK k k KA KAKAK k k KAKA KAKAK KAKAK KAKAK AK Do not move or tilt the Hard Disk Drive unit while the drive is running Permanent damage to the drive may occur resulting in the loss of information or damage to the disk Do not drop the Hard Disk Drive unit from any height as permanent damage to the drive may occur Radio fhaek soe u I 5 Meg Hard Disk Service Manual 1 Overview The TRS 80 5 Meg Hard Disk Unit consists of two non removable 5 25 inch disks There are four Read Write heads one on each side of each platter which move towards or away from the center of the disk as needed The Disks and Read Write heads are fully enclosed in a sealed chamber A special air filteration system prevents dust and other particles
56. or C33 for a 10 MHZ output at TP9 and the frequency control voltage input TP8 to 2 5 V 5 V It should be noted here that both of these adjustments are done using the same trim cap C33 The output of the error amplifier and filter is fed to the VCO and represents how far the VCO frequency is from that of the incoming signal The error signal which is proportional to the difference allows the VCO to shift from center Frequency and become the same as the frequency of the frequency of the input signal When the loop is in lock the difference frequency component will be DC and is passed by the low pass filter Frequency control is actually a matter of frequency range The difference component may fall outside of the band edge of the low pass filter and be removed along with the sum frequency component If this is the case then no information is transmitted around the loop and the VCO remains at its initial free running frequency As the input frequency approaches that of the VCO the frequency of the difference component decreases and approaches the band edge of the filter Now part of this difference component is passed which tends to drive the VCO to the frequency of the difference component more and allows more of it to be passed through the filter This is a positive feedback which causes the VCO to snap into lock with the input signal 34 5 Meg Hard Disk Service Manual The term capture range can be described
57. ot TT 6 eo 9 09 e 99 A o 0 0 0 o w 6999 0 agar a 66 8 6899988888 e 00 Ze b a e 0800008 k 000000 o e 888588988 7o TT od A 086800 TN e Manas e o Quinizn o 888008008 0000000088 bb 00 e Pi ce 9 o go 9 e o9 o e e o o e Ze 9 Ki mung asondnna 290 0 2yo o o BRB amaguouoaa se fin m Bas 00900000008 gaaaduan ngandeg 0000000000000008089 8998899988 108000 086 Te TUT 88 o o 9909 e o o 8 9 o 00 04 9 00 di HD 585888858 55555559 e STILI 80 dom gt 000600000 kab 88 e en o TETT a000 o000000m BBB P o ga oossssgsoo S TE e ED o 00008 Joodovavas ana o e o o o 99 Q 2 2 888888808808 oo o pandika o 90 o KE iun e 000 VIUIRIZITO 89 e 9 oo 8988888989998 F eee 90 0000000008 RA p 55088800 e 9 eg 880088 x FIDE 00 2 00 p ee 20 o 96 oe oo 000868098 posses 40000000 0002806 2 000220 9 eoo diae o 30 99 8 oe e 9999 o ve ai NAN E o gaaaanaaaad d o 88888888 K o 9 e og 9 LITA Ja g ogous nn og L e ee KEEN 00 o e o el me 0808088 0080900 se DOO e 9990888 Be gana og Ze e 9 B ED 2 0000000 3 0800008 Saaf oo 000 apenas mann ouseeseg e br PORTA 9 9 IOE A 2 38 ee g oe o ond 908089 caus L j o 9 o0 0 898888889 oe 00980808 08080008 c e 9 e 00 090 8899859 e e
58. rd and center stand off Fasten the board 23 5 Meg Hard Disk Service Manual using five 6 screws 4 Reconnect all cables the lamp driver harness and the power harness Make sure that the lamp driver harness is toward the rear of the unit Be sure that the data cables are connected so that the cable comes from the left hand side of the plug when looking from the front of the unit dia Replace the case top and 3 6 screws in the rear panel 94 5 Meg Hard Disk Service Manual 6 Maintenance The only regular maintenance the 5 Meg Disk Drive requires is a periodic cleaning of the filter on the back of the unit Clean this filter whenever it becomes filled with dust and particles To clean the filter carefully remove the outer grill DO NOT REMOVE THE SCREWS Then remove the filter and rinse with tap water When the filter is completely dry put lt back in the drive 25 mi OG ux 5 Meg Hard Disk Service Manual 7 Theory of Operation Hard Disk Controller Board General The hard disk controller board is a discrete implementation of all functions required to control the 5 25 inch disk drive via a standard data and control bus The controller is fabricated using a mix of high speed bipolar and MNOS devices contained on a single two sided PC board The design of the circuitry makes use of a high speed microcontroller the 8X300 newly developed NMOS support devices Schottky a
59. re of the device is used in writing certain fields used in formatting CRC Generation The CRC generator checker U6 is used to generate the CRC bits and to append them to the end of the data being written to the disk This is the complementary function to that performed during reads The operation of the polynomial generator is identical to read operations except that at the end of the data field the processor sets a signal which causes the device to output the computed CRC after the data instead of reading the CRC and checking it The initial state of the shift registers within the device is forced to all ones by the processor pulsing CRCIZ for approximately 250 nanoseconds while the parallel to serial device is outputting all zeros on the NRZ data line At that time a latch is set which holds the registers at ones until the first non zero bit enters the device The first non zero bit will be the MSB of the AM HEX Al of the data field to be written When the processor decides that enough zeros have been written to satisfy the sync field requirements it will store a HEX Al in the parallel to serial device At the proper time in sync with BDONE the parallel to serial device will begin to send the MSB of the AM to the CRC device This will start the CRC polynomial generator and the CRC will be computed As the processor writes the last byte of data to the parallel to serial device it will drop the 1BLA 1 Byte Look Ahead signal on
60. receiver U54 The receiver converts differential input data to TTL levels for use by the controller The data from the selected drive is then routed to gate U53 At this point data and clocks are still combined and appear as 50 nanoseconds nominal active high pulses spaced at intervals of one one and a half or two times the RCLK period This data is presented to the input of another AND OR INVERT gate U4 which will gate either MFM data or a reference clock into the first stage of the VCO error amplifier circuitry Reference Clock The reference clock is derived from the write clock crystal oscillator Ql U10 and associated circuitry This oscillator uses a fundamental cut crystal to oscillate at four times the RCLK frequency The 4X output is then divided by UlO to produce both a 2X clock 2XDR which is used as a reference and a 1X clock WCLK which is used to produce 32 5 Meg Hard Disk Service Manual MFM write data for the disk The crystal Y1 frequency is 20 000 MHz for compatible drives Clock Gating The gating of the reference and MFM data into the data separator is dependent upon the condition of the Read Gate signal RGATE and the spacing of the data on the serial stream after RGATE is brought true Due to the techniques which are employed to separate data from clocks it is necessary to run the VCO at a rate twice the data clock RCLK rate The VCO is therefore set to an open loop frequency o
61. ry drive 5 Meg Hard Disk Service Manual CONTROL IN DATA IN Control In 34 pin Connect one end of a Secondary Hard Disk Expansion Cable to this jack The other end connects to the previous Hard Disk E Drive EE Control Out 34 pin Connect one Ve end of a Secondary Hard Disk Expansion Cable to this jack The other end b connects to the next secondary drive ii 4 Data In 20 pin Connect one end of the Data Cable from the the primary 2 drive to this jack a del ord Filter Figure 3 A Fully Configured Hard Disk System 5 Meg Hard Disk Service Manual Connecting the Primary Hard Drive to the Model I To connect the hard disk drives to the Model I you need a Model I Kit Catalog Number 26 1132 Included in this kit are A Model I Adapter Cable A Three DisXettes HARD DISR OPERATING SYSTEM XTRA INITIALIZATION Important Note The Expansion Interface must be buffered before the hard disk can be connected to your Model I Instructions on how to determine whether the Expansion Interface is buffered are given next There are two types of Buffered Expansion Interfaces The first type is recognized by its cables The flat ribbon cable between the Expansion Interface and the Keyboard will have a black box on it There will also be a 3 wire cable with a din plug type co
62. shot is adjusted for a pulse width of one and one fourth times the RCLK period This is 250 nanoseconds 10 ns These adjustments of the DRUN one shot Ul provide tolerances of up to one fourth the RCLK period in jitter on the MFM data bits while still being able to distinguish MFM zeros or ones from other data patterns 33 5 Meg Hard Disk Service Manual Each clock or data bit on the serial stream triggers the one shot If the time between successive triggers is less than the one shot time constant the one shot remains retriggered As the one shot is triggered by data stream bits so is the up down counter U2 whose count mode is controlled by the state of the one shot outputs While the one shot is being retriggered the counter counts up When any data bit fails to reach the one shot before its time constant is over the one shot resets and in turn clears the counter Only when 16 successive retriggers occur can the counter reach its terminal count At this time the counter overflow goes true and sets the DRUN latch output U3 pin 6 low which switches read data in and reference clock out An AND OR INVERT gate U4 performs the switching DRUN is read through U74 by the 8X300 to determine the condition of the MFM data stream VCO The Hard Disk controller uses a single chip VCO U32 which Simplifies circuitry and adjustments The operating point of the VCO is initially set by adjusting the variable capacit
63. ters Warm Up Period Minimum On Power Up 2 minutes Minimum to Turn System On After Turning System Off 15 seconds Hard Disk Drive Disk Organization Tracks per Unit 612 Tracks per Platter 306 Sectors per Track 34 Bytes per Sector 256 Cylinders per Disk 153 Average Latency 8 34 msec Rotational Speed 3600 rpm 1 Recording Density 7690 Flux Density 7690 Track Density 254 Storage Capacity Hard Disk Unformatted Bytes per Track 10400 5 Meg Hard Disk Service Manual Bytes per Surface Bytes per Drive Formatted Bytes per Drive IO 1 59 MEG 6 33 MEG 5 M Primary 5 M Secondary P adie fhaek EE 5 Meg Hard Disk Service Manual 3 Connections Connecting Your Primary Drive to a Model III Be sure all power is OFF Note Master unit does not come with Data Out connectors These are supplied with each secondary unit and require installations Locate the hard disk expansion cable Connect one end to the I O bus card edge of your Model III Be sure the cable exits the rear of the computer so that it won t bind Connect the opposite end of this cable to the COMPUTER IN connector located on the rear panel of the primary drive Connect the power cord to the primary drive Plug the other end into an appropriate AC power source Radio Jn aek A e cb 5 Meg Hard Disk Service Manual Figure 1 Back Panel of Hard Disk Drive Computer In 50 pin Connect the
64. which destroy data from reaching the disks Another filtering system allows pressure equalization with the outside air pressure UNDER NO CIRCUMSTANCES MUST THE CHAMBER BE UNSEALED IN THE FIELD A CLASS 100 CLEAN ROOM ENVIRONMENT IS NEEDED FOR UNDER THE BUBBLE REPAIR On all Hard Disk Units flaws in the media are indentified at the factory before the disk drives are delivered to the customer Attached to the bottom of each disk drive unit is a Media Error Map This map identifies the flawed tracks on that particular unit 5 Meg Hard Disk Service Manual 2 Technical Specifications Basically the hard disk unit consists of two platters or disks lying parallel within the unit There are also four Read Write heads one on each side of each platter These heads move towards or away from the center of the disk as needed When a unit is purchased there will be no more than 3 tracks per head with defects This will not exceed 8 tracks per drive with defects Also there will not be any flaws on Track 0 Disks Platters 2 Heads Recording Surfaces 4 Tracks per Inch 254 Cylinders 153 Tracks 612 Hard Disk Cylinders Tracks Sectors Bytes 1 153 612 19 584 5 013 504 ies l 4 128 32 768 m 1 32 8 192 e av 1 256 EE sasawan A VER vum A A wu A me ar a t ma a w h w s arwa e wa mh O W s ms asqa aq A OR wn ARE van A A lt ddnde CU UA SITO KOR IO zeg AD Q eege samin s vs ED vm mmm aranan rd er vg engm
65. y a data byte of of HEX Al requires a clocking pattern of HEX OE In fact due to the rules of MFM data encoding an alternating clock pattern such as HEX A or HEX 5 cannot exist legally The AM is used to uniquely identify the start of a field of information data or ID field within each sector A long run of zero data always precedes each AM on the disk Zeros have a clock bit for every RCLK When attempting to read information from the disk the Controller first acquires phase lock over a field of zeros When this acquisition is achieved the processor releases the AM detector Ull by raising the Search control line SRCH on the MAC CNTRL port U29 dra 5 Meg Hard Disk Service Manual Due to the circuitry associated with the VCO to RCLK divider the RDAT output of the data separator Ul3 8 will be high and the CLKS output Ul2 8 will be low RCLK will be the shifting clock for RDAT and RCLK will be the shifting clock for CLKS These four signals are routed into the AM detector Inside the AM detector RDAT is shifted into an 8 bit synchronous serial shift register and clocked on the falling edge of RCLK CLKS is shifted into a similar shift register on the falling edge of RCLK The output stage of the RDAT register is dumped into an Al comparator and the output stage of the CLKS register is dumped into a 0A comparator AM detection occurs when both detectors are true thereby setting the AMDET l
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5-Meg Hard Disk Service Manual (1982)(Tandy)

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