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DEVA001 PCI encoder interface card User's Manual

1. DO7s 1 0 DO6s 1 0 DO5s 1 0 DO4s 1 0 DO3s 1 0 DO2s 1 0 DO1s 1 0 DOOSs 1 0 5 3 1 120ffset 24h 28h Digital UO direction register The upper 16 bits of this register are designated the Digital UO direction registers These read write registers control the direction of digital I Os Digital UO direction register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 IOb1d ObOd lOb0d Direction of digital UO byte 0 1 Input O Output lOb1d Direction of digital UO byte 1 1 Input O Output 5 3 1 130ffset 40h 44h 48h Channel control register 0 The lower 16 bits of these registers are designated Channel control register 0 These read write registers are used to configure the data acquisition mode such as clock frequency and bit length from the SSI encoder There is a register for each channel The registers hold zero after a system reset Channel control register 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit11 Bit8 Bit7 Bit3 Bit 2 Bit 0 Out Output Gray Binary Extra bit mode Offset Data length Frequency 0 Out Low Binary mode0 No Extra bit Oto 15 bits 1 to 31 bits 0 2 78 MHz 1 OutHigh f1 Gray mode i Power Fail bit 0 32 bits 1 1 39 MHz 2 Even Parity bit 2 926 KHz 3 Odd Parity b
2. Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 CH2ioCH1io CHOio BRDioTMRiq TMRio Timer interrupt occurred BRDio Board interrupt s occurred CHOio Channel 0 interrupt s occurred CH1io Channel 1 interrupt s occurred CH2io Channel 2 interrupt s occurred Offset 08h Timer latch The lower 8 bits of the register at offset 08h are designated the Timer latch This read write register specifies the reload value in 0 1ms of the Timer function This register holds FFh after system reset Offset 08h Timer counter The upper 16 bits of the register at offset O8h are designated the Timer counter This read only register returns the current value of the count down timer counter in 0 1ms When the timer function is disabled the timer counter resets to the value of the timer latch Page 42 DEVAO01 User s Manual PCI Incremental encoder interface hardware 4 4 1 8 Offset OCh Time Stamper latch The lower 16 bits of the register at offset OCh are designated the Time Stamper latch This read only register allows access to the timestamp of the event associated with the Time Stamper The register holds zero after system reset 4 4 1 9 Offset OCh Time Stamper counter The upper 16 bits of the register at offset OCh are designated the Time Stamper counter This
3. Timer 1 Sync Occur User Event 0 Occur Board Digital Input 0 Occur Pulse Generator 0 Sync Occur Axis Compare 0 Sync Occur Axis Compare 1 Sync Occur NIDIA B Go PO Reserved 3 1 13 Pulse generator information Command amp equate Channel 120 PULSEGENO Axis no 121 PULSEGENO_MODE Axis no DEVAO001 User s Manual Controls the source event of the Time stamper latch Operation Allows access to the 16 bit pulse generator register in units of 1 quadrature count Controls the mode of operation of the pulse generator Bit Function 0 Direction when in Uni directional mode 1 0 1 Bi directional operation 1 0 Bi directional Uni directional 2 Hardware Start Stop by Axis Comparators 1 0 On Off 3 Deglitch Do not repeat the same pulse sequentially 1 0 On Off 122 PULSEGENO_EN Axis no 123PULSEGENO_OCCUR Axis no 124PULSEGENO_OUT_EN Axis no Writing a value of 1 0 enables disables the pulse generator function Returns a value of 1 every time a pulse generator interrupt has occurred Enables the pulse generator 0 digital outputs Specifying 1 0 in each bit field enables disables the equivalent digital output Bit Status Pulse Width 0 Pulse Generator 0 Occur Occur to serviced 1 Pulse Generator 0 Terminal Count Quadrature count width 125PULSEGENO_INT_VECT Axis no 3 1 14 Axis compare
4. 1 1016 1032 2 017 1033 3 1018 1034 4 1019 1035 5 020 1036 6 1021 1037 7 022 1038 8 1023 1039 9 024 1040 10 1025 1041 11 1026 1042 12 1027 1043 13 1028 1044 14 1029 1045 15 1030 1046 16 1031 1047 17 GND GND 18 GND GND 19 45v 5v 20 12v 12v 4 3 4 Sync connector The sync connector provides a method of linking cards in hardware to allow events to be routed from one card to another In general a ribbon cable connecting all 10 connections between all cards is required Pin Number Function Sync0 Timer occur GND Sync1 Pulse Generator 0 occur GND Sync2 Axis Compare 0 occur GND Sync3 Axis Compare 1 occur GND GND GND O OTN Oy BT OTP CH Page 37 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 4 4 4 1 Direct hardware programming The DEVA001 incremental encoder interface card is supplied with a variety of device drivers for Microsoft Windows operating systems which perform all low level access functions required for its operation Using a device driver offers several benefits including not having to read any more of this manual and the ability to re use application software and routines with any of DEVA Electronics compatible products The device drivers and the common software interface are described in section 3 For applications where hardware access is essential the following sections give an overview of
5. Board Digital Input 0 Probe Occur Foot Switch Occur User Request 0 Timer Occur Timer TCNT Interrupt Controller D Timer 0 1ms to 25 6ms 0 1ms Step K Time Stamper lus Resolution Pulse Gen Omni Bi Dir 65k Counts MAX A NOU Probe 50ms debounce Foot Switch Edge Detector Yb oy Wy og eer eg Digital Input Pos Edge Det renn A No No No Board Digital Output 0 Board Digital DEVAO01 User s Manual Timer Occur Pulse Generator 0 Occur Probe Occur Foot Switch Occur Board Digital Input 0 Occur User Request 0 Output 1 Pulse Generator 0 Occur w Pulse Generator 0 TCNT Board Digital User Request 0 Output 2 Timer Occur L Pulse Generator 0 Occur Syn c Bus Axis Compare 0 Occur Axis Compare 1 Occur Page 32 Level Sensitive Asserted Low 48 Digital UO Byte Configurable Direction 16 Selectable Special I O Timer Syne Occur Pulse Generator 0 Syne Occur Axis Compare 0 Syne Occur Axis Compare 1 Sync Occur DEVA001 User s Manual PCI Incremental encoder interface hardware 4 1 10 2Incremental channel level block diagram Channel 0 Latch 1 Comp 0 H gt Axis Compare 0 Occur Marker Occur Zero Occur Pulse Generator 0 Sync Occur User Request 0 Channel Digital Input 0 Occur Axis Compare 0 Sync Occur Axis Compare 1 Sync Occur MO Va wi Za Counter 32 bit 10MHz Max C R Tim
6. CC E po po LL Pao0cDICC t TSTc IT Me Page 40 DEVA001 User s Manual PCI Incremental encoder interface hardware 4 4 1 3 4 4 1 4 TMRc_ Clear timer occur flag TSTc Clear time stamper overflow occur flag Dioc Clear board digital input O occur flag PGOc Clear pulse generator 0 occur flag Offset 00h Special function status register The upper 16 bits of the register at offset OOh are designated the Special function status register This read only register allows access to board based status information Special function status register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 PG0o DIOo ACio ACOo TSTo TMRoFi nPi Fo Po Po Probe occur flag Fo Footswitch occur flag nPi Direct probe input inverted Fi Direct footswitch input TMRo_ Timer occur flag TSTo Time Stamper overflow occur flag ACOo Axis Compare 0 occur flag ACTio Avis Compare 1 occur flag DIOo Board Digital Input 0 occur flag PGOo Pulse Generator 0 occur flag Offset 04 Interrupt mask register This 16 bit read write register sets the interrupt masks to select which interrupt sources generate interrupts A logic zero disables an interrupt and a logic one enables an interrupt The register holds zero after syst
7. software at any time Telescope directional feedback To measure the direction of a telescope on a turntable a single turn absolute SSI encoder may be employed at the centre of rotation If greater resolution is required a multi turn encoder may be employed at the circumference of the table An absolute SSI encoder has the advantage that the telescope position is always available and DEVA001 User s Manual Overview 1 3 1 3 1 1 3 2 1 3 3 hence the telescope does not need to be rotated through 360 whenever the power is re applied Support software A variety of software drivers and libraries are provided with the interface card to enable software development to be performed within a number of operating systems and applications Software support is an ongoing activity if support for a particular application or operating system is not currently provided please call the Deva office to determine its availability Windows 98 NT4 2000 ME XP Both ISA and PCI cards are supported in Windows 98 NT4 2000 ME XP by a variety of virtual device drivers VXD Kernel mode drivers KMD and Windows driver model drivers WDM The drivers all support a standard programming interface Please refer to section 3 Device Driver Usage for more details National Instruments LabVIEW LabVIEW support is provided via an LLB of VI s which allow the access to the device driver functions These VI s allow users to develop powerful applications very
8. 1 every time an axis position compare 1 has occurred Allows access to the interrupt vector or interrupt call back executed by an axis compare 1 interrupt Operation Returns a value of 1 every time a board user event 0 has been triggered and acknowledged Writing any value triggers the board user event Writing a value of 1 0 enables disables the user event 0 digital output at the specified I O bit provided such mapping is possible Operation Writing a value of 1 0 enables disables the equivalent board digital input positive edge detector Returns a value of 1 every time a board digital input interrupt has occurred Allows access to the interrupt vector or interrupt call back executed by an board digital input interrupt Writing a value of 1 0 enables disables the equivalent axis digital input positive edge detector Page 15 Device Driver Usage 156 AXIS INPUT OCCUR Axis no 157 AXIS INPUT INT VECT Axis no Page 16 Rd Rd Wr DEVA001 User s Manual Returns a value of 1 every time an axis digital input positive edge has occurred Allows access to the interrupt vector or interrupt call back executed by an axis digital input interrupt Device Driver Usage DEVA001 User s Manual 3 1 17 Digital UO information Command amp equate 16010 16110 DIR 16510 32 16610 32 DIR 169 NUM 10S Channel I O no I O no Reg no Reg no N A 3 1 18 FIFO buffer information The followin
9. No No Yes 156 AXIS INPUT OCCUR No No Yes 157 AXIS INPUT INT VECT No No Yes 16010 No No Yes 16110 DIR No No No 16510 32 No No Yes 16610 32 DIR No No Yes 169NUM JOS No No Yes 170BUF CLK CH No No Yes 171BUF CLK TYPE No No Mes 172BUF CLK DIV No No Mes 173BUF NUM DATA No No Mes 174BUF DATA INDEX No No Yes 175BUF DATA CH No No Yes 176BUF DATA TYPE No No Yes 180BUF SIZE No No Yes 181 BUF MODE No No Yes 182 BUF EN No No Yes 183BUF FLUSH No No Yes 184BUF STAT No No Yes 185BUF READ No No Yes 187 BUF MEMFREE No No Yes 188BUF MAXDATA No No Yes 189NUM BUFFERS No No Yes 200INUM_LOSTCALLBACKS No Yes Yes Page 22 DEVA001 User s Manual Device Driver Usage 3 3 3 3 1 3 3 2 3 3 3 3 3 4 Device driver programming from C In order to simplify the user software required to access the MS DOS and Windows 9x NT4 2000 ME XP device drivers a selection of functions are supplied on the distribution CDROM The functions are prototyped in the C header file enclib h This section describes the C functions provided for device driver access short open_encoder void Opens the device driver and provides access to the functions provided Entry l none Exit returns 0 if no error returns 1 if error void close_encoder void Closes the device driver Entry none Exit returns 0 if no error returns 1 if error long read_encoder short command short channel Returns in a 32 bit integer the result of reading the dev
10. amp nMi inputs In this case the driver will zero the counter readings in software The inputs nLimO and nLimi are digital inputs intended to be used to connect normally closed overtravel inputs The differential inputs use RS422 levels which accept OV for logic low and from 5V to 12V for logic high Because they are differential inputs one input should be low when the other is high For Example to trigger the marker function set Mi input to high and set nMi input to low To turn the marker function off reverse these voltages An internal resistor network is provided which allows connection of single ended signals to the non inverting inputs The 12V and 5V power supply pins may be used to supply the dc power requirements for the encoders Renishaw probe input connections The Renishaw connection kit provides a 9 way female D connector which may be used with the bracket supplied or mounted in a free cut out on the PC case Connections to this socket should be made with reference to the following pin out table Pin Number Signal Function 1 Led C Led cathode 2 Ov Ov 3 Led A Led anode 4 Probe Probe 5 Probe Ov 6 Siren Siren 5v 7 Siren Ov 8 FootSw Footswitch input 9 FootSw Ov Page 35 DEVAO01 User s Manual PCI Incremental encoder interface hardware 4 3 3 Digital IO connections There are three 20 pin headers labelled 100 101 and IO2 w
11. be read when the occur flag of that event is set Various source events can be selected by the equivalent source event selector accessible through the channel control register The register contents are zero after system reset 4 4 1 200Offset aOh a4h a8h Latch 2 Probe latch These three registers allow access to the three 32 bit Probe latches Each latch stores the counter value when the associated source event occurs and should only be read when the occur flag of that event is set Various source events can be selected by the equivalent source event selector accessible through the channel control register The register contents are zero after system reset Page 47 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 1 5 1 1 PCI Absolute SSI interface hardware Functional description The DEVA001 is designed to interface up to three absolute SSI encoders or linear scales to the PC PCI bus The following sections describe the various functions of the interface for a detailed description of how to program these facilities please refer to section 5 3 Programmable clock frequency bit length and offset The clock frequency and encoder bit length may be independently programmed for each encoder The frequency may be set to one of eight values in the range 78 KHz to 2 5 MHz see sections 5 2 2 and 5 3 1 13 for details The bit length may be programmed in the range 1 to 32 bits The time taken to make a reading will dep
12. bus The following sections describe the various functions of the interface for detailed description of how to program these facilities please refer to section 4 4 Quadrature input Each encoder channel has four differential single ended input circuits designated A B Z and M The A and B inputs accept the quadrature signals from the encoder and drive an up down counter via a x4 directional discriminator circuit The counter has 32 bit resolution and may be read at any time The maximum count rate is in excess of 10 MHz Marker input The M input circuit designated marker is a positive edge triggered input which can synchronously latch the counter value To gain the most accurate result the input conditioning circuit latches the counter when both A and B inputs are at a logic one level The user must therefore phase the A and B signals carefully to meet this criteria Should this not be achievable circuit operation is still possible although the latched value will not be accurate to a single count Correct phasing may also be achieved by using the input invertors on signals A B amp M To use the marker input the marker circuit must be enabled Once a positive edge has occurred on the marker input the counter is latched when both A and B are at logic one The marker latch register may now be read while the counter continues to maintain position To enable the maker latch to capture a further marker event the marker function should be disab
13. input interrupt has occurred 26 MARK_LATCH_SEL Axis no Rd Wr Controls the source event of the Marker associated latch of each axis Value Source 0 Marker Occur 1 Zero Occur 2 Pulse Generator 0 Sync Occur 3 User Event 0 Occur 4 Channel Digital Input 0 Occur 5 Axis Compare 0 Sync Occur 6 Axis Compare 1 Sync Occur 7 N A Axis Compare 0 Enable 27 MARK OUT EN Zero information Command amp equate 30 ZERO INPUT 31 ZERO INT 32 ZERO FUNC 33 ZERO INT VECT 34 ZERO INT OCCUR Extended axes Command amp equate 40 AXIS_32 41 MARK_32 42 VEL_INST Axis no Channel Axis no Axis no Axis no Axis no Axis no Channel Axis no Axis no Axis no Rd Wr Writing a value of 1 0 enables disables the marker digital output Rd Wr Operation Rd Returns either 0 or 1 depending on the state of the zero input Rd Wr Allows access to the card interrupt controller mask Writing a value of 1 0 enables disables an interrupt from the zero input This function is for special applications only Rd Wr Writing a value of 1 0 enables disables the channel zero function Rd Wr Allows access to the interrupt vector or interrupt call back executed by a zero input interrupt Rd Returns a value of 1 every time an encoder zero interrupt has occurred Rd Wr Operation Rd Wr Allows access to the 32 bit counter register values or to pseudo incremental 32 bit position for absolute SSI encod
14. latch encoder positions or trigger a digital output for external circuitry synchronisation Page 30 DEVA001 User s Manual PCI Incremental encoder interface hardware 4 1 9 Time Stamper The time stamper is a 16 bit high speed timer with a resolution of 1us It can be programmed to latch its value on an event so to provide an accurate time stamp at which the event occurred 4 1 10 Event System Many features of the card produce events When an event occurs a flag called the occur flag is set The occur flag may be polled by the user to establish that the event has occurred The card has a variety of actions which may be configured to respond to events The actions include latching the current position in one of three latches generating an interrupt triggering a digital output or latching a time stamp of the event The following diagrams show the board level and channel level events and actions which may be programmed Page 31 PCI Incremental encoder interface hardware 4 1 10 1Incremental board level block diagram Timer Occur Probe Occur Pulse Generator 0 Occur Board Digital Input 0 Occur Channel 0 Interrupts Channel 1 Interrupts Channel 2 Interrupts Probe Occur Timer Syne Occur User Request 0 Board Digital Input 0 Occur Pulse Generator 0 Syne Occur Axis Compare 0 Syne Occur Axis Compare 1 Sync Occur Channel 0 Sync Axis Compare 0 Occur Start Axis Compare 1 Occur Stop Probe Input Foot Switch Input
15. other function the timer latch source is set to See commands 65 and 64 Operation Returns either 0 or 1 depending on the state of the input Operation This command allows access to the interval values of the on board user timers The timer intervals are programmed in units of 0 1 ms Writing a value of 1 0 enables disables the user timer interrupt Allows access to the interrupt vector or interrupt call back executed by the user timer interrupt Returns a value of 1 every time a user timer interrupt has occurred Controls the source event of the timer latch of each axis Page 11 Device Driver Usage 65 TIMER1 FUNC Axis no Rd Wr 66 TIMER OUT EN Timer no Rd Wr DEVAO001 User s Manual Writing a value of 1 0 enables disables the user timer function for the specific axis This allows for position readings latched on every timer 1 interval of the equivalent board Enables the timer digital outputs Specifying 1 0 in each bit field enables disables the equivalent digital output Bit Status Pulse Width 0 Timer Occur Occur to serviced 1 Timer Terminal Count flus 3 1 8 DAC Control Command amp equate Channel Rd Wr 70 DAC_MV Axis no Rd Wr 71 DAC UV Axis no Rd Wr 3 1 9 Output control Command amp equate Channel Rd Wr 80 OUTPUT Output no Rd Wr 81 SERVO_ENABLE Axis no Rd Wr 3 1 10 Probe information Command amp equate Channel Rd Wr 90 PROBE_16 Axis no Rd 91 PROBE
16. quickly using the LabVIEW system Digital Readout A powerful digital readout is supplied which is capable of exercising all the common facilities of the DEVA001 This is useful to allow users to quickly verify that the DEVAO001 is installed correctly and to make checks of their system without having to write their own software The DRO will handle up to four cards 12 axes and displays both absolute and incremental positions The DRO also displays the marker register probe register and allows control of the probe and footswitch options To allow the user to read meaningful values each axis of the DRO may be independently scaled to display real units For the incremental card all facilities such as marker and probe may be toggled on and off If a probe is activated the probed values are shown in the probe register if a marker is activated the value is shown in the marker register For the absolute SSI card it is possible to configure all features via a pop up menu Page 3 Overview DEVAO01 User s Manual 1 4 Accessories The DEVA001 incremental encoder interface is supplied with three high density 15 way D type connectors and matching shells Deva can of course supply a wide range of encoders pre wired and tested for use with the DEVA001 Page 4 DEVAO01 User s Manual Installation and configuration 2 1 2 2 2 2 1 2 2 2 Installation and configuration Software support CDROM The DEVAO001 3 axis encoder
17. specific to other features of the card and has hardwired directions The direction of the other 2 groups may be programmed in blocks of 8 bits Pulse Generator The DEVAO01 has a 16bit Pulse Generator circuit which can produce a pulse every n counts of the X axis encoder where n is programmable from 1 to 65536 The pulse can be sent directly to a digital output cause a hardware event or generate an interrupt Please refer to the event system diagrams for details of which actions can be triggered by the pulse generator event The pulse generator range of operation start and stop positions may optionally be controlled through hardware If hardware control is selected the axis compare functions are used as start and stop positions Please note that the pulse generator function needs to be enabled for this feature to operate The pulse generator has both uni directional and bi directional modes configurable direction when in uni directional mode and incorporates an optional de glitch circuit that does not allow a pulse to be generated at the same position sequentially Axis Compare The X axis has two axis compare registers which may be used to generate events when the axis position matches the compare position The axis compare registers are shared with the Marker and Probe latches Timer The timer is an 8 bit interval timer which can be programmed in steps of O 1ms up to a maximum of 25 6ms This timer may be used to generate interrupts
18. 001 User s Manual 5 2 3 2 Digital IlO connectors 1 and 2 connections 5 2 4 5 3 Pin Connector I01 Connector 102 1 1016 1032 2 017 1033 3 1018 1034 d 1019 1035 5 020 1036 6 1021 1037 7 022 1038 8 1023 1039 9 024 1040 10 1025 1041 11 1026 1042 12 1027 1043 13 1028 1044 14 1029 1045 15 1030 1046 16 1031 1047 17 GND GND 18 GND GND 19 45v 5v 20 12v 12v Sync connector PCI Absolute SSI interface hardware The sync connector provides a method of linking cards in hardware to allow events to be routed from one card to another connections between all cards is required Pin Number Function Sync0 Timer occur GND Sync1 Undefined GND Sync2 Undefined GND Sync3 Undefined GND GND O OTN amp A A OPM CH GND Direct hardware programming In general a ribbon cable connecting all 10 The DEVA001 incremental encoder interface card is supplied with a variety of device drivers for Microsoft Windows operating systems which perform all low level access functions required for its operation Using a device driver offers several benefits Page 57 PCI Absolute SSI interface hardware DEVAO01 User s Manual including not having to read any more of this manual and the ability to re use application software and routines with any of DEVA Electronics compatible p
19. 1 16 CCR15 0 CCR15 0 44h Y Channel status control register Y Channel clear control register CSR31 16 CCR15 0 CCR15 0 48h Z Channel status control register Z Channel clear control register CSR31 16 CCR15 0 CCR15 0 60h X Latch D31 0 64h Y Latch D31 0 68h Z Latch D31 0 Coh X Channel control register 1 X Channel control register 1 CCR15 0 CCR15 0 Gah Y Channel control register 1 Y Channel control register 1 CCR15 0 CCR15 0 C8h IZ Channel control register 1 Z Channel control register 1 CCR15 0 CCR15 0 5 3 1 1 Offset 00h Special function control register The lower 16 bits of the register at offset 0Oh are designated the Special function control register This read write register allows control of board based facilities The register contents are zero after system reset Special function control register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit6 Bit5 Bit4 Bits Bit2 Du BitO URO DIOie TSTs 2 0 TMRe Be Page 59 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 3 1 2 5 3 1 3 TMRe Enable Disable timer function MTSTs Time stamper event select register Didie Enable Disable board digital input O interrupt URO Enable Disable user request 0 flag Time stamper event sources TSTs Source Timer Sync occur flag User Request 0 flag Board Digital Input 0 occur f
20. 16 bits of this register are designated the Digital I O bus 0 mux register This read write register allows control of the multiplexers source selectors of digital outputs on I O bus 0 For each digital output there are 2 selection bits allowing for 4 possible signal sources For a list of possible source routings on each pin please refer to section 4 3 3 1 Digital I O bus 0 mux register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 DO7s 1 0 DO6s 1 0 DO5s 1 0 DO4s 1 0 DO3s 1 0 DO2s 1 0 DO1s 1 0 DOOSs 1 0 4 4 1 140ffset 24h 28h Digital UO direction register The upper 16 bits of this register are designated the Digital I O direction registers These read write registers control the direction of digital I Os Digital I O direction register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 p E eo ee EE eo et E ck odoo lOb0d Direction of digital I O byte 0 1 Input O Output lOb1d Direction of digital I O byte 1 1 Input O Output 4 4 1 15Offset 40h 44h 48h Channel control register The lower 16 bits of these registers are designated the Channel control registers These read write registers allow control of channel based facilities The registe
21. 24 DEVA001 User s Manual Device Driver Usage 3 3 6 Example C programming Example program to demonstrate device driver access S include stdlib h include conio h include stdio h include enclib h void main void LA t long axis_position 12 up to 4 cards x 3 axes short num_channels short i open device driver exit if error if open encoder 1 exit 1 read number of installed encoder channels num channels read encoder NUM AXES OL loop while not key pressed while kbhit display axis positions for i 0 i num channels i axis_position i read_encoder AXIS 32 i printf Slu 081x i axis position i Prante NP close device driver close encoder Page 25 Device Driver Usage DEN AOOT User s Manual 3 4 3 4 1 3 4 2 3 4 3 3 4 4 Device driver programming from Visual Basic In order to simplify the user software required to access the Windows 9x NT4 2000 ME XP device drivers a selection of Visual Basic functions is supplied on the distribution disk The functions are declared in the enclib bas module This section describes the Visual Basic functions provided for device driver access Function open_encoder As Integer Opens the device driver and provides access to the functions provided Entry none Exit returns O if no error returns 1 if error Functio
22. 65 IO 32 Value Axis Data 16 Timer Latch SSI Latch See command 48 TIMER 32 47 ABSOLUTE 32 17 Marker Latch See command 41 MARK 32 18 Probe Latch See command 46 PROBE 32 19 Incremental Position See command 40 AXIS 32 180 BUF_SIZE Bufferno Rd Wr Allows the user to detect or specify the FIFO buffer size in data elements Writing to this function disables and initialises data in the buffer Buffer memory allocation succeeds if a non zero value is returned 181 BUF_MODE Buffer no Rd Wr Controls the mode of operation of the FIFO buffer Bit Mode 0 Logging mode 1 0 Discard old data when full Discard new data when full Page 18 DEVA001 User s Manual Device Driver Usage Writing a value of 1 0 enables disables FIFO buffer logging Writing to this function clears the contents of the FIFO buffer The value parameter passed to this command is ignored Allows access to the status register of the FIFO 182 BUF_EN Buffer no Rd Wr 183 BUF_FLUSH Buffer no Wr 184 BUF_STATUS Buffer no Rd buffer Value Status 1 Overflow 0 Empty Ave Number of data elements currently in buffer 185 BUF_READ Buffer no 187 BUF_MEMFREE Not used 188 BUF_MAXDATA Not used 189 NUM_BUFFERS Not used Rd Rd Rd Rd 3 1 19 Software call back information Command amp equate Channel 200 NUM_LOSTCALLBACKS Not used Rd Wr Rd Returns a single data element from the FIFO buffer Returns the total amoun
23. 7kHz to 2 78MHz Parity Odd Even Power Failure Grey Binary User Request 0 Timer Sync Occur On Channel Digital Input 0 Occur Read Trigger Axis Compare 0 Sync Occur Axis Compare 1 Sync Occur Pulse Generator 0 Sync Occur Probe Occur Continuous Axis Output Axis Output Differential Channel Digital Input 0 Digital Input Channel Digital Input 0 Occur Pos Edge Det User Request 0 Read Trigger N gt Channel Digital Output 0 Read Complete Read Complete Channel Digital Input 0 k gt Channel Tnterripts Page 52 DEVAO001 User s Manual PCI Absolute SSI interface hardware 5 2 Connection details The DEVAOO1 has three input channels for SSI data signals from absolute encoders designated x y amp z Connection of each channel to the outside world is made through a 15 way D type connector The designation of the connectors is shown in the diagram below Encoder input channel x Encoder input channel y Encoder input channel z ojo oe Eye Page 53 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 2 1 5 2 2 Encoder input connections Connections to these sockets should be made with reference to the following pin out table and simplified circuit shown below Pin Number Signal Function 1 Clock Clock output 2 Out Out output 3 Data Data input RS422 line driver 4 Spare Spare output SN 5 6 Clock C
24. Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 AC10 ACOo ER10 EROo DIOo nLIMinLIMOZo Zi Mi Bi Ai Mo Mo Marker occur flag Ai Direct A channel input Bi Direct B channel input Mi Direct M marker channel input Zi Direct Z zero channel input Zo Zero occur flag nLIMO Direct Limit O channel input inverted nLIM1 Direct Limit 1 channel input inverted DIOo Channel digital input O occur flag EROo Error 0 quadrature occur flag ER1o Error 1 power occur flag ACOo Axis compare 0 occur flag AC1o Axis compare 1 occur flag 4 4 1 18Offset 60h 64h 68h Latch 0 Timer latch These three registers allow access to the three 32 bit Timer latches Each latch stores the counter value when the associated source event occurs and should only be read when the occur flag of that event is set Various source events can be selected Page 46 DEVAO01 User s Manual PCI Incremental encoder interface hardware by the equivalent source event selector accessible through the channel control register The register contents are zero after system reset 4 4 1 19Offset 80h 84h 88h Latch 1 Marker latch These three registers allow access to the three 32 bit Marker latches Each latch stores the counter value when the associated source event occurs and should only
25. DEVAO001 PCI encoder interface card User s Manual A EE lle B aE ES M Data en Clock LJ LI LJ V2 2 ELECTRONIC CONTROLS 52 Woodside Business Park Birkenhead Wirral CHAT 1EL United Kingdom Tel 44 0 151 647 3222 Fax 44 0 151 647 4511 Email support deva co uk Web www deva co uk All information of a technical nature and particulars of the product and its use are given by Deva Electronic Controls Ltd in good faith However it is acknowledged that there may be errors and omissions in this manual We shall not be liable for loss or damage whatsoever arising from the use of any information or particulars in or any omissions from this document V2 2 DEVAO01 PCI User s Manual Overview 1 1 1 1 1 1 1 2 1 1 3 1 2 1 2 1 1 2 2 1 2 3 1 3 1 3 1 1 3 2 1 3 3 1 4 2 1 2 2 2 2 1 2 2 2 2 2 3 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 1 5 3 1 6 3 1 7 3 1 8 CO M NUI OO W nn EE 1 Product Features c cccecceececeececesceseeeecescueceeeeeeuseueuseuseeeuseneees 1 Common Incremental interface features ccccccssscsseecseeecseeecseeeeeeeeeeees 1 Common Absolute interface features ccccccssscssseecssseseeeeseseecseeeeeeseeees 1 PCI specific features sci ssc oo kavo ini ent aks ko dada anan ce kon gege 2 Typical APPliCAllON Ss kek kako on kte w w ki ie kn n a kaba an ko a ke 2 Co ordinate measuring MachIiNE 00 0rrrrrreeeeeeanannrrrrrss
26. Hz 3 7 Reserved 8 11 Offset O to 15 bits 12 13 Extra bit O None 1 Power fail 2 Even Parity 3 Odd parity 14 O Binary 1 Gray 15 Output control 0 Off 1 On 16 18 Acquisition mode 0 One Shot 1 Timer 2 3 Continuous 4 Channel Digital Input 0 18 22 Reserved 23 Read Complete Interrupt Enable 0 Off Default 1 On 24 29 Data length 1 to 32 30 31 Reserved 12 AXIS_SIZE Axis no Rd Returns the number of 16 bit registers allocated to an input channel 13 ENCODER TYPE Axis no Rd 0 Incremental 1 SSI 14 AXIS INPUTS Axis no Rd Returns the status of the axis post filter a INC_INPUTS Bit Status 0 Quadrature input A 1 Quadrature input B 2 Marker input M 3 Zero input Z 4 Limit input 0 5 Um input 1 SSI INPUTS Bit Status inverter inputs The bit fields indicate 0 or 1 depending on the state of the axis inputs Incremental inputs register formed from a variety of bit fields SSI inputs register formed from a variety of bit fields 0 Raw SSI data input Page 8 DEVA001 User s Manual 15 AXIS_STATUS INC_STATUS Axis no Bit Status 0 Power supply failure 1 Quadrature error SSI_STATUS Bit Status Power supply failure 0 1 Parity failure 2 Read complete occur 16 AXIS_OUT_EN INC_OUT_EN SSI OUT EN Axis no Bit Status 0 SSI Read Trigger 1 SSI Read Complete 3 1 3 Mar
27. No No Yes 66 TIMER OUT EN No No Yes 70 DAC MN No No No 71 DAC UV No No No 80 OUTPUT No No No 81 SERVO ENABLE No No No 90 PROBE 16 Yes Yes Yes 91 PROBE INPUT IZX Renishaw option Renishaw option Renishaw option 92 PROBE_INT Yes No Yes 93 PROBE FUNC Yes Yes Yes 94 PROBE INT VECT Yes Yes Yes 95 PROBE INT OCCUR Yes Yes Yes 96 PROBE SENSE Yes No No 97 PROBE LED MODE Yes Auto Auto 98 PROBE _ SOUND Yes Yes Yes 99 PROBE FOOTSWITCH Wes Yes Yes 100PROBE_LATCH_SEL Defaults to probe Defaults to probe Yes 101PROBE_OUT_EN No No Yes 110TIMESTAMP_NOW No No Yes 111TIMESTAMP_EVENT No No Yes 112TIMESTAMP_SEL No No Yes 120PULSEGENO No No Yes 121PULSEGENO MODE No No Yes 122PULSEGENO EN No No Yes 123PULSEGENO OCCUR No No Yes 124PULSEGENO OUT EN No No Yes 125PULSEGENO INT VECT No No Yes 130COMPAREO No No Yes 131ICOMPAREO FUNC No No Yes 132COMPAREO OCCUR No No Yes 133COMPAREO OUT EN No No Yes 134COMPAREO INT VECT No No Yes 135COMPARE1 No No Yes 136COMPARE1 FUNC No No Yes 137COMPARE1 OCCUR No No Yes 139COMPARE1 INT VECT No No Yes 140USEREVENTO OCCUR No No Yes 141USEREVENTO OUT EN No No Yes 1ms granularity Page 21 Device Driver Usage DEVAO001 User s Manual No Equate DEVAO001 issue 3 x DEVAO001 issue 4 1 DEVAOOI issue 4 2 150 BOARD INPUT EN No No Yes 151BOARD INPUT OCCUR No No Yes 152 BOARD INPUT INT OCCUHNo No Yes 155 AXIS INPUT EN
28. The card is installed by inserting it into any available PCI slot Page 5 Installation and configuration DEN AOOT User s Manual 2 2 3 2 2 3 1 2 2 3 2 2 2 3 3 Page 6 Device driver installation MS DOS installation The MSDOS driver has been discontinued please contact Deva if you have a requirement for this driver Windows 98 SE ME 2000 XP installation During the first re boot after the card has been installed windows will indicate that a new PCI device has been found and will start the standard driver installation procedure If this does not occur it is possible to initiate this process manually via the add new hardware icon in the control panel or via the windows device manager Follow the instructions and when requested select have disk and then browse to the directory on the installation CDROM containing the Deva001 inf file For example for Win2000 select PC interface products Deva001 Ilssue4 x Drivers Win2000 Deva001 inf Click ok and follow instructions to complete the installation The installation may be tested using the supplied DRO program which may be found on the CD in the utils win32 directory Windows NT4 installation To load the Windows NT driver go to the Winnt directory on the CDROM for the relevant product and locate the Deva001 inf file For example PC interface products Deva001 lssue4 x Drivers Winnt Deva001 inf Right click on the file and select install A message wil
29. _INPUT Board no Rd 92 PROBE INT Board no Rd Wr 93 PROBE FUNC Board no Rd Wr Page 12 Operation Allows access to the analog output channel for each axis in a system The value is in units of mV Allows access to the analog output channel for each axis in a system The value is in units of uV Operation Allows access to the system digital outputs The output is energised with a logical 1 Allows access to the system servo enable outputs for each axis The output is energised with a logical 1 Operation Returns the value of a 16 bit counter register latched by the last probe function or any other function the probe latch source is set to See commands 93 and 100 Returns either O or 1 depending on the state of the probe input Allows access to the card interrupt controller mask Writing a value of 1 0 enables disables the probe input interrupt This function is for special applications only Writing a value of 1 0 enables disables the channel probe function The probe function is DEVA001 User s Manual 94 PROBE_INT_VECT Board no Rd Wr 95 PROBE_INT_OCCUR Board no Rd 96 PROBE_SENSE Board no Rd Wr 97 PROBE_LED Board no Rd Wr 98 PROBE_SOUND Board no Rd Wr 99 PROBE_FOOTSWITCH Board no Rd Wr 3 1 11 Probe information extended Command amp equate Channel Ra Wr 100 PROBE_LATCH_SEL Axis no Rd Wr Value Source 0 Probe Occur 1 N A Read Counter 2 Pulse Generator 0 Sync Occur 3 User Ev
30. ams show the board level and channel level events and actions which may be programmed Page 50 DEVAO001 User s Manual 5 1 7 1 SSI board level block diagram Timer Occur Probe Occur PCI Absolute SSI interface hardware Pulse Generator 0 Occur Board Digital Input 0 Occur Channel 0 Interrupts Interrupt Controller Channel 1 Interrupts Channel 2 Interrupts Timer Timer Occur 0 1ms to 25 6ms 0 1ms Step Probe Occur Timer Syne Occur User Request 0 Board Digital Input 0 Occur Pulse Generator 0 Sync Occur Axis Compare 0 Sync Occur Y Time Stamper lus Resolution Axis Compare 1 Sync Occur Foot Switch Input Foot Switch L Foot Switch Occur Edge Detector ioi gt Digital Input SS Board Digital Input 0 Board Digital Input 0 Occur vi p Pos Edge Det si si Probe Occur a Foot Switch Occur g_y Board Digital User Request 0 Output 0 Timer Occur igi Timer TONT gy Board Digital 48 Digital UO User R tO Output 1 Byte Configurable Direction KA 16 Selectable Special I O N 3 Board Digital User Request 0 Output 2 Timer Occur ole Timer Sync Occur Sync Bus Level Sensitive Asserted Low Page 51 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 1 7 2 SSI channel level block diagram Channel 0 Latch 0 Read Complete gt Configuration 0 to 32 bits Count ol A A 0 to 15 bits Offset E E Shift ki aie 8
31. cted for each channel Gray to binary conversion The DEVA001 can perform Gray to binary conversion on incoming encoder data in hardware This feature may be independently selected for each channel Programmable interval timer The DEVA001 has an 8 bit interval timer which can be programmed in steps of 0 1ms up to a maximum of 25 6ms This timer may be used to generate interrupts or start encoder readings Page 49 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 1 5 5 1 6 Time Stamper The time stamper is a 16 bit high speed timer with a resolution of 1us It can be programmed to latch its value on an event so to provide an accurate time stamp at which the event occurred Digital 10 The DEVAO01 has 48 digital IO lines arranged in 3 groups of 16 bits The first group of 16 bits may be associated with special input and output functions specific to other features of the card and has hardwired directions The direction of the other 2 groups may be programmed in blocks of 8 bits Event System Many features of the card produce events When an event occurs a flag called the occur flag is set The occur flag may be polled by the user to establish that the event has occurred The card has a variety of actions which may be configured to respond to events The actions include triggering an encoder position read generating an interrupt triggering a digital output or latching a time stamp of the event The following diagr
32. cur flag NTR o N A Continuous Page 64 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito DlOie RCie Dl0e RCe RTs 2 0 RTs Read trigger event select register RCe Enable Disable read complete function Dl0e Enable Disable channel digital input 0 function RCie Enable Disable read complete interrupt DI0ie Enable Disable channel digital input O interrupt PaVa ELECTRONIC CONTROLS 52 Woodside Business Park Birkenhead Wirral CH41 1EL United Kingdom Tel 44 0 151 647 3222 Fax 44 0 151 647 4511 Email support deva co uk Web www deva co uk
33. d LabelPosition Channel With LabelPosition Channel Top Top Height Channel Visible True End With oad LabelMark Channel With LabelMark Channel Top Top Height Channel Visible True End With oad LabelVelocity Channel With LabelVelocity Channel Page 27 Device Driver Usage DEN AOOT User s Manual Top Top Height Channel Visible True End With oad LabelAccel Channel With LabelAccel Channel Top Top Height Channel Enabled True Visible True End With Next Channel End Sub Private Sub Form Unload Cancel As Integer Call close encoder End Sub Private Sub TimerUpdate Timer LabelName 1 Caption x LabelName 2 Caption y LabelName 3 Caption z For Channel 1 To 3 LabelPosition Channel Caption read encoder AXIS 32 Channel 1 LabelMark Channel Caption read encoder MARK 32 Channel 1 LabelVelocity Channel Caption read encoder VEL INST Channel 1 LabelAccel Channel Caption read encoder ACCEL INST Channel 1 Next Channel End Sub Page 28 DEVA001 User s Manual PCI Incremental encoder interface hardware 4 4 1 4 1 1 4 1 2 PCI Incremental encoder interface hardware Functional description The DEVAO001 is designed to interface up to three incremental encoders or linear scales to the PC PCI
34. ds 00h after system reset Please note that since the PCI interrupt system is level sensitive all interrupt requests must be cleared to free the interrupt line allocated the device The bit assignment for this register is as follows Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 CH2io CH1io CHOio BRDioT MRig TMRio Timer interrupt occurred BRDio Board interrupt s occurred CHOio Channel 0 interrupt s occurred CH1io Channel 1 interrupt s occurred CH2io Channel 2 interrupt s occurred Offset 08h Timer latch The lower 8 bits of the register at offset 08h are designated the Timer latch This read write register specifies the reload value in 0 1ms of the Timer function This register holds FFh after system reset Page 61 PCI Absolute SSI interface hardware DEVAO01 User s Manual 5 3 1 7 5 3 1 8 5 3 1 9 Offset 08h Timer counter The upper 8 bits of the register at offset 08h are designated the Timer counter This read only register returns the current value of the count down timer counter in 0 1ms When the timer function is disabled the timer counter resets to the value of the timer latch Offset OCh Time Stamper latch The lower 16 bits of the register at offset OCh are designated the Time Stamper latch This read only register allows acc
35. eeeeeeeneees 25 3 4 Device driver programming from Visual Basic 00 26 3 4 1 Function open_encoder AS INteQe cccssssseseeeeeeeeeeeeeeeeeeeeeeeeeeees 26 3 4 2 Function close encoder AS Integer rrrrrrrrrrrrrrttttrtttttttanaaannannnnnnn 26 3 4 3 Function read encoder ByVal com As Integer ByVal chan As Integer As LON aie ide cenit aaah 26 3 4 4 Function write_encoder ByVal com As Integer ByVal chan As Integer ByVal value As Long AS Integer cssssseeeeeeeeeeeeeseeeeeeeeees 26 3 4 5 Example Visual Basic programming cccccsesseeeeeeeeeeeeeeeeeeeneeeeeeeeeeeees 27 4 PCI Incremental encoder interface hardware 29 4 1 Functional description 0 cccceeeeeeeeeeeeeeeeeeeeeeeeseeneneeeeeeneees 29 41 1 Tele HE 29 CIS Marker TON e oases cae e a n dee 29 4 1 3 Zero MOUN e eee an see Sadan Seca ke n on e a n e ae 29 DEVAO01 PCI User s Manual Overview 4 1 4 Renishaw probe interface 000 0erarrrrrrrrrrrreseaaaaaaaaannnonnnnasansaaannnnnnnnnnnn 30 ke Eeer 30 4 1 6 Pulse GONG E 30 4 1 7 ele 30 41 8 TIMOR EE 30 A159 TIME SAM POL ene e nn e an n a n ie 31 4 11 10 Event SYSTON EE 31 4 2 Connection detailS raaeeeaeeeerrrrrranansasssssssannnnnanasanasannnonnn 34 4 3 Encoder input CONNECTIONS cccceeceeeeeeeeeeeeeeeeeeeeeeeeeeees 34 4 3 1 Input Signal descriptions sseeeeeeeee cece eeeeeeeeeeeeeeeeeeeeeseeeeneeeeeeeeeeeeees 35 4 3 2 Renisha
36. eeeenees 13 3 1 12 Time stamper information ssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 13 3 1 13 Pulse generator information ssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnman 14 3 1 14 Axis compare information cceeeeeeeeee eee ee eee eeeeeneeeneneeeeeeeeseeeeeeeeeeeeeeneees 14 3 1 15 User event information ssssssssssssnunnunuunnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnen n nnmnnn 15 3 1 16 Input event information ssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 15 3 1 17 Digital I O le TO E Le 17 3 1 18 FIFO buffer information cccccccccecceeeessneseseeesseeeeeeeeeeeeeeessesssssssesssseees 17 3 1 19 Software call back information cccceceesseeesseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 19 3 2 FUNCTION COMPAUIDUNY in ia e kisa s aske b sons ake soson kann n sonpknknanon 20 3 3 Device driver programming from C rrrrreessssterrrrrsasassasannn 23 3 3 1 short open encoder VOI cccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenees 23 3 3 2 void close encoder void ccccccccceeeeeseeeeeeeeeeeeeeeeseeseseeseeseseeesseneneesesnseneeees 23 3 3 3 long read encoder short command short channel eessen 23 3 3 4 void write encoder short command short channel long value 23 3 3 5 short enclib callback short receive long priority rrrrrrrrrrroororrrrrrren 24 3 3 6 Example C programming cccsssssseseeeeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeee
37. eeeeseeeneeeeeeeeeees 57 5 3 1 Register address Map 42e ere eee cette asoe kissa onn kode non ine eke saiiaptpstn 58 DEVA001 User s Manual Overview 1 1 Overview Product Features The DEVAO001 range of 3 axis incremental and absolute encoder interface cards have been designed to enable simultaneous reading of 3 encoders using a PC based system They can be used for a wide range of measurement and motion control applications such as CNC machines robotics and co ordinate measuring machines The range includes support for both PCI and ISA bus interfaces Both types share many common features however the PCI variant has several additional facilities Common Incremental interface features e Three encoder inputs for differential or single ended input e 32 bit counters for each encoder channel Marker input freeze capture for each encoder channel Zero input for each encoder channel e 5v 12v power supplies available on encoder connectors Digital filters on all channels Timer event driven interrupt logic e Optional Renishaw probe input Common Absolute interface features e Three encoder inputs e 32 bit register for each encoder channel e Programmable data and scan rates Programmable bit length and Gray to binary conversion Power fail and parity detection e 5v 12v power supplies available on encoder connectors Timer event driven interrupt logic Page 1 Overview DEVAO01 User
38. em reset The bit assignment for this register is as follows Interrupt mask Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito CH2ieCH1ie CH0ie BRDieT MRig Page 41 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 4 1 5 4 4 1 6 4 4 1 7 Bit Description Source TMRie Timer interrupt enable Timer reload occur flag BRDie Board interrupts enable Board occur flags Probe Pulse Generator 0 Board Digital Input 0 CHOie Channel 0 interrupts enable Channel 0 occur flags Marker Zero Channel Digital Input 0 Axis Compare 0 1 CH1ie Channel 1 interrupts enable Channel 1 occur flags Marker Zero Channel Digital Input 0 CH2ie Channel 2 interrupts enable Channel 2 occur flags Marker Zero Channel Digital Input 0 Offset 04 Interrupt request register This 16 bit read only register indicates which interrupt sources have generated interrupts Logic one indicates that an interrupt has occurred To clear an interrupt request the occurred flags of all associated interrupt sources must be cleared The register holds 0Oh after system reset Please note that since the PCI interrupt system is level sensitive all interrupt requests must be cleared to free the interrupt line allocated to the device The bit assignment for this register is as follows
39. end on both the clock frequency and the bit length as follows Reading time bit length 2 Clock frequency Bit length Clock frequency Reading time 12 625 KHz 22 4us 13 625 KHZ 24us 21 2 5 MHz 9 2us The offset feature allows the data read from the encoder to be shifted left a further O 15 bits This is typically used to align the angular part of the encoder data to the 16 bit boundary In this case the MSW represents the number of turns and the LSW represents the angular component Consider a system which has the following three encoders i 15 bit single turn encoder ii 12 bit single turn encoder iil 21 bit multi turn encoder with 13 bits of angular resolution By applying offsets of 1 4 and 3 bits respectively the angular component of the measurement will be aligned to the LSW of the latch in each case As a result of this all three encoders will return the same value for the same angle Power fail and parity detection The DEVA001 can be programmed to read an additional bit after the last data bit This bit may be treated as a parity bit or a power fail bit by the DEVA001 In the case of parity the DEVA001 performs a parity check and sets a status bit if the data fails Page 48 DEVAO01 User s Manual PCI Absolute SSI interface hardware 5 1 3 the test In the case of power failure the extra bit is latched and may be read from the status register These features may be independently sele
40. ent 0 Occur 4 Channel Digital Input 0 Occur 5 Axis Compare 0 Sync Occur 6 Axis Compare 1 Sync Occur 7 N A Axis Compare 1 Enable 101 PROBE OUT EN Board no Rd Wr Status Pulse Width 0 Probe Occur Occur to serviced 1 Footswitch Occur Occur to serviced 3 1 12 Time stamper information Command amp equate Channel 110 TIMESTAMP_NOW Board no 111 TIMESTAMP_EVENT Board no Rd Wr Rd Wr Rd Device Driver Usage level triggered by the probe input and the function reset automatically after execution of the function Allows access to the interrupt vector or interrupt call back executed by a probe input interrupt Returns a value of 1 every time a probe input interrupt has occurred Allows access to the probe sense control Writing a value of 0 1 sets probe operation to active high low 0 Off 1 On 2 Auto 0 Off 1 On n time in ms 0 Off 1 Auto 2 Auto Inverted Operation Controls the source event of the Probe associated latch of each axis Enables the probe digital outputs Specifying 1 0 in each bit field enables disables the equivalent digital output Operation Allows access to the current value of the 32 bit time stamper register in units of 1us Allows access to the latched value of the 32 bit time stamper register in units of 1us Page 13 Device Driver Usage 112 TIMESTAMP SEL Board no Value Source Probe Occur
41. er Syne Occur Bypass Pulse Generator 0 Sync Occur User Request 0 ee Probe Occur Bypass Pulse Generator 0 Sync Occur User Request 0 Channel Digital Input 0 Occur Axis Compare 0 Sync Occur Axis Compare 1 Sync Occur Latch 2 Comp 1 L Marker Input Marker Optional A B Sync Zero Input Zero Pos Edge Det Axis Limit 0 Input Axis Limit 1 Input Limits Active Low Channel Digital Input 0 Digital Input Pos Edge Det L L L gt User Request 0 Marker Occur Axis Compare 0 Occur Marker Occur Zero Occur gt Axis Compare 0 Occur Axis Compare 1 Occur Channel Digital Input 0 Occur Ve Ak A n A Comparators available only in Channel 0 ak Axis Compare 1 Occur Marker Occur Zero Occur Axis Limit 0 Status Axis Limit Status Channel Digital Input 0 Occur Channel Digital Output 0 Channel Interrupts Page 33 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 2 4 3 Connection details The DEVAOO1 has three input channels for quadrature signals from incremental encoders designated x y amp z Connection of each channel to the outside world is made through a 15 way D type connector The designation of the connectors is shown in the diagram below Encoder input channel x Encoder input channel y Encoder input channel z te ele ele Encoder input connections Connections to
42. er command handler Returns the total number of axis channels available from the installed cards Returns the total number of timers available from the installed cards Returns the total number of digital inputs available from the installed cards Returns the total number of digital to analog converters available from the installed cards Returns the total number of digital outputs available from the installed cards Returns the number of encoder cards present in the system Returns the card type identifier Returns the device driver version number multiplied by 100 Operation Allows direct 16 bit read write of the counter chip registers Page 7 DEVAO001 User s Manual Device Driver Usage 11 MODE Axis no Rd Wr Allows access to the mode registers of the incremental encoder counter chip or the SSI mode register INC_MODE Incremental mode number formed from a variety of bit fields Bit Function 0 3 Count mode 5 QUADx4AB read only 4 Invert quadrature signal A 5 Invert quadrature signal B 6 Invert marker signal M 7 Invert zero signal Z 8 Disable marker synchronisation with signals A amp B SSI MODE SSI mode number formed from a variety of bit fields Bit Function 0 2 ISA Frequency 0 2 50Mhz 1 1 25Mhz 2 625kHz 3 313kHz 4 156kHz 5 7 78 1kHz 0 2 PCI Frequency 0 2 78Mhz 1 1 39Mhz 2 694kHz 3 347kHz 4 174kHz 5 7 86 8k
43. ers Rd Returns the value of a 32 bit counter register latched by the last marker function or any other function the marker latch source is set to See commands 23 and 26 Rd Returns the counter velocity per interrupt time Page 10 DEVAO01 User s Manual 3 1 6 3 1 7 43 VEL FILT Axis no Rd 44 ACCEL INST Axis no Rd 45 ACCEL FILT Axis no Rd 46 PROBE 32 Axis no Rd 47 ABSOLUTE_32 Axis no Rd 48 TIMER_32 Axis no Rd Input status Command amp equate Channel Rd Wr 50 INPUT Input no Rd Timer information Command amp equate Channel Rd Wr 60 TIMER Timer no Rd Wr 61 TIMER INT Timer no Rd Wr 62 TIMER INT VECT Timer no Rd Wr 63 TIMER INT OCCUR Timerno Rd 64 TIMER LATCH SEL Axis no Rd Wr Value Source 0 Timer 1 Sync Occur 1 N A Read Counter 2 Pulse Generator 0 Sync Occur 3 User Event 0 Occur Device Driver Usage Returns 10 times the counter velocity per interrupt period filtered over 10 samples Returns the counter acceleration per interrupt time Returns 102 times the counter acceleration per interrupt period filtered over 10 samples Returns the value of a 32 bit counter register latched by the last probe function or any other function the probe latch source is set to See commands 93 and 100 Returns the 32 bit absolute position latched by the last read of an absolute SSI encoder Returns the value of a 32 bit counter value latched by the last timer 1 function or any
44. ess to the timestamp of the event associated with the Time Stamper The register holds zero after system reset Offset OCh Time Stamper counter The upper 16 bits of the register at offset OCh are designated the Time Stamper counter This read only register returns the current value of the count up time stamper counter in 1us 5 3 1 100ffset 20h 24h 28h Digital I O control status register The lower 16 bits of these registers are designated the Digital I O control status registers These read write registers allow control of the digital outputs and access to the digital inputs of the equivalent I O bus The register contents are zero after system reset Please note that on Digital I O bus 0 I Os 0 to 7 are hardwired as outputs and I Os 8 to 15 are hardwired as inputs 5 3 1 11 Offset 20h Digital UO bus 0 mux register The upper 16 bits of this register are designated the Digital UO bus 0 mux register This read write register allows control of the multiplexers source selectors of digital outputs on I O bus 0 For each digital output there are 2 selection bits allowing for 4 possible signal sources For a list of possible source routings on each pin please refer to section 5 2 3 1 Digital I O bus 0 mux register Page 62 DEVAOO1 User s Manual PCI Absolute SSI interface hardware Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
45. g tables list a number of tasks to be carried out when setting up and using a FIFO buffer Rd Wr Rd Wr Rd Wr Rd Wr Rd Wr Rd Operation Allows access to individual digital I O register bits Allows access to the direction of individual digital I Os This function only affects I Os that can be individually configured For further hardware details please refer to section 4 3 3 Digital 10 connections of this manual Allows access to 32 digital I O register bits Allows access to the direction of 32 digital I Os For I Os whose direction can only be configured in groups all bits of the group need to be set to the same direction For further hardware details please refer to section 4 3 3 Digital IO connections of this manual Returns the total number of digital I O available Set up task Related Function s operation Configure buffer clock which event triggers a data capture BUF_CLK_CHANNEL BUF_CLK_TYPE BUF_CLK_DIV Configure buffer data block how many and which data elements to be captured per buffer clock pulse BUF NUM DATA BUF DATA INDEX BUF DATA CHANNEL BUF DATA TYPE Set buffer size BUF SIZE Set buffer mode BUF MODE Usage task Related Function Enable buffer BUF EN Monitor amount of buffer contents BUF STATUS Read buffer contents BUF READ Command 8 equate Channel Rd Wr Operation 170 BUF_CLK_CHANNEL Buffer no Rd Wr C
46. hich provide access to 3 groups of 16 bits of digital IO The IO conforms to 5v TTL levels Voh min 2 4v at 8ma and Vil maximum 0 4 at 12ma 4 3 3 1 Digital IO connector 0 connections The direction of IO connector 0 pins is fixed Pins 1 to 8 IOO to 107 are outputs Pins 9 to 16 IO8 to 1015 are inputs Pin Connector 100 Special Function 1 100 URO MOx ACOOx User request 0 Marker occur x Axis compare 0 occur 2 101 URO MOy User request 0 Marker occur y 3 102 URO MOZ User request 0 Marker occur z 4 103 5 104 PO FO URO Probe occur Footswitch occur User request 0 6 IO5 TMRO TMRTCNT UROTimer occur Timer terminal count User request 0 7 IO6 PGOO PGOTCNT URO Pulse gen 0 occur Pulse gen 0 terminal count User request 0 8 IO7 URO User request 0 9 108 CDIOx Channel x digital input 0 10 O9 CDIOy Channel y digital input 0 11 010 CDIOzZ Channel z digital input 0 12 1011 13 1012 BDIO Board digital input 0 14 1013 15 1014 16 1015 17 GND 18 GND 19 5v 20 12v Page 36 DEVA001 User s Manual PCI Incremental encoder interface hardware 4 3 3 2 Digital IO connectors 1 and 2 connections The direction of IO connectors 1 and 2 pins is software configurable in groups of 8 1 to 8 and 9 to 16 Pin Connector 101 Connector 102
47. i CCLR31 16 CCR15 0 44h Y Channel status control register Y Channel clear control register CSR31 16 CCRI15 0 CCLR31 16 CCR15 0 48h Z Channel status control register Z Channel clear control register CSR31 16 CCR15 0 CCLR31 16 CCRI5 0 60h X Timer Latch X Timer Latch D31 o D31 0 64h Y Timer Latch Y Timer Latch D31 o D31 0 68h Z Timer Latch Z Timer Latch D31 o D31 0 80h X Marker latch X Marker latch D31 o D31 0 84h Y Marker latch Y Marker latch D31 o D31 0 88h Z Marker latch Z Marker latch D31 o D31 0 AOh X Probe latch X Probe latch D31 o D31 0 A4h Y Probe latch Y Probe latch D31 o D31 0 Ash Z Probe latch Z Probe latch D31 o D31 0 4 4 1 1 Offset 00h Special function control register The lower 16 bits of the register at offset 0Oh are designated the Special function control register This read write register allows control of board based facilities The register contents are zero after system reset Page 39 PCI Incremental encoder interface hardware 4 4 1 2 Special function control register DEVAO01 User s Manual ITMRe_ Enable Disable timer function ITSTs_ Time stamper event select register DI0ie Enable Disable board digital input O interrupt PG0Oe Enable Disable pulse generator O function PGOie Enable Disable pulse generator 0 interrupt PGOcr Pulse generator 0 control
48. ice driver See section 3 1 for a description of the command and channel parameters Entry command 16 bit command channel 16 bit channel Exit returns 32 bit value void write_encoder short command short channel long value Writes a 32 bit integer to the device driver See section 3 1 for a description of the command and channel parameters Entry command 16 bit command channel 16 bit channel value 32 bit value Exit none Page 23 Device Driver Usage DEN AOOT User s Manual 3 3 5 short enclib_callback short receive long priority Enables software call backs A user level function can be defined as call back function by setting the function address function pointer as the interrupt vector value using the appropriate _INT_VECT function of section 3 1 Please note that this function is required only for Microsoft Windows operating systems Call backs are currently available only to a single software application process Entry S receive 16 bit flag 1 to enable 0 to disable priority 32 bit call back thread priority defined in winbase h e For high speed operations THREAD_PRIORITY_TIME_CRITICAL THREAD_PRIORITY_HIGHEST THREAD_PRIORITY_ABOVE_NORMAL THREAD_PRIORITY_NORMAL e For not real time notifications THREAD_PRIORITY_BELOW_NORMAL THREAD_PRIORITY_LOWEST THREAD_PRIORITY_IDLE Exit returns O if no error returns 1 if already enabled for this process returns 2 if aresource allocation error occurs Page
49. information Command amp equate Channel Page 14 Allows access to the interrupt vector or interrupt call back executed by a pulse generator 0 interrupt Operation DEVA001 User s Manual 130 COMPAREO Axis no 131 COMPAREO FUNC Axis no 132 COMPAREO OCCUR Axis no 133COMPAREO OUT EN Axis no 134 COMPAREO_INT_VECT Axis no 135 COMPARE1 Axis no 136 COMPARE1_FUNC Axis no 137 COMPARE1_OCCUR Axis no 139 COMPARE1_INT_VECT Axis no 3 1 15 User event information Command amp equate Channel 140 USEREVENTO OCCUR Board no 141USEREVENTO OUT EN 1 O no 3 1 16 Input event information Command amp equate Channel 150 BOARD_INPUT_EN 151 BOARD_INPUT_OCCUR Board no 152 BOARD_INPUT_INT_VECT Board no 155 AXIS_INPUT_EN Axis no Board no Rd Wr Rd Wr Rd Rd Wr Rd Wr Rd Wr Rd Wr Rd Rd Wr Rd Wr Rd Wr Rd Wr Rd Wr Rd Wr Rd Rd Wr Rd Wr Device Driver Usage Allows access to the 32 bit axis compare 0 register Writing a value of 1 0 enables disables the axis compare 0 function Returns a value of 1 every time an axis position compare 0 has occurred Writing a value of 1 0 enables disables the axis compare 0 digital output Allows access to the interrupt vector or interrupt call back executed by an axis compare 0 interrupt Allows access to the 32 bit axis compare 1 register Writing a value of 1 0 enables disables the axis compare 1 function Returns a value of
50. interface card is supplied with a software support CDROM containing support for all Deva 001 encoder interfaces along with support and information for many of Deva s other products The CDROM includes the following items MS DOS device driver and Windows 9x NT4 2000 ME XP device drivers providing coherent encoder interface card hardware management Windows 9x NT4 2000 ME XP DLL and import library containing the driver access functions C language library routines and header files which create a simple interface to device driver functions Example C programs illustrating card read write using device driver functions Visual Basic Module which provides constant and function definitions to allow simple DLL access Example Visual Basic programs illustrating card read write using device driver functions National Instruments LabVIEW driver VI library Demonstration Digital Readout Program for both Windows and MSDOS PCI Plug and Play cards System requirements The device driver library functions and the demonstration software require an IBM PC compatible 486 or above recommended with one spare PCI slot System processor requirements for use with Windows and LabVIEW will depend on the application but at least Pentium is recommended Card Installation The DEVA 001 requires 4k bytes of memory space which is automatically assigned by the Plug and Play manager OS BIOS when the computer is rebooted with the card installed
51. inuous mode of operation which starts a new reading as soon as the encoder indicates it is ready without the side effect that could otherwise cause the system to lock up in an un synchronised state in the presence of noise The 12V and 5V power supply pins may be used to supply the dc power requirements for the encoders Page 55 DEVAO001 User s Manual PCI Absolute SSI interface hardware 5 2 3 Digital IO connections There are three 20 pin headers labelled 100 101 and IO2 which provide access to 3 groups of 16 bits of digital IO The IO conforms to 5v TTL levels Voh min 2 4v at 8ma and Vil maximum 0 4 at 12ma 5 2 3 1 Digital IO connector 0 connections Pin Connector 100 Special Function 1 IOO URO RTRIGx RCOx User request 0 Read trigger x Read complete occur x 2 101 URO RTRIGy RCOy User request 0 Read trigger y Read complete occur y 3 ID2 URO RTRIGz RCOz _ User request 0 Read trigger z Read complete occur z 4 103 5 104 URO User request 0 6 IO5 TMRO TMRTCNT UROTimer occur Timer terminal count User request 0 7 lo6 URO User request 0 8 IO7 URO User request 0 9 108 CDIOx Channel x digital input 0 10 0O9 CDIOy Channel y digital input 0 11 1010 CDIOz Channel z digital input 0 12 1011 13 1012 BDIO Board digital input 0 14 1013 15 1014 16 015 17 GND 18 GND 19 5v 20 12v Page 56 DEVA
52. it 3 694 KHz 4 463 KHz 5 347 KHz 6 174 KHz 7 86 8 KHz 5 3 1 140ffset 40h 44h 48h Channel status register 0 The upper 16 bits of these registers are designated Channel status register 0 These read only registers allow access to channel based status information These bits are treated as dont cares when writing to these registers Channel status register 0 Bit 20 DIOo Bit 19 RCo Bit 18 RARF Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 17 Bit 16 ko TE SE oa e sie AGS de ae ee PWRFDI Page 63 PCI Absolute SSI interface hardware Di Direct SSI data channel input PWRF Power failure or no encoder flag PARF Parity failure flag RCo Read complete occur flag DIOo Channel digital input 0 occur flag 5 3 1 150ffset COh C4h C8h Channel control register 1 DEVAO001 User s Manual The lower 16 bits of these registers are designated Channel control register 1 These read write registers allow control of the SSI read trigger and other channel based facilities The registers hold zero after a system reset Channel control register 1 Read trigger events RTs Source User Request 0 flag Timer Sync occur flag Channel Digital Input 0 oc
53. ker information Command amp equate 20 MARK_16 21 MARK_INPUT 22 MARK_INT 23 MARK_FUNC 24 MARK_INT_VECT Channel Axis no Axis no Axis no Axis no Axis no Rd Rd Rd Wr Rd Rd Rd Wr Rd Wr Rd Wr Device Driver Usage Returns the axis status register The bit fields indicate 0 or 1 depending on the status bit Incremental status register formed from a variety of bit fields SSI status register formed from a variety of bit fields Enables the axis digital outputs Specifying 1 0 in each bit field enables disables the equivalent digital output N A SSI axis digital output enable register formed from a variety of bit fields Operation Returns the value of a 16 bit counter register latched by the last marker function or any other function the marker latch source is set to See commands 23 and 26 Returns either 0 or 1 depending on the state of the marker input Allows access to the card interrupt controller mask Writing a value of 1 0 enables disables an interrupt from the marker input This function is for special applications only Writing a value of 1 0 enables disables the channel marker function Allows access to the interrupt vector or interrupt call back executed by a marker input interrupt Page 9 Device Driver Usage DEN AOOT User s Manual 3 1 4 3 1 5 25 MARK_INT_OCCUR Axis no Rd Returns a value of 1 every time a marker
54. l 0 shared withNo Yes probe input B1 ZERO INT Yes No Yes 32 ZERO FUNC Zero function performed in No IZero function performed in software software 33 ZERO INT VECT Yes No Yes B4 ZERO INT OCCUR Yes No Yes 40 JAXIS 32 B2 bit hardware counter 32 bit hardware counter B2 bit hardware counter 41 IMARK_32 B2 bit hardware latch value32 bit hardware latch value32 bit hardware latch value 42 VEL INST Software generated using Yes based on software Yes timer 1 interrupt system Omer 43 VEL FILT Software generated using Yes based on software Yes timer 1 interrupt system Omer 44 ACCEL_INST Software generated using Yes based on software Yes timer 1 interrupt system Omer 45 ACCEL_FILT Software generated using Yes based on software Yes timer 1 interrupt system Omer 46 IPROBE_32 32 bit hardware latch value32 bit hardware latch value32 bit hardware latch value 47 ABSOLUTE_32 Yes Yes Yes Page 20 DEVA001 User s Manual Device Driver Usage No Equate DEVAO001 issue 3 x DEVAO001 issue 4 1 DEVA001 issue 4 2 48 TIMER 32 No No B2 bit hardware latch value 50 INPUT Yes No No 60 TIMER Timer 1 value x 0 1ms Timer 1 value x 0 1ms Timer 1 value x 0 1ms 61 TIMER INT Timer 1 No Yes 62 TIMER INT VECT Timer 1 No Yes 63 TIMER INT OCCUR Timer 1 No Yes 64 TIMER LATCH SEL No No Yes 65 TIMER1 FUNC
55. l be displayed to indicate successful installation It is now necessary to re boot the computer The installation may be tested using the supplied DRO program which may be found on the CD in the utils win32 directory DEVA001 User s Manual 3 1 3 1 1 3 1 2 Device Driver Usage Device driver functions Device Driver Usage The supplied MS DOS and Windows 9x NT4 2000 ME XP device drivers provide a simple method of accessing card functions and remove the need for direct register programming Use of the device driver ensures that the user s application software is compatible with other Deva products and is protected from any future changes in the card hardware or register layout The device driver determines the total number of axes and UO available from all the cards in a system This section describes the functions provided by the device driver whilst the compatibility chart in section 3 2 details the functions available from particular cards System information Command amp equate 0 VECTOR 1 NUM AXES 2 NUM TIMERS 3 NUM INPUTS 4 NUM DACS 5 NUM OUTPUTS 7 NUM_BOARDS 8 CARD_TYPE 9 VERSION_NUM Channel information Command amp equate 10 CNT_16 Channel Not used Not used Not used Not used Not used Not used Not used Not used Not used Channel Axis no Rd Wr Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Wr Rd Wr Operation Provides a vector to the device driv
56. lag N A direct counter read Pulse Generator 0 Sync occur flag User Request 0 flag Channel Digital Input 0 occur flag Axis Compare 0 Sync occur flag Axis Compare 1 Sync occur flag NTO O17 BY OT POT oO Axis Compare 1 Enable PCI Incremental encoder interface hardware Page 45 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 4 1 16Offset 40h 44h 48h Channel clear register The upper 16 bits of these registers are designated the Channel clear registers These write only registers can be used to clear occur flags of channel based facilities by writing 1 to the equivalent bit The status of all relevant flags is cleared after system reset Channel clear register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 AC1c ACOc ER1c EROc DlOc Die Clear channel digital input 0 occur flag EROc Clear error 0 quadrature occur flag ER1c Clear error 1 power occur flag ACOc Clear axis compare 0 occur flag AC1c Clear axis compare 1 occur flag 4 4 1 17Offset 40h 44h 48h Channel status register The upper 16 bits of these registers are designated the Channel status registers These read only registers allow access to channel based status information Channel status register
57. lag Pulse Generator 0 Sync occur flag BY OTM Offset 00h Special function clear register The upper 16 bits of the register at offset OOh are designated the Special function clear register This write only register can be used to clear occur flags of board based facilities by writing 1 to the equivalent bit The status of all relevant flags is cleared after system reset Special function clear register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 fe oh ue ios be EE Dolt Tan s StemMRee F SE 28 TMRce Clear timer occur flag TSTc Clear time stamper overflow occur flag Dioc Clear board digital input 0 occur flag Offset 00h Special function status register The upper 16 bits of the register at offset OOh are designated the Special function status register This read only register allows access to board based status information These bits are treated as don t cares when writing to this offset Special function status register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Poa jks ap E swen k E Dot L ISTOTIMROE t t E TMRo Timer occur flag TSTo Time Stamper overflow occur flag DIOo Board Digital Input 0 occu
58. led and then re enabled Marker synchronisation with signals A amp B can optionally be disabled Zero input The Z input circuit designated zero is a positive edge triggered input which can asynchronously latch the counter value It has been provided to maintain compatibility with previous issues and offer more flexibility when connecting encoders The marker function which accurately latches the counter value is equally suited to performing a zero type operation by using the latched value as an offset which is subsequently subtracted from the counter reading Page 29 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 1 4 Renishaw probe interface The DEVAOOI incorporates a Renishaw compatible probe input This input provides the correct signal conditioning to allow a volt free contact type touch probe to be used The probe function works like the marker function but latches all three axis counters simultaneously Unlike the marker function it operates asynchronously and hence does not require that the A and B signals are at a logic one level The probe function has its own enable bit The card also incorporates an output to drive the probe led an output to drive an audible sounder and a further input to allow the probe to be controlled via a footswitch Digital 10 The DEVAO01 has 48 digital IO lines arranged in 3 groups of 16 bits The first group of 16 bits may be associated with special input and output functions
59. lock output E H Out Out output 8 Data Data input RS422 line receiver 9 Spare Spare output Da Ge 10 11 12V 12 volts supply ae 12 4 5V 5 volt supply 13 OV 0 volt common 14 15 12V 12 volt supply Note Do not connect the 15 way D type plug from a VGA monitor into one of the encoder input channels as damage may result SSI signal descriptions The SSI interface uses two differential signals clock and data which have the connections Clock Clock Data and Data The DEVAO01 has a third uncommitted signal designated Out with the connections Out and Out which may be controlled to select encoder dependent features such as forward reverse The Spare and Spare connections should be left unconnected The Deva001 interrogates the encoder for its positional value by sending a pulse train from its clock output The number of clock pulses depends on the bit length of the encoder The first high low transition at point 1 triggers the encoders monostable and parallel data is stored in the encoders parallel to serial converter While the monostable is at logic O no more parallel data can be stored in the parallel to serial converter At the first low high transition at point 2 the most significant data bit is output by the encoder and received on the data input At each subsequent low high transition in the pulse train the next highest bit is transmitted The pulses continuously re trigger the monostable so that i
60. n close_encoder As Integer Closes the device driver Entry none Exit returns O if no error returns 1 if error Function read_encoder ByVal com As Integer ByVal chan As Integer As Long Returns in a 32 bit integer the result of reading the device driver See section 3 1 for a description of the command and channel parameters Entry command 16 bit command channel 16 bit channel Exit returns 32 bit value Function write_encoder ByVal com As Integer ByVal chan As Integer ByVal value As Long As Integer Writes a 32 bit integer to the device driver See section 3 1 for a description of the command and channel parameters Entry a command 16 bit command channel 16 bit channel value 32 bit value Exit none Page 26 DEVA001 User s Manual 3 4 5 Example Visual Basic programming Device Driver Usage Encoder card MSVB example Option Explicit Dim Axes name 1 To 12 As String Dim Version string As String Dim Channel As Integer Dim temp As Integer Private Sub Form Load If open encoder lt gt 0 Then Call MsgBox Unable to load Driver Info vbExclamation Digital Read Out End End If Call write encoder TIMER 1 10 Call write_encoder TIMER_INT 1 1 For Channel 1 To 3 Call write encoder MARK FUNC Channel 1 1 Load LabelName Channel With LabelName Channel Top Top Height Channel Visible True End With oa
61. nasananaasaaanonnnoanaanananan 2 Synchronised measurement of three encoders aeeeeeeasassanaannnnnnnan 2 Telescope directional feedback cccccccessseeeeeeeeeeeeseeenseneneneeeeeeeeseeeees 2 Support SoftWare ensi eee ko a e kb aa pk kn ro kipa ra kk a ke e ai a 3 Windows 98 NT4 2000 ME XP 0v2eeeereserressssstesssssssssasenaoaasooaannnonanannnonannnnan 3 National Instruments LabVIEW c cccecceecceeccesceecceeeeeeeeseeeeeneeeeeseeseees 3 Digital PROG e EE 3 AS S SONE EE 4 Installation and CONfiQuratiONn scscceeeeeeeeeeeeeeeee 5 Software support CDROM cccceseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeees 5 PCI Plug and ROUER TEE 5 System requirements ae irik are s ce bk ile kos is deeen eesti a eet 5 Gard InstallatiON ebe e e nn e ko n A Ee 5 Device driver installation 0 ccccceecceceeeceecceeccesceeseeeeeuseeseeeeenseeseeseenseeees 6 Device Driver Usage siriako nananana enues 7 Device driver functions 02cecccececeeeececececeececececeeeeneeeeeeeeeenes 7 System infor EE 7 GhHanne liAfORA ANON sac Ge ea Gees 7 Marker information w ki ek n nn ke othe eee eee 9 Zero information ee ee ee 10 ele e EE 10 lee TT 11 Timer information WEE 11 DAC Control konti te dot te ee ee eS es 12 Overview DEVAO01 PCI User s Manual 3 1 9 OUIPUt Gorete ee ence ae en eee 12 3 1 10 Probe information EE 12 3 1 11 Probe information extended cccceecessseeeeeeeeeeeeeeseeeeeeeeeeeeeeeee
62. ontrols the channel timer board axis of the event that triggers a buffer data capture 171 BUF_CLK_TYPE Buffer no Rd Wr Controls the type of event that triggers a buffer data capture Page 17 Device Driver Usage Value Timer Event 0 Timer 1 Occur Value Board Event 1 Probe Occur 2 Board Digital Input 0 Occur 3 User Event 0 Occur Value Axis Event 16 Marker Occur 17 Zero Occur 18 Pulse Generator 0 Occur 19 Axis Compare 0 Occur 20 Axis Compare 1 Occur 21 Channel Digital Input 0 Occur 22 SSI Read Complete Interrupt Occur DEVA001 User s Manual functions 172BUF_CLK_DIV Buffer no Rd Wr Controls the buffer clock divider 173BUF_NUM_DATA Bufferno Rd Wr Specifies the number of data elements to be captured in a FIFO buffer block on each clock pulse 174BUF_DATA_INDEX Buffer no Rd Wr Selects which data element of a FIFO buffer block is accessed by data element BUF_DATA_CHANNEL and BUF_DATA_TYPE 175BUF DATA CHANNEL Buffer no Rd Wr Controls the channel buffer board axis of the data to be captured 176BUF_DATA_TYPE Buffer no Rd Wr Controls the type of data to be captured Value Buffer Data Note 0 Buffer clock counter Resets on a buffer Enable Flush or Configuration Value Board Data 1 Time Stamp Now See command 110 TIMESTAMP_NOW 2 Time Stamp Event See command 111 TIMESTAMP_EVENT 3 Digital I O See command 1
63. r contents are zero after system reset Channel control register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit8 Bit7 Bit6 Bits Bit4 Bit3 Bit2 Bit1 Bito L2s 2 0 L1s 2 0 Los 1 0 Dl e MSe Ze jinvZ mv invB nvA Me Page 44 DEVA001 User s Manual Me Enable Disable marker function invA Invert signal A invB Invert signal B invM Invert signal M invZ Invert signal Z Ze Enable Disable zero function MSe Enable Disable marker synchronisation with signals A amp B DI0ie Enable Disable channel digital input O interrupt LOs Latch 0 Timer latch select register Lis Latch 1 Marker latch select register L2s Latch 2 Probe latch select register Source events of Latch 0 Timer latch LOs Source Timer Sync occur flag N A direct counter read Pulse Generator 0 Sync occur flag GIN o User Request 0 flag Source events of Latch 1 Marker latch Lis Source Marker occur flag Zero occur flag Pulse Generator 0 Sync occur flag User Request 0 flag Channel Digital Input 0 occur flag Axis Compare 0 Sync occur flag Axis Compare 1 Sync occur flag NTO O17 BY OT PT oO Axis Compare 0 Enable Source events of Latch 2 Probe latch L2s Source Probe occur f
64. r flag Page 60 DEVAO0O1 User s Manual PCI Absolute SSI interface hardware 5 3 1 4 Offset 04 Interrupt mask register 5 3 1 5 5 3 1 6 This 16 bit read write register sets the interrupt masks to select which interrupt sources generate interrupts A logic zero disables an interrupt and a logic one enables an interrupt The register holds zero after system reset The bit assignment for this register is as follows Interrupt mask Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito CH2ieCH1ie CH0ie BRDieT MRig Bit Description Source TMRie Timer interrupt enable Timer reload occur flag BRDie Board interrupts enable Board occur flags Probe Board Digital Input 0 CH te Channel 0 interrupts enable Channel 0 occur flags Read complete Channel Digital Input 0 CH1ie Channel 1 interrupts enable Channel 1 occur flags Read complete Channel Digital Input 0 CH2ie Channel 2 interrupts enable Channel 2 occur flags Read complete Channel Digital Input 0 Offset 04 Interrupt request register This 16 bit read only register indicates which interrupt sources have generated interrupts Logic one indicates that an interrupt has occurred To clear an interrupt request the occurred flags of all associated interrupt sources must be cleared The register hol
65. read only register returns the current value of the count up time stamper counter in 1us 4 4 1 100ffset 10h Pulse Generator 0 latch The lower 16 bits of the register at offset 10h are designated the Pulse Generator 0 latch This read write register specifies the reload value in quadrature counts of the pulse generator 0 function Writing to this register resets the pulse generator O counter This register holds zero after system reset 4 4 1 110ffset 10h Pulse Generator 0 counter The upper 16 bits of the register at offset 10h are designated the Pulse Generator 0 counter This read only register returns the current value of the pulse generator 0 up down counter in quadrature counts The pulse generator 0 counter resets to zero on a write operation to the pulse generator 0 latch This register holds zero after system reset 4 4 1 120ffset 20h 24h 28h Digital UO control status register The lower 16 bits of these registers are designated the Digital I O control status registers These read write registers allow control of the digital outputs and access to the digital inputs of the equivalent I O bus The register contents are zero after system reset Please note that on Digital I O bus 0 I Os 0 to 7 are hardwired as outputs and I Os 8 to 15 are hardwired as inputs Page 43 PCI Incremental encoder interface hardware DEVAO01 User s Manual 4 4 1 130ffset 20h Digital UO bus 0 mux register The upper
66. register URO Enable Disable user request 0 flag Time stamper event sources TSTs Source Probe occur flag Timer Sync occur flag User Request 0 flag Board Digital Input 0 occur flag Pulse Generator 0 Sync occur flag Axis Compare 0 Sync occur flag Axis Compare 1 Sync occur flag Reserved NTO OTT BT OPT e Pulse Generator 0 control register bit fields PGOcr bit Function 0 Direction of operation 1 positive O negative 1 Bi Directional mode 1 On 0 Off 2 Hardware Control Start Stop 1 On 0 Off 3 Deglitch mode 1 On 0 Off Offset 00h Special function clear register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito URO PGOcr 3 0 PGOielPGOe DlOie TSTs 2 0 TMReFs Be Fe Pe Pe Enable Disable probe function Fe Enable Disable footswitch function Be Enable Disable buzzer output Fs Footswitch input sense The upper 16 bits of the register at offset 0Oh are designated the Special function clear register This write only register can be used to clear occur flags of board based facilities by writing 1 to the equivalent bit The status of all relevant flags is cleared after system reset Special function clear register Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
67. roducts The device drivers and the common software interface are described in section 3 For applications where hardware access is essential the following sections give an overview of the register set and card functionality 5 3 1 Register address map The card implements several 32 bit read write registers which are grouped by function and appear at different offsets within the 4k memory space allocated to the card by the plug and play bios operating system Page 58 DEVA001 User s Manual PCI Absolute SSI interface hardware Offset Read Function Write Function ooh Special Function status control register Special Function clear control register SFS31 16 SFR15 0 SFC31 16 SFR15 0 04h Interrupt request mask register Interrupt mask register IRR31 16 IMR15 0 IMR15 0 08h Timer counter latch Timer latch TMRC31 16 TMR iQ TMRL7 Q och Time Stamper counter latch TSTC31 16 TSTL15 0 10h 20h Digital Output bus 0 mux I O bus 0 status Digital Output bus 0 mux control DOM31 16 DIOS15 o DOM31 16 DOC7 0 24h Digital UO bus 1 direction status Digital UO bus 1 control DIOD17 16 DIOS15 0 DIOC15 0 28h Digital UO bus 2 direction status Digital UO bus 2 control DIOD17 16 DIOS15 0 DIOC15 0 40h X Channel status control register X Channel clear control register CSR3
68. s Manual 1 1 3 1 2 1 2 1 1 2 2 1 2 3 Page 2 PCI specific features PCI interface cards from issue 4 2 onwards have the following additional set of facilities e 16 32 TTL level digital IO Flexible event system Axis Compare Pulse generator Time stamper Data acquisition buffer Typical applications A few examples are given to illustrate how the Deva 001 may be effectively used within a target application Co ordinate measuring machine In this application the linear incremental encoders from the X Y and Z axes are connected to the X Y and Z channel of the Deva 001 Each encoder has a marker or index signal which is connected to the M input This will allow a reference cycle to be performed when the equipment is switched on A measurement probe is connected to the Renishaw touch probe input This will allow the X Y and Z axes positions to be captured when the probe is deflected Synchronised measurement of three encoders The PCI variant of the Deva001 is able to make measurements of encoder position Synchronised in hardware to several different events including timer pulse generator axis compare and digital input For this example the pulse generator is programmed to generate an event every 10 counts of the master encoder Every time an event is generated the card is programmed to capture all three encoder positions Captured data is placed in a user configurable FIFO buffer and may be retrieved by user
69. t of free memory available to FIFO buffers in units of data elements Returns the maximum number of data elements that can be captured by a FIFO buffer on each clock pulse Returns the total number of FIFO buffers available to the system Operation Returns the number of lost software call backs since this function was last read Page 19 Device Driver Usage 3 2 Function compatibility DEVA001 User s Manual No Equate DEVAO001 issue 3 x DEVAOOI issue 4 1 DEVAOOI issue 4 2 0 VECTOR Yes No No 1 NUM AXES B channel 0 2 3 channel 0 2 3 channel 0 2 2 NUM TIMERS 2 timer 1 for user only 2 timer 1 for user only 2 timer 1 for user only 8 NUM INPUTS 6 input 0 5 0 0 4 NUM DACS 0 0 0 5 NUM OUTPUTS 0 0 0 7 NUM BOARDS 0 0 Number of encoder cards 8 CARD TYPE Yes Yes Yes 9 MERSION NUM Yes Yes Yes 10 CNT 16 Yes Yes Yes 11 MODE Mode 5 or SSI CMR Mode 5 or SSI CMR INC or SSI mode 12 AXIS SIZE 2 x 16 bits 2 x 16 bits 2 x 16 bits 13 IENCODER_TYPE Yes Yes Yes 14 AXIS_INPUTS No No Yes 15 AXIS _ STATUS No No Yes 16 AXIS OUT EN No No Yes 20 MARK 16 Yes Yes Yes 21 MARK INPUT Yes Yes Yes 22 MARK INT Yes No Yes 23 MARK FUNC Yes Yes Yes 24 MARK INT VECT Yes Yes Yes 25 MARK INT OCCUR Yes Yes Yes 26 MARK LATCH SEL Defaults to marker Defaults to marker Yes 27 MARK OUT EN No No Yes 30 ZERO INPUT Yes channe
70. the register set and card functionality Register address map The card implements several 32 bit read write registers which are grouped by function and appear at different offsets within the 4k memory space allocated to the card by the plug and play bios operating system Page 38 DEVA001 User s Manual PCI Incremental encoder interface hardware Offset Read Function Write Function ooh Special Function status control register Special Function clear control register SFS31 16 SFR15 ol SFC31 16 SFRI5 0 04h Interrupt request mask register Interrupt mask register IRR31 16 IMR15 0 IMR15 0 ogh Timer counter latch Timer latch TMRC31 16 TMRL7 Q TMRL7 Q och Time Stamper counter latch TSTC31 16 TSTLis 0 40h Pulse Generator 0 counter latch Pulse Generator 0 latch PGOC31 16 PGOL15 0 PGOL15 0 20h Digital UO bus 0 mux status Digital UO bus 0 mux control DOM31 16 DIOS15 o DOM31 16 DOC7 0 24h Digital UO bus 1 direction status Digital UO bus 1 control DIOD17 16 DIOS15 0 DIOC15 0 28h Digital UO bus 2 direction status Digital UO bus 2 control DIOD17 16 DIOS15 0 DIOC15 0 40h X Channel status control register X Channel clear control register CSR31 16 CCR15 o
71. these sockets should be made with reference to the following pin out table and simplified input circuit Pin Number Signal Function 1 Ai A phase input 2 Bi B phase input GO Zi Zero input 4 Mi Marker input 5 nLimO Limit O 6 nAi nA phase input 180 3 H nBi nB phase input 8 nZi nZero input A a 9 nMi NMarker input nAixp ANN 10 nLim1 nLimit 1 11 12V 12 volts supply Zen line receiver 12 HOV 5 volt supply ah 13 OV 0 volt common t ik 14 nLimOxpb NAN b nLimit0 15 12V 12 volt supply Note Do not connect the 15 way D type plug from a VGA monitor into one of the encoder input channels as damage may result Page 34 DEVA001 User s Manual PCI Incremental encoder interface hardware 4 3 1 4 3 2 Input signal descriptions The Ai amp nAi Bi amp nBi inputs are differential pairs for connection to the A phase and B phase quadrature outputs of an incremental encoder The Mi 8 nMi inputs are differential inputs for the channel marker signal This function will latch the counter reading for the relevant channel allowing an accurate reading of the position of a moving encoder to be made at a specific instant The marker function does not stop the counter itself which is able to continue reading the encoder position and so it will not cause the card to lose track of the system s datum position The Zi amp nZi may be used as an alternative to the Mi
72. ts output stays at logic zero preventing further storage of data When the least significant bit is Page 54 DEVAO0O1 User s Manual PCI Absolute SSI interface hardware received by the DEVAOOI1 the pulse train is terminated The monostable is no longer triggered and at point 4 after an interval tm the output returns to logic 1 allowing the storage of new parallel data in the parallel to serial converter clock S Mi GE xo H ts tm data l ToS a es e a Monostable Register value Clock frequency Clock period tc Setup time ts 0 2 78 MHz 0 36 uS 0 1 us 1 1 39 MHz 0 72 us 0 1 us 2 926 KHz 1 08 uS 0 1 us 3 694 KHz 1 44 us 0 1 us 4 463 KHz 2 16 us 0 1 us 5 347 KHz 2 88 us 0 1 us 6 174 KHz 5 76 uS 0 1 us 7 86 8 KHz 11 5uS 0 1 us Under normal circumstances the encoder data should go to logic 0 after point 3 returning to logic 1 at point 4 indicating the encoder is ready to be read again The DEVAOO0O1 waits for the data to return to logic 1 before it starts any subsequent readings If the data does not go to logic O at point 3 the DEVAOOt1 assumes that synchronisation with the encoder has been lost at some time before or during the reading The DEVA001 now outputs up to 32 clock pulses until a logic O is detected at this point the clock is stopped and the DEVA001 waits for the encoder mono stable to time out This re synchronisation process makes possible the cont
73. w probe input CONNECTIONS ccccccceeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeees 35 4 3 3 Digital IO CONNECHONS vire aie nek cases fete nsec ded cade eege See 36 B34 SYNC CON NMECTON E 37 4 4 Direct hardware programmMing s sceccceeeeeeeeeeeeeeeeeeeeeeees 38 4 4 1 Register address MAP ccccceeeeeeeseeeeeeeeeeeeeeeeeeeeeeesseneeeeeeeeeeeeeeeseees 38 5 PCI Absolute SSI interface hardware rrrrrrrreee 48 5 1 Fu nctional description e esac vives aki kk apa ya ka pan easa osans pokasy enben 48 5 1 1 Programmable clock frequency bit length and offset 48 5 1 2 Power fail and parity AEteCtiOn ccccccceeeeeeeeeeeeeeeeeeeeeeesenneeneeeeeeeeeess 48 5 1 3 Gray to binary conversion icceicsccccecsaecccicececcetsides secdceceeiccetectaciiersiticenness 49 5 1 4 Programmable interval titmer eeceeeeeeeseeeeeeeeeeeeeeeeeeeeeeeneeeeeeeees 49 BTS TIME Stampe E 50 5 1 6 DIQRA IER ege eege 50 e E AT JEVONE SYSTON EE 50 5 2 Connection details ik kise ar isaa sasa kib kan bosi akiobasn anan ak osssskasokbone 53 5 2 1 Encoder input CONNECTIONS cceeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeseeeeeeeeeeeneees 54 5 2 2 SSI signal descriptions ei io cscs ve secede kon n in l n l ki a din 54 5 2 3 Digital lO CONMGCUONS 46e kk kek bb oaas obstak o dako do bo bi east san k dap nnmnnn nnna 56 5 24 SYNC GON NASC TON EE 57 5 3 Direct hardware programMing scecceeeee

DEVA001 PCI encoder interface card User's Manual

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