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Kinetis Quick Reference User Guide

1. 141 Chapter 16 FlexCAN Module VOL A cH M 145 IOLI Hiro T 145 I Xe iL EET 146 15 2 Contrario EX LER iii bi 146 Dee ur iA doa rIDelio om 147 IZLI Cod czample and Boecl ic me 147 1622 a 149 162 21 Code example and explana Oi serorari nrin repete to Flo kr R NANT MR REAR HU IRPIPHR EAR EA Po a EH EEEREN RSEN MER 149 A DEQUOSHL o e IHE dte oid cence hs abet Lo eate su ooo MledtU xoc EM Su Pete Lilo at nae ated f redet 149 16231 Cagsexsmple arid SAO dio EU HIS ee hut DS REL daz be Oa E pd iaee sa 149 De ME CONI TO 150 16 241 Codeooxampleand explo dani 150 15 2 5 Conaligur don of RX FIFO ID fiker table elements A ii 151 16231 Codecxumiple and expli bad 151 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 11 Section number Title Page Chapter 17 Segment LCD Controller TEL PR c Mr PT 1353 ER ioa beceui ca sate Sansa cancun A catia PipM LR pee qi bee ea Ld Mar ase e dde Red 133 Ta PCI SEDIS rise ii A oia iii plis 154 GEO POSE PEN mmm 155 LA RT or ori liada A 155 ES IAS A M 156 175 1 General routing and pIACORIEFIL ni pa 156 170 EMC and ESD et E 156 PE AE AE a T o o E P A is 156 ET Denoon COE 2 aoi eua id e A aa 158 Chapter 18 Touch Sense Input TSI Module ILS o mmm 1
2. 122 136 POR Design Recommendation a eec oorpore a 123 GOTI LAO suo M 123 EO AI Taeneral Routing and Place ue dp eph Tae eee praebebat E ico 123 Chapter 14 USB Device Charger Detection USBDCD Module E o vm 125 DLL VPRO 1 CIA E 125 VALLA I iodo iaa ci 125 141 3 Battery charger peca il ia 126 12 Moduls A diene ERE 126 142 1 Module dep dE rin RARA AA 126 Lia DEN rn mln ON oi 127 IET onu ess PTT 128 Chapter 15 Universal Serial Bus OTG Module pb MUTA A ERR IR Uf dbabiadibce t t dido cable asse iM dudo p vapio iati bio ctio M dBIE Id uti t ed du M Dic dp ado dnbs oU ud idet de to 131 13 0 ca LNs P 131 15 3 USB Operation modes d 131 Kinetis Quick Reference User Guide Rev 2 08 2012 10 Freescale Semiconductor Inc Section number Title Page 54 VOS TU operation A 132 A o O erdt ded pir one dae aiemianate 134 1x5 Module dependencies acusa peat bruni plos eds desea Ulp ei Re osuere o God v a R 134 1332 USR Enid tuis m 134 D33 VU EUA A iia 136 13 5 RE OI A ios 136 ol Connection dia ir EH 136 15 62 Components and placement SUELES OE pi ii 138 503 Lagsutregorsie Nel I HB qae pact anvanipaatasiagnieciesaiaelapsocd stamp ob ic didus ac Ea UM duin iR M OA ROE 139 NM ong rel pt AA AA AAA NE 140 13 7 1 Device CO 140 PE cla m o A
3. Additional examples can be found in Normal c and more detailed descriptions of each SSD API can be found in the FTFL SSD User s Manual ErrorTrap returnCode 8 6 Additional resources In addition to the Flash Memory Module chapter of the Kinetis Reference Manual related information regarding the FTFL can be found in the following documents on http www freescale com e Standard Software Driver for FTFL User s Manual included in FTFL SSD download AN4282 Using the Kinetis Family Enhanced EEPROM Functionality Kinetis Quick Reference User Guide Rev 2 08 2012 82 Freescale Semiconductor Inc Chapter 9 Using the FlexMemory 9 1 Using the FlexNVM 9 1 1 Overview This quick start guide demonstrates how to configure devices that offer the FlexMemory 9 1 1 1 Introduction The flash memory module FTFL includes several accessible memory regions depending on the device configuration Program flash Non volatile flash memory that can store program code and data e FlexNVM Non volatile flash memory that can store program code store data and backup EEPROM data FlexRAM Byte writeable RAM memory that can be used as traditional RAM or as high endurance EEPROM storage Program flash only devices have two blocks of flash with 2 KB sectors and offer swap capability FlexMemory enabled devices have one block of program flash with 2 KB sectors one block of FlexNVM with 2 KB sectors and one block of FlexRAM but do
4. RXDV CRSDV Magnetics RJ45 MIIO RXCLK 4 MIIO RXER RMIIO RXER j RXCLK RXERR MIIO TXCLK TXCLK TXEN Differential MII RMII interface TX TX MIlO_TXEN RMIIO_TXEN MIIO_TXD 3 2 MIIO TXD 1 0 RMIIO TXD 1 0 MIIO CRS MIIO COL lt ACT LINK SPEED TXD 3 2 TXD 1 0 CRS COL INT RST XO XI VDD GND Kinetis MII RMII interface 17 signals N C N C RSTIN 25MHz pin osc Figure 13 3 MII connection NOTE The indicates special precautions that must be taken for a each specific Ethernet PHY manufacturer The CRSDV function may be located in either pin NOTE The TXER signal is not required for this example this is why there are 17 signals and not 18 13 5 RMII mode The reduced media independent interface RMII is a configuration mode that requires nine signals to communicate to a generic PHY The RMII operates at 50 MHz and requires synchronization between the PHY and the ENET RMII interface clock input EXTAL Depending on the PHY specifications the clock options used by the MCU can be PHY clock input PHY clock output if provided Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 121 RMII mode 13 5 1 Code example and explanation The following example code shows the registers needed to configure the MAC NET controller in RMII mode Example code PORTA PCR14 P
5. Configure NVIC to enable interrupts if isCANO NVICICPRO NVICICPRO amp 0x07 lt lt 29 0x07 29 Clear any pending interrupts on FLEXCANO NVICISERO NVICISERO 0x07 lt lt 29 0x07 29 Enable interrupts for FLEXCANO NVICICPR1 NVICICPR1 amp 0x1F lt lt 0 0x1F Clear any pending interrupts on FLEXCANO NVICISER1 NVICISER1 0x1F lt lt 0 Ox1F Enable interrupts for FLEXCANO else NVICICPR1 NVICICPR1 OxFF 5 OxFF 5 Clear any pending interrupts on FLEXCAN1 NVICISER1 NVICISER1 OxFF 5 OxFF 5 Enable interrupts for FLEXCAN1 Now configure pins for FlexCAN Configure CAN RX TX pins muxed with PTE24 25 for FlexCAN1 PORTE PCR24 PORT PCR MUX 2 PORT PCR PE MASK PORT PCR PS MASK PORTE PCR25 PORT PCR MUX 2 PORT PCR PE MASK PORT PCR PS MASK Now everything is ready and it is time to initialize the FlexCAN step by step as shown below 1 Make sure FlexCAN module is disabled after reset it is disabled Select clock source for FlexCAN by setting clearing CTRL1 CLK_SRC bit Enable FlexCAN module by clearing MCR MDIS bit Wait until FlexCAN module is out of low power mode MCR LPM_ACK 0 Wait until FlexCAN goes into freeze mode MCR FRZ_ACK 1 Initialize other MCR bits as needed a Enable the individual filtering per MB and reception queue features by setting MCR IRMQ bit Enable th
6. 17 6 EMC and ESD considerations The charge pump can be sensitive in a noisy environment Therefore use the external voltage for the LCD reference VLL3 to EXT V When the VLL3 is connected to 3 3 V either the charge pump or the bias resistor network can generate VLL1 and VLL2 17 6 1 Code example and explanation For LCD initialization and use of the SLCD module these steps must be followed 1 Enable the SCLD clock gate SCGC3 SLCD 1 LCD clock gate enable 2 LCD analog operation for all used LCD pins PORTx PCRn MUX 0 3 Prepare and ensure that the LCD clock source is available Kinetis Quick Reference User Guide Rev 2 08 2012 156 Freescale Semiconductor Inc AKI A Chapter 17 Segment LCD Controller 4 Configure the NVIC The SLCD interrupt vector in K40 is 102 the NVIC must be configured as follows NVICISER2 l 1 lt lt 22 NVICICPR2I 1 22 5 LCD General Control Register GCR Configure the LCD clock source SOURCE bit Select 1 0 V or 1 67 V for 3 V or 5 V glass HREFSEL Enable regulated voltage RVEN Trim the regulated voltage RVTRIM Enable charge pump CPSEL bit Configure charge pump clock LADJ 1 0 Configure LCD power supply VSUPPLYT 1 0 Configure LCD frame frequency interrupt LCDIEN bit Configure LCD behavior in low power mode LCDWAIT and LCDSTP bits Configure LCD duty cycle DUTY 2 0 Select and configure LCD frame frequency LCLK 2 0 6 Enable pi
7. EEE Chapter 4 Clocking System MCGPLLCLK this is the output of the PLL and is available any time the PLL is enabled MCGIRCLK this is the output of the selected IRC The selected IRC will be enabled whenever this clock is selected MCGFFCLK this is either the slow IRC or the external clock source divided by the FLL external reference divider FRDIV This clock is available in all modes except FLL bypassed internal FBI and bypassed low power internal BLPI when the slow IRC is selected The source of this clock is selected by the value of the internal reference select bit IREFS In addition to the clocks provided by the MCG there are three other system level clock sources available for use by various peripheral modules OSCERCLK this is the clock provided by the system oscillator and is the output of the oscillator or the external square wave clock source ERCLK32K this is the output of the RTC oscillator or the system oscillator if it is set to provide a 32 kHz clock in low power mode e LPO this is the output of the low power oscillator It is an on chip very low power oscillator with an output of approximately 1 kHz that is available in all run and low power modes 4 1 3 Configuration examples The MCG can be configured in one of several modes to provide a flexible means of providing clocks to the system for a wide range of applications Some of the more commonly used modes are described in the following confi
8. VBAT The VBAT supply pins can be driven independently from VDD but should be powered up to at least VBATmin Since there is no equivalent LVD circuitry for the VBAT supply the VBAT minimum is the POR release point POR max 1 5 V External bypass capacitors should be supplied XTAL32 and EXTAL32 Connected to a secondary watch crystal for supplying clock to the RTC module No load capacitors or bias resistor is required as these are supplied internally Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 53 Using the mode controller 5 2 Using the mode controller 5 2 1 Overview This section will demonstrate how to use the Mode Controller MC The MC is responsible for controlling the entry and exit from all of the run wait and stop modes of the MCU This module works in conjunction with the PMC and the LLWU to wakeup the MCU and move between power modes 5 2 1 1 Introduction There are 10 power modes They are described below Run Default Operation of the MCU out of Reset On chip voltage regulator is On full capability 2 Wait ARM core enters Sleep Mode NVIC remains sensitive to interrupts Peripherals Continue to be clocked 3 Stop ARM core enters DeepSleep Mode NVIC is disabled WIC is used to wake up from interrupt peripheral clocks are stopped 4 Very Low Power Run VLPR On chip voltage regulator is in a mode that supplies only enough power to run the MCU in
9. The MPU is a Freescale Kinetis module for memory protection This module should not be confused with ARM s MPU ARM s MPU is not integrated in Kinetis MCUs However both Freescale and ARM MPU shared the same purposes regions protection access permissions and overlapping regions protection In addition the Freescale MPU provides access error detection and multiple bus masters monitor 6 1 3 Features A Memory Management Unit MMU is designed for complex memory management and memory protection in microprocessors with Translation Look aside Buffer TLB paging dynamic allocation access protection and virtual memory This MMU implementation will be costly for the overall system it will have a large memory footprint higher power consumption paging segmentation and larger die size for Kinetis MCUs Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 65 Configuration examples The MPU module is designed for less complex memory management without TLB paging dynamic allocation and virtual memory It provides lower power consumption and no paging segmentation therefore an MPU is better suited for MCUs 6 1 4 Configuration examples 6 1 4 1 Region descriptors setup Example code define TCML BASE 0x20000000 Upper SRAM bitband region define TCML SIZE 0x00010000 MPU Configuration MPU RGDO WORD2 0 Disable RGDO Set RGD1 MPU RGD1 WORDO 0 Start address MPU_RGD1
10. fb ad 14 PORTA PCR25 PORT PCR MUX 5 fb ad 13 PORTA PCR26 PORT PCR MUX 5 fb ad 12 PORTA PCR27 PORT PCR MUX 5 fb ad 11 PORTA PCR28 PORT PCR MUX 5 fb ad 10 PORTD PCR10 PORT PCR MUX 5 b ad 9 PORTD PCR11 PORT PCR MUX 5 b ad 8 PORTD PCR12 PORT PCR MUX 5 fb ad 7 PORTD PCR13 PORT PCR MUX 5 b ad 6 PORTD PCR14 PORT PCR MUX 5 fb ad 5 PORTE PCR8 PORT PCR MUX 5 fb ad 4 PORTE PCR9 PORT PCR MUX 5 b ad 3 PORTE PCR10 PORT PCR MUX 5 fb ad 2 PORTE PCR11 PORT PCR MUX 5 fb ad 1 PORTE PCR12 PORT PCR MUX 5 fb ad 0 control signals PORTA PCR11 PORT PCR MUX 5 fb oe b PORTD PCR15 PORT PCR MUX 5 fb rw b PORTE PCR7 PORT PCR MUX 5 fb cs0 b PORTE PCR6 PORT PCR MUX 5 fb ale 8 bit write vuint8 MRAM START ADDRESS n OxAC 8 bit read rdata8 vuint8 MRAM START ADDRESS n 16 bit write vuint16 MRAM START ADDRESS n 0x1234 16 bit read rdatal6 vuintl6 amp MRAM START ADDRESS n 32 bit write vuint32 MRAM START ADDRESS n 0x87654321 32 bit read rdata32 vuint32 amp MRAM START ADDRESS n Alt 5 XA XA n offset n offset n offset n n n offset offset offset Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 103 PCB design recommendations 11 1 1 4 Hardware implementation Eight data lin
11. 16 data lines 16 data lines 16 data lines AD 81 0 AD 31 0 AD 15 0 AD 15 0 AD 15 0 AD 15 0 Non Up to 30 Up to 24 Up to 21 N A N A N A N A N A muxed address address address mode A 29 16 AD 23 0 Up to AD 20 0 Up to AD 15 0 Up to 8 data lines 8 data lines 16 data lines AD 31 24 Up AD 31 24 AD 31 16 to 16 address AD 15 0 Up to16 data lines AD 31 16 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc LATT Using the Flexbus module Table 11 2 FlexBus signals on LCD devices Signals AD 31 0 CS 5 0 Muxed mode Up to 32 address Up N A N A N A N A N A N A N A to 32 data lines AD 31 0 Non muxed Up to 24 N A N A N A N A N A N A N A mode address AD 23 0 Up to 8 data lines AD 31 24 Up to 16 address AD 15 0 Up to16 data lines AD 31 16 Up to 16 N A N A N A N A N A N A N A data lines AD 15 0 or AD 31 16 LCD mode 11 1 1 2 4 Burst cycles The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination The initiation of a burst cycle is encoded on the size pins For burst transfers to smaller port sizes FB_TSIZ 1 0 indicates the size of the entire transfer 11 1 1 2 5 Data Byte Alignment and Physical Connections The device aligns data transfers in FlexBus byte lanes with the nu
12. EDMAC DADDR 0x1FFF9000 Destination Address 0x500 Ext RAM DMAC TCDO W5 0 EDMAC CITER E LINK Do not set ELINK bit no channel linking EDMAC CITER 0x1 Current Iter Count gt 1 NBYTES transfer EDMAC DOFF 0x0 Destination addr offset 0x0 no increment DMAC TCDO W6 EDMAC DLAST 0x0 Do not adjust DADDR upon channel completion DMAC TCDO W7 0 EDMAC BITER Ox1 Beginning Iteration Count 1 CITER EDMAC _BWC 0x0 Bandwidth control 0 gt No eDMA stalls EDMAC MAJOR LINKCH 0x0 Ignored no channel linking gi Ej Bd Bd B i Configure DMA Channel 1 TCD EDMAC TCD1 WO EDMAC SADDR uint32 amp command Source Addr address of command var EDMAC TCDi W1 0 EDMAC SMOD 0xO Source Modulo feature disabled EDMAC SSIZE 0x2 Source Size 0x2 32 bit transfers EDMAC DMOD 0xO Destination Modulo feature disabled EDMAC DSIZE 0x2 Destination Size 0x2 gt 32 bit transfers EDMAC SOFF 0x0 Source addr offset 0x0 do not increment EDMAC TCD1 W2 EDMAC NBYTES 0x4 Transfer 4 bytes per channel activation EDMAC TCD1 W3 EDMAC SLAST 0x0 Do not adjust SADDR upon channel completion EDMAC TCD1 W4 EDMAC DADDR 0x4003B000 Dest Addr ATD Command Word Register E y DMAC TCD1 W5 0 EDMAC CITER E LINK Do not set ELINK bit no channel linking ED
13. Freescale Users Guide KQRUG Rev 2 08 2012 Kinetis Peripheral Module Quick Reference A Compilation of Demonstration Software for Kinetis Modules This collection of code examples useful tips and quick reference material has been created to help you speed the development of your applications Most chapters in this document contain examples that can be modified to work with Kinetis MCU Family members When you are developing your application consult your device data sheet and reference manual for part specific information such as which features are supported on your device Sample code can be found at KINETIS512_SC zip available from http freescale com Information about the ARM core can be found in the help center at http ARM com The most up to date revisions of our documents are on the Web Your printed copy may be an earlier revision To verify that you have the latest information available refer to http freescale com O Freescale 2012 All rights reserved e Lg K freescale Revision History Revision Page Date Level Description Number s 11 2010 0 Initial release N A Added two new chapters Chapter 8 Using the Flash Software Drivers and Chapter 20 Using OPAMP for Kinetis Microcontrollers Updated Fig 13 3 Fig 13 4 and Fig 13 5 of Chapter 13 ENET Module Also updated Section 13 5 1 1 Hardware Implementation 03 2012 1 of the same chapter N A Added a
14. PHY DUPLEX STATUS Full duplex ENET RCR amp unsigned portLONG ENET RCR DRT MASK ENET TCR ENET TCR FDEN MASK else half duplex ENET RCR ENET RCR DRT MASK ENET TCR amp unsigned portLONG ENET TCR FDEN MASK Setup speed if usData amp PHY SPEED STATUS 10Mbps ENET RCR ENET RCR RMII 10T MASK if configUSE PROMISCUOUS MODE gut ENET RCR ENET RCR PROM MASK Hendif Hifdef ENHANCED_BD ENET_ECR ENET_ECR_EN1588_MASK else ENET ECR 0 Hendif Set Rx Buffer Size ENET MRBR unsigned portSHORT configENET RX BUFFER SIZE Point to the start of the circular Rx buffer descriptor queue ENET RDSR unsigned portLONG amp xENETRxDescriptors 0 Point to the start of the circular Tx buffer descriptor queue ENET TDSR unsigned portLONG xENETTxDescriptors Clear all ENET interrupt events NET EIR unsigned portLONG 1 HN Enable interrupts ENET EIMR ENET EIR TXF MASK ENET EIMR RXF MASK ENET EIMR RXB MASK ENET EIMR UN MASK ENET EIMR RL MASK ENET EIMR LC MASK ENET EIMR BABT MASK ENET EIMR BABR MASK ENET EIMR EBERR MASK Create the task that handles the MAC ENET RX RTOS TCP IP stack dependent Enable the MAC itself ENET ECR ENET ECR ETHEREN MASK Indicate that there have been empty receive buffers produced ENET RDAR ENET RDAR RDAR MASK Static void prvInitial
15. size of EERAM block UINT32 EEEBlockSize size of EEE block BOOL DebugEnable debug mode enable bit PCALLBACK CallBack pointer to callback function FLASH SSD CONFIG PFLASH SSD CONFIG The values of these structure members are defined when the user selects a value for the define riasn_pertvative in SSD_FTFL h For devices that feature FlexMemory parameters DFlashBlockSize and zriashBlocksize are initialized in the riasntnit function based on the values in the D Flash information row IFR caliBack is a function pointer that allows the user to specify a function that is called to service a time critical event An example of such an event is a watchdog service routine but another type of function can be called if the duration of a flash command operation exceeds a certain timeout period 8 4 2 SSD derivative The value of the define rzasu berrvarive in SSD_FTFL h selects additional defines that assigns corresponding values to the program flash block size program flash block base data flash block size data flash block base and the FTFL register base e On the TWR K60N512 Tower Module which has 512 KB of program flash the appropriate value for FLASH DERIVATIVE iS FTFL KX 512K OK OK e On the TWR K40X256 Tower Module which has 256 KB of program flash 256 KB of FlexNVM and 4 KB of FlexRAM the appropriate value for riasH_peRtvarive 1S FTFL KX 256K 256K 4K 8 5 Demo code CAUTION A flash memory loc
16. 1 5 At this point the application is polling the PTBO pin for VBUS detection but a port interrupt can also be used to avoid polling method Waiting for VBUS if FLAG CHK 0 GPIOB PDIR amp amp FLAG CHK VBUS Flag gu8InterruptFlags USBDCD CONTROL USBDCD CONTROL IE MASK USBDCD CONTROL IACK MASK FLAG SET USBDCD CONTROL START SHIFT USBDCD CONTROL FLAG SET VBUS Flag gu8InterruptFlags 6 Finally when the detection sequence is completed the application needs to read the results in the DCD registers and send them to the terminal DCD results if FLAG CHK DCD Flag gu8InterruptFlags u8Error DCD GetChargerType if u8Error amp OxFO0 printf Oooooops DCD Error else if u8Error amp OxOF STANDARD HOST printf Connected to a Standard Host if u8Error amp OxOF CHARGING HOST printf Connected to a Charging Host if u8Error amp OxOF DEDICATED CHARGER printf Connected to a Dedicated Charger The function that returns the charger type result is UINT8 DCD GetChargerType void UINT8 u8ChargerType u8ChargerType UINT8 USBDCD STATUS amp USBDCD STATUS SEQ RES MASK gt gt 16 u8ChargerType UINT8 USBDCD STATUS amp USBDCD STATUS FLAGS MASK gt gt 16 return u8ChargerType Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 129 Example code The DCD interrupt service routine void DCD ISR void USBDCD CONTROL USBDCD CONTR
17. 19 2 Configuration example In this case the ADC is configured simply to read and average singled ended inputs The ADCO inputs are not connected to anything of interest for this demo but are just demonstrated to function ADC1 both when using the A registers and when using the B registers is configured for channel 20 which matches with the onboard potentiometer This means that of the four conversions scheduled two are for ADCI And both of the ones for ADC1 are on channel 20 which is K2 which is the POT The ADCs are configured to be triggered by the PDB and the PDB is configured to output four triggers each PDB cycle ADCO is activated in this case but also not connected to the POT It is also triggered by the PDB however its readings do not contribute to the digital filter resulting in the fifth output of the demonstration program POT reading 19 2 1 PDB triggered single ended ADC conversions There are several steps taken in the course of the execution of this demo involving setting up the peripherals These steps are further detailed with code from the adc_demo project and explained in the sections that follow numbered after the manner of the steps 1 Turn on clocks to the ADC and PDB module using the SIM module 2 Configure System Integration Module for defaults as far as ADC 3 Configure the Peripheral Delay Block PDB 4 Determine the configuration the ADC using a structure to store the desired configuratio
18. 2 08 2012 86 Freescale Semiconductor Inc eee ee AAA Chapter 9 Using the FlexMemory The bytes not assigned to data flash via the FlexNVM Partition Code are used by the FTFL to obtain an effective endurance increase for the EEPROM data The built in EEPROM record management system raises the number of program erase cycles that can be attained prior to device wear out by cycling the EEPROM data through a larger EEPROM NVM storage space The endurance factor of a subsystem can be calculated for a partitioned device using the formula Endurance_Subsystem E Flash 2 EEESPLIT EEESIZE EEESPLIT EEESIZE Record_Efficiency Endurance_Factor Where Endurance_Subsystem Maximum writes to EERAM for a given subsystem E Flash allocated EEPROM backup for each subsystem min 16 KB max 128 KB EEESPLIT Split factor for subsystem A B 0 5 0 5 or 0 25 0 75 or 0 125 0 875 EEESIZE allocated RAM for EEE min 32 bytes max 4 KB Record_Efficiency 0 5 for 16 bit and 32 bit writes 0 25 for 8 bit writes Endurance_Factor 10000 native cycles Example 1 A Kinetis device configured as in example 2 with 2 subsystems of 2 KB of EERAM backed up by 128 KB of E Flash provides 310 000 cycles with 16 bit or 32 bit writes for each subsystem Endurance subsystem E Flash 2 EEESPLIT EEESIZE EEESPLIT EEESIZE Record_Efficiency Endurance_Factor Endurance subsystem 128 KB 2 5 4 KB 5 4 KB 5 10 000 Endurance_subsystem 124 K
19. 24bitaddress z I EZPQ High Z 1 Data 1 i Data 2 0000000 Figure 10 1 READ command timing Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 91 Using the EzPort module EZBOS Wo _ _ command 24bitaddress EZPD HAD Li EZPQ High Z i 97MM wow nmm 1 EZPCS em UVTI M Du mmy EZPD 40900900 i EZPO uc Figure 10 2 FAST READ command timing 10 1 1 4 Status register The Ezport module provides a status register to reflect some reset out flash status and also write progress flags The FS FLEXRAM and BEDIS bits reflect flash security FIexRAM configurations and whether bulk erase is supported under secure mode respectively The status register can be read with the RDSR command to check reset out status and whether a write command has completed Table 10 3 Ezport status register 7 6 5 4 3 2 1 0 FS WEF FLEXRAM BEDIS WEN WIP 10 1 2 Configuration examples Kinetis Quick Reference User Guide Rev 2 08 2012 92 Freescale Semiconductor Inc SSS eee Chapter 10 EzPort Module 10 1 2 1 Hardware connections Any SPI master could be used to connect to the Ezport module for flash programming Either QSPI or DSPI module on existing Coldfire devices could be used in this case Figure 10 3 shows the connection between the QSPI module on MCF5282 and Kinetis Here QSPI_CS1 and QSPI_CS2 are used as
20. AIEN OFF DIFF SINGLE AIEN OFF DIFF SINGLE LK ADICLK BUS can be anything can be anything since not using compare feature ADC SC1 ADCH 31 ADC SC1 ADCH 31 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 175 Configuration example 19 2 1 5 Using ADC driver Configure ADC as it will be used but because ADC_SC1_ADCH is 31 the ADC will be inactive Channel 31 is just disable function There really is no channel 31 ADC Config Alt ADCO BASE PTR amp Master Adc Config config ADC 19 2 1 6 Calibrate ADCs Calibrate the ADCs in the configuration in which they will be used and then restore the desired configuration ADC Cal ADCO BASE PTR do the calibration The structure still has the desired configuration So restore it Why restore it The calibration makes some adjustments to the configuration of the ADC These are now undone config the ADC again to desired conditions ADC Config Alt ADCO BASE PTR amp Master Adc Config Repeat this for both ADC s However we will only use the results from the ADCI wired to the Potentiometer on the Kinetis Tower Card Repeating for ADC1 ADC Config Alt ADC1 BASE PTR amp Master Adc Config config ADC ADC Cal ADC1 BASE PTR do the calibration Configure the ADC again to default conditions ADC Config Alt ADC1 BASE PTR amp Master Adc Config 19 2 1 7 Enable ADC and PDB interrupts Enable the AD
21. If the wakeup source s interrupt flag is not cleared by the LLWU interrupt handler then the next interrupt vector for the wakeup source is taken and the flag in the port or module can be cleared Code execution then continues with the instruction following the WFI instruction that sent the MCU into the low power mode For VLLS1 VLLS2 or VLLS3 the exit is always through the reset vector and then through the interrupt vector of the LLWU There is a WAKEUP bit in the SRS register that allows the user to tell if the reset was due to an LLWU wakeup event An example of wakeup test code is shown here if MC SRSL amp MC SRSL WAKEUP_MASK printf outSRS Pin Reset wakeup from low power modes Wn The state of PMCTRL LPLLSM prior to clearing due to update of PMPROT indicates which power mode was exited and should be used by initialization software for proper power mode recovery if MC PMCTRL amp MC PMCTRL LPLLSM MASK printf outSRS Pin Reset wakeup from Normal Stop n if MC PMCTRL amp MC PMCTRL LPLLSM MASK 2 printf outSRS Pin Reset wakeup from Very Low PowerStop VLPS n if MC PMCTRL amp MC PMCTRL LPLLSM MASK 3 printf outSRS Pin Reset wakeup from Low Leakage Stop LLS n The I O states and the oscillator setup are held if the wakeup event is from VLLS1 VLLS2 or VLLS3 The user is required to clear this hold by writing to the ACKISO bit in the LLWU CS register Prior to relea
22. LCD GCR VSUPPLY 1 0 3 LCD GCR LCDIEN MASK LCD GCR FDCIEN MASK LCD GCR ALTDIV 0 0 3 LCD GCR LCDWAIT MASK LCD GCR LCDSTP MASK LCD GCR LCDEN MASK LCD GCR SOURCE MASK LCD GCR LCLK 3 0 3 LCD GCR DUTY 7 0 3 Enable LCD pins 0 32 LCD PENH 0x00000001 LCD PENL OxFFFFFFFF Enable LCD pins used as Backplanes 0 7 LCD BPENH 0x00000000 LCD BPENL 0x000000FF Configure backplane phase LCD WF3TOO 0x08040201 LCD WF7TO4 0x80402010 Fill information on what segments are going to be turned on Front Plane information LCD WF11TO8 OxFFFFFFFF LCD WF15TO12 OxFFFFFFFF Complete information of all Front planes Enable LCD module LCD GCR LCD GCR LCDEN MASK 17 7 Demonstration code The demo code allows the user to experiment with the SLCD module in real time write your own messages control contrast blinking vertical scroll experiment with the new LCD segment feature fault detection select the clock source for the module work on LCD low power modes change the frequency of operation and so on The demonstration code is prepared for the TWR K40 TWRPI SLCD and the communication board Kinetis Quick Reference User Guide Rev 2 08 2012 158 Freescale Semiconductor Inc S Chapter 17 Segment LCD Controller bee J HT iN gt freescale A Figure 17 2 Tower system with TWR K40x256 and the TWRPI SLCD The segment LCD included in the TWRPI SLC
23. On the TWR K60N512 Tower Module which has 512 KB of program flash with address 0x0000 0000 0x0007 FFFF the above example will erase the flash sector in the address range 0x0007_F800 0x0007_FFFF Onthe TWR K40X256 Tower Module which has 256 KB of program flash with address 0x0000_0000 0x0003_FFFF the above example will erase the flash sector in address range 0x0003 F800 0x0003 FFFF Performing a program operation The following example illustrates how to perform a program operation using the Program Section command It assumes that an erase operation has already been performed on the area to be programmed BORK KK KK ke RK RK KK kk ke KK RR k ok Sk Sk k RR RK RRR RR RK RRR RR RR KK RRR k k k FlashProgramSection HR KK KR RR KK RK KR KK KR RRR KK RR RRR RRR k k k k k RR k k k k RR ee k k k x f Write some values to EERAM for i 0 i lt 0x10 1 4 WRITE32 flashSSDConfig EERAMBlockBase i 0x11223344 Program the values to PFLASH phraseNumber 0x2 destination PFLASH BLOCK BASE PBLOCK SIZE phraseNumber FTFL PHRASE SIZE returnCode pFlashProgramSection amp flashSSDConfig destination phraseNumber pFlashCommandSequence if FTFL_OK returnCode ErrorTrap returnCode The Program Section command programs the data stored in the section program buffer to previously erased locations in the flash memory using an embedded algorithm The desired data to be programmed is preloaded into the s
24. RMIIO MDIO MIIO MDIO PORT PCR MUX 4 GPIO RMIIO MDC MIIO MDC FSL start MII interface mii init 0 periph clk khz 1000 MHz Can we talk to the PHY do vTaskDelay netifLINK DELAY usData Oxffff mii read 0 configPHY ADDRESS PHY PHYIDR1 amp usData while usData Oxffff Start auto negotiate mii write 0 configPHY ADDRESS PHY BMCR PHY BMCR AN RESTART PHY BMCR AN ENABLE void mii init int ch int sys clk mhz ENET_MSCR ch 0 ifdef TSIEVB TSI EVB requires a longer hold time than default 10 ns ENET MSCR HOLDTIME 2 endif ENET_MSCR_MIT_SPEED 2 sys clk mhz 5 1 int mii write int ch int phy addr int reg addr int data int timeout Clear the MII interrupt bit Kinetis Quick Reference User Guide Rev 2 08 2012 118 Freescale Semiconductor Inc ENET EIR ch ENET EIR MII MASK Initiatate the MII Management write ENET MMFR ch 0 ENET MMFR ST 0x01 ENET MMFR OP 0x01 ENET MMFR PA phy addr ENET MMFR RA reg addr ENET MMFR TA 0x02 ENET MMFR DATA data Poll for the MII interrupt interrupt should be masked for timeout 0 timeout lt MII TIMEOUT timeout if ENET EIR ch amp ENET EIR MII MASK break if timeout MII TIMEOUT return 1 Clear the MII interrupt bit ENET EIR ch ENET EIR MII MASK return 0 BORK KKK KK k k kk k
25. Rev 2 08 2012 Freescale Semiconductor Inc 183 User case examples The programmable gain options are 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Vout Vin2 Vinl Gain Vinl Inverting application with programmable gain In the inverting application the user connects an input signal normally a mixed AC and DC signal to Vinl while a user defined DC reference voltage is connected to Vin2 The programmable gain options are 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Vout Vinl Vin2 Gain Vin2 NOTE Rf and Ri shown in Figure 20 3 are on chip internal resistive network and the values are encapsulated The user shall not use external resistors in an attempt to yield other gain voltage If the user desires other gain option the OPAMP should then be configured as General Purpose mode and use external gain resistive network for the desired gains configuration instead 20 5 1 On chip integration Programmable input selections for OPAMPO and for OPAMPI By default the inputs of OPAMPO and OPAMP are routed to the external pin signal Additionally users can also select input signals from other on chip modules Figure 20 4 shows all the input signals that are available for the OPAMPO and OPAMPI at the positive and negative input terminals For example the on chip 12 bit DAC can be selected as an input to the OPAMP internally This eliminates the need of external circuit routing Kinetis
26. The user can move the potentiometer to bring down the DC level to see the peak again Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 189 User case examples Kinetis Quick Reference User Guide Rev 2 08 2012 190 Freescale Semiconductor Inc Appendix A How to Load QRUG Examples A 1 Overview This chapter describes how to load and run the sample code described in other sections of the Kinetis Quick Reference User Guide It walks through the procedures used to make sure your Tower system is connected properly and explains how to load the example projects A 2 Software configuration First install the latest P amp E Micro Kinetis Tower Toolkit as described in the Quick Start Guide It can be found online or on the DVD that came with your Tower board This will install the necessary drivers for downloading software to the Kinetis tower board via OSJTAG the virtual serial port drivers and the P amp E terminal program You will also need to install IAR for ARM 6 10 or later It supports OSJTAG which is firmware located on your Kinetis tower board that enables you to flash and debug code with only a mini B USB cable A 3 Hardware configuration You will need to put together your tower kit for examples using Ethernet FlexCAN or USB The other examples can be ran with the Kinetis microcontroller module in stand alone mode To put together the tower system plug in the primary side of
27. detection grouping of controls like keypads sliders and rotaries It also implements advanced filtering and automatic baseline tracking providing further robustness to the measurements Also included is the standard GPIO based sensing method if 16 electrodes are not enough GPIO pins can be used to provide even more touch sensors For more info on the TSS library and downloads visit www freescale com touchsensing Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 167 TSI configuration 18 4 1 1 Code Example and Explanation After initialization in the TSI configuration the next step is to detect touches As can be seen in the figure the end of scan interrupt is used At each end of scan the interrupt subroutine is called by the TSI module and all post processing is done in the ISR There is no baseline tracking baseline is assumed to be constant and this way the main algorithm to implement is debouncing Debouncing is the process of validating that a button push or in this case a touch is valid Debouncing is something that needs to be done even in standard mechanical keyboards or buttons In mechanical buttons electrical disturbances caused by the two metal contacts approaching may cause more than one button press event to be logged or detected In capacitive touch sensors as the finger approaches the electrode capacitance varies the same as with mechanical buttons Variations in capacitance due to f
28. electrodes 5 Components and traces must not be placed directly underneath the electrodes area Good results can be obtained if the number of components behind the electrodes is minimized and running as few traces as possible It is always important to consider ground planes A ground plane below and around the electrodes adds noise suppression and a reference ground for the electrodes The problem is that a continuous ground plane below the electrodes also increases the base capacitance causing the touch delta to be reduced To work around this issue an x hatch ground plane is recommended as in Figure 18 8 The x hatch pattern helps with filtering out noise Because the area is smaller it will not increase the base capacitance as much as a continuous plane and thus does not affect sensitivity as much Figure 18 8 Recommended x hatch ground plane pattern X hatch pattern on BOTTOM side underneath electrodes Electrodes placed on Top layer Filled ground plane in Top and bottom for analog and digital circuitry including proximity sensing wiring Kinetis Quick Reference User Guide Rev 2 08 2012 170 Freescale Semiconductor Inc Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions 19 1 Overview This chapter will demonstrate how to use the PDB module to schedule and perform ADC conversions of the analog voltage available from the on board demonstration
29. not offer swap capability 9 1 1 2 Features By default there is no need for the user to configure the FTFL The configuration default allows for the flash memory controller FMC to accelerate flash transfers For FlexMemory enabled devices FlexNVM is configured as program data flash and the Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 83 E Using the FlexNVM FlexRAM is configured as a general purpose RAM Security is disabled and because the flash is in an erased state the program flash data flash and EEPROM protections are disabled so the regions can be programmed or erased 9 1 2 Configuration examples The user can configure FlexMemory enabled devices as either e FlexNVM as data flash and FlexRAM as traditional RAM e FlexNVM as EEPROM flash records to support the built in EEPROM feature and FlexRAM as EEPROM Or a combination of both 9 1 2 1 Basic data flash In this particular configuration the FlexNVM can be used as non volatile flash memory that can execute program code or store data The FlexRAM can be used as traditional RAM This is the default configuration prior to execution of the Program Partition Command 9 1 2 1 1 Code example and explanation This is the default configuration for devices with FlexMemory There is no need for partitioning the device in this implementation 9 1 2 2 EEPROM flash records In this particular configuration the FlexNVM is used excl
30. peripheral has its interrupts enabled the NVIC serves any pending request from that module by going to the module s ISR 3 1 2 1 1 Code example and explanation This example shows how to set up the NVIC for a specific module In this case the LPTMR is used The steps to configure the NVIC for this module are 1 Identify the vector number and the IRQ number of the module from the vector table in the device specific reference manual in the section Interrupt Channel Assignments For the LPTMR the vector is 101 Kinetis Quick Reference User Guide Rev 2 08 2012 38 Freescale Semiconductor Inc p e a Chapter 3 Nested Vector Interrupt Controller NVIC Table 3 2 LPTMR vector Address Vector IRQ Source Module Source Description 0x0000 018C 99 83 TSI Single interrupt Source 0x0000 0190 100 84 MCG 0x0000 0194 101 85 LPTMR 2 Determine which NVICSERx register contains the IRQ Each NVICSERx register contains 32 IRQs Therefore the NVICSERO can enable from IRQ 0 to IRQ 31 the NVICSERI from IRQ 32 to IRQ 63 and NVICSER2 from IRQ 64 to IRQ 95 For this example the NVICSER2 is used because the LPTMR IRQ is 85 The NVICCPRx takes on the same number in this case NVICCPR2 3 To know which bit to set perform a modulo operation to obtain the remainder by 32 of the IRQ number This number is used to enable the interrupt on NVICSER2 and to clea
31. potentiometer The application will sense the potentiometer control and report it over the serial port The code example shows how to Make a low level driver for the ADC Configure the ADC for averaging a single ended voltage conversion Use the bus clock to clock the ADC Use a simple exponential filter on the averaged results Have the ADC conversions scheduled at time intervals determined by the PDB module Calibration of the ADC is also illustrated 19 1 1 Introduction Timing of ADC conversions relative to system events is a key to applications such as motor control and metering requiring timing of ADC conversions for the best time to get a noise reduced reading When the Kinetis MCU is acting as a controller it will output control changes from time to time Scheduling ADC conversions around these changes which may make transient disturbances in the system is key Scheduling the ADC conversions at a time after the transient effects of the last control change has been made can enable smooth operation of control loops The PDB allows simple scheduling of one or both of the ADC peripherals conversions Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 171 JAE Overview In this example both ADC s will be scheduled but only the results from ADC1 connected to the onboard potentiometer on channel 20 will be used to report the control input For this demonstration the PDB timers
32. y Chapter 16 FlexCAN Module else pMBData uint8 amp pFlexCANReg MB iMB WORDO 3 for i 0 i lt bno i pBytes i wno lt lt 2 pMBData Read time stamp timeStamp pFlexCANReg gt MB iMB CS FLEXCAN MB CS TIMESTAMP MASK Unlock the MB code pFlexCANReg gt TIMER 16 2 5 Configuration of Rx FIFO ID filter table elements The Rx FIFO ID tables or ID filter table elements are used as message acceptance filters whose ID fields function as acceptance ID code It is necessary to configure the Rx FIFO ID filter table elements in freeze mode Kinetis supports up to 40 ID tables therefore CTRL2 RFEN 4 at maximum There are three types of ID table structure formats Forma 31 30 fa I 16 1 1 9 8 7 0 l l LL j l LI LII RXIDA A RIR IDE Standard 29 19 Extended 29 1 gt RXIDB 0 RXIDB 1 B RIR IDE RTR IDE Standard 29 19 Extended 29 16 Standard 13 3 Extended 13 0 4 1 1 gt RXIDC 0 RXIDC 1 RXIDC 2 RXIDC 3 Std Ext 31 24 Std Ext 7 0 Std Ext 23 16 Std Ext 15 8 n 16 2 5 1 Code example and explanation Example code for configuring ID table in Format A if bISExtID Format A with extended ID pIDTabElement id 1 bIsExtID 30 bISRTR 31 single ID acceptance codes else Format A with standard ID pIDTabElement
33. 08 2012 52 Freescale Semiconductor Inc Ey Chapter 5 Power Management Controller PMC MODECTL Mid 1 trip point selected VLVW VLVW2 1 84 Mid 2 trip point selected VLVW VLVW3 1 94 High trip point selected VLVW VLV4 2 04 NVICICPRO NVICISERO 1 lt lt 20 Clear any pending interrupts on LVD 1 lt lt 20 Enable interrupts from LVD module 5 1 2 3 Interrupt code example and explanation The LVD circuitry can be programmed to cause an interrupt You should create a service routine to clear the flags and react appropriately An example of such an interrupt service routine is given Notice the NVIC module references This clearing is redundant if the module clearing is done correctly void pmc_lvd_isr void printf rPMC_LVD ISR entered if PMC LVDSC2 amp PMC LVDSC2 LVWF MASK PMC LVDSC2 PMC LVDSC2 LVWACK MASK if PMC LVDSC1 amp PMC LVDSC1 LVDF MASK PMC LVDSC1 PMC LVDSC1 LVDACK MASK NVICICPRO 1 20 Clear any pending interrupts on LVD 5 1 2 4 Hardware implementation RESET PIN The reset pin is driven out if the internal circuitry detects a reset This is true for all resets including a reset that causes a recovery from the VLLSx modes Since these could be warm starts customers who do want not their external circuitry reset do not want to connect external circuitry to the MC reset pin VDD The Vdd supply pins can be driven between 1 71 V and 3 6 V DC
34. 20 continuous triggers sw trigger and use prescaler too PDB SC PDB SC CONT MASK Continuous rather than one shot mode PDB SC PDBEN MASK PDB enabled PDB SC PDBIE MASK PDB Interrupt Enable PDB SC PRESCALER 0x5 Slow down the period of the PDB for testing PDB SC_TRGSEL 0xf Trigger source is Software Trigger to be invoked in this file PDB SC MULT 2 Multiplication factor 20 for the prescale divider for the counter clock the software trigger PDB SC SWTRIG MASK is not triggered at this time PDB IDLY 0x0000 need to trigger interrupt every counter reset which happens when modulus reached PDB MOD Oxffff largest period possible with the selections above so slow you can See each conversion channel 0 pretrigger 0 and 1 enabled and delayed PDB CHOC1 PDB CHOC1 EN 0x01 Kinetis Quick Reference User Guide Rev 2 08 2012 174 Freescale Semiconductor Inc SSS M M eS Se ee Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions PDB CHODLYO PDB_CHODLY1 channel 1 PDB_CH1C1 PDB CHIDLYO PDB_CH1DLY1 PDB_CH0C1_TOS 0x01 PDB CHOC1 EN 0x02 PDB CHOC1 TOS 0x02 ADCO DLYA ADCO DLYB pretrigger 0 and 1 enabled and delayed PDB CH1C1 EN 0x01 PDB CH1C1 TOS 0x01 PDB CH1C1 EN 0x02 PDB CH1C1 TOS 0x02 ADC1 DLYA ADC1 DLYB PDB SC PDB SC CONT MASK Continuous rathe
35. After the table has been copied set the proper offset for the VTOR register Set the VTOR to be on RAM SCB VTOR VECTOR RAM It is important to follow the above mentioned steps in the order indicated This ensures there is always a valid vector table Kinetis Quick Reference User Guide Rev 2 08 2012 40 Freescale Semiconductor Inc Chapter 3 Nested Vector Interrupt Controller NVIC 3 1 2 3 Disabling priorities There are applications with important code where just certain interrupt priorities are allowed to interrupt this is because these interrupts are more critical to the application In other cases all the interrupts need to be disabled to ensure the code is atomic for example a context switch on Operating Systems The Cortex M4 provides the BASEPRI register that allows disabling lower interrupt priorities from any priority you choose or the option of disabling them all The BASEPRI is used as the NVICIPxx register Therefore 16 interrupt priorities can be masked and only the most significant nibble is used Please note that BASEPRI does not disable any of the fixed priority exceptions as Reset priority 3 a non maskable interrupt NMI priority 2 and Hard Fault priority 1 BASEPRI can be set only in privilege mode The reset value is 0x00 therefore all interrupts are enabled 3 1 2 3 1 Code example and explanation To set up BASEPRI a function from your development tools can be used For example in I
36. EZP_CLK PTA2 JTAG_TDO TRACE_SWO EZP_DO PTA1 JTAG_TDI EZP_DI RESET_b PTAG TRACE_CLKOUT PTA10 TRACE_DO PTA9 TRACE_D1 PTAS TRACE_D2 PTA7 TRACE_D3 PTA4 EZP_CS_b TARGET POWER 5V TARGET POWER 5V Figure 2 7 20 pin debug interface PTA3 JTAG_TMS SWD_DIO PTAO JTAG_TCLK EZP_CLK PTA2 JTAG_TDO TRACE_SWO EZP_DO PTA1 JTAG_TDI EZP_DI PTA4 EZP_CS_b RESET_b Figure 2 8 10 pin debug interface The debug signals are multiplexed with general purpose I O pins so some signals will require proper biasing to select the operating mode The JTAG_TMS signal on PTA3 requires a strong pullup resistor for mode selection The Cortex Debug specification recommends that the JTAG_TCLK and JTAG TDI pins on PTAO and PTA1 have pull resistors high or low to force a known state on these debug input pins Note that the RESET b signal in the debug interface is the MCU s reset pin and not the JTAG_TRST signal The connectors for this interface are keyed dual row 0 050 centered headers When implementing either of these headers on a target system pin 7 must be depopulated to use the 19 pin or 9 pin adapters from the debug tool The Samtec part numbers for these connectors are e FTSH 110 01 L DV K 20 pin keyed connector e FTSH 105 01 L DV K 10 pin keyed connector Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 35 Other module hardware considerations FTSH 110 01 L DV 20 pin connector no ke
37. FlexNVM and 4 KB of FlexRAM This example assumes the part is erased and that the flash memory clock gate control is enabled in the system integration module SIM The default state in the SIM is flash memory clock enabled In this example the EEPROM data size code being used is 0x32 which selects a size of subsystem A subsystem B 2 KB The FlexNVM partition code use is 0x05 representing the size of our data partition as 128 KB and the size of the EEPROM backup memory as 128 KB The system created has 128 KB of program data flash and two 2 KB EEPROM subsystems each backed up by 64 KB of EEPROM backup memory Example Code Write the FCCOB registers FTFL FCCOBO FTFL FCCOBO CCOBn 0x80 FTFL FCCOB1 FTFL FCCOB2 FTFL FCCOB3 Selects the PGMPART command 0x00 0x00 0x00 FTFL FCCOBA 0x32 Subsystem A and B are both 2 KB FTFL FCCOB5 0x05 Data flash size 128 KB EEPROM backup size 128 KB FTFL FSTAT FTFL FSTAT CCIF MASK Launch command sequence while FTFL FSTAT amp FTFL FSTAT CCIF MASK Wait for command completion 9 1 3 Endurance While different partitions of the FlexNVM are available the intention is that a single choice for the FlexNVM Partition Code and EEPROM Data Set Size will be used throughout the entire lifetime of a given application The FlexNVM partition choices affect the endurance and data retention characteristics of the device Kinetis Quick Reference User Guide Rev
38. Guide Rev 2 08 2012 Freescale Semiconductor Inc 27 Hardware considerations Figure 2 4 Potential crystal layout for BGA Kinetis Quick Reference User Guide Rev 2 08 2012 28 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations Figure 2 5 Potential crystal layout for LQFP 2 1 3 4 General filtering General purpose I O pins should have adequate isolation and filtering from transients 2 1 3 4 1 RESET b and NMI b Critical input pins like RESET b and NMI b should have 100 nF capacitors close to the MCU for transient protection Each pin has a weak internal pullup but an external 4 7 kO to 10 kO pullup is recommended As with power pin filtering it is recommended to minimize the ground loop for the capacitor and the VDD loop for the pullup resistor for these pins Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 29 al Hardware considerations The RESET_b pin also has a configurable digital filter to reject potential noise on this input after power up The configuration bits are located in the SIM_SOPT6 register While use of this filter may negate the need for the pullup and capacitor mentioned above it is still recommended to use external filtering in electrically noisy environments 2 1 3 4 2 General purpose I O General purpose inputs such as low speed inputs timer inputs and signals from off board should have low pass f
39. Guide Rev 2 08 2012 6 Freescale Semiconductor Inc Section number Title Page Chapter 7 Enhanced Direct Memory Access eDMA Controller Al eror rd RP UTR RR 67 DT E Scu ee mI HT TU 67 pne MEME co Ao a 67 Pl GRIS Pme 69 pA WEE SE o eee E 69 ALL TAREE ROS ed 70 ALZ 3 Mil ple TEADSIGE UE rn 71 Tl Tr nsierprocess major and minor transfer in ira TA EHE WEG Huit s t PETIT O ULM O E E E 33 TI Exampe rPI sated DMA POQUESTS oie iia T3 A RTL NE E IUE E T3 PLSS Module conn enra eonen A i S aa aE 74 Chapter 8 Using the Flash Standard Software Drivers EEO A A E E E E E ry 52 Downloading isl SOIUVATE A oue rtr rre trthe PRR aaa UK X AL ad p e FIER SPURS EE EAN EENE CER HAT Re UR HUE UA ay M CU e y 0 O E E A E A E E 78 R E Fae PAM oa E I E PE TEE A E E E E N T 78 AE IET ih al UD E COST UD N AA E rier E m tr eter 78 See Sol Cer LI t M S fe A NUR aule Fr IP 79 26 ROI teU err A RE R 82 Chapter 9 Using the FlexMemory 9 1 Using the PICKIN VME M 83 Y Veri c 83 KELI GAC QNM MN 83 CAN SUME tr 83 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 7 Section number Title Page LS as noua eammestedeaieden nieve eno 84 PA AA Ape TE 84 SLALI sEodsecxample snd SuplimatyD nca ctia exp cbe pileo ERES R eq espe ibi crea reden 84 ET PERON si ast dpa du
40. Hifdef NBUF LITTLE ENDIAN xENETRxDescriptors ux data uint8 t REV uint32 t pcBufPointer else xENETRxDescriptors ux data pcBufPointer Hendif pcBufPointer configENET RX BUFFER SIZE ifdef ENHANCED BD xENETRxDescriptors ux bdu 0x00000000 xENETRxDescriptors ux ebd status RX BD INT endif Set the wrap bit in the last descriptors to form a ring xENETTxDescriptors configNUM ENET TX BUFFERS 1 status TX BD W xENETRxDescriptors configNUM ENET RX BUFFERS 1 status RX BD W uxNextRxBuffer 0 uxNextTxBuffer 0 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 117 PHY management interface 13 3 PHY management interface The PHY management interface is the path to communicate to the PHY control status registers which describes the network Communication between the MAC NET and the PHY is made by 2 signals One clock generated from the ENET interface for the PHY Clock cannot be greater than 2 5 MHz and is controlled by register ENET_MSCR MII_SPEED divider which uses peripheral clock as reference One bidirectional signals which sends receives data to from the PHY 13 3 1 Code example and explanation The following example code starts the PHY management interface that starts the auto negotiation process from the PHY to the network Example code void enet_start_mii void PORTB PCRO PORTB PCR1 PORT PCR MUX 4 GPIO
41. Kinetis family It includes module initialization power supply clock source load adjustment frame frequency interrupts and the use of features as blinking alternate display segment fault detection and using the module on low power modes 17 1 1 Introduction The segment LCD module SLCD generates all the waveforms required for an LCD The SLCD module supports up to 64 pins The K40 family implements up to 48 LCD pins Eight of them can be configured as COM or backplane allowing control of up to 8 x 40 320 segments The power supply for the LCD can be selected from different options depending on the LCD panel voltage the application environment and the way the contrast control is required The SLCD has a charge pump that allows to control both 3 V and 5 V LCD panels Automatic blinking and the capacity to display two messages in alternate mode without refreshing the segments when less than five backplanes are used are available These features can be used to simplify the code and reduce power consumption in low power modes Segment fault detection is now possible by measuring the capacitance in each pin of the LCD The module measures the capacitance of each pin including cables connector and the LCD panel A reference capacitance must be determined when the LCD is operating correctly and stored in the memory While the product is operating the capacitance can be compared periodically to verify if there s an open connection sho
42. MEDII AA AAA AAA AAN AAA A 54 Salz Pri 25 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc Section number Title Page 32a LORO E e aii Nm 35 Sol MC codeexample and Exp Olson papi ide ipea le Ritus 56 2244 Enteros low leakage stop LLS OUS iiic ia tandi 56 EN MEME aC ri Diii C tora eacreccateacsantediwcat tasahoupepiaoedieceavneieaiuenghencaduetieniatuaseamvesaadines a 3122 ELIO power id 57 X3 Une thie Lip kabes vubeup UO e cesta dain secon idabc cuv e Cu a eai E eai i Dub esM R LUC Cap quo dins E eR Me Ee 58 SaN MEE UG etn PH E 58 ISLI Mode IAS a AAA 58 Jm MEE ril i e aiwasanian unnenahavn O aedeeimastauranianannaniaaniaaes 58 53 2 as abd aedi e octo apiid i T piu eai a di MeL luce eeu ipdd Qu de ab il incubo 58 3321 NIGQULS ri cripo 58 O EA 59 5 0 2 5 LEWU port and module mter T 59 mood Wn Serie ii E A ELEC EOS Ond 60 S4 Module operation m low power TAREE aie sura eet pis bd tics repris ral 61 2 5 Wade RASO QUIM st A da 62 so o AA pean nie Lapap CEPI Cabal aliqao tuc pH cM CA asap asin caduueaaabiamesanassaencis 64 Chapter 6 Memory Protection Unit MPU 6l Using The memory protection unit mole iia a a E R ae 65 Gli ONENEN Dm 65 De LEO A 5 N EVR REAN EA AA AR N AS A N A 65 Oke To ti AO 65 Old nn OO T pss EE E TA A A AAA E N esti Een 66 GAl JEn desc plebs BBDUB ains ies iai a R iE pi AA 66 Kinetis Quick Reference User
43. PCR12 PORT PCR MUX 4 RMIIO RXD1 MIIO RXD1 PORTA PCR13 PORT PCR MUX 4 RMIIO RXDO MIIO RXDO PORTA PCR15 PORT PCR MUX 4 RMIIO TXEN MIIO TXEN PORTA PCR16 PORT PCR MUX 4 RMIIO TXDO MIIO TXDO PORTA PCR17 PORT PCR MUX 4 RMIIO TXD1 MIIO TXD1 PORTA PCR11 PORT PCR MUX 4 MIIO RXCLK PORTA PCR25 PORT PCR MUX 4 MIIO TXCLK PORTA PCR9 PORT PCR MUX 4 MIIO RXD3 PORTA PCR10 PORT PCR MUX 4 MIIO RXD2 PORTA PCR28 PORT PCR MUX 4 MIIO TXER PORTA PCR24 PORT PCR MUX 4 MIIO TXD2 PORTA PCR26 PORT PCR MUX 4 MIIO TXD3 PORTA PCR27 PORT PCR MUX 4 MIIO CRS PORTA PCR29 PORT PCR MUX 4 MIIO COL ENET RCR ENET RCR MAX FL configENET RX BUFFER SIZE ENET RCR MII MODE MASK ENET RCR CRCFWD MASK 13 4 1 1 Hardware implementation The following figure shows the connection needed from the MAC NET pins to a generic Ethernet PHY in MII mode In MII mode Rx and Tx are synchronous to MIIO RXCLK and MIIO TXCLK respectively There is no additional requirement from the MAC NET to synch from the PHY to the MII RMII interface The PHY data sheet must be followed for all electrical requirements Kinetis Quick Reference User Guide Rev 2 08 2012 120 Freescale Semiconductor Inc MIIO_MDC RMIIO_MDC MIIO_MDIO RMIIO_MDIO l Serial management Chapter 13 ENET Module MIIO_RXD 3 2 52 RXD 3 2 Differential MIIO RXD 1 0 RMIIO RXD 1 0 RXD 1 0 Rx To MIIO_RXDV RMIIO_CRS_DV
44. Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 71 A eDMA transfer request is asserted to a channel of a higher priority The lower priority channel halts its transfer on completion of the current read write operation and allows the channel of higher priority to work In round robin mode the eDMA cycles through the channels from the highest to the lowest checking for a pending request When a channel with a pending request is reached it is allowed to perform its transfer After the transfer has been completed the eDMA continues to cycle through the channels looking for the next pending request 7 1 3 Transfer process major and minor transfer loop Each channel requires a 32 byte transfer control descriptor TCD for defining the desired data movement operation The channel descriptors are stored in the eDMA local memory in sequential order Each time a channel is activated and executes n bytes are transferred from the source to the destination This is referred to as a minor transfer loop A major transfer loop consists of a number of minor transfer loops and this number is specified within the TCD As iterations of the minor loop are completed the current iteration CITER TCD field is decremented When the current iteration field has been exhausted the channel has completed a major transfer loop Figure 7 6 shows the relationship between major and minor loops In this example a channel is configured so
45. Software Library document number AN3934 and Designing Touch Sensing Electrodes document number AN3863 at the Freescale webpage www freescale com touchsensing There are three modes of operation that must be considered when configuring the TSI The three modes are used in most applications Continuous active mode All enabled electrodes are scanned continuously e Scanning period is determined by SMOD register deal for scanning once the application is in run mode e Software triggered active mode Kinetis Quick Reference User Guide Rev 2 08 2012 164 Freescale Semiconductor Inc p Aay Chapter 18 Touch Sense Input TSI Module All enabled electrodes are scanned once No scanning period as scan is run only once deal for scanning initially For example when the initial baseline values for the electrodes are determined Continuous low power mode Only one electrode is continuously scanned e Single enabled electrode can be used to wake up the system from low power mode e Scanning period is independent from the active mode scanning period Enabled when the MCU goes into low power mode if the STPE bit is set Usually a much slower scanning period is used in low power mode this further reduces power consumption Configuration tips Enable the TSI clock gate before reading or writing TSI registers Initialize with the module disabled TSIEN 0 When a configuration change is needed make sure the module is
46. USB operation modes Device Mode The USB is configured to respond to external host requests In this mode the MCU has no control of the USB bus AII the transfers are started by the Host controller that is also providing the VBUS voltage The DCD was designed to run together with this USB mode First the DCD detects the host type and after the USB takes the control of the D and D signals Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 131 Voltage regulator operation modes Device lam w Figure 15 1 USB device mode Host Mode In this mode the module works as the USB master having the entire control of the USB bus The Serial interface engine takes care of the timing and the frames The software stack takes care of the transfer management of the bus The host also needs to provide the 5 v VBUS power line to supply the remote devices in case its needed meN m Host Figure 15 2 USB host mode 15 4 Voltage regulator operation modes The voltage regulator is composed of two different regulators the standby regulator and the run regulator You can select which regulator will be used by using the standby bit in the system integration module The input pin for the regulator is called VREGIN and the output pin is VOUT33 Run Mode Kinetis Quick Reference User Guide Rev 2 08 2012 132 Freescale Semiconductor Inc Chapter 15 Universal Serial Bus OTG Module Th
47. WORD1 TCML BASE TCML SIZE End Address MPU RGD1 WORD2 0x0061F7DF No magic s Bus master 3 SM all access List what the Bus masters are in addition to s Bus master 2 SM all access Bus master 2 UM all access Bus master 1 SM all access Bus master 1 UM all access Bus master 0 SM all access Bus master 0 UM all access MPU RGD1 WORD3 0x00000001 region is valid OCOORRNN Set RGD2 MPU RGD2 WORDO TCML BASE TCML SIZE 0x40 MPU RGD2 WORD1 OxFFFFFFFF End Address MPU RGD2 WORD2 0x0061F7DF MPU RGD2 WORD3 0x00000001 region is valid Enable MPU function MPU CESR 0x00000001 Kinetis Quick Reference User Guide Rev 2 08 2012 66 Freescale Semiconductor Inc Chapter 7 Enhanced Direct Memory Access eDMA Controller 7 1 eDMA 7 1 1 Overview This chapter is a compilation of code examples and quick reference materials that have been created to help you speed up the development of your applications with the eDMA module of the Kinetis family Consult the device specific reference manual for specific part information This chapter demonstrates how to configure and use the eDMA module to create data movement between different memory and peripheral spaces without the CPU s intervention 7 1 1 1 Introduction The DMA controller provides the ability to move data from one memory mapped location to another After it is configured and initiated the DMA co
48. and enhanced timer support for Ethernet controller The following figure represents how the MAC NET interfaces with internal SoC connections Each component has its own clock MII EXTAL can be any value e a ia AUI RMII EXTAL and PHY clk must be MIIO TXCLK 4 mii SOMHz MIIO_RXCLK i EE P 25MHz 50MHz EAM a Core al 4 XTAL ENET 1588 CLKIN MAC NET Controller PTE26 Timer Channels SIM_SOPT2 4 TIMESRC Figure 13 2 MAC NET interfaces The following sections describes some modes of operations and how the module needs to be configured 13 1 2 Features The MAC NET key value add components are as follows The MAC NET controller is compatible with the FEC controller present in previous ColdFire MCUs and MPUs and low end PPC like the MPC5553 4 The hardware acceleration block helps software implementation with Pv4 and IPv6 support P TCP UDP and ICMP checksum generation and checking Kinetis Quick Reference User Guide Rev 2 08 2012 112 Freescale Semiconductor Inc EEE y Chapter 13 ENET Module e Configurable discard of erroneous frames e Configurable Ethernet payload alignment to allow for 32 bit word aligned header and payload processing Industrial communication can require the use of time synchronization between distributed nodes The MAC NET provides support for the IEEE1588 standard to overcome one of the drawbacks of Ethernet 13 2 Configuration examples W
49. any other low power mode Once the PMPROT register has been written the write to the PMCTRL control register sets the mode entry and exit selection For our example entry into LLS mode would be enabled with this write MC PMCTRL MC BMCTRL LPLLSM 0x3 set LPLLSM 0b11 5 2 2 2 Entering low leakage stop LLS mode Once the previous two setup steps have been done the low power stop mode would be entered with a write to the SCR register in the core control logic to set the SLEEPDEEP bit SCB SCR SCB SCR SLEEPDEEP MASK When the WFI instruction is executed the mode controller will step through the low power entry state machine making sure all of the modules are ready to enter the low power mode If for instance the UART is finishing a serial transmission it would hold off the entry into the LLS until the transmission was completed In C the syntax to execute the core instruction WFI is asm WFI Kinetis Quick Reference User Guide Rev 2 08 2012 56 Freescale Semiconductor Inc AAA XA lt 2 X lt lt Chapter 5 Power Management Controller PMC MODECTL This statement can be placed anywhere in the code and once execute the MCU will enter the selected low power mode It takes approximately 1 microsecond to enter the low power mode 5 2 2 3 Entering wait mode If you want to use WAIT mode then the SLEEPDEEP bit needs to be cleared before executing the WFI instruction SCB SCR amp SCB SCR SLEEPDEEP
50. are created and any FlexRAM not configured as EEPROM is unusable The EEPROM data size code being used is 0x32 which selects a size of subsystem A subsystem B 2 KB The FlexNVM partition code used is 0x08 representing the size of our data partition as 0 KB and the size of the EEPROM backup memory as 256 KB This creates 2 EEPROM subsystems 2 KB in size with each subsystem being backed up by 128 KB of EEPROM backup memory Example Code Write the FCCOB registers FTFL FCCOBO FTFL FCCOBO CCOBn 0x80 Selects the PGMPART command FTFL FCCOB1 0x00 FTFL FCCOB2 0x00 FTFL FCCOB3 0x00 FTFL FCCOB4 0x32 Subsystem A and B are both 2 KB FTFL FCCOB5 0x08 Data flash size 0 KB EEPROM backup size 256 KB FTFL FSTAT FTFL FSTAT CCIF MASK Launch command sequence while FTFL FSTAT amp FTFL FSTAT CCIF MASK Wait for command completion Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 85 A Using the FlexNVM 9 1 2 3 Combination In this configuration the FlexNVM is partitioned to use part of the available memory as data flash and part as EEPROM backup space The FlexRAM partitioned for EEPROM can range from a minimum of 32 bytes to the maximum size of FlexRAM 0 bytes selects a configuration with no EEPROM The size of the EEPROM backup space must be at least 16 KB in size 9 1 2 3 1 Code example and explanation The following example uses a device with 256 KB of
51. choice is made between this signal and the USB_CLKIN pin The fractional divider value can be configured in the SIM_CLKDIV2 register inside the system integration module SIM MCGFLLCLK i MCGPLLCLK st H SIM_SOPT2 SIM _SCGC4 Figure 15 5 USB clock diagram Voltage Regulator The USB transceiver power supply comes directly from VOUT33 voltage regulator output Therefore the regulator must be enabled to supply 3 3 V to the transceiver 15 5 2 USB initialization process The USB module can work in either device or host mode During initialization the two modes are similar but there are minor differences between the two Device Mode Initialization In device mode the USB module activates the pullup resistor after initialization is complete to be detected by the remote host Kinetis Quick Reference User Guide Rev 2 08 2012 134 Freescale Semiconductor Inc Chapter 15 Universal Serial Bus OTG Module USB Init USB ResetIiSR System Reset all EP s A SUME integration Module Configure EPO System USB clock gating integration Clear all USB flags I nius Enable USB Reset USB module Interrupt sources software Set BDT base registers USBISR s Clear all USBISR flags and enable weak pull downs USB STACK Enable USB Reset interrupt Enable pull up resistor Waiting for Host connection AD EE emcees nitialization a sche Figure 15 6 Device mode initialization flo
52. communication port will be described For full details on the UART module including all of its features and modes of operation please refer to the device specific reference manual 12 2 Features The feature set available on UARTs can vary from UART to UART Basic UART functionality is available on all UARTs but the clock source for the module and the transmit and receive FIFO sizes can vary The table below lists the UART features that vary based on UART module instantiation Table 12 1 UART instantiations on Kinetis UART instance ISO 7816 supported O HFOs Module clock UARTO Yes 8 entry TxFIFO 8 entry Core Clock RxFIFO UART1 No 8 entry TxFIFO 8 entry Core Clock RxFIFO UART2 UARTn No No FIFOs double buffered Peripheral Clock operation Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 105 et Configuration example NOTE The table above describes the UART instantiations on the Kinetis family devices available as of the writing of this document As new Kinetis devices become available the UART instantiations could change Please refer to the Chip Configuration chapter of the device specific reference manual to verify the UART instantiation information for your device 12 3 Configuration example The following sections give a software example for using a UART as an RS 232 communication port to an 8 N 1 PC terminal The software is broken up into ini
53. functional blocks power domains when necessary Note that the Tower System boards have multiple decoupling filters to separate digital and analog domains Also note that decoupling may not be needed in many applications physical separation of domains may be sufficient Kinetis Quick Reference User Guide Rev 2 08 2012 22 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations Vpp J Vpp iso FILTERED DC INPUT UNFILTERED DC INPUT Vas Vas 180 Figure 2 1 Generic decoupling filter In general the decoupling network series elements are small inductors or ferrite beads that have a small impedance about 100 Q at 100 MHz The capacitors are generally 10nF to 1uF and do not have to be the same value on both sides of the filter select a lower value for the side that has the higher frequency content 2 1 3 PCB routing considerations This section covers critical power and filtering aspects of PCB layout 2 1 3 1 Power supply routing Routing of power and ground to digital systems is a topic that is discussed and debated in many textbooks and references The basic concept is to ensure that the MCU and other digital components have a low impedance path to the power supply The typical guidance that was given for one and two layer PCBs was to use wide traces and few layer transitions The recommendations for today s high speed MCUs follow those given for high speed microprocessor s
54. id lt lt 19 bISRTR 31 single ID acceptance codes Example code for configuring ID table in Format B Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 151 Configuration examples Format B two IDs pIDTabElement id OxO3fff 16 1 bISExtID 3 bIsExtID lt lt 30 bISRTR lt lt 31 RXIDB 0 i if i lt nIDTab id idList i amp CAN MSG IDE MASK CAN MSG TYPE MASK bIsExtID idList i amp CAN MSG IDE MASK CAN MSG IDE BIT NO bIsRTR idList i amp CAN MSG TYPE MASK gt gt CAN MSG TYPE BIT NO pIDTabElement id amp OxO3fff 1 bIsExtID 3 bIsExtID 14 bISRTR 15 RXIDB 1 lt Example code for configuring ID table in Format C j 0 pIDTabElement id amp OxOOff lt lt 24 j 3 RXIDC 0 i j do if i lt nIDTab id idList i amp CAN MSG IDE MASK CAN MSG TYPE MASK bIsExtID idList i amp CAN MSG IDE MASK gt gt CAN MSG IDE BIT NO bISRTR idList i CAN MSG TYPE MASK gt gt CAN MSG TYPE BIT NO pIDTabElement id OxOOff lt lt 24 j 3 RXIDC 1 RXIDC 3 j i Else break while j lt 3 Kinetis Quick Reference User Guide Rev 2 08 2012 152 Freescale Semiconductor Inc Chapter 17 Segment LCD Controller 17 1 Overview This document explains how to use the segment LCD controller SLCD for the
55. k k k k k k k k k k k k k k k k k k Sk k k k k k k k k k k k k kk k k kk kk RK RR RK ke ke ke x int mii_read int ch int phy_addr int reg_addr int data int timeout Clear the MII interrupt bit ENET EIR ch ENET EIR MII MASK Initiatate the MII Management read ENET MMFR ch 0 ENET MMFR ST 0x01 ENET MMFR OP 0x2 ENET MMFR PA phy addr ENET MMFR RA reg addr ENET MMFR TA 0x02 Poll for the MII interrupt interrupt should be masked for timeout 0 timeout lt MII TIMEOUT timeout if ENET EIR ch amp ENET EIR MII MASK break if timeout MII TIMEOUT return 1 Clear the MII interrupt bit ENET EIR ch ENET EIR MII MASK data ENET MMFR ch amp Ox0000FFFF return 0 Kinetis Quick Reference User Guide Rev 2 08 2012 Chapter 13 ENET Module Freescale Semiconductor Inc 119 MII mode 13 4 MII mode The media independent interface MII is a configuration mode that requires 18 signals to communicate to a generic PHY The MII operates at 25 MHz The synchronization signals are part of the MII external signals provided by the Ethernet PHY 13 4 1 Code example and explanation The following example code shows the registers needed to configure the MAC NET controller in MII mode PORTA PCR14 PORT PCR MUX 4 RMIIO CRS DV MIIO RXDV PORTA PCR5 PORT PCR MUX 4 RMIIO RXER MIIO RXER PORTA
56. may be partitioned as data flash D Flash and or E Flash for EEPROM backup and FlexRAM which may be used as traditional RAM or as high endurance enhanced EEPROM EEE storage The following examples will reference the FTFL Flash found on some Kinetis variants but can be equally applied to the other derivatives with minor differences Please refer to the specific SSDs for your FTFx derivative for more details 8 2 Downloading flash software drivers The FTFL standard software drivers can be downloaded from http www freescale com using the following steps 1 Visit http www freescale com webapp sps site homepage jsp code KINETIS 2 Select a Kinetis microcontroller family 3 Navigate the Software and Tools tab 4 Select Device Drivers 5 Select the file COOTFS FLASH DRIVER Alternatively the COOTFS flash software drivers can be located by typing CO9O0TFS FLASH DRIVER in the keyword search field of http www freescale com Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 77 Features 8 3 Features The FTFL SSDs allow the user to perform the following tasks on the flash Flash initialization Erase flash single block all blocks sector Read 1s single block all blocks section Program longword section Program check Calculate flash checksum Program information row Read information row Program Flash Data Flash Set Get interrupt enable Get security
57. module FB_AD 31 0 In a non multiplexed mode this is the data bus In a multiplexed mode the FB_AD 31 0 bus carries the address and the data The number of byte lanes carrying the data is determined by the port size FB_CS 5 0 The chip select signal indicates what device is selected A particular chip select asserts when the transfer address is within the device s address space The next two tables show how the number of chip selects available depend on the pin configuration FB_BE BWE 3 0 When driven low these outputs indicate the data latched or driven onto a specific lane of the data bus FB_OE The output enable signal is sent to the interfacing memory to enable a read transfer FB_OE is asserted only during a read access when a chip select matches the current address decode FB_R W The processor drives this signal to indicate the current bus operation 1 during read bus cycles and 0 during write bus cycles FB_ALE The assertion of this signal indicates that the device has started a bus transaction and the address and attributes are valid FB_TSIZ 1 0 These signals along with FB TBST indicate the data transfer size of the current bus operation FB_TBST Transfer burst indicates that a burst transfer is in progress and driven by the device FB TA This input signal indicates that the external data transfer is complete When the processor recognizes FB TA during a read cycle it latche
58. plane Thick core Layer 3 inner signals and power plane Layer 4 bottom ground plane and pads for bottom mounted components no signals 4 Layer PCB B Layer 1 top MCU location signals and poured power Layer 2 inner ground plane Thick core Layer 3 inner ground plane Layer 4 bottom signals and poured power 6 Layer PCB A Layer 1 top MCU power plane and pads for top mounted components no signals Layer 2 inner signals and ground plane Layer 3 inner power plane Layer 4 inner ground plane Layer 5 inner signals and power plane Layer 6 bottom ground plane and pads for bottom mounted components no signals 6 Layer PCB B Layer 1 top MCU signals and power plane Layer 2 inner ground plane Layer 3 inner signals and power plane Layer 4 inner ground plane Layer 5 inner power plane Layer 6 bottom signals and ground plane Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 31 ee sl Hardware considerations 6 Layer PCB C Layer 1 top MCU signals and power plane Layer 2 inner ground plane Layer 3 inner signals and power plane Layer 4 inner signals and ground plane Layer 5 inner power plane Layer 6 bottom signals and ground plane 8 Layer PCB A Layer 1 top MCU signals Layer 2 inner ground plane Layer 3 inner signals Layer 4 inner power plane Layer 5 inner ground plane L
59. see next section connected to the POT on every PDB cycle This very fast and simple exponential filter is included in the interrupt service routines of ADC for illustration of how to smooth readings with minimal MCU cycle count It is implemented in only two lines of C code with no looping This filter is optional and can be used with or without the averaging feature of the ADC itself In the example both are used for increased smoothness of result Hardware triggering of the ADC with the PDB Kinetis Quick Reference User Guide Rev 2 08 2012 172 Freescale Semiconductor Inc a a a a ee Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions The ADC module works with the PDB to trigger the ADC s conversions The ADC trigger to convert is based on configuration choices In this case the ADC will be configured to be triggered only by the PDB The PDB will be triggered by the application software using an instruction to start its timed sequence of conversions Once it does this it will trigger each conversion in sequence based on its configurable timers It will repeat each time its counter wraps starting another cycle of conversions of both ADCO and ADC1 Only the readings from ADCI will be filtered and displayed as POT 16 bit resolution The conversion results in this example are 16 bit unsigned Differential or single ended Single ended mode is illustrated in this example
60. state Security bypass via backdoor key e Suspend Resume erase flash sector operation e Set Get program flash protection For devices that feature FlexMemory the FTFL SSDs allow the user to perform the following additional tasks e Partition FlexNVM e Set Get data flash protection e Set Get EERAM protection e Set EEE enable Write EEPROM The function that performs the flash initialization r1asninic must be invoked first to provide the software driver with Information about the flash Data flash and EEPROM size for devices that feature FlexMemory 8 4 Configuration parameters 8 4 1 SSD configuration structure The FTFL software drivers use a structure rnash_ssp_cowr1G that includes chip specific static parameters for the FTFL The type definition of this structure is shown below and can be found in SSD_FTFL h Kinetis Quick Reference User Guide Rev 2 08 2012 78 Freescale Semiconductor Inc SSS ee Chapter 8 Using the Flash Standard Software Drivers Flash SSD Configuration Structure typedef struct ssd config UINT32 ftflRegBase FTFL control register base UINT32 PFlashBlockBase base address of PFlash block UINT32 PFlashBlockSize size of PFlash block UINT32 DFlashBlockBase base address of DFlash block UINT32 DFlashBlockSize size of DFlash block UINT32 EERAMBlockBase base address of EERAM block UINT32 EERAMBlockSize
61. struct uint16_t status control and status uinti6 t length transfer length uint8 t data buffer address uint32 t ebd status uinti6 t length proto type uinti6 t payload checksum uint32 t bdu uint32 t timestamp uint32 t reserverd wordl uint32 t reserverd word2 NBUF else typedef struct uint16_t status control and status uint16_t length transfer length uint8 t data buffer address NBUF endif ENHANCED BD Static void enet init int usData const unsigned portCHAR ucMACAddress 6 configMAC ADDRO configMAC ADDR1 configMAC ADDR2 configMAC ADDR3 configMAC ADDRA4 configMAC ADDR5 Enable the ENET clock SIM SCGC2 SIM SCGC2 ENET MASK FSL allow concurrent access to MPU controller Example ENET uDMA to SRAM otherwise bus error MPU CESR 0 prvInitialiseENETBuffers Set the Reset bit and clear the Enable bit ENET ECR ENET ECR RESET MASK Wait at least 8 clock cycles for usData 0 usData 10 usData asm NOP FSL start MII interface mii init 0 periph clk khz 1000 MHz enet interrupt routine Set irq priority 76 6 enable irq 76 ENET xmit interrupt enet interrupt routine Set irq priority 77 6 enable irq 77 ENET rx interrupt enet interrupt routine Set irq priority 78 6 enable irq 78 ENET error and misc interrupts Make sure the external interface signal
62. sure that the USBDCD bit is set to enable the clock source to the DCD module I O Signal The DCD module needs to know when the USB connector is plugged in This can be made using an I O signal measuring the status of the VBUS line of the USB connector When the VBUS line becomes high the software must call the start sequence routine of the DCD module see I O section for more details of the pin configuration USB Module The host detection sequence ends after the pullup resistor is enabled in the D signal Only the USB module can enable this pullup The USB module needs to be pre initialized to enable the pullup when needed and start the USB enumeration process if required only if detection results on a standard host or charging host type Voltage Regulator The USB transceiver power line comes directly from the VOUT33 voltage regulator output Therefore the regulator must be enabled to make sure that the pull up is present when needed 14 3 DCD hardware implementation The basic connection to use the DCD module is the differential lines routed to the USB connector with the proper coupling resistors and an I O signal sensing the VBUS pin Remember that the Kinetis family has 5 V tolerant pins meaning that there is no need to add a level shifter or resistor divider to sense the VBUS line USB Connector VBUS Sense Port USB DPS esa USB DI Full speed DCD Figure 14 1 DCD hardw
63. talk to the PHY do RTOS DELAY netifLINK DELAY usData Oxffff mii read 0 configPHY ADDRESS PHY PHYIDR1 amp usData while usData Oxffff Start auto negotiate configPHY ADDRESS PHY BMCR PHY BMCR AN RESTART PHY BMCR AN ENABLE mii write 0 Wait for auto negotiate to complete do RTOS DELAY netifLINK DELAY mii read 0 configPHY ADDRESS PHY BMSR amp usData while usData amp PHY BMSR AN COMPLETE When we get here we have a link find out what has been negotiated usData 0 mii read 0 configPHY ADDRESS PHY STATUS amp usData Clear the Individual and Group Address Hash registers ENET IALR ENET IAUR ENET GALR ENET GAUR OoOooo E Set the Physical Address for the selected ENET enet set address 0 ucMACAddress if configUSE MII MODE Various mode status setup ENET RCR ENET RCR MAX FL configENET RX BUFFER SIZE ENET RCR CRCFWD MASK else ENET RCR ENET RCR MAX FL configENET RX BUFFER SIZE ENET RCR CRCFWD MASK ENET RCR RMII MODE MASK Hendif FSL clear rx tx control registers ENET_TCR 0 Kinetis Quick Reference User Guide Rev 2 08 2012 Chapter 13 ENET Module ENET_RCR_MII_MODE_MASK ENET_RCR_MII_MODE_MASK Freescale Semiconductor Inc 115 Configuration examples Setup half or full duplex if usData
64. that a major loop consists of three iterations of a minor loop The minor loop is configured as a transfer of 4 bytes Source Data Transferred DMA Request Pytes n 4 Minor Loop channel activated CITER 3 DMA Request Time Major Loop CITER 2 DMA Request CITER 1 Figure 7 6 Major and minor transfer loops Kinetis Quick Reference User Guide Rev 2 08 2012 72 Freescale Semiconductor Inc Chapter 7 Enhanced Direct Memory Access eDMA Controller 7 1 4 Configuration steps To configure the eDMA the following initialization steps must be followed 1 Write the eDMA control register only necessary if the configuration of another than the default is required 2 Configure channel priority registers in the DCHPRIn if necessary 3 Enable error interrupts using either the DMAEEI or DMASEEI register if necessary 4 Write the transfer control descriptors for channels that will be used 5 Configure the appropriate peripheral module and configure the e DMA MUX to route the activation signal to the appropriate channel All transfer attributes for a channel are defined in the unique TCD for the channel Each 32 bit TCD is stored in the eDMA controller module Only the DONE ACTIVE and STATUS fields are initialized at reset All other TCD fields are undefined at reset and must be initialized by the software before the channel is activated Failure to do this results in unpredictable behavior Refer to
65. the device specific reference manual for the TCD detail description 7 1 5 Example PIT gated DMA requests In this example the eDMA is used to supply the analog to digital converter with a command word and move the result of AD to a location in the internal SRAM The AD command word stores all the information that the AD module requires for a conversion so by using the DMA to provide the command words the module can be instructed to perform conversions without any CPU intervention After the result is transferred by the eDMA to internal SRAM the application can make further analysis on the data 7 1 5 1 Requirements The input to the ADCO must be sampled every 1 ms To achieve this a 32 bit AD command word must be supplied to the ADCO_SCIA 0x4003B000 every 1 ms when the module is able to accept the command The command word is located in the internal SRAM This example only requires a single command word to be provided to the AD It is stored in a variable labeled command After the AD has completed the conversion the result is moved from the AD result register ADCO RA located at 0x4003B010 to address Ox1FFF9000 in internal SRAM Figure 7 7 illustrates the functionality of this example Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 73 eDMA AD command DMA request gated with 1ms PIT pulse AD result DMA request Internal RAM Figure 7 7 Example 2 overview 7 1 5 2 Modul
66. this point in this example notice that the RTC the segment LCD the TSI and the comparator are among a few modules that are fully functional in several of the lowest power modules In this example system the MCU would spend most of the time in one of the lowest power modes waking up every second to update the time of day variables and update the display plus other house keeping tasks Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 55 EE el Using the mode controller The MCU could also wakeup from a user input This could be hitting a button a touch of a capacitive sensor the rise or fall of an analog signal from a sensor feeding the comparator To enable these sources please refer to the LLWU section 3 for configuration details The example codes for MC are available from the Freescale Web site www freescale com 5 2 2 1 MC code example and explanation There are two registers in the mode controller the PMPROT register and the Power Management Protection register This is a write once register after a reset This means that once written all subsequent writes are ignored In our example system above our two basic modes of operation are run mode and LLS mode If we do not want the MCU to be in any other low power mode we would want to write the ALLS bit in the PMPROT register MC PMPROT MC PMPROT ALLS MASK This write allows the MCU to enter LLS only It is then no longer possible to enter
67. trip point selected VLVD VLVDL 01 High trip point selected VLVD VLVDH 10 Reserved 11 Reserved x Choose one of the following statements PMC LVDSC1 PMC LVDSC1 LVDRE MASK Enable LVD Reset PMC_LVDSC1 amp PMC LVDSC1 LVDRE MASK Disable LVD Reset Choose one of the following statements PMC_LVDSC1 PMC_LVDSC1_LVDV_MASK amp 0x01 High Trip point 2 48V PMC_LVDSC1 amp PMC LVDSC1 LVDV MASK amp 0x00 Low Trip point 1 54 V Choose one of the following statements PMC LVDSC2 PMC LVDSC2 LVWACK MASK PMC LVDSC2 LVWV 0 0b00 low trip point LVWV PMC LVDSC2 PMC LVDSC2 LVWACK MASK PMC LVDSC2 LVWV 1 0b01 midl trip point LVWV PMC LVDSC2 PMC LVDSC2 LVWACK MASK PMC LVDSC2 LVWV 2 0b01000010 mid2 trip point LVWV PMC LVDSC2 PMC LVDSC2 LVWACK MASK PMC LVDSC2 LVWV 3 0b01000011 high trip point LVWV ack to clear initial flags PMC LVDSC1 PMC LVDSC1 LVDACK MASK clear detect flag if present PMC LVDSC2 PMC LVDSC2 LVWACK MASK clear warning flag if present LVWV if LVDV high range selected Low trip point selected VLVW VLVW1 2 62 Mid 1 trip point selected VLVW VLVW2 2 72 Mid 2 trip point selected VLVW VLVW3 2 82 High trip point selected VLVW VLV4 2 92 LVWV if LVDV low range selected Low trip point selected VLVW VLVW1 1 74 Kinetis Quick Reference User Guide Rev 2
68. 1 1 General Routing and Placement Use the following general routing and placement guidelines when laying out a new design for the ENET Series termination guidelines must be placed as close as possible to the origin of the signal This must be followed by PHY and ENET outputs When working in RMII mode a 50 MHz external reference must be connected to the EXTAL pin Then the MII RMII interface is able to communicate with the PHY which uses the same clock If your PHY clock presents an output delay compared to the input clock this delay must be properly matched frequency and phase to the EXTAL pin or data corruption occurs Some PHYs output a 50 MHz clock which must be used for the MCU EXTAL pin Follow your PHY specifications and considerations for the RMII mode Kinetis Quick Reference User Guide Rev 2 08 2012 124 Freescale Semiconductor Inc Chapter 14 USB Device Charger Detection USBDCD Module 14 1 Overview This chapter intends to show the general configuration sequence and the service routines needed to be able to detect the host type and charger that is connected to the USB module 14 1 1 Introduction The USB battery charger specification defines limits detection control and reporting mechanisms that permit devices to draw current in excess of the USB 2 0 specification for charging or powering up from dedicated chargers hosts and hubs and for charging downstream ports These mechanisms are backward compati
69. 1_isr void if ADC1_SC1A amp ADC SC1 COCO MASK ADC SC1 COCO MASK check which of the two conversions just triggered PIN2 HIGH do this asap resultlA ADC1 RA this will clear the COCO bit that is also the interrupt flag This is the exponential filter portion for ADCIA Begin exponential filter code for Potentiometer setting for demonstration of filter effect exponentially filtered resultl1 result1A exponentially filtered result1 2 Spikes are attenuated 6 dB 12 dB 24 dB and so on until they die out End exponential filter code add f sample divide by f 1 f is 1 for this case These cycle flags are used to keep track of which results are available at the program level cycle flags ADC1A DONE mark this step done else if ADC1_SC1B amp ADC_SC1 COCO MASK ADC SC1 COCO MASK PIN2 LOW result1B ADC1 RB This is the exponential filter portion for ADCIB Begin exponential filter code for Potentiometer setting for demonstration of filter effect exponentially filtered resultl result1B exponentially filtered result1l 2 Spikes are attenuated 6 dB 12 dB 18 dB and so on until they die out End exponential filter code add f sample divide by f 1 f is 1 for this case Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 177 PCB design recommendations cycle flags ADC1B DONE return 19 2 2 AD
70. 3 2 1 Set AVLLSx in PMPROT LPLLSM 101 for VLLS3 110 for VLLS2 111 for VLLS1 Execute STOP 5 6 Source of wakeup pins and modules Table 5 3 Source of wakeup pins and modules LLWU LLWU PO LLWU MOIF LLWU P1 PTE2 DSPI1 SCK SDHCO DCLK LLWU P2 PTE4 DSPI1 PCSO SDHCO D3 LLWU P3 PTA4 FTMO_CH1 NMI LLWU_P4 PTA13 CANO_RX FTM1_CH1 FTM1_QD_PHB LLWU_P5 PTBO I2CO SCL FTM1 CHO FTM1 QD PHA LLWU P6 PTC1 SCI1 RTS FTMO CHO LLWU P7 PTC3 SCI1 RX FTMO CH2 LLWU P8 PTC4 DSPIO_PCSO FTMO_CH3 LLWU_P9 PTC5 DSPIO_SCK LLWU_P10 PTC6 PDBO_EXTRG LLWU_P11 PTC11 SSIO_RXD LLWU_P12 PTDO DSPIO PCSO SCI2 RTS LLWU P13 PTD2 SCI2 RX LLWU P14 PTD4 SCIO RTS FTMO CH4 EWM IN LLWU P15 PTD6 SCIO_RX FTMO_CH6 FTMO_FLTO LLWU_MOIF LPT1 LLWU_M1IF CMPO JLLWU_M2IFO MP LLWU_MSIF CMP2 LLWU_M4IF TSI LLWU_MB5IF RTC LLWU_M6IF Reserved LLWU_M7IF Error Detect wake up source unknown Kinetis Quick Reference User Guide Rev 2 08 2012 64 Freescale Semiconductor Inc Chapter 6 Memory Protection Unit MPU 6 1 Using the memory protection unit module 6 1 1 Overview This chapter demonstrates how to use the MPU module which concurrently monitors system BUS activities and its access privileges on internal RAM The following example shows how to program the region descriptors that define internal RAM memory spaces and their access rights 6 1 2 Introduction
71. 61 Esto IC LUSIT PME iaa iia 161 18 3 Lu 163 IS ME En ura ino m 164 124 1 Contieuration sc Chir M 166 RALF Code Example and x plane Onn osse tipa reet tende tbe FREE bera i RAI HERE RU M ep AS Fx o Mo abl ERE Rs 167 185 TALLE oplemerbalotm dais 169 143 1 PCB Routine md Pisces asta ii ii ad 169 Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions A o p 171 19 11 Ei M 171 Lam c 172 19 2 Worten ii 173 1921 PDB triggered single ended ADC COMVELSIONS is iccavsnzenieoduspivseradstecsnscssveuonsdneabassasteniconacqassnabans iuednegsevess cd 123 Maid uen on ADE ama POB ONES ueni i eon bp dade St naer ld icon 174 Kinetis Quick Reference User Guide Rev 2 08 2012 12 Freescale Semiconductor Inc Section number Title Page W212 Configure System Integration module for ADC defaults ici 174 19 2 13 Conhigure Peripheral Delay Block PDB Lo casara dies 174 IEA Determine ADO CO A A AS 175 MALOS MSIE DE ONE asp UR Codes pA eed iE E INED rates ptu DH SEU 176 I Rex CA ADE vem THES 176 OLL Frie ADC and POB nisi T e AE A 176 TZ O Sohvat urreni PUB is 176 19 19 Handle ADL and POE menna T
72. AR tools the function is called set BASEPRI 1 For disabling lower interrupt priorities set the lowest priority level that the application allows For example priority 5 0 are allowed BASEPRI must take the priority 5 Disable interrupts priorities from 0x06 Ox0F Set BASEPRI 0x50 2 For disabling all priorities to ensure atomic code the BASEPRI must take the maximum priority value available for Kinetis MCUs which is priority 15 Disable all interrupt priorities Set BASEPRI 0xFO Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 41 NVIC Kinetis Quick Reference User Guide Rev 2 08 2012 42 Freescale Semiconductor Inc Chapter 4 Clocking System 4 1 Clocking 4 1 1 Overview This chapter will demonstrate how to configure the Clocking System and the Multipurpose Clock Generator MCG module in various modes that a typical application may require The examples will show how to enable the on chip PLL for high speed operation and how to move backwards and forwards between using the PLL and a low power low speed mode for entering very low power run mode VLPR Also an example is provided of how to configure the frequency locked loop FLL as the main system clock source using the RTC oscillator as the reference clock 4 1 2 Features The clocking system is summarized in Figure 4 1 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconduc
73. B 2 KB 5000 Endurance_subsystem 62 5000 Endurance_subsystem 310 000 Example 2 A Kinetis device configured as in example 3 with a subsystem of 2 KB of EE backed up by 64 KB of E Flash provides 150 000 cycles with 16 bit or 32 bit writes Endurance subsystem E Flash 2 EEESPLIT EEESIZE EEESPLIT EEESIZE Record_Efficiency Endurance_Factor Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 87 Using the FlexNVM Endurance_subsystem 64 KB 2 5 4 KB 5 4 KB 5 10 000 Endurance_subsystem 60 KB 2 KB 5000 Endurance_subsystem 30 5000 Endurance_subsystem 150000 Kinetis Quick Reference User Guide Rev 2 08 2012 88 Freescale Semiconductor Inc Chapter 10 EzPort Module 10 1 Using the EzPort module 10 1 1 Overview This section demonstrates how to use the Ezport module for in system programming ISP of Kinetis on chip flash memory 10 1 1 1 Introduction The Ezport module provides a serial programming interface that allows reading erasing and programming Kinetis on chip flash memory in a compatible format with many stand alone flash memory chips Kinetis has two functional modes single chip mode default and Ezport mode for ISP programming The mode entered depends on both the EZPCS state during reset and the Ezport disable bit in FOPT register as shown in Table 1 Table 10 1 Mode selection during reset External conditions during reset Mode en
74. C module is a 32 768 kHz crystal Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 25 Hardware considerations 2 1 3 3 1 RTC oscillator The RTC oscillator connected to the EXTAL32 and XTAL32 pins is the simplest to route Both pins are located on outside ring pads on the BGA package so the crystal can be placed on the top layer of the PCB close to the MCU Since this oscillator does not require any other external components the routing is straight from the crystal to the MCU pins While the 32 768 kHz crystal is available in leaded cylindrical and surface mount packaging we recommend using the cylindrical package to simplify placement and routing The EXTAL32 and XTAL32 pins can be brought out directly from the MCU and the crystal can be placed as close as possible to the MCU which improves noise immunity Surface mount crystals may have pad spacing that is further apart than the leaded crystals making the routing and placement more complex 2 1 3 3 2 MCG oscillator While the RTC oscillator can also be used as a source for the MCG module it is limited to 32 kHz The high speed oscillator that can be used to source the MCG module is very versatile The component choices for this oscillator are detailed in the device specific reference manual The placement of this crystal or resonator is described here The EXTAL and XTAL pins are located on the outside pad ring of the BGA package and on corner
75. C and PDB interrupts in NVIC enable irq ADCO irq no ready for this interrupt enable irq ADC1 irq no ready for this interrupt enable irq PDB irq no ready for this interrupt In case previous demo did not end with interrupts enabled enable used ones EnableInterrupts Kinetis Quick Reference User Guide Rev 2 08 2012 176 Freescale Semiconductor Inc Sr re ee eS ee eee Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions 19 2 1 8 Software triggering of PDB Software trigger the PDB PDB SC PDB SC SWTRIG MASK kick off the PDB just once The system is now working The PDB is continuously triggering ADC conversions Now to display the results The line above was the SOFTWARE TRIGGER 19 2 1 9 Handle ADC and PDB interrupts Interrupt servicing is simple even the digital filter is only two lines of C code It is placed in both ADCIA and ADCIB portions of the ISR BORK KKK KR KR RK kk Sk ke KK KR kk Sk Sk KK KR RK ok Sk Sk Sk KR RK RRR RR RR KK RR ke ke ke k adcl_isr void use to signal ADC1 end of conversion In n a Out exponentially filtered potentiometer reading The ADC1 is used to sample the potentiometer on the A side and the B side ping pong That reading is filtered for an aggregate of ADC1 readings exponentially filtered result1 thus the filtered POT output is available for display SSA E E void adcl
76. C device hardware implementation The ADC input pins are generally configured with a small inexpensive RC filter The R value is typically 100 Ohms and the C value is chosen to assure adequate roll off of frequencies above the Nyquist frequency which is the sampling frequency divided by two The advantage of a high sampling rate made possible by the Kinetis ADC PDB combination is that smaller RC values may be used for the anti aliasing filter 19 2 3 PDB device hardware implementation The PDB itself can be triggered by hardware There are two ball locations that are available for serving as external triggers for the PDB No special considerations for these but it is advised to use only one not both of the two ball locations for the hardware trigger of the PDB 19 3 PCB design recommendations 19 3 1 Layout guidelines 19 3 1 1 General routing and placement Use the following general routing and placement guidelines when laying out a new design These guidelines will help to minimize signal quality problems The ADC validation efforts focused on providing very stable voltage reference planes and ground planes 1 Use high quality RC components for the anti aliasing filter Place this RC filter as close to the ADC input pins as possible where it can remove the most noise 2 Provide very stable analog ground and voltage planes both for analog power and voltage references if full accuracy of the ADC is required 3 Provide very stab
77. D has 3 7 segment characters 7 special symbols and uses 4 backplanes and 7 frontplanes To use this demo the TWR must be connected to a serial port with a terminal program configured to 115200 n 8 1 Commands are ASCII characters The following table shows the commands and syntax Table 17 3 List of commands print Print a message in the LCD message msgmode Select the message mode user cmd user counter time counter time temperature and percentage percentage vScroll Enable vertical scroll val O Normal N scroll down N Scroll up N 1 5 Not functional with a 7 seg Panel symbol Turn on and off x symbol lt val gt 1 FSL 2 3 4 5 AM 6 PM cmd on off segtest Send a predefined pattern to the LCD lt gt faultDetect Enable and disable LCD fault detection cmd enable disable setref status measureall trim Read and set the regulator voltage trim lt val gt 0 15 value blink Turn on and off the blink Enable cmd on off alt norm alternate mode blinkrate Read and set blink rate lt val gt 0 6 ladj LCD load adjustment lt val gt 0 3 Table continues on the next page Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 159 Demonstration code Table 17 3 List of commands continued Iclk Change LCD clock prescaler lt val gt 0 7 resulting frequency must be in 28 58 Hz range pinmux
78. DCLK Internal Reference Fast Clock 2MHz Figure 17 1 SLCD clock source options on the K40 family Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 155 Hardware considerations Table 17 2 LCD clock source options on the K40 family LCD Clock Source LCD and System Configuration Notes 32 kHz Internal Reference SOURCE 1 ALTDIV 0 1 Slow internal reference clock selected MCG C1 IRCLKEN 1 See the Multipurpose Clock Generator MCG C2 IRCS 0 MCG IREFSTEN MCG for more details 1 MCG_C3_SCTRIM 2 MHz Internal Reference SOURCE 1 ALTDIV 2 2 MHz 64 Fast internal reference clock selected MCG C1 IRCLKEN 1 See Multipurpose Clock Generator MCG C2 IRCS 1 MCG IREFSTEN MCG for more details 1 MCG C4 FCTRIM System Clock SOURCE 0 SOPT1 OSCS32KSEL 0 Crystal must be in the 32 kHz range The system oscillator drives a 32 kHz clock to the SLCD TSI and LPT RTC oscillator clock SOURCE 0 SOPT1 OSC32KSEL 1 RTC oscillator drives a 32 kHz clock to RTC CR OSCE 1 RTC CR CLKO the SLCD TSI and LPT See RTC 1 Oscillator Chapter and the RTC Clock Module 17 5 Hardware considerations 17 5 1 General routing and placement Minimize the trace length Take advantage of any LCD pin that can be configured as FP or BP to reduce trace lengths and routing of the LCD Place the capacitors for the charge pump VLL1 VLL2 and VLL3 as close as possible to the MCU
79. Direct Memory Access eDMA Controller M3 M4 M5 Crossbar switch Other Slave SRAM Figure 7 2 Crossbar switch configuration The crossbar switch forms the heart of this multi master architecture It links each master to the required slave device If both masters attempt joint access to the same slave an arbitration scheme commences eliminating the bus contention Both fixed priority and round robin arbitration schemes are available If both masters attempt to access different slaves an arbitration scheme works for the judgement 7 1 2 eDMA trigger Each channel of the Kinetis eDMA module can be triggered to start DMA transfer of multiple sources from peripherals or software The eDMA module integrates the DMA Mux to route a different trigger source to the 16 channels With the DMA Mux up to 63 events occurring within other peripheral modules can activate an eDMA transfer In many modules event flags can be asserted as either eDMA or Interrupt requests These sources can be selected through DMAMUX_CHCFGn SOURCE registers But different devices may have different peripheral source configurations Refer to the device specific reference manual for details Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 69 A eDMA 7 1 2 1 DMA multiplexer The DMA channel Mux helps to configure the eDMA source 32 peripheral slots and 10 always on slots can be routed to 16 channels The first four cha
80. FF PDB Static FF FF Static Static OFF LPT FF FF FF FF FF FF Watchdog FF FF FF FF Static OFF EWM Static FF Static Static Static OFF 16 bit ADC ADC internal Clk FF FF ADC internal Clk Static OFF CAN Wakeup FF FF Wakeup Static OFF CMP HS or LS FF FF HS or LS LS LS 6 bit DAC Static FF FF Static Static Static VREF FF FF FF FF Static OFF OPAMP FF FF FF FF Static OFF TRIAMP FF FF FF FF Static OFF 12 bit DAC Static FF FF Static Static Static USB FS LS Static Static Static Static Static OFF USB DCD Static FF FF Static Static OFF USB DCD Static FF FF Static Static OFF USB Regulator Optional Optional Optional Optional Optional Optional Ethernet Wakeup Static Static Static Static OFF RTC Ext OSC2 FF FF FF FF FF FF CMP HS or LS FF FF HS or LS LS LS 6 bit DAC Static FF FF Static Static Static VREF FF FF FF FF Static OFF 5 5 Mode transition requirements Table 5 2 Mode transition requirements 1 RUN WAIT Execute WAIT This means that sleep now or sleep on exit modes entered with SLEEPDEEP clear WAIT RUN Interrupt or Reset Table continues on the next page Kinetis Quick Reference User Guide Rev 2 08 2012 62 Freescale Semiconductor Inc SSS ee Chapter 5 Power Management Controller PMC MODECTL 2 Table 5 2 Mode transition requirements continued STOP Execute STOP This means that sleep now or sleep on exit modes entered with SLEEPDEEP set Interrupt or R
81. GPIO to control the timing between manual reset of Kinetis and sampling of EZPCS QSPI DIN Kinetis OSPI DOUT OSPI_CLK Figure 10 3 Connection between MCF5282 and Kinetis Example code for set_to_ezp_mode Configure as GPIO pins to monitor RSTOUT pins and assert RCON MCF5282 GPIO POSPAR 0x0 GPIO function MCF5282 GPIO DDROS 0x08 CS0 as output MCF5282 GPIO PORTQS 0x08 Drive CSO HIGH set up wrap register for a single 8 bit transfer MCF5282 QSPI OWR MCF5282 OQSPI QWR CSIV Enable QSPI Pins MCF5282 GPIO POSPAR 0x7F Configure as GPIO pins to monitor RSTOUT pins and assert RCON MCF5282 GPIO POSPAR 0x0 GPIO function MCF5282 GPIO DDROS 0x28 CS0 and CS2 as output MCF5282 GPIO PORTOS 0x28 Drive RCON HIGH amp RSTIN HIGH MCF5282 GPIO PORTOS 0x08 Drive RCON HIGH amp RSTIN LOW while data in amp 0x10 wait till RSTOUT LOW data in MCF5282 GPIO PORTQSP MCF5282 GPIO PORTOS 0x20 Drive RCON LOW amp RSTIN HIGH while data in amp 0x10 wait till RSTOUT HIGH data in MCF5282 GPIO PORTOSP Exiting reset and entering EZPORT mode MCF5282 GPIO PORTOS 0x28 Drive RCON HIGH again Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 93 Using the EzPort module 10 1 2 2 Write enable and disable Before issuing a write command SP SE BE WRFCCOB or WRFLEXRAM in the Ezport module first enable the WEN bit i
82. If no character is received then the code will remain in the while loop indefinitely In order to avoid code getting stuck when no traffic is being received it is a good idea to include a function to test if a character is present or not The uart getchar present function can be called prior to calling the uart getchar function in cases where UART receive traffic is not guaranteed or required before moving on with program execution int uart getchar present UART MemMapPtr channel return UART S1 REG channel amp UART S1 RDRF MASK 12 3 8 UART transmit example The function below shows an implementation for a simple polled UART transmit function The parameters passed in to this function are the UART channel that will be used to transmit uartch and the character to be sent ch void uart putchar UART MemMapPtr channel char ch Wait until space is available in the FIFO while UART S1 REG channel amp UART S1 TDRE MASK Send the character UART D REG channel uint8 ch 12 3 4 UART configuration for interrupts or DMA requests The examples included here poll UART status flags to determine when receive data is available or when transmit data can be written into the FIFO This approach is the most CPU intensive but it is often the most practical approach when handling small messages As message sizes increase it might be useful to use interrupts or the DMA to decrease the Kinetis Quick Reference User Gu
83. MAC CITER 0x1 Current Iter Count gt 1 NBYTES transfer EDMAC DOFF 0x0 Destination addr offset 0x0 no increment EDMAC TCD1 W6 EDMAC DLAST 0x0 Do not adjust DADDR upon channel completion EDMAC TCDi W7 0 EDMAC BITER E LINK Do not set ELINK bit no channel linking EDMAC BITER 0x1 Beginning Iteration Count 1 CITER EDMAC BWC 0x0 Bandwidth control 0 gt No eDMA stalls EDMAC MAJOR LINKCH 0x0 Ignored no channel linking Using these configurations produces the required eDMA functionality for this example Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 75 eDMA Kinetis Quick Reference User Guide Rev 2 08 2012 76 Freescale Semiconductor Inc Chapter 8 Using the Flash Standard Software Drivers 8 1 Overview This chapter provides an introduction to the standard software drivers SSDs for 90 nm thin film storage flash FTFx derivatives which include the Kinetis family These software drivers are a set of application programming interfaces APIs intended to provide program and erase capability security related commands and interrupt configurations in a set of functions for use by embedded system developers and third party flash programming tool developers The FTFx SSDs provide support for program flash P Flash and for Kinetis variants that feature FlexMemory the FTFx SSDs provide support for FlexNVM which
84. MASK 5 2 2 4 Exiting low power modes Each of the power modes has a specific list of exit methods In general an enabled interrupt from a pin an enabled module trigger or a reset will exit the low power modes and return to RUN or VLPR mode These exit methods are discussed in Section 3 on the LLWU Recovery from VLLSx is through the wakeup reset event The MCU will wake from VLLSx by means of reset an enabled pin or an enabled module See table 3 12 LLWU inputs in the LLWU configuration section for a list of the sources The wakeup flow from VLLSI 2 and 3 is through reset The wakeup bit in the SRS registers is set indicating that the MCU is recovering from a low power mode Code execution begins but the I O are held in the pre low power mode entry state and the oscillator is disabled even if EREFSTEN had been set before entering VLLSx The user is required to clear this hold by writing to the ACKISO bit in the LLWU CS register Prior to releasing the hold the user must re initialize the I O to the pre low power mode entry state so that unwanted transitions on the I O do not occur when the hold is released The oscillator cannot be re enabled before the ACKISO bit is cleared and must be reconfigured after the acknowledge write has been done Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 57 Using the low leakage wakeup unit 5 3 Using the low leakage wakeup unit 5 3 1 Overview This
85. Manager window a Freescale CDC device will be found after the enumeration process is completed Kinetis Quick Reference User Guide Rev 2 08 2012 140 Freescale Semiconductor Inc ESY Chapter 15 Universal Serial Bus OTG Module iBixi Ele Action Yiew Help gt amp 5 X x ES Network adapters H B PCMCIA adapters J Ports COM amp LPT a Communications Port COMI Freescale CDC Device COM4 R gar El Ve COMS Y RIM Virtual Serial Port v2 COM6 SB Processors XQ Smart card readers H O Sound video and game controllers System devices Universal Serial Bus controllers Figure 15 13 Windows device manager Then open HyperTerminal pointing to the COMx device in this case COMA with 8 bit size 1 stop bit no flow control 9600 baudrate and begin typing in the terminal The software running in the MCU returns the same characters ioj xj Ele Edt yow Cal Transfer Help Ol 9 3 ols e Freescale Kinetis family _ Figure 15 14 HyperTerminal window 15 7 2 Host code Host operation is more complex than the device in terms of software stack and task handling However it is less time dependent because the application running in the MCU has control of the entire bus This example code basically enumerates an HID USB mouse and sends that information to a terminal using the serial port It also reports all movements and button changes directly in the terminal Kinetis Quick Reference
86. OL IACK MASK ackowledge if USBDCD STATUS amp Ox000C0000 0x00080000 FLAG SET USBOTG CONTROL DPPULLUPNONOTG SHIFT USBOTG CONTROL enable pullup if USBDCD STATUS amp 0x00400000 USBDCD STATUS amp 0x00300000 FLAG SET DCD Flag gu8InterruptFlags charger detection completed The example code included in this user guide is for demonstration purposes only For general purpose applications please download Freescale USB stack with PHDC support or Freescale MQX Software Solutions from http www freescale com usb Kinetis Quick Reference User Guide Rev 2 08 2012 130 Freescale Semiconductor Inc Chapter 15 Universal Serial Bus OTG Module 15 1 Introduction The Universal Serial Bus USB is a serial bus standard for communicating between a host controller and different types of devices USB has become the standard connection method for PCs PDAs and video games and more recently has been used on power cords This is because USB can connect printers keyboards mice game devices communication devices storage devices and custom devices USB 2 0 full speed allows 12 Mbit s communication between the host controller and the device 15 2 Features USB Full Speed 2 0 compliant 12 Mbit s Dual role operation 16 double buffered bidirectional endpoints On chip USB full speed PHY Integration with device charger detection DCD module 120 mA on chip regulator for MCU and external components 15 3
87. ORTA PCR5 PORTA PCR12 PORTA PCR13 PORTA PCR15 PORTA PCR16 PORTA PCR17 PORT PCR MUX 4 RMIIO CRS DV MIIO RXDV PORT PCR MUX 4 RMIIO RXER MIIO RXER PORT PCR MUX 4 RMIIO RXD1 MIIO RXD1 PORT PCR MUX 4 RMIIO RXDO MIIO RXDO PORT PCR MUX 4 RMIIO TXEN MIIO TXEN PORT PCR MUX 4 RMIIO TXDO MIIO TXDO 4 PORT PCR MUX RMIIO TXD1 MIIO TXD1 ENET RCR ENET RCR MAX FL configENET RX BUFFER SIZE ENET RCR MII MODE MASK ENET RCR CRCFWD MASK ENET RCR RMII MODE MASK 13 5 1 1 Hardware implementation The following two figures show the connection needed from the MAC NET pins to any generic Ethernet PHYs in RMII mode The connection from the RMIIO CRS DV is dependent on the PHY implementation In the first figure the RMIIO CRS DV signal is connected to the RXDV CRSDV pin MIIO MDC RMIIO MDC MDC Serial MIIO MDIO RMIIO MDIO MDIO management 5 RXD 3 2 Differential MIIO RXD 1 0 RMIIO RXD 1 0 RXD 1 0 Rx To MIIO RXDV RMIIO CRS DV RXDV CRSDV Magnetics RXCLK Differential TX RJ45 MIIO_RXER RMIIO_RXER RXERR Miiri Tx TX TXCLK interface MIIO_TXEN RMIIO_TXEN TXEN ACT o TXD 3 2 LINK MIIO TXD 1 0 RMIIO TXD 1 0 TXD 1 0 SPEED CRS COL INT RST XO XI VDD GND Kinetis MII RMII interface 9 signals N C N C RSTIN 50MHz pin osc Figure 13 4 RMII mode connection example 1 The RMIIO CRS DV is connected to the CRS CRSDV Hardware designs need to be taken into consideration depending on t
88. Quick Reference User Guide Rev 2 08 2012 184 Freescale Semiconductor Inc I Chapter 20 Using OPAMP for Kinetis Microcontrollers External pin signal On chip internal signals External pin signal On chip internal signals Figure 20 4 OPAMPO and OPAMP 1 positive input signal and negative input signal selection Output connections In addition to outputting to an external pin the output of the OPAMPs are also available to other modules on the MCU internally without the need of external routing Take Figure 20 5 for example the outputs of OPAMPs are also routed internally to a ADCO channel and an input of an analog comparator CMP OPAMP number OPAMP output signal connection Output to internal module 0 OPO OUT output signal Output to external pin NENNEN SNR Output to internal module a ae OP1_OUT output signal Output to external pin Figure 20 5 OPAMPO and OPAMP1 output connections Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 185 User case examples 20 5 2 Device hardware implementation The following actions are recommended for device hardware implementation Use external low high or band pass filter circuit to help reduce uninterested noise Use 1 tolerant external resistors and capacitors instead of the standard 5 ones When OPAMP is not used disable it to conserve current draw from Vdda Layout guidelines Use the following general
89. Ramp system clock to selected frequency etn UNIT A A e N E AE 1 1 4 2 6 Enable UART for terminal communication eere 1 1 4 2 7 Jump to start of main function for application eee Chapter 2 General System Setup Hardware Considerations E oia eT REPO RTI O A A A MIRI EXON DLRA S dC D EORR Kinetis Quick Reference User Guide Rev 2 08 2012 Page Freescale Semiconductor Inc Section number Title Page PEE PCB TOR PONSA a 23 A Pesers ppbe OUND AA 5D mP O dpa Died ut een s Batu deeds lcd tuv eden av dba eMe diu reel aede 23 2132 Powersupply cheep ie arid Deme oscar eit HU PME M reip De exec Lui Fi eec ifia 24 CN AE CS i 25 ACE O 26 EAE SS MGOMO m cT 26 pU ES n rapid re UI 29 DIAT RESET AL Bine iust d rbd e Heidelb dels 29 2d Aencral pupas IA rS 30 pu XE ioo np dS 30 ALA PEB Ayer roc 30 2 1 3 Other module hardware CONCA et 33 EXE Ll VBA 33 LSS A bia eben Adria obese tU bora Ud 34 A o A AATA AE T EE E N 34 Chapter 3 Nested Vector Interrupt Controller NVIC A PP 37 Solel A s 37 Sl noo Me 37 CHEM oo A EER AAEREN A S 37 Silk Confonration example ii ERE E A AAA AE 38 LSI angunng A a eiaa 38 SLALI o e a necne na cepi ese PE aE EAEI pls FaR TEE AEAEE 38 SLZ E Clo n oir i e cd O o t cp 39 312 451 Co
90. S iar A A 177 PO cee POS deus hardware implemen DON ac aoiseteiates Fa E oidulod it np a op RU UR ts 178 es FDE device Feed pe care mp enmendada 178 193 PCB d sipn recommendation NR 178 LEAL Layout cmdline Sa ia E N E ER RS 178 19 3 1 General routne and BIagerlefitus qa 178 19 3 2 ES DPE MI COROS ri id AAA ienaa aia E X RR ED aeai 179 Chapter 20 Using OPAMP for Kinetis Microcontrollers FE o AAA SAR iba 181 20a A cps cannes ac able a E A G 181 20 3 PAM AAA AAA AAA AAA AAA 181 204 DMomenciaie aii A AA A 182 AUS WIRE e A A AA AAA AR 182 EUREN Der i 184 21 5 2 Device hardware implementato rieki vid eoe titer bec Iia ene tir dide te EL bantur dise pestis MES ene salad 185 ID OPAMP dino sol DU pd UTE EH AN EE E ANE DIES QUA Ge EXON S 186 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 13 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc Chapter 1 General System Setup Software Considerations 1 1 Software considerations 1 1 1 Overview This chapter provides a quick look at some of the general characteristics of the Kinetis family of MCUs This is a brief introduction of the operation of the devices and typical software initialization For more information see the device specific reference manual and data sheet 1 1 2 Code execution The Kinetis family features embedd
91. Select MUX O analog and 7 Port PAD lt val gt 0 7 enable PowerMode Select power mode operation lt val gt 0 Run 1 wait 2 stop ClockSource set LCD clock source val O System Osc 1 Def RTC 2 ALT Int 32 kHz 3 Int 2 MHz powersel LCD power supply selection mode VLL1 VIREG HREFO VLL1 VIREG HREF1 VLL3 VDD VLL3 EXT CP VLL3 EXT BR VLL2 VDD help Display the available commands and lt gt their syntax Fault detection example To enable the Fault detection type in the following commands 1 faultDetect setref 2 faultDetect enable 3 To generate a fault in any LCD pin use a wire jumper from ground to the LCD pin 4 When a fault is detected it reports into the terminal Alternate example To enable the alternate function type in the following commands 1 printalt 1234 2 print 1789 3 blink on 4 blink alt Kinetis Quick Reference User Guide Rev 2 08 2012 160 Freescale Semiconductor Inc Chapter 18 Touch Sense Input TSI Module 18 1 Overview The Touch Sensing Input TSI module is designed to interface the MCU with capacitive touch sensing electrodes to easily implement advanced user input controls The TSI module includes hardware that is able to drive touch sensing electrodes or capacitors created by flat conductive areas providing robustness above traditional GPIO based RC measurements and logic that automatically scans up to 16 electrodes measures and outputs the results and g
92. User Guide Rev 2 08 2012 Freescale Semiconductor Inc 141 Example Code To run this demo 1 Connect one serial cable between the board and the PC 2 Open a terminal console 8 bit 1 stop bit no flow control 115200 baudrate 3 Make sure that the jumper configuration is appropriate to supply 5 V through the USB port 4 Run the application The application will send a message that it is waiting for an HID USB mouse to be attached I coMi1 115200baud Tera Term VT B xj File Edit Setup Control Window Help rev Full size P flash 128 kBytes of RAM Main OK Timer Init OK USB HOST Init OK USB HID Mouse Waiting for USB Mouse to be attached Figure 15 15 Host state before connecting USB mouse After this message appears connect a USB mouse to the connector Automatically a message will appear stating that a single device was connected and the type of device COM1 115200baud Tera Term YT Bf x File Edit Setup Control Window Help Main OK Timer Init OK USB HOST Init OK USB HID Mouse Waiting for USB Mouse to be attached fittach Event Class 3 SubClass 1 Protocol Mouse device attached Interfaced Event Mouse interfaced setting protocol Mouse device ready try to move the mouse Figure 15 16 USB mouse successfully enumerated Kinetis Quick Reference User Guide Rev 2 08 2012 142 Freescale Semiconductor Inc SSS ee ee ee ee Chapter 15 Universal Serial B
93. VDD supply or from a dedicated back up battery cell A simple battery isolator consists of a dual Schottky array with common cathodes The TWR board example below Figure 2 6 uses the BAT54C device to provide battery back up when the main system power is off A 100 nF bypass capacitor placed as near as possible to the MCU is recommended to minimize the effects of supply switching events Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 33 Other module hardware considerations VDD VBAT BAT54C Figure 2 6 VBAT connection example 2 1 5 2 Voltage reference module If the output from the Voltage Reference Module is used in tight regulation buffer mode a 100nF capacitor must be connected between the VREF_OUT pin and ground 2 1 5 3 Debug interface The Kinetis MCUs use the Cortex Debug interfaces for debugging and programming The 19 pin Cortex Debug ETM interface provides connections for JTAG and Serial Wire debugging as well as target power The 9 pin Cortex Debug interface provides connections for JTAG and Serial Wire debugging Figure 2 7 shows the 20 pin header implementation 19 pins populated as used on the TWR system boards Figure 2 8 shows the 10 pin header implementation 9 pins populated Kinetis Quick Reference User Guide Rev 2 08 2012 34 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations PTA3 JTAG_TMS SWD_DIO PTAO JTAG_TCLK SWD_CLK
94. Vp The OPAMP is disabled out of MCU reset After it is enabled it defaults to Buffer mode where the Vn is connected to the Vout internally within the MCU Kinetis Quick Reference User Guide Rev 2 08 2012 182 Freescale Semiconductor Inc Chapter 20 Using OPAMP for Kinetis Microcontrollers General Purpose mode OPAMPXx CO register field MODE 1 0 0b10 V dda Vn m out Vp Figure 20 2 OPAMP in General Purpose mode In this mode the OPAMP is used as a general purpose operational amplifier By default Vn Vp and Vout are routed directly to the MCU external pins Vn and Vp can also be selected to connect to other input signals outlined in the input signals selection table given in the chip configuration chapter of the reference manual OPAMP Programmable Gain mode OPAMPXx CO register field MODE 1 0 0bx1 Figure 20 3 OPAMP in Programmable Gain mode Because the integrated OPAMP is a single supply OPAMP one of the input terminals is used as a reference voltage to bias the input signal that feeds to the other terminal Normally this programmable gain feature is used by the user as either a non inverting or inverting application Non inverting application with programmable gains In the non inverting application the user connects an input signal normally a mixed AC and DC signal to Vin2 while a user defined DC reference voltage is connected to Vin1 Kinetis Quick Reference User Guide
95. WU_PE1 WUPEO 0x02 defining PORT El as a wakeup source for LLWU 5 3 2 3 LLWU port and module interrupts In the low power modes the ARM core is off the NVIC is off some of the time and the WIC is kept alive allowing an interrupt from the pin or module to propagate to the mode controller to indicate a wakeup request To enable the LLWU interrupt we would replace the default vector in the interrupt vector table with the appropriate LLWU interrupt handler with the following sequence Enable LLWU Interrupt in NVIC VECTOR_RAM 37 uint32 11wu handle Replace ISR NVICICPRO 1 21 Clear any pending interrupts on LLWU NVICISERO 1 21 Enable interrupts from LLWU module Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 59 Using the low leakage wakeup unit For our example we allow the processing of the pin PTE we add this initialization code VECTOR RAM 107 uint32 porte isr Replace ISR NVICICPR2 1 27 Clear pending interrputs on Port E NVICISER2 1 27 Enable interrupts from Port E Then there is a need for an interrupt service routine for the LLWU and one for the port enabled as a wakeup source 5 3 2 4 Wakeup sequence The wakeup sequence is not obvious for some of the modes For most of the wait and stop modes code execution follows a predictable flow For LLS mode which requires the LLWU the LLWU vector is fetched and taken right after the wakeup event
96. XCAN MB CS LENGTH iNoBytes 16 2 4 Read message Before reading the message content it is necessary to lock the Rx MB After reading the message content unlock the Rx MB Polling or interrupt method can be used to check an Rx MB to see whether it has received a message 16 2 4 1 Code example and explanation Here is a code example for checking the IFLAGI MB and reading the message from the Rx MB if pFlexCANReg gt IFLAG1 amp 1 iMB Read the Message content information clear flag pFlexCANReg gt IFLAG1 1 iMB This code is used to read the message content Lock the MB code FLEXCAN get code pFlexCANReg gt MB iMB CS length FLEXCAN get_length pFlexCANReg gt MB iMB CS format pFlexCANReg gt MB iMB CS amp FLEXCAN MB CS IDE 1 0 id pFlexCANReg gt MB iMB ID amp FLEXCAN MB ID EXT MASK if format standard ID id gt gt FLEXCAN MB ID STD BIT NO else xid CAN MSG IDE MASK flag extended ID format pFlexCANReg gt MB iMB CS amp FLEXCAN MB CS RTR 1 0 if format id CAN MSG TYPE MASK flag Remote Frame type Read message bytes wno length 1 gt gt 2 bno length 1 if wno gt 0 uint32 pBytes pFlexCANReg gt MB iMB WORDO swap 4bytes pBytes bno 4 pMBData uint8 amp pFlexCANReg gt MB iMB WORD1 3 Kinetis Quick Reference User Guide Rev 2 08 2012 150 Freescale Semiconductor Inc
97. a reduced frequency Core and Bus frequency limited to 2 MHz 5 Very Low Power Wait VLPW ARM core enters Sleep Mode NVIC remains sensitive to interrupts FCLK ON On chip voltage regulator is in a mode that supplies only enough power to run the MCU at a reduced frequency 6 Very Low Power Stop VLPS ARM core enters DeepSleep Mode NVIC is disabled FCLK OFF WIC is used to wake up from interrupt peripheral clocks are stopped On chip voltage regulator is in a mode that supplies only enough power to run the MCU at a reduced frequency all SRAM is operating content retained and I O states held 7 Low leakage stop LLS ARM core enters DeepSleep Mode NVIC is disabled LLWU is used to wake up peripheral clocks are stopped all SRAM is operating content retained and I O states held most of peripheral are in state retention mode cannot operate 8 Very low leakage stop3 VLLS3 ARM core enters SleepDeep Mode NVIC is disabled LLWU is used to wake up peripheral clocks are stopped all SRAM is operating content retained and I O states held most modules are disabled Kinetis Quick Reference User Guide Rev 2 08 2012 54 Freescale Semiconductor Inc ET Chapter 5 Power Management Controller PMC MODECTL 9 Very low leakage stop 2 VLLS2 ARM core enters SleepDeep Mode NVIC is disabled LLWU is used to wake up peripheral clocks are stopped Only portion of SRAM is operating content retained and I O state
98. airs are routed to other layers under the package This allows easier attachment of the VDD and VSS pins to the power and ground planes within those layers The bypass capacitors can be placed in the area below the MCU with connections very close to the power pins See Figure 2 2 Kinetis Quick Reference User Guide Rev 2 08 2012 24 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations Place bypass caps on bottom layer in center of via field Figure 2 2 K60 TWR board top layer BGA pad arrangement e Supply routing For Quad Flat Pack QFP packages the power supply pins may be supplied radially to the MCU using traces rather than from planes While it is adequate to place the bypass capacitors close to the VDD and VSS pins on the traces leading to the MCU it is better to have the ground side of the bypass capacitor tied to the ground plane through a via and short trace close to the VSS pin and the VDD side tied to the power plane through a via and short trace close to the VDD pin 2 1 3 3 Oscillators The Kinetis MCU starts up with an internal digitally controlled oscillator DCO to control the bus clocking and then software is used to enable one or two external oscillators if desired The external oscillator for the Multipurpose Clock Generator MCG module can range from a 32 768 kHz crystal up to a 32 MHz crystal or ceramic resonator The external oscillator for the Real Time Clock RT
99. also applies to accurate sampling of analog signals Cost is influenced by component selection of which the PCB may be the most expensive element Quality involves manufacturability reliability and conformance to industry or governmental standards The Freescale Tower Systems are great for evaluating the operation and performance of the many features of Freescale MCUs However evaluation systems are not ideal examples for implementation of robust system design techniques This document will mention some of the hardware techniques found on the Freescale Tower Systems and will give recommendations that are more appropriate to conventional systems that are not required to implement all of the feature options 2 1 2 Floorplan The organization of the printed circuit board PCB depends on many factors Typically there are connectors mechanical components high speed signals low speed signals switches and power domains among others that need to be considered While placement of connectors and some mechanical components switches relays etc is critical to the end product s form there are some basic recommendations that can significantly affect the electrical performance and electromagnetic compatibility EMC of the PCB assembly Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 21 Hardware considerations 2 1 2 1 Connectors The PCB should be organized so that all the connectors are along one e
100. ange from 10 pF for high speed conversions to 1uF for low speed conversions Series resistors can range from a few hundred Ohms to 10 kO 2 1 4 PCB layer stack up The Kinetis MCUS are high speed integrated circuits Care must be taken in the PCB design to ensure that fast signal transitions rise fall times and continuous frequencies do not cause RF emissions Likewise transient energy that enters the system needs to be suppressed before it can affect the system operation compatibility The guidance from Kinetis Quick Reference User Guide Rev 2 08 2012 30 Freescale Semiconductor Inc gu HL a A a S Chapter 2 General System Setup Hardware Considerations high speed PCB designers is to have all signals routed within one dielectric core or prepreg of a return path which usually is a ground plane This allows return currents to predictably flow back to the source without affecting other circuits which is the primary cause of radiated emissions in electronic systems This approach requires full planes within the PCB layer stack and partial planes copper pours on signal layers where possible All ground planes and ground pours must be connected with plenty of vias Likewise all like power planes and power pours must be connected with plenty of vias Recommended layer stackups 4 Layer PCB A Layer 1 top MCU location Ground plane and pads for top mounted components no signals Layer 2 inner signals and power
101. are diagram Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 127 EPA Example code 14 4 Example code The DCD example code sends a message to a terminal showing what type of host is attached to the USB module To be able to test the three different types of hosts it is necessary to have a special tool Because the standard is new only a few companies have support for this The tool that Freescale uses is the Allion USB battery Charging Test feature Using this tool and a regular PC is enough to emulate any host and test the DCD module For more information about the Allion USB battery Charging Test feature go to http www allion com TestTool USB_Charging pdf The code waits until the USB cable is attached sending 5 V to PTBO After the software detects the rising edge in the VBUS signal starts the DCD detection sequence and waits until the sequence is completed or the module sends an error notification The next three windows show the result of each host type COM1 115200baud Tera Term WT 10 x 10 x Ele Edt Setup Control Window Help Ele Edt Setup Contro Window Hel Softuare Reset Softuare Reset rev Full size P flash 128 kBytes of RAM rev B Full size P f lash 128 kBytes of RAM Debug Pins ON dehus Fine Gt wee USB DCD Module Testing mem me USB DCD Module Testing Connected to a Dedicated Charger Connected to a Charging Host ipi x Ele Edk Setup Contro W
102. are set to intervals long enough to easily observe the timing on an onboard LED after which a message summarizing the readings is presented The messages will be filtered such that if no significant change in the potentiometer is made no report will be issued 19 1 2 Features The ADC features demonstrated by the adc_demo example code include e Simple calibration of the ADC A simple driver for the ADC which facilitates using both ADCs and their calibration with minimal software is included in the adc_demo example code Prior to taking the first measurement during the initialization of the demo project the ADC will be calibrated The use of the driver of the ADC will simplify this While the ADC can be used prior to calibration for conversions the calibration of the ADC enables it to meet its specifications Averaging by 1 4 8 16 or 32 The ADC s ability to average up to thirty two conversion values prior to ending the conversion process and generating a result will be demonstrated This feature reduces CPU load it also reduces the effect of a noise spike on any readings It is a simple arithmetic averaging of thirty two or less if so configured ADC conversions These conversions are taken upon the PDB triggering the ADC The ADC s interrupts The interrupt feature of the ADC is also used in the example In the Interrupt Service Routine ISR for ADC1 a digital filter is placed It filters the two inputs from ADCI both
103. ation must be in the erased state before being programmed Cumulative programming of bits or back to back program operations without an intervening erase within a flash memory location is not allowed Reprogramming of existing Os to 0 is not allowed as this overstresses the device Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 79 Demo code The FTFL SSD download includes example projects that execute from SRAM to illustrate program and erase capability security related commands and interrupt configurations on the flash using the TWR K60N512 Tower Module featuring 512 KB of program flash and the TWR K40X256 Tower Module featuring FlexMemory and 256 KB of program flash These projects can be opened and compiled using the IAR Embedded Workbench IDE The structure pointer flasnsspconfig Of type FLasH_ssp_conrte is created using defines whose values are dependent on the define rrasg DERIVATIVE The following code is excerpted from NormalDemo c which is included in the FTFL SSD download FLASH SSD CONFIG flashSSDConfig FTFx REG BASE FTFx control register base PFLASH BLOCK BASE base address of PFlash block PBLOCK SIZE size of PFlash block DEFLASH BLOCK BASE base address of DFlash block 0 size of DFlash block EERAM BLOCK BASE base address of EERAM block EERAM BLOCK SIZE size of EERAM block 0 size of EEE block DEBUGENABLE backgr
104. ayer 6 inner signals Layer 7 inner ground plane Layer 8 bottom signals 8 Layer PCB B Layer 1 top MCU signals and power plane Layer 2 inner ground plane Layer 3 inner signals and power plane Layer 4 inner ground plane Layer 5 inner power plane Layer 6 inner signals and ground plane Layer 7 inner power plane Layer 8 bottom signals and ground plane 8 Layer PCB C Layer 1 top MCU signals and ground plane Layer 2 inner power plane Layer 3 inner ground plane Layer 4 inner signals Thick core Layer 5 inner signals Layer 6 inner ground plane Layer 7 inner power plane Layer 8 bottom signals and ground plane 8 Layer PCB D Layer 1 top MCU signals and ground plane Layer 2 inner power plane Layer 3 inner ground plane Kinetis Quick Reference User Guide Rev 2 08 2012 32 Freescale Semiconductor Inc ETT Chapter 2 General System Setup Hardware Considerations Layer 4 inner signals and power plane Thick core Layer 5 inner signals and power plane Layer 6 inner ground plane Layer 7 inner power plane Layer 8 bottom signals and ground plane In general avoid placing one signal layer adjacent to another signal layer 2 1 5 Other module hardware considerations 2 1 5 1 VBAT The VBAT input supplies power to the RTC and a 32 byte register file during powerdown and low power modes This pin can be sourced from the
105. ble with USB 2 0 compliant hosts and peripherals The USB ports on personal computers are convenient places for portable devices to draw current for charging their batteries This convenience has led to the creation of USB chargers that expose a USB standard A receptacle This allows portable devices to use the same USB cable to charge from either a PC or from a USB charger Freescale Kinetis microprocessors include a device charger detection DCD module capable of identifying if the device is connected to a PC host or to a USB dedicated charger 14 1 2 Features The USBDCD module works with the USB transceiver to detect if the USB device is attached to a charging port either a dedicated charging port or a charging host The system software coordinates the detection activities of the module and controls an off chip integrated circuit that performs the battery charging The main features of the DCD module are the following USB battery charger specification compliant rev 1 1 Programmable timing parameters Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 125 Module Configuration Uses the same D and D signals as the USB module Enables rechargeable batteries usage Low power operation 14 1 3 Battery charger specification The USB battery charger specification establishes three different types of downstream ports Standard Downstream Port Refers to a downstream port on a device tha
106. can be connected to a PC or is able to handle external USB devices such as fingerprint readers mice USB flash drives and so on The application running on the MCU will be configured in device mode not applying 5 V to the VBUS line until the ID signals become low This indicates that a host mode reconfiguration is needed and 5 V is then applied to the VBUS signal using the external IC power distribution IC ox circuit Figure 15 10 Dual role diagram 15 6 2 Components and placement suggestions The MCU does not include a signal for supplying the 5 V VBUS power for the USB An external power management chip or discrete logic for enabling VBUS is required for the host operation Kinetis Quick Reference User Guide Rev 2 08 2012 138 Freescale Semiconductor Inc ET Chapter 15 Universal Serial Bus OTG Module The power distribution circuit must have over current detection capability to be compliant with the USB standard The 33 O series termination resistors are recommended for the FS and LS USB transceiver These series termination resistors must be placed as close as possible to the transceiver to maximize the eye diagram for the data lines Power Gatribution chip or cr e ENB VBUS oc FLAC Optonai ESO cea 38 DM La gt D 33 USB DP e Place resators close 10 Pe processor Figure 15 11 Components and placement 15 6 3 Layout recommendations Route the USB D and D signals as parallel 90 O d
107. current sources in the internal oscillator are part of the same silicon as the external electrode oscillator When the output drifts because of temperature or voltage changes both oscillators change making the final touch detection compensated When configuring TSI users must make sure to have the reference oscillator oscillate faster than the external oscillator this causes more reference counts per electrode oscillation More counts or more resolution allow more headroom for touch detection and noise rejection Figure 18 4 shows the relationship between internal and external oscillations with or without touch AVANT MANO ONO UY Touch Figure 18 4 Internal reference oscillations vs external reference oscillations Notice how the frequency becomes slower when a finger touches the electrode and how more reference oscillations blue fit into one electrode black oscillation 18 3 Features The TSI module includes several features designed to simplify touch sensing as well as add versatility and performance Capacitive touch sensing detection across all low power modes Automatic periodic scan or software triggered single scan Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 163 A TSI configuration Low power mode current adder can be lt 1 uA 16 input capacitive touch sensing pins each with individual result registers Automatic detection of electrode capacitance changes with p
108. cuted under secure mode are restricted Example code ezp wren cmd fccob 0 0x06 program longword command fccob 1 0x00 flash address is 0x00040c fccob 2 0x04 fccob 3 0x0c fccob 4 Oxff program data is Oxfffffffe fccob 5 Oxff fccob 6 Oxff fccob 7 Oxfe ezp wrfccob cmd fccob Loop until command has completed sr EP SR WIP Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 95 a G Using the EzPort module Poll SR until WIP goes low while sr amp EP SR WIP EP SR WIP Sr ezp rdsr cmd 10 1 2 5 Write and read FlexRAM The WRFLEXRAM command allows you to write four bytes of data to the FlexRAM If the FlexRAM is configured for EEPROM configuration the WRFLEXRAM command can effectively be used to create data records in EEPROM flash memory The address of the FlexRAM location should be 32 bit aligned If more than or fewer than four bytes of data is received this command has unexpected results RDFLEXRAM command returns data from FlexRAM It also has a fast speed version command FAST RDFLEXRAM which includes the dummy byte and runs at up to half of internal system clock frequency Example code ezp wren cmd ezp wrflexram cmd address buffer Loop till command has completed sr EP SR WIP Poll SR unti
109. d sr EP SR WIP Poll SR until WIP goes low while sr amp EP SR WIP EP SR WIP Kinetis Quick Reference User Guide Rev 2 08 2012 94 Freescale Semiconductor Inc _ _ _ _ _ _ _ _ y Chapter 10 EzPort Module sr ezp rdsr cmd ezp wren cmd 4 Sector program ezp pp cmd sector addr 64 pg buffer Loop till command has completed sr EP SR WIP Poll SR until WIP goes low while sr amp EP SR WIP EP SR WIP Sr ezp rdsr cmd 10 1 2 4 Write and read FCCOB registers The flash command object registers consist of a group of 12 registers each 1 byte wide These are used for sending command codes and data to the memory controller FCCOB number Command parameter contents 0 FCMD code which defines the FTFL command 1 3 Flash address 23 0 4 B Data byte 0 7 The WRFCCOB command allows you to write to the flash common command object registers via the Ezport module and execute any command allowed by flash After receiving 12 bytes of data Ezport writes the data to FCCOB registers and then automatically launches the command within flash While the FAST_RDFCCOB command allows user to read the contents of flash common command object registers NOTE If more than or fewer than 12 bytes of data are received by the WRFCCOB command the result will be unexpected Also because in Ezport mode the flash is in an NVM special mode commands that can be exe
110. d Exe IRSDUTE iii ii 102 ILLLA Hardware opine T 103 11 1 2 PCB design P conimeldat 08d as aee onec corte neret a D ERR UEU E tin tege EE p pUr RRS 104 IIZI Layout guidelines E 104 Chapter 12 Universal Asynchronous Receiver and Transmitter UART Module TEL Oi 105 DW PAI AAA AN A Aa 105 1234 Configuration emplea di ms 106 IZA USE Aic E sini ee cape a A 106 123 2 UART receive Ox anne P 107 123 3 VAR Tirada A A A AR 108 12 34 UART configuration Tor interrupts oc DMA Requests mins reir 108 124 UART RS 32 hardware dmplermembslOh ii A ia 109 Chapter 13 ENET Module DIM ARES m 111 as A e AS 111 La cir ii E 112 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 9 Section number Title Page ENDE ROTATE A 113 13 2 1 Basie MAC ENET initialisation ford genene TCP IP Sk asii da 113 Beti Code example and expr uio dp erra eid Sof na dena Gd tr i AE 113 15 3 PEL Urine nent TnEGE TOR a ous aec ced ren dH IER RAE EX ICE ties dre E Dele Seti rur ou rapi Dots ta a rt ula v Ue aber Iud 118 13 3 Code sxample dnd x Pa TAR ote a 118 CT ML A F AE N PT Pr 120 13 5 Ende exoniple ande Pia 120 Maida HMurgdbeureqmplenimntabv Ol idos 120 IE ON go A P 121 ikal Xdeexanipte and explanada eine Fed cro id doll dte l id Era cu a 121 13 35 11 Hardware staple pea Oi E
111. de example and Sx p lama Onis iie eas ciens accendit adedu ia 40 ALS DI Pori Ue di 40 3123 1 CEA a A 41 Kinetis Quick Reference User Guide Rev 2 08 2012 4 Freescale Semiconductor Inc Section number Title Page Chapter 4 Clocking System 2l ICE oci aite ticae det cuia huis Site caeca dau ada eeu qu ued baie Uda phat alga AE 43 EA Nere cer rl RT M d 43 LONE S Uo ii ad 43 AS Coni curation sram le emm 45 4131 Transitioning te PLL engaged external mode coincido oie 46 413 L1 Code example and explonalloti a sosoran r a Na 46 4 1 3 2 Transitioning between PLL engaged external mode and bypassed low power internal mode 47 413 21 Code example and explain Eve oue Rn EUR EDU 47 4 13 3 Configuring the PLL with the RTC oscillator as amp Feferenoe uscire tiit arc e cien kt cra 48 HIN odecxample and explomibtOn aie acie ar 48 ld Clocking system device hardware implementa Occitan sica 49 41 5 Layout guidelines for general routing and placem nt o ii pd netta cin esed 50 AO E A ai 50 Chapter 5 Power Management Controller PMC MODECTL 31 UiigthepowermaiaremecntcoMttollen ira 31 Dll A ARAS 51 Sal OIEA rara AAA ORAR 2 S Using the low voltage detect ESTE o ideoque ip ii lidia 2 NEM Ti M S 24 SLZ ie Ot EM 52 S144 Toterruptcode exaniple and explandtlofi ii iii 33 ILLA Hardware E i nS Et o oom em 33 Se Mae me mode collar oa DO FIEIPLUR estaba a piti do prove a 54 Seal c rer 54 V
112. detect circuit and the second is reset detect circuit Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 51 Ee ES EA Using the low voltage detection system As voltage falls below the warning level the LVW circuit flags the warning event and can cause an interrupt If the voltage continues to fall the LVD circuit flags the detect event and can either cause a reset or an interrupt The user can choose what action to take in the interrupt service routine If a detect is selected to drive reset the LVD circuit holds the MCU in reset until the supply voltage rises above the detect threshold There are two independent POR circuits for the MCU one for VDD and another for VBAT The POR circuit for the MCU will hold the MCU in reset based upon the VDD voltage The POR circuit for VBAT will reset both the RTC and OSC2 modules but will not reset the MCU If VBAT supply is not present then accesses to the RTC registers may not occur and could result in a core lockup type reset in the MCU 5 1 2 2 Configuration examples LVD and LVW initialization code is given below Notice the comments describing the chosen settings You should select the statement options for your application The NVIC vector flag may be set and should be cleared The Interrupt is enabled in the NVIC in this initialization void LVD Init void setup LVD Low Voltage Detect Voltage Select Selects the LVD trip point voltage VLVD 00 Low
113. dge of the board and away from the MCU The concept here is to prevent placing the MCU in between connectors that can become effective radiators when cables are attached This also keeps the MCU from being in the path of high energy transients that can shoot across the board from one connector to another Connectors may be placed on adjacent edges of the PCB if necessary as long as the MCU is not in a direct path between the connectors Connector locations should allow for placement of filter components Noise must be suppressed at the connector before it can propagate onto the PCB There will be more information on this topic in the input filtering section 2 1 2 2 Power domains While many systems have only one power supply voltage they typically have clean and noisy sections The definitions of clean and noisy are not important the concept is that noise from one section should not interfere with another In general AC power should be separated from DC power and digital should be separated from analog Power domain isolation is described in more detail in Freescale application note AN2764 Improving the Transient Immunity Performance of Microcontroller Based Applications The basic concept is to isolate or place a low pass filter between power domains The AC power domain should be physically isolated from the DC domains Physical separation or decoupling filters Figure 2 1 should be used to separate different DC
114. ductor Inc 165 EE KK TSI configuration the TSI with the multiplexing bits in the PORTA pin control register PCR All other TSI pins are enabled by default 2 Configure the general control and status register GENCS Configure the number of scans prescaler which is a multiplier for the number of scans Additionally it is possible to enable the continuous scan mode STM bit as well as TSI interrupts error detection low power mode and whether the end of scan or out of range interrupts are requested When using low power modes it is also important to define what low power reference clock is used LPCLKS and the scanning interval for low power mode LPSCNITV 3 Configure the scan control register SCANC Allows you to define the current that charges the electrodes and the internal reference EXTCHRG and REFCHRG as well as the delta voltage DELVOL that is applied to both The other critical configuration for SCANC is the scanning period which is dependent on the active mode clock AMCLKCS the clock prescaler AMPSC and the clock modulo SMOD An internal counter counts the number of reference clock cycles as they are output from the prescaler to the SMOD value If SMOD is configured as zero the module scans continuously without stopping after an end of scan 4 Configure the pin enable register PEN The 16 lowest bits of this 32 bit register enables each of the electrodes in active mode The low power mode scanning elect
115. e TSI SelfCalibration is called This function performs a single scan at the beginning of the program to determine a baseline or untouched value for the electrodes In this application the baseline value and the touch value are stored in separate data arrays The touch value is equal to the baseline value of each electrode plus a delta value This delta value must be below the touch value but above the noise level of the untouched electrode By debugging an ideal delta value is determined It is always best to keep this delta value as high as possible but low enough that all touches are detected Notice that the TSI SelfCalibration function performs a single scan and waits for the scan to finish and the values to be updated in the registers The calibration function also disables the TSI module afterwards so that the following code enables the module as needed During application time the TSI is interrupt driven See Figure 18 5 Figure 18 5 Application start up procedure TSI Initialization TSI Self calibration Start continuou scanning Enable end o scan interrupt Enable TSI module This application is specifically designed to show the small amount of code and CPU resources that are required to track touches with the TSI For advanced HMI functionality Freescale provides the Touch Sensing Software TSS library free of charge This library provides basic touch sensing and advanced API for HMI functions like multiple key
116. e configuration To implement this example two eDMA channels are required one to transfer the command word and the other to transfer the result The command transfer request requires a 1 ms PIT trigger and an always on trigger The DMA MUX must be configured for PIT gated channel activation Channel 1 is configured to perform this transfer Channel 0 is used to transfer the AD result to RAM This transfer is activated when the AD result ready flag is asserted The default channel arbitration gives channel 1 priority over channel 0 This configuration ensures that the AD receives a command word every 1 ms It could however cause results to be overwritten in the result register before they have been moved by the eDMA as the channel reading the results does not have priority The setup can be changed to ensure every result is captured to give the channel reading the results higher priority The DMA MUX configuration for channels 0 and 1 is Configure DMAMux for Channel 0 DMAMUX CHCONFIGO 0 DMAMUX ENABLE Enable routing of DMA request DMAMUX SOURCE 40 Channel Activation Source AD A Result Configure DMAMux for Channel 1 DMAMUX CHCONFIG1 0 DMAMUX ENABLE Enable routing of DMA request DMAMUX TRIG Trigger Mode Periodic DMAMUX SOURCE 54 Channel Activation Source AD A Command Channel 1 is configured to use a periodic trigger PIT1 The PIT1 module must be enabled and configured f
117. e example Enable the clock to the UART module UART is not active while it is being configured This step is not needed if the uart_init function is always called while the UART is already in a disabled state the UART is disabled after reset by default Configure the UART control registers for the desired format For 8 N 1 operation no UART registers actually need to be configured the default register settings configure the UART for 8 N 1 operation Calculate the baud rate dividers This includes calculating the 13 bit whole number baud rate divider the SBR field stored in the UARTx BDH and UARTx BDL registers and the 5 bit fractional baud rate divider the UARTx_C4 BRFA field Enable the transmitter and receiver to start the UART Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 107 Configuration example 12 3 2 UART receive example The function below shows an implementation for a simple polled UART receive function The parameter passed in to this function is the UART channel to receive a character uartch The function returns the character that is received char uart getchar UART MemMapPtr channel Wait until character has been received while UART S1 REG channel amp UART S1 RDRF MASK Return the 8 bit data from the receiver return UART D REG channel Since this is a polled implementation the function will wait until a character is received
118. e following list of application notes associated with crystal oscillators are available on the Freescale website at www freescale com They discuss common oscillator characteristics potential problems and troubleshooting guidelines AN1706 Microcontroller Oscillator Circuit Design Considerations e AN1783 Determining MCU Oscillator Start Up Parameters AN2606 Practical Considerations for Working With Low Frequency Oscillators AN3208 Crystal Oscillator Troubleshooting Guide Kinetis Quick Reference User Guide Rev 2 08 2012 50 Freescale Semiconductor Inc Chapter 5 Power Management Controller PMC MODECTL 5 1 Using the power management controller 5 1 1 Overview This section will demonstrate how to use the Power Management Controller PMC module to protect the MCU from unexpected low Vpp events References to other protection options will also be made 5 1 1 1 Introduction This chapter is a brief description of the power management features of the Kinetis 32 bit MCU There are three modules covered in this chapter Power Management Controller PMC Mode Controller MC Low Leakage Wakeup Unit LLWU 5 1 2 Using the low voltage detection system 5 1 2 1 Features The LVD features includes the protection of memory contents from brown out conditions and the operation of the MCU below the specified VDD levels The user has full control over the trip voltages of two detection circuits The first is a warning
119. e regulating loop of the RUN regulator and the STANDBY regulator are active but the switch connecting the STANDBY regulator output to the external pin is open Standby Mode The regulating loop of the RUN regulator is disabled and the standby regulator is active The switch connecting the STANDBY regulator output to the external pin is closed Shutdown The module is disabled STANDBY Regulator Regulated Output i Voltage Figure 15 3 Voltage regulator block diagram When the input power supply is below 3 6 V the regulator goes to pass through mode The following figure shows the ideal relation between the regulator output and input power supply OUTPUT Volt 33 L MM 27 L r og PREMISE E 1 1 1 uc i i ho 1 1 1 30 36 5 5 INPUT Volt Figure 15 4 Regulator output Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 133 Module configuration 15 5 Module configuration 15 5 1 Module dependencies Clock Source The USB module needs a 48 MHz clock to operate There are three possible sources for the USB clock PLL FLL and an external pin called USB_CLKIN With PLL or FLL there is a fractional divider after the MUX It divides the frequency of the PLL or FLL to enable the MCU to operate at higher frequencies than 48 MHz The output of the fractional divider goes to a MUX and then a
120. e warning interrupts by setting the MCR WRN_EN bit Disable self reception by setting the MCR SRX DIS bit Enable the RxFIFO by setting MCR RFEN bit Enable the abort mechanism by setting the MCR AEN bit Enable the local priority feature by setting the MCR LPRIO_EN bit 7 Configure baud rate and initialize CTRL1 amp CTRL2 bits as needed a Determine the bit timing parameters PROPSEG PSEGI PSEG2 RJW b Determine the bit rate by programming the PRESDIV field c Determine the internal arbitration mode LBUF bit 8 Initialize the message buffers MB by executing transmit process for Tx MBs and receive process for Rx MBs 9 Initialize the ID filter table if Rx FIFO was enabled 10 Initialize the Rx Individual Mask Registers RXIMRn if individual Rx masking and queue is enabled MCR IRMQ 1 QN tA E C2 WN 00Q00 9 Kinetis Quick Reference User Guide Rev 2 08 2012 148 Freescale Semiconductor Inc Chapter 16 FlexCAN Module 11 Enable the corresponding interrupts by setting required interrupt mask bits in IMASKn register for all MB interrupts CTRLn register for Bus off amp Error interrupts and MCR register for wakeup interrupt 12 Negate the MCR HALT bit 13 Wait till FlexCAN is out of freeze mode MCR FRZ_ACK 0 16 2 2 Receive process FlexCAN requires three steps to configure an MB as an Rx MB to initiate a receive process 16 2 2 1 Code example and explanation The receive process
121. each electrode The processor or sensing ASIC measures the time it takes the electrode or capacitor to become charged when a finger approaches the electrode the capacitance increases and so does the charging time this charge time change is considered a touch The problem with this method is the pullup It is a weak pullup and thus susceptible to external noise The TSI uses a different measurement method It has two constant current sources one for charging and the other for discharging the electrode This creates a triangular wave This wave has a configurable peak to peak voltage or delta voltage Observe Figure 18 2 It shows the electrode current source oscillator structure External Electrode Figure 18 2 TSI Electrode current source oscillator Kinetis Quick Reference User Guide Rev 2 08 2012 162 Freescale Semiconductor Inc AAA AAA Chapter 18 Touch Sense Input TSI Module The time the electrode takes to charge is directly proportional to the current source output and the size of the capacitor per the following formula I Fae urs V Figure 18 3 TSI electrode frequency formula The TSI measures the length of the charging time with a reference oscillator To increase the robustness of the measurement the TSI relies on an internal oscillator similar to the one shown above but with an internal capacitor instead of an external electrode The reason to do this as opposed to counting bus clock cycles is that the
122. each tower board most modules will mark this side with a white stripe into the primary elevator which has the white connectors Then attach the other elevator board onto the other side of the modules The TWR ELEV box will also have instructions for putting together the tower Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 191 L Ses Terminal configuration Finally connect a USB cable to the mini USB port on the Kinetis tower module This will be J16 on TWR K40X256 and J13 on TWR K60N512 When you plug in the USB cable to your board you should see some LED s on all the tower boards turn on This will let you know your tower was put together correctly A 4 Terminal configuration The OSJTAG feature on the Kinetis Tower Board will create a virtual serial port that communicates to your computer over the USB cable connected in the previous section This virtual serial port is connected to UARTO on the TWR K40X256 and UARTS5 on TWR K60N512 Next open the Terminal Utility from the Start Menu by going to P amp E Multilink Embedded Toolkit gt Utilities gt Terminal Utility Configure the terminal client to use USB COM 115200 baud 8 data bits 1 stop bit and no parity Then click Open Serial Port to start the connection A Terminal Window application v1 01 Duplex Terminal Window Clear Window A 5 Download sample code 1 Download the latest sample code repository for your Towe
123. ecification and is used when one device can act as a host or as a device depending on which plug is connected into the Kinetis Quick Reference User Guide Rev 2 08 2012 136 Freescale Semiconductor Inc ESSE a eS ee Chapter 15 Universal Serial Bus OTG Module board connector The mini A plug which indicates that this part is a host has the ID pin grounded while the ID in the mini B plug is floating indicating that this part will act as a device Host Only If the application supports only host mode it is not necessary to include the ID line in the hardware However because it is a host the hardware must provide 5 V with enough current to supply the device side when plugged This voltage is typically provided by an external IC controlled by the MCU Figure 15 8 Host only diagram Device Only In many cases the application just needs to communicate with an application running on a PC In this case the application running on the MCU supports only device mode This application can be self powered using an external power supply or bus powered powered from the 5 V coming from the host In both cases the USB regulator must be enabled to supply the USB transceiver Also the ID line is not needed in this scenario Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 137 Hardware implementation Figure 15 9 Device only diagram Dual Role This mode is used when the application
124. ection program buffer by writing to the programming acceleration RAM on devices with program flash only or FlexRAM on devices with FlexMemory when it is configured to function as traditional RAM The above mentioned example 1 Writes the 32 bit value 0x 11223344 four times successively into addresses 0x 1400_0000 0x1400_000F 2 Issues the Program Section command which loads the section program buffer with values stored in 0x 1400_0000 0x 1400_OOOF and programs them into the last 16 bytes of program flash with address 0x0003 FFF0 0x0003 FFFF FlexNVM partitioning for devices with FlexMemory Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 81 Additional resources For devices with FlexMemory the following example illustrates how to configure the FlexRAM for 2048 bytes of EEPROM and partition the FlexNVM for 128 KB of D Flash and 128 KB of E Flash EEPROM backup space BORK RR RK KR ke KK RR KR KR Sk Sk e KK KR KK A DEFlashPartition ESA EEEDataSizeCode 0x03 set EEPROM size for 2048 bytes DEPartitionCode 0x05 set FlexNVM for 128 KB of D Flash 128 KB for EE backup returnCode pDEFlashPartition amp flashSSDConfig Y EEEDataSizeCode DEPartitionCode pFlashCommandSequence if FTFL OK returnCode ErrorTrap returnCode Call FlashInit again to get the new Flash configuration returnCode pFlashInit amp flashSSDConfig if FTFL OK returnCode
125. ector table for this purpose the user needs to set up the Vector Table Offset Register VTOR with the address offset for the new position Use the bit TBLBASE 29 to indicate the table is either on RAM with 1 or flash with O and the TBLOFF 28 7 to indicate the address offset for the table The Cortex M4 assumes the RAM starts at 0x20000000 and expects the vector table to be stored in that address if the VTOR TBLBASE 29 bit 1s set Because the Kinetis MCU family RAM starts at Ox 1fff0000 this bit must be cleared If the vector table is planned to be stored in RAM you must the table copy from the flash to RAM Also note that in some low power modes a portion of the RAM will not be powered which can lead to a vector table corruption In this case locate the vector table in the flash prior to entering a low power mode 3 1 2 2 1 Code example and explanation The vector table is usually in flash after reset This indicates that moving the table from flash to RAM is the most common action To achieve this two steps must be performed 1 Copy from flash to RAM the entire vector table The linker command file labels are useful in this step This is what the code looks like Address for VECTOR TABLE and VECTOR RAM come from the linker file extern uint32 _ VECTOR TABLE extern uint32 VECTOR RAM Copy the vector table to RAM if VECTOR RAM VECTOR TABLE for n2 0 n 0x410 n VECTOR RAM n _ VECTOR TABLE n 2
126. ed Flash and SRAM memory for data storage and program execution Additionally external memory can be accessed over the FlexBus external bus interface Code can also be executed over the FlexBus For maximum performance executing from internal memory is recommended 1 1 3 Reset and booting When the processor exits reset it fetches the initial stack pointer SP from vector table offset 0 and the program counter PC from vector table offset 4 The initial vector table must be located in the flash memory at the base address 0x0000 0000 However the vector table can be relocated to SRAM after the boot up sequence if desired Kinetis devices only support booting from internal flash Any secondary boot must first go through an initialization sequence in flash After fetching the stack pointer and program counter the processor branches to the PC address and begins executing instructions Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 15 Software considerations For more information see the Reset and Boot chapter of the device specific reference manual 1 1 3 1 Device state during reset With the exception of the JTAG pins during reset the digital I O pins go to a disabled high impedance state with internal pullups pulldowns disabled Pins with analog functionality will default to their analog functions 1 1 3 2 Device state after reset After reset the digital I O pins remain disabled unti
127. el ra polest anlar e pel 84 9 1221 Code Example and Explanatio s ui acea ket do Cli Rose irae dor rai 85 PER ME E EDU PUE m RETI 85 91231 Codesxample and explanatione eai aiea Aa EA 86 CN ME E A A 86 Chapter 10 EzPort Module DU o A E E E E A A O A dais 89 IA M Peo E E AN E A E A A E T 89 II A A E A E E A N E E E 89 OLE FONES cenaa PTT 89 VELLA Command deseri pitis ia 90 jig e S Ena A ip di 90 IWAL NTU UE IA daria 91 MELLA SIETE IN i E 92 10 12 Conner RAISES us ii 92 HEZE Hardware COIE cian satis deca 92 E22 Wii enable mil 94 10 1 2 3 Sector erase and PU AA CAR 94 01 24 entend pend PGCIDE HE EISESES s testium A ena E deer bed v Eel tun 95 10 1755 Write and ead Plex RAM rara dnd 96 Chapter 11 Flexbus Module 1 4 Vome the Bile x Gs Mole il pt tbal an vetesa tu dien ded au anion sa dU Ih anie ditt UR bc UR ual Iq d 97 ELT ERES A AAA AAA 97 TEA TA iaa 97 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc Section number Title Page 11 112 Lon m 97 MA descpHONS sedie d edpshoipebees O br AAE RENSA 97 LLL Address and data bus multiplexing uaa cace Ia ea eb epe esi PL near eli EAE 98 ILLLIS NMIXES tl OPE sli 99 LALA Burt iii 100 1141 L2 5 Data Byte Alignment and Physical Connections aiu coe ruis e aserto cardio 100 LLLI Memory DEI ia e iiu ae dic 101 ILI ET Belergnpe IO li 101 MAS Canario Ele IOTER 102 Vd Codeexample an
128. enerates interrupt signals to the CPU 18 2 Introduction Capacitive touch sensing has become one of the de facto input technologies for user input in Human Machine Interfaces HMI It now has a place in all types of markets from industrial control panels to portable consumer devices Though capacitive touch sensing is not the only touch sensing method it is one of the most common and most practical to implement The basic element in capacitive touch sensing is the electrode In this case the electrode is a an area of conductive material with dielectric material on the top usually plastic or glass This is what the user touches This conductive area plus the dielectric material effectively creates a capacitor referenced to the system ground By touching the dielectric on top of the electrode the user effectively changes the electrode capacitance both by adding a second conductive area that is grounded the conductive part of the finger and by increasing the dielectric of the original capacitor The sensor in this case the TSI module uses a capacitive sensing method to measure changes in the electrode capacitance Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 161 Introduction Electrode Figure 18 1 Capacitive touch sensing electrode model A common measurement method for capacitive touch sensing is the RC method In this method a large pullup resistor approximately 1 MQ is connected to
129. es FB_D 7 0 and twenty four address lines FB_A 23 0 from the FlexBus module are connected to the MRAM memory in an non multiplexed mode B AD 19 0 FB AD 31 24 B CS0 FB WE B OE FB ALE Figure 11 5 FlexBus device external connections 11 1 2 PCB design recommendations 11 1 2 1 Layout guidelines Due to the critical timing required while driving external memories there are a number of considerations that must be taken into account during PCB layout Each group of signals traces must have identical loading and similar routing in order to maintain timing and signal integrity Control and clock signals are routed point to point Components could and should be placed as close as possible to the MCU To avoid crosstalk keep address and command signals separate that is a different routing layer from the data and data strobes Kinetis Quick Reference User Guide Rev 2 08 2012 104 Freescale Semiconductor Inc Chapter 12 Universal Asynchronous Receiver and Transmitter UART Module 12 1 Overview The UART module on the Kinetis family devices supports asynchronous full duplex serial communications with peripheral devices or other CPUs The UART module has three main modes of operation UART IrDA and ISO 7816 mode The following sections will discuss the features and use of the UART in UART mode In particular the use of the UART as an RS 232 serial
130. eset Interrupt goes to ISR no LLWU VLPR Reduce system bus and core frequency to 2 MHz or less Flash access frequency limited to 1 MHz AVLP 1 Set RUNM 10 Note Poll VLPRS bit before executing VLPR specific code You also could wait 5 us instead of waiting for VLPRS VLPR Set RUNM 00 or Interrupt with LPWUI 1 or Reset Note Poll REGONS bit before increasing frequency VLPR VLPW Execute WAIT VLPW VLPR Interrupt with LPWUI 0 VLPW Interrupt with LPWUI 1 or Reset VLPS LPLLSM 000 or 010 execute STOP VLPR Interrupt with LPWUI 0 VLPS AVLP 1 LPLLSM 010 execute STOP Interrupt with LPWUI 1 or Reset Set ALLS in PMPROT LPLLSM 011 Execute STOP LLS Wakeup from enabled LLWU pin or module source or Reset pin VLPR LLS Set ALLS in PMPROT LPLLSM 011 Execute STOP VLLS 3 2 1 Set AVLLSx in PMPROT LPLLSM 101 for VLLS3 110 for VLLS2 111 for VLLS1 Execute STOP Table continues on the next page Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 63 Source of wakeup pins and modules Table 5 2 Mode transition requirements continued VLLS 3 2 1 RUN Wakeup from enabled LLWU input source or Reset All wakeup goes through Reset sequence Check SRS for source of wakeup Check LPLLSM for mode 11 VLPR VLLS
131. esistor In certain applications where conducted emissions or ESD is a concern external protective components can be added The idea is to use only a transient voltage suppression TVS diode designed for ESD suppression and a low value 100 470 Q resistor as protection for current that might flow into the MCU Series resistor recommended for overcurrent protection Electrode TVS diode for ESD protection Figure 18 7 For further information on designing electrodes and in depth considerations on hardware and electrode design search for application notes Designing Touch Sensing Electrodes document AN3863 at www freescale com touchsensing Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 169 TSI hardware implementation 18 5 1 PCB Routing and Placement The following list includes the most important things to consider when designing touch sensing electrodes for the TSI 1 Trace width Keep the trace width as thin as possible 5 7 mil traces are recommended The wider the traces the more base capacitance 2 Clearance Leave a minimum clearance of 10 mil At the trace connection to the MCU the pitch is lower than 10 mil therefore use bottleneck mode 3 Keep trace length as short as possible As traces becomes longer the baseline capacitance increases and is also more susceptible to coupled noise 4 Electrode traces must be routed in a different layer from the one containing the
132. et and DRS is set to 1 48 MHz from a 32 768 kHz crystal MCG C4 MCG C4 DMX32 MASK MCG C4 DRST DRS 1 4 1 4 Clocking system device hardware implementation It is possible to provide all the system level clocks from internal sources However if the PLL is to be used or an accurate reference clock is required an external clock must be provided This can be from an externally generated clock source that provides a square wave clock or it can be from an internal oscillator using an external crystal or resonator There are two independent on chip crystal oscillators one for the RTC and one to provide a reference for the main system clocks The RTC clock source comes only from the dedicated RTC oscillator In many cases the RTC oscillator will require only an external 32 kHz crystal The oscillator feedback resistor is integrated within the device along with selectable internal load capacitors The main system oscillator can be configured in various ways depending on the crystal frequency and mode being used Refer to the device specific reference manual for details The main oscillator also has programmable internal load capacitors When the main oscillator is configured for low power an integrated oscillator feedback resistor is provided Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 49 Clocking The internal crystal load capacitors in both oscillators are selectable in softwa
133. g WDOG STCTRLH amp WDOG STCTRLH WDOGEN MASK Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 17 Software considerations 1 1 4 2 2 Initialize RAM Depending on the application the next steps may be required First copy the vector table from flash to RAM copy initialized data from flash to RAM clear the zero initialized data section and copy functions from flash to RAM 1 1 4 2 3 Enable port clocks To configure the I O pin muxing options the port clocks must first be enabled This allows the pin functions to later be changed to the desired function for the application SIM SCGC5 SIM SCGC5 PORTA MASK SIM SCGC5 PORTB MASK SIM SCGC5 PORTC MASK SIM SCGC5 PORTD MASK SIM SCGC5 PORTE MASK 1 1 4 2 4 Ramp system clock to selected frequency The Multipurpose Clock Generator MCG provides several options for clocking the system Configure the MCG mode reference source and selected frequency output based on the needs of the system 1 1 4 2 5 Enable pin interrupt In this example pin PTA4 is connected to a push button An interrupt is generated when the button is pressed A GPIO interrupt is used instead of an NMI interrupt because an edge sensitive interrupt is preferred versus a level sensitive interrupt This ensures that one interrupt will occur per button press Interrupts need to be enabled in the ARM core as described in the NVIC chapter Configure the PTA4 pin f
134. ge MCG Static IRCLK 2 MHz IRC 2 MHz IRC Static no clock Static no clock OFF optional PLL possible CORE CLK OFF 2 MHz max OFF OFF OFF OFF Sys CLK OFF 2 MHz max 2 MHz max OFF OFF OFF Bus CLK OFF 2 MHz max 2 MHz max OFF OFF OFF FLASH Powered 1 MHz max no Low Power Low Power OFF OFF pgm erase Portion of Powered Powered Powered Powered Powered Powered in SRAM_U VLLS3 4 2 Remaining Powered Powered Powered Powered Powered Powered in SRAM_U and VLLS3 4 2 SRAML FlexMemory Powered Powered Powered Powered Powered Powered in VLLS3 Sys Reg File Powered Powered Powered Powered Powered Powered VBAT Reg File VBAT Powered VBAT Powered VBAT Powered MODULES VBAT Powered VBAT Powered DMA Static FF FF Static Static OFF UART Static WU 125 kbit s 125 kbit s Static WU Static OFF SPI Static 1 Mbit s 1 Mbit s Static Static OFF 12C Static address 100 kbit s 100 kbit s Static address Static OFF WU WU CAN Wakeup FF FF Wakeup Static OFF Table continues on the next page Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 61 Mode transition requirements Table 5 1 Module operation in low power modes continued FF FF OFF 128 Static Static Static Segment LCD FF FF FF FF FF RTC clk FF RTC clk TSI Wakeup FF FF Wakeup Wakeup One Wakeup One pin pin FTM Static FF FF Static Static OFF PIT Static FF FF Static Static O
135. guration examples After exiting reset or recovering from a very low leakage state the MCG will be in FLL engaged internal FEI mode with MCGCLKOUT at 20 97 MHz assuming a factory trimmed slow IRC frequency of 32 768 kHz If a different MCG mode is required the MCG can be transitioned to that mode under software control Although not included in the sample code you should include a timeout mechanism when checking the status bits within the MCG After making changes to clock selection bits enabling the oscillator or the PLL the appropriate status bits should be verified before continuing If for some reason the bit being checked does not update the while loop will never exit unless a timeout mechanism is used A timeout counter should be started before checking the status bits This counter must then be stopped and reset after the loop exits If a timeout is generated a decision can be made about what to do depending on the status bits that failed to update For example if the oscillator does not start due to a damaged PCB trace the decision to continue with an internal only clocking mode can be made with an appropriate indication to the user or a central monitoring station Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 45 EE el Clocking 4 1 3 1 Transitioning to PLL engaged external mode PLL engaged external mode uses an external clock from either the crystal oscillator or an ex
136. he specific PHY used Kinetis Quick Reference User Guide Rev 2 08 2012 122 Freescale Semiconductor Inc Chapter 13 ENET Module MIIO MDC RMIIO MDC MDC Serial MIIO_ MDIO RMIIO MDIO MDIO management RXD 3 2 Differential MIIO RXD 1 0 RMIIO RXD 1 0 RXD 1 0 Rx To RXDV Magnetics RXCLK Differential TX RJ45 Tx TX MIIO RXER RMIIO RXER RXERR ivan 4 TXCLK interface MIIO_TXEN RMIIO_ TXEN TXEN ACT T TXD 3 2 LINK MIIO_TXD 1 0 RMIIO_TXD 1 0 TXD 1 0 SPEED MIIO RXDV RMIIO CRS DV CRS CRSDV COL INT RST XO XI VDD GND Kinetis MII RMII interface 9 signals N C N C RSTIN 50MHz pin osc Figure 13 5 RMII mode connection example 2 NOTE The indicates special precautions that must be taken for a each specific Ethernet PHY manufacturer The CRSDV function may be located in either pin The hardware considerations from the PHY to the Ethernet Magnetics or the RJ45 connector are supplied from the PHY manufacturer 13 6 PCB Design Recommendations ENET interface signals function at 25 or 50 MHz Design guidelines must be followed 13 6 1 Layout Guidelines Each vendor implementation guide must be closely followed The quality of the Ethernet connection is many times dependent on board routing magnetics quality and the configured mode of operation for the PHY Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 123 PCB Design Recommendations 13 6
137. hen using the MAC NET interface most of the time it runs over an RTOS Regardless of the type of RTOS some generic modes need to be defined and followed before integrating to an existing software The main 4 modes of operations are as follows e Basic Initialization basic steps needed to run the MAC NET PHY Management Interface configuration needed to get set PHY configurations MII media independent interface to the PHY e RMII reduced media independent interface to the PHY 13 2 1 Basic MAC ENET initialization for a generic TCP IP stack Basic initialization is needed when configuring the MAC NET controller 13 2 1 1 Code example and explanation The following list is a sequence of steps needed to correctly configure the ENET interface Enable ENET clock and disable the MPU Configure buffer descriptions BD in little endian Reset MAC controller Configure pins MII or RMII mode Clear and unmask ENET xmit rx and error interrupts Set interrupt level and priority Take network speed and duplex from PHY then configure ENET accordingly Configure MAC address with hash support Point MAC ENET to xmit and Rx BD Configure maximum packet size Start MAC ENET controller 10 Set ENET ready to receive OMAANNMNBWN KE Example code Buffer Descriptor Format ifdef ENHANCED BD Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 113 Configuration examples typedef
138. ide Rev 2 08 2012 108 Freescale Semiconductor Inc SSS ee ee A a Chapter 12 Universal Asynchronous Receiver and Transmitter UART Module CPU loading However the overhead required to set up the interrupts or DMA should be taken into account If the additional overhead outweighs the reduction in CPU loading then polling is the best approach Using the UART interrupts to signal the CPU that data can be read from or written to the UART will help to decrease the CPU loading The UART has a number of status and error interrupt flags that can be used but for typical receive and transmit operations the receive data register full flag UARTx SI RDRF and transmit data register empty flag UARTx SI TDRE would be enabled using the UARTx_C2 TIE RIE bits The names of these flags are a bit misleading since they don t always indicate a full or empty condition For UARTs that include a FIFO the full or empty condition is determined based on the amount of data in the FIFO compared to a programmable watermark If both the RDRF and TDRE interrupt requests are enabled then the UART interrupt handler would need to read the S1 register to determine which condition is true then read and or write to the UART data register UARTx_D to clear the flags Since the CPU is still responsible for moving data there is CPU loading associated with an interrupt driven software approach Using the DMA to move data can help to decrease the CPU loading even more tha
139. ifferential pairs Match the trace lengths as closely as possible Matching within 150 mil is a good guideline Try to maintain short trace lengths not longer than 15 cm Avoid placing USB differential pairs near signals such as clocks periodic signals and I O connectors that might cause interference Minimize vias and corners Route differential pairs on a signal layer next to the ground plane Avoid signal stubs Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 139 Example Code Processor pins USB DE i m p p B 0 0a USB DP 4 o D 33 ohm resistor Maintain 90 ohm differential spacing for both traces Figure 15 12 USB layout recommendations 15 7 Example Code NOTE The example code included in this user guide is for demonstration purposes only For general purpose applications please download Freescale USB stack with PHDC support or Freescale MQX Software Solutions from http www freescale com usb 15 7 1 Device code This demo is a simple echo terminal using the communication device class The USB is recognized as a standard COM port that can be used for the HyperTerminal or any program that uses a serial port To run this demo it is necessary to have a 48 MHz frequency out of the USB clock After the board is connected the PC requests a driver Point to the Freescale CDC Driver kinetis inf file to install the device on your computer In the Device
140. ilters series resistor and capacitor to ground to prevent data corruption due to crosstalk or transients The filter capacitor should be placed close to the MCU pin while the resistor can be placed closer to the source Inputs that come from connectors should have low pass filtering at the connector to prevent noise from propagating onto the PCB This requires a robust ground structure around the connector Series resistors for signals that come from off board should be placed as close to the connector as possible A filter cap closer to the MCU input pin may be required if the signal trace length is very long and can pick up noise from other circuits Output pins should not have any significant capacitance placed close to the MCU These signals can have capacitors at the load or connector to minimize radiated emissions if necessary 2 1 3 4 3 Analog inputs Analog inputs should have low pass filters as well The challenge with analog inputs especially for high resolution analog to digital conversions is that the filter design needs to consider the source impedance and sample time rather than a simple cutoff frequency This topic cannot be discussed in detail here but the general concept is that fast sample times will require smaller capacitor values and source impedances than slow sample times Higher resolution inputs may require smaller capacitor values and source impedances than lower resolution inputs In general capacitor values can r
141. indow Help Software Reset re v 8 Full size P flash 128 kBytes of RAN Debug Pins ON wee USB DCD Module Testing e Connected to a Standard Hosti Figure 14 2 DCD demo results Software Explanation The software is simple This section will explain in detail how to set the clocks USB and I O pins to run the DCD example 1 First configure one I O pin as input In this example PTBO is used for the VBUS detection Kinetis Quick Reference User Guide Rev 2 08 2012 128 Freescale Semiconductor Inc Chapter 14 USB Device Charger Detection USBDCD Module FLAG SET SIM SCGC5 PORTB SHIFT SIM SCGC5 Enable clock for PTB PORTB PCRO 0 PORT PCR MUX 1 configure PTBO as I O pin 2 Next enable the USB and the DCD clock gating bits in the SIM SIM Configuration SIM SCGC4 SIM_SCGC4 USBOTG MASK USB Clock Gating SIM SCGC6 SIM SCGC6 USBDCD MASK USB Clock Gating 3 Pre initialize the USB This is required to enable the pullup resistor that is controlled by the USB module USB pre initialization USBOTG USBTRCO USBOTG USBTRCO USBRESET MASK while FLAG CHK USBOTG USBTRCO USBRESET SHIFT USBOTG USBTRCO FLAG SET USBOTG ISTAT USBRST MASK USBOTG ISTAT Enable USB Reset Interrupt LAG SET USBOTG INTEN USBRSTEN SHIFT USBOTG INTEN USBOTG USBCTRL 0x00 USBOTG USBTRCO 0x40 USBOTG CTL 0x01 4 Configure the DCD clock register rj USBDCD CLOCK DCD TIME BASE 2
142. inger approaching or moving away may falsely trigger more than one touch Debouncing code can be read in the QRUG application code Figure 18 6 shows a flow diagram that explains the debouncing algorithm Figure 18 6 Debounce algorithm flowchart Initialize debounce counter Counter gt touch threshold Clear Touch flag ext electrode Y es Ser Clear Touch fiag lear Touch fl Touch flag Clear Touch fag The interrupt subroutine is also in charge of checking if the ValidTouch flag was enabled after debouncing for each of the four electrodes and toggling the appropriate LED The DBOUNCE COUNTS macro can be found in the TSI h file This value defines how many scans with the capacitance above the touch threshold are needed for a touch to be considered valid This value can be modified to suit the specific needs of different applications and electrode sizes Kinetis Quick Reference User Guide Rev 2 08 2012 168 Freescale Semiconductor Inc Chapter 18 Touch Sense Input TSI Module 18 5 TSI hardware implementation The critical external component for the TSI is the electrode Electrodes are flat conductive areas that can be etched into a PCB or drawn with conductive inks on plastic or crystal With the GPIO measurement method an external pullup resistor is needed In the case of the TSI the electrode charge is driven by the current sources therefore there is no need for an external pull up r
143. interrupt sources including 16 that are core specific It also implements up to 16 priority levels that are fully programmable The NVIC uses a vector table to manage the interrupts This vector table can be stored in either flash or RAM depending on the application Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 37 NVIC Table 3 1 Core exceptions Address Vector IRQ Source module Source description ARM Core System Handler Vectors 0x0000_0000 0 ARM core Initial stack pointer 1 ARM core Initial program Counter 2 ARM core NMI 3 ARM core Hard fault 4 ARM core Memory manage fault 5 ARM core Bus fault 6 ARM core Usage fault 11 ARM core SVCall 12 TEE ARM core Debug monitor 14 ARM core Pendable request for system service 15 ARM core System tick timer 3 1 2 Configuration examples The NVIC is easy to configure Two examples are shown in this section The first example shows how to configure the NVIC for a module The low power timer LPTMR is used as the base for this example The second example shows how to locate the vector table from the flash to RAM 3 1 2 1 Configuring the NVIC Configuring the NVIC for the specific module involves writing three registers NVICSERx NVIC Set Enable Register NVICCPRx NVIC Clear Pending Register and NVICIPxx NVIC Interrupt Priority After the NVIC is configured and the desired
144. iseENETBuffers void unsigned portBASE TYPE ux unsigned char pcBufPointer pcBufPointer amp xENETTxDescriptors unaligned O while unsigned long pcBufPointer amp OxOfUL 0 pcBufPointer xENETTxDescriptors NBUF pcBufPointer Kinetis Quick Reference User Guide Rev 2 08 2012 116 Freescale Semiconductor Inc AAA Chapter 13 ENET Module pcBufPointer amp xENETRxDescriptors unaligned 0 while unsigned long pcBufPointer amp OxOfUL 0 pcBufPointer xENETRxDescriptors NBUF pcBufPointer Setup the buffers and descriptors pcBufPointer amp ucENETTxBuffers O while unsigned long pcBufPointer amp OxOfUL 0 pcBufPointer for ux 0 ux lt configNUM ENET TX BUFFERS ux xENETTxDescriptors ux status TX BD TC ifdef NBUF LITTLE ENDIAN xENETTxDescriptors ux data uint8 t REV uint32_t pcBufPointer else xENETTxDescriptors ux data pcBufPointer Hendif pcBufPointer configENET TX BUFFER SIZE xENETTxDescriptors ux length 0 ifdef ENHANCED BD xENETTxDescriptors ux ebd status TX BD IINS TX BD PINS endif pcBufPointer amp ucENETRxBuffers 0 while unsigned long pcBufPointer amp OxOfUL 0 pcBufPointer for ux 0 ux lt configNUM ENET RX BUFFERS ux xENETRxDescriptors ux status RX BD E xENETRxDescriptors ux length 0
145. l WIP goes low while sr amp EP SR WIP EP SR WIP Sr ezp rdsr cmd Kinetis Quick Reference User Guide Rev 2 08 2012 96 Freescale Semiconductor Inc Chapter 11 Flexbus Module 11 1 Using the Flexbus module 11 1 1 Overview A multi function external bus interface called the FlexBus interface controller is provided with a basic functionality of interfacing to slave only devices It can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry external ROMs flash memories programmable logic devices or other simple target slave devices 11 1 1 1 Introduction The FlexBus has up to six independent user programmable chip select signals FB_CS 5 0 8 bit 16 bit and 32 bit port sizes with configuration for multiplexed or non multiplexed address and data buses Size configurable transfers 8 bit 16 bit 32 bit Programmable burst and burst inhibited address setup time with respect to the assertion of chip select address hold time with respect to the negation of chip select and transfer direction Extended address latch enables option help with glueless connections to synchronous and asynchronous memory devices 11 1 1 2 Features 11 1 1 2 1 Signal descriptions FB_A 31 0 In a non multiplexed configuration this is the address bus Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 97 AAA AA Using the Flexbus
146. l enabled by software Also interrupts are disabled and the clocks to most of the modules are off The default clock mode after reset is FLL Engaged Internal FEI mode In this mode the system is clocked by the frequency locked loop FLL using the slow internal reference clock as its reference The watchdog timer is active therefore it will need to be serviced or disabled if debugging The core clock system clock and flash clock are enabled after reset to support booting Also the flash memory controller cache and prefetch buffers are enabled 1 1 4 Typical system initialization The following is a summary of typical software initialization The code snippets are taken from a hello world project written in IAR Embedded Workbench This project is available in the Kinetis sample code found in the file KINETIS512 SC zip which accompanies this users guide 1 1 4 1 Lowest level assembly routines These routines are assembly source code found in the file crtO s The address of the start of this code is placed in the vector table offset 4 initial program counter so that it is executed first when the processor starts up This is accomplished by labeling this section exporting the label and placing the label in the vector table The vector table can be found in vectors h In this example the label used is __ startup 1 1 4 1 1 Initialize general purpose registers As a general rule it is recommended to initialize the processor general purpose
147. le analog ground and voltage planes both for analog power and voltage references if full accuracy of the ADC is required Kinetis Quick Reference User Guide Rev 2 08 2012 178 Freescale Semiconductor Inc Chapter 19 Using Peripheral Delay Block PDB to Schedule Analog to Digital Converter ADC Conversions 19 3 2 ESD EMI considerations The RC filter used for anti aliasing is all that is required to enhance ESD protection EMI interference is also dealt with by the same inexpensive filter Minimizing loop area for any RF ranged signals is also essential Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 179 Layout guidelines Kinetis Quick Reference User Guide Rev 2 08 2012 180 Freescale Semiconductor Inc Chapter 20 Using OPAMP for Kinetis Microcontrollers 20 1 Overview This chapter will demonstrate how to configure the operational amplifier OPAMP module in various modes that a typical application may require and also showcases a demonstration example 20 2 Introduction The OPAMP module is integrated on existing Kinetis K50 family devices Its plus side input minus side input and output are accessible from external pins and can be used in combination with external circuitry Currently the integrated OPAMP is available in the Kinetis K50 family which consists of K50 K51 K52 and K53 series devices Other future Kinetis devices may also have built in OPAMP Dependi
148. mation in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which failure of the Freescale Se
149. mber of lanes depending on the data port width Figure 11 2 shows the byte lanes that external memory connects to and the sequential transfers of a 32 bit transfer for the supported port sizes when byte lane shift is disabled or enabled Kinetis Quick Reference User Guide Rev 2 08 2012 100 Freescale Semiconductor Inc PET Chapter 11 Flexbus Module Disable Enable Caterral Data Bus J2 b amp Port Momory 32 bit Port Mareos y TICE Ayto 2 yte 1 8yte By TL Byte Byte c gt gt gt gt gt ss o NIIMEDIM dit Port Memory Uv e Eo Bait Port Memory B bit Port Memory Figure 11 2 Sequential 32 bit transfers byte lane shift differences 11 1 1 2 6 Memory map Typical memory mapping as shown in Figure 11 3 0x6000_000 0xA000 0000 is the FlexBus space used for execution OxXA000 0000 OXEO00 0000 can only be used for data Figure 11 3 FlexBus memory range 11 1 1 2 7 Reference clock Figure 11 4 shows a high level diagram for the FlexBus reference clock The maximum FlexBus clock frequency in run mode is up to 50 MHz Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 101 Using the Flexbus module Figure 11 4 Clocking diagram 11 1 1 3 Configuration examples In this example the FlexBus is connected to the MRAM memory of the TWR MEM board 11 1 1 3 1 Code example and explanation Figure 11 4 shows the FlexBus reference clock derived from
150. me basic chip information and then write Hello World to the terminal After that it will echo anything typed into the terminal screen 13 Hit the Break button to pause the debugger You can then step line by line via the Step Over button and dive into function calls with the Step Into button 14 Hit the Stop button to end the debugging session Kinetis Quick Reference User Guide Rev 2 08 2012 194 Freescale Semiconductor Inc How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan Ofreescale com Asia Pacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 86 10 5879 8000 support asia freescale com Document Number KQRUG Rev 2 08 2012 Infor
151. miconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS complaint and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners O 2012 Freescale Semiconductor Inc freescale v
152. n 5 Use the ADC driver to send the desired configuration to the ADC s Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 173 Configuration example 6 Calibrate the ADCs in the configuration in which they will be used and then restore the desired configuration 7 Enable the ADC and PDB interrupts in NVIC 8 Software trigger the PDB The PDB will then start triggering the ADC as it times the intervals 9 Handle the PDB ADCO and ADC1 interrupts 19 2 1 1 Turn on ADC and PDB clocks Example Code from the adc_demo project Clocks need to be turned on to the ADC and PDB using the SIM module Turn on the ADCO and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB SIM_SCGC6 SIM SCGC6 ADCO MASK SIM SCGC3 SIM SCGC3 ADC1 MASK SIM SCGCe SIM SCGC6 PDB MASK 19 2 1 2 Configure System Integration module for ADC defaults SIM SOPT7 amp SIM SOPT7 ADCIALTTRGEN MASK SIM SOPT7 ADCIPRETRGSEL MASK SIM SOPT7 ADCOALTTRGEN MASK SIM SOPT7 ADCOALTTRGEN MASK SIM SOPT7 SIM SOPT7 ADCOTRGSEL 0 applies only in case of ALT trigger in which case selects PDB not ALT trigger selects PDB not ALT trigger PDB external pin input trigger for ADC SIM SOPT7 SIM SOPT7 ADCITRGSEL 0 same for both ADCs 19 2 1 3 Configure Peripheral Delay Block PDB Configure the Peripheral Delay Block PDB enable PDB pdb counter clock busclock
153. n lab3 c find the comment and uncomment the following code as below Kinetis Quick Reference User Guide Rev 2 08 2012 186 Freescale Semiconductor Inc Chapter 20 Using OPAMP for Kinetis Microcontrollers vfnOPAMPConfig LAB3a Non inverting OPAMPO positive selects DACO negative selects DAC1 v nOPAMPConfig LAB3b Inverting OPAMPO positive selects DAC1 negative selects DACO v nOPAMPConfig LAB3c Non inverting OPAMPO positive selects DACO negative selects DAC1 4 In the common h file uncomment the following code as below define LAB3 5 Compile the project as shown below 4v 8 uomo 95 6 Flash the code by clicking the green play button as shown below Y Sw veg We 7 Open Serial Grapher Utility as shown below Li ad fa P amp E OSBDM OSJTAG Virtual Serial Toolkit fan Utilities Serial Grapher Utility v e Freescale MQX 3 7 gt P e Toolkit Launchpad 4 Acceleromoter Demo E Setup AUNKARML 20h E Freescale CodeWarrior gt f Documentation gt Terminal Utility Y Y MB serial Redirector de Favorites gt 8 On the P amp E Serial Grapher configure serial communication port as USBCOM with the baud rate of 115 200 9 Click Open Serial Port Start Demo Serial Port Graphing Utility v2 05 Port Open Serial Port end Star Demo freescale PE Homepes tt sr ue 1 11 At this moment the user must be able to see a sine wave as below If no
154. n the status register with the WREN command After those commands are completed the WEN bit will automatically clear so next time you issue another write command the WREN command should be issued again Example code ezp wren cmd ezp write byte EZPORT WREN while MCF5282 OSPI OIR amp MCF5282 QSPI QIR SPIF ezp wrdi cmd ezp write byte EZPORT WRDI while MCF5282 OSPI OIR amp MCF5282 OQSPI QIR SPIF NOTE The code above assumes lower level byte sending with QSPI has been implemented with ezp write byte You could easily implement this and port it to other SPI modules like DSPI 10 1 2 3 Sector erase and program The SP command programs up to one section of flash memory that has previously been erased by an SE command The starting address of both commands should be 64 bit aligned three LSBs being zero The Ezport module buffer will receive program data in FlexRAM programming acceleration RAM before executing the SP command so the number of bytes to be programmed should be a multiple of eight and up to one section size at a time Example code set to ezp mode ezp spi init 0 6 0 0 max permitted clock speed for read 1 Boot up from reset with EZPORT enabled ezp wren cmd 2 Verify WEN flag is set Sr ezp rdsr cmd if sr EP SR WEN printf Failure in SR value WEN not set n error _count 3 Sector erase ezp se cmd sector addr Loop till command has complete
155. n using the UART interrupts The UART s same RDRF and TDRE flags used for an interrupt driven software approach can be re routed to the DMA controller instead This is done by setting the UARTx CS TDMAS RDMAS bits Each of these requests would be routed to a different DMA channel the specific DMA channels would be selected by programming the DMA channel mux One DMA channel would be responsible for handling receive traffic so it would read one or more bytes from the UART for each request The second DMA channel would be responsible for handling the transmit traffic so it would write one or more bytes to the UART for each request When the entire transmit or receive DMA movement is complete the DMA can interrupt the core to notify it of the completion In this approach the CPU has no loading associated with the actual data movement AII of the CPU loading is the result of the initial configuration of both the UART and DMA modules and then any processing of data that is required to prepare it for transmission or interpret it after reception 12 4 UART RS 232 hardware implementation The diagram below shows a block diagram of the hardware connections for an RS 232 implementation The diagram shows the optional hardware flow control signals but only the RX and TX data connections are required Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 109 LTTE T UART RS 232 hardware implementation UART RS 232 Xc
156. ng on the package type some of these devices have two OPAMP modules while others have only one OPAMP This chapter uses the K53 144 pin package as an example The K53 144 pin package has OPAMPO and OPAMPI 20 3 Features Each OPAMP has the following features Five programmable OPAMP modes General purpose mode Buffer mode Programmable Gain mode Low Power mode High Speed mode Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 181 a Nomenclature Programmable input signal routing Output readable by ADC without external routing Access to plus side input minus side input and output via external pins 20 4 Nomenclature The OPAMP can be accessed externally with the following pin names OPO_DPO OPAMP module 0 differential positive input 0 e OPO_DMO OPAMP module 0 differential minus also called negative input O OPO_OUT OPAMP module 0 output e OP1_DP0 OPAMP module 1 differential positive input O e OPI DMO OPAMP module 1 differential minus also called negative input O e OPI OUT OPAMP module 1 output 20 5 User case examples For all the modes mentioned below e Vp Positive terminal Vn Negative terminal Vout Output terminal Buffer mode OPAMPXx CO register field MODE 1 0 0b00 Vout Vp Figure 20 1 OPAMP in Buffer mode In this mode the OPAMP is used as a voltage follower The output of the OPAMP is same as the input signal selected for
157. nnels additionally provide periodic trigger functionality And each channel router can be assigned to one of the 52 possible peripheral DMA slots or to one of the 10 always on slots The logic structure of the DMA Mux is illustrated in Figure 7 3 0lld L Lld c Lld Source 0 Disable Source 1 RSV channel 1 channel 2 channel 3 MA channel 4 channel 5 eDMA channel 15 Figure 7 3 DMA Mux block diagram 7 1 2 2 Trigger mode The DMA Mux supports three different options for triggering DMA transfer requests Disabled Mode No request signal is routed to the channel and the channel is disabled This is the reset state of a channel in DMA Mux Disabled mode can also be used to suspend an eDMA channel while it is reconfigured or not required Normal Mode A DMA request is routed directly to the specified eDMA channel Periodic Trigger Mode This mode is only available on eDMA channel 0 3 In this mode a PIT request is working as a strobe for the channel s DMA request source which means the DMA source may only request a DMA transfer periodically The transfer may be started only when both the DMA request source and the period Kinetis Quick Reference User Guide Rev 2 08 2012 70 Freescale Semiconductor Inc Chapter 7 Enhanced Direct Memory Access eDMA Controller trigger are active This provides a means to gate or throttle transfer requests using the PIT This is normally used f
158. not scanning SCNIP 0 It is not necessary to disable the module go into software triggered mode and wait for the current scan to finish Clear any pending flags error overrun out of range or end of scan before enabling interrupts The following is a typical TSI initialization Enable clock gates SIM SCGC5 SIM SCGC5 TSI MASK SIM SCGC5 SIM SCGC5 PORTA MASK PORTA PCR4 PORT PCR MUX 0 Enable ALTO for portA4 Configure the number of scans and enable the interrupt TSI GENCS TSI GENCS NSCN 10 TSI GENCS TSIIE MASK TSI GENCS PS 3 TSI SCANC TSI SCANC EXTCHRG 3 TSI SCANC REFCHRG 31 TSI SCANC DELVOL 7 TSI SCANC SMOD 0 TSI SCANC AMPSC 0 Enable the channels desired TSI PEN TSI PEN PEN5 MASK TSI PEN PEN7 MASK TSI PEN PEN8 MASK TSI PEN PEN9 MASK uint32 TSI CHAN5 OFFSET uint32 TSI CHAN7 OFFSET uint32 TSI CHAN8 OFFSET uint32 TSI CHAN9 OFFSET TSI THRESHLD5 TSI THRESHLD7 TSI THRESHLDS8 TSI THRESHLD9 Y y Enable TSI module TSI GENCS TSI GENCS TSIEN MASK Enables TSI Steps taken to enable the module 1 Enable clock gates Both the TSI and the PORTA clock gates are enabled PORTA clock gate is enabled because TSI channel 5 is shared with PORTA 4 This pin does not have the TSI as a primary function It is necessary to change the pin function to Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semicon
159. note to Section 14 4 Example Code of Chapter 14 USB Device Charger Detection USBDCD Module and Section 15 7 Example Code of Chapter 15 Universal Serial Bus OTG USBOTG Module Deleted the sentence Refer to the full source code for this example in the ZIP file from the Section 7 1 5 2 Module configuration of Chapter 7 Enhanced Direct Memory Access eDMA Controller e Minor editorial changes 08 2012 2 N A Kinetis Peripheral Module Quick Reference Rev 2 2 Freescale Semiconductor Contents Section number Title 1 1 Software considerations LIA 1 1 2 1 1 3 1 1 4 2 1 Hardware considerations Chapter 1 General System Setup Software Considerations NEVE A E veces tad AE E E E E A kat ar a ane ann COSER M M Rost amb DOORS optet metit tbe tora A LRL Devir stie diine resa UU T LO LL3 f Device stat aner TE henaa a r R Typical Sy SS a DUE IO arnoa n A di 113 Tews level assembly YOUBDER asec sess censariesahcavcaceuienie sautaiecascdedetoieabuscamseinecanialaacdicuees 1141 1 Tmitialize general purpose PEEISUBES oec deer ttd bitur roti tenes apad LA dd Unmask mierrupis at ARM Gore sisanra 1 1 4 1 1 2 Branch to start of C initialization code 1142 DEMOTORES T LII Disable watchdog iue ert ttr as LIAL Tiialize RAM e LIS Sd Enable ora dcn neo desees eli e bera beide 1 4 2 4
160. ns to be used LCD PENH LCD PENL 7 Enable LCD pins to be used as BackPlanes LCD BPENH LCD BPENL 8 Configure the phase of the backplanes LCD WFXxTOy used as backplanes 9 Configre the AR register 10 Enable the LCD module This is the code snippet for the SLCD intialization Code Snippet SLCD Initialization enable clock gate for Ports SIM SCGC5 SIM SCGC5 LPTIMER MASK SIM SCGC5 REGFILE MASK SIM SCGC5 TSI MASK SIM SCGC5 PORTA MASK SIM SCGC5 PORTB MASK SIM SCGC5 PORTC MASK SIM SCGC5 PORTD MASK SIM SCGC5 PORTE MASK Master General Purpose Control Register Set mux to LCD analog operation After RESET these register are configured as 0 but indicated here for reference PORTB PCRO PORT PCR MUX 0 LCD_PO PORTB PCR1 PORT PCR MUX 0 LCD P1 PORTB PCR2 PORT PCR MUX 0 LCD P2 Complete for all used pins Configure NVIC for SLCD interrupt SLCD interrupt vector 102 NVICICPR2 1 22 Clear any pending interrupts on LCD NVICISER2 1 22 Enable interrupts from LCD interrupt SLCD clock gate on SIM SCGC3 SIM SCGC3 SLCD MASK Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 157 Demonstration code Digable LCD LCD GCR amp LCD GCR LCDEN MASK Configure LCD Control Register LCD GCR LCD GCR RVEN MASK LCD GCR RVTRIM 8 0 15 LCD GCR CPSEL MASK LCD GCR HREFSEL MASK LCD GCR LADJ 3 0 3 mBIT18
161. ns to that mode after VLPR is exited In VLPR mode the system clock dividers cannot be changed These dividers should be configured when the MCG is in BLPI mode before the MCU power mode is changed to VLPR 4 1 3 2 1 Code example and explanation Moving from PEE to BLPI first move from PEE to PBE MCG C1 MCG C1 CLKS 2 select external reference clock as MCG OUT Wait for clock status bits to update indicating clock has switched while MCG S amp MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x2 now move to FBE mode make sure the FRDIV is configured to keep the FLL reference within spec MCG C1 amp MCG C1 FRDIV MASK clear FRDIV field MCG C1 MCG C1 FRDIV 3 set FLL ref divider to 256 MCG C6 amp MCG C6 PLLS MASK clear PLLS to select the FLL while MCG S amp MCG S PLLST MASK Wait for PLLST status bit to clear to indicate switch to FLL output now move to FBI mode MCG C2 MCG C2 IRCS MASK set the IRCS bit to select the fast IRC set CLKS to 1 to select the internal reference clock keep FRDIV at existing value to keep FLL ref clock in spec set IREFS to 1 to select internal reference clock MCG C1 MCG C1 CLKS 1 MCG C1 FRDIV 3 MCG C1 IREFS MASK wait for internal reference to be selected Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 47 Clocking while MCG S MCG S IREFST MASK wait for fast inte
162. ntroller operates in parallel to the core performing data transfers that would otherwise have been handled by the CPU This results in reduced CPU loading and a corresponding increase in system performance Figure 7 1 illustrates the functionality provided by a DMA controller Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 67 eDMA Source e g RAM DMA Transfer request DMA controller OxDSS9A AA A DMA mads soume data DMA write source data to the destin atio Destination eg SPI TX Register Figure 7 1 DMA operational overview The Kinetis family features an enhanced Direct Memory Access eDMA controller for data movement The eDMA controller of the Kinetis family contains a 16 bit data buffer as temporary storage see Figure 7 1 Because Kinetis is a crossbar based architecture the CPU is the primary bus master hooked on the MO and M1 master port The eDMA is connected to the M2 master port of the crossbar switch Therefore the CPU and eDMA can access different slave ports simultaneously With this multi master architecture the system can make the maximum usage of the eDMA feature Figure 7 2 shows the basic architecture of the Kinetis family A specialized device may have differences refer to the device specific reference manual for details Kinetis Quick Reference User Guide Rev 2 08 2012 68 Freescale Semiconductor Inc Chapter 7 Enhanced
163. or Inc ETT Chapter 5 Power Management Controller PMC MODECTL the system when its interrupt flag is set To do this we need to enable the RTC module to cause an interrupt and then allow that interrupt to cause a wakeup To enable the RTC to cause a wakeup the corresponding module wakeup bits must be set LLWU ME LLWU ME WUME5_MASK enable the RTC to wake up from low power modes Other modules have to be enabled in the same way The table in Mode transition requirements identifies the wakeup enable bit that must be set for each module by the number of the bit 5 3 2 2 Pin wakeup To configure a pin to wakeup the MCU from the low power modes requires a study of the port configuration register controls and the GPIO functionality The PCR registers select the multiplex selection the pull enable function and the interrupt edge selection If we want to initialize the first wakeup pin PTE1 as an LLWU wakeup enabled pin we need to 1 Initialize the PCR for PTEI 2 Make sure the pin is an input 3 Enable PTE as a valid wakeup source in the LLWU The code for this is below This would need to be done for each of the pins you want to enable as wakeup sources PORTE PCR1 PORT PCR ISF MASK clear Flag if there PORT PCR MUX 01 GPIO PORT PCR IRQC OxOA falling edge enable PORT PCR PE MASK Pull enable PORT PCR PS MASK pull up enable GPIOE POER amp OxFFFFFFFD set Port El as input LLWU PE1 LL
164. or its GPIO function PORTA _PCR4 PORT PCR MUX 0x1 GPIO is alt function for this pin Configure the PTA4 pin for rising edge interrupts PORTA PCR4 PORT PCR IRQC 0x9 Initialize the NVIC to enable the specified IRQ enable irq 87 NOTE To save space the enable irq function is not shown See the interrupts section for details on how to enable the IRQ Also to save space the interrupt service routine is not shown 1 1 4 2 Enable UART for terminal communication See in this document chapter 11 Universal Asynchronous Receiver and Transmitter UART Module Kinetis Quick Reference User Guide Rev 2 08 2012 18 Freescale Semiconductor Inc Chapter 1 General System Setup Software Considerations 1 1 4 2 7 Jump to start of main function for application Jump to main process main Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 19 Software considerations Kinetis Quick Reference User Guide Rev 2 08 2012 20 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations 2 1 Hardware considerations 2 1 1 Overview This chapter will outline the best practices for hardware design when using the Kinetis MCUs The designer must consider numerous aspects when creating the system so that performance cost and quality meet the end user expectations Performance usually implies high speed digital signalling but it
165. or periodically polling the peripheral source status to control the transfer schedule or for periodical transferring Figure 7 4 shows the relationship between the PIT periodic trigger peripheral transfer source request and the transfer activation PIT trigger Perphe ral Request Channel Acted Figure 7 4 PIT gated transfer activation The hardware provides ten always enabled request sources that can be used in periodic trigger mode These permit transfers to be initiated based only on the PIT This is shown in Figure 7 5 PIT trigger Perpherial Request fa ways mb led Channel Ac lived Figure 7 5 PIT only transfer activation 7 1 2 3 Multiple transfer requests Only one channel can actively perform a transfer To manage multiple pending transfer requests the eDMA controller offers channel prioritization Fixed priority or round robin priority can be selected In the fixed priority scheme each channel is assigned a priority level When multiple requests are pending the channel with the highest priority level performs its transfer first By default fixed priority arbitration is implemented with each channel being assigned a priority level equal to its channel number Higher priority channels can preempt lower priority channels Preemption occurs when a channel is performing a transfer while a Kinetis
166. or the desired time interval Kinetis Quick Reference User Guide Rev 2 08 2012 74 Freescale Semiconductor Inc EE Chapter 7 Enhanced Direct Memory Access eDMA Controller The command data of the AD module must be prepared according to the definition of the AD command register before starting the DMA transfer enable PIT1 Each channel in this example transfers data to or from the static address 32 bit wide command or result register respectively Therefore it is necessary to restore the address pointers in the TCD when the major or minor transfer loop is complete This example has no table of data to transfer making only a single minor loop necessary to complete a major loop The source and destination addresses are therefore restored on completion of the major loop The TCD configuration for channels 0 and 1 is Configure DMA Channel 0 TCD EDMAC TCDO WO EDMAC SADDR 0x4003B010 Source Address AD Result Register EDMAC TCDO W1 0 EDMAC_SMOD 0x0 Source Modulo feature disabled EDMAC SSIZE 0x2 Source Size 0x2 gt 32 bit transfers EDMAC DMOD 0xO Destination Modulo feature disabled EDMAC DSIZE 0x2 Destination Size 0x2 32 bit transfers EDMAC SOFF 0x0 Source addr offset 0x0 do not increment DMAC TCDO W2 EDMAC NBYTES 0x4 Transfer 4 bytes per channel activation DMAC TCDO W3 EDMAC SLAST 0x0 Do not adjust SADDR upon channel completion DMAC TCDO W4
167. ound debug mode enable bit NULL CALLBACK pointer to callback function Once defined the structure pointer 1asnsspconrig is passed to the SSD functions for use during flash operations The size of D Flash block and the EEE block are initialized to 0 but will be updated during the r1asn1nic function which determines the D Flash and EEE block sizes by reading the D Flash IFR A return code is passed back to the calling function to indicate the success or failure of the API execution Upon successful completion the passing value FTFL OK assigned to value 0x0 is returned BORK RR KR KR RK ke KR RK KR KK RK RRR A FlashInit ESE returnCode pFlashInit amp flashSSDConfig if FTFL OK returnCode ErrorTrap returnCode Erasing a sector The following example illustrates how to erase a sector in program flash BORK RRR KK RK RR KR RK KR RR KK RR RRR KR RR RRR RR RR RR RR ke ke ke ke KK k k FlashEraseSector EEES Erase the last sector of PFLASH size FTFL SECTOR SIZE destination PFLASH BLOCK BASE PBLOCK SIZE size returnCode pFlashEraseSector amp flashSSDConfig destination size pFlashCommandSequence Kinetis Quick Reference User Guide Rev 2 08 2012 80 Freescale Semiconductor Inc SESS ee EA AAA Chapter 8 Using the Flash Standard Software Drivers if FTFL_OK returnCode ErrorTrap returnCode On Kinetis a sector is defined as 2 KB 0x800
168. pins of the QFP package This allows room for placement and routing of the crystal or resonator on the top layer close to the MCU The feedback resistor and load capacitors if needed can be placed on the top layer as well See Figure 2 3 Figure 2 4 and Figure 2 5 Note that the low power modes of this oscillator do not require a feedback resistor and may not require external load capacitors Check the device specific reference manual for details This makes it as simple as possible since only one component has to be placed and routed Low power oscillators are more susceptible to interference by system generated noise so the guidelines for crystal routing are important The crystal or resonator should be located close to the MCU No signals of any kind should be routed on the layer directly below the crystal A ground plane on the layer directly below the crystal is recommended A guard ring should be placed around the crystal and its load components to protect it from crosstalk from adjacent signals on the mounting layer This guard ring can originate from the VSS pin adjacent to the crystal pins Note that the guard ring and load capacitors is connected to the ground plane in Figure 2 4 and Figure 2 5 Kinetis Quick Reference User Guide Rev 2 08 2012 26 Freescale Semiconductor Inc Chapter 2 General System Setup Hardware Considerations R2 XTAL EXTAL Figure 2 3 Typical crystal circuit Kinetis Quick Reference User
169. r module from http freescale com twr k40x256 and http freescale com twr k60n5 12 2 Unzip the KINETIS512_SC zip file into any directory Go to kinetis sc build iar to see all the different projects available 4 The next section describes running the basic Hello World example but the same instructions can be used with other projects as well Oo A 6 Running the Hello World demo 1 Open IAR and go to File gt Open gt Workspace in the menu bar 2 Open the hello_world eww workspace at kinetis sc build iar hello_world Kinetis Quick Reference User Guide Rev 2 08 2012 192 Freescale Semiconductor Inc 3 4 Appendix A How to Load QRUG Examples The workspace that opens up contains a Hello World project for both TWR K40X256 and TWR K60N512 There are many different RAM and flash combinations available in the Kinetis family which this project supports However for the processor on your tower board you should choose one of the targets below to maximize the memory space that the linker makes available for your chip TWR K40X256 RAM_64KB FLASH_256KB_PFLASH_256KB_DFLASH TWR K60N512 e RAM I28KB FLASH 512KB PFLASH Select the project and configuration you would like to run by choosing the project from the drop down box that is circled in red You may also right click on a project and select Set as Active To start select the flash target appropriate for your board as listed in the previou
170. r than one shot mode PDB SC PDBEN MASK PDB enabled PDB SC PDBIE MASK PDB Interrupt Enable PDB SC PRESCALER 0x5 Slow down the period of the PDB for testing PDB SC TRGSEL Oxf Trigger source is Software Trigger to be invoked in this file PDB SC MULT 2 Multiplication factor 20 for the prescale divider for the counter clock PDB SC LDOK MASK Need to ok the loading or it will not load certain registers triggered at this time the software trigger 19 2 1 4 Determine ADC configuration PDB SC SWTRIG MASK is not Set up the initial ADC default configuration This configuration is set into a structure where it can be reused as required prior to and after calibration for either ADC Master Adc Config Master Adc Config Master Adc Config Master Adc Config Master Adc Config Master Adc Config Master Adc Config Master Adc Config Master Adc Config CONFIG1 CONFIG2 ADLPC NORMAL ADC CFG1 ADIV ADIV 4 ADLSMP LONG ADC CFG1 MODE MODE 16 ADC CFG1 ADICI MUXSEL ADCA ADACKEN DISABLED ADHSC HISPEED ADC CFG2 ADLSTS ADLSTS 20 COMPARE1 0x1234u COMPARE2 0x5678u STATUS2 ADTRG HW STATUS3 PGA STATUS1A STATUS1B ACFE DISABLED ACFGT GREATER ACREN ENABLED DMAEN DISABLED ADC SC2 REFSEL REFSEL EXT CAL OFF ADCO SINGLE AVGE ENABLED ADC SC3 AVGS AVGS 32 PGAEN DISABLED PGACHP NOCHOP PGALP NORMAL ADC PGA PGAG PGAG 64
171. r the pending interrupts from NVICCPR2 Example LPTMR BIT 85 mod 32 LPTMR BIT 21 4 At this point the interrupt for the LPTMR can be configured NVICICPR2 1 21 Clear any pending interrupts on LPTMR NVICISER2 1 21 Enable interrupts from LPTMR module 5 Next set the interrupt priority level This is application dependent On Kinetis MCUs there are 16 different priority levels To set the priority write to the NVICIPxx register the xx represents the IRQ number in this example NVICIP85 Note the most significant nibble is used to set up the priority the lower nibble is reserved and reads as zero The LPTMR example sets the priority to 3 NVICIP85 0x30 Set Priority 3 to the LPTMR module 6 After the NVIC registers are set up finish the peripheral configuration that must enable the interrupt 7 In the ISR clear the peripheral interrupt flag to avoid re entrance For this example void vfnLPTMR ISR void LPTMRO CSR LPTMR CSR TCF MASK Clear LPTMR Compare flag ISR code goes here Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 39 ed NVIC 3 1 2 2 Relocating the vector table Some applications need the vector table to be located in RAM For example in an RTOS implementation the vector table needs to be in RAM this allows the Kernel to install ISRs by modifying the vector table during runtime The NVIC provides a simple way to reallocate the v
172. re to provide up to 30 pF in 2 pF increments for each of the EXTAL and XTAL pins This provides an effective series capacitive load of up to 15 pF The parasitic capacitance of the PCB should also be included in the calculation of the total crystal load The combination of these two values will often mean that no external load capacitors are required If either of the main oscillator pins are not being used they may be left unconnected in their default reset configuration or may be used as general purpose outputs not inputs 4 1 5 Layout guidelines for general routing and placement Use the following general routing and placement guidelines when laying out a new design These guidelines will help to minimize electromagnetic compatibility EMC problems To minimize parasitic elements surface mount components should be used where possible All components should be placed as close to the MCU as possible f external load capacitors are required they should use a common ground connection shared in the center If the crystal or resonator has a ground connection it should be connected to the common ground of the load capacitors Where possible keep high speed IO signals as far from the EXTAL and XTAL signals as possible do not route signals under oscillator components on same layer or layer below select the functions of pins close to EXTAL and XTAL to have minimal switching to reduce injected noise 4 1 6 References Th
173. registers RO R12 to zero This is done with the move instruction Kinetis Quick Reference User Guide Rev 2 08 2012 16 Freescale Semiconductor Inc eee MM Chapter 1 General System Setup Software Considerations MOV r0 0 Initialize the GPRs MOV r1 0 MOV r2 H0 MOV r3 H0 MOV r4 0 MOV r5 0 MOV r6 0 MOV r7 0 MOV r8 0 MOV r9 0 MOV r10 0 MOV r11 0 MOV r12 0 1 1 4 1 1 1 Unmask interrupts at ARM core CPSIE i Unmask interrupts 1 1 4 1 1 2 Branch to start of C initialization code import start BL start call the C code 1 1 4 2 Startup routines These routines are C source code found in the files start c and sysinit c This code provides general system initialization that may be adapted depending on the application 1 1 4 2 1 Disable watchdog For code development and debugging it is best to disable the watchdog This requires unlocking the watchdog first Keep in mind that there are timing requirements for the execution of the unlock steps The two step unlock sequences must execute within 20 clock cycles of each other Therefore interrupts must be disabled and single step debugging cannot be done during this section disable all interrupts asm CPSID i Write 0xC520 to the unlock register WDOG UNLOCK 0xC520 Followed by 0xD928 to complete the unlock WDOG UNLOCK 0xD928 enable all interrupts asm CPSIE i Clear the WDOGEN bit to disable the watchdo
174. rnal reference to be selected while MCG S MCG S IRCST MASK wait for clock to switch to IRC while MCG S MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x1 now move to BLPI MCG C2 MCG C2 LP MASK set the LP bit to enter BLPI set up the SIM clock dividers BEFORE switching to VLPR to ensure the System clock speeds are in spec MCGCLKOUT 2 MHz in BLPI mode core 2 MHz bus 2 MHz flexbus 2 MHz flash 1 MHz SIM CLKDIV1 SIM CLKDIV1 OUTDIV1 0 SIM CLKDIV1 OUTDIV2 0 SIM CLKDIV1 OUTDIV3 0 SIM CLKDIV1 OUTDIV4 1 Now that MCGCLKOUT is at 2 MHz the MCU VLPR power mode may be selected Refer to the power management controller for details on this When the MCU transitions back to normal run mode the MCG will still be configured in BLPI mode The MCG is then configured in PLL engaged external mode by means of software as follows Moving from BLPI to PEE first move to FBI MCG C2 amp MCG C2 LP MASK clear the LP bit to exit BLPI move to FBE clear IREFS to select the external ref clock set CLKS 2 to select the ext ref clock as clk source it is assumed the oscillator parameters in MCG C2 have not been changed MCG C1 MCG C1 CLKS 2 MCG C1 FRDIV 3 wait for the oscillator to initialize again while MCG S amp MCG S OSCINIT MASK wait for Reference clock to switch to external reference while MCG S amp MCG S IREFST MASK wait for MCGOUT to swi
175. rode is configured with bits 16 to 19 5 Configure the thresholds THRESHLDXx These registers configure each the low and high 16 bit thresholds for the 16 electrodes The low 16 bits configure the high threshold and the high 16 bits configure the low threshold The high threshold sets the OUTRGE bit when the capacitance measurement goes above that value and the low threshold sets it when the capacitance goes below that value The most common use case is to use these as an alarm for drastic changes to the capacitance or to wake up the module from low power mode 6 Enable the TSI module TSIEN Enabling the module is relinquished to the end of the configuration after everything else is set 18 4 4 Configuration Example The following example uses the four electrodes from the Kinetis Tower board The application detects touches These touches turn on and off the LEDs below the electrodes Baseline is not tracked but measured initially and assumed to be constant Baseline tracking is critical in applications where the environment is susceptible to change Because this example is intended to be simple baseline tracking has not been implemented Kinetis Quick Reference User Guide Rev 2 08 2012 166 Freescale Semiconductor Inc SSS UELUT Chapter 18 Touch Sense Input TSI Module The most relevant part of initialization is enabling the module after configuration In this application after initial configuration th
176. rogrammable upper and lower threshold for each electrode e TSI interrupt end of scan Interrupt after scanning all electrodes once Electrode short Detects when electrode is shorted to Vpp or Vss e Conversion overrun If the conversion time of electrodes goes above scan period NOTE This feature will be available in the second mask of the TSI These features enable the following special characteristics Noexternal components needed the pin can be directly connected to an electrode a series resistor can be used to limit the current that might flow into the pin in case of an ESD event but it is not necessary e Single pin per electrode architecture Operation of 16 electrodes on run modes and 1 wake up electrode in all low power modes Automatic touch event interrupt from any of the electrodes External and reference oscillator subject to the same temperature variation so calibration thresholds are compensated no touch detection variations over temperature range Number of scan can be configured for faster response time or for higher resolution Current sources are far more robust than external weak pull ups used in traditional GPIO measurement methods 18 4 TSI configuration All use cases for the TSI module refer to using capacitive electrodes as touch sensors For further information on using touch sensors and HMI see application notes titled How to Implement a Human Machine Interface Using the Touch Sensing
177. routing and placement guidelines when laying out a new design These guidelines will help to minimize signal quality and electromagnetic interference EMI problems To minimize parasitic elements surface mount components must be used wherever possible All components should be placed as close to the IC as possible The components should be placed closest to the IC in the following order f it is required the feedback resistor Rf should be placed first If it is required the series resistor Rs should be placed next f external load capacitors are required they should be placed third nput sources such as sensor should be placed last f external load capacitors are required they should use a common ground connection shared in the center f input source has a ground connection it should be connected to the common ground of the load capacitors Where possible Keep high speed I O signals as far from the OPMAP signals as possible Select the functions of pins close to the OPAMP terminals to have minimal switching to reduce injected noise 20 5 3 OPAMP demo with DAC This lab demonstrates how to use the selectable OPAMP internal gain and adjust voltage offset for proper amplified output signal The input signal is generated from the integrated on chip 12 bit DAC module 1 This project is named as analog labs eww 2 In analog lab c comment the code as following v nLab1 v nLab2 vfnLab3 3 I
178. rovide the instantaneous energy demanded by the high speed digital circuits Power supply bypass capacitors must be placed close to the MCU supply pins The basic concept is that the bypass capacitor provides the instantaneous current for every logic transition within the MCU Fortunately each Kinetis MCU has a low voltage internal regulator for the MCU core logic so the abrupt current demands of the internal high speed logic are not as critical However external signals demand energy from the power rails when they transition from one logic level to the other The bypass capacitors provide the local filtering so that the effects of the external pin transitions are not reflected back to the power supply which causes RF emissions The basic rule of placing bypass capacitors as close as possible to the MCU is still appropriate The idea is to minimize the loop created by the capacitor between the VDD and VSS pins The implementation of this rule depends on the number of mounting layers how the supplies are routed and the physical size of the capacitors Number of mounting layers PCBs with components mounted on the top side only will have a significant limitation on how close the bypass caps can be located due to the number of components that require space PCBs that have components mounted on both sides of the PCB allow closer placement of the bypass capacitors e Supply routing With the Ball Grid Array BGA package all of the VDD VSS p
179. rt circuit or a substantial change in the reference capacitance that indicates a fault Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 153 Power supply 17 2 Power supply Table 17 1 shows power supply modes and suggests the use according to the environment and contrast control required Table 17 1 SLCD power supply options Contrast Control Configura tion LCD Power Supply mode LCD Noisy Nominal Environm Voltage ent Advantages Disadvantages VLL1 to VIREG Voltage 3 V Not Most VLLx voltages are fixed Not recommend for internal regulator recommen recommen over a width range of noisy applications VIREG 1 0 V ded ded VDD input voltage The HREFSEL 0 Charge regulator voltage can pump generates VLL2 be trimmed RVTRIM and VLL3 for software contrast control VLL1 to VIREG 5V Not Most VLLx voltages are fixed Not recommend for HREFSEL 1 VIREG recommen recommen over a width range of noisy applications 1 67V Charge pump ded ded VDD input voltage The generates VLL2 and regulator voltage can VLL3 be trimmed RVTRIM for software contrast control VLL3 to VDD internal 3 V Most Not This configuration can Contrast Control is not connection Charge recommen recommen be suitable for noisy possible pump generates VLL2 ded ded application and VLL1 VLL3 driven externally 3 V Most Recomme Allows external contrast This configuration is no
180. s are enabled PORTB PCRO PORT PCR MUX 4 GPIO RMIIO MDIO MIIO MDIO PORTB PCR1 PORT PCR MUX 4 GPIO RMIIO MDC MIIO MDC if configUSE MII MODE PORTA PCR14 PORT PCR MUX 4 RMIIO CRS DV MIIO RXDV Kinetis Quick Reference User Guide Rev 2 08 2012 114 Freescale Semiconductor Inc PORTA PCR5 PORTA PCR12 PORTA PCR13 PORTA PCR15 PORTA PCR16 PORTA PCR17 PORTA PCR11 PORTA PCR25 PORTA PCR9 PORTA PCR10 PORTA PCR28 PORTA PCR24 PORTA PCR26 PORTA PCR27 PORTA PCR29 else PORTA PCR14 PORTA PCR5 PORTA PCR12 PORTA PCR13 PORTA PCR15 PORTA PCR16 PORTA PCR17 Hendif PORT_PCR_MUX PORT_PCR_MUX PORT_PCR_MUX PORT_PCR_MUX PORT_PCR_MUX PORT_PCR_MUX RMIIO RXER MIIO RXER RMIIO RXD1 MIIO RXD1 RMIIO RXDO MIIO RXDO RMIIO TXEN MIIO TXEN RMIIO TXDO MIIO TXDO RMIIO TXD1 MIIO TXD1 4 4 4 4 4 4 4 PORT PCR MUX 4 M 4 i 4 4 4 4 4 PORT PCR MUX 4 MIIO_RXCLK IIO TXCLK PORT PCR MUX 4 MIIO RXD3 PORT PCR MUX 4 MIIO RXD2 PORT PCR MUX 4 MIIO TXER PORT PCR MUX 4 MIIO TXD2 PORT PCR MUX 4 MIIO TXD3 PORT PCR MUX 4 MIIO CRS PORT PCR MUX 4 MIIO COL PORT PCR MUX 4 RMIIO CRS DV MIIO RXDV PORT PCR MUX 4 RMIIO RXER MIIO RXER PORT PCR MUX 4 RMIIO RXD1 MIIO RXD1 PORT PCR MUX 4 RMIIO RXDO MIIO RXDO PORT PCR MUX 4 RMIIO TXEN MIIO TXEN PORT PCR MUX 4 RMIIO TXDO MIIO TXDO PORT PCR MUX 4 RMIIO TXD1 MIIO TXD1 Can we
181. s held most modules are disabled 10 Very low leakage stop I VLLS1 Lowest Power Mode ARM core enters SleepDeep Mode NVIC is disabled LLWU is used to wake up peripheral clocks are stopped All SRAM is powered down and I O states held most modules are disabled only two 32 byte register file modules retained and I O states held The modules available in each of the power modes is a described in a table Please see Module operation in low power modes for the details of the module operations in the each of the low power modes 5 2 1 2 Features Mode Control controls entry into and exit from each of the power modes 5 2 2 Configuration examples How you decide which modes to use in your solution is an exercise in matching the requirements of your system and selecting which modules are needed during each mode of the operation for your application The best way to explain would be to work through an example For example consider the case of a battery operated human interface device that requires a real time clock timebase It will wake up every second update the time of day and check the conditions of several sensors Then it will take action based upon the state and when requested perform high levels of computation to control the operation of a device After reviewing the power modes table in Module operation in low power modes you should be able to identify which of the modules are functioning in each of the low power modes At
182. s step Workspace hello world k4Q tower FLASH_256KB_PFLASH_256KB_DFLASH SR i Files El 8 hello world OD hella world k60 tower FLASH 512KB PF E T Cj hello world k40 tower FLASH 256k Make Rebuild All Clean Add b Remove Source Code Control gt File Properties Set as Active The selected project will appear in bold font To ensure a fresh start clean the project first by right clicking on the project name and selecting Clean Compile the project by clicking the Make icon or right click on the project and select Make Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 193 9 In the build dialog box at the bottom you will see any errors or warnings If the compilation was successful you will see something like the image below if there are no errors there may be some warnings depending on the code k60_tower_demo out Performing Post Build Action Total number of errors 0 Total number of warnings 0 Build 10 Now download the code to the board and start the debugger by pressing the Download and Debug button 11 The code will download into RAM or flash depending on the project settings and the debugger screen will appear and pause at the first instruction Hit the Go button to start running z ETM SWO X Lan dama c esti 12 After you have selected Go the software will print out so
183. s the data and then terminates the bus cycle FB CLK FlexBus clock the system provides a dedicated clock source to the FlexBus module s external FB CLK Its clock frequency is derived from a divider SIM CLKDIVI OUTDIV3 of the MCGOUTCLK 11 1 1 2 2 Address and data bus multiplexing Figure 11 1 shows the supported combinations of address and data bus widths The bus sends the address at the first stage light blue and the data at the second stage green Kinetis Quick Reference User Guide Rev 2 08 2012 98 Freescale Semiconductor Inc Chapter 11 Flexbus Module FB_AD FB_AD FB_AD FB_AD 31 24 23 16 15 8 7 0 Address lt p 32 bit port Data Address 16 bit port 8 bit port By Address phase B Data phase Figure 11 1 FlexBus multiplexed operating modes 11 1 1 2 3 Modes of Operation Table 11 1 and Table 11 2 show the assignment of FlexBus signals available for the Kinetis MCUs depending on the package Non LCD devices are those without a segment LCD peripheral Table 11 1 FlexBus signals on non LCD devices Packa 48 ge pin Signal A 29 16 AD 31 0 AD 31 24 5 CS AD 19 0 4 CS AD 19 0 2 CS AD 17 0 2 CS N A N A S AD 31 0 CS 5 CS 5 0 0 Muxed Up to 32 Up to 32 Up to 21 Up to 20 Up to 20 Up to 18 N A N A mode jaddress Upto address Upto address Upto address Upto address Upto address Up to 32 data lines 32 data lines 16 data lines
184. section will demonstrate how to use the Low Leakage Wakeup Unit LLWU The LLWU is responsible for selecting and enabling the sources of exit from all of the low power modes of the MCU This module works in conjunction with the PMC and the MCU to wake the MCU up 5 3 1 1 Mode transitions There are particular requirements for exiting form each of the 10 power modes Please see Mode transition requirements for a table of the transition requirements for each of the modes of operation 5 3 1 2 Wakeup sources There are a possible 16 pin sources and up to 7 modules available as sources of wakeup Please see Source of wakeup pins and modules for a table of external pin wakeup and module wakeup sources 5 3 2 Configuration examples There are five 8 bit wakeup source enable registers for the pin and module source selection Three 8 bit wakeup flag registers to indicate which wakeup source was triggered and one 8 bit status and control register to control the digital filter enable for external pins and an acknowledge bit to allow certain peripherals and pads to release their held low leakage state 5 3 2 1 Module wakeup To configure a module to wakeup the MCU from one of the low power modes requires a study in the control and function of each of the modules capable of waking the MCU Since the RTC can be on in all low power mode we can configure the RTC to wake up Kinetis Quick Reference User Guide Rev 2 08 2012 58 Freescale Semiconduct
185. sed as the serial port to interface to HyperTerminal and CANI is used to interface to the CAN bus The HyperTerminal communication setup is Baud rate 115200 Data 8 bit Parity None Stop 1 bit Flow control none The example codes for SCI2CAN are available from the Freescale Web site www freescale com 16 2 1 FIlexCAN initialization Enable the clock to the FlexCAN module before accessing its registers The following steps are performed before initializing the FlexCAN module 1 Initialize MCG and OSC to enable PLL and ERCLK 2 Initialize the clock gating in SIM to enable clocks to the FlexCAN module s and the corresponding ports whose pins are to function as FlexCAN pins 3 Configure the corresponding port pins for FlexCAN through port control 16 2 1 1 Code example and explanation The following code snippet shows how to enable ERCLK clock Must enable ERCLK OSC CR OSC CR ERCLKEN MASK Clock gating code for all ports and FlexCAN Enable clocks to all ports for pin muxing configuration later SIM SCGC5 SIM SCGC5 PORTA MASK SIM SCGC5 PORTB MASK SIM SCGC5 PORTC MASK SIM SCGC5 PORTD MASK SIM SCGC5 PORTE MASK if isCANO SIM SCGC6 SIM SCGC6 FLEXCANO MASK else SIM SCGC3 SIM SCGC3 FLEXCAN1 MASK Configure NVIC to enable corresponding interrupts for FlexCAN Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 147 Configuration examples
186. sing the hold the user must re initialize the I O to the pre low power mode entry state so that unwanted transitions on the I O do not occur when the hold is released if LLWU CS amp LLWU CS ACKISO MASK 1 RE INITIALIZE MODULES and PORT OUTPUTS HERE LLWU CS LLWU CS ACKISO MASK The RTC may be powered by a separate power source and therefore would not need to re initialized A simple check of the state of the RTC registers to see if they are already enabled would work Kinetis Quick Reference User Guide Rev 2 08 2012 60 Freescale Semiconductor Inc EEY Chapter 5 Power Management Controller PMC MODECTL 5 4 Module operation in low power modes Table 5 1 Module operation in low power modes EzPort Disabled Disabled Disabled Disabled Disabled Disabled SDHC Wakeup FF FF Wakeup Static OFF GPIO Wakeup FF FF Wakeup Static pins OFF Pins Latched Latched FlexBus Static FF FF Static Static OFF CRC Static FF FF Static Static OFF RNGB Static FF Static Static Static OFF CMT Static FF FF Static Static OFF NVIC Static FF FF Static Static OFF Mode Controller FF FF FF FF FF FF LLWU Static Static Static Static FF FF Regulator ON Low Pwr Low Pwr Low Pwr Low Pwr Low Pwr LVD ON Disabled Disabled Disabled Disabled Disabled LPO KHz ON ON ON ON ON ON Sys OSC ERCLK optional ERCLK 4 MHz ERCLK 4 MHz ERCLK 4 MHz Limited to low Limited to low range ran
187. smitter UART Module else if uartch UART4 BASE PTR SIM _SCGC1 SIM _SCGC1_UART4 MASK else SIM _SCGC1 SIM_SCGC1_UART5 MASK Make sure that the transmitter and receiver are disabled while we change settings UART C2 REG uartch amp UART C2 TE MASK UART C2 RE MASK Configure the UART for 8 bit mode no parity We need all default settings so entire register is cleared UART C1 REG uartch 0 Calculate baud settings ubd uint16 sysclk 1000 baud 16 Save off the current value of the UARTx BDH except for the SBR temp UART BDH REG uartch amp UART BDH SBR Ox1F UART BDH REG uartch UART BDL REG uartch temp UART BDH SBR ubd amp OxlF00 gt gt 8 uint8 ubd amp UART BDL SBR MASK Determine if a fractional divider is needed to get closer to the baud rate brfa sysclk 32000 baud 16 ubd 32 Save off the current value of the UARTx C4 register except for the BRFA temp UART C4 REG uartch amp UART C4 BRFA Ox1F UART C4 REG uartch temp UART C4 BRFA brfa Enable receiver and transmitter UART C2 REG uartch UART C2 TE MASK UART C2 RE MASK The initialization above can be simplified to the following steps L 2 Disable the transmitter and receiver This step is included to make sure that the Enable the UART pins by configuring the appropriate PORTx PCRn registers not shown in the cod
188. t charge pump enabled recommen nded control suitable for 5 V LCD Charge pump ded generates VLL2 and VLL1 VDD must be 3V VLL3 driven externally 3 V Most Recomme Allows external contrast Requires an external voltage divider recommen nded control Because the power supply and it enabled Resistor bias ded Charge Pump is must be a variable network generates disabled power Contrast control is VLL2 and VLL1 VLL3 consumption is reduced required Not suitable connected to external for 5 V LCD voltage 3 V Charge pump is disabled VLL2 to VDD internal 3 V Not VDD voltage must be in connection VDD 2 0 recommen an appropriate range V Charge pump ded for a 3 V LCD generates VLL3 and VLL1 VLL2 to VDD internal 5 V Not VDD voltage must be in connection VDD 3 33 recommen an appropriate range V Charge pump ded for a 5 V LCD generates VLL3 and VLL1 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc SS________Ah y Chapter 17 Segment LCD Controller 17 3 Low power modes The SLCD module can function in any low power mode available in the Kinetis family RUN VLPR STOP VLPW VLPS LLS VLLSx NOTE End of frame wakeup is not supported in the LLS and VLLSx modes 17 4 Clock source The SLCD module supports four different clock sources See the Table 17 2 and Figure 17 1Figure 17 1 below SOPT1_OSC32KSEL CD_SOURCE Internal Reference Slow Clock 32KHz LC
189. t rotate the potentiometer counterclockwise until such waveform is observed Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 187 User case examples A lhe QQ Channels 45000 40000 o 2 S n a E 1 A NIA IA JA N H ii Fi HHI ir OIEA HOMO AA 0 12 From the TWR K53N512 board press the IRQO button to increase the gain Press the SW2 button to decrease the gain The amplitude of the sine wave will be adjusted accordingly 13 Stop the debugger session p ttu c C amp CH CZ C 14 In lab3 c find the comment and uncomment the following code as below v nOPAMPConfig LAB3a Non inverting OPAMPO positive selects DACO negative selects DAC1 v nOPAMPConfig LAB3b Inverting OPAMPO positive selects DAC1 negative selects DACO vfnOPAMPConfig LAB3c Non inverting OPAMPO positive selects DACO negative selects DAC1 15 Compile download and run the project 16 Rotate the potentiometer in either direction to see the sine wave DC level being adjusted This is an example of offset voltage adjustment using OPAMP Kinetis Quick Reference User Guide Rev 2 08 2012 188 Freescale Semiconductor Inc gu S E gt E E E Eoea u _ mhii_ __ MM MM M Chapter 20 Using OPAMP for Kinetis Microcontrollers 17 Now keep on increasing the gain of the OPAMP see step 12 and the output of the OPAMP will eventually be saturated
190. t complies with the USB 2 0 definition of a host or hub A standard downstream port expects a downstream device to draw less than a 2 5 mA average when disconnected or suspended up to 100 mA maximum when connected and not suspended up to 500 mA maximum if configured and not suspended Charging Downstream Port A charging downstream port is a downstream port on a device that complies with the USB 2 0 definition of a host or a hub It can supply a maximum of 1 5 A to a low full speed port and 900 mA to a high speed port Dedicated Charger A dedicated charging port is a downstream port on a device that outputs power through a USB connector but is not capable of enumerating a downstream device A dedicated charging port is able to supply a maximum of 1 8 A A dedicated charging port is required to short the D line to the D line In other words the amount of current that the device is able to draw to charge the system batteries depends on the type of downstream port it is connected to 14 2 Module Configuration 14 2 1 Module dependencies The DCD module depends on other modules to operate correctly Clock Source Kinetis Quick Reference User Guide Rev 2 08 2012 126 Freescale Semiconductor Inc Ey Chapter 14 USB Device Charger Detection USBDCD Module The DCD module needs a 48 MHz clock This clock is the same as that applied to the USB module but the DCD has its own clock gating bit in the SIM SCGC6 register Make
191. t of a vehicle Cost effectiveness Required bandwidth The FlexCAN module is an advanced CAN protocol controller which is fully compliant with the CAN 2 0B specification It also provides Enhanced powerful message filtering mechanism Flexible message storage and transmission scheme Automatic response to remote frames Flexible transmit priority scheme Global timer synchronization Rich error indication Different low power modes Remote wakeup capability It enables real time communication over the CAN bus while minimizing processor intervention Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 145 Configuration examples 16 1 2 Features In the FlexCAN module each Mailbox MB is configurable as Rx or Tx supporting standard and extended messages Configuration of an MB begins the Transmit Process for a Tx MB or Receive Process for an Rx MB The Rx FIFO with six levels of MBs can be enabled when the CPU has slow response time to each received message The ID filter table element can be configured for the Rx FIFO to accept only wanted messages FlexCAN also supports Individual Rx Mask configured per Mailbox or per Rx FIFO ID filter table element With timer SYNC feature enabled global network time can be synchronized by a specific message When multiple messages are pending for transmission the highest priority message is selected to be transmitted first There are three
192. t osc CLKS 2 select the external clock source FRDIV 3 set the FLL ref divider to keep the ref clock in range even if FLL is not being used 8 MHz 256 31 25 kHz IREFS 0 select the external clock IRCLKEN 0 disable IRCLK can enable it if desired IREFSTEN 0 disable IRC in stop mode can keep it enabled in stop if desired MCG C1 MCG C1 CLKS 2 MCG C1 FRDIV 3 wait for oscillator to initialize while MCG S MCG S OSCINIT MASK wait for Reference clock to switch to external reference while MCG S amp MCG S IREFST MASK Wait for MCGOUT to switch over to the external reference clock while MCG S amp MCG S CLKST MASK gt gt MCG S CLKST SHIFT Ox2 Now configure the PLL and move to PBE mode set the PRDIV field to generate a 4 MHz reference clock 8 MHz 2 MCG C5 MCG C5 PRDIV 1 PRDIV 1 selects a divide by 2 set the VDIV field to 0 which is x24 giving 4 x 24 96 MHz the PLLS bit is set to enable the PLL the clock monitor is enabled CME 1 to cause a reset if crystal fails LOLIE can be optionally set to enable the loss of lock interrupt MCG C6 MCG C6 CME MASK MCG C6 PLLS MASK Kinetis Quick Reference User Guide Rev 2 08 2012 46 Freescale Semiconductor Inc p M A Chapter 4 Clocking System wait until the source of the PLLS clock has switched
193. tch over to the external reference clock while MCG S amp MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x2 configure PLL and system clock dividers as FEI to PEE example MCG C5 MCG C5 PRDIV 1 MCG C6 MCG C6 PLLS MASK while MCG S MCG S PLLST MASK while MCG S MCG S LOCK MASK configure the clock dividers back again before switching to the PLL to ensure the system clock speeds are in spec core PLL 96 MHz bus PLL 2 48 MHz flexbus PLL 2 48 MHz flash PLL 4 24 MHz SIM CLKDIV1 SIM CLKDIVI1 OUTDIV1 0 SIM CLKDIV1 OUTDIV2 1 SIM _CLKDIV1 OUTDIV3 1 SIM CLKDIV1 OUTDIV4 3 MCG C1 amp MCG C1 CLKS MASK while MCG S MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x3 4 1 3 3 Configuring the FLL with the RTC oscillator as a reference The MCG can generate all the system clocks using the FLL with the RTC oscillator being used as the reference for it This has the benefit that an accurate reference clock can be used without the cost of additional external components in an application where the RTC is already being used 4 1 3 3 1 Code example and explanation Using the RTC OSC as Ref Clk Configure and enable the RTC OSC select the load caps application dependent and the oscillator enable bit Kinetis Quick Reference User Guide Rev 2 08 2012 48 Freescale Semiconductor Inc p M9 Chapter 4 Clocking S
194. tered EZPCS 1 Single chip mode EZPCS 0 amp amp FOPT EZPORT_DIS 0 Single chip mode EZPCS 0 amp amp FOPT EZPORT_DIS 1 Ezport mode 10 1 1 2 Features The Ezport module has these features Implements a subset of SPI format supporting either of the following two modes CPOL 0 CPHA 0 or CPOL 1 CPHA 1 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 89 Using the EzPort module Able to read erase and program on chip flash memory Able to reset Kinetis allowing it to boot from flash memory after firmware updated 10 1 1 3 Command description When in Ezport mode Kinetis operates as a SPI slave and receives commands from an external SPI master and translates those commands to flash memory accesses Table 10 2 is a complete list of commands supported by the Ezport module Table 10 2 Ezport commands Command Description Code Address Dummy Data bytes bytes byte 0 0 0 WREN Write enable 0x06 WRDI Write disable 0x04 0 0 0 RDSR Read status register 0x05 0 0 1 READ Flash read data 0x03 3 0 1 FAST_READ Flash read data at high speed OxOb 3 1 1 SP Flash sector program 0x02 3 0 8 section SE Flash sector erase Oxd8 3 0 0 BE Flash bulk erase Oxc7 0 0 0 RESET Reset chip Oxb9 0 0 0 WRFCCOB Write FCCOB registers Oxba 0 0 12 FAST RDFCCOB Read FCCOB registers at high Oxbb 0 1 1 12 speed WRFLEXRAM Write FlexRAM O
195. ternally generated square wave as the reference for the on chip PLL An on chip divider allows an external clock to provide the reference clock to the PLL within the required range of 2 4 MHz The PLL provides the most accurate clock source for frequencies greater than can be generated by an external source In this example an 8 MHz crystal is used to generate a 96 MHz system clock The system clock dividers are set to allow the maximum system performance with this clock source The PLL frequency can be divided down to provide the USB clock of 48 MHz The MCG is configured to minimize PLL jitter maximum PLL frequency with the minimum multiplication factor 4 1 3 1 1 Code example and explanation If the internal load capacitors are being used they should be selected before enabling the oscillator Application specific 16 pF and 8 pF selected in this example OSC CR OSC CR SC16P MASK OSC CR SC8P MASK Enabling the oscillator for 8 MHz crystal RANGE 1 should be set to match the frequency of the crystal being used HGO 1 high gain is selected provides better noise immunity but does draw higher current EREFS 1 enable the external oscillator LP 0 low power mode not selected not actually part of osc setup IRCS 0 slow internal ref clock selected not actually part of osc setup MCG C2 MCG C2 RANGE 1 MCG C2 HGO MASK MCG C2 EREFS MASK Select ext oscillator reference divider and clear IREFS to start ex
196. the MCGOUTCLK The software needs to configure a stable clock This example configures 96 MHz of core frequency Example code Code Snippet int MRAM START ADDRESS 0x60000000 uint8 wdata8 0x00 uint8 rdata8 0x00 uintl6 wdatal6 0x00 uintl6 rdatal6 0x00 uint32 wdata32 0x00 uint32 rdata32 0x00 Set Base address FB CSARO MRAM START ADDRESS Enable CS signal FB CSMRO FB CSMR V MASK FB CSCRO FB CSCR BLS MASK right justified mode Kinetis Quick Reference User Guide Rev 2 08 2012 102 Freescale Semiconductor Inc FB CSCR PS 1 8 bit port FB CSCR AA MASK auto acknowledge FB CSCR ASET Ox1 assert chip select on second clock edge after address is asserted Chapter 11 Flexbus Module FB CSCR WS 0x1 1 wait state may need a wait state depending on the bus speed Set base address mask for 512 KB address space FB CSMRO FB CSMR BAM 0x7 Set BEO 1 to MRAM FB CSPMCR 0x02200000 Reference clock divided by 3 SIM CLKDIV1 amp SIM CLKDIV1 OUTDIV3 OxF SIM CLKDIV1 SIM CLKDIV1 OUTDIV3 0x3 Configure the pins needed to FlexBus Function this example uses low drive strength settings address Data PORTA PCR7 PORT PCR MUX 5 fb ad 18 PORTA PCR8 PORT PCR MUX 5 fb ad 17 PORTA PCR9 PORT PCR MUX 5 fb ad 16 PORTA PCR10 PORT PCR MUX 5 fb ad 15 PORTA PCR24 PORT PCR MUX 5
197. tialization transmit and receive sections The example uses the UART in a simple polled configuration but a description is provided to discuss how the UART could be used in interrupt mode or in conjunction with the DMA to help decrease CPU loading 12 3 1 UART initialization example The initialization code below can be used to configure the UART for 8 N 1 operation eight data bits no parity and one stop bit with interrupts and hardware flow control disabled The parameters passed in to this function are the UART channel to initialize uartch the module clock frequency for the UART in kHz sysclk and the desired baud rate for communication baud NOTE The UART modules are pinned out in multiple locations so the initialization function below doesn t know which UART pins to enable The desired UART pins should be enabled before calling this initialization function void uart init UART MemMapPtr uartch int sysclk int baud register uint16 ubd brfa uint8 temp Enable the clock to the selected UART if uartch UARTO BASE PTR SIM SCGC4 SIM SCGC4 UARTO MASK else if uartch UARTI1 BASE PTR SIM SCGC4 SIM SCGC4 UART1 MASK else if uartch UART2 BASE PTR SIM SCGC4 SIM SCGC4 UART2 MASK else if uartch UART3 BASE PTR SIM SCGC4 SIM SCGC4 UART3 MASK Kinetis Quick Reference User Guide Rev 2 08 2012 106 Freescale Semiconductor Inc Chapter 12 Universal Asynchronous Receiver and Tran
198. to prepare a Rx MB is Deactivate the rx MB for cpu write pFlexCANReg gt MB iMB CS LEXCAN MB CS CODE FLEXCAN MB CODE RX INACTIVE Write ID id2 id amp CAN MSG IDE MASK CAN MSG TYPE MASK if id amp CAN MSG IDE MASK pFlexCANReg gt MB iMB ID id2 else pFlexCANReg gt MB iMB ID id2 lt lt FLEXCAN MB ID STD BIT NO Activate the MB for rx pFlexCANReg MB iMB CS FLEXCAN MB CS CODE FLEXCAN MB CODE RX EMPTY 16 2 3 Transmit process FlexCAN requires four steps to configure an MB as a Tx MB to initiate a transmit process 16 2 3 1 Code example and explanation The transmit process to prepare and start a Tx MB is Follow 4 steps for Transmit Process pFlexCANReg MB iTxMBNo CS FLEXCAN MB CS CODE FLEXCAN MB CODE TX INACTIVE write inactive code wno lt lt FLEXCAN MB CS IDE BIT NO bno lt lt FLEXCAN MB CS RTR BIT NO pFlexCANReg gt MB iTxXMBNo ID prio lt lt FLEXCAN MB ID PRIO BIT NO msgID amp CAN MSG IDE MASK CAN MSG TYPE MASK lt lt i pFlexCANReg gt MB iTxMBNo WORDO word 0 Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 149 Configuration examples pFlexCANReg gt MB iTxMBNo WORD1 word 1 Start transmit with specified tx code pFlexCANReg gt MB iTxMBNo CS pFlexCANReg gt MB iTxMBNo CS amp FLEXCAN MB CS CODE MASK FLEXCAN MB CS CODE txCode write activate code FLE
199. to the PLL while MCG S MCG S PLLST MASK wait until the PLL has achieved lock while MCG S MCG S LOCK MASK set up the SIM clock dividers BEFORE switching to the PLL to ensure the system clock speeds are in spec core PLL 96 MHz bus PLL 2 48 MHz flexbus PLL 2 48 MHz flash PLL 4 24 MHz SIM CLKDIV1 SIM CLKDIV1 OUTDIV1 0 SIM CLKDIV1 OUTDIV2 1 SIM _CLKDIV1 OUTDIV3 1 SIM CLKDIV1 OUTDIVA4 3 Transition into PEE by setting CLKS to 0 previous MCG C1 settings remain the same just need to set CLKS to 0 MCG C1 amp MCG C1 CLKS MASK Wait for MCGOUT to switch over to the PLL while MCG S MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x3 The USB clock divider in the System Clock Divider Register 2 SIM CLKDIV2 should be configured to generate the 48 MHz USB clock before configuring the USB module SIM CLKDIV2 SIM CLKDIV2 USBDIV 1 sets USB divider to 2 assuming reset state of the SIM CLKDIV2 register 4 1 3 2 Transitioning between PLL engaged external mode and bypassed low power internal mode To be able to move the MCU into the VLPR or wait mode the MCG must be set in a low power low frequency mode with MCGCLKOUT 2 MHz This mode is provided by means of selecting the fast IRC when the MCG is set in BLPI mode This example shows how to move to this clock mode from PLL engaged external mode before entering VLPR and then retur
200. tor Inc 43 Clocking MCG Slow IRC Clock options for some peripherals T Core system clocks Bus clock FlexBus clock Flash clock y Osc gt logic RTC oscillator CG Clock gate EXTAL X XTAL x Clock options for some peripherals PMC logic EXTAL32 X J XTAL32 x Real time clock Figure 4 1 Clock distribution diagram The system level clocks are provided by the MCG The MCG consists of Two individually trimable internal reference clocks IRC a slow IRC with a frequency of 32 kHz and a fast IRC with a frequency of 4 MHz with a fixed divide by 2 Frequency locked loop FLL using the slow IRC or an external source as the reference clock Phase locked loop PLL using an external source as the reference clock Auto trim machine ATM to allow both of the IRCs to be trimmed to a custom frequency using an externally generated reference clock The clocks provided by the MCG are summarized as follows MCGOUTCLK this is the main system clock used to generate the core bus and memory clocks It can be generated from one of the on chip reference oscillators the on chip crystal resonator oscillator an externally generated square wave clock the FLL or the PLL MCGFLLCLK this is the output of the FLL and is available any time the FLL is enabled Kinetis Quick Reference User Guide Rev 2 08 2012 44 Freescale Semiconductor Inc
201. types of transmission priority scheme suitable for all application needs Lowest ID Lowest buffer number Highest local priority Transmission of messages can be aborted per request in order to transmit a higher priority message Remote request frames may be handled automatically by FlexCAN or by software Low power modes are also supported Other additional features are available please refer to the device specific reference manual 16 2 Configuration examples The SCI2CAN demo shows how to nitialize the FlexCAN module Configure a message buffer for transmit and or receive Read messages received in the interrupt service routine The demo codes are SCI2CAN bridge demo and Rx FIFO demo The bridge demo in the local node will send the character entered in the local HyperTerminal to the CAN loop back node which echoes it to the local node The Rx FIFO demo will configure Rx FIFO ID filter table elements in format A to receive eight messages with specified identifiers configure one MB as Rx MB and send nine messages to the CAN loop back node The local node will print received messages as well as the recipient information on the HyperTerminal The CAN loop back node by default is the local node itself and can be configured as the remote node via macros The CAN bit rate is 83 33k by default Kinetis Quick Reference User Guide Rev 2 08 2012 146 Freescale Semiconductor Inc EE MM Chapter 16 FlexCAN Module UARTS is u
202. us OTG Module Finally move the mouse or other pointing device or press any button and the status will be displayed in the terminal screen VW cOM1 115200baud Tera Term VT i Bl x File Edit Setup Control Window Help Mouse device ready try to move the mouse Left Click Right Click Right Click Figure 15 17 Mouse events Code explanation For USB host support the application needs to schedule BUS space for all the available devices on the USB bus The code is a little complex to explain in this document but this example code is based on the Freescale USB stack with Personal Healthcare Device Class PHDC support Documentation and API information is available on the Freescale website the stack is free and is MQX Freescale Real time operating system compatible For more information regarding this demo please visit www freescale com medicalusb Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 143 Example Code Kinetis Quick Reference User Guide Rev 2 08 2012 144 Freescale Semiconductor Inc Chapter 16 FlexCAN Module 16 1 Overview This chapter will describe how to execute a quick start of the FlexCAN module for Kinetis MCUs 16 1 1 Introduction The CAN protocol was primarily but not only designed to be used as a vehicle serial data bus meeting the specific requirements of this field Real time processing Reliable operation in the EMI environmen
203. usively for EEPROM backup space To configure the part the user must use the Flash Common Command Object FCCOB registers to pass the Program Partition Command and associated parameters to the memory controller in the FTFL module The FCCOB requirements for execution of this command are below Table 9 1 Program partition command FCCOB requirements FCCOB Number FCCOB Contents 7 0 0 0x80 PGMART 1 Not used 2 Not used 3 Not used Table continues on the next page Kinetis Quick Reference User Guide Rev 2 08 2012 84 Freescale Semiconductor Inc eee B Chapter 9 Using the FlexMemory Table 9 1 Program partition command FCCOB requirements continued FCCOB Number FCCOB Contents 7 0 4 EEPROM data size code FIexNVM partition code 9 1 2 2 1 Code Example and Explanation The following example uses a device with 256 KB of FlexNVM and 4 KB of FlexRAM This example assumes the part is erased and that the flash memory clock gate control is enabled in the system integration module SIM The default state in the SIM is flash memory clock enabled For a complete list of EEPROM data size codes and FlexNVM Partition codes please see the device specific reference manual In this example the FlexNVM is configured to use all 256 KB of available memory as EEPROM backup memory The available 4 KB of FlexRAM are configured as EEPROM When configuring the FlexRAM for EEPROM 2 subsystems
204. vr Connector RS232_TXD NI e IL UARTn_RX ife lg RS232 RXD UARTn RTS Bp Se VITRO Iz jT RES Figure 12 1 UART RS 232 hardware connections block diagram Kinetis Quick Reference User Guide Rev 2 08 2012 110 Freescale Semiconductor Inc Chapter 13 ENET Module 13 1 Overview The following chapter demonstrates how to use the media access controller MAC called ENET to connect to a generic external Ethernet physical transceiver also called PHY The following examples show how they connect to each other hardware and the registers software that link up to a network 13 1 1 Introduction The MAC NET controller is one of the communication interfaces included with the Kinetis family The following block diagram represents how the MAC NET fits in the system to connect to a local area network MII RMII MAC NET Generic ETH PHY Magnetics R 145 Interface m Some RJ45 manufacturers offer this in a single component Kinetis MCU Figure 13 1 MAC NET block diagram The MAC NET controller has three main components e MAC Controller Controls the buffers and registers Controls the MIT RMII Interface and IEEE15888 controller Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 111 NA Overview MII RMII Interface Interacts with the ETH PHY It works in two modes MII and RMII e EEE1588 Controller Adds time stamping
205. w Host Mode Initialization To enable host support one bit needs to be set This enables 1 ms SOF start of frame generation in the USB module When a pullup is detected in the D or D signal the module generates the attached interrupt which indicates that one device is attached to the bus and the enumeration process must start Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 135 Hardware implementation amp 72ZZZZZZEEZZZZEEEZZZZESEZRZERSERREEZEEZESEZEREZA AEE EE ESS ESET SEES SESE SS SET ESSE ES EEE EEE EEE USB Init USB Attach ISR Ide Integration Module Trigger SOF System packets USB clock gating Integration Module Reset USB module software Set BDT base Host registers Scheduler Clear all USB ISR flags and enable weak pull downs Send requests To device Enable USB Attach interrupt Enable USB Host mode support Waiting for Device nitialization Service routines Figure 15 7 Host mode initialization flow 15 5 3 Voltage regulator initialization The USB regulator is enabled by default therefore no initialization is required unless the regulator was previously disabled by the software after the last POR 15 6 Hardware implementation 15 6 1 Connection diagram The USB 2 0 requests the D and D signals VBUS 5 V power line ground and in some cases the ID pin This ID pin is included in the OTG sp
206. xbc 3 0 4 RDFLEXRAM Read FlexRAM Oxbd 3 0 1 FAST_RDFLEXRAM Read FlexRAM at high speed Oxbe 3 1 1 NOTE The 1 in the data bytes column means the SPI master could read data continuously from the Ezport module Starting from one byte the reading address will increment automatically while reading In this way the whole flash memory could be read with one single command 10 1 1 3 1 Command format As shown in Table 10 2 each command the Ezport module recognizes should start with a command byte that is mandatory and be followed by an optional address byte dummy byte or data byte This is shown below The bracketed items are optional Command address dummy byte read or write data byte Kinetis Quick Reference User Guide Rev 2 08 2012 90 Freescale Semiconductor Inc _ SSS Chapter 10 EzPort Module For example some commands like WREN and WRDI need to send only the command byte while the other commands may have optional items The dummy byte is used to differentiate normal speed and fast speed read operations For fast speed operations the external master should shift in one dummy byte before valid data is shifted out FAST_READ and FAST_RDFCCOB commands are examples that need to send the dummy byte 10 1 1 3 2 Command timing Figure 10 1 and Figure 10 2 are the command timing for the READ and FAST READ commands Here it assumes CPOL 1 and CPHA 1 EZPCS eck UUU UU I command
207. y FTSH 105 01 L DV 10 pin connector no key This interface 1s useful during the development phase of a project The header may not need to be populated in the production phase of the project but the PCB pads should be kept available for future debugging purposes Kinetis Quick Reference User Guide Rev 2 08 2012 36 Freescale Semiconductor Inc Chapter 3 Nested Vector Interrupt Controller NVIC 3 1 NVIC 3 1 1 Overview This chapter shows how the NVIC is integrated into the Kinetis MCUs and how to configure it and set up module interrupts It also demonstrates the steps to set the interrupts for the desired peripheral and how to locate the vector table from flash to RAM 3 1 1 1 Introduction The NVIC is a standard module on the ARM Cortex M series This module is closely integrated with the core and provides a very low latency for entering an interrupt service routine ISR 12 cycles and exiting an ISR 12 cycles The NVIC provides 16 different interrupt priorities Priority 0 is the highest and the lowest is15 This can be used to control which interrupt must be serviced For example on a motor control application if a UART and a timer interrupt occur at the same time serving the timer interrupt that moves the motor is more critical than the UART interrupt that just received a character In this case the timer priority must be set higher than the UART 3 1 1 2 Features On Kinetis MCUs the NVIC provides up to 120
208. ystem note that other bits in this register may need to be set depending on the intended use of the RTC RTC CR RTC CR SCi16P MASK RTC CR SC8P MASK RTC CR OSCE MASK time delay ms 1000 wait for the RTC oscillator to initialize select the RTC oscillator as the MCG reference clock SIM SOPT2 SIM SOPT2 MCGCLKSEL MASK ensure MCG C2 is in the reset state key item is RANGE 0 to select the correct FRDIV factor MCG C2 0x0 Select the Reference Divider and clear IREFS to select the osc CLKS 0 select the FLL as the clock source for MCGOUTCLK FRDIV 0 set the FLL ref divider to divide by 1 IREFS 0 select the external clock IRCLKEN 0 disable IRCLK can enable if desired IREFSTEN 0 disable IRC in stop mode can keep it enabled in stop if desired MCG C1 0x0 wait for Reference clock to switch to external reference while MCG S amp MCG S IREFST MASK Wait for clock status bits to update while MCG S amp MCG S CLKST MASK gt gt MCG S CLKST SHIFT 0x0 Can select the FLL operating range freq by means of the DRS and DMX32 bits Must first ensure the system clock dividers are set to keep the core and bus clocks within spec core FLL 48 MHz bus FLL 48 MHz flexbus PLL 48 MHz flash PLL 2 24 MHz SIM CLKDIV1 SIM CLKDIV1 OUTDIV1 0 SIM CLKDIV1 OUTDIV2 0 SIM_CLKDIV1_OUTDIV3 0 SIM _CLKDIV1_OUTDIV4 1 In this example DMX32 is s
209. ystems specifically use planes for power and ground This may raise the PCB cost but the benefits of crosstalk reduction reduction of RF emissions and improved transient immunity can be realized with lower overall production and maintenance costs In general the ground routing should take precedence over any other routing Ground planes or traces should never be broken by signals For packages with leads like the LQFP a ground plane directly below the MCU package is recommended to reduce RF emissions and improve transient immunity All of the VSS pins of the MCU should be tied to a ground plane Ground traces from a plane should be kept as short as possible as they are routed to circuitry on signal layers top and bottom Power planes may be broken to supply different voltages All of the VDD pins of the MCU should be tied to Kinetis Quick Reference User Guide Rev 2 08 2012 Freescale Semiconductor Inc 23 ee S Hardware considerations the proper power plane Power traces from the planes should be kept as short as possible as they are routed to circuitry pullups filters other logic amp drivers on the top and bottom layers More information is given in the PCB Layer Stack up section below 2 1 3 2 Power supply decoupling and filtering As mentioned in the power domains section decoupling networks are used to separate domains Bypass capacitors while also called decoupling capacitors are the storage elements that p

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