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HardCopy II Clock Uncertainty Calculator User Guide

1. The multi cycle clock occurs when there is a delay At that is greater than the clock period between the source register and destination register Refer to Figure 1 7 The default hold clock uncertainty value is considered that the source clock and destination clock are on the same edge When the multi cycle path timing exception is set you need pay attention for the hold clock uncertainty of Intra clock transfers since the possible hold checks are not at the launch edge for both source and destination clock due to the extra delay At on the data path 3 4 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Design Case Exceptions Figure 3 7 Multi Cycle Clock DI Source Destination Register Register CLK1 R1 Cat Re PLL INBUF CLK2 Launch Capture Ed sai Edge A AN N N AN E0 EI E2 E3 E4 t A A A A Possible Hold Checks Setup Check Altera Corporation In the example shown in Figure 3 7 the multi cycle path timing exception is set and the hold margin is not checked at the launch clock edge in other words the hold margin is checked at E1 E2 or E3 edge You should use the setup clock uncertainty value from clock uncertainty calculator for hold clock uncertainty constraints Figure 3 8 shows the clock uncertainty result from the schematic circuit The setup clock uncertainty is 100 ps and the hold clock unce
2. 0 2nd PLL 1st PLL 9 2nd PLL 7 A 29 HardCopy Il Clock Uncertainty Calculator User Guide VO Interface with Cascaded PLLs Figure A 31 shows an example of a clock pair CLK6 to Off chip Figure A 31 Output Interface with Cascaded PLLs LK X gt PLL10 Co INBUF PLL2 CLK2 Source Clock AX DATA Source Register Table A 31 shows input of the PLL index for Figure A 31 with respect to the source and destination clocks Table A 31 Location of Input PLLs Source Clock Destination Clock 1st PLL 10 2nd PLL 2 1st PLL 2nd PLL 0 A 30 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation
3. Altera Corporation 1 7 August 2007 HardCopy II Clock Uncertainty Calculator User Guide General Description Figure 1 7 Clock Uncertainty Set up and Hold Check Source Clock Clock hold check with uncertainty Clock steup check with uncertainty Clock Hold Uncertainty Destination Clock Clock Setup Uncertainty 0 0 ns 5 0 ns 10 0 ns To obtain the clock uncertainty values from HardCopy II devices you should use the Altera HardCopy II Clock Uncertainty Calculator which consists of the Tcl based script for obtaining the PLL setting summary and the Microsoft Excel based spreadsheet of clock uncertainty calculators Both utilities are packaged in the Altera HardCopy II Clock Uncertainty Calculator which is available on the Altera web site www altera com 1 8 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide August 2007 Chapter 2 Launching the JN OS RYA HardCopy Il Clock Uncertainty Calculator Release Table 2 1 provides information about the version of HardCopy II Clock A Uncertainty Calculator spreadsheet documented in this user guide Information Table 2 1 HardCopy Il Clock Uncertainty Calculator Spreadsheet Version HardCopy Il Clock Uncertainty Device Family Calculator Spreadsheet Version HardCopy II 2 2 and later Devi ce Fa m i ly The HardCopy II Clock Uncertainty Calculator supports the following HardCopy II
4. 6 shows an example of a clock pair CLK2 to CLK7 Figure A 6 Inter Clock Domain with Two PLLs Source Register Source CLK2 Clock Destination CLK7 Register Destination Clock Table A 6 shows input of the PLL index for Figure A 6 with respect to the source and destination clocks Table A 6 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 5 9 A 6 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Figure A 7 shows an example of a clock pair CLK3 to CLK9 Figure A 7 Inter Clock Domain with Two Independent Clocks and a PLL on the Destination Clock Source K CLK3 Clock INBUF9 gt INBUF11 Altera Corporation PLL4 CLK9 Source Register Destination Clock Destination Register Table A 7 shows input of the PLL index for Figure A 7 with respect to the source and destination clocks Table A 7 Location of Input PLLs Source Clock Destination Clock 1st PLL 0 2nd PLL 1st PLL 2nd PLL 4 A 7 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with PLL Figure A 8 shows an example of a clock pair CLK7 to CLK11 Figure A 8 Inter Clock Domain with Two Independent Clocks and a PLL on the Source Clock Source Register CLK7 C
5. A 27 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with Cascaded PLLs Figure A 29 shows an example of a clock pair CLK11 to CLK6 Figure A 29 Inter Clock Domain with Two Independent Clocks and Cascaded PLLs on Both Source and Destination Clocks Source lock i CLK10 CLK11 ee X PLL5 PLL9 INBUF3 CLK5 CLK6 X PLL4 PLL3 P Destination INBUF4 dik Source Register Destination Register A 28 Table A 29 shows input of the PLL index for Figure A 29 with respect to the source and destination clocks Table A 29 Location of Input PLLs Source Clock Destination Clock 1st PLL 5 2nd PLL 9 1st PLL 4 2nd PLL 3 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation I O Interface with Cascaded PLLs This section provides clock transfer examples for an I O interface with cascaded PLLs Figure A 30 shows an example of a clock pair Off chip to CLK8 Figure A 30 Input Interface with Cascaded PLLs Den Bb PLL9 INBUF CLK3 CLK8 DATA PLE gt Destination Clock Destination Register Altera Corporation Table A 30 shows input of the PLL index for Figure A 30 with respect to the source and destination clocks Table A 30 Location of Input PLLs Source Clock Destination Clock 1st PLL
6. Clock INBUF Without PLL 350 350 P With PLL 150 150 I O Interf VO Interface Without PLL 180 180 To set the clock uncertainty constraints correctly you should create a virtual clock for the circuit The following code example shows the SDC used to constrain the design as shown in Figure 3 1 Example 3 1 SDC Constraints for i O create clock CLK1 period set_input_delay min clock VIRI set_clock_uncertainty from CLK1 10 TUAL TUAL get_ports CLK1 create clock name VIRTUAL CLK period 10 set input delay max clock VIRI C K 8 00 K 2 00 get_ports DIN1 get_ports DIN1 to CLK1 setup 0 200 set_clock_uncertainty from CLK1 to CLK1 hold 0 050 set_clock uncertainty from VIRTUAL CLK1 to CLK1 setup 0 180 set_clock_uncertainty from VIRTUAL CLK1 to CLK1 hold 0 180 Altera Corporation Various Clock Structures Various Clock When a clock is generated in the core additional clock uncertainty may be introduced by the additional routing The HardCopy II Clock Structures Uncertainty Calculator supports the following clock structures m AND and MUX gated clocks B Clock divider E Ripple clock Mm Multiple clock networks Mm Multi cycle clock For each global and local clock network added to any of the examples in Appendix A clock uncertainty values should be increased by 25 ps The
7. Uncertainty Values button Under the Source Clock and Destination Clock cells in Figure 2 8 there are first PLL and second PLL cells on the worksheet which means the advanced clock uncertianty calculator supports designs with cascaded PLLs and each clock path has a maximum of two PLLs cascaded If there is no PLL in the design you still must enter 0 for the first PLL cell on the worksheet As in the advanced clock uncertianty calculator click the yellow Reset Table button to clear all previous clock uncertainty results You can enter notes for reference in the last cell of the table The advanced clock uncertianty calculator supports up to 200 clock transfer combinations Figure 2 8 HardCopy Il Advanced Clock Uncertainty Calculator without Calculation ATERA HARDCOPY II Step 1 Enter PLL Information Step 3 Read Clock Uncertainty Values Transfer Source Clock Destination Clock Intra ciock__ Inter Clock 10 Transfer Messages ra 1st PLL 2nd PLL 1st PLL 2nd PLL Setup ps Hold ps Setup ps Hold ps Setup ps Hold ps Before beginning the calculation of clock uncertainty values refer to the clock transfer report and PLL_Names txt The clock transfer report shows all clock to clock transfers in detail and PLL_Names txt provides the corresponding PLL index for each PLL name Figure 2 9 show how to enter the PLL indices for the advanced clock uncertianty calculator 2
8. associated PLL names Even if the design does not contain a PLL you still must run the Tel script Clock Transfer Report Before continuing on to the clock uncertainty calculator spreadsheet you must generate the clock transfer report using TimeQuest Timing Analyzer The clock transfer report covers the clock to clock transfer in the design if a path exists between two registers that are clocked by two clocks The two clocks are source and destination clocks and they may be the same or different clocks This report of clock transfer from the TimeQuest Timing Analyzer is not an input file for the clock uncertainty calculator but rather provides useful information you may need when setting the clock uncertainty timing constraints SDC for the design For example set_clock uncertainty setup from clk source to clk destination 0 150 where clk source is source clock name and clk _destinationisthe destination clock name Clock uncertainty is based on I O buffer noise clock network noise core noise PLL jitter or static phase error Thus the clock transfer information plays an important role in the clock uncertainty calculator flow There are three types of clock transfers that clock uncertainty calculator flow covers BH Intra clock transfer E Inter clock transfer E I O transfer Refer to the TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook for more information about report clock transfer Altera Corpo
9. devices in Commercial and Industry temperature ranges Support sal i HC240 HC230 HC220 HC210 HC210W Use HC210 clock uncertainty value for HC210W The HardCopy II Clock Uncertainty Calculator was developed for calculating the clock uncertainties caused by clock jitter duty cycle distortion and phase shift error With different interfaces of the clock transferring on the chip you may have different outcomes for the clock uncertainty As shown in Figure 2 1 the HardCopy II Clock Uncertainty Calculator covers clock transfer at the following locations M Within core M Between the core and I O M Between the core and SERDES DDR blocks Altera Corporation 2 1 System and Software Requirements Figure 2 1 HardCopy Il Clock Uncertainty Calculator Coverage i x X X DI DI K x rh DDR 1 c b X s mi X Xe CORE o X x E HC230 2 x 2 pH XK tro pi Hp D DDR 1 DI bd DI Be Da DI Note to Figure 2 1 1 Transfer covered by DTW 2 Transfer covered by SERDES 3 Transfer covered by Altera HardCopy II Clock Uncertainty Calculator Syste m and The Altera HardCopy II Clock Uncertainty Calculator spreadsheet requires the following hardware and software Software Re q uirements Mm A PC running the Windows NT 2000 XP operating system M Microsoft Office 2003 SP 1 o
10. 8 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Launching the HardCopy II Clock Uncertainty Calculator Refer to the highlighted column in Figure 2 9 of the clock transfer report and PLL_Names txt for the following procedures 1 From the clock transfer report trace the pin or port under From Clock For example altpl10 PLLO altpll altpll_component _clk1 Refer to the PLL_Name txt file to and see what the PLL index is associated to For example altpl10 PLLO altpll altpll_component associates to PLL_2 From the clock transfer report trace the pin or port under To Clock For example altpl10 PLL1 altpll altpll_component _clk0 Refer to the PLL_Name txt file in Figure 2 9 to see what the PLL index associated to For example altpl10 PLL1 altpll altpll_component associates to PLL_1 You now know the source clock from PLL_2 and the destination clock from PLL_1 Enter 2 and 1 into the first PLL cell of the source clock and the destination clock respectively as shown in Figure 2 10 on page 2 10 Figure 2 9 Clock Transfer Report and PLL_Names txt Setup Transfers I From Clock 11 altplio PLLOlaltpli atpli_componentL_clk0 altpll0 PLLOlaltpll altpl_componentL_clk0 PLL_1L altpl 0 PLL1 altpl altp _component p 2 virtual_clk1 altpll0 PLLOlaltpl altpl_componentLclkO IPLL_2 altp110 PLLO altp11 altp11_compone
11. Advanced Clock Uncertainty Calculator Create Clock Uncertainty Timing Constraints on a SDC Chapter 3 Design Case Exceptions Multiple Clock Uncertainty on a Single Clock Transfer iii Various Clock Structure es Clock Gated in Core Clock Divider Ripple Clock sssi Multiple Clock Networks Multi Cyele Clock icnir ci RI illa Altera Corporation iii August 2007 Contents Appendix A Clock Transfer Examples Intra Clock Domain With PLL Intra Clock Domain without PLL Inter Clock Domain with PLL Inter Clock Domain without PLL I O Interface with PLL i I O Interface without PLL Intra Clock Domain with Cascaded PLLS A 14 Inter Clock Domain with Cascaded PLLS A 16 I O Interface with Cascaded PLLS Mei A 29 iv Altera Corporation HardCopy II Clock Uncertainty Calculator User Guide August 2007 Ae About this User Guide Revision Hi story The following table shows the revision history for this User Guide Date Version Changes Made Summary of Changes August 2007 v1 0 N A How to Conta ct For the most up to date information about Altera products refer to the following table Altera Contact Contact 1 Method Address Technical support Website www altera com support Te
12. BUF7 Source Register Destination Register Table A 10 shows input of the PLL index for Figure A 10 with respect to the source and destination clocks cS If no PLL exists enter 0 for both the source and destination clocks Table A 10 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 0 o 1st PLL 0 2nd PLL A 10 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation O nte rfa ce This section provides clock transfer examples for an I O interface with at with PLL least one PLL Figure A 11 shows an example of a clock pair Off chip to CLK5 Figure A 11 Input Interface with a PLL K gt PLL10 INBUF CLK5 DATA Destination Clock Destination Register Table A 11 shows input of the PLL index for Figure A 11 with respect to the source and destination clocks Table A 11 Location of Input PLLs Source Clock Destination Clock 1st PLL 0 2nd PLL 1st PLL 2nd PLL 10 Altera Corporation A 11 HardCopy Il Clock Uncertainty Calculator User Guide VO Interface without PLL Figure A 12 shows an example of a clock pair CLK2 to Off chip Figure A 12 Output Interface with a PLL XK DATA X eal Source CLK2 Clock INBUF Source Register Table A 12 sho
13. HardCopy Il Clock Uncertainty Calculator User Guide AN DTE RYAN 101 Innovation Drive San Jose CA 95134 www altera com Software Version Document Date Document Version 7 1 1 0 August 2007 Copyright 2007 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services I S EN ISO 9001 UG 01015 1 0 ii Altera Corporation HardCopy Il Cloc
14. LL 1st PLL 2nd PLL 9 1 0 Altera Corporation A 17 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with Cascaded PLLs Figure A 19 shows an example of a clock pair CLK5 to CLK7 Figure A 19 Inter Clock Domain with Cascaded PLLs and One PLL Shared and the Second PLL on the Destination Clock INBUF CLK5 Source PLL7 CLK4 PLL9 CLK7 Clock Source Register Destination Destination Register Clock A 18 HardCopy Il Clock Uncertainty Calculator User Guide Table A 19 shows input of the PLL index for Figure A 19 with respect to the source and destination clocks Table A 19 Location of Input PLLs Source Clock Destination Clock 1st PLL 7 2nd PLL 1st PLL 7 2nd PLL 9 Altera Corporation Figure A 20 shows an example of a clock pair CLK7 to CLK8 Figure A 20 Inter Clock Domain with Cascaded PLLs and One PLL Shared and the Second PLL on the Source Clock XH gt PLL3 INBUF CLK5 CLK7 Sadeg S pilo CLK8 Destination Clock Source Register Destination Register Table A 20 shows input of the PLL index for Figure A 20 with respect to the source and destination clocks Table A 20 Location of Input PLLs Source Clock Destination Clock 1st PLL 3 2nd PLL 2 1st PLL 3 2nd PLL Alt
15. PLL 2nd PLL 1st PLL 2nd PLL 9 9 Altera Corporation A 1 Intra Clock Domain with PLL Figure A 2 shows an example of a clock pair CLK5 to CLK6 Figure A 2 Intra Clock Domain with Two PLL Outputs Source Register Source CLK5 Clock XH PLL11 Destination INBUF t Register CLK6 9 Destination Clock Table A 2 shows input of the PLL index for Figure A 2 with respect to the source and destination clocks Table A 2 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 11 11 A 2 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Intra Clock Domain without PLL This section provides clock transfer examples for an intra clock domain without a PLL Figure A 3 shows an example of a clock pair CLK1 to CLK1 Figure A 3 Intra Clock Domain without a PLL Source Register Source CLK1 Clock Destination INBUF l R CLKI egister Destination Clock Table A 3 shows input of the PLL index for Figure A 3 with respect to the source and destination clocks DS If no PLL exists enter 0 for both the source and destination clocks Table A 3 Location of Input PLLs Source Clock Destination Clock Altera Corporation 1st PLL 0 2nd PLL 1st PLL 0 2nd PLL HardCopy Il Clock Uncertainty Calculator Us
16. User Guide Inter Clock Domain with Cascaded PLLs Figure A 27 shows an example of a clock pair CLK2 to CLK10 Figure A 27 Inter Clock Domain with Two Independent Clocks and Cascaded PLLs on the Destination Clock and One PLL on the Source Clock x gt PLL10 x gt PLL4 INBUF6 INBUF3 CLK2 Source Clock L CLK9 CLK10 PLL8 Destination Clock Db Source Register Destination Register A 26 Table A 27 shows input of the PLL index for Figure A 27 with respect to the source and destination clocks Table A 27 Location of Input PLLs Source Clock Destination Clock 1st PLL 10 2nd PLL 1st PLL 4 2nd PLL 8 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation Figure A 28 shows an example of a clock pair CLK8 to CLK9 Figure A 28 Inter Clock Domain with Two Independent Clocks and Cascaded PLLs on Source Clock and One PLL on the Destination Clock Source lock CLK5 CLK8 SE Source X PLL4 PLL11 Register INBUF2 xX gt PLL3 CLK9 D Destination Register Destination INBUF7 Clock Table A 28 shows input of the PLL index for Figure A 28 with respect to the source and destination clocks Table A 28 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 4 11 3 Altera Corporation
17. ainty values to collect both setup and hold uncertainty values For example Intra Clock Transfer and with PLL Setup CU 100 ps Hold CU 50 ps Altera Corporation 2 11 HardCopy Il Clock Uncertainty Calculator User Guide Running the Clock Uncertainty Calculator Flow 4 Create the clock uncertainty constraint on a SDC For example set_clock uncertainty from altpl10 PLLO altpll altpll_component _clk0 to altpl10 PLLO altpll altpll_component _clk1 setup 0 100 set clock uncertainty from altpl10 PLLO altpll altpll_component _clk0 to altpl10 PLLO altpll altpll_componentl _clk1 hold 0 050 Figure 2 12 Clock Transfer Report and Clock Uncertainty Values fee remain rep amn os n jih ui ANO TE RYAN a o HARDCOPY II aa Clock Transfer Type Setup CU ps Hold CU ps Messages l Intra Clock With PLL 100 50 This assumes intra clock transfer of PLL1 output Without PLL 200 50 Inter Clock With PLL 310 310 This assumes inter clock transfer between PLL1 and PL Without PLL 350 350 10 Interface ith PLL 140 140 This assumes IO transfer to from PLL1 output without PLL 180 180 Setup Transfers To Clock 1 altplio PLLOJaltpt altpli_component _clk0 altpll0 PLLOlaltpll altpll_companent _cik0 2 virtual_clk1 altpll0 PLLOlaltpil altplL_componentLclkO E atpllo PLL Ojaltpl altpll_ component _clk0 altpll0 PLLOlaltpl altoll_ componenti_clk1 4 virtual_clk1 altpll0 PLLOlaltplt altpl_c
18. ation Clock Altera Corporation Ripple Clock Figure 3 5 shows a ripple clock as an intra clock transfer example A ripple clock is similar to a divided clock but uses a different calculation to account for extra clock uncertainty value CLKO is accounted for by the clock uncertainty calculator but not CLK1 and CLK2 You need to add 25 ps uncertainty for the CLK1 network and also add 25 ps uncertainty for the CLK2 network Therefore you should add 50 ps on both setup and hold clock uncertainty for the example shown in Figure 3 5 Figure 3 5 Ripple Clock for Intra Clock Transfer reg_c reg_d CLKI o CLK2 clk_a clk_b CLKO gt CLK1 3 3 HardCopy Il Clock Uncertainty Calculator User Guide Various Clock Structures Multiple Clock Networks Figure 3 6 shows an example of multiple clock networks Figure 3 6 Multiple Clock Networks Source CLK3 Clock CLK2 i Source CLK1 gt Register x gt PLL U INBUF Destination gt CLK6 inati Register CLK5 Destination CLKA Clock Vv The CLK1 and CLK4 networks are accounted for by the clock uncertainty calculator but the CLK2 CLK3 CLK5 and CLK6 networks are ignored Therefore you should add 25 ps for each ignored clock network to the setup and hold clock uncertainty for the example in Figure 3 6 Multi Cycle Clock
19. chnical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Altera literature services Email literature altera com Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to table 1 You can also contact your local Altera sales office or sales representative Altera Corporation v August 2007 HardCopy II Clock Uncertainty Calculator User Guide Typographic Conventions Typographic Conventions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type Italic Type with Initial Capital Letters Italic type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name
20. er Guide A 3 Inter Clock Domain with PLL Inte r CI ock This section provides clock transfer examples for an inter clock domain i ith a PLL Domain with ici PLL Figure A 4 shows an example of a clock pair CLK3 to CLK5 Figure A 4 Inter Clock Domain with a PLL on the Destination Clock X PLL7 INBUF Source CLK3 Clock CLK5 Destination Clock Source Register Destination Register Table A 4 shows input of the PLL index for Figure A 4 with respect to the source and destination clocks Table A 4 Location of Input PLLs Source Clock Destination Clock 1st PLL 0 2nd PLL 1st PLL 7 2nd PLL A 4 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation Figure A 5 shows an example of a clock pair CLK8 to CLK10 Figure A 5 Inter Clock Domain with a PLL on the Source Clock X PLL3 INBUF Source CLK8 Clock CLK10 Destination Clock Source Register Destination Register Table A 5 shows input of the PLL index for Figure A 5 with respect to the source and destination clocks Table A 5 Location of Input PLLs Source Clock Destination Clock 1st PLL 3 2nd PLL 1st PLL 0 2nd PLL Altera Corporation A 5 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with PLL Figure A
21. era Corporation A 19 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with Cascaded PLLs Figure A 21 shows an example of a clock pair CLK8 to CLK11 Figure A 21 Inter Clock Domain with Cascaded PLLs on the Destination Clock and One PLL on the Source Clock Source Register CLK6 CLK8 ui PLL3 pesutaven egister X puig EHO pipz LEKTO Destination Clock INBUF Table A 21 shows input of the PLL index for Figure A 21 with respect to the source and destination clocks Table A 21 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 3 9 7 A 20 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Figure A 22 shows an example of a clock pair CLK7 to CLK10 Figure A 22 Inter Clock Domain with Cascaded PLLs on the Source Clock and One PLL on the Destination Clock CLK5 Sorres X PLL4 pike CH7 Soe INBUF CLK2 PLL11 CLK10 Destination Clock Source Register Destination Register Table A 22 shows input of the PLL index for Figure A 22 with respect to the source and destination clocks Table A 22 Location of Input PLLs Source Clock Destination Clock 1st PLL 4 2nd PLL 6 1st PLL 11 2nd PLL Altera Corporation A 21 HardCopy Il Clock Uncerta
22. following examples are for intra clock transfer with PLL the same rules apply for inter clock transfer and I O transfers as well as for all cases not involving PLLs Clock Gated in Core In Figures 3 2 and 3 3 the source register is driven by an AND or MUX gated clock CLK2 Because the clock uncertainty calculator does not account for the clock network on CLK2 you must add 25 ps on both the setup and hold clock uncertainty values Figure 3 2 AND Gated Clock for Intra Clock Transfer Source Clock LK2 CLK1 c gt Source gt PLL Register INBUF U CLK3 Destination Register Destination Clock Figure 3 3 MUX Gated Clock for Intra Clock Transfer Source Clock LK2 CLK1 B c gt Source x gt PiL Register INBUF U CLK3 K Destination Destination Register Clock 3 2 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Design Case Exceptions Clock Divider Figure 3 4 shows an example of a clock divider for intra clock transfer in which CLK1 is accounted for in the clock uncertainty calculator but not CLK2 You should add 25 ps to both the setup and hold clock uncertainty values Figure 3 4 Clock Divider for Intra Clock Transfer CLK1 gt hb A X gt PLL Register INBUF Source Clock 77 CLK2 Source CLK3 Destination Register Destin
23. g Analyzer Summary FtomClock Tocioek RR Paths RF Paths EA SDC File List bwcki Clock Transfers A crelsi 470 ER Setup Transterg E Hold Transfers cralsi false path cralso 4 cralso false path crxlso_div4 false path cralso_div4 4 crao false path v Open Project E cnoc 16 E Netlist Setup i crxa_div2 16 Create Timing Netlist crxo_div2 false path gt Read SDC File crxo_div2_sclk false path gt Update Timing Netlist crxo_div2_sclk 128 Sy Reports crxo_sclk 128 E a Individual Reports crxo_sclk false path i ES Report Fmax Summary ctxi_sclk 16 i EF Report Setup Summary ctxlsi 470 i E Report Hold Summary ctelsi false path i ER Report Recovery Summary ctxlso 4 ER Report Removal Summary chdso false path i ctxlso_div4 false path eport Minimum Pulse Width cast 76 R Report SDC R eport Unconstrained Paths etherosci_div8_ false path You can also use the report_clock transfers command to generate a report that details all clock to clock transfers in the design as shown in Figure 2 5 on page 2 6 A clock to clock transfer is reported if a path exists between two registers measured by two different clocks Altera Corporation 2 5 HardCopy Il Clock Uncertainty Calculator User Guide Running the Clock Uncertainty Calculator Fl
24. gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it displays is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier 1 2 3 and Numbered steps are used in a list of items when the sequence of the items is a b c etc important such as the steps listed in a procedure Be Bullets are used in a list of items when the sequence of the items is not important VA The checkmark indicates a procedure that consists of one step only IS The hand points to information that requires special attention A A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or the user s work i A warning calls attention to a condition or possible situation that can cause injury WARNING to t
25. he user The angled arrow indicates you should press the Enter key a The feet direct you to more information on a particular topic vi Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide August 2007 Chapter 1 About HardCopy ll JNO E RYA Clock Uncertainty Calculator Introduction Altera Corporation August 2007 Clock uncertainty is the interval of confidence around the ideal clock value such that the measured value is always within the stated interval Common sources of clock uncertainty include clock jitter duty cycle distortion and phase shift error Due to these sources clock uncertainty must be factored in to guard against deep submicron effects that are not explicitly reflected in the timing models The HardCopy II Clock Uncertainty Calculator provides the clock uncertainty values for HardCopy II devices based on PLL phase error PLL jitter I O buffer clock network noise and core noise Therefore timing constraints that consider clock uncertainty are required for the HardCopy II devices You must prepare the clock uncertainty timing constraints before starting HardCopy II migration General Description General Description sD 1 2 Figure 1 1 shows the HardCopy II development flow including the HardCopy II Clock Uncertainty Calculator flow Figure 1 1 Top level Flow for HardCopy Il Development Flow FPGA Quartus Il Database TimeQuest Ti
26. hock KH gt PLL12 ee INBUF4 CLK11 X Destination Clock INBUF6 Destination Register Table A 8 shows input of the PLL index for Figure A 8 with respect to the source and destination clocks Table A 8 Location of Input PLLs Source Clock Destination Clock 1st PLL 12 2nd PLL 1st PLL 2nd PLL 0 A 8 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation Figure A 9 shows an example of a clock pair CLK9 to CLK12 Figure A 9 Inter Clock Domain with Two Independent Clocks with a PLL KR PLL4 INBUF3 gt INBUF2 Altera Corporation PLL2 Source Register Source CLK9 Clock CLK12 Destination Clock Destination Register Table A 9 shows input of the PLL index for Figure A 9 with respect to the source and destination clocks Table A 9 Location of Input PLLs Source Clock Destination Clock 1st PLL 4 2nd PLL 1st PLL 2nd PLL 2 A 9 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain without PLL Inte r CI ock This section provides clock transfer examples for an inter clock domain i 3 ithout a PLL Domain without PLL Figure A 10 shows an example of a clock pair CLK6 to CLK9 Figure A 10 Two Independent Clocks without a PLL Source x lt gt CLK6 Clock INBUF3 CLK9 X Destination Clock IN
27. ide Inter Clock Domain with Cascaded PLLs Figure A 25 shows an example of a clock pair CLK9 to CLK7 Figure A 25 Inter Clock Domain with Two Independent Clocks and Cascaded PLLs on the Destination Clock Source CLK9 Clock DX gt INBUF2 q CLK5 CLK7 ag X PLL10 PLL11 gt Destination INBUF4 Eni Source Register Destination Register Table A 25 shows input of the PLL index for Figure A 25 with respect to the source and destination clocks Table A 25 Location of Input PLLs Source Clock Destination Clock 1st PLL 0 2nd PLL 1st PLL 10 2nd PLL 11 A 24 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation Figure A 26 shows an example of a clock pair CLK5 to CLK9 Figure A 26 Inter Clock Domain with Two Independent Clocks and Cascaded PLLs on the Source Clock Source Clock LK3 CLK5 x pLLi2 PLL2 P INBUF10 lt lt xX gt CLK9 5 Destination INBUF11 Clock Source Register Destination Register Altera Corporation Table A 26 shows input of the PLL index for Figure A 26 with respect to the source and destination clocks Table A 26 Location of Input PLLs Source Clock Destination Clock 1st PLL 12 2nd PLL 2 1st PLL 0 2nd PLL A 25 HardCopy Il Clock Uncertainty Calculator
28. inty Calculator User Guide Inter Clock Domain with Cascaded PLLs Figure A 23 shows an example of a clock pair CLK3 to CLK6 Figure A 23 Inter Clock Domain with Cascaded PLLs and One Shared and One on Source Clock and One on Destination Clock KH INBUF Sure CLK2 PLL3 CLK3 Cloci PLL12 CLK5 CLK6 Role Destination Clock Source Register Destination Register A 22 HardCopy Il Clock Uncertainty Calculator User Guide Table A 23 shows input of the PLL index for Figure A 23 with respect to the source and destination clocks Table A 23 Location of Input PLLs Source Clock Destination Clock 1st PLL 12 2nd PLL 3 1st PLL 12 2nd PLL 7 Altera Corporation Figure A 24 shows an example of a clock pair CLK7 to CLK12 Figure A 24 Inter Clock Domain with Cascaded PLLs and Two PLLs on the Source Clock and Two PLLs on the Destination Clock Source lock i CLK6 CLK7 Cloe Source PLL4 PLL3 Register INBUF pig OLK Ip ESE Destination Register Destination Clock Table A 24 shows input of the PLL index for Figure A 24 with respect to the source and destination clocks Table A 24 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 4 3 5 8 Altera Corporation A 23 HardCopy Il Clock Uncertainty Calculator User Gu
29. k Uncertainty Calculator User Guide August 2007 N D TE RYN Contents Chapter 1 About HardCopy Il Clock Uncertainty Calculator Introduction General Description PLL Extraction Clock Transfer Report Intra Clock Transfer Inter Clock Transfer Tif VAIS LON pes cascades alici Aa Clock Uncertainty Calculator Spreadsheet Instruetions a faria alla ana aria Clock Uncertainty Calculator ilaria Advanced Clock Uncertainty Calculator i 1 7 Chapter 2 Launching the HardCopy Il Clock Uncertainty Calculator Release Information taren entnstnntn stantan tanranrs ee sennnn reren enne Device Family Support siene E E E ii System and Software Requirements Download and Install the HardCopy II Clock Uncertainty Calculator 2 3 Installation of HardCopy II Clock Uncertainty Calculator Running the Clock Uncertainty Calculator Flow PLL Settings Summary Extraction ccccccsseseeseseseeseteseseesessssessessssesseesseseseessssseneasseseeeeneessesenes SYDIAX ucraina aa Running get_pll tcl on the Quartus II Tcl Console Running get_pll tcl on the Command Line or UNIX iii Report Clock Transfers Using the TimeQuest Timing Analyzer i 2 5 Run HardCopy II Clock Uncertainty Calculator Spreadsheet Using the Clock Uncertainty Calculator ui Using the
30. ll run the design through the Quartus IT software PLL settings summary extraction requires the Tcl script get_pll tcl within the working directory Syntax Use the following syntax for the PLL settings summary extraction SQUARTUS HOME bin quartus sh t get pll tcl lt project_name gt where SQUARTUS_HOME is the installation directory of the Quartus II software 2 3 HardCopy Il Clock Uncertainty Calculator User Guide Running the Clock Uncertainty Calculator Flow Running get_pll tcl on the Quartus Il Tcl Console Figure 2 2 shows the PLL settings summary extraction using the Quartus II software Figure 2 2 Example for Getting PLL Settings on the Quartus Il Tcl Console x Quartus II Tcl Console quartus_sh t get_pll tc my_design gt pll_extract log Running get_pll tcl on the Command Line or UNIX Figure 2 3 shows the PLL settings summary extraction using the command line or UNIX Figure 2 3 Example for Acquiring PLL Settings on UNIX Prompt CS 5 ZzZz o iii Terminal E window Edit Options Help stechan shama Projects my_design 165 quartus_sh t get_pll tcl my_design amp tee pll_extraction 10g l After you complete the PLL extraction you will have generated two files pll_settings_summary txt and PLL_Names txt in the working directory You should also check the log file to confirm that the PLL extraction job has completed without any errors The pll_setting
31. ming Analyzer Analysis Run Clock Uncertainty Calculator Flow 1 based on FPGA database Fix Timing Violations Vv Generate CU Recompile for Constraint File HardCopy Il ee Vv Create HC II Re run Clock Companion Uncertainty Revision Calculator Flow 7 Ta TimeQuest based on FPGA database Compile for __ Generate HardCopy Il Revised CU 6 Constraint File Note to Figure 1 1 1 Initially run clock uncertainty calculator flow on FPGA database all subsequent times are found in the HardCopy II database Refer to the Quartus II Support of HardCopy Series Device chapter in the Quartus II Handbook for more details After the Stratix II FPGA design is compiled and the database is generated successfully Altera recommends that you run the clock uncertainty CU calculator flow Although the Stratix II FPGA database may not be migrated to a HardCopy II companion device the source used to calculate the clock uncertainty in Stratix II devices is same source used in the initial stage of HardCopy s clock uncertainty calculation In addition creating and applying the clock uncertainty constraints during the HardCopy II compilation and static timing analysis will increase efficiency Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide August 2007 About HardCopy Il Clock Uncertainty Calculator Altera Corporation August 2007 All timing violations that a
32. ncertainty Calculator Figure 2 6 HardCopy Il Clock Uncertainty Calculator without Calculation NOTSRYA HARDCOPY II With PLL With PLL Inter Cloek aficui PLL III With PLL LO Interface io PLL Ii This Calculator does not cover Cascaded PLLs To start the calculation of clock uncertainty values click the green Calculate Clock Uncertainty Values button All setup and hold clock uncertainty values for different clock transfers are displayed in picosecond ps units The clock uncertainty values are contained in the CU_Values txt file If you have a previously existing clock uncertainty value file generated by the clock uncertainty calculator the file will be renamed to be CU_Values txt old Figure 2 7 HardCopy Il Clock Uncertainty Calculator with Calculation ATERA ES HARDCOPY II Intra Clock With PLL 100 This assumes intra clock transfer of PLL1 output Without PLL 200 Without PLL 350 350 Without PLL 180 180 This Calculator does not cover Cascaded PLLs Altera Corporation 2 7 HardCopy Il Clock Uncertainty Calculator User Guide Running the Clock Uncertainty Calculator Flow Using the Advanced Clock Uncertainty Calculator The third worksheet contains the advanced clock uncertianty calculator From Step 1 Enter PLL Information as shown in Figure 2 8 enter the PLL indices for source clock and destination clock before you click the green Step 2 Calculate Clock
33. nt p11 3 attpll0 PLLOlaltpl altpl_component _clk0 altpll0 PLLOlaltpll altpll_component _clk1 ane Ha 4 virtual_clk1 altpliO PLLOlaltplialtpli component_clk1 F PLL_5 N ZA KE attpll0 PLLOIaltpli Eee e SEGRE lE esi f PLL G N A virtual_clk1 altpll0 PLL1 altpll altpli_component _clk0 ewes nA altpll0 PLLOlaltpll altpll__componentLclk0 sysclk2 ikiPLLo wN A 8 altpll0 PLLOlaltpll altpl_componentl_clk1 sysclk2 PLL_10 N altpliO PLL1 altpli altpii_ component _cIk0 sysclk2 PLL_11 N A plate component PLL_12 N A Altera Corporation 2 9 HardCopy Il Clock Uncertainty Calculator User Guide Running the Clock Uncertainty Calculator Flow Figure 2 10 shows a detailed view of the advanced clock uncertianty calculator spreadsheet It is important that the first PLL be an integer number even if there is no PLL involved in the clock transfer After having the clock transfer between the different PLLs enter the PLL index with respect to the PLL in the spreadsheet as shown on Figure 2 10 Figure 2 10 Detailed View of the Advanced Clock Uncertianty Calculator Step 1 Enter PLL Information Transfer lege a Sei nani e a n a a as a EA a For more examples of how to enter the source clock and destination clock components refer to Appendix A Clock Transfer Examples After you complete all entries for the source and destination clock components click the Step 2 Calculate Clock Uncertainty Values button All
34. omponent_clk1 5 altpll0 PLLOlaltpll altpl_component _clk1 altpll0 PLL1 altplt altpl_component _clk0 6f virtual_clk1 altpll0 PLL1 altpll altpl_componentLclk0 7 altpll0 PLLOlaltpll altpl_component_clk0 sysclk2 8 altpll0 PLLOlaltpllaltpll_component _cik1 sysclk2 9 altpll0 PLL1laltpl altpl_componentl_clk0 sysclk2 This Calculator does not cover Cascaded PLLs gt mi Instructions Y CU Calculator Advanced CU Calculator de For more information about the clock transfer types refer to Chapter 1 About HardCopy II Clock Uncertainty Calculator In addition there are examples of clock transfer types in Chapter A Clock Transfer Examples of this user guide 2 12 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Chapter 3 Design Case x Exceptions Multiple Clock Uncertainty on a Single Clock In real designs there are some special cases for calculating clock uncertainty values that require extra steps Figure 3 1 shows a design with both I O transfer and intra clock Transfer transfer In this case there are two possible clock uncertainties I O and data paths for the same clock transfer Figure 3 1 Circuit with Intra Clock Transfer and I O Interface pini XK Clock Transfer Type Setup CU ps Hold CU ps da With PLL 100 50 Intra Clock Without PLL 200 50 CIKI x lt With PLL 330 330 Inter
35. or are considered more precise than the clock uncertainty calculator because it accounts for each dedicated PLL s utilization within the design The advanced clock uncertainty calculator requires the input of PLLs indices for both the source and destination clock Therefore entering the PLLs indices on the advanced clock uncertainty calculator should be relied on for both the PLL_Names txt file and the clock transfer report to generate the clock uncertainty values Also you should use this calculator if there are cascading PLLs in the design After clock uncertainty calculation the clock uncertainty values are displayed on the spreadsheet and written to a text file CU_Advanced_vValues txt Both the advanced clock uncertainty and clock uncertainty calculators can calculate and display the setup and hold uncertainty results for different types of clock transfers You can apply these clock uncertainty constraints to model jitter and noise to ensure integrity with clock signals When a clock uncertainty constraint exists for a clock signal the TimeQuest Timing Analyzer performs the most conservative setup and hold checks For a clock setup check the setup uncertainty is subtracted from the data time requirement For the clock hold check the hold uncertainty is added to the data time requirement Figure 1 7 on page 1 8 shows examples of clock sources with a clock setup uncertainty applied and clock sources with clock hold uncertainty applied
36. ow Information such as the number of destinations and sources is also reported Ignore these clock transfers for clock uncertainty if they are set as false paths Clock transfers must be verified before you specify the clock uncertainty Figure 2 5 Command of Report Clock Transfers for the Time Quest Timing Analyzer Da Cons ua p 212 2 6 Refer to the Quartus II Handbook for more information about report clock transfer Run HardCopy II Clock Uncertainty Calculator Spreadsheet From the design s working directory browse to the Microsoft Excel file HCII_CU_Calculator Rev lt version number gt xls which is the spreadsheet for the HardCopy II Clock Uncertainty Calculator Open the file to see the three worksheets in this file The first worksheet provides instructions on how to use the clock uncertainty calculator You should read the terms and conditions at the end of this page before you use the clock uncertainty calculator Using the Clock Uncertainty Calculator The second worksheet contains the clock uncertainty calculator On this worksheet notice the N A entries Figure 2 6 indicating there is no clock uncertainty calculation If there are numbers on the worksheet from aprevious calculation click the yellow Reset Table button to clear all previous clock uncertainty results Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Launching the HardCopy Il Clock U
37. pends on the design s timing requirement the PLL structures or both Create Clock Uncertainty Timing Constraints on a SDC After you have the clock transfer report and clock uncertainty values you can start to create the clock uncertainty constraints file in SDC format Use the TimeQuest Timing Analyzer SDC File Editor to create a constraint file Use the following syntax to set the clock uncertainty value set_clock_uncertainty fall from lt fall from clock gt fall_to lt fall to clock gt from lt from clock gt hold rise from lt rise from clock gt rise to lt rise to clock gt setup to lt to clock gt lt uncertainty gt Refer to the highlighted column in Figure 2 12 of the clock transfer report and clock uncertainty values for the following procedures 1 From the clock transfer report identify the transfer clock type of the pair of source and destination clocks For example from altp110 PLLO altpll altp1I_componentl _clk0 source clock to altp110 PLLO altpll altpll_component _clk1 destination clock the trasfer clock type is Intra Clock Transfer 2 From the clock transfer report identify the cell type of both source and destination clock pins For example both altp110 PLLO altpll altpll_component _clk0 source clock and altpl10 PLLO altpll altpll_component _clk1 destination clock are the PLL s output clock pins 3 Based on the step 1 and 2 information refer to the clock uncert
38. ples of clock transfer cases Clock Uncertainty Calculator Spreadsheet The clock uncertainty calculator spreadsheet consists of three parts E Instructions E Clock uncertainty calculator m Advanced Clock Uncertainty ACU calculator Instructions The clock uncertainty calculator spreadsheet is a Microsoft Excel based file The first worksheet provides quick start instructions for using the calculators Both the clock uncertainty and advanced clock uncertainty Altera Corporation HardCopy II Clock Uncertainty Calculator User Guide August 2007 About HardCopy Il Clock Uncertainty Calculator calculators require the PLL settings summary file pll_settings_summary txt as input data to calculate the clock uncertainty values Clock Uncertainty Calculator The clock uncertainty calculator is on the second worksheet It operates with a single green button and supports all designs except designs with a cascading PLL structure When the clock uncertainty values are calculated they are displayed on the spreadsheet and simultaneously written to a text file CU_Values txt The clock uncertainty values are for worst case scenarios and account for I O buffer noise clock network noise core noise PLL jitter and static phase error Advanced Clock Uncertainty Calculator The advanced clock uncertainty calculator is different than the clock uncertainty calculator The clock uncertainty values from the advanced clock uncertainty calculat
39. r higher E Quartus II software version 6 0 or higher 2 2 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Launching the HardCopy Il Clock Uncertainty Calculator Running the Clock Uncertainty Calculator Flow Altera Corporation Download and Install the HardCopy Il Clock Uncertainty Calculator The HardCopy II Clock Uncertainty Calculator includes a Tel script for PLL extraction and a clock uncertainty calculator spreadsheet and is available from the Altera web site www altera com After reading the terms and conditions and clicking I Agree you can download the package in zip format to your hard drive Installation of HardCopy Il Clock Uncertainty Calculator After you download the zip file of the HardCopy II Clock Uncertainty Calculator package unzip the file to extract the following files M get plIltcl E HCII CU Calculator Rev lt version number gt x1s Copy or move these two files into the design s Quartus II working directory This section provides detailed procedures for the HardCopy II Clock Uncertainty Calculator flow It includes PLL extraction clock transfer report and instructions for running the HardCopy II Clock Uncertainty Calculator spreadsheet PLL Settings Summary Extraction Before starting the PLL settings summary extraction you should have the generated FPGA design database ready in the Quartus II software Even if your design does not contain any PLLs you must sti
40. ration HardCopy Il Clock Uncertainty Calculator User Guide August 2007 About HardCopy Il Clock Uncertainty Calculator Intra Clock Transfer Intra clock transfer occurs when the source and destination clocks come from the same PLL I O clock pin as shown in Figure 1 3 Figure 1 3 Intra Clock Transfer S Source P Register CLK11 Clock gt DS gt vee D Destination Destination ___ Register Clock Inter Clock Transfer Inter clock transfer occurs when the source and destination clocks come from different PLLs and I O clock pins as shown in Figure 1 4 Figure 1 4 Inter Clock Transfer Source Source Register CLK2 Clock DX PLL5 b INBUF Ri PELO aw Destination Destination Register Clock Altera Corporation 1 5 August 2007 HardCopy II Clock Uncertainty Calculator User Guide General Description 1 6 I O Transfer I O transfer occurs when the clock transfer from an off chip to the destination clock input or clock transfer from the source clock to an off chip output as shown in Figures 1 5 and 1 6 Figure 1 5 Input Transfer DATA Destination xX PLL10 Register INBUF 2 Destination Clock Figure 1 6 Output Transfer x pil INBUE Source CLK2 Clock gt q DATA Source Register Refer to Appendix A Clock Transfer Examples for more exam
41. rce and destination clocks Table A 14 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 0 0 This section provides clock transfer examples for an intra clock domain with cascaded PLLs Figure A 15 shows an example of a clock pair CLK7 to CLK7 Figure A 15 Intra Clock Domain with Cascaded PLLs and Shared PLL Output KH gt INBUF Source Register Source CLK7 PLL5 cas PLL4 Destination CLK7 egister Destination Clock A 14 Table A 15 shows input of the PLL index for Figure A 15 with respect to the source and destination clocks Table A 15 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 5 4 5 4 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Figure A 16 shows an example of a clock pair CLK6 to CLK7 Figure A 16 Intra Clock Domain with Cascaded PLLs and 2 PLL Outputs KH gt INBUF CLK5 PLL9 PLL11 Source CLK6 Clock CLK7 Destination Clock Source Register Destination Register Altera Corporation Table A 16 shows input of the PLL index for Figure A 16 with respect to the source and destination clocks Table A 16 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1
42. re reported during HardCopy II compilation and static timing analysis must be resolved When you have PLL setting changes that cause new PLL jitter and or static phase error on the design you are required to re run the clock uncertainty calculator flow to acquire new clock uncertainty constraints Altera s HardCopy II Clock Uncertainty Calculator flow can be separated into three parts m PLL extraction m Clock transfer report m Clock uncertainty calculator spreadsheet Figure 1 2 shows PLL extraction the clock transfer report and the clock uncertainty calculator spreadsheet within the HardCopy II Clock Uncertainty Calculator flow Figure 1 2 HardCopy Il Clock Uncertainty Calculator Flow PLL Extraction Tcl Script y Clock Transfer Report TimeQuest Timing Analyzer PLL_Names txt pll_settings_summary txt gt Clock Uncertainty Advanced Clock Calculator Uncertainty Calculator Spreadsheet Spreadsheet CU_Values txt CU_Advanced_Values txt PLL Extraction All of the PLLs settings and names must be extracted to two separated output files by using a Tcl script get_pll tcl One of the output files pll_settings_summary txt contains the PLL settings summary which is 1 3 HardCopy Il Clock Uncertainty Calculator User Guide General Description 1 4 used as the input file for clock uncertainty calculators The other file PLL_Names txt contains the PLL indices and the
43. rtainty is 50 ps If the hold margin is on E1 E2 or E3 use the following example set clock uncertainty from CLK1 to CLK2 hold 100ps If the hold margin is on E0 use the following example set clock uncertainty from CLK1 to CLK2 hold 50ps 3 5 HardCopy Il Clock Uncertainty Calculator User Guide Various Clock Structures Figure 3 8 Clock Uncertainty from a Schematic Circuit Clock Transfer Type Setup CU ps Hold CU ps With PLL 50 Intra Clock Without PLL 200 50 With PLL 330 330 Inter Clock Without PLL 350 350 With PLL 150 150 I O Interface Without PLL 180 180 3 6 HardCopy Il Clock Uncertainty Calculator User Guide Altera Corporation Appendix A Clock Transfer JANO E RYA Examples This appendix provides clock transfer examples for the HardCopy I Clock Uncertainty Calculator Intra Clock This section provides clock transfer examples for an intra clock domain Domain with with at least one PLL PLL Figure A 1 shows an example of a clock pair CLK11 to CLK11 Figure A 1 Intra Clock Domain with a Shared PLL Output Source Register Source CLK11 Clock KH gt PLL9 INBUF Destination R CLK11 egister Destination Clock Table A 1 shows input of the PLL index for Figure A 1 with respect to the source and destination clocks Table A 1 Location of Input PLLs Source Clock Destination Clock 1st
44. s_summary txt file contains PLL indices PLL names feedback counter M values charge pump current loop filter resistances voltage controlled oscillator Vco frequency and phase frequency detector frequency that are required for running the clock uncertainty calculators You will need pll_settings_summary txt to continue the clock uncertainty calculator spreadsheet 2 4 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Launching the HardCopy II Clock Uncertainty Calculator IS If the above parameters in pll_settings_summary txt changed during the HardCopy II design development you should re run the HardCopy II Clock Uncertainty Calculator and update the clock uncertainty constraints PLL_Names txt is an optional file for the clock uncertainty calculator spreadsheet However it provides useful information when using the advanced clock uncertainty calculator worksheet as it helps to identify the corresponding PLL index for each PLL name Report Clock Transfers Using the TimeQuest Timing Analyzer After you confirm that all clock assignments are correct run report clock transfers or in the Tasks pane on the TimeQuest Timing Analyzer s GUI double click Report Clock Transfers The command generates a summary table with the number of paths between each clock domain as shown in Figure 2 4 Figure 2 4 TimeQuest Timing Analyzer s Report Clock Transfers o C Setup Transfers ES TimeQuest Timin
45. setup and hold clock uncertainty values for the different clock transfers are displayed in picoseconds You now have the all the clock uncertainty values in the CU_Values_Advanced txt file If you have a previously existing clock uncertainty value file generated by the advanced clock uncertianty calculator the file will be renamed to be CU_Values_Advanced txt old Figure 2 11 HardCopy Il Advanced Clock Uncertainty Calculator with Calculation AADTERA e HARDCOPY II Enter User s Notes Transfer Optional Step 1 Enter PLL Information Step 3 Read Clock Uncertainty Values Source Clock Destination Clock Intra clock Inter Clock IO Transfer Messages 1st PLL 2nd PLL 1st PLL 2nd PLL Setup ps Hold ps Setup ps Hold ps Setup ps Hold ps 4 4 100 50 1 2 3 0 4 320 290 150 120 4 11 0 270 330 100 150 5 10 11 300 200 2 10 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Launching the HardCopy Il Clock Uncertainty Calculator LS If the clock uncertainty values exceed 500 ps they will be highlighted on the spreadsheet The values provided are based on the general design s maximum clock uncertainty You must verify whether the clock uncertainty causes the timing closure for the design Redesign may be necessary if you must reduce the clock uncertainty number to close timing Using the clock uncertainty or advanced clock uncertainty calculators de
46. st PLL 2nd PLL 9 11 9 11 A 15 HardCopy Il Clock Uncertainty Calculator User Guide Inter Clock Domain with Cascaded PLLs Inter Clock Domain with Cascaded PLLs This section provides clock transfer examples for an inter clock domain with cascaded PLLs Figure A 17 shows an example of a clock pair CLK7 to CLK9 Figure A 17 Inter Clock Domain with Cascaded PLLs on Destination Clock INBUF CLK7 Source pig C PLL5 CLK9 Clock Source Register Destination Destination Register Clock A 16 HardCopy Il Clock Uncertainty Calculator User Guide Table A 17 shows input of the PLL index for Figure A 17 with respect to the source and destination clocks Table A 17 Location of Input PLLs Source Clock Destination Clock 1st PLL 0 2nd PLL 1st PLL 3 2nd PLL 5 Altera Corporation Figure A 18 shows an example of a clock pair CLK4 to CLK7 Figure A 18 Inter Clock Domain with Cascaded PLLs on the Source Clock Source Register CLK1 CLK4 Saee X PLL9 PLL11 INBUF Destination CLK7 Register Destination Clock Table A 18 shows input of the PLL index for Figure A 18 with respect to the source and destination clocks Table A 18 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd P
47. ws input of the PLL index for Figure A 12 with respect to the source and destination clocks Table A 12 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 7 0 O nte rfa ce This section provides clock transfer examples for an I O interface without a PLL without PLL A 12 Altera Corporation HardCopy Il Clock Uncertainty Calculator User Guide Figure A 13 shows an example of a clock pair Off chip to CLK8 Figure A 13 Input Interface without PLL DATA Destination X Register INBUF ai Destination Clock Table A 13 shows input of the PLL index for Figure A 13 with respect to the source and destination clocks Le If no PLL exists enter 0 for both the source and destination clocks Table A 13 Location of Input PLLs Source Clock Destination Clock 1st PLL 2nd PLL 1st PLL 2nd PLL 0 0 Figure A 14 shows an example of a clock pair CLK12 to Off chip Figure A 14 Output Interface without a PLL D gt CLK12 INBUF Source Clock DATA Source Register Altera Corporation A 13 HardCopy Il Clock Uncertainty Calculator User Guide Intra Clock Domain with Cascaded PLLs Intra Clock Domain with Cascaded PLLs Table A 14 shows input of the PLL index for Figure A 14 with respect to the source and destination clocks ce If no PLL exists enter 0 for both the sou

HardCopy II Clock Uncertainty Calculator User Guide

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