Reed-Solomon Compiler User Guide
Contents
1. clk sink val T sink sop A i sink_eop rsin 8 1 Source ena Source val source sop Source eop rsout 8 1 The decoder has the following optional outputs which you turn on in IP Toolbench m Error symbol m Bit error count Error Symbol Output The error symbol output rserr is the Galois field error correction value The RS decoder finds the error values and location and adds these values in the Galois field to the input value Galois field addition and subtraction is the same operation An XOR operation performs this operation between bits of the two values November 2012 Altera Corporation Reed Solomon Compiler User Guide 3 6 Chapter 3 Functional Description Interfaces Figure 3 5 on page 3 6 shows the error symbol output Figure 3 5 Error Symhol Output rsin Memory gt amp Control gt gt rsout Solve Key Chien Search Calculation P Equation amp Fomeys rserr Algorithm Whenever rserr is not 0 while decfail is 0 an error correction successfully takes place The rsout is the rserr XORed with the corresponding rsin where XOR is done for each bit so you know that the respective symbo2. 101 Innovation Drive San Jose CA 95134 www altera com UG RSCOMPILER 12 0 Reed Solomon Compiler User Guide MA Feedback Subscribe 2012 Altera Corporation rights reserved ALTERA ARRIA CYCLONE HARDCOPY MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered November 2012 Altera Corporation Reed Solomon Compiler User Guide N DTE SYN Contents Chapter 1 About This Compiler licum 1 1 Release Information sitive ki as se he a eb b pa dU edd red red b rer C Era 1 2 Device Fam
3. Number of Errors Decoder Behavior Errors lt R 2 Decoder detects and corrects errors 2 errors lt R Decoder asserts decfail and can only detect errors 7 Errors gt R Unpredictable results Note to Table 3 1 1 The decoder may fail assert decfail for low values of 4 5 or 6 or when using erasures and the differences between the number of erasures and R is small 4 5 or 6 Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 3 Functional Description 3 5 RS Decoder The RS decoder observes Avalon ST interface standard for input and output data One clock cycle after the decoder asserts sink ena you can assert sink val The decoder accepts the data at rsin as valid data The codeword is started with sink sop The numcheck and numn signals are latched to sink sop The codeword is finished when sink eop is asserted If sink ena is de asserted from one clock cycle onwards the decoder cannot process any more data until sink ena is asserted again At the output the operation is identical If you assert source ena the decoder asserts source val and provides valid data on rsout if available Also it indicates the start and end of the codeword with source sop and source eop respectively Figure 3 4 shows the operation of the RS decoder Figure 3 4 Decoder Timing
4. sink eop source eop rr eras sym decbit Avalon ST Interface Avalon ST Interface Parameters Table 3 2 shows the implementation parameters Table 3 2 Implementation Parameters Parameter Value Description Encoderor Specifies an encoder or a decoder Refer to Functional Description on Decoder page 3 1 Variable On or Off Specifies the variable option Refer to Variable Encoding and Decoding on page 3 3 Erasures supporting decoder On or Off Specifies the erasures supporting decoder option This option substantially 1 increases the logic resources used Refer to Erasures on page 3 2 Specifies the error symbol output Refer to RS Decoder on page 3 4 and 1 Error symbol On or Off Table 3 8 on page 3 10 You can set the bit error output to be either Split count or Full count Refer to 1 pir error Ori dr Qi RS Decoder on page 3 4 and Table 3 8 on page 3 10 The keysize parameter allows you to trade off the amount of logic resources Half or against the supported throughput Full has twice as many Galois field Keysize 1 Ful multipliers as half A full decoder uses more logic and is probably slightly slower in frequency but supports a higher throughput If both full and half give you the required throughput for your parameters always select half Note to Table 3 2 1 This parameter applies to the decoder only November 2012 Altera Corporation Reed Sol
5. M 3 The number of check symbols per codeword R The throughput in megabits per second Mbps is derived from the formulas in Table 3 9 on page 3 11 and maximum frequency at which the design can operate Overall resource requirements vary widely depending on the parameter values used The number of logic elements LEs or combinational ALUTS required to implement the function is linearly dependent on both the field size and the number of check symbols More memory is required for 9 10 11 or 12 bits per symbol Specifying the erasures supporting and the variable option also increases the memory required Installation and Licensing November 2012 Altera Corporation The 5 Compiler is part of the MegaCore IP Library which is distributed with the Quartus II software and can be downloaded from the Altera website www altera com For system requirements and installation instructions refer to the Altera Software Installation and Licensing manual Reed Solomon Compiler User Guide Chapter 1 About This Compiler Installation and Licensing Figure 1 1 shows the directory structure after you install the RS Compiler where path is the installation directory for the Quartus II software The default installation directory on Windows is c NalteraN version and on Linux is opt altera lt version gt Figure 1 1 Directory Structure path Installation directory ip Contains the Altera MegaCore IP Library and thi
6. register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key e 1 2 3 and a b and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate list of items when the sequence of the items is not important 57 The hand points to information that requires special attention The question mark directs you to a software help system with related information p The feet direct you to another document or website with related information imd The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up t
7. November 2012 121 Added support for Arria V GZ devices m Updated support level to final support for Arria II GX Arria 11 GZ Cyclone III LS and Cyclone IV GX devices May 2011 11 0 um m Updated support level to HardCopy Compilation for HardCopy 111 HardCopy IV E and HardCopy IV GX devices 101 m Added preliminary support for Arria 11 GZ devices December 2010 Updated support level to final support for Stratix IV GT devices July 2010 10 0 Added prelminary support for Stratix V devices m Maintenance update November 2009 9 1 m Reorganized to clarify two design flows m Added preliminary support for Cyclone III LS Cyclone IV and HardCopy IV GX devices March 2009 9 0 Added Arria Il GX device support November 2008 8 1 No changes May 2008 8 0 Added device support for Stratix IV devices October 2007 7 2 No changes May 2007 7 1 Updated rserr signal December 2006 7 0 Added support for Cyclone III devices December 2006 6 1 Updated format How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com November 2012 Altera Corporation Reed Solomon Compiler Use
8. Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook You can simulate an RS MegaCore function in your design and perform a time limited evaluation of your design in hardware Fore more information about OpenCore Plus hardware evaluation using the RS Compiler refer to OpenCore Plus Evaluation on page 1 6 November 2012 Altera Corporation N 3 Functional Description Background To use Reed Solomon RS codes a data stream is first broken into a series of codewords Each codeword consists of several information symbols followed by several check symbols also known as parity symbols or redundant symbols Symbols can contain an arbitrary number of bits In an error correction system the encoder adds check symbols to the data stream prior to its transmission over a communications channel When the data is received the decoder checks for and corrects any errors Figure 3 1 Figure 3 1 RS Codeword Example Symbol Codeword mE 0010 0110 4 to 10 bits per symbol 1010 0011 0111 1011 1 Information symbols which Check symbols added by contain the original data the RS encoder before transmission over a communications channel RS codes are described as N K where N is the total number of symbols per codeword and K is the number of information symbols R is the number of check symbols N K Errors are defined on a symbol basis
9. Simulation An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software The model allows for fast functional simulation of IP using industry standard VHDL and Verilog HDL simulators You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design CAUTION To generate an IP functional simulation model for your MegaCore function follow these steps 1 Click Step 2 Set Up Simulation in IP Toolbench Figure 2 3 on page 2 4 shows the IP Toolbench 2 Turn on Generate Simulation Model as shown in Figure 2 7 3 Choose the required language in the Language list 4 Some third party synthesis tools can use a netlist that contains only the structure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 2 Getting Started 2 1 MegaWizard Plug In Manager Flow 5 Click OK Figure 2 7 Generate Simulation Model Set Up Simulation Reed Solomon Compiler rEDA Generate Simulation Model Language VHDL An IP Functional Simulation Model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software The
10. output files project path variation name gt Figure 2 2 shows the parameter editor after you specify these settings Figure 2 2 Select the Megafunction MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Select a megafunction from the list below Installed Plug Ins Altera SOPC Builder H Arithmetic E CI Communications C3 psp E Error Detection Correction Reed Solomon 10 0 amp Viterbi v10 0 8 C Filters e C3 Signal Generation Transforms 8 Video and Image Processing C Gates amp C3 uo Interfaces amp CJ JTAG accessible Extensions H Memory Compiler Which device Family will you be using Cyclone II 7 Which type of output file do you want to create AHDL VHDL O Verilog HDL What name do you want the output file LJ C mydesigns rs_examples rs_0 Return to this page for another create operation Note To compile a project successfully in the Quartus II software your design files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu or a library specified in the Libraries page of the Settings dialog box Assignments menu Your current user library directories are Finish 7 Click Next to launch IP Toolbench Parameterize the MegaCore Function To parameterize your MegaCore function follow these steps November 2012 Altera Co
11. vhd A timing and resource netlist for use in some third party synthesis tools variation name hsf variation name or v variation name nativelink tcl Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 2 Getting Started Simulate the Design 2 9 Table 2 1 Generated Files Part 2 of 2 7 Filename Description variation name testbench vhd runs the simulation This file instantiates the function variation file and the The testbench variation file which defines the top level testbench that testbench from the reed_solomon lib directory variation name vsim script tcl Starts the MegaCore function simulation in the ModelSim simulator variation name block period stim txt The testbench stimuli includes information such as number of codewords number of symbols and check symbols for each codeword variation name encoded data txt Contains the encoded test data variation name html A MegaCore function report file in hypertext markup language format variation name A single Quartus II IP file is generated that contains all of the assignments and other information required to process your MegaCore function variation in the Quartus compiler You are prompted to add this file to the current Quartus II project when you exit the parameter editor Notes to Table 2 1 1 variation name
12. 1 111 01 020302 os o6 07 m co source val agree z eee eee eee eee es rsout 8 1 E i j jo ez yos oa os 06 97 oa YPrjrzys Pa esos 10 1 5 j i numcheck 4 1 05 8m E TE E Source sop RS Decoder The decoder implements an Avalon ST based pipelined three codeword depth architecture However if the parameters are in the continuous range refer to Table 3 3 on page 3 8 the decoder shows continuous behavior and can accept a new symbol every clock cycle The decoder is self flushing it processes and delivers a codeword without needing a new codeword to be fed in Therefore latency between the input and output does not depend on the availability of input data The throughput latency is approximately three codewords The reset is active high and can be asserted asynchronously However it has to be de asserted synchronously with clk The RS decoder always tries to detect and correct errors in the codeword However as the number of errors increases the decoder gets to a stage where it can no longer correct but only detect errors at which point the decoder asserts the decfail signal As the number of errors increases still further the results become unpredictable Table 3 1 shows how the decoder corrects and detects errors depending on R Table 3 1 Decoder Detection and Correction
13. 2 972 1 676 5 193 1 213 Variable decoder Half 8 204 16 1 886 1 074 5 202 1 620 Erasures decoder Half 8 204 16 3 151 1 561 5 188 1 500 Erasures and variable decoder Half 8 204 16 3 465 1 704 6 191 1 527 Standard encoder 8 204 16 256 210 324 2 593 Variable encoder 8 204 16 1 048 313 237 1 897 Variable encoder 8 204 32 2 341 580 227 1 813 Notes to Table 1 4 1 The number of bits per symbol m 2 The number of symbols per codeword M 3 The number of check symbols per codeword Table 1 5 shows the typical performance using the Quartus II software for Stratix EP3SE50F780C2 devices Table 1 5 Performance Stratix Ill Devices Parameters ALUTS Logic Memory fmax Throughput Options Keysize symbels Chank Registers MHz Mbps Standard decoder Half 4 15 6 417 366 5 403 378 Standard decoder Half 8 204 16 1 139 998 5 358 2 865 Split bit error decoder Half 8 204 16 1 196 1 060 5 336 2 686 Full bit error decoder Half 8 204 16 1 181 1 065 5 328 2 624 Standard decoder Half 8 255 32 2 027 1 685 5 319 2 011 Variable decoder Half 8 204 16 1 273 1 082 5 359 2 071 Erasures decoder Half 8 204 16 2 092 1 564 5 309 2 469 Erasures and variable decoder Half 8 204 16 2 200 1 708 6 311 2 490 Standard encoder 8 204 16 204 210 621 4 969 Variable encoder 8 204 16 779 313 397 3 179 Variable e
14. 3 4 Error symbol Outputs ovp dtd eee ee oe Chee dene ee te 3 5 Bit Error dun diee e exiens ud 3 6 Interfaces tee ee dea ce Cube babel 3 6 Parameters edes ide e ce 3 7 Signals ee pd en a ended 3 8 Throughput Calculator ecd R ae on eode rne lesa 3 10 Appendix A Using the RS Encoder or Decoder in a CCSDS System IntrOOctlOTi Eo eee ae neces Ake ges Ree ante aa decanted se beue erae oso A 1 LestLatterns i eda e dte od d A 1 Additional Information Revision Estoy Ee Rag nO esee EREA Info 1 How to Contact Altera isesi RR p EI duet uec Xu ip de kd ta Info 1 Typographic Conventions 0 I hh Info 2 November 2012 Altera Corporation Reed Solomon Compiler User Guide iv Contents edit Document Title variable in cover month year Altera Corporation edit Document Type variable in cover JA DTE RA 1 About This Compiler Features This document describes the Altera Reed Solomon RS Compiler The Altera RS Compiler comprises a fully parameterizable encoder and decoder for forward error correction applications RS codes are widely used for error detection and correction in a wide range of DSP applications for
15. Any number of bit errors within a symbol is considered as only one error RS codes are based on finite field i e Galois field arithmetic Any arithmetic operation addition subtraction multiplication and division on a field element gives a result that is an element of the field The size of the Galois field is determined by the number of bits per symbol specifically the field has 2 elements where is the number of bits per symbol A specific Galois field is defined by a polynomial which is user defined for the RS Compiler IP Toolbench lets you select only valid field polynomials The maximum number of symbols in a codeword is limited by the size of the finite field to 2 1 For example a code based on 10 bit symbols can have up to 1 023 symbols per codeword The RS Compiler supports shortened codewords The following equation represents the generator polynomial of the code R 1 869 IT x io i 0 where i0 is the first root of the generator polynomial a is the rootspace Ris the number of check symbols ais a root of the polynomial November 2012 Altera Corporation Reed Solomon Compiler User Guide 3 2 Erasures Chapter 3 Functional Description Background For example for the following information g x II x of i 0 a is a root of the binary primitive polynomial x x7 x x 1 10 120 You can calculate the following parameters R 1 3 m a 1 ais to the power 1 times i
16. The field polynomial can be obtained by replacing x with 2 thus 28 27 22 2 1 391 In normal operation the RS decoder detects and corrects symbol errors The number of symbol errors that can be corrected C depends on the number of check symbols R and is given by C R 2 If the location of the symbol errors is marked as an erasure the RS decoder can correct twice as many errors so C R Erasures are symbol errors with a known location External circuitry identifies which symbols have errors and passes this information to the decoder using the eras symsignal The eras syminput indicates an erasure when the erasures supporting decoder option is selected The RS decoder can work with a mixture of erasures and errors A codeword is correctly decoded if 2e E x where e errors with unknown locations E erasures number of check symbols For example with ten check symbols the decoder can correct ten erasures or five symbol errors or four erasures and three symbol errors If the number of erasures marked approaches the number of check symbols the ability to detect errors without correction decfail asserted diminishes Refer to Table 3 1 on page 3 4 Shortened Codewords Reed Solomon Compiler User Guide A shortened codeword contains fewer symbols than the maximum value of N which is 2 1 A shortened codeword is mathematically equivalent to a maximum length code with the extra data symbols
17. analysis for the device family It can be used in production designs with caution HardCopy Device Families HardCopy Companion The IP core is verified with preliminary timing models for the HardCopy companion device The IP core meets all functional requirements but might still be undergoing timing analysis for the HardCopy device family It can be used in production designs with caution Final support The IP core is verified with final timing models for this device family The IP core meets all functional and timing requirements for the device family and can be used in production designs HardCopy Compilation The IP core is verified with final timing models for the HardCopy device family The IP core meets all functional and timing requirements for the device family and can be used in production designs Reed Solomon Compiler User Guide November 2012 Altera Corporation Chapter 1 About This Compiler Performance and Resource Utilization Table 1 3 shows the level of support offered by the RS Compiler to each of the Altera device families Table 1 3 Device Family Support Device Family Support Arria GX Final Arria Il GX Final Arria GZ Final Arria V GZ Preliminary Cyclone Final Cyclone Final Cyclone Final Cyclone III LS Final Cyclone IV GX Final HardCopy II HardCopy Compilation HardCopy III HardCopy Compilation HardCopy HardCopy C
18. at the start of the codeword set to 0 For example 204 188 is a shortened codeword of 255 239 Both of these codewords use the same number of check symbols 16 November 2012 Altera Corporation Chapter 3 Functional Description RS Encoder To use shortened codewords with the Altera RS encoder and decoder you use IP Toolbench to set the codeword length to the correct value in the example 204 Variable Encoding and Decoding RS Encoder Under normal circumstances the encoder and decoder allow variable encoding and decoding you can change the number of symbols per codeword N using sink eop but not the number of check symbols while decoding However you cannot change the length of the codeword if you turn on the erasure supporting option If you turn on the variable option you can vary the number of symbols per codeword using the numn signal and the number of check symbols using the numcheck signal in real time from their minimum allowable values up to their selected values even with the erasures supporting option turned on Table 3 7 on page 3 10 shows the variable option signals The sink sop signal starts a codeword sink eop signals its termination An asserted sink val indicates valid data The sink sop is only valid when sink valis asserted Only assert sink val clock cycle after the encoder asserts sink ena By de asserting sink ena the encoder signals that it cannot sink more incoming symbol
19. ata ready and valid signals The Avalon ST interface can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels The Avalon ST interface inherently synchronizes multi channel designs which allows you to achieve efficient time multiplexed implementations without having to implement complex control logic November 2012 Altera Corporation Chapter 3 Functional Description 3 7 Parameters The Avalon ST interface supports backpressure which is a flow control mechanism where a sink can signal to a source to stop sending data The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when there is congestion on its output When designing a datapath which includes the RS MegaCore function you may not need backpressure if you know the downstream components can always receive data You may achieve a higher clock rate by driving the source ready signal source ena of the RS high and not connecting the sink ready signal sink ena For more information about the Avalon ST interface refer to the Avalon Interface Specifications Figure 3 6 shows the RS encoder and decoder Avalon ST interfaces Figure 3 6 Avalon ST Interface RS Encoder or Decoder Sink Source ena ta sink_ena source_ena Vi User Module Sop P sink val source val User Module Source sink sop source sop J Sink
20. cify your variation name to match the Quartus II project name November 2012 Altera Corporation Reed Solomon Compiler User Guide 2 10 Chapter 2 Getting Started Compile the Design 2 Check that the absolute path to your third party simulator executable is set On the Tools menu click Options and select EDA Tools Options 3 On the Processing menu point to Start and click Start Analysis amp Elaboration 4 On the Tools menu click Tcl scripts Select the the variation name nativelink tcl Tcl script and click Run Check for a message confirming that the Tcl script was successfully loaded 5 On the Assignments menu click Settings expand EDA Tool Settings and select Simulation Select a simulator under Tool Name 6 On the Tools menu point to EDA Simulation Tool and click EDA RTL Simulation Compile the Design You can use the Quartus II software to compile your design Refer to Quartus Help for instructions on performing compilation Program a Device Reed Solomon Compiler User Guide After you have compiled your design program your targeted Altera device and verify your design in hardware With Altera s free OpenCore Plus evaluation feature you can evaluate an RS MegaCore function before you purchase a license OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time limited programming file For more information about IP functional simulation models refer to the
21. d must be disregarded To determine whether new data has been received the sink interface qualifies the sink val signal with the previous state of the sink ena signal sink sop sop Input Start of packet codeword signal sop delineates the codeword boundaries on the rsin bus When sink_sop is high the start of the packet is present on the rsin bus sink_sop is asserted on the first transfer of every codeword sink eop Input End of packet codeword signal sink eop delineates the packet boundaries on the rsin bus When sink eop is high the end of the packet is present on the aat bus sink eop is asserted on the last transfer of every packet rsin m 1 data Input Data input for each codeword symbol by symbol Valid only when sink val is asserted eras sym data Input When asserted the symbol in rsin is marked as an erasure Valid only for the decoder with Erasures supporting decoder option Table 3 6 shows the Avalon ST source data output interface Table 3 6 Avalon ST Source Interface Part 1 of 2 Avalon ST Direction Description Data transfer enable signal source ena is driven by the sink interface and controls the flow of data across the interface ena behaves as a read enable from sink to source When the source interface observes source ena asserted on the clk rising edge it drives on the following clk rising edge
22. ily Support ssa e by SEHR Petia th oye ae Par ye vel baec ae da 1 2 Performance and Resource Utilization s ra rense i e een eee 1 3 Installation and Licensing eb epe rr ERR eer ER eee eee ts 1 5 OpenCore Plus Evaluation ota E oes dtes studiato uai sede les bap tei 1 6 OpenCore Plus Time Out Behavior eene 1 6 Chapter 2 Getting Started Desin LOWS seca R 2 1 DSP Builder Ce pene peer pe hee Pauper egets 2 1 MegaWizard Plug In Manager Flow ssssssseeseee 2 2 Parameterize the MegaCore Function enn 2 3 Set Simulation s erae ded Ep ae Reate quete peque 2 6 Generate the MegaCore Function enn 2 7 Simulate the Design issu etie ce pepe 2 9 Compile the D Sigfi i i5 Leider eH E e de die atn 2 10 Programa Device uses esce sot qb te n cto ir Re e ero eene eon RR etc Re o td 2 10 Chapter 3 Functional Description Background tod dat lhe died lad Ede e dae ER Eee he Hbri edad 3 1 I3 M RR 3 2 Shortened Codewords osc is be 3 2 Variable Encoding and Decoding 2 3 3 RS Encoder E EC M TT 3 3 RS Decoder eroriren e ee edendum mM EE I md UEM ED a
23. in your model to display the RS Compiler parameter editor and parameterize your RS Compiler variation For an example of setting parameters for the RS Compiler refer to Parameterize the MegaCore Function on page 2 3 4 Click Finish in the parameter editor to complete the parameterization and generate your RS Compiler MegaCore function variation For information about the generated files refer to Table 2 1 on page 2 8 5 Connect your RS Compiler MegaCore function variation to the other blocks in your model November 2012 Altera Corporation Reed Solomon Compiler User Guide 2 2 Chapter 2 Getting Started MegaWizard Plug In Manager Flow 6 Simulate the MegaCore function variation in your DSP Builder model T For more information about the DSP Builder flow refer to the Using MegaCore Functions chapter in the DSP Builder User Guide 57 When you are using the DSP Builder flow device selection simulation Quartus compilation and device programming are all controlled in the DSP Builder environment DSP Builder supports integration with SOPC Builder using Avalon Memory Mapped Avalon MM master slave and Avalon Streaming Avalon ST source sink interfaces Ta For more information about the Avalon MM and Avalon ST interfaces refer to the Avalon Interface Specifications MegaWizard Plug In Manager Flow The MegaWizard Plug in Manager flow allows you to customize a RS Compiler MegaCore function and manually i
24. ion Data MegaCore function variation file which defines a VHDL top level description of the custom MegaCore function Instantiate the entity defined by rs_O vhd npe aay this file inside of your design Include this file when compiling your design in PES MegaCore Function Generation successful Table 2 1 describes the generated files and other files that may be in your project directory The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL Table 2 1 Generated Files Part 10f2 7 Filename Description Quartus symbol file for the MegaCore function variation You can use this file in the Quartus block diagram editor variation name or vho VHDL or Verilog HDL IP functional simulation model A MegaCore function variation file which defines a VHDL Verilog HDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus software A VHDL component declaration for the custom MegaCore function Add variation name cmp the contents of this file to any VHDL architecture that instantiates the MegaCore function Tcl Script that sets up NativeLink in the Quartus Il software to natively simulate the design using selected EDA tools variation name syn v or
25. is the variation name 2 After you review the generation report click Exit to close IP Toolbench Then click Yes on the Quartus II IP Files prompt to add the qip file describing your custom MegaCore function to the current Quartus II project Refer to the Quartus II Help for more information about the MegaWizard Plug In Manager You can now integrate your custom variation into your design and simulate and compile Simulate the Design IP Toolbench generated Tcl scripts drive the simulation For the decoder the testbench includes a channel and the instantiated decoder Data is read from an IP Toolbench generated file For the encoder the testbench reads the same data file and just compares the encoder output with a data file In the channel some errors are introduced at various locations of the RS codeword The testbench then receives the data decoded by the RS decoder and compares it with the originally transmitted data You can perform a simulation in a third party simulation tool from within the Quartus II software using NativeLink For more information about NativeLink refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook You can use the Tcl script file variation name nativelink tcl to assign default NativeLink testbench settings to the Quartus II project To set up simulation in the Quartus II software using NativeLink follow these steps 1 Createa custom variation but ensure you spe
26. ized testbench and customized Tcl script November 2012 Altera Corporation Reed Solomon Compiler User Guide DSP Builder ready Chapter 1 About This Compiler Release Information m IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators m Support for OpenCore Plus evaluation Release Information Table 1 1 provides information about this release of the Reed Solomon RS Compiler Table 1 1 RS Compiler Release Information Item Description Version 12 1 Release Date November 2012 IP RSENC Encoder Ordering Codes IP RSDEC Decoder 0039 0041 Encoder Product IDs 0080 0041 Decoder Vendor ID 6AF7 72 For more information about this release refer to the MegaCore IP Library Release Notes and Errata Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release Device Family Support Table 1 2 defines the device support levels for Altera IP cores Table 1 2 Altera IP Core Device Support Levels FPGA Device Families Preliminary support the IP core is verified with preliminary timing models for this device family The IPcore meets all functional requirements but might still be undergoing timing
27. l has been corrected The value of rserr shows which bits of the symbol have been corrected For each bit of rserr that is 1 the corresponding bit of rsout is corrected The rsout and the corresponding rserr value appear at the output at the same clock cycle Bit Error Count Interfaces Reed Solomon Compiler User Guide The decoder can provide the bit error count found in the correction process The bit error count has the following options m Fullcount The output num err bitis connected which shows the valid value m Split count The outputs num err bit0 and num err _bit1 are connected which show the valid values For information about these outputs refer to Table 3 8 on page 3 10 The RS encoder and decoder use the Avalon Streaming Avalon ST interface for data input and output The input is an Avalon ST sink and the output is an Avalon ST source The Avalon ST interface READY LATENCY parameter is set to 1 The Avalon ST interfaces allow for flow control The Avalon ST interface is an evolution of the Atlantic interface The Avalon ST interface defines a standard flexible and modular protocol for data transfers from a source interface to a sink interface and simplifies the process of controlling the flow of data in a datapath The Avalon ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries Such interfaces typically contain d
28. n modes m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely November 2012 Altera Corporation Chapter 1 About This Compiler 1 7 Installation and Licensing megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior might be masked by the time out behavior of the other megafunctions The untethered time out for a R5 Compiler MegaCore function is one hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires and the data output rsout remains low November 2012 Altera Corporation Reed Solomon Compiler User Guide Reed Solomon Compiler User Guide Chapter 1 About This Compiler Installation and Licensing November 2012 Altera Corporation DTE 2 Getting Started Design Flows The RS Compiler supports the following design flows m DSP Builder Use this flow if you want to create a DSP Builder model that includes a RS Compiler variation m MegaWizard Plug In Manager Use this flow if you would like to create a RS Compiler variation that you can instantiate manually in your design This chapter describes how y
29. ncoder 8 204 32 1 650 581 365 2 923 Notes to Table 1 5 1 The number of bits per symbol m 2 The number of symbols per codeword M 3 The number of check symbols per codeword R Reed Solomon Compiler User Guide November 2012 Altera Corporation Chapter 1 About This Compiler Installation and Licensing Table 1 6 shows the typical performance using the Quartus II software for Stratix IV EP4SGX70DF29C2X devices Table 1 6 Performance Stratix IV Devices Parameters Memory ALUTS Logic fmax Throughput Options Keysize p STANS uu Registers ALUTs M9K MHz Mbps Standard decoder Half 4 15 6 426 382 8 3 413 387 Standard decoder Half 8 204 16 1 220 1 034 64 3 368 2 945 Split bit error decoder Half 8 204 16 1 273 1 092 64 3 340 2 719 Full bit error decoder Half 8 204 16 1 255 1 092 64 3 325 2 603 Standard decoder Half 8 255 32 2 100 1 713 64 3 324 2 038 Variable decoder Half 8 204 16 1 362 1 119 64 3 356 2 850 Erasures decoder Half 8 204 16 2 170 1 596 64 3 314 2 510 Fraswesandvarabe War 8 204 16 2922 1746 9 3 310 2480 Standard encoder 8 204 16 204 210 620 4 960 Variable encoder 8 204 16 TIT 313 387 3 099 Variable encoder 8 204 32 1 651 582 347 2 775 Notes to Table 1 6 1 The number of bits per symbol m 2 The number of symbols per codeword
30. ntegrate the MegaCore function variation in a Quartus design Follow the steps below to use the MegaWizard Plug in Manager flow 1 Create a new project using the New Project Wizard available from the File menu in the Quartus II software 2 Launch MegaWizard Plug in Manager from the Tools menu and select the option to create a new custom megafunction variation Figure 2 1 Figure 2 1 MegaWizard Plug In Manager 4 MegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions Which action do you want to perform Create a new custom megafunction variation Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright C 1991 2010 Altera Corporation Cancel 3 Click Next and select Reed Solomon lt version gt from the DSP gt Error Detection Correction section in the Installed Plug Ins tab Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 2 Getting Started MegaWizard Plug In Manager Flow 2 3 4 Verify that the device family is the same as you specified in the New Project Wizard 5 Select the top level output file type for your design the wizard supports VHDL and Verilog HDL 6 The MegaWizard Plug In Manager shows the project path that you specified in the New Project Wizard Append a variation name for the MegaCore function
31. o receive update notifications for Altera documents Reed Solomon Compiler User Guide November 2012 Altera Corporation Additional Information s Typographic Conventions November 2012 Altera Corporation Reed Solomon Compiler User Guide Additional Information Typographic Conventions Reed Solomon Compiler November 2012 Altera Corporation User Guide
32. omon Compiler User Guide 3 8 Chapter 3 Functional Description Signals Table 3 3 shows the RS codeword parameters Table 3 3 RS Codeword Parameters Range Parameter Range Continuous Description Number of bits per 3to 12 6 to 12 Specifies the number of bits per symbol m symbol Number of symbols per a m4 Specifies the total number of symbols per codeword RUM eee codeword Number of check symbols 7 Specifies the number of check symbols per codeword Me TI codeword Specifies the primitive polynomial defining the 1 Field polynomial Any valid polynomial Galois field First root of generator 010 2v 2 Specifies the first root of the generator polynomial polynomial h Root spacing in generator 1 Specifies the minimum distance between roots in polynomial AI valid Rod apang the generator polynomial a Notes to Table 3 3 1 IP Toolbench allows you to select only legal values For m 8 not all legal values of the field polynomials and rootspace are present in IP Toolbench If you cannot find your intended field polynomial or rootspace in the IP Toolbench list contact Altera MySupport Signals Table 3 4 shows the global signals Table 3 4 Global Signals Name Description clk clk is the main system clock The whole MegaCore function operates on the rising edge of clk Reset The entire decoder is asynchronously rese
33. ompilation HardCopy IV GX HardCopy Compilation Stratix Final Stratix Final Stratix I GX Final Stratix Final Stratix IV GT Final Stratix IV GX E Final Stratix V Preliminary Stratix GX Final Other device families No support Performance and Resource Utilization Table 1 4 shows the typical performance using the Quartus II software for Cyclone III EP3C10F256C6 devices gt Table 1 4 Performance Cyclone Ill Devices Part 1 of 2 Cyclone III devices use combinational look up tables LUTs and logic registers Stratix III and Stratix IV devices use combinational adaptive look up tables ALUTs and logic registers Parameters LUTs Logic Memory fmax Throughput Options Keysize u Registers MHz Mbps Standard decoder Half 4 15 6 541 365 5 230 216 Standard decoder Half 8 204 16 1 720 995 5 202 1 613 November 2012 Altera Corporation Reed Solomon Compiler User Guide Table 1 4 Performance Cyclone Ill Devices Part 2 of 2 Chapter 1 About This Compiler Performance and Resource Utilization Parameters LUTs Logic Memory fmax Throughput Options Keysize yg symbols gc Registers MHz Mbps Split bit error decoder Half 8 204 16 1 765 1 057 5 194 1 552 Full bit error decoder Half 8 204 16 1 778 1 058 5 190 1 519 Standard decoder Half 8 255 32
34. ou can use a RS Compiler in either of these flows The parameterization provides the same options in each flow and is described in Parameterize the MegaCore Function on page 2 3 After parameterizing and simulating a design in either of these flows you can compile the completed design in the Quartus II software DSP Builder Flow Altera s DSP Builder product shortens digital signal processing DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm friendly development environment DSP Builder integrates the algorithm development simulation and verification capabilities of The MathWorks MATLAB and Simulink system level design tools with Altera Quartus II software and third party synthesis and simulation tools You can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore function variation blocks to verify system level specifications and perform simulation In DSP Builder a Simulink symbol for the MegaCore function appears in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library browser To use the RS Compiler in the MATLAB Simulink environment follow these steps 1 Create a new Simulink model 2 Select the reed_solomon_ lt version gt block from the MegaCore Functions library in the Simulink Library Browser add it to your model and give the block a unique name 3 Double click on the reed_solomon_ lt version gt block
35. p to a maximum value set by the parameter variable option numcheck 5 only The decoder samples numcheck only when sink sop is asserted Variable value of N Can be any value from the minimum allowable value of N up to the selected value of M numn variable and erasures supporting option only The decoder samples numn only when sink sop 15 asserted Table 3 8 shows the status signals decoder only Tahle 3 8 Status Signals Name decfail Description Indicates non correctable codeword Valid when source sop is asserted Avalon ST type err num err sym Number of symbols errors Valid when source sop is asserted invalid when decfail is asserted num err bit Number of bits errors corrected in the codeword Valid when source sop is asserted invalid when decfail is asserted Connected only when the Bit error Full count option is turned on Refer to RS Decoder on page 3 4 num err bit0 Number of bit errors for the corrections from bit 1 to bit 0 The latest is the correct bit Valid when source is asserted invalid when decfail is asserted The decoder presents these values at the next source sop assertion at the next codeword Connected only when the Bit error Split count option is turned on num err bitl Number of bit errors for the corrections from bit 0 to bit 1 The latest is the correct bit Valid when sop source is asserted invalid when decfail is asserted The decoder presents the
36. r Guide Info 2 Additional Information Typographic Conventions Contact software licensing Contact Method Email Address authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets lt gt For example file name and lt project name gt poft file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port
37. rd party IP cores altera Contains the Altera MegaCore IP Library L common __ Contains shared components reed solomon Contains the Reed Solomon Compiler files 7 lib Contains encrypted lower level design files OpenCore Plus Evaluation With Altera s free OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPPSM megafunction within your system m Verify the functionality of your design as well as evaluate its size and speed quickly and easily Generate time limited device programming files for designs that include megafunctions m Program a device and verify your design in hardware You only need to purchase a license for the 5 Compiler when you are completely satisfied with its functionality and performance and want to take your design to production After you purchase a license you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative For more information about OpenCore Plus hardware evaluation refer to AN320 OpenCore Plus Evaluation of Megafunctions OpenCore Plus Time Out Behavior Reed Solomon Compiler User Guide OpenCore Plus hardware evaluation supports the following operatio
38. rporation Reed Solomon Compiler User Guide 2 4 Chapter 2 Getting Started MegaWizard Plug In Manager Flow 1 Click Step 1 Parameterize in IP Toolbench Figure 2 3 on page 2 4 Figure 2 3 IP Toolbench Parameterize Reed Solomo m x T Aboutthis Core Documentation Step 1 n Step 2 Set Up Simulation fe Step 3 Q Generate 2 Select Encoder or Decoder Figure 2 4 Reed Solomon Compiler Figure 2 4 Select the Encoder or Decoder r Parameterize Reed Solomon Compiler SEE Function Output decoder options Encoder Error symbol Split count Decoder Bit error Full count Options Keysize Erasures supporting decoder Full C variable 3 If you select Encoder you can also turn on the Variable option For more information about the variable option refer to Variable Encoding and Decoding on page 3 3 Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 2 Getting Started 2 5 MegaWizard Plug In Manager Flow 4 If Decoder is selected the following controls are available a Youcan turn on the Erasures supporting decoder or Variable options b You can select Full or Half keysize You can turn on the Error Symbol or Bit Error outputs For the bit error output you can select Split Count or Full Count For more information about these parameters refer to Table 3 2 on page 3 7 5 Click Next 6 Selec
39. s after sink eopis signalled at the input During this time it is generating the check symbols for the current codeword Figure 3 2 shows the operation of the RS encoder The example shows a codeword with eight information symbols and five check symbols Figure 3 2 Encoder Timing clk sink ena 4 sink val sink sop sink eop Source ena E Source val Source sop Source eop rsout 8 1 ammEEEcscepssmm E 15 2 The numcheck input is latched inside the encoder when sink sop is asserted November 2012 Altera Corporation Reed Solomon Compiler User Guide 3 4 Chapter 3 Functional Description RS Decoder You can change the number of symbols in a codeword at run time without resetting the encoder You must make the changes between complete codewords you cannot change numcheck during encoding Figure 3 3 shows variable encoding Figure 3 3 Variable Encoding skea sinkval i i jf sink sop sink eop OP P IF rsin 8
40. se models allow fast functional simulations of IP using industry standard VHDL and HDL simulators You may only use these simulation model output files for simulation purposes and expressly notfor synthesis or any other purposes Using these models for synthesis will create a non functional design Ifyou are synthesizing your design with a third party EDA synthesis tool you can generate a netlistfor the synthesis tool to estimate timing and resource usage for this megafunction Generate the MegaCore Function To generate your MegaCore function follow these steps November 2012 Altera Corporation Reed Solomon Compiler User Guide 2 8 Chapter 2 Getting Started MegaWizard Plug In Manager Flow 1 Click Step 3 Generate in IP Toolbench Figure 2 3 on page 2 4 The generation phase may take several minutes to complete The generation progress and status is displayed in a report window Figure 2 8 shows the generation report Figure 2 8 Generation Report 9 Generation Reed Solomon Compiler Entity Hame Variation HDL Output Directory c mydesignss_examples File Summary The interface is creating the following files in the output directory File Description rs_0_testbench vhd Testbench File rs vsim script tcl TCL Script rs 0 nativelink tcl TCL Script for nativelink simulation rs D encoded datatxt Testbench Simulation Data rs O block period stimtxt Testbench Simulat
41. se values at the next source sop assertion at the next codeword Connected only when the Bit error Split count option is turned on Throughput Calculator Reed Solomon Compiler User Guide The IP Toolbench throughput calculator decoder only uses the following equation Throughput in megasymbols per second N x frequency MHz Nc For Mbps multiply by the number of bits per symbol November 2012 Altera Corporation Chapter 3 Functional Description Throughput Calculator Table 3 9 shows the value of Table 3 9 Calculate Ng 3 11 Erasures Keysize Me No Half Max N 10 x R 4 No Full Max N 7 x R 5 Yes Half N 10 x R 4 6 Yes Full Max 8 x R 4 November 2012 Altera Corporation Reed Solomon Compiler User Guide 3 12 Chapter 3 Functional Description Throughput Calculator Reed Solomon Compiler November 2012 Altera Corporation User Guide A Using the RS Encoder or Decoder in a JAN OTS RAN CCSDS System Introduction The Reed Solomon RS encoder or decoder MegaCore functions work in canonical base otherwise known as conventional base This base can cause confusion when trying to implement the RS encoder or decoder directly into a dual base system for example when working with the Consultative Committee for Space Data Systems CCSDS standard To transfer from a canonical base to a dual base system a Berlekamp transform is used which
42. storage retrieval and transmission of data The RS Compiler has the following options Erasures supporting option the RS decoder can correct symbol errors up to the number of check symbols if you give the location of the errors to the decoder Refer to Erasures on page 3 2 Variable encoding or decoding you can vary the total number of symbols per codeword and the number of check symbols in real time from their minimum allowable values up to their selected values when you are encoding or decoding Error symbol output the RS decoder finds the error values and location and adds these values in the Galois field to the input value Bit error output either split count or full count The Altera Reed Solomon Compiler supports the following features High performance encoder decoder for error detection and correction Fully parameterized RS function including m Number of bits per symbol m Number of symbols per codeword m Number of check symbols per codeword m Field polynomial m First root of generator polynomial m Space between roots in generator polynomial Decoder features m Variable option m Erasures supporting option Encoder features variable architectures Support for shortened codewords Conforms to Consultative Committee for Space Data Systems CCSDS Recommendations for Telemetry Channel Coding May 1999 Easy to use IP Toolbench interface m Generates parameterized encoder or decoder m Generates custom
43. t the parameters that define the specific RS codeword that you wish to implement Figure 2 5 Figure 2 5 Choose the Parameters 9 Parameterize Reed Solomon Compiler EEA Number of bits per symbol Number of symbols per codeword Number of check symbols per codeword Field polynomial First root of polynomial generator Root spacing in generator polynomial Preset choices You can enter the parameters individually or click DVB Standard to use digital video broadcast DVB standard values or CCSDS Standard to use the CCSDS standard values For more information about these parameters refer to Table 3 3 on page 3 8 7 Click Next November 2012 Altera Corporation Reed Solomon Compiler User Guide 2 6 Chapter 2 Getting Started MegaWizard Plug In Manager Flow 8 For a decoder throughput calculation enter the frequency in MHz select the desired units and click Calculate Figure 2 6 shows the decoder throughput calculation page Figure 2 6 Throughput Calculator r Parameterize Reed Solomon Compiler Throughput calculation For decoder Display throughput in Megasymbols second Megahits second Enter clock frequency MHz Calculate Cancel Prev For more information about the throughput calculator refer to Throughput Calculator on page 3 10 9 Click Finish For more information about the RS Compiler parameters refer to Parameters on page 3 7 Set Up
44. t when reset is asserted high The reset signal resets the entire system The reset signal must be de asserted synchronously with respect to the rising edge of clk Reed Solomon Compiler November 2012 Altera Corporation User Guide Chapter 3 Functional Description Signals 3 9 Table 3 5 shows the Avalon ST sink data input interface Table 3 5 Avalon ST Sink Interface sink ena Avalon ST Type ena Direction Output Description Data transfer enable signal sink ena is driven by the sink interface and controls the flow of data across the interface sink ena behaves as a read enable from sink to source When the source observes sink ena asserted on the clk rising edge it drives on the following c1k rising edge the Avalon ST data interface signals and asserts val if data is available The sink interface captures the data interface signals on the following c1k rising edge If the source is unable to provide new data it de asserts val for one or more clock cycles until it is prepared to drive valid data interface signals sink val val Input Data valid signal sink indicates the validity of the data signals sink val is updated on every clock edge where sink ena is asserted sink valandthe dat bus hold their current value if sink ena is de asserted When sink val is asserted the Avalon ST data interface signals are valid When sink val is de asserted the Avalon ST data interface signals are invalid an
45. the Avalon ST data Source ena ena Input interface signals and asserts source val when data from sink interface is available The sink interface captures the data interface signals on the following clk rising edge If this source is unable to provide new data it de asserts source val for one or more clock cycles until it is prepared to drive valid data interface signals m Output Data valid signal source_val is asserted high whenever there is a valid output on rsout it is de asserted when there is no valid output on rsout Source sop sop Output Start of packet codeword signal Source eop eop Output End of packet codeword signal November 2012 Altera Corporation Reed Solomon Compiler User Guide 3 10 Chapter 3 Functional Description Throughput Calculator Tahle 3 6 Avalon ST Source Interface Part 2 of 2 Avalon ST uis Name Type Direction Description ies Output The rsout signal contains decoded output when source val is asserted The corrected symbols are in the same order that they were entered idet Output id ao value decoder only optional Refer to Error Symbol Output on Table 3 7 shows the configuration signals Table 3 7 Configuration Signals Name Description CEN A one bit signal that sets if the codewords are bypassed or not decoder only The decoder continuously samples bypass Sets the variable number of check symbols u
46. you need to implement in logic Figure A 1 shows an example use of the Berlekamp transform Figure A 1 Using the Berlekamp Transform Pre transform Dual to Canonical Berlekamp RS Encoder Transform Canonical to Dual Channel Berlekamp Rs Den Post transform RS Decoder Dual Test Patterns If you are working with a dual base system for example CCSDS and wish to supply the RS encoder or decoder with some test patterns from the dual base system follow these steps 1 Apply the Berlekamp transform dual to canonical to the test pattern 2 Apply the test pattern to RS encoder or decoder 3 Apply the Berlekamp transform canonical to dual to the encoder output 4 Check the test pattern For more information about implementing the transformation function refer to Annex B of the standard specification document CCSDS 101 0 B 5 at www ccsds org November 2012 Altera Corporation Reed Solomon Compiler User Guide A 2 Reed Solomon Compiler User Guide Appendix A Using the RS Encoder or Decoder in a CCSDS System Test Patterns November 2012 Altera Corporation Additional Information This chapter provides additional information about the document and Altera Revision History The following table shows the revision history for this user guide Date Version Changes Made
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