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1. 4 C 2 CA Serial Port J14 wisn ened Sige eee ER E REPRE E EE E EE EN CER LET DE C 3 CS TelcoClock J17 siss ooetaetuswxuk C 3 C6 AMCBIRAMCB2 1208 123 C 4 7 ATCAT OATCA3 1 J21 bra Ea C 5 GB Power Ra ER Wa C 6 D BIOSSetup Error Codes eee id eds Del D 1 Initialization Code D 1 D 2 Bootblock Recovery Code Checkpoints D 2 D 3 POSTCodeCheckpoints 0 2 0 4 DIM 0 5 0 5 ACPI Runtime Checkpoints 0 6 0 6 Memory Initialization ERROR D 6 E Software Update REEF EE a E 1 Flash BIOS Update Procedure 1 2 IPMCFirmware Update 1 F Getting 1 F 1 Returning Defective
2. xiii Limited Warranty gt 0r I rae rye pa Ur xiv 1 Product Description o d 1 1 ProductOVerVieW 1 12 WhatsIncl ded 1 1 3 Board 5 5 1 1 4 Compliance E IER ER 3 1 5 Hot Plug 4 1 6 Interfacing with the Environment 4 1 6 1 RTM rear transition 4 16 2 Ped edu 4 2 Board aaa e Uds a D 2 1 BlockDiagram rera rp pe rs EEES 5 2 2 System CONC ERR EE ERES Ke S HS 6 2 2 1 PrOC SSOIS E Rr E ER RR 6 2 2 2 InteLE7520 Chipset DR RR MEETS 7 2 3 USB 2 0 1 2442555 e e Aw eS A RT 7 2 4 Onboard 5 lt 524 2 6 lt nh ne IRE 8 2 5 SeralPorts 12 5220
3. 16 2 15 Hardware 16 2 15 1 Hardware Management Overview 16 2 15 2 Sensor Data 5 0 17 2 15 3 50 5 Re Re CR RR ERE C 18 2 15 4 Events supported 4 isole Rr eR RS EE RE 23 2 15 5 Field Replaceable Unit FRU Information 24 2 15 6 Over LAN IOL 2 1 7 35 2 15 7 Serial Over LAN support 501 37 2 15 8 37 2 15 9 Updating the 8020 0 37 2 15 10 1 lt 38 2 15 11 Commands 9m RR ey Ly 44 2 15 12 5 Processi te e hm bre RR EE ena 47 2 16 Deb gging were E RE ES t ET 51 2 16 1 5 51 3 the oer oos Doi Roc Po eh lcu we o RI bo ew 3 1 Setting JOMPpers 52 6
4. 59 4 1 1 wees ER ERU e AERA 59 4 1 2 10 P a 60 4 1 3 External Storage Devices 2 60 4 1 4 Power Supply EU eR E ERE EP RE 60 4 1 5 Mechanical Keying and 60 5 Software Setup 5 1 Setup 61 5 1 1 Accessing the BIOS Setup 61 5 1 2 L 63 5 1 3 Menu P ERE RR CERE AE 65 5 122 Advanced MEN PP PER 65 5 1 5 Security Menu eser pk RP ER AREE 77 5 1 6 Boot Men iiiaae aia a a eaa 78 5 1 7 System Management 79 5 1 8 Exit Men TE 82 5 2 BootUtiliti s ss sene rA 83 5 2 1 Pressing Del or F4 from a Console Redirection 83 5 2 2 Pressing lt F11 gt or F3 from a Console Redirection terminal 83 5 0 3 BOOT Menu POP
5. 52 3 1 1 Jumper Description 1 4 1 52 3 1 2 Setting Jumpers amp Locations 52 3 2 550 225 REPE EAS TE ES 53 3 3 Memory 53 3 3 1 Memory 5 55 iii AT8020 www kontron com Table of Contents 3 4 Onboard Interconnectivity and 56 3 441 Onboard Connectors and 56 3 4 2 Front Plate Symbol Chart 5 556 56 3 5 Board Hot Swap and Installation 57 3 5 1 Installing the Board in the 5515 57 3 5 2 Removing the Board Rr re REIR E Ee 3 57 3 5 3 Instalingan AMC c i mr hake oe awe 58 3 5 4 Removingan 12 58 3 5 5 Instal nga RTM m 58 3 5 6 Removing SA ene Eee e I eee SG 58 4 Building an ATCA System nh Race oh 59 4 1 Buildingan
6. 1 F2 When Returning 2 www kontron com v AT8020 List of Figures List of Figures Figure 2 1 Block Diagram URS NR E RE DU ER 5 Figure 3 1 Setting Jumpers amp Locations 4 52 Figure 3 2 Memory Installation 55 Figure 3 3 Front Plate Symbol Chart REY 56 Figure 4 1 ATUS 185515 unie eR REOR RO ese 59 vi AT8020 www kontron com List of Tables List of Tables Table 1 1 Board 5 1 1 1 1 2 1 Table 2 1 USB Connector Pinout 8 Table 2 2 Serial Ports Communication Mode and Output Path 8 2 3 Serial PortPinout J5 3 08455 aise sabes oes REX RETE E deen ad Shee pla 9 Table 2 4 AMC Ports Mapping 1 13 Table 2 5 AMC Ports Mapping 2 14 Table 2 6 5 5016 252 52 4 Ae 18 Table 2 7 Sensor bance eR RR EU
7. S 23 Table 2 8 Type 14 Atca Board Point To Point Connectivity Record 25 Table 2 9 17 Carrier Activation And Current Management Record 26 Table 2 10 18 Carrier Point To Point Connectivity 27 Table 2 11 19h AMC Point To Point Connectivity Record 1 of 4 MCH PCI Express PortC 29 Table 2 12 Type 19h AMC Point To Point Connectivity Record 2 of 4 MCH PCI Express PortB 30 Table 2 13 Type 19h AMC Point To Point Connectivity Record 3 of 4 Xpoint GbE 32 Table 2 14 19h AMC Point To Point Connectivity Record 4 33 Table 2 15 1Ah Carrier Information Table 1 35 Table 2 16 IPMI Over Lan Default 36 Table 2 17 Commands 2 2 38 Table 2 18 Commands 44 Table 2 19 Reset BIOS 1 44 2 20 Set Control SMe cc Rn eeu 44 Table 2 21 Get Control State 45 Table 2 22 GetBoardDeviceChannelPortSelection 45 Table 2 23 SetBoardDevice
8. ET T e 8 2 5 1 S nal Port 1 J5 8 2 5 2 SenalPort2 ER ROS 9 ii AT8020 www kontron com Table of Contents 26 Real time Clock amp NURAM RR REUS E EGET IRR sake ERE UR een 9 2 7 EthernetInterfacaS E 10 2 7 1 1825510 Ethernet 10 2 7 2 182571 Base 10 2 7 3 182571 Fabric Interface 0 1 11 2 7 4 182571EB Fabric Interface Port 1 Daughter Card 11 2 8 SAS Daughter Card 5 5 ks 4 Ra RR RH 11 2 9 CrosspointSwitches 12 2 10 AMC 12 2 10 1 AMC Ports Mapping 1 13 2 10 2 AMC Ports Mapping 2 14 2 11 Redundant BIOS Flash 15 2 12 Redundant IPMC Flash amp FWUM 15 2 13 GAS RAE 15 2 14 Telecom Clock Option
9. Read Postcode 80 81h Write Postcode Reset 00h Postcodes Postcodes are captured in this register as they are written Be careful postcodes are not always 16 bit The high byte in register 81h could be unrelated to the content of register 80h Also the legacy floppy disk controller if any MUST be disabled The LPC bridge in this design does a full decode and cycle acknowledge 1 0 81h and this will conflict with any other resources that decodes this address B 2 AT8020 www kontron com 2 3 AOOh Version Address Action 07 05 04 03 02 01 00 Write Reset Customer MajorVersion B 2 4 Customer MajorVersion NU NU NA NA Customer identification 000 generic Kontron board 001 customer 1 additional customer only registers are present others reserved FPGA major version For the production test software to verify that the latest code was used in the JTAG programming phase i e trap production mistakes See also LPC A04h for minor version 01 Debug LED amp Mfg flag oo 01 Write Reset MfgFlag MfgFlag 0 MfgFlag NU NU NU NU NU NU NU 0 NA NA NA NA NA NA NA NA A memory element used by the BIOS and test software in manufacturing Note This bit is cleared power up but is not affected by reset
10. Software Setup 5 1 4 4 2 Primary IDE Master Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Primary IDE Slave Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the device is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDMAn UltraDMAn Enable Disabled 32 bit Data Transfer 69 AT8020 ron com Software Setup 5 1 4 4 3 Secondary IDE Master Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Secondary IDE Master Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled
11. 2 10 07 BOM version 01 facon 0 7 BOM6 5 BOM4 BOM3 BOM2 07 Write NU NU NU NU NU NU Reset NU NU NU NU NU NU BOM 7 0 BOM Version Spare bit may be redefined for other use 7 6 5 4 3 2 1 0 X X X X X X X 1 Flash Drive presence 1 X Management LAN presence X X X X20 1 X X Reserved X X x X 1 X X FMLInterface used BOM1 NU NU BOMO NU NU B 6 AT8020 www kontron com 0 X Reserved X X 0 X X X X X Reserved X Reserved 0 X X X X X X X Reserved Note A The FPGA IPMC must adapt to the fact that there is no 5V rail Note A The telecom clock functionality has an entire byte to specify the configuration or absence return FF of the circuit B 2 11 3 A08h T2604 Mezzanine Flash BIOS EEPROM Control Address e p ps pre pi EEWP NU NU NU NU ID Read 0 TestMode HIDE 08 Write EEWP NU NU NU NU NU NU HIDE Reset Iz NU NU NU NU NU N A 0 not cleared a reset power up only EEWR Serial EEPROM write protect 1 write protected 0 unprotected An equivalent bit exists in the IPMC address space The EEPROM is not protected if either the BIOS or the IPMC wants to access it IDO Indicate the current state of FWHs IDO input When 1 a T2604 is present and is the active FWH When cleared will always be cleared when HIDE
12. AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 Coh 02h N A N A N A 00315 gt PICMG Record ID 19h gt Point To Point Connectivity Record 00h 00h gt On Carrier device Device 0 PCI Express Port C 0111 0F18820h OFh 03h 02h 0111 00h 00102 00 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 015 00h gt Single Channel Link O1h gt Carrier Reference clock is spread spectrum 002h AMC 1 PCI Express OFOOh gt Channel 0 lane 0 1 2 and 3 AMC Link Descriptor 00002 00 h Reserved Bits 39 34 03Fh AMC Asymmetric Match Bits 33 32 211 This Carrier provides Secondary PCI Express Port Matches with 29 AT8020 www kontron com Board Features Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 1
13. 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 8086h 3590h 3591h 3594h 3595h 3596h 3597h 3598h 3599h 359Ah 359Bh 25Aeh 25A9h 25Aah 25Abh 25Ach 25Adh 25A1h 25A2h 25A1h 25A3h 25A4h 1209h 105Eh 0 1 0 E7520 Memory Controller Hub E7520 Memory Error Reporting E7520 DMA Controller E7520 Host to PCI Express A Bridge x8 or x4 E7520 Host to PCI Express A1 Bridge x4 only E7520 Host to PCI Express B Bridge x8 or x4 Support Hot Plug E7520 Host to PCI Express B1 Bridge x4 only E7520 Host to PCI Express C Bridge x8 or x4 Support Hot Plug E7520 Host to PCI Express C1 Bridge x4 only E7520 Extended Configuration Registers 16300ESB ICH HUB Interface to PCI X Bridge 16300ESB ICH USB UHCI Controller 1 16300ESB ICH USB UHCI Controller 2 16300ESB ICH Watchdog Controller 16300ESB ICH IOAPIC bus B 16300ESB ICH USB Controller 16300ESB ICH HUB Interface to PCI Bridge 16300ESB ICH LPC Interface 16300ESB ICH IDE Controller 16300ESB ICH Serial ATA Controller 16300ESB ICH SMBus Controller Intel Corporation 8255xLR 82551IT Fast Ethernet Controller Intel Corporation 82571EB Gigabit Ethernet Controller rev 06 Bridge host bridge multi function Bridge host bridge multi function System peripheral
14. Alt Modifier lt ESC gt A Control Modifier lt ESC gt C Home Key lt ESC gt h End Key lt ESC gt k Insert Key lt ESC gt Delete Key lt ESC gt Page Up Key lt ESC gt Page Down Key lt ESC gt These escape sequences are supported VT UTF8 compliant terminal connections such as Windows Server 2003 Emergency Management Services EMS AMIBIOSS Serial Redirection supports these key sequences under two configurations Terminal Type setup question is set to VT UTF8 Terminal Type setup question is set to VT100 or ANSI and VTUTF8 Combo Key Support setup question is set to Enabled 5 4 Installing Drivers Various drivers are provided for different operating systems and software To install a driver use the Setup program located on the CD DVD provided with your board For other operating system drivers and installa tion instructions or for more information visit our Web site at www kontron com or our FTP site at ftp kon tron ca support or you may also contact Kontron s Technical Support department 85 AT8020 WWW kontron com amp 1 0 A 1 Memory Mapping FFFFFh System BIOS E0000h 1MB to top of DRAM Optional ROM free LAN BIOS if activated 30KB See Note 2 m Fibre Channel SAS BIOS 7 if activated 18KB at runtime See Note 1 E 9 34 Optional ROM Free 5 See detailed 2 M
15. Note When RTM 1 the ICH second serial port will automatically be connected to the RTM B 2 6 AO3h BIOS to IPMC Mailbox Address Action 07 A03h Write Reset LN RN MI7 MI6 MI5 MI4 MI3 2 MIO MI7 MI6 MI5 MI2 MIO 0 0 0 0 0 0 0 0 Blade insertion only No reset after that 0 7 Message from BIOS to The state written here is copied to a register in the IPMC address space Readback by the BIOS is a local readback The IPMC can clear any of those bits by writing a 1 the corresponding IPMC register Definition of those bits is entirely left to the software Definitions may be copied here for convenience WWW kontron com B 4 AT8020 2 7 amp Development Features Se Re eS ELE eee eee Read Write Reset A04h MinorVersion SSCO 55 1 MinorVersion SSC1 SSCO NU NU NU NU NU NU SSC1 SSCO NU NU NU NU NU NU 1 1 Minor version that doesn t impact the IPMC For in house minor version tracking Special Serial Connection bit 0 Special Serial Connection bit 1 Those bits define special connections between serial devices that are meaningless to the end user They are development and or manufacturing facilities Leave those bits in their default state for end user operation 11 Normal operation no development tricks 01 Float FW RXD pin Use this to program the FWUM wi
16. Primary IDE Slave Secondary IDE Master Secondary IDE Slave Third IDE Master Fourth IDE Master Hard Disk Write Protect IDE Detect Time Out Thermal Management sub menu Enabled Disabled Enabled Disabled Enabled Disabled Enabled 1 in use Disabled TM1 not in use Use only for testing purposes Enabled TM2 in use Disabled TM2 not in use Use only for testing purposes Enabled DTS for each core is in use IDE Configuration sub menu Disabled P ATA Only S ATA Only P ATA amp S ATA This is a sub menu This is a sub menu This is a sub menu This is a sub menu This is a sub menu This is a sub menu Enabled Disabled 0 5 10 15 20 25 30 35 Select IDE Mode P ATA Only 4 P ATA amp 2 S ATA S ATA Only 2 S ATA P ATA amp S ATA 2 P ATA amp 2 S ATA While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE
17. Select the number of stop bits transmitted and received in each serial character Select flow control for console redirection Select the type of console emulation used N A Select terminal display mode Select if BIOS POST messages are duplicated in a separate reserved memory region for OS examination 79 AT8020 WWW k on com Software Setup LN M A 01 Channel Number p Channel Status x Invalid display IP Address N A MAC Address N A Subnet Mask N A Gateway Address N A Disabled Active LAN Channel 01 Number 02 Both LON RSS Set LAN Configuration Sub menu Enter Channel Number for SET LAN Config Command Proper value below 16 Enter for IP Address Configuration Enter for MAC Address Configuration Enter for Subnet Mask Configuration Enter for Gateway IP Address Configuration Enter Active LAN Channel Number for Set LAN Configuration Command Only one LAN Channel can be activated IP Configuration sub menu LAN Parameter Selector 03 Channel Number 53 Channel Status 217 Invalid display IP Address XXX XXX XXX XXX Current IP Address XXX XXX XXX XXX 5 1 7 4 N A Enter Channel Number for SET LAN Config Command Proper value below 16 N A Enter IP Address in decimal in the form XXX XXX less than 256 and in decimal only N A MAC Address Configuration sub menu LAN Parameter Selector 05 N A 01 Enter Channel Number for SET LAN Config C
18. 9 2 Advanced GAE AT8020 1 3 15101 Document Rev December 2009 Y ntro 11 19 2 Revision History 1 0 First Release 11 Second Release 1 2 Third Release 1 3 Fourth Release Customer Service Contact Information Kontron Canada Inc 4555 Ambroise Lafortune Boisbriand Qu bec Canada J7H 0A4 Tel 450 437 5682 800 354 4223 Fax 450 437 8053 E mail support ca kontron com March 2007 May 2008 May 2009 December 2009 Kontron Modular Computer GMBH Sudetenstrasse 7 87600 Kaufbeuren Germany 49 0 8341 803 333 49 0 8341 803 339 support kom kontron com Visit our site at www kontron com 2009 Kontron an International Corporation All rights reserved The information in this user s guide is provided for reference only Kontron does not assume any liability arising out of the application or use of the information or products described herein This user s guide may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Kontron nor the rights of others Kontron is a registered trademark of Kontron All trademarks registered trademarks and trade names used in this user s guide are the property of their respective owners All rights reserved Printed in Canada This user s guide contains information proprietary
19. gt AMC Channel 0 lane 0 1 2 and 3 FE00102100 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h gt Single Channel Link gt Carrier Reference clock is spread spectrum 002h gt AMC 1 PCI Express 0100h gt AMC Channel 0 lane 0 FE00102F01 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h gt Single Channel Link 018 gt Carrier Reference clock is spread spectrum 002h gt AMC 1 PCI Express OFO1h gt AMC Channel 1 lane 0 1 2 and 3 FE00002F01 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h gt Single Channel Link gt Carrier Reference clock is not spread spectrum 002h AMC 1 PCI Express gt AMC Channel 1 lane 0 1 2 and 3 FE00102101 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 10157 00h gt Single Channel Link O1h gt Carrier Reference clock is spread spectrum 002h gt AMC 1 PCI Express 0101h gt Channel 1 lane 0 FE00002101 h 03Fh 31 AT8020 www kontron com Board Features AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h
20. gt AMC Channel 6 lane 0 00107106 03Fh 02h gt Implements SATA Client Interface 00h gt Single Channel link 018 gt Serial ATA 007h gt AMC 3 Storage 0106h gt AMC Channel 6 lane 0 FC00207107h 03Fh 020b Exact match gt Single Channel link 02h gt Serially Attached SCSI SATA 007h gt AMC 3 Storage 0107h gt Channel 7 lane 0 FE00107107h 03Fh 02h gt Implements SATA Client Interface gt Single Channel link O1h gt Serial ATA 007h gt AMC 3 Storage 0107h gt Channel 7 lane 0 34 AT8020 ron com Board Features 2 15 5 2 8 Type 1 Carrier Information Table Table 2 15 Type 1Ah Carrier Information Table Record Type ID Coh Record format version 02h Record Length N A Record Checksum N A Header Checksum N A Manufacturer ID 00315Ah PICMG Record ID PICMG Record ID 1Ah Carrier Information Table Record Format Version 00h 0 Extension Version O1h 0 R2 0 Carrier Site Number Count 02h Carrier Site Number 05h Carrier Site Number 06h 2 15 6 Over LAN IOL support The AT8020 provides IPMI Over LAN support over the 2 Ethernet connections of the base interface The 82571EB chip connected to the base interface is also connected to the IPMC The IPMI Over LAN solution is compatible with the IPMI 1 5 and IPMI 2 0 specification and support both RMCP and RMCP payload type It is also suppor
21. gt Single Channel Link 00h gt Carrier Reference clock is not spread spectrum 002h gt AMC 1 PCI Express 0101h gt AMC Channel 1 lane 0 2 15 5 2 6 Type 19h AMC Point To Point Connectivity Record 3 of 4 Xpoint GbE Table 2 13 Type 19h AMC Point To Point Connectivity Record 3 of 4 Xpoint GbE Record Type ID Record format version Record Length Record Checksum Header Checksum Manufacturer ID PICMG Record ID Record Format Version Record Type Connected device ID AMC Channel Descriptor Count AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Channel Descriptor Reserved Bits 23 20 Coh 02h N A N A N A 00315Ah gt PICMG Record ID 19h gt Point To Point Connectivity Record 00h O1h On Carrier device Device 2 Xpoint GbE 04h OFFFFEOh OFh 1Fh 1Fh 1Fh 00h OFFFFE1h OFh 1Fh 1Fh 1Fh 01 OFFFFE2h OFh 1Fh 1Fh 1Fh 02h OFFFFE3h OFh www kontron com 32 AT8020 Board Features
22. 1 indicate that an onboard FWH is active HIDE Hide T2604 flash When this bitis cleared the LPC Flash on the T2604 has an IDO of 0 and the flashes on the board will be forced to different addresses When this bit is set the T2604 flash will be at a higher ID From the board main CPU point of view this is almost like removing the T2604 This bit will be typically used to program its on board flash for the first time TestMode When set indicate that the alternate setup default manufacturing configuration must be used by the BIOS This bit reflects the presence of the jumper on the T2604 8 7 8020 WWW kontron com B 2 12 09 RTM PLD Version Read VALID RPLD3 RPLD2 RPLD1 RPLDO 09 Write NU NU NU NU NU NU NU NU Reset NU NU NU NU NU NU NU NU Valid When set indicate that field RPLD is valid RPLD 3 0 PLD Version B 2 13 A AOAh Reset History IEEE EIS Read LastReset Write NU NU NU NU NU NU NU NU Reset NU NU NU NU NU NU NU NU LastReset This value indicates the last reset that happened In case of multiple back to back resets only the last one is reported here Interpretation is as follow 0000 Reserved 0001 Power up 0010 Reserved Initial WD 0011 Reserved Prog wd cold 0100 Reserved Prog wd warm 0101 Software initiated cold reset ICH s CF9h write 0110 Software initiated warm reset ICH s CF9h write 0111 Co
23. 20 30 40 50 Waking from sleep state 51 52 53 54 or S5 D 6 Memory Initialization ERROR Code Eth Memory Error No memory installed E2h Memory Error Memory type mismatch E3h Memory Error Unsupported DIMM type E4h Memory Error Channel mismatch EAh Memory Error Memory timing error EEh Memory Error Memory unsupported size EFh Memory Error Memory population order Fih Memory Error DIMM configuration error F3h Memory Error Error code for unsuccessful Memory Test F4h Memory Error Error code for unsuccessful ECC and Memory Initialization F5h Memory Error Receive enable is busted so halt here D 6 AT8020 WWW k on com Software Update E 1 Flash BIOS Update Procedure The Flash BIOS update procedure is detailed in a ReadMe file included with the Flash BIOS package as well as the update utility This package can be downloaded from our website www kontron com or from our FTP site ftp ftp kontron ca Support 2 Firmware Update Procedure The IPMC Firmware update procedure is detailed in a ReadMe file included with the IPMC Firmware package as well as the update utility This package can be downloaded from our website http www kontron com or from our FTP site ftp ftp kontron ca Support E 1 AT8020 www kontron com F Getting Help If atany time you encounter difficulties with your application or with any of our products or if you simply need guidance on syste
24. B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 12V PS1 MP_3V3 GAO RSV GND RSV 12V GND RxDO GND GND GA1 12V GND RxD1 RxD1 GND TxD1 TxD1 GND GA2 12V GND RxD2 RxD2 GND TxD2 TxD2 GND RxD3 RxD3 GND TxD3 TxD3 AMC B1 8 B2 220 8 J23 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 GND B86 GND RxD4 RxD4 GND TxD4 TxD4 GND RxD5 RxD5 GND TxD5 TxD5 GND IPMB L SCL 12V GND RxD6 RxD6 GND TxD6 TxD6 GND RxD7 RxD7 GND TxD7 TxD7 GND IPMB_SDA 12V GND TCLKA TCLKA GND TCLKB TCLKB GND FCLKA FCLKA B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 08 TxD8 GND RxD8 RxD8 GND TxD9 TxD9 GND RxD9 RxD9 GND TxD10 TxD10 GND RxD10 RxD10 GND TxD11 TxD11 GND RxD11 RxD11 GND TxD12 TxD12 GND RxD12 RxD12 GND TxD13 TxD13 GND RxD13 RxD13 GND TxD14 TxD14 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B
25. XXXX 2 MB Enabled Disabled N A N A N A N A N A N A Enabled Processor virtualization in use Disabled Processor virtualization not in use Setting can only be changed after power ON After a reset or a soft reboot this option stay in grey and can not be changed Configures SpeedStep technology Configures thermal monitors SpeedStep Configuration sub menu Maximum Speed Minimum Speed Variable Speed Fixed Speed Disabled 1000 MHz here all supported speeds between LFM and HFM as supported by Intel 2000 MHz 2300 MHz later Enabled Enabled Disabled 1000 MHz here all supported speeds between LFM and HFM as Maximum CPU speed is set to maximum Minimum CPU speed is set to minimum Variable CPU speed is controlled by operating system Fixed CPU speed is set to fixed value Disabled Default CPU speed is used Minimum speed 1000 MHz Maximum speed 2000 MHz N A Enabled is in use for processor 0 and processor 1 i e both cores are available for both processors Disabled CMP is not used for either processor Minimum speed 1000 MHz supported by Intel Maximum speed 2000 MHz 2000 MHz 2300 MHz later Processor 1 Core 0 Enabled N A Enabled P 1 1 rocessor 1 Core Disabled 66 8020 www kontron com Software Setup 5 1 4 3 Thermal Monitor 1 Thermal Monitor 2 Digital Thermal Sensor 5 1 4 4 IDE Configuration Primary IDE Master
26. 0100 T5511 1000Base BX only mezzanine The FPGA will sequence the power supplies and grab various statuses from the mezzanine 1 0101 T5511 SAS amp 1000Base BX mezzanine The FPGA will sequence the power supplies and grab various statuses from the mezzanine 1 Others Reserved for now Removal of the mezzanine while the power is ON is an illegal operation 2 15 AOC AOFh Telcom Clock Interface Please refer to section B3 for more details on the actual configuration used B 9 AT8020 WWW kontron com 2 16 378 37Ah Xilinx DLC5 JTAG Programmer Emulator 378h LPT data register ERR el 8 2 16 1 378 Write Reset LD 7 0 LD7 LD6 LD5 104 103 0 0 0 0 0 LPT data write and readback Only subset of those pins has a physical implementation 102 0 101 0 NU NU LDO 0 NU NU B 2 16 2 379h LPT status register ESO Dr otn BUSY ACK SLCTI ERR IRQ 379h Write NU NU NU NU NU NU Reset NU NU NU NU NU NU BUSY Printer busy ACK Printer acknowledge Always return 1 no ack PE Printer out of paper paper empty SLCTI Select in ERR Error Interrupt status Always return 1 no interrupt B 2 16 3 37Ah LPT control register ee SlctO INIT ALF STRB 37Ah Write NU NU NU NU SlctO INIT STRB Reset NU NU NU NU 1 1 1 1 SLCTO Printer Sel
27. 0S Operating System PHYsical layer Generic electronics term referring to a special electronic integrated circuit or PHY functional block of a circuit that takes care of encoding and decoding between a pure digital domain on off and a modulation in the analog domain PICMG PCI Industrial Computer Manufacturers Group PICMG PCI Industrial Computer Manufacturers Group POST Power On Self Test prAMC Processor AMC RAID Redundant Array of Independent Disks Redundant Array of Inexpensive Disks RAM Random Access Memory RHEL Red Hat Enterprise Linux RoHS Restriction of the Use of Certain Hazardous Substances RS 232 Same as RS232 Recommended Standard 232 RS232 Same as RS 232 Recommended Standard 232 RTC Real Time Clock RTM Rear Transition Module RTM Link Rear Transition Module Link Kontron 3 wire protocol RTS Request To Send G 3 AT8020 www kontron com 5 5 Serial Attached 5 51 SATA Serial ATA SEL System Event Log SFP Small Form factor Pluggable ShMC Shelf Management Controller SMB Same as SMBus SMBUS System Management Bus SMBIOS System Management BIOS SMBUS Same as SMB SMBus System Management Bus SMBus Same as SMB SMBUS System Management Bus SOL Serial Over LAN SPI Serial Peripheral Interface SpeedStep Same as EIST Enhanced Intel SpeedStep Technology SSE2 Streaming SIMD Extension 2 SIMD is Single Instruction Multiple Data SSE3 Streaming SIMD Extension 3 SIMD is Single Instruction Multip
28. 15 6 2 Users 5 users are available for IPMI Over LAN connections The user 1 is defined by the IPMI specification and cannotbechanged following tables show the pre defined users They can be changed using the proper IPMI commands See supported IPMI commands set on AT8020 at section 2 16 12 Table 2 16 IPMI Over Lan Default Users No 1 NULL NULL User 2 admin admin Yes Administrator 3 Undefined Undefined Yes Undefined 4 Undefined Undefined Undefined Undefined 5 Undefined Undefined Undefined Undefined 36 AT8020 www kontron com Board Features 2 15 7 Serial Over LAN support SOL Serial Over LAN SOL is the name for the redirection of baseboard serial controller traffic over an IPMI Session The IPMC has connections to the primary serial port connected to the front panel and to the management port of the base interface Ethernet controller The serial port is implemented in such way that if there is a cable connected to the RJ 45 connector the traffic is directed to the cable and the IPMC only monitors traffic If there is no cable connected the traffic is directed to the The AT8020 supports SOL payload within a connection as defined in the IPMI 2 0 specification To setup SOL use the following procedure Configure the IP address Subnet Mask and Gateway address in the BIOS LAN configuration page Set Active the LAN channel to use Inthe BIOS menu Remote Access Configuration S
29. 400MHz DDR2 400 1 8V max 1 2 inches high registered DIMMs must be used The maximum DDR2 SDRAM size is 16GB This maximum will depend on the board configuration The minimum size of DDR2 SDRAM is 256MB if only a single 256MB DIMM is used in single channel mode For dual channel mode the minimum size is 512MB with two DIMMs The unit does support single sided and dual sided memory modules All DIMM types supported by the MCH are supported by the AT8020 Also both one row and two row DIMMs are supported Only use validated memory with this product Thermal issues or other problems may arise if you don t use recommended modules At the time of publication of this user guide the following memory were confirmed functional with the product As the memory market is volatile this list is subject to change please consult your local technical support for an up to date list MT18HTF12872Y 40EA2 HYS72T128000HR 5 A M393T2950BZ0 CCC MT18HTF12872Y 40EB3 VL393T5663 D5S VL393T5663 D5E VL393T5663 D5F VL393T2953 D5S DIMM DDR2 400 1GB 128M 72 REG ECC 1 2 DIMM DDR2 400 1GB 128M 72 REG ECC 1 2 DIMM DDR2 400 1GB 128M 72 REG ECC 1 2 DIMM DDR2 400 1GB 128M 72 REG ECC 1 2 DIMM DDR2 533 2GB 256M 72 X8 REG ECC LP DIMM DDR2 533 2GB 256M 72 X8 REG ECC LP DIMM DDR2 533 2GB 256M 72 X8 REG ECC LP DIMM DDR2 533 1GB 128M 72 REG ECC 1 18 Micron Technology Inc INFINEON TECHNOLOGIES Samsung Semiconductor Micron Technology Inc VIRTIUM VIRTIUM VIR
30. 8 Reserved Leave the jumper OUT JP1 9 10 FWH Top block Protect When the jumper is ON write protect is disabled JP1 11 12 FPGA PROM Selection When the jumper is ON it s the factory PROM when it s OUT it s the user PROM 1 13 14 Reserved Leave the jumper OUT JP2 1 2 Postcodes Display When the jumper is ON it display the postcodes JP2 3 4 BIOS Serial Recovery When the jumper is ON it does a BIOS serial recovery JP2 5 6 Reserved Leave the jumper OUT JP2 7 8 Reserved Leave the jumper OUT JP2 9 10 Clear CMOS Setup in Flash When the jumper is ON it restores on boot the CMOS setup in flash 2 11 12 When the jumper is ON it disables the possibility to write on the onboard flash Flash drive write protect JP2 13 14 drive 3 1 2 Setting Jumpers amp Locations Figure 3 1 Setting Jumpers amp Locations JUMPER SETTINGS Default Setting essi mem m 1 2 Watchdog O JP2 1 2 Reserved 88 Disabled in Reserved in 545025954 Enabled Reserved out o o E o 9 o S399 IS JP1 3 4 Shelf Manager Activatioi JP2 3 4 Postcodes Display w vapa p Override in Reserved in Normal Operation out Normal BIOS postcodes _ out St JP1 5 6 2 2 5 6 BIOS Recovery Override Board always in Recovery Mode in 9 Normal Operation out 9 Normal Operation out O J
31. Express Port C 86h AMC Bay Device 6 AMC B2 08 000202h 0 0 2 02h gt Carrier Device 2 Xpoint GbE 002302h 0 1 3 02h gt Carrier Device 2 Xpoint GbE 004003h 0 2 0 03h gt Carrier Device 3 SAS Controller 006104h 0 3 1 04h gt Carrier Device 4 Xpoint SAS 008001h 0 4 0 gt Carrier Device 1 PCI Express Port B 00A101h 0 28 AT8020 www kontron com Board Features Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 5 1 gt Carrier Device 1 MCH PCI Express Port 00 201 0 6 2 gt Carrier Device 1 MCH PCI Express Port 2 15 5 2 4 19h AMC Point To Point Connectivity Record 1 of 4 MCH PCI Express Port C Table 2 11 Type 19h AMC Point To Point Connectivity Record 1 of 4 MCH PCI Express Port C Record Type ID Record format version Record Length Record Checksum Header Checksum Manufacturer ID PICMG Record ID Record Format Version Record Type Connected device ID AMC Channel Descriptor Count AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Link Descriptor Reserved Bits 39 34
32. FEh 0 M 0 Other Bridge Commands 0 0 0 Error Report ICMB Bridge FFh AdvancedTCA 0 55 Get PICMG Properties 3 9 PICMG 00h M M Yes Get Address Info 3 8 PICMG 01h M 2 Get Shelf Address Info 3 13 PICMG 02h M 0 No Set Shelf Address Info 3 14 PICMG 03h M 0 No FRU Control 3 22 PICMG 04h M M Yes Get FRU LED Properties 3 24 PICMG 05h M M Yes Get LED Color Capabilities 3 25 PICMG 06h M M Yes Set FRU LED State 3 26 PICMG 07h M M Yes Get FRU LED State 3 27 PICMG 08h M M Yes Set IPMB State 3 51 PICMG 09h M M Yes 42 AT8020 www kontron com Board Features IPMISpec IPMIBMC Shelf Man IPM Con Kontron section require require troller re support on ment ment quirement AT8020 Set FRU Activation Policy 3 17 PICMG OAh M M Yes Get FRU Activation Policy 3 18 PICMG OBh M M Yes Set FRU Activation 3 16 PICMG OCh M M Yes 5 Device Locator Record 3 29 PICMG ODh 0 15 M 2 Set Port State 3 41 PICMG OEh 0 MP 0 MB Yes Get Port State 3 42 PICMG OFh 0 13 0 13 Yes Compute Power Properties 3 60 PICMG 10h 15 Yes Set Power Level 3 62 PICMG 11h MP M Yes Get Power Level 3 61 PICMG 12h Mt M Yes Renegotiate Power 3 66 PICMG 13h M 0 No Get Fan Speed Properties 3 63 PICMG 14h MH MH No Set Fan Level 3 65 PICMG 15h Get Fan Level 3 64 PICMG 16h 3 44 17h 0 M 0 M No Get IPMB Link Info 3 49 PICMG 18h 0 1 0 M No 1 Thiscommand
33. M M M Yes Get Auxiliary Log Status 25 12 Storage 5Ah 0 0 0 No Set Auxiliary Log Status 25 13 Storage 5Bh 0 0 0 No LAN Device Commands 0 M 0 LAN fi i 6 19 1 Transport 01 0 M M 0 M Yes Parameters LAN fi i oS 19 2 Transport 02h 0 M M 0 M Yes Parameters Suspend BMC ARPs 19 3 Transport 03h 0 M 0 M 0 3 Yes GetIP UDP RMCP Statistics 19 4 Transport 04h 0 0 0 No Serial Modem Device Commands 0 E 0 Set Serial Modem 3 3 3 12201 20 1 Transport 10h 0 M 0 M 0 M No Get Serial Modem 3 3 3 20 2 Transport 11 0 M 0 M 0 M No Set Serial Modem Mux 20 3 Transport 12h 03 03 03 Get Response Codes 20 4 Transport 13h 03 03 03 Set PPP UDP Proxy Transmit 20 5 44h 03 03 03 No Data PP i GeEEPPLUDPI rox Transport 15h 03 03 03 Data Send PPP UDP Proxy Packet 20 7 Transport 16h 03 03 03 UDP P i Transport 17h 03 03 02 Data ial M Transport 18h 3 0 M3 3 Active Callback 20 10 Transport 19h 0 0 0 No Set User Callback Options 20 11 Transport 1Ah 0 0 0 No Get User Callback Options 20 12 Transport 1Bh 03 03 03 Bridge Management Commands ICMB 5 Get Bridge State ICMB Bridge 00h 0 Set Bridge State ICMB Bridge 01h 2 0 Get ICMB Address ICMB Bridge 02h 0 M 0 M 0 No Set ICMB Address ICMB Bridge 03h 2 0 41 8020 WWW kontron com Board Features I
34. Note Unused bits are reserved for alternate LED functionality B 2 5 02 FWUM nnn ee Eee Read 02 Write Reset RESET NU Status DoProg RollBack UART MODE RESET NU RTM NU DoProg RollBack UART MODE RESET 0 NU 0 0 0 1 0 1 FWUM reset The power up state of this bit will be 0 under normal operating conditions When the T2604 is present with its jumper inserted or a jumper is inserted between pin 1 and 2 of the T2604 connector the power up state will be 1 FWUM and IPMC in reset Alternately the jumper identified as IPMI Override has the same effect as the T2604 jumper Note that this bitis not affected by a reset other than a power up B 3 AT8020 WWW kontron com MODE UART RollBack DoProg Status RTM FWUM mode pin Set this bit to connect UART1 to the internal FWUM for programming Deassert to connect UART1 to the RTM FWUM for programming Setto 1 for manual rollback in conjunction with DoProg Leave to 0 for normal operation Set to 1 then to 0 to start programming the IPMC with the new code 1 FWUM Ready 0 FWUM Busy Asserting this bit will assert signal RESET in the connector Depending on the type of RTM used the behavior will be as follow Non intelligent RTM reset payload devices futur RTM ignore this signal Intelligent RTM Put the FWUM on the RTM in firmware upgrade mode Use this bit only for firmware update and leave it to 0 otherwise
35. WWW k on com C 8 Power P10 2 1 3 4 HAO 5 1 2 7 8 HA4 9 10 11 12 7 SCL 13 14 SDA A SCL B 15 16 SDA B N C 17 18 N C N C 19 20 N C 21 22 N C N C 23 24 N C SHELF_GND 25 26 LOGIC_GND ENABLE_B 27 28 VRIN A VRTN B 29 30 EARLY A EARLY B 31 32 ENABLE A 48V A 33 34 48V_B C 6 AT8020 www kontron com D BIOS Setup Error Codes D 1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset memory and other components before system memory is available The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS Before D1 01 00 02 03 04 05 06 07 08 09 DA E1 E8 EC EE Early chipset initialization is done Early super 1 0 initialization is done including and keyboard controller NMI is disabled Perform keyboard controller BATtest Check if waiking up from power management suspend state Save power on CPUID value in scratch CMOS Go to flat mode with 408 limit and GA20 enabled Verify the bootblock checksum Disable CACHE before memory detection Execute full memory sizing module Verify that flat mode is enabled If memory sizing module not executed start memory refresh and do memory sizing in Bootblock code Do additional chipset initialization Re enable CACHE Ve
36. cables come from various manufacturers pinouts can differ The direct crimp design offered by Kontron allows the simplest cable assembly All cables are available from Kontron Sales Department Storing Boards Electronic boards are sensitive devices Do not handle or store device near strong electrostatic electromagnetic magnetic or radioactive fields xii AT8020 www kontron com Regulatory Compliance Statements FCC Compliance Statement for Class B Devices This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generated uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more ofthe following measures Reorientor relocate the receiving antenna Increase the separation between the equipment and receiver Connectthe equipment into an outlet on a circuit different from that to whic
37. chassis The onboard IPMC manages the board s power up and power down transitions The list below illustrates this process for power down request 1 Ejector latch is opened HOT SWAP assertion IPMC firmware detects the assertion of this signal 2 IPMCsends Deactivation Request message to SHMC M state moves from M4 M5 3 Board moves from M5 gt M6 if the SHMC grants the request 4 TheIPMC s ACPI timer 3 minutes starts if an ACPI enable OS is loaded Otherwise it goes to Step 6 below IPMC asserts 20 ms pulse on SMC_PWRBTN 5 The Power Button Status register is set It then asserts SCI to the OS If ACPI OS is enabled SCI interrupt handler on the OS is called Interrupt handler clears PWRBTN 515 bit OS starts to perform a graceful shutdown 6 Thefirmware deasserts payload power and sets the IPMI locked bit before it transitions from M6 to M1 state Note Bs If the upper level software moves the IPMC to M6 the same procedure is followed starting with Step 4 2 19 12 1 Hot Swap LED The AT8020 supports a blue Hot Swap LED mounted on the front panel The position of this LED is near the bottom handle This LED indicates when it is safe to remove the board from the chassis The on board IPMC drives this LED to indicate the hot swap state The following states are possible Table 2 25 Hot Swap LED State OFF Board is in M4 state normal state when board is in operation ON Ready for hot swap Short blink M5
38. clock frequency and connection with the backplane refer to section Telecom Clock Option 12 AT8020 www kontron com Board Features 2 10 1 AMC Ports Mapping B1 Table 2 4 AMC Ports Mapping AMC B1 TCLKA TCLKB TCLKC TCLKD FCLKA Ui W E OE Sg SENS Ui KR WH 20 Telco clock Telco clock Telco clock Telco clock Fabric clock Ethernet Ethernet SAS SATA SAS SATA PCIe PCIe PCIe PCIe N C N C N C N C N C N C N C N C N C N C N C N C N C J20 CLK2 RX None None N C 100MHz PCIe CLK None None Daughter card P3 None MCH MCH MCH MCH N C N C N C N C N C N C N C N C N C N C N C N C N C J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 N C None Fabric CH1 P1 OR Fabric CH2 P1 OR Daughther P7 OR Daugther P8 Fabric CH1 P1 OR Fabric CH2 P1 OR Daughther P7 OR Daugther P8 None RTM P2 None None None None N C N C N C N C N C N C N C N C N C N C N C N C N C Note For each possible Telco clock connection it is hardware wise possible software may need to be implemented to transmit or receive clock Using this option with the T5511B daughter card would mean the daughter card s 8257 1EB Ethernet ports wouldn t be connected to the Fabric Channel 1 P1 and Channel 2 P1 WWW kontron com 13 AT802
39. enter SETUP AMIBIOS C 2005 American Megatrends Inc KONTRON AT8020 CPU Intel R Xeon TM CPU 2 00GHz Speed 2 00 GHz Count 2 Press DEL to run Setup F4 on Remote Keyboard Press F12 if you want to boot from the network Press 11 for BBS POPUP F3 on Remote Keyboard C American Megatrends Inc 61 AT8020 www kontron com Software Setup The main menu of the AMI BIOS CMOS Setup Utility appears on screen AMIBIOS BIOS Version Build Date BIOS ID Boot Block Version FPGA Ver Channel A1 Memory Size Channel B1 Memory Size Channel A2 Memory Size Channel B2 Memory Size System Memory Speed System Memory Extended Memory System Time System Date BIOS Setup Utilit 08 00 14 08 16 07 5004 300 3 00 41 602 INGE 62 400 2 642 4192768 16 56 04 108 08 2007 wise se gt N Tab Til 10 5 Exit ENTER TAB one SHIFT TAB TEO select a field ee configure system Time Select Screen Select Item Change Field Select Field General Help Save and Exit American Megatrends Inc Setup Default values provide optimum performance settings for all devices and system features Note Note CAUTION These parameters have been provided to give control over the system However the values for these options should be changed only if the user has a full underst
40. failure 04h Unrecoverable system board failure ODh CPU speed matching failure Critical Interrupt Includes the following supported offset type 00h Front Panel NMI 04h PCI PERR 05h PCI SERR Boot Error Includes the following supported offset type 00h No bootable media POST Memory Resize Sensor Type OEh Indicates if CMOS memory size is wrong Platform Security Violation Attempt Sensor Type 06h Sensor Specific Offset O1h Pre Boot Password Violation User password BIOS password check location is critical 04h Other Pre Boot Password Violation BIOS password check location is not critical Firmware Hub 0 Boot Error Specifies if it was unable to boot from the BIOS on the Firmware Hub 0 www kontron com 21 AT8020 Board Features Firmware Hub 1 Boot Error Specifies if it was unable to boot from the BIOS on the Firmware Hub 1 65 66 67 68 69 70 71 72 73 74 75 76 78 79 80 81 82 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 1 FRU1 Mp Over Icc FRU1 Over Icc FRU1 Sensor Err FRU2 Mp Over Icc FRU2 Over Icc FRU2 Sensor Err FRU3 Mp Over Icc FRU3 Over Icc FRU3 Sensor Err FRUO Pwr Denied FRU1 Pwr Denied FRU2 Pwr Denied FRU3 Pwr Denied FRUO FRU Agent FRU1 FRU Agent FRU2 FRU Agent FRU3 FRU Agent IPMC Storage Err Firmware Upg Mng IpmC Reboot Ver change SEL State IPMI Info 1 IPMI Info
41. non specific single function Bridge PCI to PCI single function type 1 header Bridge PCI to PCI single function type 1 header Bridge PCI to PCI single function type 1 header Bridge PCI to PCI single function type 1 header Bridge PCI to PCI single function type 1 header Bridge PCI to PCI single function type 1 header Ethernet Controller Ethernet Controller www kontron com A 3 AT8020 Intel Corporation 82571EB Gigabit 8086h 105Eh 1 Ethernet Controller rev 06 Ethernet Controller Intel Corporation 82571EB Gigabit 4 0 8086h 1060h 0 Ethernet Controller rev 06 Ethernet Controller Intel Corporation 82571EB Gigabit 4 0 8086h 1060h 1 Ethernet Controller rev 06 Ethernet Controller LSI Logic Symbios Logic 5 0 1000h 0056h 0 SAS1064E PCI Express Fusion MPT SCSI Storage Controller SAS rev 02 5 0 1000h 0056h 1 Ethernet Controller Intel Corporation 82571EB Gigabit 6 0 8086h 1060h 1 Ethernet Controller rev 06 Ethernet Controller Intel Corporation 82571EB Gigabit 6 0 8086h 1060h 1 Ethernet Controller rev 06 Ethernet Controller A 4 AT8020 n com Kontron Extension Registers B 1 FPGA CPLD Registers Definition Unused bits are reserved To insure compatibility with other products and upgrades to this product do not modify unused bits Bits marked NU are not used on this board Writing to such bit does nothing and reading i
42. so that CPU boots off redundant BIOS bank Table 2 19 Reset BIOS Flash Type NetFn LUN NetFn OEM Request RsLUN Command 01h BIOS checksum success failure indication Byte 1 00h Checksum success 01 Checksum failure Byte 1 Completion code 2 15 11 2 Set Control State This command sets the state of a control pin and overrides the control pin s auto state Table 2 20 Set Control State ZS eS EGRE NetFn LUN NetFn 3Eh OEM Request RsLUN Command 20h Byte 1 Control number B Control state 0 Deassert 1 Assert 3 Reserved FF Don t change 2 settings Byte 1 Completion code 44 AT8020 www kontron com Board Features 2 13 11 3 Get Control State This command sets the state of a control pin This command overrides the AUTO state of the control pin Table 2 21 Get Control State ESI ERE EE NetFn LUN NetFn 3Eh OEM Request RsLUN Command 21h 1 Control number Byte 1 Completion code B Control state 0 Deassert 1 Assert 3 Reserved FF Don t change 2 settings 2 15 11 4 GetBoardDeviceChannelPortSelection This command returns the current device routing selection The command is available over any working interface Table 2 22 GetBoardDeviceChannelPortSelection Kontron IANA number 003A98h Requ
43. state deactivation request Long blink 2 state Activation Request When the lower ejector handle is disengaged from the faceplate the hot swap switch embedded in the PCB will assert a signal to the IPMC and the IPMC will move from the M4 state to the M5 state At the M5 state the IPMC will ask the SHMC or Shelf Manager for permission to move to the M6 state The Hot Swap LED will indicate this state with a short blink Once permission is received from the SHMC or higher level software the board will move to the M6 state 47 8020 WWW kontron com Board Features The SHMC or higher level software can reject the request to move to the M6 state If this occurs the Hot Swap LED returns to a solid off condition indicating that the board has returned to M4 state Ifthe board reaches the M6 state either through an extraction request through the lower ejector handle or a direct command from higher level software and an ACPI enabled OS is loaded on the board the IPMC communicates to the OS that the module must discontinue operation in preparation for removal The Hot Swap LED continues to flash during this preparation time just like it does at the M5 state When main board power is successfully removed from the AT8020 the Hot Swap LED remains lit indicating itis safe to remove it from the chassis Table 2 26 Hot Swap LED Status Off Normal status Preparing for removal insertion Long blink indicates activation is in progr
44. the available devices 1st Drive Varies Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device Specifies the boot priority of the available devices Nth Drive Varies Select the boot device with UpArrow or DownArrow key Press Enter to set the selection as the intended boot device 78 AT8020 WWW kontron com Software Setup 5 1 7 System Management Menu Remote Access Configuration Set LAN Configuration Watchdog Timers System Information 5 1 7 1 Serial Port Number Serial Port 11 0 address Serial Port 2 I 0 address Baud Rate Data Bits Parity Stop Bits Flow Control Terminal Type Terminal Size Terminal Display Mode BIOS Printouts N A N A N A N A N A IPMIover LAN and Serial Over LAN N A N A Remote Access Configuration sub menu COM1 COM2 3F8 IRQ4 2F8 TRQ3 9 6 KB 19 2 KB 38 4 KB 57 6 KB 115 2 KB 7 8 Even Odd None 1 2 Hardware Software None ANSI VT100 VTUTF8 80x24 Normal Mode Recorder Mode Enabled Disabled Select serial port for console redirection Hardware address of the COM 1 port Hardware address of the COM 2 port Select serial port Baud rate Select the number of data bits in each transmitted or received serial character Select if parity bitis generated transmit data or checked receive data between the last data word bit and stop bit of the serial data
45. to Kontron Customers may reprint and use this user s guide in other publications Customers may alter this user s guide and publish it only after they remove the Kontron name cover and logo Kontron reserves the right to make changes without notice in product or component design as warranted by evolution in user needs or progress in engineering or manufacturing technology Changes that affect the operation of the unit will be documented in the next revision of this user s guide www kontron com i AT8020 Table of Contents Table of Contents Sdfety Instructions Before You Begin gt RE viii Preventing Electrostatic Discharge ix Howto UseThisGuide x Customer COMMENCES tases xi Advisory 5 ss Unpacking Powering Up the 5 xii Adapter Cables REN wise avers Storing Boards 4 Regulatory Compliance 54
46. to the right 0000h XBDA USB Legacy BIOS Stac 0 622 A0000h Note 1 LAN BIOS address may vary Note2 Fibre Channel SAS BIOS address may vary Size is only 2KB if no device 00000 9B7FF 9B800 9FFFF A0000 BFFFF C0000 DBFFF 0000 100000 0 622 KB DRAM 622KB 640 KB XBDA USB Legacy BIOS Stack Video DRAM Optional ROM Free LAN BIOS around 30KB if activated address may vary External Fiber Channel BIOS 18KB 64KB address may vary System BIOS DRAM available A 1 AT8020 ron com 2 10 Mapping 000 01 020 03 040 05 060 06 070 07 080 09F 0A0 0BF 0 0 00 OFO OF1 OF8 OFF 1F0 1F7 3F6 170 177 376 378 37F 3F8 3FF COM1 2F8 2FF COM2 2F8 2FF COM2 3F8 3FF COM1 DMA Controller 1 Interrupt Controller 1 Timer Keyboard Real time clock DMA Page Register Interrupt Controller 2 DMA Controller 2 Math Coprocessor Primary IDE Secondary IDE Parallel Port Used as PLD POD Serial Port 1 COM1 by default Serial Port 2 COM2 by default 400 9FF Chipset Reserved 00 1 Kontron Registers on board 00 Chipset Reserved A 2 AT8020 www kontron com 3 e 1 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 7 0 28 0 29 0 29 0 29 0 29 0 29 0 30 31 0 31 0 31 0 31 1 1 3 0 PCI IDSEL and Device numbers AU 8086h 8086h 8086h 8086h 8086h 8086h 8086h
47. 0 Board Features 2 10 2 AMC Ports Mapping B2 Table 2 5 AMC Ports Mapping AMC B2 TCLKA TCLKB TCLKC TCLKD FCLKA 03 0 9 10 11 12 13 14 15 16 17 18 19 20 Telco clock Telco clock Telco clock Telco clock Fabric Clock Ethernet Ethernet SAS SATA SAS SATA PCIe PCIe PCIe PCIe Ethernet Ethernet N C N C N C N C N C Serial port N C N C N C N C N C J20 CLK2 RX None None N C 100MHz PCIe CLK Fabric CH1 P2 Fabric CH2 P2 Daughter card P2 None MCH MCH MCH MCH None None None None None None None None None None None None None J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 J20 CLK1 OR J20 CLK2 TX OR J20 CLK3 N C None Fabric CH2 P2 OR Fabric CH1 P3 OR Fabric CH2 P3 Fabric CH1 P2 OR Fabric CH2 P3 OR Fabric CH1 P3 None RTM Port3 None None None None Daughter card P9 through Daughter card P7 can be connected to Fabric Chanel 1 P1 OR to Channel 2 P1 OR to AMC B1 PO OR to AMC B1 P1 Daughter card P10 through Daughter card P8 can be connected to Fabric Chanel 1 P1 OR to Channel 2 P1 OR to AMC B1 PO OR to AMC B1 P1 None None None None None Serial port to RTM None None None None None Note For each possible Telco clock connection it is hardware wise possible software may need to be implemented to transmit or receive clock Using this option with the T5511B daught
48. 0 is unpowered for a long time only the time will be lost 9 AT8020 WWW kontron com Board Features 2 7 Ethernet Interfaces The AT8020 has a dual 1000 Base T supports also 10 Base T and 100 Base TX interfaces to the base interface and two dual 1000 Base BX interfaces to the fabric interface Three two onboard and one on the dauther card 82571EB dual gigabit Ethernet controllers provide those interfaces The AT8020 also has a 10 100 management port connected with 1825510 controller 2 7 1 1825510 Ethernet Management The management port is implemented with a 1825510M Ethernet chip It supports a 10 100 Base T connection with autonegociation The 1825510 features high performance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K Consult www intel com for additional details on the 1825510 The AT8020 has boot from LAN capability PXE on this port This option must be enabled from the BIOS Setup Program wits BIOS Settings 1010 Advanced gt Expansion ROM Configuration gt Ethernet 825510M Expansion ROM Signal Path The Ethernet Management is located on the faceplate RJ45 connector 215 2 7 2 182571EB Base Interface The ATCA base interface is implemented with a 182571 twin gigabit Ethernet controller It supports 10 100 1000 Base T connections with autonegociation to the base interface channel 1 and 2 The 182571EB features high perfor
49. 1 0 2355 55 B 00h gt Single Channel Link 00h gt Carrier Reference clock is not spread spectrum 002h gt AMC 1 PCI Express OFOOh gt AMC Channel 0 lane 0 1 2 and 3 FE00102100 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 1015 00h gt Single Channel Link O1h gt Carrier Reference clock is spread spectrum 002h AMC 1 PCI Express 0100h gt Channel 0 lane 0 FE00002100 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h gt Single Channel Link gt Carrier Reference clock is not spread spectrum 002h gt AMC 1 PCI Express 0100h gt AMC Channel 0 lane 0 Type 19h AMC Point To Point Connectivity Record 2 of 4 MCH PCI Express Port Table 2 12 Type 19h AMC Point To Point Connectivity Record 2 of 4 MCH PCI Express Port B Record Type ID Record format version Record Length Record Checksum Header Checksum Manufacturer ID PICMG Record ID Record Format Version Record Type Connected device ID AMC Channel Descriptor Count AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Coh 02h N A N A N A 00315Ah gt PICMG Record ID 19h gt AMC Point To Point Connectivity Record 00h gt On Carrier device Device 1 PCI Express Port B 01 0F18820h O
50. 1 Memory Size Channel B1 Memory Size Channel A2 Memory Size Channel B2 Memory Size System Memory Speed System Memory Extended Memory System Time System Date 5 1 4 Advanced Menu X KB MB GB X KB MB GB X KB MB GB X KB MB GB X MHz X KB X KB HH MM SS MM DD YYYY N A N A N A N A N A N A N A N A N A N A N A N A Use or to configure system time Use or to configure system date Advanced Processor Configuration IDE Configuration ACPI Configuration Event Log Configuration Expansion ROM Configuration PCI Express Configuration USB Configuration Advanced Chipset Control MPS Revision 5 1 4 1 N A N A N A N A N A N A N A N A 1 4 Advanced Processor Configuration sub menu N A N A N A N A N A N A N A N A Multiprocessor specification revision level Physical Processors 2 N A Logical Processors 4 N A Processor Type Sossaman N A Processor 0 Speed Varies N A Processor 1 Speed Varies N A FSB Speed Varies N A 65 AT8020 WWwW kontron com Software Setup Processor 0 Microcode Processor 0 L2 Cache Size Processor 1 Microcode Processor 1 L2 Cache Size Processor Virtualization SpeedStep Thermal Management 5 1 4 2 SpeedStep Processor 0 Speed Processor 0 Core 0 Processor 0 Core 1 Processor 1 Speed CPUID XXX Update Revision XXXX 2 MB CPUID XXX Update Revision
51. 149 B150 B151 B152 B153 B154 155 156 157 158 159 160 161 162 163 164 165 166 167 TxD15 15 GND RxD15 RxD15 GND TCLKC TCLKC GND TCLKD TCLKD GND TxD17 TxD17 GND RxD17 RxD17 GND TxD18 18 GND RxD18 RxD18 GND TxD19 TxD19 GND RxD19 RxD19 GND TxD20 TxD20 GND RxD20 RxD20 GND TCLK TMS TRST C4 AT8020 ron com 8 208 01 82 125 168 TDO B41 ENABLE B83 126 RxD14 B169 TDI 42 12 B84 12V B127 RxD14 B170 GND B85 GND B128 GND 7 1 0 ATCA 3 1 221 1 Tx2 2 Tx2 2 Rx2 2 Rx2 2 2 Tx3 2 2 Tx0 2 2 2 Rxo 2 1 2 Tx1 2 3 Tx2 1 Tx2 1 Rx2 1 Rx2 1 1 1 4 1 Txo 1 RxO 1 Rxo 1 1 1 Tx1 1 5 BI DA14 DA1 BI_DB1 BI_DB1 BI_DC1 BI_DC1 6 BI_DA2 DI_DA2 BI_DB2 BI_DB2 DI DC24 BI DC2 7 N C N C N C N C N C N C 8 N C N C N C N C N C N C 9 N C N C N C N C N C N C 10 N C N C N C N C N C N C 1 Rx3 2 Rx3 2 2 Rx1 2 Rx1 2 GND GND GND GND 3 Rx3 1 Rx3 1 GND GND GND GND 4 Rx1 1 Rx1 1 GND GND GND GND 5 BI_DD1 DD1 GND GND GND GND 6 BI DD2 DI DD2 GND GND GND GND 7 N C N C GND GND GND GND 8 N C N C GND GND GND GND 9 N C N C GND GND GND GND 10 N C N C GND GND GND GND C 5 AT8020
52. 2 DCM Temp Board DCM Temp LAN DCM Vcc 1 1V DCM Vcc 1 2V DCM Vcc 1 8V DCM Vcc 3 3V DCM Vcc 3 3VSUS DCM Vcc 12V FRU 1 Management Power Over Current FRU 1 Over Current FRU 1 Error during Sensor discovery FRU 2 Management Power Over Current FRU 2 Over Current FRU 2 Error during Sensor discovery FRU 3 Management Power Over Current FRU 3 Over Current FRU 3 Error during Sensor discovery FRU 0 Power Denied FRU 1 Power Denied FRU 2 Power Denied FRU 3 Power Denied Board FRU 0 Data agent that verifies FRU Data validity checksum E key etc Board FRU 0 Data agent that verifies FRU Data validity checksum E key etc Board FRU 0 Data agent that verifies FRU Data validity checksum E key etc Board FRU 0 Data agent that verifies FRU Data validity checksum E key etc Management sub system health non volatile memory error Firmware Upgrade Manager Status IPMC reboot detection IPMC firmware upgrade detection SEL state Specifies if the SEL is full Internal IPMC firmware diagnostic Internal IPMC firmware diagnostic For more details IPMI sensors consult 09004 AT8020 Sensor User Guide on Kontron web site www kontron com AT8020 Board Features 2 15 4 Events supported 2 15 4 1 Link Sensor The AT8020 provides two IPMB links to increase communication reliability to the shelf manager and other IPM devices on the IPMB bus These IPMB links work together for increased thro
53. 8 82571 82571 1 38200 i A gt 82166 FWHI SE Opnir Ophir 8 CPLD OE TOFPIAA 1 TSSOP40 550 40 9 95144 I 18x18mm 1 TQFP144 1 18x18mm 1 1 1 Zone2 1 Base Interface I M LVDS SPI 256KB FWUM Daughter Card AMC I R8C 13 gt 1 SPI256KB TQFP32 Zone Fabric and RTM I O Type i Q iPMBDA SAS gt 4 5 I Suspend power 1 Any 4 d 020 www kontron com Board Features 2 2 System Core 2 2 1 Processors The Dual Core Intel Xeon processor LV 2 0 GHz 15 a member of Intel s growing product line of multi core processors This processor combines the benefits of dual core with dual processor capabilities providing four high performance cores per platform While incorporating advanced processor technology this dual core processor remains software compatible with previous 32 bit Intel Architecture processors Product highlights are listed below Two complete execution cores in one processor package provide advancements in simultaneous computing such as multi threaded applications and multi tasking environments 667 MHz front side bus FSB Combined with dual core processing this supports up to four simultaneous threads on the system Enhanced Intel SpeedStep technology allows a system to dynamically adjust processor voltage and core frequency decreasing average power consumption and
54. An UltraDMAn Enable Disabled 32 bit Data Transfer 72 AT8020 ron com Software Setup 5 1 4 4 6 Fourth IDE Master Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Fourth IDE Master Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the device is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDMAn UltraDMAn Enable Disabled 32 bit Data Transfer 73 AT8020 ron com Software Setup 5 1 4 5 ACPI Version Features ACPI APIC Support Headless Mode 5 1 4 6 ACPI Configuration sub menu ACPI v1 0 ACPI v2 0 ACPI v3 0 Enabled Disabled Enabled Disabled Enabled RSDP pointer to 64 bit Fixed System De
55. Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the device is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDMAn UltraDMAn Enable Disabled 32 bit Data Transfer 70 AT8020 ron com Software Setup 5 1 4 4 4 Secondary IDE Slave Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Secondary IDE Slave Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the devi
56. C O specification contains several requirements about IPMB L fault detection and isolation it was decided to include an IPMB L failure detection sensor This IPMB L Link State sensor matches the PICMG 3 0 0 Link State sensor defined sensor type F1h 0 sensor includes redundant channels IPMB A and IPMB B See specification PICMG 3 0 R2 0 section 3 8 4 for all details related to this sensor To define IPMB L sensor we had to take an OEM sensor type because the 0 IPMB L Link State C3h type is reserved for Port Link A amp B IPMB L Sensor Port Link is placed at the same location as IPMB A of IPMB 0 sensor Compare to 0 all bytes related to IPMB B are set to enable working state The sensor will only use the following bit offset Sensor byte 4 bit offset 0 Reserved 1 Reserved 2 1b IPMB L disabled 3 1b IPMB enabled Associated event reading type code This sensor match the ATCA defined type F1h OEM Firmware Info COh 23 AT8020 www k on com Board Features Descriptions Including Associated Event Reading type code Sensor giving information about board reset source All defined bits will have assertion event mask set ATCA Reset Sensor C4h Associated event reading type code 6Fh IPMI Sensor Specific Formerly 76h OEM ATCA Reset Sensor Sensor indicating if there has been an error during the FRU In
57. C port 0 and 1 Telco clock on CLK1 SAS on AMC port 2 and 3 4 AT8020 www kontron com Board Features 2 Board Features 2 1 Figure 2 1 Block Diagram Block Diagram I 1 Primary Secondary boa 1 38V to 72V 12V SUS EVRMII Isolated I Converter Tihe 48V to 12V SUS Switcher I suspend suspend Intel Dual Core Xeon LV Sossaman Intel Dual Core Xeon LV Sossaman 1 33V12V uFCPGA478 uFCPGA478 1 hoes E 1 1 T T 1 Switcher Hotswap Dual core CPU Ee 2 MB
58. ChannelPortSelection 1 46 Table 2 24 Controls 46 Table 2 25 Hot Swap LED State 47 Table2 26 Hot Swap LED Status 2 1 48 Table 2 27 005160 ATCA LED 1 5 48 Table 2 28 005 Led ATCA LED 1 Short Blink Mode 49 Table 2 20 Health Led ATCA LED 2 5 49 Table 2 30 Health LED Sensors Agregation 49 Table 3 1 Jumper Description 2 52 Table 3 2 Onboard Connectors and 56 vii AT8020 www kontron com Safety Instructions Safety Instructions Before You Begin Before handling the board read the instructions and safety guidelines on the following pages to prevent damage to the product and to ensure your own personal safety Refer to the Advisories section in the Preface for advisory conventions used in this user s guide including the distinction between Warnings Cautions Important Notes and Notes Always use caution when handling operating the computer Only qualified experienced authorized elect
59. Device 0 PCI Express Port C 00A100h 0 5 27 AT8020 www kontron com Board Features Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point AMC Resource Descriptor Resource ID Point to Point Count Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 1 gt Carrier Device 0 PCI Express Port 00C200h 0 6 2 00h gt Carrier Device 0 PCI Express Port 00E300h 0 7 3 00h gt Carrier Device 0 MCH PCI
60. EG TMPESR Eyes Get System GUID 18 13 App 37h 0 0 0 No Get Channel Authentication 18 12 A 5 Capabilities 8 PP 38 0 M 0 Get Session Challenge 18 14 App 39h 0 M3 03 Yes 38 AT8020 www kontron com Board Features IPMISpec IPMIBMC Shelf Man IPM Con Kontron section require require troller re support ment quirement AT8020 Activate Session 18 15 App 3Ah 0 M3 0 Yes Set Session Privilege Level 18 16 App 3Bh 0 M3 0 Yes Close Session 18 17 App 3Ch 0 M3 0 Yes Get Session Info 18 18 App 3Dh 0 M3 0 Yes Get AuthCode 18 19 App 3Fh 0 M 0 Yes Set Channel Access 18 20 App 40h 0 M3 0 Yes Get Channel Access 18 21 App 41h 0 M3 03 Yes Get Channel Info 18 22 App 42h 0 M3 0 Yes Set User Access 18 23 App 43h 0 M3 03 Yes Get User Access 18 24 App 44h 0 M3 0 Yes Set User Name 18 25 App 45h 0 M3 03 Yes Get User Name 18 26 App 46h 0 M3 0 Yes Set User Password 18 27 App 471 0 M3 03 Yes Chassis Device Commands 0 0 0 Get Chassis Capabilities 22 1 Chassis 00h M 5 0 5 Get Chassis Status 22 2 Chassis 01h 0 M M 0 Yes Chassis Control 22 3 Chassis 02h 0 M3 Me 0 Yes Chassis Reset 22 4 Chassis 03h 0 0 0 No Chassis Identify 22 5 Chassis 04h 0 0 0 No Set Chassis Capabilities 22 6 Chassis 05h 0 0 0 No Set Power Restore Policy 22 7 Chassis 06h 0 0 0 No Get System Restart Cause 22 9 Chassis 07h 0 0 0 No Get System Restart Cause 22 10 Chassis 08h 03 03 03 Get System Restart Cause 22 11 Chassis 09h 03 03 03 Get System
61. Fh 03h 02h 01 30 8020 www kontron com Board Features Lane 0 Port Number Bits 4 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 00h 00102 00 h 03Fh 10b gt This Carrier provides a Secondary PCI Express Port Matches with 01b 00h gt Single Channel Link 01h gt Carrier Reference clock is spread spectrum 002h gt AMC 1 PCI Express OFOOh
62. IOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS EO E9 EA EB EF FO F1 F2 2 0 3 Initialize the floppy controller in the super 1 0 if present Some interrupt vectors initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled Set up floppy controller and data Attempt to read from media Enable ATAPI hardware Attempt to read from ARMD and ATAPI CDROM Disable ATAPI hardware Jump back to checkpoint E9 Read error occurred on media Jump back to checkpoint EB Search for pre defined recovery file name in root directory Recovery file not found Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file Start reading the recovery file cluster by cluster Validate the recovery file configuration with the current configuration of the flash Enable flash write through chipset and OEM specific method Detect proper flash part Verify that the found flash part is the same size than the recovery file The recovery file size does not equal the found flash part size Erase the flash part Program the flash part The flash has been updated successfully Make flash write disabled Disable ATAPI hardware Restore CPUID
63. Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 2 15 5 2 7 19h AMC Point To Point Connectivity Record 4 of 4 1Fh 1Fh 1Fh 03h FC00005104h 03Fh 00b Exact match gt Single Channel link 01h gt 1000 Base BX 005h gt AMC 2 Ethernet 0104h gt AMC Channel 4 lane 0 00005105 03Fh Exact match 00h gt Single Channel link 00h gt 1000 Base 005h gt AMC 2 Ethernet 0105h gt AMC Channel 5 lane 0 Table 2 14 Type 19h AMC Point To Point Connectivity Record 4 of 4 Record Type ID Record format version Record Length Record Checksum Header Checksum Manufacturer ID PICMG Record ID Record Format Version Record Type Connected device ID AMC Channel Descriptor Count AMC Channel Descriptor Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Chan
64. Operating 15 to 90 55 C 131 F non condensing Storage and Transit 5 to 95 40 C 104 F non condensing Operating 4 000 m 13 123 ft Storage and Transit 15 000 m 49 212 ft Operating 3G half sine 11ms each axis Storage and Transit 18G half sine 6ms Operating 0 2G 5 200Hz each axis Storage and Transit 0 2G 5 200Hz each axis Operating 5 Hz to 10 Hz 2 12 dB oct slope up 10 Hz to 50 Hz 0 02 2 53 0 000292 flat 50 Hz to 100 Hz 2 12 dB oct slope down 30 minutes per each 3 axes Storage and Transit 5 Hz to 20 Hz 1 2 5 0 01 g Hz flat 20 Hz to 200 Hz 2 3 dB oct slop down 30 minutes per each 3 axes Whole board protected by active breakers USB voltage protected by active breakers Meets or exceeds Safety UL 60950 1 CSA 22 2 No 60950 1 03 EN 60950 1 2001 CB report and certificate to IEC 60950 1 47 CFR Part 15 Class Mark to 55022 55024 300386 Two years limited warranty Note lt Most Shelf Manager will only allow a maximum of 200W slot by default This includes the board the AMCs and the RTM Therefore the power budget could be exceeded causing the last entity to ask for activation to stay in power state M3 Ifthe environment allows to exceed 200W per slot and still meets temperature requirements it is possible to modify the shelf manager s settings in order to grant more power 1 4 Compliance This pro
65. P1 7 8 AMC Activation 2 7 8 Reserved Override in Reserved in Normal Operation out Reserved out JP1 9 10 Reserved JP2 9 10 Reserved Reserved in Reserved in Reserved out 9 Reserved out JP1 11 12 FWH Top block Protect 2 11 12 Clear CMOS Setup Unprotect in Restore on Boot in L 9 Normal out 9 Normal Operation out JP1 13 14 FPGA PROM Selection JP2 13 14 Flash drive write protect H Factory Default in Protection controlled by BIOS in 9 Normal Operation out Write Enabled out 52 AT8020 ron com Installing the Board 3 2 Processor This product ships with the CPU installed and a thermal solution installed The thermal solution is custom and the thermal interface is critical for passive cooling Kontron does not guarantee thermal performance if the heatsink is removed and then reinstalled by the end user 3 3 Memory The unit supports four 240 pin 22 5 degree DIMM sockets There are two parallel memory channels operating as a logical one wide memory channel The unit can also be operated with a single memory channel only the chipset also enables these memory channels to operate in mirrored mode or to use spare DIMMs When both memory channels are used there must be at least two DIMMs These DIMMs in parallel must be identical identical size speed and organization The memory bus operates at 200MHz clock speed with dual data rate data is transferred at
66. PMISpec IPMIBMC Shelf Man IPM Con Kontron section require require troller re support ment ment quirement AT8020 Set Bridge Proxy Address 0 Get Bridge Statistics ICMB Bridge 05h 0 Get ICMB Capabilities ICMB Bridge 06h 2 0 Clear Bridge Statistics ICMB Bridge 08h 0 Get Bridge Proxy Address ICMB Bridge 09h 0 Get ICMB Connector Info ICMB Bridge OAh 0 Get ICMB Connection ID ICMB Bridge 0Bh 0 M 0 No Send ICMB Connection ID Bridge OCh 0 Discovery Commands ICMB 0 0 0 Prepare For Discovery ICMB Bridge 10h 0 M 0 M 0 No Get Addresses ICMB Bridge 11h 0 Set Discovered ICMB Bridge 12h 0 Get Chassis Device ICMB Bridge 13h 0 0 Set Chassis Device ID ICMB Bridge 14h 0 M 0 M 0 No Bridging Commands ICMB 0 0 0 Bridge Request ICMB Bridge 20h 0 Bridge Message ICMB Bridge 21h 0 M 0 Event Commands 2 0 0 0 Get Event Count ICMB Bridge 30h 0 Set Event Destination ICMB Bridge 31h 0 Set Event Reception State Bridge 32h 0 M 0 No Send ICMB Event Message Bridge 33h 2 0 Get Event Destination ICMB Bridge 34h 0 M 0 No Get Event Reception State Bridge 35h 0 for Bridge 0 0 0 OEM Commands ICMB Bridge COh
67. Point Connectivity Record Record Type ID Record format version Record Length Record Checksum Header Checksum Manufacturer ID PICMG Record ID Record Format Version Point to Point AMC Resource Descriptor Resource ID Point to Point Count Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Ressorce Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Remote Port Bit 12 8 Remote Ressource ID Bits 7 0 Point to Point Resource Descriptor Reserved Bits 23 18 Local Port Bits 13 17 Coh 02h N A N A N A 00315Ah PICMG Record ID 18h Carrier Point To Point Connectivity Record 00h 85h AMC Bay Device 5 AMC B1 08h 000002h 0 0 0 02h gt Carrier Device 2 Xpoint GbE 002102h Oh 1 1 02h gt Carrier Device 2 Xpoint GbE 004103h 0 2 1 03h gt Carrier Device 3 SAS Controller 006004h 0 3 0 04h gt Carrier Device 4 Xpoint SAS 008000h 0 4 0 00h gt Carrier
68. Restart Cause 22 12 Chassis OFh 03 03 03 Event Commands M M M Set Event Receiver 23 1 S E 01h M M M Yes Get Event Receiver 23 2 S E 02h M M M Yes ud hes 23 3 S E 03h M M M Yes PEF and Alerting Commands 0 0 0 Get PEF Capabilities 24 1 S E 10h M3 M3 M3 No Arm PEF Postpone Timer 24 2 S E 11h M 3 24 3 S E 12h 3 3 3 24 4 S E 13h 3 3 3 Set Last Processed EventID 24 5 S E 14h M3 M3 M3 No Get Last Processed EventID 24 6 S E 15h Alert Immediate 24 7 S E 16h 03 03 03 Acknowledge 24 8 5 17h 03 03 03 No 39 AT8020 www kontron com Board Features IPMISpec IPMIBMC Shelf Man IPM Con Kontron section require require troller re support ment quirement AT8020 Sensor Device Commands 0 M M Get Device SDR Info 29 2 S E 20h 0 M M Yes Get Device SDR 29 3 S E 21h 03 Yes SDR 29 4 S E 22h 0 M3 3 Yes GetSensorReadingFactors 29 5 S E 23h 03 0 M3 No Set Sensor Hysteresis 29 6 S E 24h 0 0 0 Yes Get Sensor Hysteresis 29 7 S E 25h 0 0 0 Yes Set Sensor Threshold 29 8 S E 26h 0 0 0 Yes Get Sensor Threshold 29 9 S E 27h 03 03 03 5 Set Sensor Event Enable 29 10 S E 28h 0 0 0 Yes Get Sensor Event Enable 29 11 S E 29h 03 0 03 Yes Re arm Sensor Events 29 12 S E 2Ah 0 0 03 Get Sensor Event Status 29 13 S E 2Bh 0 0 0 No Get Sensor Reading 29 14 S E 2Dh M M M Yes Set Sensor Type 29 15 S E 2Eh 0 0 0 No Get Sensor Type 29 16 S E 2Fh 0 0 0 N
69. SUS VOLTAGE BOARD 3V3 VOLTAGE BOARD 3V3SUS VOLTAGE BOARD 2V5 VOLTAGE BOARD 2V5REF VOLTAGE BOARD 2V5SUS VOLTAGE BOARD 1V8 VOLTAGE BOARD 1V5 VOLTAGE BOARD 1V5SUS VOLTAGE BOARD 1V2SUS VOLTAGE BOARD 1V1 VOLTAGE BOARD VOLTAGE PWRGOOD EVENT ID BOARD POWER ID AMC B1 POWER AMC B2 POWER POWER OEM RESET ID WATCHDOG ID POST ERROR POST VALUE CRITICAL INT MEMORY ERR MOS MEMORY SIZE PASSWORD FWHO BOOT ERROR FWH1 BOOT ERROR FWUM 50 AT8020 WWW kontron com Board Features 2 16 Debugging Features 2 16 1 Lamp Test lamp test does the sequence shown below in the order 1 2 3 4 1 2 3 etc Step 415 not displayed when the regional bit is set for Europe no red allowed The lamp test can be initiated by keeping the reset pushbutton pressed LED arrangement and face plate finish may vary depending on board configuration No LEDs 1 All green amp blue LEDs 2 amber LEDs 3 All red LEDs 4 51 AT8020 www kontron com Installing the Board 3 Installing the Board 3 1 Setting Jumpers 3 1 1 Jumper Description Table 3 1 Jumper Description Watchdog When the jumper is ON it disables the watchdog JP1 1 2 Shelf Manager Activation When the jumper is ON it overrides the shelf manager activation JP1 3 4 IPMI When the jumper is ON the board is always on it overrides the IPMI JP1 5 6 AMC Activation When the jumper is ON it overrides the AMC activation JP1 7
70. Specification for Storage A subsidiary specification to the Advanced Mezzanine Card Base Specification 0 ANSI American National Standards Institute API Application Programming Interface APIC Advanced Programmable Interrupt Controller ASCII American Standard Code for Information Interchange ASCII codes represent text in computers communications equipment and other devices that work with text ATA Advanced Technology Attachment ATAPI Advanced Technology Attachment Packet Interface ATCA Advanced Telecommunications Computing Architecture BBS BIOS Boot Specification BI Base Interface Backplane connectivity defined by the ATCA BIOS Basic Input Output System BMC Base Management Controller CD Compact Disk CDROM Same as CD ROM Compact Disk Read Only Memory CD ROM Same as CDROM Compact Disk Read Only Memory CFM Cubic Foot per Minute CLI Command Line Interface CLK1 AdvancedTCA bused resource Synch clock group 1 CLK1A AdvancedTCA bused resource Synch clock group 1 bus A CLK1B AdvancedTCA bused resource Synch clock group 1 bus A CLK2 AdvancedTCA bused resource Synch clock group 2 CLK2A AdvancedTCA bused resource Synch clock group 2 bus A CLK2B AdvancedTCA bused resource Synch clock group 2 bus B CLK3 AdvancedTCA bused resource Synch clock group 3 CLK3A AdvancedTCA bused resource Synch clock group 3 bus A CLK3B AdvancedTCA bused resource Synch clock group 3 bus B CMOS Complementary Metal Oxide Semiconduct
71. TIUM VIRTIUM www kontron com 53 AT8020 Installing the Board Memory should have the following characteristics DDR2 400 1 8V only Single sided or double sided 1 layer of BGA on PCB side X4 or X8 configuration supported Serial Presence Detect SPD EEPROM 72 bit DIMMs only 1 2 inch maximum height Registered and ECC DIMMs WARNING A Because static electricity can cause damage to electronic devices take the following precautions Keep the board in its anti static package until you are ready to install memory Wear a grounding wrist strap before removing the board from its package this will discharge any static electricity that may have built up in your body Handle the board by the faceplate or its edges www kontron com 54 AT8020 Installing the Board 3 3 1 Memory Installation Figure 3 2 Memory Installation anti static plane place the board so that you are facing the memory sockets Insert the memory module into any available socket aligning the notches on the module with the socket s key inserts Push down the memory module until the retaining clips clip on each side Repeat these steps to populate the other socket To remove a memory module from a socket push sideway the retaining clips on each side of the socket to release the module Pull out the memory from the socket 55 AT8020 www kontron com Instal
72. TR 2 6 RX TX 3 7 05 GND DCD 4 8 CTS C 5 TelcoClock J17 1 CLK1A CLK1A CLK1B CLK1B CLK2A CLK2A 2 Tx4 UP Tx4 UP Rx4 UP Rx4 UP CLK3A CLK3A 3 Tx2 UP Tx2 UP Rx2 UP Rx2 UP Tx3 UP Tx3 UP 4 Tx0 UP Tx0 UP RxO UP RXO UP Tx1 UP Tx1 UP 5 Tx2 15 N C Txe 15 N C Rx2 15 N C Rxe 15 N C Tx3 15 N C 3 151 6 TxO 15 N C TxO 15 N C 15 Rxo 15 N C Tx1 15 N C Tx1 15 N C 7 Tx2 14 N C Tx2 14 N C Rx2 14 N C Rxe 14 N C Tx3 14 N C Tx3 14 N C 8 TxO 14 N C TxO 14 N C RxO 14 N C Rxo 14 N C Tx1 14 N C Tx1 14 N C 9 Tx2 13 N C Tx2 13 N C Rx2 13 N C Rxe 13 N C Tx3 13 N C Tx3 13 N C 10 TxO 13 N C TxO 13 N C Rxo 13 N C Rxo 13 N C Tx1 13 N C Tx1 13 N C ROW G ROW H ROW AB ROW CD ROW EF ROW GH GND GND GND GND 1 CLK2B CLK2B 2 CLK3B CLK3B GND GND GND GND 3 Rx3 UP Rx3 UP GND GND GND GND 4 Rx1 UP Rx1 UP GND GND GND GND 5 Rx3 15 N C Rx3 15 N C GND GND GND GND 6 1 15 Rx1 15 N C GND GND GND GND 7 Rx3 14 N C RG 14 N C GND GND GND GND 8 Rx1 14 N C Rx1 14 N C GND GND GND GND 9 Rx3 13 N C Rx3 13 N C GND GND GND GND 10 Rx1 13 N C Rx1 13 N C GND GND GND GND 23 8020 WWW kontron com C 6 B1 GND B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
73. Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Coh 02h 00315Ah gt PICMG Record ID 14h ATCA Board Point To Point Connectivity Record 00h 00h 00001101 h Oh gt Single Channel Link Oh None O1h gt PICMG 3 0 Base Interface 10 100 1000 Base T 101h gt Base Interface Channel 1 Port 0 00001102 h Oh gt Single Channel Link Oh None O1h gt PICMG 3 0 Base Interface 10 100 1000 Base T 102h gt Base Interface Channel 2 Port 0 00002341 h Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h gt PICMG 3 1 Ethernet Fabric Interface 341h gt Fabric Interface Channel 1 Port 0 amp 1 00002141 h Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h gt PICMG 3 1 Ethernet Fabric Interface 141h gt Fabric Interface Channel 1 Port 0 00002441h Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h PICMG 3 1 Ethernet Fabric Interface 441h gt Fabric Interface Channel 1 Port 2 00002342 h Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h PICMG 3 1 Ethernet Fabric Interface 342h gt Fabric Interface Channel 2 Port 0 amp 1 00002142 h 25 AT8020 www kontron com Board Features Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link Type Ext
74. UP RR 83 5 3 Console Redirection VT100 Mode rn ye heh 83 5 3 1 5 83 5 3 2 Running Without 2 84 5 333 100 Keystroke 0 84 5 3 4 VI UTF8 Keystroke 0 85 5 4 Installing Drivers ES AR 85 iv AT8020 www kontron com Table of Contents A Memory Y A MemoryMapping c ocior eh ra setae enr E nra A 1 A2 IUU0Mappiltj ae seek ER ERE REX A 2 PCIIDSEL and Device numbers 15 524545 hr hr xa yh sex A 3 B Kontron Extension lt lt 1 B 1 TFPGA CPLD Registers 55 B 1 2 Sossaman Addressing 5 1 C Connector PIBUUES cios e i Wis Rex e C 1 Connectors and Headers 5 C 1 2 RIM Connector 17 C 2 6 3 USBPort 313
75. abled Logging Disabled Disabled System bus event logging disabled Memory Buffer Event Enabled Enabled Memory buffer event logging enabled Logging Disabled Disabled Memory buffer event logging disabled Enabled Enabled PCI error event logging enabled Disabled Disabled PCI error event logging disabled PCI Express Error Enabled Enabled PCI E error event logging enabled Logging Disabled Disabled PCI E errror event logging disabled PCI Express Error Masking YA 74 AT8020 www kontron com Software Setup 5 1 4 7 Mask duplicate Errors Mask Unsupported Requests 5 1 4 6 Ethernet BI Expansion ROM Ethernet FI Expansion ROM Ethernet MEZ Expansion ROM Ethernet 825510M Expansion ROM FC SAS Expansion ROM AMC Slot 1 Expansion ROM AMC Slot 2 Expansion ROM PCI Express Error Masking sub menu Yes No Yes No Yes Mask duplicate errors found in successive SMIinterrupts No Duplicate errors found in successive SMI interrupts are not masked Note Duplicate errors in single SMI interrupt are always masked Yes Unsupported request errors can be masked No Default mask is used Expansion ROM Configuration sub menu Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Initializes base interface PXE expansion ROM Disabled Base interface PXE expansion ROM not used If disabled
76. amage to hardware and tells you how to avoid the problem A WARNING Indicates potential for bodily harm and tells you how to avoid the problem A Disclaimer We have tried to identify all situations that may pose a warning or a caution condition in this user s guide However Kontron does not claim to have covered all situations that might require the use of a Caution or a Warning xi AT8020 www kontron com Unpacking Follow these recommendations while unpacking e Remove all items from the box If any items listed on the purchase order are missing notify Kontron customer service immediately Inspectthe product for damage If there is damage notify Kontron customer service immediately Save the box packing material for possible future shipment Powering Up the System Before any installation or setup ensure that the board is unplugged from power sources or subsystems If you encounter a problem verify the following items Make sure that all connectors are properly connected Verify your boot devices Ifthe system does not start properly try booting without any other 1 0 peripherals attached including AMC adapters Make sure your system provides the minimum DC voltages required at the board s slot especially if DC power is carried by cables If you are still not able to get your board running contact our Technical Support for assistance Adapter Cables Because adapter
77. ancedMC modules through Rear 1 0 One 2GBytes onboard flash drive Front Panel Serial RJ 45 USB Ethernet Management Port RJ 45 PICMG 3 0 PICMG AMC 0 Compatible PICMG 1 PICMG AMC 2 PICMG AMC 3 05 Save CMOS in NVRAM option Boot from gigabit Ethernet Base and Fabric interfaces Boot from Ethernet Management port Boot from SAS Boot from USB 2 0 Floppy CD ROM Hard Disk Auto configuration and extended setup Diskless Keyboard less and battery less operation extensions System and LAN BIOS shadowing HDD S M A R T support Advanced Configuration and Power Interface ACPI 1 0 2 0 amp 3 0 advanced thermal management such as overheat alarm and auto slow down Console redirection to serial port VT100 with CMOS setup access Field updateable BIOS Event SERR PERR correctable uncorrectable ECC POST errors PCI Express log support to IPMC Management Controller is compatible to 3 0 0 IPMI v1 5 rev 1 1 Management Controller is run time field reprogrammable without payload impact Robust fail safe reprogramming implementation which includes two firmware images that can perform automatic or manual rollback if a problem occurs during critical reprogramming phase Remote upgrade capability from all IPMI interfaces CPU Host Interface IPMB 0 LAN Management Controller self test which can detect failure under its c
78. anding ofthe timing relationships involved Note All options in Bold are the default settings The CMOS setup option described in this section is based on BIOS Version 3 40 The options and default settings may change in a new BIOS release When an asterisk is present in the menu this mean that this menu is optional and it will be present only with certain options N 62 AT8020 Software Setup 5 1 2 Menu Bar The Menu Bar at the top of the window lists these selections Main Use this menu for basic system configuration Advanced Use this menu to set the Advanced Features available on your system Security Use this menu to configure Security features Boot Use this menu to determine the booting device order System Management Use this menu to set the System Managment on your system Exit Use this menu to choose Exits option Use the left and right arrows keys to make a selection 5 20051 Use the keys listed in the legend bar the bottom to make your selections or exit the current menu chart on the following page describes the legend keys and their alternates F1 General Help windows see 4 1 2 2 Esc Exit this menu gt arrow keys Select a different menu Home or End Move cursor to top or bottom of window lt gt Select the Previous Value for the field lt gt Select the Next Value for the field F2 and F3 Change colors use
79. ate IPMI commands defined by the PICMG 3 0 specification are used for either granting or rejecting the E keys Additionnal E Keying is prodived for connectivity between the AMC carrier and the AMC bays as described in the Section 3 9 and 3 7 of the 0 RC 2 0 specification The Set Get Port State IPMI commands defined by the 0 specification are used for either granting or rejecting the E keys 24 AT8020 WWW kontron com Board Features 8 1558 FRU Multirecord 2 15 5 2 1 Type 14 Atca Board Point To Point Connectivity Record Table 2 8 Type 14 Atca Board Point To Point Connectivity Record Record Type ID Record format version Manufacturer ID PICMG Record ID Record Format Version OEM GUID Count Link Descriptor Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link Type Extension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 Link Descriptor Link Grouping ID Bits 31 24 Link
80. average heat production Intel Smart Cache Design allows two execution cores to share 2 MB of L2 cache reducing FSB traffic and enhancing system responsiveness Intel Advanced Thermal Manager supports new digital temperature sensors and thermal monitors on each execution core to enhance thermal monitoring accuracy Streaming SIMD Extensions 3 SSE3 provides significant performance enhancement for multi media applications Additional instructions designed to improve thread synchronization complex arithmetic graphics and video encoding Fully code compatible with existing Intel architecture based 32 bit application software FSB address data and response parity protection provides a key reliability and data integrity feature for the communications storage and other embedded market segments Enhanced 36 bit memory addressing supports up to 16 GB of DDR2 memory when paired with the Intel E7520 chipset www kontron com 6 AT8020 Board Features 2 2 2 Intel E7520 Chipset The Intel E7520 Memory Controller Hub includes PCI Express serial 1 0 technology and DDR2 memory technology to help increase 1 0 bandwidth and reduce system latency for data intensive applications It is the central hub for all data passing among the core system elements including processors memory PCI Express 1 0 and legacy 1 0 subsystems Product Highlights are listes below 222 1 Memory Intel E7520 chipset based platforms is designed t
81. ble through the Get Device SDR Info command All SDRs can be queried using Device SDR commands to the firmware Baseboard sensors that have been implemented are listed below Note 2 SDR is based on version SDR 38 17 AT8020 www kontron com Board Features 2 15 3 Table 2 6 IPMI Sensors IPMI Sensors 0 RW N e 10 11 12 13 14 15 16 17 18 19 20 FRUO Hot Swap FRU1 Hot Swap FRU2 Hot Swap FRU3 Hot Swap FRUO Reconfig Temp Air Inlet Temp CPU 0 Vcore Temp CPUO Temp CPU1 Temp DIMMA Inlet Temp DIMMB Inlet Temp DIMM Outlet Temp MCH Temp MCH Inlet Temp LAN BIntf Temp LAN FIntf Temp Mez Area Power Good Power Good Event VCORE 0 VCORE 1 ATCA Board FRU Hot Swap Sensor AMC Bay B1 Hot Swap sensor AMC Bay B2 Hot Swap sensor RTM Hot swap sensor Sensor Population Change on Carrier Upper Non Critical event 45 deg C Upper Critical event 50 deg C Upper Non Critical event 85 deg C Upper Critical event 90 deg C Upper Non Recoverable 105 deg C Temperature of CPU 0 Upper Non Critical event 85 deg C Upper Critical event 90 deg C Upper Non Recoverable 100 deg C Temperature of CPU 1 Upper Non Critical event 85 deg C Upper Critical event 90 deg C Upper Non Recoverable 100 deg C Upper Critical event 60 deg C Upper Non Critical event 55 deg C Upper Critical event 60 deg C Upper Non Critical event 55 deg C Upper Critical eve
82. ce is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDMAn UltraDMAn Enable Disabled 32 bit Data Transfer 71 AT8020 ron com Software Setup 5 1 4 4 5 Third IDE Master Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Third IDE Master Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the device is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDM
83. ces USB supports Plug and Play and hot swapping operations 05 level These features allow USB devices to be automatically attached configured and detached without reboot or running setup 7 AT8020 www kontron com Board Features Table 2 1 USB Connector Pinout 1 VCC 2 DATA 3 DATA 4 GND Signal Path The USB Port is available through the front plate J13 and through the RTM connector 2 4 Onboard Flash Drive There is a 2GBytes onboard flash drive on the AT8020 This drive is connected through the Primary IDE logical interface and is set in master mode This drive supports ATA IDE protocol with up to PIO Mode4 and Multi word DMA Mode 2 interface 2 5 Serial Ports Two serial ports are provided on board for asynchronous serial communications They support 8 byte FIFO buffers for transfer rates from 50bps to 115 2Kbps Each serial port is specified as follows Table 2 2 Serial Ports Communication Mode and Output Path Communication Mode Output Path Serial Port A COM1 RS 232 Front Plate Serial port or IPMI over LAN Serial Port B COM2 RS 232 RTM UART registers are individually addressable and fully programmable 2 5 1 X Serial Port 1 314 Serial Port A is buffered directly for RS 232 operation Signals include the complete signal set for handshaking modem control interrupt generation and data transfer Serial Port A 1 is automatically switched to the front plate when a terminal is c
84. ction sensor ACPI State General health status Aggregation of critical sensors This list is flexible and could be adjusted based on Customer requirements CPU 0 Status Includes the following supported offset type 00h IERR 05h Configuration Error 07h Processor Presence Detected no event www kontron com 20 AT8020 Board Features 54 55 56 57 58 59 60 61 62 63 64 CPU 0 ThermTrip CPU 1 Status CPU 1 ThermTrip Memory POST Value POST Error Critical Int Boot Error CmosMemorySize Preboot Password FWH 0 Boot Error 01h Thermal Trip CPU 1 Status Includes the following supported offset type 00h IERR 05h Configuration Error 07h Processor Presence Detected no event O1h Thermal Trip Memory Status Includes the following supported offset type 00h Correctable ECC O1h Uncorrectable ECC 03h Memory Scrub Failed stuck bit 04h Memory Device Disabled 05h Correctable ECC Memory logging limit Reach Current POST Code Generates an event with current post CODE in data2 data3 System Firmware Progress Includes the following supported offset type 00h System Firmware Error Post Error Event Data 2 00h Unspecified CMOS settings wrong CMOS checksum bad CMOS Date Time Not set O1h No system memory is physically installed in the system 02h No usable system memory 03h Unrecoverable hard disk ATAPI IDE device
85. d This will discharge any static electricity that may have built up in your body e When transporting a sensitive component first place it in an antistatic container or packaging Handle all sensitive components at an ESD workstation If possible use antistatic floor pads and workbench pads Handle components and boards with care Don t touch the components or contacts on a board Hold a board by its edges or by its metal mounting bracket Donothandle or store system boards near strong electrostatic electromagnetic magnetic or radioactive fields When you wantto remove the protective foil if present make sure you are properly grounded and that you touch a metalic part of the board A CAUTION A Removing the protective foil from the top and bottom cover might create static A When you remove those protections make sure you follow the proper ESD procedure ix AT8020 www kontron com Preface Preface How to Use This Guide This user s guide is designed to be used as step by step instructions for installation and as a reference for operation troubleshooting and upgrades For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned The following is a summary of chapter contents Chapter 1 Product Description Chapter 2 Board Features Chapter 3 Installing the board Chapter 4 Building Syst
86. d from its enclosure WARNING Always use grounding wrist wrap before installing or removing the board from a A chassis 3 5 1 Installing the Board in the Chassis To install a board in a chassis 1 Remove the filler panel ofthe slot or see Removing the Board below 2 Ensurethe board is configured properly 3 Carefully align the PCB edges in the bottom and top card guide 4 Insert the board in the system until it makes contact with the backplane connectors 5 Using both ejector handles engage the board in the backplane connectors until both ejectors are locked 6 Fasten screws at the top and bottom of the faceplate 3 5 2 Removing the Board If you would like to remove a board from your chassis please follow carefully these steps 1 Unscrew the top and the bottom screw of the front panel 2 Unlockthe lower handle latch depending on the software step this may initiate a clean shutdown of the operating system 3 Waituntil the blue LED is fully ON this mean that the hot swap sequence is ready for board removal 4 Use both ejectors to disengage the board from the backplane 5 Pull the board out of the chassis 57 AT8020 www kontron com Installing the Board 3 5 3 Installing AMC To install an AMC 1 Remove the AMC filler panel 2 Carefully engage the AMC into the card guide Push the until it fully mates with it s connector Secure the AMC handle to the locking position 3 In normal condi
87. d in Setup F7 Disacard the changes for all menus F9 Load the Optimal Default Configuration values for all menus lt F10 gt Save and exit lt Enter gt Execute Command display possible value for this field or Select the sub menu To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field To save value commands in the Exit Menu save the values displayed in all menus To display a submenu use the arrow keys to move the cursor to the submenu you want Then press lt Enter gt A pointer 2 marks sub menus 5122 Field Help Window The help window on the right side of each menu displays the help text for the selected field It updates as you move the cursor to each field 63 AT8020 WWW kontron com Software Setup 5 18 2 General Help Windows Pressing lt F1 gt on any menu brings up the General Help window that describes the legend keys and their alternates General Help lt Select Screen T Select Item Change Option Field Enter Go to Sub Screen PGDN Next PGUP Previous Page HOME Go to Top of Screen END Go to Bottom of Screen F2 F3 Change Colors F7 Discard Changes F10 Save and Exit F9 Load Optimal Defaults 5 Exit OK 64 AT8020 www kontron com Software Setup 5 1 3 Main Menu BIOS Version Build Date BIOS ID Boot Block Version FPGA Version Channel A
88. devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices Disabled Enabled device write protection This will be effective only if device is accessed through BIOS Configures the time out value for detecting ATA ATAPI device s www kontron com 67 AT8020 Software Setup 5 1 4 4 1 Primary IDE Master Type LBA Large Mode Block Multi Sector Transfer PIO Mode DMA Mode 32Bit Data Transfer Primary IDE Master Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S M A R T Not installed Auto CD DVD ARMD Disabled Auto Disabled Auto Auto SWDMAO SWDMA1 SWDMA2 MWDMAO MWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMA3 UDMA4 Disabled Enabled This is a list of modes and features supported by the drive not how it is setup Select the type of device connected to the system Disabled Disables LBA Mode Auto Enables LBA Mode if the device supports it and the device is not already formatted with LBA Mode3 disabled Disabled the data transfer from and to the device occurs one sector at the time Auto the data transfer from and to the device occurs multiple sector at a time it the device supports it Select PIO Mode Select DMA Mode Auto Auto detect SWDMAn SingleWordDMAn MWDMAn MultiWordDMAn UDMAn UltraDMAn Enable Disabled 32 bit Data Transfer 68 AT8020 ron com
89. duct conforms to the following specifications e PICMG3 0R2 0 Advanced TCA core specification e PICMG3 1R1 0 Ethernet Fiber Channel over Advanced TCA Compatible to 0 R2 0 Advanced mezzaninne card base specification e 1 R1 0 Advance mezzaninne card PCI Express 3 AT8020 ron com Product Description 1 5 Hot Plug Capability The AT8020 supports Full Hot Plug capability as per PICMG3 0R1 0 It can be removed from or installed in the system while itis on without powering down the system Please refer to the PICMG3 0R1 0 specification for additional details 1 6 Interfacing with the Environment 1 6 1 RTM rear transition module The RTM8020 is a single slot 6HP ATCA Rear Transition Module This module provides additional connectivity for AT8020 CPU front blade and complies to e PICMG3 0 R2 0 002 Advanced Telecommunication Computing Architecture SAS1R10 Serial Attached SCSI 1 1 Revision 10 SAS 1 1 SFF 8470 110 Technical Committee and SCSI Trade Association 1 6 2 AMC Mezzanine The AT8020 has two AMC bays Using a mezzanine allows to add storage or 1 0 not provided on board See Kontron s mezzanine offering for additional I O capabilities Both AMC sites provide the same feature set Each slot provides a AMC 1 type 8SE2 This mean that the following signalling are supported e PCI Express X4 on AMC port 4 7 PCI Express clock on FCLKA Gigabit Ethernet on AM
90. e Checkpoints section of document for more information 39 Initializes DMAC 1 amp DMAC 2 3A Initialize RTC date time 3B Test for total memory installed in the system Also Check for DEL or ESC keys to limit memory test Display total memory in the system 3C Mid POST initialization of chipset registers 40 Detect different devices Parallel ports serial ports and coprocessor in CPU etc successfully installed in the system and update the BDA EBDA etc 50 Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed 52 Updates CMOS memory size from memory found in memory test Allocates memory for Extended BIOS Data Area from base memory 60 Initializes NUM LOCK status and programs the KBD typematic rate 75 Initialize Int 13 and prepare for IPL detection 78 Initializes IPL devices controlled by BIOS and option ROMs 7 Initializes remaining option ROMs 7C Generate and write contents of ESCD in NVRam D 3 AT8020 www kontron com 84 Log errors encountered during POST 85 Display errors to the user and gets the user response for error 87 Execute BIOS setup if needed requested 8C Late POST initialization of chipset registers 8D Build ACPI tables if ACPI is supported 8E Program the peripheral parameters Enable Disable NMI as selected 90 Late POST initialization of system management interrupt 0 Check boot password if installed A1 Clean up wo
91. ect Output INIT Reset printer 1 normal ALF Auto Line Feed STRB Strobe B 10 AT8020 WWW kontron com C Connector Pinouts C 1 Connectors and Headers Summary Connector Description J7 J13 J14 J17 J20 921 223 1 USB 2 0 Connector Serial Port Connector Telco Clock Connector amp Fabric Interface AMC B1 Base Interface Connector AMC B2 Power Connector www kontron com 8020 2 1 0 RTM Connector 37 1 12V 1 V 12V 5 V 12V 2 V 3V2 SUS RTM EJECT RTM_PRSNT 2 V_12V_3 V_12V_6 V_12V_4 IPMC_INT IPMC_SCL IPMC_SDA 3 5 5 SP DTR SP RTS SP CTS SP DSR 4 Reserved Reserved Reserved Reserved RTML TX RTML RX 5 N C N C N C N C N C N C 6 N C N C N C N C N C N C 7 N C N C N C N C N C N C 8 N C N C N C N C N C N C 9 PO TX PO RX P1 TX P1 TX P1 TX 10 P2 P2 TX P2 RX P2 RX P3 P3 TX Pin ROW G ROW H ROW AB ROW CD ROW EF ROW GH 1 RTM_HS_LED RTM_EN 2 USB1_D R USB1_D R GND GND GND GND 3 GND GND GND GND 4 RTML CLK N C GND GND GND GND 5 N C N C GND GND GND GND 6 N C N C GND GND GND GND 7 N C GND GND GND GND 8 N C N C GND GND GND GND 9 P1_RX P1_RX GND GND GND GND 10 P3_RX P3_RX GND GND GND GND USB Port 313 1 DATA 2 DATA 3 GND 4 C 2 AT8020 www kontron com C 4 Serial 314 RTS 1 5 GND D
92. ee section 5 1 set the following parameters Remote Access to enabled Primary Serial port number to COM1 or both for dual output COM1 and COM2 Serial Port Mode to the desire speed e Flow control to Software or hardware Flow control is required do not use None Terminal type to the desire value The recommended IPMI Over Lan Serial Over LAN tools for Linux is IPMITool This utility is available from the following web site http ipmitool sourceforge net index html 2 15 8 IPMC Firmware Code IPMC firmware code is organized into boot code and operational code both of which are stored in a flash module Upon an IPMC reset the IPMC executes the boot code and performs the following 1 Selftestto verify the status of its hardware and memory 2 Performs a checksum of the operational code 3 Communicates with the Firmware Upgrade Manager FWUM in order to inform the IPMC watchdog that the actual IPMC firmware is suitable for execution Upon successful verification of the operational code checksum the firmware will jump to the operational code 2 15 9 Updating the AT8020 To update the software of your board it is recommended to use the Kontron update CD A version of this CD can be found on the CD DVD provided with your board The latest version is available from the Kontron Canada s FTP site 37 AT8020 www kontron com Board Features 2 15 10 IPMI Commands Set The next table presents
93. em Chapter 5 Software Setup Appendix A Memory amp 1 0 Maps Appendix B Extension Registers Appendix C Connector Pinout Appendix D BIOS Setup Error Codes e Appendix Software Update e Appendix F Getting Help Appendix G Glossary 8020 www kontron com Customer Comments If you have any difficulties using this user s guide discover an error or just want to provide some feedback please send a message to Tech Writer ca kontron com Detail any errors you find We will correct the errors or problems as soon as possible and post the revised user s guide on our Web site Advisory Conventions Seven types of advisories are used throughout the user guides to provide helpful information or to alert you tothe potential for hardware damage or personal injury They are Note Signal Paths Jumpers Settings BIOS Settings Software Usage Cautions and Warnings The following is an example of each type of advisory Use caution when servicing electrical components 101 900 00101 101 Pp Note Indicate information that is important for you to know Signal Path Indicate the places where you can fin the signal on the board Jumper Settings Indicate the jumpers that are related to this sections BIOS Settings Indicate where you can set this option in the BIOS Software Usage Indicates how you can access this feature through software CAUTION Indicate potential d
94. ements exceed carrier power budget or SetPowerLevel 0 has been received while in M2 or M3 As per AMC O ifthe current draw requirements exceed AMC O carrier power budget the AT8020 will keep the AMC in M1 state with the blue HotSwap LED in the ON state 2 15 12 4 Health Led ATCA LED 2 The AT8020 supports a green amber health LED mounted on the front panel The LED is located under the 005 Led The on board FWUM or the IPMC can drives this LED to indicate the health status The OEM application can also drive this LED using the PICMG LED control APIs The following states are possible Table 2 29 Health Led ATCA LED 2 State Green Health OK Amber Health Error Critical Payload power down or in reset Application Defined be controlled by an application using PICMG Other application defined LED usage may be implemented Below is the Health sensors agregation Table 2 30 Health LED Sensors Agregation Sensor Name TEMP BOARD INLET ID TEMP VCORE ID TEMP CPUO DIODE ID TEMP CPU1 DIODE ID TEMP DIMM CHNLA INLET ID TEMP DIMM CHNLB INLET ID TEMP DIMM OUTLET ID TEMP MCH TEMP ID TEMP MCH INLET ID TEMP BI OPHIR ID TEMP FI OPHIR ID TEMP MEZ ID TEMP BOARD INLET ID BOARD VCORE CPUO VOLTAGE 49 AT8020 WWW kontron com Board Features Sensor Name BOARD VCORE CPU1 VOLTAGE BOARD DMX 5 VOLTAGE BOARD NEGA48V VOLTAGE BOARD 12V VOLTAGE BOARD 5V VOLTAGE BOARD 5V
95. ension Bits 23 20 Link Type Bits 19 12 Link Designator Bits 11 0 2 15 5 2 2 Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h PICMG 3 1 Ethernet Fabric interface 141h gt Fabric Interface Channel 2 Port 0 00002442 h Oh gt Single Channel Link Oh gt Fixed 1000 Base BX 02h PICMG 3 1 Ethernet Fabric interface 442h gt Fabric Interface Channel 2 Port 2 Type 17 Carrier Activation And Current Management Record Table 2 9 Type 17 Carrier Activation And Current Management Record Record Type ID Record format version Manufacturer ID PICMG Record ID Record Format Version Maximum Internal Current Allowance for Module Activation Readiness Module Activation and Power Descriptor Count Carrier Activation and Power Descriptors Local IPMB Address Maximum Module Current Reserved Carrier Activation and Power Descriptors Local IPMB Address Maximum Module Current Reserved Carrier Activation and Power Descriptors Local IPMB Address Maximum Module Current Reserved 02h 00315Ah 17h 00h 1Eh 3 0 Amps at 12 V gt 36 Watts 002h 03h 7Ah 19h FFh 7Ah 19h 2 5 Amps at 12 V gt 30 Watts FFh 7Ch 19h FFh 7Ch 19h 2 5 Amps at 12 V 2 30 Watts FFh 90h 15h FFh 90h 15h 2 1 Amps at 12 V gt 25 2 Watts FFh 26 AT8020 ron com Board Features 2 15 5 2 3 18 Carrier Point To Point Connectivity Record Table 2 10 Type 18 Carrier Point To
96. er Board Reset EventRcv ComLost IPMI Watchdog IPMBO Link State FRUO IPMBL State FRU1 IPMBL State FRU2 IPMBL State FRU23IPMBL State ACPI State Health Error CPU 0 Status Voltage on 1 2v suspend management board power supply Upper Critical event 1 26v 10 Lower Critical Event 1 14v 10 Hysteresis 0 018v 1 5 Voltage on 1 2v board power supply Upper Critical event 1 16v 1096 Lower Critical Event 1 04v 10 Hysteresis 0 017v 1 5 Voltage on the memory 1 05 Upper Critical event 1 11v 1096 Lower Critical Event 0 99v 1096 Hysteresis 0 016v 1 5 Fuse presence and fault detection 48 V on supply A Fuse presence and fault detection 48 V on supply B FRU 0 Power consumption in watts Upper Critical 0 180 480 Upper Non Critical 0 165 120 FRU 1 Power consumption in watts Upper Critical 0x40 30 080 Upper Non Critical 27 260 FRU 2 Power consumption in watts Upper Critical 0x40 30 080 Upper Non Critical 427 260 FRU 3 Power consumption in watts Upper Critical 0x72 24 966 Upper Non Critical 0x61 21 243 System Reset Specify if the communication with the event receiver has been lost IPMIWatchdog As defined in the IPMI specification 0 fault detection sensor As defined by PICMG 3 0 specification IPMB L fault detection sensor IPMB L fault detection sensor IPMB L fault detection sensor IPMB L fault dete
97. er card would mean the daughter card s 82571 Ethernet ports wouldn t be connected to the Fabric Channel 1 P1 and Channel 2 P1 WWW k on com 14 AT8020 Board Features 2 11 Redundant BIOS Flash Two BIOS flashes firmware hub or FWH are present on the AT8020 If a BIOS update corrupts a flash and prevents the CPU from completing the boot sequence the IPMC will force a reboot from the other BIOS flash Note A Since the CMOS setup is saved in flash this will also restore the previous BIOS setup 2 12 Redundant IPMC Flash amp FWUM IPMC runs a firmware from its internal 512KB flash It is programmed by an other microcontroller named FWUM Firmware Update Manager The FWUM keeps the last two copies of the IPMC firmware in dedicated flash memories The FWUM acts as a watchdog to the IPMC and can rollback a firmware update in the IPMC in case of problems The FWUM itself is a microcontroller with internal flash FWUM firmware is field updatable possibly with payload impact however Note and the FWUM have an internal hardware watchdog 2 13 The FPGA has many functions One of them is to act as a companion chip to the IPMC The states of all the critical signals controlled by the IPMC are memorized in the FPGA and are preserved while the IPMC firmware is being updated The FPGA is a RAM based chip that is preloaded from a separate flash memory at power up Two such flash memory de
98. ess Bining Blue short blink when deactivation is in progress Solid Blue Ready for hot swap 2 15 12 2 Ejector Mechanism In addition to captive retaining screws the AT8020 has two ejector mechanisms to provide a positive cam action this ensures the blade is properly seated The bottom ejector handle also has a switch that is connected to the IPMC 215 123 005 Led LED 1 The AT8020 supports a red Out Of Servive LED mounted on the front panel The LED is near the Lan A connector The on board FWUM or the IPMC can drives this LED to indicate the service state of the IPMC The OEM application can also drive this LED using the PICMG LED control APIs The following states are possible Table 2 27 OOS Led ATCA LED 1 State OFF Normal Idle board is in service unless blue led is on ON Out of service condition IPMC is hold in reset Power denied condition detected Short blink Payload has been left in M3 for more than 30secs or SetPowerLevel 0 has been received while in M2 or M3 Blink 50 50 The FWUM is currently programming the IPMC Other application defined LED usage may be implemented The 8020 0 carrier board also implements the 005 LED Short blink mode for its AdvancedMC mates on detection of power denied conditions 48 AT8020 www kontron com Board Features Table 2 28 00S Led ATCA LED 1 Short Blink Mode Power denied condition detected Short blink AMC current draw requir
99. est Data 158 first MSB last 4 Device to select port see below 1 Completion Code 2 Kontron IANA number 003A98h Response Data LSB first MSB last 5 Device channel port selection see below 6 Device channel port HW setting see below Device list 19h PCIe Clock Channel port list 19h PCIe Clock SSC Mode 1Ah PCIe Clock Non SSC Mode 45 AT8020 WWW kontron com Board Features 2 15 11 5 SetBoardDeviceChannelPortSelection This command selects the onboard device port routing as specified in the request data bytes The command is available on any working interface Table 2 23 SetBoardDeviceChannelPortSelection Kontron IANA number 003A98h ub LSB first MSB last Reguest Data 4 Device to select port see below 5 Device channel port selection see below 1 Completion Code Response Data 27 number 003A98h LSB first MSB last Device list 19h PCIe Clock Channel port list 19h PCIe Clock SSC Mode 1Ah PCIe Clock Non SSC Mode 2 18 11 0 Controls Identifier Table This table lists the control identifiers that can be used with Set Get Control State IPMI commands to query or set information on certain controls in the firmware Table 2 24 Controls Identifier Table Control Description Control Number FWH Hub for BIOS bank information O 0 46 AT8020 WWW kontron com Board Features 2 15 12 Hot Swap Process The AT8020 has the ability to be hot swapped in and out of a
100. f this second microcontroller is the Firmware Upgrade Manager FWUM The FWUM can handle two Firmware codes that are stored in two external SEPROM memories If a failure occurs during firmware upgrade the FWUM will automatically rollback to the redundant IPMC firmware image 2 15 2 Sensor Data Record SDR Every sensor on the baseboard is associated with a Sensor Data Record SDR Sensor Data Records contain information about the sensors identification such as sensor type sensor name sensor unit SDR also contain the configuration of a specific sensor such as threshold hystheresis event generation capabilities that specifies sensor behavior Some field of the sensor SDR are configurable through IPMI v1 5 command and are set to built in initial value Finally one field which is the sensor owner must reflect the baseboard addresses that allow the ShMc to identify the owner of the SDR when it is scanned from the satellite management controller and saved within the ShMc SDR repository The AT8020 management controller is set up as a satellite management controller SMC It does support sensor devices and use the IPMI dynamic sensor population feature of IPMI v1 5 to merge the hot swapped AMC and RTM sensors with the AT8020 sensors population The usual way the ShMc is informed about an AMC insertion is through the AMC carrier Hot Swap sensor However to remain compliant to IPMI v1 5 the IPMC updates the population change indicator timestamp accessi
101. formation Agent scan used for E Keying Associated event reading type code OAh DMI Based Availability Sensor indicating the BIOS POST error code Associated event reading type code 6Fh IPMI Sensor Specific Formerly 78h OEM POST value Sensor Sensor indicating the state of the Firmware Update Manager for rollback and such FWUM Status C7h Associated event reading type code 6Fh IPMI Sensor Specific Formerly 79h OEM FWUM Status FIA Error Sensor C5h Post Value Sensor C6h 2 15 5 Field Replaceable Unit FRU Information The FRU Information provides specific data about a board for servicing usage Typical information like the part number and board s version can be read via IPMI software tools This information is retrieved by the shelf manager ShMC enabling reports of board specific information through an out of band mechanism The following are definitions of multirecord implemented by the firmware as part of FRU data 2 15 5 1 E Keying E Keying has been defined in the PICMG 3 0 Specification to prevent board damage prevent misoperation and verify fabric compatibility The FRU data contains the board point to point connectivity record as described in Section 3 7 2 3 of the PICMG 3 0 specification When the board enters M3 power state the shelf manager reads in the board point to point connectivity record from FRU and determines whether the board can enable the Fibre Channel ports to the back plane Set Get Port St
102. h the receiver is connected Consultthe dealer or an experience radio TV technician for help WARNING This is Class B product If not installed in a properly shielded enclosure and used in A accordance with this User s Guide this product may cause radio interference in which case users may need to take additional measures at their own expense Safety Certification All Kontron equipment meets or exceeds safety requirements based on the IEC EN UL CSA 60950 1 family of standards entitled Safety of information technology equipment All components are chosen to reduce fire hazards and provide insulation and protection where necessary Testing and reports when required are performed under the international IECEE CB Scheme Please consult the Kontron Safety Conformity Policy Guide for more information For Canada and USA input voltage must not exceed 60Vdc for safety compliance CE Certification The product s described in this user s guide complies with all applicable European Union CE directives if it has a CE marking For computer systems to remain CE compliant only CE compliant parts may be used Maintaining CE compliance also requires proper cable and cabling techniques Although Kontron offers accessories the customer must ensure that these products are installed with proper shielding to maintain CE compliance Kontron does not offer engineering services for designing cabling systems In addition Kontron will not retest o
103. hecksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K Consult www intel com for additional details on the 182571 The AT8020 has boot from LAN capability PXE on those ports This option must be enabled from the BIOS Setup Program BIOS Settings 01 00 0101 Advanced gt Expansion ROM Configuration gt Ethernet MEZ Expansion ROM 2 8 SAS Daughter Card SAS interface is provided through a daughter card Both AMC slots have the same SAS connectivity For a particular AMC there is one link from the SAS controller to the AMC for an AMC based SAS HDD and a second link is connected directly from the AMCto the RTM The SAS controller used on the daughter card is the LSISAS1064e from LSI SAS HDD can be used either with one CPU board no connection to the RTM or as a two CPU boards two HDD redundant pair In this case both CPU boards have access to both HDDs via the RTM and cabling 11 AT8020 WWW kontron com Board Features 2 9 Crosspoint Switches The crosspoint switches are multiport devices that allow connecting any inputs to any ouputs Two 8x8 crosspoint switches are used Vitesse VSC3108 Those switches are protocol agnostic and can carry SERDES type signals at up to 6 5Gb s NRZ data This means that any compatible endpoint can be connected The connectivity is controlled by the IPMI e keying After the initialisation the configuration is static The crosspoint switches also ac
104. inal document of purchase a full description of the application the product is used on and a description of the defect Pack the product in such a way as to ensure safe transportation see our safety instructions Kontron provides for repair or replacement of any part assembly or sub assembly at their own discretion or to refund the original cost of purchase if appropriate In the event of repair refunding or replacement of any part the ownership of the removed or replaced parts reverts to Kontron and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report issued by Kontron with the repaired or replaced item Kontron will not accept liability for any further claims resulting directly or indirectly from any warranty claim other than the above specified repair replacement or refunding In particular all claims for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time are excluded The extent of Kontron liability to the customer shall not exceed the original purchase price of the item for which the claim exists Kontron issues no warranty or representation either explicit or implicit with respect to its products reliability fi
105. is sent using the Broadcast format on IPMB See command description for details 2 SeeICMB specification for details If an ICMB is implemented then these commands are mandatory However methods to implement dual Shelf Managers with ICMB interfaces are not defined by either PICMG 3 0 or the ICMB specification 3 Additional constraints apply see appropriate IPMI v1 5 section for details 4 PICMG 3 0 requires IPMB 0 Channel 0 for SMC to IPM Controller communication 5 PICMG 3 0 doesn t require the implementation of KCS SMIC or BT system interfaces on any IPM controller including a ShMC PICMG 3 0 designates a Payload Interface between an IPM Controller and its Payload but does not constrain the implementation of that interface However if any IPMI defined system interface is to be implemented these commands are mandatory 6 The Shelf Manager shall apply this command to an entire Shelf 7 PICMG 3 0 does not require a centralized SDR Repository in the Shelf Manager though a partial SDR repository is necessary the Shelf Manager 8 IPMIdoes not allow for multiple SELs However PICMG 3 0 does allow for optional SELs on the IPM Controllers since it may be appropriate for some architectures 9 These commands are required if a System Manager Interface or other Channels are supported 10 All AdvancedTCA and PICMG specific request commands use the NetFN 2Ch with the PICMG identifier The response uses NetFN 2Dh with the PICMG identifie
106. l you must include your name your company name your address your city your postal zip code your phone number and your e mail You must also include the serial number of the defective product and a description of the problem When Returning a Unit In the box you must include the name and telephone number of a contact person in case further explanations are required Where applicable always include all duty papers and invoice s associated with the item s in question Ensure that the unit is properly packed Pack itin a rigid cardboard box Clearly write or mark the RMA number on the outside of the package you are returning Ship prepaid We take care of insuring incoming units www kontron com North America EMEA Kontron Canada Inc Kontron Modular Computers GmbH 4555 Ambroise Lafortune Sudetenstrasse 7 Boisbriand Qu bec 87600 Kaufbeuren J7H 0A4 Canada Germany F2 AT8020 Glossary Advanced Configuration amp Power Interface AdvancedMC Same as AMC Advanced Mezzanine Card AMC Same as AdvancedMC Advanced Mezzanine Card 0 Advanced Mezzanine Card Base Specification PCI Express and Advanced Switching on AdvancedMC subsidiary specification to the Advanced Mezzanine Card Base Specification 0 Ethernet Advanced Mezzanine Card Specification A subsidiary specification to the Advanced ANCE Mezzanine Card Base Specification AMC 0 AMC 3 Advanced Mezzanine Card
107. ld reset initiated by IPMC 1000 Warm reset initiated by IPMC 1001 Warm reset initiated by front panel pushbutton Others reserved B 8 AT8020 WWW kontron com B 2 14 AOBh Mezzanine Identification eene Read LoopIn MezzPr MezzID3 MezzID2 MezzID1 MezzIDO AOCh Write NU NU LoopOut NU NU NU NU NU PowerUp NU NU 0 NU NU NU NU NU MezzPr Indicate that the PCI Express mezzanine daughter card piggy back storage mezzanine is present If not present MezzID is not valid see below Note that this bit will not switch to 1 immediately on a power up The FPGA has to read the mezzanine identification through a shift register As soon as the ID has been read the presence bit is asserted MezzID Mezzanine ID Indicate the type of mezzanine that is present If MezzPr 0 this field is meaningless Currently supported mezzanines are listed in the table below Note that the FPGA reads the mezzanine information continuously but some delay is required immediately at power up The IPMI subsystem is left in reset as long as the status of the mezzanine is unknowned 0 XXXX No mezzanine board 1 1111 SATA Bypass mezzanine Fully passive The FPGA does nothing special for this one 1 0001 T5511 SAS only mezzanine The FPGA will sequence the power supplies and grab various statuses from the mezzanine 1 0010 FC mezzanine The FPGA will sequence the power supplies and grab various statuses from the mezzanine 1
108. le Data SSH Secure SHell A network protocol that allows data to be exchanged over a secure channel between two computers TCLKA Telecom CLocK A AMC Clock Interface TCLKB Telecom CLocK B AMC Clock Interface TCLKC Telecom CLocK C AMC Clock Interface TCLKD Telecom CLocK D AMC Clock Interface TX Transmit TXD Transmit UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VCC Power supply VLAN Virtual Local Area Network XAUI a ten Attachement Unit Interface A standard for connecting 10 Gigabit Ethernet 10GbE G 4 AT8020 www kontron com
109. les and contains two fields The details of the high byte of these checkpoints are as follows HIGH BYTE XY The upper nibble X indicates the function number that is being executed X can be from 0 to 7 0 funcitO disable all devices on the BUS concerned 1 func 1 static devices initialization on the BUS concerned 2 func 2 output device initialization on the BUS concerned 3 func 3 input device initialization on the BUS concerned 4 func 4 IPL device initialization on the BUS concerned 5 func 5 general device initialization on the BUS concerned 6 func 6 error reporting for the BUS concerned 7 func 7 add on ROM initialization for all BUSes 8 func 8 BBS ROM initialization for all BUSes The lower nibble Y indicates the BUS on which the different routines are being executed Y can be from 0 to 5 D 5 AT8020 www kontron com 0 Generic DIM Device Initialization Manager 1 2 On board System devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices D 5 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state The following table describes the type of checkpoints that may occur during ACPI sleep or wake events AC First ASL check point Indicates the system is running in ACPI mode AA System is running in APIC mode 01 02 03 04 05 Entering sleep state 51 52 53 54 or S5 10
110. ling the Board 3 4 Onboard Interconnectivity and Indicators 3 4 1 Onboard Connectors and Headers Table 3 2 Onboard Connectors and Headers CPU J5 Second CPU CPU J6 First CPU This CPU must always be present RTM Connector J7 RTM connector to connect to the RTM8020 DDR 2 Memory Connectors 38 39 310 amp 311 4angled memory sockets 212 USB 2 0 Connector J13 Serial Port J14 RJ45 serial port connector Telco Clock Connector amp Fabric Interface i Daughter Card Connectors J18 amp J19 AMCB1 J20 Base Interface Connector J21 AMC B2 J23 Power Connector P1 3 4 2 Front Plate Symbol Chart Figure 3 3 Front Plate Symbol Chart Out Of Service 7 Hot Swap lt gt Management IPMI Serial Port Base Interface 8 User Defined F Healthy 4 Reset lt gt USB Ethernet FI Fabric Interface Ej Flash or SAS Drive 56 AT8020 www kontron com Installing the Board 3 5 Board Hot Swap and Installation Because of the high density pinout of the hard metric connector some precautions must be taken when connecting or disconnecting a board to from a backplane 1 Rail guides must be installed on the enclosure to slide the board to the backplane 2 Do not force the board if there is mechanical resistance while inserting the board 3 Screw the frontplate to the enclosure to firmly attach the board to its enclosure 4 Useextractor handles to disconnect and extract the boar
111. m setups and capabilities contact our Technical Support at North America EMEA Tel 450 437 5682 Tel 49 0 8341 803 333 Fax 450 437 8053 Fax 49 0 8341 803 339 If you have any questions about Kontron our products or services visit our Web site at www kontron com You also can contact us by E mail at North America support ca kontron com EMEA support kom kontron com Or at the following address North America EMEA Kontron Canada Inc Kontron Modular Computers GmbH 4555 Ambroise Lafortune Sudetenstrasse 7 Boisbriand Qu bec 87600 Kaufbeuren J7H 0 4 Canada Germany F 1 Returning Defective Merchandise Before returning any merchandise please do one of the following all 1 Call our Technical Support department in North America at 450 437 5682 and in EMEA at 49 0 8341 803 333 Make sure you have the following on hand our Invoice your Purchase Order and the Serial Number of the defective unit 2 Providethe serial number found on the back of the unit and explain the nature of your problem to a service technician F 1 AT8020 www kontron com E mail F 2 The technician will instruct you on the return procedure if the problem cannot be solved over the telephone Make sure you receive RMA from our Technical Support before returning any merchandise Send us an e mail at RMA 2ca kontron com in North America and at orderprocessing 2 kontron modular com in EMEA In the e mai
112. mance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K Consult www intel com for additional details on the 182571 The AT8020 has boot from LAN capability PXE on those ports This option must be enabled from the BIOS Setup Program wits BIOS Settings 10108 Advanced gt Expansion ROM Configuration gt Ethernet BI Expansion ROM 10 AT8020 WWW kontron com Board Features 2 7 3 182571 Fabric Interface Port 0 A second 182571EB is used Both ethernet ports are routed to the fabric channel port 0 The fist one is connected to channel 1 and the second is connected to channel 2 The i82571EB features high performance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K Consult www intel com for additional details on the 182571 The AT8020 has boot from LAN capability PXE on those ports This option must be enabled from the BIOS Setup Program wits BIOS Settings 900 22108 Advanced gt Expansion ROM Configuration gt Ethernet FI Expansion ROM 2 7 4 182571EB Fabric Interface Port 1 Daughter Card Athird 182571EB is used in various configurations through a daughter card Both ethernets ports are routed to the fabric channel 1 and channel 2 of port 1 The fist one is connected to channel 1 and the second is connected to channel 2 The 182571EB features high performance with TCP IP and UDP IP c
113. memory configuration Es Disabled Memory RAS features disabled Enabled Enabled DMA controller enabled Disabled Disabled DMA controller disabled 3 9 uS 78 Allows override selection of the DDR2 refresh rate for normal SH operation Auto Enabled Allows setting of Clock Spread Spectrumfor EMI Enabled control Disabled Disabled Denies setting of Clock Spread Spectrum for EMI control 5 1 5 Security Menu Supervisor Password User Password Set Supervisor Password Set User Password Clear User Password User Access Level Execute Disable Bit I f in AN d Indicates the status of the supervisor password I 4 Indicates the status of the user password Enter Install or change the supervisor password Only the first 5 characters will be used Enter Install or change the user password Only the first 5 characters will be used Enter Clears user password L h ility tee Controls access to the setup utility No Access Prevents user access View Only Limited View only allows read only user access Full Access Limited Allows limited fields to be changed Full Access Allows unlimited user access Enabled Allows processor to prevent application code access Enabled to certain memory areas Needs supporting operating system Disabled Disabled No restrictions to application code memory area access by processor www kontron com 77 AT8020 Software Setup 5 1 6 Boot Menu eade N A Config
114. n HW HardWare 12 Inter Integrated Circuit bus ICH 1 0 Controller Hub ICT In Circuit Test ID IDentification IEEE Institute of Electrical and Electronics Engineers Intel Mobile Voltage Positioning The Intel Mobile Voltage Positioning specification for the Intel IMVP 6 Core Duo Processor It is a DC DC converter module that supplies the required voltage and current to a single processor 10 Same as 1 0 Input Output IOH 1 0 Hub IOL IPMI Over LAN IP Internet Protocol G 2 AT8020 www kontron com Intelligent Platform Management IPMB Intelligent Platform Management Bus 0 Intelligent Platform Management Bus Channel 0 the logical aggregation of IPMB A and IPMB B IPMB A Intelligent Platform Management Bus A IPMB B Intelligent Platform Management Bus B IPMB L Intelligent Platform Management Bus Local IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface IPMIFWU Intelligent Platform Management Interface FirmWare Update IPv6 Internet Protocol version 6 IRQ Interrupt ReQuest JTAG Joint Test Action Group KHz KiloHertz LAN Local Area Network LED Light Emitting Diode LFM Low Frequency Mode The lowest operating speed for the processor LPC Low Pin Count port MAC Media Access Controller address of a computer networking device MB MegaByte MCH Memory Controller Hub MHz MegaHertz MMC Module Management Controller MMCs are linked to the IPMC NC Not Connected 005 Out Of Service
115. nel Descriptor Coh 02h N A N A N A 00315Ah gt PICMG Record ID 19h gt Point To Point Connectivity Record 00h 03h gt On Carrier device Device 3 SAS Controller 02h FFFFEOh OFh 1Fh 1Fh 1Fh 00h FFFFE1h 33 AT8020 www kontron com Board Features Reserved Bits 23 20 Lane 3 Port Number Bits 19 15 Lane 2 Port Number Bits 14 10 Lane 1 Port Number Bits 9 5 Lane 0 Port Number Bits 4 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 AMC Link Descriptor Reserved Bits 39 34 AMC Asymmetric Match Bits 33 32 Link Grouping ID Bits 31 24 AMC Link Type Extension Bits 23 20 AMC Link Type Bits 19 12 AMC Link Designator Bits 11 0 OFh 1Fh 1Fh 1Fh 01 00207106 03Fh 00b gt Exact match 00h gt Single Channel link 02h gt Serially Attached SCSI SATA 007h gt AMC 3 Storage 0106h
116. nit Local APIC Set up boot strap processor Information C2 Set up boot strap processor for POST C5 Enumerate and set up application processors C6 Re enable cache for boot strap processor 7 Early CPU Init Exit 0A Initializes the 8042 compatible Key Board Controller 0B Detects the presence of PS 2 mouse oc Detects the presence of Keyboard in KBC port Testing and initialization of different Input Devices Also update the Kernel Variables OE Traps the INTO9h vector so that the POST INTO9h handler gets control for IRQ1 Uncompress all available language BIOS logo and Silent logo modules 13 Early POST initialization of chipset registers 24 Uncompress and initialize any platform specific BIOS modules 30 Initialize System Management Interrupt 2 Initializes different devices through DIM See DIM Code Checkpoints section of document for more information 2C Initializes different devices Detects and initializes the video adapter installed in the system that have optional ROMs 2E Initializes all the output devices 3 Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Activate ADM module 33 Initializes the silent boot module Set the window for displaying text information 37 Displaying sign on message CPU information setup key message and OEM specific information 38 Initializes different devices through DIM See DIM Cod
117. nt 68 deg C Upper Non Critical event 62 deg C Upper Critical event 85 deg C Upper Non Critical event 80 deg C Upper Critical event 80 deg C Upper Non Critical event 75 deg C Upper Critical event 90 deg C Upper Non Critical event 85 deg C Upper Critical event 90 deg C Upper Non Critical event 85 deg C Upper Critical event 80 deg C Upper Non Critical event 75 deg C Current power status Power status event that occured since the last power on or reset CPU 0 Core Voltage Upper Critical event 1 377V Upper Non Critical event 0 783 CPU 1 Core Voltage Upper Critical event 1 377V Upper Non Critical event 0 783 www kontron com 18 AT8020 Board Features Voltage on 48v board input power supply Upper Critical event 75V Lower Critical Event 37 8V Hysteresis 1 25V 22 23 24 25 26 21 28 29 30 Bill 32 33 Vcc 48V Vcc 12V Vcc 5V Vcc 5V SUS Vcc 3 3V Vcc 3 3V SUS Vcc 2 5V Vcc Ref 2 5V Vcc 2 5V SUS Vcc 1 8V Vcc 1 5V Vcc 1 5V SUS Voltage on 12v board power supply Upper Critical event 12 60v 5 Lower Critical Event 11 40v 5 Hysteresis 0 180v 1 5 Voltage on 5v board power supply Upper Critical event 5 25v 5 Lower Critical Event 4 75v 5 Hysteresis 0 075v 1 5 Voltage on 5v suspend management board power supply Upper Critical event 5 25v 5 Lower Critical Event 4 75v 5 Hystere
118. o FRU Device Commands M M M Get FRU Inventory Area Info 28 1 Storage 10h M M M Yes Read FRU Data 28 2 Storage 11h M M M Yes Write FRU Data 28 3 Storage 12h M M M Yes SDR Device Commands M 0 Get SDR Repository Info 27 9 Storage 20h M M M No Tum er 27 10 Storage 21h 0 0 0 No Reserve SDR Repository 27 11 Storage 22h M M M No Get SDR 27 12 Storage 23h M3 M3 M3 No Add SDR 27 13 Storage 24h 3 16 0 M 5 No Partial Add SDR 27 14 Storage 25h 3 16 0 M 5 No Delete SDR 27 15 Storage 26h 03 03 03 Clear SDR Repository 27 16 Storage 27h M3 M36 0 3 5 Get SDR Repository Time 2747 Storage 28h 0 M 0 M 0 M No Set SDR Repository Time 27 18 Storage 29h 0 M3 0 M3 0 M3 No 27 19 Storage 2Ah 0 0 0 No Repository Update Storage 281 3 3 3 Initialization Agent 27 21 Storage 2Ch 03 03 03 SEL Device Commands 05 Get SEL Info 25 2 Storage 40h M Yes Get SEL Allocation Info 25 3 Storage 41h 0 0 0 No 40 AT8020 www kontron com Board Features IPMISpec IPMIBMC Shelf Man IPM Con Kontron section require require troller re support quirement AT8020 Reserve SEL 25 4 Storage 42h 03 03 03 Get SEL Entry 25 5 Storage 43h M M M Yes Add SEL Entry 25 6 Storage 44h M M M Yes Partial Add SEL Entry 25 7 Storage 45h 3 M M Yes Delete SEL Entry 25 8 Storage 46h 0 0 0 No Clear SEL 25 9 Storage 47h M M M Yes Get SEL Time 25 10 Storage 48h M M M Yes Set SEL Time 25 11 Storage 49h
119. o support single or dual channel DDR2 400 memory up to 16 GB The memory subsystem interface to the MCH is dual channel supporting two registered DIMMs per channel for total system bandwidth of up to 6 4 GB s PCI Express For demanding 1 0 and networking applications PCI Express interfaces attach a variety of 1 0 components and adapters directly to the Intel E7520 MCH at throughput speeds of up to 10 GB s on each x4 interface allowing 1 0 to keep pace with the rest of the platform The has three x8 PCI Express interfaces which can each be bifurcated into two x4 interfaces for additional configuration flexibility A RUE Intel 6300ESB 1 0 Controller Hub Available as the 1 0 controller hub for legacy 1 0 support the Intel 6300ESB 1 0 Controller Hub ICH attaches directly to the MCH through the Intel Hub Interface 1 5 connection Four Hi Speed USB 2 0 ports allow easy 1 0 connection while offering improved bandwidth compared to USB 1 1 devices The Intel 6300ESB ICH incorporates the functionality of two 16550 compatible serial ports and of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts 2 3 USB 2 0 Interfaces USB features include apability to daisy chain as many as 127 devices per interface Fastbi directional Isochronous asynchronous interface 480 Mb stransfer rate Standardization of peripheral interfaces into a single format Retro compatible with USB 1 1 devi
120. ode integrity and trigger an automatic rollback Initiation of a Host CPU reboot on redundant BIOS image base on BIOS IPMC handshake result Fast interrupt driven SMS host interface compliant to IPMI KCS v1 5 rev 1 1 Serial Over LAN SOL redirection of the Host CPU serial controller traffic to enable asynchronous serial based 05 and 05 communication via standard RMCP LAN application through the Management Controller Standard Management Controller message bridging to IPMB L Management Controller support standard PCI Hot Plug for PCI Express Management Controller can initiate standard graceful OS shutdown via ACPI support Supports system management interface IPMI V1 5 compliant controller Watchdog for BIOS execution and OS loading through and FPGA watchdogs Hardware system monitor voltages temperature CPU temperature monitor alarm board temperature sensor power failure through IPMC Red Hat Enterprise Linux V 4 and V 5 200W maximum including AMC modules Additional 25W maximum for RTM see note on page 3 www kontron com 2 AT8020 Product Description Environmental Temperature Environmental Humidity Environmental Altitude Environmental Shock Environmental Vibration Random Vibrations Reliability Safety EMC Warranty Operating 0 55 C 32 131 F with 30CFM airflow Storage and Transit 40 to 70 C 40 to 158 F
121. ommand Channel Number 02 Proper value below 16 Valid or Invalid display Channel Status only N A display only 80 AT8020 WWW kontron com Software Setup 2 1 7 2 LAN Parameter Selector 06 01 Channel Number 02 Valid or Invalid display Channel Status only Subnet Mask XXX XXX XXX XXX Current Subnet Mask XXX XXX XXX XXX 5 1 7 0 Subnet Mask Configuration sub menu N A Enter Channel Number for SET LAN Config Command Proper value below 16 N A Enter Subnet Mask in decimal in the form of XXX XXX XXX XXX XXX less than 256 and in decimal only N A Gateway Address Configuration sub menu LAN Parameter Selector 12 01 02 Valid or Invalid display only Channel Number Channel Status Gateway Address Current Gateway XXX XXX XXX XXX Address S Eu N A Enter Channel Number for SET LAN Config Command Proper value below 16 N A Enter Gateway IP Address in decimal in the form of XXX less than 256 and in decimal only N A Watchdog Timer sub menu 0 60 120 150 300 600 No Action Hard Reset Power Down Power Cycle 0 60 120 150 300 600 No Action Hard Reset Power Down Power Cycle BIOS POST Timeout BIOS POST Action OS Load Timeout OS Load Action Select the BIOS POST IPMI HW watchdog timeout value Select which action to
122. onnected in the front panel RJ 45 connector When assigned as Serial Port A it is 100 compatible with the IBM AT serial port in RS 232 mode 8 AT8020 WWW kontron com Board Features Table 2 3 Serial Port Pinout J14 RTS DTR Dat GND DCD GND RX DSR CTS 00 NOW W ro Note A Standard product uses a RJ 45 8 pins connector RI ring indicator and DCD data carrier detect signals are not available The pinout is a custom one it is not the same as RS 232D TIA EIA 561 Signal Path The Serial Port A signals are always available in front access through 214 or through the IPMC ip 05 Settings 49194 is no BIOS settings but Serial Port is fixed to the following address 3F8h IRQ 4 2 5 2 Serial Port 2 Serial Port 2 is only available on the RTM Serial port signals are connected to the RTM through J7 101 BIOS Settings 000 MET There is no BIOS settings but Serial Port B is fixed to the following address 2F8h IRQ 3 2 6 Real Time Clock amp NVRAM The AT8020 is a battery less board The real time clock and non volatile RAM integrated in the 6300ESB ICH are powered by the main supply when available or by a double layer SuperCap when the main power is absent The SuperCap will keep the real time clock running for a minimum of 2 hours Although itis possible to save the CMOS setup in NVRAM or CMOS RAM the default configuration saves the setup in flash So when the AT802
123. oot Utilities are Menu POP UP Boot Menu POP UP is a boot screen that displays a selection of boot devices from which you can boot your operating system 5 2 1 Pressing Deb or F4 from a Console Redirection terminal Pressing lt Del gt or F4 from a Console Redirection terminal during POST enters Setup 5 2 2 Pressing lt F11 gt or F3 from a Console Redirection terminal Pressing lt F11 gt or F3 from a Console Redirection terminal displays the Boot Menu POP UP with these options 1 Loadthe operating system from a boot device of your choice 2 Exitthe Boot Menu POP UP with lt 5 gt and load the operating system from the boot devices in the order specified in Setup 5 2 3 BOOT Menu POP UP The BOOT Menu POP UP expands your boot options by letting you choose your boot device which could be a hard disk floppy disk CDROM Flash Disk SCSI or LAN You can select your boot device in Setup or you can choose a different device each time you boot during POST by selecting your boot device in the Boot device lt F11 gt or F3 from a Console Redirection terminal 5 3 Console Redirection VT100 Mode The VT100 operating mode allows remote setup of the board This configuration requires a remote terminal that must be connected to the board through a serial communication link 5 3 1 Requirements The terminal should emulate a VT100 or an ANSI terminal Terminal emulation programs such as TelixO Hy
124. or Also refers to the small amount of battery or capacitor powered CMOS memory to hold the date time and system setup parameters CPLD Complex Programmable Logic Device CP TA Communications Platforms Trade Association CPU Central Processing Unit This sometimes refers to a whole blade not just a processor component G 1 AT8020 www kontron com CTS Clear To Send DDR3 DDR3 SDRAM or Double Data Rate three 3 Synchronous Dynamic Random Access Memory DHCP Dynamic Host Configuration Protocol DIMM Dual In line Memory Module DMA Direct Memory Access DMI Desktop Management Interface DTC Data Transfer Controller DTR Data Terminal Ready DTS Digital Thermal Sensor in IA32 processors DVD Digital Video Disk ECC Error Checking and Correction EMI ElectroMagnetic Interference ETH Same as Ethernet FC Fibre Channel FCC Federal Communications Commission FI Fabric Interface Backplane connectivity defined by the ATCA FIFO First In First Out FPGA Field Programmable Gate Array FRU Field Replaceable Unit Any entity that can be replaced by a user in the field Not all FRUs are hot swappable FWH FirmWare Hub Boot flash connected to the LPC bus containing BIOS FW Gb Gigabit GB Same as GByte GigaByte GByte Same as GB GigaByte GbE Gigabit Ethernet GHz GigaHertz GND GrouND HDD Hard Disc Drive HPM PICMG Hardware Platform Management specification family HPM 1 Hardware Platform Management IPM Controller Firmware Upgrade Specificatio
125. orm the following functions Reset Detect and Disable function 0 Static Device Initialization function 1 Boot Output Device Initialization function 2 Function 0 disables all device nodes PCI devices and PnP ISA cards It also 2 assigns PCI bus numbers Function 1 initializes all static devices that include manual configured onboard peripherals memory and 1 0 decode windows in PCI PCI bridges and noncompliant PCI devices Static resources are also reserved Function 2 searches for and initializes any PnP PCI or AGP video devices Initialize different buses and perform the following functions Boot Input Device Initialization function 3 IPL Device Initialization function 4 General Device Initialization function 5 Function 3 searches for and configures PCI input devices and d detects if system has standard keyboard controller Function 4 searches for and configures all PnP and PCI boot devices Function 5 CONFIGURES all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices DD DE OEM PCI init debug POST code during DIMM init DEh during BUS number assignment and DDh during ressource allocation Hight byte is the BUS number While control 16 in the different functions additional checkpoints are output to port 80h as word value to identify the routines under execution The low byte value indicates the main POST Code Checkpoint The high byte is divided into two nibb
126. perTerminal Windows minicom Linux or ProcommO Windows can also be used 83 AT8020 WWW kontron com Software Setup 5 3 2 Running Without a Terminal The board can boot up without a screen or terminal attached If the speed is set to Auto and no terminal is connected the speed is set to 115 200 bauds 5 3 3 Up Down Right Left Home End F1 F2 F3 F4 Full Setup DE 5 VT100 Terminal Note Partial Setup esl COM Connector 2 a 2 Refer to Serial Port 1 35 section for connector location and pinout ANSI and VT100 Keystroke Mapping lt ESC gt A lt ESC gt B lt ESC gt C lt ESC gt D lt ESC gt H lt ESC gt K lt ESC gt OP lt ESC gt 0Q lt ESC gt OR lt 5 gt 0 www kontron com 84 AT8020 Software Setup 5 3 4 VT UTF8 Keystroke Mapping The following escape sequences are defined in the Conventions for Keys Not in VT100 Terminal Definition and ASCII Character Set section of Standardizing Out of Band Management Console Output and Terminal Emulation VT UTF8 and VT100 available for download at microsoft com F1 Key lt ESC gt 1 F2 Key lt ESC gt 2 F3 Key lt 5 gt 3 F4 Key lt 5 gt 4 5 lt 5 gt 5 lt 5 gt 6 7 lt 5 gt 7 F8 Key lt 5 gt 8 9 lt 5 gt 9 F10 Key lt 5 gt 0 11 lt ESC gt F12 Key lt ESC gt
127. pped with the following items One AT8020 board One CD ROM containing documentations and drivers Cables that have been ordered AMCs gap fillers If any item is missing or damaged contact the supplier 1 3 Board Specifications Table 1 1 Board Specifications One Two Dual Core Intel Xeon LV Processors 2 0GHz Passive heatsinks 32 L1 instruction and 32 L1 data cache dedicated for each core 2 12 cache on each processor chip shared both cores North Bridge Intel E7520 South Bridge Intel 6300 5 CPUs Front Side bus at 667 MHz 64 bit data 36 bit address Bus Interface Memory bus at 400 MHz 144 bit data 2 channel Six onboard PCI Express x4 2 Mid size AdvancedMC bays 1 Type 4 compliant x4 PCI Express 2 compliant 2 X1000Base BX Ports AMC 3 compliant dual port SAS SATA Processors Cache Memory Chipset Expansion Slot 1 AT8020 WWW kontron com Product Description System Memory Flash Memory Storage Connectors Board Specifications BIOS Features IPMI Features Supervisory 05 Compatibility Power Requirements Up to 16 4x240 pin latching DDR 2 400MHz SDRAM 2 3200 ECC support support S4EC D4ED when using x4 SDRAM devices 2 DDR 2 channels Two redundant 1MB BIOS Field software upgradeable Roll back functionality controlled 4 ports SAS available through each Adv
128. r 00h 11 These commands are required by the IPM Controllers that control Shelf fans 12 IPM Controllers are only required to support a subset of this command see Section 3 2 3 Addressing for details 13 These commands are only mandatory for Boards that implement E Keying governed interfaces 14 These commands are only mandatory for Boards that implement E Keying governed shared bus interfaces namely the Synchronization Clocks and Metallic Test Bus 15 Mandatory group for Shelf Managers that act as either an active or backup Shelf Manager 16 Mandatory for at least the System Manager Interface on the Shelf Manager 17 Since non intelligent devices are not allowed to attach to either IPMB A or IPMB B this command is optional for those two buses 18 For the Shelf Manager these WDT commands are mandatory only if there is a Payload function associated with the ShMC 19 Mandatory for IPM Controllers that incorporate an 0 Hub 43 AT8020 Board Features 2 15 11 OEM IPMI Commands This section documents the OEM style IPMI commands implemented and supported on the AT8020 Table 2 18 OEM IPMI Commands Reset BIOS Flash Type 3Ah 01h SetBoardDeviceChannelPortSelection 3Ah 10h GetBoardDeviceChannelPortSelection 3Ah 11h GetBoardDevicePossibleSelection 3Ah 13h Set Control State 3Eh 20h Get Control State 3Eh 21h 2 15 11 1 Reset BIOS Flash Type This command resets the processor and changes the BIOS bank select signal
129. r other ATCA node boards 5 Possibly some rear transition modules Consult Kontron s web site for available chassis switches and node boards Consult your system s manual for more details Figure 4 1 ATCA Chassis 4 1 1 Backplane The AT8020 is compliant to ATCA 3 0R1 0 spec It can be used in a Dual Star or a Full Mesh configuration 59 AT8020 www kontron com Building System 4 1 2 X Rear Panel I O This feature is intended to extend the 1 0 capabilities of the AT8020 to the rear of the enclosure using a RTM 1 0 1 0 module gathers all the 1 0 signals of the CPU board and makes them easily accessible through standard headers and connectors located at the rear of enclosure WARNING Always use Kontron s with your Kontron s board if not permanent damage A could occur 4 1 3 External Storage Devices The AT8020 supports external storage device through the SAS connector available on the RTM 4 1 4 Power Supply The AT8020 expects two 48V feeds as per PICMG3 0R1 0 The AT8020 is fully working over a range of 38V to 72 as required by the specification Note lt 10W Management power can be lightly exceeded when the power feed is between 60V and 72V 4 1 5 Mechanical Keying and Alignment Although ATCA systems are managed by electronic keying E Keying mechanical features are also defined for keying and alignment of the front board backplane and RTM Differen
130. r recertify systems or components that have been reconfigured by customers xiii AT8020 WWW kontron com Limited Warranty Kontron grants the original purchaser of Kontron s products a TWO YEAR LIMITED HARDWARE WARRANTY as described in the following However no other warranties that may be granted or implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron Kontron warrants their own products excluding software to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase This warranty 15 nottransferable nor extendible to cover any other users or long term storage of the product does not cover products which have been modified altered or repaired by any other party than Kontron or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence improper use incorrect handling servicing or maintenance or which has been damaged as a result of excessive current voltage or temperature or which has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty If the customer s eligibility for warranty has not been voided in the event of any claim he may return the product at the earliest possible convenience to the original place of purchase together with a copy of the orig
131. remote LAN boot via BIis not available to boot the system Enabled Initializes fabric interface PXE expansion ROM Disabled Fabric interface PXE expansion ROM not used If disabled remote LAN boot via FI 15 not available to boot the system Enabled Initializes mezzanine PXE expansion ROM Disabled Mezzanine PXE expansion ROM not used If disabled remote LAN boot is not available to boot the system Enabled Initializes mezzanine PXE expansion ROM Disabled Mezzanine interface PXE expansion ROM not used If disabled remote LAN boot is not available to boot the system Enabled Initializes FC SAS expansion ROM Disabled FC SAS expansion ROM not used If disabled any FC SAS devices attached to the system are not available to boot the system Enabled Initializes AMC slot 1 expansion ROM Disabled AMC slot 1 expansion ROM not used Enabled Initializes AMC slot 2 expansion ROM Disabled AMC slot 2 expansion ROM not used 75 AT8020 ron com Software Setup 5 1 4 9 PCI Express Configuration sub menu Hot Plug Support AMC Enabled Enabled Set PCI Express Hot Plug capability B1 Disabled Disabled Hot Plug is not available on this port Hot Plug Support AMC Enabled Enabled Set PCI Express Hot Plug capability B2 Disabled Disabled Hot Plug is not available on this port SSC Actual Clock Mode State Non SSC Display Only Select thePCI Express Clock Mode SSC Warning To change the PCI Expre
132. rify that flat mode is enabled Test base 512KB memory Adjust policies and cache first 8MB Set stack Bootblock code is copied from ROM to lower system memory and control is given to it BIOS now executes out of RAM Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced Main BIOS checksum is tested If BIOS recovery is necessary control flows to checkpoint EO See Bootblock Recovery Code Checkpoints section of document for more information Restore CPUID value back into register The Bootblock Runtime interface module is moved to system memory and control 15 given to it Determine whether to execute serial flash The Runtime module is uncompressed into memory CPUID information is stored in memory Store the Uncompressed pointer for future use in PMM Copying Main BIOS into memory Leaves all RAM below 1MB Read Write including E000 and F000 shadow areas but closing SMRAM Restore CPUID value back into register Give control to BIOS POST ExecutePOSTKernel See POST Code Checkpoints section of document for more information OEM memory detection configuration error This range is reserved for chipset vendors amp system manufacturers The error associated with this value may be different from one platform to the next Refer to memory initialization ERROR CODE D 5 D 1 AT8020 ron com 0 2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the B
133. rk needed before booting to OS Takes care of runtime image preparation for different BIOS modules Fill the free area in A2 F000h segment with OFFh Initializes the Microsoft IRQ Routing Table Prepares the runtime language module Disables the system configuration display if needed A4 Initialize runtime language module Displays the system configuration screen if enabled Initialize the CPU s before boot which oy includes the programming of the MTRR s A8 Prepare CPU for OS boot including final MTRR values 9 Wait for user input at config display if needed AA Uninstall POST INT1Ch vector and INTO9h vector Deinitializes the ADM module AB Prepare BBS for Int 19 boot AC End of POST initialization of chipset registers B1 Save system context for ACPI 00 Passes control to OS Loader typically INT19h 61 70 OEM POST Error This range is reserved for chipset vendors amp system manufacturers The error associated with this value may be different from one platform to the next DD DE OEM PCI init debug POST code during DIMM init See DIM Code Checkpoints section of document for more information D 4 AT8020 www kontron com 0 4 DIM Code Checkpoints The Device Initialization Manager DIM gets control at various times during BIOS POST to initialize different system busses The following table describes the main checkpoints where the DIM module is accessed Checkpoint Description Initialize different buses and perf
134. ronics service personnel should access the interior of the computer The power supplies produce high voltages and energy hazards which can cause bodily harm Useextreme caution when installing or removing components Refer to the installation instructions in this user s guide for precautions and procedures If you have any questions please contact Kontron Technical Support WARNING A High voltages are present inside the chassis when the unit s power cord is plugged A into an electrical outlet Turn off system power turn off the power supply and then disconnect the power cord from its source before removing the chassis cover Turning off the system power switch does not remove power to components viii AT8020 www kontron com Safety Instructions Preventing Electrostatic Discharge Static electricity can harm system boards Perform service at an ESD workstation and follow proper ESD procedure to reduce the risk of damage to components Kontron strongly encourages you to follow proper ESD procedure which can include wrist straps and smocks when servicing equipment Take the following steps to prevent damage from electrostatic discharge ESD When unpacking a static sensitive component from its shipping carton do not remove the component s antistatic packing material until you are ready to install the component in a computer Just before unwrapping the antistatic packaging be sure you are at an ESD workstation or grounde
135. rs IPMB isolators are used to switch and isolate the backplane system IPMB bus from the faulted board Where possible the IPMC will isolate the failure line and will use the other bus to re establish system management communication to report the fault The onboard DC voltages currents and temperature are monitored by the IPMC microcontroller device The IPMC will log an event into the ShMc SEL if any thresholds are exceeded To increase the reliability of the AT8020 management subsystem an external watchdog supervisor only for the IPMC 15 implemented The IPMC must strobe the external watchdog at two second intervals to ensure continuity of operation of the board s management subsystem If the IPMC ceases to strobe the watchdog 16 AT8020 www kontron com Board Features supervisor the watchdog isolates the IPMC from the IPMBs and resets the IPMC The watchdog supervisor does not reset the payload power the restart of the IPMC will not affect the payload and will restore the previous Hot Swap state and power level negotiated with the ShMc The watchdog timeout expires after six seconds if strobes are not generated The external watchdog supervisor is not configurable and must not be confused with the IPMI v1 5 watchdog timer commands This external watchdog of the IPMC is implemented in a second microcontroller This microcontroller is responsible to monitor the IPMC and to manage IPMC fail safe firmware upgrade process The name o
136. s undefined either 0 or 1 may be returned Legend U Unchanged stay unchanged after reset X Not Defined bit not used on this board NU Not Used B 2 Sossaman Addressing Space The following ranges will be used on Kontron Canada ATCA boards e 1 00080 00811 for 16 bit postcodes e J 00A00 0A1Fh to reserve permanently 32 locations in 1 0 space for on board resources e 1 00378 037 hidden legacy LPT port for Xilinx JTAG programmer Not all those 1 0 locations are used but the LPC bridge will answer the cycle in zero wait state B 1 AT8020 WWW kontron com B 2 1 Summary of On board Registers Those registers are physically implemented in the AT8020 FPGA 80 81h Postcodes Version 01 Debug LED and Mfg flag 2 Firmware Update Manager FWUM related A03h BIOS to IPMC Mailbox 04 Development features for in house use only 05 LED configuration test 06 Jumpers version A07h BOM version component straps 08 T2604 Flash control 09 PLD Version AOAh Reset History AOBh Mezzanine presence and identification A10 A1Fh Reserved for future ATCA boards 378 37Ah Legacy LPT port for FPGA upgrade exclusively 600 7FFh Reserved for customer extension in case of hardware conflict possible alternate addresses are e LPT1 378 37Ah e LPT2 278 27Ah e LPT3 3BC 3BFh B 2 2 80 81h Postcodes Address Acion Ds Ds D
137. scription Tables Different ACPI version has some addition Enabled ACPI APIC table support Disabled ACPI APIC table not supported Enabled Headless operation mode through ACPI supported Disabled Headless operation mode through ACPI not supported Event Log Configuration sub menu Space Available Shows if space is available in the Event Log for new log Event Log capacity No Sreca events Enabled Enabled Event Log is used Event Logging Disabled Disabled Event Log is not used If this option is disabled no SEL events are available from this blade View Event Log Enter View all unread events in the Event Log Mark Events as read Enter Mark all unread events as read in the Event Log Clear all Event Logs Enter Discard all events in the Event Log 2 ECC x4 Chip Fail ECC used in dual channel mode 72 bit ECC Data Integrity used in single channel mode Non ECC Use only for testing purposes Enabled Enabled ECC event logging enabled ECE Event Logging Disabled Disabled ECC event logging disabled Correctable Correctable ECC for testing purposes ECC Error Reportin Uncorrectable Uncorrectable ECC errors reported p 9 Both Both ECC errors for testing purposes Disabled Disabled ECC errors not reported Hub Interface Event Enabled Enabled Hub interface event logging enabled Logging Disabled Disabled Hub interface event logging disabled System Bus Event Enabled Enabled System bus event logging en
138. sis 0 075v 1 5 Voltage on 3 3v board power supply Upper Critical event 3 47v 5 Lower Critical Event 3 13v 5 Hysteresis 0 050v 1 5 Voltage on 3 3v suspend management board power supply Upper Critical event 3 47v 5 Lower Critical Event 3 13v 5 Hysteresis 0 050v 1 5 Voltage on 2 5v board power supply Upper Critical event 2 63 5 Lower Critical Event 2 37v 5 Hysteresis 0 038 1 5 Voltage on 2 5v board power supply Upper Critical event 2 63v 5 Lower Critical Event 2 37 5 Hysteresis 0 038v 1 5 Voltage on 2 5v suspend management board power supply Upper Critical event 2 63 5 Lower Critical Event 2 37v 5 Hysteresis 0 038 1 5 Voltage on 1 8v suspend management board power supply Upper Critical event 1 89v 5 Lower Critical Event 1 71 5 Hysteresis 0 027v 1 5 Voltage on 1 5v board power supply Upper Critical event 1 58v 10 Lower Critical Event 1 42v 10 Hysteresis 0 025v 1 5 Voltage on 1 5v suspend management board power supply Upper Critical event 1 58v 10 Lower Critical Event 1 42v 10 Hysteresis 0 025v 1 5 www kontron com 19 AT8020 Board Features 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Vcc 1 2V SUS Vcc 1 1V SUS Vcc VIT DDR 48V A Pres Fuse 48V B Pres Fuse FRUO Power FRU1 Power FRU2 Power FRU3 Pow
139. ss Clock Mode you need to Mode etting Non SSC re insert the blade into the shelf AMC ekeying use this setting to allow SSC or non SSC PCI Express AMC 5 1 4 10 USB Configuration sub menu USB Devices Enabled N A FullSpeed FullSpeed 12 Mbps USB 2 0 Controller Mode HiSpeed HiSpeed 480 Mbps Enabled Enabled EHCI hand off support enabled BIOS er eee Disabled Disabled EHCI hand off support disabled USB Mass Storage Device Configuration D ea precenti USE N A Configure the USB Mass Storage Class Devices Mass Storage detected 5 1 4 11 USB Mass Storage Device Configuration sub menu 10 Sec USB Mass Storage Reset 20 Sec N A Delay 30 Sec 40 Sec Device 1 6 N A N A Auto If Auto USB devices less than 530MB will emulated as Forced FDD Floppy and remaining as hard drive Forced FDD option can For each device Hard Disk be used to force a HDD formatted drive to boot as FDD CDROM WWW kontron com 76 AT8020 Software Setup 5 1 4 12 Memory Remapping Memory Mirroring Sparing DMA Controller DDR2 Refresh Spread Spetrum Clocking Mode Advanced Chipset Control sub menu Enabled Allows remapping of overlapped PCI memory above eM the total physical memory Requires PAE support in OS gig Disabled Memory remapping not allowed Mirroring Mirroring Memory mirroring feature enabled if supported Sparin Sparing Memory sparing feature enabled if supported by y
140. t angle positions are defined in the PICMG 3 0 specification and each rotation corresponds to a unique value ATCA backplanes and front boards A1 K1 Alignment Keying values are 1 1 for a zero degree rotation These values are mandatory for all ATCA boards However the keying is defined by the front board manufacturer Currently Kontron also uses the 2 2 values of 1 1 in order to match the front CPU board to the RTM If unwanted mechanical matching ever happens in the field E Keying would prevent connection of such incompatible components through the supervision of the Intelligent Platform Management Controller IPMC 60 AT8020 www kontron com Software Setup 5 Software Setup 5 1 AMI BIOS Setup Program All relevant information for operating the board and connected peripherals are stored in the CMOS memory backed up by supercap or in the main BIOS flash 5 1 1 Accessing the BIOS Setup Utility The system BIOS Basic Input Output System provides an interface between the operating system and the hardware of the AT8020 It uses the AMISetup program a setup utility in flash memory that is accessed by pressing the DELETE key at the appropriate time during system boot This utility is used to set configuration data in CMOS RAM To run the AMI Setup program incorporated in the ROM BIOS Turn on or reboot the system When you getthe following messages hit DELETE key or F4 on Remote Keyboard to
141. t as a buffer between the AMC ports 0 1 and the fabric interface to properly configure the 1 0 depending on the daughter card that is installed 2 10 AMC Mezzanines Two AMC sites are available Characteristics of each AMCare as follow Type B Support mid size single width mechanical format e PCI Express X4 with reference clock AMC FCLKA Fully compliant PCI hot swap support PortO and 1 connected to crosspoint switches LAN Provision for telecom clocks on TCLKA B C Both slots a SAS link to the daughter card and an other SAS link to the RTM connector Compliantto AMC 1 AMC 2 and AMC 3 compatible to AMC O R2 0 The electric power budget for one AMC is limited to 42W 60W total for both AMCs and it is controlled by the IPMI As per AMC 1 R2 0 the carrier board AT8020 is required to provide PCI E 100MHz reference clock to the AMC on FCLKA However modules are not required to use it Kontron recommends using AMC Express modules that use the reference clock on FCLKA If the module makes its own reference clock then the spread spectrum of the AT8020 clock synthetizer needs to be disabled in the BIOS setup otherwise the behavior of the PCI Express link will be erratic at best Note electromagnetic compatibility tests have been done with spread spectrum Disabling the spread spectrum can complicate EMC The telco clock signal allows the AT8020 to provide clock to the AMC on TCLKA For possible
142. take when the BIOS POST IPMI HW watchdog expires Select the OS Load IPMI HW watchdog timeout value Setto 0 to disable watchdog Select which action to take when the 05 Load IPMI HW watchdog expires www kontron com 81 AT8020 Software Setup 5 1 7 3 System Information sub menu Board Product Name AT8020 N A Board Vendor Kontron N A Board Serial Number Varies N A Board Part Number Varies N A Chassis Slot 15 10 In Use Secondary Display Only IPMI Device FW Info N A N A 5 1 7 0 IPMI Device and FW Info sub menu IPMI Version 1 5 N A IPMI Device ID Varies N A IPMI Device Revision Varies N A IPMI Firmware Version Varies N A SDR Revision Varies Display Only 5 1 8 Exit Menu Exit system setup after saving the changes h E N A Save Granges and Exi F10 key can be used for this operation Exit system setup without saving any changes ESC key can be used for this operation Discard Changes and Load Optimal Default values for all the setup questions L i Def N A F9 key be used for this operation Discards changes done so far to any of the setup questions Di h N A feat ues F7 key can be used for this operation Exit amp Update BIOS N A Force BIOS recovery mode on next system reset 2 Swap BIOS FWH without saving changes 82 AT8020 WWW k on com Software Setup 5 2 Boot Utilities AMI B
143. th the POD 10 Connect FW RXD and FW TXD to RJ45 RS232 port 00 Connect B1 IPMC uart 1 to ICH UART1 B 2 8 A05h LEDs Configuration amp RTM Test ESTEE I Write Reset A05h RtmTest RtmTest RtmTest NU NU NU NU NU NU NU 0 NU NU NU NU NU NA NA The value written to this bit is transferred to the in the RTM Link The value received by the RTM can be read from location A20h when a production RTM is used T5702 The RTM also returns the bit through the RTM Link The value read from this register comes from the RTM Link Testing procedure e set bit RtmTest waitforthe round trip read bit RtmTest must be 1 clear bit RtmTest waitforthe round trip WWW kontron com B 5 AT8020 read bit RtmTest must 0 Note A This register may be redefined to add LED configuration information MagJack vs SerDes etc B 2 9 06 Jumpers and PCB version Address Action D7 D5 04 03 02 01 Address Action f D7 Read PROM 2 JMP1 JMPO PCB3 PCB2 PCB1 PCBO A06h Write NU NU NU NU NU NU NU NU Reset NU NU NU NU NU NU NU NU PCB 3 0 PCB Version JMP 2 0 Various jumpers JMP2 clear CMOS in flash for BIOS use JMP1 reserved for now JMPO reserved for now PROM Indicate which PROM is currently selected for the FPGA based on selection jumper 1 Jumper absent user PROM selected 0 Jumper present factory PROM selected
144. the supported IPMI commands within the AT8020 All these commands are compatible to IPMI v1 5 and PICMG 3 0 specifications Table 2 17 IPMI Commands Set IPMI Spec NetFn CMD IPMIBMC Shelf Man IPM Con Kontron section require require troller re support ment ment quirement AT8020 IPM Device Global Commands H Get Device ID 17 1 App 01 Yes Cold Reset 17 2 App 02h 0 0 0 Yes Warm Reset 17 3 App 03h 0 0 0 No Get Self Test Results 17 4 App 04h M M M Yes Manufacturing Test On 17 5 App 05h 0 0 0 No Set ACPI Power State 17 6 App 06h 0 0 0 Yes Get ACPI Power State 17 7 App 07h 0 0 0 Yes Get Device GUID 17 8 App 08h 0 0 0 No B d Devi cerpevice 17 9 App 018 34 34 Yes BMC Watchdog Timer 18 Commands Yes Reset Watchdog Timer 21 5 App 22h M M M Yes Set Watchdog Timer 21 6 App 24h M M M Yes Get Watchdog Timer 21 7 App 25h M M M Yes BMC Device and Messaging Commands i o Set BMC Global Enables 18 1 App 2Eh M 0 M 0 M Yes Get BMC Global Enables 18 2 App 2Fh M M 0 M Yes Clear Message Flags 18 3 App 30h M 0 M 0 M Yes Get Message Flags 18 4 App 31h M 0 M 0 M Yes E M h nable essage Channel 18 5 ADD 32h 0 0 0 Get Message 18 6 App 33h M 0 M9 0 gt 9 Yes Send Message 18 7 App 34h M M 0 5 Read Event Message Buffer 18 8 App 35h 0 0 0 Yes Get BT Interface 18 A 3 5 3 5 8 9 36 0 0 M Yes Master Write Read 18 10 App 52h 0 M 517
145. ting the SOL payload type as described in the section 2 16 7 The 2 channels are referred as channel 1 and channel 2 They can be accessed through those numbers when you use the IPMI commands related to channels Only one channel can be activated at a time The implementation supports up to 4 simultaneous sessions only one can enable SOL payload If a session is inactive for 1 minute it will be closed automatically The BIOS provides some basic functionality to see and configure the IPMI Over LAN Using the BIOS the following parameters can be seen configured IP address MAC address Subnet Mask Gateway address Active LAN channel Theses settings are available in the BIOS section LAN configuration The recommended IPMI Over Lan Serial Over LAN tools for Linux is IPMITool This utility is available from the following web site http ipmitool sourceforge net index html 35 AT8020 WWW kontron com Board Features 2 15 6 1 Authentication Integrity and Confidentiality The AT8020 support 2 types of authentication for RMCP session connections None and Straight Password For RMCP session connections the AT8020 support from Cipher ID 0 to Cipher Id 3 The following algorithms are supported e Authentication RAKP HMAC SHA1 Integrity None HMAC SHA1 96 e Confidentiality None AES CBC 128 When RMCP authentication or RMCP Cipher ID 015 used privilege level is limited to User 2
146. tion the blue LED shall turn ON as soon as the AMC is fully inserted It will turn OFF at the end of the hot swap sequence 3 5 4 Removing To remove an AMC 1 Pull out the handle to unlock the AMC 2 Waitforthe blue LED to turn on 3 Pull outthe AMC using the handle 3 5 5 Installing a RTM To install a RTM 1 Removethe filler panel of the slot 2 Ensurethe board is configured properly 3 Carefully align the PCB edges in the bottom and top card guide 4 Insertthe board in the system until it makes contact with the CPU board 5 Using both ejector handles engage the board in the CPU board connectors until both ejectors are locked 6 Fasten screws at the top and bottom of the faceplate 3 5 6 Removing RTM To remove a RTM 1 Unscrew the top and the bottom screw of the faceplate 2 Unlockthe lower handle latch 3 Wait until the blue LED is fully ON this mean that the hot swap sequence is ready for board removal 4 Use both ejectors to disengage the board from the CPU board 5 Pullthe board out of the chassis 58 AT8020 www kontron com Building System 4 Building System 4 1 Building an ATCA System The basic components needed to build an ATCA system include 1 Chassis which includes backplane power supply or power entry modules fans 2 Base interface switches and optional fabric interface switches 3 Shelf manager controllers ShMC 4 One or more AT8020 o
147. tness quality marketability or ability to fulfil any particular application or purpose As a result the products sold as 15 and the responsibility to ensure their suitability for any given task remains that of the purchaser In no event will Kontron be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even if Kontron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase Please remember that no Kontron employee dealer or agent is authorized to make any modification or addition to the above specified terms either verbally or in any other form written or electronically transmitted without the company s consent xiv AT8020 WWW kontron com Product Description 1 Product Description 1 1 Product Overview The Kontron AT8020 AdvancedTCA processor board features one or two Intel Dual Core Xeon processors and support for two AdvancedMC modules The result is an open modular processing platform that will increase the number of deployments of AdvancedTCA solutions at the heart of every compute intensive mobile IMS network element from the transcoding of live multimedia mobile content on a Multimedia Resource Function Processor MRFP to concurrent processing of subscriber data on Home Subscriber Locator HLR systems 1 2 What s Included This board is shi
148. ughput where both busses are actively used for communication at any point A request might be received over IPMB Bus A and the response is sent over IPMB Bus B All requests that time out are retried on the redundant IPMB bus In the events of any link state changes the events are written to the AT8020 SEL The IPMC monitors the bus for any link failure and isolates itself from the bus if it detects that it is causing errors on the bus Events are sent to notify the failure of a bus or conversely the recovery of a bus 2 15 4 2 FRU Hot Swap The hot swap event message conveys the previous and the current state of the FRU Also as the FRU state changes the IPMC determines the cause and that info is added to the event Refer to PICMG 3 0 specifications for further details about the hot swap state 2 15 4 3 OEM Sensor Types Table 2 7 Sensor Types Descriptions Including Associated Event Reading type code Sensor giving info about firmware state According to the Event Reading Type the 2 first bits will have assertion mask set Associated event reading type code 0 70 Firmware Info 1 0x71 OEM Firmware Info 2 0x75 OEM Firmware Info 2 On AMC carrier the IPMB L for IPMB Local is the link between the IPMC and the MMC The IPMB L doesn t require to support a failure detection sensor as opposed to the 0 which is connected between the ShMC and the IPMC However since the AM
149. ure Settings during System Boot Boot Device Priority N A Specifies the priority of the available boot sources Hard Disk Drives N A Lists available hard disk drives in priority order Removable Drives N A Lists available removable disk drives in priority order CD DVD Drives N A Lists available CD DVD drives in priority order USB Drives N A Lists available USB drives in priority order Network Drives N A Lists available network drives in priority order Other Drives N A Specifies the Lists available other drives in priority order 5 1 6 4 Boot Settings Configuration sub menu Enabled Allows skipping the memory tests during a cold Quick Boot Mode Enabled boot Disabled Disabled Allows the extended memory test to be executed during a cold boot Enabled Enabled Extended memory test is applicable when Quick Extended Memory Test Disabled Boot is disabled and a cold reset occurs 198236 Disabled Extended memory test is not performed in a reset 5 16 2 Boot Device Priority sub menu Specifies the boot sequence from the available devices 15 Boot Device Type Boot device A device enclosed in parenthesis has been disabled in the corresponding type menu Specifies the boot sequence from the available devices Boot Device Type Boot device A device enclosed in parenthesis has been disabled in the corresponding type menu nth 4 16 3 Hard Disk removable CD DVD USB Network and other drives sub menu Specifies the boot priority of
150. ution please consult your local technical support 2 15 Hardware Management 2 15 1 Hardware Management Overview The main processors communicate with the Intelligent Management Controller IPMC using the Keyboard Controller Style KCS system management interface BIOS uses SMM interface The base address of the LPC interface for SMS is OxCA2 and OxCA4 for SMM operation Besides that the BIOS is able to communicate with the IPMC for POST error logging purposes and fault resilient purposes The memory subsystem of the IPMC consists of an integrated flash memory to hold the IPMC operation code and integrated RAM for data The field replacement unit FRU inventory information is stored in the nonvolatile memory on an EEPROM connected via local 12C interface to the IPMC microcontroller It is possible to store up to 4 KBytes within the FRU inventory information Event generation over IPMB bus to reach the ShMc SEL ensures that post mortem logging information is available even if the main processor becomes disabled The IPMC also implements it s own SEL that can store up to 1023 events The IPMC provides six I2C bus connections Two are used as the redundant IPMB bus connections to the backplane is used for IPMB L bus with AMC modules is used for LAN connections for the IPMI over LAN support An other one is also used by the monitoring chip and the last one is for local EEPROM storage If an IPMB bus fault or IPMC failure occu
151. value back into register Give control to F000 ROM at F000 FFFOh POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre boot process The following table describes the type of checkpoints that may occur during the POST portion of the BIOS 03 04 05 06 Disable NMI Parity video for EGA and DMA controllers Initialize BIOS POST Runtime data area Also initialize BIOS modules on POST entry and GPNV area Initialized CMOS as mentioned in the Kernel Variable wCMOSFlags Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verify CMOS checksum manually by reading storage area If the CMOS checksum is bad update CMOS with power on default values and clear passwords Initialize status register A Initializes data variables that are based on CMOS setup questions Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware generally PIC and interrupt vector table Do R W test to CH 2 count reg Initialize 0 as system timer Install the POSTINT1Ch handler Enable IRQ 0 in PIC for system timer interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock WWW kontron com D 2 AT8020 Initializes the CPU The BAT test is being done Program the keyboard controller 08 command byte is being done after Auto detection of KB MS using AMI KB 5 co Early CPU Init Start Disable Cache I
152. vices are provided One that can only be programmed in factory and an other one that can be updated in the field The factory flash can be selected by inserting jumper JP1 pins 13 14 Field updates require a power cycle of the board The appropriate procedure to upgrade the FPGA will be provided with the update code when needed 15 AT8020 www kontron com Board Features 2 14 Telecom Clock Option This board provides an elaborate set of Telecom clocks also called Telco clocks which allows several configurations It can generate its own clock which can be routed to the backplane or to an AMC It can also receive the signal from the backplane and route it to an AMC and vice versa The circuit is made of Multipoint Low Voltage Differential Signaling MLVDS buffers a Complex Programmable Logic Device CPLD and a Digital Phase Locked Loop DPLL Tt could generate or receive clocks in the backplane as specified in the PICMG3 0 specification for a variety of SONET SDH standard frequencies ranging from 2 kHz to 19 44 MHz These clocks could be either driven or received on the following signals CLK1A CLK1B CLK2A CLK2B CLK3A CLK3B same goes for the telecom clocks interfaces provided by the 0 specification These clocks are defined as TCLKA TCLKB and TCLKC No clock can be used on TCLKD signal Interrupts could also be generated based on PICMG3 0 or 0 clock For a detailed sol
153. ytes Dual core CPU 2 MBytes a Fog 50V 2 5V controller L2 cache L2 cache moe mid 1 18 1 5V 12 for lt on die lt lt on die 1 11 1 05 amp RTM 33 1 1 Clock Generator CK409 VSC3108 Clock Generat 1 1 59325208 X Switch2 Thermal diode Thermal diode 1 STD config PCI Express Clock THERM SYSTEM BUS CLK THERM SYSTEMBUS JTAG 1 5 1 1121314151617 8 AGTL 667MHz EC SYSTEM BUS 5 5 2X DDR2 400 registered DIMMs E7520 gt bie LindenHurst DDR2 645400 PA 8 2X DDR2 400 registered DIMMs e x42mm g gt al 8 amp Express Management 24 CI BI ALIS 182551QM 5 N 2g 5 rax 5 lt 8 Front Plate Sake B Es 5 4 x4 4 x4 6300 5 54 B2 lower 5 a lt Hance Rapids T z BGA698 gt 95 16 gt lt 37 37 5 2GB Bo E 5 FLASH E 5 E 4 2 Sd 9g Bl upper TPM COMI R45 ai AMC 1 not installed Front Plate BoB 8 g gt RTM Link 5 214 Reset lt 2131415161 8 pm 1 wv wd PCLE PCLE LPC COMI 8 310

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