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POS-PHY Level 2 and 3 Compiler User Guide

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1. POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description Interface Signals 3 25 Tahle 3 12 POS PHY Level 2 Receive Interface Part 2 of 3 Signal rmod 2 Direction PHY to link Description The receive word modulo signal xmod indicates the size of the current word rmod is only used during the last word transfer of a packet when is asserted During a packet transfer every word must be complete except the last word which can be composed of 1 or 2 bytes xmod set high indicates a 1 byte word present on MSBs LSBs are discarded rmod set low indicates a 2 byte word The PHY layer device tri states rmod when renb is high rmod is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle rsop PHY to link Receive start of packet signal xsop marks the first word of a packet transfer The PHY layer device must assert rsop for every packet The PHY layer device tri states rsop When renb is high rsop is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle reop PHY to link The receive end of p
2. more information on IP functional simulation models refer to the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook You can simulate the POS PHY Level 2 and 3 Compiler in your design and perform a time limited evaluation of your design in hardware November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 16 Chapter 2 Getting Started Set Up Licensing SS For more information on OpenCore Plus hardware evaluation using the POS PHY Level 2 and 3 Compiler see OpenCore Plus Evaluation on page 1 4 OpenCore Plus Time Out Behavior on page 3 6 and AN 320 OpenCore Plus Evaluation of Megafunctions Set Up Licensing You need to purchase a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production After you purchase a license for the POS PHY Level 2 and 3 MegaCore function you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation 3 Functional Description ANU S RYA The POS PHY Level 2 and 3 Compiler has two interfaces an A interface and one or many B
3. EER ee Notes to Figure 3 16 1 The renb signal is sampled low another read may take place 2 The renb signal is sampled high all signals must stabilize and remain unchanged on the following rfclk rising edge 3 The renb signal was sampled high on the previous rfclk rising edge all signals must remain unchanged The MegaCore function uses this time to sample data from rdat 31 0 The POS PHY specification allows data to be sampled anytime between 3 and 6 3 4 5 or 6 are all valid R The renb signal remains high all signals must remain unchanged a SI The renb signal is sampled low therefore data may change on the next r c1k rising edge g Data on rdat 31 0 and all other signals may change According to the POS PHY specifications when renb is sampled low by the PHY device a read is performed from the receive FIFO buffer and the rdat 31 0 signals are updated on the following rising edge of rfclk POS PHY Level 2 Interface The interface direction is shown as either link to PHY or PHY to link For a POS PHY level 2 link layer MegaCore function the following applies m Linkto PHY results in an output port on the MegaCore function m PHY to link results in an input port on the MegaCore function For a POS PHY level 2 PHY layer MegaCore function the following applies m Linkto PHY results in an input port on the MegaCore function m PHY to link results in an output port on th
4. Figure 2 3 Select the Megafunction MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Stratix II Select a megafunction from the list below using Installed Plug Ins Which type of output file do you want to create Altera SOPC Builder C E Arithmetic C VHDL Communications i a Additional Functions Verilog HDL Encoding Decoding fj POS PHY POS PHY Level 2 and 3 Con POS PHY Level 4 gj UTOPIA m DSP Gates fg 1 0 What name do you want for the output file Browse C altera projects pl2_project examplel Retum to this page for another create operation Interfaces xfj JTAG accessible Extensions xfj Memory Compiler fi Storage Bg IP MegaStore Note To compile a project successfully in the Quartus Il software your design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel lt Back 6 Click Next to launch IP Toolbench POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started 2 5 POS PHY Level 2 amp 3 Walkthrough Step 1 Parameterize To parameterize your MegaCore function follow these steps 1 Click Parameter
5. 7 0 is supported tsop Link to PHY Transmit start of packet signal t sop delineates the packet boundaries on the bus When t sop is high the start of the packet is present on the tdat bus t sop is required to be present at the beginning of every packet and is valid only when tenb is asserted teop Link to PHY Transmit end of packet signal teop delineates the packet boundaries on the bus When teop is high the end of the packet is present on the tdat bus tmod indicates the number of valid bytes the last double word is composed of when teop is asserted ceop is required to be present at the end of every packet and is valid only when tenb is asserted terr Link to PHY Transmit error indicator signal terr indicates that the current packet should be aborted When terr is set high the current packet is aborted terr should only be asserted when teop is asserted tprty Link to PHY Transmit bus parity signal The transmit parity signal indicates the parity calculated over the tdat bus tprty is valid only when tenb is asserted When tprty is supported the PHY layer device must support both even and odd parity The PHY layer device must report any parity error to higher layers but does not interfere with the transferred data tmod 1 0 Link to PHY Transmit word modulo tmod indicates the number of valid data bytes in tdat The tmod bus is normally zero except during th
6. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services UG POSPHY2_3 9 1 LS EN ISO 9001 ATEA Contents Chapter 1 About This Compiler Release Information seeeeeeeeeeee eee he a ee 1 1 Device Family Support e mener ede v e Coh Her e AH HER P Rav 1 1 koe p eee bee as ra seb ew pod dub a RR OA V Reed a used tui etii 1 2 General Description eite eue t e desit eoe ape eedem tenenda tad dtes 1 3 Atlantic Interface ed Red de antlers iie dee oett aide 1 4 OpenCore Plus Evaluation 5 eese eerte e ee ae icr 1 4 Performance and Resource Utilization 0 0 0 0 les 1 5 Chapter 2 Getting Started 2 1 POS PHY Level 2 amp 3 Walkthr hisset nnn 2 2 Create New Quartus IL Project ree ee ret hee men tenter acera Gon ede taa 2 2 Launch IP Toolbench Lee ete eden e Ie tendido pee Pet v eee darts 2 3 step 1s Parameterize 5 cies ser ege ke edens m n e FOU ERU RICE TR ERR RUE Red 2 5 Step 2 Set Up Simulation it eae eee pe LER Ua e EUER ee dee a d eee ted 2 9 Step 3r Generate eu descend des desde eden 2 10 Simulate the Design i e diete eet he d oi e a e e A eed Lebe
7. B Interfaces A Interface None Pass Through Generate Odd Generate Even Parity Control ParErr on Error Pin Press F1 for help e For more information on the parity settings see Parity Settings on page 3 8 10 Click Next 11 Choose the first in first out FIFO buffer settings see Figure 2 9 Figure 2 9 Choose the FIFO Buffer Settings Parameterize POS PHY Level 2 and 3 Compiler FIFO Settings All values in bytes A Interface B Interfaces Size FulThresh Burst Remote Burst Empty Threshold 64 Burst Remote Burst B2 Detect FIFO Overflow FIFO Diagrams AB1 burst empty full Press F1 for help Cancel 7 Prev Next Finish J If you select the Fixed Burst option you must also set the burst size by entering a value in the Burst field Data is then sent in bursts of the specified burst size only or in bursts containing an end of packet November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough La The wizard indicates the minimum Burst value supported You must also adjust the FIFO thresholds so that the data sent to the FIFO for a burst is greater than the burst an end of packet of packet flushes the FIFO The minimum and maximum values are set as follows m Theminimum value mu
8. interfaces Table 3 1 shows the possible interfaces Table 3 1 Possible Interfaces N Interface B Interface PHY level 3 SPHY or MPHY PHY level 3 SPHY only PHY level 2 SPHY or MPHY PHY level 2 SPHY only Link level 3 SPHY or MPHY Link level 3 SPHY only Link level 2 SPHY or MPHY Link level 2 SPHY only Atlantic master SPHY only Atlantic slave SPHY only Figure 3 1 and 3 2 show example interfaces Le MegaCore function data flow direction is from source to sink that is data flows from a physical layer PHY receive source to a link receive sink A MegaCore function must have a minimum of one source and one sink interface Figure 3 1 Example MegaCore Function Interfaces MegaCore Function i FIFO B1 Source i Interface i B2 Source FIFO gt Interface I B3 Source FIFO gt Interface d Bn Source FIFO Interface H A Sink Interface November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 2 Chapter 3 Functional Description Example Configurations Figure 3 2 Fxample Interface MegaCore Function Bi Sink in 4 FIFO Interface i A Source B2 Sink Interface FIFO Interface lt B3 Sink i lt FIFO Interface lt Bn Sink FIFO lt Interface POS PHY level 3 is a point to poin
9. 2 Gbps and level 2 operating at up to 832 Mbps The POS PHY Level 2 and 3 Compiler is compliant with all applicable standards including m POS PHY Level 3 Specification Issue 4 June 2000 m POS PHY Level 2 Specification Issue 5 December 1998 m Optical Internet working Forum OIF System Packet Interface Level 3 SPI 3 m Altera Corporation Atlantic Interface Specification This allows efficient translation between the different formats including mapping between different bus speeds and bus widths as well as customizable FIFO buffer parameters The compiler allows configurations such as PHY PHY link link bridges or packet multiplexing MegaCore functions and SPHY and MPHY applications Figure 1 1 on page 1 3 shows the possible interfaces Figure 1 2 on page 1 4 shows the possible bridges Figure 1 1 Interfaces MegaCore Function i PHY Atlantic User Interface Interface Logic SPHY SPHY MegaCore i Link FUretion Amanti User i Interface Interface Logic TANIEN meme SPHY SPHY MegaCore Function Atlantic User Interface Logic i PHY Link Atlantic User Interface Interface Logic x Z MPHY i SPHY Atlantic User Interface Logic November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler U
10. 3 Walkthrough Figure 2 11 Product Order Code Parameterize POS PHY Level 2 and 3 EBX Order Code s The order code s for the selected core is are IP POSPHY L3 Press F1 for help Step 2 Set Up Simulation An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software It allows for fast functional simulation of IP using industry standard VHDL and Verilog HDL simulators You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes Using these models for synthesis will create a nonfunctional design CAUTION To generate an IP functional simulation model for your MegaCore function follow these steps 1 Click Set Up Simulation in IP Toolbench see Figure 2 12 on page 2 9 Figure 2 12 Toolbench Set Up Simulation Pos PHY Lev E f About this Core Documentation Display Symbol Step 1 Parameterize ZER L7 Set Up Simulation Step 3 Generate 2 Turn on Generate Simulation Model see Figure 2 13 xi E 2 kod o n v gt v E gt m Uu o November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 10 Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough Figure 2 13 Generate Simulation Model Set Up Simulation Genera
11. HDL November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 12 Table 2 1 Generated Files Chapter 2 Getting Started Simulate the Design Extension variation name syn v or Variation name gt syn vhd Description A timing and resource netlist for use in some third party synthesis tools variation name hsf Quartus 11 symbol file for the MegaCore function variation You can use this file in the Quartus 11 block diagram editor variation name cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name ppt This XML file describes the MegaCore function pin attributes to the Quartus II Pin Planner MegaCore function pin attributes include pin direction location 1 0 standard assignments and drive strength If you launch IP Toolbench outside of the Pin Planner application you must explicitly load this file to use Pin Planner variation name ppx This XML file is a Pin Planner support file that Pin Planner automatically uses This file must remain in the same directory as the variation name gt ppt file variation name vhd or variation name v A MegaCore function variation file which defines a VHDL or Verilog HDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside your
12. MegaCore Function ALUTs Registers M9K fmax MHz SPHY receive 121 307 2 243 SPHY transmit 160 294 2 286 MPHY 4 port receive 489 999 8 222 MPHY 4 port transmit 587 984 8 260 November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide POS PHY Level 2 and 3 Compiler User Guide Chapter 1 About This Compiler Performance and Resource Utilization November 2009 Altera Corporation A DTE B4AN 2 Getting Started Design Flow To evaluate the POS PHY Level 2 and 3 Compiler using the OpenCore Plus feature include these steps in your design flow 1 Obtain and install the POS PHY Level 2 and 3 Compiler The POS PHY Level 2 and 3 MegaCore function is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website www altera com S For system requirements and installation instructions refer to Quartus II Installation amp Licensing for Windows and Linux Workstations Figure 2 1 on page 2 1 shows the directory structure after you install the POS PHY Level 2 and 3 Compiler where path is the installation directory The default installation directory on Windows is c altera 90 on Linux it is opt altera90 Figure 2 1 Directory Structure C1 path Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores altera Contains the Altera MegaCore IP Library mo L
13. PHY layer interface configured by the POS PHY Level 2 and 3 Compiler In all cases packets of random length were successfully passed through the system and verified at the other end November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 32 Chapter 3 Functional Description MegaCore Verification POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation ANU S 8J AN Additional Information Revision History The following table shows the revision history for this user guide Date Version Changes Made November 2009 9 1 Added obsolesence notification March 2009 9 0 Added Arria GX device support November 2008 8 1 No changes May 2008 8 0 m Added support for Stratix IV devices m Updated ena signal description m Corrected rfc1k rate October 2007 7 2 Improved desciption of rerr signal May 2007 7A m Updated the device support m Improved rsx signal description December 2006 7 0 Updated the device support December 2006 6 1 m Updated the release information m Updated the directory structure m Added the fixed burst length information to the FIFO buffer settings procedure m Added a procedure for running a testbench simulation with NativeLink How to Contact Altera For the most up to date information about Altera products see the following table Contact Contact Note 1 Method Address Technical support W
14. Performance POS PHY Level 2 Link Layer Stratix 111 Device Memory Blocks Logic MegaCore Function ALUTs Registers M9K fmax MHz SPHY receive 177 348 2 344 SPHY transmit 210 326 2 310 MPHY 4 port receive 558 1 051 8 320 MPHY 4 port transmit 624 1 024 8 221 Table 1 5 Performance POS PHY Level 2 PHY Layer Cyclone Device Part 1 of 2 Memory Blocks MegaCore Function LEs M4K fmax MHz Device EP2C5F256C6 SPHY receive 354 2 174 November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 1 6 Chapter 1 About This Compiler Performance and Resource Utilization Table 1 5 Performance POS PHY Level 2 PHY Layer Cyclone 11 Device Part 2 of 2 Memory Blocks MegaCore Function LEs fmax MHz SPHY transmit 285 2 159 Device EP2C15AF484C6 MPHY 4 port receive 1 175 8 161 MPHY 4 port transmit 1 126 8 139 Table 1 6 Performance POS PHY Level 2 PHY Layer Stratix III Device Memory Blocks Logic MegaCore Function ALUTs Registers M9K fmax MHz SPHY receive 122 309 2 340 SPHY transmit 123 234 2 346 MPHY 4 port receive 487 995 8 318 MPHY 4 port transmit 529 918 8 293 Table 1 7 Performance POS PHY Level 3 Link Layer Cyclone IIl Device Memory Blocks MegaCore Function LEs M9K fmax MHz SPHY receive 379 2 165 SPHY trans
15. and parity errors mty 2 0 1 0 mty 0 0 Word empty bytes mty indicates the number of invalid empty bytes of data dat The mty bus should always be all zero except during the last transfer of a packet on dat When eop is asserted the number of invalid packet data bytes on dat is specified by mty The definition of mty is compatible with the mod signal in the POS PHY level 2 and 3 specifications ty 000 All dat bytes are valid ty 001 dat 7 0 are invalid ty 010 dat 15 0 are invalid ty 011 dat 23 ty 100 dat 31 0 are invalid 0 ty 101 dat 39 0 are invalid 0 0 are invalid ty 110 dat 47 0 are invalid ty l1l dat 55 d 8 zm mu uc are invalid An 8 bit aat bus requires no mty signal A 16 bit dat bus requires amty 0 signal A 32 bit dat bus requires amty 1 0 signal A 64 bit dat bus requires amty 2 0 signal mty can only be non zero when eop is asserted Table 3 14 shows the Atlantic control interface signal definitions POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 29 Interface Signals Table 3 14 Atlantic Interface Control Signals Signal Description ena Data transfer enable ena is always driven by the master and controls the data flow across the interface When the master is the source ena behaves as a write enable
16. are prefixed by b1 b2 and so on POS PHY Level 3 Interface The interface direction is shown as either link to PHY or PHY to link For a POS PHY level 3 link layer MegaCore function the following rules apply November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 18 Chapter 3 Functional Description Interface Signals m Linkto PHY results in an output port on the MegaCore function m PHY to link results in an input port on the MegaCore function For a POS PHY level 3 PHY layer MegaCore function the following rules apply m Linkto PHY results in an input port on the MegaCore function m PHY to link results in an output port on the MegaCore function A interface signals are prefixed by B interface signals are prefixed by b1 b2 and so on Table 3 9 describes the POS PHY level 3 transmit interface Table 3 9 POS PHY Level 3 Transmit Interface Part 1 of 2 Signal tfclk Direction Input Description Transmit FIFO buffer write clock t c1k synchronizes data transfer transactions between the link layer device and the PHY layer device c c1k can cycle at a rate up to 104 MHz tdat 31 0 Link to PHY Transmit packet data bus This bus carries the packet octets that are written to the selected transmit FIFO buffer The tdat bus is valid only when tenb is asserted The data must be transmitted in big endian order on tdat When an 8 bit interface is used only tdat
17. be asserted when is asserted Conditions that can cause to be set can be but are not limited to FIFO buffer overflow abort sequence detection missing SOP missing EOP and parity errors terr is asserted at its input is valid only when rva1 is asserted rmod 1 0 PHY to link Receive word modulo signal xmod indicates the number of valid bytes of data in rdat The rmod bus should always be all zero except during the last double word transfer of a packet on rdat When is asserted the number of valid packet data bytes on rdat is specified by rmod When rmod 1 0 00 rdat 31 0 is valid When rmod 1 0 01 rdat 31 8 is valid When xmod 1 0 10 rdat 31 16 is valid When rmod 1 0 11 rdat 31 24 is valid rmod is valid only when rval is asserted rprty PHY to link Receive parity signal rprty indicates the parity calculated over the rdat bus When rprty is supported the PHY layer device must support both odd and even parity renb Link to PHY Receive read enable see Figure 3 16 renb controls the flow of data from the receive FIFO buffers During data transfer xva1 must be monitored as it indicates if rprty rmod rsop reop rsx and rerr are valid The system can deassert renb at anytime if it is unable to accept data from the PHY device When renb is sampled low by the PHY device a read is performed from the receive FIFO buffer
18. big endian order on dat that is most significant bit MSB first and all valid bits are contiguous with dat 15 0 the MSB dat 7 0 par Parity signal optional indicates the parity calculated over the aat bus Odd and even parity are supported sop Start of packet sop delineates the packet boundaries on the dat bus When sop is high the start of the packet is present on the dat bus sop is asserted on the first transfer of every packet eop End of packet eop delineates the packet boundaries on the dat bus When eop is high the end of the packet is present on the dat bus indicates the number of invalid bytes the last word is composed of when eop is asserted eop is asserted the last transfer of every packet November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 28 Chapter 3 Functional Description Interface Signals Table 3 13 Atlantic Interface Data Signals Part 2 of 2 Signal err Description Error indicator err indicates that the current packet is aborted and should be discarded err may be asserted at any time during the current packet but once asserted it can only be deasserted on the clock cycle after eop is asserted The POS PHY MegaCore function sees this signal as either terr or rerr depending on the data flow direction Conditions that can cause rerr to be set can be but are not limited to FIFO buffer overflow abort sequence detection missing SOP missing EOP
19. common c Contains shared components posphy l2 I3 Contains the POS PHY Level 2 and 3 Compiler files and documentation A doc Contains the documentation for the MegaCore function lib Contains encrypted lower level design files sim_lib Contains the MegaCore function simulation models mo L modelsim Contains the ModelSim simulation models testbench Contains the testbench 2 Create a custom variation of a POS PHY Level 2 or 3 MegaCore function using IP Toolbench 57 IP Toolbench is a toolbar from which you can quickly and easily view documentation specify parameters and generate all of the files necessary for integrating the parameterized MegaCore function into your design November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 2 For more information on IP functional simulation models refer to the Simulating Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough 3 Implement the rest of your design using the design entry method of your choice 4 Use the IP Toolbench generated IP functional simulation model to verify the operation of your design Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook 5 Use the Quartus II software to compile your design 57 You can also generate an OpenCore Plus time limited programming file which you can use to verify the operation of your design in hard
20. dat rprty rmod rsop reop rerr rsx and rval are updated on the following rising edge of x c1k When renb is sampled low by the PHY device a read is not performed and rdat rprty rmod rsop reop rerr rsx and rval are not updated on the following rising edge of x c1k POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description Interface Signals 3 21 Table 3 10 POS PHY Level 3 Receive Interface Part 2 of 2 Signal rval Direction PHY to link Description Receive data valid xva1 indicates the validity of the receive data signals rval transitions low when a receive FIFO buffer is empty or at the end of a packet When rval is high rdat rprty rmod rsop reop and rerr are valid When rval is low the rdat rprty rmod rsop reop and rerr signals are invalid and must be disregarded The rsx signal is valid when xva1 is low rsx PHY to link Receive start of transfer rsx indicates when the in band port address is present on the rdat bus When rsx is high and rval is low the value of rdat 7 0 is the address of the receive FIFO buffer to be selected by the PHY Subsequent data transfers on the rdat bus are from the FIFO buffer specified by this in band address For single port devices the rsx signal is optional as the device does not need to generate in band addresses rsx is valid only when rval is not asserted In normal cond
21. multiple POS PHY level 2 devices to an OC 48 switch Figure 3 8 Example Implementation 2 FPGA MegaCore Function Level 2 Level 2 PHY Device Interface Level 2 Eod Level 2 FIFO Lin io PHY Device i Interface p i OC48 Level 3 Do Switch H PHY Link i Interface Level 2 Level 2 Bod BIRO Lin PHY Device i Interface Level 2 X d i FIFO Lin I ia 2 A Interface Interface 2 evice B Interface Internal Architecture The POS PHY Level 2 and 3 Compiler comprises the following four MegaCore functions m POS PHY level 2 link layer m POS PHY level 2 PHY layer m POS PHY level 3 link layer m POS PHY level 3 PHY layer POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 5 Internal Architecture Each MegaCore function includes a separate receiver and transmitter which can be instantiated in a single device or separate devices There are many similarities in the internal architecture of these blocks The main difference is in the non symmetrical handshaking on the physical interface between receive and transmit directions Figure 3 9 on page 3 5 shows the sink MegaCore function block diagram Figure 3 10 on page 3 5 shows the source MegaCore function block diagram Figure 3 9 Sink MegaCo
22. not verify compilation with MegaCore function versions older than one release Device Family Support MegaCore functions provide either full or preliminary support for target Altera device families m Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs m Preliminary support means the MegaCore function meets all functional requirements but may still be undergoing timing analysis for the device family it may be used in production designs with caution Table 1 2 shows the level of support offered by the POS PHY Level 2 and 3 Compiler to each Altera device family November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide Features POS PHY Level 2 and 3 Compiler User Guide Table 1 2 Device Family Support Chapter 1 About This Compiler Features Device Family Support Arria GX Full Arria Il GX Preliminary Cyclone Full Cyclone Full Cyclone III Full HardCopye Full HardCopy III Preliminary HardCopy IV E Preliminary Stratixe Full Stratix Il Full Stratix II GX Full Stratix III Full Stratix IV Preliminary Stratix GX Full Other device families No support Conforms to POS PHY level 2 and level 3 specifications Link layer or PHY layer POS PHY interfaces Creates bridges between different POS PHY interfaces Support for traffic up to a rate of 3 2 giga
23. the t dat bus fill the FIFO buffer specified by this in band address For single port PHY devices the t sx signal is optional because the PHY device ignores in band addresses when tenb is high t sx is valid only when tenb is not asserted PHY to link Byte level mode Direct transmit packet available dtpa provides status indication of the corresponding port in the PHY device dtpa asserts high when a predefined user programmable minimum number of bytes is available in the transmit FIFO buffer dtpa high does not indicate that the transmit FIFO buffer is full When dtpa transitions low it indicates that its transmit FIFO buffer is full or nearly full user programmable dtpa is required if byte level transfer mode is supported is updated on the rising edge of t c1k tadr 1 Link to PHY Transmit address tadr is used with ptpa to poll the transmit FIFO buffer s packet available status When is sampled the rising edge of t c1k by the PHY the polled packet available indication ptpa is updated with the status of the port specified by the address on the following rising edge of t c1k stpa 2 PHY to link Selected PHY transmit packet available stpa transitions high when fifo threshold Words are available in the transmit FIFO buffer specified by the in band address on tdat When high scpa indicates that the transmit FIFO buffer is not full When stpa transitions low it in
24. 2 Getting Started 2 15 Compile the Design Figure 2 16 Fxample of New Test Bench Settings for NativeLink New Test Bench Settings Create new test bench settings Test bench name Pl3 simulator Top level module in test bench _ _ Design instance name test bench rx Simulation period C Run simulation until all vector stimuli are used End simulation at 100 ns Test bench files Eile name File Library HDL Version auk pac mrs ref tb v Default Cancel 10 When you have entered the required information for your new testbench click OK in the New Test Bench Settings window 11 Click OK in the Test Benches window and then click OK in the Settings window 12 On the Tools menu point to Run EDA Simulation Tool and click EDA RTL Simulation The simulation now begins with your chosen simulation tool Compile the Design You can use the Quartus II software to compile your design Refer to Quartus II Help for instructions on compiling your design Program a Device After you have compiled your design program your targeted Altera device and verify your design in hardware With Altera s free OpenCore Plus evaluation feature you can evaluate the POS PHY Level 2 and 3 Compiler before you purchase a license OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time limited programming file
25. 2 bytes When set high tmod indicates a 1 byte word present on MSBs LSBs are discarded when set low tmod indicates a 2 byte word tsop Link to PHY Transmit start of packet t sop indicates the first word of a packet t sop must be present at the beginning of every packet and is valid only when tenb is asserted teop Link to PHY Active high transmit end of packet teop marks the end of a packet on the bus When teop is high the last word of the packet is present on the tdat stream and tmod indicates how many bytes this last word is composed of t sop must not be high when teop is high teop provides support for one or two bytes packets as indicated by the value of tmod terr Link to PHY The transmit error indicator cexx must only be asserted during the last word transfer of a packet tenb Link to PHY Transmit MPHY write enable tenb is an active low input and is used along with the tadr inputs to initiate writes to the transmit FIFO buffers POS PHY supports byte level and packet level transfer Packet level transfer operates with a selection phase when tenb is deasserted and a transfer phase when tenb is asserted While tenb is asserted is used for polling Byte level transfer works on a cycle basis When tenb is asserted data is transferred to the selected PHY Nothing happens when tenb is deasserted Polling is not available in byte level transfer mode and direct packet ava
26. FO buffers 1 FIFO buffer per channel FIFO buffer burst When there is the internal FIFO buffer full flag is deasserted This allows the interface to start transferring data as soon as it detects the PHY receive interface has indicated it has data When operating in polled mode this is detected using the PRPA input When operating in direct status mode this is detected using the DRPA inputs less than FIFO buffer burst spaces in the FIFO buffer the internal FIFO buffer full flag is asserted In MPHY mode at the end of each FIFO buffer burst the MegaCore function re arbitrates for a new channel in a round robin fashion Set FIFO buffer burst FIFO buffer threshold In SPHY mode this should be set to the minimum value allowed POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 13 Parameters Table 3 4 POS PHY Level 2 FIFO Buffer Settings Part 2 of 2 Interface Direction FIFO Threshold FIFO Burst FIFO Remote Burst PHY When there is more than or equal to FIFO When there is less than FIFO buffer Transmit buffer threshold spaces for bytes in any of burst spaces for bytes in any of its Sink its FIFO buffers 1 FIFO buffer per channel FIFO buffers 1 FIFO buffer per the interface indicates this on a per channel channel the interface indicates this basis to the link transmit interface on a per channel basis to the
27. Global Interface Description Note 1 Signal Direction Description treset n Input Asynchronous reset for all flip flops on the POS PHY source t clk clock domain active low Can be asserted asynchronously but must be deasserted synchronously to t c1k rreset n Input Asynchronous reset for all flip flops on the POS PHY receive rfclk clock domain active low Can be asserted asynchronously but must be deasserted synchronously to x c1k reset n Input Asynchronous reset for the Atlantic interface active low Can be asserted asynchronously but must be deasserted synchronously to clk clk Input Clock rising edge active The Atlantic interface uses single edge clocking All signals are synchronous to clk and master and slave in the same clock domain 7 Note to Table 3 8 1 POS PHY clock signals are described in the relevant interface tables The A interface and each P interface have independent resets which are provided to allow you to assert the reset asynchronously to its clock domain They are not intended to provide individual channel resets If one channel needs a reset all channels must be reset Deasserting the resets must be done synchronously to its clock domain Additionally IP Toolbench can connect the independent resets and clocks to a common reset and clock see Common B Clock on page 3 8 A interface signals are prefixed by a_ B interface signals
28. OS PHY Level 2 and 3 Compiler DER Interface Type B Interfaces A Interface Interface Type B1 Atlantic Slave Level 3 Link Layer POS PHY Level 3 PHY Layer POS PHY Level 2 Link Layer POS PHY Level 2 PHY Layer Press F1 for help 6 Click Next 7 Choose the interface settings see Figure 2 7 on page 2 6 57 POS PHY Level 3 Specification Issue 4 June 2000 supports an 8 or 32 bit interface Additionally this MegaCore function supports a 16 bit interface for POS PHY level 3 5 POS PHY Level 2 Specification Issue 5 December 1998 supports a 16 bit interface Additionally this MegaCore function supports 8 and 32 bit interfaces for POS PHY level 2 5 The Atlantic interface can be 8 16 32 or 64 bits wide Figure 2 7 Choose the Interface Settings Parameterize POS PHY Level 2 and 3 Compiler Interface Settings B Interfaces Bus Width Clock Selection 4 Interface Y B Clock Bus Width 32 Press F1 for help POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started 2 1 POS PHY Level 2 amp 3 Walkthrough 8 Click Next 9 Select the parity settings of the interfaces see Figure 2 8 57 If parity is used the polarity setting must be the same for all interfaces Figure 2 8 Select the Parity Settings Parameterize POS PHY Level 2 and 3 Compiler Parity Settings
29. OS PHY Level 2 and 3 Compiler User Guide 3 6 Chapter 3 Functional Description OpenCore Plus Time Out Behavior Packet Data Width Conversion Packet data width conversion provides conversion from a narrower to a wider data stream and from a wider to a narrower data stream if required such as 8 bit to 32 or 16 bit or 32 bit to 8 or 16 bit and so on Packet FIFO Buffer The packet FIFO buffer has configurable width depth and fill level options The FIFO buffer stores packet data in line with its associated packet flags start of packet SOD end of packet EOP modulo mod and so on B Interface The P interface can be positioned at four different places as follows 1 After the first data width conversion you provide a FIFO like interface The data width must be greater than or equal to the required POS PHY bus width Atlantic interfaces here can only be masters 2 After the packet FIFO buffer you must interface to the internal packet FIFO buffer at the data width of the FIFO buffer which is greater than or equal to that of the required POS PHY bus Atlantic interfaces here can be master or a slave interfaces 3 After the second data width conversion this position provides an interface where the data width can be narrower than that supported by the FIFO buffer For example a 32 bit POS PHY to or from an 8 bit POS PHY Atlantic interfaces here can be a master or a slave interfaces 4 After a POS PH
30. OS PHY Level 3 Specification Issue 4 June 2000 Table 3 10 POS PHY Level 3 Receive Interface Part 1 of 2 Signal rfclk Direction Input Description Receive FIFO buffer write clock x c1k is used to synchronize data transfer transactions between the link layer device and the PHY layer device x c1k can cycle at a rate up to 104 MHz rdat 31 7 0 PHY to link Receive packet data bus The rdat bus carries the packet octets that are read from the receive FIFO buffer rdat is valid only when is asserted Data must be received in big endian order on rdat When an 8 bit interface is used only rdat 7 0 is supported rsop PHY to link Receive start of packet rsop delineates the packet boundaries on the rdat bus When rsop is high the start of the packet is present on the rdat bus rsop must be present at the beginning of every packet and is valid only when rval is asserted reop PHY to link Receive end of packet delineates the packet boundaries on the rdat bus When reop is high the end of the packet is present on the rdat bus rmod indicates the number of valid bytes the last double word is composed of when reop is asserted reop is required to be present at the end of every packet and is valid only when rval is asserted rerr PHY to link Receive error indicator is used to indicate that the current packet is aborted and should be discarded should only
31. POS PHY Level 2 and 3 Compiler User Guide A The IP described in this document is scheduled for product obsolescence and ATON discontinued support as described PDN0906 Therefore Altera does not recommend use of this IP in new designs For more information about Altera s current IP offering refer to Altera s Intellectual Property website ANU S RA 101 Innovation Drive San Jose CA 95134 www altera com MegaCore Version 9 1 Document Date November 2009 Copyright 2009 Altera Corporation rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation
32. RU ERE RP ALPE Eee eR 3 8 lied cic ME 3 8 Pass Through Mode as copied ood ats epistularum tegat 3 8 ParErr On Error vo ess ssis sebane erii a PE Yeu eut Vals D wu wa ce Op Pe Yeh 3 9 FIFO Butter Seting Saree ove a tonc tens UL UC S Cu 3 9 Atlantic Interface FIFO Buffer Settings eene 3 13 FIFO Buffer Size mo br E EE OEE EREE ENEE EDAR RERE ECER EE ERE 3 15 Address amp Packet Available Settings nnn eens 3 15 POS PHY Level3 Interfaces be ERR E ene EE EE 3 15 POS PHY Level 2 Interfaces ERR HERESe ero ee ae IER Ranae ad 3 15 Bas Address eer prar bre E e ReEE EN EE NRENEEAT E br REF Y e bem 3 16 SACAIWAYS s sexes ted rep dus cox ee PPP S ee edi a qa incre d Vaca 3 16 Int rtace Signals ces Feces sheet tu UM PM A UU M SP UN ST 3 16 Global Interface succ e ee Re REDE IE PX ELE RIEN er Rer 3 17 POS PHY Level 3 Interface serii uere EN eee ta EK E E Ra d ates 3 17 POS PH Y Level 2 Interface is cutee ioe eR ekeni RE ERR ED e CREER CUP n E pd 3 22 Atlantic Interface iiec Leer x es bee DER A Lbs e dere Eee eee eed ER E dare 3 26 TMINE dM rrr 3 29 Signal Naming Conventio espe e a bte a E te I pee E atit eei 3 30 Compatibility e Rev r9 E DER eed nies Yee E PEST eee erede dud 3 31 Example Racket Types eben tet
33. Step 2 Set Up Simulation lea Step 3 F Generate POS PHY Level 2 and 3 Compiler Figure 2 15 on page 2 11 shows the generation report Figure 2 15 Generation Report Generation POS PHY Level 2 and 3 Compiler DER Generation Report POS PHY Level 2 and 3 Megacore Compiler File Summary The MegaVVizard interface is creating the following files in the output directory File pescription This XML file is a Pin Planner support file that Pin Planner automatically uses This file must remain in the same directory as the example ppf file This XML file describes the MegaCore pin attributes to the Quartus Il Pin lexample ppf Planner MegaCore pin attributes include pin direction location VO standard assignments and drive strength If you launch the MegaVVizard outside of the Pin Planner application you must explicitly load this file to use Pin Planner MegaCore function variation file which defines a Verilog HDL top level exemple description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus Il software MegaCore Function Generation Successful ancel Table 2 1 describes the generated files and other files that may be in your project directory The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog
34. The wr_outA output goes low m The val_outA output goes low m The sx_outA output goes low m The sop_outA output goes low m heeop outA output goes low m Theerr outAoutput goes high m Thedata outAoutput goes low La For more information on OpenCore Plus hardware evaluation see OpenCore Plus Evaluation on page 1 4 and AN 320 OpenCore Plus Evaluation of Megafunctions The function s parameters which can only be set in IP Toolbench see Step 1 Parameterize on page 2 5 include the following settings Parameters Parameters Interface Settings Interface Settings Parity Settings FIFO Buffer Settings Address amp Packet Available Settings FIFO Buffer amp Clock Selector Options The following interface FIFO buffer and clock selector options are available A Clock No FIFO buffer only available if the B interface is an Atlantic master and the B interface bus width 2 the A interface bus width The relevant B interface does not use an internal FIFO buffer and is clocked by the A interface clock pin This is recommended only if you connect B interfaces directly to another MegaCore function with an Atlantic slave interface A Clock the corresponding B interface uses an internal single clock FIFO buffer and is clocked by the A interface clock pin November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 8 Parity Settin
35. Y interface where you can create a POS PHY bridge From a single compiler you can build a MPHY to multiple SPHY bridge or an SPHY to SPHY bridge You can create more complex solutions by instantiating more than one MegaCore function OpenCore Plus Time Out Behavior Le OpenCore Plus hardware evaluation supports the following two operation modes m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions For MegaCore functions the untethered timeout is 1 hour the tethered timeout value is indefinite Your design stops working after the hardware evaluation time expires and the following events occur POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 7 For the POS PHY receive interface m The sop_ina input goes low m The addr_outa output goes low m The dpav_outa output goes low m The ppav_outa output goes low m The spav_outa output goes low m The rd_outa output goes low For the POS PHY transmit interface m
36. a the MegaCore function always detects the parity error For a source Atlantic interface the par pin is an output that indicates the sink interface has received parity errors For a sink Atlantic interface the par pin is an input that sees either a one or a zero depending on the incoming data s parity value POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 9 Parameters If a parity error is detected on a sink interface port which has a wider data width than its corresponding source interface port the parity output is high on all output words that correspond to the input word with an error see Table 3 2 When a parity error is detected as the data comes in but the data width changes increases there are two options pass through or error Pass through the word that goes out which contains the erroneous word and a good word is flagged with an incorrect parity Error the par signal functionality changes It does not show parity but goes high only when there is an error with the word that is it goes high to show where the error is ParErr On Error Pin When you check this option the err signal 15 created which looks for parity errors in the entire packet The err signal can go high at anytime but is valid only at the end of the packet in accordance with the POS PHY specifications A high indicates a parity error somewhere in the packet A parity err
37. a Packet 1 2 dig Cee eee se crores eee eren oe ee ee ee QUE NE E mty i oe sop Notes to Figure 3 20 1 sop marks the start of the data packet 2 eop marks the end of the data packet and mt y indicates the number of invalid bytes MegaCore Verification Before releasing a version of the POS PHY Level 2 and 3 Compiler Altera runs a comprehensive regression test which executes the wizard to create the instance files Next VHDL testbenches are run in the ModelSim simulator to exercise the VHDL models The regression suite covers various parameters such as input and output interface types and bus widths varying FIFO buffer parameters and relevant architecture options Several computers automatically run these simulations for many days to ensure that the MegaCore function is robust In addition to automated computerized regression testing human testers use IP Toolbench and test many combinations of options and buttons The POS PHY Level 2 and 3 Compiler has also been verified for interworking with simulation models for two PMC Sierra chips The PM5351 uses a POS PHY level 2 4 channel PHY interface and was tested by connecting a POS PHY level 2 link interface configured by the POS PHY Level 2 and 3 Compiler The PM7325 uses a POS PHY level 3 PHY layer or link layer interface and was tested by connecting a POS PHY level 3 link layer or
38. acket signal marks the end of packet on the rdat bus During this same cycle xmod is used to indicate if the last word has 1 or 2 bytes rsop must not be high when reop is high This provides support for one or two bytes packets as indicated by the value of xmod The PHY layer device tri states xeop when renb is high reop is also tri stated when either the null PHY address Ox1F or an address not matching the PHY layer device address is presented on the signals when renb is sampled high has been deasserted during the previous clock cycle rerr PHY to link The receive error indicator signal is used to indicate that the current packet is aborted and should be discarded can only be asserted during the last word transfer of a packet Conditions that can cause to be set may be but are not limited to FIFO buffer overflow abort sequence detection missing SOP missing EOP and parity errors The PHY layer device tri states rerr when renb is high terr is asserted at its input rerr is valid only when rval is asserted is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle renb Link to PHY Receive multi PHY read enable signal renb is used to initiate reads from the receive FIFO buffers The POS PHY specific
39. ation supports both byte level and packet renb transfer Packet level transfer operates with a selection phase when renb is deasserted and a transfer phase when renb is asserted While renb is asserted is used for polling prpa Byte level transfer works on a cycle basis When renb is asserted data is transferred from the selected PHY and is used to select the PHY Nothing happens when renb is deasserted high In byte level transfer mode polling is not possible packet availability is directly indicated by drpa x renb must operate in conjunction with r c1k to access the FIFO buffers at a high enough rate to prevent FIFO buffer overflows The system may deassert renb at anytime it is unable to accept another byte radr 4 0 Link to PHY Receive read address signals The signal is used to select the FIFO buffer and hence port that is read from using the renb signal For packet level transfer is also used to determine the FIFO buffers whose packet available signal is polled on the prpa output Address 1Fh is the null PHY address and must not be responded to by any PHY layer device November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 26 Chapter 3 Functional Description Interface Signals Table 3 12 POS PHY Level 2 Receive Interface Part 3 of 3 Signal rval Direction PHY to link Description Receive data valid signal xva1 indicates th
40. bits per second Gbps POS PHY level 3 or 832 megabits per second Mbps POS PHY level 2 such as SONET OC 48 Single PHY SPHY or up to 8 channel multi PHY MPHY operation with polled and direct packet available options Atlantic interface that allows a consistent interface between all Altera cell and packet MegaCore functions Selectable POS PHY interface bus widths 8 16 32 bit and Atlantic interface bus widths 8 16 32 64 bit allowing translation between different bus types Parity generation detection Configurable first in first out FIFO options selectable FIFO width depth and fill thresholds Easy to use IP Toolbench interface IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators Support for OpenCore Plus evaluation November 2009 Altera Corporation Chapter 1 About This Compiler 1 3 General Description General Description The POS PHY Level 2 and 3 Compiler generates MegaCore functions for use in link layer or physical layer PHY devices that transfer data to and from packet over SONET SDH POS devices using the standard POS PHY bus The POS PHY Level 2 and 3 Compiler comprises separately configurable modules which can be easily combined via the IP Toolbench to generate a highly parameterized module allowing POS PHY compliant interfaces and non standard interfaces to be included in custom designs The compiler supports POS PHY level 3 operating at up to 3
41. ces to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input Active low signals are denoted by suffix n Example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Hm Bullets indicate a list of items when the sequence of the items is not important e The hand points to information that requires special attention A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The angled arrow instructs you to press the enter key The feet direct you to more information about a particular topic POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation
42. d click Start Analysis amp Elaboration a If the analysis and elaboration is not successful fix the error before moving to the next step 6 On the Assignments menu click Settings The Settings window appears Expand EDA Tool Settings and select Simulation 7 In Tool name select a simulator tool from the list In EDA Netlist Writer options select Verilog from the list for Format for output netlist Select VHDL if you are preparing a VHDL simulation In NativeLink settings select the Compile test bench option and then click Test Benches The Test Benches window appears 8 In the Test Benches window click New The New Test Bench Settings window appears 9 In the New Test Bench Settings window enter the information described in Table 2 2 see also Figure 2 16 on page 2 15 To enter the files described in the table browse to the files in your project Table 2 2 NativeLink Test Bench Settings Parameter Setting File Name Test bench name any name Top level module in test bench auk pac mrx ref 1 Design instance name in test bench mrx 1 Run for 100 ns Test bench files auk pac mrx ref tb v 2 Notes to table 1 Use mtx for Tx simulations 2 If you are preparing a VHDL simulation use auk pac mrx ref tb vhd in the vhdl directory Figure 2 16 shows the testbench settings for a receive simulation POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter
43. design Include this file when compiling your design the Quartus II software variation name wo or variation name vho VHDL or Verilog HDL IP functional simulation model 2 After you review the generation report click Exit to close IP Toolbench and click Yes on the Quartus II IP Files message gt The Quartus File qip is a file generated by the MegaWizard interface or SOPC Builder that contains information about a generated IP core You are prompted to add this qip file to the current Quartus II project at the time of file generation In most cases the qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler Generally a single qip file is generated for each MegaCore function and for each SOPC Builder system However some more complex SOPC Builder components generate a separate qip file so the system qip file references the component qip file You can now integrate your custom MegaCore function variation into your design simulate and compile Simulate the Design You can simulate your design using the IP Toolbench generated VHDL and Verilog HDL IP functional simulation models For more information on IP functional simulation models refer to IP Functional Simulation Model on page 2 13 and the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook Altera als
44. dicates that the transmit FIFO buffer is full or near full user programmable st pa always provides status indication for the selected port of the PHY device to avoid FIFO buffer overflows while polling is performed The port which stpa reports is updated on the following rising clock edge of t c1k after the PHY address tdat is sampled by the PHY device stpa is required if byte level transfer mode is supported stpa is updated on the rising edge of tfclk ptpa 1 PHY to link Polled PHY transmit packet available ptpa transitions high when fifo threshold words are available in the polled transmit FIFO buffer When high pt pa indicates that the transmit FIFO buffer is not full When ptpa transitions low it indicates that the transmit FIFO buffer is full or near full user programmable ptpa allows the polling of the PHY selected by the address bus The port that ptpa reports is updated on the following rising edge of t c1k after the PHY address on tadr is sampled by the PHY device ptpa is required if packet level transfer mode is supported ptpa is updated on the rising edge of t clk Notes to Table 3 9 1 Packet level mode only 2 Byte level mode only Table 3 10 describes the POS PHY level 3 receive interface November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 20 Chapter 3 Functional Description Interface Signals La These signals are compliant with the P
45. e MegaCore function A interface signals are prefixed by B interface signals are prefixed by b1 b2 and so on Table 3 11 describes the POS PHY level 2 transmit interface POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description Interface Signals 3 23 Table 3 11 POS PHY Level 2 Transmit Interface Part 1 of 2 Signal tdat 15 7 0 1 Direction Link to PHY Description Transmit packet data bus tdat carries the packet octets that are written to the selected transmit FIFO buffer tdat is valid only when tenb is simultaneously asserted Data must be transmitted in big endian order Given the previously defined data structure bits are transmitted in the following order 15 14 8 7 6 1 0 tprty Link to PHY Transmit bus parity torty indicates the parity calculated over the whole bus When tprty is supported the PHY layer device is required to support both even and odd parity The PHY layer device reports any parity error to higher layers but does not interfere with the transferred data tprty is valid only when tenb is asserted tmod 2 Link to PHY The transmit word modulo tmod indicates the size of the current word tmod should always be low except during the last word transfer of a packet when teop is asserted During a packet transfer every word must be complete except the last word which can comprise 1 or
46. e ce AEN eed tds das eter arent 3 31 MegaCore Verification e ER EA URNA IE Ruta eg qe bea ede d 3 31 Additional Information Revision HIStory dace oes eae CR UO RR aa ec WU os HP geret eeu een 1 1 How to Contact Alter e bem RE hh EB e ean ERU TER eec 1 1 Typographic Conventions E Na ERIT Veteri pede E onte de 1 1 POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation 1 About This Compiler ANU S RYA Release Information Table 1 1 provides information about this release of the Altera POS PHY Level 2 and 3 Compiler Table 1 1 POS PHY Level 2 and 3 Compiler Release Information Item Description Version 9 1 Release Date November 2009 Ordering Codes m POS PHY level 2 PHY IP POSPHY P2 m POS PHY level 2 link IP POSPHY L2 m POS PHY level 3 PHY IP POSPHY P3 m POS PHY level 3 link IP POSPHY L3 Product IDs m POS PHY level 2 PHY 0058 0071 m POS PHY level 2 link 0070 0071 m POS PHY level 2 PHY 0051 0071 m POS PHY level 2 link 0050 0071 Vendor ID 6AF7 La For more information about this release refer to the MegaCore IP Library Release Notes and Errata Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does
47. e last double word transfer of a packet on tdat When teop is asserted the number of valid packet data bytes on c dat is specified by tmod When tmod 1 0 00 31 0 is valid When tmod 1 0 01 tdat 31 8 is valid When tmod 1 0 10 31 16 is valid When tmod 1 0 11 31 24 is valid When tmod 1 0 should only be asserted when teop is asserted POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description Interface Signals 3 19 Table 3 9 POS PHY Level 3 Transmit Interface Part 2 of 2 Signal Direction tenb Link to PHY Description Transmit write enable tenb controls the flow of data to the transmit FIFO buffers When tenb is high tdat tsop teop and terr are invalid and are ignored by the PHY layer The t sx signal is valid and is processed by the PHY when tenb is high When tenb is low tdat tmod tsop teop and terr are valid and are processed by the PHY layer Also the c sx signal is ignored by the PHY layer when tenb is low If you choose Atlantic master for the B interface the tenb signal is combinational tsx Link to PHY Transmit start of transfer signal t sx indicates when the in band port address is present on the tdat bus When tsx is high and tenb is high the value of tdat 7 0 is the address of the transmit FIFO buffer to be selected Subsequent data transfers on
48. e validity of the receive data signals When rval is high the receive signals rdat rsop reop rmod rxprty and rerr are valid When rval is low all receive signals are invalid and must be disregarded rval transitions low on a FIFO buffer empty condition or on an end of packet Data is not removed from the receive FIFO buffer while zva1 is deasserted When deasserted rval remains deasserted until current the PHY has been deselected xva1 allows you to monitor the selected PHY during a data transfer while monitoring or polling other PHYs is done using prpa or x The PHY layer device tri states rval when renb is deasserted rval is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle prpa 3 PHY to link Receive polled multi PHY packet available signal pxpa indicates when data is available in the polled receive FIFO buffer When prpa is high the receive FIFO buffer has at least one end of packet or a predefined number of bytes to be read the number of bytes might be user programmable prpa is low when the receive FIFO buffer fill level is below the assertion threshold and the FIFO buffer contains no end of packet prpa allows to poll every PHY while transferring data from the selected PHY prpa is driven by a PHY layer device when its address is polled on
49. ebsite www altera com support Technical training Website www altera com training Email custrain altera com Altera literature services Email literature altera com Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions that this document uses November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide Additional Information Typographic Conventions Visual Cue Bold Type with Initial Capital Letters Indicates command names dialog box titles dialog box options and other GUI labels For example Save As dialog box bold type Indicates directory names project names disk drive names file names file name extensions and software utility names For example qdesigns directory d drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicates document titles For example AN 519 Stratix IV Design Guidelines Italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets gt For example file name and project gt file Initial Capital Letters Indicates keyboard keys and menu names For example Delete key and the Options menu Subheading Title Quotation marks indicate referen
50. emote burst when the slave deasserts dav the master can transfer up to FIFO buffer remote burst more bytes of data before stopping Figure 3 11 Behavior of the dav Signal as an Input to the Atlantic Master Source Note 1 Slave has space dav y Slave has no space Note to Figure 3 11 1 The slave asserts dav high for two reasons it has passed its threshold or an EOP has occurred November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 14 Chapter 3 Functional Description Parameters For the Atlantic master sink the dav signal is an input The slave indicates to the master that it has data by asserting dav The master then tries to empty the slave FIFO buffer Figure 3 12 shows the behavior of the dav signal FIFO buffer burst is not applicable FIFO buffer remote burst is not applicable Figure 3 12 Behavior of the dav Signal as an Input to the Atlantic Master Sink Note 7 Slave has data Slave has no data Note to Figure 3 12 1 The slave asserts dav high for two reasons it has passed its threshold or an EOP has occurred For the Atlantic slave sink the dav signal is an output The dav signal high indicates that there is space for more data When the FIFO buffer is below full threshold dav is high When the FIFO buffer is filling dav remains high until the FIFO buffer reaches burst threshold When the FIFO buffer is emptying dav remains low until
51. from master to slave The master asserts ena and dat simultaneously When the slave observes ena asserted on the c1k rising edge it immediately captures the Atlantic data interface signals see Figure 3 20 When the slave is the source ena behaves as a read enable from master to slave When the slave observes ena asserted on the c1k rising edge it drives on the next c1k edge the Atlantic data interface signals and asserts val The master captures the data interface signals on the following c1k rising edge If the slave is unable to provide new data it deasserts va1 for one or more clock cycles until it is prepared to drive valid data interface signals For POS PHY level 2 and 3 source variations that uses an Atlantic master sink interface on the B side the bN ena Output signals on the Atlantic master sink interfaces are not guaranteed to be zero during reset bN reset nlow Instead these signals reflect the value of the bN_ dav input signals The bN ena signal may be asserted despite the assertion ofthe reset n signal If your Atlantic source slave logic asserts the bN dav while the POS PHY Level 2 and MegaCore function is in reset the MegaCore function inadvertently begins to read data from the sink logic The data read is not stored in the MegaCore function s buffers nor is it transmitted which results in lost data Ensure that the bN dav input the MegaCore function holds the desired value for bN ena while the MegaCore funct
52. gs Chapter 3 Functional Description Parameters m BClock the corresponding P interface uses an internal dual clock FIFO buffer and is clocked by the corresponding B interface clock pin The FIFO buffer width is the greater of the A bus width and the associated B bus width Common B Clock With MPHY configurations there is more than one B interface in the MegaCore function Select this option to use a common clock and reset pins for all the B interfaces that use the B clock option If you select this option the B interface clock and reset pins are labeled b c1k and b reset n This section describes pass through mode and the parerr on error pin Pass Through Mode In pass through mode any detected data parity errors on a sink interface are regenerated on the source interface even when there is a bus width change If a parity error is detected on a sink interface port that has a wider data width than its corresponding source interface port the parity error is generated on all output words that correspond to the input word with an error Table 3 2 shows the number of errors generated per input error Table 3 2 Number of Errors Generated Data Width In Data Width Out Number of Errors Generated per Input Error 64 8 8 64 16 4 64 32 2 64 64 1 32 8 4 32 16 2 32 32 1 16 8 2 16 16 1 8 8 1 If you are using the parity bit and the parity does not match the dat
53. hardware POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 1 About This Compiler 1 5 Performance and Resource Utilization You only need to purchase a license for the megafunction when you are completely satisfied with its functionality and performance and want to take your design to production lt For more information on OpenCore Plus hardware evaluation using the POS PHY Level 2 and 3 Compiler see OpenCore Plus Time Out Behavior on page 3 6 and AN 320 OpenCore Plus Evaluation of Megafunctions Performance and Resource Utilization Table 1 3 through 1 7 show typical expected performance for SPHY and 4 port POS PHY MegaCore functions All results are push button performance and use a FIFO buffer size of 512 bytes These results were obtained using the Quartus II software version for the following devices m Cyclone II see tables for device details m Cyclone III EP3C5F256C6 for POS PHY level 3 m Stratix III EP3SL70F484C2 for POS PHY level 2 EP3SL50F484C2 for POS PHY level 3 m Stratix IV EPASGX70DF29C2X Table 1 3 Performance POS PHY Level 2 Link Layer Cyclone II Device Memory Blocks MegaCore Function LEs M4K fmax MHz Device EP2C5F256C6 SPHY receive 416 2 176 SPHY transmit 407 2 149 Device EP2C15AF484C6 MPHY 4 port receive 1 267 8 167 MPHY 4 port transmit 1 272 8 128 Table 1 4
54. idging Functions i MegaCore Function 1 50 MHz Level2 16bit FIFO PHY i Interface 100MHz 50 MHz 32 bit Level 3 Level 2 16bit Link FIFO PHY j Interface Interface 1100 2 Level3 FIFO PHY Interface Figure 3 6 on page 3 3 shows an MPHY to MPHY POS PHY bridge which includes an MPHY POS PHY level 2 interface and one first in first out FIFO buffer per supported address MPHY Figure 3 6 Example Configuration 3 MPHY to MPHY Bridge Atlantic Interfaces MegaCore Function 1 A MegaCore Function 2 i if i FIFO H IM 100 MHz LAI i 50 MHz 8bit Level3 Eq i Level2 i 16 bit FIFO LL Link Interface U i Interface Example Implementations Figure 3 7 shows the FPGA interfacing to an OC 48 framer November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 4 Chapter 3 Functional Description Internal Architecture Figure 3 7 Example Implementation Atlantic Interfaces FPGA quem MegaCore Function 1 i Level 3 Link Dd 4 H Interface p PHY U Source Sod User Logie OC48 Framer MegaCore Functi i Level 3 Link Interface 4 N PHY U i Sink Pod Figure 3 8 on page 3 4 shows the FPGA interfacing
55. ilability is provided by x tadr 4 0 Link to PHY Transmit PHY address bus The bus is used to select the FIFO buffer and hence the port that is written to using the tenb signal and the FIFO buffer whose packet available signal is visible on the PTPA output when polling Address 1Fh is the null PHY address and must not be identified to any port on the POS PHY bus stpa 3 PHY to link Selected PHY transmit packet available signal stpa transitions high when fifo threshold words are available in the selected transmit FIFO buffer the one data is written into When high stpa indicates that the transmit FIFO buffer is not full When stpa transitions low it indicates that the transmit FIFO buffer has reached i o threshold words stpa always provides status indication for the selected PHY to avoid FIFO buffer overflows while polling is performed The PHY layer device tri states stpa when tenb is deasserted scpa is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the signals when tenb is sampled high has been deasserted during the previous clock cycle November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 24 Chapter 3 Functional Description Interface Signals Table 3 11 POS PHY Level 2 Transmit Interface Part 2 of 2 Signal Direction Description ptpa 3 PHY to l
56. in In the POS PHY receive direction the MegaCore function uses renb and rval and does not use an rsx pin POS PHY Level 2 Interfaces The POS PHY level 2 interfaces can be multi or single channel Table 3 7 shows the multi channel packet available mode options November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 16 Ls Chapter 3 Functional Description Interface Signals Table 3 7 Multi amp Single Channel Packet Available Mode Options POS PHY Level 2 Option Description Direct In the POS PHY transmit direction the MegaCore function uses one dtpa pin per supported channel In the POS PHY receive direction the MegaCore function uses one drpa pin per supported channel Polled In the POS PHY transmit direction the MegaCore function uses tadr ptpa and stpa to support all channels In the POS PHY receive direction the MegaCore function uses and prpa to support all channels Polled Ignore In the POS PHY transmit direction the MegaCore stpa function uses cadr and ptpa pins to support all channels The scpa signal is removed from the MegaCore function Direct No Addressing mode does not include address matching or bus tri stating currently not supported Base Address Base address is only supported in POS PHY level 2 mode It configures the base address of the POS PHY port For a single channel interface A or B the interface res
57. ink Polled PHY transmit packet available signal pt pa transitions high when fifo threshold words is available in the polled transmit FIFO buffer When high ptpa indicates that the transmit FIFO buffer is not full When pt pa transitions low it indicates that the transmit FIFO buffer has reached threshold words PTPA allows to poll the PHY address selected by tadr when tenb is asserted ptpa is driven by a PHY layer device when its address is polled on tadr A PHY layer device tri states ptpa when either the null PHY address 0x1F or an address not matching available PHY layer devices is provided on tadr dtpa x 4 PHY to link Direct transmit packet available dtpa x provides direct status indication for the corresponding port referred to by the index x dtpa x transitions high when fifo threshold words are available in the transmit FIFO buffer When high dtpa x indicates that the transmit FIFO buffer is not full When x transitions low it indicates that the transmit FIFO buffer has reached fifo threshold words tfclk Link to PHY Transmit FIFO buffer write clock c c1k is used to synchronize data transfer transactions from the link layer device to the PHY layer device c c1k can cycle at any rate from 25 MHz up to 50 MHz Votes to Table 3 11 1 The 8 bit mode is an Altera extension to the POS PHY Level 2 specification 2 Not present in 8 bit mode 3 Packet level mode on
58. interface indicates this on a channel basis to the link transmit per channel basis to the link interface transmit interface When operating in polled mode When operating in polled this is indicated by asserting PTPA mode this is indicated by and STPA outputs deasserting the PTPA and When operating in direct status STPA outputs mode this is indicated by asserting When operating in direct the DTPA outputs status mode this is indicated by deasserting the DTPA outputs PHY When each FIFO buffer fills to Indicates the maximum Receive above the FIFO buffer threshold number of bytes the interface Source level or contains a packet or transfers in each FIFO buffer packet fragment with an EOP it burst triggers its not empty flag The In MPHY mode at the end of interface then tries to empty each sach FIFO buffer burst the of the FIFO buffers with data as MegaCore function re soon as it detects the link receive arpitrates for a new channel interface has asserted low the in a round robin fashion RENB input Set FIFO buffer burst lt FIFO buffer threshold In SPHY mode this should be set to the minimum value allowed Table 3 4 shows the effect of the FIFO buffer settings for POS PHY level 2 interfaces November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 12 Chapter 3 Functional Description Parameters Table 3 4 POS PHY Level 2 FIFO Buffer Settings Part 1 of 2 Inte
59. ion is in reset which can be implemented in one of the following ways m Ensure that the Atlantic slave source logic is reset while the MegaCore function is in reset m Drive the bN dav input signal from a flip flop reset by bN reset fed by your desired dav signal val Data valid Present only on a slave source and master sink interface When high va1 indicates valid data signals va1 is updated on every clock edge where ena is sampled asserted and holds its current value along with the dat bus where ena is sampled deasserted Invalid signals va1 low must be disregarded To determine whether new data has been received the master must qualify the va1 signal with the previous state of the ena signal dav Data available When the dat bus is in slave to master direction if is high the slave has at least threshold words available to be read or the data can be read up to an end of packet without risk of underflow When the dat bus is in master to slave direction if dav is high the slave has enough space for threshold words to be written 1 Note to Table 3 13 1 thresholdis implementation dependent and typically corresponds to FIFO buffer almost full empty levels Timing For a slave source to master sink there is a single cycle delay after ena is asserted or deasserted and dataflow on dat and associated data interface signals starts or stops However the interface is pipelined so the delay does
60. itions rsx indicates a change of address If the enable signal goes inactive as the core decides to select the address you can have rsx going high while enable is deasserted When enable gets reasserted the core may reassert rsx With a different address selected For example when the core decides to reselect the same address just before it is asked to go inactive By default the core reselects the same address if data is still available even if less than a burst When enable gets de asserted the core checks all possible addresses and if another address reaches the threshold it selects the new address instead Although it does not violate any POS PHY protocol some devices may select the address on the first xsx and not reselect the address on the second rsx To avoid this issue use the fixed burst size For fixed burst sizes the core waits at the end of a packet to ensure the presence of data If no other port has data the core reselects the current one after a short pause Thus the rsx signal gets asserted when enable goes high inactive The rsx signal stays high until the enable goes active again but the address does not change Figure 3 16 shows the renb signal behavior November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 22 Chapter 3 Functional Description Interface Signals Figure 3 16 The renb Signal Behavior rdat 31 0 SEE TIENE NY E 1 3 4 5 6
61. ize in the IP Toolbench see Figure 2 4 on page 2 5 Figure 2 4 P Toolbench Parameterize POS PHY Lev EJER HU Display Symbol R step 1 Buon Step 2 Set Up Simulation Step 3 Generate 2 Select your architecture options where the POS PHY A interface is a data source or sink see Figure 2 5 POS PHY Level 2 and 3 Compiler 57 Source indicates that interface A is an output from the MegaCore function Sink indicates that interface A is an input to the MegaCore function Figure 2 5 Select the A Interface Direction Parameterize POS PHY Level Architecture Options Interface Bus Direction Source O Sink Number of channels 1 Press F1 for help 3 Ina MPHY architecture there is a B interface for each supported channel maximum eight Select the number of supported channels that you require Ka Tocreate a design that supports source and sink data directions you must run IP Toolbench twice to create the source and sink designs separately November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 6 Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough 4 Click Next 5 Select your interface types see Figure 2 6 a Select interface A using the radio buttons b Choose B interfaces using the drop down menus Figure 2 6 Select the Interface Types Parameterize P
62. link When operating in polled mode this is transmit interface indicated by asserting PTPA and STPA When operating in polled mode outputs this is indicated by deasserting the When operating in direct status mode this PTPA output is indicated by asserting the DTPA outputs When operating in direct status mode this is indicated by deasserting the DTPA outputs PHY When there are more than FIFO buffer When there are less than or equal to Receive threshold bytes any of its FIFO buffers 1 FIFO buffer burst bytes any of its Source FIFO buffer per channel the interface FIFO buffers 1 FIFO buffer per indicates this on a per channel basis to the channel the interface indicates link receive interface this on a per channel basis to the When operating in polled mode this is link receive interface indicated by asserting the PRPA output When operating in polled mode When operating in direct status mode this this is indicated by deasserting the is indicated by asserting the DRPA outputs PRPA output When operating in direct status mode this is indicated by deasserting the DRPA outputs Atlantic Interface FIFO Buffer Settings For the Atlantic master source the dav signal is an input The slave indicates to the master that it has space by asserting dav The master then tries to fill the slave FIFO buffer Figure 3 11 shows the behavior of the dav signal FIFO burst is not applicable FIFO buffer r
63. ly 4 Byte level mode only Table 3 12 describes the POS PHY level 2 receive interface Ka All these signals are compliant with the POS PHY Level 2 Specification Issue 5 December 1998 Table 3 12 POS PHY Level 2 Receive Interface Part 1 of 3 Signal Direction Description rdat 15 7 0 PHY to link Receive packet data bus The rdat bus carries the packet octets that are read from the 1 selected receive FIFO buffer xaat is valid only when renb is simultaneously asserted and a valid PHY layer device has been selected via the signals Data must be received in big endian order Given the defined data structure bits are received in the following order 15 14 8 7 6 1 0 The PHY layer device tri states rdat when renb is high rdat is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle rprty PHY to link Receive parity signal xprty signal indicates the parity of the rdat bus When rprty is supported the PHY layer device must support both odd and even parity The PHY layer device tri states rprty when renb is high rprty is also tri stated when either the null PHY address 1Fh or an address not matching the PHY layer device address is presented on the radr signals when renb is sampled high has been deasserted during the previous clock cycle
64. mit 377 2 139 MPHY 4 port receive 1 202 8 171 MPHY 4 port transmit 1 242 8 164 Table 1 8 Performance POS PHY Level 3 Link Layer Stratix 111 Device Memory Blocks Logic MegaCore Function ALUTs Registers M9K fmax MHz SPHY receive 149 330 2 234 SPHY transmit 164 313 2 205 MPHY 4 port receive 522 1 019 8 217 MPHY 4 port transmit 613 1 009 8 178 Table 1 9 Performance POS PHY Level 3 Link Layer Stratix IV Device Memory Blocks Logic MegaCore Function ALUTS Registers M9K fmax MHz SPHY receive 149 330 2 231 SPHY transmit 164 313 2 180 MPHY 4 port receive 522 1 019 8 254 MPHY 4 port transmit 613 1 009 8 174 POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 1 About This Compiler Performance and Resource Utilization 1 7 Table 1 10 Performance POS PHY Level 3 PHY Layer Cyclone 111 Device Memory Blocks MegaCore Function LEs M4K fmax MHz SPHY receive 350 2 174 SPHY transmit 365 2 173 MPHY 4 port receive 1 175 8 169 MPHY 4 port transmit 1 218 8 143 Table 1 11 Performance POS PHY Level 3 PHY Layer Stratix Device Memory Blocks Logic MegaCore Function ALUTs Registers M9K fmax MHz SPHY receive 121 307 2 270 SPHY transmit 160 294 2 287 MPHY 4 port receive 489 999 8 245 MPHY 4 port transmit 587 984 8 231 Table 1 12 Performance POS PHY Level 3 PHY Layer Stratix IV Device Memory Blocks Logic
65. ms Altera Quartus II version Windows Start menu to run the Quartus II software Alternatively you can also use the Quartus II Web Edition software 2 Choose New Project Wizard File menu 3 Click Next in the New Project Wizard Introduction page the introduction does not display if you turned it off previously 4 In the New Project Wizard Directory Name Top Level Entity page enter the following information a Specify the working directory for your project For example this walkthrough uses the c Naltera projects V plI2pl3 project directory a The Quartus II software automatically specifies a top level design entity that has the same name as the project This walkthrough assumes that the names are the same b Specify the name of the project This walkthrough uses example for the project name 5 Click Next to close this page and display the New Project Wizard Add Files page When you specify a directory that does not already exist a message asks if the specified directory should be created Click Yes to create the directory 6 Click Next to close this page and display the New Project Wizard Family amp Device Settings page 7 On the New Project Wizard Family amp Device Settings page choose the target device family in the Family list 8 The remaining pages in the New Project Wizard are optional Click Finish to complete the Quartus II project You have finished creating your new Quartus II
66. n direct no addressing mode POS PHY Level 3 Interfaces The POS PHY level 3 interfaces can be multi or single channel Table 3 5 shows the multi channel packet available mode options Table 3 5 Multi Channel Packet Available Mode Options POS PHY Level 3 Option Description Direct In the POS PHY transmit direction the MegaCore function uses one dtpa pin per supported channel Inthe POS PHY receive direction the MegaCore function uses renb and rva1 to support all channels Polled In the POS PHY transmit direction the MegaCore function uses ptpa and stpa to support all channels Polled Ignore stpa In the POS PHY transmit direction the MegaCore function uses and ptpa to support all channels For compatibility with some POS PHY interfaces that do not support the functionality of the stpa pin the stpa signal is ignored and removed from the MegaCore function Table 3 6 shows the multi channel packet available mode options B interfaces always operate in direct mode Table 3 6 Single Channel Packet Available Mode Options POS PHY Level 3 Option Description Direct In the POS PHY transmit direction the MegaCore function uses one dtpa pin and uses a tsx pin In the POS PHY receive direction the MegaCore function uses renb and rval and uses rsx pin Direct No Addressing In the POS PHY transmit direction the MegaCore function uses one dtpa pin and does not use a tsx p
67. not affect the net throughput of the interface Figure 3 18 on page 3 30 shows the timing of the Atlantic interface with a master sink November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 30 Chapter 3 Functional Description Interface Signals Figure 3 18 Atlantic Interface Timing Slave Source to Master Sink 1 phe ngu JE X e Notes to Figure 3 18 1 Slave source indicates that data is available either threshold words available or EOP 2 Master sink begins reading data 3 Master sink decides to stop reading the data for one clock cycle val remains asserted and data sop and eop hold their current values 4 Slave source indicates that it has less than threshold words available The master sink can continue to read data until it detects val deasserted 5 Master sink continues to read data validates data with va1 D Slave source cannot supply any more data so deasserts val T N Master sink goes idle until dav is re asserted Figure 3 19 shows the timing of the Atlantic interface with a master source Figure 3 19 Atlantic Interface Timing Master Source to Slave Sink 1 3 4 5 6 7 PP PP AP r wae MEN c 9 Notes to Figure 3 19 1 Slave sink indicates it has space for at leas
68. o provides fixed example VHDL and Verilog HDL testbenches that you can use to simulate example sink or source POS PHY systems You can use a testbench as a basis for your own design The testbenches can be used with the IP functional simulation models The testbenches and associated files are located in the sim libNtestbench directory POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started 2 13 Simulate the Design IP Functional Simulation Model This section tells you how to use the demonstration testbench with the ModelSim simulator or with other simulators using NativeLink For more information on NativeLink refer to the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook Testbench with the ModelSim Simulator To use an example testbench with IP functional simulation models in the ModelSim simulator follow these steps 57 The testbench includes pregenerated Verilog HDL IP functional simulation models 1 Start the ModelSim simulator 2 Change the directory to the sim_lib modelsim directory 3 For VHDL type the following command do compile p13 link source fixed example vlog ipfs tcle or for Verilog HDL type the following command do compile p13 link source fixed example vhdl ipfs tcle 57 For the sink example replace source with sink Testbench with NativeLink You can run receive and transmit tests wi
69. or detected on a sink interface is signalled by setting the err pin at the end of the affected packet on the source interface FIFO Buffer Settings Table 3 3 shows the effect of the FIFO buffer settings for POS PHY level 3 interfaces Ka All FIFO buffer parameters are shown in bytes November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 3 10 Chapter 3 Functional Description Parameters Table 3 3 POS PHY Level 3 FIFO Buffer Settings Part 1 of 2 Interface Direction FIFO Threshold FIFO Burst FIFO Remote Burst Link When each FIFO buffer overflows Indicates the maximum Prevents the PHY transmit interface Transmit the FIFO buffer threshold level number of bytes the interface from overflowing Must be compatible Source contains a packet or packet transfers in each FIFO buffer with the PHY transmit interface FIFO fragment with an EOP it triggers burst buffer burst setting When the interface its not empty flag The interface In MPHY mode at the end of is in the process of transferring data then tries to empty each of the FIFO each FIFO buffer burst the and the PHY transmit interface indicates buffers containing data as soon as MegaCore function re itis almost full link transmit interface it detects the PHY transmit arbitrates for a new channel transfers up to FIFO buffer remote burst interface has indicated it has space in a round robin fashion more bytes before stopping When opera
70. ponds to only the configured base address For a multi channel interface A only the interface responds to addresses between base address and base address number of B interfaces SX Always SX always is only valid for POS PHY level 3 link transmit multi channel or PHY receive source interfaces You can set the SX output behavior to one of the following conditions m Normal generates an SX cycle only when changing channels m Always an SX cycle is generated for every burst and at the end of packets For POS PHY level 3 sink interfaces the MegaCore function supports either behavior transparently Interface Signals The following section describes the interface signals for the MegaCore functions Figure 3 15 shows the input output specification POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 17 Interface Signals Figure 3 15 Input Output Specification Sink MegaCore Function A 8 to 32 Bus Width 8 to 64 bit 8 to 64 Bus Width 8 to 64 mP Conversion FIFO mP Conversion p gt lated Interface wider narrower menace A 8 to 32 Bus Width 8 to 64 8 to 64 bit 8 to 64 bes Width 8 to 64 S d M Cc i onversion interface ibique FIFO wider Interface Global Interface Table 3 8 describes the global interface signals Table 3 8
71. project Launch IP Toolbench To launch IP Toolbench in the Quartus II software follow these steps 1 Start the MegaWizard Plug In Manager by choosing MegaWizard Plug In Manager Tools menu The MegaWizard Plug In Manager dialog box displays 57 Refer to the Quartus II Help for more information on how to use the MegaWizard Plug In Manager November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 4 Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough Figure 2 2 MegaWizard Plug In Manager MegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions Which action do you want to perform Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright 1991 2009 Altera Corporation Cancel 2 Specify that you want to create a new custom megafunction variation and click Next 3 Expand the Communications gt POS PHY directory then click POS PHY Level 2 amp 3 Compiler 4 Select the output file type for your design the wizard supports VHDL and Verilog HDL 5 The MegaWizard Plug In Manager shows the project path that you specified in the New Project Wizard Append a variation name for the MegaCore function output files lt project path gt lt variation name gt Figure 2 3 shows the wizard after you have made these settings
72. r cem ig ote eol 2 12 IP Functional Simulation eene 2 13 Testbench with the ModelSim Simulator eens 2 13 Testbench with Nativelink hehehe herede rre rr eens 2 13 Com pile the boi Ge Ed dicte Ded pete edet dene 2 15 Program a Device 3 222 ei er e RR REC nni nq La e db de Rb e a Rd n RR 2 15 Set Up Licensing Cea dec iade fada d aera e E eee qa e Pra per dest 2 16 Chapter 3 Functional Description Example Configurations ep e HERE DER RC E RE DIR ERE RE 3 2 Example Implementations Coe Ra ee Pacte A Pee eet 3 3 Interral Arch tecture eat ans E adeste ede ida 3 4 POS PELY Interface isis ditt ae ERE t ln a rh a eli tet e aedi teretes 3 5 Packet Data Width Conversion 00 nee 3 6 Packet FIFO tree pee oce ee ed ded ee poe d pe doe e dio 3 6 Bi Bterface ae don pec tite 3 6 OpenCore Plus Time Out Behavior ai e 3 6 November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide Parameters TP a 3 7 Interface ULT 3 7 FIFO Buffer amp Clock Selector Options 0 3 7 Common Clock crises ine ere e e eR
73. radr A PHY layer device tri states prpa when either the null PHY address 1Fh or an address not matching available PHY layer devices is provided on radr drpa x 4 PHY to link Receive packet available direct status indication signals These signals provides direct status indication for the corresponding port referred to by x drpa x indicates when data is available in the receive FIFO buffer When drpa x is high the receive FIFO buffer has at least one end of packet or a predefined number of bytes to be read The number of bytes is user programmable drpa x is low when the receive FIFO buffer fill level is below the assertion threshold and the FIFO buffer contains no end of packet rfclk Link to PHY Receive FIFO buffer write clock x c1k is used to synchronize data transfer transactions from the link layer device to the PHY layer device x c1k can cycle at a any rate from 25 MHz up to 50 MHz Notes to Table 3 12 1 The 8 bit mode is an Altera extension to the POS PHY Level 2 specification 2 4 2 Not present in 8 bit mode 3 Packet level mode only 4 Byte level mode only Atlantic Interface The Atlantic interface is a full duplex synchronous point to point connection protocol The POS PHY Level 2 and 3 Compiler supports data widths of 8 16 32 and 64 bits on the Atlantic interface For further information on the Atlantic interface refer to the Atlantic Interface F
74. re Function Block Diagram Date Port N e e p gt p Port 2 p gt e p e p p Control Port i Data Packet Data Packet Data Link layer Link layer or Width Packet i Width i PHY Layer PHY Layer Conversion i FIFO i Conversion Source Contro Sink wider 4 i p 4 H p narrower Interface 4 gt Interface Br o B Interface Options Figure 3 10 Source MegaCore Function Block Diagram Data Port N duo S gt 4 Control 44 00 Multiplexer Port 0 Packet Data Packet Data Link layer or Width Packet Width PHY Layer Ink cayenror Conversion FIFO d Conversion Sink Control PHY Layer wider Interface Source Interface narrower Lid d B Interface Options POS PHY Interface Each POS PHY supports single and multi PHY implementations The POS PHY interface interfaces to an internal multiplexer which allows access to multiple single internal packet FIFO buffers Status information from the FIFO buffers is used to control the POS PHY interface The source interface provides polled or direct packet available modes November 2009 Altera Corporation P
75. rface Direction FIFO Threshold FIFO Burst FIFO Remote Burst Link When each FIFO buffer fills to above the Indicates the maximum number of When the interface is in Transmit FIFO buffer threshold level or contains a bytes the interface transfers in each the process of Source packet or packet fragment with an EOP it FIFO buffer burst transferring data and the triggers its not empty flag The interface In MPHY mode at the end of each PHY transmit interface then tries to empty each of the FIFO buffers FIFO buffer burst the MegaCore indicates it is almost full containing data as soon as it detects the function re arbitrates for a new the link transmit interface PHY transmit interface has indicated it has channel in a round robin fashion transfers up to FIFO space Set FIFO buffer burst lt buffe buffer remote burst more e uffer burst lt uffer When operating in polled mode this is threshold bytes before stopping detected using the PTPA and STPA inputs Mt i hle in SPHY mod When operating in polled ot applicable in mode iei When operating in direct status mode this mode this is detected is detected using the DTPA inputs using the PTPA and STPA inputs When operating in direct status mode this is detected using the DTPA inputs Link When there is more than or equal to FIFO Indicates the maximum number of Receive buffer threshold spaces for bytes in any of bytes the interface transfers in each Sink its FI
76. ser Guide 1 4 Chapter 1 About This Compiler General Description Figure 1 2 Bridges MegaCore Function Level 2 3 Level 2 3 Link Link Interface Interface MegaCore Function 3 Level 2 3 Level 2 3 PHY PHY Interface Interface M SPHY p SPHY i MegaCore Function Level 2 3 Level 2 3 Link PHY i Interface Interface SPHY SPHY MegaCore Level 2 3 Function PHY Link Interface Level 2 3 Level 2 3 PHY Link PHY Link Interface Interface MPHY i sPHY i Level 2 3 i PHY Link Interface Atlantic Interface The Atlantic interface allows a consistent interface between all Altera cell and packet MegaCore functions The Atlantic interface supports a point to point connection For more information on the Atlantic interface refer to FS 13 Atlantic Interface OpenCore Plus Evaluation With Altera s free OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPP M megafunction within your system m Verify the functionality of your design as well as evaluate its size and speed quickly and easily m Generate time limited device programming files for designs that include megafunctions m Program a device and verify your design in
77. st be set at the size of the remote burst If you set any value below this it is automatically adjusted to the size of the remote burst m The maximum value is derived from the empty threshold It must take into account the latency in the pipeline and the time that the core takes to decide to stop sending data Therefore the maximum burst size is calculated as follows A interface empty threshold in bytes 5 x i o byte width Where fifo byte width is the width in bytes of the FIFO 4 for a 32 bit data width For more information on the FIFO buffer settings see FIFO Buffer Settings on page 3 9 12 Click Next 13 Choose the address and packet available settings see Figure 2 10 Figure 2 10 Choose the Address and Packet Available Settings Parameterize POS PHY Level 2 and 3 Compiler Address amp Packet Available Settings A Interface B Interfaces Packet Available Mode Base Addr SX Always Direct No Addressing v Packet Available Mode Direct No Addressing Base Address La Press F1 for help For more information on the address and packet available settings see Address amp Packet Available Settings on page 3 15 14 Click Next 15 IP Toolbench shows the product order codes see Figure 2 11 Click Finish POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started 2 9 POS PHY Level 2 amp
78. t system transmit joins to transmit channel 0 joins to channel 0 and so on see Figure 3 3 POS PHY level 2 is a unidirectional bus system Figure 3 3 Connecting POS PHY Level 3 MegaCore Functions PHY Transmit Sink Source Link Transmit i Function Interface Interface Function PHY Receive Source Sink Link Receive Function Interface Interface Function Example Configurations Figure 3 4 on page 3 2 shows a packet processing function which receives packets at one end from a POS PHY PHY interface processes them and passes them on to a POS PHY link interface Figure 3 4 Example Configuration Use of the Atlantic Interface Atlantic Atlantic Interfaces Interfaces MegaCore Function 1 f MegaCore Function 2 FIFO H L FIFO i V V d 100 MHz A A i 100 MHz 32bit Level 3 Packet L i Level 3 32 bit Link FIFO H 1 1 Processing FIFO PHY ER Interface V Function U i Interface 1 AN f FIFO t FIFO U U POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 3 Example Implementations Figure 3 5 shows a bridging function with multiple lower rate ports which can be 8 bit POS PHY level 3 or 16 bit POS PHY level 2 Figure 3 5 Fxample Configuration 2 POS PHY Br
79. t threshold words 2 The master source begins writing data to the slave sink 3 Slave sink indicates it has space for threshold words Master source can continue to send data but must ensure that the slave sink does not overflow Master source stops sending data Slave sink indicates it has space for at least threshold words Master source begins writing data to the slave sink Slave sink indicates it still has space but the master source has run out of data 4 5 6 7 Signal Naming Convention When you include an Atlantic interface in a design the IP Toolbench generates the signal names which are prefixed by port name such as b1 ena b1 val b2 ena b2 val POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 31 MegaCore Verification Compatibility To ensure that individual implementations of an Atlantic interface are compatible they must have the following m Thesame data bus width m Compatible data directions data source connecting to data sink m Compatible control interfaces master interface connecting to slave interface m Compatible FIFO buffer threshold levels slave sink can overflow and slave source can operate inefficiently if thresholds are incorrectly set Example Packet Types Figure 3 20 shows an example data packet The assumption is that ena and val are continuously asserted Figure 3 20 Example Dat
80. te Simulation Model Language Verilog HDL An IP Functional Simulation Model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus software These models allow fast functional simulations of IP using industry standard VHDL and Verilog HDL simulators You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes Using these models for synthesis will create a non functional design Ifyou are synthesizing your design with a third party EDA synthesis tool you can generatea netlist for the synthesis tool to estimate timing and resource usage for this megafunction 3 Choose the language in the Language list 4 Some third party synthesis tools can use a netlist that contains only the structure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist 5 Click OK Step 3 Generate To generate your MegaCore function follow these steps 1 Click Step 3 Generate in IP Toolbench see Figure 2 14 POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started POS PHY Level 2 amp 3 Walkthrough 2 11 Figure 2 14 P Toolbench Generate pos PHY Lev X Aboutthis Core E Documentation Display Symbol Step 1 Parameterize
81. th third party IP functional simulators using NativeLink for VHDL or Verilog HDL The following procedure describes a receive test for the Verilog HDL model To use the testbench with NativeLink follow these steps 1 Using the New Project Wizard in the Quartus II software create a new project in the posphy_12_13 sim_lib testbench verilog directory with the project name and top level entity name of auk pac mrx pl3 link For the VHDL model replace the verilog directory with the vhdl directory gt For the transmit test replace mrx with mtx 2 Add the POS PHY level 2 and 3 library a On the Assignments menu click Settings b Under Category click Libraries c In Project library name click d Browse to phy 1213Mib and click Open e Click Add f Click OK November 2009 Altera Corporation POS PHY Level 2 and 3 Compiler User Guide 2 14 Chapter 2 Getting Started Simulate the Design 3 Add the following files to the project from the Nposphy 12 13Mib directory m auk pac gen if vhd m auk pac functions vhd m auk pac components vhd The files must be in the order shown from top to bottom which is the order of compilation Use the Up and Down buttons in the New Project Wizard Add Files window to order the files 4 Check that the absolute path to your third party simulation tool is set Set the path from EDA Tool Options in the Options dialog box Tools menu 5 On the Processing menu point to Start an
82. the FIFO buffer reaches full threshold Figure 3 13 shows the behavior of the dav signal FIFO buffer remote burst is not applicable Figure 3 13 Behavior of the dav Signal Atlantic Slave Sink 1 dav v Full Burst threshold threshold For the Atlantic slave source the dav signal is an output When dav is high there is data to send When the FIFO buffer is above the empty threshold dav is high When the FIFO buffer is filling dav remains low until the FIFO buffer reaches empty threshold When the FIFO buffer is emptying dav remains high until the FIFO buffer reaches burst threshold Figure 3 14 shows the behavior of the dav signal FIFO buffer remote burst is not applicable Figure 3 14 Behavior of the dav Signal Atlantic Slave Source 1 dav v Burst Empty threshold threshold POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 15 Parameters FIFO Buffer Size The FIFO buffer size is automatically set to be as wide as the widest of the input and the output port Each word in the FIFO buffer can only contain at most one packet Where the FIFO buffer width is N bytes packets of 1 to N bytes in length occupy 1 FIFO buffer word So a FIFO buffer of M words x N bytes can only hold M packets with a length of 1 to N bytes Address amp Packet Available Settings Ls The Atlantic interface always operates i
83. ting in polled mode Set FIFO buffer burst lt FIFO When operating in polled mode this is tms ie indicated using the PIPA Guiferthirashald indicated using the PTPA and STPA and STPA inputs When operating i inputs in direct status mode this is Not applicable in SPHY E indicated using the DTPA inputs Mode When operating in direct status mode this is indicated using the DTPA inputs Link The interface indicates by This should be set to the Receive asserting low the RENB output minimum value allowed Sink that it is not full when it has more than or equal to FIFO buffer threshold spaces for bytes in all of its FIFO buffers 1 FIFO buffer per channel The interface indicates by deasserting high the RENB output that it is full when it has no more spaces for bytes in any of its FIFO buffers 1 FIFO buffer per channel POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description Parameters 3 11 Table 3 3 POS PHY Level 3 FIFO Buffer Settings Part 2 of 2 Interface Direction FIFO Threshold FIFO Burst FIFO Remote Burst PHY When there is more than or equal When there is less than FIFO Transmit to FIFO buffer threshold spaces for buffer burst spaces for bytes Sink bytes in any of its FIFO buffers 1 in any of its FIFO buffers 1 FIFO buffer per channel the FIFO buffer per channel the interface indicates this on a per
84. unctional Specification Figure 3 17 shows the following two Atlantic interface control options and all four interface types m Master source to slave sink POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 3 Functional Description 3 27 Interface Signals m Master sink to slave source The data flow on the Atlantic interface can be in either direction Figure 3 17 Atlantic Interface Control Options dat dat te par par IL Bs sop S A 6 eop eop __ Atlantic Interface Atlantic Interface lt 4 Atlantic Interface Atlantic Interface Master mty Slave Master mty Slave Source L M Sink Sink a Source ena ena val K dav dav f Note to Figure 3 17 1 Buses are unidirectional only A slave sink responds to write commands from the master source and behaves like a synchronous FIFO buffer A master sink generates read commands to a slave source when it requires data and behaves like a synchronous FIFO buffer controller Table 3 13 shows the Atlantic data interface signal definitions Table 3 13 Atlantic Interface Data Signals Part 1 of 2 Signal Description dat 63 0 Data bus dat carries the packet octets that are transferred across the interface Data is transmitted in dat 31 0
85. ware 6 Purchase a license for the POS PHY Level 2 and 3 Compiler After you have purchased a license for the POS PHY Level 2 and 3 compiler the design flow requires these additional steps 1 Setup licensing 2 Generate a programming file for the Altera device s on your board 3 Program the Altera device s with the completed design 4 Perform design verification POS PHY Level 2 amp 3 Walkthrough This walkthrough explains how to create a POS PHY Level 2 or 3 MegaCore function using the Altera POS PHY Level 2 and 3 Compiler IP Toolbench and the Quartus II software When you finish generating a POS PHY Level 2 or 3 MegaCore function you can incorporate it into your overall project IP Toolbench only allows you to select legal combinations of parameters and warns you of any invalid configurations This walkthrough involves the following steps m Create a New Quartus II Project m LaunchIP Toolbench m Step 1 Parameterize m Step 2 Set Up Simulation m Step 3 Generate Create a New Quartus Il Project You need to create a new Quartus II project with the New Project Wizard which specifies the working directory for the project assigns the project name and designates the name of the top level design entity To create a new project follow these steps POS PHY Level 2 and 3 Compiler User Guide November 2009 Altera Corporation Chapter 2 Getting Started 2 3 POS PHY Level 2 amp 3 Walkthrough 1 Choose Progra

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