ALTDQ and ALTDQS Megafunctions User Guide
Contents
1. E e 8 5 2 8 5 2 Option Description 2 e 8 6 gt lt e 5 x S a e 8 a What effect should the dqs_areset Use the dqs_areset port to asynchronously Yes Yes Yes Yes port have on output enable registers Preset or Clear the output enable registers If set to None the port is not instantiated and you have the option to specify the power up state of output enable registers What effect should the dqs_sreset port Use the qs areset port to synchronously Yes Yes Yes Yes have on output enable registers 7 Preset or Clear output enable registers If set to None the dgs_areset port is not instantiated 2 How should the output enable registers If None is selected for the What effect should the Yes Yes Yes Yes power up 7 dgs areset port have on output enable registers option use this option to specify power up condition of output enable registers Hold output drive at high impedance for Delays DQS write mode by half a clock cycle The Yes Yes Yes Yes an extra half clock cycle when output DQS transitions from Z to 0 providing a cleaner enable goes high start to sequence than a Z to 1 transition Use clock enable for the output enable Creates the outclkena port if not Yes Yes Yes Yes Notes to Table 5 1 Cyclone 11 devices do not support this feature Option is disabled when Cyclone II device family is selected 2 This option i2. Notes to Table 16 1 Available for Stratix II devices only 2 Available for Cyclone 11 devices only Table 17 ALTDQS Megafunction Output Ports Port Name dginclk Yes Required Description Phase shifted bos strobe generated for input registers from the Dos input Width of bus is equal to number of DQS pins The size of the output port is dependent on the NUMBER OF parameter dll delayctrlout No Delay buffer setting output If omitted the default value is GND The width of the output port is 6 bit wide 1 dll upndnout No Output for DLL phase comparator 1 dqddioinclk No Clocks generated for DQ negative edge input registers from DQSn pins The width of the bus is equal to the number of DQS pins The size of the output port is dependent on the NUMBER OF Dos parameter 1 dqsundelayedout No Non delayed outputs from the DQS pins Width of bus is equal to number of pos pins The size of the output port is dependent on the NUMBER OF parameter Note to Table 17 1 Available for Stratix II devices only Table 18 ALTDQS Megafunction Bidirectional Ports dgs Port Name Required Description Bidirectional DQS pins Width of bus is equal to number of DQS pins The size of the bidirectional port is dependent on the NUMBER OF DOS parameter dqsn padio Bidirectional DQSn pins Width of bus is equal to number of DQSn pins The size of
3. ALTDQ and ALTDQS ANU S RYA Megafunctions User Guide November 2009 UG MF9304 3 1 Introduction The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units such as adders and counters to advanced phase locked loop PLL blocks multipliers and memory structures These megafunctions are performance optimized for Altera devices and therefore provide more efficient logic synthesis and device implementation because they automate the coding process and save valuable design time You should use these functions during design implementation so you can consistently meet your design goals General Description This user guide discusses the following topics m General features of the ALTDQ and ALTDQS megafunctions m Parameterization of the ALTDQ and ALTDOS megafunctions through the MegaWizard Plug In Manager m Port and parameter definitions of the ALTDQ and ALTDQS megafunctions The ALTDQ and ALTDQS megafunctions allow you to control the functionality of the DDRI O pins for each of the device families Most of the features of the megafunction map directly into features of the I O element IOE for each device family For Cyclone II devices that do not have DDR I O registers in the IOE the features are implemented in logic cells The ALTDQ and ALTDQS megafunctions are provided in the Quartus II software MegaWizard Plug In Manager You can configure the DQ and DOS pins as input output or b
4. the bidirectional port is dependent on the NUMBER OF pos parameter 7 Note to Table 18 1 Available for Stratix II devices only ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Ports and Parameters Page 25 Table 19 ALTDQS Megafunction Parameters Part 1 of 3 Parameter DLL PHASE SHIFT Type String Required Ye e Description Specifies DLL phase shift The values are 0 72 or 90 DQS OE ASYNC RESET String No Specifies whether the dqgs_areset port clears presets or has no effect on the oe register The values are CLEAR PRESET Or NONE DOS OE ASYNC RESET parameter is specified to CLEAR PRESET dqs areset port is required If omitted the default value is NONE DQS OE POWER UP DQS OE REGISTER MODE String String No No Specifies power up condition of the oe registers The values are HIGH or LOW If omitted the default value is LOW Specifies whether the oe port is registered The values are REGISTER Or NONE If omitted the default value is NONE DQS OE SYNC RESET String No Specifies whether the dqs_sreset port clears presets or has no effect on the oe register The values are CLEAR PRESET Or NONE 08 OE SYNC RESET parameter is specified to CLEAR PRESET the 4 sreset port is required If omitted the default value is NONE DQS OPEN DRAIN OUTPUT String No Specifies whether to use o
5. Ifthe 005 LATCHES ENABLE parameter is set to TRUE the 005 USE DEDICATED DELAYCTRLIN parameter cannot be set to FALSE 1 GATED DQS String No Specifies whether to AND DQS output with a register clocked by delayed pos signal The values are TRUE Or FALSE If omitted default is FALSE The GATED 05 parameter can only be used when the DOSN MODE parameter is set to NONE Or OUTPUT 2 DELAY CHAIN MODE String No Specifies delay chain mode 7 There are two modes m DLL Feedback Loop Counter used to control the DQS nDQS delay chains m No DLL used DQS DELAY CHAIN Integer No Specifies value of delay chain The legal values range from o SETTING through 63 The 05 DELAY CHAIN SETTING parameter is ignored ifthe HAS DOS DELAY REQUIREMENT parameter is specified to TRUE 3 DQS DELAY REQUIREMENT String No Specifies delay requirement value This parameter is available only ifthe HAS 005 DELAY REQUIREMENT parameter is specified to TRUE HAS DQS DELAY String No Specifies whether to use a delay requirement The values are REQUIREMENT TRUE Or FALSE If omitted the default value is FALSE LPM HINT String No Allows you to specify Altera specific parameters in VHDL Design Files vhd Default is UNUSED LPM TYPE String No Identifies library of parameterized modules LPM entity name in VHDL Design Files INTENDED DEVICE _ String No This parameter is used for modeling and behavioral simulation FAMILY pu
6. Table 7 1 For more information refer to Table 3 on page 7 2 For more information about utilizing the offset refer to A 550 Using the DLL Phase Offset Feature in Stratix and HardCopy Il Devices Page 9 of the MegaWizard Plug In Manager is the EDA page This page lists the simulation model files needed to simulate the generated design files On this page you can enable the Quartus II software to generate a synthesis area and timing estimation netlist for this megafunction for use by third party tools Page 10 of the MegaWizard Plug In Manager is the Summary page On this final page the wizard displays a list of the types of files to be generated The automatically generated Variation file contains wrapper code in the language you specified on page 2a On this page you can specify additional types of files to be generated Choose from the AHDL Include file function name gt inc VHDL component declaration file ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Page 13 lt function name gt cmp Quartus II symbol file lt function name gt bsf Instantiation template file lt function name gt v and Verilog HDL black box file lt function name gt _bb v If you select Generate Netlist on the Simulation Model page the file for that netlist is also available A gray checkmark indicates a file that is automatically generated and a red checkmark indicates generation of
7. Yes Data input port for DQS output register which outputs on falling edge of outclk signal The size of the input port is dependent on the NUMBER OF parameter dqs sreset No Synchronous set or reset signal for DQS output and output enable registers inclk Yes System reference clock port that drives DLL oe No Output enable for DQS output registers When enabled the oe port defaults to outclk Yes Clock to DQS output and output enable registers ALTDQ and ALTDQS Megafunctions User Guide Page 24 Table 16 ALTDQS Megafunction Input Ports Ports and Parameters Port Name Required Description outclkena No Clock enable port for 005 output and oe registers The oe port defaults to Vec when enabled dll addnsub No Bus for DLL delay setting offset that adds or subtracts If omitted value is GND 1 dll upndnin No Data input for DLL delay setting offset If omitted value is GND 1 dll offset No Data input for DLL delay setting offset The width of the input port is 6 bit wide If omitted value is GND 1 delayctrlin No Control input to DQS delay buffers The width of the input port is 6 bit wide If omitted value is GND 1 dll upndninclkena No Clock enable for DLL delay setting offset If omitted value is GND 1 enable dqs No Specifies whether DQS is disabled during post amble read The enable portis only available if the GATED parameter is specified to TRUE 2
8. an optional file MegaWizard Plug In Manager Page Option and Description ALTDQ Megafunction Table 8 defines the parameterization options that are available for the ALTDQ megafunction Table 8 MegaWizard Plug In Manager Page Option and Description Page Options Descriptions Which action do you want to perform You can select from the following options Create a new custom 1 megafunction variation Edit an existing custom megafunction variation or Copy an existing custom megafunction variation Select a megafunction from the list Select ALTDQ from the 1 0 category below Which device family will you be Specify the device family you want to use using a Which type of output file do you want You can choose from AHDL tdf VHDL vhd or Verilog HDL to create v as the output file type What name do you want for the output Specify the file name without the file extension file November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 14 Getting Started Page 3 of the ALTDQ MegaWizard interface is the Parameter Settings page Table 9 on page 14 describes options available on page 3 of the ALTDQ megafunction Table 9 Parameter Settings Part 1 of 2 Option Currently selected device family How many DQ pins would you like Description Specifies the Altera device family you are using Specifies the width of the data buses If you are using
9. estimation This page normally lists the simulation libraries required for functional simulation by third party tools However the ALTDQS megafunction does not have simulation model files and cannot be simulated ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Design Example Implement DDR 1 0 Interface Page 17 Page 5 of the MegaWizard Plug In Manager allows you to specify the generated file types The Variation file contains wrapper code in the HDL you specified on page 2a You can optionally generate Pin Planner ports PPF file ppf AHDL Include file function name inc VHDL component declaration file function name gt cmp Quartus II symbol file function name gt bsf Instantiation template file function name v and Verilog HDL black box file function name syn v is also available A gray check marks indicate files that are always generated the other files are optional and are generated only if selected indicated by a red check mark Turn on the boxes to select the files that you want the wizard to generate Perform these steps to continue creating an ALTDQ megafunction 1 Turn on the Instantiation template file and Verilog Black Box declaration file options 2 Turn off the AHDL Include file VHDL Component declaration file and Quartus symbol file options 3 Click Finish The ALTDQ module is generated The next section shows you how to create an ALTDOS mega
10. mode is enabled the phase comparator also issues a clock enable signal to the up down counter notifying the counter when to update the DQS settings In low jitter mode the enable signal is only active when the upndn signal is incremented or decremented by 4 otherwise the clock enable is off and the DQS delay settings do not get updated This enable signal is always active if the DLL is in fast lock mode 2 Stratix II devices do not support this feature and the option is disabled in the MegaWizard Plug In Manager for these devices ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Page 9 Page 5 of the ALTDQS MegaWizard interface is the Output Registers page Table 4 on page 9 describes options available on page 5 of the ALTDQS megafunction Table 4 Output Register Settings Supported Devices Option Description Cyclone Il Cyclone Ill Cyclone IV GX Stratix Stratix GX Stratix II Stratix II GX Arria GX HardCopy Il e What effect should the dqs_areset port Use the qs areset port asynchronously Yes Yes Yes Ye have on output registers preset or clear output registers If you select the None option the signal is not instantiated and you can specify the power up state of the output registers What effect should the dqs sreset port Use the dqs sreset port synchronously Yes Yes Yes Yes have on output registers 7 preset or clear outp
11. of data is captured on a falling edge clock NUMBER OF DQ Integer Yes Specifies the number of DQ pins OE REG String No Specifies whether to register the oe port The values are REGISTERED UNREGISTERED POWER UP HIGH String No Specifies the power up condition of the 1 0 registers The values are ON or OFF If omitted the default value is OFF LPM HINT String No Allows you to specify Altera specific parameters in VHDL Design Files whd The default is UNUSED LPM TYPE String No Identifies the library of parameterized modules LPM entity name in VHDL Design Files INTENDED DEVICE FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the ALTDQ megafunction with the MegaWizard Plug in Manager to calculate the value for this parameter Table 16 shows the input ports Table 17 shows the output ports Table 18 shows the bidirectional ports and Table 19 shows the parameters for the ALTDOS megafunction Table 16 ALTDQS Megafunction Input Ports November 2009 Altera Corporation Port Name Required Description dqs areset No Asynchronous set or reset signal for DQS output and output enable registers dqs datain h Yes Data input port for DQS output register which outputs on rising edge of outclk signal The size of the input port is dependent on the NUMBER OF parameter dqs datain 1
12. of the ALTDQS MegaWizard Plug In Manager is the DOS nDOS Delay Chain page Table 7 on page 12 describes options available on page 8 of the ALTDQS megafunction Table 7 DQS nDQS Delay Chain Port Settings Device Supported 4 E e e cs 2 5 e e n 5 z 8 gt lt 2 5 Option Description o a gt lt 5 8 s 2 Sx 5 a S 25 E 8 Offset options for DOS nDQS Allows tuning of the 005 delay chain Depending on No No No Yes delay chain settings from wizard page 4 the offset applies either a coarse or fine delay 7 When a static delay is added the value of delay is equivalent to offset value multiplied by coarse or fine offset buffer delay If a dynamic delay is selected a dll offset port is added to the megafunction The unsigned integer values on d11 offset port may then be added subtracted or dynamically controlled with a dll addsub port by selecting one of the options For static offset the value is added to the DLL feedback counter and output on the 411 delayctrlout output bus The legal integer values are 63 to 63 Enable the latches for the DOS These latches ensure that the offset value is not changed No No No Yes delay chain setting 2 while the DQS transitions and also determines whether the DQS delay buffer control signals are latched or not Create reset for the DLL If enabled a reset input is added to clear the DLL No No No Yes Note to
13. options depend upon the DQS frequency you entered 1 For the respective modes refer to the respective device datasheet No No Yes Yes What is the delay buffer mode What is the DLL delay chain length Only available in custom frequency mode Delay buffers can be set for High or Low delay modes Option only available in custom frequency mode A delay chain length of 10 12 or 16 buffers may be implemented No No Yes No No Yes Yes Yes How much phase shifting would you like to use for the 005 clock Allow DQS to be disabled during read post amble Select phase shift with pull down options of 0 72 or 90 The values calculated from previously specified delay buffer mode and DLL delay chain setting Inhibits the ddioinc1k signal during read postamble when DQS transitions from 0 to Z This stops the ddioincilk signal from creating false clocks as the DQS goes into a tri state The device architecture cannot implement this option on the DQSn port Therefore if you select this option the DQSn port may only be used as an output or left used The ddioinclk signal is inhibited by a register clocked by the DLL delayed DQS The das aresetanddqs sreset signals control this register You must set the dqgs_sreset signal to Vec due to architectural constraints and control the ddioinc1k signal using dqs areset signal No No Yes No No Yes Yes Yes November 2009 Alte
14. the I O elements of the data strobe DOS in supported Altera devices You typically use the ALTDOS megafunction used with the ALTDQ megafunction which provides the following features m A group of DOS pins used to strobe the read and write data in external DDR memory interfaces using a common DLL to phase shift the read strobe m Implementing one DLL and a number of user specified DOS pins the maximum number of DQS supported by a DLL is also dependent on the device side m Clocks generated for the DQ negative edge input registers from the DQSn pins that is the dqddioinclk signal available for Stratix II devices only m Delay buffer setting output option m Frequency settings of DOS inputs and system reference clock Active high asynchronous clear and clock enable control inputs m Registered or unregistered output enable input m DOSoutputs configurable as open drain mode m Speed setting of the DOS and delay buffers as either low or high available for Stratix II devices only ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Page 3 Common Applications The ALTDQ and ALTDOS megafunctions implement proprietary interfaces and variations of the external memories that require features not supported by the Altera SDRAM controller and external memory interfaces Ka You should use the clear text data path generated by the DDR SDRAM Controller to implement all DDR SDRAM DDR2 SDRAM RL
15. Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are NSAI advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services LS EN ISO 9001
16. DRAM II and QDRII systems This data path has been validated by Altera and you can generate this data path for many variations of these interfaces To use the clear text data path you need not purchase or instantiate the Altera DDR SDRAM controller IP For more information refer to the DDR amp DDR2 SDRAM Controller Compiler User Guide RLDRAM II Controller MegaCore Function User Guide and QDRII SRAM Controller MegaCore Function User Guide Resource Utilization and Performance For details about the resource utilization and performance of ALTDO and ALTDOS megafunctions refer to the MegaWizard Plug In Manager and the compilation reports for each device in the Quartus II software Getting Started a The instructions in this section require the Quartus II software version 9 1 or later For operating system support information refer to the Operation System Support page on the Altera website MegaWizard Plug In Manager Page Option and Description for ALTDQS Megafunction Table 1 defines the parameterization options that are available in the MegaWizard Plug In Manager for the ALTDOS megafunction Table 1 MegaWizard Plug In Manager Page Option and Description Page Option Description Which action do you want to You can select from the following options Create a new custom 1 perform megafunction variation Edit an existing custom megafunction variation or Copy an existing custom megafunction variation Select a m
17. _dqs_DesignExample zip to any working directory 2 In the Quartus II software open the dq_dqs_ex qar project On the Tools menu click MegaWizard Plug In Manager Table 10 shows the MegaWizard Plug In Manager page options and description you should select to create the example ALTDQS megafunction Table 10 Parameter Settings for ALTDQ Megafunction Create an output enable port Page Option Description 1 Which action do you want to perform Select Create a new custom megafunction variation Select a megafunction from the list Select ALTDQ from the 1 0 category below Which device family will you be Select Cyclone Il T using Which type of output file do you want Select Verilog HDL to create What name do you want for the output Browse to the folder dq_dqs_ex_1 0_restored Name the file dq file If asked if it is okay to overwrite an existing file click OK How many DQ pins would you like Select 8 Which asynchronous reset port would Select Asynchronous clear aclr you like Create a clock enable port for each Turn off option clock port 3 Turn on option Register output enable Turn off option Delay switch on by a half clock cycle Turn off option Invert input clock Turn off option Use ddioinclk port from DQSn bus Turn off option Page 4 of the MegaWizard Plug In Manager allows you to specify options for stimulation and timing and resource
18. ces chapter in volume 2 of the Arria GX Device Handbook 4 Formore information about the clock delay control block refer to the Clock Delay Control section of the External Memory Interfaces in Cyclone Devices chapter in volume 1 of the Cyclone II Device Handbook 5 For Cyclone 111 Cyclone 111 GX and Cyclone III LS devices you must use the Input Delay from Dual Purpose Clock Pin assignment in the Assignment Editor to set DQS clock delay 6 For more information about the DQS postamble circuitry refer to the DQS Postamble section of the External Memory Interfaces in Cyclone 1 Devices chapter in volume 1 of the Cyclone Device Handbook Page 4 of the ALTDOS MegaWizard interface is the General 2 page Table 3 on page 7 describes options available on page 4 of the ALTDOS megafunction ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Table 3 General 2 Settings Part 1 of 2 Page 7 Option What is the frequency of the DOS inputs s Description The input clock frequency for the 1 or outclk signals For the supported frequencies refer to the External Memory chapter in the respective device handbook Supported Devices Cyclone Il Cyclone Ill Cyclone IV GX Stratix Stratix GX No No Yes Stratix Il Stratix II GX Arria GX HardCopy Il Y e What is the frequency mode Controls internal set up of delay chains Available
19. cycles SIM VALID LOCK Integer No Specifies number of half cycles required before the DLL locks onto signal The default value is 1 TIE OFF DOS OUTPUT CLOCK ENABLE String No Specifies whether clock enable for output registers is tied off does not affect the output registers The values are TRUE or FALSE If omitted the default value is FALSE TIE OFF DOS OE CLOCK ENABLE String No Specifies whether clock enable for oe registers that are controlled by the outclkena port should be tied off The values are TRUE Or FALSE If omitted the default value is FALSE November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 26 Ports and Parameters Table 19 ALTDQS Megafunction Parameters Part 2 of 3 Parameter DELAY BUFFER_MODE Type String No Required Description Specifies speed of DLL and DQS delay buffers The values are LOW Or HIGH If omitted the default value is Low 7 DLL DELAY CHAIN LENGTH Integer No Specifies number of delay buffers used in DLL loop The values are 0 1 2 3 or 4 If omitted the default value is 3 7 DLL DELAYCTRL MODE DLL JITTER REDUCTION String String No No Specifies delay control mode used to feed DQS and DQSn delay buffers The values are NORMAL NORMAL OFFSET OFFSET ONLY Or NONE If omitted the default value is NORMAL 1 Enables or disables jitter r
20. d default is TRUE If the DLL DELAYCTRL MODE parameter is set to NONE the CTRL LATCHES ENABLE parameter cannot be set to TRUE 1 DOS DELAY CHAIN LENGTH Integer No Specifies number of delay buffers used in DQS delay chain The values are o 1 2 3 or 4 If omitted the default value is 3 7 DQS EDGE DETECT ENABLE String No Specifies whether edge detection prevents updates to DQS delay buffer control latches during a DQS transition The values are TRUE Or FALSE If omitted default is FALSE If 05 CTRL LATCHES ENABLE parameter is set to FALSE DQS EDGE DETECT ENABLE parameter cannot be set to TRUE 1 ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Ports and Parameters Page 27 Table 19 ALTDQS Megafunction Parameters Part 3 of 3 cs Parameter Type E Description DQS USE DEDICATED String No Specifies whether the DLL directly feeds the 005 delay buffer DELAYCTRLIN control signals The values are TRUE Or FALSE If omitted default is FALSE If the DLL DELAYCTRL MODE parameter is set to NONE the 008 USE DEDICATED DELAYCTRLIN parameter cannot be set to TRUE If the 05 CTRL LATCHES ENABLE parameter is set to TRUE the DQS USE DEDICATED DELAYCTRLIN parameter cannot be set to FALSE 1 DQSN MODE String No Specifies whether to use the dqsb_padio port The values are NONE INPUT OUTPUT Or BIDIR lf omitted default is NONE
21. e the MegaWizard Plug In Manager interface Table 12 shows the input ports Table 13 shows the output ports Table 14 shows the bidirectional ports and Table 15 shows the parameters for the ALTDQ megafunction Table 12 ALTDQ Megafunction Input Ports Port Name Required Description aclr No Asynchronous clear input If the aclr port is connected the aset port cannot be used aset No Asynchronous set input If the aset port is connected the aclr port cannot be used datain hl Yes Data to be output to the padio port at the rising edge of the out c1k signal The size of the port is dependent on the NUMBER OF parameter datain 1 Yes Data to be output to the padio port at the falling edge of the outc1lk signal The size of the port is dependent on the NUMBER OF DQ parameter ddioinclk No Clock input for the negative edge input register If omitted the default is GND 1 inclock Yes Clock input that drives the data strobe inclocken No Clock enable for the inclock port oe No Output enable signal The oe port defaults to Veg when enabled outclock Yes Clock signal for the output and oe registers outclocken No Clock enable signal for each clock port Note to Table 12 1 Available for Stratix II devices only Table 13 ALTDQ Megafunction Output Ports Port Name Required Description dataout Yes Data output from the input ports at the rising edge of the si
22. eduction on the dll delayctrlout output ports The values are TRUE Or FALSE If omitted the default value is TRUE 7 DLL OFFSETCTRL MODE String No Specifies DLL phase offset mode used with DQS delay buffer control The values are DYNAMIC ADD DYNAMIC SUB DYNAMIC ADDNSUB STATIC Or NONE lf omitted the default value is NONE 1 DLL STATIC OFFSET Integer No Adds a value to the DLL feedback counter and output on the dll delayctrlout output bus The legal integer values are 63 to 63 If omitted default is o If the DLL OFFSETCTRL MODE parameter is set to a value other than sTATIC the DLL STATIC OFFSET parameter is ignored 1 DLL USE UPNDNIN DLL USE UPNDNINCLKENA String String No No Specifies whether to use the 411 upndnin port to update the DLL counter The values are TRUE Or FALSE If omitted default value is FALSE lf the DU USE UPNDNIN parameter is set to TRUE DLL JITTER REDUCTION parameter must be set to FALSE 1 Specifies whether to use the 4111 upndninclkena portas a clock enable for DLL counter The values TRUE FALSE lf omitted the default value is FALSE If the DLL USE UPNDNINCLKENA parameter is set to TRUE the DLL USE UPNDNINCLKENA parameter overrides DLL control of the clock enable for DLL counter 1 DQS CTRL LATCHES ENABLE String No Enables or disables latches for DQS delay buffer control signals The values are TRUE Or FALSE If omitte
23. egafunction from the list Select ALTDQS from the 1 0 category below Which device family will you be Specify the device family you want to use using a Which type of output file do you want You can choose from AHDL tdf VHDL vhd or Verilog HDL to create as the output file type What name do you want for the Specify the file name without the file extension output file November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 4 Getting Started Page 3 of the ALTDQS MegaWizard interface is the General page Table 2 on page 4 describes options available on page 3 of the ALTDQS megafunction Table 2 General Settings Part 1 of 3 Supported Devices option to register the output enable port with the outclk signal S S lt z E 5 5 gt Option Description 2 9 9 e gt lt 5 g 2 a e T T a Currently selected device family Displays the currently selected device family Yes Yes Yes Yes What is the frequency ofthe 005 This is the input 005 frequency 7 Yes Yes No No input s How many DOS pins would you Specifies the number of DQS pins that are Yes Yes Yes Yes like implemented or the number of DQS DQSn pairs generated The maximum number of pins possible depends on the chosen device and the dqsn padio port option 2 Create an output enable for the This enables the DQS output
24. function Table 11 shows the MegaWizard Plug In Manager page options and description you should select to create the example ALTDQS megafunction Table 11 Parameter Settings for ALTDQS Megafunction Page Option Description 1 Which action do you want to perform Select Create a new custom megafunction variation Select a megafunction from the list below Select ALTDQS from the 1 0 category Which device family will you be using Select Cyclone Il 2a Which type of output file do you want to create Select Verilog HDL What name do you want for the output file Browse to the folder dq 145 ex 1 0 restored Name the file dqs If asked if it is okay to overwrite an existing file click OK 3 How many DOS pins would you like Select 1 What is the frequency of the 005 input s Select 133 333 MHz Create an output enable port Turn on option 4 Register the output enable Turn off option How should the delay chain be specified Select As delay chain setting and select 50 Allow DQS to be disabled during read post amble Turn off option Invert dqs_padio port when driving output Turn off option 5 What effect should the dqs_areset port have on Select Clear output registers 6 How do you want to use the dqsn_padio port Select Not Used Page 7 of the MegaWizard Plug In Manager lists the simulation model file needed to properly simulate the generated design files No further input is needed Perf
25. gnal The size of the output port is dependent on the NUMBER parameter dataout Yes Data output from the input ports at the falling edge of the signal The size of the output port is dependent on the NUMBER OF parameter Tahle 14 ALTDQ Megafunction Bidirectional Ports padio Port Name Required Description Yes Bidirectional double data rate DDR port that should directly feed a bidirectional pin in the top level design The size of the bidirectional port is dependent on the NUMBER OF DQ parameter ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Ports and Parameters Table 15 ALTDQ Megafunction Parameters Page 23 Parameter DDIOINCLK INPUT String Type Required Description No Specifies whether to feed the ddioinclk ports The values DQSB_BUS Of NEGATED _INCLK If omitted the default value is NEGATED INCLK You use the DQSB_BUS value with Stratix devices only EXTEND OE DISABLE String No Specifies whether to use the second oE register The values are TRUE Or FALSE If omitted the default value is FALSE INVERT INPUT CLOCKS String No Specifies whether to invert the input clocks The INVERT INPUT CLOCKS parameter should be used with DDR memory When the input clock is inverted the first bit of data is captured on a rising edge clock when the input clock in not inverted the first bit
26. he parameter is set to TRUE otherwise it defaults to FALSE Yes Yes Yes Yes November 2009 Altera Corporation Design Example Implement DDR 1 0 Interface Page 15 Table 9 Parameter Settings Part 2 of 2 Option Invert Input Clock Supported Devices Description Cyclone Il Cyclone Ill Cyclone IV GX Stratix Stratix GX Stratix II Stratix II GX Arria GX HardCopy Il If enabled the first bit of data is captured on the rising edge of the input clock if not enabled itis Yes Yes Yes Yes captured on the falling edge of the input clock Use ddioinclk port from DOSn bus Creates a ddioinclk port This port clocks the negative edge triggered input capture register of Yes Yes Yes Yes the ALTDQ instance Page 4 of the MegaWizard Plug In Manager is the EDA page This page lists the simulation model files needed to simulate the generated design files On this page you can enable the Quartus IT software to generate a synthesis area and timing estimation netlist for this megafunction for use by third party tools Page 5 of the MegaWizard Plug In Manager is the Summary page On this final page the ALTDQ MegaWizard Plug In Manager displays a list of the types of files to be generated The automatically generated Variation file contains wrapper code in the language you specified on page 2a On this page you can specify additional types of files to be generated C
27. hoose from the AHDL Include file lt function name gt inc VHDL component declaration file lt function name gt cmp Quartus II symbol file lt function name gt bsf Instantiation template file lt function name gt v and Verilog HDL black box file lt function name gt _bb v If you select Generate Netlist on the Simulation Model page the file for that netlist is also available A gray checkmark indicates a file that is automatically generated and a red checkmark indicates generation of an optional file Design Example Implement DDR 1 0 Interface Design Files This design example uses the ALTDQ and ALTDQS megafunction to implement DDR I O interface This example uses the MegaWizard Plug In Manager in the Quartus II software As you go through the wizard each page is described in detail The design files are available in the Examples for ALTDO and ALTDOS Megafunction User Guide page on the Altera website November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 16 Example Design Example Implement DDR 1 0 Interface In this example you perform the following tasks m Create a DDR I O interface using the ALTDQ and ALTDQS megafunctions and the MegaWizard Plug in Manager m Implement the design and assign the EP2C5T144C6 device to the project m Compile and simulate the design Create an ALTDQ Megafunction Perform the following tasks to create an ALTDOS megafunction 1 Unzip the altdq
28. idirectional DDR pins on all the I O banks of the device depending on the specific custom external memory interface requirements Both DO and DOS are bidirectional the same signals are used for both writes and reads A group of DO pins is associated with one DOS pin Use the ALTDQ and ALTDQS megafunctions to configure the DO and DQS paths respectively Device Family Support The ALTDQ and ALTDO DOS megafunctions support the following Altera device families m Arria GX m Cyclone II m Cyclone III m Cyclone IV GX m HardCopy m Stratix m Stratix GX November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 2 Introduction m Stratix II Stratix II GX ALTDQ Megafunction The ALTDQ megafunction allows you to easily configure the DDR I O elements in supported Altera devices for DQ data signal functionality The ALTDQ megafunction is a variation of the ALTDDIO BIDIR megafunction modified to be used with the ALTDOS megafunction The ALTDQ megafunction implements a DDR interface and offers many additional features which include Transmission and reception of data on both edges of the reference clock m ddioinclk clock input for the negative edge input register available for Stratix II devices only m Active high asynchronous clear and clock enable control inputs m Registered or unregistered output enable input ALTDQS Megafunction The ALTDOS megafunction allows you to easily configure
29. n the Quartus II Simulator Figure 2 on page 21 shows the expected simulation results in ModelSim Altera ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation uoneJodjo2 eJelly 6002 JequieAoN 1esp suorounjeDey SOALTY pue parv Figure 2 ModelSim Simulation Results Wire dq datain h Wire dq datain Ut wire dq aclr 4 wie dq inclock Wire areset wire dq outclock E SIG ELTON Wire dgs datain wire oe Wire dqs outclk dq dataout h Wire dq dataout wire das dainclk _dqsundelayedout dq padio L wire dgs 6 be ee ee 1 wa ees See es ae eee w s ae EE ee oe Pee et SP RE eF EMET be sae 0121334015 IE YF Veto PLU UP wu LL u LI COMO ee i 100 n 150 ns 92eji91u 0 1 HA 0 ejduex3 ufiseq 1950 suonounjefay 50017 pue DOLIV 12 Page 22 Ports and Parameters Ports and Parameters This section describes all of the ports and parameters that are available for the ALTDQ and ALTDQS megafunctions The parameter details are only relevant if you bypass the MegaWizard Plug In Manager interface and use the megafunction as a directly parameterized instantiation in your design The details of these parameters are hidden if you us
30. of the Cyclone III Device Handbook 2 For number of DQS DQSn pair pins available in supported devices refer to the External Memory Interfaces in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook External Memory Interfaces in Cyclone Devices chapter in volume 1 of the Cyclone II Device Handbook External Memory Interfaces in Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook External Memory Interfaces in Stratix and Stratix GX Devices chapter in volume 2 of the Stratix Device Handbook or the External Memory Interfaces in Stratix Il and Stratix Il GX Devices chapter in volume 2 of the Stratix Device Handbook 3 The delay locked loop DLL controls the delay chain settings to achieve a compensated delay for PVT For example you can use a DQS read strobe or clock that is edge aligned to its associated read data to clock the data into I O registers if the data is delayed before reaching the register The DLL block computes the necessary delay settings by comparing the period of an input reference clock to the delay through an internal delay chain For more information about DLL refer to the DQS Phase Shift Circuitry section of the External Memory Interfaces in Stratix and Stratix GX Devices chapter in volume 2 of the Stratix Device Handbook External Memory Interfaces in Stratix Il and Stratix Il GX Devices chapter in volume 2 of the Stratix Device Handbook and External Memory Interfaces in Arria GX Devi
31. orm these steps to continue creating an ALTDQS megafunction 1 Turn on the Instantiation template file and Verilog Black Box declaration file options November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 18 Design Example Implement DDR 1 0 Interface 2 Turn off the AHDL Include file VHDL Component declaration file and Quartus symbol file options 3 Click Finish The ALTDQS module is generated Combine ALTDQ and ALTDQS Modules to Create a DDR 1 0 Interface This section describes how to create a new top level Verilog HDL file that combines the ALTDQ and ALTDOS modules 1 With the dqs ex qar project open open the dq dqs ex v file 2 Verify that the DO and DOS functions are correctly connected in the top level dq dqs ex v file refer to Figure 1 on page 19 3 On the Project menu click Add Remove Files in Project The Settings window appears 4 In the Settings window browse to the 4 dqs ex v file in the project folder Click Open then Add to add the file to the project 5 Click OK The top level file is now added to the project You have now created the complete design file shown in Figure 1 on page 19 You can view the block diagram after compiling the project inthe RTL Viewer La The schematic shown in Figure 1 on page 19 is not included in the project file ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation uoneJodjo2 Bally 6002 Jeq
32. path Turn onthis Yes Yes Yes Yes DOS pins option to create an output enable for the DQS pins If you select the no output enable port is used option the daqs padio signal drives out permanently Register the output enable This enables the DQS OE path Turn on this Yes Yes Yes Yes What will control the DOS nDQS delay chains m DLL feedback loop counter controls the DOS nDOS delay chains This is the default option DLL inserts a delay equivalent to requested phase shift at input clock frequency Input clock frequency and phase shift are set on page 4 3 m No DLL is used No DLL and no delay is added between the DQS nDQS and the port Yes Yes Yes Yes Have Always an option uses to choose DLL eitherDLL or no DLL ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Table 2 General Settings Part 2 of 3 Page 5 Supported Devices Z Stops the ddioinclk signal from creating false clocks as the DQS goes to tristate If selected adds an enable dqs input port to stop the ddioinclk signal E e 8 gt 2 gt e 25 Option Description 2 5 e a gt lt 5 S E 2 9 R x s a How should the delay chain be This can be either a setting in ps or a value Yes Yes No No specified from 0 63 This is the user requested delay on 5 the clock delay control block Delay i
33. pen drain mode The values are TRUE Or FALSE If omitted the default value is FALSE DQS OUTPUT ASYNC RESET String No Specifies whether the dqs areset port clears presets or has no effect on the DQS output registers The values are CLEAR PRESET Or NONE If the DOS OUTPUT ASYNC RESET port is specified to CLEAR or PRESET the dqs areset is required If omitted the default value is NONE DQS OUTPUT POWER UP DQS OUTPUT SYNC RESET String String No No Specifies power up condition of DQS output registers The values are HIGH or LOW If omitted the default value is LOW Specifies whether the dqgs_sreset port clears presets or has no effect on DQS output registers The values are CLEAR PRESET Of NONE If DOS OUTPUT SYNC RESET port is specified to CLEAR Of PRESET dqs_sreset is required If omitted the default value is NONE EXTEND OE DISABLE String No Specifies whether to use second oe register The values are TRUE or FALSE When the EXTEND OE DISABLE is Set to TRUE the output drive is held at high impedance for an extra half clock cycle when the oe port goes high INPUT FREQUENCY NUMBER OF DOS String Integer No Yes Specifies frequency of DQS inputs and system reference clock Specifies number of DQS pins that are implemented SIM INVALID LOCK Integer No Specifies number of half cycles that DLL keeps signal locked after a bad clock is detected The default is 32 half
34. ra Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 8 Getting Started Table 3 General 2 Settings Part 2 of 2 Supported Devices E e t 5 215 2X Option Description o e 8 e gt lt e S x e 5 s How many valid half cycles of the Only affects simulation and has no affect on actual No No Yes Yes inclk input should pass before the device operation Use to reduce number of clock DLL simulates a lock cycles for which a simulation must be run before the DLL locks By setting this to 1 the DLL immediately locks and simulation can begin transferring data How many invalid half clock cycles Only affects simulation and has no affect on actual No No Yes Yes of the inclk input should pass device operation Use to reduce number of clock before the DLL simulates a loss of cycles for which a simulation must be run before the lock 2 DLL locks By setting this to 1 the DLL immediately locks and simulation can begin transferring data Notes to Table 3 1 Low high refers to jitter mode The DLL in Stratix Il device DOS phase shift circuitry can operate between 100 and 300 MHz in either fast lock mode or low jitter mode Fast lock mode requires fewer clock cycles to calculate the input clock period but the low jitter mode is more accurate The DQS delay settings the up down counter output are updated every eight clock cycles If the low jitter
35. rposes Create the ALTDQS megafunction with the MegaWizard Plug in Manager to calculate the value for this parameter Notes to Table 19 1 Available for Stratix II devices only 2 Available for Stratix Il and Cyclone Il devices only 3 Available for Cyclone II devices only November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Revision History Revision History The following table shows the revision history for this user guide Document Date Version Changes Made November 2009 3 1 Updated for Quartus II v9 1 m Updated Device Family Support on page 1 m Removed Resource Utilization and Performance section m Removed MegaWizard Plug In Manager figures m Added MegaWizard Plug In Manager Page Option and Description for ALTDQS Megafunction on page 3 MegaWizard Plug In Manager Page Option and Description ALTDQ Megafunction on page 13 August 2009 3 0 Maintainence release July 2008 2 1 m Updated template no other changes August 2006 2 0 m Updated screen shots m Added ModelSim Altera simulation procedure m Minor text edits for the Quartus II software version 6 0 release April 2005 1 1 Minor corrections to tables 2 2 and 2 8 March 2005 1 0 Initial release ANU S RYA 101 Innovation Drive San Jose CA 95134 www altera com Technical Support www altera com support Copyright 2009 Altera Corporation All rights reserved
36. s not available for Stratix II devices if the Allow DQS to be disabled during read post amble option has been selected on a previous page of the MegaWizard Plug In Manager refer to Table 3 on page 7 ALTDQ and ALTDQS Megafunctions User Guide November 2009 Altera Corporation Getting Started Page 11 Page 7 of the ALTDQS MegaWizard interface is the Dsqn_padio Port page Table 6 on page 11 describes options available on page 7 of the ALTDQS megafunction Table 6 DQSn_padio Port Settings Supported Devices E e e 5 2 gt 6 5 2 Option Description o e s 9 a gt lt 2 8 z o e 8 x s a How do you want to use the Use negative DQS pin as an input during read cycles Yes Yes No Yes dgsn padio port and output during write cycles or a bidirectional signal for read and write If the Allow 005 to be disabled during read post amble option has been selected on page 3 only Not used and Output modes options are available If Allow 005 to be disabled during read post amble option selected on page 3 all modes are available What is the phase shift when This is the phase shift amount 0 30 60 90 120 Yes Yes No Yes used in timing analysis assumed during timing analysis This is to compute the static delay during timing analysis November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 12 Getting Started Page 8
37. s specified either by number of delay buffers used or desired time delay Time delay is converted to number of buffers during compilation For the actual buffer delay refer to the respective device data sheet These buffers have a fixed delay which is not dependent on input clock frequency clock delay control circuit on each DQS pin allows a phase shift that center aligns the incoming DQS signals within the data window of their corresponding DQ data signals 4 Allow DQS to be disabled during Inhibits the ddioinclk signal during read Yes Yes No No read post amble postamble when the DQS transitions from 0 to 6 November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 6 Getting Started Table 2 General Settings Part 3 of 3 Supported Devices E e e 5 gt gt g a S 2X Option Description o 9 gt lt el 8 z 2 amp S 2 E s Invert 105 padio port when When you select this option the dqs padio Yes Yes No No driving output port is inverted if driven as an output Notes to Table 2 1 For supported DQS frequencies in these devices refer to the Cyclone DDR Memory Support Overview section of the External Memory Interfaces in Cyclone Devices chapter in volume 1 of the Cyclone II Device Handbook or the Introduction section of the External Memory Interfaces in Cyclone Devices chapter in volume 1
38. t DDR 1 0 Interface Simulate the DDR 1 0 Interface Design in ModelSim Altera Tool You can simulate the design in the ModelSim tool to compare the results of both simulators This user guide assumes that you are familiar with using the ModelSim Altera tool before trying out the design example If you are unfamiliar with this tool refer to the ModelSim Altera Software Support page on the Altera website There are various links to topics such as installation usage and troubleshooting Set up the ModelSim Altera simulator by performing the following steps 1 O o N Unzip the altdq_dqs_msim zip file to any working directory on your PC Browse to the folder in which you unzipped the files and open the altdqdqs do file in a text editor In line 1 of the altdqdqs do file replace insert directory path here with the directory path of the appropriate library files For example C Modeltech ae altera verilog cycloneii On the File menu click Save Start ModelSim Altera On the File menu click Change Directory Select the folder in which you unzipped the files Click OK On the Tools menu click Execute Macro Select the altdqdqs do file and click Open This is a script file for ModelSim that automates all the necessary settings for the simulation 10 Verify the results shown in the Waveform Viewer window You may need to rearrange signals remove redundant signals and change the radix to suit the results i
39. the Quartus software version 6 0 or earlier this megafunction displays output ports as dataout_h and dataout_1 the Quartus software version 6 0 and later displays output ports as dataout and dataout ddio Supported Devices Yes Yes Cyclone Yes Yes Cyclone Ill Cyclone IV GX Stratix Stratix GX Yes Yes Ye n Yes Stratix II Stratix II GX Arria GX HardCopy Il Which asynchronous reset port would you like You can use the asynchronous clear ac1r or the asynchronous preset aset as the asynchronous reset If you do not use either clear option you must specify whether the registers should power up high or low Yes Yes Yes Yes Create a clock enable port for each clock port Create an output enable port Creates an input clock enable port inclken and an output clock Creates an output enable port oe for this instance of the ALTDQ instance Yes Yes Yes Yes Yes Yes Yes Yes Register output enable Sets the REGISTER MODE parameter When enabled a register is placed in the OE path and the parameter is set to register When disabled parameter defaults to NONE Yes Yes Yes Yes Delay switch on by a half clock cycle ALTDQ and ALTDQS Megafunctions User Guide Sets the EXTEND OE DISABLE parameter When enabled the pin does not drive out until the falling edge of the outc1k signal When enabled t
40. uieAoN Jasp suorounjeDey SOGL Ty pue parv Figure 1 DDR 1 0 Interface Using ALTDQ and ALTDQS Megafunctions dqs areset D 0 D idgqs_datain_h 0 0 _ 3 dqs datain IDOE dqs oe D 0 fus dqs outclk O 0 225 dq acl gt 44 outclock dq gt dq datain h 7 0 dq datain I 7 0 5 dqs dqs inst dq dq inst daloutt 2 p dq dataout h 7 0 dq patic o c 5 22 2 Ee dg_dataout_lI 0 dqzundelayedougo o 4 2 0 2 0 gt dq_inclock LA i05 dqinclk O 0 JL eee odas dqsundelayed HT LPS das padio D 0 Implement the DDR 1 0 Interface Design This section describes how to assign the EP2C5T144C6 device to the project and compile the project 1 ND GF F With the dq_dqs_ex qar project open on the Assignments menu click Device The device page of the Settings dialog box appears In the Family list select Cyclone II In the Target device list select Specific device selected in Available devices list In the Available devices list select EP2C5T144C6 Leave the default settings for the other options on the Settings page and click OK On the Processing menu click Start Compilation compile the design When a message indicates that Full compilation was successful click OK 0 1 HA 0 ejduex3 ufiseq apiny Jasp suonounjefay 50017 pue 001717 61 afed Page 20 Design Example Implemen
41. ut registers If you select the None option the port is not instantiated 2 How should the output registers If you selected None for the What effect should Yes Yes Yes Yes power up 1 the dqs_areset port have on output registers option use this option to specify power up condition of output registers Use clock enable for the output register Create the outclkena port if not Yes Yes Yes Yes 3 implemented for the output registers Use as a clock enable for the output registers Notes to Table 4 1 Cyclone 11 devices do not support this feature Option is disabled when Cyclone II device family is selected 2 This option is not available for Stratix Il devices if the Allow DQS to be disabled during read postamble option has been selected on a previous page of the wizard refer to Table 3 on page 7 3 This option is enabled only when Register the output enable option is turned on in page 3 of the MegaWizard Plug In Manager November 2009 Altera Corporation ALTDQ and ALTDQS Megafunctions User Guide Page 10 Getting Started Page 6 of the ALTDQS MegaWizard interface is the Output Enable Registers page Table 5 on page 10 describes options available on page 6 of the ALTDQS megafunction Table 5 Output Enable Registers Settings Supported Devices register implemented for output enable register Use as a clock enable for output enable register
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