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MAX 10 Analog to Digital Converter User Guide

1. altera adc peripheral clock altera adc sequencer altera adc control adc pll dock peripheral reset clock from dedicated PLL CSR S Egan command T SRC adc pll locked locked signal from dedicated PLL response altera adc sample store Avalon ST Splitter Core response CSR 4 gt S SNK J sr SNK IRQ SRC altera_adc_threshold_detect response threshold lt SRC SNK In dual ADC mode you can configure the threshold detection of each ADC instance independently of each other This capability is available because each ADC instance measures different analog metrics Figure 2 10 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection Altera Modular Dual ADC IP Core threshold altera_dual_adc SRC altera adc threshold detect altera adc sequencer altera adc control SNK idc pll clock command Tesponse fi amp adc pli dod peripheral clock SRC SNK SRC response clock from dedicated PLL peripheral reset SRC
2. 8 7 ADCI 1A 6 1B 2 5 Eg 1 0 Bank 3 v ADC Block MAX 10 ADC Architecture and Features Altera Corporation LJ Send Feedback 2 4 Single or Dual ADC Devices Figure 2 4 ADC Block Location in MAX 10 25 40 and 50 Devices Package E144 of these devices have only one ADC block UG M10ADC 2015 06 11 Ld 1 0 Bank 8 7 ADCI ADC2 1A 1B 2 3 4 ADC Block Single or Dual ADC Devices MAX 10 devices are available with single or dual ADC blocks For devices with one ADC block you can use up to 17 ADC channels e These channels include one dedicated analog input and up to 16 dual function pins e You can use the dual function pins as GPIO pins when you do not use the ADC Note MAX 10 devices in the E144 package have only 8 dual function ADC pins For devices with two ADC blocks you can use up to 18 ADC channels For dual ADC devices each ADC block can support one dedicated analog input pin and up to 8 dual function pins e Ifyou use both ADC blocks in dual ADC devices you can use up to two dedicated analog input pins and 16 dual function pins e For simultaneous measurement you can use only dedicated analog input pins in both ADC blocks because the package routing of both dedicated analog pins are matched For dual function pins the routing latenc
3. ADC2 CH9 ANAIN2 CH10 ADC2IN1 CH11 ADC2IN2 CH12 ADC2IN3 CH13 ADC2IN4 CH14 ADC2IN5 CH15 ADC2IN6 CH16 ADC2IN7 CH17 ADC2IN8 Altera Modular ADC and Altera Modular Dual ADC Interface Signals Depending on parameter settings you specify different signals are available for the Altera Modular ADC or Altera Modular Dual ADC IP core Command Interface of Altera Modular ADC and Altera Modular Dual ADC The command interface is an Avalon ST type interface that supports a ready latency of 0 Table 5 10 Command Interface Signals Width Description Bit valid 1 Indication from the source port that current transfer is valid ready 1 Indication from the sink port that it is ready for current transfer channel 5 Indicates the channel that the ADC hard block samples from for current command 31 recalibration request 30 18 not used 17 temperature sensor 16 0 channels 16 to 0 where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins Altera Modular ADC IP Core References C Send Feedback Altera Corporation UG M10ADC 5 12 Response Interface of Altera Modular ADC and Altera Modular Dual ADC 2015 06 11 Width Description Bit startofpacket 1 Indication from the source port that current transfer is the start of packet e Foraltera adc sequencer core implementation the IP core asserts this signal during the first slot
4. devices up to 2 5V Single supply devices up to 3 63 V reference voltage to the ADC Altera Modular ADC IP Core References C Send Feedback Altera Corporation UG M10ADC 5 8 Altera Modular Dual ADC Parameters Settings 2015 06 11 Table 5 7 Altera Modular Dual ADC Parameters Channels This group of parameters is divided into two main tabs for ADC1 and ADC2 For each tab there are several channel tabs one for each channel and one tab for the TSD in ADCI Use Channel 0 or 9 e On Enables the dedicated analog input pin for ADCI or Dedicated analog input Off ADC2 pin ANAIN CHO tab for ADCI or CH9 tab for ADC2 Use Channel N e On Enables the dual function analog input where N is Each channelinitsown Off e Channels 1 to 8 for ADCI tab e Channels 10 to 17 for ADC2 Use on chip TSD e On Specifies that the IP core reads the built in temperature TSD tab in ADCI only Off oe If you turn on this option the ADC sampling rate is up to 50 KHz when it reads the temperature measurement After it completes the temperature reading the ADC sampling rate is up to 1 MHz Note If you select the TSD for a sequencer slot in ADCI select NULL for the same sequencer slot number in ADC2 Enable Maximum e On Enables the maximum threshold feature for the channel cirespold for thann Nie Or This option is available only if you select the Standard Each channel in its own sequencer with
5. clock 1 Single clock that clocks all Altera Modular ADC or Altera Modular Dual ADC micro cores Peripheral Reset Interface of Altera Modular ADC and Altera Modular Dual ADC The peripheral reset interface is a reset sink interface type Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual 5 15 Table 5 16 Peripheral Reset Interface Signals Width Description Bit reset_n 1 Single reset source that that resets all Altera Modular ADC or Altera Modular Dual ADC micro cores ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC The ADC PLL clock interface is a clock sink interface type Table 5 17 ADC PLL Clock Interface Signals Width Description Bit etek 1 ADC hard IP clock source from co output of dedicated PLLI or PLL3 Export this interface from the Qsys system Related Information e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Parameters Settings for Generating ALTPLL IP Core on page 4 3 ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC The ADC PLL locked interface is a conduit end interface type Table 5 18 ADC PLL Locked Interface Signals Width Description Bit Sonde 1 ADC hard IP locked signal output of dedicated PLL1 or PLL3 Export this interface from the Qsys system Related Information e Customizing
6. Guide e June 2015 2015 06 11 Updated the board design guidelines for analog input May 2015 2015 05 04 e Added the Altera Modular Dual ADC IP core e Removed F672 from the 10M25 device and added ADC informa tion for the E144 package of the 10M04 device e Updated the ADC block counts Updated the ADC vertical migration support Updated the ADC channel counts e Updated the table that lists the ADC channel count to list only 8 dual function pins instead of 16 for the M153 and U169 packages e Updated the ADC vertical migration diagram to clarify that there are single ADC devices with eight and 16 dual function pins e Updated the topic about ADC conversion to specify that in prescaler mode the analog input in dual and single supply devices can measure up to 3 0 V and 3 6 V respectively Updated the ADC IP core architecture figures to include features for the dual ADC IP core e Added information and topics about the response merge and dual ADC synchronizer micro cores e Removed notes about contacting Altera for the ADC pin RLC filter design e Updated the ADC prescaler topic to change the ADC2 channel that supports prescaler from channel 16 to channel 17 e Updated the diagram that shows the ADC timing To clarify that the numbers are hexadecimal numbers e Relabeled the signals to match the command and response interface signal names O 2015 Altera Corporation All rights reserved ALTERA
7. ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any a a egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 ANU S RYA UG M10ADC A 2 Document Revision History for MAX 10 Analog to Digital Converter User 2015 06 11 ENEINEBI INE caas December 2014 2014 12 15 Updated the RC constant and filter value and the filter design example figure to clarify the source of the example values Added guidelines for setting up the sequencer in dual ADC mode Added topics that list the mapping of Altera Modular ADC and Altera Modular Dual ADC IP cores chann
8. 0 reference voltage This setting is available only if you select the Standard sequencer with Avalon MM sample storage and threshold violation detection core variant Enter Minimum Threshold for on chip TSD TSD tab Specifies the minimum threshold value in Celsius This setting is available only if you select the Standard sequencer with Avalon MM sample storage and threshold violation detection core variant Enable Prescaler for Channel N Enables the prescaler function where N is Channels 8 and 16 if available for single ADC devices e Channel 8 of ADC1 or ADC2 for dual ADC devices Table 5 3 Altera Modular ADC Parameters Sequencer Number of slot used 1 to 64 Specifies the number of conversion sequence slots to use The Conversion Sequence Channels section displays the slots available according to the number of slots you select here Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name 5 5 Slot N Enabled channel Specifies which enabled ADC channel to use for the slot number CH N in the sequence The selection option lists the ADC channels that you turned on in the Channels parameter group Related Information e Sequencer Core on page 2 17 Configuration 1 Standard Sequencer with Avalon MM Sample Storage on page 2 10 Configuration 2 St
9. Migration Support 1 3 ADC Channel Counts Per Device oi f romos J romos tome J tomas J TN NNNM 1 1 1 1 1 Dedicated 1 E144 Dual 8 8 8 8 8 8 function Dedicated 1 1 2 2 2 F484 Dual 16 16 16 16 16 function Dedicated 2 2 F672 Dual 16 16 function Related Information MAX 10 FPGA Device Overview MAX 10 ADC Vertical Migration Support on page 1 3 MAX 10 ADC Vertical Migration Support Figure 1 1 ADC Vertical Migration Across MAX 10 Devices Preliminary The arrows indicate the ADC migration paths The devices included in each vertical migration path are shaded Package Device M153 U169 U324 F256 E144 F484 F672 10M04 10M08 10M16 10M25 10M40 10M50 Dual ADC Device Each ADC ADC1 and ADC2 supports 1 dedicated analog input pin and 8 dual function pins Single ADC Device Single ADC that supports 1 dedicated analog input pin and 16 dual function pins Single ADC Device Single ADC that supports 1 dedicated analog input pin and 8 dual function pins MAX 10 ADC Overview Altera Corporation CJ Send Feedback UG M10ADC 1 4 MAX 10 Single or Dual Supply Devices 2015 06 11 Table 1 3 Pin Migration Conditions for ADC Migration Single ADC device Single ADC device You can migrate all ADC input pins Dual ADC device Dual ADC device Single ADC device Dual ADC device One dedicated ana
10. Threshold for Enter the minimum threshold voltage for the channel The IP core will Channel N generate a threshold violation notification signal to indicate that the sampled data is below the threshold value that you specify Enter Minimum Threshold for Enter the maximum threshold temperature for the temperature sensor on chip TSD TSD tab in Celsius The IP core will generate a threshold violation notification signal to indicate that the sampled temperature is below the tempera ture that you specify Table 4 4 Parameters Settings in Sequencer Group Number of slot used Select the number of channels to use for conversion The parameter editor displays the number of slots available in the Conversion Sequence Channels based on your selection Slot N For each available slot select the channel to sample in the sequence The available channels depend on the channels that you turned on in the Channels parameters group If you turned on a channel but do not select the channel in any of the sequencer slots the unselected channel is not measured during the ADC sampling sequence The ADC block samples the measurements in the sequence you specify After it reaches the last slot in the sequence it repeats the sampling from the first slot Related Information e Creating MAX 10 ADC Design on page 4 2 e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Completing ADC Design on page 4 7 e Alt
11. device are generating the IP core There are feature differences between the two ADC blocks The temperature sensor is available only in the first ADC block There are also different channel counts in both ADC blocks ADC Input Clock Select the same frequency that you set for the ALTPLL IP core that clocks the Altera Modular ADC IP core Reference Voltage Source Select whether you want to use external or internal reference voltage There is only one vrer pin For dual ADC blocks you can use one external Vpgr source for both ADC blocks or external Vggg for one ADC block and internal Vggg for the other ADC block External Reference Voltage If you use external Vpgp source in your design specify the V pgp level Table 4 3 Parameters Settings in Channels Group You can navigate through the tabs for all the available channels and turn on the channel you want to use In each channel and TSD tab you can specify the settings in this table Use Channel 0 Dedicated This option is available in the CHO tab analog input pin ANAIN CHO is the dedicated analog input channel If you want to use the dedicated analog input turn on this option Use Channel N You can select which dual function ADC channels to turn on or off There are 16 channels CH1 to CH16 for single ADC devices and 8 channels CH1 to CH8 for each ADC block in dual ADC devices Use on chip TSD This option is available in the TSD tab The TSD channel i
12. enabled ADC channel to use for the slot in the sequence The selection option lists the ADC channels that you turned on in the Channels parameter group for ADC1 and ADC2 Note If you select the TSD for a sequencer slot in ADCI select NULL for the same sequencer slot number in ADC2 Related Information e Sequencer Core on page 2 17 Configuration 1 Standard Sequencer with Avalon MM Sample Storage on page 2 10 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection on page 2 11 Configuration 3 Standard Sequencer with External Sample Storage on page 2 13 Configuration 4 ADC Control Core Only on page 2 13 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 5 e Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 10 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Each ADC channel in the Altera Modular Dual ADC IP core corresponds to different device pin name Table 5 9 Altera Modular Dual ADC IP Core Channel to Pin Mapping CHO ANAINI CHI ADCIINI CH2 ADCIIN2 CH3 ADCIIN3 ADCI CH4 ADCIIN4 CH5 ADCIIN5 CH6 ADCIIN6 CH7 ADCIIN7 QH8 ADOHINS Altera Corporation Altera Modular ADC IP Core References G send Feedback UG M10ADC 2015 06 11 Altera Modular ADC and Altera Modular Dual ADC Interface Signals 5 11
13. of conversion sequence data array e Foraltera adc control core implementation this signal is ignored The IP core just passes the received information back to the corresponding response interface PPOO EPA CEEE 1 Indication from the source port that current transfer is the end of packet e For altera_adc_sequencer core implementation IP core asserts this signal during the final slot of conversion sequence data array e Foraltera adc control core implementation this signal is ignored The IP core just passes the received information back to the corresponding response interface Related Information e Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 5 e Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 10 Response Interface of Altera Modular ADC and Altera Modular Dual ADC The response interface is an Avalon ST type interface that does not support backpressure To avoid overflow condition at the source port implement sink ports with response data process time that is fast enough or with enough buffers storage Table 5 11 Response Interface Signals Width Description 5119 valid 1 Indication from the source port that current transfer is valid channel 5 Indicates the ADC channel to which the ADC sampling data corresponds for the current response e 31 18 not used e 17 temperature sensor e 16 0 channels 16 to 0 where c
14. on page 4 2 Completing ADC Design on page 4 7 e MAX 10 Clock Networks and PLLs User Guide e ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC on page 5 15 e ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC on page 5 15 Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core Navigate through the Altera Modular ADC IP core parameter editor and specify the settings required for your design After you have specified all options as listed in the following tables you can generate the HDL files and the optional simulation files Altera recommends that you save the generated files in the design file directory default setting For more information about each Altera Modular ADC or Altera Modular Dual ADC parameter refer to the related information section Table 4 2 Parameter Settings in General Group Core Variant There are four configuration variants of the Altera Modular ADC IP core Select the core variant that meets your requirement For more information refer to the related information Debug Path Turn this on to enable the debug path for the selected core variant Altera Corporation MAX 10 ADC Implementation Guides G send Feedback UG M10ADC 2015 06 11 Parameters Settings for Generating Altera Modular ADC or Altera Modular 4 5 Generate IP for which ADCs of For devices with two ADC blocks select the ADC block for which you this
15. register to configure the intended conversion mode e You can configure the length and content of the conversion sequence data only when generating the IP core e You can access the register of the sequencer core through the Avalon MM slave interface e The command information to the downstream core goes through the Avalon ST interface Sample storage This core stores the ADC samples that are received through the Avalon ST interface e The samples are stored in the on chip RAM You can retrieve the samples through the Avalon MM slave interface e With this core you have the option to generate interrupt when the ADC receives a block of ADC samples one full round of conversion sequence Response merge This core merges simultaneous responses from two ADC control cores into a single response packet to send to the sample storage core This core is available only if you use the Altera Modular Dual ADC IP core in the following configurations e Standard Sequencer with Avalon MM Sample Storage e Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection Dual ADC synchronizer core This core performs synchronization handshakes between two ADC control cores This core is available only if you use the Altera Modular Dual ADC IP core MAX 10 ADC Architecture and Features LJ Send Feedback Altera Corporation UG M10ADC 2 16 ADC Control Core 2015 06 11 Threshold detection e This c
16. slot in ADCI for temperature sensing you must set the same sequencer slot number in ADC2 to NULL Related Information ADC Sequencer on page 2 8 Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC uu mm 2015 06 11 ADC Timing p ADC Timing Figure 2 6 MAX 10 ADC Timing Diagram This figure shows the timing diagram for the command and response interface of the Altera Modular ADC control core The timing diagram shows the latency of the first valid response data and the latency between the first acknowledgment of the first command request and the back to back response data dock E reset n command valid commandd channel 4 0 oo Y 0x10 i o 00 EEG EE command starofpacket command endofpacket command ready i s i response_valid response channel 4 0 0x00 ouof 0x00 Joxo Y response data 11 0 0x000 i e Joxos 0x000 Yoxoo1 response_startofpacket i i response_endofpacket ac 3 ADC soft IP clock 2 us 4 5 E a Y 4 3 ADC soft IP clock 3 us gt The timing diagram shows an example where e The conversion sequence is channel 16 gt channel 1 gt channel 2 e The response data for channel 16
17. temperature sensing mode and vice versa calibration is run automatically for the changed clock frequency The calibration incurs at least six clock calibration cycles from the new sampling rate The ADC TSD measurement uses a 64 samples running average method For example e The first measured temperature value is the average of samples 1 to 64 e The second measured temperature value is the average of samples 2 to 65 e The third measured temperature value is the average of samples 3 to 66 e The subsequent temperature measurements follow the same method For dual ADC devices the temperature sensor is available in ADCI only Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC 2015 06 11 Temperature Measurement Code Conversion Use the temperature measurement code conversion table to convert the values measured by the ADC TSD to actual temperature Temperature Measurement Code Conversion 2 7 Table 2 1 Temperature Code Conversion Table Preliminary 3798 6 3738 3670 3593 6 3510 39 3796 5 3736 29 3667 63 3592 97 3507 38 3795 4 3733 30 3666 64 3591 98 3504 37 3793 3 3732 31 3664 65 3590 99 3501 36 3792 2 3731 32 3662 66 3589 100 3500 35 3790 1 3730 33 3660 67 3585 101 3498 34 3788 0 3727 34 3658 68 3582 102 3496 33 3
18. there is no REFGND plane e Use REFGND as ground reference for the ADC input signal e For prescaler enabled input signal set the ground reference to REFGND Performance degrades if the ground reference of prescaler enabled input signal is set to common ground cup Input Low PassFilter Selection e A low pass RC filter can reduce the trace spacing between analog input signal and digital I O signal to meet 100 dB crosstalk requirement Altera recommends that you place active low pass filter to help in meeting the required settling time e Place the low pass filter as close as possible to the analog input signals The cut off frequency depends on the analog input frequency Altera recommends that the Feutoff 348 is five times the input frequency e You can download the ADC input SPICE model for ADC front end board design simulation from the Altera website Table 3 1 RC Constant and Filter Value This table is an example of the method to quantify the RC constant and identify the RC filter value Total RC Constant Rpriver RgoAnp RpAcKAGE RFILTER X Cpriver Cpoarp CpackacE CrILTER Cpr M neuen Total RC Settling Time Fcutoft 3dB TN Unc ns 4 82 42 34 42 4 5 49 41 48 42 4 Figure 3 2 Passive Low Pass Filter Example ADC Analog Input Board RC Reuter Driver RC AAA 2 Place thiscap T close to the pin an LJ D Altera S Device RE
19. to 3 63 V e Dual supply Specifies the voltage of vccvreF pin if you use it as devices upto _ reference voltage to the ADC Table 5 2 Altera Modular ADC Parameters Channels This group of parameters is divided into several tabs one for each channel and one tab for the TSD Use Channel 0 Dedicated e On Enables the dedicated analog input pin analog input pin e Off ANAIN CHO tab Use Channel N e On Enables the dual function analog input where N is Each channel in its own eu e 1to 16 channels for single ADC devices tab e lto8 channels for dual ADC devices Use on chip TSD e On Specifies that the IP core reads the built in temperature TSD tab Off sensor in the ADC If you turn on this option the ADC sampling rate is up to 50 KHz when it reads the temperature measurement After it completes the temperature reading the ADC sampling rate is up to 1 MHz Enable Maximum e On Enables the maximum threshold feature for the channel threshold for Channel N Off This option is available only if you select the Standard Each channel in its own sequencer with Avalon MM sample storage and tab threshold violation detection core variant Enable Maximum e On Enables the maximum threshold feature for the TSD threshold for on chip Off TSD This option is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core varia
20. 15 06 11 MAX 10 ADC Conversion 5 Figure 1 2 ADC Measurement Display for 2 5 V Output Code Full Scale Transition EM FFF FFE FFD Full scale input 2 5 V Resolution 212 4096 1LSB 2 5V 4096 610 35 V 12 bit Output Code Hex 003 002 001 000 1 1 1 1 1 1 1 1 1 1 1 1 1 d 1 1 1 1 1 1 1 1 1 1 1 1 1 610 354 1220 704 2 4993896 Input Voltage V The MAX 10 ADC is a 1 MHz successive approximation register SAR ADC If you set up the PLL and Altera Modular ADC IP core correctly the ADC operates at 1 MHz during normal sampling and 50 kHz during temperature sensing Note The analog value represented by the all ones code is not full scale but full scale 1 LSB This is a common convention in data conversion notation and applies to ADCs Related Information e Creating MAX 10 ADC Design on page 4 2 Altera Modular ADC Parameters Settings on page 5 1 Altera Modular Dual ADC Parameters Settings on page 5 6 MAX 10 ADC Overview Altera Corporation LJ Send Feedback MAX 10 ADC Architecture and Features 2015 06 11 UG M10ADC CX subscribe LJ Send Feedback In MAX 10 devices the ADC is a 12 bits SAR ADC that provides the following features e Sampling rate of up to 1 MSPS e Up to 18 channels for analog measurement 16 dual function channels and two dedicated analog input channels in dual ADC devices e Single ended measurement capability e Simultaneous measureme
21. 3673 61 3594 95 3513 ADC Sequencer The Altera Modular ADC and Altera Modular Dual ADC IP cores implement the sequencer Use the Altera Modular ADC or Altera Modular Dual ADC parameter editor to define the ADC channel acquisition sequence and generate the HDL code The sequencer can support sequences of up to 64 ADC measurement slots While configuring the Altera Modular ADC or Altera Modular Dual ADC IP core you can select which channel including the TSD channel to sample in each sequencer slot During runtime you cannot change the channel sequence but you can configure the conversion mode using the Nios II HAL driver API You can specify up to 64 slots and assign the channel for each slot You can repeat the same channel number several times if required Related Information Guidelines ADC Sequencer in Altera Modular Dual ADC IP Core on page 2 8 Guidelines ADC Sequencer in Altera Modular Dual ADC IP Core Follow these sequencer guidelines if you use dual ADC blocks with the Altera Modular Dual ADC IP core e The conversion sequence length of both ADC blocks must be the same You can configure independent patterns for the conversion sequence of each ADC blocks e You can set a sequencer slot in ADC2 to NULL If you set the slot to NULL ADC2 will perform a dummy conversion for the slot with output of 0 The NULL option is available only for ADC2 The temperature sensor is available only in ADCI If you configure a sequencer
22. 6 11 Table 5 1 Altera Modular ADC Parameters General Core Variant e Standard Selects the core configuration for the Altera Modular sequencer with ADC IP core Avalon MM sample storage e Standard sequencer with Avalon MM sample storage and threshold violation detection e Standard sequencer with external sample storage e ADC control core only Debug Path e Disabled Enables the debug path e Enabled Generate IP for which e Ist ADC For devices that have two ADC blocks specifies which ADCs of this device 2nd ADC ADC block you want to instantiate using the IP core ADC Input Clock 2 10 20 40 and Specifies the frequency of the PLL clock counter zero 80 MHz co clock supply for the ADC core clock e You must configure the co of the first ALTPLL IP core that you instantiate to output one of the frequen cies in the allowed values list e Connect the ALTPLL co output signal to the Altera Modular ADC clk in pll c0 input signal Reference Voltage Source External Specifies the source of voltage reference for the ADC s ierat e External uses vccvnkr pin as the voltage reference source e Internal uses the on chip 2 5 V 3 0 3 3V on voltage regulated devices as the voltage reference source Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Altera Modular ADC Parameters Settings 5 3 External Reference Voltage 2 5 V e Single supply devices up
23. 786 1 3725 35 3656 69 3579 103 3494 32 3785 2 3721 36 3654 70 3576 104 3492 31 3782 3 3720 37 3651 71 3573 105 3490 30 3781 4 3719 38 3648 72 3570 106 3489 29 3780 5 3717 39 3645 73 3567 107 3486 28 3779 6 3715 40 3643 74 3564 108 3483 27 3777 7 3713 41 3642 75 3561 109 3480 26 3775 8 3711 42 3641 76 3558 110 3477 25 3773 9 3709 43 3640 77 3555 111 3474 24 3771 10 3707 44 3638 78 3552 112 3471 23 3770 11 3704 45 3636 79 3551 113 3468 22 3768 12 3703 46 3634 80 3550 114 3465 21 3766 13 3702 47 3632 81 3549 115 3461 20 3765 14 3700 48 3630 82 3548 116 3460 19 3764 15 3699 49 3628 83 3547 117 3459 18 3762 16 3698 50 3625 84 3546 118 3456 all S752 17 3697 51 3622 85 3542 119 3451 16 3756 18 3696 52 3619 86 3538 120 3450 15 3754 19 3695 53 3616 87 3534 121 3449 14 3752 20 3688 54 3613 88 3530 122 3445 l3 3751 21 3684 55 3610 89 3526 123 3440 12 3750 22 3682 56 3607 90 3525 124 3432 11 3748 23 3680 57 3604 91 3524 125 3431 MAX 10 ADC Architecture and Features J send Feedback Altera Corporation UG M10ADC 2 8 ADC Sequencer 2015 06 11 3746 4 3678 3601 3522 9 3744 25 3677 59 3598 93 3519 8 3742 26 3676 60 3595 94 3516 7 3740 27
24. 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG M10ADC 3 2 Guidelines Board Design for Analog Input 2015 06 11 Figure 3 1 Recommended RC Filter for Power Traces Ferrite Beads dn VCCADC_2P5 Supply 10 pF 0 1 pF Place this cap close to the pin GND Ferrite Beads GND T VCCADC_1P Supply ze 10 pF O 1 MF T Place this cap close to the pin GND GND There is no impedance requirement for the RErcGNp Altera recommends that you use the lowest impedance with the most minimum DC resistance possible Typical resistance is less than 1 Q Altera recommends that you set a REFGND plane that extends as close as possible to the corresponding decoupling capacitor and FPGA e Ifpossible define a complete REFcnp plane in the layout e Otherwise route the REFGND using a trace that is as wide as possible from the island to the FPGA pins and decoupling capacitor The REFGND ground is the reference ground plan
25. ADC sample corresponds Table 5 21 ADC Sample Register ADC_SAMPLE of Altera Modular Dual ADC Address Offset 0x3r slot 63 0x0 slot 0 a T NN NN E Reserved Read Reserved B Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Sample Storage Core Registers 5 17 Altera Modular ADC IP Core References a NEN I NN a Sample Read The slot number to which the 0 to 63 jn ADC sample corresponds for ADC2 15 Reserved Read Reserved 0 12 11 Sample Read The slot number to which the 0 to 63 0 ADC sample corresponds for ADCI Table 5 22 Interrupt Enable Register IER Address Offset 0x40 Clear the enable bit to prevent the corresponding interrupt status bit from causing interrupt output assertion IRQ The enable bit does not stop the interrupt status bit value from showing in the interrupt status register ISR CKIEEEI INNEN L NENNEN NN Reserved Read Reserved Es 0 M EOP Read Write The enable bit for the end of o i pm 0 packet EOP interrupt corresponding interrupt e 0 Disables the corresponding interrupt Table 5 23 Interrupt Status Register ISR Address Offset 0x41 CNETENEI INNEN T NN NN RN E Reserved Read Reserved P 0 EOP Read Write EOP interrupt e 1 Indicates complete 1 one cycle receipt of a sample block e 0 Automatically clears to 0 after indica
26. Avalon MM sample storage and tab threshold violation detection core variant Enable Maximum On Enables the maximum threshold feature for the TSD threshold for on chip Off 4 TSD This option is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core variant Enter Maximum Depends on Specifies the maximum threshold value in Volts reference voltage paco o This setting is available only if you select the Standard Each channel in its own sequencer with Avalon MM sample storage and tab including channel 0 threshold violation detection core variant Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Altera Modular Dual ADC Parameters Settings 5 9 Enter Maximum Threshold for on chip TSD Specifies the maximum threshold value in Celsius This setting is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core variant Enable Minimum e On Enables the minimum threshold feature for the channel threshold tor Channel N Tiao This option is available only if you select the Standard Each channel in its own sequencer with Avalon MM sample storage and tab including channel 0 threshold violation detection core variant Enable Minimum e On Enables the minimum threshold feature for the TSD threshold for on chi
27. C2IN4 CH5 ADC2IN5 CH6 ADC2IN6 CH7 ADC2IN7 CH8 ADC2IN8 Altera Modular Dual ADC Parameters Settings There are three groups of options General Channels and Sequencer Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Altera Modular Dual ADC Parameters Settings 5 7 Table 5 6 Altera Modular Dual ADC Parameters General Core Variant Standard sequencer with Avalon MM sample storage Standard sequencer with Avalon MM sample storage and threshold violation detection Standard sequencer with external sample Selects the core configuration Dual ADC IP core for the Altera Modular storage e ADC control core only ADC Input Clock 2 10 20 40 and Specifies the frequency of the PLL clock counter zero 80 MHz co clock supply for the ADC core clock You must configure the co of the first ALTPLL IP core that you instantiate to output one of the frequen cies in the allowed values list e Connect the ALTPLL co output signal to the Altera Modular Dual ADC clk_in_pll_cO input signal aren Voltage ADC External Specifies the source of voltage reference for the ADC or Internal e External uses vccvrer pin as the voltage reference source e Internal uses the on chip 2 5 V 3 0 3 3V on voltage regulated devices as the voltage reference source External Reference e Dual supply Specifies the voltage of vccvnEr pin if you use it as Voltage
28. FGND MAX 10 ADC Design Considerations Altera Corporation LJ Send Feedback UG M10ADC 3 4 Guidelines Board Design for ADC Reference Voltage Pin 2015 06 11 Figure 3 3 First Order Active Low Pass Filter Example This figure is an example You can design nth order active low pass filter Board RC ADC Analog Input R Driver RC ANN I quoc E V Altera REFGND Device Related Information e How can I change the sampling rate of the ADC in MAX 10 devices Provides more information about reducing the total sampling rate e SPICE Models for Altera Devices Provides the MAX 10 ADC spice model download Guidelines Board Design for ADC Reference Voltage Pin The crosstalk requirement for analog to digital signal is 100 dB up to 2 GHz There is no parallel routing between analog input signals and I O traces Route the Vg traces as adjacent as possible to REFGND If a REFGND plane is not possible route the analog input signal as adjacent as possible to REFGND There is one ADC reference voltage pin in each MAX 10 device This pin uses REFGND as ground reference Keep the trace resistance less than 0 8 O Figure 3 4 RC Filter Design Example for Reference Voltage Pin Place the RC filter as close as possible to the analog input pin VREF bd ANN gt 100 10 0 uF 1pF Altera i l device REFGND REFGND Altera Corporation MAX 10 ADC Design Consideration
29. IP cores to form a working ADC system that uses the Altera ADC HAL drivers 10 In the Qsys window select File gt Save You can copy an example HDL code to declare an instance of your ADC system In the Qsys window select Generate HDL Example Altera Corporation MAX 10 ADC Implementation Guides C Send Feedback UG M10ADC 2015 06 11 Parameters Settings for Generating ALTPLL IP Core 4 3 Related Information Creating MAX 10 ADC Design on page 4 2 Parameters Settings for Generating ALTPLL IP Core on page 4 3 Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core on page 4 4 Configuration 1 Standard Sequencer with Avalon MM Sample Storage on page 2 10 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection on page 2 11 Configuration 3 Standard Sequencer with External Sample Storage on page 2 13 Configuration 4 ADC Control Core Only on page 2 13 ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC on page 5 15 ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC on page 5 15 Parameters Settings for Generating ALTPLL IP Core Navigate through the ALTPLL IP core parameter editor and specify the settings required for your design After you have specified all options as listed in the following table you can generate the HDL files and the optional simulation files For more information about all ALTPL
30. Indicates the type of threshold violation e 1 Exceeds maximum threshold value e 0 Below minimum threshold value Related Information e Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 5 e Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 10 Altera Modular ADC IP Core References Altera Corporation C Send Feedback UG M10ADC 5 14 CSR Interface of Altera Modular ADC and Altera Modular Dual ADC 2015 06 11 CSR Interface of Altera Modular ADC and Altera Modular Dual ADC The CSR interface is an Avalon MM slave interface Table 5 13 CSR Interface Signals Width Description Bit address lor7 Avalon MM address bus The address bus width is in the unit of word addressing e altera adc sample store core address width is seven e altera adc sequencer core address width is one read 1 Avalon MM read request write 1 Avalon MM write request writedata 32 Avalon MM write data bus readdata 32 Avalon MM read data bus IRQ Interface of Altera Modular ADC and Altera Modular Dual ADC The IRQ interface is an interrupt interface type Table 5 14 IRQ Interface Signals Width Description Bit irq 1 Interrupt request Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC The peripheral clock interface is a clock sink interface type Table 5 15 Peripheral Clock Interface Signals Width Description Bit
31. L input clock source the Quartus II Fitter merges both PLLs as one In dual ADC mode both ADC instance must share the same ADC clock setting ADC Voltage Reference Each ADC block in MAX 10 devices can independently use an internal or external voltage reference In dual ADC devices you can assign an internal voltage reference to one ADC block and an external voltage reference to the other ADC block There is only one external vngr pin in each MAX 10 device Therefore if you want to assign external voltage reference for both ADC blocks in dual ADC devices share the same external voltage reference for both ADC blocks Altera recommends that you use external voltage reference for the ADC blocks If the ADC block uses an internal voltage reference the ADC block is tied to its analog voltage and the conversion result is ratiometric ADC Temperature Sensing Diode The ADC block in MAX 10 devices has built in TSD You can use the built in TSD to monitor the internal temperature of the MAX 10 device e While using the temperature sensing mode the ADC sampling rate is 50 kilosamples per second during temperature measurement e After the temperature measurement completes if the next conversion in the sequence is normal sampling mode the Altera Modular ADC IP core automatically switches the ADC back to normal sampling mode The cumulative sampling rate in normal sampling mode is 1 MSPS e When the ADC switches from normal sensing mode to
32. L parameters refer to the related information Table 4 1 ALTPLL Parameters Settings Parameter Settings gt General What is the frequency Modes To generate the PLL for the ADC use the following settings Specify the input frequency to the PLL of the inclk0 input peo put irequency Parameter Settings gt Inputs Create an areset input to asynchronously reset the PLL Turn off this option Create locked output Lock Turn on this option You need to connect this signal to the adc p11 1ocked port of the Altera Modular ADC or Altera Modular Dual ADC IP core MAX 10 ADC Implementation Guides Altera Corporation LJ Send Feedback UG M10ADC 4 4 Parameters Settings for Generating Altera Modular ADC or Altera Modular 2015 06 11 Use this clock Turn on this option Enter output clock Specify an output frequency of 2 10 20 40 frequency or 80 MHz You can specify any of these frequencies The ADC block runs at 1 MHz internally but it contains a clock divider that Output Clocks gt clk c0 can further divide the clock by a factor of 2 10 20 40 and 80 Use this same frequency value in your Altera Modular ADC or Altera Modular Dual ADC IP core You need to connect this signal to the adc pll clock port of the Altera Modular ADC or Altera Modular Dual ADC IP core Related Information e Creating MAX 10 ADC Design on page 4 2 Customizing and Generating Altera Modular ADC IP Core
33. MAX 10 Analog to Digital Converter User Guide ES Subscribe UG M10ADC 2015 06 11 LJ Send Feedback 101 Innovation Drive San Jose CA 95134 N DTE BJAN www altera com TOC 2 Contents MAX 10 ADC Overview m 1 1 ADG Block Counts in MAX 10 Devices ici sisciscscandicriencseissncatemanatuninaryusnmeduumansemenien 1 1 ADC Channel Counts in MAX 10 DeVlCgsi beca netter odeb rale mpada dettes obtu bn ated stus todo ne st papi 1 2 MAX 10 ADC Vertical Migration BUDDOEL a espe btt QE QUEP MEIN FI GER pA NE VERNA EERIIRM DEEP GN CHER 1 3 MAX 10 Single or Dual Supply Devices ircecsetntratent tinte anahisi 1 4 MAX 10 Sb OTI c 1 4 MAX 10 ADC Architecture and Features eese eee eee eene 2 1 MAX 10 ADG Hard IP Block ett emere deer e iR ERE ERE EE FEET aS 2 1 ADC Block Eocations 9 eea eit TODO doi ad anda dn aac utes 2 2 Singleor Dual ADC Devices ou oer DURO RM QUPD En DN MENU DERE 2 4 ADC Analog Inp t PRES eT 2 5 ADU Prescaleiss sacs cesewenen ni EU MN TUNER SES EU QUEM qM dH 2 5 ADC Clock SOUrCES 2 5 IR ee clc dui iro P c M 2 6 ADC Temperature Sensing DIO uo opea ON a In e DIS ha v Rc 2 6 PIBIeR Tiu P 2 8 ADC yii c 2 9 Altera Modular ADC and Altera Modular Dual ADC IP Cores enean roten ternas nso 2 9 Altera Modular ADC IP Cor
34. MAX 10 Devices 2015 06 11 Table 1 1 Number of ADC Blocks in MAX 10 Devices and Packages For more information about the device part numbers that feature ADC blocks refer to the device overview Power DIS Sii Eee 2 a ea a Package M153 Single U169 Single 1 1 1 U324 Dual 1 1 1 F256 Dual 1 1 1 2 p 2 E144 Single 1 1 1 1 1 1 F484 Dual 1 1 2 p 2 2 2 Related Information MAX 10 FPGA Device Overview ADC Channel Counts in MAX 10 Devices Different MAX 10 devices support different number of ADC channels Table 1 2 ADC Channel Counts in MAX 10 Devices e Devices with two ADC blocks have two dedicated analog inputs and each ADC block has 8 dual function pins You can use the dual function pins in an ADC block as general purpose I O GPIO pins if you do not use the ADC For more information about the device part numbers that feature ADC blocks refer to the device overview ADC Channel Counts Per Device Package Pin Type tomes 1omos tomie 1om25 toma 10M50 1 1 Dedicated M153 Dual 8 8 function Dedicated 1 1 1 U169 Dual 8 8 8 function Dedicated 1 1 1 U324 Dual 16 16 16 function Dedicated 1 1 1 2 2 2 F256 Dual 16 16 16 16 16 16 function Altera Corporation MAX 10 ADC Overview C Send Feedback UG M10ADC 2015 06 11 MAX 10 ADC Vertical
35. MAX 10 devices Figure 2 5 ADC Prescaler Block Diagram Analog AAA Input 3 6 kQ Mux O V Le REFGND The prescaler feature is available on these channels in each ADC block e Single ADC device channels 8 and 16 if available e Dual ADC device e Using Altera Modular ADC IP core channel 8 of first or second ADC e Using Altera Modular Dual ADC IP core channel 8 of ADCI and channel 17 of ADC2 ADC Clock Sources The ADC block uses the device PLL as the clock source The ADC clock path is a dedicated clock path You cannot change this clock path MAX 10 ADC Architecture and Features Altera Corporation CJ Send Feedback UG M10ADC 2 6 ADC Voltage Reference 2015 06 11 Depending on the device package the MAX 10 devices support one or two PLLs PLLI only or PLL1 and PLL3 For devices that support two PLLs you can select which PLL to connect to the ADC You can configure the ADC blocks with one of the following schemes e Both ADC blocks share the same clock source for synchronization e Both ADC blocks use different PLLs for redundancy If each ADC block in your design uses its own PLL the Quartus II Fitter automatically selects the clock source scheme based on the PLL clock input source e Ifeach PLL that clocks its respective ADC block uses different PLL input clock source the Quartus II Fitter follows your design two PLLs e Ifboth PLLs that clock their respective ADC block uses the same PL
36. Nios II Gen 2 4 cadcaidtaveidis tite pacto eu de a Ed o cupa 5 18 Additional Information for MAX 10 Analog to Digital Converter User Altera Corporation MAX 10 ADC Overview 1 2015 06 11 UG M10ADC CX subscribe LJ Send Feedback MAX 10 devices feature up to two analog to digital converters ADC The ADCs provide the MAX 10 devices with built in capability for on die temperature monitoring and external analog signal conversion The ADC solution consists of hard IP blocks in the MAX 10 device periphery and soft logic through the Altera Modular ADC IP core The ADC solution provides you with built in capability to translate analog quantities to digital data for information processing computing data transmission and control systems The basic function is to provide a 12 bit digital representation of the analog signal being observed The ADC solution works in two modes e Normal mode monitors single ended external inputs with a cumulative sampling rate of 1 million samples per second MSPS e Single ADC devices up to 17 single ended external inputs one dedicated analog and 16 dual function input pins e Dual ADC devices up to 18 single ended external inputs one dedicated analog and eight dual function input pins in each ADC block e Temperature sensing mode monitors external temperature data input with a sampling rate of up to 50 kilosamples per second In dual ADC devices only the first ADC block supports this mode
37. Related Information MAX 10 ADC Architecture and Features on page 2 1 MAX 10 ADC Design Considerations on page 3 1 MAX 10 ADC Implementation Guides on page 4 1 e Altera Modular ADC IP Core References on page 5 1 ADC Block Counts in MAX 10 Devices The ADC block is available in single and dual supply MAX 10 devices O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG M10ADC 1 2 ADC Channel Counts in
38. amp adc_pll_locked SRC response locked signal from dedicated PLL p handshake gt SNK SRC Avalon ST Splitt SNK na ag a altera_adc_response_merge altera adc sample store CR 1 S altera dual adc synchronizer SNK SRC response SNK SEE gt SR Avalon ST Splitter ol SNK SNK Core gt IRQ fsm handshake SNK SRC response SRC SRC command ES response SRC SNK SRC response SNK altera_adc_control altera adc threshold detect SRC threshold Related Information e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Completing ADC Design on page 4 7 Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC 2015 06 11 Configuration 3 Standard Sequencer with External Sample Storage 2 13 Configuration 3 Standard Sequencer with External Sample Storage In this configuration variant you can use the standard sequencer micro core and store the ADC samples in external storage You need to design your own logic to interface with the external storage Figure 2 11 Standard Sequencer with External Sample Storage Altera Modular ADC IP Core altera adc adc pll dock heral clock er adc p Seed MEM clock from dedicated PLL altera adc sequencer altera adc control adc pll locked locked signal from dedicated PLL ck REB cman SNK SRC response Figure 2 12 Standard Sequenc
39. and Generating Altera Modular ADC IP Core on page 4 2 Parameters Settings for Generating ALTPLL IP Core on page 4 3 Altera Modular ADC Register Definitions The registers in the generated Altera Modular ADC IP core provide the IP core with the control and settings during operation Altera Modular ADC IP Core References Altera Corporation C Send Feedback UG M10ADC 5 16 Sequencer Core Registers 2015 06 11 Sequencer Core Registers Table 5 19 Command Register CMD Address Offset 0x0 LINCENEI INNEN oe 31 4 Reserved Read Reserved 3 1 Mode Read Write Indicates the operation modeof e 7 Recalibrate the 0 the sequencer core ADC This register is ignored when the 19 ESC run bit bit 0 is set e 1 Single cycle ADC conversion In continuous conversion the CROSS COnmIcUS ADC data will be overwritten after a i conversion complete sampling sequence 0 Run Read Write Use this control bit to trigger the e 1 Run 0 sequencer core operation e 0 Stop The Altera Modular ADC IP core waits until the sequencer core completes its current operation before writing to this register bit Related Information Sequencer Core on page 2 17 Sample Storage Core Registers Table 5 20 ADC Sample Register ADC_SAMPLE of Altera Modular ADC Address Offset 0x3r slot 63 0x0 slot 0 a a RN GE 31 Reserved Read Reserved 12 11 Sample Read The slot number to which the 0 to 63 0 0
40. andard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection on page 2 11 Configuration 3 Standard Sequencer with External Sample Storage on page 2 13 Configuration 4 ADC Control Core Only on page 2 13 e Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 5 e Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 10 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Each ADC channel in the Altera Modular ADC IP core corresponds to different device pin name for single and dual ADC devices Table 5 4 Altera Modular ADC IP Core Channel to Pin Mapping for Single ADC Devices CHO ANAINI CHI ADCIINI CH2 ADCIIN2 CH3 ADCIIN3 CH4 ADCIIN4 CH5 ADCIIN5 CH6 ADCIIN6 CH7 ADCIIN7 CH8 ADCIIN8 CH9 ADCIIN9 CH10 ADCIIN10 CH11 ADCIIN11 CH12 ADCIIN12 CH13 ADCIIN13 CH14 ADCIIN14 Altera Modular ADC IP Core References C Send Feedback Altera Corporation UG M10ADC 5 6 Altera Modular Dual ADC Parameters Settings 2015 06 11 CH15 ADCIINI5 CH16 ADCIINI6 Table 5 5 Altera Modular ADC IP Core Channel to Pin Mapping for Dual ADC Devices CHO ANAINI CHI ADCIINI CH2 ADCIIN2 CH3 ADCIIN3 First ADC CH4 ADCIIN4 CH5 ADCIIN5 CH6 ADCIIN6 CH7 ADCIIN7 CH8 ADCIIN8 CHO ANAIN2 CHI ADC2IN1 CH2 ADC2IN2 CH3 ADC2IN3 Second ADC CH4 AD
41. bout pin connections including pin names and connection guidelines Guidelines Board Design for Power Supply Pin and ADC Ground reren The crosstalk requirement for analog to digital signal is 100 dB up to 2 GHz There must be no parallel routing between power ground and I O traces If a power plane is not possible route the power and ground traces as wide as possible To reduce IR drop and switching noise keep the impedance as low as possible for the ADC power and ground The maximum DC resistance for power is 1 5 Q e The power supplies connected to the ADC should have ferrite beads in series followed by a 10 uF capacitor to the ground This setup ensures that no external noise goes into the device power supply pins e Decouple each of the device power supply pin with a 0 1 uF capacitor Place the capacitor as close as possible to the device pin O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any
42. control cores Both ADC hard IP cores communicate with the dual ADC synchronizer core through the Avalon ST interface For example although a new command valid event from the sequencer arrives at both ADC control cores at the same peripheral clock cycle the end of conversion signals arrive at one peripheral clock cycle difference between ADC1 and ADC2 To avoid the condition where ADCI begins conversion earlier or later than ADC2 the ADC control core performs synchronization handshake using the dual ADC synchronizer core An ADC control core asserts a sync valid signal when it detects an ADC PLL clock domain event The dual ADC synchronizer core asserts the sync ready signal after it receives sync valid signals from both ADC control cores After the sync ready signal is asserted both ADC control cores proceed to their next internal state MAX 10 ADC Architecture and Features Altera Corporation LJ Send Feedback UG M10ADC 2 20 Threshold Detection Core 2015 06 11 Figure 2 19 Dual ADC Synchronizer Core High Level Block Diagram altera dual adc synchronizer peripheral clock 5 peripheral reset sync handshake SNK Synchronizer sync handshake 9 SNK logic Threshold Detection Core The threshold detection core compares the sample value that the ADC block receives to the threshold value that you define during Altera Modular ADC IP core conf
43. dc_pll_locked sync handshake locked signal from dedicated PLL SNK altera_adc_response_merge altera adc sample store SR 3 S altera_dual_adc_synchronizer o spe eee SNK S csp SNK pe gt IRQ sync handshake SRC c ona ci SRC response altera adc control Related Information e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Completing ADC Design on page 4 7 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection In this configuration variant you can use the standard sequencer micro core with internal on chip RAM for storing ADC samples with the additional capability of detecting threshold violation This configuration is useful for system monitoring application where you want to know whether the ADC samples value fall outside the maximum or minimum threshold value When the threshold value is violated the Altera Modular ADC or Altera Modular Dual ADC IP core notifies the discrete logic component The discrete component then triggers system recovery action For example the system can increase the fan speed in a temperature control system MAX 10 ADC Architecture and Features Altera Corporation LJ Send Feedback UG M10ADC 2 12 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and 2015 06 11 Figure 2 9 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection Altera Modular ADC IP Core
44. e Configuration Variants esee 2 10 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture 2 14 Altera ADC HAL DEIVGE esee tenete rre aaaeaii aee dio i deinen tede dea 2 20 MAX 10 ADC Design Considerations eere eee ee eene nete eee tn annue 3 1 Guidelines ADC Ground Plane LOofffec IO au estoieeta sb ttnteosbda lesen niii pi ph red Rok al i pado pi da 3 1 Guidelines Board Design for Power Supply Pin and ADC Ground REFGND sess 3 1 Guidelines Board Design for Analog DSDULa gear Lese on dial petet d dede oni EK RR dp 3 2 Guidelines Board Design for ADC Reference Voltage Pin erret ttes 3 4 MAX 10 ADC Implementation Guides eese eene eene 4 1 Creating MAX 10 ADC Design eee reco er EH RR HR EX ern E Xen Hato 4 2 Customizing and Generating Altera Modular ADC IP Core eese 4 2 Parameters Settings for Generating ALTPLL IP Col depu bd efi beu En bui 4 3 Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP CONG 4 4 Compl ting ADG Desig RT 4 7 Altera Modular ADC IP Core References eere eee eene eene 5 1 Altera Modular ADC Parameters Settings eco ras oues erga SERRE RO HER bnE VR IRAE NASCE E V D eU MEE ME 5 1 Altera Corporation Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Map
45. e for the ADC V ggg and analog input e Connect REFGND ground to the system digital ground through ferrite beads You can also evaluate the ferrite bead option by comparing the impedance with the frequency specifications Guidelines Board Design for Analog Input The crosstalk requirement for analog to digital signal is 100 dB up to 2 GHz There must be no parallel routing between analog input signals and I O traces and between analog input signals and FPGA I O signal traces The total RC constant including package trace and parasitic driver must be less than 42 4 ns This consideration is to ensure that the input signal is fully settled during the sampling phase Ifyoureduce the total sampling rate you can calculate the required settling time as 0 45 Fg gt 10 62 x RC constant To gain more total RC margin Altera recommends that you set the driver source impedance as low as possible e For prescaler disabled channel less than 1 kQ e For prescaler enabled channel less than 11 Q Altera Corporation MAX 10 ADC Design Considerations C Send Feedback UG M10ADC 2015 06 11 Guidelines Board Design for Analog Input 3 3 Trace Routing e If possible route the switching I O traces on different layer e There is no specific requirement for input signal trace impedance However the DC resistance for the input trace must be as low as possible e Route the analog input signal traces as adjacent as possible to REFGND if
46. el names to MAX 10 device pin names Corrected the address offset of the interrupt enable register from 0x41 to 0x40 and interrupt status register from 0x40 to 0x41 for the sample storage core Updated the sample storage core registers table to include registers for Altera Modular Dual ADC Removed statements about availability of the threshold trigger feature in a future version of the Quartus II software The feature is now available from version 15 0 of the software Added ADC prescaler block diagram Replaced the ADC continuous conversion timing diagram with the ADC timing diagram Corrected a minor error in the example in the topic about the sample storage core Added information that the ADC TSD measures the temperature using a 64 samples running average method Updated majority of the temperature codes in the table that lists the temperature code conversion Added chapter that provides the ADC design considerations Removed mention of value 0 for values allowed for the number of sequencer slots used in Altera Modular ADC IP core parameter editor Only values 1 to 64 are allowed Removed the statement about enabling and disabling additional ADC response interface or debugging in the topic about the Altera Modular ADC IP core configuration variants You can enable or disable the debug path in the parameter editor Removed the debug paths diagrams for each ADC core configura tion Removed the statement about using the sequ
47. encer core to trigger recalibration The ADC is automatically recalibrated when it switches from normal sensing mode to temperature sensing mode Edited text to clarify about routing power or ground traces if power or ground plane is not possible Updated the total RC constant values in the table that shows the RC constant and filter values calculation Corrected spelling for prescaler September 2014 2014 09 22 Initial release Altera Corporation Additional Information for MAX 10 Analog to Digital Converter User Guide C Send Feedback
48. er with External Sample Storage Altera Modular Dual ADC IP Core altera dual adc altera adc sequencer altera adc control peripheral clock SRC commandi SNK SRC peripheral reset gt response SRC K adc_pll_clock synchandshake clock from dedicated PLL k adc_pll_locked SNK locked signal from dedicated PLL CSR lt gt S altera_dual_adc_synchronizer SNK sync handshake SRC CUE T SRC gt response altera adc control Related Information e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Completing ADC Design on page 4 7 Configuration 4 ADC Control Core Only In this configuration variant the Altera Modular ADC generates only the ADC control core You have full flexibility to design your own application specific sequencer and use your own way to manage the ADC samples MAX 10 ADC Architecture and Features LJ Send Feedback Altera Corporation UG M10ADC 2 14 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture 2015 06 11 Figure 2 13 ADC Control Core Only Altera Modular ADC IP Core i altera adc adc pll dock eripheral clock j adc pil ed e EN clock from dedicated PLL altera_adc_control adc_pll_locked locked signal from dedicated PLL command snk SRC gt res
49. era Modular ADC Parameters Settings on page 5 1 e Altera Modular Dual ADC Parameters Settings on page 5 6 e Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 5 e Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5 10 Altera Corporation MAX 10 ADC Implementation Guides C Send Feedback UG M10ADC 2015 06 11 Completing ADC Design 4 7 Completing ADC Design The ADC design requires that the ALTPLL IP core clocks the Altera Modular ADC IP core Before you begin Generate the ALTPLL and Altera Modular ADC IP cores with the settings in the related information Figure 4 2 Basic MAX 10 ADC Design Altera Modular ADC clock sample store irq ie clock_clk la irq sample store irq irq PLL reset sink reset sink reset n reset n n adc pll cock indk0 C a inck0 frequency 100 000 MHz adc pll dock dk clk Operation Mode Normal adc pll locked locked Clk Ratio Ph dg DC adc_pll_locked_export export c 1 10 0 00 50 00 sequencer_csr sequencer_csr_address sequencer_csr_read sequencer_csr_write sequencer_csr_writedata 31 0 sequencer csr readdata 31 0 sample store csr sample store csr address 6 0 sample store csr read sample store csr write sample store csr writedata 31 0 sample store csr readdata 31 0 1 Create the design as s
50. et 64 RAM Entries for RAM ADC Sample Storage Control k response IER Register Interrupt IRQ ISR Register Control Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC PET 2015 06 11 Response Merge Core Related Information Sample Storage Core Registers on page 5 16 Response Merge Core The response merge core merges simultaneous responses from two ADC control cores in the Altera Modular Dual ADC IP core The Altera Modular Dual ADC IP core uses the response merge core if you use the following configura tions e Standard Sequencer with Avalon MM Sample Storage e Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection Figure 2 18 Response Merge Core High Level Block Diagram altera_adc_response_merge peripheral clock 3 peripheral reset response gt SNK Response merge SRC response logic response SNK Dual ADC Synchronizer Core The dual ADC synchronizer core performs synchronization handshakes between two ADC control cores in the Altera Modular Dual ADC IP core The peripheral clock domain is asynchronous to the ADC PLL clock domain in the ADC control core Control event from the ADC hard IP block can appear at the peripheral clock domain at the same time or by a difference of one peripheral clock between ADC1 and ADC2
51. hannel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins Altera Corporation Altera Modular ADC IP Core References C Send Feedback UG M10ADC 2015 06 11 Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC 5 13 Width Description Bit data 12 or 24 ADC sampling data e 12 bit width for Altera Modular ADC e 24 bit width for Altera Modular Dual ADC startotpacket 1 Indication from the source port that current transfer is the start of packet For altera_adc_control core implementation the source of this signal is from the corresponding command interface endotp cke 1 Indication from the source port that current transfer is the end of packet For altera_adc_control core implementation the source of this signal is from the corresponding command interface Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC The threshold interface is an Avalon ST type interface that does not support backpressure Table 5 12 Threshold Interface Signals Width Description Bit valid 1 Indication from the source port that current transfer is valid cue 5 Indicates the ADC channel for which the threshold value has been violated e 31 18 not used e 17 temperature sensor e 16 0 channels 16 to 0 where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins dna 1
52. hown in the preceding figure 2 Connect the co signal from the ALTPLL IP core to the adc p11 clock clk port of the Altera Modular ADC IP core 3 Connect the locked signal from the ALTPLL IP core to the adc p11 locked export port of the Altera Modular ADC IP core 4 Create the ADC Avalon slave interface to start the ADC Related Information Creating MAX 10 ADC Design on page 4 2 e Parameters Settings for Generating ALTPLL IP Core on page 4 3 Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core on page 4 4 Configuration 1 Standard Sequencer with Avalon MM Sample Storage on page 2 10 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection on page 2 11 Configuration 3 Standard Sequencer with External Sample Storage on page 2 13 Configuration 4 ADC Control Core Only on page 2 13 MAX 10 ADC Implementation Guides Altera Corporation LJ Send Feedback Altera Modular ADC IP Core References 2015 06 11 UG M10ADC CX subscribe LJ Send Feedback The Altera Modular ADC IP core is a soft controller for the ADC hard IP blocks You can generate soft IPs to instantiate the on chip ADC blocks With this IP core you can configure the ADCs and abstract the low level handshake with the ADC hard IP blocks The Quartus II software generates your customized Altera Modular ADC IP core according to the parameter options that you set in the parameter edito
53. iguration This core does not have run time configurable options If the ADC sample value is beyond the maximum or minimum threshold limit the threshold detection core issues a violation notification through the Avalon ST interface The threshold detection core has a single clock domain Figure 2 20 Threshold Detection Core High Level Block Diagram peripheral clock altera_adc_threshold_detect peripheral reset Comparator threshold SRC Logic SNK response Altera ADC HAL Driver The Altera ADC HAL driver supports the following features e Read ADC channel data e Enable maximum or minimum threshold and return a user callback when the interrupt is triggered Command the control of the ADC run stop and recalibrate Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback MAX 10 ADC Design Considerations 2015 06 11 UG M10ADC CX subscribe LJ Send Feedback There are several considerations that require your attention to ensure the success of your designs Unless noted otherwise these design guidelines apply to all variants of this device family Related Information MAX 10 ADC Overview on page 1 1 Guidelines ADC Ground Plane Connection For power pins use the cnp pin For the ADC and Vgg pins use the REFGND pin Related Information MAX 10 FPGA Device Family Pin Connection Guidelines Provides more information a
54. is 8 e The response data for channel 1 is 1 Altera Modular ADC and Altera Modular Dual ADC IP Cores You can use the Altera Modular ADC and Altera Modular Dual ADC IP cores to generate soft IP controllers for the ADC hard IP blocks in MAX 10 devices There are two ADC IP cores e Altera Modular ADC IP core each instance can control one ADC hard IP block In a dual ADC device you can instantiate one Altera Modular ADC IP core instance for each ADC block However both instances will be asynchronous to each other e Altera Modular Dual ADC IP core you can control both ADC hard IP block with a single IP instance For the analog input pins ANAIN1 and ANAIN2 in both ADC hard IP blocks the measurement is synchronous e For the dual function input pins there are some measurement timing differences caused by the routing latency MAX 10 ADC Architecture and Features Altera Corporation LJ Send Feedback UG M10ADC 2 10 Altera Modular ADC IP Core Configuration Variants 2015 06 11 You can perform the following functions with the Altera Modular ADC or Altera Modular Dual ADC IP core parameter editor e Configure the ADC clock and reference voltage e Select which analog input channels that the ADC block samples e Configure the threshold value to trigger a threshold violation notification e Set up a conversion sequence to determine which channel requires more frequent attention Related Information Altera Modular ADC IP Co
55. log input pin Dual ADC device Single ADC device e Eight dual function pins from the ADCI block of the source device to the ADCI block of the target device Related Information ADC Channel Counts in MAX 10 Devices on page 1 2 MAX 10 Single or Dual Supply Devices MAX 10 devices are available in single or dual supply packages e For devices with single power supply e Use on chip regulator to power up the digital supply Use Vcca to power up the ADC analog e For dual power supply devices you must provide external power supplies of 1 2 V and 2 5 V to power up the ADC To choose the correct device refer to the MAX 10 device overview For more information about the ADC parameter refer to the device datasheet Related Information MAX 10 Device Datasheet MAX 10 FPGA Device Overview MAX 10 ADC Conversion The ADC in dual supply MAX 10 devices can measure from 0 V to 2 5 V In single supply MAX 10 devices it can measure up to 3 0 V or 3 3 V depending on your power supply voltage e In prescaler mode the analog input can measure up to 3 0 V in dual supply MAX 10 devices and up to 3 6 V in single supply MAX 10 devices e The analog input scale has full scale code from 000n to rrrn However the measurement can only display up to full scale 1 LSB e For the 12 bits corresponding value calculation use unipolar straight binary coding scheme Altera Corporation MAX 10 ADC Overview C Send Feedback UG M10ADC 1 20
56. nd then stops the conversion Related Information e Altera Modular ADC Parameters Settings on page 5 1 Lists the parameters available during Altera Modular ADC IP core configuration e Altera Modular Dual ADC Parameters Settings on page 5 6 Lists the parameters available during Altera Modular Dual ADC IP core configuration e Sequencer Core Registers on page 5 16 Lists the registers for run time control of the sequencer core Sample Storage Core The sample storage core stores the ADC sampling data in the on chip RAM The sample storage core stores the ADC samples data based on conversion sequence slots instead of ADC channels For example if you sample a sequence of CH1 CH2 CH1 CH3 CH1 and then CH4 the ADC sample storage core stores the channel sample data in the same RAM entry sequence This means that CH1 sample data will be in the first third and fifth RAM entries one for each sequence slot The sample storage core asserts IRQ when it completes receipt of a sample block You can disable the IRQ assertion during run time using the interrupt enable register IER of the sample storage core If you disable IRQ assertion you must create polling methods in your design to determine the complete receipt of a sample block The sample storage core has a single clock domain Figure 2 17 Sample Storage Core High Level Block Diagram altera_adc_sample_store peripheral clock 4 peripheral res
57. nt Enter Maximum Depends on Threshold for Channel N reference voltage Specifies the maximum threshold value in Volts This setting is available only if you select the Standard Each channel in its own sequencer with Avalon MM sample storage and tab including channel 0 threshold violation detection core variant Altera Modular ADC IP Core References C Send Feedback Altera Corporation Altera Modular ADC Parameters Settings UG M10ADC 2015 06 11 Enter Maximum Threshold for on chip TSD Specifies the maximum threshold value in Celsius This setting is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core variant Enable Minimum e On Enables the minimum threshold feature for the channel threshold tor Channel N Tiao This option is available only if you select the Standard Each channel in its own sequencer with Avalon MM sample storage and tab including channel 0 threshold violation detection core variant Enable Minimum e On Enables the minimum threshold feature for the TSD threshold for on chip Off E TSD This option is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core variant Enter Minimum Depends on Specifies the minimum threshold value in Volts Threshold for Channel N Each channel in its own tab including channel
58. nt capability at the dedicated analog input pins for dual ADC devices e Soft logic sequencer e On chip temperature sensor with sampling rate of 50 kilosamples per second e Internal or external voltage references usage The source of the internal voltage reference is the ADC analog supply the ADC conversion result is ratiometric Related Information MAX 10 ADC Overview on page 1 1 MAX 10 ADC Hard IP Block The MAX 10 ADC is a successive approximation register SAR ADC that converts one analog sample in one clock cycle Each ADC block supports one dedicated analog input pin and up to 16 channels of dual function pins You can use the built in temperature sensing diode TSD to perform on chip temperature measurement O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application
59. onitoring application In a system monitoring application the ADC captures a block of samples data and stores them in the on chip RAM The host processor retrieves the data before triggering another block of ADC data sample request The speed of the host processor in servicing the interrupt determines the interval between each block sample request Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC 2015 06 11 Configuration 2 Standard Sequencer with Avalon MM Sample Storage and 2 11 Figure 2 7 Standard Sequencer with Avalon MM Sample Storage Altera Modular ADC IP Core altera adc peripheral clock altera adc sequencer altera adc control adc pll dock peripheral reset dock from dedicated PLL SR lt S SRC command SNK SRC adc pll locked locked signal from dedicated PLL altera adc sample store response CR L S SNK IRQ Figure 2 8 Standard Sequencer with Avalon MM Sample Storage Altera Modular Dual ADC IP Core altera dual adc altera adc sequencer altera adc control peripheral clock giri emma oiy mg e adc pll dock peripheral reset clock from dedicated PLL SRC k a
60. or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 UG M10ADC 2 2 ADC Block Locations 2015 06 11 Figure 2 1 ADC Hard IP Block in MAX 10 Devices Note In dual ADC devices the temperature sensor is available only in ADCI PLL Clock In Dedicated ADC Hard IP Block Analog Input ADCAnaloglnput Mux 12 bit 1 Mbps ADC Dual Function 16 1 Temperature Sensor ADC Voer CE Internal Vprr ADC Block Locations The ADC blocks are located at the top left corner of the MAX 10 device periphery Figure 2 2 ADC Block Location in MAX 10 04 and 08 Devices 8 J ADC 1A 6 1B 2 5 1 0 Bank 3 ADC Block Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC AS 2015 06 11 ADC Block Locations Figure 2 3 ADC Block Location in MAX 10 16 Devices
61. ore supports fault detection The threshold detection core receives ADC samples through the Avalon ST interface and checks whether the samples value exceeds the maximum or falls below the minimum threshold value e The threshold detection core conveys threshold value violation informa tion through the Avalon ST interface e You can configure which channel to enable for maximum and minimum threshold detection and the threshold values only during IP core generation ADC Control Core The ADC control core drives the ADC hard IP according to the command it receives The control core also maps the channels from the Altera Modular ADC IP core to the channels in the ADC hard IP block The ADC control core of the Altera Modular ADC IP core implements only the functions that are related to ADC hard IP block operations For example e Power up e Power down e Analog to digital conversion on analog pins e Analog to digital conversion on on chip temperature sensor The ADC control core has two clock domains e One clock domain for clocking the ADC control core soft logic e Another clock domain for the ADC hard IP block The ADC control core does not have run time configurable options Figure 2 15 ADC Control Core High Level Block Diagram altera adc control adc pll dod peripheral dock 35 dock from dedicated PLL peripheral reset ADC ADC K adc_pll_locked locked signal from dedicated PLL Controller Ha
62. p Off E TSD This option is available only if you select the Standard sequencer with Avalon MM sample storage and TSD tab threshold violation detection core variant Enter Minimum Depends on Specifies the minimum threshold value in Volts Threshold for Channel N Each channel in its own tab including channel 0 reference voltage This setting is available only if you select the Standard sequencer with Avalon MM sample storage and threshold violation detection core variant Enter Minimum Threshold for on chip TSD TSD tab Specifies the minimum threshold value in Celsius This setting is available only if you select the Standard sequencer with Avalon MM sample storage and threshold violation detection core variant Enable Prescaler for Channel N Enables the prescaler function where N is e Channel 8 in ADCI e Channel 17 in ADC2 Table 5 8 Altera Modular Dual ADC Parameters Sequencer Number of slot used 1 to 64 Specifies the number of conversion sequence slots to use for both ADCI and ADC2 The Conversion Sequence Channels section displays the slots available for ADC1 and ADC2 according to the number of slots you select here Altera Modular ADC IP Core References C Send Feedback Altera Corporation 5 10 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name UG M10ADC 2015 06 11 Slot N Enabled channel number CH N Specifies which
63. ping 5 5 Altera Modular Dual ADC Parameters Settings seeders toits ir xe p i er ER e bt HARE 5 6 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name uk c 5 10 Altera Modular ADC and Altera Modular Dual ADC Interface Signals sss 5 11 Command Interface of Altera Modular ADC and Altera Modular Dual ADC 5 11 Response Interface of Altera Modular ADC and Altera Modular Dual ADC 5 12 Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC 5 13 CSR Interface of Altera Modular ADC and Altera Modular Dual ADC 5 14 IRQ Interface of Altera Modular ADC and Altera Modular Dual ADC 5 14 Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC 5 14 Peripheral Reset Interface of Altera Modular ADC and Altera Modular Dual ADC 5 4 ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC 5 15 ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC 5 15 Altera Modular ADC Register Definitions certet tarea Fees bnt c ra iiU rea RE eH E ROIG 5 15 Sequencer Core REGiSters m 5 16 Sample Storage Core D BISDSES cuoio RF Ov papa pp Op Qu Apu pu Ferr prp ipa 5 16 ADC HAL Device Driver for
64. ponse Figure 2 14 ADC Control Core Only Altera Modular Dual ADC IP Core altera dual adc altera adc control command 1 SNK SRC gt response peripheral clock SRC adc_pll_clock peripheral reset sync handshake dock from dedicated PLL adc pll locked SNK locked signal from dedicated PLL altera_dual_adc_synchronizer SNK sync handshake SRC command SNK SRC gt response altera adc control Related Information e Customizing and Generating Altera Modular ADC IP Core on page 4 2 Completing ADC Design on page 4 7 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture The Altera Modular ADC IP core consists of six micro cores MAX 10 ADC Architecture and Features C Send Feedback Altera Corporation UG M10ADC 2015 06 11 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture 2 15 Table 2 2 Altera Modular ADC Micro Cores ADC control This core interacts with the ADC hard IP block The ADC control core uses Avalon ST interface to receive commands from upstream cores decodes and drives the ADC hard IP block accordingly Sequencer This core contains command register and static conversion sequence data The sequencer core issues commands for downstream cores to execute e You can use the command
65. r Related Information e MAX 10 ADC Overview on page 1 1 e Altera Modular ADC and Altera Modular Dual ADC IP Cores on page 2 9 e Altera Modular ADC IP Core Configuration Variants on page 2 10 Altera Modular ADC Parameters Settings There are three groups of options General Channels and Sequencer O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG M10ADC 5 2 Altera Modular ADC Parameters Settings 2015 0
66. r core has a single clock domain Figure 2 16 Sequencer Core High Level Block Diagram altera adc sequencer peripheral dock 5 peripheral reset Command Register Sequencer Controller src command CSR gt s Static Conversion Sequence Data Array Sequencer command up to 64 slots Controller dual ADC only Table 2 4 Sequencer Core Conversion Modes Single cycle ADC In this mode when the run bit is set ADC conversion starts from the channel that CONVEFSION you specify in the first slot e The conversion continues onwards with the channel that you specify in each sequencer slot e Once the conversion finishes with the last sequencer slot the conversion cycle stops and the ADC hard IP block clears the run bit MAX 10 ADC Architecture and Features Altera Corporation LJ Send Feedback 2 18 Sample Storage Core UG M10ADC 2015 06 11 Continuous ADC conversion you specify in the first slot sequencer slot again from the first slot of the sequence cycle e Inthis mode when the run bit is set ADC conversion starts from the channel that e The conversion continues onwards with the channel that you specify in each e Once the conversion finishes with the last sequencer slot the conversion begins e To stop the continuous conversion clear the run bit The sequencer core continues the conversion sequence until it reaches the last slot a
67. rd IP command snk FSM Wrapper Ida response sc sync handshake dual ADC only Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC 2015 06 11 Sequencer Core 2 17 Table 2 3 ADC Control Core Backpressure Behavior Backpressure Behavior Command The ADC control core asserts ready when it is ready to perform a sample conversion The ADC control core only accepts one command at a time The control core releases ready when it completes processing current command and prepares to perform the next command Once the ADC control core asserts cmd ready 1 to acknowledge the current command the Sequencer core provides the next valid request within two clock cycles If the next valid request comes after two clock cycles the ADC control core perform non continuous sampling Response The ADC control core does not support backpressure in the response interface The fastest back to back assertion of valid request is 1 us Sequencer Core The sequencer core controls the type of conversion sequence performed by the ADC hard IP You can configure the conversion mode during run time using the sequencer core registers During Altera Modular ADC or Altera Modular Dual ADC IP core configuration the sequencer core provides up to 64 configurable slots You can define the sequence that the ADC channels are sampled by selecting the ADC channel for each sequencer slot The sequence
68. re References on page 5 1 Altera Modular ADC IP Core Configuration Variants The Altera Modular ADC IP core provides four configuration variants that target different ADC use cases These configuration variants support usages from basic system monitoring to high performance ADC data streaming Configuration 1 Standard Sequencer with Avalon MM Sample Storage on page 2 10 In this configuration variant you can use the standard sequencer micro core with internal on chip RAM for storing ADC samples Configuration 2 Standard Sequencer with Avalon MM Sample Storage and Threshold Violation Detection on page 2 11 In this configuration variant you can use the standard sequencer micro core with internal on chip RAM for storing ADC samples with the additional capability of detecting threshold violation Configuration 3 Standard Sequencer with External Sample Storage on page 2 13 In this configuration variant you can use the standard sequencer micro core and store the ADC samples in external storage Configuration 4 ADC Control Core Only on page 2 13 In this configuration variant the Altera Modular ADC generates only the ADC control core Related Information Altera Modular ADC IP Core References on page 5 1 Configuration 1 Standard Sequencer with Avalon MM Sample Storage In this configuration variant you can use the standard sequencer micro core with internal on chip RAM for storing ADC samples This configuration is useful for basic system m
69. ries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA 4 2 Creating MAX 10 ADC Design UG M10ADC 2015 06 11 Creating MAX 10 ADC Design To create your ADC design you must customize and generate the ALTPLL and Altera Modular ADC IP cores The ALTPLL IP core provides the clock for the Altera Modular ADC IP core 1 2 3 4 Customize and generate the ALTPLL IP core Customize and generate the Altera Modular ADC IP core Connect the ALTPLL IP core to the Altera Modular ADC IP core Create ADC Avalon slave interface to start the ADC Related Information Customizing and Generating Altera Modular ADC IP Core on page 4 2 Parameters Settings for Generating Al
70. s C Send Feedback 2015 06 11 MAX 10 ADC Implementation Guides UG M10ADC C subscribe LJ Send Feedback You can implement your ADC design in the Quartus II software The software contains tools for you to create and compile your design and configure your device The Quartus II software allows you to set up the parameters and generate your Altera Modular ADC IP core For more information about using the Quartus II software refer to the related information Figure 4 1 High Level Block Diagram of the MAX 10 ADC Solution Altera FPGA Altera Modular ADC IP Core Avalon MM Slave ADC soft IP clock RAM Block User Design d RAM read write CSR po eaae Bidirectional and ADC digital output Sequencer state machine Altera PLL Dear dock ADChadlP Control status and data IP Core block signals to sample analog input pin one pin at a time External voltage reference pin Analog input pins Related Information MAX 10 ADC Overview on page 1 1 Quartus II Handbook Volume 1 Design and Synthesis Provides more information about using IP cores in the Quartus II software O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other count
71. s the temperature sensing channel Turn on this option if you want the IP core to read the built in temperature sensor in the ADC block The sampling rate of the ADC block falls to 50 KHz when it reads the temperature measurement After it completes the temperature reading the ADC sampling rate returns to 1 MHz For the Altera Modular Dual ADC IP core if you specify the TSD in a sequencer slot for ADCI specify NULL in the same sequencer slot number for ADC2 Enable Maximum threshold for Turn on this option if you want to set a maximum threshold value for Channel N the channel Enter Maximum Threshold for Enter the maximum threshold voltage for the channel The IP core will Channel N generate a threshold violation notification signal to indicate that the sampled data is over the threshold value that you specify MAX 10 ADC Implementation Guides Altera Corporation LJ Send Feedback UG M10ADC 4 6 Parameters Settings for Generating Altera Modular ADC or Altera Modular 2015 06 11 Enable Maximum threshold for Enter the maximum threshold temperature for the temperature sensor on chip TSD TSD tab in Celsius The IP core will generate a threshold violation notfication signal to indicate that the sampled temperature is over the temperature that you specify Enable Minimum threshold for Turn on this option if you want to set a minimum threshold value for Channel N the channel Enter Minimum
72. tera Modular ADC or Altera Modular Dual ADC IP Core on page 4 4 Parameters Settings for Generating ALTPLL IP Core on page 4 3 Completing ADC Design on page 4 7 Customizing and Generating Altera Modular ADC IP Core Altera recommends that you use the Altera Modular ADC IP core with a Nios II processor which supports the ADC HAL driver 1 Create a new project in the Quartus II software While creating the project select a device that has one or two ADC blocks In the Quartus II software select Tools gt Qsys In the Qsys window select File gt New System A clock source block is automatically added under the System Contents tab In the System Contents tab double click the clock name In the Parameters tab for the clock source set the Clock frequency In the IP Catalog tab in the Qsys window double click Processors and Peripherals gt Peripherals gt Altera Modular ADC The Altera Modular ADC appears in the System Contents tab and the Altera Modular ADC parameter editor opens In the Altera Modular ADC parameter editor specify the parameter settings and channel sampling sequence for your application In the System Contents tab in the Qsys window double click the Export column of the adc pll clock and adc pll locked interfaces to export them Connect the clock reset sink sample store csr and sample store irq signals Optionally you can use the Nios II Processor On Chip Memory and JTAG UART
73. tion of complete receipt Related Information Sample Storage Core on page 2 18 Altera Corporation C Send Feedback 5 18 ADC HAL Device Driver for Nios Il Gen 2 UG M10ADC 2015 06 11 ADC HAL Device Driver for Nios II Gen 2 The Altera Modular ADC IP core provides a HAL device driver You can integrate the device driver into the HAL system library for Nios II Gen 2 systems The Altera Modular ADC IP core provides software files that define low level access to the hardware You can use the macros definition and functions in the software files to initialize the Altera Modular ADC core Altera Corporation altera_modular_adc_sequencer_regs h this file defines the register map for the sequencer core It provides symbolic constants to access the low level hardware altera_modular_adc_sample_store_regs h this file defines the register for sample storage core It provides symbolic constants to access the low level hardware altera modular adc h include this file into your application It automatically includes the other header files and defines additional functions altera modular adc c this file implements helper functions that are defined in the header file Altera Modular ADC IP Core References C Send Feedback 2015 06 11 UG M10ADC Additional Information for MAX 10 Analog to Digital Converter User Guide A x Subscribe Send Feedback Document Revision History for MAX 10 Analog to Digital Converter User
74. y between two ADC blocks may cause data mismatch in simultaneous measurement e For simultaneous measurement use the Altera Modular Dual ADC IP core To choose the correct device refer to the MAX 10 device overview Related Information MAX 10 FPGA Device Overview Altera Corporation MAX 10 ADC Architecture and Features C Send Feedback UG M10ADC 2015 06 11 ADC Analog Input Pins 2 5 e ADC Channel Counts in MAX 10 Devices on page 1 2 ADC Analog Input Pins The analog input pins support single ended and unipolar measurements The ADC block in MAX 10 devices contains two types of ADC analog input pins e Dedicated ADC analog input pin pins with dedicated routing that ensures both dedicated analog input pins in a dual ADC device has the same trace length e Dual function ADC analog input pin pins that share the pad with GPIO pins If you use bank 1A for ADC you cannot use the bank for GPIO Each analog input pin in the ADC block is protected by electrostatic discharge ESD cell For more information refer to the device datasheet Related Information MAX 10 Device Datasheet ADC Prescaler The ADC block in MAX 10 devices contains a prescaler function The prescaler function divides the analog input voltage by half Using this function you can measure analog input greater than 2 5 V In prescaler mode the analog input can handle up to 3 V input for the dual supply MAX 10 devices and 3 6 V for the single supply

MAX 10 Analog to Digital Converter User Guide

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