Device-Specific Power Delivery Network (PDN) Tool User Guide
Contents
1. You enter the design specific information such as plane dimensions plane configuration and dielectric material used The tool calculates a plane capacitance value You can save custom values restore custom values and restore the default settings Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool 1 13 Cap Mount The Cap Mount tab shown in Figure 1 8 calculates the capacitor mounting inductance seen by the decoupling capacitor Figure 1 8 Cap Mount Tab Cap Mounting Inductance CAP Mounting Inductance Space between pads Width of pads Pitch between traces Metal thickness Height above reference plane Trace length Trace width Via radius h Via pitch Top via length Bottom via length Power plane dielectric thickness Cap mounti Cap mounting inductance Bottom Save Custom Rectore Custom Restore Default 0201 0402 0603 vos vos VOE vos VOE vos 157 157 238 238 s T 316 T x 51 4 06 0 35 2 5 Vos 47 ma 472 06 36 Symbol Unit Gap Width Pitch t h w r B thk Ltop mils mils mils mils mils 05 35 20 mils n 3 20 ESPERTI mils 411 41 6 6 mils o mils nH nH alf of dr2. d aca 1 10 Import Geometries 1 10 Proceed toiSystem Decap sro 1 10 BGA Vidi nor 1 11 Plane 1 12 Cap MOUDES A ese repr bee V RF ROI er 1 13 2 MOUs cack haces ae he ee EE SANEGA Re eS 1 14 Library me _____ __ _ 1 15 Two Terminal Decoupling Capacitors ssssssseeeeesses eee ene 1 16 Bulk Capacitors ves HOUR aia ead eer 1 16 X2Y Decoupling Gapatcitors esri esee eroe Ce hate P CELERE TU oc eae a ews 1 16 BGA Via and Plane Capacitance gt tirad resid enman pe Ken it pade 1 16 VRM Library iR RR Re nh IRE Y dees Ge Kee ee ea a d era ces 1 16 spreading IS Js Parasitics siepe keidi ti eD OE e PUEDE e eb d e bed 1 16 Dielectric Material Libraty tene eU ewe a a ee dance geri atti 1 17 User Set PEFFECTIVE aad dora aca dada d dos dee rcd d dede abd d TR E C ERR 1 17 5 eis cede 2 dupli teat 1 18 Family Device Power Rail Information eee e 1 19 Component Parameters Setting 2 1 19 Electric Parameters and Design 2 1 20 Decoupling Capacitor High Mid Frequency 1 21
3. e201 0402 Decoupliss E ESR 0 ESL aH ESR 0 ESL ESR 0 ESL oH ESR 0 ESL eH ESR 0 ESL ESR 0 F Lmat 0 001 3 ext pom ore 3 ANTA m 0 0022 0 0047 e De p DE 9 01 9 022 ETD E E E 358 398 1983 0 047 0001 J J 1000 01 pom iue Oe TE 0 47 ES EE EEE GR SEES Pee eee MTD iis Yeas Ya RI RIAM A pa pe ER A RI I A mm RIA 0003 Ma Bulk Custom BGA Via amp Plane ESR 0 ESL aH ESA 0 F mat nb Cap BGA Via Plane Cap 0805 1206 2Y Cap ESR 0 ESL aH ESR 0 eH ESR 0 ESL ESR 0 ESL 0 001 Spreading 0 Ls ignore Dielectric Materia rns 4000 6 _ Mote capacitor ESE and ESL vals have boon derind using Spice jose te venous vendors These tocds mag Ne oM aed tht wettite few c which are heres RAKE com wv ov vw Prata com wc com am ww com among other Al other defit waders are typical vasos Fou best accuracy vales mag be and saved with Custer vales Setenmined by the iron Notes to Figure 1 18 The numbers correspond to the following steps 1 2 3 4 5 1 Enter the ESR ESL and Lmn
4. ducto E RR CS CK ope duces Hite ae 1 1 PDN Decoupling Methodology Review 2 1 1 PON Circuit PRS ee due E 12 ovn 1 2 gne MM 1 4 Major Fabs ot PDN Tool iier eme eee eem PIC ee ie Ree eee Pee Eae te ate eee ebd 1 5 oystem Decap 552 esses Speedos jase dude pd 1 6 Family Device Power Sharing Scheme Selection 8 8 1 6 Power Rail Data and Power Sharing Scheme 666 cece ccc ene eens 1 7 Power Via Length and Number 6 0 6 enn 1 8 Regulator Data ees etie ta ore Its d Loup MD Ed ee ge 1 8 Rail Group Summaty erbe ee ELE EE RUP e Yea a ede tees danse 1 8 D coupling Selections creer ERR PE RENE ag Pes SUE Re er 1 8 Result Summary eee hw epe her Peta Da ep Re ci 1 8 Additonal DUftOrs cortes esconde enr LUC deed Hut utes cup eat 1 8 Recommended Flow for Deriving Decoupling for FPGA System using the System Decap Tap 1 9 rg era eC Pa E Rr Ee UE 1 9 stackup iod es RE ER EUROPEE ION UR PIA Ee qe PEE ev de ped ps t 1 10 Stack p STUD os cest pee tuu LIN III DU 1 10 Pull Stackup tenete qe aa de keener gee ei po Rang dct ond 1 10 CODSEIUCEDIAICKUD
5. 6 1 8 1 9 Frequency Hz Derive Decoupling in the Power Sharing Scenarios It is a common practice that several power rails in the FPGA device share the same power supply For example you can connect VCCIO VCCPD VCCPGM and CLKIN rails that require the same supply voltage to the same PCB power plane This can be required by the design such as in the memory interface case This can also come from the needs to reduce BOM cost You can use the System Decap tab to facilitate the decoupling design for the power sharing scenarios Refer to the to the System Decap on page 1 6 for details When deriving decoupling capacitors for multiple FPGAs sharing the same power plane each FPGA should be analyzed separately using the PDN tool For each design combine the required power rails as described above and analyze the decoupling scheme as if the FPGA was the only device on the power rail Then repeat for each of the remaining FPGAs on the board High frequency decoupling capacitors are meant to provide the current needed for AC transitions and must be placed in a close proximity to the FPGA power pins Thus the PDN tool should be used to derive the required decoupling capacitors for the unique power requirements for each FPGA on the board The power regulators must be able to supply the total combined current requirements for each load on the supply but the decoupling capacitor select
6. following table Contact 7 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Device Specific Power Delivery Network PDN Tool User Guide Info 2 Additional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and lt project name gt poft file Initial Capital Letters Indicat
7. A warning calls attention to a condition or possible situation that can cause you injury Lj The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation
8. Derive the PCB decoupling scheme The red numbers in Figure 1 19 show the field to work with in each of these steps For more information on these fields refer to Decap Selection on page 1 18 Figure 1 19 Decap Selection Tab in a Single Rail Design Design Tool V2 0 for Stratix Power Supply Summary Options R L nM VRM Sn Low BGA Vie Caicute Plane Cap Caicute Target Impedance Supply Voltege Min i mor Current Vripple Effective Frequency Ztaroet AV A Decoupling Caps Valve uF Footprint Layer Orientation QTY Cap ESR 0 5 ni Eqv Linet Legend Tote Decoupling amp Bulk Capacitors Used In Step 2 the PDN tool uses the inductance and resistance value calculated in the BGA Via tab if you choose the Calculate option for the BGA via Incorrect parameters may negatively affect the derived decoupling design These values are calculated using the parameters you entered in the BGA Via tab You must check the BGA Via tab to ensure the numbers you entered especially the number and length of the BGA power via pair matches the settings of the power rail selected in Step 1 Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 27 Design PCB Decoupling Using the PDN Tool In Step 3 you need to have
9. group in this section Select the PCB layer where the power group is located and the tool calculates the Via length using the PCB stackup information from the Stackup tab An incorrect input may result in overly pessimistic or optimistic decoupling results You must use the layer number of power rails that consumes most of the current if the power rails in the group are not located in the same layer Regulator Data Enter the regulator parameters such as DC supply voltage at VRM input switcher VRM efficiency ambient temperature and of linear VRM in this section The tool calculates input current and linear junction temperature This section provides information that helps you select the VRM module Data input in this section does not affect the decoupling Rail Group Summary You find a list of calculated key parameters such as voltage total current transient current percentage allowed voltage ripple ZyAncgr and Fgeggcrivg Of all power groups in this section Decoupling Selections You let the tool to derive the decoupling for all power groups using the Decouple all rails button You can also select the power group you want to decouple from a pull down list and click the Decouple only this group button The tool will derive the decoupling for a selected power group Result Summary You can find the list of the number and type of capacitors used for each group and the summary of all the capacitors used
10. PDN impedance profile is the impedance over frequency looking from the device side Figure 1 1 PDN Topology Lmnti Lmnt2 Cc2 et 2 a ee Decoupling CAP Model For first order analysis the voltage regulator module VRM can be simply modeled as a series connected resistor and inductor as shown in Figure 1 1 At low frequencies up to approximately 50 KHz the VRM has a very low impedance and is capable of responding to the instantaneous current requirements of the FPGA The equivalent series resistance ESR and equivalent series inductance ESL values can be obtained from the VRM manufacturer At higher frequency the VRM impedance is primarily inductive making it incapable of meeting the transient current requirement PCB decoupling capacitors are used for reducing the PDN impedance up to tens of MHz The on board discrete decoupling capacitors provides the required low impedance depending on the capacitor intrinsic parasitics Ren Cen Len and the capacitor mounting inductance Lmnin The inter planar capacitance between the power ground planes typically has lower inductance than the discrete decoupling capacitor network making it more effective at higher frequencies tens of MHz As frequency increases tens of MHz and above the PCB decoupling capacitors become less effective The limitation comes from the parasitic inductance seen wit
11. Rcrr based on the user input from related fields and displays the results in the column below The tool calculates the effective frequency for the rail selected You can also set Feffective to a frequency you select To do so you must set the Feffective option to Override and enter the frequency in the Library tab Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 21 Major Tabs of the PDN Tool Decoupling Capacitor High Mid Frequency You can select the various decoupling capacitors both two terminal and X2Y types based on footprint layer and orientation to meet the target impedance for the mid to high frequency The capacitance value for the X2Y capacitor may be different from that of the two terminal capacitor A warning message of Wrong Footprint is displayed if you choose a wrong combination of capacitance and footprint The VOE and VOS option do not affect the mounting inductance for X2Y type capacitors because their via locations are symmetric You also have the option of defining custom capacitor values 1 User4 needed for high mid frequency decoupling specific to the design You cannot change the capacitor parasitics ESR and ESL in this tab This can only be done in the Library tab Decoupling Capacitor Bulk You can select the desired bulk capacitors based on the footprint for the low to
12. mid frequency decoupling need You can only change the parasitics of the bulk decoupling capacitors and define the mounting inductance specific to the design in the Library tab You also have the option of defining custom capacitor values User5 and User6 for low mid frequency decoupling specific to the design Zerr Plot The effective impedance that the Altera device encounters is shown in Figure 1 15 Other information such as Zragcey and are also shown in the plot along with the impedance profile of components such as capacitors VRM and BGA via within the PDN system The plot is updated automatically when related parameters are changed Figure 1 15 Plot zu e Sao Impedance 0 0 01 0 001 1E 3 1E 4 TEES 1E 6 IERA 12 8 1E 9 Frequency Hz As provided in other tabs you can save and restore the final capacitor count and other settings for a specific set of assumptions There is also flexibility to revert back to default settings December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 22 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Auto Decouple You can use the Auto Decouple function to derive the desired decoupling network To use this function click Auto Decouple after entering all the required information and the tool will automatica
13. through the spreadsheet tool are intended only as preliminary estimate and not as a specification For an accurate impedance profile Altera recommends a post layout simulation approach using any of the available EDA tools such as Sigrity PowerSI Ansoft SIWave Cadence Allegro PCB PI etc Application of the Tool The purpose of the PDN tool is to help the design of a robust power delivery network for the device in the targeted device family by determining an optimum number type and value of decoupling capacitors needed for selected device power rail to meet the desired to This spreadsheet tool is useful for exploring the various what if scenarios during the early design phase without extensive and time consuming pre layout analysis PDN Decoupling Methodology Review This section describes general PCB decoupling methodology and explains in detail the two parameters Zyarcer and provided by the PDN tool for guiding PCB decoupling design December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 2 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool PDN Decoupling Methodology Review PDN Circuit Topology The PDN tool is based on a lumped equivalent model representation of the power delivery network topology Figure 1 1 shows a schematic representation of the circuit topology modeled as part of the tool The
14. Additional Buttons There are two buttons on this page Export and Restore Default Use the Export button to get a summary of system decouple resorts Click the Restore Default button to update all entries within this tab to the system default Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 9 Major Tabs of the PDN Tool Recommended Flow for Deriving Decoupling for FPGA System using the System Decap Tap To use the System Decap tap perform the following steps 1 Setup the stack up information in the Stackup tab 2 Select the Altera device family device 3 Select the decoupling scheme The tool will update the power rail connection configuration to the scheme recommended in the PCG 4 Ensure that default parameters such as power rail configuration relativity of power rails within the same power group power group layer number of power ground Via pairs DC voltage supply for VRM module or the decoupling cap location match your system and make necessary changes 5 Enter the projected current consumption of each power rail 6 Click the Decouple All Groups button to generate a decoupling scheme for all power groups listed or select the group to be decoupled from the drop down menu of the Decouple only this group cell and click the Decouple the Selected Group button 7 You may see violations if you c
15. Decoupling Capacitor Bulk nee teens 1 21 ZEFF Ini T dual 1 21 Auto Decouple s esee er RC PUEROS IUE e 1 22 Verny ea eee Ut ded 1 22 BOM 1 23 Be Arce POE ec Te Pa I tec DPI 1 24 December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide iv Contents Design PCB Decoupling Using the PDN Tool sssssssssessse 1 24 Pre Layout Instructions neri arr i eese cece bende E X RES Md dd Sees 1 24 Derive Decoupling in a Single Rail Scenario eens 1 25 Derive Decoupling in the Power Sharing Scenarios 2 1 28 Additional Information Document Revision History wis ce cena Cee ee Pee due a ee aee e v Er TET Info 1 How to Contact Alteran s saeta a a Info 1 Typographic Conventions eres etr eb A RAW ae boda md bebe wer ed eer Info 2 Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation 1 User Guide for the Device Specific ANU S T Power Delivery Network PDN Tool This user guide provides a brief overview of the various tabs in the device specific PDN tool You can quickly and accurately design a robust power deliv
16. Device Specific Power Delivery Network PDN Tool User Guide 101 Innovation Drive San Jose CA 95134 www altera com UG 01134 1 0 Subscribe 2012 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX are Reg U S Pat amp Tm Off and or trademarks of Altera Corporation in the U S and other countries All other trademarks and service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard Warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera quatity customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products 50 90012008 Services NSAI Certified Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation N DTE RYN Contents Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool OVGOEVIeW detected duced 1 1 Applicationof the ToOl er
17. V Al Q Ztarget You need to enter information for m PowerSupply Voltage min m Transient Current m Allowable Voltage Ripple Percentage a Feffective Option The percentage of transient current is signal pattern dependent Use a calculation simulation or a measurement to obtain the transient current dynamic current values You can use the Quartus II PowerPlay Power Analyzer PPPA to accurately estimate the transient current values when you import design specific activity test vectors for analysis If none of these methods are routinely available Altera recommends the values available in the Intro tab in each Device Specific PDN tool for your design You must set the Feffective option to Calculate if you want the tool to decouple to the calculated Feffective You need to set the option to override if you want the tool to decouple to the designated Feffective Feffective Will increase as the spreading inductance is reduced For a good PCB layout there is less ESL for the PCB decoupling capacitors and they are able to affect the PDN impedance at higher frequencies For a less optimal PCB layout with high spreading inductance there is more ESL for the PCB decoupling capacitors and they are less effective in affecting the PDN impedance at high frequencies Therefore Feffective is lower when parasitic inductance such as plane spreading inductance and mounting inductance is high The tool then calculates Zt
18. a good estimate of the parameters entered to derive the proper decoupling guidelines Zrarcer and Fggggcrivg Although you need to determine those guidelines based on the worst case scenario pessimistic settings result in hard to achieve guidelines and over design of your PCB decoupling For the recommended settings of the percentage of transient current and maximum allowable voltage ripple for selected power rail refer to Table 1 1 on page 1 4 In Step 4 you must adjust the number and value of the PCB capacitors in the Decoupling Capacitor Mid High Frequency and Decoupling Capacitor Bulk fields to keep the plotted below until Fggggcrivre You can derive the decoupling for the selected power rail manually You can also select the Auto Decouple button and let the PDN tool derive the decoupling scheme If you are not able to find a capacitor combination that meets your design goal you can try to change the parameters at Step 2 for example reducing the BGA via inductance used in the Calculate option by reducing the BGA via length in the BGA VIA tab and using the low option for plane spreading These changes reduce parasitic inductance and make it easier to achieve your decoupling goal To achieve the low spreading setting you must place the mid to high frequency PCB capacitors close to the FPGA device You also must minimize the dielectric thickness between the power and ground plane If you are not able to meet the Zya
19. alculate the effective via inductance based on the layout If you are in the middle of layout you can directly enter the effective loop R L via parasitics in the Library tab and choose the Custom setting under BGA Via to include the via parasitics Plane Capacitance Based on the design you can either choose to Ignore the inter planar capacitance between the power and ground plane or Calculate the plane capacitance based on the layout If you are in the middle of layout you can directly enter the plane capacitance in the Library tab and choose the Custom setting under the Plane Cap to include the plane capacitance parasitics December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 20 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Electric Parameters and Design Guidelines The PDN tool calculates ZrAgcgr based on the user inputs in this field The PDN tool also displays that is derived based on the PCB stack up and power rail information Figure 1 14 The details regarding the calculation procedure are described in on page 1 2 and Fggpgcrivg on page 1 4 Figure 1 14 Electric Parameters and Design Guidelines Target Impedance Units Value Legend Supply Voltage Min V max A 5 425 1 0 6 Transient Current Vripple Calculate MHz Feffective Ztarget A
20. d combination is chosen Figure 1 12 Figure 1 12 Device Power Rail Information Family Device Stratix V Available Devices 5SGSED6K 40 Power Supply Rail VCC Component Parameters Setting You can either enable or disable the following components of the PDN network shown in Figure 1 13 Figure 1 13 Parameter Settings for PDN Components Options L nH uF Spreading BGA Via Calculate ITI BE Calculate Table 1 3 describes the PDN components Table 1 3 Parameters of PDN Components Parameter VRM Description to disable this component select Ignore To enable the VRM parasitics select Linear Switcher or Custom Spreading BGA Via Based on the design you can select either Low Medium High or a Custom value for the effective spreading R L values that the decoupling capacitors see with respect to the FPGA You can also ignore the spreading inductance by selecting Ignore Ignoring the spreading inductance leads to an optimistic result and is not an accurate representation of the impedance profile that the FPGA sees The Ignore option helps you understand that the spreading inductance in combination with the BGA via inductance is the limiting factor from a PCB perspective to decouple the FPGA at high frequencies Be careful when choosing the Ignore option while coming up with a final capacitor count Based on the design you can choose to Ignore the BGA via component or to C
21. e keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus 1 Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b and so on such as the steps listed in a procedure Hmm Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention A question mark directs you to a software help system with related information ue The feet direct you to another document or website with related information CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING
22. e various parameters and observe the resultant impedance profile This is the main user interface to the tool This tab points to various libraries capacitor dielectric materials and so on that are called by Introduction System Decap Decap Selection Library other tabs You can change the default values listed as part of these libraries BGA Via This tab provides an interface to calculate the BGA mounting inductance based on design specific via parameters and the number of vias Plane Ca This tab provides an interface to calculate the plane capacitance based on design specific p parameters This tab provides an interface to input design specific parameters for calculating the capacitor Cap Mount mounting inductance for two different capacitor orientations Via on Side VOS and Via on End VOE X2Y Mount This tab provides an interface to input design specific parameters for calculating the capacitor mounting inductance for X2Y type capacitors BOM This tab provides a summary of the final capacitor count needed to meet the target impedance Enlarged Graph This tab provides an enlarged view of the Z profile shown in Decap Selection tab You can input design specific information in the various tabs to arrive at a very accurate PDN profile for a given power supply The following sections describe the major tabs for the tool December 2012 Altera Corporation Device Specific Power Delivery Ne
23. eas Figure 1 4 Area 1 is for the device power rail information and Area 2 is for configuring the power sharing scheme Figure 1 4 Power Rail Data and Power Sharing Scheme Section Group Regulator Separator switcher Parent Group none m gt filter Voltaae relat relat relat Enter the power rail voltage and current consumption of every power rail listed in Area 1 You must enter the total current consumption of related power rails before you can use the system decoupling function Each column in Area 2 represents a power group in your system You add or remove a power group using the Add Group or Remove Group button The first row of each group is the Regulator Separator type Set the source type for the power group and available options from the pull down list as switcher linear filter The second row is the Parent Group type The available options for this row are None and the number representing all listed power groups You input power sharing hierarchy in this column You set the power rail connection using the remaining rows The PDN tool defines the power sharing tree using the Parent Child power group A power group is a child power group if that power group attaches to another power group The other power group is the parent group in this case A parent group can have multiple child groups However a child group cannot have a child group A parent power group numbe
24. elivery Network PDN Tool User Guide 1 18 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Decap Selection The Decap Selection tab shown in Figure 1 11 is where you perform the analysis for the PCB decoupling design The user interface shown here is from the PDN tool for the Stratix IV device family Figure 1 11 Decap Selection Tab PON Design Tool 12 1 eiuf footprint Layer Orientatio i vos f o um E From Een ANE 4 1 ELEME 0 0402 vos J 3 022 7 This tab is divided into the following sections m Family Device Power Rail Information m Component Parameters Setting m Electric Parameters and Design Guidelines m Decoupling Capacitor High Mid Frequency m Decoupling Capacitor Bulk m Zerr Plot Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 19 Major Tabs of the PDN Tool Family Device Power Rail Information You select the Family Device Power rail to work in this field A pull down menu with the names of the available devices and power rails for the Altera device family selected by the tool is shown when you click the corresponding cell The tool validates the selected device power rail combination A warning is shown beneath the field if an invali
25. en the analysis is done you can print out the final profile and capacitor count to achieve the profile by clicking Print BOM on the top right corner It defaults to the default printer assigned in the File Print file by clicking Export Data December 2012 Altera Corporation menu You can also export the data as an xls Device Specific Power Delivery Network PDN Tool User Guide 1 24 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Design PCB Decoupling Using the PDN Tool Enlarged Graph In the Enlarged Graph tab you can view the enlarged Z profile plot shown in Figure 1 17 The PDN tool switches to this tab when you click on the Z profile plot in the Decap Selection tab You can go back to the Decap Selection tab when you click on the Return button Figure 1 17 Enlarged Graph Tah Gettoctrre Impedance 0 a c c am dp ctm ano cmo om Retum Design PCB Decoupling Using the PDN Tool PCB decoupling keeps PDN smaller than Zyarcerr with the properly chosen PCB capacitor combination up to the frequency where the capacitor on the package and die take over the PDN decoupling This section describes the procedure of designing PCB decoupling using the PDN tool in different power rail configurations This section also provides design examples using the Stratix IV device PDN tool Pre Layout Instructions The PDN tool provid
26. er diameter ID 10 Via pitch B Via length Number of BGA PWR GND via pairs 3B Linear inductance Llin Via inductance Lvia Via resistance Effective via inductance Lvia eff Effective via resistance Ruia eff You enter the layout specific information such as the via drill diameters via length via pitch and the number of power ground via pairs under the BGA The tool calculates the effective via loop inductance and resistance value You can save the change made to the tab restore the changes and restore the tab back to the default settings December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 12 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Plane Cap The Plane Cap tab calculates the distributed plane capacitance in microfarads uF that is developed between the power ground planes based on the parallel plate capacitor equation Figure 1 7 shows the Plane Cap tab Figure 1 7 Plane Cap Tab Save Custom Restore Custom Restore Default Planar Capacitance Symbol Unit Value Plane length Length mils 15000 Plane width Width mils 11000 Metal thickness t mils Height to 1st GND plane h1 mils 2 700 Height to 2nd GND plane h2 mils 18 600 Dielectric material 1 Dielectric material 2 Er2 Plane capacitance 1 C1 Plane capacitance 2 074 Total planar capacitance Ctotal Total sheet resistance Rtotal
27. ery network by calculating an optimum number of capacitors that meet the target impedance requirements for a given power supply Overview PCB designers must estimate the number value and type of decoupling capacitors needed to develop an efficient PCB decoupling strategy during the early design phase without going through extensive pre layout simulations Altera s Power Delivery Network PDN tool provides these critical pieces of information Because all device specific PDN tools have a similar user interface this document serves as the user guide to all Altera device specific PDN tools The device family being supported by the tool is shown on the top right corner of the major tabs of the tool in this case Stratix V Arria V Arria II GZ Cyclone V and Cyclone IV devices St For more information about Altera s general purpose PDN tool with no device support refer to the Power Delivery Network PDN Tool User Guide The PDN tool is a Microsoft Excel based spreadsheet tool used to calculate an impedance profile based on user inputs For a given power supply the spreadsheet requires only basic design information such as the board stackup transient current information and ripple specifications to calculate the impedance profile and the optimum number of capacitors to meet the desired impedance target Zyarcrr The tool also provides device and power rail specific PCB decoupling cut off frequency Ferrective The results obtained
28. es an accurate estimate of the number and types of capacitors needed to design a robust power delivery network regardless of where you are in the design phase However the accuracy of the results depends highly on the user inputs for the various parameters If you have finalized the board stack up and have access to board database and layout information you can step through the tabs and enter the required information to arrive at an accurate decoupling scheme In the pre layout phase of the design cycle when no specific information about the board stack up and board layout is known you can follow the instructions in the following sections to explore the solution space when finalizing key design parameters such as stack up plane size capacitor count capacitor orientation and so on Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 25 Design PCB Decoupling Using the PDN Tool In the pre layout phase you can ignore the Plane Cap and Cap Mount tabs and go directly to the Library tab when you do not have the layout information Figure 1 18 shows the fields in the Library tab that you will use to enter the various parameters If available enter the values shown in Figure 1 18 in the Library tab To use the default values go directly to the Decap Selection tab to begin the analysis Figure 1 18 Library Tab Fields
29. ettings Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 15 Major Tabs of the PDN Tool Library The Library tab stores all the device parameters that are referred to in the other tabs Figure 1 10 shows the Library tab Figure 1 10 Library Tab 0002 0400 0003 0 00 0004 0 600 00 000 9001 0 300 1000 ANIRWIENIRIRE REI RN R Y 190 This tab is divided into the following sections Two Terminal Decoupling Capacitors High Mid Frequency X2Y Decoupling Capacitors High Mid frequency Bulk Capacitors Mid Low Frequency BGA Via and Plane Capacitance VRM Library Spreading R L Parasitics Dielectric Material Library User Set FEFFECTIVE Stackup You can change each of the default values listed in the respective sections to meet the specific needs of your design December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 16 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Two Terminal Decoupling Capacitors The decoupling capacitors section contains the default ESR and ESL values for the various two terminal capacitors in different footprints 0201 0402 0603 0805 and 1206 You also
30. h respect to the FPGA which consists of capacitor mounting inductance PCB spreading inductance ball grid array BGA via inductance and packaging parasitic inductance All these parasitics are modeled in this PDN tool to capture the effect of the PCB decoupling capacitors accurately To simplify the circuit topology all parasitics are represented with lumped inductors and resistors despite the distributed nature of PCB spreading inductance ZTARGET According to Ohm s law voltage drop across a circuit is proportional to the current flow through the circuit and impedance of the circuit The transient component of PDN current gives rise to voltage fluctuation within the PDN which may lead to logic and timing issues You can reduce excessive voltage fluctuation by reducing PDN impedance One design guide line is target impedance Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 3 PDN Decoupling Methodology Review Zrarget is defined using the maximum allowable voltage ripple and transient current and is calculated as follows Equation 1 1 7 _ Voltagehail e 28200 TARGET 7 100 MaxTransientCurrent For example to reliably decouple 3 3 volt power that allows 5 of AC ripple and a maximum 2 A current draw 5096 of which is transient current the desired target i
31. have the option of either modifying the default values or entering your own commonly used custom values in the Custom field If you are using a capacitor with a footprint that is not available in the tool you must use the Custom field to enter the capacitor parasitics and the corresponding mounting inductance The decoupling capacitors section also provides the option for the user defined capacitors such as User1 User4 You can define the ESR and ESL parasitics for the various footprints and enter the corresponding capacitor value in the Decap Selection tab Choose the corresponding footprint when defining the capacitor values Bulk Capacitors The bulk capacitors section contains the commonly used capacitor values for decoupling the power supply at mid low frequencies You can change the default values to reflect the parameters specific to the design X2Y Decoupling Capacitors The X2Y decoupling capacitors section contains the default ESR and ESL values for the various X2Y capacitors in different footprints 0603 0805 1206 and 1210 You also can replace the default ESR and ESL values with your own commonly used custom values BGA Via and Plane Capacitance The BGA via and plane capacitance section provides an option to directly enter the values for effective via loop inductance under the BGA and plane capacitance during the pre layout phase when no design specific information is available If you have access to design specific i
32. heck the impedance profile of the decoupling scheme derived in the System Decap tab located in the Decap Selection tab This is because the protocol used in System Decap tab has optimizations for power sharing scenario Stackup Enter the PCB stackup information of your design in the Stackup tab shown in Figure 1 5 This tab updates related data in the Via Plane Cap Cap Mount and the X2Y Mount tabs You also use the stackup information in this tab for the System decap tab Brief instructions are provided at the beginning of the tab Follow the instructions to fill in the content for this tab Figure 1 5 Stackup Tab Stackup Generation Flow This sheet is for entering board stsckup information t will generate most of the dats n BGA_Via Plane Cap Cap Mount and X2Y_Mount sheets all cels in these sheets with yellow background have their values derived from the data in here You can stili manually update these sheets However the amount of data entry and calculations you have to do is much smaller if you use this sheet Instructions 1 Enter basic board data in Stackup Data table Number of Layers and Stackup Configuration directly affect final stackup n Full Stackup table 2 Enter thickness values for every layer in Stackup Stub 3 Construct Stackup The ful stackup wil be shown in Full Stackup table using Number of Layers Stackup Configuration and Stack Stub dats 4 Manually adjust Thickness and Dk material in Ful
33. her than Reducing PDN parasitic inductance and increasing the isolation between the FPGA device and noise source reduces this risk You must perform a transfer impedance analysis to clearly identify any noise interference risk Major Tabs of the PDN Tool Figure 1 2 shows the tabs of the PDN tool spreadsheet Table 1 2 describes the PDN tool tabs Figure 1 2 Tabs in the PDN Tool 41 User2 Custom 1 TOP vos 0 42 2 Duetai m MOS n 7 46 M M Release Notes Introduction System Stackup Decap Selection Library Va Plane Cap Cap Mount X2Y Mount Enlarged Graph Ready 2 jg a 21 100 Table 1 2 Tabs in the PDN Tool Tab Description Release Notes This tab provides the legal disclaimers the revision history of the tool and the user agreement This tab shows the schematic representation of the circuit that is modeled as part of the PDN tool The tab also provides related information such as a quick start instruction recommended settings for some power rails and a brief description of decoupling design procedures under different power supply connection schemes This tab provides an interface to enter the user power sharing scheme for selected a FPGA device and derive the decoupling for the device based on the input Stackup This tab provides an interface to enter user stackup information into the PDN tool This tab provides an interface to input th
34. ill size inductance Top December 2012 Altera Corporation The capacitor mounting calculation is based on the assumption that the decoupling capacitor is a two terminal device The capacitor mounting calculation is applicable to any two terminal capacitor with the following footprints 0201 0402 0603 0805 and 1206 You enter all the information relevant to your layout and the tool provides a mounting inductance for a capacitor mounted on either the top or bottom layer of the board Depending on the layout you can choose between VOE Via on End or VOS Via on Side to achieve an accurate capacitor mounting inductance value If you plan to use a footprint capacitor other than a regular two terminal capacitor or X2Y capacitor for decoupling you can skip the Cap Mount tab and directly enter the capacitor parasitics and capacitor mounting inductance in the Library tab under the Custom field in the Decoupling Cap section of the library As with the other tabs you can save the changes made to the tab restore the changes and restore the tab back to the default settings Device Specific Power Delivery Network PDN Tool User Guide 1 14 X2Y Mount Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool The X2Y Mount tab shown in Figure 1 9 calculates the capacitor mounting inductance seen by the X2Y decoupling capacitor Figure 1 9 X2Y Mount Tab X2Y Cap Moun
35. ing the capacitors closer to the FPGA from an electrical standpoint m Minimizing via perforations in the power ground sandwich in the current path from the decoupling caps to the FPGA device Due to layout and design constraints the PDN design may not be optimal In this case you can choose either a Medium or High value of spreading R and L You also have the option of changing the default values or using the Custom field listed in the library specific to the design Dielectric Material Library The dielectric materials section lists the dielectric constant values for the various commonly used dielectric materials These values are used in the plane capacitance calculations listed under the Plane Cap tab You can change the values listed in this section If you change the default values listed in the various sections in the Library tab you can save the changes by clicking Save Custom You can restore the default library by clicking Restore Default located at the top right hand corner of the Library page You can also restore the saved custom library by clicking Restore Custom User Set You must decouple to a higher than what is calculated for the power rails of some Altera device families In this case you must set the Fggggcrivg option to Override in the Decap Selection tab and the PDN tool will then use the Frrrrctive value entered here December 2012 Altera Corporation Device Specific Power D
36. ions should be analyzed on a single FPGA basis Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation JA DTE RA Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes m Updated for Stratix V Arria V Arria II GZ Cyclone V and Cyclone IV device use and published with new part number m Updated the Ferrective section m Added the User Set FEFFECTIVE section m Added the System Decap section m Added the Stackup section 10 Updated the Family Device Power Rail Information section December 2012 New Updated the Electric Parameters and Design Guidelines section PN a Added the Auto Decouple section m Added the Verify Solution section m Added the Enlarged Graph section m Updated the Derive Decoupling in a Single Rail Scenario section m Updated the Derive Decoupling in the Power Sharing Scenarios section m Updated Figure 1 2 Figure 1 10 Figure 1 11 Figure 1 12 Figure 1 14 and Figure 1 18 September 2012 11 Updated the Derive Decoupling in the Power Sharing Scenarios section July 2009 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the December 2012 Altera Corporation
37. l Stackup table if required 5 Select target and reference power planes in Pwr Planes column of Full Stackup table These affect planar capacitance values in Plane Cap sheet 6 Cick Import Geometries to import the stackup data to all the other sheets that require t BGA Plane Cap Cap Mount and X2Y Mount 7 Switch to System Decap sheet to do decoupling Construct Stack up Import Geometries Proceed to System December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 10 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool The Stackup tab consists of the following sections m Stackup Data m Stackup Stub m FullStackup Stackup Data Enter board dimension data and other parameters such as board dimension board stackup settings power via and dielectric material in the Stackup Data section Stackup Stub The content in this section is updated based on the settings in Stackup Configuration in the Stackup Data section Enter the thickness of the metal dielectric material for each layer in this section The stackup shown in this section is used as the basic unit to construct the complete PCB stackup Full Stackup This section lists the complete stackup of your board You can modify content in the section to better match your board design The last column in the section is PWR plane types In a single rai
38. l analysis case assign the layer where the power rail is located as target and the ground layer that the power rail refers to as reference The Stackup tab contains the following buttons m Construct Stackup m Import Geometries m Proceed to System Decap Construct Stackup Click the Construct Stackup button and the tool populates the Full Stackup section to the number of layers defined in the Stackup Data section using the blocks listed in the Stackup Stub section Import Geometries Click the Import Geometries button and the tool updates geometry parameters in the BGA Via Plane Cap Cap Mount and X2Y Mount tabs using your input from the Stackup Data section The tool also checks that the PWR plane column in the Full Stackup section has only one target layer and provides a warning for this error Proceed to System Decap After you click the Proceed to System Decap button you will proceed to System Decap tab Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 11 Major Tabs of the PDN Tool BGA Via The BGA Via tab calculates the vertical via loop inductance under the BGA pin field Figure 1 6 is a snapshot taken from the tool Figure 1 6 BGA Via Tah HGA Via Inductance Save Custom Restore Custom Restore Default o0 BGA Via Inductance Symbol Value Via drill outer diameter oD Via drill inn
39. lly select decoupling capacitors to meet the set based on the information you provide Verify Solution You can use the Verify Solution function to check if your design meets the decoupling requirement The tool calculates PDN impedance up to the and warns you about any violations found Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool Figure 1 16 shows the BOM tab Date 3 27 2008 Time 39 18 39 Export Data Print BOM 10 Impedance 2 4 e 1 23 Figure 1 16 Tab Feffective 2671 MHz Z target 0 0077 0 0 L nH uF RM Type 0 0010 10 0000 Spreading 0 0005 0 0150 BGA Via 0 0004 0 0180 Plane Cap 0 0010 0 0038 Total Capacitor Count ot 7 0 001 res 1E 3 1 4 1 5 1E 6 1E 7 1 8 1 9 Frequency Hz Beport Summary Item alue QTY Footprint Supply 09 Volts Imaz 7 Amps poe ee I transient 50 x EE ee ripple 3 x p Ire Coon OO Fw NH 047 9 x2v E ee Sas ae ae ___47 2 DEREN ae ee LEES aes aa E 330 7 umm es es ne Se SS ae Wh
40. mpedance is Equation 1 2 3 3 0 05 To accurately calculate the Zi for any power rail the following information must be known m Themaximum transient current requirements for all devices in the system that are powered by the power rail under consideration You can obtain this information from manufacturers of the respective devices You can calculate the maximum transient current of a device using the maximum total current and the transient current percentage 57 The percentage of transient current is signal pattern dependent It changes as the output signal pattern varies for drivers using the power rail You need to choose the value that represents the worst case scenario of the power rail For information about recommended settings refer to the table in the Introduction tab of the PDN tool Table 1 1 on page 1 4 is from the PDN tool for a Stratix IV GX device It lists the Stratix IV GX default power supply voltage the recommended settings of the transient current percentage and the allowable voltage ripple for power rails gt You can obtain accurate estimations on the maximum total current for Altera devices using the Altera PowerPlay Early Power Estimator EPE tool or the Quartus II PowerPlay Power Analyzer tools You can download the EPE tool for your target Altera device from the PowerPlay Early Power Estimator EPE and Power Analyzer December 2012 Altera Corporation Device Specific Power Delivery Network PDN To
41. nformation you can ignore this section and enter the design specific information in the Plane Cap and BGA Via tabs that calculate the plane capacitance and the BGA via parasitics respectively VRM Library The VRM section lists the default values for both the linear and switcher regulators You can change the VRM parasitics listed under the linear switcher rows or add the custom parasitics for the VRM relevant to the design in the Custom field Spreading R L Parasitics The spreading L library provides various options for the default effective spreading inductance values that the decoupling capacitors see with respect to the FPGA based on the quality of the PDN design You can choose a Low value of effective spreading inductance if you have optimally designed your PDN Network Optimum PDN design involves implementing the following design rules m PCB stackup that provides a wide solid power ground sandwich for a given supply with a thin dielectric between the planes This minimizes the current loop which reduces the spreading inductance The thickness of the dielectric material between the power ground pair directly influences the amount of spreading inductance that a decoupling cap can see with respect to the FPGA Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 17 Major Tabs of the PDN Tool m Plac
42. ol User Guide 1 4 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool PDN Decoupling Methodology Review m The maximum allowable AC ripple on the power rail as a percentage of the supply voltage The maximum allowable AC ripple varies for different power rails For information about the recommended maximum allowable AC ripple for power rails refer to the table in the Introduction tab of the PDN tool Table 1 1 shows ripple information for the power rails of Stratix IV GX devices Table 1 1 Settings for the Stratix IV GX Device Power Rails Note 1 vey Mma ie ait Cat gy vcc 0 9 V 5 50 Core 12V 30V 5 50 1 0 Bank VCCPD 25V 5 50 Pre Drivers PLL 25V 3 20 PLL Analog VCCD PLL 09V 3 20 PLL Digital CLKIN 25V 5 50 Diff Clock Input VCCR 14V 3 30 XCVR RX Analog VGCT 11V 3 30 XCVR TX Analog VCCA 30V 5 10 ee GXB 15V 3 10 XCVR 1 0 Buffer Block VCCL_GXB 11V 3 20 XCVR Clock Block VCCHIP 09V 5 50 PCIE Hard IP Digital VCCPT 15V 3 20 eee Powar VCCAUX 25V 3 20 De P RS Note to Table 1 1 1 For more information about power rail functions refer to the pin connection guidelines for the selected device family FEFFECTIVE As shown in Figure 1 1 on page 1 2 a capacitor reduces PDN impedance by providing a least impedance route between power and ground Impedance of a capacit
43. or at high frequency is determined by its parasitics ESL and ESR For a PCB mount capacitor the parasitics include not only the parasitic from the capacitors themselves but also the parasitics associated with mounting PCB spreading and packaging Therefore PCB capacitor parasitics are generally higher than those of on package decoupling capacitor and on die capacitance Decoupling using PCB capacitors becomes ineffective at high frequency Using PCB capacitors for PDN decoupling beyond their effective frequency range brings little improvement to PDN performance and raises the bill of materials BOM cost To help reduce over design of PCB decoupling this release of the PDN tool provides a suggested PCB decoupling design cut off frequency Fgppecrve as another guideline It is calculated using the PCB package and die parasitics You only need to design PCB decoupling that keeps Zgrr under ZrarceT Up to FEppECTIVE Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 5 Major Tabs of the PDN Tool 57 Feprecrive may not be enough when the Altera FPGA device shares a power rail with another device The noise generated from other device propagates along the PDN and affects FPGA device performance The frequency of the noise is determined by the transfer impedance between the noise source and the FPGA device and can be hig
44. r is required for the child group The parent group number of a parent power group is assigned to None because the group has no parent group The available options are m Device rail does not connect to the power group m X Device rail connects to the power group m X related Device rail connects to the group and its activity is related to other rails that connect to the same group for VCCIO and VCCPD rails You must select x related if that VCCIO VCCPD power rail is related to other rails within the same power rail group December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool 57 Two IO rails are related if their output activities are in sync For example when two VCCIO rails are assigned to the same memory interface The maximum current will usually be reached at the same time for these related rails As the result the total current of related rails equals the sum of current of all shared rails The total current of unrelated rails is calculated using the root mean square RMS method The PDN tool sets the default power rail sharing configuration based on the selected Altera recommended power sharing scheme listed above Make changes to better match your design Power Via Length and Number You set the power Via length and number of Power Ground Via pair for each power
45. rcrr requirement with the above changes the PDN in your design may have reached its physical limitation under the parameters entered in Step 3 You need to go back to Step 3 and re examine these parameters to check if they are over pessimistic The design shown in Figure 1 20 is a decoupling example for S4GX230KF40 VCC power rail Assume that the minimum voltage supply is 0 9 V Imax 15 7 A transient current is 50 of Imax and the maximum allowable ripple 15 3 of supply voltage The Vcc rail has 50 power BGA vias The length of BGA via is assumed to be 60 mil December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 28 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Design PCB Decoupling Using the PDN Tool The PDN tool calculated that is 0 0077 and 15 24 91 MHz Figure 1 20 shows one of the capacitor combinations that you can select to meet the design goal Figure 1 20 is the enlarged view of the Zgpp plot As shown in the plot remains under up to There are many combinations but the ideal solution is to minimize the quantity and the type of capacitors needed to achieve a flat impedance profile below the Zyarcer Figure 1 20 Enlarged Plot of Zeff Using the Figure 1 16 Design 100 NI lt gt e Impedance 0 7 0 001 d 1 3 1 4 1 5 1
46. t values for the capacitors under the Custom field 2 Enter the effective BGA via loop parasitics for the power supply being decoupled 3 Enter the plane capacitance seen by the power ground plane pair on the board for the power supply under Plane Cap 4 Enter the VRM parasitics if available under the Custom row b Enter the effective spreading inductance seen by the decoupling capacitors in Custom row Derive Decoupling in a Single Rail Scenario A power supply connects to only one power rail on the FPGA device in a single rail scenario The PDN noise is created by the transient current of the single rail You determine Zrarcer and based on the parameters related to the selected rail only The PDN tool provides two ways to derive a decoupling network You can set up the tool with the information needed and let the tool derive the PDN decoupling for your system You can also manually enter the information and derive decoupling manually December 2012 Altera Corporation Device Specific Power Delivery Network PDN Tool User Guide 1 26 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Design PCB Decoupling Using the PDN Tool You must follow the steps below to derive the desired capacitor combination 1 Select the device power rail to work with 2 Select the parameter setting for the PDN components 3 Enter the electric parameters to set ZyAgcgr and 4
47. ting Inductance A B vias A via pair B via pair ctr ctr spacing lt Y axis ctr ctr lt gt G Vias G1 G2 ctr ctr spacing Save Custom G A B vias spacing G1 G2 to A G1 G2to B Refer to figures below for detailed pad layout and dimensions Mounting inductance values for gt 13 2mils are extrapolated X2Y CAP Mounting Inductance Metal Thickness t Height above reference plane h Pad to Via trace width W Via radius half of drill size r Center to Center Spacing G1 62 Vias mils Center to Center Spacing A Vias Long Axis spacing between G1 G2 and Top Via Length 1 Bottom via length C2 Power plane dielectric thickness thk X2Y Cap mounting inductance Top Units 0603 mils mils mils mils mils Vias mils X2Y Cap mounting inductance Bottom n ha jajo sms o j jj IN en o w e o olea olo o olo Y o Lo On Restore Custom 1206 1210 m e e 120 120 301 160 0 160 0 30 01 Restore Default You enter all the information relevant to your layout and the tool provides mounting inductance for a X2Y capacitor mounted on either the top or bottom layer of the board As with the other tabs you can save the changes made to the tab restore the changes and restore the tab back to the default s
48. twork PDN Tool User Guide 1 6 Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool Major Tabs of the PDN Tool System Decap You can determine the decoupling of selected FPGA devices based on the power sharing scheme entered in the System Decap tab shown in Figure 1 3 The System Decap tab is divided into the following sections Family Device Power sharing scheme selection Power rail data power sharing configuration Via length and number of via pair Regulator data Rail group summary Decoupling selection Result summary wo Sw gU gx co der d Additional buttons Figure 1 3 System Decap Tah Family Device Power Sharing Scheme Selection Select the Family Device Power sharing scheme in this section using the pull down list of a selected cell The tool updates the list of the power rails and power sharing scheme in the power rail data configuration section based on your selection The tool also updates contents in power rail power sharing configuration section accordingly Device Specific Power Delivery Network PDN Tool User Guide December 2012 Altera Corporation Chapter 1 User Guide for the Device Specific Power Delivery Network PDN Tool 1 7 Major Tabs of the PDN Tool Power Rail Data and Power Sharing Scheme Enter the power supply voltage current consumption of each power rail and setup device power sharing scheme in this section This section is divided into two ar
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