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1. FPGA Pin Net Name Quad Connector AF36 MGTREFCLKO 103 N 103 J43 AD35 MGTREFCLK1_103_P 103 J43 AD36 MGTREFCLK1_103_N 103 J43 AB35 MGTREFCLKO 104 P 104 44 AB36 MGTREFCLKO 104 N 104 44 Y35 MGTREFCLKI 104 P 104 44 Y36 MGTREFCLKI 104 N 104 J44 V35 MGTREFCLKO 105 P 105 JA5 V36 MGTREFCLKO 105 N 105 J45 T35 MGTREFCLK1_105_P 105 J45 T36 MGTREFCLKI 105 N 105 JA5 ANS8 MGTREFCLKO 112 P 112 J46 AN7 MGTREFCLKO 112 N 112 J46 AH10 MGTREFCLKI 112 P 112 J46 AH9 MGTREFCLKI 112 N 112 J46 AF10 MGTREFCLKO 113 P 113 J47 AF9 MGTREFCLKO 113 N 113 J47 AD10 MGTREFCLK1_113_P 113 J47 AD9 MGTREFCLKI 113 N 113 J47 AB10 MGTREFCLKO 114 P 114 48 AB9 MGTREFCLKO 114 N 114 J48 Y10 MGTREFCLKI 114 P 114 J48 Y9 MGTREFCLK1_114_N 114 J48 V10 MGTREFCLKO 115 P 115 49 V9 MGTREFCLKO 115 N 115 J49 T10 MGTREFCLKI 115 P 115 49 T9 MGTREFCLKI 115 N 115 J49 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 37 Chapter 1 ML628 Board Features and Operation Z XILINX USB to UART Bridge Figure 1 2 callout 20 Communications between the ML628 board and a host computer are through a USB cable connected to J9 Control is provided by U26 a USB to UART bridge Silicon Laboratories CP2103 Table 1 21 lists the pin assignments and signals for the USB connector J9 Table 1 21 USB Type B Connector Pin Assignments and Signals J9 Pin Signal Name Descriptio
2. FPGA Pin Net Name FMC Pin AR13 FMC2 HA09 N E10 AV7 FMC2 HA10 P K13 AW6 FMC2 HA10 N K14 AP11 FMC2_HA11_P JA2 ARII FMC2 N J13 AM15 FMC2 HA12 P F13 ANI4 FMC2 HA12 N F14 13 FMC2 13 P E12 AN12 FMC2_HA13_N E13 AU9 FMC2 HA14 P J15 AV8 FMC2 HA14 N J16 AJ16 FMC2 HA15 P F16 AJ15 FMC2 HA15 N F17 AK17 FMC2_HA16_P El5 AK16 FMC2_HA16_N E16 AP13 FMC2 HA17 CC P K16 AR12 FMC2_HA17_CC_N K17 AKI5 FMC2_HA18_P J18 AL15 FMC2 HA18 N J19 AL14 FMC2_HA19_P F19 AM14 FMC2 HA19 N F20 AW1 FMC2 HA20 P E18 AVI FMC2 HA20 N E19 BD5 FMC2 21 P K19 BD4 FMC2_HA21_N K20 AY2 FMC2 HA22 P J21 BA2 FMC2_HA22_N J22 BB2 FMC2_HA23_P K22 BB1 FMC2 HA23 N K23 BC13 FMC2 HBOO CC P K25 BC12 FMC2 HB00 CC N K26 BC16 FMC2 HB01 P J24 BD15 FMC2 801 N J25 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX ML628 Board User Guide Table 1 25 VITA 57 1 FMC2 HPC Connections at J441 Cont d FPGA Pin Net Name FMC Pin BC17 FMC2 HBO2 P F22 BD16 FMC2 HB02 N F23 AY17 FMC2 HBO3 P E21 AY16 FMC2 HBO3 N E22 BD14 FMC2 HBO4 P F25 BD13 FMC2 HBO4 N F26 BD11 FMC2_HB05_P E24 BD10 FMC2 HBO5 N E25 BB16 FMC2 HBO6 CC P K28 BB15 FMC2 HB06 CC N K29 AV16 FMC2 HB07 P J27 AW16 FMC2 HB07 N J28 BB12 FMC2_HB08_P F28 BC11 FMC2_HB08_N F29 AY18 FMC2_HB09_P E27 BA18 FMC
3. Z2 Pp FU IS FU Hg FU a a hg RX2 11 RX3 11 RX3 11 RX3 11 RX3 11 RX3 11 RX3 11 RX3 11 RX3 11 RX3 100 N RX3 100 P RX3 101 N RX3 101 P RX3 102 N RX3 102 P RX3 103 N RX3 103 P RX3 104 N RX3 104 P RX3 105 N RX3 105 P RX3 106 N RX3 106 P RX3 107 N RX3 107 P RX3 108 N RX3 108 P e FU 12_N 12_P w w FU IS IS FU LOC d LOC d LOC LOC ii LOC ui LOC i LOC d LOC LOC il LOC d LOC 4 LOC LOC b LOC T LOC ei LOC T LOC i LOC ui LOC w pa LOC LOC d LOC LOC d LOC N LOC i LOC ii LOC ki LOC d LOC LOC S LOC LOC d LOC LOC d LOC H LOC d LOC i LOC T LOC ud LOC d LOC N LOC 4 LOC T LOC d LOC i LOC dd LOC d LOC d LOC ki LOC x LOC LOC N LOC T LOC 5 LOC N LOC LOC LOC gt LOC RX3_11 OY U U Z U 7 U y U 00 S U y y Es y y a U 00 MW U i U U U S y y n U U y y U y U U d U 00 y y WE U U U y U y y y U y Mp U U BB397 BB40 AT39 ATAO AJ37 AJ38 AF39 AF40 AB39 AB40 V39 V40 N38 N37 H40 H39 B40 B39 AJ8 AJ7 AF6 AF5 AB6 AB5 06 Mar NAN N8 H6 B5 Bo BA41 BA42 4AP39 AP40 4AK39 AK40 AE37 AE38
4. SuperClock 2 Module GTX Transceiver Power Module GTH Transceiver mm Power Module UG771 1 01 022211 Figure 1 1 ML628 Board Block Diagram Detailed Description Figure 1 2 shows the ML628 board described in this user guide Each numbered feature that is referenced in Figure 1 2 is described in the sections that follow Note Figure 1 2 is for reference only and might not reflect the current revision of the board 8 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX o Os Q O vOe Os m 10 VIRTEXU XILINX 1a Main power switch SW1 9 1b 12V Mini Fit connector J122 10 1c 12V ATX connector 0141 11 1d Power regulation jumpers J30 J32 J61 J102 J104 J105 J129 12 te Regulation inhibit J289 18 1f External power supply jacks 14 1g TI PMBus connector J14 15 1h GTX transceiver power supply module 16 11 GTH transceiver power supply module 17 1j Active cooling power connector J221 18 2 FPGA configuration connector 01 19 3 PROG B push button active Low SW5 20 4 DONE LED DS6 21a 5 INIT LED DS20 21b 6 System ACE controller U25 22 7 System ACE reset active Low SW2 23 8 Configuration address DIP switch SW3 Detailed Description UG771 ci 02 020314 JTAG isolation jumpers J22 J23 J195 J196 200 MHz 2 5V LVDS oscillator U7 Single ended SMA global clock input J171 J172 Differential SMA global clock inp
5. U1 C28 NET USER IO 4 LOC U1 C27 NET USER IO 5 LOC U1 A29 NET USER IO 6 LOC U1 A28 NET USER PB1 LOC U1 A27 NET USER PB2 LOC U1 B27 NET USER 881 LOC U1 J29 NET USER SW2 LOC U1 J28 NET USER SW3 LOC U1 R27 NET USER SW4 LOC U1 T27 NET USER SW5 LOC U1 H29 NET USER SW6 LOC U1 H28 NET USER SW7 LOC UL L29 NET USER SW8 LOC U1 L28 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendix C ML628 Master UCF Listing XILINX 70 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Appendix D References Additional information relevant to Virtex amp 6 devices the ML628 Virtex 6 FPGA GTX and GTH transceiver characterization board and intellectual property is available in the documents listed here UG806 ML628 IBERT Getting Started Guide DS150 Virtex 6 Family Overview D5152 Virtex 6 FPGA Data Sheet DC and Switching Characteristics UG360 Virtex 6 FPGA Configuration User Guide UG361 Virtex 6 FPGA SelectIO Resources User Guide UG362 Virtex 6 FPGA User Guide Clocking Resources UG364 Virtex 6 FPGA Configurable Logic Block User Guide UG365 Virtex 6 FPGA Packaging and Pinout Specifications UG366 Virtex 6 FPGA GTX Transceivers User Guide UG370 Virtex 6 FPGA System Monitor User Guide UG371 Virtex 6 FPGA GTH Transceivers User Guide DS581 XPS External Peri
6. AA37 AA38 SUR LU U38 M40 M39 J38 A D40 D39 AK6 AK5 AE8 AE7 AA8 AAT7 U8 SO MB 66 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET MGTRX3 116 P LOC U1 M6 NET MGTRX3 117 N LOC U1 J7 NET MGTRX3 117 P LOC U1 J8 NET MGTRX3 118 N LOC Ul D5 NET MGTRX3 118 P LOC U1 D6 NET MGTTXO 100 N LOC U1 BB43 NET MGTTXO 100 P LOC U1 BB44 NET MGTTXO 101 N LOC Ul AU41 NET MGTTXO 101 P LOC UL AUA2 NET MGTTXO 102 N LOC Ul AN41 NET MGTTXO 102 P LOC UL AN42 NET MGTTXO 103 N LOC Ul AJ41 NET MGTTXO 103 P LOC U1 AJ42 NET MGTTXO 104 N LOC U1 AE41 NET MGTTXO 104 p LOC U1 AE42 NET MGTTXO 105 N LOC U1 AA41 NET MGTTXO 105 P LOC U1 AAA2 NET MGTTXO 106 N LOC Ul T44 NET MGTTXO 106 P LOC Ul T43 NET MGTTXO 107 N LOC UL L42 NET MGTTXO 107 P LOC Ul L41 NET MGTTXO 108 N LOC Ul F44 NET MGTTXO 108 P LOC Ul F43 NET MGTTXO 112 N LOC U1 AN4 NET MGTTXO 112 P LOC U1 AN3 NET MGTTXO 113 N LOC U1 AJ4 NET MGTTXO 113 P LOC U1 AJ3 NET MGTTXO 114 N LOC U1 AE4 NET MGTTXO0 114 P LOC Ul AE3 NET MGTTXO 115 N LOC U1 AA4 NET MGTTXO 115 P LOC U1 AA3 NET MGTTXO 116 N LOG UL TI N
7. CM CTRL 13 CM CTRL 14 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC U y U n U Mp U y U y a y U y y y y 00 U y U y I U U U U N28 P28 K28 LATE K27 K26 P26 R26 AC33 AP33 R31 AP34 AN33 313257 Ber S G26 G25 H23 1237 1237 25 7 D26 E26 D25 E25 M25 M24 A25 B25 3 225 3 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 57 Appendix C ML628 Master UCF Listing XILINX J E Ed Dd bd QQ b bd Ld bd bd m C 5 5 5 C 5 5 C C C C Zaz zZazZzZZZZZIZIZIZIZIZIIZIZIZIZIZIZIZIZZ IZIZIZIZIZIZIZIZIZIZIZIZIZIZZIZZ IIZZIZIZIZIZIZIZIZZ SS SS S Z C C C C C C C C C C C C 5 C C E C C C C El C C C El C C C C C m 5 5 5 C C C C C C C Ej Dd bd Ld bd bd Ed D Dd pd Ed bd Ej D Dd Ltd Ed bd bd Dd Dd bd Dd HE bd Dd bd bd D IIe Ed bd bd od pd CM CTRL 15 LOC CM CTRL 16 LOC CM CTRL 17 LOC CM CTRL 18 LOC CM CTRL 19 LOC CM CTRL 20 LOC CM CTRL 21 LOC CM CTRL 22 LOC CM CTRL 23 LOC CM
8. LOC U1 AM30 NET FMC1 8603 P LOC U1 AL30 NET FMC1 HBO4 N LOC U1 BC32 NET FMC1 HBO4 P LOC U1 BB32 NET FMC1 HBO5 N LOC U1 BA32 NET FMC1 HBO5 P LOC U1 AY32 NET FMC1 HBO6 CC N LOC U1 AV31 NET FMC1 HBO6 CC P LOC U1 AU31 NET FMC1 HBO7 N LOC U1 AM32 NET FMC1 HBO7 P LOC Ul AM31 NET FMC1 HBO8 N LOC Ul AY31 NET FMC1 HBO8 P LOC U1 AW31 NET FMC1 HB09 N LOC U1 AT32 NET FMC1 HBO9 P LOC Ul AR31 NET FMC1_HB10_N LOC U1 AL32 NET FMC1 HB10 P LOC Ul AK31 NET FMC1 HB11 N LOC U1 AR30 NET FMC1 HB11 P LOC U1 AP30 NET FMC1 HB12 N LOC U1 AU30 NET FMC1 HB12 P LOC U1 AT30 NET FMC1 HB13 N LOC U1 AJ31 NET FMC1 HB13 P LOC U1 AJ30 NET FMC1 HB14 N LOC U1 AV32 NET FMC1 HB14 P LOC U1 AU32 NET FMC1 HB15 N LOC U1 AR32 NET FMC1 HB15 P LOC U1 AP31 NET FMC1 HB16 N LOC U1 AN32 NET FMC1 HB16 P LOC U1 AN31 NET FMC1_HB17_CC_N LOC U1 AK30 NET FMC1 HB17 CC P LOC U1 AJ29 NET FMC1 HB18 N LOC U1 AL33 NET FMC1 HB18 P LOC U1 AK32 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendix C ML628 Master UCF Listing XILINX DD DD SS S S S S S SS SGS SS SS SS S SS S SS SS SS S SGS S SS S SS SS SS S SS SS SS SS 2424 E Dd Ed E bd b Ed D Dd bd Ed bd bd D Dd Ltd Ed Dd bd bd Dd bd bd bd b bd Dd Ed bd bd bd bd pd Ed b
9. The following table shows the revision history for this document Date Version Revision 03 23 2011 1 0 Initial Xilinx release 07 06 2011 1 0 1 Revised link in Appendix D on page 71 to point to the version of UG806 supporting ISE software version 13 2 02 19 2014 11 Updated disclaimer and copyright Added callouts 2 3 and 10 to Figure 1 2 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Table of Contents REVISION S TE YE i l l a A d dog e data 2 Preface About This Guide Guide Contents 46 6646 5 Conventlofs es l e Beat ae ed race td eu dor diia 5 Ivpo raphi ali ou eere pt hte ere tbe beso eem 5 Online Doct ment Si esses se des a eu dt da ar SR em 6 Chapter 1 ML628 Board Features and Operation ML628 Board 8 5 7 Detailed Desi phin skarnat kaa ate Ad aet dead die ka d 8 Power Management id bred eere e idus 10 Board Power and Switch eseeee eee eee 10 Onboard Power Regulation e eee eee nee nee een 11 GTH Transceiver Power Module eee eee eee ern 13 GTX Transceiver Power Module eee eee eee 14 Active Heatsink Power Connector rene e none en has 15 FPGA Configuration lt a ga die ata eee ER eek P en ce pr ad a a 17 PROG B Push Button
10. y y W U y y U U y U 00 U U y U U U y U y U y U t U U U d T N23 BA38 BA37 AU38 AU37 AN38 AN37 AF36 ARID 7 AB36 AB35 V36 i e AN7 AN8 AF9 AF10 AB9 AB10 MON V10 AW38 AW3 7 AR38 AR37 AH36 AH35 AD36 AD35 2Y36 SY De T36 7035 AH9 AH10 AD9 AD10 MOU Y10 T9 110 R42 RA1 AD sal B42 E41 RS R4 SIS JA ES SEAT BD39 BD40 AY39 3 AY40 AL37 64 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET MGTRXO 102 P LOC U1 AL38 NET MGTRXO 103 N LOC U1 AH39 NET MGTRXO 103 P LOC U1 AH40 NET MGTRXO 104 N LOC U1 AD39 NET MGTRXO 104 P LOC U1 AD40 NET MGTRXO 105 N LOC U1 Y39 NET MGTRXO 105 P LOC Ul Y40 NET MGTRXO 106 N LOG Ul U42 NET MGTRXO 106 P DOC UL ULI NET MGTRXO 107 N LOC UL K40 NET MGTRXO 107 P LOC U1 K39 NET MGTRXO 108 N LOC U1 G38 NET MGTRXO 108 P LOC U1 G37 NET MGTRXO 112 N LOC Ul AL8 NET MGTRXO 112 P LOC U1 AL7 NET MGTRXO 113 N LOC U1 AH6 NET MGTRXO 113 P LOC U1 AH5 NET MGTRXO 114 N LOC U1 AD6 NET MGTRXO 114 P LOC Ul AD5 NET MGTRXO 115 N LOC
11. 104 P 104 44 3 139 AA37 MGTRX3 104 N 104 44 3 140 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 33 Chapter 1 ML628 Board Features and Operation 34 Table 1 19 GTX Transceiver Pins Cont d XILINX Trace Length FPGA Pin Net Name Quad Connector Mils AA42 MGTTXO 105 P 105 J45 8 305 AA41 MGTTXO 105 N 105 J45 8 305 Y40 MGTRX0_105_P 105 JA5 7 237 Y39 MGTRXO 105 N 105 J45 7 236 Y44 MGTTX1_105_P 105 J45 7 068 Y43 MGTTX1_105_N 105 J45 7 068 W38 MGTRX1_105_P 105 J45 7 455 W37 MGTRX1_105_N 105 J45 7 456 W42 MGTTX2_105_P 105 J45 6 717 W41 MGTTX2_105_N 105 J45 6 717 V40 MGTRX2_105_P 105 J45 8 331 V39 MGTRX2_105_N 105 J45 8 331 V44 MGTTX3_105_P 105 J45 6 213 V43 MGTTX3_105_N 105 J45 6 212 U38 MGTRX3_105_P 105 J45 7 386 U37 MGTRX3_105_N 105 J45 7 385 AN3 MGTTX0_112_P 112 J46 6 021 AN4 MGTTX0_112_N 112 J46 6 020 AL7 MGTRX0_112_P 112 J46 5 915 AL8 MGTRX0_112_N 112 J46 5 914 AM1 MGTTX1_112_P 112 J46 5 559 AM2 MGTTX1_112_N 112 J46 5 560 AM5 MGTRX1_112_P 112 J46 5 708 AM6 MGTRX1_112_N 112 J46 5 707 AL3 MGTTX2_112_P 112 J46 5 395 AL4 MGTTX2_112_N 112 J46 5 396 AJ7 MGTRX2_112_P 112 J46 4 506 AJ8 MGTRX2_112_N 112 J46 4 506 AK1 MGTTX3_112_P 112 J46 5 986 AK2 MGTTX3_112_N 112 J46 5 985 AK5 MGTRX3_112_P 112 J46 5 094 AK6 MGTRX3_112_N 112 J46 5 094 www xilinx com ML62
12. 118 J55 3 152 A4 MGTTX2 118 P 118 J55 2 271 A3 MGTTX2 118 N 118 J55 2 271 B6 MGTRX2 118 P 118 J55 2 518 B5 MGTRX2 118 N 118 J55 2 518 C4 MGTTX3 118 P 118 J55 2560 C3 MGTTX3 118 N 118 55 2 561 D6 MGTRX3 118 P 118 J55 2 426 D5 MGTRX3 118 N 118 J55 2426 Information for each GTH transceiver clock input is shown in Table 1 18 Table 1 18 GTH Transceiver Clock Inputs to the FPGA FPGA Pin Net Name Quad Connector R41 MGTREFCLK 106 P 106 J50 R42 MGTREFCLK_106_N 106 J50 J41 MGTREFCLK_107_P 107 J51 J42 MGTREFCLK_107_N 107 J51 E41 MGTREFCLK_108_P 108 J52 E42 MGTREFCLK_108_N 108 J52 UG771 v1 1 February 19 2014 www xilinx com 29 Chapter 1 ML628 Board Features and Operation XILINX Table 1 18 GTH Transceiver Clock Inputs to the FPGA Cont d FPGA Pin Net Name Quad Connector R4 MGTREFCLK 116 P 116 J53 R3 MGTREFCLK 116 N 116 J53 J4 MGTREFCLK 117 P 117 24 J3 MGTREFCLK 117 N 117 J54 E4 MGTREFCLK_118_P 118 J55 E3 MGTREFCLK 118 N 118 J55 GTX Transceivers and Reference Clocks Figure 1 2 callout 18 The ML628 board provides access to all GTX transceiver and reference clock pins on the FPGA as shown in Figure 1 13 The GTX transceivers are grouped into six sets of four RX TX lanes Four lanes are referred to as a Quad Note Figure 1 13 is for reference only and might not reflect the current revision of the
13. AP28 NET FMC1 LA30 P LOC U1 AN28 NET FMC1 LA31 N LOC U1 AP29 NET FMC1 LA31 P LOC U1 AN29 NET FMC1 LA32 N LOC U1 BC31 NET FMC1 LA32 P LOC U1 BB31 NET FMC1 LA33 N LOC U1 AM29 NET FMC1 LA33 P LOC U1 AL29 NET FMC1 PRSNT M2C L LOC U1 BD25 NET FMC2 CLKO M2C N LOC U1 BD6 NET FMC2 CLKO M2C P LOC Ul BC6 NET FMC2 CLK1 M2C N LOC Ul AL12 NET FMC2 CLK1 M2C P LOC Ul AL13 NET FMC2 CLK2 M2C N LOC U1 AJ19 NET FMC2 CLK2 M2C P LOC U1 AJ20 NET FMC2 CLK3 M2C N LOC U1 BB4 NET FMC2 CLK3 M2C P LOC U1 BB5 NET FMC2 HAOO CC N LOC U1 AU10 NET FMC2 HAOO CC P LOC U1 AU1l NET FMC2 HAO01 CC N LOC U1 AW8 NET FMC2 HAO01 P LOC Ul AV9 NET FMC2 HA02 N LOC U1 AU12 NET FMC2 HA02 P LOC U1 AT12 NET FMC2 HAO3 N LOC Ul AW11 NET FMC2_HA03_P LOC Ul AV12 NET FMC2 HAO4 N LOC Ul AY6 NET FMC2 HAQA P LOC U1 AY7 NET FMC2 HAO5 N LOC U1 AM16 NET FMC2 HAO05 P LOC Ul AL17 NET FMC2 HAO6 N LOC U1 AV6 NET FMC2 HAO6 P LOC U1 AU7 NET FMC2 HA07 N LOC U1 AW10 NET FMC2 07 P LOC Ul AV11 NET FMC2 HAO8 N LOC Ul AY8 NET FMC2 HAO8 P LOC U1 AW9 NET FMC2 HAO9 N LOC Ul AR13 NET FMC2 HAO9 P LOC Ul AP14 NET FMC2_HA10_N LOC U1 AW6 NET FMC2_HA10_P LOC U1 AV7 NET FMC2_HA11_N LOC Ul AR11 NET FMC2 HAL
14. Database of silicon software and IP questions and answers see the Xilinx website at http www xilinx com support This document uses the following conventions An example illustrates each convention Typographical ML628 Board User Guide The following typographical conventions are used in this document www xilinx com 5 UG771 v1 1 February 19 2014 Preface About This Guide XILINX Convention Courier font Meaning or Use Messages prompts and program files that the svstem displavs Example speed grade 100 Courier bold Literal commands that vou enter in a svntactical statement ngdbuild design name Helvetica bold Commands that vou select from a menu File Open Keyboard shortcuts Cirl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Command Line Tools User Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Online Document The following conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Blue underlined text Hype
15. FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 HA17 CC P LOC HA18 N LOC HA18 P LOC HA19 N LOC HA19 P LOC HA20 N LOC HA20 P LOC HA21 N LOC HA21 P LOC HA22 N LOC HA22 P LOC HA23 N LOC HA23 P LOC HB00 CC N LOC HB00 CC P LOC HB01 N LOC HB01 P LOC HB02 N LOC HB02 P LOC HB03 N LOC HB03 P LOC HB04 N LOC HB04 P LOC HB05 N LOC HB05 P LOC HB06 CC N LOC HB06 CC P LOC HB07 N LOC HB07 P LOC HB08 N LOC HB08 P LOC HB09 N LOC HB09 P LOC HB10 N LOC HB10 P LOC HB11 N LOC HB11 P LOC _HB12_N LOC HB12 P LOC HB13 N LOC HB13 P LOC HB14 N LOC HB14 P LOC HB15 N LOC HB15 P LOC HB16 N LOC HB16 P LOC HB17 CC N LOC HB17 CC P LOC LAO00 CC N LOC LAO00 CC P LOC LAO01 CC N LOC LAO01 CC P LOC LA02 N LOC LA02 P LOC LA03 N LOC LA03 P LOC _LA04_N LOC LAQA P LOC U y U y U y y M U t U y y y D U 00 U y U U y U y U y U U U y y 0 y a y U y U p U U S U U U U U y y y U y U 0 U BD4 BD5 BA2 SAYS 62 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET FMC2 LAO5 N LOC Ul AY5 NET FMC2 LAO5 P LOC U1
16. GCLK N LOC CM GCLK P LOC CM LVDS1 N LOC CM LVDS1 P LOC CM LVDS2 N LOC CM LVDS2 P LOC CM LVDS3 N LOC CM LVDS3 P LOC CM RST LOC DUT I2C SCL LOC DUT I2C SDA LOC DUT PMB ALERT LOC DUT PMB CLK LOC DUT PMB CTRL LOC DUT PMB DATA LOC FMC1 CLKO M2C N LOC FMC1 CLKO M2C P LOC FMC1 CLK1 M2C N LOC FMC1 CLK1 M2C P LOC FMC1 CLK2 M2C N LOC FMC1 CLK2 M2C P LOC FMC1 CLK3 M2C N LOC FMC1 CLK3 M2C P LOC FMC1 HAO00 CC N LOC FMC1 HAOO CC P LOC FMC1 HA01 CC N LOC FMC1 HAO1 CC P LOC FMC1 HAO2 N LOC FMC1 HAO2 P LOC FMC1 HAO3 N LOC FMC1 HAO3 P LOC FMC1 HAO4 N LOC FMC1 HAQA P LOC FMC1 HAO5 N LOC FMC1 HAO5 P LOC FMC1 HAO6 N LOC FMC1 HAO6 P LOC FMC1 07 LOC FMC1 HAO7 P LOC FMC1 08 N LOC FMC1 HAO8S P LOC FMC1 HAO9 N LOC FMC1 HAO9 P LOC FMC1 HA10 N LOC FMC1 HA10 P LOC FMC1 HALL N LOC FMC1 HALL P LOC FMC1 HA12 LOC FMC1 HA12 P LOC FMC1 HA13 N LOC U y U y U y i U U U Es p y 00 U 00 y U U U y 0 y U y y U U y t y y y U U y U p U U SU U y y y y a y U 00 Sp 0 U L24 B24 C23 C24 D23 AK23 L23 B26 40206057 A24 A23 B36 B35 CI C12 BD33 BC33 D24 R25 P25 G27 F29 H27 G2
17. GTX and GTH transceiver characterization board Net names in the constraints listed below correlate with net names on the ML628 board schematic Users must identify the appropriate pins and replace the net names below with net names in the user RTL See the Constraints Guide for more information Users can refer to the UCF files generated by tools such as Memory Interface Generator MIG for memory interfaces and Base System Builder BSB for more detailed I O standards information required for each particular interface The FMC connectors J290 and J441 are connected to 2 5V V banks Because each user s FMC card implements customer specific circuitry the FMC bank I O standards must be uniquely defined by each customer ML628 Master UCF Listing J E Ed Ld E 13 B Bd dB 3 3 4 3 3 3103 HHA 5 d C APP LED1 APP LED2 APP LED3 APP LEDA APP LED5 APP LED6 APP LED7 APP LED8 CCLK 0 1 ET C 2 ET C K DIFF 1 N ET C ET C K DIFF 1 P K DIFF 2 N ET C K DIFF 2 P 354523 3 1 4 oh C d E3 E3 EJ KJ 4 Ej EET 42 C El 2 2 2 2 2 2 2222222222222222 22323222322 E E td Ed Dd E Ed Dd Dd Bl E bd Dd Bd tid C 1 CM CTRL 0 CM CTRL 1 CM CTRL 2 CM CTRL 3 CM CTRL 4 CM CTRL 5 CM CTRL 6 CM CTRL 7 CM CTRL 8 CM CTRL 9 CM CTRL 10 CM CTRL 11 CM CTRL 12
18. H20 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX ML628 Board User Guide Table 1 25 VITA 57 1 FMC2 HPC Connections at 4441 Cont d FPGA Pin Net Name FMC Pin AW13 FMC2 LA16 P G18 AY13 FMC2 LA16 N G19 ATI4 FMC2 LA17 CC P D20 AT13 FMC2 LA17 CC N D21 AU15 FMC2 LA18 CC P C22 AV14 FMC2 LA18 CC N C23 AL20 FMC2 LA19 P H22 AM20 FMC2 LA19 N H23 AU14 FMC2 LA20 P G21 AV13 FMC2 LA20 N G22 AW15 FMC2 LA21 P H25 AW14 FMC2_LA21_N H26 AK20 FMC2 LA22 P G24 AL19 FMC2 LA22 N G25 AR15 FMC2 LA23 P D23 AT15 FMC2 LA23 N D24 AP18 FMC2 LA24 P H28 AR17 FMC2 LA24 N H29 AJ18 FMC2 LA25 P G27 AK18 FMC2_LA25_N G28 AM19 FMC2 LA26 P D26 AN19 FMC2_LA26_N D27 AN18 FMC2 LA27 P C26 AN17 FMC2 1 27 N C27 AJ21 FMC2 LA28 P H31 AK21 FMC2 LA28 N H32 AP16 FMC2 LA29 P G30 AR16 FMC2 LA29 N G31 AL18 FMC2_LA30_P H34 AM17 FMC2_LA30_N H35 AN16 FMC2_LA31_P G33 AP15 FMC2_LA31_N G34 BC18 FMC2_LA32_P H37 UG771 v1 1 February 19 2014 www xilinx com Detailed Description 49 Chapter 1 ML628 Board Features and Operation 50 Table 1 25 VITA 57 1 FMC2 HPC Connections at J441 Cont d XILINX FPGA Pin Net Name FMC Pin BD18 FMC2 LA32 N H38 BB14 FMC2 LA33 P G36 BC14 FMC2 LA33 N G37 BC4 FMC2 PRS
19. LEE MGTHAVCCPLL MGTHAVIT MGTAVCC GTX Transceiver Power Module MGTAVTT UG771_c1_03_022211 Figure 1 3 ML628 Board Power Supply Block Diagram ML628 Board User Guide www xilinx com 11 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation XILINX The ML628 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1 1 The board can also be configured to use external bench power supply for each voltage See Using External Power Sources Table 1 1 Onboard Power System Devices l Power External Reference ee Power Rail Typical Device Description Regulation Supply Designator Net Name Voltage Jumper Jack Core voltage controller and regulators UCD9240PFC U8 PMBus compliant digital PWM system controller address 52 PTD08A020W U10 Adjustable switching regulator VCCINT 1 0V J102 J223 20A 0 6V to 3 6V PTD08A020W U41 Adjustable switching regulator VCCINT 1 0V J61 J440 20A 0 6V to 3 6V VCCINT B PTD08A020W U12 Adjustable switching regulator VCCAUX 2 5V J104 J227 20A 0 6Vto 3 6V PTDOSAO20W U13 Adjustable switching regulator VCCO 2 5V J105 J98 20A 0 6V to 3 6V Auxiliary voltage controller and regulators UCD9240PFC U19 PMBus compliant digital PWM system controller address 53 PTD08A020W U23 Adjustable switching r
20. This driver permits the CP2103 USB to UART bridge to appear as a COM www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 Z XILINX Detailed Description port to the host computer communications application software for example HyperTermimal or TeraTerm The VCP driver must be installed on the host computer prior to establishing communications with the ML628 board FMC HPC Connectors Figure 1 2 callouts 21a and 21b The ML628 board features two high pin count HPC connectors as defined by the VITA 57 1 1 FMC specification The FMC HPC connector is a 10 x 40 position socket See Appendix B VITA 57 1 FMC HPC Connector Pinout for a cross reference of signal names to pin coordinates FMC1 HPC connector J290 provides connectivity for e 80 differential user defined pairs e 3ALA pairs e 24 HA pairs e 22 HB pairs e 4 differential clocks FMC2 HPC connector J441 provides connectivity for e 76 differential user defined pairs e 34LA pairs e 24 HA pairs e 18 HB pairs e 4 differential clocks Note The Vap voltage for the FMC HPC connectors on the ML628 board is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The VITA 57 1 FMC interfaces on the ML628 board are compatible with 2 5V mezzanine cards capable of supporting 2 5V Vapy The FMC HPC connectors on the ML628 board are identified as FMC1 at J290 and FMC2 at J441 The connections for each of these connectors are listed in Table 1
21. board 9999919 el Y rper d f QUAD 113 QUAD 104 p QUAD 103 ja T TaD ED 09 L Lo Oe so Or 00 0 6 UG771_c1_12_030111 Figure 1 13 GTX Transceiver and Reference Clock SMA Locations 30 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Detailed Description Each GTX Quad and its associated reference clocks CLKO and CLK1 are brought out to a connector pad which is designed to interface with Samtec BullsEye connectors such as the Samtec HDR 155805 01 BEYE cable assembly Contact Samtec Inc for information about other cable assemblies Figure 1 14 A shows the connector pad Figure 1 14 B shows the connector pinout o Y x Do 5 o Le o o la 00000 68 6 6 G D GTX Connector Pad GTX Connector Pinout UG771 c1 14 032211 Figure 1 14 A GTX BullsEye Connector Pad B GTX BullsEye Connector Pad Information for each GTX transceiver pin is shown in Table 1 19 Table 1 19 GTX Transceiver Pins FPGA Pin Net Name Quad Connector ern BB44 MGTTXO 100 P 100 J37 5 825 BB43 MGTTXO 100 N 100 J37 5 825 BD40 MGTRXO 100 P 100 J37 5 316 BD39 MGTRXO 100 N 100 J37 5 316 AY44 MGTTX1_100_P 100 J37 6 178 AV43 MGTTXI 100 N 100 J37 6 178 BC42 MGTRXI 100 P 100 J37 5 702 BC41 MGTRXI 100 N 100 J37 5 701 AW42 MGTTX2_100_P 100 J37 7 107 AW41 MGTTX2_100_N 10
22. erent asd rne ER tex Batut od Ba pene pad cute clan gids 18 DONE EBD e e ueteri Pee iet HE dun 18 TINT Des LIS derum MEME IE 19 System ACE Controllet e EE eR 19 System ACE Controller Reset ro 19 Configuration Address DIP Switches ce 19 JTAG Isolation Jumpers icc code aaa Rer nt aa at RR 19 200 MHz 2 5V LVDS Oscillator esset e pee bee uo ee POR a 20 Single Ended SMA Global Clock Inputs 20 Differential SMA Global Clock Inputs 3 21 SuperClock 2 Module 60 re eer RE na olt la dna at e 21 User LEDs Active High 1 22 User DIP Switches Active High 23 User Push Buttons Active High 23 User Test OM cic ein teste e 24 GTH Transceivers and Reference 10 098 24 GTX Transceivers and Reference Clocks 30 USB to UART Bridge cocinas PGE ank dd Gere pee et dtc ta a 38 FMC HPC ConnectOtS ir das o A 39 System MODILOL l 50 FC Bus Managetment s Lee teh tuia eb ede teh RERO Ue 50 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 XILINX Appendix A Default Jumper Positions Appendix B VITA 57 1 FMC HPC Connector Pinout Appendix C ML628 Master U
23. stored on a CompactFlash memory card see Configuration Address DIP Switches page 19 The JTAG chain of the board is illustrated in Figure 1 8 the four System ACE interface isolation jumpers described in JTAG Isolation Jumpers are not shown Shorting pins 1 2 on header J162 automatically bypasses the FMC modules GTH transceiver power supply module and GTX transceiver power supply module in the chain ML628 Board User Guide www Xilinx com 17 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation Z XILINX J29 TI3_TDO UCD9240 UCD9240 UCD9240 GTXPM_TDI PWM System PWM System PWM System Controller Controller Controller JTAG Connector System Ace Virtex 6 Controller FPGA DUT FMC 2 Connector GTH Power GTX Power Module Module FMC 1 Connector GTXPM_TDI Analog Switch Figure 1 8 JTAG Chain PROG B Push Button Figure 1 2 callout 3 Analog Switch UG771_c1_08_022211 Pressing the PROG push button SW5 grounds the active Low program pin of the FPGA DONE LED Figure 1 2 callout 4 The DONE LED DS6 indicates the state of the DONE pin of the FPGA When the DONE pin is High DS6 lights indicating the FPGA is successfully configured 18 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 Z XILINX Detailed Description INIT LED Figure 1 2 callout 5 The INIT LED DS20 lights during FPGA initialization Sy
24. switch SW7 provides a set of eight active High switches that are connected to user I O pins on the FPGA as shown in Table 1 14 These pins can be used to set control pins or any other purpose determined by the user Table 1 14 User DIP Switches FPGA Pin Net Name J29 USER_SW1 J28 USER_SW2 R27 USER_SW3 T27 USER_SW4 H29 USER_SW5 H28 USER_SW6 L29 USER_SW7 L28 USER_SW8 Reference Designator SW7 User Push Buttons Active High Figure 1 2 callout 16 SW5 and SW6 are active High user push buttons that are connected to user I O pins on the FPGA as shown in Table 1 15 These switches can be used for any purpose determined by the user ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 23 Chapter 1 ML628 Board Features and Operation Table 1 15 User Push Buttons FPGA Pin Net Name Designator A27 USER PB1 SW6 B27 USER PB2 SW4 XILINX User Test I O Figure 1 2 callout 17 A standard 2 x 6 100 mil pitch header J285 brings out 6 FPGA I O for test purposes Table 1 16 lists these pins Table 1 16 User Test I O FPGA Pin Net Name J285 Pin M26 USER IO 1 2 N26 USER 10 2 4 C28 USER I0 3 6 C27 USER 10 4 8 A29 USER I0 5 10 A28 USER 10 6 12 GTH Transceivers and Reference Clocks Figure 1 2 callout 19 The ML628 board provides access to all GTH transceiver and reference clock pins on
25. these clock inputs remove jumpers across AFX SEL headers J186 and J187 Table 1 10 Single Ended SMA Clock Connections FPGA Pin Net Name SMA Connector AP33 CLK 1 J171 R31 CLK 2 J172 Differential SMA Global Clock Inputs Figure 1 2 callout 12 SuperClock 2 Module ML628 Board User Guide UG771 vi 1 February 19 The ML628 board provides two pairs of differential SMA transceiver clock inputs that can be used for connecting to an external function generator The FPGA clock pins are connected to the SMA connectors as shown in Table 1 11 Table 1 11 Differential SMA Clock Connections FPGA Pin Net Name SMA Connector AN33 CLK DIFF 1 P J167 AP33 CLK DIFF 1 N J168 33 CLK DIFF 2 P J169 H33 CLK DIFF 2 N J170 Figure 1 2 callout 13 The SuperClock 2 module connects to the clock module interface connector J32 and provides a programmable low noise and low jitter clock source for the ML628 board The clock module maps to FPGA I O by way of 24 control pins 3 LVDS pairs 1 regional clock pair and 1 reset pin Table 1 12 shows the FPGA I O mapping for the SuperClock 2 module interface The ML628 board also supplies 5V 3 3V and 2 5V input power to the clock module interface Table 1 12 SuperClock 2 FPGA I O Mapping FPGA Pin Net Name J32 Pin B35 CM LVDSI P 1 B36 CM LVDSI N 3 C12 CM LVDS2 P 9 C11 CM_LVDS2_N 11 BC33 CM_LVDS3_P 17 BD33 C
26. 0 J37 7 107 BB40 MGTRX2 100 P 100 J37 6 653 BB39 MGTRX2_100_N 100 J37 6 652 AV44 MGTTX3_100_P 100 J37 6 662 AV43 MGTTX3 100 N 100 J37 6 662 BA42 MGTRX3 100 P 100 J37 6 158 BA41 MGTRX3 100 N 100 J37 6 157 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 31 Chapter 1 ML628 Board Features and Operation 32 Table 1 19 GTX Transceiver Pins Cont d XILINX Trace Length FPGA Pin Net Name Quad Connector Mils AU42 MGTTXO 101 P 101 J41 5 335 AU41 MGTTX0_101_N 101 J41 5 335 AY40 MGTRX0_101_P 101 J41 4 955 AY39 MGTRX0_101_N 101 J41 4 955 AT44 MGTTX1_101_P 101 J41 5 647 AT43 MGTTX1_101_N 101 J41 5 647 AV40 MGTRX1_101_P 101 J41 5 347 AV39 MGTRX1_101_N 101 J41 5 347 AR42 MGTTX2_101_P 101 J41 5 990 AR41 MGTTX2_101_N 101 J41 5 990 AT40 MGTRX2_101_P 101 J41 5 586 AT39 MGTRX2_101_N 101 J41 5 586 AP44 MGTTX3_101_P 101 J41 6 987 AP43 MGTTX3_101_N 101 J41 6 988 AP40 MGTRX3_101_P 101 J41 5 677 AP39 MGTRX3_101_N 101 J41 5 678 AN42 MGTTX0_102_P 102 J42 5 056 AN41 MGTTX0_102_N 102 J42 5 055 AL38 MGTRXO 102 P 102 42 4 603 AL37 MGTRXO 102 N 102 J42 4 603 AM44 MGTTX1_102_P 102 J42 5 241 AM43 MGTTXI 102 N 102 42 5 241 AM40 MGTRXI 102 P 102 42 5 029 AM39 MGTRXI 102 102 J42 5 028 AL42 MGTTX2_102_P 102 J42 5 883 AL41 MGTTX2_102_N 102 J42 5 883 AJ38 MGTRX2_102_P 102 J42 5 468 A
27. 00 00 00 co cc OO 00 co 00 00 GEI GTH POWER MODULE 6771 c1 04 022211 Figure 1 4 Mounting Location GTH Transceiver Power Module ML628 Board User Guide www xilinx com 13 UG771 v1 1 February 19 2014 14 Chapter 1 ML628 Board Features and Operation Z XILINX Table 1 2 describes the nominal voltage values for the MGTHAVCC MGTHAVCCRX MGTHAVTT and MGTHAVCCPLL power rails The table also lists the maximum current ratings for each rail supplied by either module Table 1 2 GTH Transceiver Power Module Power Supply Rail Nominal Maximum Current Net Name Voltage Rating MGTHAVCC 1 1V 5 10A MGTHAVCCRX 1 1V 3 45A MGTHAVTT 1 2V 1 50A MGTHAVCCPLL 1 8V 2 60A The GTH transceiver power rails also have corresponding input voltage jacks to supply each voltage independently from a bench top power supply The external jacks are indicated in Table 1 3 Caution The GTH module MUST be removed when providing external power to the GTH transceiver rails Table 1 3 GTH External Supply Jacks Power Supply Rail External Supply Net Name Jack MGTHAVCC 279 MGTHAVCCRX J280 MGTHAVTT J282 MGTHAVCCPLL J283 GTX Transceiver Power Module The GTX transceiver power module supplies MGTAVCC and MGTAVTT voltages to the FPGA GTX transceivers Three GTX power modules are provided with the ML628 board for evaluation Any one of the three modules can be plugged into connectors J34
28. 014 Z XILINX Detailed Description Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin U38 18 FMC1 TMS D33 Notes 1 This signal is not directly connected to the FPGA The value in the leftmost column represents the device and pin the signal is connected to For example U27 9 U27 pin 9 Table 1 25 VITA 57 1 FMC2 HPC Connections at J441 FPGA Pin Net Name FMC Pin BC6 FMC2 CLKO M2C P H4 BD6 FMC2 CLKO M2C N H5 AL13 FMC2 CLKI M2C P G2 AL12 FMC2_CLK1_M2C_N G3 AJ20 FMC2 CLK2 M2C P KA AJ19 FMC2 CLK2 M2C N K5 BB5 FMC2 CLK3 M2C P J2 BB4 FMC2 CLK3 M2C N J3 AUT FMC2 CC P F4 AU10 FMC2 HA00 CC N F5 AV9 FMC2 HAO01 CC P E2 AWS FMC2 HA01 CC N E3 AT12 FMC2 HA02 P K7 AU12 FMC2 HAO2 N K8 AV12 FMC2 HA03 P J6 AW11 FMC2 03 7 AY7 FMC2 04 P F7 AY6 FMC2 HA04 N F8 ALI7 FMC2 HA05 P E6 AM16 FMC2 HA05 N E7 AU7 FMC2 HAO6 P K10 AV6 FMC2 N K11 AVII FMC2_HA07_P 9 AW10 FMC2 HA07 N J10 AW9 FMC2 08 P F10 AX8 FMC2 HA08 N F11 AP14 FMC2_HA09_P E9 ML628 Board User Guide www xilinx com 45 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation 46 Table 1 25 VITA 57 1 FMC2 HPC Connections at J441 Cont d
29. 2 3 of header J24 AUX POR RESET Default Jumper Positions A list of shunts and shorting plugs and their required positions for normal board operation is provided in Appendix A Default Jumper Positions Monitoring Voltage and Current Voltage and current monitoring and control are available for selected power rails through Texas Instruments Fusion Digital Power graphical user interface GUI The three onboard TI power controllers U8 at PMBUS address 52 U19 at PMBUS address 53 and U32 at PMBUS address 54 are wired to the same PMBus The PMBus connector J14 is provided for use with the TI USB Interface Adapter PMBus pod and associated TI GUI References More information about the power svstem components used bv the ML628 board are available from the Texas Instruments digital power website at http www ti com ww en analog digital power index html GTH Transceiver Power Module The GTH transceiver power module supplies MGTHAVCC MGTHAVCCRX MGTHAVTT and MGTHAVCCPLL voltages to the FPGA GTH transceivers Two GTH power modules are provided with the ML628 board for evaluation Either of the modules can be plugged into the connectors J6 and J197 in the outlined and labeled power module location shown in Figure 1 4 Note The GTH and GTX power modules have different connectors and form factors to prevent GTH modules from being connected to the GTX headers and vice versa Q 9 Q e Q e Q e e e Q Q e IM 00
30. 24 and Table 1 25 respectively Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 FPGA Pin Net Name FMC Pin AL22 FMC1 CLKO M2C P H4 AM22 FMCI CLKO M2C N H5 N12 FMC1 CLK1 M2C P G2 M12 FMCI CLK1 M2C N G3 AJ26 FMC1 CLK2 M2C P KA AK27 FMCI CLK2 M2C K5 BB22 FMC1_CLK3_M2C_P J2 BC22 FMC1_CLK3_M2C_N J3 AY22 FMC1_HA00_CC_P F4 BA22 FMC1_HA00_CC_N F5 ML628 Board User Guide www xilinx com 39 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation 40 Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin BA20 FMCI CC P E2 BB20 FMCI HA01 CC N E3 AU21 FMC1_HA02 P K7 AV21 FMC1 HAO2 K8 AN23 FMC1 HAQ3 P J6 AN22 FMC1 HA03 N J7 AW21 FMC1_HA04_P F7 AY21 FMC1_HA04_N F8 AV23 FMCI HA05 P E6 AW23 FMC1 HA05 N E7 AP23 FMC1 HA06 P K10 AR23 FMC1 HA06 N K11 AY23 FMCI HA07 P 9 BA23 FMCI HA07 N J10 AW20 FMCI HA08 P F10 AY20 FMC1 HA08 N F11 AT20 FMC1_HA09_P E9 AU20 FMC1_HA09_N E10 AV19 FMC1_HA10_P K13 AW19 FMC1 HA10 N K14 AU22 FMCI HA11 P JA2 AV22 FMCI HA11 N 13 BA19 FMCI HA12 P F13 BB19 FMCI HA12 F14 BC23 FMCI HA13 P E12 BD23 FMC1 HA13 N E13 AT23 FMCI HA14 P J15 AT22 FMC1 HA14 N J16 BB21 FMCI HA15 P F16 BC21 FMCI HA15 N F17 BC19 FMC1 HA16 P E15 BD19 FMCI HA16 N E16 AR22 FMCI HA1
31. 2_HB09_N E28 AP21 FMC2_HB10_P K31 AR20 FMC2_HB10_N K32 AV18 FMC2_HB11_P J30 AW18 FMC2 HB11 N J31 BA17 FMC2 HB12 P F31 BB17 FMC2 HB12 F32 AP20 FMC2 HB13 P E30 AP19 FMC2 HB13 N E31 AU17 FMC2 HB14 P K34 AV17 FMC2 HB14 N K35 AT19 FMC2 HB15 P 33 AU19 FMC2 HB15 N J34 AR18 FMC2_HB16_P F34 AT18 FMC2_HB16_N F35 AT17 FMC2 HB17 CC P K37 AU16 FMC2_HB17_CC_N K38 U27 13 FMC2 I2C SDA 1 C31 UG771 v1 1 February 19 2014 www xilinx com Detailed Description 47 Chapter 1 ML628 Board Features and Operation 48 Table 1 25 VITA 57 1 FMC2 HPC Connections at 4441 Cont d FPGA Pin Net Name FMC Pin U27 14 FMC2 DC SCL 1 C30 BC8 FMC2 1 400 CC P G6 BC7 FMC2 1 400 CC N G7 BA5 FMC2 LAO1 CC P 128 BA4 FMC2 LAO1 CC N D9 BC3 FMC2 1 02 P H7 BC2 FMC2 1 2 N H8 AY3 FMC2 LAQ3 P 39 BA3 FMC2 LAO3 N G10 BD9 FMC2 LAQA P H10 BD8 FMC2 LA04 H11 AW5 FMC2 1 405 P D11 AY5 FMC2 LA05 N D12 BA12 FMC2 LA06 P C10 BB11 FMC2 LA06 N C11 BAS FMC2 LAQ7 P H13 BA7 FMC2 1 N H14 AY12 FMC2 1 08 P G12 AY11 FMC2 LAO8 N G13 BB10 FMC2_LA09_P D14 BC9 FMC2_LA09 N D15 BB7 FMC2_LA10_P C14 BB6 FMC2 LA10 N C15 AY10 FMC2 LA11 P H16 BA9 FMC2 LA11 N H17 BA10 FMC2 LA12 P G15 BB9 FMC2 LA12 N G16 AY15 FMC2 LA13 P D17 BA15 FMC2 LA13 N D18 AM21 FMC2 LA14 P C18 ANDI FMC2 LA14 N C19 BA14 FMC2 LA15 P H19 BA13 FMC2 LA15 N
32. 31 AL32 FMC1 HB10 N K32 AP30 FMC1 HB11 P J30 AR30 FMC1_HB11_N J31 AT30 FMCI HB12 P F31 AU30 FMCI HB12 N F32 AJ30 FMCI HB13 P E30 AJ31 FMC1 HB13 N E31 AU32 FMC1 HB14 P K34 AV32 FMC1 HB14 N K35 AP31 FMCI HB15 P 33 AR32 FMCI HB15 J34 AN31 FMC1_HB16_P F34 AN32 FMC1_HB16_N F35 AJ29 FMC1_HB17_CC_P K37 AK30 FMC1_HB17_CC_N K38 AK32 FMC1_HB18_P J36 AL33 FMC1_HB18_N J37 BA33 FMC1_HB19_P E33 BA34 FMC1_HB19_N E34 AW35 FMC1_HB20_P F37 AY35 FMC1_HB20_N F38 AW33 FMC1_HB21_P E36 AY33 FMC1_HB21_N E37 C31 FMC1_I2C SDA U27 10 C30 FMC1 DC SCL U27 11 AV24 FMC1_LA00_CC_P G6 AW24 FMC1_LA00_CC_N G7 BB26 FMC1_LA01_CC_P D8 BC26 FMC1_LA01_CC_N D9 AL25 FMC1_LA02_P H7 AM25 FMCI LAO2 N H8 AP25 FMCI LA03 P 39 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX ML628 Board User Guide Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin AR25 FMC1_LA03_N G10 AP26 FMC1_LA04_P H10 AR26 FMC1 LA04 N H11 AW25 FMCI LAQS P 1211 AV25 FMCI LA05 N 1212 AK22 FMCI 1 406 P C10 AL23 FMCI LA06 N C11 AU26 FMC1 LAO7 P H13 AV26 FMCI LAO7 N H14 BA25 FMCI LAO08 P G12 BB25 FMCI LA08 N G13 AJ23 FMC1_LA09_P 14 AK23 FMCI LA09 N D15 AW26 FMCI LA10 P C14 AY26 FMCI LA10 N C15 AM26 FMCI LA11 P H16 AN26 FMCI LA11 N H17 AT25 FMC1_LA12 P G15
33. 7 CC P K16 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX ML628 Board User Guide Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin AR21 FMCI HA17 CC N K17 BD21 FMCI HA18 P J18 BD20 FMC1_HA18_N J19 BA24 FMC1_HA19_P F19 BB24 FMC1_HA19_N F20 AN24 FMC1_HA20_P E18 AP24 FMC1_HA20_N E19 AT24 FMCI HA21 P K19 AU24 FMC1 HA21 N K20 BC24 FMCI HA22 P J21 BD24 FMC1_HA22 N J22 AL24 FMC1_HA23_P K22 AM24 FMC1_HA23_N K23 BA30 FMC1_HB00_CC_P K25 BB30 FMC1_HB00_CC_N K26 AW30 FMC1 HB01 P J24 AY30 FMC1 HB01 N J25 BD30 FMC1_HB02_P F22 BD31 FMC1_HB02_N F23 AL30 FMC1_HB03_P E21 AM30 FMC1_HB03_N E22 BB32 FMC1_HB04_P F25 BC32 FMC1 HB04 N F26 AY32 FMC1 HB05 P E24 BA32 FMC1 HB05 N E25 AU31 FMC1 HB06 CC P K28 AV31 FMC1 HB06 CC N K29 AM31 FMC1 HB07 P J27 AM32 FMCI HB07 N J28 AW31 FMC1_HB08_P F28 AY31 FMC1_HB08_N F29 AR31 FMC1_HB09_P E27 AT32 FMC1_HB09_N E28 UG771 v1 1 February 19 2014 www xilinx com Detailed Description 41 Chapter 1 ML628 Board Features and Operation 42 Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin AK31 FMCI HB10 P K
34. 8 Board User Guide UG771 v1 1 February 19 2014 XILINX Table 1 19 GTX Transceiver Pins Cont d Detailed Description FPGA Pin Net Name Quad Connector irn AJ3 MGTTXO 113 P 113 J47 5 669 AJ4 MGTTXO 113 N 113 J47 5 668 AH5 MGTRX0_113_P 113 J47 5 878 AH6 MGTRXO 113 N 113 J47 5 878 AHI MGTTXI 113 P 113 J47 5 020 AH2 MGTTX1_113_N 113 J47 5 020 AG7 MGTRX1_113_P 113 J47 5 715 AG8 MGTRX1_113_N 113 J47 5 715 AG3 MGTTX2_113_P 113 J47 5 026 AG4 MGTTX2 113 N 113 47 5 025 AF5 MGTRX2 113 P 113 J47 4 225 AF6 MGTRX2 113 N 113 J47 4 224 AF1 MGTTX3_113_P 113 J47 5 457 AF2 MGTTX3_113_N 113 J47 5 456 AE7 MGTRX3_113_P 113 J47 5 135 AE8 MGTRX3 113 N 113 J47 5 135 AE3 MGTTX0_114_P 114 J48 4 623 AE4 MGTTXO 114 N 114 J48 4 623 AD5 MGTRXO 114 P 114 J48 4 150 AD6 MGTRX0_114_N 114 J48 4 150 ADI MGTTXI 114 P 114 J48 5 211 AD2 MGTTX1_114_N 114 J48 5 211 AC7 MGTRX1_114_P 114 J48 4 693 AC8 MGTRXI1 114 N 114 J48 4 693 AC3 MGTTX2_114_P 114 J48 5 330 AC4 MGTTX2_114 N 114 J48 5 330 AB5 MGTRX2_114_P 114 J48 5 465 AB6 MGTRX2_114 N 114 J48 5 465 AB1 MGTTX3_114_P 114 J48 5 542 AB2 MGTTX3 114 N 114 J48 5 541 AA7 MGTRX3_114_P 114 J48 4 896 AAS MGTRX3 114 N 114 J48 4 897 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 35 Chapter 1 ML628 Board Features and Operation 36 Table 1 19 GTX Tr
35. 9 AM22 AL22 M12 oR Ys AK27 AJ26 BC22 BB22 BA22 AY22 BB20 BA20 AV21 AU21 AN22 AN23 AY21 AW21 AW23 AV23 AR23 AP23 BA23 AY23 AY20 AW20 AU20 AT20 AW19 AV19 AV22 AU22 BB19 BA19 BD23 58 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET FMC1 HA13 P LOC U1 BC23 NET FMC1 HA14 N LOC U1 AT22 NET FMC1 HA14 P LOC U1 AT23 NET FMC1 HA15 N LOC Ul BC21 NET FMC1 HA15 P LOC U1 BB21 NET FMC1 HA16 N LOC Ul BD19 NET FMC1 HA16 P LOC U1 BC19 NET FMC1 HA17 CC N LOC Ul AR21 NET FMC1 HA17 CC P LOC U1 AR22 NET FMC1 HA18 N LOC U1 BD20 NET FMC1 HA18 P LOC U1 BD21 NET FMC1 HA19 N LOC U1 BB24 NET FMC1 HA19 P LOC U1 BA24 NET FMC1 HA20 N LOC U1 AP24 NET FMC1 HA20 P LOC U1 AN24 NET FMC1 HA21 N LOC U1 AU24 NET FMC1 HA21 P LOC U1 AT24 NET FMC1 HA22 N LOC U1 BD24 NET FMC1 HA22 P LOC U1 BC24 NET FMC1 HA23 N LOC U1 AM24 NET FMC1 HA23 P LOC U1 AL24 NET FMC1 HBOO CC N LOC U1 BB30 NET FMC1 HBOO CC P LOC U1 BA30 NET FMC1_HBO1_N LOC U1 AY30 NET FMC1 HBO1 P LOC U1 AW30 NET FMC1 HBO2 N LOC Ul BD31 NET FMC1 HBO2 P LOC U1 BD30 NET FMC1 HBO3 N
36. AU25 FMCI LA12 N G16 BC28 FMCI LA13 P D17 BD28 FMCI LA13 N D18 AJ24 FMCI LA14 P C18 AK25 FMCI LA14 N C19 AY27 FMCI LA15 P H19 BA27 FMCI LA15 N H20 BB27 FMCI LA16 P G18 BC27 FMCI LA16 N G19 AU27 FMC1_LA17 CC P D20 AV27 FMCI LA17 CC N 1221 AV28 FMCI LA18 CC P C22 AW28 FMCI LA18 CC N C23 AM27 FMCI LA19 P H22 AN27 FMCI LA19 N H23 UG771 v1 1 February 19 2014 www xilinx com Detailed Description 43 Chapter 1 ML628 Board Features and Operation 44 Table 1 24 VITA 57 1 FMC1 HPC Connections at J290 Cont d FPGA Pin Net Name FMC Pin BC29 FMCI LA20 P G21 BD29 FMC1_LA20_N G22 BA29 FMC1_LA21_P H25 BB29 FMC1_LA21_N H26 AJ25 FMCI LA22 P G24 AK26 FMCI LA22 N G25 AY28 FMCI LA23 P D23 BA28 FMCI LA23 N D24 AR27 FMC1_LA24 P H28 AT27 FMCI LA24 N H29 AL27 FMCI LA25 P G27 AL28 FMCI LA25 N G28 AT29 FMCI LA26 P D26 AU29 FMCI LA26 N D27 AR28 FMCI LA27 P C26 AT28 FMCI LA27 N C27 AJ28 FMCI LA28 P H31 AK28 FMCI LA28 N H32 AV29 FMCI LA29 P G30 AW29 FMCI LA29 N G31 AND8 1 LA30 P H34 AP28 FMCI LA30 H35 AN29 FMC1 LA31 P G33 AP29 FMC1_LA31_N G34 BB31 FMC1_LA32_P H37 BC31 FMC1_LA32_N H38 AL29 FMC1_LA33_P G36 AM29 FMC1_LA33_N G37 BD25 FMC1_PRSNT_M2C_L H2 U38 16 FMC1_TCK D29 w a FMC1 TDI D30 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2
37. AW5 NET FMC2 N LOC U1 BB11 NET FMC2_LA06_P LOC U1 BA12 NET FMC2 7 N LOC U1 BA7 NET FMC2 LAO07 P LOC U1 BA8 NET FMC2 LAO8 N LOC Ul AY11 NET FMC2 LAO8 P LOC Ul AY12 NET FMC2_LA09_N LOC Ul BC9 NET FMC2_LA09_P LOC Ul BB10 NET FMC2_LA10_N LOC U1 BB6 NET FMC2 LA10 P LOC U1 BB7 NET FMC2 LA11 N LOC U1 BA9 NET FMC2 LA11 P LOC Ul AY10 NET FMC2 LA12 N LOC U1 BB9 NET FMC2 LA12 P LOC U1 BA10 NET FMC2 LA13 N LOC U1 BA15 NET FMC2 LA13 P LOC Ul AY15 NET FMC2_LA14_N LOC Ul AN21 NET FMC2 LA14 P LOC U1 AM21 NET FMC2 LA15 N LOC U1 BA13 NET FMC2 LA15 P LOC U1 BA14 NET FMC2 LA16 N LOC Ul AY13 NET FMC2 LA16 P LOC U1 AW13 NET FMC2 LA17 CC N LOC Ul AT13 NET FMC2 LA17 CC P LOC U1 AT14 NET FMC2 LA18 CC N LOC U1 AV14 NET FMC2 LA18 CC P LOC U1 AU15 NET FMC2 LA19 N LOC U1 AM20 NET FMC2 LA19 P LOC U1 AL20 NET FMC2 LA20 N LOC Ul AV13 NET FMC2 LA20 P LOC U1 AU14 NET FMC2 LA21 N LOC U1 AW14 NET FMC2 LA21 P LOC Ul AW15 NET FMC2 LA22 N LOC U1 AL19 NET FMC2 LA22 P LOC U1 AK20 NET FMC2 LA23 N LOC U1 AT15 NET FMC2 LA23 P LOC U1 AR15 NET FMC2 LA24 N LOC U1 AR17 NET FMC2 LA24 P LOC Ul AP18 NET FMC2 LA25 N LOC Ul AK18 NET FMC2 LA25 P LOC U1 AJ18 NET
38. CC P LOC _LA19_N LOC _LA19_P LOC _LA20_N LOC _LA20_P LOC _LA21_N LOC _LA21_P LOC LA22 N LOC LA22 P LOC LA23 N LOC LA23 P LOC _LA24_N LOC _LA24_P LOC _LA25_N LOC LA25 P LOC LA26 N LOC U S U y U y y SB U U U si y y U n U 00 y U U U U U y U y y U U y t U y y U y U p y y y y U U a p U 00 y U U BA34 BA33 AY35 AW35 AY33 7 AW33 AW24 AV24 BC26 BB26 AM25 AL25 AR25 AP25 AR26 AP26 AY25 AW25 AL23 AK22 AV26 AU26 BB25 BA25 AK23 AJ23 AY26 AW26 AN26 AM26 AU25 AT25 BD28 BC28 AK25 AJ24 BA27 AY2 7 BB27 AV27 AU27 AW28 AV28 AN27 AM27 BD29 BC29 BB29 BA29 AK26 AJ25 BA28 AY28 AT27 AR27 AL28 AL27 AU29 60 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET FMC1 LA26 P LOC Ul AT29 NET FMC1 LA27 N LOC U1 AT28 NET FMC1 LA27 P LOC U1 AR28 NET FMC1 LA28 N LOC Ul AK28 NET FMC1 LA28 P LOC U1 AJ28 NET FMC1 LA29 N LOC U1 AW29 NET FMC1 LA29 P LOC U1 AV29 NET FMC1 LA30 N LOC U1
39. CF Listing Appendix D References www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Preface About This Guide This document describes the basic setup features and operation of the ML628 Virtex 6 FPGA GTX and GTH transceiver characterization board The ML628 board provides the hardware environment for characterizing and evaluating the GTX and GTH transceivers available on the Virtex 6 XC6VHX380T 2C FFG1923 FPGA The latest revision of this document is available online at http www xilinx com products boards ml628 reference_designs htm Guide Contents Conventions This user guide contains the following chapters and appendices e Chapter 1 ML628 Board Features and Operation describes the components features and operation of the ML628 Virtex 6 FPGA GTX and GTH transceiver characterization board e Appendix A Default Jumper Positions lists the jumpers that must be installed on the board for proper operation e Appendix B VITA 57 1 FMC HPC Connector Pinout provides a pinout reference for the FPGA mezzanine card FMC connector e Appendix C ML628 Master UCF Listing provides a listing of the ML628 master user constraints file UCF e Appendix D References provides a list of references and links to related documentation To find additional documentation see the Xilinx website at http www xilinx com support documentation index htm To search the Answer
40. ET MGTTXO 116 P LOC Ul T2 NET MGTTXO 117 N LOC U1 L3 NET MGTTXO 117 P LOC U1 L4 NET MGTTXO 118 N LOC Ul F1 NET MGTTXO 118 P LOC U1 F2 NET MGTTX1 100 N LOC Ul AY43 NET MGTTX1 100 P LOC Ul AY44 NET MGTTX1 101 N LOC U1 AT43 NET MGTTX1 101 P LOC Ul AT44 NET MGTTX1 102 N LOC U1 AM43 NET MGTTX1 102 P LOC Ul AM44 NET MGTTX1_103_N LOC U1 AH43 NET MGTTX1 103 P LOC Ul AH44 NET MGTTX1 104 N LOC U1 AD43 NET MGTTX1 104 P LOC U1 AD44 NET MGTTX1 105 N LOC Ul YA43 NET MGTTX1 105 P LOC Ul Y44 NET MGTTX1_106_N LOC U1 P44 NET MGTTX1_106_P LOC U1 P43 NET MGTTX1 107 N LOC Ul K44 NET MGTTX1 107 P LOC U1 KA3 NET MGTTX1 108 N LOC 1 44 NET MGTTX1 108 P LOC U1 D43 NET MGTTX1 112 N LOC U1 AM2 NET MGTTX1 112 P LOC U1 AM1 NET MGTTX1 113 N LOC U1 AH2 NET MGTTX1 113 P LOC Ul AH1 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendix C ML628 Master UCF Listing XILINX NET MGTTX1 114 N LOC U1 AD2 NET MGTTX1 114 P LOC Ul AD1 NET MGTTX1 115 N LOC U1 Y2 NET MGTTX1 115 P LOC Ul Y1 NET MGTTX1 116 N LOC Ul P1 NET MGTTX1 116 P LOC Ul P2 NET MGTTX1 117 N LOC Ul K1 NET MGTTX1 117 P LOC Ul K2 NET MGTTX1 118 N LOC U
41. F44 NET MGTTX3 104 N LOC U1 AB43 NET MGTTX3 104 P LOC U1 AB44 NET MGTTX3 105 N LOC U1 V43 NET MGTTX3 105 P LOC Ul V44 NET MGTTX3_106_N LOC U1 NA2 NET MGTTX3 106 P LOC Ul N41 NET MGTTX3 107 N LOC Ul H44 NET MGTTX3 107 P LOC Ul H43 NET MGTTX3 108 N LOC Ul C42 68 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX NET MGTTX3 108 P LOG UL Cai NET MGTTX3 112 N LOC Ul AK2 NET MGTTX3 112 P LOC Ul AK1 NET MGTTX3 113 N LOC U1 AF2 NET MGTTX3 113 P LOC Ul AF1 NET MGTTX3 114 N LOC U1 AB2 NET MGTTX3 114 P LOC U1 AB1 NET MGTTX3 115 N LOC U1 V2 NET MGTTX3 115 P LOC Ul V1 NET MGTTX3_116_N LOC U1 N3 NET MGTTX3 116 P LOC Ul N4 NET MGTTX3 117 N LOC Ul H1 NET MGTTX3 117 P LOC Ul H2 NET MGTTX3 118 N LOG UL E3 s NET MGTTX3 118 P LOC Ul c4 NET MGT MOD SPI D LOC U1 J26 NET MGT MOD SPI Q LOC Ul N24 NET MGT MOD SPI SCK LOC U1 H26 NET USB CTS I B LOC U1 F27 NET USB GPIO 0 LOC U1 E28 NET USB GPIO 1 LOC U1 F28 NET USB GPIO 2 LOC U1 M27 NET USB GPIO 3 LOC Ul N27 NET USB_RTS_0_B LOC U1 E27 NET USB RXD I LOC Ul C29 NET USB TXD O LOC U1 B29 NET USER IO 1 LOC U1 M26 NET USER IO 2 LOC U1 N26 NET USER IO 3 LOC
42. FMC2 LA26 N LOC U1 AN19 NET FMC2 LA26 P LOC Ul AM19 NET FMC2_LA27_N LOC Ul AN17 NET FMC2 LA27 P LOC U1 AN18 NET FMC2 LA28 N LOC U1 AK21 NET FMC2 LA28 P LOC U1 AJ21 NET FMC2_LA29_N LOC U1 AR16 NET FMC2 LA29 P LOC Ul AP16 NET FMC2 LA30 N LOC Ul AM17 NET FMC2 LA30 P LOC Ul AL18 NET FMC2_LA31_N LOC Ul AP15 NET FMC2 LA31 P LOC U1 AN16 NET FMC2 LA32 N LOC Ul BD18 NET FMC2 LA32 P LOC Ul BC18 NET FMC2 LA33 N LOC Ul BC14 NET FMC2 LA33 P LOC Ul BB14 NET FMC2 PRSNT M2C L LOC U1 BC4 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendix C ML628 Master UCF Listing XILINX SS S S S S S SS SGS SS SS SS S SS IZIZIZIZIZIZIZIZIZIZIZIZIZIZIZIZIZIIZIZIZIZIZIZIZIZIZIZIZIZIZIGZ E E Ej Dd Bd Ej Ed Dd Dd Bd Dd Bd D Bd Ed Dd Bd bj Ed D Dd Bd bd Bd B B Ed Dd Bd td bd Dd Dd Bd bd Bd Bl B Ed Dd ed d ed Dd Dd Bl Bd Bd Bl d ed ed a E bd d D Bl Bd C 5 5 C C 5 C C C C C m C C C C C C C C C C C C C C C C C C C C C C C C C 5 5 C C C C C C C C C C C C C C C C C C C n n GTH MOD SPI CS GTX MOD SPI CS MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
43. J37 MGTRX2_102_N 102 J42 5 469 AK44 MGTTX3_102_P 102 J42 5 806 AK43 MGTTX3_102_N 102 J42 5 806 AK40 MGTRX3_102_P 102 J42 5 383 AK39 MGTRX3_102_N 102 J42 5 382 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Table 1 19 GTX Transceiver Pins Cont d Detailed Description FPGA Pin Net Name Quad Connector 42 MGTTXO 103 P 103 JA3 6 626 AJA1 MGTTXO 103 N 103 J43 6 627 AH40 MGTRX0_103_P 103 J43 6 500 AH39 MGTRX0_103_N 103 J43 6 500 AH44 MGTTX1_103_P 103 J43 7 261 AH43 MGTTX1_103_N 103 J43 7 261 AG38 MGTRX1_103_P 103 J43 7 179 AG37 MGTRX1_103_N 103 J43 7 180 AG42 MGTTX2_103_P 103 J43 7 333 AG41 MGTTX2_103_N 103 J43 7 333 AF40 MGTRX2 103 P 103 J43 7 092 AF39 MGTRX2_103_N 103 J43 7 091 AF44 MGTTX3_103_P 103 J43 8 388 AF43 MGTTX3 103 N 103 JA3 8 388 AE38 MGTRX3 103 P 103 J43 7 453 AE37 MGTRX3 103 N 103 J43 7 A54 AE42 MGTTXO 104 P 104 44 2 665 AE41 MGTTXO 104 N 104 JA4 2 666 AD40 MGTRXO 104 P 104 144 2 994 AD39 MGTRXO 104 N 104 44 2 994 AD44 MGTTX1_104_P 104 44 2 696 AD43 MGTTXI 104 N 104 144 2 696 AC38 MGTRXI 104 P 104 144 2 786 AC37 MGTRXI 104 N 104 44 2 786 AC42 MGTTX2 104 P 104 144 3 091 AC41 MGTTX2_104_N 104 44 3 092 AB40 MGTRX2 104 P 104 JA4 2 435 AB39 MGTRX2 104 N 104 J44 2 436 AB44 MGTTX3_104_P 104 44 3 846 AB43 MGTTX3 104 N 104 144 3 847 AA38 MGTRX3
44. L P LOC Ul AP11 NET FMC2 HA12 N LOC U1 AN14 NET FMC2 HA12 P LOC U1 AM15 NET FMC2_HA13_N LOC Ul AN12 NET FMC2 HA13 P LOC U1 AN13 NET FMC2 HA14 N LOC U1 AV8 NET FMC2 HA14 P LOC U1 AU9 NET FMC2 HA15 N LOC U1 AJ15 NET FMC2 HA15 P LOC U1 AJ16 NET FMC2 HA16 N LOC Ul AK16 NET FMC2 HA16 P LOC U1 AK17 NET FMC2 HA17 CC N LOC Ul AR12 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendix C ML628 Master UCF Listing XILINX Zaz zZzzZZZZZZIZIZIZIZIZIIZIZIZIZIZIZIZIZZ IZIZIZIZIZIZIZIZIZIZIZIZIZIZZIZZ 4422424242442 SS SS SS S Z E E Ej Dd Bd E Ed Dd Dd Bd Dd Bd D Dd Bd E Ed D Dd Bd bd Bd B B Ed Dd Bd td Ed Dd Dd Bl Bd Bd B EB Ed Dd Bd bd Dd Dd Dd Bl Bd Bd Bl E Ed Dd Bd bj bd Dd D Bl Bj C El 5 5 C El C C C C C C C C C C C C C C C C C C C C C C C C C C C C El C C C 5 C C C C C C C C C C C C C C C C FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2 FMC2
45. MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT REFC REFC REFC REFC REFC EFC LKO 100 N LKO 100 P LKO 101 N LKO 101 P LKO 102 N KO 102 P KO 103 31 KO 103 P KO 104 N KO 104 P KO 105 N LKO 105 P LKO 112 N LKO 112 P LKO 113 N LKO 113 P LKO 114 N KO 114 P KO 115 N KO 115 P KI 100 N KI 100 P KI 101 N LK1 101 P LK1 102 N LK1 102 P LK1 103 N LK1 103 P LK1 104 N KI 104 P KI 105 N KI 105 P KI 112 N KI 112 P KI 113 N LK1 113 P LK1 114 N LK1 114 P LK1 115 N LK1 115 P LK 106 N IK 106 P K 107 N K 107 P Kk 108 N Kk 108 P K 116 N REFC LK 116 P LK 117 N LK 117 P LK 118 N RXO_ RXO_ RXO_ RXO_ RXO_ LK 118 P 100 N 100 P 101 N 101 P 102 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC U S U n U 00 U U Mi U y it y y y D U y W y MD 0 y U y y y
46. MGTRX3 106 P 106 J50 2 711 M40 MGTRX3 106 N 106 J50 2 710 L41 MGTTXO 107 P 107 J51 3 050 L42 MGTTX0_107_N 107 J51 3 049 K39 MGTRX0_107_P 107 J51 2 919 K40 MGTRX0_107_N 107 J51 2 920 K43 MGTTX1_107_P 107 J51 3 890 44 MGTTXI 107 N 107 J51 3 890 L37 MGTRXI 107 P 107 J51 3 184 L38 MGTRXI 107 N 107 J51 3 184 341 MGTTX2 107 P 107 J51 3 905 G42 MGTTX2_107_N 107 J51 3 906 H39 MGTRX2 107 P 107 J51 3 407 H40 MGTRX2 107 N 107 J51 3 406 H43 MGTTX3_107_P 107 J51 3 865 HA4 MGTTX3 107 N 107 J51 3 864 J37 MGTRX3_107_P 107 J51 3 525 J38 MGTRX3 107 N 107 J51 3 525 F43 MGTTXO 108 P 108 J52 3 644 F44 MGTTX0_108_N 108 J52 3 645 G37 MGTRX0_108_P 108 J52 2 791 G38 MGTRX0_108_N 108 J52 2 791 D43 MGTTXI 108 P 108 J52 2 677 D44 MGTTX1_108_N 108 J52 2 678 F39 MGTRX1_108_P 108 J52 2 528 F40 MGTRX1_108_N 108 J52 2 528 A41 MGTTX2 108 P 108 J52 2 349 ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 27 Chapter 1 ML628 Board Features and Operation Z XILINX Table 1 17 GTH Transceiver Pins Cont d FPGA Pin Net Name Quad Connector A42 MGTTX2 108 N 108 J52 2 349 B39 MGTRX2 108 P 108 J52 2 207 B40 MGTRX2 108 N 108 J52 2 207 C41 MGTTX3_108_P 108 J52 2 874 C42 MGTTX3 108 N 108 J52 2 874 D39 MGTRX3 108 P 108 J52 2 564 D40 MGTRX3 108 N 108 J52 2 563 T2 MGTTXO 116 P 116 J185 3 565 TI MGT
47. ML628 Virtex 6 FPGA GTX and GTH Transceiver Characterization Board User Guide XILINX Z XILINX Notice of Disclaimer The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject
48. M_LVDS3_N 19 A23 CM_GCLK_P 25 A24 CM_GCLK_N 27 G26 CM CTRL 0 61 www xilinx com 2014 21 Chapter 1 ML628 Board Features and Operation 22 Table 1 12 SuperClock 2 FPGA I O Mapping Cont d FPGA Pin Net Name J32 Pin G25 CM CTRL 1 63 H23 CM CTRL 2 65 J23 CM_CTRL_3 67 J25 CM_CTRL_4 69 K25 CM_CTRL_5 71 D26 CM_CTRL_6 73 E26 CM_CTRL_7 75 1225 CM CTRL 8 77 E25 CM CTRL 9 79 M25 CM CTRL 10 81 M24 CM CTRL 11 83 A25 CM CTRL 12 85 B25 CM CTRL 13 87 L25 CM CTRL 14 89 L24 CM CTRL 15 91 B24 CM CTRL 16 93 C23 CM CTRL 17 95 C24 CM CTRL 18 97 D23 CM CTRL 19 99 K23 CM CTRL 20 101 L23 CM CTRL 21 103 B26 CM CTRL 22 105 C26 CM CTRL 23 107 D24 CM RST 66 User LEDs Active High Figure 1 2 callout 14 XILINX DS10 through 13517 are eight active High LEDs that are connected to user I O pins on the FPGA as shown in Table 1 13 These LEDs can be used to indicate status or anv other purpose determined by the user www xilinx com ML628 Board User Guide UG771 vi 1 Februarv 19 2014 XILINX Table 1 13 User LEDs FPGA Pin Net Name alae N28 APP_LEDI DS17 P28 APP LED2 DS16 K28 APP LED3 DS15 27 APP LED4 3514 27 APP LED5 10513 K26 APP LED6 DS12 P26 APP LED7 10611 R26 APP LEDS DS10 User DIP Switches Active High Figure 1 2 callout 15 Detailed Description The DIP
49. NT M2C L H2 U38 15 FMC2 TCK 1 D29 J31 2 164 1 FMC2 TDI 1 1030 J162 3 1642 FMC2 TDO 1 D31 U38 17 EMC2 TMS 1 D33 Notes 1 This signal is not directly connected to the FPGA The value in the leftmost column represents the device and pin the signal is connected to For example U27 9 U27 pin 9 Table 1 26 Power Supply Voltages for the HPC Connector Voltage Allowable Number Maximum Toleranc Maximum Supply Voltage Range of Pins Amps Capacitive Load Vapj Fixed 2 5V 4 4 5 1 000 pF 3P3VAUx 3 3V 1 0 020 5 150 uF 3P3V 3 3V 4 3 5 1 000 uF 12POV 12V 2 1 5 1 000 uF System Monitor Figure 1 2 callout 22 System Monitor measurements can be monitored using the ChipScope Pro tool The ML628 board provides two ways of setting the System Monitor reference voltage e Jumper pins 1 2 EXT on J15 In this configuration an on board low temperature coefficient 1 25V reference U14 Texas Instruments part number REF3012AIDBZT is connected to System Monitor VREFP e Jumper pins 2 3 INT on J15 In this configuration the FPGA s System Monitor uses an internal reference circuit Note A jumper should be installed in one of the two positions during normal operation Bus Management Figure 1 2 callout 23 The EC bus is controlled through U27 an 8 channel 12C bus multiplexer NXP Semiconductor PCA9547 The FPGA communicates with the multiplexer through PC data and clo
50. TXO 116 N 116 J194 3 565 U4 MGTRXO 116 P 116 J53 967 U3 MGTRXO 116 N 116 J53 967 P2 MGTTXI 116 P 116 J180 3 704 P1 MGTTXI 116 N 116 J180 3 704 T6 MGTRXI 116 P 116 J53 132 T5 MGTRXI 116 N 116 J53 89 M2 MGTTX2_116_P 116 J53 2 766 M1 MGTTX2 116 N 116 J53 2 767 N8 MGTRX2 116 P 116 J53 3 214 N7 MGTRX2_116_N 116 J53 3 214 N4 MGTTX3_116_P 116 J53 2 911 N3 MGTTX3_116_N 116 J53 2 912 M6 MGTRX3_116_P 116 J53 3 052 M5 MGTRX3_116_N 116 J53 3 051 L4 MGTTX0_117_P 117 J54 2 898 L3 MGTTXO 117 N 117 J54 2 899 K6 MGTRX0_117_P 117 J54 3 144 K5 MGTRXO 117 N 117 J54 3 145 K2 MGTTXI 117 P 117 J54 3 926 K1 MGTTXI 117 N 117 J54 3 927 L8 MGTRXI 117 P 117 J54 3 156 L7 MGTRXI 117 N 117 J54 3 156 G4 MGTTX2_117_P 117 J54 3 269 28 www xilinx com ML628 Board User Guide UG771 vi 1 February 19 2014 XILINX ML628 Board User Guide Table 1 17 GTH Transceiver Pins Cont d Detailed Description FPGA Pin Net Name Quad Connector 33 MGTTX2 117 N 117 J54 3 268 H6 MGTRX2_117_P 117 J54 3A75 H5 MGTRX2_117_N 117 J54 3 474 H2 MGTTX3 117 P 117 J54 2 717 H1 MGTTX3 117 N 117 J54 2 717 J8 MGTRX3 117 P 117 J54 2 902 J7 MGTRX3_117_N 117 J54 2 901 F2 MGTTX0_118_P 118 J55 3 492 FI MGTTXO 118 N 118 J55 3 492 G8 MGTRXO 118 P 118 J55 3 433 G7 MGTRXO 118 N 118 J55 3 434 D2 MGTTX1_118_P 118 J55 2 864 D1 MGTTXI 118 N 118 J55 2 865 F6 MGTRXI 118 P 118 J55 3 151 F5 MGTRXI 118
51. Ul Y6 NET MGTRXO 115 P LOC Ul Y5 NET MGTRXO 116 N LOC U1 U3 NET MGTRXO 116 P LOC U1 U4 NET MGTRXO 117 N LOC Ul K5 NET MGTRXO 117 P LOC UL Ko NET MGTRXO 118 N LOC U1 G7 NET MGTRXO 118 P LOC U1 G8 NET MGTRX1 100 N LOC UL BCAl NET MGTRX1 100 P LOC Ul BC42 NET MGTRX1 101 N LOC U1 AV39 NET MGTRX1 101 P LOC U1 AV40 NET MGTRX1 102 N LOC U1 AM39 NET MGTRX1 102 P LOC U1 AM40 NET MGTRX1 103 N LOC U1 AG37 NET MGTRX1 103 P LOC U1 AG38 NET MGTRX1 104 N LOC U1 AC37 NET MGTRX1 104 P LOC U1 AC38 NET MGTRX1 105 N LOC U1 W37 NET MGTRX1 105 P LOC U1 W38 NET MGTRX1 106 N LOC U1 T40 NET MGTRX1 106 P LOC U1 T39 NET MGTRX1 107 N LOC U1 L38 NET MGTRX1 107 P LOC U1 L37 NET MGTRX1 108 N LOC U1 F40 NET MGTRX1 108 P LOC U1 F39 NET MGTRX1 112 N LOC U1 AM6 NET MGTRX1 112 P LOC Ul AM5 NET MGTRX1 113 N LOC U1 AG8 NET MGTRX1 113 P LOC U1 AG7 NET MGTRX1 114 N LOC U1 AC8 NET MGTRX1 114 P LOC U1 AC7 NET MGTRX1 115 N LOC U1 W8 NET MGTRX1 115 P LOC U1 W7 NET MGTRX1 116 N LOC U1 T5 NET MGTRX1 116 P LOC U1 T6 NET MGTRX1 117 N LOC Ul L7 NET MGTRX1 117 P LOC U1 L8 NET MGTRX1 118 N LOC Ul F5 NET MGTRX1 118 P LOC Ul F6 ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Appendi
52. alled 1129 VCC5 Installed 54 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 Z XILINX Appendix B VITA 57 1 EMC HPC Connector Pinout Table B 1 provides a cross reference of signal names to pin coordinates for the VITA 57 1 FMC HPC connector K H z z EE ees sel 0 0 o o 0 z D Q 17 19 0 ES Q z Q z jeni ni NY NY NI PY NY DY 0 4 2 w co wo 0 GND GND VREF A M2C VIO B M2C VIO B M2C GND Figure B 1 LAO1 P CC LA01 N CC GND LAO5 P LA05 N GND LA09 P LAO9 N GND LA13 P LA13 N GND LA17 P CC LA17 N CC GND LA23 P LA23 N GND LA26 P LA26 N GND GND GOD GND GND GND GND LA18 P CC LA18 N CC GN GN LA27 P LA27_N GND GND GND GND UG771_aB_01_100710 FMC HPC Connector Pinout ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com 55 Appendix B VITA 57 1 FMC HPC Connector Pinout XILINX 56 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Appendix C ML628 Master UCF Listing The ML628 master user constraints file UCF template provides for designs targeting the ML628 Virtex 6 FPGA
53. also be driven directly from these headers by attaching the flying wire JTAG cable to pin 2 of each header Figure 1 9 shows a more detailed representation of the isolation jumpers as part of the broader JTAG chain in Figure 1 8 System ACE Controller CFGTCK CFGTDI CFGTDO CFGTMS UG771 1 09 022211 Figure 1 9 JTAG Isolation Jumpers Table 1 8 indicates the FPGA pin name associated with each jumper Table 1 8 JTAG Isolation Jumpers Reference Designator FPGA Pin Name 122 TMS J23 TDI J195 TDO J196 TCK 200 MHz 2 5V LVDS Oscillator Figure 1 2 callout 10 The ML628 board has one 2 5V LVDS differential 200 MHz oscillator U7 connected to the FPGA global clock inputs Table 1 9 lists the FPGA pin connections to the LVDS oscillator The 200 MHz differential clock is enabled by placing two shunts P N across J188 header pins 1 3 and 2 4 LVDS Table 1 9 LVDS Oscillator Global Clock Connections FPGA Pin Net Name U7 Pin AK13 IIO LVDS GC 34 P 4 AKI2 IO LVDS GC 34 N 5 Single Ended SMA Global Clock Inputs Figure 1 2 callout 11 The ML628 board provides two single ended clock input SMA connectors that can be used for connecting to an external function generator The FPGA clock pins are connected to the SMA connectors as shown in Table 1 10 20 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Detailed Description To use
54. and J179 in the outlined and labeled power module location shown in Figure 1 5 Note The GTX and GTH power modules have different connectors and form factors to prevent GTX modules from being connected to the GTH headers and vice versa www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Detailed Description GTX POWER MODULE ee AI ee ee ee eo ee ee ee 00 co LI 000 00 9 UG771_c1_05_022211 Figure 1 5 Mounting Location GTX Transceiver Power Module Table 1 4 describes the nominal voltage values for the MGTAVCC and MGTAVTT power rails It also lists the maximum current ratings for each rail supplied by GTX modules included with the ML628 board Caution The Intersil module features an MGTAVCC voltage adjust header J1 Make sure to REMOVE any jumper across J1 before powering the board with the Intersil module installed Failure to do so may damage the FPGA Table 1 4 GTX Transceiver Power Module Power Supply Rail Nominal Maximum Net Name Voltage Current Rating MGTAVCC 1 025V 10A MGTAVTT 1 2V 6A The GTX transceiver power rails also have corresponding input voltage jacks to supply each voltage independently from a bench top power supply The external jacks are shown in Table 1 4 Caution The GTX module MUST be removed when providing external power to the GTX transceiver rails Table 1 5 GTX External Supply Jacks Pow
55. ansceiver Pins Cont d XILINX FPGA Pin Net Name Quad Connector o AA3 MGTTXO 115 P 115 J49 5 020 AA4 MGTTXO 115 N 115 J49 5 020 Y5 MGTRXO 115 P 115 49 5 269 Y6 MGTRXO 115 N 115 49 5 269 Y1 MGTTXI 115 P 115 J49 4 563 Y2 MGTTXI 115 N 115 J49 4 562 W7 MGTRXI 115 P 115 49 5 134 W8 MGTRX1_115_N 115 49 5 134 W3 MGTTX2 115 P 115 J49 4 238 WA MGTTX2 115 N 115 J49 4 238 V5 MGTRX2 115 P 115 J49 4 534 V6 MGTRX2 115 N 115 J49 4 533 V1 MGTTX3_115_P 115 J49 4 941 V2 MGTTX3_115_N 115 J49 4 941 U7 MGTRX3_115_P 115 J49 4 698 U8 MGTRX3_115_N 115 J49 4 698 Information for each GTX transceiver clock input is shown in Table 1 20 Table 1 20 GTX Transceiver Clock Inputs to the FPGA FPGA Pin Net Name Quad Connector BA37 MGTREFCLKO 100 P 100 J37 BA38 MGTREFCLKO 100 N 100 J37 AW37 MGTREFCLKI 100 P 100 J37 AW38 MGTREFCLKI 100 N 100 J37 AU37 MGTREFCLKO 101 P 101 J41 AU38 MGTREFCLKO 101 N 101 J41 AR37 MGTREFCLKI 101 P 101 J41 AR38 MGTREFCLKI 101 N 101 J41 AN37 MGTREFCLKO 102 P 102 42 AN38 MGTREFCLKO 102 N 102 42 AH35 MGTREFCLKI 102 P 102 42 AH36 MGTREFCLKI 102 N 102 42 AF35 MGTREFCLKO 103 P 103 J43 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Detailed Description Table 1 20 GTX Transceiver Clock Inputs to the FPGA Cont d
56. ard and void the board warranty Power can also be provided through e Connector J141 which accepts an ATX hard disk 4 pin power plug e Jack J234 which can be used to connect to a bench top power supply Caution Do NOT apply power to J122 and connectors J141 and or J234 at the same time Doing so will damage the ML628 board The ML628 board power is turned on or off by switch SW1 When the switch is in the ON position power is applied to the board and a green LED 13536 illuminates 10 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 Z XILINX Detailed Description Onboard Power Regulation Figure l 3 shows the onboard power supplv architecture Note Power regulation jumpers are not shown in Figure l 3 Power Supplv 12V PWR IN External Supply Jacks Ji22 or J141 or J234 Power Controller 1 440 22 UCD9240PFC U8 Switching Module PTD08A020W VCCINT A 1 0V at 20A max U41 Switching Module PTD08A020W VCCINT B VCCINT l 1 0V at 20A max U10 Switching Module PTD08A020W L VCCAUX 2 5V at 20A max U12 Switching Module PTD08A020W l VCCO 2 5V at 20A max U13 Power Controller 2 n2 UCD9240PFC U19 Switching Module PTD08A020W VCC2V5 n 2 5V at 20A max U23 Switching Module PTD08A020W VCC3V3 3 3V at 20A max U22 g PTV12020WAH DC DC Converter VCC5 5 0V at 13A max U31 MGTHAVCC MGTHAVCCRX GTH Transceiver P Modul
57. ck signals mapped to FPGA pins H34 and H33 respectively The PC idcode for the PCA9547 device is 0x70 The bus hosts five components ML628 Board User Guide UG771 v1 1 February 19 2014 www xilinx com XILINX Detailed Description SuperClock 2 module GTH transceiver power supplv module GTX transceiver power supplv module FMC1 FMC2 An PC component can be accessed by selecting the appropriate channel through the control register of the MUX as shown in Table 1 27 Table 1 27 I C Channel Assignments Channel mer I C Component 0 SuperClock 2 module 1 GTX transceiver power supply module 2 GTH transceiver power supply module 3 FMC1 4 FMC2 ML628 Board User Guide www xilinx com 51 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation 52 www xilinx com XILINX ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Default Jumper Positions Appendix Table A 1 shows the standard black shunts that must be installed on the board for proper operation Table A 2 shows the high current red shunts that must be installed to enable the on board power supplies These jumpers must alwavs be installed except where specificallv noted in this user guide Refer to PCB Assemblv Drawing 0431587 for the default placement of all on board jumpers and their respective connectors as thev are located on the board Note Anv connector not sho
58. d bd Hd bd Ltd Ed Hd Dd bd Dd bd bd E bd bd bd bd bd bd pd pu 3 C 5 5 5 C El C C E C C C C C C C C C C C C C C C C C C C C C E C C C C El C C C El C C C C C m 5 5 5 C C C C C C C FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMCI FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 FMC1 HB19 N LOC HB19 P LOC _HB20_N LOC HB20 P LOC HB21 N LOC HB21 P LOC LA00 CC N LOC LA00 CC P LOC LAO01 CC N LOC LAO01 CC P LOC LA02 N LOC LA02 P LOC LA03 N LOC LA03 P LOC _LA04_N LOC LA04 P LOC LA05 N LOC LA05 P LOC _LA06_N LOC _LA06_P LOC _LAO7_N LOC LA07 P LOC LA08 N LOC LAO08 P LOC LA09 N LOC LA09 P LOC _LA10_N LOC _LA10_P LOC LA11_N LOC _LA11_P LOC _LA12_N LOC _LA12_P LOC _LA13_N LOC _LA13_P LOC _LA14_N LOC _LA14_P LOC _LA15_N LOC LA15 P LOC _LA16_N LOC _LA16_P LOC _LA17_CC_N LOC _LA17_CC_P LOC _LA18_CC_N LOC LA18
59. egulator VCC2V5 2 5V J31 J175 20A 0 6V to 3 6V PTDOSAO20W U22 Adjustable switching regulator VCC3V3 3 3V J30 1174 20A 0 6V to 3 6V 5V auxiliarv power PTV12020WAH U31 Switching regulator VCC5 5 0V J129 J173 13A 5 0V Notes 1 The UCD9240PCF U8 synchronizes the PTD power stages U10 and U41 so that a maximum of 40A can be supplied to the VCCINT rail 12 Using External Power Sources The maximum output current rating for each power regulator is listed in Table 1 1 If a design exceeds this value on any power rail power for that rail must be supplied through the external power jack using a supply capable of providing the required current Each power rail has a corresponding jack and jumper that is used to supply voltage to the rail using an external power supply The jack jumper and regulator for each power rail is listed in Table 1 1 Caution The power regulation jumper see Power Regulation Jumper column inTable 1 1 must be removed before applying external power to the power rail through its corresponding supply jack Caution The external power supply jacks have a maximum current rating of 15A ML628 Board User Guide UG771 vi 1 February 19 2014 www xilinx com XILINX Detailed Description Disabling Onboard Power Voltage regulators U10 U12 U13 U22 U23 and U41 are disabled by installing a jumper at J289 TI PWR INHIBIT Voltage regulator U31 is disabled by installing a jumper across pins
60. er Supply Rail External Supply Net Name Jack MGTHAVCC J279 MGTHAVCCRX J280 MGTHAVTT J282 MGTHAVCCPLL J283 Active Heatsink Power Connector An active heatsink is provided for the FPGA Figure 1 6 A 12V fan is affixed to the heatsink and is powered from the 3 pin header J101 ML628 Board User Guide www xilinx com 15 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation 16 XILINX Figure 1 6 Active Heatsink UG771 c1 06 022211 The fan power connections are detailed in Table 1 6 and shown in Figure 1 7 Table 1 6 Fan Power Connections Fan Wire Header Black J101 GND Red J101 12V Blue Not Connected www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Detailed Description UG771 c1 07 022211 Figure 1 7 Fan Power Connector J101 FPGA Configuration Figure 1 2 callout 2 The FPGA is configured in JTAG mode only using one of the following options e Platform Cable USB e Parallel Cable IV e Parallel Cable III e System ACE controller Detailed information on the System ACE controller is available in DS080 System ACE CompactFlash Solution The FPGA is configured through one of the aforementioned cables by connecting the cable to the JTAG cable connector J1 The FPGA is configured through the System ACE controller by setting the 3 bit configuration address DIP switches SW3 to select one of eight bitstreams
61. inch to separate connectors located near the perimeter of the FPGA MGTTXO 116 and MGTTXO 116 N are terminated to removable SMA connectors Molex part number 73251 1851 J185 and J194 respectively MGTTX1 116 P and MGTTXI 116 N are terminated to probe pad J180 Figure 1 12 4 80 gt gt MGTTX0_116_P 104 15 20 MGTTXO 116 N 15 Note Dimensions are in mils 1 mil 0 001 inch UG771_c1_12_030211 Figure 1 12 Microprobe Test Pad Dimensions J180 Information for each GTH transceiver pin is shown in Table 1 17 Table 1 17 GTH Transceiver Pins FPGA Pin Net Name Quad Connector m T43 MGTTXO 106 P 106 J50 3 025 T44 MGTTXO 106 N 106 J50 3 025 U41 MGTRXO 106 P 106 J50 2 135 U42 MGTRXO 106 N 106 J50 2 135 P43 MGTTXI 106 P 106 J50 3 337 P44 MGTTXI 106 N 106 J50 3 337 T39 MGTRXI 106 P 106 J50 2 250 T40 MGTRXI 106 N 106 J50 2 250 M43 MGTTX2 106 P 106 J50 2 793 26 www xilinx com ML628 Board User Guide UG771 vi 1 February 19 2014 XILINX Table 1 17 GTH Transceiver Pins Cont d Detailed Description FPGA Pin Net Name Quad Connector legal M44 MGTTX2 106 N 106 J50 2 793 N37 MGTRX2 106 P 106 J50 2 192 N38 MGTRX2 106 N 106 J50 2 192 N41 MGTTX3 106 P 106 J50 2 800 N42 MGTTX3_106_N 106 J50 2 799 M39
62. l D1 NET MGTTX1 118 P LOC U1 D2 NET MGTTX2 100 N LOC Ul AW41 NET MGTTX2 100 P LOC U1 AW42 NET MGTTX2 101 N LOC Ul AR41 NET MGTTX2 101 P LOC U1 AR42 NET MGTTX2 102 N LOC Ul AL41 NET MGTTX2 102 P LOC Ul AL42 NET MGTTX2 103 N LOC Ul AG41 NET MGTTX2 103 P LOC U1 AG42 NET MGTTX2 104 N LOC Ul AC41 NET MGTTX2 104 P LOC Ul AC42 NET MGTTX2 105 N LOC Ul W41 NET MGTTX2 105 P LOC U1 W42 NET MGTTX2 106 N LOC Ul M44 NET MGTTX2 106 P LOC Ul M43 NET MGTTX2 107 N LOC Ul G42 NET MGTTX2 107 P LOC U1 G41 NET MGTTX2 108 N LOC U1 A42 NET MGTTX2 108 P LOC U1 A41 NET MGTTX2 112 N LOC Ul AL4 NET MGTTX2 112 P LOC U1 AL3 NET MGTTX2 113 N LOC U1 AG4 NET MGTTX2 113 P LOC U1 AG3 NET MGTTX2 114 N LOC U1 AC4 NET MGTTX2 114 P LOC U1 AC3 NET MGTTX2 115 N LOC Ul W4 NET MGTTX2 115 P LOC U1 W3 NET MGTTX2 116 N LOC Ul M1 NET MGTTX2 116 P LOC U1 M2 NET MGTTX2 117 N LOC U1 G3 NET MGTTX2 117 P LOC U1 G4 NET MGTTX2 118 N LOC U1 A3 NET MGTTX2 118 P LOC U1 A4 NET MGTTX3 100 N LOC U1 AV43 NET MGTTX3 100 P LOC Ul AV44 NET MGTTX3 101 N LOC U1 AP43 NET MGTTX3 101 P LOC U1 AP44 NET MGTTX3 102 N LOC Ul AK43 NET MGTTX3 102 P LOC Ul AK44 NET MGTTX3 103 N LOC U1 AF43 NET MGTTX3 103 P LOC Ul A
63. mtec BullsEye connector pads for the GTX transceivers and reference clocks e Power status LEDs e General purpose DIP switches LEDs push buttons and test I O Two VITA 57 1 FMC HPC connectors e USB to UART bridge PCbus e PMBus connectivity to on board digital power supplies e Active cooling for the FPGA ML628 Board User Guide www xilinx com 7 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation XILINX The ML628 board block diagram is shown in Figure 1 1 Caution The ML628 board can be damaged by electrostatic discharge ESD Follow standard ESD prevention measures when handling the board FMC Interface FMC1 FMC2 ANSI VITA 57 1 2008 v1 1 Transceiver and USB to UART Transceiver Clock SMA Bridge GTH QUAD 106 GTH QUAD 107 GTH QUAD 108 GTH QUAD 116 GTH QUAD 117 Svstem Monitor FPGA Power Source GTH QUAD 118 Interface On board Regulation Virtex 6 FPGA VCCINT 1 0V at 40 Amps XC6VHX380T 2FFG1923C VCCO 2 5V at 20 Amps Transcelver and VCCAUX 2 5V at 20 Amps Transceiver Clock SMA System ACE Controller I2C Bus Management GTX QUAD 100 GTX QUAD 101 GTX QUAD 102 GTX QUAD 103 GTX QUAD 104 Auxiliary Power GTX QUAD 105 On board Regulation GTX QUAD 112 5 0V at 13 Amps GTX QUAD 113 3 3V at 20 Amps GTX QUAD 114 2 5V at 20 Amps GTX QUAD 115 User GPIO 200 MHz LVDS Clock Push Buttons Differential User SMA Clocks DIP Switches a and LEDs Singe Ended User SMA Clocks
64. n 1 VBUS 5V into the CP2103 USB to UART bridge at U26 Used to sense USB network connection 2 USB DATA N Bidirectional differential serial data N side 3 USB DATA P Bidirectional differential serial data P side 4 GROUND Signal ground The CP2103 supports an IO voltage range of 1 8V to 2 5V on the ML628 board The connections between the FPGA and CP2103 should use the LVCMOS25 IO standard UART IP for example Xilinx XPS UART Lite must be implemented in the FPGA fabric The FPGA supports the USB to UART bridge using four signal pins e Transmit TX e Receive RX e Request to Send RTS e Clear to Send CTS Connections of these signals between the FPGA and the CP2103 at U26 are listed in Table 1 22 Table 1 22 FPGA to U26 CP2103 USB to UART Bridge Connections FPGA Pin FPGA Function Net Name U26 Pin U26 Function E27 RTS output USB_CTS 22 CTS input F27 CTS input USB_RTS 23 RTS output B29 TX data out USB_RX 24 RXD data in C29 RX data in USB_TX 25 TXD data out The bridge device also provides as many as 4 GPIO signals that can be defined by the user for status and control information Table 1 23 Table 1 23 CP2103 USB to UART Bridge User GPIO FPGA Pin Net Name U26 Pin E28 USB GPIOO 19 F28 USB GPIO1 18 M27 USB GPIO2 17 N27 USB GPIO3 16 A royalty free software driver named Virtual COM Port VCP is available from Silicon Laboratories
65. pheral Controller EPC Data Sheet DS606 XPS IIC Bus Interface v2 00a Data Sheet UG770 HW CLK 101 SCLK2 SuperClock 2 Module User Guide To find additional documentation see the Xilinx website at http www xilinx com support documentation index htm ML628 Board User Guide www xilinx com 71 UG771 v1 1 February 19 2014 Appendix D References XILINX 72 www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014
66. rlink to a website URL Go to http www xilinx com for the latest speed files www xilinx com ML628 Board User Guide UG771 v1 1 February 19 2014 XILINX Chapter 1 ML628 Board Features and Operation This chapter describes the components features and operation of the ML628 Virtex 6 FPGA GTX and GTH transceiver characterization board The ML628 board provides the hardware environment for characterizing and evaluating the GTX and GTH transceivers available on the Virtex 6 XC6VHX380T 2C FFG1923 FPGA ML628 schematics bill of material BOM layout files and reference designs are available online at http www xilinx com products boards ml628 reference_designs htm ML628 Board Features e Virtex 6 XC6VHX380T 2C FFG1923 FPGA e On board power supplies for all necessary voltages e Power supply jacks for optional use of external power supplies e JTAG configuration port for use with Platform Cable USB or Parallel Cable III IV cables e System ACE controller e Separate power modules supporting all Virtex 6 FPGA GTX and GTH transceiver power requirements e fixed 200 MHz 2 5V LVDS oscillator wired to global clock inputs e Two single ended global clock inputs with SMA connectors Two pairs of differential global clock inputs with SMA connectors e SuperClock 2 module supporting multiple frequencies e Six Samtec BullsEye connector pads for the GTH transceivers and reference clocks e Ten Sa
67. stem ACE Controller Figure 1 2 callout 6 The onboard System ACE controller U25 allows storage of multiple configuration files on a CompactFlash card These configuration files can be used to program the FPGA The CompactFlash card connects to the CompactFlash card connector U24 located directly below the System ACE controller on the back side of the board System ACE Controller Reset Figure 1 2 callout 7 Pressing push button SW2 RESET resets the System ACE controller Reset is an active Low input Configuration Address DIP Switches Figure 1 2 callout 8 DIP switch SW3 selects one of the eight configuration bitstream addresses in the CompactFlash memory card The switch settings for selecting each address are shown in Table 1 7 Table 1 7 SW3 DIP Switch Configuration Address ADR2 ADR1 ADRO 0 oO o o 1 0 0 co 2 O C O 3 O C C 4 C O O 5 C O C 6 C C O 7 C C C Notes 1 O indicates the open switch position logic 0 2 Cindicates the closed switch position logic 1 JTAG Isolation Jumpers Figure 1 2 callout 9 The group of four 2 pin headers shown in Figure 1 9 provide the option to isolate the FPGA JTAG interface from the System ACE controller by removing the shunts from all ML628 Board User Guide www xilinx com 19 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation XILINX four headers The FPGA JTAG interface can
68. the FPGA as shown in Figure 1 10 The GTH transceivers are grouped into six sets of four RX IX lanes Four lanes are referred to as a Quad Note Figure 1 10 is for reference only and might not reflect the current revision of the board ML628 Board User Guide UG771 v1 1 February 19 2014 24 www xilinx com XILINX Detailed Description FI U 29 1 L m VIRTEXU XILINX A d 0 6 UG771_c1_10_030111 Figure 1 10 GTH Quad Locations Each GTH Quad and its associated reference clock CLKO are routed from the FPGA to a connector pad which is designed to interface with Samtec BullsEye connectors such as the Samtec HDR 155805 01 BEYE cable assembly Contact Samtec Inc for other cable assemblies Figure 1 11 A shows the connector pad Figure 1 11 B shows the connector pinout A O Le 0000 NO 60 9 9 Q 6020200 GTH Connector Pad GTH Connector Pinout UG771 c1 11 032211 Figure 1 11 A GTH BullsEye Connector Pad B GTH BullsEye Connector Pad ML628 Board User Guide www xilinx com 25 UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation XILINX Two GTH transmitters are not connected to a BullsEye connector pad These are transmitter pairs MGTTXO 116 P MGTTXO 116 N and MGTTXI 116 P MGTTXI 116 N To provide optimum test conditions for these transmitters both pairs are routed on very short traces less than 1
69. to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at www xilinx com legal htm tos Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS APPLICATIONS RELATED TO I THE DEPLOYMENT OF AIRBAGS Il CONTROL OF A VEHICLE UNLESS THERE IS A FAIL SAFE OR REDUNDANCY FEATURE WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR OR III USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS Copyright 2011 2014 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zvnq and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History
70. uts J167 J170 SuperClock 2 module User LEDs active High DS10 DS17 User DIP switches active High SW7 User push buttons active High SW4 SW6 User test I O J285 GTX transceiver Connector Pad GTH transceiver Connector Pad USB to UART bridge J9 and U26 FMC1 connector J290 FMC2 connector J441 System Monitor bus management U27 UG771 1 02 030111 Figure 1 2 ML628 Board Features ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 Chapter 1 ML628 Board Features and Operation Z XILINX Power Management Numbers la through 1j refer to the callouts in Figure 1 2 1a Main power switch SW1 1b 12V Mini Fit connector J122 lc 12V ATX connector J141 1d Power regulation jumpers J30 J32 J61 J102 J104 J105 J129 le Regulation inhibit J289 1f External power supply jacks J234 JA40 J223 J174 J98 J175 J227 J173 J220 1g TI PMBus cable connector J14 1h GTX transceiver power supply module 1i GTH transceiver power supply module 1j Active heatsink power connector Board Power and Switch The ML628 board is powered through J122 using the 12V AC adapter included with the board J122 is a 6 pin 2 x 3 right angle Mini Fit type connector Caution Do NOT plug a PC ATX power supply 6 pin connector into J122 on the ML628 board The ATX 6 pin connector has a different pinout than J122 Connecting an ATX 6 pin connector into J122 will damage the ML628 bo
71. wn in Table A 1 should be left open for normal operation Table A 1 Standard Shunts Connector Name Shunt Position Quantitv Pins Jumper Label 1286 PMBUS CTRL Installed 1 1 2 GND 24 AUX POR Installed 1 1 2 AUTO J176 VFS 0 Installed 1 1 2 VCCAUX 7188 SYSTEM CLOCK Installed Horizontally 2 1 3 2 4 LVDS 292 PMBUS ALERT Installed 1 2 3 AFX J293 PMBUS CTRL Installed 1 2 3 AFX J294 PMBUS CLK Installed 1 2 3 AFX 295 PMBUS DATA Installed 1 2 3 AFX 19 PMBUS LEVEL TRANSLATION Installed 1 1 2 AFX CABLE 287 PMBUS LEVEL TRANSLATION Installed 1 1 2 AFX J162 JTAG CHAIN Installed 1 1 2 DUT ONLY J4 SYSTEM ACE CLK Installed 1 1 2 ON J22 SYSACE JTAG ENABLE Installed 1 1 2 J23 SYSACE JTAG ENABLE Installed 1 1 2 J195 SYSACE JTAG ENABLE Installed 1 1 2 J196 SYSACE JTAG ENABLE Installed 1 1 2 J15 SYS MON Installed 1 1 2 EXT J31 FMC1 JTAG Installed 1 1 2 BYPASS J64 FMC2 JTAG Installed 1 1 2 BYPASS Notes 1 Italicized entries in the Name column are not visible in the PCB silkscreen labels ML628 Board User Guide www xilinx com UG771 v1 1 February 19 2014 53 Appendix A Default Jumper Positions XILINX Table A 2 Digital Power Shorting Plugs Connector Name SEE J30 VCC3V3 Installed J32 VCC2V5 Installed J102 VCCINT A Installed J61 VCCINT_B Installed J104 VCCAUX Installed J105 VCCO Inst
72. x C ML628 Master UCF Listing XILINX DD DD SS S S S S S SS SGS S S SS SS S SS S SS SS SS S SGS S SS S SS SS SS S SS 32332333323 E E Ed D Bd E Ed Dd Dd Bd Dd Dd D Bl Dd Dd Bd E Ed D Dd Bd bd Bd B B Ed Dd Bd d ed Dd Dd Bl Bd Bd B EB Ed Dd Bd td Dd Dd Dd Bl bd Bd Bl E Ed Dd Bd bj bd Dd D Bl Bd C C C C C 5 C C C C C C El C C C C C C C C C C El C C C 5 C C C C C C C C C 5 5 E C C E C C C C C C C C C C C C C C C MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT PRX2 100 N RX2 100 P RX2 101 N RX2 101 P RX2 102 N RX2 102 P RX2 103 N 2 103 P RX2 104 N RX2 104 P RX2 105 N RX2 105 P RX2 106 N RX2 106 P RX2 107 N RX2 107 P RX2 108 N RX2 108 P ri n ri ni ri Ti ci ta ci n ri n ri ni ci Ti ci n ci E ci ri ni ri ri Fi ri Ti ci ta ci ri ri ci MGT RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 RX2 11 12_N

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