Home

EB78 - MachXO2-4000HC Control Development Kit User's Guide

1. 5 4 3 z 3 2 2 Resistor Mux between Prototype Header ue MachXO2 Bank 0 and Video Channel 2 7 1LVDS 1 NE e PB4A PBSA PBSA yaa X02_IN3_1_N PB4B PB3B PB3B 10 IN 2 p amp lt AOBINS ORSO DNI _______ 8 XO2 SPI SEBTOM oS PTOANPTOANPTOAN 02 OU TS E oura p GPIO 0 1 01 9 SERTC1 SEHI T 9 PB4C PBSA PB4A CSSPIN PT9B PT9BYPT9BA XO2_OUT3_N 11 n xoz cpio o XO GPIO 0 Ro 9 SERTC1 SMBA 6078 0 M XO2 CLKOUT P 2 N 5 DNI XO2 1 Aa P XE XO2 Ni 1P PTIOAVPTTIANPTUTAS KOS CLOUT m t0 XO2 1 2 lt RNI S ONL IN1 1 OW OS INN 7 PTIOBAPTTTBNPTITBA 22_ 2 CIKOULN _ 2 CLKOUT 11 XO2_IN1_1_N PB6B PB6B PB7B X02_GPIO_1 XO2 GPIO 1 401 8 CLK 0278 0 60 ROSE DNI Mi PTIOC PTI2C PTI3C 84 SE EN R XO2 CLKIN 2 33 DNI 02 10 2 9 SERTFG1 SERTFGI Di Na MCLK CCLK PT10D PT12D PT13D TDI KK TD 63 10 xO2_CLKIN_2_P lt lt ANA SERTFG1 MISO 0 MWR 1 Di PB6D PB8B PB9B SO SPISO B5 XO2 OUT2 P 2 eoi 78 XO2 SPI OUT 1 PNG PTI 1A PTISAYPTI4A4 es xoz oure N 2202 OUT P 11 XO2 cpio 2 XO2 G
2. C107 0 duF DI 3 3 VCC33 1018 O C89 0_iuF 0 tuF DI DI u7 ad lt 3 999826 145 HVOUTI vecioss 02 5 2 ONZ 598353 HVOUT 5 ICCIO33 Sen VMON3 76 5 perpe VMON4 5 SMBA_OUT3 12 2 OUTS __ VMONS OUT4 i PM LEDT VMON6 OUTS 36 PM_LEDZ VMON7 OUT6 5 PM LED3 VMON8 OUT 8 PM_OUT8 7 VMON9 ours PM OUTS 7 VMON10 VMON10 OUTS 5 PM OUTIO QUIT PM OUTIT PM_IN1 E INT OUT PM OUTI2 PM_IN2 IN2 OUT12 gt PM OUTIS IN3 OUTI3 PM_OUT14 IN4 QUT14 TDISEL ATDI S PM METK 6 PM TDI 16 TDI MCLK Fag 6 PM_TMS B ig RESETB 6 22 ick 6 TDO 30 41 SCL GNDD 3t 2 B 358 SCL GNDD 4 SDA 3 38 SDA 7 ispPAC POWRTOT4A Di Voltage Ramp Circuit VCC33 VCC33 R196 HVOUT2 PM LEDs LED LED LED LED D10 D9 D PM_LEDO PM_LED1 PM_LED2 9 RN4 RN2 4 470 DI 7 HVOUT1 7 HvouT2 7 gt gt PM SMBA OUTS 14 PM_OUT8 3 5 PM_OUT9 5 2 OUTI1 PM_OUT12 PM_OUT13 PM_OUT14 PM_PLDCLK 7 14 PM_MCLK 7 14 PM DIP SWITCH vecs3 PM DIP Switch sw2 PM INS PM_IN4 SW DIP_2 DI R164 DI 10K YRY63_ DI 10i 5555 N E Moore Court Hills
3. MOON Clkcin S Touta p INTUS t 3x m 5 Oe EA Toure H 02 1 Shield QE9 ga ___ 2 TX 2 R102 s 2 Pourtan Pay TOUTE E gt TOUTS PZ Reo 3x auem His sea 5 14 Plug Video Quoi 28 rsvp Ti high 8 TxCLKOUTN page a Ryo 2 N 5 Power HI AE Pg Wii TXCLKDUTP CLKIN 2 P GND for 5V 1 3 0012 ook nw 2 3 9012 m NS Lvoc 2 16 R247 DFO 2 Q011 LVDSVCC Hot Plug Detoct Aw aor gp Qo L3 LYDSGND STAND EJ 43 STAG G08 LYDSGND 33 LYDSGND PDN_2 6 TXINA Z 34 NS PVCC 2 37 2 DATAO POON 2 SE Nisz pee TMOS Datao ig fTMDS 2 DATAT P 5 4 panes 4 13 2 PLLGND 36 19 DVDD 2 o QE3 Tap TXINB 2 7 _ _ 9 4 1 QE QE mos Das aE a TOR 88 151002 N 2 R113 Shiela 2 7 DGND mos 2 DGND 3 905 TX OUT N 2 R208 TMDS_Clack 24 TMDS 2 CLK N _ OUT1 P 2 R207 DNI AMD O look ILOWN 2 18 M GAIL 28 902 TX OUT2 N 2 109 DNI Ea 90 4 MDR TX OUT2 P2 B06 DNI 44 TXCLKIN 2 0590 287 U18 MDR_TX_OUT3_N_2 R104 Analog Red 1 ODCK MDR_TX_OUT3_P_2 FOS DNI
4. 1 DATA TMDS 1 CLK P 93 5 QE13 24 1 TXINZ T TxOUTIP RxCP i az 4 E MDSL DATALP IMDS L Clk in ae 4 Toutan pi REQUE E IN2 1 N 34 26 avon Gee uod 1 A BENZ noura pig BRE OUR ILL Data 2 98 cos 8 87 gt ot Pn Mo prio 39 nsvo cro niom 99 E posco pi BOE 5 GU 45V Power 008 8 TxGLKOUTP rra GG INL 199 ock my Gon wwosvoo Hot Pug Detect 18 RAB Ray D 986 Su LL PIS 3 Lvoganp 36 STAGN Hie ST 47 LVDSGND 49 or H 16 NS PVCC 1 LI MOS DATAO N PON 9E 8 A anni 18 MDS 1 DATAO P 8 9 5 14 TMDS_Datad Plano 3 45 6 aes PLLGND TMOS Shieid 1 7 amp ote ee 1 DVDD QE1 49 xine 1 voc TMDS_Datas 2 DVDD DOBE voc H7 TMDS_Data5 ae oo 58 Vee rae TX QUTO N R218 22 55 TMDS Clock 22 4 DGND 5 DGND 5 GND 23 mos 3 53 QUT N 1 R216 TMDS_Clock 004 GND TMS 24 TTBS CKN ma E MOR OUTI P L R215 DNI 18 51 28 OVOD m oom E QUT N 1 R214 43 48 DNI 43 9 78 OVOD 44 TXCLKIN 1 DSe0CR287 119 TX OUT3 1 R210 DNI Analog Red oock TX OUT3 P 1 R209 DNI
5. LATTICE SEMICONDUCTOR MachXO2 4000HC Control Development Kit User s Guide November 2013 Revision 78 01 1 oma 2 4000 Control Development Kit LATTICE User s Guide Introduction Thank you for choosing the Lattice Semiconductor MachXO2 4000HC Control Development Kit This guide describes how to start using the MachXO2 4000HC Control Development Kit an easy to use platform for rapidly prototyping system control designs using MachXO2 PLDs Along with the evaluation board and accesso ries this kit includes a pre loaded control system on chip Control SoC design that demonstrates board diagnostic functions including control voltage monitoring time stamps and data logging to non volatile memory The Power Manager II ispPAC POWR1014A and 8 bit LatticeMico8 microcontroller are featured in the board and demonstration design The contents of this user s guide include demo operation top level functional descriptions of the various portions of the evaluation board descriptions of the on board connectors switches a complete set of schematics and bill of materials for the MachXO2 4000HC Control Evaluation Board Note Static electricity can severely shorten the lifespan of electronic components See the MachXO2 4000HC Control Development Kit QuickSTART Guide for handling and storage tips Features The MachXO2 4000HC Control Development Kit includes MachXO2 4000HC Control Evaluation
6. NCP1117ST33 SOT_223 NCP1117ST33T3G ONSemi D 91 1 912 NCP1117ST18 SOT_223 NCP1117ST18T3G ONSemi D 92 1 MCP6L71R SOT_23_5 MC MCP6L71RT E OT Microchip D 93 1 uta AT25DF041A SH B SOIC_8 AT25DF041A SH B Atmel D 94 1 015 AT25DF041A MH B UDFN AT25DF041A MH B Atmel DNI 95 1 U16 AD8604ARZ 14_SOIC AD8604ARZ Analog Devices D 96 1 017 Value MRAO8A_M LP3879MR 1 2 National DNI 97 1 018 DS90CR287 TSSOP_56 DS90CR287MTD NOPB DNI 98 1 DS90CR287 TSSOP_56 DS90CR287MTD NOPB D 99 1 020 FT2232HL tqfp64_0p5_12p2x12p2_h1p6 FT2232HL FTDI D 100 1 121 93LC56 SO8 so8 50 244 93LC56T I SN Microchip MW D 101 Jx CTS CB3LV 3C 25MHz SMD 7 00mm x 5 00mm CB3LV 3C 25M0000 CTS 980 DOO MAS DNI 102 1 49 24 000MABJ UT SMD HCM49 24 000MABJ UT Citizen Finetech 24000 103 1 12MHZ crystal_4p_3p2x2p5 7M 12 000MAAJ T TXC cip 26
7. B t SPDR BAG 303 joz 6 13801 0510 5 g PB15C PB19A PB23A PT15D PT20D PT28D PROGRAMN c X02_GPIO_6 X92 GPIO 6 Quyen I 7 PB15D PB19B PB23B SERTC 2 LPDDR RASn PTIGAWPTZIAWPT24A HOi SERTG 5 ni 9 ne ow ASE IOS MB PB18A PB21A PB24A PTIGBAPT2TBA PT24B 211 SERC SERTC A PB18B PB21B PB24B 7 X92 GPIO 7 13701 NOSE 16 22 25 ei sene 2 SERTFG XC2 N0 2 P 26 DNI 2 IO 8 05 108 PT1 PBI8C PB22A PB27A PT16D PT22BYPT25BA p ES gt gt SERTFG 10 x02_INo_2 P NE EE PB18D PB22B PB27B X02_GPIO_8 15201 XO2 IN21 P Mii 17 2 27 55 TEDDE WEN 2 Pio 8 2 XO2 IN2 1 P C xO2 IN2 1 N Pia PB20A PB24A PB29A PT17B PT28BYPT27BA I gt LPDDR WEn X02_IN2_1_N PB20B PB24B PB29B 2 IND AN 8 R24 DNL U Xo2 GPIO ee N12 PT17C PT24C PT28C d LPDDR_CASn 6 9 11 SERTFG2 lt lt SERTFGZ 5 257 DNI Pis PB20C PB25A PB30A SN PT17D PT24D PT28D DONE 5 91 55 PDDR CSn U 9 lt lt ma 11 SERTFG2 KKwiosr R253 DI PB20D PB25B PB30B SI SISPI AB VCCIO33 7 8 Xo2 IN vecioo lead 2 vccioo m Swe L9 BRERA veclo2 True LVDS 98 i Is Ies kes 801 sERTC Pi o oe 1 2K 2K 4K 2nd Fn
8. Enter name and choose an icon for the connection Name 5 Specify a Name and Icon for the new connection Click OK The Connect To dialog appears 6 Select the COM port identified in Step 3 from the Connect using list Click OK Figure 7 Selecting the COM Port Connect To Enter details for the phone number that you want to dial Country region Area code Phone number Connect using COM3T 7 The Properties dialog appears where is the COM port selected from the list 8 Select the following Port Settings and click OK Bits per second 115200 Data bits 8 Parity None Stop bits 1 Flow control None Figure 8 COM Port Properties COM31 Properties Port Settings Bits per second 115200 Data bits 8 Parity None Stop bits 1 Flow control None Restore Defaults OK Apply oma 2 4000 Control Development Kit LATTICE User s Guide 9 The HyperTerminal window appears 10 From the MachXO2 4000HC Control Evaluation Board press the reset push button with reference designator 51 The Control SoC demo main menu appears Setting Up Linux Minicom Minicom is a terminal program found with most Linux distributions It can be used to communicate with the MachXO2 4000HC Control Evaluation Board To setup Minicom 1 Check active serial ports dmesg grep tty Note the tty label assigned to the USB port 2
9. LATTICE 5555 N E Moore Court Hillsboro Oregon 97124 www latticesemi com Title SW LED Crystal Header ize Project B 2 Control Board alo Tuesday June 26 2012 Bheet 7 of 1 14 16 User s Guide LPDDR 128Mb 4 Meg x 4 banks x 8 data 4MBit SPI VCC18 gess Package SOIC8 WIDE en ines eun Di Opie or 8 5 XO2 SPI CSO 14 aoacoccoc 98 ch X02 SPLCLK 88955858 aw X02_SPI_OUT SPLIN 41 docs vs XO2 SPL OUT 7 14 LPDDR AO LPDDR_AO AO AT25DFO41A SH B LPDDR_A1 ey pao 48 E0BR_D8 5 14 pee LPDDR_A2 KTI A Dao LPDDR_DO1 0 LPDDR D U LPDDR_A3 Q1 ____ _002 Loar LPDDR A3 A3 DQ2 68 008 092 9 LPDDR LPDDR A4 K2 C7 LPDDR A4 A4 Gg LFDDR DO4 39 LPDDR i 5 DQ4 Dz __ lt LFDDR_DO4 U15 LPDDR A6 6 Das HDs POOR DeeS 005 14 LPDDR_A7 J2 58 LPDDR DO6 LPDDR A7 AT HES BDDR DQ 5 LPDDR_DO6 i4 8 Tu LPDDR AB 7 LFDDR_DO7 5 1 vec 5 LPDDR AB AB DQ 55 LPDpR m Rest LPDDR A9 CPDDRCAIS
10. 008 xm W D LPDDR A10 A10 0 iuF 4 2 02 SPI OUT z LPDDR_A11 H2 VCC18 bi Vs LPDDR 11 11 0010 LPDDR A12 A12 pati LPDDR CK 62 Dat LPDDR Cn cke bata Package UDFN LPDDR_CKE QQ PPR 0015 LPDDR cen 081__ cs 2 4000 Control Development Ki LPDDR RASn G9 LPDDR RASI RAS GB case UDM 17 upas LPDDR BAO H8 LPDDR_BAO LPDDR BAi Ha LPDDR HS LDM Es trope LOGS LPDDR LDM i4 LPDDRWEn G7 LDQS 22 58 LPDDR_LDQS 14 LPDDR_WEn 3 we E Lower Byte Mask amp Strobe NC 5558 MT46H16M16LFBF Us Micro SD Card Socket 29009090 vocas R186 25585555 gt 225865 u1 14 uSD_DAT2 3 DAT2 14 u D_DAT3 55 3 CD DATS 5 14 uSD_CMD 5 CMD 14 uSD_CLK paj 950 B tuF LPDDR DQO 9 VCC18 14 uSD DAT pi 10 LPDDR DQ2 17 vos LPDDR DQS 12 5 LPDDR DO4 13 4 microSD Socket LPDDR DO5 14 3 LPDDR_DQ6 _ 15 LPDDR DQ7 16 1 RN2 RN E Y K DNI Empty External Pull UP resistors The internal XO2 resistors are used for bias 5555 N E Mo Court LAT 7 ICE Hillsboro Oregon 97124 4 www latticesemi com Ei ri
11. 18 Levon Power B pd m Nof ay we pono is Bit mokour 8 meiour zy Fire vaoo 1 1 Pup Dott wee x i vee moms eine a vp owo RE at a 36 GND vier quos 17 uo pes vamo Hes EDGE F pono 8 DATO TOS 35 DGND 64 19 pene ie nos pases Ui ea ER E al duc RESERVED Te o GND x meer CIL 7 49 22 one we Ho 221 cos CTLUATIDKT TMDS CLK P 23 OS HE ssa REMA se BE BUG pow 288 gi TFP410 a Red Za Analog Horizontal Sync SH Analog Ground 1 kra Grande wes LED will be OFF when a powered moche tenance co vl iS MSEN 55 08 Eur boue e adi bee 3 a a p Lour oF 1 2 Ns TOP Package View 3 Drain d ais JE uit uie ul 2 Source HILATTICE 22 25 www latticesemi com ite Video Output im Project 5 2 Control Board Tuesday June 26 2012 Ehet 11 o 14 T 20 User s Guide 2 4000 Control Development Ki PWM Analog Signal Output VCC33 o C69 0 1
12. 2 19 2 onas Analog Green 28 OGND CLKOUT 18212 Analog Bho 45 0101 MOCDCGIKQUT P RA A ONE 58 Analog Horizontal Sc 78 pe L8 os Analog Ground_1 F8 47 Tys 1 Analog Ground 2 TLPVDD 1 97 WU az E 98 scor 8 AUE MDR Connector Supporting Circuits D DVDD 1 470 LED will be ON when link is 55 active LED_Green sco high 3 a SCDT i 5 1 DI PWROWN 1 2 Di NS STB 1 D DFO TOP Package View R230 Di STAGN 1 3 Drain R242 sri OCK NV sor 23 B237 NS Y Do Ed 1 Gate 2 Source 18 Camera Link RX Frame Grabber ODCK opposite edge from Video Source 2 iHLATTICE 5555 Moore Court Hillsboro Oregon 97124 www latticesemi com Video Input 1 zo Project 2 Control Board id oat Tuesday June 26 2012 s d i4 LAT SEMICONDUCTOR Figure 16 Video Input 1 z 1 z I E I z I 1 User s Guide 2 4000 Control Development Ki Video Input Source 2 DVI or MDR for direct 7 1LVDS DVI Connector DVI TMDS Decoder LVDS Translator Resistor
13. DI R147 dE 2 2K DE DI T Voce TERM 1 4 R154 DI AUDIO SIG 10uF TERM2 H DI CMA 4544PF W 14 AUDIO OUT AUDIO OUT C67 21 INI Audio Amplifier Di ect Optional Bypass j AUDIO_SIG STEREO fo IF R150 10K R160 680K C78 ul T WAN AW 162 000K l AUDIO_SIG 149 000K MCP6L71R m 5555 N E Moore Court MELAT TICE Hillsboro Oregon 97124 www latticesemi com Title Audio In Audio Out ize Project 7 p 2 Control Board jale Tuesday June 26 2012 Bheet 12 of 14 5 3 z 1 sm LATTICE Figure 19 Audio In Audio Out SEMICONDUCTOR 5 4 E 2 1 Expand JTAG Chain to Prototype Header User s Guide MachXO2 JTAG Port MachXO2 Bank 3 us 2 4000 Control Development Ki 22 gt gt TDLHDR m MachXO2 Bank 1 PLECIPL11A PL16A 43 ED DATO 3 uSD DATO PLBD PL 1B PL16B lt 2 HESETo X02_AESETn VCC38 7 B14 LPDDR_A12 PLS
14. From a command prompt start Minicom minicom 5 The configuration menu appears Highlight Serial port setup and press Enter Serial port settings appear Press A Serial Device Specify the active serial device noted in Step 1 and press Enter Press E Bps Par Bits Specify 115200 None 8 and press Enter 3 4 5 6 Press F Hardware Flow Control Specify None and press Enter 7 Press Esc The configuration menu appears 8 Select Save setup as dfl Minicom saves the port setup as the new default 9 Select Exit The Minicom interface appears 10 From the evaluation board press the S1 push button GSR The Control SoC demo main menu appears Ordering Information China RoHS Environment Friendly Description Ordering Part Number Use Period EFUP MachXO2 4000HC Control Development Kit LCMXO2 4000HC C EVN fe Technical Support Assistance Hotline 1 800 LATTICE North America 1 503 268 8001 Outside North America e mail techsupport latticesemi com Internet www latticesemi com 2 4000 Control Development Kit zs LAT TICE User s Guide ME SEMICONDUCTOR Revision History Date Version Change Summary October 2012 01 0 Initial release November 2013 01 1 Removed LPDDR from features list added performance note 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi c
15. agp ____ 3 PM PLDCLK 47 Expand JTAG Chain to Prototype Header PRBCIPRIAQAPR14A LPDDR DQ7 R G PL5B PL7D PL10D PCLKC4_0 7 LED3 1 PRED PR1OB PR14B lt 12 m 3 LPDDR DQ6 PL5C PL9A PL13A USB_UART_TX 6 LPDDR DOS 4 PLSD PLSB PL13B _USB_UART HX S UsB_UART_AX 6 PR9A PR11A PR15A kia LPDDR 3 LPDDR_DQ5 uSD_CMD JTAG Header ls PR9B PR11B PR15B LPDDR_DQ4 PLBA PL1OA PL14A X uSD_CMD 712 32 uSD_CLK lt PROC PRI2AIPRIGA Hett TESDE DOS gt gt LPDDR Mi3 LPDDR DQi 3 Z PR9D PR12B PR16B LPDDR_DQ1 e Tuo ROO Mi2____LPDDR_DQ2 1 2K 2K 4K 2nd Fn Machxo2 PR10A PR13A PR18A 44 39 LPDDR_DQ2 PR10B PR13B PR18B M4 LFDDA DOO 3 LPDDR_DQO N13 LPDDR_AO TDI PR10C PR14A PR19A N14 T PDDR Ai gt gt LPDDR AO 7 d DIE LPDDR_AT BA LCMXO2 1 2K 2K AK MN132 VCCIO18 H14 VCCIO pj ru b ps 2 Bank 5 i K K AK ind Lebe tur pitur 8877 GE i ADC Delta Sigma Interface DNI B B2 ___ 5 SZ PL2B PL1B PL3B L_GPLLC_FB uSD DAT2 8 AUDIO IN R168 Di LCMXO2 1 2K 2K 4K MN132 x 2 PLOCIPLOA PL4A L_GPLLT IN 21 WM FB Delta Sigma AUDIO IN gt gt RW PL2D PL2B PL4B L GPLLC IN 3 5309413 5 lt pars 8 X02_ADG_INX ADC_IN_R165_
16. Board The MachXO2 4000HC Control Evaluation Board features the following on board components and circuits MachXO2 LCMXO2 4000HC csBGA132 PLD Power Manager II POWR1014A mixed signal PLD 4 Mbit SPI Flash memory microSD micro Secure Digital memory socket Current and voltage sensor circuits Voltage ramp circuits Electret microphone Audio amplifier and Delta Sigma ADC PWM analog output circuit Audio output channel Up to two DVI sources and one DVI output Up to two 7 1 LVDS sources and one 7 1 VDS output e g Camera Link Expansion header for JTAG SPI and PLD I Os LEDs and switches Standard USB cable for device programming RS 232 USB and JTAG USB interface RoHS compliant packaging and process AC adapter international plugs Pre loaded Reference Designs and Demo The kit includes the pre loaded Control SoC demo design that integrates several Lattice reference designs including the LatticeMico8 microcontroller master WISHBONE bus controller soft Delta Sigma ADC SPI master controller UART peripheral Embedded Block RAM and additional control functions USB connector Cable A mini B USB port provides a communication and debug port via a USB to RS 232 physical channel and programming interface to the MachXO2 JTAG port AC Adapter international plugs with 5V DC output QuickSTART Guide Provides information on connecting the MachXO2 4000HC Control Ev
17. C7 C12 C14 C17 C26 C37 C39 C50 C55 1 19 C71 C113 C114 C125 0 001uF SM C 0201 D C131 C132 C135 C137 C139 C2 C5 C6 C15 C18 C24 C25 C32 C34 C36 C38 2 23 C40 C41 C51 C52 C56 0_01uF SM C 0201 D C72 C91 C117 C124 C130 C136 C138 C3 C9 C13 C20 C21 C22 C43 C49 C60 C62 3 18 C111 C118 C120 C121 10uF SM C 0603 C1608Y5V0J106Z TDK D C122 C127 C129 C140 4 2 C4 C11 12pF SM C 0603 D C8 C10 C16 C19 C42 C44 C45 C46 C47 C57 C58 C59 C61 C63 C64 5 32 C69 C74 C81 C89 C99 0_1uF SM C 0603 D C105 C107 C109 C110 C112 C115 C116 C123 C128 C133 C134 C141 CAP CER 18PF 6 2 C23 C29 18pF 0402 C0402C180K3GACTU Kemet 25V COG 0402 D C27 C30 C31 C48 C82 7 10 C85 C104 C119 C126 0402 0402C104K4RACTU Kemet COD A D C145 Cap Cer 10uF 8 1 C28 10u cc0603 ECJ 1VB0J106M Panasonic 6 3V 2096 X5R D 0603 9 4 C33 C106 C142 C143 10uF SM C 0805 JMK212BJ106KD T TAIYO YUDEN D 10 2 C35 C83 1uF SM C 0805 D 11 2 C53 C65 22uF SM C 0805 LMK212BJ226MG T TAIYO YUDEN D 12 4 C54 C66 C70 C73 10uF SM C 0805 D 13 1 C67 10uF SM C 0603 D 14 1 C68 0 1uF SM C 0603 DNI C75 C76 C77 C79 C80 15 13 C84 C90 C92 C96 C97 0 1uF SM C 0201 D C98 C100 C103 16 1 C78 3300pF SM_C_0603 D C86 C87 C88 C93 C94 17 8 C95 C101 C102 O0 1uF SM C 0201 DNI 18 1 C108 0_01uF SM_C_0201 D Cap Cer 4 7uF 19 1 C144 4u7 0603 ECJ 1VB0J475K Panasonic 6 3V 1096 X5R D 0603 20
18. ET ites WEE E im 17 Eek uF D tu uF b tu SWO 1 SERTFG bos 1 2K 2K 4K 2nd Fn T TH DNI m swo WE R LCMXO2 1_2K 2K 4K MN132 LPDDR 3p3 sERTFG LCMXO2 1 2K 2K AK MN132 Interface between LVCMOS33 and LPDDR1 8V 12 Bus Pull up Resistors VCC38 LVCMOS33 Open Drain LVCMOS33 Voltage Devider 1 LPQDR_BA1 323 LPDDR 3p3 LPDDR 3 3 5 1 g 5 a 8 Q BOE i amp gt a vox 2 8 8 8 soL t amp LPDDR 1p8 a LPDDR 1 8 B LPDDR 1 8 SDA 2 BI 9 g LPDD 8 2 8 LPDDR_CKE 0 8 LPDDR_RASn E LPDDR ie rea x x x m 5555 N E Moore Court ALAT 7 IC E Hillsboro Oregon 97124 u U N LPDDR_CSn a latticesemi com 5 LPDDR Tite Q x w p 2 Banks 0 2 2 ze Project V O 8 2 Control Board U ate Tuesday June 26 2012 Bheet 14 of u 5 4 3 1 S s gt N u 5 ir Appendix B Bill of Materials LATTICE SEMICONDUCTOR Table 1 Bill of Materials 2 4000 Control Development Kit User s Guide 24 Manufacturer Item Quantity Reference Value PCB Footprint Part Number Manufacturer Description Populate C1
19. MUX 19 79 DVI Integrated ka Ee quos 2 DATA 80 pop 9222 c xn TMDS I DATA 8 R in 8 nosa Et TMDS 2 DATA2 N Cent ss 2 TDS ORTAZ P XLAVDD 2 82 aoo 53 AGND 37 TMDS_Data2 4_Shield amo QE16 4 2 parai d TMDS_Datat Gy 5 IMOS 2 OAA N 8 G in Gz 6 IDDC 87 eS DDC Clock DC CLK AGND 3 0020 7 cone amp AGND Analog_Vertical_Syne 2 TMDS_2 DATA 90 gov 48 TX OUTON 2 TX OUTO N 2 ups zoo d qi 8 PB 3 Sid B in z Txoutop OUT PP A acis 00 009 92 55 46 TX OUTIN 2 TX oui N 2 pis moune AGND TX OUTI P 2 DOPA x 2 Twos 2 cik P gall cs TROUTIP X Datat i a rear 5 9 NOS 2 ATAT P
20. R99 R102 R103 R107 R108 R111 R112 R131 R137 R138 R139 R140 R141 R142 R143 R144 R152 R153 R154 R157 R165 R166 R167 R170 R171 R174 R186 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R230 R231 R238 R247 R248 R250 R251 R252 R253 R254 R255 R256 R262 R263 R264 R265 SM_R_0402 DI 50 R22 R48 R101 R237 R243 R245 R246 10K SM R 0402 DNI 51 R27 R64 R114 R122 470 SM_R_0603 ERJ 3EKF4700V Panasonic ECG 52 R31 510 1 SM_R_0603 53 R54 R55 R65 R66 R84 R85 R88 R89 R205 4_7K SM_R_0603 54 R56 2k2 cr0402 TNPWO04022K20BEED Vishay Dale RES 2 20K OHM 1 16W 0 1 0402 55 R58 0 SM R 0805 56 59 1 SM_R_0805 57 R60 R219 220 SM_R_0603 58 R63 R68 SM_R_0603 59 60 R69 R187 R188 R74 R175 R176 R177 R178 R182 R183 R234 820 1K SM_R_0402 SM_R_0402 61 R79 100K SM_R_0603 62 R80 R86 68 SM_R_0402 63 R90 R91 4_7K SM_R_0402 o 25 LATTICE SEMICONDUCTOR 2 4000 Control Development Kit User s Guide Table 1 Bill of Materials Continued M
21. Ray DI PL3A PL3A PL6A PCLKT5_O ka lt x2 7 R53 Jumper 2way NI PL3B PL3B PL6B PCLKCS 0 10K Rist _ PLSOPLANPLTA El ins P VREF m DI 10K veo 14 LVDS COMP P A OUT LVDS_COMP_N vec PLANPLSA PLBA i AUDIO OUT 6 lt vec d 76 PL4B PL5B PL8B LEDI 3 2 LED pe VEG Rat 78 _1uF biur b_iuF VCCIO33 10K R180 Ne 7 veciosiveciosvecios H id 1 2K 2K 4K 2nd Fi 77 80 bw GND tur tur GND NI DNI PWM_FB_Delta_Sigma EA LCMXO2 1 2K 2K AK MN 132 GND GND GND GND 5555 N E Moore Court GND Socket 08050 132U6618A Mounting Holes LATTICE oregon 97124 N www latticesemi com 2 LCMXO2 1 2K 2K AK MN132 Title Q Q Banks 1 3 4 5 amp JTAG MLHOLEI MEHOLEI M HOLE Project IW_MNTO IW MNTO IW MNTO IW MNTO 2 Control Board U ate Tuesday June 26 2012 Bheet 13 __ 5 3 3 z 1 S 5 gt LATTICE SEMICONDUCTOR User s Guide 2 4000 Control Development Ki 23
22. a lower case L character Pressing will sample the voltage in pin 2 of header J9 and log the data in the SPI Flash device on the board The WRITE page pointer will increment when F is pressed The initial value of the page pointer after power up or after a reset is 0 d This option will read the data from SPI Flash device and display it on the HyperTerminal window The READ page pointer will increment when d is pressed The initial value of the page pointer after power up or after a reset is 0 c This option will clear reset the WRITE and READ page pointers e This selection will perform a bulk erase of the Flash memory in the SPI Flash device Setting up the Board Drivers and Firmware Before you begin you will need to obtain the necessary hardware drivers for Windows from the Lattice web site 1 Browse to the www latticesemi com MachXO2 control kit and locate the hardware device drivers for the USB interface oma MachXO2 4000HC Control Development Kit LATTICE cd SEMICONDUCTOR User s Guide 2 Download the ZIP file to your system and unzip it to a location on your PC Linux Support The USB interface drivers for the evaluation board are included in Linux kernel 2 4 20 or greater including distribu tions compatible with Lattice Diamond design software Red Hat Enterprise v 3 v 4 or Novell SUSE Enterprise v 10 The Control SoC Demo is preprogrammed into the MachXO2 4000HC Control Evaluation
23. another Windows ver sion 1 From the Start menu select Control Panel System The System Properties dialog appears 2 Select the Hardware tab and click Device Manager The Device Manager dialog appears Figure 5 Device Manager COM Port Device Manager BEE File Action View g a Bl 125532 Batteries Bluetooth Devices Computer Disk drives Display adapters 42 DVD CD ROM drives ig Human Interface Devices 43 IDE controllers amp IEEE 1394 Bus host controllers ue Keyboards Mice and other pointing devices e Modems Monitors BB Network adapters 4 Other devices Broadcom USH PCI Serial Port Ports LPT E Bluetooth Communications Port COM4 7 USB Serial Port COM31 Ge SCSI and RAID controllers Secure Digital host controllers SQ Smart card readers Sound video and game controllers System devices 4 Universal Serial Bus controllers WD Drive Management devices 3 Expand the Ports COM amp LPT entry and note the COM port number for the USB Serial Port 4 From the Start menu select Programs Accessories Communications HyperTerminal The HyperTer minal application and a Connection Description dialog appear oma 2 4000 Control Development Kit LATTICE User s Guide Figure 6 New Connection COM Port Connection Description New Connection
24. m L AGBUS1 zm FT EECS 63 ACBUS7 z 51 EEDATA BDBUS1 f EE EE d osco ms DI AW Ww USB UART RX 14 R82 g DI BCBUSO BCBUS2 TEST BCBUSS BCBUSA BCBUSS FTDI High Speed USB Bceus5 BCBUS7 Ras 0 Ra02 0 R241 10k 10k 10k uar vcc cs NU eng cg D 0 1uF 1 2 1 991055508 OF 5 E ka C30 Sue cc c amp 15 HILATTICE 22 25 mI www latticesemi com Configuration USB Port ize Project 9 2 Control Board id oat Tuesday June 28 2012 e a m 5 E I T LAT SEMICONDUCTOR Figure 13 Configuration USB Port 2 4000 Control Development Ki sm LAT SEMICONDUCTOR User s Guide Figure 14 Software LED Crystal Header XO2 LEDs Reset Push Button Switch vocs3 RN2 4 470 DI 14 XO2_RESETn lt LEDLED LED LED 04 0 02 DI ipi DI XO2 LEDO xoa LEDO LEDT XOZ LED2 99 02 2 14 Xo2 LEDs 22 02 LEDS 2x20 Header VcCi2 VCC33 J4 1 2 XO2 IN Sip
25. the installation was successful Programming the PLDs The three pin header with reference designator J6 is used to select between the JTAG port of the 2 or POWR1014A device Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4 This exam ple shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been selected oma 2 4000 Control Development Kit SEMICONDUCTOR Figure 4 J6 Header Used for Selecting the JTAG Port of the PLDs Using Diamond Programmer software included with the Diamond installation users can scan and perform JTAG operations including programming with the MachXO2 and POWR1014A devices Setting Up Windows HyperTerminal You will use a terminal emulator program to communicate with the evaluation board The following instructions describe the Windows HyperTerminal program which is found on most Windows PCs You may use another termi nal program if desired although setup will be different Windows 7 does not include HyperTerminal Tera Term has been verified to work with Windows 7 For Linux Minicom is a good alternative Note This step uses the procedure for Windows XP users Steps may vary slightly if using
26. 00 Control Development Ki LAT SEMICONDUCTOR Figure 18 Video Output Video Output DVI or MDR for direct 7 1LVDS Resistor De MUX 14 K 14 Xo2 ouo P 14 ort 14 Xo2 ourt P 14 OUT2 14 P 14 N 114 P 14 CLKOUT 14 XO2_CLKOUT_P Ra Sa Ba dzo Brows Cm UTE T aes MOR_AX_CLKOUT_N MDR RXCCLKOUT P MDR Connector FXCINS MDR RXCINS P pri eium Z mane ask Camera Link TX Camera 10226 TATOPEND 210VE Supporting Circuits RXOUT ASO LVDS Translator TMDS DVI Decoder TMDS DVI Connector CCS 5 DVI Integrated __ sou s a FX_INO_P 109 FXOUT26 FXOUTO 37 DATARS 5 DATA2 hi 5 RXOUT25 BXOU
27. A PLIZA PL17A PCLKTS 0 HSI PM MOLK 3 PM MCLK x Y PR2A PRIA PR2A R_GPLLT_FB ors LPDDR X LPDDR A12 8 PLSB PL12B PL17B PCLKC3 0 5 DATI 1 PR2B PR1B PR2B R GPLLC FB LPDDR A11 POWER C14 LPDDR A9 PL10B PL13B PL19B 2 FM OUTIL 22 2 PR2C PR2A PR3A R_GPLLT_IN 512 LPDDR A9 Mi OUTI2 TDO D PR2D PR2B PR3B R GPLLC LPDDR A8 8 PL10C PL14A PL20A M2 py OUT 0912 3 TDI R157 DNI PRSA PRSA PRSA HER LEDDR AT d TOI 2 2 DI XO2 PRODPROB PRSB En LPDDR A6 8 H E13 LPDDR A5 5 ovecioss EEE TMS 67 4 PR4A PR4A PR6A A LPDDR A5 1 2K 2K 4K 2nd Fn TRST 16K 67 14 PR4B PR4B PREB LPDDR A4 8 5 TMS PRACIPRSAPRBA 19 _LPDDR_AS gt Y ipppR e n Eye ee ie BE LPDDR_A2 LEDDROA2 81 LCMXO2 1 2K 2K 4K MN132 cupi PR5A PR6A PR9A 00 eia Ga LPDDR CK 8 HS Xo XO2 TMS XO2 TDI PR5B PR6B PR9B DQSN LPDDR_CKn MachXO2 Bank 4 XO2 TCK noe 613 LPDDR A10 UAE P Dr LALA a rk D Hi2 LPDDR A REA NOT Populated RIP X02 TDO 5 10K FZ PLAGIPLOAPLOA EG XOS TED mum m PIN J12 LPDDR_LDQS PL4D PL6B PL9B LED2 gt gt XO2 TDO PIN 14 PRBA PRSA PR13A DQS LPDDR LDOS 8 PR8B PROB PR13B DOSN 214 X02 GPIO 10 ail PLSAIPLTC PLIOC PCLKT4_0
28. Analog Green 29 ons 12 032 28 41 2 MDR TX CLKOUT N 2896 DNI Analog Boo 45 OGND cna NDR DCCEKOUT 2602 DNI Analog Horizontal sync 4 78 OGND OGND Grund 1 Ge Analog Grund 2 2 ST sop WU o i a W MDR Connector Supporting Circuits Di inner shield o DVD 2 470 inner shield2 MOR AW W NDR TX QUTO P2 Ry DNI Cris NDR DCOUTIN 2 LED will be ON NDR DX OUTI P2 chan ARRAS on MOR TX N 2 active LED Green NDR DCOUT2 2 ctive AE NDR IX CLKOUT 2 scot high m NDR TX CLKOUT P gt Rio D PON 2 NDR DECOUTS 2 P_O0tuF atts Di __ 2 pi J 3 Di PWRDWN 2 1 CDT 2 B85138LT1 1 2 B120 D ooe poor r bi J Rite Di STAGN 2 TOP Package View pr RR NS 2 mra strz 3 Drain LE otur 2 bi mex ns sre 2 5 1 2 Source 10226 1A1OPE ND 10226 1210VE Camera Link RX co Frame Grabber LATTICE more Court 593 7 Hillsboro Oregon 97124 www latticesemi com lis Video Input 2 ize Project 9 2 Control Board 9 Tuesday June 26 2012 Ehet 10 of 14 5 4 I 3 I 2 T LAT SEMICONDUCTOR Figure 17 Video Input 2 User s Guide 2 40
29. Board however over time it is likely that your board will be modified To download the demo source files and reprogram the MachXO2 4000HC Control Evaluation Board 1 Download demo application source code from www latticesemi com mxo2 control kit 2 Use MDemo MachXO2 Control SoCprojecticontrol demo jed to restore the MachXO2 4000HC Control SoC demo design 3 Use Demo PM Control BMWrojectibm demo jed to restore the POWR1014A Board Management demo design Connecting to the MachXO2 4000HC Control Evaluation Board 1 Plug the AC DC adopter to an outlet 2 Power the board by inserting the AC DC adopter into the power jack with reference designator J11 Once the connection is made a red LED with reference designator D12 will illuminate 3 Connect the evaluation board to your PC using the USB cable provided The USB connector in the board has reference designator J5 4 f you are prompted Windows may connect to Windows Update select No not this time from available options and click Next to proceed with the installation 5 Choose the Install from specific location Advanced option and click Next 6 Select Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created earlier Select the CDM 2 04 06 WHQL Certified folder and click OK 7 Click Next A screen will display as Windows copies the required driver files Windows will display a message indicating that
30. CK BUMPON HEMI SPHERE 44X 20 BLACK 38 Q1 Q3 Q6 Q8 BSS138LT1 SOT_23 BSS138LT3G ON Semi 39 Q2 Q5 2N7002E SM_SOT23 2N7002ET1G ON_Semi 40 Q4 2N2369A 2N2369A_SOT23 MMBT2369A Fairchild 41 Q7 ZDT758 SM 8 DUAL PNP ZDT758 Diodes Zetex 42 RN1 RN4 RN2 4 470 RN2 4 470 0603 TC164 JR 07470RL Yageo 43 RN2 RN1 8 10K RN1 8 10K 0603 MNR18E0APJ103 Rohm Semi 44 u a p a a pl a RN3 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi o ojo o o o o 45 45 R1 R7 R18 R19 R20 R21 R32 R41 R43 R44 R45 R46 R47 R53 R73 R81 R94 R97 R115 R116 R117 R118 R119 R120 R121 R123 R124 R125 R126 R127 R128 R132 R151 R158 R159 R163 R164 R180 R181 R200 R233 R236 R239 R242 R244 10K SM_R_0402 DI 46 R2 1M SM R 0603 DI 47 53 R3 R5 R8 R10 R11 R15 R16 R24 R25 R26 R28 R29 R30 R33 R35 R40 R42 R52 R57 R92 R96 R98 R100 R104 R105 R106 R109 R110 R113 R155 R156 R161 R168 R169 R172 R173 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R257 R258 R259 R260 R261 SM_R_0402 DNI 48 R4 R67 R195 R196 R232 1K SM_R_0603 DI 49 80 R6 R9 R12 R13 R14 R17 R23 R34 R36 R37 R38 R39 R49 R50 R51 R61 R62 R70 R71 R75 R76 R78 R82 R83 R87 R93 R95
31. PI Flash Log ADC Result Display RDC Result From Flash Memory Clear Page Pointers of Flash Memory Erase Flash Memory Thank you for using the MachM02 Control Evaluation Board Connected 0 00 20 ANSIW 115200 8 N 1 Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the Terminal emulator menu The available options are m This option will re display the main menu anytime during the demonstration a This option will sample the voltage in the pin 2 of header 9 By default the node is biased at 1 65V which is half of the VCCIO 3 30V The voltage will be displayed in the HyperTerminal window The ADC input voltage should be limited to the range 0 to 3 0V to avoid device damage s This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal The resulting ID is hexadecimal 0x44 which corresponds to AT25DF041A device This option samples and displays the elapsed time since the reset was de asserted r This option samples the DIP switches reference designator SW1 on the board and displays the data in the HyperTerminal Users can change the DIP switches on the board and press r to display the new value 0 9 These are BCD numerical values that can be typed on the keyboard The value will be received by LatticeMico8 which will update the LEDs DO D3 on the board T This is
32. PIO 2 XO2 CLKIN 1 for cen XO2 CLKINCT NP6 PB9A PB11A PB13A PCLKT2_0 PT11B4PT13BYPT14BA 95 XO2 OUT2 11 8 XO2 CLKIN PB9B PB11B PB13B PCLKC2 0 2 N Q2 OKIN 2 N RRB DNL 02 10 3 PM INT s PTHC PTIGCIPTISC TCK 88 2 67 13 GPIO 3 44101 1 SERTC2 SERTC2 M5 PB9C PBJA PB10A PT11D PT16D PT15D TMS XO2 TMS 6 7 13 m Xo2GPl03 XO2 GPIO 3 SERTC2 IND RZE5 DI PB9D PB9B PB10B AT XO2 OUT XO2 IN2 2 P XO2 10 4 02 TANT TIGAR POUKTO T XO UT 09 02 OUT 10 IN2 2 P ______ 0210 5 Ng PB11A PB16A PB20A PCLKT2 1 PTI2BAPTI7B PTI8B PCLKCO 1 2 2 1255 OUTI N 11 XO2 GPIO 4 14001 NL PBI1B PB16B PB20B PCLKC2 1 sat 4402 8104 x02 10 0 7 PT12C PT18C PT20C SCL PCLKTO 0 SD g SCL 47 0101 Ny PB11C PB12A PB15A PT12D PT18D PT20D SDA PCLKCO 0 SDA 47 10 2 O RIZON 202 101 NI PBiD PBIT2B PBI5B ch SG Gdroh PTISANPTISAWPT21A a9 Xos OUTO N RQ 7 X02_GPIO_5 X02 GPIO 5 INO 1 TONN we Na FE PB15A PB18A PB21A PT15B PT19BYPT21BA xo oun i QQ XO2_OUTON 11 XO2_INO_1_N PB15B PB18B PB21B 10 2 AP ARETON ____ TP ee PTISC PT2OC PT23C JTAGENB
33. TIT 38 Estes o 31 TMDS DATA2 P DATAZ P 2 RSE Udan Routa 3 ROUTE e bara e Vim pal Twos DATAE 5 Pg SOUT EAN 8 spra ROTH THO Dana RxOUT22 55 RXOUT21 RXOUT5 42 DATAS 4 RKINZN RXOUT21 54 RXOUT20 RXOUT27 434 DATAI7 28 TMDS_DATA1_P R245 5 05 Dala4 RROUTZO 6 RXOUTIS RXOUTS 443 DATATE 1 per TMDS_DATAT_N THOS _Datads ROUTE 48 DATATS eux 000 00 DOUTE 85 OATS Kone paral T En Eun 5 08 Twos DATO P RECEN 0 oaran 2 ROR pet TROS Barat MEM m AGE bel te Ma NS LVCC 13 RKOUTI1 41 FXOUT10_ FXOUT6 543 DATAS 22 IMDS CLK P LVDSVCC RXOUTI0 ay RXOUTS BXOUTA 553 DATAT Out 2609 TMDS CLKCN TMDS_DATA1 9 RXOUTS RXOUTB RXOUTI3 583 DATAS Ut TXCN TMDS_DATA1 10 TMDS Datat oso 8 SIUS ETE Tos Denn Rmo ar 504 MI OUR HUR Er outs PATA ns muc 95 E rao 2 sor gia pant 3 peus En un pow Rep meum moxo E pe po
34. ai tie 6 XO2 GPIO T1 R GFIO 6 8 gt XO2_GPIO_11 woe PIG XO2 GPIO 1 10 HVOUTI KOS 2 XO2 GPIO 2 12 I OS GPIO S XO2 GPIO 3 14 HVOUT2 HVOUT2 te NOS BPO XO2 GPIO 4 16 PM OUTIS POWA XO2 GPIO 5 XO 5 18 PLDCLK PM_PLDCLK 4 14 X02 GPlO 6 Xo GPO S __18 PM MCLK PM_MCLK 4 141 OZ GPIO XO2 GPIO 7 21 22 z bo Hor 23 24 SGL 25 R SDA fa 61314 TMS_HDR zn EJ 02 GPIO 10 2 GPIO 10 61314 E 20 XO2_GPIO_9 X02_GPIO_9 S y 31 32 XO2 GPIO 8 NOS PIDE 33 34 XO2 SPI CIK Sas 35 36 XOZ SPILIN XO2 SPI 8 1 XO2 8 14 y VMON10 37 38 XO2_SPI OUT Mesure 1 4 CON40A DNI 2x20x100mil 1 X02 Global Reset VCC33 R128 10K 14 14 24 MHz Crystal 4 DIP Switch VCC33 9 2 R127 R126 gt R125 gt R124 10K 2 10K 2 10K 10K DI DI DI DI SWi CT1934M5 ND swo 1 8 SW 6 5wi 2 T swe SW2 3 6 mem 4 4 5 SWDIP 4 DI HCM49 24 000MABJ UT XU xi CTS CB3LV 3C 25MHz x n 102 R4 1 Te 2 qu T 12pF L 0 m 0 18pF 12 Ground Plane 6pF 25 MHz OSC Ri x x 1 vec 4 2 3 GND OUTPUT 1
35. aluation Board installing Windows hardware drivers and running the Control SoC demo ATTICE MachXO2 4000HC Control Development Kit HH SEMICONDUCTOR User s Guide Figure 1 shows the top side of the MachXO2 4000HC Control Evaluation Board with comments on the specific fea tures that are designed in the board Figure 1 MachXO2 4000HC Control Evaluation Board Top Side DVI 7 1 LVDS Video Output Video Output 5V Power Indicator MachX02 DIP Switches Electret Microphone GSR Push button 2x20 GPIO Header MachX02 4000HC Speaker Headphone Jack AC DC Adapter Jack ADC Input J9 Pin 2 LPDDR Memory POWR1014A JTAG Device Select J6 MachX02 Position Shown MachX02 LED Field microSD Socket 7 1 LVDS Video Source Camera Link TT iln Us DVI Video Source USB 2 0 Interface Socket Notes Video Source 1 is available in both DVI and 7 1 LVDS interfaces Video Source 2 is not populated An LPDDR memory device is installed on the PCB but performance is limited to 20MHz max Lattice Semiconductor Devices MachXO2 This board features a 3 3V MachXO2 PLD packaged in a 132 ball csBGA package This package allows density migration to devices from 256 to 4340 LUTs A complete description of this device can be found in the MachXO2 Family Handbook Power Manager II This board also features a Power Manager II mixed signal PLD The POWR1014A device serves as a general purpose power suppl
36. anufacturer Item Quantity Reference Value PCB Footprint Part Number Manufacturer Description Populate R129 R130 R133 R134 s oc R206 65 1 R145 330 SM_R_0603 D 66 1 8147 2_2K SM_R_0603 D 67 2 148 R235 2 SM_R_0805 D 68 2 149 R162 1000K SM R 0603 D 69 1 150 10K SM R 0603 D 70 1 8160 680K SM R 0603 D 7 2 179 R198 200 SM_R_0603 D 72 4 R189 R190 Ri92 R193 3_92K SM_R_0603 D 73 2 197 R204 2K SM_R_0603 D 74 1 R199 12k cr0402 RCO402FR 0712KL Yageo S ami 75 4 R202 R203 R241 R249 10 cr0402 RCO402FR 0710KL Yageo o MEME 76 1 R240 2 2K SM R 0402 RCO402FR 072K2L Yageo POS D SWITCH DIP 7 1 swi SWDIP_4 SMD_8check 3 5435640 5 Tyco 4POS SEALED D GOLD SWITCH SIDE 78 1 swe SW DIP_2 SP_75 195 2MST CTS ACTUATED 2 D SEC SWITCH LT 6MM 79 1 Global Reset SMT_SW EVQ Q2K03W Panasonic 180GFH 31MM D 80 1 microSD Socket SM SD 460DE08C3 MULTICOMP D 81 1 gt TFP401A HTQFP_100 TFP401APZPG4 D 82 1 TFP410 HTQFP 64 TFP410PAP D 83 1 wea CSBGA132 LCMX02 4000HC 6MG132 Lattice Semi D 84 1 us STG3693QTR QFN STG3693QTR STMicroelectronics D 85 1 ue MT46H16M16LFBF SM 60VFBGA MT46H16M16LFBF Micron D 86 1 lu ispPAC POWR1014A _ TQFP 48 ispPAC POWR1014A 01TNA8l Lattice D 87 1 us CMA 4544PF W 2 Solder Pins TH CMA 4544PF W CUI Inc D 88 1 Jug TFP401A 100 TFP401APZPG4 DNI 89 1 DS90CR288A TSSOP_56 DS90CR288AMTD NOPB National Semi D 90 1
37. boro Oregon 97124 www latticesemi com Title Power ispPAC POWR1014A ize Project 7 2 Control Board 26 2012 Bheet 4 14 1 13 User s Guide 2 Power Rails Current Sense 8 Core Current VCC33 2 _ 9 9 9 C44 DI C142 R219 10uF DNI oi 220 DI ZDT758 VCC33 Ow 34 PM_OUT8 gt gt 5 DI ol R59 R201 1 100 U16B U16A DI DI bi ICCN ADB604ARZ 3 ADB604ARZ gt gt ICC_Sense 14 1 108 1011 142 C143 to limit Vecio ramp rates to data sheet spec MachXO2 ICCIO33 Current 2 4000 Control Development Ki VCC33 VCCIO38 1 1 pal OtuF DI 4 c C105 PII II ouf DI DI R191 R194 100 E 100 3 U16D DI AD8604ARZ DI ICCIO33 pap 12 AD8604ARZ 8 3 Sense 4 1 18 Sense 4 14 DI 100 R184 MachXO2 ICCIO18 Current R193 3 92K VCC18 VCCIO18 le m un 5 roi o ICCIO18 P ICCIO18 1014 1015 5555 Moore Court U k LAT TICE zi Oregon 97124 U 5 T T www latticese
38. e Project lev 5 2 Control Board 9 ite Tuesday June 26 2012 Bheet 2 of 14 1 User s Guide AC DC Jack 5V Linear VREG Step Down 5V to 3 3V Rail 5 gt TAB 3 R122 VCC5 1019 Uti 3 2 OUT c54 GND 10uF DI 1 NCP1117ST33 C53 22uF DI 1020 470 a 4 J11 PWR_JACK DI 2 4000 Control Development Ki 12 Linear VREG Step Down 3 3V to 1 2V Rail Linear VREG Step Donn 3 3V Rail T VCC CORE VCC33 visum 9 LP3879MR 12 R20 m DI 10K iia Ene 1 5 2 BYPASS OUTPUT 6 3 GND SAGA 2 I GND s g 2s 1 Q a C106 Qe 2 10uF 10uF BSS138LT1 145 e DI DI gt W s 9 e U 9 HLATTICE tv gt 5 9 www latticesemi com Title Q Power VCC33 VCC18 VCC12 2 Project v d 2 Control Board jale Tuesday June 26 2012 Bheet 3 14 U o 5 4 3 2 1 lt gt gt a 5 S lt u na 5 gt Se User s Guide 2 4000 Control Development Ki LAT SEMICONDUCTOR Figure 11 Power ispPAC POWR1014A
39. e Memory LPDDR SD SPI Project V 2 Control Board ate Tuesday June 26 2012 Bheet 8 14 Figure 15 Memory LPDDR SD SPI sm LATTICE SEMICONDUCTOR User s Guide 2 4000 Control Development Ki Video Input Source 1 DVI or MDR for direct 7 1LVDS DVI Connector DVI TMDS Decoder LVDS Translator Resistor MUX 79 a __ DVI Integrated Geos 36 Mi IMOS 1 922 seni 1 THDS I DATAZ BP 5 921 3 x quos patan 1 MOS 1 N Oeo r9 m IMDS Dasz 2 MOS DATAE 821 go aei 3 Tae Aan Fag TMDS_Data2 4_Shield 801 avoo 4 qos 1 d TMDS_Datat ROP c i 0023 TOS 5 IMDS TOATA 86 Goin 73 DDC Clock DC AGND 3 udo Bua Gut rm i RR Analog Vertical Sync TMDS 1 DATAO 90 48 TX_OUTO_N_1 L1 DATAO b N IMSL DATO N 91 ROP B in isa Tours XOT PL ES 22 a S84 Tourn PAS N
40. er management is handled in two phases by the MachXO2 4000HC Control Evaluation Board system 1 Power On After power is supplied to the board and the 3 3V rail is stable the POWR1014A sequences four supply rails Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETS using the high voltage HVOUT outputs and two demonstrate power rail enable of VCC_CORE and of the MachXO2 using digital outputs Next the POWR1014A asserts the MachXO2 reset Finally the POWR1014A enters a supply monitoring state 2 Post Power On During the second phase of power management the board s condition is monitored Power supply rail voltage and current is monitored by the POWR1014A If any supply rail fails the POWR1014A asserts a reset for the 2 MachXO2 Function After the reset is de asserted LatticeMico8 initializes the peripherals embedded in the MachXO2 device and uploads the user menu onto the Terminal emulator window of a PC ATTICE 2 4000 Control Development Kit SEMICONDUCTOR User s Guide Figure 3 HyperTerminal User Menu com31 HyperTerminal File Edit View Call Transfer Help ose 68 DB Welcome to the Machk02 4000 Control Evaluation Board Control SoC Demo Rev 1 1 September 2012 Re display Main Menu Read ADC Digital Data Read External SPI Flash IDCode Up time counter I 0 Control Read Dip Switches 0 9 I 0 Control Write to LED Data Logging to S
41. mi com 3 Title Q Power Current Sense 2 Project V 2 Control Board jale Tuesday June 26 2012 Bheet 5 of 14 U o 5 2 1 lt z N u an 5 5 n H gt USB Port CPLD Configuration amp USB lt gt UART Communication User s Guide RES 2 RGB A7K D o Selected 0033 Pin 3 X02 is Selected RES AX AX 1 Di Di E 3 gt Jumper 2way ol 2 1 2 000hm SOMA zi Soe mig a ur 04 37 6 lllo SB EL pe mus vooss 0 182 gt gt 7 1344 mro 0 01 PM TDI W gt gt 9 net 2 0 L Be pl MDO 9 2 13 ADI 5 gt puts qq XOLTMS gt TMS 5 8 ds VCORE VCORE The USB interface draws no power from the USB bus It is self powered vccio 88 98 SS VCORE Fa 5 USB MINI DI ADBUS2 a eee ae A tg Ta om ADBUSG AM DP ADBUS7 2 4000 Control Development Ki ACBUSO
42. om legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice User s Guide 2 4000 Control Development Ki sa LAT SEMICONDUCTOR Appendix A Schematic Figure 9 Architecture MachXO2 Control Board Architecture SPI Page 8 AMbit E T S High Voltage Drivers Voltage Monitor Page 7 Page 4 Power Manager II ispPAC POWR1014A DVI Conn 7 1LVDS Conn Page 11 7 1LVDS to DVI Page 12 Conversion Audio IN Audio OUT ADC Page 14 Page 8 2 SD Flash DAC Page 12 7 1LVDS TX ADC DAC Page 8 LPDDR 128Mb d 4 GPIO H Page 7 RESET SW amp LEDs 7 1LVDS RX Page 13 14 Page 7 a 3 Crystal SW amp LEDs Board Power Managment Page 4 Page 3 5 DVI to 7 1LVDS DVI to 7 1LVDS USB PORT Conversion Conversion UART amp TT 5555 N E Moore Court JTAG Chain Page 9 Page 10 LA ICE Hillsboro Oregon 97124 Ere a www latticesemi com 7 1LVDS Conn DVI Conn DVI Conn 7 1LVDS Conn Architectur
43. s 041 D2 D3 04 07 08 SM_D_0603 LTST C190CKT LITE ON D 21 2 D5 D6 LED_Green SM_D_0603 LTST C190KGKT LITE ON D 22 1 D11 LED Green SM D 0603 LTST C190KGKT LITE ON DNI 23 1 012 LED SM_D_0603 LTST C190CKT LITE ON D 102 103 104 105 107 108 109 1010 1011 1012 24 20 1013 1014 1015 1016 T POINT TP DNI 1017 1018 1019 1020 1021 1022 CONN RECEPT 25 2 J1 J8 10226 1A10PE ND 10226 1A10PE ND 10226 1A10PE 3M 26POS R A 050 D SMD CONN RECEPT 26 1 J13 10226 1A10PE ND 10226 1A10PE ND 10226 1A10PE 3M 26POS R A 050 DNI SMD 27 2 J2 J3 DVI I DVI I 74320 1004 Molex D 28 1 J4 CON40A 2x20x100mil TSW 120 07 T D Samtec D 29 1 J5 USB MINI B TYPE B UX60 MB 5ST Hirose D 30 1 J6 Jumper 2way JP 2WY TSW 103 07 G S Samtec Inc D 31 1 J7 XO2 JTAG HD XO2 JTAG HD DNI 32 1 J9 Jumper 2way JP 2WY TSW 103 07 G S Samtec Inc DNI 33 1 J10 DVI I DVI I 74320 1004 Molex DNI 34 1 J11 PWR JACK PWR CON RAPC712 Switchcraft DI LATTICE SEMICONDUCTOR 2 4000 Control Development Kit User s Guide Table 1 Bill of Materials Continued Item Quantity Reference Value PCB Footprint Manufacturer Part Number Manufacturer Description Populate 35 1 J12 PHONEJACK STEREO SM MJ1 3510 SMT CUI D 36 L3 6000hm 500mA 0603 BLM18AG601SN1D Murata Ferrite Bead 600ohm 100MH z 500mA 0603 D 37 MH1 MH2 MH13 MH16 M_HOLE1 IW_MNTO SJ 5003 BLA
44. y monitor reset generator sequence controller and high voltage FET drivers More information about Power Manager II devices can be found on the Lattice web site at www latticesemi com products powermanager Software Requirements You should install Lattice Diamond design software version 2 0 or higher before you begin developing designs for the evaluation board m 2 4000 Control Development Kit SEMICONDUCTOR Control SoC Demonstration Design The Control System on Chip SoC demonstration illustrates the use of the LatticeMico8 microcontroller peripher als and firmware integrated to provide system control features such as power supply sequencing voltage monitor ing data logging to nonvolatile memory I O control embedded block RAM utilization UART communication and PLL status monitoring The Power Manager II device sequences the power up of voltage rails on the board and performs reset distribu tion atticeMico8 executable program initializes the peripherals that are embedded in the SoC design During initial ization LatticeMico8 uploads the user menu on a Terminal emulator e g HyperTerminal Tera Term of a PC Users interact with LatticeMico8 and the board through the Terminal emulator of a PC Figure 2 Control SoC Demo Block Diagram MachXO2 Control Evaluation Board MachX0O2 1200 WISHBONE Bus Analog SPI Signal Flash Pow

EB78 - MachXO2-4000HC Control Development Kit User's Guide

Contents

Download Pdf Manuals

Related Search

Related Contents