UG-2864ASYCG01 UG-2864ASOCG01 Evaluation Kit User Guide
Contents
1. Read High Parameter read Read Low Parameter read IPWLRGE lCYRGE Read cycle time Data read Read High Data read k ia Read Low Data read maga Data setup time Data hold time Data output access time CL toooes Data output disable time Table 3 68 Series MPU parallel Interface Write Timing Characteristics ISEB ATH 4 3 SPI Interface SERIAL INTERFACE CHARACTERISTICS SCLK DO in t V ngu Figure 4 Serial peripheral interface Timing Diagram VDD 2 BV a 25 C o serial clock cycle High pulse width Low pulse width 055 Data setup time Data hold time SID 01 Chip select setup time Chip select hold time select nen pulse width sso aaa te Table 4 Serial peripheral interface Timing Characteristics IRE AR 5 EVK use introduction Figure 5 EVK PCB and OLED UG 2864ASYCG01 is COG type module please refer to Fig5 Fig6 User can use leading wire to connect EVK with customer s system The example shows as Fig7 Figure 6 The combination of the module and EVK 10 Note 1 Note 2 Note 3 Note 4 IRE AR Fig 7 EVK with test platform It is OLED high voltage supply lt is logic voltage supply Those are leading wire connect to control board Those are data 00 07 Those are leading wire connect to control board Those are control pin DC CS RD WR RES 112. ISEB ATH BRS UG 2864ASYCG01 UG 2864ASOCG01 Evaluation Kit User Guide Writer James Wang Email james_wang univision com tw Version Preliminary ISEB ATH Contents 1 REVISION HISTORY case tite cep since tcc bus Sloan 3 2 ZU T E 4 8 ul sljejkol iil4 A 5 4 TIMMING CHARACTERISTICS nenanannnnnanannnnannnnnnannnnannn ann nn annan annan na 6 4 1 80 Series MPU parallel Interface 6 4 2 6800 Series MPU parallel Interface eese seres 8 4 3 OP Me ce ee ea ee EE 9 9 EVK USE INLOJUCHON NER 10 6 Power down and Power up 12 D How itolsessSDI3S05modHUlO s un 13 SC OW ee een 14 7 2 RD recommend Initial Code for 80 Interface 14 7 2 1 Sub Function for 80 Interface eese eese eee een 14 ISEB ATH BRS 1 REVISION HISTORY Univision 2 EVK Schematic ISEB ATH 3 Symbol define VCC Power supply for panel driving voltage VSS This is ground pin VDD Power supply for core logic operation VDDIO Power supply for interface logic level BSO BS2
3. ISEB ATH 6 Power down and Power up Sequence To protect OLED panel and extend the panel lifetime the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Power up Vpp Send Display off command Display on Driver IC Initial Setting Clear Screen Power up Vppu Delay 100ms when Vpp is stable Vpp pur ll s Vss Ground 7 Send Display on command Power down Sequence Display off _ Vec off Send Display off command 2 Power down Vppu 3 Delay 100ms when 1s reach and panel is completely Vpp discharges 4 Power down Vpp Neg Grune 12 IRE AR 7 How to use SSD1305 module 7 1 Initial Step Flow Reset Driver IC RES 0 Delay 10ms RES 1 Driver IC Initial Code Suggest all register set again Display on Clear RAM Start Display ISEB ATH 7 2 RD recommends Initial Code void initial write_command 0xae display on write_command 0x00 set low column address write_command 0x10 set high column address write_command 0x40 display start set write_command 0x2e stop horzontal scroll write_command 0xb0 page address write_command 0x81 set contrast control register write_command 0x7f write_command 0xa1 set segment
4. bus interface selection pin BSO pulled LOW in internal CS This pin is chip select input active LOW RES This pin is reset signal input active LOW D C This is DATA COMMAND control pin When it is Pulled HIGH the data at D 0 7 is treated as data When it is pulled LOW the data at D 0 7 will be transferred to the command register In I2C mode this pin acts as SAO for slave address select R W This is read write control input pin connecting to the MCU interface When interface to a 6800 series microprocessor Read mode will be carried out when this pin is pulled HIGH and write mode when low When interface to an 8080 microprocessor this pin when be the data Write input When serial interface is selected this pin must be connected to Vss E RD When interface to a 6800 series microprocessor this pin will be used as the Enable E signal When interface to an 8080 microprocessor this pin receives the Read RD signal 00 07 These are 8 bit bi directional data bus to be connected to the microprocessor s data bus When serial interface mode is selected DO SCLK will be the serial clock input D1 SDIN will be the serial data input D2 should be left opened When I2C mode is selected D1 SDAin AND D2 SDAout should be tied together DO SCL is the I2Cclock input IREF This is segment output current reference pin VCOMH This pin for COM signal deselected level voltage ISEB ATH BRS 4 TIMMING CHARAC
5. re map write_command 0xa4 normal display mode write_command 0xa6 set normal inverse display write_command 0xa8 set multiplex ratio write_command 0x3f write_command 0xd3 set display offset write_command 0x00 write command 0xad set dc dc on off write_command 0x8e write command 0xc8 set com output scan direction write command 0xd5 set display clock divide ratio oscillator freguency write command 0xt0 write command 0xd8 set area color mode on off amp low power display mode write command 0x05 write command 0xd9 set pre charge period write command 0xc2 write command 0xda set com pins hardware configuration write command 0x12 write command 0xdb set vcom deselect level write command 0x08 write command Oxaf display on WRITE DATA amp COMMAND SUB FUNCTION void write_command unsigned char aa IOCLR 0x000000ff IOSET RD IN RD 1 14 ISEB ATH BRS IOCLR DC_IN DC 0 IOCLR CS_IN CS 0 IOCLR WR_IN WR 0 IOSET aa input command IOSET WR IN3 WR 1 IOSET CS IN CSz1 IOCLR RD IN void write_data unsigned char bb IOCLR 0x000000ff IOSET RD_IN RD 1 IOSET DC_IN DC 1 IOCLR CS_IN CS 0 IOCLR WR_IN WR 0 IOSET bb input data IOSET WR_IN WR 1 IOSET CS_IN CS 1 Note RD recommends Initial code and sub function for 8080 series CPU interface
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7. TERISTICS 4 1 80 Series MPU parallel Interface WRITE CHARACTERISTICS Figure 1 80 Series MPU parallel Interface Write Timing Diagram VDD a wies pn Wis me EMI Im ERNEUT and Select setup time ian Address and Select hold time wade Address setup time Laadi Address hold time Select setup time hold time e Low pulse width Select High pulse width wets Data setup time yet Data hold time Table 1 80 Series MPU parallel Interface Write Timing Characteristics ISEB ATH BR READ CHARACTERISTICS Figure 2 80 Series MPU parallel Interface Read Timing Diagram Conditions _ Related Pins uo ewe tee Address and Select setup time 0 Address and Select hold time 0 Address setup time AD 50 Address hold time 20 select Setup time eme REM Low pulse width ___ RB 20 n EEUU Data ir TT lime 200 Table 2 80 Series MPU parallel Interface Read Timing Characteristics Univision ERL m 4 2 6800 Series MPU parallel Interface PARALLEL INTERFACE CHARACTERISTICS 6800 SERIES MPU D15 to DO Figure 3 68 Series MPU parallel Interface Write Timing Diagram el VDD i Ta 25 Icswsa Chip select D time 10 las Address setup time AO 50 Address hold time RAN 20 levee White cycle time iewHwWES Write High Time IPwLWES Write Low Time Read cycle time Parameter read
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