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RLDRAM II Controller MegaCore Function v9.1 User Guide

1. Signals Table 2 3 shows the system signals Table 2 3 System Signals Part 1 of 3 Name clk Width Bits 1 Input Direction Description System clock for the control logic and datapath write_clk 1 Input Shifted clock that center aligns write data to the memory 2 22 RLDRAM II Controller MegaCore Function User Guide Altera Corporation November 2009 MegaCore Version 9 1 Functional Description Table 2 3 System Signals Part 2 of 3 Width Bits addr cmd clk 1 Input Address and command output register clock The addr_cmd_clk clock frequency must be the same as the system clock clk and the write clock write clk frequencies Name Direction Description In addition when there is a separate address and command clock phase no timing paths related to this clock should be cut to ensure that any paths using a separate clock for address and command are timing analysed das delay ctrl 6 Input Delay bus for DLL to shift DQS inputs DQS mode only non dqgs capture clk 1 Input Optional clock that captures read data and clocks read data logic Non DQS mode only reset clk n 1 Input Reset input for logic on the system clock domain The reset clk ncanbe asserted asynchronously but must be deasserted synchronous to the rising edge of the system clock
2. Name pees Direction Description rldramii_qvld The number of Input Read data valid flag RLDRAM II devices attached to memory interface rldramii_a_0 local addr Output Memory address signals rldramii a 1 1 rldramii ba O 3 Output Memory bank address signals rldramii ba 1 1 rldramii clk 1 to 3 wtih Output Memory command output clock rldramii clk n dedicated PLL clocks or 1 to 8 otherwise rldramii cs n 0 1 Output Memory chip select signal rldramii cs n 1 1 rldramii d Data bus width Output Memory write data bus SIO devices only rldramii dm The number of Output Memory DM optional RLDRAM II devices attached to memory interface rldramii ref n O0 1 Output Memory refresh request signal rldramii ref n 1 1 rldramii we n O0 1 Output Memory write enable signal rldramii we n 1 1 Note to Table 2 5 1 The default signal is signal 0 When you specify additional address and command busses both signal 0 and signal 1 are present Altera Corporation MegaCore Version 9 1 2 27 November 2009 RLDRAM II Controller MegaCore Function User Guide Parameters Table 2 6 shows the datapath interface signals Table 2 6 Datapath Interface Signals Width Eel s ae Name Bits Direction Description control a local addr Input Address bits control ba 3 Input Bank address bits con
3. 3 Filename variation name auk rldramii dm group vhd or VV Description Data mask DM group variation name gt _auk_rldramii_dqs_group vhd or V DQS group lt variation name auk rldramii pipeline addr cmd vhd or Vv Address and command pipeline registers variation name auk rldramii pipeline qvid vhd or v Valid data flag QVLD pipeline registers lt variation name auk rldramii pipeline rdata vhd or v Read data pipeline registers variation name auk rldramii pipeline wdata vhd or v Write data pipeline registers variation name auk rldramii qvid group vhd or v QVLD group lt variation name gt html MegaCore function report file lt variation name gt qip Contains Quartus II project information for your MegaCore function variations Notes to Table 3 1 1 2 3 lt variation name gt is the name you assign lt device name gt is the device family name lt top level name gt is the name of the Quartus II project top level entity 1 After you review the generation report click Exit to close IP Toolbench The Quartus II IP File qip is a file generated by the MegaWizard interface and contains information about the generated IP core You are prompted to add this qip file to the current Quartus II project at the time of file generation In most cases the qip file contains all of the necessary
4. Parameters Table 2 12 shows the pin loading parameters Table 2 12 Pin Loading Parameters Parameter Range pF Description Pin loading on FPGA 0 to 100 Enter the pin loading to match your board and memory devices DQ DQS pins Pin loading on FPGA 0 to 100 Enter the pin loading to match your board and memory devices address and command pins Pin loading on FPGA 0 to 100 Enter the pin loading to match your board and memory devices clock pins Project Settings Table 2 13 shows the example design settings Table 2 13 Example Design Settings Parameter Automatically apply RLDRAM II controller specific constraints to the Quartus II project Description When this option is turned on the next time you compile the Quartus Il software automatically runs the add constraints script Turn off this option if you do not want the script to run automatically Update the example design file that instantiates the RLDRAM Il controller variation When this option is turned on IP Toolbench parses and updates the example design file It only updates sections that are between the following markers lt lt START MEGAWIZARD INSERT lt tagname gt lt lt END MEGAWIZARD INSERT lt tagname gt If you edit the example design file ensure that your changes are outside of the markers or remove the markers Once you remove the markers you must keep the file updated because IP Toolbench can no l
5. Table 2 7 shows the memory type parameters Table 2 7 Memory Type Parameters Parameter Range Units Description RLDRAM II device Part number A part number for a particular memory device Choosing an entry sets many of the parameters in the wizard to the correct value for the specified part You can add your own devices to this list by editing the memory_types dat file in the constraints directory Clock speed 100 to 400 MHz The memory controller clock frequency The constraints script and the datapath use this clock speed It must be set to the value that you intend to use The first time you use IP Toolbench or if you turn on Update example design system PLL it uses this value for the IP Toolbench generated PLL s input and output clocks Interface voltage 1 5 or 1 8 V The RLDRAM II interface voltage DQ per DQS 8 9 16 18 Bits Number of DQ bits per DQS input pin CIO devices only Q per DQS 8 9 16 18 Bits Number of Q bits per DQS input pin SIO devices only Data bus width Device Bits The width of the memory interface dependent For more information about supported interface data widths refer to AN 325 Interfacing RLDRAM II with Stratix II Stratix amp Stratix GX Devices Table 2 8 shows the memory initialization options Table 2 8 Memory Initialization Options termination Parameter Range Description Memory configuration 1 2 or 3 Refer to you
6. reset addr cmd clk n 1 Input Reset input for logic on the address and command clock domain The reset addr cmd clk n canbe asserted asynchronously but must be deasserted synchronous to the rising edge of the address and command clock Altera Corporation MegaCore Version 9 1 2 23 November 2009 RLDRAM II Controller MegaCore Function User Guide Signals Table 2 3 System Signals Part 2 of 3 Width Name Bits addr cmd clk 1 Direction Input Description Address and command output register clock The addr_cmd_clk clock frequency must be the same as the system clock clk and the write clock write clk frequencies In addition when there is a separate address and command clock phase no timing paths related to this clock should be cut to ensure that any paths using a separate clock for address and command are timing analysed dgs delay ctrl 6 Input Delay bus for DLL to shift DQS inputs DQS mode only non dqgs capture clk 1 Input Optional clock that captures read data and clocks read data logic Non DQS mode only reset clk n 1 Input Reset input for logic on the system clock domain The reset clk ncanbe asserted asynchronously but must be deasserted synchronous to the rising edge of the system clock reset addr cmd clk n 1 Input Reset input for logic on the address and command clock domain The reset addr cmd clk n canbe as
7. Figure 2 11 RLDRAM II Initialization Sequence ridramii_clk Command EE ees OMM oO NTCCNS Moo NN oami anA Oo COMM NENNEN SONNEN NENNEN B ae ooo NEN NENEE NN RO NERO ea 200 ms 10 Clock 2 048 6 x 2 048 Pg Cycles tunsc Clock Cycles Clock Cycles MRS Mode Register Set CFG Mode Register Configuration Data RFx Refresh AC User Command The mode register set MRS command configures the RLDRAM II devices In the ten cycle MRS sequence the first nine MRS commands are dummy commands and all address bits are held at zero to reset the RLDRAM II DLL the final MRS command configures the memory The RLDRAM II configuration data CFG is output on the rldramii_a_0 bus during the final MRS command The following memory parameters are setup during the final MRS command cycle E RLDRAM II termination E Impedance matching resistor W DLL enable disable WB RLDRAM II configuration Writes When you assert 1ocal write req the control logic issues the write transaction immediately at the memory interface The control logic then requests write data by asserting 1ocal wdata req so that the RLDRAM II tw period is satisfied during write transactions This functionality means that the write request is decoupled from the write data Figure 2 12 shows three write requests at the local and SIO RLDRAM II interface In this example the mem
8. over multiple clock cycles for any requested read transactions If the memory burst length is set to two beats the read data is returned in a single clock cycle at the local interface local rdata valid The number of Output RLDRAM II devices attached to memory interface Read data valid signal which indicates that valid data is present on the read data bus The local rdata valid signalis aligned with the local read data 1ocal rdata Thereis only one 1ocal rdata valid per attached RLDRAM II device local wdata req 1 Output Write data request signal When the local interface asserts 1ocal wdata req all the write data for the burst should be available in contiguous clock cycles Table 2 5 shows the memory interface signals Table 2 5 Memory Interface Signals Part 1 of 2 Width Name Bits Direction Description rldramii dq Data bus width Bidirectional Memory data bus CIO devices only rldramii gk 1to9 Bidirectional In DQS mode the memory data strobe signal that captures read data into the Altera device in non DQS mode the RLDRAM II controller does not use rldramii_gqk rldramii q Data bus width Input Memory read data bus SIO devices only 2 26 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Table 2 5 Memory Interface Signals Part 2 of 2
9. Nonmultiplexed addressing Datapath generation Data strobe signal DOS and non DOS capture modes Automatic constraint generation Easy to use IP Toolbench interface IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators Support for OpenCore Plus evaluation The RLDRAM II controller MegaCore function handles the complex aspects of using RLDRAM II initializing the memory devices and translating read and write requests from the local interface into all the necessary RLDRAM II command signals The RLDRAM II controller is optimized for Altera Stratix II devices and has preliminary support for Stratix II GX and HardCopy II devices The advanced features available in these devices allow you to interface directly to RLDRAM II devices Figure 1 1 on page 1 3 shows a system level diagram including the example design that the RLDRAM II Controller MegaCore function creates for you MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 About This MegaCore Function Figure 1 1 RLDRAM II Controller System Level Diagram Example Design i Local Pass i Example Quee Control Logic or Fail Driver Encrypted Clock p System __p IRLDRAM II PLL Interface RLDRAM II Datapath Clear Text DLL Fedback Clock PLL 1 RLDRAM II Controlle
10. refer to OpenCore Plus Evaluation on page 1 4 OpenCore Plus Time Out Behavior on page 2 12 and AN 320 OpenCore Plus Evaluation of Megafunctions In the MegaWizard flow to implement your design based on the example design replace the example driver in the example design with your own logic gt A FIFO buffer is not implemented in the core you must implement a FIFO buffer You need to obtain a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production MegaCore Version 9 1 3 15 RLDRAM II Controller MegaCore Function User Guide Set Up Licensing After you obtain a license for RLDRAM II controller you can request a license file from the Altera web site at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative 3 16 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Additional Information Revision Histo ry The table below displays the revision history for the chapters in this user guide Date Version Changes Made November 2009 9 1 Updated the release information March 2009 9 0 Updated the release information November 2008 8 1 Updated the release information May 2008 8 0 e A
11. Environment Altera has carried out extensive functional tests using industry standard models to ensure the functionality of the RLDRAM II controller In addition Altera has carried out a wide variety of gate level tests on the RLDRAM II controller to verify the post compilation functionality of the controller Hardware Testing Table 2 16 shows the Altera development board on which Altera hardware tested the RLDRAM II controller Table 2 16 Altera Development Boards Development Board Altera Device Memory Device Stratix II Memory Demonstration Board 1 EP2S60F1020C3 Micron 18 bit CIO and SIO RLDRAM II devices Altera Corporation November 2009 MegaCore Version 9 1 2 33 RLDRAM II Controller MegaCore Function User Guide MegaCore Verification 2 34 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 3 Getting Started i Design Flow Altera Corporation November 2009 To evaluate the RLDRAM II Controller MegaCore function using the OpenCore Plus feature include these steps in your design flow 1 Obtain and install the RLDRAM II Controller MegaCore Function The RLDRAM II Controller is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website www altera com For system requirements and installation instructions refer to Altera Software Installation and Licensing Figure
12. beats The RLDRAM II device is setup with a tgc of six clock cycles configuration two Figure 2 14 Read Example eT UU UU AAA AAA Local Interface local_read_req local_write_req i ORERO local addr local bank addr A Y ooo Anoia ABoCo C2 CA local rdata valid local rdata RLDRAM II Interface rldramii clk rldramii clk n rldramii cs n rldramii we n rldramii ref n ridramii a 3 ridramii ba ridramii dm ridramii_d dram gli GmpaaRemaraaaRanomaqaee ridramii_qk ridramii qvld i i Figure 2 15 shows an example of a read following a write at a CIO RLDRAM II interface In this example the memory burst length is set to eight beats The RLDRAM II device is setup with a tgc of six clock cycles configuration two D For more information about bus turnaround timing calculations with CIO devices re
13. rldramii a O Note 2 ridramii ba O ridramii cs n O ridramii ref n O ridramii we n O C3 P Stratix II DLL You can connect the addr cmd c1k RLDRAM II controller input to clk write clk or to the dedicated PLL output C2 2 14 RLDRAM II Controller MegaCore Function User Guide Example Design IP Toolbench creates an example design that shows you how to instantiate and connect up the RLDRAM II controller to an example driver The example design is a working system that can be compiled and used for both static timing checks and board tests It also instantiates an example PLL that generates all the required clocks for the controller In DQS mode a DLL is instantiated that controls the DOS capture delay phase In non DQS mode the example design instantiates a fedback PLL The output of the fedback PLL is a phase shifted rldramii_gk data strobe which captures the read data The example driver is a self checking test generator for the RLDRAM II controller It uses a state machine to write data patterns to all memory banks It then reads back the data and checks that the data matches If any read data fails the comparison the pnf per byte output transitions low for one cycle and the pn persist permanent output transitions low and stays low Figure 2 10 shows a testbench and an example design Altera Corporation November 2009 MegaCore Version 9 1 Functional Description Figure 2 10 T
14. up tables ALUTS and logic registers for the RLDRAM II controller Table 1 5 Typical Size Note 1 Device Memory Width Bits Mti d Stratix Il and 9 127 169 Stratix II GX 18 130 209 36 151 287 72 185 444 Notes to Table 1 5 1 These sizes are a guide only and vary with different choices of parameters MegaCore Version 9 1 1 5 RLDRAM II Controller MegaCore Function User Guide Performance and Resource Utilization 1 6 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 N B 8 RYAN 2 Functional Description Block Figure 2 1 shows the RLDRAM II Controller MegaCore function block diagram Description Figure 2 1 RLDRAM II Controller Block Diagram Note 1 2 RLDRAM II Controller local addr 3j 4 rldramii dq local bank addr 3j 4 rldramii_q local dm 3 rldramii qk local read req gt 4 rldramii qvld local refresh req gt local wdata gt Control Loaic 3 ridramii a O local write reg E lt Datapath 3 rldramii ba O rldramii cIk local init done lt rldramii clk n local rdata lt 39 rldramii cs n O local rdata valid lt r rldramii d l
15. writing to the datapath Figure 2 3 Datapath Write Control Signal Timing clk control_doing_wr control_wdata_valid control wdata EE 01 23 45 67 control dm EE 1 1 i Memory Clock Generator The memory clock generator generates memory clocks There can be up to four memory clocks and they are generated with an altddio_out megafunction Address amp Command Output Registers The address and command output registers can have the following options W System write or dedicated clock clocking for the output registers W Rising or falling edge clocking MegaCore Version 9 1 2 5 RLDRAM II Controller MegaCore Function User Guide Block Description Pipeline Registers IP Toolbench can insert pipeline registers into the datapath to help meet timing at higher frequencies IP Toolbench offers the following pipeline options W Insert address and command and write data pipeline registers The pipeline depth is the same for the write data path and the address and command path The write data and address and command pipeline registers are clocked off the system clock m Insert read data and OVLD pipeline registers The pipeline depth is the same for the read data path and the OVLD path The read data and QVLD pipeline registers are clocked off the clock that captures the read data the delayed rldramii qgk signal in DOS mode th
16. 0 Pipeline t Data ridramii gk 1 control rdata 53 36 Registers Logic DQS Group 0 RLDRAM II Optional Read rldramii_dq 8 0 Device 0 Pipeline t Data gt rldramii qk 0 Registers 1 Logic capture cIk 0 lt Optional 34 s control qvid 0 lt Pipeline lt Eras E ridramii qvId 0 Registers p Figure 2 6 shows the following points which are applicable for all interface configurations WB Each DOS ridramii dq byte group is captured by the delayed version of its associated rldramii qk data strobe Altera Corporation MegaCore Version 9 1 2 9 November 2009 RLDRAM II Controller MegaCore Function User Guide Block Description rldramii dq rldramii gk e rldramii dq 8 0 is captured by the delayed 0 ii rldramii gk 1 2 2 3 7 9 is captured by the delayed rldramii dq ridramii gk amp rldramii dq rldramii gk 3 B OVLD is always captured by the delayed version of rldramii qk 0 for the associated RLDRAM II device In Figure 2 6 there are four rldramii_gqk signals Only rldramii gk 0 per RLDRAM II device captures the associated OVLD signal e rldramii qvld 0 is captured by the delayed rldramii qgk 0 e rldramii qvld 1 is captured by the delayed rldramii gk 2 m After the capture registers all captured read data is clocked off the undelayed rldramii qk signal that captures the OVLD signal for a particular RLDRAM II devic
17. 3 1 shows the directory structure after you install the RLDRAM II Controller where lt path gt is the installation directory The default installation directory on Windows is c altera lt version gt on Linux it is opt altera lt version gt Figure 3 1 RLDRAM II Controller Directory Structure lt path gt Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores altera Contains the Altera MegaCore IP Library en common Contains shared components ridram ii controller Contains the RLDRAM II Controller MegaCore function files and documentation constraints Contains scripts that generate an instance specific Tcl script for each instance of he RLDRAM II Controller in various Altera devices m dat Contains a data file for each Altera device combination that is used by the Tcl script to generate the instance specific Tcl script L doc Contains the documentation for the RLDRAM I Controller MegaCore function Lf iib Contains encrypted lower level design files and other support files 2 Create a custom variation of the RLDRAM II Controller MegaCore function using IP Toolbench MegaCore Version 9 1 3 1 RLDRAM II Controller Walkthrough RLDRAM II Controller Walkthrough 3 2 Le IP Toolbench is a toolbar from which you quickly and easily view documentation specify parameters and generate all of the files necessary for i
18. H MegaCore RLDRAM II Controller MegaCore Function User Guide ANU S n AN 101 Innovation Drive San Jose CA 95134 www altera com Document Date MegaCore Version 9 1 November 2009 Copyright 2009 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services I S EN ISO 9001 UG RLDRAM 8 1 ii MegaCore Version 9 1 Altera Corporation
19. RLDRAM II Controller MegaCore Function User Guide N D E PYN Contents Chapter 1 About This MegaCore Function Release Information 2 eret ert t HO RERO RR HER EU E EER Er ES EEE Device Family Support hori d General Description tir tete aieia EEE aa aaae Era E N ravisi iiaiai OpenCore Plus Evaluation tenete iena a iaeiiai 1 4 Performance and Resource Utilization cccccccccssccssessecesecsscessceseccsscssecesscsccsssesssesscesssesecssecaeesssenes 1 4 Chapter 2 Functional Description Block Descriptions M 2 1 Control LOGIC p 2 2 price dE E EE a r A E A 2 3 Op nCore Plus Time Otut Behavior nicissarii aseni e dn a 2 12 Device Leyel Config rati n svastara testen reor ero PER Aiea ieia 2 12 PLL Configuration gat Example Design 2 odoeg eoe E ii tecti ei E areal teas Constraints Interfaces Initialization Writes Pan Redds MEC Signals Bb D ERER pahazeed E ciaeedi eee UD Project Settinps 4 aote dut cae aded iet ui e MegaCore Verification Simulation Environment ire att o nn e e Pb da ona erra oe vta ev FR eed Vae apa ea aen adag ona va 2 33 Hardware Testing M 2 33 Chapter 3 Getting Started IprspaNdo 3 1 RLDRAM II Controller Walkthrough ses
20. S CIO devices or the Q per DOS SIO devices Choose the memory initialization options Choose your memory interface parameters Click the Timing tab For more information on timing parameters refer to Timing on page 2 31 6 Enter the datapath pipeline options 7 Choose the clocking modes 8 Turn on the appropriate capture mode DQS or non DQS capture mode If you turn off Enable DOS mode non DOS capture mode you can turn on Use migratable bytegroups 9 Click the Project Settings tab For more information on project settings refer to Project Settings on page 2 32 MegaCore Version 9 1 3 5 RLDRAM II Controller MegaCore Function User Guide RLDRAM II Controller Walkthrough 10 Altera recommends that you turn on Automatically apply RLDRAM II controller specific constraints to the Quartus IT project so that the Quartus II software automatically applies the constraints script when you compile the example design You must turn on this option the first time you run IP Toolbench 11 Ensure Update the example design file that instantiates the RLDRAM II controller variation is turned on for IP Toolbench to automatically update the example design file c You must turn on this option the first time you run IP Toolbench 12 Turn off Update example design system PLL if you have edited the PLL and you do not want the wizard to regenerate the PLL when you regenerate the variation l You must turn o
21. aCore Function User Guide November 2009 Getting Started Program a Device Implement Your Design Set Up Licensing Altera Corporation November 2009 s To achieve a higher frequency increase the number of address and command and write data pipeline registers or increase the number read data pipeline registers refer to step 6 on page 3 5 To view the constraints in the Quartus II Assignment Editor choose Assignment Editor Assignments menu Sz If you have characters in the Quartus II Assignment Editor the Quartus II software cannot find the entity to which it is applying the constraints probably because of a hierarchy mismatch Either edit the constraints script or enter the correct hierarchy path in the Project Settings tab refer to step 13 on page 3 6 For more information on constraints refer to Constraints on page 2 16 After you have compiled the example design you can perform gate level simulation refer to Simulate the Example Design on page 3 11 or program your targeted Altera device to verify the example design in hardware With Altera s free OpenCore Plus evaluation feature you can evaluate the RLDRAM II Controller MegaCore function before you obtain a license OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time limited programming file For more information on OpenCore Plus hardware evaluation using the RLDRAM II Controller MegaCore function
22. and command busses both signal 0 and signal 1 are present The datapath performs the following functions W Interfaces to CIO or SIO RLDRAM II devices B Outputs write data to the RLDRAM II interface W Captures RLDRAM II read data and data valid OVLD signals with e In DOS mode a delayed r1dramii qk generated by the dedicated DOS delay circuitry e Innon DQS mode an external capture clock 2 4 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Altera Corporation November 2009 E Generates the RLDRAM II clocks E Generates addresses and commands on e System dedicated or write clock e Rising or falling edge W Inserts pipeline registers in address and command and write data path WB Inserts pipeline registers in read data and OVLD path The datapath provides the interface between the read and write data busses of the datapath interface and the double clocked bidirectional data bus of the memory interface The datapath data busses are twice the width of the memory data bus because the memory interface transfers data on both the rising and falling edges of the clock IP Toolbench generates a clear text VHDL or Verilog HDL datapath which matches your custom variation If you are designing your own controller Altera recommends that you use this module as your datapath Figure 2 3 shows the write control signals timing relationship when
23. assignments and information required to process the core or system in the Quartus II compiler Generally a single qip file is generated for each MegaCore function or system in the Quartus II compiler Now simulate the example design refer to Simulate the Example Design on page 3 11 edit the PLL s and compile refer to Compile the Example Design on page 3 14 3 10 MegaCore Version 9 1 RLDRAM II Controller MegaCore Function User Guide Altera Corporation November 2009 Getting Started Si mulate the This section describes the following simulation techniques Exa mp e D esit n B Simulate with IP Functional Simulation Models W Simulating in Third Party Simulation Tools Using NativeLink Simulate with IP Functional Simulation Models You can simulate the example design using the IP Toolbench generated IP functional simulation models IP Toolbench generates a VHDL or Verilog HDL testbench for your example design which is in the testbench directory in your project directory For more information on the testbench refer to Example Design on page 2 14 You can use the IP functional simulation model with any Altera supported VHDL or Verilog HDL simulator To simulate the example design with the ModelSim simulator follow these steps 1 Obtain a memory model that matches your chosen parameters and save it to the directory name Ntestbench directory For example you can download a RLDRAM II model from the Mic
24. ata associated with rldramii qk rising edge E Data associated with rldramii qk falling edge Figure 2 8 shows that any read data captured on the rising edge of the delayed rldramii qk signal is located in the lower half bit locations of control rdata Any read data captured on the falling edge of the delayed r1dramii_qk signal is located in the upper half bit locations Altera Corporation MegaCore Version 9 1 2 11 November 2009 RLDRAM II Controller MegaCore Function User Guide Device Level Configuration of control rdata which means different bit ranges of the control rdata are associated with different capture clk signals Ls Figure 2 8 is a specific example but the mapping and clock association applies to any RLDRAM II controller interface and memory configuration OpenCore Plus Time Out Behavior OpenCore Plus hardware evaluation can support the following two modes of operation W Untethered the design runs for a limited time W Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions ce For MegaCore
25. ck frequency that you entered in IP Toolbench In addition IP Toolbench correctly sets all the phase offsets of all the relevant clock outputs for your design You can edit the PLL input clock to make it conform to your system requirements If you re run IP Toolbench and wish to save your PLL edits turn off Update example design system PLL Ds If you turn off Enable DOS mode IP Toolbench generates a second PLL the fedback PLL You need not edit the fedback PLL For more information on the PLL refer to PLL Configuration on page 2 12 To edit the example PLL follow these steps 1 Choose MegaWizard Plug In Manager Tools menu 2 Select Edit an existing custom megafunction variation and click Next 3 Inyour Quartus II project directory for VHDL choose rldramii_pll_ lt device name vhd for Verilog HDL choose rldramii pll device name gt v 4 Click Next 5 Edit the PLL parameters in the altp11 MegaWizard Plug In For more information on the altp11 megafunction refer to the Quartus II Help or click Documentation in the ALTPLL MegaWizard Plug In MegaCore Version 9 1 3 13 RLDRAM II Controller MegaCore Function User Guide Compile the Example Design Compile the Example Design 3 14 Before the Quartus II software compiles the example design it runs the IP Toolbench generated Tcl constraints script auto add rldramii constraints tcl which calls the add constraints for variation name gt tcl script for eac
26. dded timing assignment information for capture to first level resyncronization registers e Registers clocked by DQS in the core now use undelayed DQS May 2007 7 1 No changes March 2007 7 0 No changes December 2006 6 1 e Added timing assignment information for 18 and 36 bit RLDRAM II devices e Updated device initialization sequence April 2006 1 1 0 Updated format October 2005 1 0 0 First published How to Contact Altera Altera Corporation For the most up to date information about Altera products refer to the following table Information Type Contact Vote 1 Technical support www altera com mysupport Technical training www altera com training Technical training services custrain Q altera com Product literature www altera com literature FTP site ftp altera com Note to table 1 You can also contact your local Altera sales office or sales representative MegaCore Version 9 1 i RLDRAM II Controller MegaCore Function User Guide Typographic Conventions Typographic Conventions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Indicates command names dialog box titles dialog box options and other GUI labels For example Save As dialog box bold type Indicates directory names project names disk drive names file names file name extensions and software utility names For example qdes
27. design as well as evaluate its size and speed quickly and easily E Generate time limited device programming files for designs that include MegaCore functions W Program a device and verify your design in hardware You only need to obtain a license for the megafunction when you are completely satisfied with its functionality and performance and want to take your design to production For more information on OpenCore Plus hardware evaluation using the RLDRAM II controller refer to OpenCore Plus Time Out Behavior on page 2 12 and AN 320 OpenCore Plus Evaluation of Megafunctions Table 1 3 shows typical expected performance for the RLDRAM II Controller MegaCore function with the Quartus II software Table 1 3 Performance Device Capture Mode fmax MHz Stratix Il Non DQS 200 EP2S60F1020C3 Das 300 Stratix II GX Non DQS 200 EP2SGX30CF780C3 Das T zo Altera Corporation November 2009 MegaCore Version 9 1 About This MegaCore Function Altera Corporation November 2009 Stratix II and Stratix II GX devices support RLDRAM at up to 300 MHz Table 1 4 shows the clock frequency support for Stratix II and Stratix GX device families with the Quartus II software Table 1 4 RLDRAM II Maximum Clock Frequency Support in Stratix Il amp Stratix GX Devices Speed Grade Frequency MHz 3 300 4 250 5 200 Table 1 5 shows typical sizes in combinational adaptive look
28. devices Generates RLDRAM II clocks Places RLDRAM II commands onto the memory command bus using one of the following system PLL clocks on either the rising or falling edge e System clock e Write clock e Dedicated clock W Places write data onto the rldramii_dg or rldramii_d bus during the correct clock cycles W Captures the read data using dedicated data strobe signal DOS delay circuitry during DOS mode or an external capture clock in non DQS mode Control Logic The control logic is responsible for controlling transactions at the memory interface The control logic accepts read write and refresh requests and executes them immediately as RLDRAM II transactions In addition to reads writes and refreshes the control logic is also responsible for controlling initialization of the RLDRAM II devices For more information on reads writes refreshes and initialization see Interfaces on page 2 16 2 2 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Table 2 1 shows the RLDRAM II control signals generated by the control logic for each operation Altera Corporation November 2009 Table 2 1 Control Signals ridramii ridramii ridramii ridramii ridramii Pardon Arann cs n we n 0 ref n 0 a 0 20 0 ha 0 2 0 Idle NOP High Don t care Don t care Don t care Don t care Mode MRS Low Lo
29. dr 3 RLDRAM II bank address local_dm The number of Input RLDRAM II devices attached to the memory interface x Optional local data mask DM Twice the width of the memory r1dramii dm bus When all high all writes are masked 2 local read req 1 Input Read request signal local refresh req 1 Input User controlled refresh request This allows complete control over when refreshes are issued to the memory The refresh is issued to the bank address on 1ocal bank addr Altera Corporation November 2009 MegaCore Version 9 1 2 25 RLDRAM II Controller MegaCore Function User Guide Signals Table 2 4 Local Interface Signals Part 2 of 2 Width Bits local wdata Data bus width x 2 Input Name Direction local write req 1 Input Description Write data bus The local interface must request local wdata over multiple clock cycles to construct the write data for any requested write bursts If the memory burst length is set to two beats the write data is requested in a single clock cycle at the local interface Write request signal local init done 1 Output Memory initialization complete signal which is asserted when the controller has completed its initialization of the memory Reads and writes should not be requested until local init done is asserted local rdata Data bus width x 2 Output Read data bus The controller returns local rdata
30. e e All RLDRAM II 0 captured data is clocked off the undelayed rldramii gk O0 e All RLDRAM II 1 captured data is clocked off the undelayed rldramii_gqk 2 WB Only one capture_clk per attached RLDRAM II device is output from the datapath e RLDRAMII0 capture data is associated with capture clk 0 which is the delayed r1dramii qgk 0 e RLDRAMII 1 capture data is associated with capture clk 1 which is the delayed rldramii_gk 2 6 18 is captured by the delayed 5 27 is captured by the delayed Read Data Capture Clock Association Figure 2 7 shows the read data and data strobes at the memory interface for the example datapath in Figure 2 6 Figure 2 8 shows how the capture clk associates with the captured read data control rdata atthe datapath interface 2 10 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Figure 2 7 Memory Interface RLDRAM II Device 1 rldramii_qk 3 ridramii da 26 18 ridramii qk 2 RLDRAM II Device 0 rerami_ deft 7 rldramii_qk 1 rldramii da 8 0 A rldramii_qk 0 LI Data associated with rldramii qk rising edge E Data associated with rldramii qk falling edge Figure 2 8 Datapath Interface capture clk 1 capture cIk 0 control rdata O D
31. e RLDRAM II controller issues the refresh command immediately to the requested bank address on local_bank_addr input You must correctly insert the refresh request and ensure that the tgc timing parameter is not violated You can issue single or ganged refreshes For ganged refreshes assert 1ocal refresh req for X clock cycles where X is the number of refreshes that you require Figure 2 16 shows a single refresh command MegaCore Version 9 1 2 21 RLDRAM II Controller MegaCore Function User Guide Signals Figure 2 16 Single Refresh Command clk Local Interface local_write_req local_read_req local_refresh_req N local addr ILLI E a local_bank_addr local_wdata_req D MINNIE Y B local wdata s local dm RLDRAM II Interface 00 rldramii_clk ridramii clk n ridramii cs n ridramii we n ridramii ref n ILLE rldramii_a AS ridramii ba ridramii dm rldramii dq ridramii qk ridramii qvid LE qe anni
32. e control doing wr D Q D Q control wdata control wdata valid write clk control rdata dq capture clk DQs capture clk lt DQS Delay lt _ gt Note 4 Notes to Figure 2 4 1 This figure shows the logic for one DQ output only 2 All clocks are clk unless marked otherwise 3 Bus width W is dependent on the DQ per DQS parameter 4 Invert combout of the I O element IOE for the dqs pin before feeding in to inclock of the IOE for the DQ pin This inversion is automatic if you use an alt dq megafunction for the DQ pins Figure 2 5 on page 2 8 shows the Stratix II series and HardCopy II devices DOS group block diagram DOS mode SIO devices Altera Corporation MegaCore Version 9 1 2 7 November 2009 RLDRAM II Controller MegaCore Function User Guide Block Description Figure 2 5 DQS Group Block Diagram DQS Mode SIO Devices Note 1 2 3 n dq oe control doing wr D Q D Q control wdata control wdata valid write clk control rdata dq capture clk DQs capture clk lt DQS Delay lt _ gt Note 4 Notes to Figure 2 4 1 This figure shows the logic for one Q output and one D input only 2 All clocks are clk unless marked otherwise 3 Bus width W is dependent on the Q per DQS paramete
33. e external capture clock in non DOS mode DQS Group The datapath instantiates one or more DOS groups which generates write data rldramii_dq CIO devices or rldramii_d SIO devices and captures read data r1dramii dq CIO devices or rldramii q SIO devices The IP Toolbench DQ per DOS CIO devices or O per DOS SIO devices parameter determines the DOS group width For example if DO per DOS is 9 bits the control wdata and control rdata signals are 18 bits wide To build larger widths the datapath instantiates multiple DOS group modules to increase the data bus width in increments of DO per DOS or Q per DOS bits ce The datapath generates the DM output r1dramii dm inthe DM group module It generates the DM output in the same way as the write data ce The datapath captures the OVLD input rldramii_qvld in the OVLD group module The r1dramii qvld signal is captured in the same way that the DOS group module captures the read data In DOS mode the delayed rldramii qgk captures rldramii_gqvld in non DQS mode the external clock captures rldramii_qvld Figure 2 4 on page 2 7 shows the Stratix II series and HardCopy II devices DOS group block diagram DOS mode CIO devices 2 6 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Figure 2 4 DQS Group Block Diagram DQS Mode CIO Devices Note 1 2 3 n dq o
34. e nennen 3 2 Create a New Quartus II Project Launch IP Toolbenchi 55 2 nct ree e tenir eec irte esr dee eed Ee Pede Eve Step 1 Paramielterize cicer inm te ri niei dederit tui ir tort He e e E beet de reor Step 2 Constraints Step 3 Set Up Simulation Step 4 Generate ET simulate the Example Design erint e tete ise teatri rer rt tauatai dosak ersi Altera Corporation MegaCore Version 9 1 iii Contents Simulate with IP Functional Simulation Models esee 3 11 Simulating in Third Party Simulation Tools Using NativeLink sse 3 12 Editthe PEE 1 ENGINE URB DENEN E ELRL EON ESTE IE LUE 3 13 Compile the Example Design eene eret ise etre OUR iria si seti erede 3 14 Program a Device Implement Your Design E 3 15 Set Up BI D A 3 15 Additional Information Revision LHstOry o desineret oH Eee eite deret ite nes iiio How to Contact Altera Typographic Conventions iv MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide ANU 8 p AA 1 About This MegaCore Function Release Information Device Family Support Altera Corporation November 2009 Table 1 1 provides information about this release of the Altera RLDRAM II Controller MegaCore function Table 1 1 Release Information Item Descrip
35. e way in which the write data is generated and allows better control of the skew between the clock and the data to meet the timing requirements of the RLDRAM II device The PLL has the following outputs W Output c0 drives the system clock that clocks most of the controller including the control logic and datapath WB Output c1 drives the write clock that lags the system clock WB Output c2 optionally drives the address and command clock WB Output c3 drives the DOS DLL clock The recommended configuration for implementing the RLDRAM II controller in Stratix II series and HardCopy II devices is to use a single enhanced PLL to produce all the required clock signals No external clock buffer is required as the Altera device can generate clock signals for the RLDRAM II devices Figure 2 9 on page 2 14 shows the recommended PLL configuration MegaCore Version 9 1 2 13 RLDRAM II Controller MegaCore Function User Guide Device Level Configuration Figure 2 9 PLL Configuration Notes to Figure 2 9 Non DQS mode only 1 2 clock source 34 FPGA Device Enhanced PLL non dqs capture clk Optional ridramii qk ee Fed Back Clock M4 PLL Note 1 RLDRAM II Controller clk ridramii clk n co altddio H write clk ci ridramii clk i altddio i 4 RLDRAM II Address amp C2 gt Command addr cmd clk Registers
36. equencies Table 2 11 shows the clocking modes Table 2 11 Clocking Modes Parameter Address and command clock Range System write or dedicated Description The clock for the address and command output registers For system clk choose System for write_clk choose Write and for a separate clock choose Dedicated If you choose Dedicated for the clock ensure the clock phase allows the Quartus II software to meet the setup time on the address and command output registers Address and command clock edge Falling or rising The clock edge on which the addresses and commands are output offset Dedicated address 180 Sets the dedicated address and command clock PLL phase for better and command clock timing PLL phase offset Enable DQS mode On or off Turn on for DQS mode otherwise the controller is in non DQS mode Stratix Il and Stratix II GX devices only HardCopy II devices allow DQS mode only Use migratable byte On or off When turned on you can migrate the design to a migration device groups When turned off the wizard allows much greater flexibility in the placement of byte groups You can only turn on this option when Enable DQS mode is turned off Fedback PLL phase 180 Sets the fedback clock PLL phase for read capture non DQS mode only Altera Corporation November 2009 MegaCore Version 9 1 2 31 RLDRAM II Controller MegaCore Function User Guide
37. estbench amp Example Design Testbench Example Design pnf persist lt test complete amp pnf per byte lt RLDRAM II Example Driver 4 X RLDRAM II Controller 4f 39 Model i i clock_source PLL DLL Altera Corporation November 2009 Table 2 2 describes the files that are associated with the example design and the testbench Table 2 2 Example Design amp Testbench Files Filename top level name tb v or vhd 7 Description Testbench for the example design top level name vhd or v 1 Example desi gn ridramii pll device name gt vhd or v Example PLL which you should configure to match your frequency ridramii fbpll device name gt vhd or V Fedback PLL lt variation name gt _example_driver v or vhd 2 Example driver variation name v or vhd 2 RLDRAM II controller Notes to Table 2 2 1 top level name is the name of the Quartus II project top level entity 2 variation name is the variation name The testbench instantiates an RLDRAM II model and generates a reference clock for the PLL c Altera does not provide a memory simulation model You must download one or use your own MegaCore Version 9 1 2 15 RLDRAM II Controller MegaCore Function U
38. fer to AN 325 Interfacing RLDRAM II with Stratix I Stratix amp Stratix GX Devices 2 20 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Figure 2 15 Read Following a Write clk Local Interface local_write_req local_read_req local_addr p 38 local bank addri local wdata req DERE local wdata az local dm local rdata valid local rdata RLDRAM II Interface fo aN 9 rldramii_clk ridramii clk n rldramii cs n ridramii we n ridramii ref n ridramii_a B ridramii ba E ridramii dm i11 gi X rldramii dq rldramii qk ridramii qvild f Ti Altera Corporation November 2009 Refreshes You must issue refreshes to the RLDRAM II devices at periodic intervals When a refresh is required assert 1ocal refresh req and th
39. functions the untethered time out is 1 hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires and the controller issues no read commands at the memory interface D For more information on OpenCore Plus hardware evaluation see OpenCore Plus Evaluation on page 1 4 and AN 320 OpenCore Plus Evaluation of Megafunctions Device Level This section describes the following topics Confi gu ration W PLL Configuration on page 2 12 W Example Design on page 2 14 W Constraints on page 2 16 PLL Configuration IP Toolbench creates up to two example PLLs in your project directory which you can parameterize to meet your exact requirements IP Toolbench generates the example PLLs with an input to output clock ratio of 1 1 and a clock frequency you entered in IP Toolbench In addition IP Toolbench sets the correct phase outputs on the PLLs clocks You can 2 12 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Altera Corporation November 2009 edit the PLLs to meet your requirements with the altp11 MegaWizard Plug In IP Toolbench overwrites your PLLs in your project directory unless you turn off Update example design system PLL The external clocks are generated using standard I O pins in double data rate I O DDIO mode using the alt ddio_out megafunction This generation matches th
40. h variation in your design The add constraints for variation name tcl script checks for any previously added constraints removes them and then adds constraints for that variation The constraints script analyzes and elaborates your design to automatically extract the hierarchy to your variation To prevent the constraints script analyzing and elaborating your design turn on Enable Hierarchy Control in the wizard and enter the correct hierarchy path to your datapath refer to step 13 on page 3 6 When the constraints script runs it creates another script remove constraints for variation name gt tcl which you can use to remove the constraints from your design To compile the example instance follow these steps 1 Choose Start Compilation Processing menu which runs the add constraints scripts compiles the example design and performs timing analysis 2 View the Timing Analyzer to verify your design meets timing If the compilation does not reach the frequency requirements follow these steps 1 Choose Settings Assignments menu 2 Expand Analysis and Synthesis Settings in the category list 3 Select Speed in Optimization Technique 4 Expand Fitter Settings 5 Turn on Optimize Hold Timing and select All Paths 6 Turnon Fast corner timing 7 Click OK 8 Re compile the example design by choosing Start Compilation Processing menu MegaCore Version 9 1 Altera Corporation RLDRAM II Controller Meg
41. igns directory d drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicates document titles For example AN 519 Stratix IV Design Guidelines Italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and project name gt pot file Initial Capital Letters Indicates keyboard keys and menu names For example Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus II Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example datal tdi and input Active low signals are denoted by suffix n For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important The hand points to information that requires special attention A caution calls attention
42. matically specifies a top level design entity that has the same name as the project Do not change it Click Next to close this page and display the New Project Wizard Add Files page La When you specify a directory that does not already exist a message asks if the specified directory should be created Click Yes to create the directory If you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software you must add the user libraries a Click User Libraries MegaCore Version 9 1 3 3 RLDRAM II Controller MegaCore Function User Guide RLDRAM II Controller Walkthrough b Type path Nip into the Library name box where lt path gt is the directory in which you installed the RLDRAM II controller c Click Add to add the path to the Quartus II project d Click OK to save the library path in the project Click Next to close this page and display the New Project Wizard Family amp Device Settings page On the New Project Wizard Family amp Device Settings page choose the target device family in the Family list The remaining pages in the New Project Wizard are optional Click Finish to complete the Quartus II project You have finished creating your new Quartus II project Launch IP Toolbench To launch IP Toolbench in the Quartus II software follow these steps 1 3 4 Start the MegaWizard Plug In Manager by choosing MegaWizard Plug In Manager Tool
43. n and copy an RLDRAM II model to a suitable location for example the testbench directory le Before running the simulation you may also need to edit the testbench to match the chosen RLDRAM II model 3 Check that the absolute path to your third party simulator executable is set On the Tools menu click Options and select EDA Tools Options 4 Onthe Processing menu point to Start and click Start Analysis amp Elaboration 5 Onthe Assignments menu click Settings expand EDA Tool Settings and select Simulation Select a simulator under Tool Name and in NativeLink Settings select Compile Test Bench and click Test Benches 6 Click New 7 Enter aname for the Test bench name 8 Enter the name of the automatically generated testbench project name tb in Test bench entity 9 Enter the name of the top level instance in Instance 10 Change Run for to 80 us 3 12 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Getting Started Edit the PLL Altera Corporation November 2009 11 Add the testbench files In the File name field browse to the location of the RLDRAM II model and the testbench project name tb click OK and click Add 12 Click OK 13 Click OK 14 On the Tools menu point to EDA Simulation Tool and click Run EDA RTL Simulation The IP Toolbench generated example design includes a PLL which has an input to output clock ratio of 1 1 and a clo
44. n this option the first time you run IP Toolbench 13 The constraints script automatically detects the hierarchy of your design The constraints script analyzes and elaborates your design to automatically extract the hierarchy to your variation To prevent the constraints script analyzing and elaborating your design turn on Enable Hierarchy Control and enter the correct hierarchy path to your datapath Figure 3 2 shows the following example hierarchy my system my system inst my sub system my sub system inst my rldramii my rldramii inst datapath datapath inst 3 6 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Getting Started Figure 3 2 System Naming example top Example Top Level Design my system Other Logic lt gt System my sub system Subystem RLDRAM II Interface my ridram m RLDRAM II RLDRAM II Contro ler PLL Datapath 14 IP Toolbench uses a prefix for example rldramii for the names of all memory interface pins Enter a prefix for all memory interface pins associated with this custom variation 15 Enter the pin loading for the FPGA pins a Youmustenter suitable values for the pin loading because the values affect timing 16 Click Finish Step 2 Constraints To choose the constraints for your device follow these steps 1 Click Ste
45. ntegrating the parameterized MegaCore function into your design Implement the rest of your design using the design entry method of your choice Use the IP Toolbench generated IP functional simulation model to verify the operation of your design For more information on IP functional simulation models refer to the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook 5 Edit the PLL 6 Use the Quartus II software to add constraints to the example 9 10 design and compile the example design Perform gate level timing simulation or if you have a suitable development board you can generate an OpenCore Plus time limited programming file which you can use to verify the operation of the example design in hardware Either obtain a license for the RLDRAM II controller MegaCore function or replace the encrypted RLDRAM II controller control logic with your own logic and use the clear text datapath s ag you obtain a license for the RLDRAM II controller you must set up licensing Generate a programming file for the Altera device s on your board Program the Altera device s with the completed design This walkthrough explains how to create a RLDRAM II controller using the Altera RLDRAM II controller IP Toolbench and the Quartus II software on a PC When you are finished generating a custom variation of the RLDRAM II controller MegaCore function you can incorporate it into yo
46. ocal wdata req amp 39 ridramii dm rldramii ref n O clk 3 39 rldramii we n O write clk addr cmd clk 9 9 non dgs capture clk Note 3 reset clk n reset addr cmd clk n reset read clk n J capture clk Note 4 4 34 dqs delay ctrl Note 4 J9 4 Notes to Figure 2 1 1 You can edit the rldramii_ prefix in IP Toolbench 2 The default signal is signal 0 When you specify additional address and command busses both signal 0 and signal 1 are present 3 Non DQS mode only 4 DQS mode only Altera Corporation MegaCore Version 9 1 2 1 November 2009 Block Description The RLDRAM II controller comprises the following two blocks W Control logic encrypted W Datapath clear text The control logic performs the following actions E Generates initialization sequence using the RLDRAM II initialization values set in IP Toolbench W Generates write read or refresh accesses when requested at the local interface E Generates datapath control signals that ensure that the write data is output on the memory r1dramii dq CIO devices or rldramii d SIO devices bus during the correct clock cycles The datapath performs the following actions W Interfaces to common I O CIO or separate I O SIO RLDRAM II
47. onger update the file Update example design system PLL When this option is turned on IP Toolbench automatically overwrites the PLL Turn off this option if you do not want the wizard to overwrite the PLL 2 32 RLDRAM II Controller MegaCore Function User Guide Altera Corporation November 2009 MegaCore Version 9 1 Functional Description Table 2 14 shows the variation path parameters Table 2 14 Variation Path Parameters Parameter Enable hierarchy control Description The constraints script analyzes your design to automatically extract the hierarchy to your variation To prevent the constraints script analyzing your design turn on Enable Hierarchy Control and enter the correct hierarchy path to your datapath Hierarchy path to RLDRAM II controller datapath The hierarchy path is the path to your RLDRAM II controller datapath minus the top level name The hierarchy entered in the wizard must match your design because the constraints scripts rely on this path for correct operation Table 2 15 shows the device pin prefixes parameter Table 2 15 Device Pin Prefixes Parameter Prefix all RLDRAM II pins on the device with Description This string prefixes the pin names for the FPGA pins that are connected to the RLDRAM II controller MegaCore Verification MegaCore verification involves simulation testing and hardware testing Simulation
48. ory burst length is set to eight beats The RLDRAM II device is setup with a tgc of six clock cycles configuration two Altera Corporation MegaCore Version 9 1 2 17 November 2009 RLDRAM II Controller MegaCore Function User Guide Interfaces Figure 2 12 Write Example niuuuuuuuuuuuuuuuuuuuuuuti Local Interface local write req local read req local addr I C i local_baf Y C y local wdata req e local wdata koyjazghas er ops pasppe pores pas cei local dmi pod oO dj dj P dj i ij i i i j j RLDRAM II Interface i i ridramii_clk rldramii_clk_n rldramii cs n aW Lf rldramii we n J i A ridramii_ref_n ae AE NE rldramii a B i rdramii_ba REIR RN ee es wmuawp a JM ridramii gk Jd IBI BEBE BERE BE BEBIEBIEBEU ridramii qvid d rldramii_q Figure 2 12 shows the transactions at the local interface are separated by the correct number of clock cycles for the ta
49. p 2 Constraints in IP Toolbench 2 Choose the positions on the device for each of the RLDRAM II byte groups To place a byte group select the byte group in the drop down box at your chosen position s The floorplan matches the orientation of the Quartus II floorplanner The layout represents the die as viewed from above A byte group consists of data DO pins for CIO devices or data Q pins for SIO devices and a data strobe signal DOS pin The number of data pins per byte group matches your choice of DO or Q per DOS Altera Corporation MegaCore Version 9 1 3 7 November 2009 RLDRAM II Controller MegaCore Function User Guide RLDRAM II Controller Walkthrough Step 3 Set Up Simulation An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software The model allows for fast functional simulation of IP using industry standard VHDL and Verilog HDL simulators You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes Using these models for synthesis will create a nonfunctional design CAUTION To generate an IP functional simulation model for your MegaCore function follow these steps 1 Click Step 3 Set Up Simulation in IP Toolbench 2 Turnon Generate Simulation Model 3 Choose the language in the Language list 4 Some third party synthesis tools can use a netlist that contains only the s
50. r Note to Figure 1 1 1 Non DOS mode only IP Toolbench generates the following items m Atestbench which instantiates the example design WB Asynthesizable example design which instantiates the following modules e RLDRAM II controller e Encrypted control logic which takes transaction requests from the local interface and issues writes reads and refreshes to the memory interface e Aclear text datapath e Example driver generates write read and refresh requests and outputs a pass fail signal to indicate that the tests are passing or failing e System phase locked loop PLL generates the RLDRAM II controller clocks e Delay locked loop DLL instantiated in DOS mode and generates the DOS delay control signal for the dedicated DOS delay circuitry Altera Corporation MegaCore Version 9 1 1 3 November 2009 RLDRAM II Controller MegaCore Function User Guide Performance and Resource Utilization Performance and Resource Utilization 1 4 RLDRAM II Controller MegaCore Function User Guide e Optional fedback clock PLL instantiated in non DOS mode and generates a capture clock for the datapath read capture and logic path OpenCore Plus Evaluation With Altera s free OpenCore Plus evaluation feature you can perform the following actions W Simulate the behavior of a megafunction Altera MegaCore function or AMPP megafunction within your system W Verify the functionality of your
51. r 4 Invert combout of the I O element IOE for the dqs pin before feeding in to inclock of the IOE for the Q pin This inversion is automatic if you use an alt dq megafunction for the Q pins Datapath Example Figure 2 6 shows an example datapath The example RLDRAM II controller and memory configuration has the following parameters E DOS mode B Two 18 bit CIO RLDRAM II devices Each RLDRAM II device has two rldramii qk data strobes each associated with 9 bits of data W 36 bit RLDRAM II interface which requires a 72 bit datapath interface 2 8 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Figure 2 6 Example Datapath Datapath DQS Group 3 Optional Read Pi rldramii dq 35 27 control rdata 35 18 Pipeline Data rldramii_qk 3 control rdata 71 54 Registers Logic DQS Group 2 RLDRAM II Optional Read a rldramii dq 26 18 Device 1 Pipeline j lt Data ridramii qk 2 Registers Logic capture clk 1 44 e Optional 34 z control qvid 1 lt Pipeline 4 amp 74 Sri E ridramii qvid 1 Registers p DQS Group 1 Optional Read ridramii dq 17 9 control rdata 17
52. r RLDRAM II data sheet Burst length 2 4 0r8 Number of beats in the burst at the memory interface The number of beats at the local interface is half this value Manually enter On or off The wizard takes the number of initialization clock cycles from the initialization clock memory dat file in the constraints directory The number is cycles calculated from the initialization entry time and the clock speed You Number of 16 to 80 000 can manually enter a number for the initialization clock cycles if you initialization clock turn on Manually enter initialization clock cycles cycles Enable on die On or off Refer to your RLDRAM II data sheet Altera Corporation November 2009 MegaCore Version 9 1 2 29 RLDRAM II Controller MegaCore Function User Guide Parameters Table 2 8 Memory Initialization Options Parameter Range Description Enable external On or off Refer to your RLDRAM II data sheet impedance matching Enable memory On or off Refer to your RLDRAM II data sheet device DLL Table 2 9 shows the memory interface parameters Note to Table 2 9 Table 2 9 Memory Interface Parameters Parameter Range Units Description Number of address 1or2 2 Depends on the number of devices If you connect only and command busses one device there can be only one address and command from FPGA to bus 1 memory for multiple devices Generate DM pins On or off Adds DM pins and logic
53. ramii a A dif rldramii bap TT A i drami am E i 4 i i i Yoo Ye wem a ridramii qk drami avag 7 3 2 1 oco b io GOGOL FEN Reads When you assert 1ocal read req the control logic issues the read transaction immediately at the memory interface In DOS mode the read data r1dramii dq CIO devices or rldramii q SIO devices and the OVLD signals rldramii qvld are captured using the delayed rldramii_gk data strobes that have been phase shifted using the dedicated DOS delay circuitry In non DQS mode the read data r1dramii dq or rldramii q and the OVLD signals r1dramii qvld are captured using an external capture clock Altera Corporation MegaCore Version 9 1 2 19 November 2009 RLDRAM II Controller MegaCore Function User Guide Interfaces During reads the local interface indicates that read data is valid by asserting the 1ocal rdata valid signal All captured read data is clocked off the clock that captures the RLDRAM II read data In DOS mode this clock is the delayed DOS signal capture clk sourced from the dedicated DOS delay circuitry In non DQS mode this clock is the external capture clock non dqs capture clk Figure 2 14 shows an example of a read at an SIO RLDRAM II interface In this example the memory burst length is set to eight
54. rget RLDRAM II device configuration If transaction requests are supplied to the RLDRAM II controller with the incorrect spacing the controller executes these transactions as requested which can result in incorrect behavior Figure 2 13 shows an example of a write following a read at a CIO RLDRAM II interface In this example the memory burst length is set to two beats The RLDRAM II device is setup with a tgc of six clock cycles configuration two 2 D For more information about bus turnaround timing calculations with CIO devices refer to AN 325 Interfacing RLDRAM II with Stratix II Stratix amp Stratix GX Devices 2 18 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Figure 2 13 Write Following a Read arii 1 Local Interface local write req tox N local read req local addr y A Y y B Y local ba A j B local wdata req woa waag O X i 410 lca dm 10 RLDRAM II Interface rldramii_clk i ridramii clk n BM ridramii cs n Hi ridramii we n ridramii ref n rid
55. ron web site at wWww micron com gt Before running the simulation you may also need to edit the testbench to match the chosen RLDRAM II model 2 Startthe ModelSim Altera simulator 3 Change your working directory to your IP Toolbench generated file directory directory name NtestbenchNmodelsim 4 Tosimulate with an IP functional simulation model simulation type the following command source uariation name vsim tcle 5 Before running the simulation you may have to edit the set memory model parameter in the variation name vsim tcl file to match the selected RLDRAM IT model 5 Fora gate level timing simulation VHDL or Verilog HDL ModelSim output from the Quartus II software type the following commands set use gate model 1 Altera Corporation MegaCore Version 9 1 3 11 November 2009 RLDRAM II Controller MegaCore Function User Guide Simulate the Example Design source uariation name vsim tcle Simulating in Third Party Simulation Tools Using NativeLink You can perform a simulation in a third party simulation tool from within the Quartus II software using NativeLink a For more information on NativeLink refer to the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook To set up simulation in the Quartus II software using NativeLink follow these steps 1 Createa custom variation with an IP functional simulation model 2 Obtai
56. s menu The MegaWizard Plug In Manager dialog box displays s Refer to Quartus II Help for more information on how to use the MegaWizard Plug In Manager Specify that you want to create a new custom megafunction variation and click Next Expand the Interfaces Memory Controllers directory then click RLDRAM II Controller v9 1 Select the output file type for your design the wizard supports VHDL and Verilog HDL The MegaWizard Plug In Manager shows the project path that you specified in the New Project Wizard Append a variation name for the MegaCore function output files lt project path variation name gt Is The variation name must be a different name from the project name and the top level design entity name Click Next to launch IP Toolbench MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Getting Started Altera Corporation November 2009 Step 1 Parameterize To parameterize your MegaCore function follow these steps For more information on parameters refer to Parameters on page 2 28 1 2 Click Step 1 Parameterize in IP Toolbench Choose the memory type a Choose the memory device gt You can add your own memory devices to this list by editing the memory_types dat file in the constraints directory b Enter the clock speed c Choose the interface voltage d Choose the data bus width e Choose the DQ per DO
57. ser Guide Interfaces D For more details on how to run the simulation script see Simulate the Example Design on page 3 11 Constraints The constraints scripts set the following constraints Sets IO standards e 15or1 8 V HSTL voltage selection e Address and command HSTL Class I e Data CIO mode HSTL Class II e DataSIO mode HSTL Class I Sets output capacitance Places data pins as per selection in pin placement constraints floor plan Allows automatic placement for DOS and non DQS modes Places all DM pins Sets up correct output enable groups Sets rlidramii a 0 rldramii ba 0 rldramii cs n 0 rldramii ref n Oand rldrainii we n O as fast output registers see note 1 in Table 2 5 Sets r1dramii qk non global signal in DOS capture mode Add Hold Relationship and Setup Relationship to all I O ports Interfaces This section describes the following RLDRAM II commands Initialization Writes Reads Refreshes Initialization The control logic initializes the RLDRAM II devices During initialization the mode register is set and each bank is refreshed in turn IP Toolbench sets the following RLDRAM II initialization features On die termination ODT Impedance matching resistor DLL enable RLDRAM II configuration Figure 2 11 shows the initialization sequence 2 16 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description
58. serted asynchronously but must be deasserted synchronous to the rising edge of the address and command clock 2 24 MegaCore Version 9 1 RLDRAM II Controller MegaCore Function User Guide Altera Corporation November 2009 Functional Description Table 2 3 System Signals Part 3 of 3 Name reset read clk n Width Bits DQS mode the number of RLDRAM II devices attached to the memory interface Non DQS mode 1 Direction Description Reset input for logic on the capture clock domain In DQS mode the capture clock domain is capture clk innon DQS mode itis non_dqs_capture_clk In DQS mode each reset read clk n is associated with the corresponding capture clk clock domain The reset read clk n canbeasserted asynchronously but must be deasserted synchronous to the rising edge of the capture clock capture clk The number of RLDRAM II devices attached to memory interface Output Undelayed DQS clock used by capture circuitry to capture RLDRAM II read data There is one capture clk per attached RLDRAM II device DQS mode only Table 2 4 shows the local interface signals Table 2 4 Local Interface Signals Part 1 of 2 Width seas Name Bits Direction Description local addr Device dependant Input RLDRAM II address IP Toolbench refers to the memory dat file and selects the address width appropriate to the device local bank ad
59. sign Constraints SDC file Use this SDC file with the DDR timing wizard DTW generated SDC file when using TimeQuest You must copy the contents of this file into the DTW generated SDC file so the example design has the correct timing constraints when using TimeQuest altera vhdl support vhd A VHDL package that contains functions for the generated entities This file may be shared between MegaCore functions variation name example driver vhd or v Example driver top level name vhd or v Example design file add constraints for variation name gt tcl Add constraints script ridramii pll device name gt vhd or v System PLL ridramii fbpll device name gt vhd or v Fedback PLL variation name auk rldramii addr cmd reg vhd or v Address and command output registers variation name auk rldramii clk gen vhd or v Memory clock generator variation name auk rldramii controller ipfs wrapper vh dor v A file that instantiates the controller variation name auk rldramii controller ipfs wrapper vh o or VO VHDL or Verilog HDL IP functional simulation model variation name gt _auk_rldramii_datapath vhd or v Datapath Altera Corporation November 2009 MegaCore Version 9 1 3 9 RLDRAM II Controller MegaCore Function User Guide RLDRAM II Controller Walkthrough Table 3 1 Generated Files Part 202 Note 1 2
60. tion Version 9 1 Release Date November 2009 Ordering Code IP RLDRAMII Product ID OOAC Vendor ID 6AF7 For more information about this release refer to the MegaCore IP Library Release Notes and Errata Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release MegaCore functions provide either full or preliminary support for target Altera device families W Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs W Preliminary support means the MegaCore function meets all functional requirements but may still be undergoing timing analysis for the device family it may be used in production designs with caution MegaCore Version 9 1 1 1 Features Features General Description 1 2 Table 1 2 shows the level of support offered by the RLDRAM II Controller MegaCore function to each Altera device family Table 1 2 Device Family Support Device Family Support HardCopy II Preliminary Stratix II Full Stratix Il GX Full Other device families No support Common I O CIO and separate I O SIO device support Memory burst length 2 4 and 8 beat support
61. to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The angled arrow instructs you to press Enter The feet direct you to more information about a particular topic MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide
62. to the design Use dedicated PLL On or off B Turn on to use dedicated PLL outputs to generate the outputs clocks which is recommended for HardCopy II devices When turned off alt ddio outputs generate the clock outputs Number of clock pairs 1 to 8 The number of RLDRAM II clock output pairs generated in from FPGA to the datapath When you turn on Use dedicated clock memory outputs only values of 1 to 3 are valid 1 The default signal is signal 0 When you specify additional address and command busses both signal 0 and signal 1 are present 2 30 MegaCore Version 9 1 RLDRAM II Controller MegaCore Function User Guide Altera Corporation November 2009 Functional Description Timing Table 2 10 shows the pipeline options Table 2 10 Pipeline Options pipeline registers Parameter Range Description Number of address 0 1 20r 3 When you choose 1 2 or 3 the wizard inserts 1 2 or 3 pipeline and command and registers between the memory controller and the command and write data pipeline address output registers and the write data output registers These registers registers may help to achieve the required performance at higher frequencies Number of read data 0 1 20r 3 When you choose 1 2 or 3 the wizard inserts 1 2 or 3 pipeline registers between the read capture registers and the memory controller These registers may help to achieve the required performance at higher fr
63. trol cs n 1 Input Chip select signal control dm The number of Input The DM bus which has valid data in the same clock RLDRAM II devices cycles that control wdata validis asserted attached to the memory interface x 2 control doing wr 1 Input Control doing wr is asserted when the controller is writing to the RLDRAM II devices and controls the output enables on rldramii_dq or rldramii d control ref n 1 Input Refresh signal control wdata Data bus width x2 Input The write data bus which has valid data in the same clock cycles that control wdata validis asserted control wdata 1 Input Enables the write data bus and DM enable registers valid so that they are only updated when valid data and enables are available control we n 1 Input Write enable signal control qvild The number of Output The read data valid flag There is only one QVLD flag RLDRAM II devices per RLDRAM II device The control qvld attached to the signal is aligned with the valid cont xol rdata memory interface and is asserted during this period The control qvild signal has the same functionality as 1ocal rdata valid control rdata Data bus width x 2 Output The captured read data same as local rdata l Pa rameters The parameters can only be set in IP Toolbench see Step 1 Parameterize on page 3 5 2 28 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Functional Description Memory
64. tructure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist 5 Click OK Step 4 Generate To generate your MegaCore function click Step 4 Generate in IP Toolbench 3 8 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Getting Started Table 3 1 describes the generated files and other files that may be in your project directory The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL Table 3 1 Generated Files Part 1 of 2 Note 1 2 3 Filename variation name vhd or v Description A MegaCore function variation file which defines a VHDL or Verilog HDL description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus II software variation name gt cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name gt bsf Quartus Il symbol file for the MegaCore function variation You can use this file in the Quartus II block diagram editor variation name sdc A Synopsys De
65. ur overall project This walkthrough requires the following steps Create a New Quartus II Project on page 3 3 Launch IP Toolbench on page 3 4 MegaCore Version 9 1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide November 2009 Getting Started Step 1 Parameterize on page 3 5 Step 2 Constraints on page 3 7 Step 3 Set Up Simulation on page 3 8 Step 4 Generate on page 3 8 Create a New Quartus Il Project You need to create a new Quartus II project with the New Project Wizard which specifies the working directory for the project assigns the project name and designates the name of the top level design entity To create a new project follow these steps T Altera Corporation November 2009 Choose Programs Altera Quartus II version Windows Start menu to run the Quartus II software Alternatively you can use the Quartus II Web Edition software Choose New Project Wizard File menu Click Next in the New Project Wizard Introduction page the introduction page does not display if you turned it off previously In the New Project Wizard Directory Name Top Level Entity page enter the following information a Specify the working directory for your project For example this walkthrough uses the c Naltera projects Nrldram project directory b Specify the name of the project This walkthrough uses project for the project name 5 The Quartus II software auto
66. w Low See your Don t care Register RLDRAM data Set sheet Read READ Low High High Address Bank address Write WRITE Low Low High Address Bank address Auto AREF Low High Low Don t care Bank address Refresh Datapath Figure 2 2 on page 2 4 shows the datapath block diagram MegaCore Version 9 1 2 3 RLDRAM II Controller MegaCore Function User Guide Block Description Figure 2 2 Datapath Block Diagram Note 1 Datapath control a rldramii a O control ba Optional Pri P ridramii ba O control cs n Pipeline 3 ouai gt ridramii_cs_n_0 control_ref_n Registers R gt pe 9 rldramii ref n control we n eee P ridramii_we_n_ Memory __ ridramii_cik Clock E 9 ridramii clk n Generator h DM j rdramii dmi Group z DQS Group control dm 4 control doing wr ai i p ridramii dq control wdata PEINE aa rldramii_d Registers Logic control wdata valid 4 Optional control rdata Pipeline Read Registers Data p ridramii q Lodi hg ridramii qk capture clk amp Ogle non_dqs_capture_clk dqs delay ctrl Optional QVLD control qvid lt Pipeline 4 amp 7j Grau KK rldramii_qvid Registers p Note to Figure 2 2 1 The default signal is signal 0 When you specify additional address

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