IPUG88 - 2D Scaler IP Core User's Guide
Contents
1. 15 EMI ep cR 15 Filter Physical Characteristics rsisi diinon eer tree petas ene ev PE ER e HERE EXE BUR aea Aaaa 15 I O SPOCifiCationssssceiss 16 IMPIOMONtAlO g A A 17 Chapter 4 IP Core Gene rat e 18 Licensing the IP Core Em 18 e uli Gh Stee 18 Configuring the 2D Scaler IP Core in IPexpress sssssssssssssseseeeneeeeenen enne enne nennen nennen enne 18 IPexpress Created Files and Top Level Directory Structure 20 Instantiating Buren E 21 Running Functional Simulation seessesssssseseseeeeeee eene nenne nnne nnenen nns EE rennen nnn enne nennen 21 Synthesizing and Implementing the Core in a Top Level Design ssseesee 21 Hardware ATI m P 22 Enabling Hardware Evaluation in Diamond ssseeseenneneeeenn E eene nnne 22 Enabling Hardware Evaluation in ispLEVER sess nnne 22 Updating Regenerating the IP Core eene dienai aa nn rnns nennen inttr rents enters nnns 22 Regenerating an IP Core in Diamond sse eene nnne ener en nnne nnne nnns nennen nennen 22 Regenerating an IP Core in ispLEVER sssssssseseeeeeeeeneeeeeneneenenen enne nnn sennnn nnn nnn nente2. Configuring the 2D Scaler IP Core in IPexpress The 2D Scaler configuration GUI is accessed via the IPexpress tool and provides an interface for setting the desired parameters and invoking the IP core generator The start up IPexpress page allows the user to select the IP to be generated project directory user designated module name design entry type and target device The File Name will be used as the username in the core generation The 2D Scaler IP core is found under IP gt DSP as shown below 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUGS88 01 2 August 2013 18 2D Scaler IP Core User s Guide Sas LAT TICE EN SEMICONDUCTOR IP Core Generation Figure 4 1 IPexpress Dialog Box Diamond Version PERSEA Help ioixi I a amp S Bs Ba anvevice Famy z Version 2D Scaler 2 0 Macro Type User Configurable IP Version Bo IP Name 20 Scaler aa ProjectPath E test Browse a 2D FIR Filter 1 0 CORDIC 1 1 File Name scaler ra Color Space Converter 2 0 G DA FIR Filter 22 Module Output Verilog Deinterlacer 10 ooo jawxcs FIR Filter 42 Gh FIR Filter 5 0 Part Name LF
3. The Dynamic parameter updating checkbox determines whether the core supports dynamic scaling Refer to the Dynamic Parameter Updating on page 7 for more information Input frame width and Input frame height define the input video frame size for fixed scaling Output frame width and Output frame height define the output video frame size for fixed scaling When dynamic scaling is enabled the Max input frame width Max input frame height Max output frame width and Max output frame height specify the largest input and output frame sizes the core needs to support The range for the frame dimensions is 32 to 4096 for both fixed scaling and dynamic scaling Filter Physical Characteristics Kernel selects the scaling algorithm of the core Number of vertical filter taps represents the number of multipliers that may be used by the core for the vertical fil ter this number varies between 4 and 12 only for the Lanczos filter IPUGS88 01 2 August 2013 15 2D Scaler IP Core User s Guide E LATTICE Parameter Settings NEN SEMICONDUCTOR Number of horizontal filter taps represents the number of multipliers that may be used by the core for the hori zontal filter this number varies between 4 and 12 only for the Lanczos filter Number of vertical filter phases is a power of 2 number which provides the setting for the number of phases of the vertical filter and may vary between 16 and 512 Setting this number high increases the vertical coefficient
4. r bh fwidth out Sra d H gt fheight out din dvalid in frmsync in 2D Scaler dout enable ready IP Core Is 6 dout pelk gt gt dvalid_out uM id frmsync out pwdat paddr prdat lt Table 2 1 Primary I O Port Size y o Description Global Signals clk 1 l System clock rstn 1 l System asynchronous active low reset signal ce 1 l Active high clock enable optional sr 1 l Active high synchronous reset optional Video Input dvalid_in 1 Input valid frmsync_in 1 l Input frame sync signal indicating current input pixel is at row 0 column 0 din 8 48 l Pixel data in ready 1 O Core is ready for input Video Output dout_enable 1 Input from down stream module to enable output data active high dvalid_out 1 O Output valid frmsync_out 1 O Output frame sync signal indicating current output pixel is at row 0 column 0 dout 8 48 O Pixel data out fwidth_out 16 O Current output frame width optional only for dynamic mode fheight_out 16 O Current output frame height optional only for dynamic mode Parameter Bus optional pclk 1 l Parameter bus clock pwrite 1 l Parameter bus write enable active high paddr 5 Parameter bus address pwdat 8 16 32 Parameter bus write data prdat 8 16 32 O Parameter bus read data Interface Descriptions Video Input Output The 2D Scaler IP core uses a simple handshake to pass pixel
5. 2D Scaler IP Core User s Guide Appendix A Resource Utilization Sas LAT TICE EN SEMICONDUCTOR This appendix gives resource utilization information for Lattice FPGAs using the 2D Scaler IP core IPexpress is the Lattice IP configuration utility and is included as a standard feature of the Diamond and ispLEVER design tools Details regarding the use of IPexpress can be found in the IPexpress Diamond and ispLEVER online help sys tems For more information on the Diamond or ispLEVER design tools visit the Lattice web site at www latticesemi com software LatticeECP3 Devices Table A 1 Performance and Resource Utilization Examples Video Max Input Max Output Parallel Pixels Coefficient Format Frame Size Frame Size Processing Dynamic Taps Width Width Registers LUT4s Slices EBRs MULT9XQs fmax YCbCr422 720x480 1280x720 No No 4x4 8 9 955 1343 948 4 8 271 YCbCr422 1280x720 720x480 Yes No 4x4 8 9 1113 1338 996 7 16 246 RGB 1280x720 1920x1080 Yes Yes 4x4 8 9 1522 1829 1856 9 24 275 1 Performance and utilization data are generated targeting a LFE3 35EA 8FN484C device using Lattice Diamond 1 3 and Synplify Pro E 2011 03L software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family Ordering Part Number The Ordering Part Number OPN for the 2D
6. X 24 pwdat KW X iH KOWX OH X VF XHE X1 X prdat Ko MM XXX KK XOX 1 X 0 In Figure 2 11 IW is the input frame width and IH is input frame height OW and OH are the output frame width and height respectively VF is the vertical scaling factor and HF the horizontal scaling factor The parameter regis ters are writable only when UPDATE register is 0 When the UPDATE register bit is set to 1 the driving block should start the parameter updating at the next active frmsync in and reset the UPDATE register to O IPUGS88 01 2 August 2013 13 2D Scaler IP Core User s Guide zs LAT TICE EN SEMICONDUCTOR This section describes how to generate the 2D Scaler IP core using the IPexpress tool Refer to IP Core Gener Chapter 3 Parameter Settings ation on page 18 for a description of how to generate the IP The 2D Scaler configuration GUI is accessed via the IPexpress tool and provides an interface for setting the desired parameters and invoking the IP core generator Since the values of some parameters affect the size of the resultant core the maximum value for these parameters may be limited by the size of the target device Table pro vides a list of the user configurable parameters for the 2D Scaler IP core Table 3 1 2D Scaler IP Core Parameters Parameter Range Options Default Video Frame In and Out Video format Single color
7. Yes Yes 4x4 8 9 1515 1715 1362 9 24 238 Performance and utilization data are generated targeting a LFXP2 30E 7F484C device using Lattice Diamond 1 3 and Synplify Pro E 2011 03L software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family Ordering Part Number The Ordering Part Number OPN for the 2D Scaler IP core targeting LatticeXP2 devices is SCALER X2 U1 IPUGS88 01 2 August 2013 26 2D Scaler IP Core User s Guide
8. data into the core The core asserts its ready output when it is ready to receive data When the driving module has data to give the core it drives the core s dvalid_in port to a 1 synchronously with the rising edge of the clk signal providing the input pixel data on port din The IPUG88_01 2 August 2013 9 2D Scaler IP Core User s Guide E LAT TIC E Functional Description NN SEMICONDUCTOR frmsync in input should be driven to a 1 during the clock cycle when the first pixel of the first row in the incoming video frame is active Correspondingly dvalid out is active when valid output pixel data is available on dout and frmsync out marks the first pixel first row of the output video frame When the input signal dout enable is asserted the core will output video pixels When dout enable is de asserted the core stops generating output pixels after some pipeline delay The maximum pipeline delay is not greater than 26 clock cycles Parameter Register Read Write Interface The 2D Scaler IP core uses a simple register read write interface to update the input and output frame size control registers for dynamic scaling The parameter bus interface can be configured to run on a separate clock It oper ates at the input pixel clock by default When pwrite is high pwdat and padar should contain valid data The contents of all parameter registers will be transferred to the core s internal storage when UPDATE is asserted If a p
9. stor age Number of horizontal filter phases is a power of 2 number which provides the setting for the number of phases of the horizontal filter and may vary between 16 and 512 Setting this number high increases the horizontal coefficient storage I O Specification The I O Specification tab provides settings for pixel data and coefficient widths coefficient data type coefficient binary point and rounding mode Figure 3 2 I O Specification Tab Architecture 1 0 Specification Implementation Data width Input pixel width B i Coefficient width js w Output pixel width B vi Parameter Bus Parameter bus width 32 vi Separate parameter bus clock m Optional Ports Synchronous reset sr Clock enable ce Output frame size ports Precision Control Rounding mode Normal vi Input pixel width sets the bit width of the incoming pixel values and may vary between 8 and 16 inclusive Coefficients width sets the bit width of the coefficients and may vary between 6 and 18 inclusive Output pixel width sets the output pixel bit width and may vary between 8 and 16 inclusive Parameter bus width sets the bus width of the parameter register s read write interface This parameter is only available when dynamic parameter updating is selected The Separate parameter bus clock checkbox determines whether the core uses a separate clock to run the parameter bus interface Th
10. 0 720x480 Yes No 4x4 8 9 1116 1267 991 7 16 263 RGB 1280x720 1920x1080 Yes Yes 4x4 8 9 1515 1715 1362 9 24 269 1 Performance and utilization data are generated targeting a LFE2 20E 7F484C device using Lattice Diamond 1 3 and Synplify Pro E 2011 03L software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 and LatticeECP2S family 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUG88_01 2 August 2013 25 2D Scaler IP Core User s Guide E LAT TIC E Resource Utilization E SEMICONDUCTOR Ordering Part Number The Ordering Part Number OPN for the 2D Scaler IP core targeting LatticeECP2 and LatticeECP2S devices is SCALER P2 U1 LatticeXP2 Devices Table A 4 Performance and Resource Utilization Examples Video Max Input Max Output Parallel Pixels Coefficient Format Frame Size Frame Size Processing Dynamic Taps Width Width Registers LUT4s Slices EBRs MULT9X9s fmax YCbCr422 720x480 1280x720 No No 4x4 8 9 953 1278 936 4 8 220 YCbCr422 1280x720 720x480 Yes No 4x4 8 9 1116 1267 991 7 16 233 RGB 1280x720 1920x1080
11. Core Supported LatticeECP2 LatticeECP2S LatticexP2 i alin eis Device FE 6E LFE3 17EA LFEZ 6E LFE3 17EA LFE2 12E LFE3 17EA Targeted Device LFE2 20E LFE3 17EA LFE2 20E LFE3 17EA LFE2 20E LFE3 17EA 7F484C 8FN484C 7F484C 8FN484C 7F484C 8FN484C Taps 4x4 4x4 4x4 Pixel width 8 8 8 Resource Coefficient width 9 9 9 Utilization TRagisters 953 955 1116 1113 1515 1522 LUTs 1278 1343 1267 1338 1715 1829 EBRs 4 4 7 7 9 9 MULT9x9 8 8 16 16 24 24 pu E Lattice Diamond 1 3 or ispLEVER 8 1 SE o9 Synthesis Synopsys Synplify Pro for Lattice E 2011 03L Simulation Aldec Active HDL 8 2 Lattice Edition Mentor Graphics ModelSim SE 6 3F Features Supports single color YCbCr 4 2 2 YCbCr 4 4 4 and RGB video formats e Supports serial and parallel processing Dynamic parameter updating Supports multi scaling algorithms Configurable pixel data width Configurable coefficient width Configurable number of filter taps for Lanczos coefficient set Configurable number of phases for Bicubic Mitchell and Lanczos coefficient sets Configurable parameter bus width and separate parameter bus clock 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to chan
12. E3 35EA SFN484C G Gamma Corrector 12 m Bw S E amp Processors Controllers and Peripherals Synthesis SynpfyPro m Customize Important Note File Name cannot be scaler core as this name has been used in the internal design of the core Note that if the IPexpress tool is called from within an existing project Project Path Module Output Design Entry in ispLEVER Device Family and Part Name default to the specified project parameters Refer to the IPexpress tool online help for further information To create a custom configuration the user clicks the Customize button in the IPexpress tool dialog box to display the 2D Scaler IP core configuration GUI as shown in Figure 4 2 From this dialog box the user can select the IP parameter options specific to their application Refer to Parameter Settings on page 14 for more information on the 2D Scaler IP core parameter settings Figure 4 2 Configuration GUI Diamond Version 2D Scaler v2 0 EJ Lattice IP Core Configuration Generate Log 2D Scaler Frame Dimensions Architecture 1 0 Specification Implementation stn iftmsync in dvalid_in P din 15 0 ready dout_enable frmsync_out dvalid out dout 15 0 Video format fYCbCr4 2 2 vi IV Parallel processing Dynamic parameter updating Input frame width 720 32 4096 Output fr
13. Scaler IP core targeting LatticeECP3 devices is SCALER E3 U1 LatticeECP2M and LatticeECP2MS Devices Table A 2 Performance and Resource Utilization Examples Video Max Input Max Output Parallel Pixels Coefficient Format Frame Size Frame Size Processing Dynamic Taps Width Width Registers LUT4s Slices EBRs MULT9X9Ss fmax YCbCr422 720x480 1280x720 No No 4x4 8 9 953 1278 936 4 8 249 YCbCr422 1280x720 720x480 Yes No 4x4 8 9 1116 1267 991 7 16 262 RGB 1280x720 1920x1080 Yes Yes 4x4 8 9 1515 1715 1362 9 24 268 1 Performance and utilization data are generated targeting a LFE2M20E 7F484C device using Lattice Diamond 1 3 and Synplify Pro E 2011 03L software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M and LatticeECP2MS family Ordering Part Number The Ordering Part Number OPN for the 2D Scaler IP core targeting LatticeECP2M S devices is SCALER PM U1 LatticeECP2 and LatticeECP2S Devices Table A 3 PPerformance and Resource Utilization Examples Video Max Input Max Output Parallel Pixels Coefficient Format Frame Size Frame Size Processing Dynamic Taps Width Width Registers LUT4s Slices EBRs MULT9XQs fmax YCbCr422 720x480 1280x720 No No 4x4 8 9 955 1278 936 4 8 248 YCbCr422 1280x72
14. YCbCr4 2 2 YcbCr4 4 4 or RGB YCbCr4 2 2 Max Input frame width 32 4096 720 Max Input frame height 32 4096 576 Max Output frame width 32 4096 1280 Max Output frame height 32 4096 720 Parallel processing Yes No Yes Dynamic parameter updating Yes or No No Filter Specification Kernel Nearest Bilinear Bicibuc Mitchell Lanczos Lanczos Number of vertical filter taps 4 12 for Lanczos only 4 Number of horizontal filter taps 4 12 for Lanczos only 4 Number of vertical filter phases for oer yc zat pd os 64 Number of horizontal filter phases for Nha EA aes os 64 I O Specifications Input pixel bit width 8 16 8 Coefficient bit width 6 16 9 Output pixel bit width 8 16 8 Parameter bus bit width 8 16 32 32 Separate parameter bus clock Yes No No Optional Ports Synchronous reset Yes or No No Clock enable Yes or No No Output frame size ports Yes No No Precision Control Rounding mode Truncation Normal Convergent Normal Memory Type Line buffer type EBR Distributed EBR Vertical coefficient memory type EBR Distributed Distributed Horizontal coefficient memory type EBR Distributed Distributed Share vertical and horizontal coefficient memories Yes or No No Synthesis Options Frequency constraint MHz 1 400 250 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered tradema
15. aler IP Core User s Guide E LATTICE Table of Contents NN SEMICONDUCTOR LatticeECP2 and batticeECP25S DeVICeS iret rre vnda d pra n dc aca ee a C VER Ve Re e O vera ara e gs 25 Ordering Part Pus m a 26 LatticeXP2 D6viC6S8 uice etie eee rose eve de ca Rr a CX vacca Fe da re a Tod ex e vea eR RR EE ER ARE AR EE pu Eo E FEX IRE Edid Ud 26 Ordering Part NUMDE Nosis 26 IPUG88_01 2 August 2013 3 2D Scaler IP Core User s Guide zz LAT TICE E SEMICONDUCTOR Chapter 1 Introduction The 2D Scaler IP core converts input video frames of one size to output video frames of a different size Its flexible architecture supports a wide variety of scaling algorithms The highly configurable design takes advantage of the embedded DSP blocks available in Lattice FPGAs A simple I O handshake makes the core suitable for either streaming video or bursty input video data In system input and output frame sizes updating is possible on a frame basis Quick Facts Table 1 1 gives quick facts about the 2D Scaler IP core Table 1 1 2D Scaler IP Core Quick Facts 2D Scaler IP Core Configuration 480P to 720P 720P to 480P 720P to 1080P YCbCr4 2 2 serial YCbCr4 2 2 parallel RGB parallel dynamic FPGA Families LatticeECP3 LatticeECP2M LatticeECP2MS
16. ame specified in the IPexpress tool Table 4 1 File List File Description username lpc This file contains the IPexpress tool options used to recreate or modify the core in the IPexpress tool The IPX file holds references to all of the elements of an IP or module after it is generated from the IPex press tool Diamond version only The file is used to bring in the appropriate files during the design implementation and analysis It is also used to re load parameter settings into the IP module generation GUI when an IP module is being re generated username ipx username ngo This file provides the synthesized IP core username bb v This file provides the synthesis black box for the user s synthesis username instv This file provides an instance template for the 2D Scaler IP core username beh v This file provides the front end simulation library for the 2D Scaler IP core Table 4 2 provides a list of additional key files that provide IP core generation status information and command line generation capability that are generated in the user s project directory IPUGS88 01 2 August 2013 20 2D Scaler IP Core User s Guide E LATTICE IP Core Generation EE SEMICONDUCTOR Table 4 2 Additional Files File Description This file is created when the GUI Generate button is pushed This file may be run from the com mand line username generate tcl username generat
17. ame width 1280 32 4096 Input frame height 576 32 4096 Output frame height 720 32 4096 L y Filter Physical Characteristics L Kernel Lanczos Yi m Number of vertical filter taps 4 xl Number of vertical filter phases e4 vi Number of horizontal filter taps 4 i Number of horizontal filter phases ea vi IPUGS88 01 2 August 2013 19 2D Scaler IP Core User s Guide E LATTICE IP Core Generation NEN SEMICONDUCTOR IPexpress Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box the IP core and supporting files are generated in the specified Project Path directory The directory structure of the generated files is shown in Figure 4 3 This example shows the directory structure generated with the 2D Scaler for LatticeECP3 device Figure 4 3 2D Scaler IP Core Directory Structure test d scaler eval E a scaler E Jb impl di precision J synpiify Ej sim E d aldec X rti X scripts X timing E modelsim X rti scripts Bb timing E di src E beh rt mY ecp3 i params E M rti E a top di ecp3 M testbench Table 4 1 provides a list of key files and directories created by the IPexpress tool and how they are used The IPex press tool creates several files that are used throughout the design cycle The names of most of the created files are customized to the user s module n
18. arallel Scaling 8 bit pixel clk dvalid_in i frmsync_in din 23 16 din 15 8 din 7 0 dvalid out ff frmsync_out ff dout 23 16 KRXRXRXRXRXRX X dout 15 8 XGXGKGKGXGKGK X dout 7 0 KBXBXB8XBXBXBX X For YCbCr 4 2 2 video serial scaling the input and output sequence should be Cb Y Cr Y For parallel scaling the Y plane occupies the upper bits of the din and dout ports and the Cb and Cr planes occupy the lower bits Cb and Cr planes are interleaved in the lower half and Cb comes before Cr Figures 2 8 and 2 9 show the timing of YCbCr 4 2 2 serial scaling and parallel scaling IPUGS88 01 2 August 2013 11 2D Scaler IP Core User s Guide E LAT TIC E Functional Description NEN SEMICONDUCTOR Figure 2 8 YCbCr 4 2 2 Serial Scaling cik L ready 1j IEEE TT dvalid in Pe ee i a frmsync_in N din X Cb X Y X Cr X Y X CbX Y X X CbX Y XCXYX X X X Xeox v X Cr dout_enable dvalid_out Jj V T TL V SG frmsync ou
19. arameter has not been written to before the assertion of UPDATE its old value will be transferred into the internal storage The prdat contains the register read data corresponding to the address value on the padar in the previous clock cycle When parameter bus data width equals 32 paddi 1 0 should be fixed to 0 When parameter bus data width equals to 16 paddr 0 should be fixed to O The parameter bus data width is determined by the system CPU data width Control Signals and Timing Line and Frame Flushing The 2D Scaler IP core can accept pixels line by line and output the pixels line by line There are several clock cycles required at the end of every line for the core to flush the current output line Figure 2 4 shows the line flush ing cycles The core cannot accept new input pixels during this time and will pull its ready output signal low Figure 2 4 Timing Diagram for Line Flushing Cycles ck LI ready 1 RU LIE uw T dvalid_in LU J frmsync in din XPooXPo1 XPo2XPosXPo4YPo5X X X POn HPOn BPOn K X X X XP10XP11XP12X__ y y dvalid out T 7 frmsync_out JJ dout POO P01 P02 P03 Similarly there is a frame flushing period at the end of each input frame for the core to complete the current output frame The number of clock cycles required
20. bus can be configured to run on a separate clock By default the parameter bus runs on the input pixel sample clock When processing YCbCr 4 2 2 video format the core averages neighboring pixels Cb and Cr vectors to construct YCbCr 4 4 4 format for scaling 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUGS88 01 2 August 2013 6 2D Scaler IP Core User s Guide E LAT TIC E Functional Description NEN SEMICONDUCTOR Algorithm and Supported Filter Kernels Video scaling is a process of generating pixels that do not exist in the original image In order to compute an output pixel from a set of fixed input pixels it is necessary to map the output pixel to the input pixel grid and estimate the location of the output pixel relative to the input pixels The algorithm approximates the output pixel value by using a filter with coefficients weighted accordingly A 4 tap Bicubic filter uses four adjacent input pixels to interpolate an output pixel for example The spaces between the adjacent pixels are divided into a configurable number of positions called phases so that the output pixel is mapped into one of these positions The weights of the coefficients are determin
21. e horizontal coefficient memory The Share vertical and horizontal coefficient memories checkbox determines whether the core uses one memory for both the vertical and horizontal coefficients This option is only available when both the vertical and horizontal coefficient memories are set as the EBR type Frequency constraint sets the required clock frequency in MHz This option is active for all the clock domains in the core Fanout limit sets the fanout limit value for the synthesis tool Resource sharing and pipelining and reti ming if enabled are synthesis directives that are used in the core generation Users can adjust these options to get a better timing result IPUGS88 01 2 August 2013 17 2D Scaler IP Core User s Guide Chapter 4 zes LAT TICE IP Core Generation This section provides information on how to generate the 2D Scaler IP core using the Diamond or ispLEVER IPex press tool and how to include the core in a top level design Licensing the IP Core An IP core and device specific license is required to enable full unrestricted use of the 2D Scaler IP core in a com plete top level design Instructions on how to obtain licenses for Lattice IP cores are given at www lattice semi com products intellectualproperty aboutip isplevercoreonlinepurchas cfm Users may download and generate the 2D Scaler IP core and fully evaluate the core through functional simulation and implementation synthesis map place and route with
22. e is the maximum input frame height specified on the IP GUI minus 1 The default value is the maximum value 0x0008 OUTWIDTH 32 R W Output frame width register The OUTWIDTH must be the output frame width minus 1 The minimum value is 31 and the maximum value is the maximum output frame width specified on the IP GUI minus 1 The default value is the maximum value Output frame width must be an even number for YCbCr4 2 2 format i e OUTWIDTH must be odd 0x000C OUTHEIGHT 32 R W Output frame height register The OUTHEIGHT must be the output frame height minus 1 The minimum value is 31 and the maximum value is the maximum output frame height specified on the IP GUI minus 1 The default value is the maximum value IPUGS88 01 2 August 2013 7 2D Scaler IP Core User s Guide E LAT TIC E Functional Description EE SEMICONDUCTOR Address Registers Size R W Description 0x0010 VSFACTOR 32 R W Vertical scaling factor register VSFACTOR FRMHEIGHT 1 1 lt lt VFCBPWIDTH OUTHEIGHT 1 Where VFCBPWIDTH is the maximum value of log2 maximum output frame height and log2 number of vertical filter phases 0x0014 HSFACTOR 32 R W Horizontal scaling factor register HSFACTOR FRMWIDTH 1 1 lt lt HFCBPWIDTH OUTWIDTH 1 Where HFCBPWIDTH is the maximum value of log2 maximum output frame width and log2 number of the horizontal filter phases 0x0018 UPDATE 32 R W Update param
23. e og This is the synthesis and map log file username gen log This is the IPexpress IP generation log file Instantiating the Core The generated 2D Scaler IP core package includes black box lt username gt _bb v and instance user name gt _inst v templates that can be used to instantiate the core in a top level design An example RTL top level reference source file that can be used as an instantiation template for the IP core is provided in lt project_dir gt scaler_eval lt username gt src rtl top Users may also use this top level reference as the starting tem plate for the top level of their complete design Running Functional Simulation Simulation support for the 2D Scaler IP core is provided for the Aldec Active HDL Verilog and VHDL simulator and the Mentor Graphics ModelSim simulator The functional simulation includes a configuration specific behav ioral model of the 2D Scaler IP core The test bench sources stimulus to the core and monitors output from the core The generated IP core package includes the configuration specific behavior model lt username gt _beh v for functional simulation in the Project Path root directory The simulation scripts supporting ModelSim evaluation sim ulation is provided in lt project_dir gt scaler_eval lt username gt sim modelsim scripts The simulation script support ing Aldec evaluation simulation is provided in lt project_dir gt scaler_eval lt username gt sim a
24. ed by the positions or phases and how close they are to the output pixel The higher the number of phases the more accurate is the interpolated out put pixel Figure 2 2 Scaling Process with 4 Tap Bicubic Filter Pa Ph Dst Ph Ph 2 Dst P coeff 1 v Ph coeff v P 1 coeff 1 v Pu coeff 2 v Source Pixel sk Destination Pixel The 2D Scaler IP core supports five adaptive scaling kernels 1 tap nearest neighbor 2 tap bilinear 4 tap bicubic 4 tap Mitchell and configurable multi tap Lanczos filters The range for the size of the Lanczos filters is from 4 taps to 12 taps Filter coefficients are generated at compile time when the kernel is configured Dynamic Parameter Updating The 2D Scaler IP core supports in system input and output frame sizes updating via a register read write interface called parameter ports The parameter registers are listed below Address Registers Size R W Description 0x0000 FRMWIDTH 32 R W Input frame width register The FRMWIDTH value must be the input frame width minus 1 The minimum value is 31 and the maximum value is the maximum input frame width specified on the IP GUI minus 1 The default value is the maximum value Input frame width must be an even number for YCbCr4 2 2 for mat i e FRMWIDTH must be odd 0x0004 FRMHEIGHT 32 R W Input frame height register The FRMHEIGHT must be the input frame height minus 1 The minimum value is 31 and the maximum valu
25. equals number of vertical filter taps 2 input frame width line flushing cycle Figure 2 5 shows the frame flushing cycle IPUGS88 01 2 August 2013 10 2D Scaler IP Core User s Guide E LAT TIC E Functional Description NN SEMICONDUCTOR Figure 2 5 Timing Diagram of Frame Flushing Cycles rad ih D a a T T T T T4 dvalid in line iine tine X L tine Tine Tine T TT frmsync_in din KX to X t X12 XLS X X Xln 3XLn 2XLn 1X_ X K LOX LI XL XLX X X X E TT T T LLLI TT TT frmsync out 1I dout XLo KX tt Xt2X i3 X X X XLn BXiLn 2XLn 1X X KX LOX LIK L2XL3X X Video Input Output Timing The 2D Scaler IP core supports single color YCbCr 4 2 2 YCbCr 4 4 4 and RGB video formats For YCbCr 4 4 4 or RGB video formats the three planes are interleaved for serial scaling and combined on the din and dout ports for parallel scaling Figures 2 6 and 2 7 show the timing of RGB serial scaling and parallel scaling Figure 2 6 RGB Serial Scaling clk i ready F1 ae eee ee L dvalid_in frmsync_in din X RXGXBXRXGXBX X X XRXGXBX X X X XR GYXB dout enable dvalid out E 1 frmsync out 1J dout XRXeXBXRXexX8BX x Figure 2 7 RGB P
26. eter enable register When the writing of the parameter registers is complete users should set this register to 1 to enable the parameter s status The default value is 0 When the core updates the new parameters it re sets this reg ister to 0 The parameter registers can be written to only when the UPDATE register bit is 0 When the UPDATE bit is set to 1 the six parameters inside the core are updated with the new values when the frmsync_in signal is active indicating a new input frame is arriving After updating its internal parameters the core resets the UPDATE bit to 0 to indicate that the parameter registers are now empty and can take on new values When dynamic parameter updating is enabled the user needs to configure the largest input and output frame sizes the system expects to handle This is so that the line buffer and various counters within the core can be configured properly The core uses the default values for the input and output frame sizes to start until the driving block updates the parameters in the subsequent frames The default values are the maximum input frame size and the maximum output frame size For most cases VFCBPWIDTH equals to log2 output frame height for fixed scaler and log2 maximum output frame height for dynamic scaler HECBPWIDTH equals to log2 output frame width for fixed scaler and log2 max imum output frame width for dynamic scaler When the number of vertical phases is greater tha
27. fficient set Block Diagram The high level architecture of the 2D Scaler IP core is shown in Figure 2 1 Figure 2 1 2D Scaler IP Core Block Diagram Pixels In Pixels Out Line Vertical Horizontal Buffer Filter m Filter ERN The 2D Scaler IP core allows different scaling factors for the horizontal and vertical dimensions It uses a separable filter architecture which as depicted by the block diagram performs the vertical and horizontal scaling in two steps The input pixel data is first stored in the line buffer The size of the line buffer is dictated by the number of the verti cal filter taps and the maximum input frame width Pixel data are read out of the line buffer and passed to the verti cal filter column by column Likewise the vertical filter coefficients are read out of the coefficient memories and passed to the vertical filter for processing along with the pixel data The row outputs from the vertical filter are then passed to the horizontal filter to generate the output pixels Output precision control is then performed on the final output pixel value The 2D Scaler IP core supports in system re programming of the input and output frame sizes via a parameter bus If the IP core is configured for dynamic parameter updating then the maximum input and output frame resolutions need to be specified so that line buffer and various counters can be configured appropriately Also the parameter
28. ge the schematic diagram of the IP core changes to show the I O and the device resources the IP core will need 7 Click Generate 8 Click the Generate Log tab to check for warnings and error messages IPUGS88 01 2 August 2013 23 2D Scaler IP Core User s Guide Chapter 5 ie LAT TICE Support Resources Lattice Technical Support There are a number of ways to receive technical support as listed below E mail Support techsupport latticesemi com Local Support Contact your nearest Lattice sales office Internet www latticesemi com References HB1009 LatticeECP3 Family Handbook HB1003 LatticeECP2 M Family Handbook HB1002 LatticeXP2 Family Handbook Revision History Document IP Core Date Version Version Change Summary February 2011 01 0 1 0 Initial release October 2011 01 1 2 0 Updated to support 2D Scaler IP version 2 0 August 2013 01 2 02 1 Modified the title for the Resource Utilization tables Updated corporate logo Updated Lattice Technical Support information Updated References format 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUGS88 01 2 August 2013 24
29. ge without notice IPUG88_01 2 August 2013 4 2D Scaler IP Core User s Guide sm LAT TICE NN SEMICONDUCTOR Selectable memory type for line buffer and coefficient memories Option for sharing vertical and horizontal filter coefficient memories Release Information 2D Scaler IP Core version 2 0 last updated September 2 2011 IPUGB88 01 2 August 2013 5 Introduction 2D Scaler IP Core User s Guide Chapter 2 E LATTICE Functional Description Key Concepts Video scaling is the process of calculating values for the pixels in an output frame of dimensions Xout by Yout from the values of pixels in an input frame of dimensions Xin by Yin Scaling up by an integer multiple involves inserting new pixels between the original pixels in the input frame and calculating each new pixel value as a weighted sum of nearby original pixel values The number of original pixel values and their weights depends on the scaling algorithm employed In general including more original pixels in the calculation results in a higher quality result but requires more FPGA resources Conversely down scaling by an integer multiple involves dropping unneeded input pixels Typically the drop opera tion is preceded by a two dimensional low pass filter to avoid a jagged appearance in the output frame The low pass filtering operation is itself a weighted sum of nearby input pixels The set of weights is referred to as the filter kernel or coe
30. is parameter is only available when dynamic parameter updating is selected The Synchronous reset checkbox determines whether the core has a synchronous reset port The Clock enable checkbox determines whether the core has a clock enable port The Output frame size ports checkbox determines whether the core provides output frame size ports This parameter is only available when dynamic parameter updating is selected IPUGS88 01 2 August 2013 16 2D Scaler IP Core User s Guide E LATTICE Parameter Settings NN SEMICONDUCTOR Rounding mode selects between Truncation Normal away from zero and Convergent rounding Implementation The Implementation tab provides settings for the optional ports and synthesis constraints Figure 3 3 Implementation Tab Architecture 1 0 Specification Implementation Memory Type Line buffer type EBR Vertical coefficient memory type Distributed Horizontal coefficient memory type Distributed x Share vertical and horitantal coefficient memories M Synthesis Options Frequency constraint MHz 250 1 400 Fanout limit 100 1 200 v Resource sharing Pipelining and retiming The Line buffer type parameter selects EBR or Distributed RAM for the line buffer implementation Vertical coefficient memory type selects EBR or Distributed RAM for the vertical coefficient memory Horizontal coefficient memory type selects EBR or Distributed RAM for th
31. ldec scripts Both ModelSim and Active HDL simulation is supported via test bench files provided in lt project_dir gt scaler_eval test bench Models required for simulation are provided in the corresponding models folder Users may run the Active HDL evaluation simulation by doing the following 1 Open Active HDL 2 Under the Tools tab select Execute Macro 3 Browse to folder lt project_dir gt scaler_eval lt username gt sim aldec scripts and execute one of the do scripts shown Users may run the ModelSim evaluation simulation by doing the following 1 Open ModelSim 2 Under the File tab select Change Directory and choose the folder lt project_dir gt scaler_eval lt user name gt sim modelsim scripts 3 Under the Tools tab select Execute Macro and execute the ModelSim do script shown Note When the simulation is complete a pop up window will appear asking Are you sure you want to finish Choose No to analyze the results Choosing Yes closes ModelSim Synthesizing and Implementing the Core in a Top Level Design Synthesis support for the 2D Scaler IP core is provided for Mentor Graphics Precision RTL or Synopsys Synplify The 2D Scaler IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress Users may synthesize the core in their own top level design by instantiating the core in their top level as described previously and then synthesizing the entire design wi
32. n the maximum output frame height the VFCBPWIDTH equals to log2 number of the vertical filter phases When the number of horizontal phases is greater than the maximum output frame width the HFCBPWIDTH equals to log2 number of horizontal filter phases For the nearest neighbor and bilinear kernels when the VFCBPWIDTH is smaller than the vertical coefficient bit width its value should be replaced by the vertical coefficient bit width Similarly when the HFBPWIDTH is smaller than the horizontal coefficient bit width its value should be replaced by the horizontal coefficient bit width The values of VFCBPWIDTH and HFCBPWIDTH can be found in the generated parameter value file lt project_dir gt scaler_eval lt username gt rtl params params v Rounding The 2D Scaler IP core provides three types of rounding on the output pixel value This is set at compile time by the parameter Rounding Mode The values are Truncation discards all bits to the right of the output s least significant bit Normal rounds away from zero if the fractional part is exactly one half Convergent rounds to the nearest integer if the fractional part is exactly one half IPUGS88 01 2 August 2013 8 2D Scaler IP Core User s Guide zs LAT TICE NN SEMICONDUCTOR Functional Description Primary I O Figure 2 3 2D Scaler IP Core I O clk rsin ce gt
33. o support top level synthesis and imple mentation will be imported to the project 4 Select the device top level entry in the left hand GUI window 5 Implement the complete design via the standard ispLEVER GUI flow Hardware Evaluation The 2D Scaler IP core supports the Lattice IP hardware evaluation capability which makes it possible to create ver sions of the IP core that operate in hardware for a limited period of time approximately four hours without requiring the purchase of an IP license It may also be used to evaluate the core in hardware in user defined designs Enabling Hardware Evaluation in Diamond Choose Project Active Strategy Translate Design Settings The hardware evaluation capability may be enabled disabled in the Strategy dialog box It is enabled by default Enabling Hardware Evaluation in ispLEVER In the Processes for Current Source pane right click the Build Database process and choose Properties from the drop down menu The hardware evaluation capability may be enabled disabled in the Properties dialog box It is enabled by default Updating Regenerating the IP Core By regenerating an IP core with IPexpress you can modify any of its settings including device type design entry method and any of the options specific to the IP core Regenerating can be done to modify an existing IP core or to create a new but similar one Regenerating an IP Core in Diamond To regenerate an IP core in Diamond 1 In IPe
34. out an IP license The 2D Scaler IP core supports the Lattice IP hardware evaluation capability which makes it possible to create versions of the IP core which operate in hardware for a limited time approximately four hours without requiring an IP license See Hardware Evaluation on page 22 for further details However a license is required to enable timing simulation to open the design in the Diamond or ispLEVER EPIC tool and to generate bitstreams that do not include the hardware evaluation timeout limitation Getting Started The 2D Scaler IP core is available for download from the Lattice IP Server using the IPexpress tool The IP files are automatically installed using isp UPDATE technology in any user specified directory After the IP core has been installed the IP core will be available in the IPexpress GUI dialog box shown in Figure 4 1 To generate a specific IP core configuration the user specifies Project Path Path to the directory where the generated IP files will be located e File Name username designation given to the generated IP core and corresponding folders and files Diamond Module Output Verilog or VHDL e ispLEVER Design Entry Type Verilog HDL or VHDL Device Family Device family to which IP is to be targeted e g LatticeECP2M LatticeECP3 etc Only fami lies that support the particular IP core are listed Part Name Specific targeted part within the selected device family
35. rks of their respective holders The specifications and information herein are subject to change without notice IPUG88_01 2 August 2013 14 2D Scaler IP Core User s Guide E LATTICE Parameter Settings NN SEMICONDUCTOR Table 3 1 2D Scaler IP Core Parameters Continued Parameter Range Options Default Fanout limit 1 200 100 Resource sharing Yes No Yes Pipelining and retiming Yes No No Architecture The Architecture tab provides settings for video frames and algorithm options Figure 3 1 Architecture Tab Architecture 1 0 Specification Implementation Frame Dimensions Video format YCbCr4 2 2 i v Parallel processing Dynamic parameter updating Input frame width 720 32 4096 Output frame width 1280 32 4096 Input frame height 576 32 4096 Output frame height 720 32 4096 Filter Physical Characteristics Kerel Lanczos vi Number of vertical filter taps 4 vi Number of vertical filter phases 64 vi Number of horizontal filter taps 4 vi Number of horizontal filter phases 64 vi Frame Dimensions This section provides settings that define the number of color planes of the video stream input output frame dimen sions and in system dynamic parameter updating Video format defines the format of a video stream It can be single color YCbCr4 2 2 YCbCr4 4 4 or RGB The Parallel processing checkbox determines whether the core processes video streams in parallel
36. s entes nennen 23 Chapter 5 Support FESOUNC CS me 24 Lattice Technical Support cimi anie e di ct aa aa das eaten einen ies detrei 24 Online FOrUMS oases accra cares ce cathe gases cibi ree ceca RR aa aeaeaie reani TREE OSAA RAEO Oi AG ARAE OEE REET RESSA 24 Telephone Support Hotline cic its elven ne iid db eee Bini 24 EPMA SUP POM P 24 Local SUPPOM P dian nin itis asin ai eae eae 24 nip EX 24 izle p 24 alise T sect 24 Appendix A Resource Utilization Luisa insana entire suck Sacer ncs x REESE DE X aa SED SERENA XE Eu EE EIER 25 LattiCCEGPS DeVICES qs 25 Ordering Part N rber senna obrero tim iis anther eor Rd teres auctioned dy onc 25 LatticeECP2M and LatticeECP2MS Devices ssssssssssssseeeees nennen nnne nnne nnne nn renn nnne 25 Ordering Part N rmber eom c cet e Ea co TER eee ee Bet DRE ERR Roe eu ERR du eL RERO i el 25 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUGS88 01 2 August 2013 2 2D Sc
37. t 1 dout Xcbx v X CryX v Xeex v Xexv Figure 2 9 YCbCr 4 2 2 Parallel Scaling 8 bit pixel ck l l Pu dvalid_in H f frmsync_in din 15 8 KYXYXYXYXYXYX KN NYX Y X YXYX XX f y XY XY din 7 0 mu um dvalid out J frmsync_out 1 dout 15 8 XYXYXYXYXYXYX X dout 7 0 X Cb X Cr X Cb X Cr X Cb X CX X Figure 2 10 shows the dout_enable control timing When the dout_enable is de asserted the core will stop output ting data after the pipeline delay Similarly when the dout_enable is asserted the core will begin outputting data after a certain pipeline delay The asserting and de asserting of dout_enable can be used to generate horizontal blank and vertical blank depending on the output video format Figure 2 10 dout_enable Control Timing clk I Pipeline delay I Pipeline delay dout enable N JJ dvalid_out J J dout 2G cR CO DEN XRYX8YX8Y IPUGS88 01 2 August 2013 12 2D Scaler IP Core User s Guide E LAT TIC E Functional Description EE SEMICONDUCTOR Dynamic Parameter Updating Figure 2 11 Timing Diagram for Dynamic Parameter Updating parameter bus width 32 ek LTEPDR a PG i i ready jaa dvalid_in _ yp frmsync_in pwrite paddr X24X__X 0X 4 X 8 X 12 X 16 X 20 X 24
38. th either Synplify or Precision RTL synthesis The top level file username eval top v provided in lt project_dir gt scaler_eval lt username gt src top supports the ability to implement the 2D Scaler IP core in isolation Push button implementation of this top level design with IPUGS88 01 2 August 2013 21 2D Scaler IP Core User s Guide E LATTICE IP Core Generation EE SEMICONDUCTOR either Synplify or Precision RTL synthesis is supported via the project files username eval Idf Diamond or syn ispLEVER located in the lt project_dir gt scaler_eval lt username gt impl synplify and the lt project_dir gt scaler_eval lt username gt impl precision directories respectively To use this project file in Diamond 1 Choose File gt Open Project 2 Browse to lt project_dir gt scaler_eval lt username gt impl synplify or precision in the Open Project dialog box 3 Select and open lt username gt df At this point all of the files needed to support top level synthesis and imple mentation will be imported to the project 4 Select the Process tab in the left hand GUI window 5 Implement the complete design via the standard Diamond GUI flow To use this project file in ispLEVER 1 Choose File Open Project 2 Browse to lt project_dir gt scaler_eval lt username gt impl synplify or precision in the Open Project dialog box 3 Select and open username syn At this point all of the files needed t
39. tion synthesis and implementation The IP core may be included in a user s design by importing the ipx file to the associated Diamond project To change the option settings of a module or IP that is already in a design project double click the module s ipx file in the File List view This opens IPexpress and the module s dialog box showing the current option settings Then go to step 6 above Regenerating an IP Core in ispLEVER To regenerate an IP core in ispLEVER 1 In the IPexpress tool choose Tools gt Regenerate IP Module 2 Inthe Select a Parameter File dialog box choose the Lattice Parameter Configuration Ipc file of the IP core you wish to regenerate and click Open 3 The Select Target Core Version Design Entry and Device dialog box shows the current settings for the IP core in the Source Value box Make your new settings in the Target Value box 4 If you want to generate a new set of files in a new location set the location in the LPC Target File box The base of the Ipc file name will be the base of all the new file names The LPC Target File must end with an Ipc extension 5 Click Next The IP core s dialog box opens showing the current option settings 6 Inthe dialog box choose the desired options To get information about the options click Help Also check the About tab in the IPexpress tool for links to technical notes and user s guides The IP core may come with addi tional information As the options chan
40. xpress click the Regenerate button 2 Inthe Regenerate view of IPexpress choose the IPX source file of the module or IP you wish to regenerate IPUGS88 01 2 August 2013 22 2D Scaler IP Core User s Guide E LATTICE IP Core Generation NN SEMICONDUCTOR 3 IPexpress shows the current settings for the module or IP in the Source box Make your new settings in the Target box 4 f you want to generate a new set of files in a new location set the new location in the IPX Target File box The base of the file name will be the base of all the new file names The IPX Target File must end with an ipx exten sion 5 Click Regenerate The module s dialog box opens showing the current option settings 6 In the dialog box choose the desired options To get information about the options click Help Also check the About tab in IPexpress for links to technical notes and user s guides IP may come with additional information As the options change the schematic diagram of the module changes to show the I O and the device resources the module will need 7 To import the module into your project if it is not already there select Import IPX to Diamond Project not available in stand alone mode 8 Click Generate 9 Checkthe Generate Log tab to check for warnings and error messages 10 Click Close The IPexpress package file ipx supported by Diamond holds references to all of the elements of the generated IP core required to support simula
41. zas LATTICE E SEMICONDUCTOR LatticeCORE 2D Scaler IP Core User s Guide August 2013 IPUG88_01 2 fas LATTICE Table of Contents E SEMICONDUCTOR Chapter 1 Introduction mme t m 4 Quick Facts morskie 4 RESIT EAE A AE E EE A PEA N E E A E E E E E E rere eer 4 Release MnionnalOiecnen asinina a EE ENE EO EOE ER 5 Chapter 2 Functional Description meet 6 Key COMCE PIS iia 6 BIOCK Diagr aliested Dm 6 Algorithm and Supported Filter Kernels ssssssessssseseseseneeeen nennen nennen nnns enne snnt nnns nnns nennen en 7 Dynamic Parameter Updating eesse octo itae one eed reete diet par ea sd ax ERE a EY uet ANS ERR AE SERE reu od 7 alese Qome HH 8 inre 9 INntemace DESCKIPUOMS E 9 Video MPU OULD Ut e 9 Parameter Register Read Write Interface ssssssssssssssssseseeee eene nnne nennen nnne nnne 10 Control Signals and Timing teorie petri eee teen taut erato ea decay evades ed ae eee eate tection ene 10 Chapter 3 Parameter Settings eoe e unt ant ete xxt asus ches Cans n ARE Sects Rte ce Aes S RMA MARE RRASNE nnnm nennen 14 AI CIITG me
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