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Xilinx UG362 Virtex-6 FPGA Clocking Resources User Guide

1. XILINX DRDY Dynamic Reconfiguration Ready General Usage Description The dynamic reconfiguration ready output DRDY provides the response to the DEN signal for the MMCMs dynamic reconfiguration feature This signal indicates that a DEN DCLK operation has completed PSDONE Phase Shift Done The phase shift done output signal is synchronous to the PSCLK When the current phase shift operation is completed the PSDONE signal is asserted for one clock cycle indicating that a new phase shift cycle can be initiated MMOM Attributes Table 2 4 MMCM Attributes Attribute Type Allowed Values Default Description BANDWIDTH String HIGH OPTIMIZED Specifies the MMCM programming LOW algorithm affecting the jitter phase OPTIMIZED margin and other characteristics of the MMCM CLKOUT 1 6 DIVIDE Integer 1 to 128 1 Specifies the amount to divide the associated CLKOUT clock output if a CLKOUT O DIVIDE F Real 110 128 or 1 different frequency is desired This L 2 000 to 128 000 in number in combination with the increments of 0 125 or CLKEBOUT MULT F and integers DIVCLK DIVIDE values will determine the output frequency CLKOUT 0 6 PHASE Real 360 000 to 360 000 in 0 0 Allows specification of the output increments of phase relationship of the associated 1 56 the Fyco and or CLKOUT clock output in number of increments depending degrees offset i e 90 indicates a 90 or on CLKOUT DIVIDE cycle offset p
2. ug362 c1 25 011609 Figure 1 26 BUFR Driving Multiple Regions 32 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Regional Clocking Resources Horizontal Clock Buffer BUFH The horizontal clock buffer BUFH drives a horizontal global clock tree spine in a single region Figure 1 27 Each region has 12 BUFHs available Every BUFH has a clock enable pin CE that allows the clocks to be turned off dynamically BUFHs can be driven from the center out by e MMCM outputs in the same region e BUFG outputs e Local interconnect e Clock capable I Os from either the left or right inner column banks that are adjacent to the horizontal clocking region BUFH BUFHCE CE ug362 ci 26 040209 Figure 1 27 BUFH and BUFHCE Primitives Table 1 9 BUFH and BUFHCE Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port CE Input 1 Output clock enable port I Input 1 Clock input port To use the BUFH the logic must fit into the two regions adjacent to each other left and right as illustrated in Figure 1 28 The clock enable pin can completely turn off the clocks thus realizing potential power savings The power consumption in a BUFH has lower power consumption when compared to a BUFG driving two adjacent regions with lower jitter and higher performance Clocking Resources www xilinx com 33 UG362 v1 6 January 17 2011 34 Chapter 1 Clocking
3. Guide Contents 0 ccc cee cece eee hh he 7 Additional Documentation 0 0 ccc cece cee eee een eee eeneeee 7 Additional Support Resources eee 8 Chapter 1 Clocking Resources Global Regional and I O Clocks sussueeesees eese 9 Global COCKS cscs 4 aes a eco oreet Eo Pa eco duse ded ac ete e ee enti bees 9 Regional Clocks and I O Clocks 00 ccc cece 9 Clocking Architecture cociecec y tanta de dale wide eed edict dee e d eens 10 Global Clocking Resources 11 Global Clock Inputs eese RE RE EISE LLLI Cr S E IA eee ee ede 12 Global Clock Input Buffer Primitives csse e 12 Clock Gating for Power Savings 0 0 6 6 cece en 12 Global Clock Buffers 2 0 0 0 0 ccc ee RR I ne 12 Global Clock Buffer Primitives 2 2 2 2 2 000 ccc ccc eee eee eee nee 14 Additional Use Models 0 0c ee ehh hh has 22 Clock Tree and Nets GCLK 1 0 0 0 ccc cence ence tenn en eee 24 Glock R gions 5 m9 ek Re cigs e n RP RER4EY ERE ERE pe T LEN ers 24 Regional Clocking Resources uu sedere wie eee in Ice pep eol C ce d a A 26 Clock Capable T Qy sciat ke n RR rk RR er aa epu 26 I O Clock Buffer BUFIO seeseeeeee RR RR RR RR n 26 BUEIO Primitive joi i eua A rac bd ep Pug wc E d ace a ac deg 27 B EIO Use Models 4 eee ed rd coercet Wiad ae rsen a RR Ma Re tad 27 Regional Clock Buffer BUFR sssssssssese I 28 bD
4. 1 and BUFR DIVIDE BYPASS When set to 1 the delay is slightly more than BYPASS All other divisors have the same delay BUFR_DIVIDE 1 The phase relationship between the input clock and the output clock is the same for all possible divisions except BYPASS The timing relationship between the inputs and output of BUFR when using the BUFR DIVIDE attribute is illustrated in Figure 1 24 In this example the BUFR DIVIDE attribute is set to three Sometime before this diagram CLR was asserted CLR TBRCKO_O TBRDO_CLRO TBRCKO_O Leni c z gu Le See Ff 49362 c1 23 040209 Figure 1 24 BUFR Timing Diagrams with BUFR DIVIDE Values In Figure 1 24 e Before clock event 1 CE is asserted High e After CE is asserted and time TgrcKo o the output O begins toggling at the divide by three rate of the input I Tggcko o and other timing numbers are best found in the speed specification Note The duty cycle is not 50 50 for odd division The Low pulse is one cycle of I longer e At time event 2 CLR is asserted After Tgrpo crgo from time event 2 O stops toggling e Attime event 3 CLR is deasserted e At time Tgrcxo o after clock event 4 O begins toggling again at the divided by three rate of I www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Regional Clocking Resources BUFR Use Models BUFRs are ideal for source synchronous applications requiring clock domain crossing or
5. UG362 v1 6 January 17 2011 the same result for the VCO The MMCM clock source can come from several sources IBUFG Global clock input buffer the MMCM will compensate the delay of this path IBUFG represents a global clock pin or a clock capable clock pin in the same region BUFGCTRL or BUFG Internal global clock buffer the MMCM will not compensate the delay of this path IBUF Not recommended since the MMCM can not compensate for the delay of the general route An IBUF clock input must route to a BUFG before routing to a MMCM BUFR Regional clock input buffer the MMCM will not compensate the delay of this path GTX GTH These serial transceivers can directly connect to the MMCM in the same clocking region www xilinx com 53 Chapter 2 Mixed Mode Clock Manager Counter Control XILINX The MMCM output counters provide a wide variety of synthesized clocks using a combination of DIVIDE DUTY CYCLE and PHASE Figure 2 6 illustrates how the counter settings impact the counter output The top waveform represents the output from the VCO Counter Clock Input VCO DIVIDE 2 DUTY CYCLE 0 5 PHASE 0 DIVIDE 2 DUTY CYCLE 0 5 PHASE 180 DIVIDE 2 DUTY CYCLE 0 75 PHASE 180 DIVIDE 1 DUTY CYCLE 0 5 PHASE 0 DIVIDE 1 DUTY CYCLE 0 5 PHASE 360 DIVIDE 3 DUTY CYCLE 0 33 PHASE 0 DIVIDE 3 DUTY CYCLE 0 5 PHASE 0 JUUUUUUU EE LT LT I IE E Ep JLI LIL
6. all bits must be set to zero DWE Dynamic Reconfiguration Write Enable The dynamic reconfiguration write enable DWE input pin provides the write read enable control signal to write the DI data into or read the DO data from the DADDR address When not used it must be tied Low DEN Dynamic Reconfiguration Enable Strobe The dynamic reconfiguration enable strobe DEN provides the enable control signal to access the dynamic reconfiguration feature and enables all DRP port operations When the dynamic reconfiguration feature is not used DEN must be tied Low DCLK Dynamic Reconfiguration Reference Clock The DCLK signal is the reference clock for the dynamic reconfiguration port The rising edge of this signal is the timing reference for all other port signals The setup time is specified in the data sheet There is no hold time requirement for the other input signals relative to the rising edge of the DCLK The pin can be drive by an IBUF IBUFG BUFG BUFR or BUFH PSCLK Phase Shift Clock This input pin provides the source clock for the dynamic phase shift interface All other inputs are synchronous to the positive edge of this clock The pin can be drive by an IBUF IBUFG BUFG BUFR or BUFH www xilinx com 49 UG362 v1 6 January 17 2011 50 Chapter 2 Mixed Mode Clock Manager XILINX PSEN Phase Shift Enable A dynamic variable phase shift operation is initiated by synchronously asserting this signa
7. serial to parallel conversion Unlike BUFIOs BUFRs are capable of clocking logic resources in the FPGAs other than the IOBs Figure 1 25 is a BUFR design example Block DSP RAM Tile Block DSP RAM Tile 000 4 gt gt Clock Capable 10 ed um To Region Above mi 1 LL MN E 1 0 Tile 1 i 1 0 Tile 1 i VO Tile 4 3 Clock Capable I O p E T r g g g g g g g g o o o o o o o o To more FPGA logic To Region resources Below ug362 ci 24 040209 Figure 1 25 BUFR Driving Various Logic Resources Clocking Resources www xilinx com 31 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources XILINX Regional Clock Nets In addition to global clock trees and nets Virtex 6 devices contain regional clock nets These clock trees are also designed for low skew and low power operation Unused branches are disconnected The clock trees also manage the load fanout when all the logic resources are used Regional clock nets do not propagate throughout the whole Virtex 6 device Instead they are limited to only one clock region One clock region contains six independent regional clock nets To access regional clock nets BUFRs must be instantiated A BUFR can drive regional clocks in up to two adjacent clock regions Figure 1 26 BUFRs in the top or bottom region can only access one adjacent region below or above respectively BUFRs
8. ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Clocking Resources www xilinx com UG362 v1 6 January 17 2011 Revision History The following table shows the revision history for this document Date 06 24 09 Version 1 0 Revision Initial Xilinx release 09 16 09 1 1 Updated the About This Guide section in the Preface Made clarifying edits in various discussion in Chapter 2 including updating the description of CLKOUT4_CASCADE Added Virtex 6 HXT devices to Table 1 5 page 25 Added note 1 to Table 2 3 page 47 Revised the COMPENSATION attribute description and added Note 1 to Table 2 4 01 19 10 1 2 Updated I O Clock Buffer BUFIO Changed Regional Clock Buffer BUFR Clarified Horizontal Clock Buffer BUFH Removed CLKFBOUT fractional divide fractional M counter capability from Chapter 2 Mixed Mode Clock Manager These changes include updating Figure 2 2 revising the allowed values for CLKFBOUT_MULT_F in Table 2 2 and revising the description for CLKFBOUT USE FINE PS Clarified Equation 2 6 and Equation 2 7 Updated CLKINSEL Clock Input Select Updated Zero Delay Buffer page 58 description 03 15 10 1 3
9. BUFGCE output can drive distinct regions of logic For example if all the logic that is required to always be operating is constrained to a few clocking regions then the BUFGCE output can drive those regions Toggling the enable of the BUFGCE provides a simple means of stopping all dynamic power consumption in the logic regions available for power savings The Xilinx Power Estimator XPE or the Xilinx Power Analyzer XPower tools are used to estimate power savings The difference is calculated by setting the frequency on the corresponding clock net to 0 MHz or providing the appropriate stimulus data to the tool Global Clock Buffers There are 32 global clock buffers in every Virtex 6 device A global clock input can directly connect from the P side of the differential input pin pair to any global clock buffer input There are eight global clock pin inputs The top bottom half rules from previous Virtex architectures no longer apply Each differential global clock pin pair can connect to either a differential or single ended clock on the PCB If using a single ended clock then the P side of the pin pair must be used because a direct connection only exists on this pin For pin naming conventions please refer to the Virtex 6 FPGA Packaging and Pinout Specification If a single ended clock is connected to the P side of a differential pin pair then the N side can not be used as another single ended clock pin However it can be used as a user I O
10. DI 15 0 Input When not used all bits must be set to zero See DI 15 0 Dynamic Reconfiguration Data Input The dynamic reconfiguration write enable DWE input pin provides the write DWE Input enable control signal to write the DI data into the DADDR address When not used it must be tied Low See DWE Dynamic Reconfiguration Write Enable The dynamic reconfiguration enable DEN provides the enable control signal to DEN Input 4855 the dynamic reconfiguration feature When the dynamic reconfiguration P feature is not used DEN must be tied Low See DEN Dynamic Reconfiguration Enable Strobe DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port See P DCLK Dynamic Reconfiguration Reference Clock PSCLK Input Phase shift clock See PSCLK Phase Shift Clock PSEN Input Phase shift enable See PSEN Phase Shift Enable PSINCDEC Tpit Phase shift increment decrement control See PSINCDEC Phase Shift Increment Decrement Control User configurable clock outputs 0 through 6 that can be divided versions of the VCO phase outputs user controllable from 1 bypassed to 128 The output clocks ed ad Cupar are phase aligned to each other unless phase shifted and aligned to the input clock with a proper feedback configuration See CLKOUTT 0 6 Output Clocks CLKOUTY 0 3 B Output Inverted CLKOUT 0 3 See CLKOUT 0 3 B Inverted Output Clocks CLKEBOUT Output Dedicated MMCM feedback output See CLKFBOU
11. MMCMs in the top half of the device can only drive the BUFGs in the top half of the device and MMCMs in bottom half can only drive BUFGs in the bottom half Similarly only BUFGs in the same half of the device can be used as feedback to the MMCMs in the same half of the device www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Clocking Resources Global Clocking Resources Global clock buffers allow various clock signal sources to access the global clock trees and nets The possible sources for input to the global clock buffers include e Global clock inputs e Clock capable inputs in the same region of the inner I O columns e Clock Management Tile CMT consisting of mixed mode clock managers two MMCMs per CMT driving BUFGs in the same half of the device e Other global clock buffer outputs BUFGs e General interconnect e Regional clock buffers BUFRs e Gigabit transceivers The Virtex 6 FPGA clock capable inputs can drive global clock buffers indirectly through the vertical clock network that exists in the MMCM column The 32 BUFGs are organized into two groups of 16 BUFGs in the top and bottom of the device Any resources e g GTX transceivers connecting to the BUFGs directly have a top bottom limitation For example each MMCM in the top can only drive the 16 BUFGs residing in that top of the device Similarly the MMCMs in the bottom drive the 16 BUFGs in the bottom All global clock buffers
12. also be used for stand alone frequency synthesis In this application the MMCM is not used to deskew a clock network but rather generate an output clock frequency for other blocks In this mode the MMCM feedback paths will be internal since it keeps all the routing local and should minimize the jitter Figure 2 4 shows the MMCM configured as a frequency synthesizer In this example an external 33 MHz reference clock is available The reference clock can be a crystal oscillator or the output of another MMCM Setting the M counter to 16 makes the VCO oscillate at 533 MHz 33 333 MHz x 16 The six MMCM outputs are programmed to provide for example a 533 MHz processor clock a 266 MHz gasket clock a 178 MHz clock a 133 MHz memory interface clock a 66 MHz PCI clock and a 33 MHz PCI clock In this example there are no required phase relationships www xilinx com 41 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX between the reference clock and the output clocks but there are required relationships between the output clocks 33 MHz Reference _ gt Processor Clock D0 2 Gasket M 16 D0 3 CLB Fabric Memory Interface 0 8 PCI 66 D 16 PCI 33 ug362_c2_04_011209 i Figure 2 4 MMCM as a Frequency Synthesizer Frequency Synthesis Using Fractional Divide Virtex 6 FPGAs support fractional non integer divides in the CLKOUTO output path If the CLKOUTO counter is used in fractiona
13. of the die Figure 1 20 By fixing the dimensions of the clock region larger Virtex 6 devices can have more clock regions As a result Virtex 6 devices can support many more multiple clock domains than previous FPGA architectures Table 1 5 shows the number of clock regions in each Virtex 6 device The CMT and global clocking resources are located to the right of the center column containing the configuration pins www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX XC6VLX75T has 6 Clock Regions 20 CLBs 20 CLBs All clock regions All clock regions span half the die span half the die X CMT Column Center Column Resources Configuration Resources Global Clocking Resources XC6VLX760 has 18 Clock Regions All clock regions are 40 CLBs tall 20 CLBs above and 20 CLBs below a horizontal row Figure 1 20 Clock Regions Table 1 5 Virtex 6 FPGA Clock Regions Device Number of Clock Regions XC6VLX75T 6 XC6VLX130T 10 XC6VLX195T 10 XC6VLX240T 12 XC6VLX365T 12 XC6VLX550T 18 XC6VLX760 18 XC6VSX315T 12 XC6VSX475T 18 XC6VHX250T 12 XC6VHX255T 12 XC6VHX380T 18 XC6VHX565T 18 Clocking Resources UG362 v1 6 January 17 2011 www xilinx com ug362_c1_19_040209 25 Chapter 1 Clocking Resources XILINX Regional Clocking Resources 26 Regional clock networks are a set of differential clock networks independent of the global cl
14. within one clock cycle of clock stoppage The signal is deasserted after the clock has restarted or switched to the alternate clock input and the MMCM has re locked CLKFBSTOPPED Feedback Clock Status Status pin indicating that the feedback clock has stopped This signal is asserted within one clock cycle of clock stoppage The signal is deasserted after the feedback clock has restarted and the MMCM has re locked LOCKED An output from the MMCM used to indicate when the MMCM has achieved phase and frequency alignment of the reference clock and the feedback clock at the input pins Phase alignment is within a predefined window and frequency matching within a predefined PPM range The MMCM automatically locks after power on no extra reset is required LOCKED will be deasserted within one clock cycle if the input clock stops the phase alignment is violated e g input clock phase shift or the frequency has changed The MMCM will automatically re lock if the clock stops or when the phase or frequency is changed DO 15 0 Dynamic Reconfiguration Output Bus The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration If DWE is inactive while DEN is active at the rising edge of DCLK then this bus holds the content of the configuration cells addressed by DADDR The DO bus must be captured on the rising edge of DCLK when DRDY is active www xilinx com Clocking Resources UG362 v1 6 January 17 2011
15. 1 6 January 17 2011 XILINX Clocking Resources General Usage Description CLKINSEL Clock Input Select The CLKINSEL signal controls the state of the clock input MUXes High CLKIN1 Low CLKIN2 see Reference Clock Switching The MMCM must be held in RESET during clock switchover RST Asynchronous Reset Signal The RST signal is an asynchronous reset for the MMCM The MMCM will be synchronously re enabled when this signal is deasserted PWRDWN Power Down Powers down instantiated but currently unused MMCMs This mode can be used to save power for temporarily inactive portions of the design and or MMCMs that are not active in certain system configurations No MMCM power is consumed in this mode DADDR 6 0 Dynamic Reconfiguration Address The dynamic reconfiguration address DADDR input bus provides a reconfiguration address for the dynamic reconfiguration The address value on this bus specifies the 16 configuration bits that are written or read with the next DCLK cycle When not used all bits must be assigned zeros DI 15 0 Dynamic Reconfiguration Data Input The dynamic reconfiguration data input DI bus provides reconfiguration data The value of this bus is written to the configuration cells The data is presented in the cycle that DEN and DWE are active The data is captured in a shadow register and written at a later time DRDY indicates when the DRP port is ready to accept another write When not used
16. Application Example The following MMCM attribute settings result in a wide variety of synthesized clocks H lt CLKOUTO_PHASE 0 CLKOUTO_DUTY_CYCLE 0 5 CLKOUTO_DIVIDE 2 CLKOUT1_PHASE 90 CLKOUT1_DUTY_CYCLE 0 5 CLKOUT1_DIVIDE 2 CLKOUT2_PHASE 0 CLKOUT2_DUTY_CYCLE 0 25 CLKOUT2_DIVIDE 4 CLKOUT3_PHASE 90 CLKOUT3_DUTY_CYCLE 0 5 CLKOUT3_DIVIDE 8 CLKOUT4_PHASE 0 CLKOUT4_DUTY_CYCLE 0 5 CLKOUT4_DIVIDE 8 CLKOUT5_PHASE 135 CLKOUT5_DUTY_CYCLE 0 5 CLKOUT5 DIVIDE 8 CLKFBOUT_PHASE 0 CLKFBOUT_MULT_F 8 D C CLK DIVIDE 1 1 KIN1_PERIOD 10 0 Figure 2 14 displays the resulting waveforms REFCLK Jo JP Lo CLKOUTO CLKOUT1 CLKOUT2 CLKOUT3 00004 OO CLKOUTS UG362 c2 14 033109 Figure 2 14 Example Waveform Dynamic Reconfiguration Port Details of the supported Virtex 6 FPGAs MMCM DRP operations are described in XAPP878 MMCM Dynamic Reconfiguration Clocking Resources www xilinx com 61 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager 62 www xilinx com XILINX Clocking Resources UG362 v1 6 January 17 2011
17. BUFIO Primitive BUFIO is simply a clock in clock out buffer There is a phase delay between input and output Figure 1 21 shows the BUFIO Table 1 6 lists the BUFIO ports A location constraint is available for BUFIO BUFIO ug362 c1 20 040209 Figure 1 21 BUFIO Primitive Table 1 6 BUFIO Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port I Input 1 Clock input port BUFIO Use Models In Figure 1 22 a BUFIO is used to drive the I O logic using the clock capable I O This implementation is ideal in source synchronous applications where a forwarded clock is used to capture incoming data Clocking Resources www xilinx com 27 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources 10 1 0 1 0 1 0 10 1 0 P IO Clock Capable I O Single Region N I O Clock Capable I O Multiple Regions N 10O Not all available BUFIOs are shown Clock Capable I O Multiple Regions N yo 6 Clock Capable I O Single Region N I O 6 10 XILINX To Adjacent To Adjacent Bank Region gt To Fabric To Adjacent To Adjacent Bank Region ug362_c1_21_062210 Figure 1 22 BUFIO Driving I O Logic Regional Clock Buffer BUFR The regional clock buffer BUFR is another clock buffer available in Virtex 6 devices BUFRs drive clock signals to a dedicated clock net within a clock region independent from 28 www xilinx com Clocking Re
18. FG GCIO or CCIO BUFR GTX BUFH Local Rounting not recommended CLKIN1 MMCM LKIN BUFG IBUFG GCIO or CCIO BUFR GTX BUFH Local Rounting not recommended CLKIN2 UG362 c2 08 033109 Figure 2 8 Input Clock Switching Missing Input Clock or Feedback Clock When the input clock or feedback clock is lost the MMCM optionally maintains the VCO frequency at a slightly lower frequency than the original The CLKINSTOPPED or CLKFBSTOPPED status signal is asserted The MMCM deasserts the LOCKED signal After the clock returns the CLKSTOPPED signal is deasserted and a RESET must be applied MMCM Use Models There are several methods to design with the MMCM The Clocking Wizard in ISE software can assist with generating the various MMCM parameters Additionally the MMCM can be manually instantiated as a component It is also possible for the MMCM to be merge with an IP core The IP core would contain and manage the MMCM Clock Network Deskew One of the predominant uses of the MMCM is for clock network deskew Figure 2 9 shows the MMCM in this mode The clock output from one of the CLKOUT counters is used to drive logic within the fabric and or the I Os The feedback counter is used to control the exact phase relationship between the input clock and the output clock if for example a 90 phase shift is required The associated clock waveforms are shown to the right for the case where the input clock and output clo
19. Figure 1 19 e At time event 1 output O uses input IO e Before time event 2 S is asserted High e At time Tpccko o after time event 2 output O uses input I1 This occurs after a High to Low transition of 10 followed by a High to Low transition of I1 is completed e At time Tgccck cr before time event 3 CE is asserted Low The clock output is switched Low and kept at Low after a High to Low transition of I1 is completed Clock Tree and Nets GCLK Virtex 6 FPGA clock trees are designed for low skew and low power operation Any unused branch is disconnected The clock trees also manage the load fanout when all the logic resources are used All global clock lines and buffers are implemented differentially This facilitates much better duty cycles and common mode noise rejection In the Virtex 6 architecture the pin access of the global clock lines are not limited to the logic resources clock pins The global clock lines can drive pins in the CLB other than CLK pins for example the control pins SR and CE Applications requiring a very fast signal connection and large load fanout benefit from this architecture Clock Regions Virtex 6 devices improve the clocking distribution by the use of clock regions Each clock region can have up to 12 global clock domains These 12 global clocks can be driven by any combination of the 32 global clock buffers The dimensions of a clock region are fixed to 40 CLBs tall 40 IOBs and spanning half
20. I LIL Ju TLE TL IL OCT Lt ttl UG362_c2_06_040209 Figure 2 6 Output Counter Clock Synthesis Examples 54 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Detailed VCO and Output Counter Waveforms Detailed VCO and Output Counter Waveforms Clocking Resources Figure 2 7 shows the eight VCO phase outputs and four different counter outputs Each VCO phase is shown with the appropriate start up sequence The phase relationship and start up sequence are guaranteed to insure the correct phase is maintained This means the rising edge of the 0 phase will happen before the rising edge of the 45 phase The O0 counter is programmed to do a simple divide by two with the 0 phase tap as the reference clock The O1 counter is programmed to do a simple divide by two but uses the 180 phase tap from the VCO This counter setting could be used to generate a clock for a DDR interface where the reference clock is edge aligned to the data transition The O2 counter is programmed to do a divide by three The O3 output has the same programming as the O2 output except the phase is set for a one cycle delay Phase shifts greater than one VCO period are possible If the MMCM is configured to provide a certain phase relationship and the input frequency is changed then this phase relationship is also changed since the VCO frequency changes and therefore the absolute shift in picoseconds will change This aspect must be
21. INE PS and CLKFBOUT USE FINE PS select the output clocks to be dynamically phase shifted The dynamic phase shift amount is common to all the output clocks selected The variable phase shift is controlled by the PSEN PSINCDEC PSCLK and PSDONE ports Figure 2 5 After the MMCM locks the initial phase is determined by the CLKOUT PHASE attribute Most commonly no initial phase shift is selected The phase of the MMCM output clock s increments decrements according to the interaction of PSEN PSINCDEC PSCLK and PSDONE from the initial or previously performed dynamic phase shift PSEN PSINCDEC and PSDONE are synchronous to PSCLK When PSEN is asserted for one PSCLK clock period a phase shift increment decrement is initiated When PSINCDEC is High an increment is initiated and when PSINCDEC is Low a decrement is initiated Each increment adds to the phase shift of the MMCM clock outputs by 1 56th of the VCO period Similarly each decrement decreases the phase shift by 1 56th of the VCO period PSEN must be active for one PSCLK period PSDONE is High for exactly one clock period when the phase shift is complete The number of PSCLK cycles is deterministic After initiating the phase shift by asserting PSEN and the completion of the phase shift signaled by PSDONE the MMCM output clocks and the MMCM output clocks gradually drift from their original phase shift to an increment decrement phase shift in a linear fashion The completion of the incremen
22. MUX SO o CEO IGNOREO UG362 c1 10 040209 Figure 1 11 BUFGMUX as BUFGCTRL Since the BUFGMUX uses the CE pins as select pins when using the select the setup time requirement must be met Violating this setup time may result in a glitch Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL Figure 1 12 illustrates the timing diagram for BUFGMUX Clocking Resources www xilinx com 19 UG362 v1 6 January 17 2011 20 Chapter 1 Clocking Resources XILINX T BCCCK CE O O SDT Ld Ld 0 NY NN TEN 4 N TN O M N i gt Tgocko o e m Taccko o begin switching using 11 ug362 c1 11 121510 Figure 1 12 BUFGMUX Timing Diagram In Figure 1 12 The current clock is IO S is activated High If I0 is currently High the multiplexer waits for 10 to deassert Low Once I0 is Low the multiplexer output stays Low until I1 transitions High to Low When 11 transitions from High to Low the output switches to I1 If Setup Hold are met no glitches or short pulses can appear on the output BUFGMUX 1 is rising edge sensitive and held at High prior to input switch Figure 1 13 illustrates the timing diagram for BUFGMUX 1 A LOC constraint is available for BUFGMUX and BUFGMUX 1 TBCCCK CE S S TNT 112 OL NLLI4 N TBCCKO_O ug362 c1 12 040209 Figure 1 13 BUFGMUX 1 Timing Diagram I
23. Operating Range The minimum and maximum VCO operating frequencies are defined in the electrical specification of the Virtex 6 FPGA Data Sheet These values can also be extracted from the speed specification 42 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX General Usage Description Minimum and Maximum Input Frequency The minimum and maximum CLKIN input frequency are defined in the electrical specification of the Virtex 6 FPGA Data Sheet Duty Cycle Programmability Only discrete duty cycles are possible given a VCO operating frequency Depending on the CLKOUT DIVIDE value a minimum and maximum range is possible with a step size that is also depending on the CLKOUT DIVIDE value The Clocking Wizard tool gives the possible values for a given CLKOUT_DIVIDE Phase Shift Clocking Resources In many cases there needs to be a phase shift between clocks The MMCM has multiple options to implement phase shifting Static phase shifting can be achieved by selecting one of the eight VCO output phases with additional fine phase shifting available in the CLKOUT output counters depending on the CLKOUT divide value In Virtex 6 FPGAs there is also an interpolated phase shifting capability in either fixed or dynamic mode The MMCM phase shifting capabilities are very powerful which can lead to complex scenarios It is best to consult the software tools for selecting the proper phase shift methodology Static Phase
24. Resources XILINX Clocking Region l O Bank c E o O D O 9 O o c si O ug362_c1_27_040209 Figure 1 28 Horizontal Clock Buffer High Performance Clocks Virtex 6 devices contain four high performance clocks HPC per I O column in each region from the MMCMs and in the same region to the inner and outer I O columns including the GTX GTH transceiver columns These clocks Figure 1 29 are directly driven by the MMCMs regulated power supply and never enter the supply domain Therefore these clocks exhibit very low jitter and minimal duty cycle distortion In the I O columns the HPC connects to the BUFIO and drives the I O logic Two of the four HPCs can drive directly into the I O banks above and below without using the multiregion BUFIO The HPCs can also directly connect to the OSERDES without going through another clock buffer This provides a forwarded clock with very low jitter and low duty cycle distortion An HPC has no buffer associated with it The ISE software automatically determines when to use this resource by examining the connections to the IOLOGIC OLOGIC in the design HPCs can also drive BUFRs in the same region to support the source synchronous interface designs Either MMCM in a CMT CLKOUTO through CLKOUT3 can drive the HPCs in the left or right side regions www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX VHDL and Verilog Temp
25. Shift Mode The Static Phase Shift SPS resolution in time units is defined as SPS period or 1 D Equati i BE yaa BMF po quation 2 3 Since the VCO can provide eight phase shifted clocks at 45 each always providing possible settings for 0 45 90 135 180 225 270 and 315 of phase shift The higher the VCO frequency is the smaller the phase shift resolution Since the VCO has a distinct operating range it is possible to bound the phase shift resolution using from 1 1 to period 8Fycomin 8F vcomax Each CLKOUT output counter is individually programmable allowing each to have an additional phase shift resolution in degrees based on the phase of the VCO selected and the CLKOUT counter divide value The granularity of the CLKOUT phase shift value can be calculated as 45 CLKOUT_DIVIDE value The maximum phase shift range is also determined by the CLKOUT_DIVIDE value The maximum phase shift is 360 when CLKOUT_DIVIDE lt 64 When CLKOUT_DIVIDE is gt 64 the maximum phase shift is 64 Maximum Phase Shift UT DIVIDE x 860 7 x Phase Shift Value Itis possible to phase shift the CLKFBOUT feedback clock In that case all CLKOUT output clocks are negatively phase shifted with respect to CLKIN Interpolated Fine Phase Shift in Fixed or Dynamic Mode Interpolated Fine Phase Shift IFPS mode in the MMCM has linear shift behavior independent of the CLKOUT_DIVIDE value a
26. T Dedicated MMCM Feedback Output CLKFBOUTB Output Inverted CLKFBOUT See CLKFBOUTB Inverted CLKFBOUT CLKINSTOPPED Output Pe pin ne that the input clock has stopped See CLKINSTOPPED Input Clocking Resources UG362 v1 6 January 17 2011 www xilinx com 47 Chapter 2 Mixed Mode Clock Manager XILINX Table 2 3 MMCM Ports Cont d Pin Name CLKFBSTOPPED y o Pin Description Status pin indicating that the feedback clock has stopped See CLKFBSTOPPED Output Feedback Clock Status LOCKED An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range The MMCM automatically locks after power on No extra reset is required LOCKED will be deasserted if the input clock stops or the phase alignment is violated e g input clock phase shift The MMCM automatically re aquires lock after LOCKED is deasserted See LOCKED Output DO 15 0 The dynamic reconfiguration output bus provides MMCM data output when using Cue dynamic reconfiguration See DO 15 0 Dynamic Reconfiguration Output Bus DRDY The dynamic reconfiguration ready output DRDY provides the response to the Output DEN signal for the MMCMs dynamic reconfiguration feature See DRDY Dynamic Reconfiguration Ready PSDONE Output Phase shift done See PSDONE Phase Shift Done Notes 1 All contro
27. U vebkECH n Rc RE erad eed 43 Phase Shift a cepe p Ete tx euasit te ce ba aa 43 Dynamic Phase Shift Interface sisremare n Oie a E a 44 Counter Cascading ielekasaececee kia ipa be v eie rar ek d a bed eee 45 MMCM Programmmg bI e reete een seta e RA ERE Eri s ades 45 Determine the Input Frequency 6 6 ccc en 45 Determine the M and D Values 0c cece eee hr 46 MMEM Ports erise ceruri avers RRENSG DRAN ERE Seed ar Ea Eae E eases 46 MMCM Port Descriptions a 2 eraot tears rr rb ad RO WR ird he a guts 48 MMCM Attributes oe Er EX REexG eu i x ened e ER Y VR baw Rada 51 MMCM Clock Input Signals csere sisi gei ee 53 Counter Control esse rinena pana E E a a a eon tee ne A atlas 54 Detailed VCO and Output Counter Waveforms ussseusueussssssss 55 Reference Clock Switching osse eese 56 Missing Input Clock or Feedback Clock ssssssssss eese esee 56 MMCM Use Models ssssse RI e 56 Clock Network Deskew xe ee nie ei Re RR LEY 4 eR Wee VAY REN REN 56 MMCM with Internal Feedback 2 2 2 een eee 57 Zero Delay Buffer iile regi Ru IER ax rr RR RETE Eds 58 MMCM to MMCM Connection 00 ccc cece eee ene n nent n 59 MMCM Application Example 0 6 n 61 Dynamic Reconfiguration Port 6 666 ccc ene eens 61 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Preface About This Guide This
28. UER Primitlve s zu aar ai Re rre rH RC En eie ae Ree GU Re 29 BUFR Attributes and Modes ccc eee hr 30 BUFR Use Models xe p rex a ER EAE CER EEG o C3 gis 31 Regional Clock Nets 5 sess e me RR RES SIDE REY IT 32 Horizontal Clock Buffer BUFH ssseeeeeeeeee eR 33 High Performance Clocks ei Ret ee De PRI RI p Rr EHE he 34 VHDL and Verilog Templates 0 35 Chapter 2 Mixed Mode Clock Manager Introduction uoo e Doer Ls eee ns eh honed pune ben ed eat ae e sedia 37 MMCM Sieti e e a a aa a e 38 General Usage Description s oii o vun oen eire derer ae aped led 39 MMCM Primitives iucsess ere Re eR RERO RARO eX Ge dE UR Yee ee 39 MMCM BASE Primitive e re Rer RR ER ced OR RAD E Rae Ree 40 MMCM ADV Primitive seee arenae aeia Hrs 40 Clock Network Deskew 5 edet tr edt ds Pg ode MP gode P tat 41 Frequency Synthesis Only Using Integer Divide 0 0 00 cee eee eee 41 Clocking Resources www xilinx com UG362 v1 6 January 17 2011 XILINX Frequency Synthesis Using Fractional Divide 2 2 2 2 42 Jitter Filtet PCT 42 Lamitatons 35v SG aces RUP RT hak ve ee ee PCR POSEE PR PR Ge ERE 42 VCO Operating Range seras anaa nea Enana S pre diets eae TI et E P Rd 42 Minimum and Maximum Input Frequency 6 60 43 Duty Cycle Progrommiabllity 5 3 9 biker kh e
29. UFGCE I O CE BUFGCE_1 I O CE BUFGMUX I0 11 O 5 BUFGMUX 1 10 11 O S BUFGMUX_CTRL 10 11 O 5 Notes 1 All primitives are derived from a software preset of BUFGCTRL BUFGCTRL The BUFGCTRL primitive shown in Figure 1 4 can switch between two asynchronous clocks All other global clock buffer primitives are derived from certain configurations of BUFGCTRL The ISE software tools manage the configuration of all these primitives BUFGCTRL has four select lines S0 51 CEO and CE1 It also has two additional control lines IGNOREO and IGNORE These six control lines are used to control the input 10 and 11 BUFGCTRL IGNORE1 CE1 0 eq E o c IGNOREO UG362 c1 O3 040209 Figure 1 4 BUFGCTRL Primitive 14 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Clocking Resources Global Clocking Resources BUFGCTRL is designed to switch between two clock inputs without the possibility of a glitch When the presently selected clock transitions from High to Low after S0 and S1 change the output is kept Low until the other to be selected clock has transitioned from High to Low Then the new clock starts driving the output The default configuration for BUFGCTRL is falling edge sensitive and held at Low prior to the input switching BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching In some applications the conditions previously described
30. Updated the Global Clock Buffers section Updated the setup hold requirements for S0 and S1 on page 21 A third paragraph about calibration circuits was added to the Introduction of Chapter 2 Updated Clock Network Deskew Changed the VCO example in Interpolated Fine Phase Shift in Fixed or Dynamic Mode In Table 2 4 updated the allowed values for CLKFBOUT MULT F and changed any type listed as String to Boolean to match the software models Updated Dynamic Reconfiguration Port 04 07 10 14 Updated the STARTUP_WAIT attribute allowed value on page 37 and Table 2 4 08 16 10 1 5 Updated CE descriptions in Table 1 7 and Table 1 9 Clarified adjacent bank connections in Figure 1 22 01 17 11 1 6 Updated Global Clock Buffers section with information on cascading BUFGs Updated waveform in Figure 1 12 In Table 2 4 added Note 1 to DIVCLK_DIVIDE 1 Also in Table 2 4 corrected allowed values for CLKIN1 PERIOD and CLKIN2 PERIOD The Reference Clock Switching section now includes the need to force a RESET after clock switchover Updated the Maximum Phase Shift equation on page 43 Updated the GTX GTH transceiver MMCM discussion on page 53 UG362 v1 6 January 17 2011 www xilinx com Clocking Resources Clocking Resources www xilinx com UG362 v1 6 January 17 2011 Table of Contents Revision History oe riei bois bue deed afe xe we den AS ed aS ICE ae aw ee bad ard 3 Preface About This Guide
31. V IGNORE1 DD VpD CE1 S S1 Asynchronous MUX Design Example 11 11 o o 10 10 gt CEO VDD VDD IGNOREO ug362 c1 15 040209 Figure 1 16 Asynchronous MUX with BUFGCTRL Design Example 22 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX at 10 TBccko Begin 11 Global Clocking Resources UG362 c1 16 040209 Figure 1 17 Asynchronous MUX Timing Diagram In Figure 1 17 The current clock is from IO S is activated High The Clock output immediately switches to I1 When Ignore signals are asserted High glitch protection is disabled BUFGMUX CTRL with a Clock Enable A BUFGMUX CTRL with a clock enable BUFGCTRL configuration allows the user to choose between the incoming clock inputs If needed the clock enable is used to disable the output Figure 1 18 illustrates the BUFGCTRL usage design example and Figure 1 19 shows the timing diagram Clocking Resources UG362 v1 6 January 17 2011 BUFGMUX CTRL CE Design Example Figure 1 18 CE GND IGNORE1 CE1 1 50 gt o CEO www xilinx com GND IGNOREO ug362 ci 17 051509 BUFGMUX CTRL with a CE and BUFGCTRL 23 Chapter 1 Clocking Resources XILINX 24 TBCCCK_CE C rr ee 4 Tgccko o m TBccko o Begin 11 Clock Off ug362_c1_18_040209 Figure 1 19 BUFGMUX_CTRL with a CE Timing Diagram In
32. Virtex 6 FPGA Clocking Resources User Guide UG362 v1 6 January 17 2011 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING
33. ability to divide the input clock frequency The Virtex 6 FPGA BUFRs can also directly drive MMCM clock inputs and BUFGs CE CLR ug362 ci 22 040209 Figure 1 23 BUFR Primitive Table 1 7 BUFR Port List and Definitions Port Name Type Width Definition O Output 1 Clock output port CE Input 1 Output clock enable port Cannot be used in BYPASS mode CLR Input 1 Asynchronous clear for the divide logic and sets the output Low Cannot be used in BYPASS mode I Input 1 Clock input port Additional Notes on the CE Pin When CE is asserted deasserted the output clock signal turns on off When global set reset GSR signal is High BUFR does not toggle even if CE is held High The BUFR output toggles after the GSR signal is deasserted when a clock is on the BUFR input port www xilinx com 29 UG362 v1 6 January 17 2011 30 Chapter 1 Clocking Resources XILINX BUFR Attributes and Modes Clock division in the BUFR is controlled in software through the BUFR DIVIDE attribute Table 1 8 lists the possible values when using the BUFR DIVIDE attribute Table 1 8 BUFR DIVIDE Attribute Attribute Name Description Possible Values BUFR DIVIDE Defines whether the output clock is a divided 1 2 3 4 5 6 7 8 version of the input clock BYPASS default Notes 1 Location constraint is available for BUFR The propagation delay through BUFR is different for BUFR_DIVIDE
34. ain two MMCMs Each MMCM within the tile can be treated separately however there exists a dedicated routing between MMCMs Using these dedicated routes frees up global resources for other design elements Additionally the use of local routes within the CMT provides an improved clock path because the route is handled locally reducing chances for noise coupling The CMT diagram Figure 2 1 shows a high level view of the connection between the various clock input sources and the MMCM to MMCM In Virtex 6 FPGAs the clock input connectivity is greatly enhanced allowing multiple resources to provide the reference clock s to the MMCMs The number of output counters dividers has increased to eight with some of them capable of driving out an inverted clock signal 180 phase shift For backward compatibility with DCMs nine independent outputs can be selected for mapping the DCM outputs directly into the MMCM The MMCM output clocks in the same CMT can be chained by multiplexing any MMCM output into a single clock signal for use as a reference clock to the other MMCM Virtex 6 FPGA MMCMs have added infinite fine phase shift capability in either direction and can be used in dynamic or fixed phase shift mode The resolution of the fine phase shift depends on the VCO frequency Fractional divide functionality in increments of 1 8th 0 125 is added to support greater clock frequency synthesis capability A fractional divide can be performed by combining two c
35. are not desirable Asserting the IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching between two clock inputs In other words asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes IGNOREO causes the output to switch away from the I0 input immediately when the select pin changes while IGNORE causes the output to switch away from the I1 input immediately when the select pin changes Selection of an input clock requires a select pair SO and CEO or 1 and CE1 to be asserted High If either S or CE is not asserted High the desired input will not be selected In normal operation both 5 and CE pairs all four select lines are not expected to be asserted High simultaneously Typically only one pin of a select pair is used as a select line while the other pin is tied High The truth table is shown in Table 1 3 Table 1 3 Truth Table for Clock Resources CEO 50 CE1 S1 0 1 1 10 1 1 0 10 0 1 1 n X 0 1 1 til 1 1 1 1 Old Input Notes 1 Old input refers to the valid input clock before this state is achieved 2 For all other states the output becomes the value of INIT OUT and does not toggle Although both S and CE are used to select a desired output each one of these pins behaves slightly different When using CE to switch clocks the change in clock selection can be faster than when using S Violation in Setup Hold time of th
36. cade MMCMs route the output of the first MMCM to the CLKIN pin of the second MMCM This path provides the lowest device jitter Cascading using the inverted CLKOUTxB outputs is not available M M M MMCM2 MMCM1 MMCM2 mc T OTE NEC rs x TUERI ME Equation 2 10 cu V MMcM2 MMCM1 X V MMCM1 MMCM2 V MMCM2 www xilinx com 59 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX IBUFG CLKIN1 CLKOUTO CLKFBIN CLKOUTOB RST CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B CLKOUT4 CLKOUTS5 CLKOUT6 CLKFBOUT CLKFBOUTB MMCM LOCKED Figure 2 12 Cascading Two MMCMs Without Any Clock Alignment IBUFG CLKIN1 CLKOUTO CLKFBIN CLKOUTOB RST CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT CLKFBOUTB MMCM LOCKED gt CLKIN1 CLKOUTO r CLKFBIN CLKOUTOB CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT CLKFBOUTB MMCM LOCKED BUFG BUFG Be To Logic Figure 2 13 Cascading Two MMCMs With Clock Alignment gt CLKIN1 CLKOUTO r CLKFBIN CLKOUTOB CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED MMCM ug362_c2_12_040209 BUFG ug362_c2_13_040209 60 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX MMCM Use Models MMCM
37. can drive all clock regions in Virtex 6 devices However only 12 different clocks can be driven in a single clock region A clock region 40 CLBs is a branch of the clock tree consisting of 20 CLB rows up and 20 CLB rows down A clock region only spans halfway across the device The clock buffers are designed to be configured as a synchronous or asynchronous glitch free 2 1 multiplexer with two clock inputs Virtex 6 device control pins provide a wide range of functionality and robust input switching In the Virtex 6 clocking architecture BUFGCNTRL multiplexers and all derivatives can be cascaded to adjacent clock buffers within the group of 16 in the upper lower half of the device effectively creating a ring of 16 BUFGMUXes BUFGCNTRL multiplexers in the upper half and another ring of 16 in the lower half Figure 1 3 shows a simplified diagram of cascading BUFGs ug362_c1_03_111510 Figure 1 3 Cascading BUFGs The following subsections detail the various configurations primitives and use models of the Virtex 6 FPGA clock buffers www xilinx com 13 UG362 v1 6 January 17 2011 Chapter 7 Clocking Resources XILINX Global Clock Buffer Primitives The primitives in Table 1 2 are different configurations of the global clock buffers Table 1 2 Global Clock Buffer Primitives Primitive Input Output Control BUFGCTRL 10 11 O CEO CE1 IGNOREO IGNORE1 50 51 BUFG I O B
38. ched from I1 to I0 without requiring a High to Low transition of I1 Other capabilities of BUFGCTRL are Pre selection of the 10 and I1 inputs are made after configuration but before device operation The initial output after configuration can be selected as either High or Low e Clock selection using CEO and CE1 only S0 and 51 tied High can change the clock selection without waiting for a High to Low transition on the previously selected clock 16 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Global Clocking Resources Table 1 4 summarizes the attributes for the BUFGCTRL primitive Table 1 4 BUFGCTRL Attributes Attribute Name INIT OUT Initializes the BUFGCTRL output to the specified 0 default 1 value after configuration Sets the positive or negative edge behavior Sets the output level when changing clock selection Description Possible Values PRESELECT 10 If TRUE BUFGCTRL output will use the 10 input FALSE default after configuration TRUE PRESELECT 11 If TRUE BUFGCTRL output will use the I1 input FALSE default after configuration TRUE Notes 1 Both PRESELECT attributes cannot be TRUE at the same time 2 The LOC constraint is available BUFG BUFG is simply a clock buffer with one clock input and one clock output This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 6 illustrates the relationship o
39. ck inputs There are eight global clock inputs per device Clock inputs can be configured for any I O standard including differential I O standards Each clock input can be either single ended or differential All eight clock inputs can be differential if desired When used as outputs global clock input pins can be configured for any output standard Each global clock input pin supports any single ended output standard or any output differential standard The global clock inputs are distributed across four banks in the inner I O columns for the most flexible selection of I O standards Global Clock Input Buffer Primitives The primitives in Table 1 1 are different configurations of the input clock I O input buffer Table 1 1 Clock Buffer Primitives Primitive Input Output Description IBUFG I O Input clock buffer for single ended I O IBUFGDS L IB O Input clock buffer for differential I O These two primitives work in conjunction with the Virtex 6 FPGA SelectIO resource by setting the IOSTANDARD attribute to the desired standard Refer to Chapter 1 of the Virtex 6 FPGA SelectIO Resources User Guide for a complete list of possible I O standards Clock Gating for Power Savings The Virtex 6 FPGA clock architecture provides a straightforward means of implementing clock gating for the purposes of powering down portions of a design Most designs contain several unused BUFGCE resources A clock can drive a BUFGCE input and a
40. ck need to be phase aligned This configuration is the most flexible but it does require two global clock networks Figure 2 9 56 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX MMCM Use Models CLKOUTO To Logic CLKOUTOB CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B a fo CLKOUT4 E CLKOUTS5 CLKOUT6 3 CLKFBOUT S E CLKFBOUTB LOCKED 5 6 MMCM UG362_c2_09_033109 Figure 2 9 Clock Deskew Using Two BUFGs There are certain restrictions on implementing the feedback The CLKFBOUT output can be used to provide the feedback clock signal The fundamental restriction is that both input frequencies to the PFD must be identical Therefore the following relationship must be met D frg Equation 2 9 As an example if f is 166 MHz D 1 M 3 and O 1 then VCO and the clock output frequency are both 498 MHz Since the M value in the feedback path is 3 both input frequencies at the PFD are 166 MHz In another more complex scenario has an input frequency of 66 66 MHz and D 2 M 15 and O 2 The VCO frequency in this case is 500 MHz and the CLKOUT output frequency is 250 MHz Therefore the feedback frequency at the PFD is 500 15 or 33 33 MHz matching the 66 66 MHz 2 input clock frequency at the PFD MMOM with Internal Feedback Clocking Resources The MMCM feedback can be internal to the MMCM when the MMCM is used as a synthesizer or jitter filter and there
41. considered when designing with the MMCM When an important aspect of the design is to maintain a certain phase relationship amongst various clock outputs e g CLK and CLK90 then this relationship will be maintained regardless of the input frequency 0 45 VCO 135 orerar 8 Phases 180 ms 225 T 270 Des ne a eg ae r Counter O1 aa Outputs 62 03 One Cycle Delay ug362 02 07 033109 Figure 2 7 Selecting VCO Phases All O counters can be equivalent anything O0 can do O1 can do In Virtex 6 devices the O0 counter has the additional capability to be used in fractional divide mode The MMCM outputs are flexible when connecting to the global clock network since they are identical In most cases this level of detail is imperceptible to the designer as the software and Clocking Wizard determines the proper settings through the MMCM attributes and Wizard inputs www xilinx com 55 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX Reference Clock Switching The MMCM reference clock can be dynamically switched by using the CLKINSEL pin The switching is done asynchronously Once the clock switches the MMCM is likely to lose LOCKED The MMCM clock MUX switching is shown in Figure 2 8 The CLKINSEL signal directly controls the MUX No synchronization logic is present The MMCM must be held in RESET during clock switchover CLKINSEL BUFG IBU
42. ct signal must meet the setup time requirement Violating this setup time may result in a glitch Figure 1 9 illustrates the timing diagram for BUFGCE BUFGCE l BUFGCECE OY BUFGCE O TB K ce o_O UG362_c1_08_040209 Figure 1 9 BUFGCE Timing Diagram BUFGCE 1 is similar to BUFGCE with the exception of its switching condition If the CE input is Low prior to the incoming falling clock edge the following clock pulse does not pass through the clock buffer and the output stays High Any level change of CE during the incoming clock Low pulse has no effect until the clock transitions High The output stays High when the clock is disabled However when the clock is being disabled it completes the clock Low pulse www xilinx com Clocking Resources UG362 v1 6 January 17 2011 g XILINX Global Clocking Resources Figure 1 10 illustrates the timing diagram for BUFGCE 1 BUFGCE 1 l af NF 7 UI NC af T BUFGCE_1 CE TBccck cE BUFGCE 1 O JUN I J K _T BCCKO_O UG362_c1_09_040209 Figure 1 10 BUFGCE 1 Timing Diagram BUFGMUX and BUFGMUX 1 BUFGMUX is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 11 illustrates the relationship of BUFGMUX and BUFGCTRL A LOC constraint is available for BUFGMUX and BUFGCTRL GND IGNORE1 S CE1 51 BUFG
43. e CE pins causes a glitch at the clock output On the other hand using the S pins allows the user to switch between the two clock inputs without regard to Setup Hold times It will not result in a glitch See BUFGMUX CTRL The CE pin is designed to allow backward compatibility from previous Virtex architectures The timing diagram in Figure 1 5 illustrates various clock switching conditions using the BUFGCTRL primitives Exact timing numbers are best found using the speed specification www xilinx com 15 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources XILINX 1 2 3 4 5 6 DP 46 a 1 141 1 l ib A ee ss ee CNN gt qpm lBccck cE CEO 2 es Se IGNOREO IGNORE1 TBCCKO_O T T e ae a j TBccko o _ Ob T pi aT ees ee e A A at 10 Begin l1 Begin 10 UG362_c1_04_040209 Figure 1 5 BUFGCTRL Timing Diagram e Before time event 1 output O uses input 10 e At time Tgcccx cr before the rising edge at time event 1 both CEO and S0 are deasserted Low At about the same time both CE1 and 51 are asserted High Attime Tpccko o after time event 3 output O uses input I1 This occurs after a High to Low transition of 10 event 2 followed by a High to Low transition of I1 e At time event 4 IGNORE T is asserted e At time event 5 CEO and SO are asserted High while CE1 and 1 are deasserted Low At Tpccko o after time event 6 output O has swit
44. eduction These three modes of operation are discussed in more detail within this section The Voltage Controlled Oscillator VCO operating frequency can be determined by using the following relationship Fvco Forku Equation 2 1 M Four Fo kIN Bx O Equation 2 2 where the M D and O counters are shown in Figure 2 2 The value of M corresponds to the CLKFBOUT MUIT F setting the value of D to the DIVCLK_DIVIDE and O to the CLKOUT DIVIDE The seven O counters can be independently programmed For example O0 can be programmed to do a divide by two while O1 is programmed for a divide by three The only constraint is that the VCO operating frequency must be the same for all the output counters since a single VCO drives all the counters Clock Network Deskew In many cases designers do not want to incur the delay on a clock network in their I O timing budget therefore they use a MMCM to compensate for the clock network delay Virtex 6 FPGAs support this feature A clock output matching the reference clock CLKIN frequency always CLKFBOUT is connected to a BUFG in the same half of the device and fed back to the CLKFBIN feedback pin of the MMCM The remaining outputs can still be used to divide the clock down for additionally synthesized frequencies In this case all output clocks have a defined phase relationship to the input reference clock Frequency Synthesis Only Using Integer Divide Clocking Resources The MMCMs can
45. f BUFG and BUFGCTRL A LOC constraint is available for BUFG IGNORE1 BUFG D IGNOREO UG362 c1 05 040209 Figure 1 6 BUFG as BUFGCTRL The output follows the input as shown in the timing diagram in Figure 1 7 P rp P m NP BUFG O EN pue Iu WM zx Pa t Tgccko o E UG362 c1 06 040209 Figure 1 7 BUFG Timing Diagram Clocking Resources www xilinx com 17 UG362 v1 6 January 17 2011 18 Chapter 1 Clocking Resources XILINX BUFGCE and BUFGCE 1 Unlike BUFG BUFGCE is a clock buffer with one clock input one clock output and a clock enable line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 8 illustrates the relationship of BUFGCE and BUFGCTRL A LOC constraint is available for BUFGCE and BUFGCE 1 BUFGCE as BUFGCTRL Va IGNORE DD enp CE BUFGCE GND S CE ce CEO GND IGNOREO UG362 c1 07 040209 Figure 1 8 BUFGCE as BUFGCTRL The switching condition for BUFGCE is similar to BUFGCTRL If the CE input is Low prior to the incoming rising clock edge the following clock pulse does not pass through the clock buffer and the output stays Low Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low The output stays Low when the clock is disabled However when the clock is being disabled it completes the clock High pulse Since the clock enable line uses the CE pin of the BUFGCTRL the sele
46. gt MRCC Pin Pair SRCC Pin Pair 4 gt SRCC Pin Pair Two BUFRs Two BUFRs l I l J In Same Region Go YY vy To Bank To Bank Below Below SRCC Single Region Clock Capable 1 O MRCC Multi Region Clock Capable I O Single ended clocks must be connected to the P side of the differential pair UG362_c1_02_011609 Figure 1 2 Inner I O Column Single Region Clocking Structure For more information on clock input pins consult the Die Level Bank Numbering and Clock Pins Overview section in UG365 Virtex 6 FPGA Packaging and Pinout Specification Global Clocking Resources Clocking Resources Global clocks are a dedicated network of interconnect specifically designed to reach all clock inputs to the various resources in an FPGA These networks are designed to have low skew and low duty cycle distortion low power and improved jitter tolerance They are also designed to support very high frequency signals Understanding the signal path for a global clock expands the understanding of the various global clock resources The global clocking resources and network consist of the following paths and components Global Clock Inputs Global Clock Buffers Clock Tree and Nets GCLK Clock Regions www xilinx com 11 UG362 v1 6 January 17 2011 12 Chapter 1 Clocking Resources XILINX Global Clock Inputs Virtex 6 FPGAs contain specialized global clock input locations for use as regular user I Os if not used as clo
47. guide serves as a technical reference describing the Virtex 6 FPGA clocking resources Guide Contents This manual contains the following chapters e Chapter 1 Clocking Resources Chapter 2 Mixed Mode Clock Manager Additional Documentation The following documents are also available for download at http www xilinx com support documentation virtex 6 htm e Virtex 6 Family Overview The features and product selection of the Virtex 6 family are outlined in this overview e Virtex 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 6 family e Virtex 6 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications e Virtex 6 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption boundary scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces e Virtex 6 FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Virtex 6 devices e Virtex 6 FPGA Configurable Logic Blocks User Guide This guide describes the capabilities of the configurable logic blocks CLBs available i
48. gure 2 3 MMCM Primitives The MMCM_BASE primitive provides access to the most frequently used features of a stand alone MMCM Clock deskew frequency synthesis coarse phase shifting and duty cycle programming are available to use with the MMCM_BASE The ports are listed in Table 2 1 Table 2 1 MMCM BASE Ports Description Ports Clock Input CLKIN CLKFBIN Control Inputs RST Clock Output CLKOUTO to CLKOUT6 CLKOUTOB to CLKOUT3B CLKFBOUT and CLKFBOUTB Status and Data Outputs LOCKED Power Control PWRDWN MMCM ADV Primitive The MMCM ADV primitive provides access to all MMCM BASE features plus additional ports for clock switching connectivity to the other MMCM in the same CMT access to the Dynamic Reconfiguration Port DRP as well as dynamic fine phase shifting The ports are listed in Table 2 2 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX General Usage Description Table 2 2 MMCM ADV Ports Description Ports Clock Input CLKIN1 CLKIN2 CLKFBIN DCLK PSCLK Control and Data Input RST CLKINSEL DWE DEN DADDR DI PSINCDEC PSEN Clock Output CLKOUTO to CLKOUT6 CLKOUTOB to CLKOUT3B CLKFBOUT and CLKFBOUTB Status and Data Output LOCKED DO DRDY PSDONE CLKINSTOPPED CLKFBSTOPPED Power Control PWRDWN The Virtex 6 FPGA MMCM is a mixed signal block designed to support clock network deskew frequency synthesis and jitter r
49. hase offset while 180 indicates a 180 offset or 1 2 cycle phase offset CLKOUT 0 6 _ Real 0 01 to 0 99 0 50 Specifies the Duty Cycle of the DUTY_CYCLE associated CLKOUT clock output in percentage i e 0 50 will generate a 50 duty cycle CLKFBOUT_MULT_F Real 5 to 64 5 Specifies the amount to multiply all Integer values only CLKOUT clock outputs if a different frequency is desired This number in combination with the associated CLKOUT _DIVIDE value and DIVCLK_DIVIDE value will determine the output frequency DIVCLK DIVIDE Integer 1 to 80 1 Specifies the division ratio for all output clocks with respect to the input clock Effectively divides the CLKIN going into the PFD Clocking Resources UG362 v1 6 January 17 2011 www xilinx com 51 Chapter 2 Mixed Mode Clock Manager Table 2 4 MMCM Attributes Cont d XILINX Attribute CLKFBOUT PHASE Type Real Allowed Values Default 0 00 to 360 00 0 0 Description Specifies the phase offset in degrees of the clock feedback output Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM REF JITTERI1 REF JITTER2 Real 0 000 to 0 999 0 100 Allows specification of the expected jitter on the reference clock in order to better optimize MMCM performance A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown If known then the va
50. ible MMOM Ports Table 2 3 summarizes the MMCM ports Table 2 4 lists the MMCM attributes www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Table 2 3 MMCM Ports General Usage Description Pin Name yo Pin Description CLKIN1 Input General clock input See CLKIN1 Primary Reference Clock Input CLKIN2 input Secondary clock input for the MMCM reference clock See CLKIN2 Secondary Clock Input CLKFBIN Input Feedback clock input See CLKFBIN Feedback Clock Input Signal controls the state of the clock input MUX High CLKIN1 Low CLKIN2 CLKINSEL Input Dynamically switches the MMCM reference clock See CLKINSEL Clock Input Select Asynchronous reset signal The RST signal is an asynchronous reset for the MMCM RST inii The MMCM will synchronously re enable itself when this signal is released i e PU MMCM re enabled A reset is not required when the input clock conditions change e g frequency See RST Asynchronous Reset Signal PWRDWN Input Powers down instantiated but unused MMCMs See PWRDWN Power Down The dynamic reconfiguration address DADDR input bus provides a DADDR 6 0 Input reconfiguration address for the dynamic reconfiguration When not used all bits must be assigned zeros See DADDR 6 0 Dynamic Reconfiguration Address The dynamic reconfiguration data input DI bus provides reconfiguration data
51. inx com support 8 www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Chapter 1 Clocking Resources Global Regional and I O Clocks For clocking purposes each Virtex 6 device is divided into regions The number of regions varies with device size six regions in the smallest device to 18 regions in the largest one A region is 40 CLBs high with a horizontal clock row in its center HROW Global I O and regional clocking resources manage complex and simple clocking requirements Non clock resources such as local routing are not recommended when performing clock functions Global Clocks Each Virtex 6 device has 32 global clock lines that can clock all sequential resources on the whole device CLB block RAM DSPs and I O Any 12 of these 32 global clock lines can be used in any region Global clock lines are only driven by a global clock buffer which can also be used as a clock enable circuit or a glitch free multiplexer It can select between two clock sources and can also switch away from a failed clock source A global clock buffer is often driven by a Clock Management Tile CMT to eliminate the clock distribution delay or to adjust its delay relative to another clock There are more global clocks than CMTs but a CMT often drives more than one global clock Regional Clocks and I O Clocks Clocking Resources Each region has up to eight differential regional clock buffers and six regional cl
52. is no required phase relationship between the MMCM input clock and the MMCM output clock The MMCM performance should increase since the feedback clock is not subjected to noise on the core supply since it never passes through a block powered by this supply Of course noise introduced on the CLKIN signal and the BUFG will still be present Figure 2 10 www xilinx com 57 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX 58 IBUFG BUFG CLKOUTO To Logic r CLKFBIN CLKOUTOB CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUTS CLKOUT3B CLKOUT4 CLKOUTS5 CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED MMCM UG362_c2_10_033109 Figure 2 10 MMCM with Internal Feedback Zero Delay Buffer The MMCM can also be used to generate a zero delay buffer clock A zero delay buffer can be useful for applications where there is a single clock signal fan out to multiple destinations with a low skew between them This configuration is shown in the Figure 2 11 Here the feedback signal drives off chip and the board trace feedback is designed to match the trace to the external components In this configuration it is assumed that the clock edges are aligned at the input of the FPGA and the input of the external component The input clock buffers for CLKIN and CLKFBIN must be the same type Both must either be a clock capable input CC in the same clocking region or both must be a global clock input GC There will be a
53. l It must be activated for one cycle of the PSCLK After initiating a phase shift the phase is gradually shifted until a High pulse on PSDONE indicates that the operation is complete There are no glitches or sporadic changes during the operation From the start to the end of the operation the phase is shifted in a continuous analog manner PSINCDEC Phase Shift Increment Decrement Control This input signal synchronously indicates if the dynamic phase shift is an increment or decrement operation positive or negative phase shift PSENCDEC is asserted High for increment and Low for decrement There is no phase shift overflow associated with the dynamic phase shift operation If more 360 or more are shifted then the phase will simply wrap around starting at the original phase CLKOUTT 0 6 Output Clocks These user configurable clock outputs 0 through 6 can be divided versions of the VCO phase outputs user controllable from 1 bypassed to 128 The input clock and output clocks can be phase aligned For possible configuration see MMCM Use Models CLKOUTO can be used in fractional divide mode All CLKOUT outputs can be used in non fractional mode to provide a static or dynamic phase shift See Static Phase Shift Mode for more information CLKOUTT O S B Inverted Output Clocks Inverted 180 phase shift of CLKOUTT0 3 CLKINSTOPPED Input Clock Status Status pin indicating that the input clock has stopped This signal is asserted
54. l and status signals except PSINCDEC are active High 48 MMOM Port Descriptions CLKIN1 Primary Reference Clock Input CLKINI can be driven by an IBUFG either through a global or clock capable clock pin BUFG BUFR BUFH interconnect not recommended or directly from a high speed serial transceiver CLKIN2 Secondary Clock Input CLKIN2 is a secondary clock input that is used to dynamically switch the MMCM reference clock CLKIN2 can be driven by an IBUFG either through a global or clock capable clock pin BUFG BUFR BUFH interconnect not recommended or directly from a high speed serial transceiver CLKFBIN Feedback Clock Input Mustbe connected either directly to the CLKFBOUT for internal feedback or IBUFG either through a global or clock capable pin for external deskew BUFG BUFH or interconnect not recommended For external clock alignment the feedback path clock buffer type should match the forward clock buffer type with the exception of BUFR BUFR can not be compensated for CLKFBOUT Dedicated MMCM Feedback Output For possible configuration see MMCM Use Models CLKFBOUT can also drive logic similar to the CLKO of the DCM in Virtex 5 FPGAs CLKFBOUTB Inverted CLKFBOUT This signal should not be used for feedback It provides an additional inverted CLKFBOUT output clock CLKFBOUTB can drive logic similar to the CLK180 clock of the DCM in Virtex 5 FPGAs www xilinx com Clocking Resources UG362 v
55. l mode then the CLKOUT5 counter output is not available The resolution of the fractional divide is 1 8 or 0 125 degrees effectively increasing the number of synthesizeable frequencies by a factor of eight For example if the CLKIN frequency is 100 MHz and the M divide value is set to 8 then the VCO frequency is 800 MHz CLKOUTO can be used to further fractionally divide the 800 MHz VCO frequency e g CLKOUTO_DIVIDE 2 5 resulting in a 320 MHz output frequency When using the fractional divider then the duty cycle and phase shift are not programmable for outputs used in the fractional mode Jitter Filter MMCMs always reduce the jitter inherent on a reference clock The MMCM can be instantiated as a standalone function to simply support filtering jitter from an external clock before it is driven into the another block As a jitter filter it is usually assumed that the MMCM acts as a buffer and regenerates the input frequency on the output e g F 100 MHz Four 100 MHz In general greater jitter filtering is possible by using the MMCM attribute BANDWIDTH set to Low Setting the BANDWIDTH to Low can incur an increase in the static offset of the MMCM Limitations The MMCM has some restrictions that must be adhered to These are summarized in the MMCM electrical specification in the Virtex 6 FPGA Data Sheet In general the major limitations are VCO operation range input frequency duty cycle programmability and phase shift VCO
56. lates To Bank Above From Bank Above From Bank Above To Bank Above IOCL Bank 2 IOCR Bank 40 1 Os 40 1 Os OSERDES OSERDES LC MMCM X0Yn In L OSERDES The Same Region OSERDES p lt 1 CLKOUT 3 0 lt HPC 3 0 CLKOUT 3 0 MMCM XOYn In The Same Region To Bank Below From Bank Below From Bank Below To Bank Below Notes 1 Any of the MMCM CLKOUTT 3 0 outputs can drive any of the HPC 3 0 to the inner or outer columns or GTX column outer I O and GTX column not shown 2 HPCs can drive OSERDES directly The same two HPCs can drive directly OSERDES in the adjacent Banks 3 Any MMCM CLKOUTT 3 0 can drive any BUFIO and any BUFR UG362 c1 28 011609 Figure 1 29 High Performance Clocks VHDL and Verilog Templates The VHDL and Verilog code for all clocking resource primitives and ISE language templates are available in the Libraries Guide Clocking Resources www xilinx com 35 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources 36 www xilinx com XILINX Clocking Resources UG362 v1 6 January 17 2011 XILINX Chapter 2 Mixed Mode Clock Manager Introduction Clocking Resources The Clock Management Tile CMT in Virtex 6 FPGAs includes two Mixed Mode Clock Managers MMCMs At the core of the MMCM is the Phase Locked Loop PLL architecture similar to Virtex 5 FPGAs with enhanced functions and capabilities There are dedicated routes within a CMT to ch
57. limitation on the maximum delay allowed in the feedback path www xilinx com Clocking Resources UG362 v1 6 January 17 2011 MMCM Use Models IBUFG BUFG OBUF Inside FPGA CLKIN1 CLKOUTO CLKOUTOB To E External CLKOUT1 CLKOUT1B RST CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B l CLKFBIN Components CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT gt 1 gt CLKFBOUTB MMCM LOCKED BUFG ug362 c2 11 033109 Figure 2 11 Zero Delay Buffer In some cases precise alignment will not occur because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the FPGA For example the external components can have an input capacitance on 1 pF to 4 pF while the FPGA has an input capacitance of around 8 pF There is a difference in the signal slope which is basically skew Designers need to be aware of this effect to ensure timing MMCM to MMCM Connection foutmmcme2 fovruucin D MM Clocking Resources The MMCM can be directly cascaded within a CMT to allow generation of a greater range of clock frequencies The frequency range restrictions still apply Equation 2 10 shows the relationship between the final output frequency and the input frequency and counter settings of the two MMCMs Figure 2 12 and Figure 2 13 The phase relationship between the output clock of the second MMCM and the input clock is undefined To cas
58. locks from either the IBUFG BUFG BUFG GTs CLKIN only or interconnect not recommended Each clock input has a programmable counter divider D The Phase Frequency Detector PFD compares both phase and frequency of the rising edges of both the input reference clock and the feedback clock If a minimum High Low pulse is maintained the duty cycle is ancillary The PFD is used to generate a signal proportional to the phase and frequency between the two clocks This signal drives the Charge Pump CP and Loop Filter LF to generate a reference voltage to the VCO The PFD produces an up or down signal to the charge pump and loop filter to determine whether the VCO should operate at a higher or lower frequency When VCO operates at too high of a frequency the PFD activates a down signal causing the control voltage to be reduced decreasing the VCO operating frequency When the VCO operates at too low of a frequency an up signal will increase voltage The VCO produces eight output phases and one variable phase for fine phase shifting Each output phase can be selected as the reference clock to the output counters Figure 2 2 Each counter can be independently programmed for a given customer design A special counter M is also provided This counter controls the feedback clock of the MMCM allowing a wide range of frequency synthesis In addition to integer divide output counters Virtex 6 devices adds a fractional counter by combining the O0 O5 co
59. lue provided should be specified in terms of the UI percentage the maximum peak to peak value of the expected jitter on the input clock CLKIN1 PERIOD Real 1 25 to 100 0 000 Specifies the input period in ns to the MMCM CLKINI input Resolution is down to the ps This information is mandatory and must be supplied CLKIN2 PERIOD Real 1 25 to 100 0 000 Specifies the input period in ns to the MMCM CLKIN input Resolution is down to the ps This information is mandatory and must be supplied CLKFBOUT USE FINE PS Boolean FALSE TRUE FALSE CLKFBOUT counter variable fine phase shift enable CLKOUTO USE FINE PS Boolean FALSE TRUE FALSE CLKOUTO counter variable fine phase shift enable CLKOUTO DIVIDE must be an integer and therefore fractional divide is not allowed CLKOUTT 1 6 USE FINE PS Boolean FALSE TRUE FALSE CLKOUTT1 6 variable fine phase shift enable STARTUP WAIT Boolean FALSE FALSE Must always be set to FALSE CLOCK HOLD Boolean FALSE TRUE FALSE When TRUE holds the VCO frequency close to the frequency prior to losing CLKIN CLKOUTA4 CASCADE Boolean FALSE TRUE FALSE Cascades the output divider counter CLKOUT6 into the input of the CLKOUTA divider for an output clock divider that is greater than 128 effectively providing a total divide value of 16 384 52 www xilinx com Clocking Resources UG362
60. n Figure 1 13 The current clock is IO S is activated High If I0 is currently Low the multiplexer waits for IO to be asserted High Once 10 is High the multiplexer output stays High until I1 transitions Low to High When 11 transitions from Low to High the output switches to I1 If Setup Hold are met no glitches or short pulses can appear on the output www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Clocking Resources Global Clocking Resources BUFGMUX CTRL The BUFGMUX CTRL replaces the BUFGMUX_VIRTEX4 legacy primitive BUFGMUX CTRL is a clock buffer with two clock inputs one clock output and a select line This primitive is based on BUFGCTRL with some pins connected to logic High or Low Figure 1 14 illustrates the relationship of BUFGMUX CTRL and BUFGCTRL IGNORE1 CE1 S1 GND Vpp BUFGMUX CTRL P gt o 5 CEO Vpp anp GNOREO ug362 c1 13 051809 Figure 1 14 BUFGMUX CTRL as BUFGCTRL BUFGMUX CTRL uses the 5 pins as select pins 5 can switch anytime without causing a glitch The Setup Hold time on S is for determining whether the output will pass an extra pulse of the previously selected clock before switching to the new clock If 5 changes as shown in Figure 1 15 prior to the setup time Tgcccx s and before 10 transitions from High to Low then the output will not pass an extra pulse of I0 If S changes following the hold time for S
61. n all Virtex 6 devices e Virtex 6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide Clocking Resources www xilinx com 7 UG362 v1 6 January 17 2011 Preface About This Guide XILINX e Virtex 6 FPGA GTH Transceivers User Guide This guide describes the GTH transceivers available in all Virtex 6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package e Virtex 6 FPGA GTX Transceivers User Guide This guide describes the GTX transceivers available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA Embedded Tri Mode Ethernet MAC User Guide This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA DSP48E1 Slice User Guide This guide describes the architecture of the DSP48E1 slice in Virtex 6 FPGAs and provides configuration examples e Virtex 6 FPGA System Monitor User Guide The System Monitor functionality available in all Virtex 6 devices is outlined in this guide e Virtex 6 FPGA PCB Design Guide This guide provides information on PCB design for Virtex 6 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xil
62. n pairs GCs spread over four banks for maximum flexibility in I O standards All I O columns contain four clock capable pin pairs CCs which can connect to BUFIO and BUFR Two of the four CCs per bank can connect to BUFIOs spanning the adjacent regions Additionally the BUFRs and CC pins in the center columns can directly drive MMCMs in the same region and indirectly BUFGs through the vertical global clock spins that drive the BUFGs Figure 1 1 shows an example of the high level banking and global clocking architecture Figure 1 2 shows a more detailed view of the clocking in a single region with two inner column I O banks IOOL IOCL Center IOCR GTX Banks Banks Bank Banks Banks Se 10 Direct Connects From the Transceivers 4 Device Center BUFH Utilizes the Horizontal t Global Clock Spines 32 Vertical Global Clock Trees UG362 c1 01 050109 Figure 1 1 Example of Block Level Banking and Global Clocking Architecture www xilinx com Clocking Resources 10 UG362 v1 6 January 17 2011 XILINX Global Clocking Resources To Bank To Bank Two Multi ABE Above Region Two Single BUFIOs N ee M 04 Region BUFIOs l MMCM XOYn In Same Region I I t SRCC Pin Pair 4 gt SRCC Pin Pair MRCC Pin Pair 4 gt MRCC Pin Pair Bou TOi Clocking o Outer o Uuter Region lt HROW HROW Columns Columns P 40 CLBs High MRCC Pin Pair 4
63. nd the phase shift resolution only depends on the VCO frequency In this mode the output clocks can be rotated 360 round robin EE 1 in linear increments of 56Fyco www xilinx com 43 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX Dynamic 44 If the VCO runs at 600 MHz then the phase resolution is approximately rounded 30 ps and at 1 6 GHz is approximately rounded 11 ps The phase shift value can be programmed as a fixed value set during configuration or a dynamic increment decrement under application control after configuration The dynamic phase shift is controlled by the PS interface of the MMCM ADV This phase shift mode equally affects all CLKOUT output clocks that are selected for this mode by setting the USE FINE PS attribute to TRUE It is possible for each individual CLKOUT counter to either select the interpolated the previously described static phase shift mode or none Fractional divide is not allowed in this mode Fixed or dynamic phase shifting of the feedback path will result in a negative phase shift of all output clocks with respect to CLKIN The dynamic phase shift interface can not be used when the phase shift mode is set to fixed Phase Shift Interface The MMCM_ADV primitive provides three inputs and one output for dynamic fine phase shifting Each CLKOUT and the CLKFBOUT divider can be individually selected for phase shifting The attributes CLKOUT 0 6 USE F
64. nt to the right of the center column with one CMT per region A CMT has two Mixed Mode Clock Managers MMCMs See Chapter 2 Mixed Mode Clock Manager The CMT column also contains the 32 vertical spines of the global clock trees In the horizontal direction Virtex 6 FPGAs are organized by regions each 40 CLBs and one bank high There is a horizontal clock row HROW in the center of each region containing the horizontal clock spines 12 six regional clock tracks BUFR and the horizontal clocks up to 12 BUFH BUFHs use the same resources as the horizontal clock spines A new type of horizontal clock tree the high performance clock is introduced in this architecture providing a low jitter clock path from the MMCMs to the I O See the Virtex 6 FPGA SelectIO User Guide for more detail Every Virtex 6 FPGA has two I O columns to the left and right of the center column labeled I O center left IOCL and I O center right IOCR with CLBs in between Every LX LXT and SXT device has an I O outer column at the left edge of the device IDOL and some devices have an outer edge I O column to the right Other devices have a Gigabit Transceiver GT column to the right instead There is a horizontal clock row HROW running in the center of each region bank The HROW contains the vertical global clock spines of the global clock buffers BUFG and the BUFHS if the vertical global clock spines are used as such The inner I O columns contain eight global clock pi
65. ock network Unlike global clocks the span of a regional clock signal BUFR is limited to three clock regions while two I O clock signals drive a single region and an additional two I O clocks can drive the regions banks above and below These networks are especially useful for source synchronous interface designs The I O banks in Virtex 6 devices are the same size as a clock region To understand how regional clocking works it is important to understand the signal path of a regional clock signal The regional clocking resources and network in Virtex 6 devices consist of the following paths and components e Clock Capable I O e I O Clock Buffer BUFIO e Regional Clock Buffer BUFR e Regional Clock Nets e Horizontal Clock Buffer BUFH e High Performance Clocks Clock Capable I O Each clock region has four clock capable I O pin pairs per I O bank in every I O column Clock capable I O pairs are regular I O pairs in select locations with special hardware connections to nearby regional clock resources and other clock resources There are four dedicated clock capable I O sites in every bank When used as clock inputs clock capable pins can drive BUFIO and BUFR Each I O column supports regional clock buffers BUFR There are up to four I O columns in each device Two inner I O columns are available in each device and support four BUFRs in each region Depending on the device used up to two outer I O columns are available When used a
66. ock trees A Virtex 6 FPGA I O bank spans exactly one region Each bank contains four clock capable clock inputs Each of these inputs can differentially or single endedly drive four I O clocks four regional clocks and one CMT in the same bank or region Two of the four I O clocks can drive into the bank above and below while the remaining two can only drive the local bank In addition regional clocks can drive regional clock trees in the adjacent regions When the clock capable I Os are driven by single ended clocks then the clock must be connected to the positive P side of the differential clock capable pin pair The negative N side can be used as a general purpose I O or left unconnected The regional clock buffer can be programmed to divide the incoming clock rate by any integer number from 1 to 8 This feature in conjunction with the programmable serializer deserializer in the IOB see Chapter 3 in the Virtex 6 FPGA SelectIO Resources User Guide allows source synchronous systems to cross clock domains without using additional logic resources www xilinx com 9 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources XILINX Clocking Architecture 12 Horizontal Global Clock Tree Spines and 6 RCLK Tracks HROW gt Bank 40 I Os Each Virtex 6 device has a center column containing the dedicated configuration pins Free regions above and below are filled with CLBs logic only There is a CMT column adjace
67. ounters in the CLKO output path In addition various ports and functions are added to make the MMCM compatible with the DCMs in previous architectures The outputs from the MMCM are not spread spectrum however a spread spectrum on the input clock will not be filtered and thus passed on the output clocks Any used MMCM requires a calibration after a user reset or user power down is issued Similarly a calibration is required after power up Some versions of the ISE software v11 5 and later automatically insert a calibration circuit that produces an additional reset of any used MMCM after the initial LOCK This circuit disables the STARTUP WAIT functionality after configuration for the MMCMs The STARTUP WAIT attribute must always be set to FALSE www xilinx com 37 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager XILINX 38 IBUFG GCIO and CCIO Local R not recommended MMCMs BUFR BUFG CLKIN1 GTX CLKIN2 BUFH outing BUFG gt BUFH BUFIO 9 CLKIN1 CLKIN2 BUFG gt BUFH BUFIO ug362 c2 01 011209 Figure 2 1 Block Diagram of the Virtex 6 FPGA CMT Virtex 6 devices contain up to nine CMT tiles The MMCMs serve as a frequency synthesizer for a wide range of frequencies serve as a jitter filter for either external or internal clocks and deskew clocks Input MUXes select the reference and feedback c
68. owing these cases to be dropped For this case only D 1 3 5 6 7 and 9 are considered since all other D values are subsets of these cases This drastically reduces the number of possible output frequencies The output frequencies are sequentially selected The desired output frequency should be checked against the possible output frequencies generated Once the first output frequency is determined an additional constraint can be imposed on the values of M and D This can further limit the possible output frequencies for the second output frequency Continue this process until all the output frequencies are selected The constraints used to determine the allowed M and D values are shown in the following equations Dyin wuni Equation 2 4 fPFD MAX Dmax rounddo EL Equation 2 5 FS PFD MIN Myin roundup x Dian Equation 2 6 Fin Mmax rounddown COMA Pad Equation 2 7 Determine the M and D Values Determining the input frequency can result in several possible M and D values The next step is to determine the optimum M and D values The starting M value is first determined This is based off the VCO target frequency the ideal operating frequency of the VCO Duin fvcoMAX MipEAL p Equation 2 8 The goal is to find the M value closest to the ideal operating point of the VCO The minimum D value is used to start the process The goal is to make D and M values as small as possible while keeping fyco as high as poss
69. s single ended clock pins then as described in Global Clock Buffers the P side of the pin pair must be used because a direct connection only exists on this pin In Virtex 6 devices the inner I O column clock capable pins can also drive MMCM and BUFG clock inputs This method of driving MMCM input clocks produces a higher performance path than connecting clocks to the MMCMs using the global clock pins The clock capable pins must be in the same region bank and to either the left or right of where the MMCM is located I O Clock Buffer BUFIO The I O clock buffer BUFIO is a clock buffer available in Virtex 6 devices The BUFIO drives a dedicated clock net within the I O columns independent of the global clock resources Thus BUFIOs are ideally suited for source synchronous data capture forwarded receiver clock distribution BUFIOs can only be driven by clock capable I Os located in the same bank In a clock region there are four BUFIOs per bank Some devices have two banks per region inner and outer columns Each BUFIO can drive a single I O clock network in the same region bank and two of the four BUFIOs can drive the regions above and below BUFIOs cannot drive logic resources CLB block RAM DSP etc because the I O clock network only reaches the I O column in the same bank clock region or bank clock region above and below www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX Regional Clocking Resources
70. sources UG362 v1 6 January 17 2011 XILINX Regional Clocking Resources the global clock tree Each BUFR can drive the six regional clock nets in the region it is located and the six clock nets in the adjacent clock regions up to three clock regions Unlike BUFIOs BUFRs can drive the I O logic and logic resources CLB block RAM etc in the existing and adjacent clock regions BUFRs can be driven by clock capable pins local interconnect GTs and the MMCMs high performance clocks In addition BUFR is capable of generating divided clock outputs with respect to the clock input The divide values are an integer between one and eight BUFRs are ideal for source synchronous applications requiring clock domain crossing or serial to parallel conversion Each I O column supports regional clock buffers There are up to four I O columns in a device with two inner columns center left and right and up to two outer left and right columns The availability of the outer columns are device dependant while the inner columns are always present The Virtex 6 architecture therefore can have up to four BUFRs per region with two driving from the inner columns out always present and two BUFRs per region driving from the outer I O columns in when present In Virtex 6 devices BUFRs can also directly drive MMCM clock inputs and BUFGs BUFR Primitive Clocking Resources BUFR Figure 1 23 and Table 1 7 is a clock in clock out buffer with the cap
71. t or decrement is signaled when PSDONE asserts High After PSDONE has pulsed High another increment decrement can be initiated There is no maximum phase shift or phase shift overflow An entire clock period 360 degrees can always be phase shifted regardless of frequency When the end of the period is reached the phase shift simply wraps around round robin style www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX General Usage Description PSEN 1 a PSDONE i ug362_2_05_020409 Figure 2 5 Phase Shift Timing Diagram Counter Cascading The CLKOUTS divider counter can be cascaded with the CLKOUT4 divider This provides a capability to have an output divider that is larger than 128 CLKOUT6 simply feeds the input of the CLKOUTA divider There is a static phase offset between the output of the cascaded divider and all other output dividers MMCM Programming Programming of the MMCM must follow a set flow to ensure configuration that guarantees stability and performance This section describes how to program the MMCM based on certain design requirements A design can be implement in two ways directly through the GUI interface the Clocking Wizard or directly implementing the MMCM through instantiation Regardless of the method selected the following information is necessary to program the MMCM e Reference clock period e Output clock frequencies up to seven maximum e Output clock duty c
72. then the output will pass an extra pulse If S violates the Setup Hold requirements the output might pass the extra pulse but it will not glitch In any case the output will change to the new clock within three clock cycles of the slower clock The Setup Hold requirements for S0 and S1 are with respect to the falling clock edge not the rising edge as for CEO and CE1 Switching conditions for BUFGMUX CTRL are the same as the 5 pin of BUFGCTRL Figure 1 15 illustrates the timing diagram for BUFGMUX CTRL TBCCKO_O H TBOCKO O ug362 ci 14 040209 Figure 1 15 BUFGMUX CTRL Timing Diagram www xilinx com 21 UG362 v1 6 January 17 2011 Chapter 1 Clocking Resources XILINX Other capabilities of the BUFGMUX_CTRL primitive are e Pre selection of I0 and I1 input after configuration Initial output can be selected as High or Low after configuration Additional Use Models Asynchronous MUX Using BUFGCTRL In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL An example is when one of the clock inputs is no longer switching If this happens the clock output would not have the proper switching conditions because the BUFGCTRL never detected a clock edge This case uses the asynchronous MUX Figure 1 16 illustrates an asynchronous MUX with BUFGCTRL design example Figure 1 17 shows the asynchronous MUX timing diagram
73. unters When used in fractional mode the O5 output is not available www xilinx com Clocking Resources UG362 v1 6 January 17 2011 XILINX General Usage Description Lock Detect General d Lock Moni Lock Routing witcl ock Monitor Circuit 8 phase taps 1 variable phase tap CLKIN1 a 9 ra CLKIN2 PFD gt CP H LF VCO CLKOUTO LE Tn Divide 5 CLKOUTOB CLKFB CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT3 ES o3 CLKOUT3B 1 The O5 output is disabled when aa the 00 output is set to a non integer divide E o CLKOUT6 E M CLKFBOUT CLKFBOUTB ug362 c2 02 010510 Figure 2 2 Detailed MMCM Block Diagram General Usage Description MMCM Primitives The two Virtex 6 FPGA MMCM primitives MMCM BASE and MMCM ADV are shown in Figure 2 3 Clocking Resources www xilinx com 39 UG362 v1 6 January 17 2011 Chapter 2 Mixed Mode Clock Manager 40 CLKIN1 CLKOUTO CLKOUTOB CLKIN2 XILINX CLKOUTO CLKOUTOB CLKFBIN RST CLKOUT1B PWRDWN CLKOUT2B CLKOUT3B MMCM_BASE MMCM BASE Primitive CLKOUT1 CLKFBIN CLKOUT1 RST CLKOUT1B PWRDWN CLKOUT2 CLKINSEL 66007 DADDR 6 0 CONSUE ole CLKOUT3B BE CLKOUT4 DEN CLKOUTS5 CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED DO 15 0 DRDY PSDONE CLKINSTOPPED CLKFBSTOPPED CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED DCLK PSINCDEC PSEN PSCLK MMCM_ADV ug362_c2_03_033109 Fi
74. v1 6 January 17 2011 XILINX Table 2 4 MMCM Attributes Cont d General Usage Description Attribute COMPENSATION Type Boolean Allowed Values ZHOLD CASCADE EXTERNAL INTERNAL BUF_IN Default ZHOLD Description Clock input compensation Must be set to ZHOLD Defines how the MMCM feedback is configured ZHOLD Indicates the MMCM is configured to provide a negative hold time at the I O registers CASCADE Indicates the cascading of two MMCMs EXTERNAL Indicates a network external to the FPGA is being compensated INTERNAL Indicates the MMCM is using its own internal feedback path so no delay is being compensated BUF IN Indicates that the configuration does not match with the other compensation modes and no delay will be compensated This is the case if a clock input is driven by a BUFG BUFH BUFR or GTX GTH Notes 1 The DIVCLK DIVIDE values of 3 and 4 cannot be used if the MMCM input clock CLKIN peque is greater than 315 MHz Multiplying up doubling both the DIVCLK DIVIDE and CLKFBOUT MULT attribute values yiel and CLKOUT frequencies 2 The COMPENSATION attribute values are documented for informational purpose only The ISE software tools automatically select the appropriate compensation based on circuit topology Do not manually select a compensation value leave the attribute at the default value MMCM Clock Input Signals Clocking Resources
75. ycle default is 50 e Output clock phase shift in number of degrees relative to the original 0 phase of the clock e Desired bandwidth of the MMCM default is OPTIMIZED and the bandwidth is chosen in software e Compensation mode automatically determined by the software e Reference clock jitter in UI i e a percentage of the reference clock period Determine the Input Frequency The first step is to determine the input frequency This allows all possible output frequencies to be determined by using the minimum and maximum input frequencies to define the D counter range the VCO operating range to determine the M counter range and the output counter range There can be a very large number of frequencies When using integer divides in the worst case there will be 80 x 64 x 128 655 360 possible combinations In reality the total number of different frequencies is less since the entire range of the M and D counters cannot be realized and there is overlap between the various settings Clocking Resources UG362 v1 6 January 17 2011 www xilinx com 45 46 Chapter 2 Mixed Mode Clock Manager XILINX As an example consider Fry 100 MHz If the minimum PFD frequency is 10 MHz then D can only go from 1 to 10 D 1 Mcanonly have values from four to 16 D 2 Mcanonly have values from eight to 32 e D 4 M can only have values from 16 to 64 In addition D 1M 4isasubsetof D 2M 8 D 4 M 16 and D 8 M 32 all

Xilinx UG362 Virtex-6 FPGA Clocking Resources User Guide

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